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fpga-logi/logi-hard | test_bench/mcp3002_tb.vhd | 2 | 3871 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:14:22 08/26/2013
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-hard/test_bench/mcp3002_tb.vhd
-- Project Name: logipi_face
-- Target Device:
-- Tool versions: ISE 14.1
-- Description:
--
-- VHDL Test Bench Created by ISE for module: mcp3002_interface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY mcp3002_tb IS
END mcp3002_tb;
ARCHITECTURE behavior OF mcp3002_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mcp3002_interface
PORT(
clk : IN std_logic;
resetn : IN std_logic;
sample : OUT std_logic_vector(9 downto 0);
dv : OUT std_logic;
chan : IN std_logic;
DOUT : OUT std_logic;
DIN : IN std_logic;
SCLK : OUT std_logic;
SSN : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal resetn : std_logic := '0';
signal chan : std_logic := '0';
signal DIN : std_logic := '0';
--Outputs
signal sample : std_logic_vector(9 downto 0);
signal dv : std_logic;
signal DOUT : std_logic;
signal SCLK : std_logic;
signal SSN : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant SCLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mcp3002_interface PORT MAP (
clk => clk,
resetn => resetn,
sample => sample,
dv => dv,
chan => chan,
DOUT => DOUT,
DIN => DIN,
SCLK => SCLK,
SSN => SSN
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
spi_process :process
begin
while true loop
wait until SCLK'event and SCLK='0';
DIN <= '1' ;
wait until SCLK'event and SCLK='0';
DIN <= '0' ;
end loop ;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
resetn <= '0' ;
wait for 100 ns;
resetn <= '1' ;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| lgpl-3.0 |
fpga-logi/logi-hard | hdl/control/rgb_32_32_matrix_ctrl.vhd | 2 | 13650 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:27:28 07/10/2014
-- Design Name:
-- Module Name: rgb_32_32_matrix_ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.logi_utils_pack.all ;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rgb_32_32_matrix_ctrl is
generic(
clk_div : positive := 10;
-- TODO: nb_panels is untested, still need to be validated
nb_panels : positive := 4 ;
bits_per_color : INTEGER RANGE 1 TO 4 := 4 ;
expose_step_cycle: positive := 1910
);
port(
clk, reset : in std_logic ;
pixel_addr : in std_logic_vector((nbit(32*32*nb_panels))-1 downto 0);
pixel_value_out : out std_logic_vector((bits_per_color*3)-1 downto 0);
pixel_value_in : in std_logic_vector((bits_per_color*3)-1 downto 0);
write_pixel : in std_logic ;
SCLK_OUT : out std_logic ;
BLANK_OUT : out std_logic ;
LATCH_OUT : out std_logic ;
A_OUT : out std_logic_vector(3 downto 0);
R_out : out std_logic_vector(1 downto 0);
G_out : out std_logic_vector(1 downto 0);
B_out : out std_logic_vector(1 downto 0)
);
end rgb_32_32_matrix_ctrl;
architecture Behavioral of rgb_32_32_matrix_ctrl is
component dpram_NxN is
generic(SIZE : natural := 64 ; NBIT : natural := 8; ADDR_WIDTH : natural := 6);
port(
clk : in std_logic;
we : in std_logic;
di : in std_logic_vector(NBIT-1 downto 0 );
a : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
dpra : in std_logic_vector((ADDR_WIDTH - 1) downto 0 );
spo : out std_logic_vector(NBIT-1 downto 0 );
dpo : out std_logic_vector(NBIT-1 downto 0 )
);
end component;
type ctrl_state is (EXPOSE, BLANK, LATCH, UNBLANK, READ, SHIFT1, SHIFT2);
constant LINE_SIZE : positive := 32*nb_panels ;
constant RAM_SIZE : positive := LINE_SIZE*32 ;
constant BOTTOM_ADDRESS_OFFSET : positive := LINE_SIZE * 16 ;
signal cur_state, next_state : ctrl_state ;
signal next_pixel_div, bin_code_delay, exposure_time : std_logic_vector(15 downto 0);
signal end_count : std_logic ;
signal col_count : std_logic_vector(nbit(LINE_SIZE)-1 downto 0);
signal line_count : std_logic_vector(3 downto 0);
signal clk_count, count_load_val : std_logic_vector(15 downto 0) ;
signal rd_bit, exp_bit : std_logic_vector(1 downto 0);
signal pixel_read_addr, line_base_addr : std_logic_vector(nbit(RAM_SIZE/2)-1 downto 0);
signal line_count_enable, col_count_enable, rd_bit_count_enable : std_logic ;
signal line_count_reset, col_count_reset : std_logic ;
signal pixel_data_line0, pixel_data_line16 : std_logic_vector((bits_per_color*3)-1 downto 0);
signal pixel_data_line16_extended, pixel_data_line0_extended : std_logic_vector(15 downto 0) ;
signal end_of_col, end_of_bits : std_logic ;
signal shift_count : std_logic_vector(3 downto 0);
signal end_of_exposure, load_exposure, load_count : std_logic ;
signal SCLK_Q, LATCH_Q, BLANK_Q : std_logic ;
signal R1_Q, G1_Q, B1_Q, R0_Q, G0_Q, B0_Q : std_logic ;
signal A_OUT_Q : std_logic_vector(3 downto 0);
signal pixel_write_addr_line0, pixel_write_addr_line16 : std_logic_vector((nbit(32*32*nb_panels))-1 downto 0);
signal pixel_write_addr : std_logic_vector((nbit(32*32*nb_panels))-1 downto 0);
signal pixel_value_out_0, pixel_value_out_1 : std_logic_vector((bits_per_color*3)-1 downto 0);
signal write_mem0, write_mem1 : std_logic ;
begin
-- ram buffer instanciation
pixel_write_addr <= pixel_addr ;
pixel_write_addr_line0 <= pixel_write_addr ;
--when pixel_write_addr < ((32*nb_panels)*16) else
--(others => '0');
pixel_write_addr_line16 <= pixel_write_addr - BOTTOM_ADDRESS_OFFSET ;
--when pixel_write_addr >= (32*nb_panels)*16 else
--(others => '0'); -- only for simulation purpose ...
write_mem0 <= write_pixel when pixel_write_addr < BOTTOM_ADDRESS_OFFSET else
'0' ;
pixel_value_out <= pixel_value_out_0 when pixel_addr < BOTTOM_ADDRESS_OFFSET else
pixel_value_out_1 ;
frame_buffer0 : dpram_NxN
generic map(SIZE => RAM_SIZE/2, NBIT => bits_per_color*3, ADDR_WIDTH => nbit(RAM_SIZE/2))
port map(
clk => clk,
we => write_mem0,
di => pixel_value_in,
a => pixel_write_addr_line0(nbit(RAM_SIZE/2)-1 downto 0) ,
dpra => pixel_read_addr,
spo => pixel_value_out_0,
dpo => pixel_data_line0
);
pixel_data_line0_extended((bits_per_color*3)-1 downto 0) <= pixel_data_line0 ;
pixel_data_line0_extended(15 downto (bits_per_color*3)) <= (others => '0') ;
write_mem1 <= write_pixel when pixel_write_addr >= BOTTOM_ADDRESS_OFFSET else
'0' ;
frame_buffer1 : dpram_NxN
generic map(SIZE => RAM_SIZE/2, NBIT => bits_per_color*3, ADDR_WIDTH => nbit(RAM_SIZE/2))
port map(
clk => clk,
we => write_mem1,
di => pixel_value_in,
a => pixel_write_addr_line16(nbit(RAM_SIZE/2)-1 downto 0) ,
dpra => pixel_read_addr,
spo => pixel_value_out_1,
dpo => pixel_data_line16
);
pixel_data_line16_extended((bits_per_color*3)-1 downto 0) <= pixel_data_line16 ;
pixel_data_line16_extended(15 downto (bits_per_color*3)) <= (others => '0') ;
-- ram buffer read address decoding
pixel_read_addr <= line_base_addr + std_logic_vector(resize(unsigned(col_count), pixel_read_addr'LENGTH)) ;
-- state machine code
-- state machine latch state process
process(clk, reset)
begin
if reset = '1' then
cur_state <= EXPOSE ;
elsif rising_edge(clk) then
cur_state <= next_state ;
end if;
end process;
-- state machine, state evolution process
process(cur_state, end_count, col_count, end_of_col, end_of_exposure)
begin
next_state <= cur_state ;
case cur_state is
when EXPOSE =>
if end_of_exposure = '1' then
next_state <= BLANK ;
end if ;
when BLANK =>
if end_count = '1' then
next_state <= LATCH ;
end if ;
when LATCH =>
if end_count = '1' then
next_state <= UNBLANK ;
end if ;
when UNBLANK =>
if end_count = '1' then
next_state <= SHIFT1 ;
end if ;
when SHIFT1 =>
if end_count = '1' then
next_state <= SHIFT2 ;
end if ;
when SHIFT2 =>
if end_of_col = '1' and end_count = '1' then
next_state <= EXPOSE ;
elsif end_count = '1' then
next_state <= SHIFT1 ;
end if ;
when others =>
next_state <= EXPOSE ;
end case ;
end process;
-- internal signals management
-- clk_count is used to generate the time interval between states
-- it is also used to generate the output clock frequency
process(clk, reset)
begin
if reset = '1' then
clk_count <= (others => '0');
elsif rising_edge(clk) then
if load_count = '1' then
clk_count <= count_load_val ;
else
clk_count <= clk_count - 1 ;
end if ;
end if;
end process;
-- helper signal to simplify equations
end_count <= '1' when clk_count = 0 else
'0' ;
load_count <= '1' when cur_state = EXPOSE else
end_count;
-- value to in interval counter, value to load is computed for next state
with cur_state select
count_load_val <= std_logic_vector(to_unsigned((clk_div*8)-1, 16) ) when EXPOSE,
std_logic_vector(to_unsigned((clk_div*8)-1, 16) ) when BLANK,
std_logic_vector(to_unsigned((clk_div-1), 16) ) when LATCH,
std_logic_vector(to_unsigned((clk_div-1), 16) ) when UNBLANK,
std_logic_vector(to_unsigned((clk_div-1), 16) ) when SHIFT1,
std_logic_vector(to_unsigned((clk_div-1), 16) ) when SHIFT2,
std_logic_vector(to_unsigned((clk_div-1), 16) ) when others;
-- counter for exposure time
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
exposure_time <= bin_code_delay;
elsif load_exposure = '1' then
exposure_time <= bin_code_delay ;
elsif exposure_time > 0 then
exposure_time <= exposure_time - 1 ;
end if ;
end if;
end process;
end_of_exposure <= '1' when exposure_time = 0 else
'0' ;
load_exposure <= '1' when cur_state = LATCH else
'0' ;
-- column counter, is incremented on each falling edge of sclk
process(clk, reset)
begin
if reset = '1' then
col_count <= (others => '0') ;
elsif rising_edge(clk) then
if col_count_reset = '1' then
col_count <= (others => '0') ;
elsif col_count_enable = '1' and col_count < (LINE_SIZE-1) then
col_count <= col_count + 1 ;
end if ;
end if;
end process;
-- helper signal to simplify equations
end_of_col <= '1' when col_count = (LINE_SIZE-1) else
'0' ;
-- the column count is reseted on end of blank
with cur_state select
col_count_reset <= '0' when SHIFT1,
'0' when SHIFT2,
end_count when UNBLANK,
'0' when others;
-- column are counted when shifintg the pixel data
with cur_state select
col_count_enable <= end_count when SHIFT2,
'0' when others ;
-- line counter, specify the line to read from memory
process(clk, reset)
begin
if reset = '1' then
line_count <= (others => '0') ;
line_base_addr <= (others => '0') ;
elsif rising_edge(clk) then
if line_count_reset = '1' then
line_count <= (others => '0') ;
line_base_addr <= (others => '0') ;
elsif line_count_enable = '1' then
line_count <= line_count + 1 ;
line_base_addr <= line_base_addr + LINE_SIZE ;
end if ;
end if;
end process;
-- increment line counter after blanking
with cur_state select
line_count_enable <= (end_count and end_of_bits) when LATCH,
'0' when others ;
line_count_reset <= '1' when line_count_enable = '1' and line_count = 15 else
'0' ;
-- rd_bit specify the bit to read from the color code
-- exp bit specify the bit being exposed on the matrix
process(clk, reset)
begin
if reset = '1' then
rd_bit <= (others => '0') ;
--exp_bit <= (others => '0') ;
elsif rising_edge(clk) then
if end_of_bits = '1' and rd_bit_count_enable = '1' then
rd_bit <= (others => '0') ;
--exp_bit <= rd_bit ;
elsif rd_bit_count_enable = '1' then
rd_bit <= rd_bit + 1 ;
--exp_bit <= rd_bit ;
end if ;
end if;
end process;
with cur_state select
rd_bit_count_enable <= (end_count) when LATCH,
'0' when others ;
-- helper signals to simplify equations
end_of_bits <= '1' when rd_bit = bits_per_color-1 else
'0' ;
-- The binary coded modulation delay is doubled for each exposed color bit
with conv_integer(rd_bit) select
bin_code_delay <= std_logic_vector(to_unsigned(expose_step_cycle, 16)) when 3,
std_logic_vector(to_unsigned(expose_step_cycle*2, 16)) when 2,
std_logic_vector(to_unsigned(expose_step_cycle*4, 16)) when 1,
std_logic_vector(to_unsigned(expose_step_cycle*8, 16)) when others ;
-- output management
-- the output are combinatorial but latched to avoid glitches
with cur_state select
SCLK_q <= '0' when SHIFT1,
'1' when SHIFT2,
'0' when others ;
with cur_state select
BLANK_q <= '1' when BLANK,
'1' when LATCH,
'0' when others ;
with cur_state select
LATCH_q <= '1' when LATCH,
'0' when others ;
with conv_integer(rd_bit) select
R0_q <= pixel_data_line0_extended(8) when 3,
pixel_data_line0_extended(9) when 2,
pixel_data_line0_extended(10) when 1,
pixel_data_line0_extended(11) when others;
with conv_integer(rd_bit) select
G0_q <= pixel_data_line0_extended(4) when 3,
pixel_data_line0_extended(5) when 2,
pixel_data_line0_extended(6) when 1,
pixel_data_line0_extended(7) when others;
with conv_integer(rd_bit) select
B0_q <= pixel_data_line0_extended(0) when 3,
pixel_data_line0_extended(1) when 2,
pixel_data_line0_extended(2) when 1,
pixel_data_line0_extended(3) when others;
with conv_integer(rd_bit) select
R1_q <= pixel_data_line16_extended(8) when 3,
pixel_data_line16_extended(9) when 2,
pixel_data_line16_extended(10) when 1,
pixel_data_line16_extended(11) when others;
with conv_integer(rd_bit) select
G1_q <= pixel_data_line16_extended(4) when 3,
pixel_data_line16_extended(5) when 2,
pixel_data_line16_extended(6) when 1,
pixel_data_line16_extended(7) when others;
with conv_integer(rd_bit) select
B1_q <= pixel_data_line16_extended(0) when 3,
pixel_data_line16_extended(1) when 2,
pixel_data_line16_extended(2) when 1,
pixel_data_line16_extended(3) when others;
-- the address to be output to the matrix is a delayed version of the
-- line being read from memory. We expose one line, while we are loading the values
-- for the next
process(clk, reset)
begin
if reset = '1' then
A_OUT_Q <= (others => '0');
elsif rising_edge(clk) then
if cur_state = BLANK and end_count = '1' then
A_OUT_Q <= line_count ;
end if ;
end if;
end process;
-- all output are latched to prevent glitches
process(clk, reset)
begin
if rising_edge(clk) then
SCLK_OUT <= SCLK_q ;
LATCH_OUT <= LATCH_q ;
BLANK_OUT <= BLANK_q ;
R_OUT(0) <= R0_q ;
R_OUT(1) <= R1_q ;
G_OUT(0) <= G0_q ;
G_OUT(1) <= G1_q ;
B_OUT(0) <= B0_q ;
B_OUT(1) <= B1_q ;
A_OUT <= A_OUT_Q ;
end if;
end process;
end Behavioral;
| lgpl-3.0 |
fpga-logi/logi-hard | hdl/virtual_instrument/logi_virtual_sw.vhd | 2 | 3238 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:15:04 12/17/2013
-- Design Name:
-- Module Name: logi_virtual_sw - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity logi_virtual_sw is
generic(
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
sw : out std_logic_vector(15 downto 0)
);
end logi_virtual_sw;
architecture Behavioral of logi_virtual_sw is
signal reg_out_d : std_logic_vector(15 downto 0) ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
reg_out_d <= (others => '0');
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
reg_out_d <= wbs_writedata;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
sw <= reg_out_d ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
end Behavioral;
| lgpl-3.0 |
tmeissner/vhdl_verification | osvvm_fsm_psl_coverage/osvvm_fsm_psl_coverage.vhd | 1 | 3274 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.env.all;
library osvvm;
use osvvm.NamePkg.all ;
use osvvm.TranscriptPkg.all ;
use osvvm.OsvvmGlobalPkg.all ;
use osvvm.AlertLogPkg.all ;
use osvvm.RandomPkg.all ;
use osvvm.CoveragePkg.all ;
use osvvm.MemoryPkg.all ;
entity osvvm_fsm_psl_coverage is
end entity osvvm_fsm_psl_coverage;
architecture sim of osvvm_fsm_psl_coverage is
type t_fsm_state is (IDLE, ADDR, DATA);
signal s_fsm_state : t_fsm_state;
signal s_clk : std_logic := '0';
signal s_reset_n : std_logic := '0';
signal s_state_cover : unsigned(2 downto 0);
shared variable sv_cover : CovPType;
begin
s_clk <= not(s_clk) after 5 ns;
s_reset_n <= '1' after 20 ns;
FsmP : process (s_reset_n, s_clk) is
begin
if (s_reset_n = '0') then
s_fsm_state <= IDLE;
elsif (rising_edge(s_clk)) then
case s_fsm_state is
when IDLE => s_fsm_state <= ADDR;
when ADDR => s_fsm_state <= DATA;
when DATA => s_fsm_state <= IDLE;
when others =>
null;
end case;
end if;
end process FsmP;
-- psl endpoint E_IDLE_ADDR is {s_fsm_state = IDLE; s_fsm_state = ADDR}@s_clk'active;
-- psl endpoint E_ADDR_DATA is {s_fsm_state = ADDR; s_fsm_state = DATA}@s_clk'active;
-- psl endpoint E_DATA_IDLE is {s_fsm_state = DATA; s_fsm_state = IDLE}@s_clk'active;
EndpointRegP : process is
begin
s_state_cover <= (others => '0');
if (E_IDLE_ADDR) then
s_state_cover(0) <= '1';
end if;
if (E_ADDR_DATA) then
s_state_cover(1) <= '1';
end if;
if (E_DATA_IDLE) then
s_state_cover(2) <= '1';
end if;
wait until rising_edge(s_clk);
end process;
sv_cover.AddBins("IDLE->ADDR", GenBin(1));
sv_cover.AddBins("ADDR->DATA", GenBin(2));
sv_cover.AddBins("DATA->IDLE", GenBin(4));
sv_cover.AddBins(ALL_ILLEGAL);
CovCollectP : process is
begin
wait until s_reset_n = '1' and rising_edge(s_clk);
-- we have to wait another cycle because endpoints are delayed by one cycle
-- if we don't wait, we get an illegal BIN hit in second cycle after released reset
wait until rising_edge(s_clk);
loop
wait until rising_edge(s_clk);
sv_cover.ICover(to_integer(s_state_cover));
end loop;
end process CovCollectP;
FinishP : process is
begin
wait until s_clk'active;
if (sv_cover.IsCovered) then
Log("FSM full covered :)", ALWAYS);
sv_cover.SetName("FSM state coverage report");
sv_cover.WriteBin;
stop(0);
end if;
end process FinishP;
-- psl default clock is rising_edge(s_clk);
-- psl IDLE_ADDR : assert always (s_fsm_state = IDLE and s_reset_n = '1') -> next (s_fsm_state = ADDR) abort not(s_reset_n)
-- report "FSM error: IDLE should be followed by ADDR state";
-- psl ADDR_DATA : assert always (s_fsm_state = ADDR and s_reset_n = '1') -> next (s_fsm_state = DATA) abort not(s_reset_n);
-- report "FSM error: ADDR should be followed by DATA state";
-- psl DATA_IDLE : assert always (s_fsm_state = DATA and s_reset_n = '1') -> next (s_fsm_state = IDLE) abort not(s_reset_n);
-- report "FSM error: DATA should be followed by IDLE state";
end architecture sim;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/modules/fabric/xwb_fabric_sink.vhd | 2 | 7688 | -------------------------------------------------------------------------------
-- Title : Wishbone Packet Fabric buffered packet sink
-- Project : WR Cores Collection
-------------------------------------------------------------------------------
-- File : xwb_fabric_sink.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-16
-- Last update: 2012-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A simple WB packet streaming sink with builtin FIFO buffer.
-- Outputs a trivial interface (start-of-packet, end-of-packet, data-valid)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-16 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
entity xwb_fabric_sink is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic
);
end xwb_fabric_sink;
architecture rtl of xwb_fabric_sink is
constant c_fifo_width : integer := 16 + 2 + 4;
signal q_valid, full, we, rd : std_logic;
signal fin, fout, fout_reg : std_logic_vector(c_fifo_width-1 downto 0);
signal cyc_d0, rd_d0 : std_logic;
signal pre_sof, pre_eof, pre_bytesel, pre_dvalid : std_logic;
signal post_sof, post_dvalid : std_logic;
signal post_addr : std_logic_vector(1 downto 0);
signal post_data : std_logic_vector(15 downto 0);
signal snk_out : t_wrf_sink_out;
begin -- rtl
p_delay_cyc_and_rd : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cyc_d0 <= '0';
rd_d0 <= '0';
else
if(full = '0') then
cyc_d0 <= snk_i.cyc;
end if;
rd_d0 <= rd;
end if;
end if;
end process;
pre_sof <= snk_i.cyc and not cyc_d0; -- sof
pre_eof <= not snk_i.cyc and cyc_d0; -- eof
pre_bytesel <= not snk_i.sel(0); -- bytesel
pre_dvalid <= snk_i.stb and snk_i.we and snk_i.cyc and not snk_out.stall; -- data valid
fin(15 downto 0) <= snk_i.dat;
fin(17 downto 16) <= snk_i.adr;
fin(21 downto 18) <= pre_sof & pre_eof & pre_bytesel & pre_dvalid;
snk_out.stall <= full or (snk_i.cyc and not cyc_d0);
snk_out.err <= '0';
snk_out.rty <= '0';
p_gen_ack : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
snk_out.ack <= '0';
else
snk_out.ack <= snk_i.cyc and snk_i.stb and snk_i.we and not snk_out.stall;
end if;
end if;
end process;
snk_o <= snk_out;
we <= '1' when fin(21 downto 18) /= "0000" and full = '0' else '0';
rd <= q_valid and dreq_i and not post_sof;
U_FIFO : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => 16)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fin,
we_i => we,
q_o => fout,
rd_i => rd,
almost_full_o => full,
q_valid_o => q_valid);
p_fout_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fout_reg <= (others => '0');
elsif(rd = '1') then
fout_reg <= fout;
end if;
end if;
end process;
post_data <= fout_reg(15 downto 0);
post_addr <= fout_reg(17 downto 16);
post_sof <= fout_reg(21) and rd_d0; --and q_valid;
post_dvalid <= fout_reg(18);
sof_o <= post_sof and rd_d0;
dvalid_o <= post_dvalid and rd_d0;
error_o <= '1' when rd_d0 = '1' and (post_addr = c_WRF_STATUS) and (f_unmarshall_wrf_status(post_data).error = '1') else '0';
eof_o <= fout_reg(20) and rd_d0;
bytesel_o <= fout_reg(19);
data_o <= post_data;
addr_o <= post_addr;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
entity wb_fabric_sink is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_dat_i : in std_logic_vector(15 downto 0);
snk_adr_i : in std_logic_vector(1 downto 0);
snk_sel_i : in std_logic_vector(1 downto 0);
snk_cyc_i : in std_logic;
snk_stb_i : in std_logic;
snk_we_i : in std_logic;
snk_stall_o : out std_logic;
snk_ack_o : out std_logic;
snk_err_o : out std_logic;
snk_rty_o : out std_logic;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic
);
end wb_fabric_sink;
architecture wrapper of wb_fabric_sink is
component xwb_fabric_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic);
end component;
signal snk_in : t_wrf_sink_in;
signal snk_out : t_wrf_sink_out;
begin -- wrapper
U_Wrapped_Sink : xwb_fabric_sink
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
snk_i => snk_in,
snk_o => snk_out,
addr_o => addr_o,
data_o => data_o,
dvalid_o => dvalid_o,
sof_o => sof_o,
eof_o => eof_o,
error_o => error_o,
bytesel_o => bytesel_o,
dreq_i => dreq_i);
snk_in.adr <= snk_adr_i;
snk_in.dat <= snk_dat_i;
snk_in.stb <= snk_stb_i;
snk_in.we <= snk_we_i;
snk_in.cyc <= snk_cyc_i;
snk_in.sel <= snk_sel_i;
snk_stall_o <= snk_out.stall;
snk_ack_o <= snk_out.ack;
snk_err_o <= snk_out.err;
snk_rty_o <= snk_out.rty;
end wrapper;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/platform/virtex6/chipscope/ila/chipscope_ila_1024.vhd | 2 | 1215 | -------------------------------------------------------------------------------
-- Copyright (c) 2013 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_ila_1024.vhd
-- /___/ /\ Timestamp : Tue Aug 13 15:39:30 BRT 2013
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_ila_1024 IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
TRIG0: in std_logic_vector(7 downto 0);
TRIG1: in std_logic_vector(31 downto 0);
TRIG2: in std_logic_vector(31 downto 0);
TRIG3: in std_logic_vector(31 downto 0);
TRIG4: in std_logic_vector(31 downto 0));
END chipscope_ila_1024;
ARCHITECTURE chipscope_ila_1024_a OF chipscope_ila_1024 IS
BEGIN
END chipscope_ila_1024_a;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_control_io.vhd | 1 | 55739 | --*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Application: MIG
-- \ \ Filename: phy_control_io.vhd
-- / / Date Last Modified: $Date: 2011/06/02 07:18:12 $
-- /___/ /\ Date Created: Aug 03 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Instantiates IOB blocks for output-only control/address signals to DRAM.
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_control_io.vhd,v 1.1 2011/06/02 07:18:12 mishra Exp $
--**$Date: 2011/06/02 07:18:12 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_control_io.vhd,v $
--******************************************************************************
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_control_io is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
BANK_WIDTH : integer := 2; -- # of bank bits
RANK_WIDTH : integer := 1; -- log2(CS_WIDTH)
nCS_PER_RANK : integer := 1; -- # of unique CS outputs per rank
CS_WIDTH : integer := 1; -- # of DRAM ranks
CKE_WIDTH : integer := 1; -- # of DRAM ranks
ROW_WIDTH : integer := 14; -- DRAM address bus width
WRLVL : string := "OFF"; -- Enable write leveling
nCWL : integer := 5; -- Write Latency
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
REG_CTRL : string := "ON"; -- "ON" for registered DIMM
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
IODELAY_HP_MODE : string := "ON"; -- IODELAY High Performance Mode
IODELAY_GRP : string := "IODELAY_MIG"; -- May be assigned unique name
-- when mult IP cores in design
DDR2_EARLY_CS : integer := 0 -- set = 1 for >200 MHz DDR2 UDIMM designs
-- for early launch of CS
);
port (
clk_mem : in std_logic;-- full rate core clock
clk : in std_logic;-- half rate core clock
rst : in std_logic;-- half rate core clk reset
mc_data_sel : in std_logic;-- =1 for MC control, =0 for PHY
dfi_address0 : in std_logic_vector(ROW_WIDTH - 1 downto 0);
dfi_address1 : in std_logic_vector(ROW_WIDTH - 1 downto 0);
dfi_bank0 : in std_logic_vector(BANK_WIDTH - 1 downto 0);
dfi_bank1 : in std_logic_vector(BANK_WIDTH - 1 downto 0);
dfi_cas_n0 : in std_logic;
dfi_cas_n1 : in std_logic;
dfi_cke0 : in std_logic_vector(CKE_WIDTH - 1 downto 0);
dfi_cke1 : in std_logic_vector(CKE_WIDTH - 1 downto 0);
dfi_cs_n0 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
dfi_cs_n1 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
dfi_odt0 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
dfi_odt1 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
dfi_ras_n0 : in std_logic;
dfi_ras_n1 : in std_logic;
dfi_reset_n : in std_logic;
dfi_we_n0 : in std_logic;
dfi_we_n1 : in std_logic;
-- DFI address/control
phy_address0 : in std_logic_vector(ROW_WIDTH - 1 downto 0);
phy_address1 : in std_logic_vector(ROW_WIDTH - 1 downto 0);
phy_bank0 : in std_logic_vector(BANK_WIDTH - 1 downto 0);
phy_bank1 : in std_logic_vector(BANK_WIDTH - 1 downto 0);
phy_cas_n0 : in std_logic;
phy_cas_n1 : in std_logic;
phy_cke0 : in std_logic_vector(CKE_WIDTH - 1 downto 0);
phy_cke1 : in std_logic_vector(CKE_WIDTH - 1 downto 0);
phy_cs_n0 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_cs_n1 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_odt0 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_odt1 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_ras_n0 : in std_logic;
phy_ras_n1 : in std_logic;
phy_reset_n : in std_logic;
phy_we_n0 : in std_logic;
phy_we_n1 : in std_logic;
-- DDR3-side address/control
ddr_addr : out std_logic_vector(ROW_WIDTH - 1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH - 1 downto 0);
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_cke : out std_logic_vector(CKE_WIDTH - 1 downto 0);
ddr_cs_n : out std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
ddr_odt : out std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
ddr_parity : out std_logic;
ddr_reset_n : out std_logic
);
end phy_control_io;
architecture arch_phy_control_io of phy_control_io is
function CALC_SINGLE_RANK_CS return integer is
begin
if ((REG_CTRL = "ON") and (DRAM_TYPE = "DDR3") and (CS_WIDTH = 1) and (nCS_PER_RANK = 2)) then
return 1;
else
return 0;
end if;
end function CALC_SINGLE_RANK_CS;
function CALC_HIGH_PERFORMANCE_MODE return boolean is
begin
if (IODELAY_HP_MODE = "OFF") then
return FALSE;
else
return TRUE;
end if;
end function CALC_HIGH_PERFORMANCE_MODE;
function XOR_BR (val : std_logic_vector) return std_logic is
variable rtn : std_logic := '0';
begin
for index in val'range loop
rtn := rtn xor val(index);
end loop;
return(rtn);
end function XOR_BR;
-- Set performance mode for IODELAY (power vs. performance tradeoff)
-- COMMENTED, 022009, RICHC. This is temporary pending IR 509123
constant HIGH_PERFORMANCE_MODE : boolean := CALC_HIGH_PERFORMANCE_MODE;
-- local parameter for the single rank DDR3 dimm case. This parameter will be
-- set when the number of chip selects is == 2 for a single rank registered
-- dimm.
constant SINGLE_RANK_CS_REG : integer := CALC_SINGLE_RANK_CS;
signal mux_addr0 : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal mux_addr1 : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal mux_ba0 : std_logic_vector(BANK_WIDTH - 1 downto 0);
signal mux_ba1 : std_logic_vector(BANK_WIDTH - 1 downto 0);
signal mux_cas_n0 : std_logic;
signal mux_cas_n1 : std_logic;
signal mux_cke0 : std_logic_vector(CKE_WIDTH - 1 downto 0);
signal mux_cke1 : std_logic_vector(CKE_WIDTH - 1 downto 0);
signal mux_cs_n0 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_cs_n1 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_cs_d1 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_cs_d2 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_cs_d3 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_cs_d4 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_ioconfig : std_logic_vector(0 downto 0);
signal mux_ioconfig_en : std_logic;
signal mux_odt0 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_odt1 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_ras_n0 : std_logic;
signal mux_ras_n1 : std_logic;
signal mux_reset_n : std_logic;
signal mux_we_n0 : std_logic;
signal mux_we_n1 : std_logic;
signal oce_temp : std_logic;
signal parity0 : std_logic;
signal parity1 : std_logic;
signal rst_delayed : std_logic_vector(3 downto 0);
signal addr_odelay : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal addr_oq : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal ba_odelay : std_logic_vector(BANK_WIDTH - 1 downto 0);
signal ba_oq : std_logic_vector(BANK_WIDTH - 1 downto 0);
signal cas_n_odelay : std_logic;
signal cas_n_oq : std_logic;
signal cke_odelay : std_logic_vector(CKE_WIDTH - 1 downto 0);
signal cke_oq : std_logic_vector(CKE_WIDTH - 1 downto 0);
signal cs_n_odelay : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal cs_n_oq : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal odt_odelay : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal odt_oq : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal parity_odelay : std_logic;
signal parity_oq : std_logic;
signal reset_n_oq : std_logic;
signal ras_n_odelay : std_logic;
signal ras_n_oq : std_logic;
signal rst_cke_odt : std_logic;
signal rst_r : std_logic;
signal oce_hack_r : std_logic;
signal oce_hack_r1 : std_logic;
signal oce_hack_r2 : std_logic;
signal oce_hack_r3 : std_logic;
signal oce_hack_r4 : std_logic;
signal oce_hack_r5 : std_logic;
-- synthesis syn_keep = 1
signal we_n_odelay : std_logic;
signal we_n_oq : std_logic;
attribute IODELAY_GROUP : string;
begin
-- XST attributes for local reset tree RST_R - prohibit equivalent
-- register removal on RST_R to prevent "sharing" w/ other local reset trees
-- synthesis attribute shreg_extract of rst_r is "no";
-- synthesis attribute equivalent_register_removal of rst_r is "no"
--***************************************************************************
-- Reset pipelining - register reset signals to prevent large (and long)
-- fanouts during physical compilation of the design. Create one local reset
-- for most control/address OSERDES blocks - note that user may need to
-- change this if control/address are more "spread out" through FPGA
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
rst_r <= rst after (TCQ)*1 ps;
end if;
end process;
--***************************************************************************
-- Generate delayed version of global reset.
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
rst_delayed(0) <= rst after (TCQ)*1 ps;
rst_delayed(1) <= rst_delayed(0) after (TCQ)*1 ps;
rst_delayed(2) <= rst_delayed(1) after (TCQ)*1 ps;
rst_delayed(3) <= rst_delayed(2) after (TCQ)*1 ps;
end if;
end process;
-- Drive ODT and CKE OSERDES with these resets in order to ensure that
-- they remain low until after DDR_RESET_N is deasserted. This is done for
-- simulation reasons only, as some memory models will issue an error if
-- ODT/CKE are asserted prior to deassertion of RESET_N
rst_cke_odt <= rst_delayed(3);
--***************************************************************************
-- The following logic is only required to support DDR2 simulation, and is
-- done to prevent glitching on the ODT and CKE signals after "power-up".
-- Certain models will flag glitches on these lines as errors.
-- To fix this, the OCE for OSERDES is used to prevent glitches. However,
-- this may lead to setup time issues when running this design through
-- ISE - because the OCE setup is w/r/t to CLK (i.e. the "fast" clock).
-- It can be problematic to meet timing - therefore this path should be
-- marked as a false path (TIG) because it will be asserted long before
-- the OSERDES outputs need to be valid. This logic is disabled for the
-- DDR3 case because it is not required
-- LOGIC DESCRIPTION:
-- Generating OCE for DDR2 ODT & CKE. The output of the OSERDES model toggles
-- when it comes out of reset. This causes issues in simulation. Controlling
-- it OCE until there is a library fix. OCE will be asserted after 10 clks
-- after reset de-assertion
process (clk)
begin
if (clk'event and clk = '1') then
oce_hack_r <= not(rst_delayed(3)) after TCQ*1 ps;
oce_hack_r1 <= oce_hack_r after TCQ*1 ps;
oce_hack_r2 <= oce_hack_r1 after TCQ*1 ps;
oce_hack_r3 <= oce_hack_r2 after TCQ*1 ps;
oce_hack_r4 <= oce_hack_r3 after TCQ*1 ps;
oce_hack_r5 <= oce_hack_r4 after TCQ*1 ps;
end if;
end process;
-- Only use for DDR2. For DDR3, drive to constant high
oce_temp <= oce_hack_r5 when (DRAM_TYPE = "DDR2") else
'1';
--***************************************************************************
-- MUX to choose from either PHY or controller for DRAM control
-- NOTE: May need to add pipeline register to meet timing
--***************************************************************************
mux_addr0 <= dfi_address0 when (mc_data_sel = '1') else
phy_address0;
mux_addr1 <= dfi_address1 when (mc_data_sel = '1') else
phy_address1;
mux_ba0 <= dfi_bank0 when (mc_data_sel = '1') else
phy_bank0;
mux_ba1 <= dfi_bank1 when (mc_data_sel = '1') else
phy_bank1;
mux_cas_n0 <= dfi_cas_n0 when (mc_data_sel = '1') else
phy_cas_n0;
mux_cas_n1 <= dfi_cas_n1 when (mc_data_sel = '1') else
phy_cas_n1;
mux_cke0 <= dfi_cke0 when (mc_data_sel = '1') else
phy_cke0;
mux_cke1 <= dfi_cke1 when (mc_data_sel = '1') else
phy_cke1;
mux_odt0 <= dfi_odt0 when (mc_data_sel = '1') else
phy_odt0;
mux_odt1 <= dfi_odt1 when (mc_data_sel = '1') else
phy_odt1;
mux_ras_n0 <= dfi_ras_n0 when (mc_data_sel = '1') else
phy_ras_n0;
mux_ras_n1 <= dfi_ras_n1 when (mc_data_sel = '1') else
phy_ras_n1;
mux_reset_n <= dfi_reset_n when (mc_data_sel = '1') else
phy_reset_n;
mux_we_n0 <= dfi_we_n0 when (mc_data_sel = '1') else
phy_we_n0;
mux_we_n1 <= dfi_we_n1 when (mc_data_sel = '1') else
phy_we_n1;
--***************************************************************************
-- assigning chip select values.
-- For DDR3 Registered dimm's the chip select pins are toggled in a unique
-- way to differentiate between register programming and regular DIMM access.
-- For a single rank registered dimm with two chip selects the chip select
-- will be toggled in the following manner:
-- cs[0] =0, cs[1] = 0 the access is to the registered chip. On the
-- remaining combinations the access is to the DIMM. The SINGLE_RANK_CS_REG
-- parameter will be set for the above configurations and the chip select
-- pins will be toggled as per the DDR3 registered DIMM requirements. The
-- phy takes care of the register programming, and handles the chip
-- select's correctly for calibration and initialization. But the controller
-- does not know about this mode, the controller cs[1] bits will be tied to
-- 1'b1; All the controller access will be to the DIMM and none to the
-- register chip. Rest of the DDR3 register dimm configurations are
-- handled well by the controller.
--***************************************************************************
gen_single_rank : if (SINGLE_RANK_CS_REG = 1) generate
process (mc_data_sel, dfi_cs_n0(0), dfi_cs_n1(0), phy_cs_n0(0), phy_cs_n1(0), phy_cs_n0(1), phy_cs_n1(1))
begin
if (mc_data_sel = '1') then
mux_cs_n0(0) <= dfi_cs_n0(0);
mux_cs_n1(0) <= dfi_cs_n1(0);
mux_cs_n0(1) <= '1';
mux_cs_n1(1) <= '1';
else
mux_cs_n0(0) <= phy_cs_n0(0);
mux_cs_n1(0) <= phy_cs_n1(0);
mux_cs_n0(1) <= phy_cs_n0(1);
mux_cs_n1(1) <= phy_cs_n1(1);
end if;
end process;
end generate;
gen_mult_rank : if (SINGLE_RANK_CS_REG /= 1) generate
process (mc_data_sel, dfi_cs_n0, dfi_cs_n1, phy_cs_n0, phy_cs_n1)
begin
if (mc_data_sel = '1') then
mux_cs_n0 <= dfi_cs_n0;
mux_cs_n1 <= dfi_cs_n1;
else
mux_cs_n0 <= phy_cs_n0;
mux_cs_n1 <= phy_cs_n1;
end if;
end process;
end generate;
-- for DDR2 UDIMM designs the CS has to be launched early.
-- Setting the OSERDES input based on the DDR2_EARLY_CS parameter.
-- when this paramter is CS will be launched half a cycle early.
-- Launching half a cycle early will cause simulation issues.
-- Using synthesis options to control the assignment
process (mux_cs_n0,mux_cs_n1)
begin
if(DDR2_EARLY_CS = 1) then
mux_cs_d1 <= mux_cs_n0;
mux_cs_d2 <= mux_cs_n1;
mux_cs_d3 <= mux_cs_n1;
mux_cs_d4 <= mux_cs_n0;
else
mux_cs_d1 <= mux_cs_n0;
mux_cs_d2 <= mux_cs_n0;
mux_cs_d3 <= mux_cs_n1;
mux_cs_d4 <= mux_cs_n1;
end if; -- else: !if(DDR2_EARLY_CS == 1)
-- For simulation override the assignment for
-- synthesis do not override
-- synthesis translate_off
mux_cs_d1 <= mux_cs_n0;
mux_cs_d2 <= mux_cs_n0;
mux_cs_d3 <= mux_cs_n1;
mux_cs_d4 <= mux_cs_n1;
-- synthesis translate_on
end process;
-- parity for reg dimm. Have to check the timing impact.
-- Generate only for DDR3 RDIMM.
-- registring with negedge. Half cycle path.
gen_ddr3_parity : if ((DRAM_TYPE = "DDR3") and (REG_CTRL = "ON")) generate
parity0 <= (XOR_BR(mux_addr0 & mux_ba0 & mux_cas_n0 & mux_ras_n0 & mux_we_n0));
process (clk)
begin
if (clk'event and clk = '1') then
parity1 <= (XOR_BR(mux_addr1 & mux_ba1 & mux_cas_n1 & mux_ras_n1 & mux_we_n1)) after (TCQ)*1 ps;
end if;
end process;
end generate;
gen_ddr3_noparity : if (not(DRAM_TYPE = "DDR3") or not(REG_CTRL = "ON")) generate
process (clk)
begin
if (clk'event and clk = '1') then
parity0 <= '0' after (TCQ)*1 ps;
parity1 <= '0' after (TCQ)*1 ps;
end if;
end process;
end generate;
--*****************************************************************
-- DDR3 reset: Note that this output is generated with an ODDR clocked
-- by the internal div-by-2 clock. It can be generated using the same
-- OSERDES structure as for the other control/address signals. However
-- there are no specific setup/hold requirements on reset_n w/r/t CK.
-- In addition, this an ODDR was used to prevent any glitching on reset_n
-- during startup. This was done for simulation considerations only -
-- the glitch causes warnings with the Denali DDR3 model (but will not
-- cause any issues in hardware).
--*****************************************************************
u_out_reset_n : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
Q => reset_n_oq,
C => clk,
CE => '1',
D1 => mux_reset_n,
D2 => mux_reset_n,
R => rst_r,
S => '0'
);
u_reset_n_obuf : OBUF
port map (
I => reset_n_oq,
O => ddr_reset_n
);
--*****************************************************************
-- Note on generation of Control/Address signals - there are
-- several possible configurations that affect the configuration
-- of the OSERDES and possible ODELAY for each output (this will
-- also affect the CK/CK# outputs as well
-- 1. DDR3, write-leveling: This is the simplest case. Use
-- OSERDES without the ODELAY. Initially clock/control/address
-- will be offset coming out of FPGA from DQ/DQS, but DQ/DQS
-- will be adjusted so that DQS-CK alignment is established
-- 2. DDR2 or DDR3 (no write-leveling): Both DQS and DQ will use
-- ODELAY to delay output of OSERDES. To match this,
-- CK/control/address must also delay their outputs using ODELAY
-- (with delay = 0)
--*****************************************************************
--*****************************************************************
-- RAS: = 1 at reset
--*****************************************************************
gen_ras_n_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
--*******************************************************
-- CASE1: DDR3, write-leveling
--*******************************************************
u_ras_n_obuf : OBUF
port map (
I => ras_n_oq,
O => ddr_ras_n
);
end generate;
gen_ras_n_nowrlvl: if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_ras_n : label is IODELAY_GRP;
begin
--*******************************************************
-- CASE2: DDR3, no write-leveling
--*******************************************************
u_ras_n_obuf : OBUF
port map (
I => ras_n_odelay,
O => ddr_ras_n
);
u_iodelay_ras_n : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => ras_n_odelay,
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => ras_n_oq,
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_ras_n : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '1', -- 1 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => ras_n_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_ras_n0,
D2 => mux_ras_n0,
D3 => mux_ras_n1,
D4 => mux_ras_n1,
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_r,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
--*******************************************************
-- CAS: = 1 at reset
--*******************************************************
gen_cas_n_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_cas_n_obuf : OBUF
port map (
I => cas_n_oq,
O => ddr_cas_n
);
end generate;
gen_cas_n_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_cas_n : label is IODELAY_GRP;
begin
u_cas_n_obuf : OBUF
port map (
I => cas_n_odelay,
O => ddr_cas_n
);
u_iodelay_cas_n : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => cas_n_odelay,
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => cas_n_oq,
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_cas_n : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '1', -- 1 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => cas_n_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_cas_n0,
D2 => mux_cas_n0,
D3 => mux_cas_n1,
D4 => mux_cas_n1,
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_r,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
--*******************************************************
-- WE: = 1 at reset
--*******************************************************
gen_we_n_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_we_n_obuf : OBUF
port map (
I => we_n_oq,
O => ddr_we_n
);
end generate;
gen_we_n_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_we_n : label is IODELAY_GRP;
begin
u_we_n_obuf : OBUF
port map (
I => we_n_odelay,
O => ddr_we_n
);
u_iodelay_we_n : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => we_n_odelay,
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => we_n_oq,
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_we_n : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '1', -- 1 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => we_n_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_we_n0,
D2 => mux_we_n0,
D3 => mux_we_n1,
D4 => mux_we_n1,
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_r,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
--*******************************************************
-- CKE: = 0 at reset
--*******************************************************
gen_cke: for cke_i in 0 to (CKE_WIDTH-1) generate
gen_cke_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_cke_obuf : OBUF
port map (
I => cke_oq(cke_i),
O => ddr_cke(cke_i)
);
end generate;
gen_cke_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_cke : label is IODELAY_GRP;
begin
u_cke_obuf : OBUF
port map (
I => cke_odelay(cke_i),
O => ddr_cke(cke_i)
);
u_iodelay_cke : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => cke_odelay(cke_i),
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => cke_oq(cke_i),
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_cke : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0', -- 0 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => cke_oq(cke_i),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_cke0(cke_i),
D2 => mux_cke0(cke_i),
D3 => mux_cke1(cke_i),
D4 => mux_cke1(cke_i),
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => oce_temp,
-- Connect SHIFTIN1, SHIFTIN2 to 0 for simulation purposes
-- (for all other OSERDES used in design, these are no-connects):
-- ensures that CKE outputs are not X at start of simulation
-- Certain DDR2 memory models may require that CK/CK# be valid
-- throughout simulation
SHIFTIN1 => '0',
SHIFTIN2 => '0',
RST => rst_cke_odt,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
end generate;
--*******************************************************
-- chip select = 1 at reset
--*******************************************************
gen_cs_n: for cs_i in 0 to (CS_WIDTH*nCS_PER_RANK - 1) generate
gen_cs_n_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_cs_n_obuf : OBUF
port map (
I => cs_n_oq(cs_i),
O => ddr_cs_n(cs_i)
);
end generate;
gen_cs_n_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_cs_n : label is IODELAY_GRP;
begin
u_cs_n_obuf : OBUF
port map (
I => cs_n_odelay(cs_i),
O => ddr_cs_n(cs_i)
);
u_iodelay_cs_n : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => cs_n_odelay(cs_i),
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => cs_n_oq(cs_i),
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_cs_n : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '1', -- 1 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => cs_n_oq(cs_i),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_cs_d1(cs_i),
D2 => mux_cs_d2(cs_i),
D3 => mux_cs_d3(cs_i),
D4 => mux_cs_d4(cs_i),
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_r,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
end generate;
--*******************************************************
-- address = X at reset
--*******************************************************
gen_addr: for addr_i in 0 to (ROW_WIDTH - 1) generate
gen_addr_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_addr_obuf : OBUF
port map (
I => addr_oq(addr_i),
O => ddr_addr(addr_i)
);
end generate;
gen_addr_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_addr : label is IODELAY_GRP;
begin
u_addr_obuf : OBUF
port map (
I => addr_odelay(addr_i),
O => ddr_addr(addr_i)
);
u_iodelay_addr : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => addr_odelay(addr_i),
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => addr_oq(addr_i),
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_addr : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0', -- 0 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => addr_oq(addr_i),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_addr0(addr_i),
D2 => mux_addr0(addr_i),
D3 => mux_addr1(addr_i),
D4 => mux_addr1(addr_i),
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_r,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
end generate;
--*******************************************************
-- bank address = X at reset
--*******************************************************
gen_ba: for ba_i in 0 to (BANK_WIDTH - 1) generate
gen_ba_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_ba_obuf : OBUF
port map (
I => ba_oq(ba_i),
O => ddr_ba(ba_i)
);
end generate;
gen_ba_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_ba : label is IODELAY_GRP;
begin
u_ba_obuf : OBUF
port map (
I => ba_odelay(ba_i),
O => ddr_ba(ba_i)
);
u_iodelay_ba : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => ba_odelay(ba_i),
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => ba_oq(ba_i),
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_ba : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0', -- 0 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => ba_oq(ba_i),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_ba0(ba_i),
D2 => mux_ba0(ba_i),
D3 => mux_ba1(ba_i),
D4 => mux_ba1(ba_i),
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_r,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
end generate;
--*****************************************************************
-- ODT control = 0 at reset
--*****************************************************************
gen_odt : for odt_i in 0 to (CS_WIDTH*nCS_PER_RANK - 1) generate
gen_odt_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_odt_obuf : OBUF
port map (
I => odt_oq(odt_i),
O => ddr_odt(odt_i)
);
end generate;
gen_odt_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_odt : label is IODELAY_GRP;
begin
u_odt_obuf : OBUF
port map (
I => odt_odelay(odt_i),
O => ddr_odt(odt_i)
);
u_iodelay_odt : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => odt_odelay(odt_i),
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => odt_oq(odt_i),
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_odt : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0', -- 0 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => odt_oq(odt_i),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_odt0(odt_i),
D2 => mux_odt0(odt_i),
D3 => mux_odt1(odt_i),
D4 => mux_odt1(odt_i),
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => oce_temp,
-- Connect SHIFTIN1, SHIFTIN2 to 0 for simulation purposes
-- (for all other OSERDES used in design, these are no-connects):
-- ensures that ODT outputs are not X at start of simulation
-- Certain DDR2 memory models may require that CK/CK# be valid
-- throughout simulation
SHIFTIN1 => '0',
SHIFTIN2 => '0',
RST => rst_cke_odt,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
end generate;
--*********************************************************************
-- Parity for reg dimm. Parity output one cycle after the cs assertion
--*********************************************************************
gen_parity_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_parity_obuf : OBUF
port map (
I => parity_oq,
O => ddr_parity
);
end generate;
gen_parity_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_parity : label is IODELAY_GRP;
begin
u_parity_obuf : OBUF
port map (
I => parity_odelay,
O => ddr_parity
);
u_iodelay_parity : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => parity_odelay,
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => parity_oq,
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_parity : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '1', -- 1 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => parity_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => parity1,
D2 => parity1,
D3 => parity0,
D4 => parity0,
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_r,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
end arch_phy_control_io;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/rd_bitslip.vhd | 1 | 6578 | --*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: rd_bitslip.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:13 $
-- \ \ / \ Date Created: Aug 03 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Shifts and delays data from ISERDES, in both memory clock and internal
-- clock cycles. Used to uniquely shift/delay each byte to align all bytes
-- in data word
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: rd_bitslip.vhd,v 1.1 2011/06/02 07:18:13 mishra Exp $
--**$Date: 2011/06/02 07:18:13 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/rd_bitslip.vhd,v $
--******************************************************************************
library unisim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity rd_bitslip is
generic (
TCQ : integer := 100
);
port (
clk : in std_logic;
bitslip_cnt : in std_logic_vector(1 downto 0);
clkdly_cnt : in std_logic_vector(1 downto 0);
din : in std_logic_vector(5 downto 0);
qout : out std_logic_vector(3 downto 0)
);
end rd_bitslip;
architecture trans_rd_bitslip of rd_bitslip is
signal din2_r : std_logic;
signal slip_out : std_logic_vector(3 downto 0);
signal slip_out_r : std_logic_vector(3 downto 0);
signal slip_out_r2 : std_logic_vector(3 downto 0);
signal slip_out_r3 : std_logic_vector(3 downto 0);
begin
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
din2_r <= din(2) after (TCQ)*1 ps;
end if;
end process;
--Can shift data from ISERDES from 0-3 fast clock cycles
--NOTE: This is coded combinationally, in order to allow register to
--occur after MUXing of delayed outputs. Timing may be difficult to
--meet on this logic, if necessary, the register may need to be moved
--here instead, or another register added.
process (bitslip_cnt, din, din2_r)
begin
case bitslip_cnt is
when "00" => -- No slip
slip_out <= (din(3) & din(2) & din(1) & din(0));
when "01" => -- Slip = 0.5 cycle
slip_out <= (din(4) & din(3) & din(2) & din(1));
when "10" => -- Slip = 1 cycle
slip_out <= (din(5) & din(4) & din(3) & din(2));
when "11" => -- Slip = 1.5 cycle
slip_out <= (din2_r & din(5) & din(4) & din(3));
when others =>
null;
end case;
end process;
--Can delay up to 3 additional internal clock cycles - this accounts
--not only for delays due to DRAM, PCB routing between different bytes,
--but also differences within the FPGA - e.g. clock skew between different
--I/O columns, and differences in latency between different circular
--buffers or whatever synchronization method (FIFO) is used to get the
--data into the global clock domain
process (clk)
begin
if (clk'event and clk = '1') then
slip_out_r <= slip_out after TCQ*1 ps;
slip_out_r2 <= slip_out_r after TCQ*1 ps;
slip_out_r3 <= slip_out_r2 after TCQ*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
case clkdly_cnt is
when "00" =>
qout <= slip_out after (TCQ)*1 ps;
when "01" =>
qout <= slip_out_r after (TCQ)*1 ps;
when "10" =>
qout <= slip_out_r2 after (TCQ)*1 ps;
when "11" =>
qout <= slip_out_r3 after (TCQ)*1 ps;
when others =>
null;
end case;
end if;
end process;
end trans_rd_bitslip;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/prime_FIFO_plain.vhd | 1 | 28991 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.49d
-- \ \ Application: netgen
-- / / Filename: prime_FIFO_plain.vhd
-- /___/ /\ Timestamp: Thu Feb 21 12:30:48 2013
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/prime_FIFO_plain.ngc /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/prime_FIFO_plain.vhd
-- Device : 7a200tffg1156-2
-- Input file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/prime_FIFO_plain.ngc
-- Output file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/prime_FIFO_plain.vhd
-- # of Entities : 2
-- Design Name : prime_FIFO_plain
-- Xilinx : /opt/Xilinx/14.4/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity reset_builtin is
port (
CLK : in STD_LOGIC := 'X';
WR_CLK : in STD_LOGIC := 'X';
RD_CLK : in STD_LOGIC := 'X';
INT_CLK : in STD_LOGIC := 'X';
RST : in STD_LOGIC := 'X';
WR_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
RD_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
INT_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end reset_builtin;
architecture STRUCTURE of reset_builtin is
signal wr_rst_reg_3 : STD_LOGIC;
signal rd_rst_reg_15 : STD_LOGIC;
signal wr_rst_reg_GND_25_o_MUX_1_o : STD_LOGIC;
signal rd_rst_reg_GND_25_o_MUX_2_o : STD_LOGIC;
signal wr_rst_fb : STD_LOGIC_VECTOR ( 4 downto 0 );
signal power_on_wr_rst : STD_LOGIC_VECTOR ( 5 downto 0 );
signal rd_rst_fb : STD_LOGIC_VECTOR ( 4 downto 0 );
signal power_on_rd_rst : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NlwRenamedSignal_WR_RST_I : STD_LOGIC_VECTOR ( 0 downto 0 );
signal NlwRenamedSig_OI_n0019 : STD_LOGIC_VECTOR ( 5 downto 5 );
begin
WR_RST_I(1) <= NlwRenamedSignal_WR_RST_I(0);
WR_RST_I(0) <= NlwRenamedSignal_WR_RST_I(0);
INT_RST_I(1) <= NlwRenamedSig_OI_n0019(5);
INT_RST_I(0) <= NlwRenamedSig_OI_n0019(5);
XST_GND : GND
port map (
G => NlwRenamedSig_OI_n0019(5)
);
wr_rst_fb_0 : FD
generic map(
INIT => '0'
)
port map (
C => WR_CLK,
D => wr_rst_fb(1),
Q => wr_rst_fb(0)
);
wr_rst_fb_1 : FD
generic map(
INIT => '0'
)
port map (
C => WR_CLK,
D => wr_rst_fb(2),
Q => wr_rst_fb(1)
);
wr_rst_fb_2 : FD
generic map(
INIT => '0'
)
port map (
C => WR_CLK,
D => wr_rst_fb(3),
Q => wr_rst_fb(2)
);
wr_rst_fb_3 : FD
generic map(
INIT => '0'
)
port map (
C => WR_CLK,
D => wr_rst_fb(4),
Q => wr_rst_fb(3)
);
wr_rst_fb_4 : FD
generic map(
INIT => '0'
)
port map (
C => WR_CLK,
D => wr_rst_reg_3,
Q => wr_rst_fb(4)
);
power_on_wr_rst_0 : FD
generic map(
INIT => '1'
)
port map (
C => WR_CLK,
D => power_on_wr_rst(1),
Q => power_on_wr_rst(0)
);
power_on_wr_rst_1 : FD
generic map(
INIT => '1'
)
port map (
C => WR_CLK,
D => power_on_wr_rst(2),
Q => power_on_wr_rst(1)
);
power_on_wr_rst_2 : FD
generic map(
INIT => '1'
)
port map (
C => WR_CLK,
D => power_on_wr_rst(3),
Q => power_on_wr_rst(2)
);
power_on_wr_rst_3 : FD
generic map(
INIT => '1'
)
port map (
C => WR_CLK,
D => power_on_wr_rst(4),
Q => power_on_wr_rst(3)
);
power_on_wr_rst_4 : FD
generic map(
INIT => '1'
)
port map (
C => WR_CLK,
D => power_on_wr_rst(5),
Q => power_on_wr_rst(4)
);
power_on_wr_rst_5 : FD
generic map(
INIT => '1'
)
port map (
C => WR_CLK,
D => NlwRenamedSig_OI_n0019(5),
Q => power_on_wr_rst(5)
);
rd_rst_fb_0 : FD
generic map(
INIT => '0'
)
port map (
C => RD_CLK,
D => rd_rst_fb(1),
Q => rd_rst_fb(0)
);
rd_rst_fb_1 : FD
generic map(
INIT => '0'
)
port map (
C => RD_CLK,
D => rd_rst_fb(2),
Q => rd_rst_fb(1)
);
rd_rst_fb_2 : FD
generic map(
INIT => '0'
)
port map (
C => RD_CLK,
D => rd_rst_fb(3),
Q => rd_rst_fb(2)
);
rd_rst_fb_3 : FD
generic map(
INIT => '0'
)
port map (
C => RD_CLK,
D => rd_rst_fb(4),
Q => rd_rst_fb(3)
);
rd_rst_fb_4 : FD
generic map(
INIT => '0'
)
port map (
C => RD_CLK,
D => rd_rst_reg_15,
Q => rd_rst_fb(4)
);
power_on_rd_rst_0 : FD
generic map(
INIT => '1'
)
port map (
C => RD_CLK,
D => power_on_rd_rst(1),
Q => power_on_rd_rst(0)
);
power_on_rd_rst_1 : FD
generic map(
INIT => '1'
)
port map (
C => RD_CLK,
D => power_on_rd_rst(2),
Q => power_on_rd_rst(1)
);
power_on_rd_rst_2 : FD
generic map(
INIT => '1'
)
port map (
C => RD_CLK,
D => power_on_rd_rst(3),
Q => power_on_rd_rst(2)
);
power_on_rd_rst_3 : FD
generic map(
INIT => '1'
)
port map (
C => RD_CLK,
D => power_on_rd_rst(4),
Q => power_on_rd_rst(3)
);
power_on_rd_rst_4 : FD
generic map(
INIT => '1'
)
port map (
C => RD_CLK,
D => power_on_rd_rst(5),
Q => power_on_rd_rst(4)
);
power_on_rd_rst_5 : FD
generic map(
INIT => '1'
)
port map (
C => RD_CLK,
D => NlwRenamedSig_OI_n0019(5),
Q => power_on_rd_rst(5)
);
wr_rst_reg : FDP
generic map(
INIT => '0'
)
port map (
C => WR_CLK,
D => wr_rst_reg_GND_25_o_MUX_1_o,
PRE => RST,
Q => wr_rst_reg_3
);
rd_rst_reg : FDP
generic map(
INIT => '0'
)
port map (
C => RD_CLK,
D => rd_rst_reg_GND_25_o_MUX_2_o,
PRE => RST,
Q => rd_rst_reg_15
);
WR_RST_I_1_1 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wr_rst_reg_3,
I1 => power_on_wr_rst(0),
O => NlwRenamedSignal_WR_RST_I(0)
);
Mmux_wr_rst_reg_GND_25_o_MUX_1_o11 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => wr_rst_fb(0),
I1 => wr_rst_reg_3,
O => wr_rst_reg_GND_25_o_MUX_1_o
);
Mmux_rd_rst_reg_GND_25_o_MUX_2_o11 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => rd_rst_fb(0),
I1 => rd_rst_reg_15,
O => rd_rst_reg_GND_25_o_MUX_2_o
);
end STRUCTURE;
-- synthesis translate_on
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity prime_FIFO_plain is
port (
rst : in STD_LOGIC := 'X';
wr_clk : in STD_LOGIC := 'X';
rd_clk : in STD_LOGIC := 'X';
wr_en : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
full : out STD_LOGIC;
empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 71 downto 0 );
dout : out STD_LOGIC_VECTOR ( 71 downto 0 )
);
end prime_FIFO_plain;
architecture STRUCTURE of prime_FIFO_plain is
component reset_builtin
port (
CLK : in STD_LOGIC := 'X';
WR_CLK : in STD_LOGIC := 'X';
RD_CLK : in STD_LOGIC := 'X';
INT_CLK : in STD_LOGIC := 'X';
RST : in STD_LOGIC := 'X';
WR_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
RD_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
INT_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component;
signal N1 : STD_LOGIC;
signal NlwRenamedSig_OI_empty : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_WR_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
empty <= NlwRenamedSig_OI_empty;
XST_GND : GND
port map (
G => N1
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt : reset_builtin
port map (
CLK => N1,
WR_CLK => wr_clk,
RD_CLK => rd_clk,
INT_CLK => N1,
RST => rst,
WR_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_WR_RST_I_1_UNCONNECTED,
WR_RST_I(0) => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
RD_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_1_UNCONNECTED,
RD_RST_I(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_0_UNCONNECTED,
INT_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_1_UNCONNECTED,
INT_RST_I(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1 : FIFO36E1
generic map(
ALMOST_EMPTY_OFFSET => X"0005",
ALMOST_FULL_OFFSET => X"0010",
DATA_WIDTH => 72,
DO_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
EN_SYN => FALSE,
FIFO_MODE => "FIFO36_72",
FIRST_WORD_FALL_THROUGH => FALSE,
INIT => X"000000000000000000",
SIM_DEVICE => "7SERIES",
SRVAL => X"000000000000000000"
)
port map (
ALMOSTEMPTY =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED
,
ALMOSTFULL => prog_full,
DBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED,
EMPTY => NlwRenamedSig_OI_empty,
FULL => full,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
RDCLK => rd_clk,
RDEN => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp,
RDERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED,
REGCE => N1,
RST => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
RSTREG => N1,
SBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED,
WRCLK => wr_clk,
WREN => wr_en,
WRERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED,
DI(63) => din(67),
DI(62) => din(66),
DI(61) => din(65),
DI(60) => din(64),
DI(59) => din(63),
DI(58) => din(62),
DI(57) => din(61),
DI(56) => din(60),
DI(55) => din(59),
DI(54) => din(58),
DI(53) => din(57),
DI(52) => din(56),
DI(51) => din(55),
DI(50) => din(54),
DI(49) => din(53),
DI(48) => din(52),
DI(47) => din(51),
DI(46) => din(50),
DI(45) => din(49),
DI(44) => din(48),
DI(43) => din(47),
DI(42) => din(46),
DI(41) => din(45),
DI(40) => din(44),
DI(39) => din(43),
DI(38) => din(42),
DI(37) => din(41),
DI(36) => din(40),
DI(35) => din(39),
DI(34) => din(38),
DI(33) => din(37),
DI(32) => din(36),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(7) => din(71),
DIP(6) => din(70),
DIP(5) => din(69),
DIP(4) => din(68),
DIP(3) => din(35),
DIP(2) => din(34),
DIP(1) => din(33),
DIP(0) => din(32),
DO(63) => dout(67),
DO(62) => dout(66),
DO(61) => dout(65),
DO(60) => dout(64),
DO(59) => dout(63),
DO(58) => dout(62),
DO(57) => dout(61),
DO(56) => dout(60),
DO(55) => dout(59),
DO(54) => dout(58),
DO(53) => dout(57),
DO(52) => dout(56),
DO(51) => dout(55),
DO(50) => dout(54),
DO(49) => dout(53),
DO(48) => dout(52),
DO(47) => dout(51),
DO(46) => dout(50),
DO(45) => dout(49),
DO(44) => dout(48),
DO(43) => dout(47),
DO(42) => dout(46),
DO(41) => dout(45),
DO(40) => dout(44),
DO(39) => dout(43),
DO(38) => dout(42),
DO(37) => dout(41),
DO(36) => dout(40),
DO(35) => dout(39),
DO(34) => dout(38),
DO(33) => dout(37),
DO(32) => dout(36),
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(7) => dout(71),
DOP(6) => dout(70),
DOP(5) => dout(69),
DOP(4) => dout(68),
DOP(3) => dout(35),
DOP(2) => dout(34),
DOP(1) => dout(33),
DOP(0) => dout(32),
ECCPARITY(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED
,
RDCOUNT(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED
,
RDCOUNT(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED
,
RDCOUNT(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED
,
RDCOUNT(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED
,
RDCOUNT(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED
,
RDCOUNT(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED
,
RDCOUNT(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED
,
RDCOUNT(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED
,
RDCOUNT(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED
,
RDCOUNT(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED
,
RDCOUNT(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED
,
RDCOUNT(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED
,
RDCOUNT(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED
,
WRCOUNT(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED
,
WRCOUNT(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED
,
WRCOUNT(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED
,
WRCOUNT(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED
,
WRCOUNT(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED
,
WRCOUNT(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED
,
WRCOUNT(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED
,
WRCOUNT(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED
,
WRCOUNT(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED
,
WRCOUNT(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED
,
WRCOUNT(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED
,
WRCOUNT(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED
,
WRCOUNT(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_empty,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp
);
end STRUCTURE;
-- synthesis translate_on
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd | 1 | 109486 | ------------------------------------------------------------------------------
-- Title : Top DSP design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-09-01
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the DSP with
-- FMC130M_4ch board
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-09-01 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Custom common cores
use work.dbe_common_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_generic_pkg.all;
-- Ethernet MAC Modules and SDB structure
use work.ethmac_pkg.all;
-- Wishbone Fabric interface
use work.wr_fabric_pkg.all;
-- Etherbone slave core
use work.etherbone_pkg.all;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
-- DSP definitions
use work.dsp_cores_pkg.all;
-- Genrams
use work.genram_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_dsp is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
rs232_txd_o : out std_logic;
rs232_rxd_i : in std_logic;
--uart_txd_o : out std_logic;
--uart_rxd_i : in std_logic;
-----------------------------------------
-- PHY pins
-----------------------------------------
-- Clock and resets to PHY (GMII). Not used in MII mode (10/100)
mgtx_clk_o : out std_logic;
mrstn_o : out std_logic;
-- PHY TX
mtx_clk_pad_i : in std_logic;
mtxd_pad_o : out std_logic_vector(3 downto 0);
mtxen_pad_o : out std_logic;
mtxerr_pad_o : out std_logic;
-- PHY RX
mrx_clk_pad_i : in std_logic;
mrxd_pad_i : in std_logic_vector(3 downto 0);
mrxdv_pad_i : in std_logic;
mrxerr_pad_i : in std_logic;
mcoll_pad_i : in std_logic;
mcrs_pad_i : in std_logic;
-- MII
mdc_pad_o : out std_logic;
md_pad_b : inout std_logic;
-----------------------------
-- FMC130m_4ch ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o : out std_logic;
fmc_adc_shdn_o : out std_logic;
fmc_adc_dith_o : out std_logic;
fmc_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc_adc0_clk_i : in std_logic;
fmc_adc0_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc0_of_i : in std_logic; -- Unused
-- ADC1 LTC2208
fmc_adc1_clk_i : in std_logic;
fmc_adc1_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc1_of_i : in std_logic; -- Unused
-- ADC2 LTC2208
fmc_adc2_clk_i : in std_logic;
fmc_adc2_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc2_of_i : in std_logic; -- Unused
-- ADC3 LTC2208
fmc_adc3_clk_i : in std_logic;
fmc_adc3_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc3_of_i : in std_logic; -- Unused
-- FMC General Status
fmc_prsnt_i : in std_logic;
fmc_pg_m2c_i : in std_logic;
--fmc_clk_dir_i : in std_logic;, -- not supported on Kintex7 KC705 board
-- Trigger
fmc_trig_dir_o : out std_logic;
fmc_trig_term_o : out std_logic;
fmc_trig_val_p_b : inout std_logic;
fmc_trig_val_n_b : inout std_logic;
-- Si571 clock gen
si571_scl_pad_b : inout std_logic;
si571_sda_pad_b : inout std_logic;
fmc_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
spi_ad9510_cs_o : out std_logic;
spi_ad9510_sclk_o : out std_logic;
spi_ad9510_mosi_o : out std_logic;
spi_ad9510_miso_i : in std_logic;
fmc_pll_function_o : out std_logic;
fmc_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc_fpga_clk_p_i : in std_logic;
fmc_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o : out std_logic;
-- EEPROM
eeprom_scl_pad_b : inout std_logic;
eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor (LM75AIMM)
lm75_scl_pad_b : inout std_logic;
lm75_sda_pad_b : inout std_logic;
fmc_lm75_temp_alarm_i : in std_logic;
-- FMC LEDs
fmc_led1_o : out std_logic;
fmc_led2_o : out std_logic;
fmc_led3_o : out std_logic;
-----------------------------------------
-- Position Calc signals
-----------------------------------------
-- Uncross signals
clk_swap_o : out std_logic;
clk_swap2x_o : out std_logic;
flag1_o : out std_logic;
flag2_o : out std_logic;
-----------------------------------------
-- General board status
-----------------------------------------
fmc_mmcm_lock_led_o : out std_logic;
fmc_pll_status_led_o : out std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_dsp;
architecture rtl of dbe_bpm_dsp is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 10;
-- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC,
--Etherbone, FMC516, Peripherals
-- Number of masters
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone, RS232-Syscon
constant c_masters : natural := 7; -- RS232-Syscon,
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone
--constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB)
constant c_dpram_size : natural := 90112/4; -- in 32-bit words (90KB)
--constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB)
--constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB)
constant c_dpram_ethbuf_size : natural := 16384/4; -- in 32-bit words (16KB)
-- GPIO num pinscalc
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- TICs counter period. 100MHz clock -> msec granularity
constant c_tics_cntr_period : natural := 100000;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
-- number of the ADC reference clock used for all downstream
-- FPGA logic
constant c_adc_ref_clk : natural := 1;
-- DSP constants
--constant c_dsp_ref_num_bits : natural := 24;
--constant c_dsp_pos_num_bits : natural := 26;
constant c_xwb_etherbone_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"68202b22",
version => x"00000001",
date => x"20120912",
name => "GSI_ETHERBONE_CFG ")));
constant c_xwb_ethmac_adapter_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"2ff9a28e",
version => x"00000001",
date => x"20130701",
name => "ETHMAC_ADAPTER ")));
-- FMC130m_4ch layout. Size (0x00000FFF) is larger than needed. Just to be sure
-- no address overlaps will occur
--constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- FMC130m_4ch
constant c_fmc130m_4ch_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter
constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400");
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 128KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size),
x"20000000"), -- 64KB RAM
3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30004000"), -- DMA control port
4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30005000"), -- Ethernet MAC control port
5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30006000"), -- Ethernet Adapter control port
6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30007000"), -- Etherbone control port
7 => f_sdb_embed_device(c_xwb_position_calc_core_sdb,
x"30008000"), -- Position Calc Core control port
8 => f_sdb_embed_bridge(c_fmc130m_4ch_bridge_sdb, x"30010000"), -- FMC130m_4ch control port
9 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"30020000") -- General peripherals control port
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well
constant c_sdb_address : t_wishbone_address := x"30000000";
-- FMC ADC data constants
constant c_adc_data_ch0_lsb : natural := 0;
constant c_adc_data_ch0_msb : natural := c_num_adc_bits-1 + c_adc_data_ch0_lsb;
constant c_adc_data_ch1_lsb : natural := c_adc_data_ch0_msb + 1;
constant c_adc_data_ch1_msb : natural := c_num_adc_bits-1 + c_adc_data_ch1_lsb;
constant c_adc_data_ch2_lsb : natural := c_adc_data_ch1_msb + 1;
constant c_adc_data_ch2_msb : natural := c_num_adc_bits-1 + c_adc_data_ch2_lsb;
constant c_adc_data_ch3_lsb : natural := c_adc_data_ch2_msb + 1;
constant c_adc_data_ch3_msb : natural := c_num_adc_bits-1 + c_adc_data_ch3_lsb;
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_sys_n : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
signal rs232_rstn : std_logic;
signal fs_rstn : std_logic;
-- 200 Mhz clocck for iodelay_ctrl
signal clk_200mhz : std_logic;
-- ADC clock
signal fs_clk : std_logic;
signal fs_clk2x : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
-- Ethernet MAC signals
signal ethmac_int : std_logic;
signal ethmac_md_in : std_logic;
signal ethmac_md_out : std_logic;
signal ethmac_md_oe : std_logic;
signal mtxd_pad_int : std_logic_vector(3 downto 0);
signal mtxen_pad_int : std_logic;
signal mtxerr_pad_int : std_logic;
signal mdc_pad_int : std_logic;
-- Ethrnet MAC adapter signals
signal irq_rx_done : std_logic;
signal irq_tx_done : std_logic;
-- Etherbone signals
signal wb_ebone_out : t_wishbone_master_out;
signal wb_ebone_in : t_wishbone_master_in;
signal eb_src_i : t_wrf_source_in;
signal eb_src_o : t_wrf_source_out;
signal eb_snk_i : t_wrf_sink_in;
signal eb_snk_o : t_wrf_sink_out;
-- DMA signals
signal dma_int : std_logic;
-- FMC130m_4ch Signals
signal wbs_fmc130m_4ch_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
signal wbs_fmc130m_4ch_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
signal fmc_mmcm_lock_int : std_logic;
signal fmc_pll_status_int : std_logic;
signal fmc_led1_int : std_logic;
signal fmc_led2_int : std_logic;
signal fmc_led3_int : std_logic;
signal fmc_130m_4ch_clk : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_data : std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
signal fmc_130m_4ch_data_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_data_ch0 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_ch1 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_ch2 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_data_ch3 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal fmc_debug : std_logic;
signal reset_adc_counter : unsigned(6 downto 0) := (others => '0');
signal fmc_130m_4ch_rst_n : std_logic_vector(c_num_adc_channels-1 downto 0);
-- fmc130m_4ch Debug
signal fmc130m_4ch_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc130m_4ch_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc130m_4ch_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
-- Uncross signals
signal un_cross_gain_aa : std_logic_vector(15 downto 0);
signal un_cross_gain_bb : std_logic_vector(15 downto 0);
signal un_cross_gain_cc : std_logic_vector(15 downto 0);
signal un_cross_gain_dd : std_logic_vector(15 downto 0);
signal un_cross_gain_ac : std_logic_vector(15 downto 0);
signal un_cross_gain_bd : std_logic_vector(15 downto 0);
signal un_cross_gain_ca : std_logic_vector(15 downto 0);
signal un_cross_gain_db : std_logic_vector(15 downto 0);
signal un_cross_delay_1 : std_logic_vector(15 downto 0);
signal un_cross_delay_2 : std_logic_vector(15 downto 0);
signal adc_ch0_data_uncross : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_ch1_data_uncross : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_ch2_data_uncross : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_ch3_data_uncross : std_logic_vector(c_num_adc_bits-1 downto 0);
signal un_cross_mode_1 : std_logic_vector(1 downto 0);
signal un_cross_mode_2 : std_logic_vector(1 downto 0);
signal un_cross_div_f : std_logic_vector(15 downto 0);
signal flag1_int : std_logic;
signal flag2_int : std_logic;
-- DSP signals
signal dsp_kx : std_logic_vector(24 downto 0);
signal dsp_ky : std_logic_vector(24 downto 0);
signal dsp_ksum : std_logic_vector(24 downto 0);
signal dsp_kx_in : std_logic_vector(24 downto 0);
signal dsp_ky_in : std_logic_vector(24 downto 0);
signal dsp_ksum_in : std_logic_vector(24 downto 0);
signal dsp_del_sig_div_thres_sel : std_logic_vector(1 downto 0);
signal dsp_kx_sel : std_logic_vector(1 downto 0);
signal dsp_ky_sel : std_logic_vector(1 downto 0);
signal dsp_ksum_sel : std_logic_vector(1 downto 0);
signal dsp_del_sig_div_thres : std_logic_vector(25 downto 0);
signal dsp_del_sig_div_thres_in : std_logic_vector(25 downto 0);
signal dsp_dds_config_valid_ch0 : std_logic;
signal dsp_dds_config_valid_ch1 : std_logic;
signal dsp_dds_config_valid_ch2 : std_logic;
signal dsp_dds_config_valid_ch3 : std_logic;
signal dsp_dds_pinc_ch0 : std_logic_vector(29 downto 0);
signal dsp_dds_pinc_ch1 : std_logic_vector(29 downto 0);
signal dsp_dds_pinc_ch2 : std_logic_vector(29 downto 0);
signal dsp_dds_pinc_ch3 : std_logic_vector(29 downto 0);
signal dsp_dds_poff_ch0 : std_logic_vector(29 downto 0);
signal dsp_dds_poff_ch1 : std_logic_vector(29 downto 0);
signal dsp_dds_poff_ch2 : std_logic_vector(29 downto 0);
signal dsp_dds_poff_ch3 : std_logic_vector(29 downto 0);
signal dsp_adc_ch0_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch1_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch2_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch3_dbg_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch0_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch1_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch2_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_adc_ch3_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_ch0_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_ch1_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_ch2_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal adc_ch3_data : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dsp_bpf_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_bpf_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_bpf_valid : std_logic;
signal dsp_mix_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_mix_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_mix_valid : std_logic;
signal dsp_poly35_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_poly35_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_cic_fofb_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_cic_fofb_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch0_valid : std_logic;
signal dsp_tbt_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch1_valid : std_logic;
signal dsp_tbt_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch2_valid : std_logic;
signal dsp_tbt_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_amp_ch3_valid : std_logic;
signal dsp_tbt_pha_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_pha_ch0_valid : std_logic;
signal dsp_tbt_pha_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_pha_ch1_valid : std_logic;
signal dsp_tbt_pha_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_pha_ch2_valid : std_logic;
signal dsp_tbt_pha_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_tbt_pha_ch3_valid : std_logic;
signal dsp_fofb_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch0_valid : std_logic;
signal dsp_fofb_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch1_valid : std_logic;
signal dsp_fofb_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch2_valid : std_logic;
signal dsp_fofb_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_amp_ch3_valid : std_logic;
signal dsp_fofb_pha_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_pha_ch0_valid : std_logic;
signal dsp_fofb_pha_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_pha_ch1_valid : std_logic;
signal dsp_fofb_pha_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_pha_ch2_valid : std_logic;
signal dsp_fofb_pha_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_fofb_pha_ch3_valid : std_logic;
signal dsp_monit_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch0_valid : std_logic;
signal dsp_monit_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch1_valid : std_logic;
signal dsp_monit_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch2_valid : std_logic;
signal dsp_monit_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal dsp_monit_amp_ch3_valid : std_logic;
signal dsp_x_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_x_tbt_valid : std_logic;
signal dsp_y_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_y_tbt_valid : std_logic;
signal dsp_q_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_q_tbt_valid : std_logic;
signal dsp_sum_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_sum_tbt_valid : std_logic;
signal dsp_x_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_x_fofb_valid : std_logic;
signal dsp_y_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_y_fofb_valid : std_logic;
signal dsp_q_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_q_fofb_valid : std_logic;
signal dsp_sum_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_sum_fofb_valid : std_logic;
signal dsp_x_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_x_monit_valid : std_logic;
signal dsp_y_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_y_monit_valid : std_logic;
signal dsp_q_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_q_monit_valid : std_logic;
signal dsp_sum_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_sum_monit_valid : std_logic;
signal dsp_x_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_x_monit_1_valid : std_logic;
signal dsp_y_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_y_monit_1_valid : std_logic;
signal dsp_q_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_q_monit_1_valid : std_logic;
signal dsp_sum_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal dsp_sum_monit_1_valid : std_logic;
signal dsp_tbt_decim_q_ch01_incorrect : std_logic;
signal dsp_tbt_decim_q_ch23_incorrect : std_logic;
signal dsp_fofb_decim_q_01_missing : std_logic;
signal dsp_fofb_decim_q_23_missing : std_logic;
signal dsp_monit_cic_unexpected : std_logic;
signal dsp_monit_cfir_incorrect : std_logic;
signal dsp_monit_pfir_incorrect : std_logic;
signal dsp_monit_pos_1_incorrect : std_logic;
signal dsp_clk_ce_1 : std_logic;
signal dsp_clk_ce_2 : std_logic;
signal dsp_clk_ce_35 : std_logic;
signal dsp_clk_ce_70 : std_logic;
signal dsp_clk_ce_1390000 : std_logic;
signal dsp_clk_ce_1112 : std_logic;
signal dsp_clk_ce_2224 : std_logic;
signal dsp_clk_ce_11120000 : std_logic;
signal dsp_clk_ce_111200000 : std_logic;
signal dsp_clk_ce_22240000 : std_logic;
signal dsp_clk_ce_222400000 : std_logic;
signal dsp_clk_ce_5000 : std_logic;
signal dsp_clk_ce_556 : std_logic;
signal dsp_clk_ce_2780000 : std_logic;
signal dsp_clk_ce_5560000 : std_logic;
-- DDS test
signal dds_data : std_logic_vector(2*c_num_adc_bits-1 downto 0); -- cosine + sine
signal dds_sine : std_logic_vector(c_num_adc_bits-1 downto 0);
signal dds_cosine : std_logic_vector(c_num_adc_bits-1 downto 0);
signal synth_adc0 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal synth_adc1 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal synth_adc2 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal synth_adc3 : std_logic_vector(c_num_adc_bits-1 downto 0);
signal synth_adc0_full : std_logic_vector(25 downto 0);
signal synth_adc1_full : std_logic_vector(25 downto 0);
signal synth_adc2_full : std_logic_vector(25 downto 0);
signal synth_adc3_full : std_logic_vector(25 downto 0);
signal dds_sine_gain_ch0 : std_logic_vector(9 downto 0);
signal dds_sine_gain_ch1 : std_logic_vector(9 downto 0);
signal dds_sine_gain_ch2 : std_logic_vector(9 downto 0);
signal dds_sine_gain_ch3 : std_logic_vector(9 downto 0);
signal adc_synth_data_en : std_logic;
signal clk_rffe_swap : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
-- Chipscope control signals
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
signal CONTROL2 : std_logic_vector(35 downto 0);
signal CONTROL3 : std_logic_vector(35 downto 0);
signal CONTROL4 : std_logic_vector(35 downto 0);
signal CONTROL5 : std_logic_vector(35 downto 0);
signal CONTROL6 : std_logic_vector(35 downto 0);
signal CONTROL7 : std_logic_vector(35 downto 0);
signal CONTROL8 : std_logic_vector(35 downto 0);
signal CONTROL9 : std_logic_vector(35 downto 0);
signal CONTROL10 : std_logic_vector(35 downto 0);
signal CONTROL11 : std_logic_vector(35 downto 0);
signal CONTROL12 : std_logic_vector(35 downto 0);
-- Chipscope ILA 0 signals
signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 1 signals
signal TRIG_ILA1_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_4 : std_logic_vector(31 downto 0);
signal fifo_in_ila1 : std_logic_vector(4*c_dsp_ref_num_bits-1 downto 0);
signal fifo_out_ila1 : std_logic_vector(4*c_dsp_ref_num_bits-1 downto 0);
signal fifo_ila1_rd : std_logic;
signal fifo_ila1_empty : std_logic;
signal fifo_ila1_valid : std_logic;
-- Chipscope ILA 2 signals
signal TRIG_ILA2_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA2_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_4 : std_logic_vector(31 downto 0);
signal fifo_in_ila2 : std_logic_vector(4*c_dsp_ref_num_bits-1 downto 0);
signal fifo_out_ila2 : std_logic_vector(4*c_dsp_ref_num_bits-1 downto 0);
signal fifo_ila2_rd : std_logic;
signal fifo_ila2_empty : std_logic;
signal fifo_ila2_valid : std_logic;
-- Chipscope ILA 3 signals
signal TRIG_ILA3_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA3_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_4 : std_logic_vector(31 downto 0);
signal fifo_in_ila3 : std_logic_vector(4*c_dsp_pos_num_bits-1 downto 0);
signal fifo_out_ila3 : std_logic_vector(4*c_dsp_pos_num_bits-1 downto 0);
signal fifo_ila3_rd : std_logic;
signal fifo_ila3_empty : std_logic;
signal fifo_ila3_valid : std_logic;
-- Chipscope ILA 4 signals
signal TRIG_ILA4_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA4_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA4_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA4_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA4_4 : std_logic_vector(31 downto 0);
signal fifo_in_ila4 : std_logic_vector(4*c_dsp_ref_num_bits-1 downto 0);
signal fifo_out_ila4 : std_logic_vector(4*c_dsp_ref_num_bits-1 downto 0);
signal fifo_ila4_rd : std_logic;
signal fifo_ila4_empty : std_logic;
signal fifo_ila4_valid : std_logic;
-- Chipscope ILA 5 signals
signal TRIG_ILA5_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA5_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA5_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA5_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA5_4 : std_logic_vector(31 downto 0);
signal fifo_in_ila5 : std_logic_vector(4*c_dsp_pos_num_bits-1 downto 0);
signal fifo_out_ila5 : std_logic_vector(4*c_dsp_pos_num_bits-1 downto 0);
signal fifo_ila5_rd : std_logic;
signal fifo_ila5_empty : std_logic;
signal fifo_ila5_valid : std_logic;
-- Chipscope ILA 6 signals
signal TRIG_ILA6_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA6_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA6_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA6_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA6_4 : std_logic_vector(31 downto 0);
signal fifo_in_ila6 : std_logic_vector(4*c_dsp_ref_num_bits-1 downto 0);
signal fifo_out_ila6 : std_logic_vector(4*c_dsp_ref_num_bits-1 downto 0);
signal fifo_ila6_rd : std_logic;
signal fifo_ila6_empty : std_logic;
signal fifo_ila6_valid : std_logic;
-- Chipscope ILA 7 signals
signal TRIG_ILA7_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA7_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA7_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA7_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA7_4 : std_logic_vector(31 downto 0);
signal fifo_in_ila7 : std_logic_vector(4*c_dsp_pos_num_bits-1 downto 0);
signal fifo_out_ila7 : std_logic_vector(4*c_dsp_pos_num_bits-1 downto 0);
signal fifo_ila7_rd : std_logic;
signal fifo_ila7_empty : std_logic;
signal fifo_ila7_valid : std_logic;
-- Chipscope ILA 8 signals
signal TRIG_ILA8_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA8_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA8_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA8_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA8_4 : std_logic_vector(31 downto 0);
signal fifo_in_ila8 : std_logic_vector(4*c_dsp_pos_num_bits-1 downto 0);
signal fifo_out_ila8 : std_logic_vector(4*c_dsp_pos_num_bits-1 downto 0);
signal fifo_ila8_rd : std_logic;
signal fifo_ila8_empty : std_logic;
signal fifo_ila8_valid : std_logic;
-- Chipscope ILA 9 signals
signal TRIG_ILA9_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA9_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA9_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA9_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA9_4 : std_logic_vector(31 downto 0);
signal fifo_in_ila9 : std_logic_vector(4*c_dsp_ref_num_bits-1 downto 0);
signal fifo_out_ila9 : std_logic_vector(4*c_dsp_ref_num_bits-1 downto 0);
signal fifo_ila9_rd : std_logic;
signal fifo_ila9_empty : std_logic;
signal fifo_ila9_valid : std_logic;
-- Chipscope ILA 10 signals
signal TRIG_ILA10_0 : std_logic_vector(7 downto 0);
signal TRIG_ILA10_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA10_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA10_3 : std_logic_vector(31 downto 0);
signal TRIG_ILA10_4 : std_logic_vector(31 downto 0);
signal fifo_in_ila10 : std_logic_vector(4*c_dsp_ref_num_bits-1 downto 0);
signal fifo_out_ila10 : std_logic_vector(4*c_dsp_ref_num_bits-1 downto 0);
signal fifo_ila10_rd : std_logic;
signal fifo_ila10_empty : std_logic;
signal fifo_ila10_valid : std_logic;
-- Chipscope VIO signals
signal vio_out : std_logic_vector(255 downto 0);
signal vio_out_dsp_config : std_logic_vector(255 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
component un_cross_top
generic(
g_delay_vec_width : natural range 0 to 16 := 16;
g_swap_div_freq_vec_width : natural range 0 to 16 := 16
);
port(
-- Commom signals
clk_i : in std_logic;
rst_n_i : in std_logic;
-- inv_chs_top core signal
const_aa_i : in std_logic_vector(15 downto 0);
const_bb_i : in std_logic_vector(15 downto 0);
const_cc_i : in std_logic_vector(15 downto 0);
const_dd_i : in std_logic_vector(15 downto 0);
const_ac_i : in std_logic_vector(15 downto 0);
const_bd_i : in std_logic_vector(15 downto 0);
const_ca_i : in std_logic_vector(15 downto 0);
const_db_i : in std_logic_vector(15 downto 0);
delay1_i : in std_logic_vector(g_delay_vec_width-1 downto 0);
delay2_i : in std_logic_vector(g_delay_vec_width-1 downto 0);
flag1_o : out std_logic;
flag2_o : out std_logic;
-- Input from ADC FMC board
cha_i : in std_logic_vector(15 downto 0);
chb_i : in std_logic_vector(15 downto 0);
chc_i : in std_logic_vector(15 downto 0);
chd_i : in std_logic_vector(15 downto 0);
-- Output to data processing level
cha_o : out std_logic_vector(15 downto 0);
chb_o : out std_logic_vector(15 downto 0);
chc_o : out std_logic_vector(15 downto 0);
chd_o : out std_logic_vector(15 downto 0);
-- Swap clock for RFFE
clk_swap_o : out std_logic;
-- swap_cnt_top signal
mode1_i : in std_logic_vector(1 downto 0);
mode2_i : in std_logic_vector(1 downto 0);
swap_div_f_i : in std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
-- Output to RFFE board
ctrl1_o : out std_logic_vector(7 downto 0);
ctrl2_o : out std_logic_vector(7 downto 0)
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
component multiplier_16x10_DSP
port (
clk : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(9 downto 0);
p : out std_logic_vector(25 downto 0)
);
end component;
component dds_adc_input
port (
aclk : in std_logic;
m_axis_data_tvalid : out std_logic;
m_axis_data_tdata : out std_logic_vector(31 downto 0)
);
end component;
component chipscope_icon_13_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0);
CONTROL2 : inout std_logic_vector(35 downto 0);
CONTROL3 : inout std_logic_vector(35 downto 0);
CONTROL4 : inout std_logic_vector(35 downto 0);
CONTROL5 : inout std_logic_vector(35 downto 0);
CONTROL6 : inout std_logic_vector(35 downto 0);
CONTROL7 : inout std_logic_vector(35 downto 0);
CONTROL8 : inout std_logic_vector(35 downto 0);
CONTROL9 : inout std_logic_vector(35 downto 0);
CONTROL10 : inout std_logic_vector(35 downto 0);
CONTROL11 : inout std_logic_vector(35 downto 0);
CONTROL12 : inout std_logic_vector(35 downto 0)
);
end component;
component chipscope_ila
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(31 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila_1024
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(7 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0);
trig4 : in std_logic_vector(31 downto 0));
end component;
component chipscope_ila_65536
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(7 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0);
trig4 : in std_logic_vector(31 downto 0));
end component;
component chipscope_ila_131072
port (
control : inout std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(7 downto 0);
trig1 : in std_logic_vector(15 downto 0);
trig2 : in std_logic_vector(15 downto 0);
trig3 : in std_logic_vector(15 downto 0);
trig4 : in std_logic_vector(15 downto 0));
end component;
component chipscope_vio_256 is
port (
control : inout std_logic_vector(35 downto 0);
async_out : out std_logic_vector(255 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
cmp_reset : gc_reset
generic map(
g_clocks => 1 -- CLK_SYS
)
port map(
free_clk_i => sys_clk_gen,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(0) <= clk_sys;
clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n and rs232_rstn;
clk_sys_rst <= not clk_sys_rstn;
mrstn_o <= clk_sys_rstn;
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
rst_button_sys_n <= not rst_button_sys;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn;
--cmp_lm32 : xwb_lm32
--generic map(
-- g_profile => "medium_icache_debug"
--) -- Including JTAG and I-cache (no divide)
--port map(
-- clk_sys_i => clk_sys,
-- rst_n_i => lm32_rstn,
-- irq_i => lm32_interrupt,
-- dwb_o => cbar_slave_i(0), -- Data bus
-- dwb_i => cbar_slave_o(0),
-- iwb_o => cbar_slave_i(1), -- Instruction bus
-- iwb_i => cbar_slave_o(1)
--);
-- Interrupt '0' is Ethmac.
-- Interrupt '1' is DMA completion.
-- Interrupt '2' is Button(0).
-- Interrupt '3' is Ethernet Adapter RX completion.
-- Interrupt '4' is Ethernet Adapter TX completion.
-- Interrupts 31 downto 5 are disabled
lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done,
4 => irq_tx_done, others => '0');
cmp_xwb_rs232_syscon : xwb_rs232_syscon
generic map (
g_ma_interface_mode => PIPELINED,
g_ma_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rstn_i => '1', -- No need for resetting the controller
-- External ports
rs232_rxd_i => rs232_rxd_i,
rs232_txd_o => rs232_txd_o,
-- Reset to FPGA logic
rstn_o => rs232_rstn,
-- WISHBONE master
wb_master_i => cbar_slave_o(0),
wb_master_o => cbar_slave_i(0)
);
-- A DMA controller is master 2+3, slave 3, and interrupt 1
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(3),
slave_o => cbar_master_i(3),
r_master_i => cbar_slave_o(1),
r_master_o => cbar_slave_i(1),
w_master_i => cbar_slave_o(2),
w_master_o => cbar_slave_i(2),
interrupt_o => dma_int
);
-- Slave 0+1 is the RAM. Load a input file containing the embedded software
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
--g_init_file => "../../../embedded-sw/dbe.ram",
--"../../top/ml_605/dbe_bpm_simple/sw/main.ram",
--g_must_have_init_file => true,
g_must_have_init_file => false,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
);
-- Slave 2 is the RAM Buffer for Ethernet MAC.
cmp_ethmac_buf_ram : xwb_dpram
generic map(
g_size => c_dpram_ethbuf_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => CLASSIC,
--g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
--g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(2),
slave1_o => cbar_master_i(2),
-- Second port connected to the crossbar
slave2_i => cc_dummy_slave_in, -- CYC always low
slave2_o => open
);
-- The Ethernet MAC is master 4, slave 4
cmp_xwb_ethmac : xwb_ethmac
generic map (
--g_ma_interface_mode => PIPELINED,
g_ma_interface_mode => CLASSIC, -- NOT used for now
--g_ma_address_granularity => WORD,
g_ma_address_granularity => BYTE, -- NOT used for now
g_sl_interface_mode => PIPELINED,
--g_sl_interface_mode => CLASSIC,
--g_sl_address_granularity => WORD
g_sl_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rst_i => clk_sys_rst,
-- WISHBONE slave
wb_slave_in => cbar_master_o(4),
wb_slave_out => cbar_master_i(4),
-- WISHBONE master
wb_master_in => cbar_slave_o(3),
wb_master_out => cbar_slave_i(3),
-- PHY TX
mtx_clk_pad_i => mtx_clk_pad_i,
--mtxd_pad_o => mtxd_pad_o,
mtxd_pad_o => mtxd_pad_int,
--mtxen_pad_o => mtxen_pad_o,
mtxen_pad_o => mtxen_pad_int,
--mtxerr_pad_o => mtxerr_pad_o,
mtxerr_pad_o => mtxerr_pad_int,
-- PHY RX
mrx_clk_pad_i => mrx_clk_pad_i,
mrxd_pad_i => mrxd_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxerr_pad_i => mrxerr_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcrs_pad_i => mcrs_pad_i,
-- MII
--mdc_pad_o => mdc_pad_o,
mdc_pad_o => mdc_pad_int,
md_pad_i => ethmac_md_in,
md_pad_o => ethmac_md_out,
md_padoe_o => ethmac_md_oe,
-- Interrupt
int_o => ethmac_int
);
---- Tri-state buffer for MII config
md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z';
ethmac_md_in <= md_pad_b;
mtxd_pad_o <= mtxd_pad_int;
mtxen_pad_o <= mtxen_pad_int;
mtxerr_pad_o <= mtxerr_pad_int;
mdc_pad_o <= mdc_pad_int;
--The Ethernet MAC Adapter is master 5+6, slave 5
cmp_xwb_ethmac_adapter : xwb_ethmac_adapter
port map(
clk_i => clk_sys,
rstn_i => clk_sys_rstn,
wb_slave_o => cbar_master_i(5),
wb_slave_i => cbar_master_o(5),
tx_ram_o => cbar_slave_i(4),
tx_ram_i => cbar_slave_o(4),
rx_ram_o => cbar_slave_i(5),
rx_ram_i => cbar_slave_o(5),
rx_eb_o => eb_snk_i,
rx_eb_i => eb_snk_o,
tx_eb_o => eb_src_i,
tx_eb_i => eb_src_o,
irq_tx_done_o => irq_tx_done,
irq_rx_done_o => irq_rx_done
);
-- The Etherbone is slave 6
cmp_eb_slave_core : eb_slave_core
generic map(
g_sdb_address => x"00000000" & c_sdb_address
)
port map
(
clk_i => clk_sys,
nRst_i => clk_sys_rstn,
-- EB streaming sink
snk_i => eb_snk_i,
snk_o => eb_snk_o,
-- EB streaming source
src_i => eb_src_i,
src_o => eb_src_o,
-- WB slave - Cfg IF
cfg_slave_o => cbar_master_i(6),
cfg_slave_i => cbar_master_o(6),
-- WB master - Bus IF
master_o => wb_ebone_out,
master_i => wb_ebone_in
);
cbar_slave_i(6) <= wb_ebone_out;
wb_ebone_in <= cbar_slave_o(6);
-- The FMC130M_4CH is slave 8
cmp_xwb_fmc130m_4ch : xwb_fmc130m_4ch
generic map(
g_fpga_device => "VIRTEX6",
g_interface_mode => PIPELINED,
--g_address_granularity => WORD,
g_address_granularity => BYTE,
--g_adc_clk_period_values => default_adc_clk_period_values,
g_adc_clk_period_values => (8.88, 8.88, 8.88, 8.88),
--g_use_clk_chains => default_clk_use_chain,
-- using clock1 from fmc130m_4ch (CLK2_ M2C_P, CLK2_ M2C_M pair)
-- using clock0 from fmc130m_4ch.
-- BUFIO can drive half-bank only, not the full IO bank
g_use_clk_chains => "1111",
g_with_bufio_clk_chains => "0000",
g_with_bufr_clk_chains => "1111",
g_use_data_chains => "1111",
--g_map_clk_data_chains => (-1,-1,-1,-1),
-- Clock 1 is the adc reference clock
g_ref_clk => c_adc_ref_clk,
g_packet_size => 32,
g_sim => 0
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => cbar_master_o(8),
wb_slv_o => cbar_master_i(8),
-----------------------------
-- External ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o => fmc_adc_pga_o,
fmc_adc_shdn_o => fmc_adc_shdn_o,
fmc_adc_dith_o => fmc_adc_dith_o,
fmc_adc_rand_o => fmc_adc_rand_o,
-- ADC0 LTC2208
fmc_adc0_clk_i => fmc_adc0_clk_i,
fmc_adc0_data_i => fmc_adc0_data_i,
fmc_adc0_of_i => fmc_adc0_of_i,
-- ADC1 LTC2208
fmc_adc1_clk_i => fmc_adc1_clk_i,
fmc_adc1_data_i => fmc_adc1_data_i,
fmc_adc1_of_i => fmc_adc1_of_i,
-- ADC2 LTC2208
fmc_adc2_clk_i => fmc_adc2_clk_i,
fmc_adc2_data_i => fmc_adc2_data_i,
fmc_adc2_of_i => fmc_adc2_of_i,
-- ADC3 LTC2208
fmc_adc3_clk_i => fmc_adc3_clk_i,
fmc_adc3_data_i => fmc_adc3_data_i,
fmc_adc3_of_i => fmc_adc3_of_i,
-- FMC General Status
fmc_prsnt_i => fmc_prsnt_i,
fmc_pg_m2c_i => fmc_pg_m2c_i,
-- Trigger
fmc_trig_dir_o => fmc_trig_dir_o,
fmc_trig_term_o => fmc_trig_term_o,
fmc_trig_val_p_b => fmc_trig_val_p_b,
fmc_trig_val_n_b => fmc_trig_val_n_b,
-- Si571 clock gen
si571_scl_pad_b => si571_scl_pad_b,
si571_sda_pad_b => si571_sda_pad_b,
fmc_si571_oe_o => fmc_si571_oe_o,
-- AD9510 clock distribution PLL
spi_ad9510_cs_o => spi_ad9510_cs_o,
spi_ad9510_sclk_o => spi_ad9510_sclk_o,
spi_ad9510_mosi_o => spi_ad9510_mosi_o,
spi_ad9510_miso_i => spi_ad9510_miso_i,
fmc_pll_function_o => fmc_pll_function_o,
fmc_pll_status_i => fmc_pll_status_i,
-- AD9510 clock copy
fmc_fpga_clk_p_i => fmc_fpga_clk_p_i,
fmc_fpga_clk_n_i => fmc_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o => fmc_clk_sel_o,
-- EEPROM
eeprom_scl_pad_b => eeprom_scl_pad_b,
eeprom_sda_pad_b => eeprom_sda_pad_b,
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b => lm75_scl_pad_b,
lm75_sda_pad_b => lm75_sda_pad_b,
fmc_lm75_temp_alarm_i => fmc_lm75_temp_alarm_i,
-- FMC LEDs
fmc_led1_o => fmc_led1_int,
fmc_led2_o => fmc_led2_int,
fmc_led3_o => fmc_led3_int,
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o => fmc_130m_4ch_clk,
adc_clk2x_o => fmc_130m_4ch_clk2x,
adc_rst_n_o => fmc_130m_4ch_rst_n,
adc_data_o => fmc_130m_4ch_data,
adc_data_valid_o => fmc_130m_4ch_data_valid,
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => open,
trig_hw_i => '0',
-- General board status
fmc_mmcm_lock_o => fmc_mmcm_lock_int,
fmc_pll_status_o => fmc_pll_status_int,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i => wbs_fmc130m_4ch_in_array,
wbs_source_o => wbs_fmc130m_4ch_out_array,
adc_dly_debug_o => adc_dly_debug_int,
fifo_debug_valid_o => fmc130m_4ch_debug_valid_int,
fifo_debug_full_o => fmc130m_4ch_debug_full_int,
fifo_debug_empty_o => fmc130m_4ch_debug_empty_int
);
gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate
wbs_fmc130m_4ch_in_array(i) <= cc_dummy_src_com_in;
end generate;
fmc_mmcm_lock_led_o <= fmc_mmcm_lock_int;
fmc_pll_status_led_o <= fmc_pll_status_int;
fmc_led1_o <= fmc_led1_int;
fmc_led2_o <= fmc_led2_int;
fmc_led3_o <= fmc_led3_int;
adc_data_ch0 <= fmc_130m_4ch_data(c_adc_data_ch0_msb downto c_adc_data_ch0_lsb);
adc_data_ch1 <= fmc_130m_4ch_data(c_adc_data_ch1_msb downto c_adc_data_ch1_lsb);
adc_data_ch2 <= fmc_130m_4ch_data(c_adc_data_ch2_msb downto c_adc_data_ch2_lsb);
adc_data_ch3 <= fmc_130m_4ch_data(c_adc_data_ch3_msb downto c_adc_data_ch3_lsb);
fs_clk <= fmc_130m_4ch_clk(c_adc_ref_clk);
fs_rstn <= fmc_130m_4ch_rst_n(c_adc_ref_clk);
fs_clk2x <= fmc_130m_4ch_clk2x(c_adc_ref_clk);
--led_south_o <= fmc_led1_int;
--led_east_o <= fmc_led2_int;
--led_north_o <= fmc_led3_int;
----------------------------------------------------------------------
-- DSP Chain Core --
----------------------------------------------------------------------
-- Testing with internal DDS
cmp_dds_adc_input : dds_adc_input
port map (
aclk => fs_clk,
m_axis_data_tvalid => open,
m_axis_data_tdata => dds_data
);
dds_sine <= dds_data(31 downto 16);
dds_cosine <= dds_data(15 downto 0);
cmp_multiplier_16x10_DSP_ch0 : multiplier_16x10_DSP
port map (
clk => fs_clk,
a => dds_sine,
b => dds_sine_gain_ch0,
p => synth_adc0_full
);
synth_adc0 <= synth_adc0_full(25 downto 10);
cmp_multiplier_16x10_DSP_ch1 : multiplier_16x10_DSP
port map(
clk => fs_clk,
a => dds_sine,
b => dds_sine_gain_ch1,
p => synth_adc1_full
);
synth_adc1 <= synth_adc1_full(25 downto 10);
cmp_multiplier_16x10_DSP_ch2 : multiplier_16x10_DSP
port map(
clk => fs_clk,
a => dds_sine,
b => dds_sine_gain_ch2,
p => synth_adc2_full
);
synth_adc2 <= synth_adc2_full(25 downto 10);
cmp_multiplier_16x10_DSP_ch3 : multiplier_16x10_DSP
port map (
clk => fs_clk,
a => dds_sine,
b => dds_sine_gain_ch3,
p => synth_adc3_full
);
synth_adc3 <= synth_adc3_full(25 downto 10);
-- MUX between sinthetic data and real ADC data
adc_ch0_data <= synth_adc0 when adc_synth_data_en = '1' else adc_data_ch0;
adc_ch1_data <= synth_adc1 when adc_synth_data_en = '1' else adc_data_ch1;
adc_ch2_data <= synth_adc2 when adc_synth_data_en = '1' else adc_data_ch2;
adc_ch3_data <= synth_adc3 when adc_synth_data_en = '1' else adc_data_ch3;
-- Switch testing. This should be inside position calc core!!!!
cmp_un_cross_top : un_cross_top
generic map (
g_delay_vec_width => 16,
g_swap_div_freq_vec_width => 16
)
port map (
-- Commom signals
clk_i => fs_clk,
rst_n_i => fs_rstn,
-- inv_chs_top core signal
const_aa_i => un_cross_gain_aa,
const_bb_i => un_cross_gain_bb,
const_cc_i => un_cross_gain_cc,
const_dd_i => un_cross_gain_dd,
const_ac_i => un_cross_gain_ac,
const_bd_i => un_cross_gain_bd,
const_ca_i => un_cross_gain_ca,
const_db_i => un_cross_gain_db,
delay1_i => un_cross_delay_1,
delay2_i => un_cross_delay_2,
--flag1_o => flag1_int,
--flag2_o => flag2_int,
-- Input from ADC FMC board
cha_i => adc_ch0_data,
chb_i => adc_ch1_data,
chc_i => adc_ch2_data,
chd_i => adc_ch3_data,
-- Output to data processing level
cha_o => adc_ch0_data_uncross,
chb_o => adc_ch1_data_uncross,
chc_o => adc_ch2_data_uncross,
chd_o => adc_ch3_data_uncross,
-- Swap clock for RFFE
clk_swap_o => clk_rffe_swap,
-- swap_cnt_top signal
mode1_i => un_cross_mode_1,
mode2_i => un_cross_mode_2,
swap_div_f_i => un_cross_div_f,
-- Output to RFFE board
ctrl1_o => open,
ctrl2_o => open
);
--clk_swap_o <= clk_rffe_swap;
clk_swap_o <= fs_clk; -- FIXME!!!!
clk_swap2x_o <= fs_clk2x; -- FIXME!!!!
-- Position calc core is slave 7
cmp_xwb_position_calc_core : xwb_position_calc_core
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => WORD,
g_with_switching => 0
)
port map (
rst_n_i => clk_sys_rstn,
clk_i => clk_sys, -- Wishbone clock
fs_rst_n_i => fs_rstn,
fs_clk_i => fs_clk, -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i => fs_clk2x, -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i => cbar_master_o(7),
wb_slv_o => cbar_master_i(7),
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i => adc_ch0_data_uncross,
adc_ch1_i => adc_ch1_data_uncross,
adc_ch2_i => adc_ch2_data_uncross,
adc_ch3_i => adc_ch3_data_uncross,
-----------------------------
-- DSP config parameter signals
-----------------------------
kx_i => dsp_kx,
ky_i => dsp_ky,
ksum_i => dsp_ksum,
del_sig_div_fofb_thres_i => dsp_del_sig_div_thres,
del_sig_div_tbt_thres_i => dsp_del_sig_div_thres,
del_sig_div_monit_thres_i => dsp_del_sig_div_thres,
dds_config_valid_ch0_i => dsp_dds_config_valid_ch0,
dds_config_valid_ch1_i => dsp_dds_config_valid_ch1,
dds_config_valid_ch2_i => dsp_dds_config_valid_ch2,
dds_config_valid_ch3_i => dsp_dds_config_valid_ch3,
dds_pinc_ch0_i => dsp_dds_pinc_ch0,
dds_pinc_ch1_i => dsp_dds_pinc_ch1,
dds_pinc_ch2_i => dsp_dds_pinc_ch2,
dds_pinc_ch3_i => dsp_dds_pinc_ch3,
dds_poff_ch0_i => dsp_dds_poff_ch0,
dds_poff_ch1_i => dsp_dds_poff_ch1,
dds_poff_ch2_i => dsp_dds_poff_ch2,
dds_poff_ch3_i => dsp_dds_poff_ch3,
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_dbg_data_o => dsp_adc_ch0_data,
adc_ch1_dbg_data_o => dsp_adc_ch1_data,
adc_ch2_dbg_data_o => dsp_adc_ch2_data,
adc_ch3_dbg_data_o => dsp_adc_ch3_data,
bpf_ch0_o => dsp_bpf_ch0,
--bpf_ch1_o => out std_logic_vector(23 downto 0);
bpf_ch2_o => dsp_bpf_ch2,
--bpf_ch3_o => out std_logic_vector(23 downto 0);
bpf_valid_o => dsp_bpf_valid,
mix_ch0_i_o => dsp_mix_ch0,
--mix_ch0_q_o => out std_logic_vector(23 downto 0);
--mix_ch1_i_o => out std_logic_vector(23 downto 0);
--mix_ch1_q_o => out std_logic_vector(23 downto 0);
mix_ch2_i_o => dsp_mix_ch2,
--mix_ch2_q_o => out std_logic_vector(23 downto 0);
--mix_ch3_i_o => out std_logic_vector(23 downto 0);
--mix_ch3_q_o => out std_logic_vector(23 downto 0);
mix_valid_o => dsp_mix_valid,
tbt_decim_ch0_i_o => dsp_poly35_ch0,
--tbt_decim_ch0_i_o => open,
--poly35_ch0_q_o => out std_logic_vector(23 downto 0);
--poly35_ch1_i_o => out std_logic_vector(23 downto 0);
--poly35_ch1_q_o => out std_logic_vector(23 downto 0);
tbt_decim_ch2_i_o => dsp_poly35_ch2,
--tbt_decim_ch2_i_o => open,
--poly35_ch2_q_o => out std_logic_vector(23 downto 0);
--poly35_ch3_i_o => out std_logic_vector(23 downto 0);
--poly35_ch3_q_o => out std_logic_vector(23 downto 0);
tbt_decim_q_ch01_incorrect_o => dsp_tbt_decim_q_ch01_incorrect,
tbt_decim_q_ch23_incorrect_o => dsp_tbt_decim_q_ch23_incorrect,
tbt_amp_ch0_o => dsp_tbt_amp_ch0,
tbt_amp_ch0_valid_o => dsp_tbt_amp_ch0_valid,
tbt_amp_ch1_o => dsp_tbt_amp_ch1,
tbt_amp_ch1_valid_o => dsp_tbt_amp_ch1_valid,
tbt_amp_ch2_o => dsp_tbt_amp_ch2,
tbt_amp_ch2_valid_o => dsp_tbt_amp_ch2_valid,
tbt_amp_ch3_o => dsp_tbt_amp_ch3,
tbt_amp_ch3_valid_o => dsp_tbt_amp_ch3_valid,
tbt_pha_ch0_o => dsp_tbt_pha_ch0,
tbt_pha_ch0_valid_o => dsp_tbt_pha_ch0_valid,
tbt_pha_ch1_o => dsp_tbt_pha_ch1,
tbt_pha_ch1_valid_o => dsp_tbt_pha_ch1_valid,
tbt_pha_ch2_o => dsp_tbt_pha_ch2,
tbt_pha_ch2_valid_o => dsp_tbt_pha_ch2_valid,
tbt_pha_ch3_o => dsp_tbt_pha_ch3,
tbt_pha_ch3_valid_o => dsp_tbt_pha_ch3_valid,
fofb_decim_ch0_i_o => dsp_cic_fofb_ch0, --out std_logic_vector(23 downto 0);
--cic_fofb_ch0_q_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch1_i_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch1_q_o => out std_logic_vector(24 downto 0);
fofb_decim_ch2_i_o => dsp_cic_fofb_ch2, --out std_logic_vector(23 downto 0);
--cic_fofb_ch2_q_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch3_i_o => out std_logic_vector(24 downto 0);
--cic_fofb_ch3_q_o => out std_logic_vector(24 downto 0);
fofb_decim_q_01_missing_o => dsp_fofb_decim_q_01_missing,
fofb_decim_q_23_missing_o => dsp_fofb_decim_q_23_missing,
fofb_amp_ch0_o => dsp_fofb_amp_ch0,
fofb_amp_ch0_valid_o => dsp_fofb_amp_ch0_valid,
fofb_amp_ch1_o => dsp_fofb_amp_ch1,
fofb_amp_ch1_valid_o => dsp_fofb_amp_ch1_valid,
fofb_amp_ch2_o => dsp_fofb_amp_ch2,
fofb_amp_ch2_valid_o => dsp_fofb_amp_ch2_valid,
fofb_amp_ch3_o => dsp_fofb_amp_ch3,
fofb_amp_ch3_valid_o => dsp_fofb_amp_ch3_valid,
fofb_pha_ch0_o => dsp_fofb_pha_ch0,
fofb_pha_ch0_valid_o => dsp_fofb_pha_ch0_valid,
fofb_pha_ch1_o => dsp_fofb_pha_ch1,
fofb_pha_ch1_valid_o => dsp_fofb_pha_ch1_valid,
fofb_pha_ch2_o => dsp_fofb_pha_ch2,
fofb_pha_ch2_valid_o => dsp_fofb_pha_ch2_valid,
fofb_pha_ch3_o => dsp_fofb_pha_ch3,
fofb_pha_ch3_valid_o => dsp_fofb_pha_ch3_valid,
monit_amp_ch0_o => dsp_monit_amp_ch0,
monit_amp_ch0_valid_o => dsp_monit_amp_ch0_valid,
monit_amp_ch1_o => dsp_monit_amp_ch1,
monit_amp_ch1_valid_o => dsp_monit_amp_ch1_valid,
monit_amp_ch2_o => dsp_monit_amp_ch2,
monit_amp_ch2_valid_o => dsp_monit_amp_ch2_valid,
monit_amp_ch3_o => dsp_monit_amp_ch3,
monit_amp_ch3_valid_o => dsp_monit_amp_ch3_valid,
x_tbt_o => dsp_x_tbt,
x_tbt_valid_o => dsp_x_tbt_valid,
y_tbt_o => dsp_y_tbt,
y_tbt_valid_o => dsp_y_tbt_valid,
q_tbt_o => dsp_q_tbt,
q_tbt_valid_o => dsp_q_tbt_valid,
sum_tbt_o => dsp_sum_tbt,
sum_tbt_valid_o => dsp_sum_tbt_valid,
x_fofb_o => dsp_x_fofb,
x_fofb_valid_o => dsp_x_fofb_valid,
y_fofb_o => dsp_y_fofb,
y_fofb_valid_o => dsp_y_fofb_valid,
q_fofb_o => dsp_q_fofb,
q_fofb_valid_o => dsp_q_fofb_valid,
sum_fofb_o => dsp_sum_fofb,
sum_fofb_valid_o => dsp_sum_fofb_valid,
x_monit_o => dsp_x_monit,
x_monit_valid_o => dsp_x_monit_valid,
y_monit_o => dsp_y_monit,
y_monit_valid_o => dsp_y_monit_valid,
q_monit_o => dsp_q_monit,
q_monit_valid_o => dsp_q_monit_valid,
sum_monit_o => dsp_sum_monit,
sum_monit_valid_o => dsp_sum_monit_valid,
x_monit_1_o => dsp_x_monit_1,
x_monit_1_valid_o => dsp_x_monit_1_valid,
y_monit_1_o => dsp_y_monit_1,
y_monit_1_valid_o => dsp_y_monit_1_valid,
q_monit_1_o => dsp_q_monit_1,
q_monit_1_valid_o => dsp_q_monit_1_valid,
sum_monit_1_o => dsp_sum_monit_1,
sum_monit_1_valid_o => dsp_sum_monit_1_valid,
monit_cic_unexpected_o => dsp_monit_cic_unexpected,
monit_cfir_incorrect_o => dsp_monit_cfir_incorrect,
monit_pfir_incorrect_o => dsp_monit_pfir_incorrect,
-----------------------------
-- Output to RFFE board
-----------------------------
clk_swap_o => open,
ctrl1_o => open,
ctrl2_o => open,
-----------------------------
-- Clock drivers for various rates
-----------------------------
clk_ce_1_o => dsp_clk_ce_1,
clk_ce_1112_o => dsp_clk_ce_1112,
clk_ce_11120000_o => dsp_clk_ce_11120000,
clk_ce_1390000_o => dsp_clk_ce_1390000,
clk_ce_2_o => dsp_clk_ce_2,
clk_ce_2224_o => dsp_clk_ce_2224,
clk_ce_22240000_o => dsp_clk_ce_22240000,
clk_ce_2780000_o => dsp_clk_ce_2780000,
clk_ce_35_o => dsp_clk_ce_35,
clk_ce_5000_o => dsp_clk_ce_5000,
clk_ce_556_o => dsp_clk_ce_556,
clk_ce_5560000_o => dsp_clk_ce_5560000,
clk_ce_70_o => dsp_clk_ce_70
);
--dsp_poly35_ch0 <= (others => '0');
--dsp_poly35_ch2 <= (others => '0');
--
--dsp_monit_amp_ch0 <= (others => '0');
--dsp_monit_amp_ch1 <= (others => '0');
--dsp_monit_amp_ch2 <= (others => '0');
--dsp_monit_amp_ch3 <= (others => '0');
-- Signals for the DSP chain
--dsp_del_sig_div_thres <= "00000000000000001000000000"; -- aprox 1.22e-4 FIX26_22
-- register DSP parameters
p_register_in_dsp_param : process(fs_clk2x)
begin
if rising_edge(fs_clk2x) then
if fs_rstn = '0' then
dsp_del_sig_div_thres <= (others => '0');
dsp_kx <= (others => '0');
dsp_ky <= (others => '0');
dsp_ksum <= (others => '0');
else
dsp_del_sig_div_thres <= dsp_del_sig_div_thres_in;
dsp_kx <= dsp_kx_in;
dsp_ky <= dsp_ky_in;
dsp_ksum <= dsp_ksum_in;
end if;
end if;
end process;
-- Division Threshold selection
with dsp_del_sig_div_thres_sel select
dsp_del_sig_div_thres_in <= "00000000000000001000000000" when "00", -- aprox 1.2207e-04 FIX26_22
"00000000000000000001000000" when "01", -- aprox 1.5259e-05 FIX26_22
"00000000000000000000001000" when "10", -- aprox 1.9073e-06 FIX26_22
"00000000000000000000000000" when "11", -- 0 FIX26_22
"00000000000000001000000000" when others;
-- Kx selection
with dsp_kx_sel select
dsp_kx_in <= "0100110001001011010000000" when "00", -- 10000000 UFIX25_0
"0010011000100101101000000" when "01", -- 5000000 UFIX25_0
"0001001100010010110100000" when "10", -- 2500000 UFIX25_0
"1000000000000000000000000" when "11", -- 33554432 UFIX25_0 for testing bit truncation
"0100110001001011010000000" when others; -- 10000000 UFIX25_0
-- Ky selection
with dsp_ky_sel select
dsp_ky_in <= "0100110001001011010000000" when "00", -- 10000000 UFIX25_0
"0010011000100101101000000" when "01", -- 5000000 UFIX25_0
"0001001100010010110100000" when "10", -- 2500000 UFIX25_0
"1000000000000000000000000" when "11", -- 33554432 UFIX25_0 for testing bit truncation
"0100110001001011010000000" when others; -- 10000000 UFIX25_0
-- Ksum selection
with dsp_ksum_sel select
dsp_ksum_in <= "0111111111111111111111111" when "00", -- 1.0 FIX25_24
"0011111111111111111111111" when "01", -- 0.5 FIX25_24
"0001111111111111111111111" when "10", -- 0.25 FIX25_24
"0000111111111111111111111" when "11", -- 0.125 FIX25_24
"0111111111111111111111111" when others; -- 1.0 FIX25_24
--dsp_kx <= "0100110001001011010000000"; -- 10000000 UFIX25_0
--dsp_kx <= "0100000000000000000000000"; -- ??? UFIX25_0
--dsp_kx <= "00100110001001011010000000"; -- 10000000 UFIX26_0
--dsp_ky <= "100110001001011010000000"; -- 10000000 UFIX24_0
--dsp_ky <= "0100000000000000000000000"; -- ??? UFIX25_0
--dsp_ky <= "00100110001001011010000000"; -- 10000000 UFIX26_0
--dsp_ksum <= "0111111111111111111111111"; -- 1.0 FIX25_24
--dsp_ksum <= "10000000000000000000000000"; -- 1.0 FIX26_25
--dsp_ksum <= "100000000000000000000000"; -- 1.0 FIX24_23
--dsp_ksum <= "10000000000000000000000000"; -- 1.0 FIX26_25
--flag1_int <= fs_clk;
flag1_int <= dsp_clk_ce_35; -- FIXME!!
flag2_int <= dsp_clk_ce_70; -- FIXME!!
flag1_o <= flag1_int;
flag2_o <= flag2_int;
-- The board peripherals components is slave 9
cmp_xwb_dbe_periph : xwb_dbe_periph
generic map(
-- NOT used!
--g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- NOT used!
--g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period => c_tics_cntr_period,
g_num_leds => c_leds_num_pins,
g_num_buttons => c_buttons_num_pins
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- UART
--uart_rxd_i => uart_rxd_i,
--uart_txd_o => uart_txd_o,
uart_rxd_i => '1',
uart_txd_o => open,
-- LEDs
led_out_o => gpio_leds_int,
led_in_i => gpio_leds_int,
led_oen_o => open,
-- Buttons
button_out_o => open,
button_in_i => buttons_i,
button_oen_o => open,
-- Wishbone
slave_i => cbar_master_o(9),
slave_o => cbar_master_i(9)
);
leds_o <= gpio_leds_int;
-- Chipscope Analysis
cmp_chipscope_icon_13 : chipscope_icon_13_port
port map (
CONTROL0 => CONTROL0,
CONTROL1 => CONTROL1,
CONTROL2 => CONTROL2,
CONTROL3 => CONTROL3,
CONTROL4 => CONTROL4,
CONTROL5 => CONTROL5,
CONTROL6 => CONTROL6,
CONTROL7 => CONTROL7,
CONTROL8 => CONTROL8,
CONTROL9 => CONTROL9,
CONTROL10 => CONTROL10,
CONTROL11 => CONTROL11,
CONTROL12 => CONTROL12
);
cmp_chipscope_ila_0_adc : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => fs_clk,
TRIG0 => TRIG_ILA0_0,
TRIG1 => TRIG_ILA0_1,
TRIG2 => TRIG_ILA0_2,
TRIG3 => TRIG_ILA0_3
);
-- ADC Data
TRIG_ILA0_0 <= dsp_adc_ch1_data & dsp_adc_ch0_data;
TRIG_ILA0_1 <= dsp_adc_ch3_data & dsp_adc_ch2_data;
TRIG_ILA0_2 <= (others => '0');
TRIG_ILA0_3 <= (others => '0');
-- Mix and BPF data
--cmp_chipscope_ila_4096_bpf_mix : chipscope_ila_4096 (
cmp_chipscope_ila_1024_bpf_mix : chipscope_ila_1024
port map (
CONTROL => CONTROL1,
--CLK => fs_clk2x,
CLK => fs_clk,
TRIG0 => TRIG_ILA1_0,
TRIG1 => TRIG_ILA1_1,
TRIG2 => TRIG_ILA1_2,
TRIG3 => TRIG_ILA1_3,
TRIG4 => TRIG_ILA1_4
);
TRIG_ILA1_0(0) <= dsp_bpf_valid; -- or dsp_mix_valid
TRIG_ILA1_0(1) <= '0';
TRIG_ILA1_0(2) <= '0';
TRIG_ILA1_0(3) <= '0';
TRIG_ILA1_0(4) <= '0';
TRIG_ILA1_0(5) <= '0';
TRIG_ILA1_0(6) <= '0';
TRIG_ILA1_1(dsp_bpf_ch0'left downto 0) <= dsp_bpf_ch0;
TRIG_ILA1_2(dsp_bpf_ch2'left downto 0) <= dsp_bpf_ch2;
TRIG_ILA1_3(dsp_mix_ch0'left downto 0) <= dsp_mix_ch0;
TRIG_ILA1_4(dsp_mix_ch2'left downto 0) <= dsp_mix_ch2;
--TBT amplitudes data
--cmp_chipscope_ila_4096_tbt_amp : chipscope_ila_4096 (
cmp_chipscope_ila_1024_tbt_amp : chipscope_ila_1024
port map (
CONTROL => CONTROL2,
--CLK => fs_clk2x,
CLK => fs_clk,
TRIG0 => TRIG_ILA2_0,
TRIG1 => TRIG_ILA2_1,
TRIG2 => TRIG_ILA2_2,
TRIG3 => TRIG_ILA2_3,
TRIG4 => TRIG_ILA2_4
);
TRIG_ILA2_0(0) <= dsp_tbt_amp_ch0_valid;
TRIG_ILA2_0(1) <= '0';
TRIG_ILA2_0(2) <= '0';
TRIG_ILA2_0(3) <= '0';
TRIG_ILA2_0(4) <= '0';
TRIG_ILA2_0(5) <= '0';
TRIG_ILA2_0(6) <= '0';
TRIG_ILA2_1(dsp_tbt_amp_ch0'left downto 0) <= dsp_tbt_amp_ch0;
TRIG_ILA2_2(dsp_tbt_amp_ch1'left downto 0) <= dsp_tbt_amp_ch1;
TRIG_ILA2_3(dsp_tbt_amp_ch2'left downto 0) <= dsp_tbt_amp_ch2;
TRIG_ILA2_4(dsp_tbt_amp_ch3'left downto 0) <= dsp_tbt_amp_ch3;
-- TBT position data
--cmp_chipscope_ila_4096_tbt_pos : chipscope_ila_4096
cmp_chipscope_ila_1024_tbt_pos : chipscope_ila_1024
port map (
CONTROL => CONTROL3,
--CLK => fs_clk2x,
CLK => fs_clk,
TRIG0 => TRIG_ILA3_0,
TRIG1 => TRIG_ILA3_1,
TRIG2 => TRIG_ILA3_2,
TRIG3 => TRIG_ILA3_3,
TRIG4 => TRIG_ILA3_4
);
TRIG_ILA3_0(0) <= dsp_x_tbt_valid;
TRIG_ILA3_0(1) <= '0';
TRIG_ILA3_0(2) <= '0';
TRIG_ILA3_0(3) <= '0';
TRIG_ILA3_0(4) <= '0';
TRIG_ILA3_0(5) <= '0';
TRIG_ILA3_0(6) <= '0';
TRIG_ILA3_1(dsp_x_tbt'left downto 0) <= dsp_x_tbt;
TRIG_ILA3_2(dsp_y_tbt'left downto 0) <= dsp_y_tbt;
TRIG_ILA3_3(dsp_q_tbt'left downto 0) <= dsp_q_tbt;
TRIG_ILA3_4(dsp_sum_tbt'left downto 0) <= dsp_sum_tbt;
-- FOFB amplitudes data
--cmp_chipscope_ila_4096_fofb_amp : chipscope_ila_4096
cmp_chipscope_ila_1024_fofb_amp : chipscope_ila_1024 -- TESTING SYNTHESIS TIME!
--cmp_chipscope_ila_65536_fofb_amp : chipscope_ila_65536
port map (
CONTROL => CONTROL4,
--CLK => fs_clk2x,
CLK => fs_clk,
TRIG0 => TRIG_ILA4_0,
TRIG1 => TRIG_ILA4_1,
TRIG2 => TRIG_ILA4_2,
TRIG3 => TRIG_ILA4_3,
TRIG4 => TRIG_ILA4_4
);
TRIG_ILA4_0(0) <= dsp_fofb_amp_ch0_valid;
TRIG_ILA4_0(1) <= '0';
TRIG_ILA4_0(2) <= '0';
TRIG_ILA4_0(3) <= '0';
TRIG_ILA4_0(4) <= '0';
TRIG_ILA4_0(5) <= '0';
TRIG_ILA4_0(6) <= '0';
TRIG_ILA4_1(dsp_fofb_amp_ch0'left downto 0) <= dsp_fofb_amp_ch0;
TRIG_ILA4_2(dsp_fofb_amp_ch1'left downto 0) <= dsp_fofb_amp_ch1;
TRIG_ILA4_3(dsp_fofb_amp_ch2'left downto 0) <= dsp_fofb_amp_ch2;
TRIG_ILA4_4(dsp_fofb_amp_ch3'left downto 0) <= dsp_fofb_amp_ch3;
-- FOFB position data
--cmp_chipscope_ila_4096_fofb_pos : chipscope_ila_4096
--cmp_chipscope_ila_131072_fofb_pos : chipscope_ila_131072
--cmp_chipscope_ila_65536_fofb_pos : chipscope_ila_65536
cmp_chipscope_ila_1024_fofb_pos : chipscope_ila_1024
port map (
CONTROL => CONTROL5,
--CLK => fs_clk2x,
CLK => fs_clk,
TRIG0 => TRIG_ILA5_0,
TRIG1 => TRIG_ILA5_1,
TRIG2 => TRIG_ILA5_2,
TRIG3 => TRIG_ILA5_3,
TRIG4 => TRIG_ILA5_4
);
TRIG_ILA5_0(0) <= dsp_x_fofb_valid;
TRIG_ILA5_0(1) <= '0';
TRIG_ILA5_0(2) <= '0';
TRIG_ILA5_0(3) <= '0';
TRIG_ILA5_0(4) <= '0';
TRIG_ILA5_0(5) <= '0';
TRIG_ILA5_0(6) <= '0';
TRIG_ILA5_1(dsp_x_fofb'left downto 0) <= dsp_x_fofb;
TRIG_ILA5_2(dsp_y_fofb'left downto 0) <= dsp_y_fofb;
TRIG_ILA5_3(dsp_q_fofb'left downto 0) <= dsp_q_fofb;
TRIG_ILA5_4(dsp_sum_fofb'left downto 0) <= dsp_sum_fofb;
-- Monitoring position amplitude
--chipscope_ila_4096 cmp_chipscope_ila_4096_monit_amp_i
cmp_chipscope_ila_1024_monit_amp : chipscope_ila_1024
port map (
CONTROL => CONTROL6,
--CLK => fs_clk2x,
CLK => fs_clk,
TRIG0 => TRIG_ILA6_0,
TRIG1 => TRIG_ILA6_1,
TRIG2 => TRIG_ILA6_2,
TRIG3 => TRIG_ILA6_3,
TRIG4 => TRIG_ILA6_4
);
TRIG_ILA6_0(0) <= dsp_monit_amp_ch0_valid;
TRIG_ILA6_0(1) <= '0';
TRIG_ILA6_0(2) <= '0';
TRIG_ILA6_0(3) <= '0';
TRIG_ILA6_0(4) <= '0';
TRIG_ILA6_0(5) <= '0';
TRIG_ILA6_0(6) <= '0';
TRIG_ILA6_1(dsp_monit_amp_ch0'left downto 0) <= dsp_monit_amp_ch0;
TRIG_ILA6_2(dsp_monit_amp_ch1'left downto 0) <= dsp_monit_amp_ch1;
TRIG_ILA6_3(dsp_monit_amp_ch2'left downto 0) <= dsp_monit_amp_ch2;
TRIG_ILA6_4(dsp_monit_amp_ch3'left downto 0) <= dsp_monit_amp_ch3;
-- Monitoring position data
-- cmp_chipscope_ila_4096_monit_pos : chipscope_ila_4096
cmp_chipscope_ila_1024_monit_pos : chipscope_ila_1024
port map (
CONTROL => CONTROL7,
--CLK => fs_clk2x,
CLK => fs_clk,
TRIG0 => TRIG_ILA7_0,
TRIG1 => TRIG_ILA7_1,
TRIG2 => TRIG_ILA7_2,
TRIG3 => TRIG_ILA7_3,
TRIG4 => TRIG_ILA7_4
);
TRIG_ILA7_0(0) <= dsp_x_monit_valid;
TRIG_ILA7_0(1) <= '0';
TRIG_ILA7_0(2) <= '0';
TRIG_ILA7_0(3) <= '0';
TRIG_ILA7_0(4) <= '0';
TRIG_ILA7_0(5) <= '0';
TRIG_ILA7_0(6) <= '0';
TRIG_ILA7_1(dsp_x_monit'left downto 0) <= dsp_x_monit;
TRIG_ILA7_2(dsp_y_monit'left downto 0) <= dsp_y_monit;
TRIG_ILA7_3(dsp_q_monit'left downto 0) <= dsp_q_monit;
TRIG_ILA7_4(dsp_sum_monit'left downto 0) <= dsp_sum_monit;
-- Monitoring 1 position data
--cmp_chipscope_ila_32768_monit_pos_1 : chipscope_ila_32768
cmp_chipscope_ila_1024_monit_pos_1 : chipscope_ila_1024
port map (
CONTROL => CONTROL8,
--CLK => fs_clk2x,
CLK => fs_clk,
TRIG0 => TRIG_ILA8_0,
TRIG1 => TRIG_ILA8_1,
TRIG2 => TRIG_ILA8_2,
TRIG3 => TRIG_ILA8_3,
TRIG4 => TRIG_ILA8_4
);
TRIG_ILA8_0(0) <= dsp_x_monit_1_valid;
TRIG_ILA8_0(1) <= '0';
TRIG_ILA8_0(2) <= '0';
TRIG_ILA8_0(3) <= '0';
TRIG_ILA8_0(4) <= '0';
TRIG_ILA8_0(5) <= '0';
TRIG_ILA8_0(6) <= '0';
TRIG_ILA8_1(dsp_x_monit_1'left downto 0) <= dsp_x_monit_1;
TRIG_ILA8_2(dsp_y_monit_1'left downto 0) <= dsp_y_monit_1;
TRIG_ILA8_3(dsp_q_monit_1'left downto 0) <= dsp_q_monit_1;
TRIG_ILA8_4(dsp_sum_monit_1'left downto 0) <= dsp_sum_monit_1;
-- TBT Phase data
--cmp_chipscope_ila_4096_tbt_pha : chipscope_ila_4096
cmp_chipscope_ila_1024_tbt_pha : chipscope_ila_1024
port map (
CONTROL => CONTROL9,
--CLK => fs_clk2x,
CLK => fs_clk,
TRIG0 => TRIG_ILA9_0,
TRIG1 => TRIG_ILA9_1,
TRIG2 => TRIG_ILA9_2,
TRIG3 => TRIG_ILA9_3,
TRIG4 => TRIG_ILA9_4
);
TRIG_ILA9_0(0) <= dsp_tbt_pha_ch0_valid;
TRIG_ILA9_0(1) <= '0';
TRIG_ILA9_0(2) <= '0';
TRIG_ILA9_0(3) <= '0';
TRIG_ILA9_0(4) <= '0';
TRIG_ILA9_0(5) <= '0';
TRIG_ILA9_0(6) <= '0';
TRIG_ILA9_1(dsp_tbt_pha_ch0'left downto 0) <= dsp_tbt_pha_ch0;
TRIG_ILA9_2(dsp_tbt_pha_ch1'left downto 0) <= dsp_tbt_pha_ch1;
TRIG_ILA9_3(dsp_tbt_pha_ch2'left downto 0) <= dsp_tbt_pha_ch2;
TRIG_ILA9_4(dsp_tbt_pha_ch3'left downto 0) <= dsp_tbt_pha_ch3;
-- FOFB Phase data
--cmp_chipscope_ila_4096_fofb_pha : chipscope_ila_4096
cmp_chipscope_ila_1024_fofb_pha : chipscope_ila_1024
port map (
CONTROL => CONTROL10,
--CLK => fs_clk2x,
CLK => fs_clk,
TRIG0 => TRIG_ILA10_0,
TRIG1 => TRIG_ILA10_1,
TRIG2 => TRIG_ILA10_2,
TRIG3 => TRIG_ILA10_3,
TRIG4 => TRIG_ILA10_4
);
TRIG_ILA10_0(0) <= dsp_fofb_pha_ch0_valid;
TRIG_ILA10_0(1) <= '0';
TRIG_ILA10_0(2) <= '0';
TRIG_ILA10_0(3) <= '0';
TRIG_ILA10_0(4) <= '0';
TRIG_ILA10_0(5) <= '0';
TRIG_ILA10_0(6) <= '0';
TRIG_ILA10_1(dsp_fofb_pha_ch0'left downto 0) <= dsp_fofb_pha_ch0;
TRIG_ILA10_2(dsp_fofb_pha_ch1'left downto 0) <= dsp_fofb_pha_ch1;
TRIG_ILA10_3(dsp_fofb_pha_ch2'left downto 0) <= dsp_fofb_pha_ch2;
TRIG_ILA10_4(dsp_fofb_pha_ch3'left downto 0) <= dsp_fofb_pha_ch3;
-- Controllable gain for test data
cmp_chipscope_vio_256 : chipscope_vio_256
port map (
CONTROL => CONTROL11,
ASYNC_OUT => vio_out
);
dds_sine_gain_ch0 <= vio_out(10-1 downto 0);
dds_sine_gain_ch1 <= vio_out(20-1 downto 10);
dds_sine_gain_ch2 <= vio_out(30-1 downto 20);
dds_sine_gain_ch3 <= vio_out(40-1 downto 30);
adc_synth_data_en <= vio_out(40);
un_cross_gain_aa <= vio_out(65 downto 50);
un_cross_gain_bb <= vio_out(81 downto 66);
un_cross_gain_cc <= vio_out(97 downto 82);
un_cross_gain_dd <= vio_out(113 downto 98);
un_cross_gain_ac <= vio_out(129 downto 114);
un_cross_gain_bd <= vio_out(145 downto 130);
un_cross_gain_ca <= vio_out(161 downto 146);
un_cross_gain_db <= vio_out(177 downto 162);
un_cross_delay_1 <= vio_out(193 downto 178);
un_cross_delay_2 <= vio_out(209 downto 194);
un_cross_mode_1 <= vio_out(211 downto 210);
un_cross_mode_2 <= vio_out(213 downto 212);
un_cross_div_f <= vio_out(229 downto 214);
dsp_del_sig_div_thres_sel <= vio_out(231 downto 230);
dsp_kx_sel <= vio_out(233 downto 232);
dsp_ky_sel <= vio_out(235 downto 234);
dsp_ksum_sel <= vio_out(237 downto 236);
-- Controllable DDS frequency and phase
cmp_chipscope_vio_256_dsp_config : chipscope_vio_256
port map (
CONTROL => CONTROL12,
ASYNC_OUT => vio_out_dsp_config
);
dsp_dds_pinc_ch0 <= vio_out_dsp_config(29 downto 0);
dsp_dds_pinc_ch1 <= vio_out_dsp_config(59 downto 30);
dsp_dds_pinc_ch2 <= vio_out_dsp_config(89 downto 60);
dsp_dds_pinc_ch3 <= vio_out_dsp_config(119 downto 90);
dsp_dds_poff_ch0 <= vio_out_dsp_config(149 downto 120);
dsp_dds_poff_ch1 <= vio_out_dsp_config(179 downto 150);
dsp_dds_poff_ch2 <= vio_out_dsp_config(209 downto 180);
dsp_dds_poff_ch3 <= vio_out_dsp_config(239 downto 210);
dsp_dds_config_valid_ch0 <= vio_out_dsp_config(240);
dsp_dds_config_valid_ch1 <= vio_out_dsp_config(241);
dsp_dds_config_valid_ch2 <= vio_out_dsp_config(242);
dsp_dds_config_valid_ch3 <= vio_out_dsp_config(243);
-- edge detect for dds config.... not actually needed as
-- long as we deassert valid not too much after
end rtl;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/modules/rffe_top/bpm_swap_ctrl/rf_ch_swap.vhd | 1 | 4646 | ------------------------------------------------------------------------------
-- Title : RF channels Swapping
------------------------------------------------------------------------------
-- Author : José Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: This core controls the swapping mechanism for ONE pair of
-- channels. It is possible swapping channels inputs @ clk_in_ext
-- frequency or stay fixed at direct/inverted/off position.
--
-- MODE: 00 turned off 01 direct 10 inverted 11 Swapping
--
-- CTRL: b1b0d1d0
-- This core was developed to Sirus Synchrotron Light Source.
-- The BPM RFFE uses HSWA2-30DR+ switches and are controlled by
-- arrangement of bits in CTRL.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-10-18 1.0 jose.berkenbrock Created
-- 2012-10-20 1.1 daniel.tavares
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rf_ch_swap is
generic
(
g_direct : std_logic_vector(7 downto 0) := "10100101";
g_inverted : std_logic_vector(7 downto 0) := "01011010"
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_swap_i : in std_logic;
mode_i : in std_logic_vector(1 downto 0);
ctrl_o : out std_logic_vector(7 downto 0));
end rf_ch_swap;
architecture rtl of rf_ch_swap is
--signal s_mode : std_logic_vector(1 downto 0);
signal ctrl : std_logic_vector(7 downto 0);
--signal ctrl_aux : std_logic_vector(7 downto 0);
--signal ctrl_old : std_logic_vector(7 downto 0);
--signal s_bit : std_logic;
begin
--------------------------------
-- Input Register
--------------------------------
-- p_reg_mode : process(rst_i, clk_i)
-- begin
-- if rst_i = '1' then
-- s_mode <= (others => '0');
-- elsif rising_edge(clk_i) then
-- s_mode <= mode_i;
-- else s_mode <= s_mode;
-- end if;
-- end process p_reg_mode;
--------------------------------
-- Swapping Process
--------------------------------
p_swap : process(clk_i,rst_i)
begin
---------------------------------------------------------------
-- if rst_i = '1' then
-- s_bit <= '0';
-- ctrl_aux <= "10100101";
-- ctrl <= "10100101";
-- elsif rising_edge(clk_i) then
-- s_bit <= not s_bit;
-- else s_bit <= s_bit;
-- end if;
---------------------------------------------------------------
if rst_i = '1' then
--ctrl_old <= "10100101"; -- initialize in direct channels
--s_bit <= '0';
ctrl <= "00000000";
elsif rising_edge(clk_i) then
if mode_i = "11" then -- crossed Swapping
-- ctrl <= not ctrl;
if en_swap_i = '0' then
ctrl <= g_direct;
else
ctrl <= g_inverted;
end if;
elsif mode_i = "10" then -- inverted
ctrl <= g_inverted;
elsif mode_i = "01" then -- direct
ctrl <= g_direct;
else
ctrl <= (others=>'0'); -- Swapping off
end if;
--ctrl_old <= ctrl;
end if;
-- ctrl <= "10100101" when s_bit = '1' else "01011010";
-- with s_bit select
-- ctrl <= "10100101" when '0',
-- "01011010" when others;
---------------------------------------------------------------
end process p_swap;
---------------------------------------------------------------
-- with s_bit select
-- ctrl_aux <= "10100101" when '0',
-- "01011010" when '1';
-- ctrl_aux when others;
--
-- with s_mode select
-- ctrl <= "00000000" when "00",
-- "10100101" when "01",
-- "01011010" when "10",
-- ctrl_aux when "11";
-- ctrl when others;
--------------------------------
-- Output Register
--------------------------------
p_reg_ctrl : process(rst_i, clk_i)
begin
if rst_i = '1' then
ctrl_o <= (others => '0'); -- rst_i = 1 => Swapping off
-- ctrl_old <= "00000000";
elsif rising_edge(clk_i) then
ctrl_o <= ctrl;
-- ctrl_old <= ctrl;
end if;
end process p_reg_ctrl;
end rtl; | lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/modules/pcie/common/wb_mem.vhd | 1 | 1119 | -- -----------------------------------------
--
-- Simple generic wishbone memory module
--
-- Created by: abyszuk
--
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity WB_MEM is
generic(
AWIDTH : natural range 2 to 29;
DWIDTH : natural range 8 to 128
);
port(
-- WISHBONE SLAVE interface:
-- Single-Port RAM with Asynchronous Read
--
CLK_I : in std_logic;
ACK_O : out std_logic;
ADR_I : in std_logic_vector(AWIDTH-1 downto 0);
DAT_I : in std_logic_vector(DWIDTH-1 downto 0);
DAT_O : out std_logic_vector(DWIDTH-1 downto 0);
STB_I : in std_logic;
WE_I : in std_logic
);
end entity WB_MEM;
architecture rtl of WB_MEM is
type ram_type is array (2**AWIDTH downto 0) of std_logic_vector(DWIDTH-1 downto 0);
signal RAM : ram_type;
begin
REG: process(CLK_I)
begin
if(rising_edge(CLK_I)) then
if((STB_I and WE_I) = '1') then
RAM(to_integer(unsigned(ADR_I))) <= DAT_I;
end if;
end if;
end process REG;
ACK_O <= STB_I;
DAT_O <= RAM(to_integer(unsigned(ADR_I)));
end architecture rtl;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd | 1 | 35666 | ------------------------------------------------------------------------------
-- Title : Top Etherbone test design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2012-11-12
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top dsign for testing the integration of Etherbone and
-- MAC cores
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-11-12 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_generic_pkg.all;
-- Ethernet MAC Modules and SDB structure
use work.ethmac_pkg.all;
-- Wishbone Fabric interface
use work.wr_fabric_pkg.all;
-- Etherbone slave core
use work.etherbone_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_ebone is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-----------------------------------------
-- PHY pins
-----------------------------------------
-- Clock and resets to PHY (GMII). Not used in MII mode (10/100)
mgtx_clk_o : out std_logic;
mrstn_o : out std_logic;
-- PHY TX
mtx_clk_pad_i : in std_logic;
mtxd_pad_o : out std_logic_vector(3 downto 0);
mtxen_pad_o : out std_logic;
mtxerr_pad_o : out std_logic;
-- PHY RX
mrx_clk_pad_i : in std_logic;
mrxd_pad_i : in std_logic_vector(3 downto 0);
mrxdv_pad_i : in std_logic;
mrxerr_pad_i : in std_logic;
mcoll_pad_i : in std_logic;
mcrs_pad_i : in std_logic;
-- MII
mdc_pad_o : out std_logic;
md_pad_b : inout std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_ebone;
architecture rtl of dbe_bpm_ebone is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 10; -- LED, Button,
-- General Dual-port memory, Buffer Single-por memory, UART, DMA control port, MAC,
--Etherbone
-- Number of masters
constant c_masters : natural := 8; -- LM32 master, Data + Instruction,
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone
constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB)
--constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB)
constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB)
-- GPIO num pinscalc
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
constant c_xwb_etherbone_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"68202b22",
version => x"00000001",
date => x"20120912",
name => "GSI_ETHERBONE_CFG ")));
constant c_xwb_ethmac_adapter_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"2ff9a28e",
version => x"00000001",
date => x"20130701",
name => "ETHMAC_ADAPTER ")));
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 128KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size),
x"20000000"), -- 64KB RAM
--3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30014000"), -- DMA control port
--4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30015000"), -- Ethernet MAC control port
--5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30016000"), -- Ethernet Adapter control port
--6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30017000"), -- Etherbone control port
--7 => f_sdb_embed_device(c_xwb_uart_sdb, x"30018000"), -- UART control port
--8 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"30019000"), -- GPIO LED
--9 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"3001A000") -- GPIO Button
3 => f_sdb_embed_device(c_xwb_dma_sdb, x"60000000"), -- DMA control port
4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"70000000"), -- Ethernet MAC control port
5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"80000000"), -- Ethernet Adapter control port
6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"90000000"), -- Etherbone control port
7 => f_sdb_embed_device(c_xwb_uart_sdb, x"A0000000"), -- UART control port
8 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"B0000000"), -- GPIO LED
9 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"C0000000") -- GPIO Button
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well
constant c_sdb_address : t_wishbone_address := x"30000000";
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_sys_n : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
-- 200 Mhz clocck for iodelay_ctrl
signal clk_200mhz : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
-- Ethernet MAC signals
signal ethmac_int : std_logic;
signal ethmac_md_in : std_logic;
signal ethmac_md_out : std_logic;
signal ethmac_md_oe : std_logic;
signal mtxd_pad_int : std_logic_vector(3 downto 0);
signal mtxen_pad_int : std_logic;
signal mtxerr_pad_int : std_logic;
signal mdc_pad_int : std_logic;
-- Ethrnet MAC adapter signals
signal irq_rx_done : std_logic;
signal irq_tx_done : std_logic;
-- Etherbone signals
signal wb_ebone_out : t_wishbone_master_out;
signal wb_ebone_in : t_wishbone_master_in;
signal eb_src_i : t_wrf_source_in;
signal eb_src_o : t_wrf_source_out;
signal eb_snk_i : t_wrf_sink_in;
signal eb_snk_o : t_wrf_sink_out;
-- DMA signals
signal dma_int : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
-- Counter signal
signal s_counter : unsigned(c_counter_width-1 downto 0);
-- 100MHz period or 1 second
constant s_counter_full : integer := 100000000;
-- Chipscope control signals
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
signal CONTROL2 : std_logic_vector(35 downto 0);
signal CONTROL3 : std_logic_vector(35 downto 0);
-- Chipscope ILA 0 signals
signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 1 signals
signal TRIG_ILA1_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 2 signals
signal TRIG_ILA2_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 3 signals
signal TRIG_ILA3_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_3 : std_logic_vector(31 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Controller 2 port
--component chipscope_icon_2_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0)
--);
--end component;
component chipscope_icon_4_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0);
CONTROL2 : inout std_logic_vector(35 downto 0);
CONTROL3 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
cmp_reset : gc_reset
generic map(
g_clocks => 1 -- CLK_SYS
)
port map(
free_clk_i => sys_clk_gen,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(0) <= clk_sys;
clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n;
clk_sys_rst <= not clk_sys_rstn;
mrstn_o <= clk_sys_rstn;
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
rst_button_sys_n <= not rst_button_sys;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => false, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn;
cmp_lm32 : xwb_lm32
generic map(
g_profile => "medium_icache_debug"
) -- Including JTAG and I-cache (no divide)
port map(
clk_sys_i => clk_sys,
rst_n_i => lm32_rstn,
irq_i => lm32_interrupt,
dwb_o => cbar_slave_i(0), -- Data bus
dwb_i => cbar_slave_o(0),
iwb_o => cbar_slave_i(1), -- Instruction bus
iwb_i => cbar_slave_o(1)
);
-- Interrupt '0' is Ethmac.
-- Interrupt '1' is DMA completion.
-- Interrupt '2' is Button(0).
-- Interrupt '3' is Ethernet Adapter RX completion.
-- Interrupt '4' is Ethernet Adapter TX completion.
-- Interrupts 31 downto 5 are disabled
lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done,
4 => irq_tx_done, others => '0');
-- A DMA controller is master 2+3, slave 3, and interrupt 1
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(3),
slave_o => cbar_master_i(3),
r_master_i => cbar_slave_o(2),
r_master_o => cbar_slave_i(2),
w_master_i => cbar_slave_o(3),
w_master_o => cbar_slave_i(3),
interrupt_o => dma_int
);
-- Slave 0+1 is the RAM. Load a input file containing the embedded software
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
g_init_file => "../../../embedded-sw/dbe.ram",
--"../../top/ml_605/dbe_bpm_simple/sw/main.ram",
g_must_have_init_file => true,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
);
-- Slave 2 is the RAM Buffer for Ethernet MAC.
cmp_ethmac_buf_ram : xwb_dpram
generic map(
g_size => c_dpram_ethbuf_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => CLASSIC,
--g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
--g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(2),
slave1_o => cbar_master_i(2),
-- Second port connected to the crossbar
slave2_i => cc_dummy_slave_in, -- CYC always low
slave2_o => open
);
-- The Ethernet MAC is master 4, slave 4
cmp_xwb_ethmac : xwb_ethmac
generic map (
--g_ma_interface_mode => PIPELINED,
g_ma_interface_mode => CLASSIC, -- NOT used for now
--g_ma_address_granularity => WORD,
g_ma_address_granularity => BYTE, -- NOT used for now
g_sl_interface_mode => PIPELINED,
--g_sl_interface_mode => CLASSIC,
--g_sl_address_granularity => WORD
g_sl_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rst_i => clk_sys_rst,
-- WISHBONE slave
wb_slave_in => cbar_master_o(4),
wb_slave_out => cbar_master_i(4),
-- WISHBONE master
wb_master_in => cbar_slave_o(4),
wb_master_out => cbar_slave_i(4),
-- PHY TX
mtx_clk_pad_i => mtx_clk_pad_i,
--mtxd_pad_o => mtxd_pad_o,
mtxd_pad_o => mtxd_pad_int,
--mtxen_pad_o => mtxen_pad_o,
mtxen_pad_o => mtxen_pad_int,
--mtxerr_pad_o => mtxerr_pad_o,
mtxerr_pad_o => mtxerr_pad_int,
-- PHY RX
mrx_clk_pad_i => mrx_clk_pad_i,
mrxd_pad_i => mrxd_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxerr_pad_i => mrxerr_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcrs_pad_i => mcrs_pad_i,
-- MII
--mdc_pad_o => mdc_pad_o,
mdc_pad_o => mdc_pad_int,
md_pad_i => ethmac_md_in,
md_pad_o => ethmac_md_out,
md_padoe_o => ethmac_md_oe,
-- Interrupt
int_o => ethmac_int
);
-- Tri-state buffer for MII config
md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z';
ethmac_md_in <= md_pad_b;
mtxd_pad_o <= mtxd_pad_int;
mtxen_pad_o <= mtxen_pad_int;
mtxerr_pad_o <= mtxerr_pad_int;
mdc_pad_o <= mdc_pad_int;
-- The Ethernet MAC Adapter is master 5+6, slave 5
cmp_xwb_ethmac_adapter : xwb_ethmac_adapter
port map(
clk_i => clk_sys,
rstn_i => clk_sys_rstn,
wb_slave_o => cbar_master_i(5),
wb_slave_i => cbar_master_o(5),
tx_ram_o => cbar_slave_i(5),
tx_ram_i => cbar_slave_o(5),
rx_ram_o => cbar_slave_i(6),
rx_ram_i => cbar_slave_o(6),
rx_eb_o => eb_snk_i,
rx_eb_i => eb_snk_o,
tx_eb_o => eb_src_i,
tx_eb_i => eb_src_o,
irq_tx_done_o => irq_tx_done,
irq_rx_done_o => irq_rx_done
);
-- The Etherbone is slave 6
cmp_eb_slave_core : eb_slave_core
generic map(
g_sdb_address => x"00000000" & c_sdb_address
)
port map
(
clk_i => clk_sys,
nRst_i => clk_sys_rstn,
-- EB streaming sink
snk_i => eb_snk_i,
snk_o => eb_snk_o,
-- EB streaming source
src_i => eb_src_i,
src_o => eb_src_o,
-- WB slave - Cfg IF
cfg_slave_o => cbar_master_i(6),
cfg_slave_i => cbar_master_o(6),
-- WB master - Bus IF
master_o => wb_ebone_out,
master_i => wb_ebone_in
);
cbar_slave_i(7) <= wb_ebone_out;
wb_ebone_in <= cbar_slave_o(7);
-- Slave 7 is the UART
cmp_uart : xwb_simple_uart
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
)
port map (
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(7),
slave_o => cbar_master_i(7),
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o
);
-- Slave 8 is the LED driver
cmp_leds : xwb_gpio_port
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_pins => c_leds_num_pins,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Wishbone
slave_i => cbar_master_o(8),
slave_o => cbar_master_i(8),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => gpio_leds_int,
gpio_in_i => gpio_leds_int,
gpio_oen_o => open
);
leds_o <= gpio_leds_int;
-- Slave 9 is the Button driver
cmp_buttons : xwb_gpio_port
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_pins => c_buttons_num_pins,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Wishbone
slave_i => cbar_master_o(9),
slave_o => cbar_master_i(9),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => open,
gpio_in_i => buttons_i,
gpio_oen_o => open
);
---- Xilinx Chipscope
cmp_chipscope_icon_0 : chipscope_icon_4_port
port map (
CONTROL0 => CONTROL0,
CONTROL1 => CONTROL1,
CONTROL2 => CONTROL2,
CONTROL3 => CONTROL3
);
cmp_chipscope_ila_0_ethmac : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => clk_sys,
TRIG0 => TRIG_ILA0_0,
TRIG1 => TRIG_ILA0_1,
TRIG2 => TRIG_ILA0_2,
TRIG3 => TRIG_ILA0_3
);
-- ETHMAC master output (slave input) control data
TRIG_ILA0_0 <= cbar_slave_o(4).dat;
-- ETHMAC master input (slave output) control data
TRIG_ILA0_1 <= cbar_slave_i(4).dat;
-- ETHMAC master control input (slave output) control signals
TRIG_ILA0_2(4 downto 0) <= cbar_slave_o(4).ack &
cbar_slave_o(4).err &
cbar_slave_o(4).rty &
cbar_slave_o(4).stall &
cbar_slave_o(4).int;
TRIG_ILA0_2(31 downto 5) <= (others => '0');
-- ETHMAC master control output (slave input) control signals
-- Partial decoding. Thus, only the LSB part of address matters to
-- a specific slave core
TRIG_ILA0_3(18 downto 0) <= cbar_slave_i(4).cyc &
cbar_slave_i(4).stb &
cbar_slave_i(4).adr(11 downto 0) &
cbar_slave_i(4).sel &
cbar_slave_i(4).we;
TRIG_ILA0_3(31 downto 19) <= (others => '0');
-- Etherbone debuging signals
--cmp_chipscope_ila_1_etherbone : chipscope_ila
--port map (
-- CONTROL => CONTROL1,
-- CLK => clk_sys,
-- TRIG0 => TRIG_ILA1_0,
-- TRIG1 => TRIG_ILA1_1,
-- TRIG2 => TRIG_ILA1_2,
-- TRIG3 => TRIG_ILA1_3
--);
--TRIG_ILA1_0 <= wb_ebone_out.dat;
--TRIG_ILA1_1 <= wb_ebone_in.dat;
--TRIG_ILA1_2 <= wb_ebone_out.adr;
--TRIG_ILA1_3(6 downto 0) <= wb_ebone_out.cyc &
-- wb_ebone_out.stb &
-- wb_ebone_out.sel &
-- wb_ebone_out.we;
--TRIG_ILA1_3(11 downto 7) <= wb_ebone_in.ack &
-- wb_ebone_in.err &
-- wb_ebone_in.rty &
-- wb_ebone_in.stall &
-- wb_ebone_in.int;
--TRIG_ILA1_3(31 downto 12) <= (others => '0');
cmp_chipscope_ila_1_ethmac_rx : chipscope_ila
port map (
CONTROL => CONTROL1,
CLK => mrx_clk_pad_i,
TRIG0 => TRIG_ILA1_0,
TRIG1 => TRIG_ILA1_1,
TRIG2 => TRIG_ILA1_2,
TRIG3 => TRIG_ILA1_3
);
TRIG_ILA1_0(7 downto 0) <= mrxd_pad_i &
mrxdv_pad_i &
mrxerr_pad_i &
mcoll_pad_i &
mcrs_pad_i;
TRIG_ILA1_0(31 downto 8) <= (others => '0');
TRIG_ILA1_1 <= (others => '0');
TRIG_ILA1_2 <= (others => '0');
TRIG_ILA1_3 <= (others => '0');
cmp_chipscope_ila_1_ethmac_tx : chipscope_ila
port map (
CONTROL => CONTROL2,
CLK => mtx_clk_pad_i,
TRIG0 => TRIG_ILA2_0,
TRIG1 => TRIG_ILA2_1,
TRIG2 => TRIG_ILA2_2,
TRIG3 => TRIG_ILA2_3
);
TRIG_ILA2_0(5 downto 0) <= mtxd_pad_int &
mtxen_pad_int &
mtxerr_pad_int;
TRIG_ILA2_0(31 downto 6) <= (others => '0');
TRIG_ILA2_1 <= (others => '0');
TRIG_ILA2_2 <= (others => '0');
TRIG_ILA2_3 <= (others => '0');
cmp_chipscope_ila_1_ethmac_miim : chipscope_ila
port map (
CONTROL => CONTROL3,
CLK => clk_sys,
TRIG0 => TRIG_ILA3_0,
TRIG1 => TRIG_ILA3_1,
TRIG2 => TRIG_ILA3_2,
TRIG3 => TRIG_ILA3_3
);
TRIG_ILA3_0(4 downto 0) <= mdc_pad_int &
ethmac_md_in &
ethmac_md_out &
ethmac_md_oe &
ethmac_int;
TRIG_ILA3_0(31 downto 6) <= (others => '0');
TRIG_ILA3_1 <= (others => '0');
TRIG_ILA3_2 <= (others => '0');
TRIG_ILA3_3 <= (others => '0');
end rtl;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/modules/dbe_wishbone/wb_fmc150/sim/amc7823_init_mem.vhd | 1 | 5466 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file amc7823_init_mem.vhd when simulating
-- the core, amc7823_init_mem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY amc7823_init_mem IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END amc7823_init_mem;
ARCHITECTURE amc7823_init_mem_a OF amc7823_init_mem IS
-- synthesis translate_off
COMPONENT wrapped_amc7823_init_mem
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_amc7823_init_mem USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "virtex6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/sim/amc7823_init_mem.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32,
c_read_depth_b => 32,
c_read_width_a => 32,
c_read_width_b => 32,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32,
c_write_depth_b => 32,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 32,
c_write_width_b => 32,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_amc7823_init_mem
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END amc7823_init_mem_a;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_top.vhd | 1 | 20825 | --LIBRARY xtek;
-- USE xtek.XHDL_std_logic.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
--*****************************************************************************
-- (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : ui_top.v
-- /___/ /\ Date Last Modified : $date$
-- \ \ / \ Date Created : Tue Jun 30 2009
-- \___\/\___\
--
--Device : Virtex-6
--Design Name : DDR3 SDRAM
--Purpose :
--Reference :
--Revision History :
--*****************************************************************************
-- Top level of simple user interface.
ENTITY ui_top IS
GENERIC (
TCQ : INTEGER := 100;
APP_DATA_WIDTH : INTEGER := 256;
APP_MASK_WIDTH : INTEGER := 32;
BANK_WIDTH : INTEGER := 3;
COL_WIDTH : INTEGER := 12;
CWL : INTEGER := 5;
ECC : STRING := "OFF";
ECC_TEST : STRING := "OFF";
ORDERING : STRING := "NORM";
RANKS : INTEGER := 4;
RANK_WIDTH : INTEGER := 2;
ROW_WIDTH : INTEGER := 16;
MEM_ADDR_ORDER : STRING := "BANK_ROW_COLUMN"
);
PORT (
-- Outputs
-- Inputs
-- Beginning of automatic inputs (from unused autoinst inputs)
-- To ui_cmd0 of ui_cmd.v
-- To ui_cmd0 of ui_cmd.v
-- To ui_cmd0 of ui_cmd.v
-- To ui_cmd0 of ui_cmd.v
-- To ui_cmd0 of ui_cmd.v
-- To ui_wr_data0 of ui_wr_data.v
-- To ui_cmd0 of ui_cmd.v
-- To ui_wr_data0 of ui_wr_data.v
-- To ui_wr_data0 of ui_wr_data.v
-- To ui_wr_data0 of ui_wr_data.v
-- To ui_wr_data0 of ui_wr_data.v
-- To ui_cmd0 of ui_cmd.v, ...
-- To ui_rd_data0 of ui_rd_data.v
-- To ui_rd_data0 of ui_rd_data.v
-- To ui_rd_data0 of ui_rd_data.v
-- To ui_rd_data0 of ui_rd_data.v
-- To ui_rd_data0 of ui_rd_data.v
-- To ui_rd_data0 of ui_rd_data.v
-- To ui_cmd0 of ui_cmd.v, ...
-- To ui_wr_data0 of ui_wr_data.v
-- To ui_wr_data0 of ui_wr_data.v
-- To ui_wr_data0 of ui_wr_data.v
-- End of automatics
-- Beginning of automatic outputs (from unused autoinst outputs)
-- From ui_rd_data0 of ui_rd_data.v
-- From ui_rd_data0 of ui_rd_data.v
-- From ui_rd_data0 of ui_rd_data.v
-- From ui_rd_data0 of ui_rd_data.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_wr_data0 of ui_wr_data.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_wr_data0 of ui_wr_data.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_wr_data0 of ui_wr_data.v
wr_data_mask : OUT STD_LOGIC_VECTOR(APP_MASK_WIDTH - 1 DOWNTO 0); -- From ui_wr_data0 of ui_wr_data.v
wr_data : OUT STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
use_addr : OUT STD_LOGIC;
size : OUT STD_LOGIC;
row : OUT STD_LOGIC_VECTOR(ROW_WIDTH - 1 DOWNTO 0);
raw_not_ecc : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rank : OUT STD_LOGIC_VECTOR(RANK_WIDTH - 1 DOWNTO 0);
hi_priority : OUT STD_LOGIC;
data_buf_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
col : OUT STD_LOGIC_VECTOR(COL_WIDTH - 1 DOWNTO 0);
cmd : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bank : OUT STD_LOGIC_VECTOR(BANK_WIDTH - 1 DOWNTO 0);
app_wdf_rdy : OUT STD_LOGIC;
app_rdy : OUT STD_LOGIC;
app_rd_data_valid : OUT STD_LOGIC;
app_rd_data_end : OUT STD_LOGIC;
app_rd_data : OUT STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
app_ecc_multiple_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
correct_en : OUT STD_LOGIC;
wr_data_offset : IN STD_LOGIC;
wr_data_en : IN STD_LOGIC;
wr_data_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rst : IN STD_LOGIC;
rd_data_offset : IN STD_LOGIC;
rd_data_end : IN STD_LOGIC;
rd_data_en : IN STD_LOGIC;
rd_data_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data : IN STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
ecc_multiple : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
clk : IN STD_LOGIC;
app_wdf_wren : IN STD_LOGIC;
app_wdf_mask : IN STD_LOGIC_VECTOR(APP_MASK_WIDTH - 1 DOWNTO 0);
app_wdf_end : IN STD_LOGIC;
app_wdf_data : IN STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
app_sz : IN STD_LOGIC;
app_raw_not_ecc : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
app_hi_pri : IN STD_LOGIC;
app_en : IN STD_LOGIC;
app_cmd : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
app_addr : IN STD_LOGIC_VECTOR(RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH - 1 DOWNTO 0);
accept_ns : IN STD_LOGIC;
accept : IN STD_LOGIC;
app_correct_en : IN STD_LOGIC
);
END ENTITY ui_top;
ARCHITECTURE trans OF ui_top IS
constant ADDR_WIDTH :integer := RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
COMPONENT ui_cmd IS
GENERIC (
TCQ : INTEGER := 100;
ADDR_WIDTH : INTEGER := 33;
BANK_WIDTH : INTEGER := 3;
COL_WIDTH : INTEGER := 12;
RANK_WIDTH : INTEGER := 2;
ROW_WIDTH : INTEGER := 16;
RANKS : INTEGER := 4;
MEM_ADDR_ORDER : STRING := "BANK_ROW_COLUMN"
);
PORT (
app_rdy : OUT STD_LOGIC;
use_addr : OUT STD_LOGIC;
rank : OUT STD_LOGIC_VECTOR(RANK_WIDTH - 1 DOWNTO 0);
bank : OUT STD_LOGIC_VECTOR(BANK_WIDTH - 1 DOWNTO 0);
row : OUT STD_LOGIC_VECTOR(ROW_WIDTH - 1 DOWNTO 0);
col : OUT STD_LOGIC_VECTOR(COL_WIDTH - 1 DOWNTO 0);
size : OUT STD_LOGIC;
cmd : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
hi_priority : OUT STD_LOGIC;
rd_accepted : OUT STD_LOGIC;
wr_accepted : OUT STD_LOGIC;
data_buf_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
accept_ns : IN STD_LOGIC;
rd_buf_full : IN STD_LOGIC;
wr_req_16 : IN STD_LOGIC;
app_addr : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
app_cmd : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
app_sz : IN STD_LOGIC;
app_hi_pri : IN STD_LOGIC;
app_en : IN STD_LOGIC;
wr_data_buf_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_buf_addr_r : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT ui_wr_data IS
GENERIC (
TCQ : INTEGER := 100;
APP_DATA_WIDTH : INTEGER := 256;
APP_MASK_WIDTH : INTEGER := 32;
ECC : STRING := "OFF";
ECC_TEST : STRING := "OFF";
CWL : INTEGER := 5
);
PORT (
app_wdf_rdy : OUT STD_LOGIC;
wr_req_16 : OUT STD_LOGIC;
wr_data_buf_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data : OUT STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
wr_data_mask : OUT STD_LOGIC_VECTOR(APP_MASK_WIDTH - 1 DOWNTO 0);
raw_not_ecc : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
app_wdf_data : IN STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
app_wdf_mask : IN STD_LOGIC_VECTOR(APP_MASK_WIDTH - 1 DOWNTO 0);
app_raw_not_ecc : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
app_wdf_wren : IN STD_LOGIC;
app_wdf_end : IN STD_LOGIC;
wr_data_offset : IN STD_LOGIC;
wr_data_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_en : IN STD_LOGIC;
wr_accepted : IN STD_LOGIC;
ram_init_done_r : IN STD_LOGIC;
ram_init_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT ui_rd_data IS
GENERIC (
TCQ : INTEGER := 100;
APP_DATA_WIDTH : INTEGER := 256;
ECC : STRING := "OFF";
ORDERING : STRING := "NORM"
);
PORT (
ram_init_done_r : OUT STD_LOGIC;
ram_init_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
app_rd_data_valid : OUT STD_LOGIC;
app_rd_data_end : OUT STD_LOGIC;
app_rd_data : OUT STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
app_ecc_multiple_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_buf_full : OUT STD_LOGIC;
rd_data_buf_addr_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
rd_data_en : IN STD_LOGIC;
rd_data_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_offset : IN STD_LOGIC;
rd_data_end : IN STD_LOGIC;
rd_data : IN STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
ecc_multiple : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_accepted : IN STD_LOGIC
);
END COMPONENT;
-- End of automatics
-- Beginning of automatic wires (for undeclared instantiated-module outputs)
SIGNAL ram_init_addr : STD_LOGIC_VECTOR(3 DOWNTO 0); -- From ui_rd_data0 of ui_rd_data.v
SIGNAL ram_init_done_r : STD_LOGIC; -- From ui_rd_data0 of ui_rd_data.v
SIGNAL rd_accepted : STD_LOGIC; -- From ui_cmd0 of ui_cmd.v
SIGNAL rd_buf_full : STD_LOGIC; -- From ui_rd_data0 of ui_rd_data.v
SIGNAL rd_data_buf_addr_r : STD_LOGIC_VECTOR(3 DOWNTO 0); -- From ui_rd_data0 of ui_rd_data.v
SIGNAL wr_accepted : STD_LOGIC; -- From ui_cmd0 of ui_cmd.v
SIGNAL wr_data_buf_addr : STD_LOGIC_VECTOR(3 DOWNTO 0); -- From ui_wr_data0 of ui_wr_data.v
SIGNAL wr_req_16 : STD_LOGIC; -- From ui_wr_data0 of ui_wr_data.v
-- Declare intermediate signals for referenced outputs
SIGNAL wr_data_mask_xhdl17 : STD_LOGIC_VECTOR(APP_MASK_WIDTH - 1 DOWNTO 0);
SIGNAL wr_data_xhdl16 : STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
SIGNAL use_addr_xhdl15 : STD_LOGIC;
SIGNAL size_xhdl14 : STD_LOGIC;
SIGNAL row_xhdl13 : STD_LOGIC_VECTOR(ROW_WIDTH - 1 DOWNTO 0);
SIGNAL raw_not_ecc_xhdl12 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL rank_xhdl11 : STD_LOGIC_VECTOR(RANK_WIDTH - 1 DOWNTO 0);
SIGNAL hi_priority_xhdl10 : STD_LOGIC;
SIGNAL data_buf_addr_xhdl9 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL col_xhdl8 : STD_LOGIC_VECTOR(COL_WIDTH - 1 DOWNTO 0);
SIGNAL cmd_xhdl7 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bank_xhdl6 : STD_LOGIC_VECTOR(BANK_WIDTH - 1 DOWNTO 0);
SIGNAL app_wdf_rdy_xhdl5 : STD_LOGIC;
SIGNAL app_rdy_xhdl4 : STD_LOGIC;
SIGNAL app_rd_data_valid_xhdl3 : STD_LOGIC;
SIGNAL app_rd_data_end_xhdl2 : STD_LOGIC;
SIGNAL app_rd_data_xhdl1 : STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
SIGNAL app_ecc_multiple_err_xhdl0 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL rst_reg : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL rst_final : STD_LOGIC;
SIGNAL app_addr_temp : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
ATTRIBUTE max_fanout : STRING;
ATTRIBUTE max_fanout OF rst_final : SIGNAL IS "10";
BEGIN
-- Drive referenced outputs
wr_data_mask <= wr_data_mask_xhdl17;
wr_data <= wr_data_xhdl16;
use_addr <= use_addr_xhdl15;
size <= size_xhdl14;
row <= row_xhdl13;
raw_not_ecc <= raw_not_ecc_xhdl12;
rank <= rank_xhdl11;
hi_priority <= hi_priority_xhdl10;
data_buf_addr <= data_buf_addr_xhdl9;
col <= col_xhdl8;
cmd <= cmd_xhdl7;
bank <= bank_xhdl6;
app_wdf_rdy <= app_wdf_rdy_xhdl5;
app_rdy <= app_rdy_xhdl4;
app_rd_data_valid <= app_rd_data_valid_xhdl3;
app_rd_data_end <= app_rd_data_end_xhdl2;
app_rd_data <= app_rd_data_xhdl1;
app_ecc_multiple_err <= app_ecc_multiple_err_xhdl0;
correct_en <= app_correct_en;
-- End of automatics
rank_add_correction1: IF ( RANKS > 1 ) GENERATE
app_addr_temp <= app_addr;
END GENERATE;
rank_add_correction2: IF ( RANKS = 1 ) GENERATE
app_addr_temp <= ('0' & app_addr ( ADDR_WIDTH - 2 DOWNTO 0));
END GENERATE;
-- Parameters
PROCESS (clk)
BEGIN
IF ( clk'EVENT AND clk = '1') THEN
rst_reg <= (rst_reg(8 DOWNTO 0) & rst);
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF ( clk'EVENT AND clk = '1') THEN
rst_final <= rst_reg(9);
END IF;
END PROCESS;
ui_cmd0 : ui_cmd
GENERIC MAP (
TCQ => TCQ,
ADDR_WIDTH => ADDR_WIDTH,
BANK_WIDTH => BANK_WIDTH,
COL_WIDTH => COL_WIDTH,
RANK_WIDTH => RANK_WIDTH,
ROW_WIDTH => ROW_WIDTH,
RANKS => RANKS,
MEM_ADDR_ORDER => MEM_ADDR_ORDER
)
PORT MAP (
-- Outputs
app_rdy => app_rdy_xhdl4,
use_addr => use_addr_xhdl15,
rank => rank_xhdl11(RANK_WIDTH - 1 DOWNTO 0),
bank => bank_xhdl6(BANK_WIDTH - 1 DOWNTO 0),
row => row_xhdl13(ROW_WIDTH - 1 DOWNTO 0),
col => col_xhdl8(COL_WIDTH - 1 DOWNTO 0),
size => size_xhdl14,
cmd => cmd_xhdl7(2 DOWNTO 0),
hi_priority => hi_priority_xhdl10,
rd_accepted => rd_accepted,
wr_accepted => wr_accepted,
data_buf_addr => data_buf_addr_xhdl9(3 DOWNTO 0),
-- Inputs
rst => rst_final,
clk => clk,
accept_ns => accept_ns,
rd_buf_full => rd_buf_full,
wr_req_16 => wr_req_16,
app_addr => app_addr_temp(ADDR_WIDTH - 1 DOWNTO 0),
app_cmd => app_cmd(2 DOWNTO 0),
app_sz => app_sz,
app_hi_pri => app_hi_pri,
app_en => app_en,
wr_data_buf_addr => wr_data_buf_addr(3 DOWNTO 0),
rd_data_buf_addr_r => rd_data_buf_addr_r(3 DOWNTO 0)
);
-- Parameters
ui_wr_data0 : ui_wr_data
GENERIC MAP (
TCQ => TCQ,
APP_DATA_WIDTH => APP_DATA_WIDTH,
APP_MASK_WIDTH => APP_MASK_WIDTH,
ECC => ECC,
ECC_TEST => ECC_TEST,
CWL => CWL
)
PORT MAP (
-- Outputs
app_wdf_rdy => app_wdf_rdy_xhdl5,
wr_req_16 => wr_req_16,
wr_data_buf_addr => wr_data_buf_addr(3 DOWNTO 0),
wr_data => wr_data_xhdl16(APP_DATA_WIDTH - 1 DOWNTO 0),
wr_data_mask => wr_data_mask_xhdl17(APP_MASK_WIDTH - 1 DOWNTO 0),
raw_not_ecc => raw_not_ecc_xhdl12(3 DOWNTO 0),
-- Inputs
rst => rst_final,
clk => clk,
app_wdf_data => app_wdf_data(APP_DATA_WIDTH - 1 DOWNTO 0),
app_wdf_mask => app_wdf_mask(APP_MASK_WIDTH - 1 DOWNTO 0),
app_raw_not_ecc => app_raw_not_ecc(3 DOWNTO 0),
app_wdf_wren => app_wdf_wren,
app_wdf_end => app_wdf_end,
wr_data_offset => wr_data_offset,
wr_data_addr => wr_data_addr(3 DOWNTO 0),
wr_data_en => wr_data_en,
wr_accepted => wr_accepted,
ram_init_done_r => ram_init_done_r,
ram_init_addr => ram_init_addr(3 DOWNTO 0)
);
-- Parameters
ui_rd_data0 : ui_rd_data
GENERIC MAP (
TCQ => TCQ,
APP_DATA_WIDTH => APP_DATA_WIDTH,
ECC => ECC,
ORDERING => ORDERING
)
PORT MAP (
-- Outputs
ram_init_done_r => ram_init_done_r,
ram_init_addr => ram_init_addr(3 DOWNTO 0),
app_rd_data_valid => app_rd_data_valid_xhdl3,
app_rd_data_end => app_rd_data_end_xhdl2,
app_rd_data => app_rd_data_xhdl1(APP_DATA_WIDTH - 1 DOWNTO 0),
app_ecc_multiple_err => app_ecc_multiple_err_xhdl0(3 DOWNTO 0),
rd_buf_full => rd_buf_full,
rd_data_buf_addr_r => rd_data_buf_addr_r(3 DOWNTO 0),
-- Inputs
rst => rst_final,
clk => clk,
rd_data_en => rd_data_en,
rd_data_addr => rd_data_addr(3 DOWNTO 0),
rd_data_offset => rd_data_offset,
rd_data_end => rd_data_end,
rd_data => rd_data(APP_DATA_WIDTH - 1 DOWNTO 0),
ecc_multiple => ecc_multiple(3 DOWNTO 0),
rd_accepted => rd_accepted
);
END ARCHITECTURE trans;
-- ui_top
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/modules/pcie/common/rx_MRd_Channel.vhd | 1 | 20501 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: abyszuk
--
-- Design Name:
-- Module Name: rx_MRd_Transact - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.30 - Ported to AXI and OHWR general-cores components 12.2013
--
-- Revision 1.20 - Literal assignments removed. 30.07.2007
--
-- Revision 1.10 - x4 timing constraints met. 02.02.2007
--
-- Revision 1.04 - Timing improved. 17.01.2007
--
-- Revision 1.02 - FIFO added. 20.12.2006
--
-- Revision 1.00 - first release. 14.12.2006
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
use work.genram_pkg.all;
entity rx_MRd_Transact is
port (
-- Transaction receive interface
m_axis_rx_tlast : in std_logic;
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tvalid : in std_logic;
-- m_axis_rx_tready : OUT std_logic;
rx_np_ok : out std_logic;
rx_np_req : out std_logic;
m_axis_rx_tbar_hit : in std_logic_vector(C_BAR_NUMBER-1 downto 0);
sdram_pg : in std_logic_vector(31 downto 0);
wb_pg : in std_logic_vector(31 downto 0);
MRd_Type : in std_logic_vector(3 downto 0);
Tlp_straddles_4KB : in std_logic;
-- MRd Channel
pioCplD_Req : out std_logic;
pioCplD_RE : in std_logic;
pioCplD_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Channel reset (from MWr channel)
Channel_Rst : in std_logic;
-- Common ports
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic
);
end entity rx_MRd_Transact;
architecture Behavioral of rx_MRd_Transact is
type RxMRdTrnStates is (ST_MRd_RESET
, ST_MRd_IDLE
, ST_MRd_HEAD2
, ST_MRd_Tail
);
-- State variables
signal RxMRdTrn_NextState : RxMRdTrnStates;
signal RxMRdTrn_State : RxMRdTrnStates;
-- trn_rx stubs
signal trn_rsof_n_i : std_logic;
signal in_packet_reg : std_logic;
signal m_axis_rx_tdata_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tbar_hit_i : std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- delays
signal m_axis_rx_tdata_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tbar_hit_r1 : std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- BAR encoded
signal Encoded_BAR_Index : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
-- Reset
signal local_Reset : std_logic;
signal local_Reset_n : std_logic;
-- Output signals
-- signal m_axis_rx_tready_i : std_logic;
signal rx_np_ok_i : std_logic := '1';
signal rx_np_req_i : std_logic := '1';
-- Throttle
signal trn_rx_throttle : std_logic;
signal MRd_Has_3DW_Header : std_logic;
signal MRd_Has_4DW_Header : std_logic;
signal Tlp_is_Zero_Length : std_logic;
signal Illegal_Leng_on_FIFO : std_logic;
-- Signal with MRd channel FIFO
signal pioCplD_din : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_Qout_wire : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_RE_i : std_logic;
signal pioCplD_we : std_logic;
signal pioCplD_empty_i : std_logic;
signal pioCplD_full : std_logic;
signal pioCplD_prog_Full : std_logic;
signal pioCplD_prog_full_r1 : std_logic;
signal pioCplD_Qout_i : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_Qout_reg : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Request for output arbitration
signal pioCplD_Req_i : std_logic;
-- Busy/Done state bits generation
type FSM_Request is (
REQST_Idle
, REQST_1Read
, REQST_Decision
, REQST_nFIFO_Req
-- , REQST_Quantity
-- , REQST_FIFO_Req
);
signal FSM_REQ_pio : FSM_Request;
begin
-- positive reset and local
local_Reset <= user_reset or Channel_Rst;
local_reset_n <= not local_reset;
-- MRd channel buffer control
-- pioCplD_RE_i <= pioCplD_RE;
pioCplD_Qout <= pioCplD_Qout_i;
pioCplD_Req <= pioCplD_Req_i; -- and not FIFO_Reading;
-- Output to the core as handshaking
m_axis_rx_tdata_i <= m_axis_rx_tdata;
m_axis_rx_tbar_hit_i <= m_axis_rx_tbar_hit;
-- Output to the core as handshaking
rx_np_ok <= rx_np_ok_i;
rx_np_ok_i <= not pioCplD_prog_full_r1;
rx_np_req <= rx_np_req_i;
rx_np_req_i <= rx_np_ok_i;
-- ( m_axis_rx_tvalid seems never deasserted during packet)
trn_rx_throttle <= not m_axis_rx_tvalid; -- or m_axis_rx_tready_i;
-- ------------------------------------------------
-- Synchronous Delay: m_axis_rx_tdata + m_axis_rx_tbar_hit
--
Synch_Delay_m_axis_rx_tdata :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
m_axis_rx_tdata_r1 <= m_axis_rx_tdata_i;
m_axis_rx_tbar_hit_r1 <= m_axis_rx_tbar_hit_i;
end if;
end process;
-- ------------------------------------------------
-- States synchronous
--
Syn_RxTrn_States :
process (user_clk, local_Reset)
begin
if local_Reset = '1' then
RxMRdTrn_State <= ST_MRd_RESET;
elsif user_clk'event and user_clk = '1' then
RxMRdTrn_State <= RxMRdTrn_NextState;
end if;
end process;
-- Next States
Comb_RxTrn_NextStates :
process (
RxMRdTrn_State
, MRd_Type
, trn_rx_throttle
, rx_np_ok_i
)
begin
case RxMRdTrn_State is
when ST_MRd_RESET =>
RxMRdTrn_NextState <= ST_MRd_IDLE;
when ST_MRd_IDLE =>
if rx_np_ok_i = '1' then
case MRd_Type is
when C_TLP_TYPE_IS_MRD_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRD_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when others =>
RxMRdTrn_NextState <= ST_MRd_IDLE;
end case; -- MRd_Type
else
RxMRdTrn_NextState <= ST_MRd_IDLE;
end if;
when ST_MRd_HEAD2 =>
if trn_rx_throttle = '1' then
RxMRdTrn_NextState <= ST_MRd_HEAD2;
else
RxMRdTrn_NextState <= ST_MRd_Tail;
end if;
when ST_MRd_Tail => -- support back-to-back transactions
if rx_np_ok_i = '1' then
case MRd_Type is
when C_TLP_TYPE_IS_MRD_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRD_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when others =>
RxMRdTrn_NextState <= ST_MRd_IDLE;
end case; -- MRd_Type
else
RxMRdTrn_NextState <= ST_MRd_IDLE;
end if;
when others =>
RxMRdTrn_NextState <= ST_MRd_RESET;
end case;
end process;
-- ------------------------------------------------
-- Synchronous calculation: Encoded_BAR_Index
--
Syn_Calc_Encoded_BAR_Index :
process (user_clk, local_Reset)
begin
if local_Reset = '1' then
Encoded_BAR_Index <= (others => '1');
elsif user_clk'event and user_clk = '1' then
if m_axis_rx_tbar_hit(0) = '1' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(0, C_ENCODE_BAR_NUMBER);
elsif m_axis_rx_tbar_hit(1) = '1' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(1, C_ENCODE_BAR_NUMBER);
elsif m_axis_rx_tbar_hit(2) = '1' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(2, C_ENCODE_BAR_NUMBER);
elsif m_axis_rx_tbar_hit(3) = '1' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(3, C_ENCODE_BAR_NUMBER);
elsif m_axis_rx_tbar_hit(4) = '1' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(4, C_ENCODE_BAR_NUMBER);
elsif m_axis_rx_tbar_hit(5) = '1' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(5, C_ENCODE_BAR_NUMBER);
elsif m_axis_rx_tbar_hit(6) = '1' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(6, C_ENCODE_BAR_NUMBER);
else
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(7, C_ENCODE_BAR_NUMBER);
end if;
end if;
end process;
-- ----------------------------------------------------------------------------------
--
-- Synchronous output: MRd FIFO write port
--
-- PIO Channel Buffer (128-bit) definition:
-- Note: Type not shows in this buffer
--
-- 127 ~ xxx : Peripheral address
-- xxy ~ 97 : reserved
-- 96 : Zero-length
-- 95 : reserved
-- 94 : Valid
-- 93 ~ 68 : reserved
-- 67 ~ 65 : BAR number
-- 64 ~ 49 : Requester ID
-- 48 ~ 41 : Tag
-- 40 ~ 34 : Lower Address
-- 33 ~ 31 : Completion Status
-- 30 ~ 19 : Byte count
--
-- 18 ~ 17 : Format
-- 16 ~ 14 : TC
-- 13 : TD
-- 12 : EP
-- 11 ~ 10 : Attribute
-- 9 ~ 0 : Length
--
RxFSM_Output_pioCplD_WR :
process (user_clk, local_Reset)
begin
if local_Reset = '1' then
pioCplD_we <= '0';
pioCplD_din <= (others => '0');
elsif user_clk'event and user_clk = '1' then
case RxMRdTrn_State is
when ST_MRd_HEAD2 =>
pioCplD_we <= '0';
if Illegal_Leng_on_FIFO = '1' then -- Cpl : unsupported request
pioCplD_din(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT) <= C_FMT3_NO_DATA;
pioCplD_din(C_CHBUF_CPLD_CS_BIT_TOP downto C_CHBUF_CPLD_CS_BIT_BOT) <= "001";
else
pioCplD_din(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT) <= C_FMT3_WITH_DATA;
pioCplD_din(C_CHBUF_CPLD_CS_BIT_TOP downto C_CHBUF_CPLD_CS_BIT_BOT) <= "000";
end if;
pioCplD_din(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT) <= m_axis_rx_tdata_r1(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT);
pioCplD_din(C_CHBUF_TD_BIT) <= '0';
pioCplD_din(C_CHBUF_EP_BIT) <= '0';
pioCplD_din(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= m_axis_rx_tdata_r1(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT);
-- <= m_axis_rx_tdata_r1(C_TLP_ATTR_BIT_TOP) & C_NO_SNOOP; -- downto C_TLP_ATTR_BIT_BOT);
pioCplD_din(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= m_axis_rx_tdata_r1(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
pioCplD_din(C_CHBUF_QVALID_BIT) <= '1';
pioCplD_din(C_CHBUF_CPLD_REQID_BIT_TOP downto C_CHBUF_CPLD_REQID_BIT_BOT) <= m_axis_rx_tdata_r1(C_TLP_REQID_BIT_TOP downto C_TLP_REQID_BIT_BOT);
pioCplD_din(C_CHBUF_CPLD_TAG_BIT_TOP downto C_CHBUF_CPLD_TAG_BIT_BOT) <= m_axis_rx_tdata_r1(C_TLP_TAG_BIT_TOP downto C_TLP_TAG_BIT_BOT);
pioCplD_din(C_CHBUF_0LENG_BIT) <= Tlp_is_Zero_Length;
if Tlp_is_Zero_Length = '1' then
pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT) <= CONV_STD_LOGIC_VECTOR(0, C_ENCODE_BAR_NUMBER);
else
pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT) <= Encoded_BAR_Index;
end if;
when ST_MRd_Tail =>
if MRd_Has_4DW_Header = '1' then
pioCplD_din(C_CHBUF_CPLD_LA_BIT_TOP downto C_CHBUF_CPLD_LA_BIT_BOT)
<= m_axis_rx_tdata_r1(C_CHBUF_CPLD_LA_BIT_TOP-C_CHBUF_CPLD_LA_BIT_BOT+32 downto 0+32);
if m_axis_rx_tbar_hit_r1(CINT_REGS_SPACE_BAR) = '1' then
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= m_axis_rx_tdata_r1(C_CHBUF_PA_BIT_TOP-C_CHBUF_PA_BIT_BOT+32 downto 0+32);
elsif m_axis_rx_tbar_hit_r1(CINT_DDR_SPACE_BAR) = '1' then
pioCplD_din(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT)
<= sdram_pg(C_CHBUF_DDA_BIT_TOP-C_CHBUF_DDA_BIT_BOT-C_DDR_PG_WIDTH downto 0) &
m_axis_rx_tdata_r1(C_DDR_PG_WIDTH-1+32 downto 0+32);
elsif m_axis_rx_tbar_hit_r1(CINT_FIFO_SPACE_BAR) = '1' then
pioCplD_din(C_CHBUF_WB_BIT_TOP downto C_CHBUF_WB_BIT_BOT)
<= wb_pg(C_CHBUF_WB_BIT_TOP-C_CHBUF_WB_BIT_BOT-C_WB_PG_WIDTH downto 0) &
m_axis_rx_tdata_r1(C_WB_PG_WIDTH-1+32 downto 0+32);
else
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= C_ALL_ZEROS(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT);
end if;
else
pioCplD_din(C_CHBUF_CPLD_LA_BIT_TOP downto C_CHBUF_CPLD_LA_BIT_BOT)
<= m_axis_rx_tdata_r1(C_CHBUF_CPLD_LA_BIT_TOP-C_CHBUF_CPLD_LA_BIT_BOT downto 0);
if m_axis_rx_tbar_hit_r1(CINT_REGS_SPACE_BAR) = '1' then
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= m_axis_rx_tdata_r1(C_CHBUF_PA_BIT_TOP-C_CHBUF_PA_BIT_BOT downto 0);
elsif m_axis_rx_tbar_hit_r1(CINT_DDR_SPACE_BAR) = '1' then
pioCplD_din(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT)
<= sdram_pg(C_CHBUF_DDA_BIT_TOP-C_CHBUF_DDA_BIT_BOT-C_DDR_PG_WIDTH downto 0) &
m_axis_rx_tdata_r1(C_DDR_PG_WIDTH-1 downto 0);
elsif m_axis_rx_tbar_hit_r1(CINT_FIFO_SPACE_BAR) = '1' then
pioCplD_din(C_CHBUF_WB_BIT_TOP downto C_CHBUF_WB_BIT_BOT)
<= wb_pg(C_CHBUF_WB_BIT_TOP-C_CHBUF_WB_BIT_BOT-C_WB_PG_WIDTH downto 0) &
m_axis_rx_tdata_r1(C_WB_PG_WIDTH-1 downto 0);
else
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= C_ALL_ZEROS(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT);
end if;
end if;
if pioCplD_din(C_CHBUF_0LENG_BIT) = '1' then -- Zero-length
pioCplD_din(C_CHBUF_CPLD_BC_BIT_TOP downto C_CHBUF_CPLD_BC_BIT_BOT)
<= CONV_STD_LOGIC_VECTOR(1, C_CHBUF_CPLD_BC_BIT_TOP-C_CHBUF_CPLD_BC_BIT_BOT+1);
else
pioCplD_din(C_CHBUF_CPLD_BC_BIT_TOP downto C_CHBUF_CPLD_BC_BIT_BOT)
<= pioCplD_din(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) &"00";
end if;
if m_axis_rx_tbar_hit_r1(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ZEROS(CINT_BAR_SPACES-1 downto 0) then
pioCplD_we <= not Tlp_straddles_4KB; --'1';
else
pioCplD_we <= '0';
end if;
when others =>
pioCplD_we <= '0';
pioCplD_din <= pioCplD_din;
end case;
end if;
end process;
-- -----------------------------------------------------------------------
-- Capture: MRd_Has_4DW_Header
-- : Tlp_is_Zero_Length
--
Syn_Capture_MRd_Has_4DW_Header :
process (user_clk, user_reset)
begin
if user_reset = '1' then
MRd_Has_3DW_Header <= '0';
MRd_Has_4DW_Header <= '0';
Tlp_is_Zero_Length <= '0';
Illegal_Leng_on_FIFO <= '0';
elsif user_clk'event and user_clk = '1' then
if trn_rsof_n_i = '0' then
MRd_Has_3DW_Header <= not m_axis_rx_tdata_i(C_TLP_FMT_BIT_BOT) and not m_axis_rx_tdata_i(C_TLP_FMT_BIT_BOT+1);
MRd_Has_4DW_Header <= m_axis_rx_tdata_i(C_TLP_FMT_BIT_BOT) and not m_axis_rx_tdata_i(C_TLP_FMT_BIT_BOT+1);
--Tlp_is_Zero_Length <= not (m_axis_rx_tdata_i(3) or m_axis_rx_tdata_i(2) or m_axis_rx_tdata_i(1) or m_axis_rx_tdata_i(0));
if m_axis_rx_tdata(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) = C_ALL_ZEROS(C_TLP_FLD_WIDTH_OF_LENG - 1 downto 0) then
Tlp_is_Zero_Length <= '1';
else
Tlp_is_Zero_Length <= '0';
end if;
if m_axis_rx_tdata_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) /= CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
and m_axis_rx_tdata_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) /= CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG)
and m_axis_rx_tbar_hit(CINT_FIFO_SPACE_BAR) = '1'
then
Illegal_Leng_on_FIFO <= '1';
else
Illegal_Leng_on_FIFO <= '0';
end if;
else
MRd_Has_3DW_Header <= MRd_Has_3DW_Header;
MRd_Has_4DW_Header <= MRd_Has_4DW_Header;
Tlp_is_Zero_Length <= Tlp_is_Zero_Length;
Illegal_Leng_on_FIFO <= Illegal_Leng_on_FIFO;
end if;
end if;
end process;
-- -------------------------------------------------
-- MRd TLP Buffer
-- -------------------------------------------------
pioCplD_Buffer :
generic_sync_fifo
generic map (
g_data_width => 128,
g_size => 16,
g_show_ahead => false,
g_with_empty => true,
g_with_full => false,
g_with_almost_empty => false,
g_with_almost_full => true,
g_with_count => false,
g_almost_full_threshold => 12)
port map (
rst_n_i => local_Reset_n,
clk_i => user_clk,
d_i => pioCplD_din,
we_i => pioCplD_we,
q_o => pioCplD_Qout_wire,
rd_i => pioCplD_RE_i,
empty_o => pioCplD_empty_i,
full_o => pioCplD_full,
almost_empty_o => open,
almost_full_o => pioCplD_prog_Full,
count_o => open);
-- ---------------------------------------------
-- Request for arbitration
--
Synch_Req_Proc :
process (local_Reset, user_clk)
begin
if local_Reset = '1' then
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= (others => '0');
pioCplD_Qout_reg <= (others => '0');
pioCplD_Req_i <= '0';
FSM_REQ_pio <= REQST_IDLE;
elsif user_clk'event and user_clk = '1' then
case FSM_REQ_pio is
when REQST_IDLE =>
if pioCplD_empty_i = '0' then
pioCplD_RE_i <= '1';
pioCplD_Req_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
FSM_REQ_pio <= REQST_1Read;
else
pioCplD_RE_i <= '0';
pioCplD_Req_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
FSM_REQ_pio <= REQST_IDLE;
end if;
when REQST_1Read =>
pioCplD_RE_i <= '0';
pioCplD_Req_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
FSM_REQ_pio <= REQST_Decision;
when REQST_Decision =>
pioCplD_Qout_reg <= pioCplD_Qout_wire;
pioCplD_Qout_i <= pioCplD_Qout_i;
pioCplD_RE_i <= '0';
pioCplD_Req_i <= '1';
FSM_REQ_pio <= REQST_nFIFO_Req;
when REQST_nFIFO_Req =>
if pioCplD_RE = '1' then
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_reg;
pioCplD_Req_i <= '0';
FSM_REQ_pio <= REQST_IDLE;
else
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
pioCplD_Req_i <= '1';
FSM_REQ_pio <= REQST_nFIFO_Req;
end if;
when others =>
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= (others => '0');
pioCplD_Qout_reg <= (others => '0');
pioCplD_Req_i <= '0';
FSM_REQ_pio <= REQST_IDLE;
end case;
end if;
end process;
-- ---------------------------------------------
-- Delay of Empty and prog_Full
--
Synch_Delay_empty_and_full :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
pioCplD_prog_full_r1 <= pioCplD_prog_Full;
end if;
end process;
-- ---------------------------------
-- Regenerate trn_rsof_n signal as in old TRN core
--
TRN_rsof_n_make :
process (user_clk, user_reset)
begin
if user_reset = '1' then
in_packet_reg <= '0';
elsif rising_edge(user_clk) then
if (m_axis_rx_tvalid) = '1' then
in_packet_reg <= not(m_axis_rx_tlast);
end if;
end if;
end process;
trn_rsof_n_i <= not(m_axis_rx_tvalid and not(in_packet_reg));
end architecture Behavioral;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdclk_gen.vhd | 1 | 41350 | --*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: phy_rdclk_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:12 $
-- \ \ / \ Date Created: Aug 03 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Generation and distribution of capture clock. One of the forwarded
-- CK/CK# clocks to memory is fed back into the FPGA. From there it is
-- forwarded to a PLL, where it drives a BUFO, then drives multiple
-- IODELAY + BUFIO sites, one for each DQS group (capture clocks). An
-- additional IODELAY and BUFIO is driven to create the resynchronization
-- clock for capture read data into the FPGA fabric.
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_rdclk_gen.vhd,v 1.1 2011/06/02 07:18:12 mishra Exp $
--**$Date: 2011/06/02 07:18:12 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_rdclk_gen.vhd,v $
--******************************************************************************
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_rdclk_gen is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
nCK_PER_CLK : integer := 2; -- # of memory clocks per CLK
CLK_PERIOD : integer := 3333; -- Internal clock period (in ps)
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
DQS_WIDTH : integer := 1; -- # of DQS (strobe),
nDQS_COL0 : integer := 4; -- # DQS groups in I/O column #1
nDQS_COL1 : integer := 4; -- # DQS groups in I/O column #2
nDQS_COL2 : integer := 0; -- # DQS groups in I/O column #3
nDQS_COL3 : integer := 0; -- # DQS groups in I/O column #4
IODELAY_GRP : string := "IODELAY_MIG" -- May be assigned unique name
-- when mult IP cores in design
);
port (
clk_mem : in std_logic; -- Memory clock
clk : in std_logic; -- Internal (logic) half-rate clock
clk_rd_base : in std_logic; -- Base capture clock
rst : in std_logic; -- Logic reset
dlyrst_cpt : in std_logic; -- Capture clock IDELAY shared reset
dlyce_cpt : in std_logic_vector(DQS_WIDTH - 1 downto 0); -- Capture clock IDELAY enable
dlyinc_cpt : in std_logic_vector(DQS_WIDTH - 1 downto 0); -- Capture clock IDELAY inc/dec
dlyrst_rsync : in std_logic; -- Resync clock IDELAY reset
dlyce_rsync : in std_logic_vector(3 downto 0); -- Resync clock IDELAY enable
dlyinc_rsync : in std_logic_vector(3 downto 0); -- Resync clock IDELAY inc/dec
clk_cpt : out std_logic_vector(DQS_WIDTH - 1 downto 0);-- Data capture clock
clk_rsync : out std_logic_vector(3 downto 0); -- Resynchronization clock
rst_rsync : out std_logic_vector(3 downto 0); -- Resync clock domain reset
-- debug control signals
dbg_cpt_tap_cnt : out std_logic_vector(5*DQS_WIDTH-1 downto 0);-- CPT IODELAY tap count
dbg_rsync_tap_cnt : out std_logic_vector(19 downto 0) -- RSYNC IODELAY tap count
);
end phy_rdclk_gen;
architecture trans of phy_rdclk_gen is
-- # cycles after deassertion of master reset when OSERDES used to
-- forward CPT and RSYNC clocks are taken out of reset
constant RST_OSERDES_SYNC_NUM : integer := 9;
-- NOTE: All these parameters must be <= 8, otherwise, you'll need to
-- individually change the width of the respective counter
constant EN_CLK_ON_CNT : integer := 8;
constant EN_CLK_OFF_CNT : integer := 8;
constant RST_OFF_CNT : integer := 8;
constant WC_OSERDES_RST_CNT : integer := 8;
-- Calculate appropriate MMCM multiplication factor to keep VCO frequency
-- in allowable range, and at the same time as high as possible in order
-- to keep output jitter as low as possible
-- VCO frequency = CLKIN frequency * CLKFBOUT_MULT_F / DIVCLK_DIVIDE
-- NOTES:
-- 1. DIVCLK_DIVIDE can be 1 or 2 depending on the input frequency
-- and assumed speedgrade (change starting with MIG 3.3 - before
-- DIVCLK_DIVIDE was always set to 1 - this exceeded the allowable
-- PFD clock period when using a -2 part at higher than 533MHz freq.
-- 2. Period of the input clock provided by the user is assumed to
-- be = CLK_PERIOD / nCK_PER_CLK
constant CLKIN_PERIOD : integer := (CLK_PERIOD/nCK_PER_CLK);
-- Maximum skew between BUFR and BUFIO networks across 3 banks in ps.
-- Includes all skew starting from when the base clock exits read MMCM
constant CLK_CPT_SKEW_PS : integer := 200;
-- Amount to shift BUFR (in ps) by in order to accomodate all possibilites
-- of BUFIO-BUFR skew after read calibration
-- = T/2 + CLK_CPT_SKEW, where T = memory clock period
constant RSYNC_SHIFT_PS : real := real((CLK_PERIOD/nCK_PER_CLK/2) + CLK_CPT_SKEW_PS);
-- Amount to shift in RSYNC_SHIFT_PS in # of IODELAY taps. Cap at 31.
function CALC_RSYNC_SHIFT_TAPS return real is
variable return_value : real;
begin
if (((RSYNC_SHIFT_PS+(1000000.0/(REFCLK_FREQ*64.0))-1.0) /
(1000000.0/(REFCLK_FREQ*64.0))) > 31.0) then
return_value := 31.0;
else
return_value := ((RSYNC_SHIFT_PS + (1000000.0/(REFCLK_FREQ*64.0)) - 1.0)/
(1000000.0/(REFCLK_FREQ*64.0)));
end if;
return return_value;
end function;
constant RSYNC_SHIFT_TAPS : integer := integer(CALC_RSYNC_SHIFT_TAPS);
-- States for reset deassertion and clock generation state machine
type RESET_STATE_TYPE_R_STATE is ( RESET_IDLE,
RESET_PULSE_WC,
RESET_ENABLE_CLK,
RESET_DISABLE_CLK,
RESET_DEASSERT_RST,
RESET_PULSE_CLK,
RESET_DONE
);
signal clk_cpt_tmp : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal cpt_odelay : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal cpt_oserdes : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal en_clk_off_cnt_r : std_logic_vector(3 downto 0);
signal en_clk_on_cnt_r : std_logic_vector(3 downto 0);
signal en_clk_cpt_even_r : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal en_clk_cpt_odd_r : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal en_clk_rsync_even_r : std_logic_vector(3 downto 0);
signal en_clk_rsync_odd_r : std_logic_vector(3 downto 0);
signal ocbextend_cpt : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal ocbextend_cpt_r : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal ocbextend_rsync : std_logic_vector(3 downto 0);
signal ocbextend_rsync_r : std_logic_vector(3 downto 0);
signal reset_state_r : RESET_STATE_TYPE_R_STATE;
signal rsync_bufr : std_logic_vector(3 downto 0);
signal rsync_odelay : std_logic_vector(3 downto 0);
signal rsync_oserdes : std_logic_vector(3 downto 0);
signal rst_off_cnt_r : std_logic_vector(3 downto 0);
signal rst_oserdes : std_logic;
signal rst_oserdes_sync_r : std_logic_vector(RST_OSERDES_SYNC_NUM - 1 downto 0);
signal rst_rsync_pre_r : std_logic;
signal wc_oserdes_r : std_logic;
signal wc_oserdes_cnt_r : std_logic_vector(3 downto 0);
signal dlyrst_cpt_r : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal dlyrst_rsync_r : std_logic_vector(3 downto 0);
signal rst_oserdes_cpt_r : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal rst_oserdes_rsync_r : std_logic_vector(3 downto 0);
-- Declare intermediate signals for referenced outputs
signal pll_lock_xhdl1 : std_logic;
signal rst_rsync_xhdl2 : std_logic_vector(3 downto 0);
attribute IODELAY_GROUP : string;
begin
-- Drive the outputs with intermediate signals
rst_rsync <= rst_rsync_xhdl2;
-- XST attributes for local reset trees - prohibit equivalent register
-- removal to prevent "sharing" w/ other local reset trees
-- synthesis attribute shreg_extract of dlyrst_cpt_r is "no";
-- synthesis attribute equivalent_register_removal of dlyrst_cpt_r is "no"
-- synthesis attribute shreg_extract of dlyrst_rsync_r is "no";
-- synthesis attribute equivalent_register_removal of dlyrst_rsync_r is "no"
-- synthesis attribute shreg_extract of rst_oserdes_cpt_r is "no";
-- synthesis attribute equivalent_register_removal of rst_oserdes_cpt_r is "no"
-- synthesis attribute shreg_extract of rst_oserdes_rsync_r is "no";
-- synthesis attribute equivalent_register_removal of rst_oserdes_rsync_r is "no"
--***************************************************************************
-- RESET GENERATION AND SYNCHRONIZATION:
-- Reset and clock assertion must be carefully done in order to ensure that
-- the ISERDES internal CLK-divide-by-2 element of all DQ/DQS bits are phase
-- aligned prior to adjustment of individual CPT clocks. This allows us to
-- synchronize data capture to the BUFR domain using a single BUFR -
-- otherwise, if some CLK-div-by-2 clocks are 180 degrees phase shifted
-- from others, then it becomes impossible to provide meeting timing for
-- the BUFIO-BUFR capture across all bits.
-- 1. The various stages required to generate the forwarded capture and
-- resynchronization clocks (both PERF and BUFG clocks are involved)
-- 2. The need to ensure that the divide-by-2 elements in all ISERDES and
-- BUFR blocks power up in the "same state" (e.g. on the first clock
-- edge that they receive, they should drive out logic high). Otherwise
-- these clocks can be either 0 or 180 degrees out of phase, which makes
-- it hard to synchronize data going from the ISERDES CLK-div-2 domain
-- to the BUFR domain.
-- 3. On a related note, the OSERDES blocks are used to generate clocks
-- for the ISERDES and BUFR elements. Because the OSERDES OCB feature
-- is used to synchronize from the BUFG to PERF domain (and provide the
-- ability to gate these clocks), we have to account for the possibility
-- that the latency across different OCB blocks can vary (by 1 clock
-- cycle). This means that if the same control is provided to all
-- clock-forwaring OSERDES, there can be an extra clock pulse produced
-- by some OSERDES blocks compared to others - this in turn will also
-- cause the ISERDES and BUFR divide-by-2 outputs to go out of phase.
-- Therefore, the OSERDES.OCBEXTEND pins of all these clock-forwarding
-- OSERDES must be monitored. If there is a difference in the OCBEXTEND
-- values across all the OSERDES, some OSERDES must have a clock pulse
-- removed in order to ensure phase matching across all the ISERDES and
-- BUFR divide-by-2 elements
-- Reset sequence:
-- 1. Initially all resets are asserted
-- 2. Once both MMCMs lock, deassert reset for OSERDESs responsible for
-- clock forwarding for CPT and RSYNC clocks. Deassertion is
-- synchronous to clk.
-- 3. Pulse WC for the CPT and RSYNC clock OSERDESs. WC must be
-- synchronous to clk, and is initially deasserted, then pulsed
-- 8 clock cycles after OSERDES reset deassertion. Keep en_clk = 1
-- to enable the OSERDES outputs.
-- - At this point the CPT/RSYNC clocks are active
-- 4. Disable CPT and RSYNC clocks (en_clk=0). Keep rst_rsync asserted
-- - At this point the CPT/RSYNC clocks are flatlined
-- 5. Deassert rst_rsync. This is done to ensure that the divide-by-2
-- circuits in all the ISERDES and BURFs will be in the same "state"
-- when the clock is once again restored. Otherwise, if rst_rsync were
-- deasserted while the CPT clocks were active, it's not possible to
-- guarantee that the reset will be deasserted synchronously with
-- respect to the capture clock for all ISERDES.
-- 6. Observe the OCBEXTEND for each of the CPT and RSYNC OSERDES. For
-- those that have an OCBEXTEND value of 1, drive a single clock
-- pulse out prior to the next step where the clocks are permanently
-- reenabled. This will "equalize" the phases of all the ISERDES and
-- BUFR divide-by-2 elements.
-- 7. Permanently re-enable CPT and RSYNC clocks.
-- NOTES:
-- 1. May need to revisit reenabling of CPT and RSYNC clocks - may be
-- fair amount of ISI on the first few edges of the clock. Could
-- instead drive out a slower rate clock initially after re-enabling
-- the clocks.
-- 2. May need to revisit formula for positioning of RSYNC clock so that
-- a single RSYNC clock can resynchronize data for all CPT blocks. This
-- can either be a "static" calculation, or a dynamic calibration step.
--***************************************************************************
--*****************************************************************
-- Keep all logic driven by PLL performance path in reset until master
-- logic reset deasserted
--*****************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
rst_oserdes_sync_r <= (others => '1') after (TCQ)*1 ps;
else
rst_oserdes_sync_r <= std_logic_vector(unsigned(rst_oserdes_sync_r) sll 1) after (TCQ)*1 ps;
end if;
end if;
end process;
rst_oserdes <= rst_oserdes_sync_r(RST_OSERDES_SYNC_NUM - 1);
process (clk)
begin
if (clk'event and clk = '1') then
if (rst_oserdes = '1') then
en_clk_off_cnt_r <= (others => '0') after (TCQ)*1 ps;
en_clk_on_cnt_r <= (others => '0') after (TCQ)*1 ps;
en_clk_cpt_even_r <= (others => '0') after (TCQ)*1 ps;
en_clk_cpt_odd_r <= (others => '0') after (TCQ)*1 ps;
en_clk_rsync_even_r <= (others => '0') after (TCQ)*1 ps;
en_clk_rsync_odd_r <= (others => '0') after (TCQ)*1 ps;
rst_off_cnt_r <= (others => '0') after (TCQ)*1 ps;
rst_rsync_pre_r <= '1' after (TCQ)*1 ps;
reset_state_r <= RESET_IDLE after (TCQ)*1 ps;
wc_oserdes_cnt_r <= (others => '0') after (TCQ)*1 ps;
wc_oserdes_r <= '0' after (TCQ)*1 ps;
else
-- Default assignments
en_clk_cpt_even_r <= (others => '0') after (TCQ)*1 ps;
en_clk_cpt_odd_r <= (others => '0') after (TCQ)*1 ps;
en_clk_rsync_even_r <= (others => '0') after (TCQ)*1 ps;
en_clk_rsync_odd_r <= (others => '0') after (TCQ)*1 ps;
rst_rsync_pre_r <= '1' after (TCQ)*1 ps;
wc_oserdes_r <= '0' after (TCQ)*1 ps;
case reset_state_r is
-- Wait for both MMCM's to lock
when RESET_IDLE =>
wc_oserdes_cnt_r <= "0000" after (TCQ)*1 ps;
reset_state_r <= RESET_PULSE_WC after (TCQ)*1 ps;
when RESET_PULSE_WC =>
-- Pulse WC some time after reset to OSERDES is deasserted
wc_oserdes_cnt_r <= (wc_oserdes_cnt_r + '1') after (TCQ)*1 ps;
if (TO_INTEGER(unsigned(wc_oserdes_cnt_r)) = (WC_OSERDES_RST_CNT-1)) then
wc_oserdes_r <= '1' after (TCQ)*1 ps;
reset_state_r <= RESET_ENABLE_CLK after (TCQ)*1 ps;
end if;
-- Drive out a few clocks to make sure reset is recognized for
-- those circuits that require a synchronous reset
when RESET_ENABLE_CLK =>
en_clk_cpt_even_r <= (others => '1') after (TCQ)*1 ps;
en_clk_cpt_odd_r <= (others => '1') after (TCQ)*1 ps;
en_clk_rsync_even_r <= (others => '1') after (TCQ)*1 ps;
en_clk_rsync_odd_r <= (others => '1') after (TCQ)*1 ps;
en_clk_on_cnt_r <= (en_clk_on_cnt_r + '1') after (TCQ)*1 ps;
if (TO_INTEGER(unsigned(en_clk_on_cnt_r)) = (EN_CLK_ON_CNT - 1)) then
reset_state_r <= RESET_DISABLE_CLK after (TCQ)*1 ps;
end if;
-- Disable clocks in preparation for disabling reset
when RESET_DISABLE_CLK =>
en_clk_off_cnt_r <= (en_clk_off_cnt_r + '1') after (TCQ)*1 ps;
if (TO_INTEGER(unsigned(en_clk_off_cnt_r)) = (EN_CLK_OFF_CNT - 1)) then
reset_state_r <= RESET_DEASSERT_RST after (TCQ)*1 ps;
end if;
-- Deassert reset while clocks are inactive
when RESET_DEASSERT_RST =>
rst_rsync_pre_r <= '0' after (TCQ)*1 ps;
rst_off_cnt_r <= (rst_off_cnt_r + '1') after (TCQ)*1 ps;
if (TO_INTEGER(unsigned(rst_off_cnt_r)) = (RST_OFF_CNT - 1)) then
reset_state_r <= RESET_PULSE_CLK after (TCQ)*1 ps;
end if;
-- Pulse extra clock to those CPT/RSYNC OSERDES that need it
when RESET_PULSE_CLK =>
en_clk_cpt_even_r <= ocbextend_cpt_r after (TCQ)*1 ps;
en_clk_cpt_odd_r <= (others => '0') after (TCQ)*1 ps;
en_clk_rsync_even_r <= ocbextend_rsync_r after (TCQ)*1 ps;
en_clk_rsync_odd_r <= (others => '0') after (TCQ)*1 ps;
rst_rsync_pre_r <= '0' after (TCQ)*1 ps;
reset_state_r <= RESET_DONE after (TCQ)*1 ps;
-- Permanently enable clocks
when RESET_DONE =>
en_clk_cpt_even_r <= (others => '1') after (TCQ)*1 ps;
en_clk_cpt_odd_r <= (others => '1') after (TCQ)*1 ps;
en_clk_rsync_even_r <= (others => '1') after (TCQ)*1 ps;
en_clk_rsync_odd_r <= (others => '1') after (TCQ)*1 ps;
rst_rsync_pre_r <= '0' after (TCQ)*1 ps;
when others =>
end case;
end if;
end if;
end process;
--*****************************************************************
-- Reset pipelining - register reset signals to prevent large (and long)
-- fanouts during physical compilation of the design - in particular when
-- the design spans multiple I/O columns. Create one for every CPT and
-- RSYNC clock OSERDES - might be overkill (one per I/O column may be
-- enough). Note this adds a one cycle delay between when the FSM below
-- is taken out of reset, and when the OSERDES are taken out of reset -
-- this should be accounted for by the FSM logic
--*****************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
dlyrst_cpt_r <= (others => dlyrst_cpt) after TCQ*1 ps;
dlyrst_rsync_r <= (others => dlyrst_rsync) after TCQ*1 ps;
rst_oserdes_cpt_r <= (others => rst_oserdes) after TCQ*1 ps;
rst_oserdes_rsync_r <= (others => rst_oserdes) after TCQ*1 ps;
end if;
end process;
--*****************************************************************
-- Miscellaneous signals
--*****************************************************************
-- NOTE: Deassertion of RST_RSYNC does not have to be synchronous
-- w/r/t CLK_RSYNC[x] - because CLK_RSYNC[x] is inactive when
-- reset is deasserted
process (clk)
begin
if (clk'event and clk = '1') then
rst_rsync_xhdl2(0) <= rst_rsync_pre_r after (TCQ)*1 ps;
rst_rsync_xhdl2(1) <= rst_rsync_pre_r after (TCQ)*1 ps;
rst_rsync_xhdl2(2) <= rst_rsync_pre_r after (TCQ)*1 ps;
rst_rsync_xhdl2(3) <= rst_rsync_pre_r after (TCQ)*1 ps;
end if;
end process;
-- Register OCBEXTEND from CPT and RSYNC OSERDES - although these will
-- be static signals by the time they're used by the state machine
process (clk)
begin
if (clk'event and clk = '1') then
ocbextend_cpt_r <= ocbextend_cpt after (TCQ)*1 ps;
ocbextend_rsync_r <= ocbextend_rsync after (TCQ)*1 ps;
end if;
end process;
--***************************************************************************
-- Generation for each of the individual DQS group clocks. Also generate
-- resynchronization clock.
-- NOTES:
-- 1. BUFO drives OSERDES which in turn drives corresponding IODELAY
-- 2. Another mechanism may exist where BUFO drives the IODELAY input
-- combinationally (bypassing the last stage flip-flop in OSERDES)
--***************************************************************************
--*****************************************************************
-- Clock forwarding:
-- Use OSERDES to forward clock even though only basic ODDR
-- functionality is needed - use case for ODDR connected to
-- performance path may not be supported, and may later want
-- to add clock-gating capability to CPT clock to decrease
-- IODELAY loading time when switching ranks
--*****************************************************************
--*******************************************************
-- Capture clocks
--*******************************************************
gen_ck_cpt : for ck_i in 0 to DQS_WIDTH - 1 generate
attribute IODELAY_GROUP of u_odelay_cpt : label is IODELAY_GRP;
begin
u_oserdes_cpt : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0',
INIT_TQ => '0',
INTERFACE_TYPE => "MEMORY_DDR3",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => ocbextend_cpt(ck_i),
OFB => cpt_oserdes(ck_i),
OQ => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TFB => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => clk_rd_base,
CLKPERFDELAY => 'Z',
D1 => en_clk_cpt_odd_r(ck_i), -- Gating of fwd'ed clock
D2 => '0',
D3 => en_clk_cpt_even_r(ck_i), -- Gating of fwd'ed clock
D4 => '0',
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_oserdes_cpt_r(ck_i),
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
WC => wc_oserdes_r
);
u_odelay_cpt : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => TRUE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "VARIABLE",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "CLOCK"
)
port map (
DATAOUT => cpt_odelay(ck_i),
C => clk,
CE => dlyce_cpt(ck_i),
DATAIN => 'Z',
IDATAIN => 'Z',
INC => dlyinc_cpt(ck_i),
ODATAIN => cpt_oserdes(ck_i),
RST => dlyrst_cpt_r(ck_i),
T => 'Z',
CNTVALUEIN => (others => 'Z'),
CNTVALUEOUT => dbg_cpt_tap_cnt(5*ck_i+4 downto 5*ck_i),
CLKIN => 'Z',
CINVCTRL => '0'
);
u_bufio_cpt : BUFIO
port map (
i => cpt_odelay(ck_i),
o => clk_cpt_tmp(ck_i)
);
-- Use for simulation purposes only
clk_cpt(ck_i) <= clk_cpt_tmp(ck_i) after 0.1 ps;
end generate;
--*******************************************************
-- Resynchronization clock
--*******************************************************
-- I/O column #1
gen_loop_col0 : if (nDQS_COL0 > 0) generate
attribute IODELAY_GROUP of u_odelay_rsync : label is IODELAY_GRP;
begin
u_oserdes_rsync : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0',
INIT_TQ => '0',
INTERFACE_TYPE => "MEMORY_DDR3",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => ocbextend_rsync(0),
OFB => rsync_oserdes(0),
OQ => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => clk_rd_base,
CLKPERFDELAY => 'Z',
D1 => en_clk_rsync_odd_r(0), -- Gating of fwd'ed clock
D2 => '0',
D3 => en_clk_rsync_even_r(0), -- Gating of fwd'ed clock
D4 => '0',
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_oserdes_rsync_r(0),
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => wc_oserdes_r
);
u_odelay_rsync : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => TRUE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "VARIABLE",
ODELAY_VALUE => 16, -- Set at midpt for CLKDIVINV cal
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "CLOCK"
)
port map (
DATAOUT => rsync_odelay(0),
C => clk,
CE => dlyce_rsync(0),
DATAIN => 'Z',
IDATAIN => 'Z',
INC => dlyinc_rsync(0),
ODATAIN => rsync_oserdes(0),
RST => dlyrst_rsync_r(0),
T => 'Z',
CNTVALUEIN => (others => 'Z'),
CNTVALUEOUT => dbg_rsync_tap_cnt(4 downto 0),
CLKIN => 'Z',
CINVCTRL => '0'
);
u_bufr_rsync : BUFR
generic map (
bufr_divide => "2",
sim_device => "VIRTEX6"
)
port map (
i => rsync_odelay(0),
o => rsync_bufr(0),
ce => '1',
clr => rst_rsync_xhdl2(0)
);
end generate;
-- I/O column #2
gen_loop_col1 : if (nDQS_COL1 > 0) generate
attribute IODELAY_GROUP of u_odelay_rsync : label is IODELAY_GRP;
begin
u_oserdes_rsync : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0',
INIT_TQ => '0',
INTERFACE_TYPE => "MEMORY_DDR3",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => ocbextend_rsync(1),
OFB => rsync_oserdes(1),
OQ => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => clk_rd_base,
CLKPERFDELAY => 'Z',
D1 => en_clk_rsync_odd_r(1), -- Gating of fwd'ed clock
D2 => '0',
D3 => en_clk_rsync_even_r(1), -- Gating of fwd'ed clock
D4 => '0',
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_oserdes_rsync_r(1),
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => wc_oserdes_r
);
u_odelay_rsync : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => TRUE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "VARIABLE",
ODELAY_VALUE => 16, -- Set at midpt for CLKDIVINV cal
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "CLOCK"
)
port map (
DATAOUT => rsync_odelay(1),
C => clk,
CE => dlyce_rsync(1),
DATAIN => 'Z',
IDATAIN => 'Z',
INC => dlyinc_rsync(1),
ODATAIN => rsync_oserdes(1),
RST => dlyrst_rsync_r(1),
T => 'Z',
CNTVALUEIN => (others => 'Z'),
CNTVALUEOUT => dbg_rsync_tap_cnt(9 downto 5),
CLKIN => 'Z',
CINVCTRL => '0'
);
u_bufr_rsync : BUFR
generic map (
bufr_divide => "2",
sim_device => "VIRTEX6"
)
port map (
i => rsync_odelay(1),
o => rsync_bufr(1),
ce => '1',
clr => rst_rsync_xhdl2(1)
);
end generate;
-- I/O column #3
gen_loop_col2 : if (nDQS_COL2 > 0) generate
attribute IODELAY_GROUP of u_odelay_rsync : label is IODELAY_GRP;
begin
u_oserdes_rsync : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0',
INIT_TQ => '0',
INTERFACE_TYPE => "MEMORY_DDR3",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => ocbextend_rsync(2),
OFB => rsync_oserdes(2),
OQ => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => clk_rd_base,
CLKPERFDELAY => 'Z',
D1 => en_clk_rsync_odd_r(2), -- Gating of fwd'ed clock
D2 => '0',
D3 => en_clk_rsync_even_r(2), -- Gating of fwd'ed clock
D4 => '0',
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_oserdes_rsync_r(2),
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => wc_oserdes_r
);
u_odelay_rsync : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => TRUE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "VARIABLE",
ODELAY_VALUE => 16, -- Set at midpt for CLKDIVINV cal
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "CLOCK"
)
port map (
DATAOUT => rsync_odelay(2),
C => clk,
CE => dlyce_rsync(2),
DATAIN => 'Z',
IDATAIN => 'Z',
INC => dlyinc_rsync(2),
ODATAIN => rsync_oserdes(2),
RST => dlyrst_rsync_r(2),
T => 'Z',
CNTVALUEIN => (others => 'Z'),
CNTVALUEOUT => dbg_rsync_tap_cnt(14 downto 10),
CLKIN => 'Z',
CINVCTRL => '0'
);
u_bufr_rsync : BUFR
generic map (
bufr_divide => "2",
sim_device => "VIRTEX6"
)
port map (
i => rsync_odelay(2),
o => rsync_bufr(2),
ce => '1',
clr => rst_rsync_xhdl2(2)
);
end generate;
-- I/O column #4
gen_loop_col3 : if (nDQS_COL3 > 0) generate
attribute IODELAY_GROUP of u_odelay_rsync : label is IODELAY_GRP;
begin
u_oserdes_rsync : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0',
INIT_TQ => '0',
INTERFACE_TYPE => "MEMORY_DDR3",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => ocbextend_rsync(3),
OFB => rsync_oserdes(3),
OQ => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => clk_rd_base,
CLKPERFDELAY => 'Z',
D1 => en_clk_rsync_odd_r(3), -- Gating of fwd'ed clock
D2 => '0',
D3 => en_clk_rsync_even_r(3), -- Gating of fwd'ed clock
D4 => '0',
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_oserdes_rsync_r(3),
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => wc_oserdes_r
);
u_odelay_rsync : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => TRUE,
IDELAY_TYPE => "FIXED", -- See CR 511257
IDELAY_VALUE => 0, -- See CR 511257
ODELAY_TYPE => "VARIABLE",
ODELAY_VALUE => 16, -- Set at midpt for CLKDIVINV cal
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "CLOCK"
)
port map (
DATAOUT => rsync_odelay(3),
C => clk,
CE => dlyce_rsync(3),
DATAIN => 'Z',
IDATAIN => 'Z',
INC => dlyinc_rsync(3),
ODATAIN => rsync_oserdes(3),
RST => dlyrst_rsync_r(3),
T => 'Z',
CNTVALUEIN => (others => 'Z'),
CNTVALUEOUT => dbg_rsync_tap_cnt(19 downto 15),
CLKIN => 'Z',
CINVCTRL => '0'
);
u_bufr_rsync : BUFR
generic map (
bufr_divide => "2",
sim_device => "VIRTEX6"
)
port map (
i => rsync_odelay(3),
o => rsync_bufr(3),
ce => '1',
clr => rst_rsync_xhdl2(3)
);
end generate;
clk_rsync <= rsync_bufr;
end trans;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dm_iob.vhd | 1 | 23232 | --*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: phy_dm_iob.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:12 $
-- \ \ / \ Date Created: Aug 03 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- This module places the data mask signals into the IOBs.
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_dm_iob.vhd,v 1.1 2011/06/02 07:18:12 mishra Exp $
--**$Date: 2011/06/02 07:18:12 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_dm_iob.vhd,v $
--******************************************************************************
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_dm_iob is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
nCWL : integer := 5; -- CAS Write Latency
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
WRLVL : string := "ON"; -- "OFF" for "DDR3" component interface
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
IODELAY_HP_MODE : string := "ON"; -- IODELAY High Performance Mode
IODELAY_GRP : string := "IODELAY_MIG" -- May be assigned unique name
-- when mult IP cores in design
);
port (
clk_mem : in std_logic;
clk : in std_logic;
clk_rsync : in std_logic;
rst : in std_logic;
-- IODELAY I/F
dlyval : in std_logic_vector(4 downto 0);
dm_ce : in std_logic;
inv_dqs : in std_logic;
wr_calib_dly : in std_logic_vector(1 downto 0);
mask_data_rise0 : in std_logic;
mask_data_fall0 : in std_logic;
mask_data_rise1 : in std_logic;
mask_data_fall1 : in std_logic;
ddr_dm : out std_logic
);
end phy_dm_iob;
architecture trans_phy_dm_iob of phy_dm_iob is
-- Set performance mode for IODELAY (power vs. performance tradeoff)
function CALC_HIGH_PERF_MODE return boolean is
begin
if (IODELAY_HP_MODE = "OFF") then
return FALSE;
elsif (IODELAY_HP_MODE = "ON") then
return TRUE;
else
return FALSE;
end if;
end function CALC_HIGH_PERF_MODE;
constant HIGH_PERFORMANCE_MODE : boolean := CALC_HIGH_PERF_MODE;
signal dm_odelay : std_logic;
signal dm_oq : std_logic;
signal mask_data_fall0_r1 : std_logic;
signal mask_data_fall0_r2 : std_logic;
signal mask_data_fall0_r3 : std_logic;
signal mask_data_fall0_r4 : std_logic;
signal mask_data_fall1_r1 : std_logic;
signal mask_data_fall1_r2 : std_logic;
signal mask_data_fall1_r3 : std_logic;
signal mask_data_fall1_r4 : std_logic;
signal mask_data_rise0_r1 : std_logic;
signal mask_data_rise0_r2 : std_logic;
signal mask_data_rise0_r3 : std_logic;
signal mask_data_rise0_r4 : std_logic;
signal mask_data_rise1_r1 : std_logic;
signal mask_data_rise1_r2 : std_logic;
signal mask_data_rise1_r3 : std_logic;
signal mask_data_rise1_r4 : std_logic;
signal out_d1 : std_logic;
signal out_d2 : std_logic;
signal out_d3 : std_logic;
signal out_d4 : std_logic;
signal xhdl1 : std_logic_vector(2 downto 0);
attribute IODELAY_GROUP : string;
attribute IODELAY_GROUP of u_odelay_dm : label is IODELAY_GRP;
begin
-- drive xhdl1 from wr_calib_dly(1 downto 0) and inv_dqs
xhdl1 <= wr_calib_dly(1 downto 0) & inv_dqs;
--***************************************************************************
-- Data Mask Bitslip
--***************************************************************************
-- dfi_wrdata_en0 - even clk cycles channel 0
-- dfi_wrdata_en1 - odd clk cycles channel 1
-- tphy_wrlat set to 0 clk cycle for CWL = 5,6,7,8
-- Valid dfi_wrdata* sent 1 clk cycle after dfi_wrdata_en* is asserted
-- mask_data_rise0 - first rising edge data mask (rise0)
-- mask_data_fall0 - first falling edge data mask (fall0)
-- mask_data_rise1 - second rising edge data mask (rise1)
-- mask_data_fall1 - second falling edge data mask (fall1)
process (clk)
begin
if (clk'event and clk = '1') then
if (DRAM_TYPE = "DDR3") then
mask_data_rise0_r1 <= dm_ce and mask_data_rise0 after (TCQ)*1 ps;
mask_data_fall0_r1 <= dm_ce and mask_data_fall0 after (TCQ)*1 ps;
mask_data_rise1_r1 <= dm_ce and mask_data_rise1 after (TCQ)*1 ps;
mask_data_fall1_r1 <= dm_ce and mask_data_fall1 after (TCQ)*1 ps;
else
mask_data_rise0_r1 <= mask_data_rise0 after (TCQ)*1 ps;
mask_data_fall0_r1 <= mask_data_fall0 after (TCQ)*1 ps;
mask_data_rise1_r1 <= mask_data_rise1 after (TCQ)*1 ps;
mask_data_fall1_r1 <= mask_data_fall1 after (TCQ)*1 ps;
end if;
mask_data_rise0_r2 <= mask_data_rise0_r1 after (TCQ)*1 ps;
mask_data_fall0_r2 <= mask_data_fall0_r1 after (TCQ)*1 ps;
mask_data_rise1_r2 <= mask_data_rise1_r1 after (TCQ)*1 ps;
mask_data_fall1_r2 <= mask_data_fall1_r1 after (TCQ)*1 ps;
mask_data_rise0_r3 <= mask_data_rise0_r2 after (TCQ)*1 ps;
mask_data_fall0_r3 <= mask_data_fall0_r2 after (TCQ)*1 ps;
mask_data_rise1_r3 <= mask_data_rise1_r2 after (TCQ)*1 ps;
mask_data_fall1_r3 <= mask_data_fall1_r2 after (TCQ)*1 ps;
mask_data_rise0_r4 <= mask_data_rise0_r3 after (TCQ)*1 ps;
mask_data_fall0_r4 <= mask_data_fall0_r3 after (TCQ)*1 ps;
mask_data_rise1_r4 <= mask_data_rise1_r3 after (TCQ)*1 ps;
mask_data_fall1_r4 <= mask_data_fall1_r3 after (TCQ)*1 ps;
end if;
end process;
-- Different nCWL values: 5, 6, 7, 8, 9
gen_dm_ddr3_write_lat : if (DRAM_TYPE = "DDR3") generate
gen_dm_ncwl5_odd : if ((nCWL = 5) or (nCWL = 7) or (nCWL = 9)) generate
process (clk)
begin
if (clk'event and clk = '1') then
if (WRLVL = "OFF") then
out_d1 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d2 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_rise1_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_fall1_r1 after (TCQ)*1 ps;
else
-- write command sent by MC on channel1
-- D3,D4 inputs of the OCB used to send write command to DDR3
-- Shift bitslip logic by 1 or 2 clk_mem cycles
-- Write calibration currently supports only upto 2 clk_mem cycles
case (xhdl1) is
-- 0 clk_mem delay required as per write calibration
when "000" =>
out_d1 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d2 <= mask_data_rise1_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_fall1_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_rise0 after (TCQ)*1 ps;
-- DQS inverted during write leveling
when "001" =>
out_d1 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d2 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_rise1_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_fall1_r1 after (TCQ)*1 ps;
-- 1 clk_mem delay required as per write cal
when "010" =>
out_d1 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_rise1_r1 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 1 clk_mem delay required as per write cal
when "011" =>
out_d1 <= mask_data_rise1_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_fall0_r1 after (TCQ)*1 ps;
-- 2 clk_mem delay required as per write cal
when "100" =>
out_d1 <= mask_data_fall0_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_rise1_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_rise0_r1 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 2 clk_mem delay required as per write cal
when "101" =>
out_d1 <= mask_data_rise0_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_fall0_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_rise1_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_fall1_r2 after (TCQ)*1 ps;
-- 3 clk_mem delay required as per write cal
when "110" =>
out_d1 <= mask_data_fall1_r3 after (TCQ)*1 ps;
out_d2 <= mask_data_rise0_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_fall0_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_rise1_r2 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 3 clk_mem delay required as per write cal
when "111" =>
out_d1 <= mask_data_rise1_r3 after (TCQ)*1 ps;
out_d2 <= mask_data_fall1_r3 after (TCQ)*1 ps;
out_d3 <= mask_data_rise0_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_fall0_r2 after (TCQ)*1 ps;
-- defaults to 0 clk_mem delay
when others =>
out_d1 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d2 <= mask_data_rise1_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_fall1_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_rise0 after (TCQ)*1 ps;
end case;
end if;
end if;
end process;
end generate;
gen_dm_ncwl_even : if ((nCWL = 6) or (nCWL = 8)) generate
process (clk)
begin
if (clk'event and clk = '1') then
if (WRLVL = "OFF") then
out_d1 <= mask_data_rise1_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_fall0_r1 after (TCQ)*1 ps;
else
-- write command sent by MC on channel1
-- D3,D4 inputs of the OCB used to send write command to DDR3
-- Shift bitslip logic by 1 or 2 clk_mem cycles
-- Write calibration currently supports only upto 2 clk_mem cycles
case (xhdl1) is
-- 0 clk_mem delay required as per write calibration
-- could not test 0011 case
when "000" =>
out_d1 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_rise1_r1 after (TCQ)*1 ps;
-- DQS inverted during write leveling
when "001" =>
out_d1 <= mask_data_rise1_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_fall0_r1 after (TCQ)*1 ps;
-- 1 clk_mem delay required as per write cal
when "010" =>
out_d1 <= mask_data_fall0_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_rise1_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_rise0_r1 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 1 clk_mem delay required as per write cal
when "011" =>
out_d1 <= mask_data_rise0_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_fall0_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_rise1_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_fall1_r2 after (TCQ)*1 ps;
-- 2 clk_mem delay required as per write cal
when "100" =>
out_d1 <= mask_data_fall1_r3 after (TCQ)*1 ps;
out_d2 <= mask_data_rise0_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_fall0_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_rise1_r2 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 2 clk_mem delay required as per write cal
when "101" =>
out_d1 <= mask_data_rise1_r3 after (TCQ)*1 ps;
out_d2 <= mask_data_fall1_r3 after (TCQ)*1 ps;
out_d3 <= mask_data_rise0_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_fall0_r2 after (TCQ)*1 ps;
-- 3 clk_mem delay required as per write cal
when "110" =>
out_d1 <= mask_data_fall0_r3 after (TCQ)*1 ps;
out_d2 <= mask_data_rise1_r3 after (TCQ)*1 ps;
out_d3 <= mask_data_fall1_r3 after (TCQ)*1 ps;
out_d4 <= mask_data_rise0_r2 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 3 clk_mem delay required as per write cal
when "111" =>
out_d1 <= mask_data_rise0_r3 after (TCQ)*1 ps;
out_d2 <= mask_data_fall0_r3 after (TCQ)*1 ps;
out_d3 <= mask_data_rise1_r3 after (TCQ)*1 ps;
out_d4 <= mask_data_fall1_r3 after (TCQ)*1 ps;
-- defaults to 0 clk_mem delay
when others =>
out_d1 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_rise1_r1 after (TCQ)*1 ps;
end case;
end if;
end if;
end process;
end generate;
end generate;
gen_dm_lat_ddr2 : if (DRAM_TYPE = "DDR2") generate
gen_ddr2_ncwl2 : if (nCWL = 2) generate
process (mask_data_rise1_r1, mask_data_fall1_r1, mask_data_rise0, mask_data_fall0)
begin
out_d1 <= mask_data_rise1_r1;
out_d2 <= mask_data_fall1_r1;
out_d3 <= mask_data_rise0;
out_d4 <= mask_data_fall0;
end process;
end generate;
gen_ddr2_ncwl3 : if (nCWL = 3) generate
process (clk)
begin
if (clk'event and clk = '1') then
out_d1 <= mask_data_rise0 after (TCQ)*1 ps;
out_d2 <= mask_data_fall0 after (TCQ)*1 ps;
out_d3 <= mask_data_rise1 after (TCQ)*1 ps;
out_d4 <= mask_data_fall1 after (TCQ)*1 ps;
end if;
end process;
end generate;
gen_ddr2_ncwl4 : if (nCWL = 4) generate
process (clk)
begin
if (clk'event and clk = '1') then
out_d1 <= mask_data_rise1_r1 ;
out_d2 <= mask_data_fall1_r1 ;
out_d3 <= mask_data_rise0 ;
out_d4 <= mask_data_fall0 ;
end if;
end process;
end generate;
gen_ddr2_ncwl5 : if (nCWL = 5) generate
process (clk)
begin
if (clk'event and clk = '1') then
out_d1 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d2 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_rise1_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_fall1_r1 after (TCQ)*1 ps;
end if;
end process;
end generate;
gen_ddr2_ncwl6 : if (nCWL = 6) generate
process (clk)
begin
if (clk'event and clk = '1') then
out_d1 <= mask_data_rise1_r2;
out_d2 <= mask_data_fall1_r2;
out_d3 <= mask_data_rise0_r1;
out_d4 <= mask_data_fall0_r1;
end if;
end process;
end generate;
end generate;
--***************************************************************************
u_oserdes_dm : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0',
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => dm_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => out_d1,
D2 => out_d2,
D3 => out_d3,
D4 => out_d4,
D5 => 'Z',
D6 => 'Z',
OCE => '1',
ODV => '0',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
-- Output of OSERDES drives IODELAY (ODELAY)
u_odelay_dm : IODELAYE1
generic map (
cinvctrl_sel => FALSE,
delay_src => "O",
high_performance_mode => HIGH_PERFORMANCE_MODE,
idelay_type => "FIXED",
idelay_value => 0,
odelay_type => "VAR_LOADABLE",
odelay_value => 0,
refclk_frequency => REFCLK_FREQ,
signal_pattern => "DATA"
)
port map (
dataout => dm_odelay,
c => clk_rsync,
ce => '0',
datain => 'Z',
idatain => 'Z',
inc => '0',
odatain => dm_oq,
rst => '1',
t => 'Z',
cntvaluein => dlyval,
cntvalueout => open,
clkin => 'Z',
cinvctrl => '0'
);
-- Output of ODELAY drives OBUF
u_obuf_dm : OBUF
port map (
i => dm_odelay,
o => ddr_dm
);
end trans_phy_dm_iob;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/testbench/wishbone/wb_fmc516_test/vhdl/wb_fmc516_tb.vhd | 1 | 13320 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Wishbone Stream Interface
use work.wb_stream_pkg.all;
-- Register Bank
use work.fmc516_pkg.all;
entity wb_fmc516_tb is
end wb_fmc516_tb;
architecture sim of wb_fmc516_tb is
-- Constants
-- 100 MHz clock
constant c_100mhz_clk_period : time := 10.00 ns;
-- 200.00 MHz clock
constant c_200mhz_clk_period : time := 5.00 ns;
-- 250.00 MHz clock
constant c_adc_clk_period : time := 4.00 ns;
constant c_sim_time : time := 10000.00 ns;
-- Specify clock chain 1 as 4.0 ns period = 250 MHz
constant c_adc_clks_period : t_clk_values_array :=
(3 => 0.0, 2 => 0.0, 1 => 4.0, 0 => 0.0);
signal g_end_simulation : boolean := false; -- Set to true to halt the simulation
-- Clock signals
signal clk_100mhz : std_logic := '0';
signal clk_200mhz : std_logic := '0';
signal clk_sys : std_logic := '0';
signal clk_sys_n : std_logic := '1';
signal sys_rst_n : std_logic := '0';
-- Wishbone signals
signal wb_slv_in : t_wishbone_slave_in := cc_dummy_slave_in;
signal wb_slv_out : t_wishbone_slave_out;
signal wbs_src_in : t_wbs_source_in := cc_dummy_src_in;
signal wbs_src_out : t_wbs_source_out;
-- Simulation signals
signal adc_clk : std_logic := '0';
signal adc_clk_n : std_logic := '1';
signal adc_ch0_data : std_logic_vector(7 downto 0);
signal adc_ch1_data : std_logic_vector(7 downto 0);
signal adc_ch2_data : std_logic_vector(7 downto 0);
signal adc_ch3_data : std_logic_vector(7 downto 0);
--signal adc_valid : std_logic;
--------------------------------
-- Functions and Procedures
--------------------------------
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
-- Generate bit with probability of '1' equals to 'prob'
procedure gen_valid(prob : real; variable seed1, seed2 : inout positive;
signal result : out std_logic)
is
-- Random real-number value in range 0 to 1.0
variable rand: real;
begin
-- generate random number
uniform(seed1, seed2, rand);
if (rand > prob) then
result <= '1';
else
result <= '0';
end if;
end procedure;
-- Generate random std_logic_vector
procedure gen_data(size : positive; variable seed1, seed2 : inout positive;
signal result : out std_logic_vector)
is
variable rand : real; -- Random real-number value in range 0 to 1.0
variable int_rand : integer; -- Random integer value in range 0..2^(c_wbs_data_width/2)
variable stim : std_logic_vector(c_wbs_data_width-1 downto 0); -- Random c_wbs_data_width-1 bit stimulus
begin
uniform(seed1, seed2, rand); -- generate random number
int_rand := integer(trunc(rand*real(2**(c_wbs_data_width/8)))); -- rescale to 0..2^(c_wbs_data_width/8), find integer part
stim := std_logic_vector(to_unsigned(int_rand, stim'length)); -- convert to std_logic_vector
result <= stim(size-1 downto 0);
end procedure;
function toggle_bus(bus_in : std_logic_vector)
return std_logic_vector
is
variable ret : std_logic_vector(bus_in'length-1 downto 0) := (others => '0');
begin
for i in 0 to bus_in'length-1 loop
ret(i) := not bus_in(i);
end loop;
return ret;
end function;
begin -- sim
p_100mhz_clk_gen : process
begin
while g_end_simulation = false loop
wait for c_100mhz_clk_period/2;
clk_100mhz <= not clk_100mhz;
wait for c_100mhz_clk_period/2;
clk_100mhz <= not clk_100mhz;
end loop;
wait; -- simulation stops here
end process;
p_200mhz_clk_gen : process
begin
while g_end_simulation = false loop
wait for c_200mhz_clk_period/2;
clk_200mhz <= not clk_200mhz;
wait for c_200mhz_clk_period/2;
clk_200mhz <= not clk_200mhz;
end loop;
wait; -- simulation stops here
end process;
-- ADC clock gen
p_adc_clk_gen : process
begin
while g_end_simulation = false loop
wait for c_adc_clk_period/2;
adc_clk <= not adc_clk;
wait for c_adc_clk_period/2;
adc_clk <= not adc_clk;
end loop;
wait; -- simulation stops here
end process;
--p_gen_adc_valid : process
-- variable seed1, seed2: positive; -- Seed values for random generator
--begin
-- seed1 := 67632;
-- seed2 := 3234;
-- adc_valid <= '0';
-- -- Wait until reset completion (synch with adc clock domain)
-- wait until sys_rst_n = '1' and rising_edge(adc_clk);
-- l_generate_valid: loop
-- gen_valid(0.5, seed1, seed2, adc_valid);
-- wait until rising_edge(adc_clk);
-- end loop;
--end process;
p_gen_adc_data : process
variable seed1, seed2: positive; -- Seed values for random generator
begin
seed1 := 432566;
seed2 := 211;
adc_ch0_data <= (others => '0');
adc_ch1_data <= (others => '0');
adc_ch2_data <= (others => '0');
adc_ch3_data <= (others => '0');
-- Wait until reset completion (synch with adc clock domain)
wait until sys_rst_n = '1' and rising_edge(adc_clk);
l_generate_data: loop
gen_data(adc_ch0_data'length, seed1, seed2, adc_ch0_data);
gen_data(adc_ch1_data'length, seed1, seed2, adc_ch1_data);
gen_data(adc_ch2_data'length, seed1, seed2, adc_ch2_data);
gen_data(adc_ch3_data'length, seed1, seed2, adc_ch3_data);
wait until rising_edge(adc_clk);
end loop;
end process;
p_main_simulation : process
begin
-- Generate reset signal
sys_rst_n <= '0';
wait for 4*c_100mhz_clk_period;
sys_rst_n <= '1';
wait for c_sim_time;
g_end_simulation <= true;
wait;
end process;
cmp_wb_fmc516 : wb_fmc516
generic map(
--g_interface_mode : t_wishbone_interface_mode := CLASSIC;
--g_address_granularity : t_wishbone_address_granularity := WORD;
g_adc_clk_period_values => c_adc_clks_period,
g_use_clk_chains => "0001",
g_use_data_chains => "1111",
--g_packet_size : natural := 32;
g_sim => 1
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => sys_rst_n,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_adr_i => f_zeros(c_wishbone_address_width),
wb_dat_i => f_zeros(c_wishbone_data_width),
wb_dat_o => open,
wb_sel_i => f_zeros(c_wishbone_data_width/8),
wb_we_i => '0',
wb_cyc_i => '0',
wb_stb_i => '0',
wb_ack_o => open,
wb_err_o => open,
wb_rty_o => open,
wb_stall_o => open,
-----------------------------
-- External ports
-----------------------------
-- System I2C Bus. Slaves: Atmel AT24C512B Serial EEPROM,
-- AD7417 temperature diodes and AD7417 supply rails
sys_i2c_scl_b => open,
sys_i2c_sda_b => open,
-- ADC clocks. One clock per ADC channel.
-- Only ch1 clock is used as all data chains
-- are sampled at the same frequency
adc_clk0_p_i => adc_clk,
adc_clk0_n_i => adc_clk_n,
adc_clk1_p_i => adc_clk,
adc_clk1_n_i => adc_clk_n,
adc_clk2_p_i => clk_sys,
adc_clk2_n_i => clk_sys_n,
adc_clk3_p_i => clk_sys,
adc_clk3_n_i => clk_sys_n,
-- DDR ADC data channels.
adc_data_ch0_p_i => adc_ch0_data,
adc_data_ch0_n_i => toggle_bus(adc_ch0_data),
adc_data_ch1_p_i => adc_ch1_data,
adc_data_ch1_n_i => toggle_bus(adc_ch1_data),
adc_data_ch2_p_i => adc_ch2_data,
adc_data_ch2_n_i => toggle_bus(adc_ch2_data),
adc_data_ch3_p_i => adc_ch3_data,
adc_data_ch3_n_i => toggle_bus(adc_ch3_data),
-- ADC clock (half of the sampling frequency) divider reset
adc_clk_div_rst_p_o => open,
adc_clk_div_rst_n_o => open,
-- FMC Front leds. Typical uses: Over Range or Full Scale
-- condition.
fmc_leds_o => open,
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o => open,
sys_spi_data_b => open,
sys_spi_cs_adc0_n_o => open, -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o => open, -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o => open, -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o => open, -- SPI ADC CS channel 3
-- External Trigger To/From FMC
m2c_trig_p_i => '0',
m2c_trig_n_i => '0',
c2m_trig_p_o => open,
c2m_trig_n_o => open,
-- LMK (National Semiconductor) is the clock and distribution IC.
-- SPI interface?
lmk_lock_i => '0',
lmk_sync_o => open,
lmk_uwire_latch_en_o => open,
lmk_uwire_data_o => open,
lmk_uwire_clock_o => open,
-- Programable VCXO via I2C?
vcxo_i2c_sda_b => open,
vcxo_i2c_scl_o => open,
vcxo_pd_l_o => open,
-- One-wire To/From DS2431 (VMETRO Data)
fmc_id_dq_b => open,
-- One-wire To/From DS2432 SHA-1 (SP-Devices key)
fmc_key_dq_b => open,
-- General board pins
fmc_pwr_good_i => '0',
-- Internal/External clock distribution selection
fmc_clk_sel_o => open,
-- Reset ADCs
fmc_reset_adcs_n_o => open,
--FMC Present status
fmc_prsnt_m2c_l_i => '0',
-----------------------------
-- ADC output signals. Continuous flow.
-----------------------------
adc_clk_o => open,
adc_data_o => open,
adc_data_valid_o => open,
-----------------------------
-- General ADC output signals
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => open,
trig_hw_i => '0',
-- General board status
fmc_mmcm_lock_o => open,
fmc_lmk_lock_o => open,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_adr_o => open,
wbs_dat_o => open,
wbs_cyc_o => open,
wbs_stb_o => open,
wbs_we_o => open,
wbs_sel_o => open,
wbs_ack_i => (others => '0'),
wbs_stall_i => (others => '0'),
wbs_err_i => (others => '0'),
wbs_rty_i => (others => '0')
);
adc_clk_n <= not adc_clk;
clk_sys <= clk_100mhz;
clk_sys_n <= not clk_sys;
end sim;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/mbuf_128x72.vhd | 1 | 27460 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.49d
-- \ \ Application: netgen
-- / / Filename: mbuf_128x72.vhd
-- /___/ /\ Timestamp: Thu Feb 21 12:33:55 2013
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/mbuf_128x72.ngc /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/mbuf_128x72.vhd
-- Device : 7a200tffg1156-2
-- Input file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/mbuf_128x72.ngc
-- Output file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/mbuf_128x72.vhd
-- # of Entities : 2
-- Design Name : mbuf_128x72
-- Xilinx : /opt/Xilinx/14.4/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity reset_builtin1 is
port (
CLK : in STD_LOGIC := 'X';
WR_CLK : in STD_LOGIC := 'X';
RD_CLK : in STD_LOGIC := 'X';
INT_CLK : in STD_LOGIC := 'X';
RST : in STD_LOGIC := 'X';
WR_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
RD_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
INT_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end reset_builtin1;
architecture STRUCTURE of reset_builtin1 is
signal wr_rst_reg_2 : STD_LOGIC;
signal wr_rst_reg_GND_25_o_MUX_1_o : STD_LOGIC;
signal wr_rst_fb : STD_LOGIC_VECTOR ( 4 downto 0 );
signal power_on_wr_rst : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NlwRenamedSignal_RD_RST_I : STD_LOGIC_VECTOR ( 0 downto 0 );
signal NlwRenamedSig_OI_n0013 : STD_LOGIC_VECTOR ( 5 downto 5 );
begin
WR_RST_I(1) <= NlwRenamedSignal_RD_RST_I(0);
WR_RST_I(0) <= NlwRenamedSignal_RD_RST_I(0);
RD_RST_I(1) <= NlwRenamedSignal_RD_RST_I(0);
RD_RST_I(0) <= NlwRenamedSignal_RD_RST_I(0);
INT_RST_I(1) <= NlwRenamedSig_OI_n0013(5);
INT_RST_I(0) <= NlwRenamedSig_OI_n0013(5);
XST_GND : GND
port map (
G => NlwRenamedSig_OI_n0013(5)
);
power_on_wr_rst_0 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(1),
Q => power_on_wr_rst(0)
);
power_on_wr_rst_1 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(2),
Q => power_on_wr_rst(1)
);
power_on_wr_rst_2 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(3),
Q => power_on_wr_rst(2)
);
power_on_wr_rst_3 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(4),
Q => power_on_wr_rst(3)
);
power_on_wr_rst_4 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(5),
Q => power_on_wr_rst(4)
);
power_on_wr_rst_5 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => NlwRenamedSig_OI_n0013(5),
Q => power_on_wr_rst(5)
);
wr_rst_reg : FDP
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_reg_GND_25_o_MUX_1_o,
PRE => RST,
Q => wr_rst_reg_2
);
wr_rst_fb_0 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(1),
Q => wr_rst_fb(0)
);
wr_rst_fb_1 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(2),
Q => wr_rst_fb(1)
);
wr_rst_fb_2 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(3),
Q => wr_rst_fb(2)
);
wr_rst_fb_3 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(4),
Q => wr_rst_fb(3)
);
wr_rst_fb_4 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_reg_2,
Q => wr_rst_fb(4)
);
RD_RST_I_0_1 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wr_rst_reg_2,
I1 => power_on_wr_rst(0),
O => NlwRenamedSignal_RD_RST_I(0)
);
Mmux_wr_rst_reg_GND_25_o_MUX_1_o11 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => wr_rst_fb(0),
I1 => wr_rst_reg_2,
O => wr_rst_reg_GND_25_o_MUX_1_o
);
end STRUCTURE;
-- synthesis translate_on
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity mbuf_128x72 is
port (
clk : in STD_LOGIC := 'X';
rst : in STD_LOGIC := 'X';
wr_en : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
full : out STD_LOGIC;
empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 71 downto 0 );
dout : out STD_LOGIC_VECTOR ( 71 downto 0 )
);
end mbuf_128x72;
architecture STRUCTURE of mbuf_128x72 is
component reset_builtin1
port (
CLK : in STD_LOGIC := 'X';
WR_CLK : in STD_LOGIC := 'X';
RD_CLK : in STD_LOGIC := 'X';
INT_CLK : in STD_LOGIC := 'X';
RST : in STD_LOGIC := 'X';
WR_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
RD_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
INT_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component;
signal N1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q_19 : STD_LOGIC;
signal NlwRenamedSig_OI_empty : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_fifo : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_WR_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
empty <= NlwRenamedSig_OI_empty;
prog_full <= U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q_19;
XST_GND : GND
port map (
G => N1
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt : reset_builtin1
port map (
CLK => clk,
WR_CLK => N1,
RD_CLK => N1,
INT_CLK => N1,
RST => rst,
WR_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_WR_RST_I_1_UNCONNECTED,
WR_RST_I(0) => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
RD_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_1_UNCONNECTED,
RD_RST_I(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_0_UNCONNECTED,
INT_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_1_UNCONNECTED,
INT_RST_I(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1 : FIFO36E1
generic map(
ALMOST_EMPTY_OFFSET => X"0002",
ALMOST_FULL_OFFSET => X"0180",
DATA_WIDTH => 72,
DO_REG => 0,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
EN_SYN => TRUE,
FIFO_MODE => "FIFO36_72",
FIRST_WORD_FALL_THROUGH => FALSE,
INIT => X"000000000000000000",
SIM_DEVICE => "7SERIES",
SRVAL => X"000000000000000000"
)
port map (
ALMOSTEMPTY =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED
,
ALMOSTFULL => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_fifo,
DBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED,
EMPTY => NlwRenamedSig_OI_empty,
FULL => full,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
RDCLK => clk,
RDEN => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp,
RDERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED,
REGCE => N1,
RST => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
RSTREG => N1,
SBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED,
WRCLK => clk,
WREN => wr_en,
WRERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED,
DI(63) => din(67),
DI(62) => din(66),
DI(61) => din(65),
DI(60) => din(64),
DI(59) => din(63),
DI(58) => din(62),
DI(57) => din(61),
DI(56) => din(60),
DI(55) => din(59),
DI(54) => din(58),
DI(53) => din(57),
DI(52) => din(56),
DI(51) => din(55),
DI(50) => din(54),
DI(49) => din(53),
DI(48) => din(52),
DI(47) => din(51),
DI(46) => din(50),
DI(45) => din(49),
DI(44) => din(48),
DI(43) => din(47),
DI(42) => din(46),
DI(41) => din(45),
DI(40) => din(44),
DI(39) => din(43),
DI(38) => din(42),
DI(37) => din(41),
DI(36) => din(40),
DI(35) => din(39),
DI(34) => din(38),
DI(33) => din(37),
DI(32) => din(36),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(7) => din(71),
DIP(6) => din(70),
DIP(5) => din(69),
DIP(4) => din(68),
DIP(3) => din(35),
DIP(2) => din(34),
DIP(1) => din(33),
DIP(0) => din(32),
DO(63) => dout(67),
DO(62) => dout(66),
DO(61) => dout(65),
DO(60) => dout(64),
DO(59) => dout(63),
DO(58) => dout(62),
DO(57) => dout(61),
DO(56) => dout(60),
DO(55) => dout(59),
DO(54) => dout(58),
DO(53) => dout(57),
DO(52) => dout(56),
DO(51) => dout(55),
DO(50) => dout(54),
DO(49) => dout(53),
DO(48) => dout(52),
DO(47) => dout(51),
DO(46) => dout(50),
DO(45) => dout(49),
DO(44) => dout(48),
DO(43) => dout(47),
DO(42) => dout(46),
DO(41) => dout(45),
DO(40) => dout(44),
DO(39) => dout(43),
DO(38) => dout(42),
DO(37) => dout(41),
DO(36) => dout(40),
DO(35) => dout(39),
DO(34) => dout(38),
DO(33) => dout(37),
DO(32) => dout(36),
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(7) => dout(71),
DOP(6) => dout(70),
DOP(5) => dout(69),
DOP(4) => dout(68),
DOP(3) => dout(35),
DOP(2) => dout(34),
DOP(1) => dout(33),
DOP(0) => dout(32),
ECCPARITY(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED
,
RDCOUNT(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED
,
RDCOUNT(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED
,
RDCOUNT(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED
,
RDCOUNT(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED
,
RDCOUNT(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED
,
RDCOUNT(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED
,
RDCOUNT(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED
,
RDCOUNT(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED
,
RDCOUNT(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED
,
RDCOUNT(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED
,
RDCOUNT(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED
,
RDCOUNT(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED
,
RDCOUNT(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED
,
WRCOUNT(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED
,
WRCOUNT(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED
,
WRCOUNT(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED
,
WRCOUNT(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED
,
WRCOUNT(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED
,
WRCOUNT(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED
,
WRCOUNT(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED
,
WRCOUNT(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED
,
WRCOUNT(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED
,
WRCOUNT(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED
,
WRCOUNT(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED
,
WRCOUNT(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED
,
WRCOUNT(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_fifo,
Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q_19
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_empty,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp
);
end STRUCTURE;
-- synthesis translate_on
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/modules/pcie/common/rx_Transact.vhd | 1 | 42351 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: rx_Transact - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.20 - Memory space repartitioned. 13.07.2007
--
-- Revision 1.10 - x4 timing constraints met. 02.02.2007
--
-- Revision 1.04 - Timing improved. 17.01.2007
--
-- Revision 1.02 - FIFO added. 20.12.2006
--
-- Revision 1.00 - first release. 14.12.2006
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
entity rx_Transact is
port (
-- Common ports
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic;
-- Transaction receive interface
m_axis_rx_tlast : in std_logic;
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tvalid : in std_logic;
m_axis_rx_tready : out std_logic;
rx_np_ok : out std_logic;
rx_np_req : out std_logic;
m_axis_rx_tbar_hit : in std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
-- PIO MRd Channel
pioCplD_Req : out std_logic;
pioCplD_RE : in std_logic;
pioCplD_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- downstream MRd Channel
dsMRd_Req : out std_logic;
dsMRd_RE : in std_logic;
dsMRd_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- upstream MWr/MRd Channel
usTlp_Req : out std_logic;
usTlp_RE : in std_logic;
usTlp_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
us_FC_stop : in std_logic;
us_Last_sof : in std_logic;
us_Last_eof : in std_logic;
-- Irpt Channel
Irpt_Req : out std_logic;
Irpt_RE : in std_logic;
Irpt_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- SDRAM and Wishbone pages
sdram_pg : in std_logic_vector(31 downto 0);
wb_pg : in std_logic_vector(31 downto 0);
-- Interrupt Interface
cfg_interrupt : out std_logic;
cfg_interrupt_rdy : in std_logic;
cfg_interrupt_mmenable : in std_logic_vector(2 downto 0);
cfg_interrupt_msienable : in std_logic;
cfg_interrupt_msixenable : in std_logic;
cfg_interrupt_msixfm : in std_logic;
cfg_interrupt_di : out std_logic_vector(7 downto 0);
cfg_interrupt_do : in std_logic_vector(7 downto 0);
cfg_interrupt_assert : out std_logic;
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add : out std_logic;
ds_DMA_Bytes : out std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- --------------------------
-- Registers
DMA_ds_PA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_HA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_BDA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Length : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Control : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
dsDMA_BDA_eq_Null : in std_logic;
DMA_ds_Status : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Done : out std_logic;
DMA_ds_Busy : out std_logic;
DMA_ds_Tout : out std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b : in std_logic;
dsBDA_is_64b : in std_logic;
-- Calculation in advance, for better timing
dsLeng_Hi19b_True : in std_logic;
dsLeng_Lo7b_True : in std_logic;
--
dsDMA_Start : in std_logic;
dsDMA_Stop : in std_logic;
dsDMA_Start2 : in std_logic;
dsDMA_Stop2 : in std_logic;
dsDMA_Channel_Rst : in std_logic;
dsDMA_Cmd_Ack : out std_logic;
--
DMA_us_PA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_HA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_BDA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Length : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Control : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
usDMA_BDA_eq_Null : in std_logic;
us_MWr_Param_Vec : in std_logic_vector(6-1 downto 0);
DMA_us_Status : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Done : out std_logic;
DMA_us_Busy : out std_logic;
DMA_us_Tout : out std_logic;
-- Calculation in advance, for better timing
usHA_is_64b : in std_logic;
usBDA_is_64b : in std_logic;
-- Calculation in advance, for better timing
usLeng_Hi19b_True : in std_logic;
usLeng_Lo7b_True : in std_logic;
--
usDMA_Start : in std_logic;
usDMA_Stop : in std_logic;
usDMA_Start2 : in std_logic;
usDMA_Stop2 : in std_logic;
usDMA_Channel_Rst : in std_logic;
usDMA_Cmd_Ack : out std_logic;
MRd_Channel_Rst : in std_logic;
-- to Interrupt module
Sys_IRQ : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Event Buffer write port
wb_FIFO_we : out std_logic;
wb_FIFO_wsof : out std_logic;
wb_FIFO_weof : out std_logic;
wb_FIFO_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_FIFO_full : in std_logic;
wb_FIFO_Empty : in std_logic;
wb_FIFO_Reading : in std_logic;
-- Registers Write Port
Regs_WrEn0 : out std_logic;
Regs_WrMask0 : out std_logic_vector(2-1 downto 0);
Regs_WrAddr0 : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin0 : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_WrEn1 : out std_logic;
Regs_WrMask1 : out std_logic_vector(2-1 downto 0);
Regs_WrAddr1 : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin1 : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR write port
DDR_wr_sof_A : out std_logic;
DDR_wr_eof_A : out std_logic;
DDR_wr_v_A : out std_logic;
DDR_wr_Shift_A : out std_logic;
DDR_wr_Mask_A : out std_logic_vector(2-1 downto 0);
DDR_wr_din_A : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_sof_B : out std_logic;
DDR_wr_eof_B : out std_logic;
DDR_wr_v_B : out std_logic;
DDR_wr_Shift_B : out std_logic;
DDR_wr_Mask_B : out std_logic_vector(2-1 downto 0);
DDR_wr_din_B : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : in std_logic;
-- Interrupt generator signals
IG_Reset : in std_logic;
IG_Host_Clear : in std_logic;
IG_Latency : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Assert : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Deassert : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting : out std_logic;
-- Additional
cfg_dcommand : in std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
localID : in std_logic_vector(C_ID_WIDTH-1 downto 0)
);
end entity rx_Transact;
architecture Behavioral of rx_Transact is
signal wb_FIFO_we_i : std_logic;
signal wb_FIFO_wsof_i : std_logic;
signal wb_FIFO_weof_i : std_logic;
signal wb_FIFO_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
------------------------------------------------------------------
-- Rx input delay
-- some calculation in advance, to achieve better timing
--
component
RxIn_Delay
port (
-- Common ports
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic;
-- Transaction receive interface
m_axis_rx_tlast : in std_logic;
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tvalid : in std_logic;
m_axis_rx_tbar_hit : in std_logic_vector(C_BAR_NUMBER-1 downto 0);
m_axis_rx_tready : out std_logic;
Pool_wrBuf_full : in std_logic;
wb_FIFO_full : in std_logic;
-- Delayed
m_axis_rx_tlast_dly : out std_logic;
m_axis_rx_tdata_dly : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep_dly : out std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd_dly : out std_logic;
m_axis_rx_tvalid_dly : out std_logic;
m_axis_rx_tready_dly : out std_logic;
m_axis_rx_tbar_hit_dly : out std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- TLP resolution
MRd_Type : out std_logic_vector(3 downto 0);
MWr_Type : out std_logic_vector(1 downto 0);
CplD_Type : out std_logic_vector(3 downto 0);
-- From Cpl/D channel
usDMA_dex_Tag : in std_logic_vector(C_TAG_WIDTH-1 downto 0);
dsDMA_dex_Tag : in std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- To Memory request process modules
Tlp_straddles_4KB : out std_logic;
-- To Cpl/D channel
Tlp_has_4KB : out std_logic;
Tlp_has_1DW : out std_logic;
CplD_is_the_Last : out std_logic;
CplD_on_Pool : out std_logic;
CplD_on_EB : out std_logic;
Req_ID_Match : out std_logic;
usDex_Tag_Matched : out std_logic;
dsDex_Tag_Matched : out std_logic;
CplD_Tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Additional
cfg_dcommand : in std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
localID : in std_logic_vector(C_ID_WIDTH-1 downto 0)
);
end component;
-- One clock delayed
signal m_axis_rx_tlast_dly : std_logic;
signal m_axis_rx_tdata_dly : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tkeep_dly : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal m_axis_rx_terrfwd_dly : std_logic;
signal m_axis_rx_tvalid_dly : std_logic;
signal m_axis_rx_tready_dly : std_logic;
signal m_axis_rx_tbar_hit_dly : std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- TLP types
signal MRd_Type : std_logic_vector(3 downto 0);
signal MWr_Type : std_logic_vector(1 downto 0);
signal CplD_Type : std_logic_vector(3 downto 0);
signal Tlp_straddles_4KB : std_logic;
-- To Cpl/D channel
signal Tlp_has_4KB : std_logic;
signal Tlp_has_1DW : std_logic;
signal CplD_is_the_Last : std_logic;
signal CplD_on_Pool : std_logic;
signal CplD_on_EB : std_logic;
signal Req_ID_Match : std_logic;
signal usDex_Tag_Matched : std_logic;
signal dsDex_Tag_Matched : std_logic;
signal CplD_Tag : std_logic_vector(C_TAG_WIDTH-1 downto 0);
------------------------------------------------------------------
-- MRd TLP processing
-- contains channel buffer for PIO Completions
--
component
rx_MRd_Transact
port(
m_axis_rx_tlast : in std_logic;
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
-- m_axis_rx_tready : OUT std_logic;
rx_np_ok : out std_logic; -----------------
rx_np_req : out std_logic;
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tvalid : in std_logic;
m_axis_rx_tbar_hit : in std_logic_vector(C_BAR_NUMBER-1 downto 0);
sdram_pg : in std_logic_vector(31 downto 0);
wb_pg : in std_logic_vector(31 downto 0);
MRd_Type : in std_logic_vector(3 downto 0);
Tlp_straddles_4KB : in std_logic;
pioCplD_RE : in std_logic;
pioCplD_Req : out std_logic;
pioCplD_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
Channel_Rst : in std_logic;
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic
);
end component;
------------------------------------------------------------------
-- MWr TLP processing
--
component
rx_MWr_Transact
port(
--
m_axis_rx_tlast : in std_logic;
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_tready : in std_logic; -- !!
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tvalid : in std_logic;
m_axis_rx_tbar_hit : in std_logic_vector(C_BAR_NUMBER-1 downto 0);
sdram_pg : in std_logic_vector(31 downto 0);
wb_pg : in std_logic_vector(31 downto 0);
MWr_Type : in std_logic_vector(1 downto 0);
Tlp_has_4KB : in std_logic;
-- Event Buffer write port
wb_FIFO_we : out std_logic;
wb_FIFO_wsof : out std_logic;
wb_FIFO_weof : out std_logic;
wb_FIFO_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Registers Write Port
Regs_WrEn : out std_logic;
Regs_WrMask : out std_logic_vector(2-1 downto 0);
Regs_WrAddr : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR write port
DDR_wr_sof : out std_logic;
DDR_wr_eof : out std_logic;
DDR_wr_v : out std_logic;
DDR_wr_Shift : out std_logic;
DDR_wr_Mask : out std_logic_vector(2-1 downto 0);
DDR_wr_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : in std_logic;
-- Common
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic
);
end component;
signal wb_FIFO_we_MWr : std_logic;
signal wb_FIFO_wsof_MWr : std_logic;
signal wb_FIFO_weof_MWr : std_logic;
signal wb_FIFO_din_MWr : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
------------------------------------------------------------------
-- Cpl/D TLP processing
--
component
rx_CplD_Transact
port(
m_axis_rx_tlast : in std_logic;
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_tready : in std_logic;
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tvalid : in std_logic;
m_axis_rx_tbar_hit : in std_logic_vector(C_BAR_NUMBER-1 downto 0);
CplD_Type : in std_logic_vector(3 downto 0);
Req_ID_Match : in std_logic;
usDex_Tag_Matched : in std_logic;
dsDex_Tag_Matched : in std_logic;
Tlp_has_4KB : in std_logic;
Tlp_has_1DW : in std_logic;
CplD_is_the_Last : in std_logic;
CplD_on_Pool : in std_logic;
CplD_on_EB : in std_logic;
CplD_Tag : in std_logic_vector(C_TAG_WIDTH-1 downto 0);
FC_pop : out std_logic;
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add : out std_logic;
ds_DMA_Bytes : out std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- for descriptor of the downstream DMA
dsDMA_Dex_Tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Downstream Handshake Signals with ds Channel for Busy/Done
Tag_Map_Clear : out std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
-- Downstream tRAM port A write request
tRAM_weB : in std_logic;
tRAM_addrB : in std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_dinB : in std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-- for descriptor of the upstream DMA
usDMA_dex_Tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Event Buffer write port
wb_FIFO_we : out std_logic;
wb_FIFO_wsof : out std_logic;
wb_FIFO_weof : out std_logic;
wb_FIFO_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Registers Write Port
Regs_WrEn : out std_logic;
Regs_WrMask : out std_logic_vector(2-1 downto 0);
Regs_WrAddr : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR write port
DDR_wr_sof : out std_logic;
DDR_wr_eof : out std_logic;
DDR_wr_v : out std_logic;
DDR_wr_Shift : out std_logic;
DDR_wr_Mask : out std_logic_vector(2-1 downto 0);
DDR_wr_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : in std_logic;
-- Common signals
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic
);
end component;
signal wb_FIFO_we_CplD : std_logic;
signal wb_FIFO_wsof_CplD : std_logic;
signal wb_FIFO_weof_CplD : std_logic;
signal wb_FIFO_din_CplD : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal usDMA_dex_Tag : std_logic_vector(C_TAG_WIDTH-1 downto 0);
signal dsDMA_dex_Tag : std_logic_vector(C_TAG_WIDTH-1 downto 0);
signal Tag_Map_Clear : std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
signal FC_pop : std_logic;
------------------------------------------------------------------
-- Interrupts generation
--
component
Interrupts
port(
Sys_IRQ : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt generator signals
IG_Reset : in std_logic;
IG_Host_Clear : in std_logic;
IG_Latency : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Assert : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Deassert : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting : out std_logic;
-- cfg interface
cfg_interrupt : out std_logic;
cfg_interrupt_rdy : in std_logic;
cfg_interrupt_mmenable : in std_logic_vector(2 downto 0);
cfg_interrupt_msienable : in std_logic;
cfg_interrupt_msixenable : in std_logic;
cfg_interrupt_msixfm : in std_logic;
cfg_interrupt_di : out std_logic_vector(7 downto 0);
cfg_interrupt_do : in std_logic_vector(7 downto 0);
cfg_interrupt_assert : out std_logic;
-- Irpt Channel
Irpt_Req : out std_logic;
Irpt_RE : in std_logic;
Irpt_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
user_clk : in std_logic;
user_reset : in std_logic
);
end component;
------------------------------------------------------------------
-- Upstream DMA Channel
-- contains channel buffer for upstream DMA
--
component
usDMA_Transact
port(
-- command buffer
usTlp_Req : out std_logic;
usTlp_RE : in std_logic;
usTlp_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
FIFO_Reading : in std_logic;
-- Upstream DMA Control Signals from MWr Channel
usDMA_Start : in std_logic;
usDMA_Stop : in std_logic;
usDMA_Channel_Rst : in std_logic;
us_FC_stop : in std_logic;
us_Last_sof : in std_logic;
us_Last_eof : in std_logic;
--- Upstream registers from CplD channel
DMA_us_PA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_HA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_BDA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Length : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Control : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
usDMA_BDA_eq_Null : in std_logic;
us_MWr_Param_Vec : in std_logic_vector(6-1 downto 0);
-- Calculation in advance, for better timing
usHA_is_64b : in std_logic;
usBDA_is_64b : in std_logic;
-- Calculation in advance, for better timing
usLeng_Hi19b_True : in std_logic;
usLeng_Lo7b_True : in std_logic;
--- Upstream commands from CplD channel
usDMA_Start2 : in std_logic;
usDMA_Stop2 : in std_logic;
-- DMA Acknowledge to the start command
DMA_Cmd_Ack : out std_logic;
--- Tag for descriptor
usDMA_dex_Tag : in std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- To Interrupt module
DMA_Done : out std_logic;
DMA_TimeOut : out std_logic;
DMA_Busy : out std_logic;
-- To Tx channel
DMA_us_Status : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
cfg_dcommand : in std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
-- common
user_clk : in std_logic
);
end component;
------------------------------------------------------------------
-- Downstream DMA Channel
-- contains channel buffer for downstream DMA
--
component
dsDMA_Transact
port(
-- command buffer
MRd_dsp_RE : in std_logic;
MRd_dsp_Req : out std_logic;
MRd_dsp_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Downstream tRAM port A write request, to CplD channel
tRAM_weB : out std_logic;
tRAM_addrB : out std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_dinB : out std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-- Downstream Registers from MWr Channel
DMA_ds_PA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_HA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_BDA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Length : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Control : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
dsDMA_BDA_eq_Null : in std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b : in std_logic;
dsBDA_is_64b : in std_logic;
-- Calculation in advance, for better timing
dsLeng_Hi19b_True : in std_logic;
dsLeng_Lo7b_True : in std_logic;
-- Downstream Control Signals from MWr Channel
dsDMA_Start : in std_logic;
dsDMA_Stop : in std_logic;
-- DMA Acknowledge to the start command
DMA_Cmd_Ack : out std_logic;
dsDMA_Channel_Rst : in std_logic;
-- Downstream Control Signals from CplD Channel, out of consecutive dex
dsDMA_Start2 : in std_logic;
dsDMA_Stop2 : in std_logic;
-- Downstream Handshake Signals with CplD Channel for Busy/Done
Tag_Map_Clear : in std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
FC_pop : in std_logic;
-- Tag for descriptor
dsDMA_dex_Tag : in std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- To Interrupt module
DMA_Done : out std_logic;
DMA_TimeOut : out std_logic;
DMA_Busy : out std_logic;
-- To Cpl/D channel
DMA_ds_Status : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
cfg_dcommand : in std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
-- common
user_clk : in std_logic
);
end component;
-- tag RAM port A write request
signal tRAM_weB : std_logic;
signal tRAM_addrB : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
signal tRAM_dinB : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
begin
wb_FIFO_we <= wb_FIFO_we_i;
wb_FIFO_wsof <= wb_FIFO_wsof_i;
wb_FIFO_weof <= wb_FIFO_weof_i;
wb_FIFO_din <= wb_FIFO_din_i;
wb_FIFO_we_i <= wb_FIFO_we_MWr or wb_FIFO_we_CplD;
wb_FIFO_wsof_i <= wb_FIFO_wsof_CplD when wb_FIFO_we_CplD = '1' else wb_FIFO_wsof_MWr;
wb_FIFO_weof_i <= wb_FIFO_weof_CplD when wb_FIFO_we_CplD = '1' else wb_FIFO_weof_MWr;
wb_FIFO_din_i <= wb_FIFO_din_CplD when wb_FIFO_we_CplD = '1' else wb_FIFO_din_MWr;
-- ------------------------------------------------
-- Delay of Rx inputs
-- ------------------------------------------------
Rx_Input_Delays :
RxIn_Delay
port map(
-- Common ports
user_clk => user_clk , -- IN std_logic;
user_reset => user_reset , -- IN std_logic;
user_lnk_up => user_lnk_up , -- IN std_logic;
-- Transaction receive interface
m_axis_rx_tlast => m_axis_rx_tlast , -- IN std_logic;
m_axis_rx_tdata => m_axis_rx_tdata , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep => m_axis_rx_tkeep , -- IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd => m_axis_rx_terrfwd , -- IN std_logic;
m_axis_rx_tvalid => m_axis_rx_tvalid , -- IN std_logic;
m_axis_rx_tbar_hit => m_axis_rx_tbar_hit , -- IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
m_axis_rx_tready => m_axis_rx_tready , -- OUT std_logic;
Pool_wrBuf_full => DDR_wr_full , -- IN std_logic;
wb_FIFO_full => wb_FIFO_full , -- IN std_logic;
-- Delayed
m_axis_rx_tlast_dly => m_axis_rx_tlast_dly , -- OUT std_logic;
m_axis_rx_tdata_dly => m_axis_rx_tdata_dly , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep_dly => m_axis_rx_tkeep_dly , -- OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd_dly => m_axis_rx_terrfwd_dly , -- OUT std_logic;
m_axis_rx_tvalid_dly => m_axis_rx_tvalid_dly, -- OUT std_logic;
m_axis_rx_tready_dly => m_axis_rx_tready_dly, -- OUT std_logic;
m_axis_rx_tbar_hit_dly => m_axis_rx_tbar_hit_dly, -- OUT std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- TLP resolution
MRd_Type => MRd_Type , -- OUT std_logic_vector(3 downto 0);
MWr_Type => MWr_Type , -- OUT std_logic_vector(1 downto 0);
CplD_Type => CplD_Type , -- OUT std_logic_vector(3 downto 0);
-- From Cpl/D channel
usDMA_dex_Tag => usDMA_dex_Tag , -- IN std_logic_vector(7 downto 0);
dsDMA_dex_Tag => dsDMA_dex_Tag , -- IN std_logic_vector(7 downto 0);
-- To Memory request process modules
Tlp_straddles_4KB => Tlp_straddles_4KB , -- OUT std_logic;
-- To Cpl/D channel
Tlp_has_4KB => Tlp_has_4KB , -- OUT std_logic;
Tlp_has_1DW => Tlp_has_1DW , -- OUT std_logic;
CplD_is_the_Last => CplD_is_the_Last , -- OUT std_logic;
CplD_on_Pool => CplD_on_Pool , -- OUT std_logic;
CplD_on_EB => CplD_on_EB , -- OUT std_logic;
Req_ID_Match => Req_ID_Match , -- OUT std_logic;
usDex_Tag_Matched => usDex_Tag_Matched , -- OUT std_logic;
dsDex_Tag_Matched => dsDex_Tag_Matched , -- OUT std_logic;
CplD_Tag => CplD_Tag , -- OUT std_logic_vector(7 downto 0);
-- Additional
cfg_dcommand => cfg_dcommand , -- IN std_logic_vector(16-1 downto 0)
localID => localID -- IN std_logic_vector(15 downto 0)
);
-- ------------------------------------------------
-- Processing MRd Requests
-- ------------------------------------------------
MRd_Channel :
rx_MRd_Transact
port map(
--
m_axis_rx_tlast => m_axis_rx_tlast_dly, -- IN std_logic;
m_axis_rx_tdata => m_axis_rx_tdata_dly, -- IN std_logic_vector(31 downto 0);
m_axis_rx_tkeep => m_axis_rx_tkeep_dly, -- IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd => m_axis_rx_terrfwd_dly, -- IN std_logic;
m_axis_rx_tvalid => m_axis_rx_tvalid_dly, -- IN std_logic;
m_axis_rx_tbar_hit => m_axis_rx_tbar_hit_dly, -- IN std_logic_vector(6 downto 0);
-- m_axis_rx_tready => open, -- m_axis_rx_tready_MRd, -- OUT std_logic;
rx_np_ok => rx_np_ok, -- OUT std_logic;
rx_np_req => rx_np_req, -- out std_logic;
sdram_pg => sdram_pg,
wb_pg => wb_pg,
MRd_Type => MRd_Type , -- IN std_logic_vector(3 downto 0);
Tlp_straddles_4KB => Tlp_straddles_4KB , -- IN std_logic;
pioCplD_RE => pioCplD_RE, -- IN std_logic;
pioCplD_Req => pioCplD_Req, -- OUT std_logic;
pioCplD_Qout => pioCplD_Qout, -- OUT std_logic_vector(127 downto 0);
Channel_Rst => MRd_Channel_Rst, -- IN std_logic;
user_clk => user_clk, -- IN std_logic;
user_reset => user_reset, -- IN std_logic;
user_lnk_up => user_lnk_up -- IN std_logic;
);
-- ------------------------------------------------
-- Processing MWr Requests
-- ------------------------------------------------
MWr_Channel :
rx_MWr_Transact
port map(
--
m_axis_rx_tlast => m_axis_rx_tlast_dly, -- IN std_logic;
m_axis_rx_tdata => m_axis_rx_tdata_dly, -- IN std_logic_vector(31 downto 0);
m_axis_rx_tkeep => m_axis_rx_tkeep_dly, -- IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd => m_axis_rx_terrfwd_dly , -- IN std_logic;
m_axis_rx_tvalid => m_axis_rx_tvalid_dly, -- IN std_logic;
m_axis_rx_tready => m_axis_rx_tready_dly, -- IN std_logic;
m_axis_rx_tbar_hit => m_axis_rx_tbar_hit_dly, -- IN std_logic_vector(6 downto 0);
sdram_pg => sdram_pg,
wb_pg => wb_pg,
MWr_Type => MWr_Type , -- IN std_logic_vector(1 downto 0);
Tlp_has_4KB => Tlp_has_4KB , -- IN std_logic;
-- Event Buffer write port
wb_FIFO_we => wb_FIFO_we_MWr , -- OUT std_logic;
wb_FIFO_wsof => wb_FIFO_wsof_MWr , -- OUT std_logic;
wb_FIFO_weof => wb_FIFO_weof_MWr , -- OUT std_logic;
wb_FIFO_din => wb_FIFO_din_MWr , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- To registers module
Regs_WrEn => Regs_WrEn0 , -- OUT std_logic;
Regs_WrMask => Regs_WrMask0 , -- OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr => Regs_WrAddr0 , -- OUT std_logic_vector(16-1 downto 0);
Regs_WrDin => Regs_WrDin0 , -- OUT std_logic_vector(32-1 downto 0);
-- DDR write port
DDR_wr_sof => DDR_wr_sof_A , -- OUT std_logic;
DDR_wr_eof => DDR_wr_eof_A , -- OUT std_logic;
DDR_wr_v => DDR_wr_v_A , -- OUT std_logic;
DDR_wr_Shift => DDR_wr_Shift_A , -- OUT std_logic;
DDR_wr_din => DDR_wr_din_A , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_Mask => DDR_wr_Mask_A , -- OUT std_logic_vector(2-1 downto 0);
DDR_wr_full => DDR_wr_full , -- IN std_logic;
-- Common
user_clk => user_clk , -- IN std_logic;
user_reset => user_reset , -- IN std_logic;
user_lnk_up => user_lnk_up -- IN std_logic;
);
-- ---------------------------------------------------
-- Processing Completions
-- ---------------------------------------------------
CplD_Channel :
rx_CplD_Transact
port map(
--
m_axis_rx_tlast => m_axis_rx_tlast_dly, -- IN std_logic;
m_axis_rx_tdata => m_axis_rx_tdata_dly, -- IN std_logic_vector(31 downto 0);
m_axis_rx_tkeep => m_axis_rx_tkeep_dly, -- IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd => m_axis_rx_terrfwd_dly, -- IN std_logic;
m_axis_rx_tvalid => m_axis_rx_tvalid_dly, -- IN std_logic;
m_axis_rx_tready => m_axis_rx_tready_dly, -- IN std_logic;
m_axis_rx_tbar_hit => m_axis_rx_tbar_hit_dly, -- IN std_logic_vector(6 downto 0);
CplD_Type => CplD_Type, -- IN std_logic_vector(3 downto 0);
Req_ID_Match => Req_ID_Match, -- IN std_logic;
usDex_Tag_Matched => usDex_Tag_Matched, -- IN std_logic;
dsDex_Tag_Matched => dsDex_Tag_Matched, -- IN std_logic;
Tlp_has_4KB => Tlp_has_4KB , -- IN std_logic;
Tlp_has_1DW => Tlp_has_1DW , -- IN std_logic;
CplD_is_the_Last => CplD_is_the_Last, -- IN std_logic;
CplD_on_Pool => CplD_on_Pool , -- IN std_logic;
CplD_on_EB => CplD_on_EB , -- IN std_logic;
CplD_Tag => CplD_Tag, -- IN std_logic_vector( 7 downto 0);
FC_pop => FC_pop, -- OUT std_logic;
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add => ds_DMA_Bytes_Add, -- OUT std_logic;
ds_DMA_Bytes => ds_DMA_Bytes , -- OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Downstream tRAM port A write request
tRAM_weB => tRAM_weB, -- IN std_logic;
tRAM_addrB => tRAM_addrB, -- IN std_logic_vector( 6 downto 0);
tRAM_dinB => tRAM_dinB, -- IN std_logic_vector(47 downto 0);
-- Downstream channel descriptor tag
dsDMA_dex_Tag => dsDMA_dex_Tag, -- OUT std_logic_vector( 7 downto 0);
-- Downstream Tag Map Signal for Busy/Done
Tag_Map_Clear => Tag_Map_Clear, -- OUT std_logic_vector(127 downto 0);
-- Upstream channel descriptor tag
usDMA_dex_Tag => usDMA_dex_Tag, -- OUT std_logic_vector( 7 downto 0);
-- Event Buffer write port
wb_FIFO_we => wb_FIFO_we_CplD , -- OUT std_logic;
wb_FIFO_wsof => wb_FIFO_wsof_CplD , -- OUT std_logic;
wb_FIFO_weof => wb_FIFO_weof_CplD , -- OUT std_logic;
wb_FIFO_din => wb_FIFO_din_CplD , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- To registers module
Regs_WrEn => Regs_WrEn1, -- OUT std_logic;
Regs_WrMask => Regs_WrMask1, -- OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr => Regs_WrAddr1, -- OUT std_logic_vector(16-1 downto 0);
Regs_WrDin => Regs_WrDin1, -- OUT std_logic_vector(32-1 downto 0);
-- DDR write port
DDR_wr_sof => DDR_wr_sof_B , -- OUT std_logic;
DDR_wr_eof => DDR_wr_eof_B , -- OUT std_logic;
DDR_wr_v => DDR_wr_v_B , -- OUT std_logic;
DDR_wr_Shift => DDR_wr_Shift_B , -- OUT std_logic;
DDR_wr_Mask => DDR_wr_Mask_B , -- OUT std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din_B , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- IN std_logic;
-- Common
user_clk => user_clk, -- IN std_logic;
user_reset => user_reset, -- IN std_logic;
user_lnk_up => user_lnk_up -- IN std_logic;
);
-- ------------------------------------------------
-- Processing upstream DMA Requests
-- ------------------------------------------------
Upstream_DMA_Engine :
usDMA_Transact
port map(
-- TLP buffer
usTlp_RE => usTlp_RE, -- IN std_logic;
usTlp_Req => usTlp_Req, -- OUT std_logic;
usTlp_Qout => usTlp_Qout, -- OUT std_logic_vector(127 downto 0)
FIFO_Reading => wb_FIFO_Reading, -- IN std_logic;
-- upstream Control Signals from MWr Channel
usDMA_Start => usDMA_Start, -- IN std_logic;
usDMA_Stop => usDMA_Stop, -- IN std_logic;
-- Upstream Control Signals from CplD Channel
usDMA_Start2 => usDMA_Start2, -- IN std_logic;
usDMA_Stop2 => usDMA_Stop2, -- IN std_logic;
DMA_Cmd_Ack => usDMA_Cmd_Ack, -- OUT std_logic;
usDMA_Channel_Rst => usDMA_Channel_Rst, -- IN std_logic;
us_FC_stop => us_FC_stop, -- IN std_logic;
us_Last_sof => us_Last_sof, -- IN std_logic;
us_Last_eof => us_Last_eof, -- IN std_logic;
-- To Interrupt module
DMA_Done => DMA_us_Done, -- OUT std_logic;
DMA_TimeOut => DMA_us_Tout, -- OUT std_logic;
DMA_Busy => DMA_us_Busy, -- OUT std_logic;
-- To Tx channel
DMA_us_Status => DMA_us_Status, -- OUT std_logic_vector(31 downto 0);
-- upstream Registers
DMA_us_PA => DMA_us_PA, -- IN std_logic_vector(63 downto 0);
DMA_us_HA => DMA_us_HA, -- IN std_logic_vector(63 downto 0);
DMA_us_BDA => DMA_us_BDA, -- IN std_logic_vector(63 downto 0);
DMA_us_Length => DMA_us_Length, -- IN std_logic_vector(31 downto 0);
DMA_us_Control => DMA_us_Control, -- IN std_logic_vector(31 downto 0);
usDMA_BDA_eq_Null => usDMA_BDA_eq_Null, -- IN std_logic;
us_MWr_Param_Vec => us_MWr_Param_Vec, -- IN std_logic_vector(5 downto 0);
-- Calculation in advance, for better timing
usHA_is_64b => usHA_is_64b , -- IN std_logic;
usBDA_is_64b => usBDA_is_64b , -- IN std_logic;
usLeng_Hi19b_True => usLeng_Hi19b_True , -- IN std_logic;
usLeng_Lo7b_True => usLeng_Lo7b_True , -- IN std_logic;
usDMA_dex_Tag => usDMA_dex_Tag , -- OUT std_logic_vector( 7 downto 0);
cfg_dcommand => cfg_dcommand , -- IN std_logic_vector(16-1 downto 0)
user_clk => user_clk -- IN std_logic;
);
-- ------------------------------------------------
-- Processing downstream DMA Requests
-- ------------------------------------------------
Downstream_DMA_Engine :
dsDMA_Transact
port map(
-- Downstream tRAM port A write request
tRAM_weB => tRAM_weB, -- OUT std_logic;
tRAM_addrB => tRAM_addrB, -- OUT std_logic_vector( 6 downto 0);
tRAM_dinB => tRAM_dinB, -- OUT std_logic_vector(47 downto 0);
-- TLP buffer
MRd_dsp_RE => dsMRd_RE, -- IN std_logic;
MRd_dsp_Req => dsMRd_Req, -- OUT std_logic;
MRd_dsp_Qout => dsMRd_Qout, -- OUT std_logic_vector(127 downto 0);
-- Downstream Registers
DMA_ds_PA => DMA_ds_PA, -- IN std_logic_vector(63 downto 0);
DMA_ds_HA => DMA_ds_HA, -- IN std_logic_vector(63 downto 0);
DMA_ds_BDA => DMA_ds_BDA, -- IN std_logic_vector(63 downto 0);
DMA_ds_Length => DMA_ds_Length, -- IN std_logic_vector(31 downto 0);
DMA_ds_Control => DMA_ds_Control, -- IN std_logic_vector(31 downto 0);
dsDMA_BDA_eq_Null => dsDMA_BDA_eq_Null, -- IN std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b => dsHA_is_64b , -- IN std_logic;
dsBDA_is_64b => dsBDA_is_64b , -- IN std_logic;
dsLeng_Hi19b_True => dsLeng_Hi19b_True , -- IN std_logic;
dsLeng_Lo7b_True => dsLeng_Lo7b_True , -- IN std_logic;
-- Downstream Control Signals from MWr Channel
dsDMA_Start => dsDMA_Start, -- IN std_logic;
dsDMA_Stop => dsDMA_Stop, -- IN std_logic;
-- Downstream Control Signals from CplD Channel
dsDMA_Start2 => dsDMA_Start2, -- IN std_logic;
dsDMA_Stop2 => dsDMA_Stop2, -- IN std_logic;
DMA_Cmd_Ack => dsDMA_Cmd_Ack, -- OUT std_logic;
dsDMA_Channel_Rst => dsDMA_Channel_Rst, -- IN std_logic;
-- Downstream Handshake Signals with CplD Channel for Busy/Done
Tag_Map_Clear => Tag_Map_Clear, -- IN std_logic_vector(127 downto 0);
FC_pop => FC_pop, -- IN std_logic;
-- To Interrupt module
DMA_Done => DMA_ds_Done, -- OUT std_logic;
DMA_TimeOut => DMA_ds_Tout, -- OUT std_logic;
DMA_Busy => DMA_ds_Busy, -- OUT std_logic;
-- To Tx channel
DMA_ds_Status => DMA_ds_Status, -- OUT std_logic_vector(31 downto 0);
-- tag for descriptor
dsDMA_dex_Tag => dsDMA_dex_Tag, -- IN std_logic_vector( 7 downto 0);
-- Additional
cfg_dcommand => cfg_dcommand , -- IN std_logic_vector(16-1 downto 0)
-- common
user_clk => user_clk -- IN std_logic;
);
-- ------------------------------------------------
-- Interrupts generation
-- ------------------------------------------------
Intrpt_Handle :
Interrupts
port map(
Sys_IRQ => Sys_IRQ , -- IN std_logic_vector(31 downto 0);
-- Interrupt generator signals
IG_Reset => IG_Reset , -- IN std_logic;
IG_Host_Clear => IG_Host_Clear , -- IN std_logic;
IG_Latency => IG_Latency , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Assert => IG_Num_Assert , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Deassert => IG_Num_Deassert , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting => IG_Asserting , -- OUT std_logic;
-- cfg interface
cfg_interrupt => cfg_interrupt , -- OUT std_logic;
cfg_interrupt_rdy => cfg_interrupt_rdy , -- IN std_logic;
cfg_interrupt_mmenable => cfg_interrupt_mmenable , -- IN std_logic_vector(2 downto 0);
cfg_interrupt_msienable => cfg_interrupt_msienable , -- IN std_logic;
cfg_interrupt_msixenable => cfg_interrupt_msixenable ,
cfg_interrupt_msixfm => cfg_interrupt_msixfm ,
cfg_interrupt_di => cfg_interrupt_di , -- OUT std_logic_vector(7 downto 0);
cfg_interrupt_do => cfg_interrupt_do , -- IN std_logic_vector(7 downto 0);
cfg_interrupt_assert => cfg_interrupt_assert , -- OUT std_logic;
-- Irpt Channel
Irpt_Req => Irpt_Req , -- OUT std_logic;
Irpt_RE => Irpt_RE , -- IN std_logic;
Irpt_Qout => Irpt_Qout , -- OUT std_logic_vector(127 downto 0);
user_clk => user_clk , -- IN std_logic;
user_reset => user_reset -- IN std_logic
);
end architecture Behavioral;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/modules/pcie/common/bram_DDRs_Control_Loopback.vhd | 1 | 40642 | ----------------------------------------------------------------------------------
-- Company: ZITI
-- Engineer: wgao
--
-- Create Date: 12:29:46 04/15/2008
-- Design Name:
-- Module Name: bram_DDRs_Control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bram_DDRs_Control_loopback is
generic (
C_ASYNFIFO_WIDTH : integer := 72;
P_SIMULATION : boolean := true
);
port (
-- -- Pins
-- DDR_CLKn : OUT std_logic;
-- DDR_CLK : OUT std_logic;
-- DDR_CKE : OUT std_logic;
-- DDR_CSn : OUT std_logic;
-- DDR_RASn : OUT std_logic;
-- DDR_CASn : OUT std_logic;
-- DDR_WEn : OUT std_logic;
-- DDR_BankAddr : OUT std_logic_vector(C_DDR_BANK_AWIDTH-1 downto 0);
-- DDR_Addr : OUT std_logic_vector(C_DDR_AWIDTH-1 downto 0);
-- DDR_DM : OUT std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
-- DDR_DQ : INOUT std_logic_vector(C_DDR_DWIDTH-1 downto 0);
-- DDR_DQS : INOUT std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
-- DMA interface
DDR_wr_sof : in std_logic;
DDR_wr_eof : in std_logic;
DDR_wr_v : in std_logic;
DDR_wr_FA : in std_logic;
DDR_wr_Shift : in std_logic;
DDR_wr_Mask : in std_logic_vector(2-1 downto 0);
DDR_wr_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : out std_logic;
DDR_rdc_sof : in std_logic;
DDR_rdc_eof : in std_logic;
DDR_rdc_v : in std_logic;
DDR_rdc_FA : in std_logic;
DDR_rdc_Shift : in std_logic;
DDR_rdc_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : out std_logic;
-- DDR_rdD_sof : OUT std_logic;
-- DDR_rdD_eof : OUT std_logic;
-- DDR_rdDout_V : OUT std_logic;
-- DDR_rdDout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : in std_logic;
DDR_FIFO_Empty : out std_logic;
DDR_FIFO_RdQout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready : out std_logic;
DDR_blinker : out std_logic;
Sim_Zeichen : out std_logic;
mem_clk : in std_logic;
user_clk : in std_logic;
user_reset : in std_logic
);
end entity bram_DDRs_Control_loopback;
architecture Behavioral of bram_DDRs_Control_loopback is
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
component DDR_ClkGen
port(
ddr_Clock : out std_logic;
ddr_Clock_n : out std_logic;
ddr_Clock90 : out std_logic;
ddr_Clock90_n : out std_logic;
Clk_ddr_rddata : out std_logic;
Clk_ddr_rddata_n : out std_logic;
ddr_DCM_locked : out std_logic;
clk_in : in std_logic;
user_reset : in std_logic
);
end component;
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
component asyn_rw_FIFO72
-- GENERIC (
-- OUTPUT_REGISTERED : BOOLEAN
-- );
port(
wClk : in std_logic;
wEn : in std_logic;
Din : in std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
aFull : out std_logic;
Full : out std_logic;
rClk : in std_logic;
rEn : in std_logic;
Qout : out std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
aEmpty : out std_logic;
Empty : out std_logic;
Rst : in std_logic
);
end component;
component prime_FIFO_plain
port (
wr_clk : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
full : out std_logic;
prog_full : out std_logic;
rd_clk : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
empty : out std_logic;
rst : in std_logic
);
end component;
-- component fifo_512x36_v4_2
-- port (
-- wr_clk : IN std_logic;
-- wr_en : IN std_logic;
-- din : IN std_logic_VECTOR(35 downto 0);
-- prog_full : OUT std_logic;
-- full : OUT std_logic;
--
-- rd_clk : IN std_logic;
-- rd_en : IN std_logic;
-- dout : OUT std_logic_VECTOR(35 downto 0);
-- prog_empty : OUT std_logic;
-- empty : OUT std_logic;
--
-- rst : IN std_logic
-- );
-- end component;
component fifo_512x72_v4_4
port (
wr_clk : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
prog_full : out std_logic;
full : out std_logic;
rd_clk : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- prog_empty : OUT std_logic;
empty : out std_logic;
rst : in std_logic
);
end component;
---- Dual-port block RAM for packets
--- Core output registered
--
-- component v5bram4096x32
-- port (
-- clka : IN std_logic;
-- addra : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
-- wea : IN std_logic_vector(0 downto 0);
-- dina : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- douta : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
--
-- clkb : IN std_logic;
-- addrb : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
-- web : IN std_logic_vector(0 downto 0);
-- dinb : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- doutb : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
-- );
-- end component;
component bram_x64
port (
clka : in std_logic;
addra : in std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
wea : in std_logic_vector(7 downto 0);
dina : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
douta : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
web : in std_logic_vector(7 downto 0);
dinb : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
doutb : out std_logic_vector(C_DBUS_WIDTH-1 downto 0)
);
end component;
-- Blinking -_-_-_-_-_-_-_-_-_-_-_-_-_-_-
component DDR_Blink
port(
DDR_Blinker : out std_logic;
DDR_Write : in std_logic;
DDR_Read : in std_logic;
DDR_Both : in std_logic;
ddr_Clock : in std_logic;
DDr_Rst_n : in std_logic
);
end component;
-- ---------------------------------------------------------------------
signal ddr_DCM_locked : std_logic;
-- -- ---------------------------------------------------------------------
signal Rst_i : std_logic;
-- -- ---------------------------------------------------------------------
signal DDR_Ready_i : std_logic;
-- -- ---------------------------------------------------------------------
signal ddr_Clock : std_logic;
signal ddr_Clock_n : std_logic;
signal ddr_Clock90 : std_logic;
signal ddr_Clock90_n : std_logic;
signal Clk_ddr_rddata : std_logic;
signal Clk_ddr_rddata_n : std_logic;
-- -- -- Write Pipe Channel
signal wpipe_wEn : std_logic;
signal wpipe_Din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
signal wpipe_aFull : std_logic;
signal wpipe_Full : std_logic;
-- Earlier calculate for better timing
signal DDR_wr_Cross_Row : std_logic;
signal DDR_wr_din_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_write_ALC : std_logic_vector(11-1 downto 0);
signal wpipe_rEn : std_logic;
signal wpipe_Qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- signal wpipe_aEmpty : std_logic;
signal wpipe_Empty : std_logic;
signal wpipe_Qout_latch : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- -- -- Read Pipe Command Channel
signal rpipec_wEn : std_logic;
signal rpipec_Din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
signal rpipec_aFull : std_logic;
signal rpipec_Full : std_logic;
-- Earlier calculate for better timing
signal DDR_rd_Cross_Row : std_logic;
signal DDR_rdc_din_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_read_ALC : std_logic_vector(11-1 downto 0);
signal rpipec_rEn : std_logic;
signal rpipec_Qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- signal rpipec_aEmpty : std_logic;
signal rpipec_Empty : std_logic;
-- -- -- Read Pipe Data Channel
signal rpiped_wEn : std_logic;
signal rpiped_Din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
signal rpiped_aFull : std_logic;
signal rpiped_Full : std_logic;
-- signal rpiped_rEn : std_logic;
signal rpiped_Qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- signal rpiped_aEmpty : std_logic;
-- signal rpiped_Empty : std_logic;
-- write State machine
type bram_wrStates is (wrST_bram_RESET
, wrST_bram_IDLE
-- , wrST_bram_Address
, wrST_bram_1st_Data
, wrST_bram_1st_Data_b2b
, wrST_bram_more_Data
, wrST_bram_last_DW
);
-- State variables
signal pseudo_DDR_wr_State : bram_wrStates;
-- Block RAM
signal pRAM_weA : std_logic_vector(7 downto 0);
signal pRAM_addrA : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
signal pRAM_dinA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_doutA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_weB : std_logic_vector(7 downto 0);
signal pRAM_addrB : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
signal pRAM_dinB : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_doutB : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_doutB_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_doutB_shifted : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wpipe_qout_lo32b : std_logic_vector(33-1 downto 0);
signal wpipe_QW_Aligned : std_logic;
signal pRAM_AddrA_Inc : std_logic;
signal wpipe_read_valid : std_logic;
-- read State machine
type bram_rdStates is (rdST_bram_RESET
, rdST_bram_IDLE
, rdST_bram_b4_LA
, rdST_bram_LA
-- , rdST_bram_b4_Length
-- , rdST_bram_Length
-- , rdST_bram_b4_Address
-- , rdST_bram_Address
, rdST_bram_Data
-- , rdST_bram_Data_shift
);
-- State variables
signal pseudo_DDR_rd_State : bram_rdStates;
signal rpiped_rd_counter : std_logic_vector(10-1 downto 0);
signal rpiped_wEn_b3 : std_logic;
signal rpiped_wEn_b2 : std_logic;
signal rpiped_wEn_b1 : std_logic;
signal rpiped_wr_EOF : std_logic;
signal rpipec_read_valid : std_logic;
signal rpiped_wr_skew : std_logic;
signal rpiped_wr_postpone : std_logic;
signal simone_debug : std_logic;
begin
Rst_i <= user_reset;
DDR_Ready <= DDR_Ready_i;
pRAM_doutB_shifted <= pRAM_doutB_r1(32-1 downto 0) & pRAM_doutB(64-1 downto 32);
-- Delay
Syn_Shifting_pRAM_doutB :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
pRAM_doutB_r1 <= pRAM_doutB;
end if;
end process;
-- -----------------------------------------------
--
Syn_DDR_CKE :
process (user_clk, Rst_i)
begin
if Rst_i = '1' then
DDR_Ready_i <= '0';
elsif user_clk'event and user_clk = '1' then
DDR_Ready_i <= '1'; -- ddr_DCM_locked;
end if;
end process;
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_Clock_Generator:
-- DDR_ClkGen
-- PORT MAP(
-- ddr_Clock => ddr_Clock , -- OUT std_logic;
-- ddr_Clock_n => ddr_Clock_n , -- OUT std_logic;
-- ddr_Clock90 => ddr_Clock90 , -- OUT std_logic;
-- ddr_Clock90_n => ddr_Clock90_n , -- OUT std_logic;
-- Clk_ddr_rddata => Clk_ddr_rddata , -- OUT std_logic;
-- Clk_ddr_rddata_n => Clk_ddr_rddata_n , -- OUT std_logic;
-- ddr_DCM_locked => ddr_DCM_locked , -- OUT std_logic;
--
-- clk_in => mem_clk , -- IN std_logic;
-- user_reset => user_reset -- IN std_logic
-- );
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_pipe_write_fifo:
-- asyn_rw_FIFO
-- GENERIC MAP (
-- OUTPUT_REGISTERED => TRUE
-- )
-- PORT MAP(
-- wClk => user_clk ,
-- wEn => wpipe_wEn ,
-- Din => wpipe_Din ,
-- aFull => wpipe_aFull ,
-- Full => wpipe_Full ,
--
-- rClk => ddr_Clock , -- ddr_Clock_n ,
-- rEn => wpipe_rEn ,
-- Qout => wpipe_Qout ,
-- aEmpty => wpipe_aEmpty ,
-- Empty => wpipe_Empty ,
--
-- Rst => Rst_i
-- );
-- DDR_pipe_write_fifo:
-- asyn_rw_FIFO72
-- PORT MAP(
-- wClk => user_clk ,
-- wEn => wpipe_wEn ,
-- Din => wpipe_Din ,
-- aFull => wpipe_aFull ,
-- Full => open ,
--
-- rClk => ddr_Clock ,
-- rEn => wpipe_rEn ,
-- Qout => wpipe_Qout ,
-- aEmpty => open ,
-- Empty => wpipe_Empty ,
--
-- Rst => Rst_i
-- );
DDR_pipe_write_fifo :
prime_fifo_plain
port map(
wr_clk => user_clk , -- IN std_logic;
wr_en => wpipe_wEn , -- IN std_logic;
din => wpipe_Din , -- IN std_logic_VECTOR(35 downto 0);
prog_full => wpipe_aFull , -- OUT std_logic;
full => wpipe_Full , -- OUT std_logic;
rd_clk => user_clk , -- IN std_logic;
rd_en => wpipe_rEn , -- IN std_logic;
dout => wpipe_Qout , -- OUT std_logic_VECTOR(35 downto 0);
empty => wpipe_Empty , -- OUT std_logic;
rst => Rst_i -- IN std_logic
);
wpipe_wEn <= DDR_wr_v;
wpipe_Din <= DDR_wr_Mask & DDR_wr_Shift & '0' & DDR_wr_sof & DDR_wr_eof & DDR_wr_Cross_Row & DDR_wr_FA & DDR_wr_din;
DDR_wr_full <= wpipe_aFull;
Sim_Zeichen <= simone_debug; --S wpipe_Empty;
Syn_DDR_wrD_Cross_Row :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
DDR_wr_din_r1(64-1 downto 10) <= (others => '0');
DDR_wr_din_r1(9 downto 0) <= DDR_wr_din(9 downto 0) - "100";
end if;
end process;
DDR_write_ALC <= (DDR_wr_din_r1(10 downto 2) &"00") + ('0' & DDR_wr_din(9 downto 2) &"00");
DDR_wr_Cross_Row <= '0'; -- DDR_write_ALC(10);
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_pipe_read_C_fifo:
-- asyn_rw_FIFO
-- GENERIC MAP (
-- OUTPUT_REGISTERED => TRUE
-- )
-- PORT MAP(
-- wClk => user_clk ,
-- wEn => rpipec_wEn ,
-- Din => rpipec_Din ,
-- aFull => rpipec_aFull ,
-- Full => rpipec_Full ,
--
-- rClk => ddr_Clock , -- ddr_Clock_n ,
-- rEn => rpipec_rEn ,
-- Qout => rpipec_Qout ,
-- aEmpty => rpipec_aEmpty ,
-- Empty => rpipec_Empty ,
--
-- Rst => Rst_i
-- );
--
-- DDR_pipe_read_C_fifo:
-- asyn_rw_FIFO72
-- PORT MAP(
-- wClk => user_clk ,
-- wEn => rpipec_wEn ,
-- Din => rpipec_Din ,
-- aFull => rpipec_aFull ,
-- Full => open ,
--
-- rClk => ddr_Clock ,
-- rEn => rpipec_rEn ,
-- Qout => rpipec_Qout ,
-- aEmpty => open ,
-- Empty => rpipec_Empty ,
--
-- Rst => Rst_i
-- );
DDR_pipe_read_C_fifo :
prime_fifo_plain
port map(
wr_clk => user_clk , -- IN std_logic;
wr_en => rpipec_wEn , -- IN std_logic;
din => rpipec_Din , -- IN std_logic_VECTOR(35 downto 0);
prog_full => rpipec_aFull , -- OUT std_logic;
full => open, --rpipec_Full , -- OUT std_logic;
rd_clk => user_clk , -- IN std_logic;
rd_en => rpipec_rEn , -- IN std_logic;
dout => rpipec_Qout , -- OUT std_logic_VECTOR(35 downto 0);
empty => rpipec_Empty , -- OUT std_logic;
rst => Rst_i -- IN std_logic
);
rpipec_wEn <= DDR_rdc_v;
rpipec_Din <= "00" & DDR_rdc_Shift & '0' & DDR_rdc_sof & DDR_rdc_eof & DDR_rd_Cross_Row & DDR_rdc_FA & DDR_rdc_din;
DDR_rdc_full <= rpipec_aFull;
Syn_DDR_rdC_Cross_Row :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
DDR_rdc_din_r1(64-1 downto 10) <= (others => '0');
DDR_rdc_din_r1(9 downto 0) <= DDR_rdc_din(9 downto 0) - "100";
end if;
end process;
DDR_read_ALC <= (DDR_rdc_din_r1(10 downto 2) &"00") + ('0' & DDR_rdc_din(9 downto 2) &"00");
DDR_rd_Cross_Row <= '0'; -- DDR_read_ALC(10);
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_pipe_read_D_fifo:
-- asyn_rw_FIFO
-- GENERIC MAP (
-- OUTPUT_REGISTERED => TRUE
-- )
-- PORT MAP(
-- wClk => ddr_Clock, -- Clk_ddr_rddata , -- ddr_Clock , -- ddr_Clock_n ,
-- wEn => rpiped_wEn ,
-- Din => rpiped_Din ,
-- aFull => rpiped_aFull ,
-- Full => rpiped_Full ,
--
-- rClk => user_clk ,
-- rEn => DDR_FIFO_RdEn , -- rpiped_rEn ,
-- Qout => rpiped_Qout ,
-- aEmpty => open , -- rpiped_aEmpty ,
-- Empty => DDR_FIFO_Empty , -- rpiped_Empty ,
--
-- Rst => Rst_i
-- );
-- DDR_pipe_read_D_fifo:
-- asyn_rw_FIFO72
-- PORT MAP(
-- wClk => ddr_Clock ,
-- wEn => rpiped_wEn ,
-- Din => rpiped_Din ,
-- aFull => rpiped_aFull ,
-- Full => open ,
--
-- rClk => user_clk ,
-- rEn => DDR_FIFO_RdEn ,
-- Qout => rpiped_Qout ,
-- aEmpty => open ,
-- Empty => DDR_FIFO_Empty ,
--
-- Rst => Rst_i
-- );
DDR_pipe_read_D_fifo :
prime_fifo_plain
port map(
wr_clk => user_clk , -- IN std_logic;
wr_en => rpiped_wEn , -- IN std_logic;
din => rpiped_Din , -- IN std_logic_VECTOR(35 downto 0);
prog_full => rpiped_aFull , -- OUT std_logic;
full => open, -- rpiped_Full , -- OUT std_logic;
rd_clk => user_clk , -- IN std_logic;
rd_en => DDR_FIFO_RdEn , -- IN std_logic;
dout => rpiped_Qout , -- OUT std_logic_VECTOR(35 downto 0);
empty => DDR_FIFO_Empty , -- OUT std_logic;
rst => Rst_i -- IN std_logic
);
DDR_FIFO_RdQout <= rpiped_Qout(C_DBUS_WIDTH-1 downto 0);
-- -------------------------------------------------
-- pkt_RAM instantiate
--
pkt_RAM :
bram_x64
port map (
clka => user_clk ,
addra => pRAM_addrA ,
wea => pRAM_weA ,
dina => pRAM_dinA ,
douta => pRAM_doutA ,
clkb => user_clk ,
addrb => pRAM_addrB ,
web => pRAM_weB ,
dinb => pRAM_dinB ,
doutb => pRAM_doutB
);
pRAM_weB <= X"00";
pRAM_dinB <= (others => '0');
-- ------------------------------------------------
-- write States synchronous
--
Syn_Pseudo_DDR_wr_States :
process (user_clk, user_reset)
begin
if user_reset = '1' then
pseudo_DDR_wr_State <= wrST_bram_RESET;
pRAM_addrA <= (others => '1');
pRAM_weA <= (others => '0');
pRAM_dinA <= (others => '0');
wpipe_qout_lo32b <= (others => '0');
wpipe_QW_Aligned <= '1';
pRAM_AddrA_Inc <= '1';
elsif user_clk'event and user_clk = '1' then
case pseudo_DDR_wr_State is
when wrST_bram_RESET =>
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_addrA <= (others => '1');
wpipe_QW_Aligned <= '1';
wpipe_qout_lo32b <= (others => '0');
pRAM_weA <= (others => '0');
pRAM_dinA <= (others => '0');
pRAM_AddrA_Inc <= '1';
when wrST_bram_IDLE =>
pRAM_addrA <= wpipe_Qout(14 downto 3);
pRAM_AddrA_Inc <= wpipe_Qout(2);
wpipe_QW_Aligned <= not wpipe_Qout(69);
wpipe_qout_lo32b <= (32 => '1', others => '0');
pRAM_weA <= (others => '0');
pRAM_dinA <= pRAM_dinA;
if wpipe_read_valid = '1' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data; -- wrST_bram_Address;
else
pseudo_DDR_wr_State <= wrST_bram_IDLE;
end if;
when wrST_bram_1st_Data =>
pRAM_addrA <= pRAM_addrA;
if wpipe_read_valid = '0' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_weA <= (others => '0'); --pRAM_weA;
pRAM_dinA <= pRAM_dinA;
elsif wpipe_Qout(66) = '1' then -- eof
if wpipe_QW_Aligned = '1' then
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not (wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70));
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
elsif wpipe_Qout(70) = '1' then -- mask(0)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not (wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71));
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
elsif wpipe_Qout(71) = '1' then -- mask(1)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= X"F0";
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
else
pseudo_DDR_wr_State <= wrST_bram_last_DW;
pRAM_weA <= not (wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71));
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
else
if wpipe_QW_Aligned = '1' then
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not (wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70));
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
elsif pRAM_AddrA_Inc = '1' then
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not (wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71));
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
else
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_AddrA_Inc <= '1';
pRAM_weA <= X"00";
pRAM_dinA <= pRAM_dinA;
wpipe_qout_lo32b <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
end if;
end if;
when wrST_bram_more_Data =>
if wpipe_read_valid = '0' then
pseudo_DDR_wr_State <= wrST_bram_more_Data; -- wrST_bram_1st_Data;
pRAM_weA <= (others => '0'); --pRAM_weA;
pRAM_addrA <= pRAM_addrA;
pRAM_dinA <= pRAM_dinA;
elsif wpipe_Qout(66) = '1' then -- eof
if wpipe_QW_Aligned = '1' then
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not (wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70));
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
elsif wpipe_Qout(70) = '1' then -- mask(0)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not (wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71));
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
else
pseudo_DDR_wr_State <= wrST_bram_last_DW;
pRAM_weA <= not (wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71));
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
else
if wpipe_QW_Aligned = '1' then
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not (wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70));
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
else
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not (wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71));
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
end if;
when wrST_bram_last_DW =>
-- pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= X"F0";
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & X"00000000";
if wpipe_read_valid = '1' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data_b2b; -- wrST_bram_Address;
wpipe_Qout_latch <= wpipe_Qout;
else
pseudo_DDR_wr_State <= wrST_bram_IDLE;
wpipe_Qout_latch <= wpipe_Qout;
end if;
when wrST_bram_1st_Data_b2b =>
pRAM_addrA <= wpipe_Qout_latch(14 downto 3);
wpipe_QW_Aligned <= not wpipe_Qout_latch(69);
if wpipe_read_valid = '0' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_weA <= (others => '0'); --pRAM_weA;
pRAM_dinA <= pRAM_dinA;
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32 => '1', others => '0');
elsif wpipe_Qout(66) = '1' then -- eof
if wpipe_Qout_latch(69) = '0' then -- wpipe_QW_Aligned
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not (wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70));
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32 => '1', others => '0');
elsif wpipe_Qout(70) = '1' then -- mask(0)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not (X"f" & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71));
pRAM_dinA <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32 => '1', others => '0');
elsif wpipe_Qout(71) = '1' then -- mask(1)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= X"F0";
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32 => '1', others => '0');
else
pseudo_DDR_wr_State <= wrST_bram_last_DW;
pRAM_weA <= not (X"f" & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71));
pRAM_dinA <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
else
if wpipe_Qout_latch(69) = '0' then -- wpipe_QW_Aligned
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not (wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70));
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32 => '1', others => '0');
elsif wpipe_Qout_latch(2) = '1' then -- pRAM_AddrA_Inc
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not (X"f" & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71));
pRAM_dinA <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
else
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_AddrA_Inc <= '1';
pRAM_weA <= X"00";
pRAM_dinA <= pRAM_dinA;
wpipe_qout_lo32b <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
end if;
end if;
when others =>
pseudo_DDR_wr_State <= wrST_bram_RESET;
pRAM_addrA <= (others => '1');
pRAM_weA <= (others => '0');
pRAM_dinA <= (others => '0');
wpipe_qout_lo32b <= (others => '0');
wpipe_QW_Aligned <= '1';
pRAM_AddrA_Inc <= '1';
end case;
end if;
end process;
--
Syn_wPipe_read :
process (user_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
wpipe_rEn <= '0';
wpipe_read_valid <= '0';
elsif user_clk'event and user_clk = '1' then
wpipe_rEn <= '1';
wpipe_read_valid <= wpipe_rEn and not wpipe_Empty;
end if;
end process;
--
Syn_rPipeC_read :
process (user_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
rpipec_read_valid <= '0';
rpiped_wr_postpone <= '0';
rpiped_wr_skew <= '0';
elsif user_clk'event and user_clk = '1' then
rpipec_read_valid <= rpipec_rEn and not rpipec_Empty;
if rpipec_read_valid = '1' then
rpiped_wr_postpone <= rpipec_Qout(2) and not rpipec_Qout(69);
rpiped_wr_skew <= rpipec_Qout(69) xor rpipec_Qout(2);
else
rpiped_wr_postpone <= rpiped_wr_postpone;
rpiped_wr_skew <= rpiped_wr_skew;
end if;
end if;
end process;
-- ------------------------------------------------
-- Read States synchronous
--
Syn_Pseudo_DDR_rd_States :
process (user_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
pseudo_DDR_rd_State <= rdST_bram_RESET;
rpipec_rEn <= '0';
pRAM_addrB <= (others => '1');
rpiped_rd_counter <= (others => '0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
elsif user_clk'event and user_clk = '1' then
case pseudo_DDR_rd_State is
when rdST_bram_RESET =>
pseudo_DDR_rd_State <= rdST_bram_IDLE;
rpipec_rEn <= '0';
pRAM_addrB <= (others => '1');
rpiped_rd_counter <= (others => '0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
when rdST_bram_IDLE =>
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= (others => '0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
if rpipec_Empty = '0' then
rpipec_rEn <= '1';
pseudo_DDR_rd_State <= rdST_bram_b4_LA; --rdST_bram_b4_Length;
else
rpipec_rEn <= '0';
pseudo_DDR_rd_State <= rdST_bram_IDLE;
end if;
when rdST_bram_b4_LA =>
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= (others => '0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
rpipec_rEn <= '0';
pseudo_DDR_rd_State <= rdST_bram_LA;
when rdST_bram_LA =>
rpipec_rEn <= '0';
pRAM_addrB <= rpipec_Qout(14 downto 3);
rpiped_wr_EOF <= '0';
rpiped_wEn_b3 <= '0';
if rpipec_Qout(2+32) = '1' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + '1';
elsif rpipec_Qout(2) = '1' and rpipec_Qout(69) = '1' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
elsif rpipec_Qout(2) = '0' and rpipec_Qout(69) = '1' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
elsif rpipec_Qout(2) = '1' and rpipec_Qout(69) = '0' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32);
else
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32);
end if;
-- elsif rpipec_Qout(2)='1' then
-- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
-- elsif rpipec_Qout(69)='1' then
-- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
-- else
-- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32);
-- end if;
pseudo_DDR_rd_State <= rdST_bram_Data;
when rdST_bram_Data =>
rpipec_rEn <= '0';
if rpiped_rd_counter = CONV_STD_LOGIC_VECTOR(2, 10) then
pRAM_addrB <= pRAM_addrB + '1';
rpiped_rd_counter <= rpiped_rd_counter;
rpiped_wEn_b3 <= '1';
rpiped_wr_EOF <= '1';
pseudo_DDR_rd_State <= rdST_bram_IDLE;
elsif rpiped_aFull = '1' then
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= rpiped_rd_counter;
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
pseudo_DDR_rd_State <= rdST_bram_Data;
else
pRAM_addrB <= pRAM_addrB + '1';
rpiped_rd_counter <= rpiped_rd_counter - "10";
rpiped_wEn_b3 <= '1';
rpiped_wr_EOF <= '0';
pseudo_DDR_rd_State <= rdST_bram_Data;
end if;
when others =>
rpipec_rEn <= '0';
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= rpiped_rd_counter;
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
pseudo_DDR_rd_State <= rdST_bram_RESET;
end case;
end if;
end process;
Syn_Pseudo_DDR_rdd_write :
process (user_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
rpiped_wEn_b1 <= '0';
rpiped_wEn_b2 <= '0';
rpiped_wEn <= '0';
rpiped_Din <= (others => '0');
elsif user_clk'event and user_clk = '1' then
rpiped_wEn_b2 <= rpiped_wEn_b3;
rpiped_wEn_b1 <= rpiped_wEn_b2;
if rpiped_wr_skew = '1' then
-- rpiped_wEn <= rpiped_wEn_b2;
rpiped_wEn <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
or (rpiped_wEn_b1 and rpiped_wr_postpone);
rpiped_Din <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB_shifted;
else
-- rpiped_wEn <= rpiped_wEn_b2;
rpiped_wEn <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
or (rpiped_wEn_b1 and rpiped_wr_postpone);
rpiped_Din <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB;
end if;
end if;
end process;
--
DDR_Blinker_Module :
DDR_Blink
port map(
DDR_Blinker => DDR_Blinker ,
DDR_Write => wpipe_rEn ,
DDR_Read => rpiped_wEn ,
DDR_Both => '0' ,
ddr_Clock => user_clk ,
DDr_Rst_n => DDR_Ready_i -- DDR_CKE_i
);
end architecture Behavioral;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/testbench/wishbone/system_test/system_test_tb.vhd | 1 | 15483 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Wishbone Stream Interface
use work.wb_stream_pkg.all;
-- Register Bank
use work.fmc150_wbgen2_pkg.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity system_test_tb is
end system_test_tb;
architecture sim of system_test_tb is
-- Constants
-- 100.00 MHz clock
constant c_100mhz_clk_period : time := 10.00 ns;
-- 200.00 MHz clock
constant c_200mhz_clk_period : time := 5.00 ns;
-- 61.44 MHz clock
constant c_sim_adc_clk_period : time := 16.00 ns;
-- 128.88 MHz clock
constant c_sim_adc_clk2x_period : time := 8.00 ns;
constant c_sim_time : time := 10000.00 ns;
signal g_end_simulation : boolean := false; -- Set to true to halt the simulation
-- Clock signals
signal clk_100mhz : std_logic := '0';
signal clk_200mhz : std_logic := '0';
signal clk_sys : std_logic := '0';
signal rst_n_i : std_logic := '0';
-- Wishbone signals
signal wb_slv_in : t_wishbone_slave_in := cc_dummy_slave_in;
signal wb_slv_out : t_wishbone_slave_out;
signal wbs_src_in : t_wbs_source_in := cc_dummy_src_in;
signal wbs_src_out : t_wbs_source_out;
-- Dummy signals
constant cc_zero_bit : std_logic := '0';
-- Simulation signals
signal s_sim_adc_clk : std_logic := '0';
signal s_sim_adc_clk2x : std_logic := '0';
signal s_sim_adc_cha_data : std_logic_vector(6 downto 0);
signal s_sim_adc_chb_data : std_logic_vector(6 downto 0);
signal s_sim_adc_valid : std_logic;
-----------------------------------------
-- Components
-----------------------------------------
component dbe_bpm_simple_top
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
--clk100_i : in std_logic;
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- FMC150 pins
-----------------------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i : in std_logic;
adc_clk_ab_n_i : in std_logic;
adc_cha_p_i : in std_logic_vector(6 downto 0);
adc_cha_n_i : in std_logic_vector(6 downto 0);
adc_chb_p_i : in std_logic_vector(6 downto 0);
adc_chb_n_i : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o : out std_logic; -- Shared SPI clock line
spi_sdata_o : out std_logic; -- Shared SPI data line
-- ADC specific signals
adc_n_en_o : out std_logic; -- SPI chip select
adc_sdo_i : in std_logic; -- SPI data out
adc_reset_o : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en_o : out std_logic; -- SPI chip select
cdce_sdo_i : in std_logic; -- SPI data out
cdce_n_reset_o : out std_logic;
cdce_n_pd_o : out std_logic;
cdce_ref_en_o : out std_logic;
cdce_pll_status_i : in std_logic;
-- DAC specific signals
dac_n_en_o : out std_logic; -- SPI chip select
dac_sdo_i : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en_o : out std_logic; -- SPI chip select
mon_sdo_i : in std_logic; -- SPI data out
mon_n_reset_o : out std_logic;
mon_n_int_i : in std_logic;
--FMC Present status
prsnt_m2c_l_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o : out std_logic_vector(7 downto 0)
);
end component;
--------------------------------
-- Functions and Procedures
--------------------------------
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
-- Generate bit with probability of '1' equals to 'prob'
procedure gen_valid(prob : real; variable seed1, seed2 : inout positive;
signal result : out std_logic)
is
variable rand: real; -- Random real-number value in range 0 to 1.0
begin
uniform(seed1, seed2, rand); -- generate random number
if (rand > prob) then
result <= '1';
else
result <= '0';
end if;
end procedure;
-- Generate random std_logic_vector
procedure gen_data(size : positive; variable seed1, seed2 : inout positive;
signal result : out std_logic_vector)
is
variable rand : real; -- Random real-number value in range 0 to 1.0
variable int_rand : integer; -- Random integer value in range 0..2^(c_wbs_data_width/2)
variable stim : std_logic_vector(c_wbs_data_width-1 downto 0); -- Random c_wbs_data_width-1 bit stimulus
begin
uniform(seed1, seed2, rand); -- generate random number
int_rand := integer(trunc(rand*real(2**(c_wbs_data_width/2)))); -- rescale to 0..2^(c_wbs_data_width/2), find integer part
stim := std_logic_vector(to_unsigned(int_rand, stim'length)); -- convert to std_logic_vector
result <= stim(size-1 downto 0);
end procedure;
begin -- sim
p_100mhz_clk_gen : process
begin
while g_end_simulation = false loop
wait for c_100mhz_clk_period/2;
clk_100mhz <= not clk_100mhz;
wait for c_100mhz_clk_period/2;
clk_100mhz <= not clk_100mhz;
end loop;
wait; -- simulation stops here
end process;
p_200mhz_clk_gen : process
begin
while g_end_simulation = false loop
wait for c_200mhz_clk_period/2;
clk_200mhz <= not clk_200mhz;
wait for c_200mhz_clk_period/2;
clk_200mhz <= not clk_200mhz;
end loop;
wait; -- simulation stops here
end process;
-- Sim ADC clock gen
p_sim_adc_clk_gen : process
begin
while g_end_simulation = false loop
wait for c_sim_adc_clk_period/2;
s_sim_adc_clk <= not s_sim_adc_clk;
wait for c_sim_adc_clk_period/2;
s_sim_adc_clk <= not s_sim_adc_clk;
end loop;
wait; -- simulation stops here
end process;
-- Sim ADC clock gen
p_sim_adc_clk_2x_gen : process
begin
while g_end_simulation = false loop
wait for c_sim_adc_clk2x_period/2;
s_sim_adc_clk2x <= not s_sim_adc_clk2x;
wait for c_sim_adc_clk2x_period/2;
s_sim_adc_clk2x <= not s_sim_adc_clk2x;
end loop;
wait; -- simulation stops here
end process;
p_gen_adc_valid : process
variable seed1, seed2: positive; -- Seed values for random generator
begin
seed1 := 67632;
seed2 := 3234;
s_sim_adc_valid <= '0';
-- Wait until reset completion (synch with adc clock domain)
wait until rst_n_i = '1' and rising_edge(s_sim_adc_clk);
l_generate_valid: loop
gen_valid(0.5, seed1, seed2, s_sim_adc_valid);
wait until rising_edge(s_sim_adc_clk);
end loop;
end process;
p_gen_adc_data : process
variable seed1, seed2: positive; -- Seed values for random generator
begin
seed1 := 432566;
seed2 := 211;
s_sim_adc_cha_data <= (others => '0');
s_sim_adc_chb_data <= (others => '0');
-- Wait until reset completion (synch with adc clock domain)
wait until rst_n_i = '1' and rising_edge(s_sim_adc_clk);
l_generate_data: loop
gen_data(s_sim_adc_cha_data'length, seed1, seed2, s_sim_adc_cha_data);
gen_data(s_sim_adc_chb_data'length, seed1, seed2, s_sim_adc_chb_data);
wait until rising_edge(s_sim_adc_clk);
end loop;
end process;
p_main_simulation : process
begin
-- Generate reset signal
rst_n_i <= '0';
wait for 3*c_100mhz_clk_period;
rst_n_i <= '1';
wait for c_sim_time;
g_end_simulation <= true;
wait;
end process;
cmp_dut : dbe_bpm_simple_top
--generic map
--(
--g_interface_mode => PIPELINED,
--g_address_granularity => WORD,
--g_packet_size => 32
--g_sim => 1
--)
port map
(
sys_clk_p_i => clk_100mhz,
sys_clk_n_i => clk_100mhz,
sys_rst_button_i => '0',
-----------------------------
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i => s_sim_adc_clk,--s_adc_clk_ab_p,
adc_clk_ab_n_i => s_sim_adc_clk,--s_adc_clk_ab_n,
adc_cha_p_i => s_sim_adc_cha_data,
adc_cha_n_i => s_sim_adc_cha_data,
adc_chb_p_i => s_sim_adc_chb_data,
adc_chb_n_i => s_sim_adc_chb_data,
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o => open,
dac_dclk_n_o => open,
dac_data_p_o => open,
dac_data_n_o => open,
dac_frame_p_o => open,
dac_frame_n_o => open,
txenable_o => open,
--Clock/Trigger connection to FMC150
--clk_to_fpga_p_i => cc_zero_bit,
--clk_to_fpga_n_i => cc_zero_bit,
--ext_trigger_p_i => cc_zero_bit,
--ext_trigger_n_i => cc_zero_bit,
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o => open, -- Shared SPI clock line
spi_sdata_o => open, -- Shared SPI data line
-- ADC specific signals
adc_n_en_o => open, -- SPI chip select
adc_sdo_i => cc_zero_bit, -- SPI data out
adc_reset_o => open, -- SPI reset
-- CDCE specific signals
cdce_n_en_o => open, -- SPI chip select
cdce_sdo_i => cc_zero_bit, -- SPI data out
cdce_n_reset_o => open,
cdce_n_pd_o => open,
cdce_ref_en_o => open,
cdce_pll_status_i => cc_zero_bit,
-- DAC specific signals
dac_n_en_o => open, -- SPI chip select
dac_sdo_i => cc_zero_bit, -- SPI data out
-- Monitoring specific signals
mon_n_en_o => open, -- SPI chip select
mon_sdo_i => cc_zero_bit, -- SPI data out
mon_n_reset_o => open,
mon_n_int_i => cc_zero_bit,
--FMC Present status
prsnt_m2c_l_i => cc_zero_bit,
-----------------------------------------
-- Wishbone Streaming Interface Source
-----------------------------------------
uart_txd_o => open,
uart_rxd_i => '0',
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i => f_zeros(8),
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o => open
);
end sim;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/modules/dbe_wishbone/wb_fmc150/adc/strobe_lvds.vhd | 1 | 2227 | -----------------------------------------------------------------------------------
-- <description>
--
-- Author: Daniel Tavares ([email protected])
-- Company: Brazilian Synchrotron Light Laboratory, Campinas, Brazil
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity strobe_lvds is
generic
(
C_DEFAULT_DELAY : natural := 0
);
port
(
clk_ctrl_i : in std_logic;
strobe_p_i : in std_logic;
strobe_n_i : in std_logic;
strobe_o : out std_logic;
ctrl_delay_update_i : in std_logic;
ctrl_delay_value_i : in std_logic_vector(4 downto 0);
ctrl_delay_value_o : out std_logic_vector(4 downto 0)
);
end strobe_lvds;
architecture rtl of strobe_lvds is
signal s_strobe_l : std_logic;
signal s_strobe_dly : std_logic;
begin
cmp_ibufgds : ibufds
generic map
(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map
(
i => strobe_p_i,
ib => strobe_n_i,
o => s_strobe_l
);
cmp_iodelay : iodelaye1
generic map
(
IDELAY_TYPE => "VAR_LOADABLE",
IDELAY_VALUE => C_DEFAULT_DELAY,
SIGNAL_PATTERN => "CLOCK",
DELAY_SRC => "I"
)
port map
(
idatain => s_strobe_l,
dataout => s_strobe_dly,
c => clk_ctrl_i,
ce => '0',
inc => '0',
datain => '0',
odatain => '0',
clkin => '0',
rst => ctrl_delay_update_i,
cntvaluein => ctrl_delay_value_i,
cntvalueout => ctrl_delay_value_o,
cinvctrl => '0',
t => '1'
);
cmp_bufr : bufr
generic map
(
SIM_DEVICE => "VIRTEX6",
BUFR_DIVIDE => "BYPASS"
)
port map
(
clr => '1',
ce => '1',
i => s_strobe_dly,
o => strobe_o
);
end rtl; | lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/modules/pcie/common/rx_CplD_Channel.vhd | 1 | 56008 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: rx_CplD_Transact - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.10 - x4 timing constraints met. 02.02.2007
--
-- Revision 1.04 - Timing improved. 17.01.2007
--
-- Revision 1.02 - FIFO added. 20.12.2006
--
-- Revision 1.00 - first release. 14.12.2006
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
use work.genram_pkg.all;
entity rx_CplD_Transact is
port (
-- Transaction receive interface
m_axis_rx_tlast : in std_logic;
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tvalid : in std_logic;
m_axis_rx_tready : in std_logic; -- !!
m_axis_rx_tbar_hit : in std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
CplD_Type : in std_logic_vector(3 downto 0);
Req_ID_Match : in std_logic;
usDex_Tag_Matched : in std_logic;
dsDex_Tag_Matched : in std_logic;
Tlp_has_4KB : in std_logic;
Tlp_has_1DW : in std_logic;
CplD_on_Pool : in std_logic;
CplD_on_EB : in std_logic;
CplD_is_the_Last : in std_logic;
CplD_Tag : in std_logic_vector(C_TAG_WIDTH-1 downto 0);
FC_pop : out std_logic;
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add : out std_logic;
ds_DMA_Bytes : out std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Tag output to downstream DMA channel
dsDMA_dex_Tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Downstream Handshake Signals with ds Channel for Busy/Done
Tag_Map_Clear : out std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
-- Downstream tRAM port A write request
tRAM_weB : in std_logic;
tRAM_addrB : in std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_dinB : in std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-- Tag output to upstream DMA channel
usDMA_dex_Tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Event Buffer write port
wb_FIFO_we : out std_logic;
wb_FIFO_wsof : out std_logic;
wb_FIFO_weof : out std_logic;
wb_FIFO_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Registers Write Port
Regs_WrEn : out std_logic;
Regs_WrMask : out std_logic_vector(2-1 downto 0);
Regs_WrAddr : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR write port
DDR_wr_sof : out std_logic;
DDR_wr_eof : out std_logic;
DDR_wr_v : out std_logic;
DDR_wr_Shift : out std_logic;
DDR_wr_Mask : out std_logic_vector(2-1 downto 0);
DDR_wr_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : in std_logic;
-- Common ports
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic
);
end entity rx_CplD_Transact;
architecture Behavioral of rx_CplD_Transact is
type RxCplDEBStates is (ST_EBWR_IDLE
, ST_EBWR_TAG
, ST_EBWR_DATA
);
signal wb_Write_State : RxCplDEBStates;
type RxCplDTrnStates is (ST_CplD_RESET
, ST_CplD_IDLE
-- , ST_Cpl_HEAD1 -- Cpl Header #1 (not used)
-- , ST_CplD_HEAD1 -- CplD Header #1
, ST_Cpl_HEAD2 -- Cpl Header #2 (not used)
, ST_CplD_HEAD2 -- CplD Header #2
, ST_CplD_AFetch_Special --
, ST_CplD_AFetch_Special_Tail --
, ST_CplD_AFetch -- Target address fetch from tRAM/registers
, ST_CplD_AFetch_THROTTLE -- Target address fetch throttled
, ST_CplD_ONLY_1DW -- Current CplD has only 1 DW
-- , ST_CplD_ONLY_1DW_THROTTLE -- Current CplD has only 1 DW, throttled
, ST_CplD_1ST_DATA -- 1st data payload of the CplD
, ST_CplD_1ST_DATA_THROTTLE -- 1st data payload of the CplD
, ST_CplD_DATA -- data receiving
, ST_CplD_DATA_THROTTLE -- data receiving throttled
, ST_CplD_LAST_DATA -- Last data payload of the CplD
);
-- State variables
signal RxCplDTrn_NextState : RxCplDTrnStates;
signal RxCplDTrn_State : RxCplDTrnStates;
-- State delay
signal RxCplDTrn_State_r1 : RxCplDTrnStates;
signal CplD_State_is_AFetch : std_logic;
signal CplD_State_is_after_AFetch : std_logic;
signal CplD_State_is_AFetch_r1 : std_logic;
-- Shifted-glued payload
signal concat_rd : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
-- trn_rx stubs
signal m_axis_rx_tdata_i : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_r1 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_r2 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_r3 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_r4 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
-- m_axis_rx_tdata_* in little endian
signal m_axis_rx_tdata_Little : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_Little_r1 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_Little_r2 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_Little_r3 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_Little_r4 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
-- signal m_axis_rx_tbar_hit_i : std_logic_vector(C_BAR_NUMBER-1 downto 0);
signal trn_rsof_n_i : std_logic;
signal in_packet_reg : std_logic;
signal m_axis_rx_tlast_i : std_logic;
signal m_axis_rx_tlast_r1 : std_logic;
signal m_axis_rx_tlast_r2 : std_logic;
signal m_axis_rx_tlast_r3 : std_logic;
signal m_axis_rx_tlast_r4 : std_logic;
-- signal Tlp_has_4KB_r1 : std_logic;
signal m_axis_rx_tkeep_i : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal m_axis_rx_tkeep_r1 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal m_axis_rx_tkeep_r2 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal m_axis_rx_tkeep_r3 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal m_axis_rx_tkeep_r4 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
-- Whether address increases
signal Addr_Inc : std_logic;
-- Spaces hit
signal FIFO_Space_Hit : std_logic;
signal DDR_Space_Hit : std_logic;
-- DDR write port
signal DDR_wr_sof_i : std_logic;
signal DDR_wr_eof_i : std_logic;
signal DDR_wr_v_i : std_logic;
signal DDR_wr_Shift_i : std_logic;
signal DDR_wr_Mask_i : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Event Buffer write port
signal wb_FIFO_we_i : std_logic;
signal wb_FIFO_wsof_i : std_logic;
signal wb_FIFO_weof_i : std_logic;
signal wb_FIFO_sof_marker : std_logic;
signal wb_FIFO_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register write port
signal Regs_WrEn_i : std_logic;
signal Regs_WrMask_i : std_logic_vector(2-1 downto 0);
signal Regs_WrAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation @ trn_rsof_n=0
signal Reg_WrAddr_if_last_us : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Reg_WrAddr_if_last_ds : std_logic_vector(C_EP_AWIDTH-1 downto 0);
-- Flow control signals
signal m_axis_rx_tready_i : std_logic;
signal m_axis_rx_tvalid_i : std_logic;
signal m_axis_rx_tvalid_r1 : std_logic;
signal m_axis_rx_tvalid_r2 : std_logic;
signal m_axis_rx_tvalid_r3 : std_logic;
signal m_axis_rx_tvalid_r4 : std_logic;
signal trn_rx_throttle : std_logic;
signal trn_rx_throttle_r1 : std_logic;
signal trn_rx_throttle_r2 : std_logic;
signal trn_rx_throttle_r3 : std_logic;
signal trn_rx_throttle_r4 : std_logic;
-- Downstream DMA transferred bytes count up
signal ds_DMA_Bytes_Add_i : std_logic;
signal ds_DMA_Bytes_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
signal CplD_is_Payloaded : std_logic;
-- Alias for header resolution
signal CplD_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto 0);
signal CplD_Leng_in_Bytes : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal CplD_Leng_in_Bytes_r1 : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal CplD_is_1DW : std_logic;
-- Small_CplD means CplD with less than 4 DW payload
signal Small_CplD : std_logic;
signal Small_CplD_r1 : std_logic;
signal RegAddr_us_Dex : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal RegAddr_ds_Dex : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal CplD_Tag_on_Dex : std_logic;
-- ----------------------------------------------------------------------
signal Req_ID_Match_i : std_logic;
signal Dex_Tag_Matched_i : std_logic;
-- The top bit of the CplD_Tag is for distinguishing data CplD or descriptor CplD
signal MSB_DSP_Tag : std_logic;
signal DSP_Tag_on_RAM : std_logic;
signal DSP_Tag_on_RAM_r1 : std_logic;
signal DSP_Tag_on_RAM_r2 : std_logic;
signal DSP_Tag_on_RAM_r3 : std_logic;
signal DSP_Tag_on_RAM_r4p : std_logic;
signal DSP_Tag_on_FIFO : std_logic;
signal DSP_Tag_on_FIFO_r1 : std_logic;
signal DSP_Tag_on_FIFO_r2 : std_logic;
signal DSP_Tag_on_FIFO_r3 : std_logic;
signal DSP_Tag_on_FIFO_r4p : std_logic;
-- ----------------------------------------------------------------------
signal FC_pop_i : std_logic;
signal Tag_Map_Clear_i : std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
signal Local_Reset_i : std_logic;
-- upstream Descriptors' tags
signal usDMA_dex_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- downstream Descriptors' tags
signal dsDMA_dex_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
signal tRAM_wea : std_logic_vector(0 downto 0);
signal tRAM_addra : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
signal tRAM_dina : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_doutA : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_weB_i : std_logic_vector(0 downto 0);
signal tRAM_DoutA_r1 : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_DoutA_r2 : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_dina_aInc : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_DoutA_latch : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-- updates the tag RAM as soon as possible
signal CplD_is_the_Last_r1 : std_logic;
signal Updates_tRAM : std_logic;
signal Updates_tRAM_r1 : std_logic;
signal Update_was_too_late : std_logic;
signal hazard_update : std_logic;
signal hazard_update_r1 : std_logic;
signal hazard_update_r2 : std_logic;
signal hazard_update_r3 : std_logic;
signal hazard_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0);
signal hazard_content : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tag_matches_hazard : std_logic;
begin
-- Event Buffer write
wb_FIFO_we <= wb_FIFO_we_i;
wb_FIFO_wsof <= wb_FIFO_wsof_i;
wb_FIFO_weof <= wb_FIFO_weof_i;
wb_FIFO_din <= wb_FIFO_din_i;
-- DDR
DDR_wr_sof <= DDR_wr_sof_i;
DDR_wr_eof <= DDR_wr_eof_i;
DDR_wr_v <= DDR_wr_v_i;
DDR_wr_Shift <= DDR_wr_Shift_i;
DDR_wr_Mask <= DDR_wr_Mask_i;
DDR_wr_din <= DDR_wr_din_i;
ds_DMA_Bytes_Add <= ds_DMA_Bytes_Add_i;
ds_DMA_Bytes <= ds_DMA_Bytes_i;
--
Tag_Map_Clear <= Tag_Map_Clear_i;
--
FC_pop <= FC_pop_i;
-- ----------------------------------------------
--
Syn_FC_pop :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
FC_pop_i <= '0';
elsif user_clk'event and user_clk = '1' then
FC_pop_i <= (CplD_on_Pool or CplD_on_EB)
and CplD_is_the_Last
and not MSB_DSP_Tag
and m_axis_rx_tlast_i
and not m_axis_rx_tlast_r1; -- Catch the raising edge of m_axis_rx_tlast
-- and not trn_rx_throttle;
end if;
end process;
-- ----------------------------------------------
-- Synchronous: CplD_is_Payloaded
--
Syn_CplD_is_Payloaded :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
CplD_is_Payloaded <= '0';
elsif user_clk'event and user_clk = '1' then
if trn_rsof_n_i = '0' and trn_rx_throttle = '0' then
CplD_is_Payloaded <= CplD_Type(3) or CplD_Type(1);
else
CplD_is_Payloaded <= CplD_is_Payloaded;
end if;
end if;
end process;
-- ----------------------------------------------
-- Synchronous Accumulation: us_DMA_Bytes
--
Syn_ds_DMA_Bytes_Add :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
ds_DMA_Bytes_Add_i <= '0';
ds_DMA_Bytes_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if m_axis_rx_tlast_i = '1' and trn_rx_throttle = '0'
and CplD_is_Payloaded = '1' and MSB_DSP_Tag = '0'
then
ds_DMA_Bytes_Add_i <= '1';
ds_DMA_Bytes_i <= CplD_Leng_in_Bytes(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
else
ds_DMA_Bytes_Add_i <= '0';
ds_DMA_Bytes_i <= (others => '0');
end if;
end if;
end process;
-- Registers writing
Regs_WrEn <= Regs_WrEn_i;
Regs_WrMask <= Regs_WrMask_i;
Regs_WrAddr <= Regs_WrAddr_i;
Regs_WrDin <= Regs_WrDin_i;
--- Dex Tag output to us DMA channel
usDMA_dex_Tag <= usDMA_dex_Tag_i;
--- Dex Tag output to ds DMA channel
dsDMA_dex_Tag <= dsDMA_dex_Tag_i;
---------------------------------------------------
Req_ID_Match_i <= Req_ID_Match;
Dex_Tag_Matched_i <= usDex_Tag_Matched or dsDex_Tag_Matched;
-- positive reset
Local_Reset_i <= user_reset;
-- Frame signals
m_axis_rx_tlast_i <= m_axis_rx_tlast;
m_axis_rx_tdata_i <= m_axis_rx_tdata;
m_axis_rx_tkeep_i <= m_axis_rx_tkeep;
m_axis_rx_tvalid_i <= m_axis_rx_tvalid;
m_axis_rx_tready_i <= m_axis_rx_tready;
-- BC of the current TLP payloads
CplD_Leng_in_Bytes <= C_ALL_ZEROS(C_DBUS_WIDTH/2-1 downto C_TLP_FLD_WIDTH_OF_LENG+3)
& CplD_Length & "00";
-- ( m_axis_rx_tvalid seems never deasserted during packet)
trn_rx_throttle <= not(m_axis_rx_tvalid_i) or not(m_axis_rx_tready_i);
-- ---------------------------------------------
-- Synchronous bit: CplD_State_is_AFetch
--
RxFSM_CplD_State_is_AFetch :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
CplD_State_is_AFetch_r1 <= CplD_State_is_AFetch;
case RxCplDTrn_State is
when ST_CplD_AFetch =>
CplD_State_is_AFetch <= '1';
when ST_CplD_AFetch_Special =>
CplD_State_is_AFetch <= '1';
when others =>
CplD_State_is_AFetch <= '0';
end case;
end if;
end process;
-- ---------------------------------------------
-- Synchronous bit: CplD_State_is_after_AFetch
--
RxFSM_CplD_State_is_after_AFetch :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_AFetch_Special_Tail =>
CplD_State_is_after_AFetch <= '1';
when ST_CplD_ONLY_1DW =>
CplD_State_is_after_AFetch <= '1';
when ST_CplD_1ST_DATA =>
CplD_State_is_after_AFetch <= '1';
when others =>
CplD_State_is_after_AFetch <= '0';
end case;
end if;
end process;
-- ---------------------------------------------
-- Delay Synchronous Delay: trn_r*
--
Syn_Delay_trn_r_x :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
m_axis_rx_tlast_r1 <= m_axis_rx_tlast_i;
m_axis_rx_tlast_r2 <= m_axis_rx_tlast_r1;
m_axis_rx_tlast_r3 <= m_axis_rx_tlast_r2;
m_axis_rx_tlast_r4 <= m_axis_rx_tlast_r3;
m_axis_rx_tvalid_r1 <= not(trn_rx_throttle); -- m_axis_rx_tvalid_i;
m_axis_rx_tvalid_r2 <= m_axis_rx_tvalid_r1;
m_axis_rx_tvalid_r3 <= m_axis_rx_tvalid_r2;
m_axis_rx_tvalid_r4 <= m_axis_rx_tvalid_r3;
trn_rx_throttle_r1 <= trn_rx_throttle;
trn_rx_throttle_r2 <= trn_rx_throttle_r1;
trn_rx_throttle_r3 <= trn_rx_throttle_r2;
trn_rx_throttle_r4 <= trn_rx_throttle_r3;
m_axis_rx_tdata_r1 <= m_axis_rx_tdata_i;
m_axis_rx_tdata_r2 <= m_axis_rx_tdata_r1;
m_axis_rx_tdata_r3 <= m_axis_rx_tdata_r2;
m_axis_rx_tdata_r4 <= m_axis_rx_tdata_r3;
m_axis_rx_tkeep_r1 <= m_axis_rx_tkeep_i;
m_axis_rx_tkeep_r2 <= m_axis_rx_tkeep_r1;
m_axis_rx_tkeep_r3 <= m_axis_rx_tkeep_r2;
m_axis_rx_tkeep_r4 <= m_axis_rx_tkeep_r3;
end if;
end process;
-- Endian reversed
m_axis_rx_tdata_Little <= Endian_Invert_64(m_axis_rx_tdata_i(63 downto 32) & m_axis_rx_tdata_i(31 downto 0));
m_axis_rx_tdata_Little_r1 <= Endian_Invert_64(m_axis_rx_tdata_r1(63 downto 32) & m_axis_rx_tdata_r1(31 downto 0));
m_axis_rx_tdata_Little_r2 <= Endian_Invert_64(m_axis_rx_tdata_r2(63 downto 32) & m_axis_rx_tdata_r2(31 downto 0));
m_axis_rx_tdata_Little_r3 <= Endian_Invert_64(m_axis_rx_tdata_r3(63 downto 32) & m_axis_rx_tdata_r3(31 downto 0));
m_axis_rx_tdata_Little_r4 <= Endian_Invert_64(m_axis_rx_tdata_r4(63 downto 32) & m_axis_rx_tdata_r4(31 downto 0));
-- ---------------------------------------------
MSB_DSP_Tag <= CplD_Tag(C_TAG_WIDTH-1);
DSP_Tag_on_RAM <= CplD_on_pool and (not CplD_Tag(C_TAG_WIDTH-1) and not CplD_Tag(C_TAG_WIDTH-2));
DSP_Tag_on_FIFO <= CplD_on_EB and (not CplD_Tag(C_TAG_WIDTH-1) and CplD_Tag(C_TAG_WIDTH-2));
--
-- Delay Synchronous: MSB_DSP_Tag_r1
--
Syn_Delay_MSB_DSP_Tag_r1 :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
DSP_Tag_on_RAM_r1 <= DSP_Tag_on_RAM;
DSP_Tag_on_RAM_r2 <= DSP_Tag_on_RAM_r1;
DSP_Tag_on_RAM_r3 <= DSP_Tag_on_RAM_r2;
DSP_Tag_on_RAM_r4p <= DSP_Tag_on_RAM_r2 or DSP_Tag_on_RAM_r3;
DSP_Tag_on_FIFO_r1 <= DSP_Tag_on_FIFO;
DSP_Tag_on_FIFO_r2 <= DSP_Tag_on_FIFO_r1;
DSP_Tag_on_FIFO_r3 <= DSP_Tag_on_FIFO_r2;
DSP_Tag_on_FIFO_r4p <= DSP_Tag_on_FIFO_r2 or DSP_Tag_on_FIFO_r3;
end if;
end process;
--
-- Delay Synchronous: CplD_Leng_in_Bytes
--
Syn_Delay_CplD_Leng_in_Bytes :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
CplD_Leng_in_Bytes_r1 <= CplD_Leng_in_Bytes;
end if;
end process;
-- ---------------------------------------------
-- Delay Synchronous Delay: RxCplDTrn_State
--
RxFSM_Delay_RxTrn_State :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
RxCplDTrn_State_r1 <= RxCplDTrn_State;
end if;
end process;
-- ----------------------------------------------
-- States synchronous
--
Syn_RxTrn_States :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
RxCplDTrn_State <= ST_CplD_RESET;
elsif user_clk'event and user_clk = '1' then
RxCplDTrn_State <= RxCplDTrn_NextState;
end if;
end process;
-- Next States
Comb_RxTrn_NextStates :
process (
RxCplDTrn_State
, CplD_Type
, MSB_DSP_Tag
, m_axis_rx_tlast_i
, trn_rx_throttle
, Req_ID_Match_i
, Dex_Tag_Matched_i
)
begin
case RxCplDTrn_State is
when ST_CplD_RESET =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
when ST_CplD_IDLE =>
if trn_rx_throttle = '0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when others =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_Cpl_HEAD2 => -- further processing to be done ...
RxCplDTrn_NextState <= ST_CplD_IDLE;
when ST_CplD_HEAD2 =>
if trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_HEAD2;
elsif Req_ID_Match_i = '1' and Dex_Tag_Matched_i = '1' then
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_AFetch_Special;
else
RxCplDTrn_NextState <= ST_CplD_AFetch;
end if;
elsif Req_ID_Match_i = '1' and MSB_DSP_Tag = '0' then
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_AFetch_Special;
else
RxCplDTrn_NextState <= ST_CplD_AFetch;
end if;
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_CplD_AFetch =>
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_ONLY_1DW;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_AFetch_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_1ST_DATA;
end if;
when ST_CplD_AFetch_Special =>
-- !!!!!!!!!!!!!!
-- Suppose 1DW CplD (sof-eof TLP) is not followed back-to-back
-- !!!!!!!!!!!!!!
RxCplDTrn_NextState <= ST_CplD_AFetch_Special_Tail;
when ST_CplD_AFetch_Special_Tail =>
if trn_rx_throttle = '0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when others =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_CplD_AFetch_THROTTLE =>
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_ONLY_1DW;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_AFetch_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_1ST_DATA;
end if;
when ST_CplD_ONLY_1DW =>
if trn_rx_throttle = '0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when others =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_CplD_1ST_DATA =>
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_1ST_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_1ST_DATA_THROTTLE =>
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_1ST_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_DATA =>
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_DATA_THROTTLE =>
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_LAST_DATA => -- Same as IDLE, to support
-- back-to-back transactions
if trn_rx_throttle = '0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when others =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when others =>
RxCplDTrn_NextState <= ST_CplD_RESET;
end case;
end process;
-- -------------------------------------------------
-- Synchronous Registered: Tag_Map_Clear_i
--
RxTrn_Tag_Map_Clear :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Tag_Map_Clear_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
for j in 0 to C_TAG_MAP_WIDTH-1 loop
-- CplD_Tag(C_TAG_WIDTH-2) used as token of BAR
if CplD_Tag(C_TAG_WIDTH-1) = '0'
and CplD_Tag(C_TAG_WIDTH-2-1 downto 0) = CONV_STD_LOGIC_VECTOR(j, C_TAG_WIDTH-2)
and CplD_is_the_Last = '1' then
Tag_Map_Clear_i(j) <= '1';
else
Tag_Map_Clear_i(j) <= '0';
end if;
end loop;
end if;
end process;
-- -------------------------------------------------
-- Synchronous Registered: CplD_Length
--
RxTrn_CplD_Length :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
CplD_Length <= (others => '0');
CplD_is_1DW <= '0';
Small_CplD <= '0';
Small_CplD_r1 <= '0';
elsif user_clk'event and user_clk = '1' then
Small_CplD_r1 <= Small_CplD;
if trn_rsof_n_i = '0' then
CplD_Length <= Tlp_has_4KB & m_axis_rx_tdata_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
CplD_is_1DW <= Tlp_has_1DW;
if m_axis_rx_tdata_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT+2) = C_ALL_ZEROS(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT+2)
and m_axis_rx_tdata_i(C_TLP_LENG_BIT_BOT+1 downto C_TLP_LENG_BIT_BOT) /= "00"
and m_axis_rx_tdata_i(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) = "01" -- Cpl/D
then
Small_CplD <= '1';
else
Small_CplD <= '0';
end if;
else
CplD_Length <= CplD_Length;
CplD_is_1DW <= CplD_is_1DW;
Small_CplD <= Small_CplD;
end if;
end if;
end process;
-- -------------------------------------------------
-- Synchronous outputs: Addr_Inc
--
RxFSM_Output_Addr_Inc :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Addr_Inc <= '1';
elsif user_clk'event and user_clk = '1' then
case RxCplDTrn_State_r1 is
when ST_CplD_RESET =>
Addr_Inc <= '1';
when ST_CplD_1ST_DATA =>
Addr_Inc <= tRAM_DoutA_r1(CBIT_AINC_IN_TAGRAM);
when ST_CplD_ONLY_1DW =>
Addr_Inc <= tRAM_DoutA_r1(CBIT_AINC_IN_TAGRAM);
when others =>
Addr_Inc <= Addr_Inc;
end case;
end if;
end process;
-------------------------------------------------
-- Calculation at trn_rsof_n
--
Syn_Dex_wrAddress :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Reg_WrAddr_if_last_us <= (others => '0'); -- C_REGS_BASE_ADDR;
Reg_WrAddr_if_last_ds <= (others => '0'); -- C_REGS_BASE_ADDR;
elsif user_clk'event and user_clk = '1' then
if trn_rsof_n_i = '0' then
Reg_WrAddr_if_last_us(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_CTRL, C_EP_AWIDTH-2-2)
- m_axis_rx_tdata_i(C_NEXT_BD_LENG_MSB downto 0);
Reg_WrAddr_if_last_ds(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_CTRL, C_EP_AWIDTH-2-2)
- m_axis_rx_tdata_i(C_NEXT_BD_LENG_MSB downto 0);
-- Reg_WrAddr_if_last_us(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_STA, C_EP_AWIDTH-2-2) - m_axis_rx_tdata_i(C_NEXT_BD_LENG_MSB downto 0);
-- Reg_WrAddr_if_last_ds(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_STA, C_EP_AWIDTH-2-2) - m_axis_rx_tdata_i(C_NEXT_BD_LENG_MSB downto 0);
else
Reg_WrAddr_if_last_us <= Reg_WrAddr_if_last_us;
Reg_WrAddr_if_last_ds <= Reg_WrAddr_if_last_ds;
end if;
end if;
end process;
-- ---------------------------------------------
-- Reg Synchronous: RegAddr_?s_Dex
--
RxFSM_Reg_RegAddr_xs_Dex :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
RegAddr_us_Dex <= (others => '1');
RegAddr_ds_Dex <= (others => '1');
elsif user_clk'event and user_clk = '1' then
if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) /= C_TAG0_DMA_USB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
RegAddr_us_Dex <= (others => '1');
elsif CplD_is_the_Last = '1' then -- us last/2nd dex
RegAddr_us_Dex <= Reg_WrAddr_if_last_us;
else -- us 1st/unique dex
RegAddr_us_Dex <= -- C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) & ,(C_DECODE_BIT_BOT-2)
-- CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_PAH, C_DECODE_BIT_BOT) & "00";
CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_PAH-1, C_DECODE_BIT_BOT) & "00";
end if;
if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) /= C_TAG0_DMA_DSB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
RegAddr_ds_Dex <= (others => '1');
elsif CplD_is_the_Last = '1' then -- ds last/2nd dex
RegAddr_ds_Dex <= Reg_WrAddr_if_last_ds;
else -- ds 1st/unique dex
RegAddr_ds_Dex <= -- C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) & ,(C_DECODE_BIT_BOT-2)
-- CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_PAH, C_DECODE_BIT_BOT) & "00";
CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_PAH-1, C_DECODE_BIT_BOT) & "00";
end if;
end if;
end process;
-- ---------------------------------------------
-- Reg Synchronous Delay: CplD_Tag_on_Dex
--
RxFSM_Delay_CplD_Tag_on_Dex :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
CplD_Tag_on_Dex <= '0';
elsif user_clk'event and user_clk = '1' then
if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) = C_TAG0_DMA_USB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
CplD_Tag_on_Dex <= '1';
elsif CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) = C_TAG0_DMA_DSB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
CplD_Tag_on_Dex <= '1';
else
CplD_Tag_on_Dex <= '0';
end if;
end if;
end process;
-------------------------------------------------------
-- Synchronous outputs: DMA_Registers
--
RxFSM_Output_DMA_Registers :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_AFetch =>
if CplD_Tag_on_Dex = '1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= "10";
Regs_WrDin_i <= m_axis_rx_tdata_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
end if;
when ST_CplD_AFetch_Special =>
if CplD_Tag_on_Dex = '1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= "10";
Regs_WrDin_i <= m_axis_rx_tdata_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
end if;
when ST_CplD_1ST_DATA =>
if CplD_Tag_on_Dex = '1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= m_axis_rx_tdata_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
end if;
when ST_CplD_ONLY_1DW =>
if CplD_Tag_on_Dex = '1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= m_axis_rx_tdata_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
end if;
when ST_CplD_DATA =>
if CplD_Tag_on_Dex = '1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= '0' & not(m_axis_rx_tkeep_r1(3) and m_axis_rx_tkeep_r1(0));
Regs_WrDin_i <= m_axis_rx_tdata_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
end if;
when ST_CplD_LAST_DATA =>
if CplD_Tag_on_Dex = '1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= '0' & not(m_axis_rx_tkeep_r1(3) and m_axis_rx_tkeep_r1(0));
Regs_WrDin_i <= m_axis_rx_tdata_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
end if;
when others =>
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
end case;
end if;
end process;
-------------------------------------------------------
-- Synchronous outputs: DMA_Registers write Address
--
RxFSM_Output_DMA_Registers_WrAddr :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Regs_WrAddr_i <= (others => '1');
elsif user_clk'event and user_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_IDLE =>
Regs_WrAddr_i <= (others => '1');
when ST_CplD_AFetch =>
Regs_WrAddr_i <= RegAddr_us_Dex and RegAddr_ds_Dex;
when ST_CplD_AFetch_Special =>
Regs_WrAddr_i <= RegAddr_us_Dex and RegAddr_ds_Dex;
when ST_CplD_1ST_DATA =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
+ CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when ST_CplD_ONLY_1DW =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
+ CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when ST_CplD_DATA =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
+ CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when ST_CplD_LAST_DATA =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
+ CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when others =>
Regs_WrAddr_i <= Regs_WrAddr_i;
end case;
end if;
end process;
-----------------------------------------------------
-- Synchronous Register:
-- dsDMA_dex_Tag_i
-- usDMA_dex_Tag_i
--
FSM_Reg_DMA_dex_Tags :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
usDMA_dex_Tag_i <= C_TAG0_DMA_USB;
dsDMA_dex_Tag_i <= C_TAG0_DMA_DSB;
elsif user_clk'event and user_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_AFetch =>
if m_axis_rx_tdata_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT) = usDMA_dex_Tag_i and CplD_is_the_Last = '1' then
usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
end if;
if m_axis_rx_tdata_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT) = dsDMA_dex_Tag_i and CplD_is_the_Last = '1' then
dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
end if;
when ST_CplD_AFetch_Special =>
if m_axis_rx_tdata_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT) = usDMA_dex_Tag_i and CplD_is_the_Last = '1' then
usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
end if;
if m_axis_rx_tdata_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT) = dsDMA_dex_Tag_i and CplD_is_the_Last = '1' then
dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
end if;
when others =>
usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
end case;
end if;
end process;
-- -------------------------------------------------------------
-- RAM holding downstream Tags of packet MRd requests
-- -------------------------------------------------------------
tRAM_addra <= CplD_Tag(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_weB_i(0) <= tRAM_weB;
dspTag_BRAM :
generic_dpram
generic map(
g_data_width => 36,
g_size => 64,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_init_file => "none",
g_dual_clock => false)
port map(
rst_n_i => '1',
clka_i => user_clk,
clkb_i => user_clk,
wea_i => tRAM_wea(0) ,
aa_i => tRAM_addra ,
da_i => tRAM_dina ,
qa_o => tRAM_doutA ,
web_i => tRAM_weB_i(0) ,
ab_i => tRAM_addrB ,
db_i => tRAM_dinB ,
qb_o => open
);
-- Synchronous delay: CplD_is_the_Last
--
Syn_Delay_CplD_is_the_Last :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
CplD_is_the_Last_r1 <= CplD_is_the_Last;
end if;
end process;
-- -----------------------------------------------------------------------------------
-- Synchronous output: Updates_tRAM
-- Update happens only at data TLP
-- The last CplD of one MRd does not trigger tRAM update,
-- to enable back-to-back transactions.
--
RxFSM_Output_Updates_tRAM :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Updates_tRAM <= '0';
elsif user_clk'event and user_clk = '1' then
Updates_tRAM <= CplD_State_is_AFetch
and (DSP_Tag_on_RAM_r1 or DSP_Tag_on_FIFO_r1)
-- and not trn_rx_throttle -- m_axis_rx_tvalid_r1
and not CplD_is_the_Last_r1;
end if;
end process;
-- -----------------------------------------------------------------------------------
-- Synchronous output: Update_was_too_late
-- For 1DW CplD the update might be too late for the
-- next CplD with the same TAG
--
RxFSM_Output_Update_was_too_late :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Update_was_too_late <= '0';
hazard_tag <= (others => '1');
tag_matches_hazard <= '0';
hazard_update <= '0';
hazard_update_r1 <= '0';
hazard_update_r2 <= '0';
hazard_update_r3 <= '0';
elsif user_clk'event and user_clk = '1' then
if Small_CplD_r1 = '1' and CplD_State_is_after_AFetch = '1' then
hazard_update <= '1';
hazard_tag <= CplD_Tag;
else
hazard_update <= '0';
hazard_tag <= hazard_tag;
end if;
if CplD_Tag = hazard_tag then
tag_matches_hazard <= '1';
else
tag_matches_hazard <= '0';
end if;
hazard_update_r1 <= hazard_update;
hazard_update_r2 <= hazard_update_r1;
hazard_update_r3 <= hazard_update_r2;
-- Update_was_too_late <= hazard_update_r1 or hazard_update_r2 or hazard_update_r3;
Update_was_too_late <= hazard_update or hazard_update_r1 or hazard_update_r2 or hazard_update_r3;
end if;
end process;
-- ---------------------------------------------
-- Delay Synchronous Delay: Updates_tRAM
--
RxFSM_Delay_Updates_tRAM :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Updates_tRAM_r1 <= Updates_tRAM;
end if;
end process;
-- ---------------------------------------------
-- Synchronous Delay: tRAM_DoutA_r2
--
Delay_tRAM_DoutA :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
if Update_was_too_late = '1' and tag_matches_hazard = '1' then
tRAM_DoutA_r1 <= hazard_content;
else
tRAM_DoutA_r1 <= tRAM_doutA;
end if;
tRAM_DoutA_r2 <= tRAM_DoutA_r1;
end if;
end process;
-- ---------------------------------------------
-- Synchronous Output: hazard_content
--
Syn_Reg_hazard_content :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
hazard_content <= (others => '1');
elsif user_clk'event and user_clk = '1' then
if tRAM_wea(0) = '1' then
hazard_content <= tRAM_dina;
else
hazard_content <= hazard_content;
end if;
end if;
end process;
-- ---------------------------------------------
-- Synchronous Calculation: tRAM_dina_aInc
--
Syn_Calc_tRAM_dina_aInc :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
tRAM_dina_aInc <= (CBIT_AINC_IN_TAGRAM => '1',
others => '0'
);
elsif user_clk'event and user_clk = '1' then
tRAM_dina_aInc(C_TAGBAR_BIT_TOP downto C_TAGBAR_BIT_BOT) <= tRAM_DoutA_r1(C_TAGBAR_BIT_TOP downto C_TAGBAR_BIT_BOT);
tRAM_dina_aInc(C_TAGBAR_BIT_BOT-1 downto 0) <= tRAM_DoutA_r1(C_TAGBAR_BIT_BOT-1 downto 0) --C_EP_AWIDTH !!!!!
+ CplD_Leng_in_Bytes_r1(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
end if;
end process;
tRAM_wea(0) <= Updates_tRAM_r1;
tRAM_dina <= tRAM_dina_aInc;
-- tRAM_dina <= ('1' & tRAM_dina_aInc(C_TAGRAM_DWIDTH-1-1 downto 0))
-- when Addr_Inc='1'
-- else ('0' & tRAM_DoutA_r2(C_TAGRAM_DWIDTH-1-1 downto 0));
-- ---------------------------------------------
-- Synchronous Calculation: tRAM_DoutA_latch
--
Syn_tRAM_DoutA_latch :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
tRAM_DoutA_latch <= (CBIT_AINC_IN_TAGRAM => '1', others => '0');
elsif user_clk'event and user_clk = '1' then
if CplD_State_is_AFetch_r1 = '0' then
tRAM_DoutA_latch <= tRAM_DoutA_latch;
elsif Update_was_too_late = '1' then
tRAM_DoutA_latch <= tRAM_DoutA_r1;
else
tRAM_DoutA_latch <= tRAM_DoutA;
end if;
end if;
end process;
-- -------------------------------------------------
-- Synchronous outputs: DDR_Space_Hit
--
RxFSM_Output_DDR_Space_Hit :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
DDR_Space_Hit <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (others => '0');
DDR_wr_din_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
case RxCplDTrn_State_r1 is
when ST_CplD_RESET =>
DDR_Space_Hit <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (others => '0');
DDR_wr_din_i <= (others => '0');
when ST_CplD_AFetch =>
if m_axis_rx_tlast_r4 = '1' then
DDR_Space_Hit <= DSP_Tag_on_RAM_r1;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= DSP_Tag_on_RAM_r4p;
DDR_wr_v_i <= DSP_Tag_on_RAM_r4p; -- DSP_Tag_on_RAM; -- and not (trn_rx_throttle_r4 and not m_axis_rx_tlast_r4);
DDR_wr_Shift_i <= '0';
DDR_wr_din_i <= m_axis_rx_tdata_Little_r4;
DDR_wr_Mask_i <= '1' & not(m_axis_rx_tkeep_r4(3) and m_axis_rx_tkeep_r4(0));
elsif DSP_Tag_on_RAM_r1 = '1' then
DDR_Space_Hit <= '1';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0'; -- not trn_rx_throttle_r1;
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (others => '0');
DDR_wr_din_i <= (others => '0');
else
DDR_Space_Hit <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (others => '0');
DDR_wr_din_i <= (others => '0');
end if;
when ST_CplD_AFetch_Special =>
if DSP_Tag_on_RAM_r1 = '1' then
DDR_Space_Hit <= '1';
else
DDR_Space_Hit <= '0';
end if;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= m_axis_rx_tlast_r4 and DDR_Space_Hit;
DDR_wr_v_i <= (not (trn_rx_throttle_r4 and not m_axis_rx_tlast_r4)) and DDR_Space_Hit;
DDR_wr_Shift_i <= '0';
DDR_wr_din_i <= m_axis_rx_tdata_Little_r4;
DDR_wr_Mask_i <= '1' & not(m_axis_rx_tkeep_r4(3) and m_axis_rx_tkeep_r4(0));
when ST_CplD_AFetch_Special_Tail =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= DDR_Space_Hit; -- '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= DDR_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
DDR_wr_Mask_i <= (others => '0');
if Update_was_too_late = '1' and tag_matches_hazard = '1' then
DDR_wr_Shift_i <= not hazard_content(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
else
DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when ST_CplD_AFetch_THROTTLE =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (others => '0');
DDR_wr_din_i <= DDR_wr_din_i;
when ST_CplD_1ST_DATA =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= DDR_Space_Hit; -- '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= DDR_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
DDR_wr_Mask_i <= (others => '0');
if Update_was_too_late = '1' and tag_matches_hazard = '1' then
DDR_wr_Shift_i <= not hazard_content(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
elsif CplD_State_is_AFetch_r1 = '0' then
DDR_wr_Shift_i <= not tRAM_DoutA_latch(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
else
DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when ST_CplD_ONLY_1DW =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= DDR_Space_Hit; -- '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= DDR_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
DDR_wr_Mask_i <= (others => '0');
if Update_was_too_late = '1' and tag_matches_hazard = '1' then
DDR_wr_Shift_i <= not hazard_content(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
elsif CplD_State_is_AFetch_r1 = '0' then
DDR_wr_Shift_i <= not tRAM_DoutA_latch(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
else
DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when others =>
if m_axis_rx_tlast_r4 = '1' then
DDR_Space_Hit <= '0';
else
DDR_Space_Hit <= DDR_Space_Hit;
end if;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= m_axis_rx_tlast_r4 and DDR_Space_Hit;
DDR_wr_v_i <= (DDR_wr_sof_i or not (trn_rx_throttle_r4 and not m_axis_rx_tlast_r4)) and DDR_Space_Hit;
DDR_wr_Shift_i <= '0';
DDR_wr_din_i <= m_axis_rx_tdata_Little_r4;
if DDR_wr_sof_i = '1' then
DDR_wr_Mask_i <= "01";
else
DDR_wr_Mask_i <= not(m_axis_rx_tkeep_r4(4)) & not(m_axis_rx_tkeep_r4(0));
end if;
end case;
end if;
end process;
concat_rd <= m_axis_rx_tdata_r3(31 downto 0) & m_axis_rx_tdata_r4(63 downto 32);
-- -------------------------------------------------
-- Synchronous outputs: wb_FIFO_Write
--
RxFSM_Output_FIFO_Space_Hit :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
FIFO_Space_Hit <= '0';
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= '0';
wb_FIFO_din_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
case RxCplDTrn_State_r1 is
when ST_CplD_RESET =>
FIFO_Space_Hit <= '0';
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= '0';
wb_FIFO_din_i <= (others => '0');
when ST_CplD_AFetch =>
if DSP_Tag_on_FIFO_r1 = '1' then
FIFO_Space_Hit <= '1';
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= '0';
wb_FIFO_din_i <= (others => '0');
else
FIFO_Space_Hit <= '0';
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= '0';
wb_FIFO_din_i <= (others => '0');
end if;
when ST_CplD_AFetch_Special =>
if DSP_Tag_on_FIFO_r1 = '1' then
FIFO_Space_Hit <= '1';
else
FIFO_Space_Hit <= '0';
end if;
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= m_axis_rx_tlast_r4 and FIFO_Space_Hit;
wb_FIFO_we_i <= (not (trn_rx_throttle_r4 and not m_axis_rx_tlast_r4)) and FIFO_Space_Hit;
when ST_CplD_AFetch_Special_Tail =>
FIFO_Space_Hit <= FIFO_Space_Hit;
wb_FIFO_wsof_i <= FIFO_Space_Hit; -- '1';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= FIFO_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
if Update_was_too_late = '1' and tag_matches_hazard = '1' then
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
else
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when ST_CplD_AFetch_THROTTLE =>
FIFO_Space_Hit <= FIFO_Space_Hit;
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= '0';
wb_FIFO_din_i <= wb_FIFO_din_i;
when ST_CplD_1ST_DATA =>
FIFO_Space_Hit <= FIFO_Space_Hit;
wb_FIFO_wsof_i <= FIFO_Space_Hit; -- '1';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= FIFO_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
if Update_was_too_late = '1' and tag_matches_hazard = '1' then
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
elsif CplD_State_is_AFetch_r1 = '0' then
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
else
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when ST_CplD_ONLY_1DW =>
FIFO_Space_Hit <= FIFO_Space_Hit;
wb_FIFO_wsof_i <= FIFO_Space_Hit; -- '1';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= FIFO_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
if Update_was_too_late = '1' and tag_matches_hazard = '1' then
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
elsif CplD_State_is_AFetch_r1 = '0' then
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
else
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when others =>
if m_axis_rx_tlast_r3 = '1' then
FIFO_Space_Hit <= '0';
else
FIFO_Space_Hit <= FIFO_Space_Hit;
end if;
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= m_axis_rx_tlast_r3 and FIFO_Space_Hit;
wb_FIFO_we_i <= (wb_FIFO_wsof_i or not (trn_rx_throttle_r3 and not m_axis_rx_tlast_r3)) and FIFO_Space_Hit;
wb_FIFO_din_i <= Endian_Invert_64(concat_rd);
end case;
end if;
end process;
-- ---------------------------------
-- Regenerate trn_rsof_n signal as in old TRN core
--
TRN_rsof_n_make :
process (user_clk, user_reset)
begin
if user_reset = '1' then
in_packet_reg <= '0';
elsif rising_edge(user_clk) then
if (m_axis_rx_tvalid and m_axis_rx_tready) = '1' then
in_packet_reg <= not(m_axis_rx_tlast);
end if;
end if;
end process;
trn_rsof_n_i <= not(m_axis_rx_tvalid and not(in_packet_reg));
end architecture Behavioral;
| lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd | 1 | 14502 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.fmc150_pkg.all;
entity fmc150_testbench is
generic(
g_sim : integer := 0
);
port
(
rst : in std_logic;
clk_100Mhz : in std_logic;
clk_200Mhz : in std_logic;
adc_clk_ab_p : in std_logic;
adc_clk_ab_n : in std_logic;
-- Start Simulation Only!
sim_adc_clk_i : in std_logic;
sim_adc_clk2x_i : in std_logic;
-- End of Simulation Only!
adc_cha_p : in std_logic_vector(6 downto 0);
adc_cha_n : in std_logic_vector(6 downto 0);
adc_chb_p : in std_logic_vector(6 downto 0);
adc_chb_n : in std_logic_vector(6 downto 0);
-- Start Simulation Only!
sim_adc_cha_data_i : in std_logic_vector(13 downto 0);
sim_adc_chb_data_i : in std_logic_vector(13 downto 0);
-- End of Simulation Only!
dac_dclk_p : out std_logic;
dac_dclk_n : out std_logic;
dac_data_p : out std_logic_vector(7 downto 0);
dac_data_n : out std_logic_vector(7 downto 0);
dac_frame_p : out std_logic;
dac_frame_n : out std_logic;
txenable : out std_logic;
--clk_to_fpga_p : in std_logic;
--clk_to_fpga_n : in std_logic;
--ext_trigger_p : in std_logic;
--ext_trigger_n : in std_logic;
spi_sclk : out std_logic;
spi_sdata : out std_logic;
rd_n_wr : in std_logic;
addr : in std_logic_vector(15 downto 0);
idata : in std_logic_vector(31 downto 0);
odata : out std_logic_vector(31 downto 0);
busy : out std_logic;
cdce72010_valid : in std_logic;
ads62p49_valid : in std_logic;
dac3283_valid : in std_logic;
amc7823_valid : in std_logic;
external_clock : in std_logic;
adc_n_en : out std_logic;
adc_sdo : in std_logic;
adc_reset : out std_logic;
cdce_n_en : out std_logic;
cdce_sdo : in std_logic;
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
dac_n_en : out std_logic;
dac_sdo : in std_logic;
mon_n_en : out std_logic;
mon_sdo : in std_logic;
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
prsnt_m2c_l : in std_logic;
adc_delay_update_i : in std_logic;
adc_str_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_cha_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_chb_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_str_cntvalueout_o : out std_logic_vector(4 downto 0);
adc_dout_o : out std_logic_vector(31 downto 0);
clk_adc_o : out std_logic;
mmcm_adc_locked_o : out std_logic
);
end fmc150_testbench;
architecture rtl of fmc150_testbench is
----------------------------------------------------------------------------------------------------
-- Constant declaration
----------------------------------------------------------------------------------------------------
constant ADC_STR_IDELAY : integer := 0; -- Initial number of delay taps on ADC clock input
constant ADC_CHA_IDELAY : integer := 0; -- Initial number of delay taps on ADC data port A
constant ADC_CHB_IDELAY : integer := 0; -- Initial number of delay taps on ADC data port B
----------------------------------------------------------------------------------------------------
-- Signal declaration
----------------------------------------------------------------------------------------------------
signal clk_ab_l : std_logic;
signal clk_ab_dly : std_logic;
signal adc_cha_ddr : std_logic_vector(6 downto 0); -- Double Data Rate
signal adc_cha_ddr_dly : std_logic_vector(6 downto 0); -- Double Data Rate, Delayed
signal adc_cha_sdr : std_logic_vector(13 downto 0); -- Single Data Rate
signal adc_chb_ddr : std_logic_vector(6 downto 0); -- Double Data Rate
signal adc_chb_ddr_dly : std_logic_vector(6 downto 0); -- Double Data Rate, Delayed
signal adc_chb_sdr : std_logic_vector(13 downto 0); -- Single Data Rate
signal adc_dout_a : std_logic_vector(15 downto 0); -- Single Data Rate, Extended to 16-bit
signal adc_dout_b : std_logic_vector(15 downto 0); -- Single Data Rate, Extended to 16-bit
signal adc_str : std_logic;
signal clk_adc : std_logic;
signal mmcm_adc_locked : std_logic;
signal fmc150_ctrl_in : t_fmc150_ctrl_in;
signal fmc150_ctrl_out : t_fmc150_ctrl_out;
signal clk_to_fpga : std_logic;
signal clk_adc_2x : std_logic;
signal dac_din_c : std_logic_vector(15 downto 0);
signal dac_din_d : std_logic_vector(15 downto 0);
signal adc_str_fbin, adc_str_out, adc_str_2x_out, adc_str_fbout : std_logic;
-- simulation only
signal toggle_ff_q : std_logic := '0';
signal toggle_ff_d : std_logic := '0';
begin
-- Synthesis Only
gen_clk : if (g_sim = 0) generate
-- I/O delay control
cmp_idelayctrl : idelayctrl
port map
(
rst => rst,
refclk => clk_200MHz,
rdy => open
);
-- ADC Clock PLL
cmp_mmcm_adc : MMCM_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 16.000,
--CLKFBOUT_MULT_F => 8.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 16.000,
--CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 8,
--CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
-- 61.44 MHZ input clock
CLKIN1_PERIOD => 16.276,
-- 122.88 MHZ input clock
--CLKIN1_PERIOD => 8.138,
REF_JITTER1 => 0.010,
-- Not used. Just to bypass Xilinx errors
-- Just input 61.44 MHz input clock
CLKIN2_PERIOD => 16.276,
REF_JITTER2 => 0.010
)
port map
(
-- Output clocks
CLKFBOUT => adc_str_fbout,
CLKFBOUTB => open,
CLKOUT0 => adc_str_out,
CLKOUT0B => open,
CLKOUT1 => adc_str_2x_out,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => adc_str_fbin,
CLKIN1 => adc_str,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_adc_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => rst
);
-- Global clock buffers for "cmp_mmcm_adc" instance
cmp_clkf_bufg : BUFG
port map
(
O => adc_str_fbin,
I => adc_str_fbout
);
cmp_adc_str_out_bufg : BUFG
port map
(
O => clk_adc,
I => adc_str_out
);
cmp_adc_str_2x_out_bufg : BUFG
port map
(
O => clk_adc_2x,
I => adc_str_2x_out
);
end generate;
-- Double clock circuit. only for SIMULATION!
gen_clk_sim : if (g_sim = 1) generate
clk_adc <= sim_adc_clk_i;
clk_adc_2x <= sim_adc_clk2x_i;
end generate;
clk_adc_o <= clk_adc;--adc_str;
-- ADC Interface
cmp_adc_if : fmc150_adc_if
generic map(
g_sim => g_sim
)
port map
(
--clk_200MHz_i => clk_200MHz,
clk_100MHz_i => clk_100MHz,
rst_i => mmcm_adc_locked,
str_p_i => adc_clk_ab_p,
str_n_i => adc_clk_ab_n,
cha_p_i => adc_cha_p,
cha_n_i => adc_cha_n,
chb_p_i => adc_chb_p,
chb_n_i => adc_chb_n,
cha_data_o => adc_cha_sdr,
chb_data_o => adc_chb_sdr,
str_o => adc_str,
-- Not used for now. Should it be removed?
clk_adc_i => adc_str,--clk_adc,
delay_update_i => adc_delay_update_i,
str_cntvalue_i => adc_str_cntvaluein_i,
cha_cntvalue_i => adc_cha_cntvaluein_i,
chb_cntvalue_i => adc_chb_cntvaluein_i,
str_cntvalue_o => adc_str_cntvalueout_o
);
-- Extend to 16-bit and register ADC data output
-- p_extend_adc_output : process (clk_adc)
-- begin
-- if (rising_edge(clk_adc)) then
gen_data : if (g_sim = 0) generate
p_extend_adc_output : process (adc_str)
begin
if (rising_edge(adc_str)) then
-- Left justify the data of both channels on 16-bits
adc_dout_a <= adc_cha_sdr(13) & adc_cha_sdr(13) & adc_cha_sdr;
adc_dout_b <= adc_chb_sdr(13) & adc_chb_sdr(13) & adc_chb_sdr;
-- adc_dout_a <= std_logic_vector(unsigned(adc_dout_a)+1);
-- adc_dout_b <= std_logic_vector(unsigned(adc_dout_b)-1);
end if;
end process;
end generate;
gen_data_sim : if (g_sim = 1) generate
adc_dout_a <= sim_adc_cha_data_i(13) & sim_adc_cha_data_i(13) & sim_adc_cha_data_i;
adc_dout_b <= sim_adc_chb_data_i(13) & sim_adc_chb_data_i(13) & sim_adc_chb_data_i;
end generate;
adc_dout_o <= adc_dout_a & adc_dout_b;
--adc_dout_o <= dac_din_c & dac_din_d;
-- DAC Interface
cmp_dac_if : fmc150_dac_if
port map
(
rst_i => mmcm_adc_locked,
clk_dac_i => clk_adc,
clk_dac_2x_i => clk_adc_2x,
dac_din_c_i => dac_din_c,
dac_din_d_i => dac_din_d,
dac_data_p_o => dac_data_p,
dac_data_n_o => dac_data_n,
dac_dclk_p_o => dac_dclk_p,
dac_dclk_n_o => dac_dclk_n,
dac_frame_p_o => dac_frame_p,
dac_frame_n_o => dac_frame_n,
txenable_o => txenable
);
mmcm_adc_locked_o <= mmcm_adc_locked;
-- Reference signal generation (need external netlist file)
-- cmp_sin_cos : sin_cos
-- port map
-- (
-- clk => clk_adc,
-- cosine => dac_din_c,
-- sine => dac_din_d,
-- phase_out => open
-- );
-- FMC150 control (SPI and direct signals)
cmp_fmc150_ctrl : fmc150_spi_ctrl
generic map(
g_sim => g_sim
)
port map
(
rst => rst,
clk => clk_100MHz,
rd_n_wr => rd_n_wr,
addr => addr,
idata => idata,
odata => odata,
busy => busy,
cdce72010_valid => cdce72010_valid,
ads62p49_valid => ads62p49_valid,
dac3283_valid => dac3283_valid,
amc7823_valid => amc7823_valid,
external_clock => external_clock,
adc_n_en => adc_n_en,
adc_sdo => adc_sdo,
adc_reset => adc_reset,
cdce_n_en => cdce_n_en,
cdce_sdo => cdce_sdo,
cdce_n_reset => cdce_n_reset,
cdce_n_pd => cdce_n_pd,
ref_en => ref_en,
pll_status => pll_status,
dac_n_en => dac_n_en,
dac_sdo => dac_sdo,
mon_n_en => mon_n_en,
mon_sdo => mon_sdo,
mon_n_reset => mon_n_reset,
mon_n_int => mon_n_int,
spi_sclk => spi_sclk,
spi_sdata => spi_sdata,
prsnt_m2c_l => prsnt_m2c_l
);
end rtl;
| lgpl-3.0 |
Ttl/bf_cpu | control.vhd | 1 | 7949 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.bfconfig.all;
entity control is
Port ( clk, reset : in STD_LOGIC;
d_jumpf : in STD_LOGIC;
d_jumpb : in STD_LOGIC;
d_write : in STD_LOGIC;
d_read : in STD_LOGIC;
c_skip : out STD_LOGIC;
alu_z : in STD_LOGIC;
pc_out : out pctype;
uart_tx_end : in STD_LOGIC;
uart_rx_ready : in STD_LOGIC);
end control;
architecture Behavioral of control is
-- It takes two cycles to reverse the direction
type modetype is (M_RESET, M_RUN, M_JUMPF1, M_JUMPF2, M_JUMPB1, M_RXWAIT);
signal mode, mode_next : modetype := M_RESET;
signal pc : pctype := (others => '0');
signal pc_next : std_logic_vector(INST_MEM_SIZE downto 0);
signal pc_cache, pc_cache_next : pctype;
signal pc_overflow : std_logic;
signal brackets, brackets_next : unsigned(7 downto 0);
-- PC stack signals
signal stack_push_notpop : std_logic;
signal stack_enable : std_logic;
signal stack_pc : pctype;
-- Jumpf cache signals
signal cache_push, cache_valid : std_logic;
signal cache_out : pctype;
signal cache_ready, cache_ready_next : std_logic;
-- Skip one instruction when skipping instructions with jumpf cache
signal skip, skip_next : std_logic;
--pragma synthesis_off
signal mispredict, mispredict_next : unsigned(31 downto 0) := to_unsigned(0,32);
signal predict, predict_next : unsigned(31 downto 0) := to_unsigned(0,32);
signal cache_miss, cache_miss_next : unsigned(31 downto 0) := to_unsigned(0,32);
signal cache_hit, cache_hit_next : unsigned(31 downto 0) := to_unsigned(0,32);
signal cache_ready_prev : std_logic;
--pragma synthesis_on
begin
-- Stack for storing the program counter for faster return from branches
pcstack : entity work.stack
Port map( clk => clk,
reset => reset,
enable => stack_enable,
push_notpop => stack_push_notpop,
pcin => pc,
pcout => stack_pc
);
jumpf_cache: entity work.cache
Generic map(WIDTH => INST_MEM_SIZE, -- Length of address
DWIDTH => INST_MEM_SIZE, -- Length of one entry
CACHE_SIZE => JUMPF_CACHE_SIZE) -- Log2 of number of entries in the cache
Port map( clk => clk,
reset => reset,
addr => pc_cache,
din => pc,
push => cache_push,
valid => cache_valid,
dout => cache_out
);
pc_out <= pc_next(INST_MEM_SIZE-1 downto 0);
process(clk, mode_next, pc_next, pc_cache_next)
begin
if rising_edge(clk) then
if reset = '1' then
mode <= M_RESET;
else
mode <= mode_next;
end if;
-- Program ended enter infinite loop
if pc_overflow = '1' then
pc <= pc;
else
pc <= pc_next(INST_MEM_SIZE-1 downto 0);
end if;
pc_cache <= pc_cache_next;
brackets <= brackets_next;
cache_ready <= cache_ready_next;
skip <= skip_next;
--pragma synthesis_off
predict <= predict_next;
mispredict <= mispredict_next;
cache_hit <= cache_hit_next;
cache_miss <= cache_miss_next;
cache_ready_prev <= cache_ready;
--pragma synthesis_on
end if;
end process;
process(mode, pc, d_jumpf, d_jumpb, d_write, d_read,
stack_pc, alu_z, pc_cache, uart_tx_end, uart_rx_ready,
brackets, cache_valid, cache_ready, cache_out, skip)
begin
stack_push_notpop <= '0';
cache_push <= '0';
cache_ready_next <= '0';
c_skip <= '0';
brackets_next <= brackets;
pc_next <= std_logic_vector(unsigned('0'&pc)+1);
pc_overflow <= pc_next(INST_MEM_SIZE);
-- Save next PC so we can get back where we were
-- if jump was predicted incorrectly
pc_cache_next <= pc_cache;
mode_next <= M_RUN;
skip_next <= '0';
stack_enable <= '0';
case mode is
when M_RESET =>
pc_cache_next <= (others => '0');
brackets_next <= to_unsigned(0,8);
c_skip <= '1';
pc_next <= (others => '0');
mode_next <= M_RUN;
if d_write = '1' then
mode_next <= M_RUN;
elsif d_read = '1' then
mode_next <= M_RXWAIT;
elsif d_jumpf = '1' then
mode_next <= M_JUMPF2;
-- ] shouldn't never be first instruction
end if;
when M_JUMPF1 =>
if d_jumpf = '1' then
-- Two consecutive jumps, we need to push both of them to stack
stack_push_notpop <= '1';
stack_enable <= '1';
brackets_next <= brackets + 1;
end if;
if alu_z = '1' then
c_skip <= '1';
stack_push_notpop <= '0';
stack_enable <= '1';
mode_next <= M_JUMPF2;
else
-- Infinite loop, but do what we are told to do
if d_jumpb = '1' then
pc_next <= '0'&pc_cache;
end if;
mode_next <= M_RUN;
end if;
when M_JUMPF2 =>
-- Readying cache takes two clock cycles
cache_ready_next <= '1';
mode_next <= M_JUMPF2;
c_skip <= '1';
if d_jumpf = '1' then
brackets_next <= brackets + 1;
elsif d_jumpb = '1' then
brackets_next <= brackets - 1;
if brackets = 0 then
-- Store jump end address to speed up future jumps
cache_push <= '1';
mode_next <= M_RUN;
end if;
end if;
if cache_valid = '1' and cache_ready = '1' then
-- Skip the next instruction
--pragma synthesis_off
cache_hit_next <= cache_hit+1;
cache_miss_next <= cache_miss;
--pragma synthesis_on
skip_next <= '1';
mode_next <= M_RUN;
pc_next <= '0'&cache_out;
--pragma synthesis_off
elsif cache_ready = '1' and cache_ready_prev = '0' then
-- We need to check previous cache_ready value
-- to avoid double counting
cache_hit_next <= cache_hit;
cache_miss_next <= cache_miss+1;
--pragma synthesis_on
end if;
when M_JUMPB1 =>
mode_next <= M_RUN;
if alu_z = '1' then
--pragma synthesis_off
mispredict_next <= mispredict + 1;
predict_next <= predict;
--pragma synthesis_on
stack_push_notpop <= '0';
stack_enable <= '1';
c_skip <= '1';
-- Necessary
skip_next <= '1';
pc_next <= '0'&pc_cache;
else
--pragma synthesis_off
mispredict_next <= mispredict;
predict_next <= predict + 1;
--pragma synthesis_on
end if;
when M_RUN =>
brackets_next <= to_unsigned(0,8);
if d_jumpf = '1' then
-- Jump forward
pc_cache_next <= pc;
mode_next <= M_JUMPF1;
stack_push_notpop <= '1';
stack_enable <= '1';
elsif d_jumpb = '1' and skip = '0' then
pc_cache_next <= pc;
pc_next <= '0'&stack_pc;
-- We need to check alu_z on the next cycle
mode_next <= M_JUMPB1;
elsif d_write = '1' then
if uart_tx_end = '0' then
c_skip <= '1';
pc_next <= '0'&pc;
mode_next <= M_RUN;
else
mode_next <= M_RUN;
end if;
elsif d_read = '1' then
pc_next <= '0'&pc;
mode_next <= M_RXWAIT;
end if;
when M_RXWAIT =>
pc_next <= '0'&pc;
mode_next <= M_RXWAIT;
if uart_rx_ready = '1' then
pc_next <= std_logic_vector(unsigned('0'&pc)+1);
mode_next <= M_RUN;
end if;
end case;
end process;
end Behavioral;
| lgpl-3.0 |
gtaylormb/opl3_fpga | fpga/modules/clks/ip/clk_gen/clk_gen_stub.vhdl | 1 | 1128 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.1 (lin64) Build 1538259 Fri Apr 8 15:45:23 MDT 2016
-- Date : Mon Jun 6 23:00:45 2016
-- Host : edinburgh running 64-bit Ubuntu 15.04
-- Command : write_vhdl -force -mode synth_stub
-- /home/greg/opl3_fpga_vivado_project/opl3_fpga_vivado_project.srcs/sources_1/ip/clk_gen/clk_gen_stub.vhdl
-- Design : clk_gen
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_gen is
Port (
clk125 : in STD_LOGIC;
clk : out STD_LOGIC;
clk_locked : out STD_LOGIC
);
end clk_gen;
architecture stub of clk_gen is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk125,clk,clk_locked";
begin
end;
| lgpl-3.0 |
gtaylormb/opl3_fpga | fpga/modules/clks/ip/clk_gen/clk_gen_sim_netlist.vhdl | 1 | 6740 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.1 (lin64) Build 1538259 Fri Apr 8 15:45:23 MDT 2016
-- Date : Mon Jun 6 23:00:46 2016
-- Host : edinburgh running 64-bit Ubuntu 15.04
-- Command : write_vhdl -force -mode funcsim
-- /home/greg/opl3_fpga_vivado_project/opl3_fpga_vivado_project.srcs/sources_1/ip/clk_gen/clk_gen_sim_netlist.vhdl
-- Design : clk_gen
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_gen_clk_gen_clk_wiz is
port (
clk125 : in STD_LOGIC;
clk : out STD_LOGIC;
clk_locked : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_gen_clk_gen_clk_wiz : entity is "clk_gen_clk_wiz";
end clk_gen_clk_gen_clk_wiz;
architecture STRUCTURE of clk_gen_clk_gen_clk_wiz is
signal clk125_clk_gen : STD_LOGIC;
signal clk_clk_gen : STD_LOGIC;
signal clkfbout_clk_gen : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk125,
O => clk125_clk_gen
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_clk_gen,
O => clk
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "HIGH",
CLKFBOUT_MULT_F => 53.375000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 8.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 87.375000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 6,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_clk_gen,
CLKFBOUT => clkfbout_clk_gen,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk125_clk_gen,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_clk_gen,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => clk_locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_gen is
port (
clk125 : in STD_LOGIC;
clk : out STD_LOGIC;
clk_locked : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_gen : entity is true;
end clk_gen;
architecture STRUCTURE of clk_gen is
begin
inst: entity work.clk_gen_clk_gen_clk_wiz
port map (
clk => clk,
clk125 => clk125,
clk_locked => clk_locked
);
end STRUCTURE;
| lgpl-3.0 |
sahandKashani/Altera-FPGA-top-level-files | DE1-SoC/DE1_SoC_top_level.vhd | 1 | 5944 | -- #############################################################################
-- DE1_SoC_top_level.vhd
-- =====================
--
-- BOARD : DE1-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.7
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE1_SoC_top_level is
port(
-- ADC
ADC_CS_n : out std_logic;
ADC_DIN : out std_logic;
ADC_DOUT : in std_logic;
ADC_SCLK : out std_logic;
-- Audio
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK : inout std_logic;
AUD_BCLK : inout std_logic;
AUD_DACDAT : out std_logic;
AUD_DACLRCK : inout std_logic;
AUD_XCK : out std_logic;
-- CLOCK
CLOCK_50 : in std_logic;
CLOCK2_50 : in std_logic;
CLOCK3_50 : in std_logic;
CLOCK4_50 : in std_logic;
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_LDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_WE_N : out std_logic;
-- I2C for Audio and Video-In
FPGA_I2C_SCLK : out std_logic;
FPGA_I2C_SDAT : inout std_logic;
-- SEG7
HEX0_N : out std_logic_vector(6 downto 0);
HEX1_N : out std_logic_vector(6 downto 0);
HEX2_N : out std_logic_vector(6 downto 0);
HEX3_N : out std_logic_vector(6 downto 0);
HEX4_N : out std_logic_vector(6 downto 0);
HEX5_N : out std_logic_vector(6 downto 0);
-- IR
IRDA_RXD : in std_logic;
IRDA_TXD : out std_logic;
-- KEY_N
KEY_N : in std_logic_vector(3 downto 0);
-- LED
LEDR : out std_logic_vector(9 downto 0);
-- PS2
PS2_CLK : inout std_logic;
PS2_CLK2 : inout std_logic;
PS2_DAT : inout std_logic;
PS2_DAT2 : inout std_logic;
-- SW
SW : in std_logic_vector(9 downto 0);
-- Video-In
TD_CLK27 : inout std_logic;
TD_DATA : out std_logic_vector(7 downto 0);
TD_HS : out std_logic;
TD_RESET_N : out std_logic;
TD_VS : out std_logic;
-- VGA
VGA_B : out std_logic_vector(7 downto 0);
VGA_BLANK_N : out std_logic;
VGA_CLK : out std_logic;
VGA_G : out std_logic_vector(7 downto 0);
VGA_HS : out std_logic;
VGA_R : out std_logic_vector(7 downto 0);
VGA_SYNC_N : out std_logic;
VGA_VS : out std_logic;
-- GPIO_0
GPIO_0 : inout std_logic_vector(35 downto 0);
-- GPIO_1
GPIO_1 : inout std_logic_vector(35 downto 0);
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
HPS_FLASH_DCLK : out std_logic;
HPS_FLASH_NCSO : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C_CONTROL : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_I2C2_SCLK : inout std_logic;
HPS_I2C2_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE1_SoC_top_level;
architecture rtl of DE1_SoC_top_level is
begin
end;
| unlicense |
sahandKashani/Altera-FPGA-top-level-files | DE1-SoC/DE1_SoC_TRDB_D5M_LT24_top_level.vhd | 1 | 7056 | -- #############################################################################
-- DE1_SoC_TRDB_D5M_LT24_top_level.vhd
-- ===================================
--
-- BOARD : DE1-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.8
-- Last updated : 2017-06-11 12:48:26 UTC
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE1_SoC_TRDB_D5M_LT24_top_level is
port(
-- ADC
ADC_CS_n : out std_logic;
ADC_DIN : out std_logic;
ADC_DOUT : in std_logic;
ADC_SCLK : out std_logic;
-- Audio
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK : inout std_logic;
AUD_BCLK : inout std_logic;
AUD_DACDAT : out std_logic;
AUD_DACLRCK : inout std_logic;
AUD_XCK : out std_logic;
-- CLOCK
CLOCK_50 : in std_logic;
CLOCK2_50 : in std_logic;
CLOCK3_50 : in std_logic;
CLOCK4_50 : in std_logic;
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_LDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_WE_N : out std_logic;
-- I2C for Audio and Video-In
FPGA_I2C_SCLK : out std_logic;
FPGA_I2C_SDAT : inout std_logic;
-- SEG7
HEX0_N : out std_logic_vector(6 downto 0);
HEX1_N : out std_logic_vector(6 downto 0);
HEX2_N : out std_logic_vector(6 downto 0);
HEX3_N : out std_logic_vector(6 downto 0);
HEX4_N : out std_logic_vector(6 downto 0);
HEX5_N : out std_logic_vector(6 downto 0);
-- IR
IRDA_RXD : in std_logic;
IRDA_TXD : out std_logic;
-- KEY_N
KEY_N : in std_logic_vector(3 downto 0);
-- LED
LEDR : out std_logic_vector(9 downto 0);
-- PS2
PS2_CLK : inout std_logic;
PS2_CLK2 : inout std_logic;
PS2_DAT : inout std_logic;
PS2_DAT2 : inout std_logic;
-- SW
SW : in std_logic_vector(9 downto 0);
-- Video-In
TD_CLK27 : inout std_logic;
TD_DATA : out std_logic_vector(7 downto 0);
TD_HS : out std_logic;
TD_RESET_N : out std_logic;
TD_VS : out std_logic;
-- VGA
VGA_B : out std_logic_vector(7 downto 0);
VGA_BLANK_N : out std_logic;
VGA_CLK : out std_logic;
VGA_G : out std_logic_vector(7 downto 0);
VGA_HS : out std_logic;
VGA_R : out std_logic_vector(7 downto 0);
VGA_SYNC_N : out std_logic;
VGA_VS : out std_logic;
-- GPIO_0
GPIO_0_D5M_D : in std_logic_vector(11 downto 0);
GPIO_0_D5M_FVAL : in std_logic;
GPIO_0_D5M_LVAL : in std_logic;
GPIO_0_D5M_PIXCLK : in std_logic;
GPIO_0_D5M_RESET_N : out std_logic;
GPIO_0_D5M_SCLK : inout std_logic;
GPIO_0_D5M_SDATA : inout std_logic;
GPIO_0_D5M_STROBE : in std_logic;
GPIO_0_D5M_TRIGGER : out std_logic;
GPIO_0_D5M_XCLKIN : out std_logic;
-- GPIO_1
GPIO_1_LT24_ADC_BUSY : in std_logic;
GPIO_1_LT24_ADC_CS_N : out std_logic;
GPIO_1_LT24_ADC_DCLK : out std_logic;
GPIO_1_LT24_ADC_DIN : out std_logic;
GPIO_1_LT24_ADC_DOUT : in std_logic;
GPIO_1_LT24_ADC_PENIRQ_N : in std_logic;
GPIO_1_LT24_CS_N : out std_logic;
GPIO_1_LT24_D : out std_logic_vector(15 downto 0);
GPIO_1_LT24_LCD_ON : out std_logic;
GPIO_1_LT24_RD_N : out std_logic;
GPIO_1_LT24_RESET_N : out std_logic;
GPIO_1_LT24_RS : out std_logic;
GPIO_1_LT24_WR_N : out std_logic;
-- HPS
HPS_CONV_USB_N : inout std_logic;
HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
HPS_DDR3_BA : out std_logic_vector(2 downto 0);
HPS_DDR3_CAS_N : out std_logic;
HPS_DDR3_CK_N : out std_logic;
HPS_DDR3_CK_P : out std_logic;
HPS_DDR3_CKE : out std_logic;
HPS_DDR3_CS_N : out std_logic;
HPS_DDR3_DM : out std_logic_vector(3 downto 0);
HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
HPS_DDR3_ODT : out std_logic;
HPS_DDR3_RAS_N : out std_logic;
HPS_DDR3_RESET_N : out std_logic;
HPS_DDR3_RZQ : in std_logic;
HPS_DDR3_WE_N : out std_logic;
HPS_ENET_GTX_CLK : out std_logic;
HPS_ENET_INT_N : inout std_logic;
HPS_ENET_MDC : out std_logic;
HPS_ENET_MDIO : inout std_logic;
HPS_ENET_RX_CLK : in std_logic;
HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
HPS_ENET_RX_DV : in std_logic;
HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
HPS_ENET_TX_EN : out std_logic;
HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
HPS_FLASH_DCLK : out std_logic;
HPS_FLASH_NCSO : out std_logic;
HPS_GSENSOR_INT : inout std_logic;
HPS_I2C_CONTROL : inout std_logic;
HPS_I2C1_SCLK : inout std_logic;
HPS_I2C1_SDAT : inout std_logic;
HPS_I2C2_SCLK : inout std_logic;
HPS_I2C2_SDAT : inout std_logic;
HPS_KEY_N : inout std_logic;
HPS_LED : inout std_logic;
HPS_LTC_GPIO : inout std_logic;
HPS_SD_CLK : out std_logic;
HPS_SD_CMD : inout std_logic;
HPS_SD_DATA : inout std_logic_vector(3 downto 0);
HPS_SPIM_CLK : out std_logic;
HPS_SPIM_MISO : in std_logic;
HPS_SPIM_MOSI : out std_logic;
HPS_SPIM_SS : inout std_logic;
HPS_UART_RX : in std_logic;
HPS_UART_TX : out std_logic;
HPS_USB_CLKOUT : in std_logic;
HPS_USB_DATA : inout std_logic_vector(7 downto 0);
HPS_USB_DIR : in std_logic;
HPS_USB_NXT : in std_logic;
HPS_USB_STP : out std_logic
);
end entity DE1_SoC_TRDB_D5M_LT24_top_level;
architecture rtl of DE1_SoC_TRDB_D5M_LT24_top_level is
begin
end;
| unlicense |
8l/luz-cpu | experimental/luz_uc/luz_uc_testbench/uc_unit_tb/uc_top_tb.vhd | 2 | 613 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
entity luz_uc_tb is end;
architecture luz_uc_tb_arc of luz_uc_tb is
signal clk: std_logic := '0';
signal reset_n: std_logic;
signal halt: std_logic;
begin
clk <= not clk after 14 ns;
reset_n <= '0', '1' after 100 ns;
process
begin
wait;
end process;
dut: entity work.luz_uc(luz_uc_arc)
port map
(
clk => clk,
reset_n => reset_n,
halt => halt
);
end;
| unlicense |
8l/luz-cpu | experimental/luz_uc/luz_uc_rtl/uc/uc_top.vhd | 2 | 5743 | -- Luz uC top-level entity
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
entity luz_uc is
port
(
clk: in std_logic;
reset_n: in std_logic;
-- '1' when the CPU executes the 'halt' instruction
--
halt: out std_logic
);
end luz_uc;
architecture luz_uc_arc of luz_uc is
signal cpu_cyc_o: std_logic;
signal cpu_stb_o: std_logic;
signal cpu_we_o: std_logic;
signal cpu_sel_o: std_logic_vector(3 downto 0);
signal cpu_adr_o: word;
signal cpu_data_o: word;
signal cpu_ack_i: std_logic;
signal cpu_err_i: std_logic;
signal cpu_data_i: word;
signal cpu_irq_i: word;
signal cpu_halt: std_logic;
signal cpu_ifetch: std_logic;
signal cpu_core_reg_read_sel: core_reg_sel;
signal cpu_core_reg_read_data: word;
signal cpu_core_reg_write_sel: core_reg_sel;
signal cpu_core_reg_write_strobe: std_logic;
signal cpu_core_reg_write_data: word;
signal mem_cyc_i: std_logic;
signal mem_stb_i: std_logic;
signal mem_we_i: std_logic;
signal mem_sel_i: std_logic_vector(3 downto 0);
signal mem_adr_i: std_logic_vector(MEM_ADDR_SIZE - 1 downto 0);
signal mem_data_i: word;
signal mem_ack_o: std_logic;
signal mem_err_o: std_logic;
signal mem_data_o: word;
signal core_reg_cyc_i: std_logic;
signal core_reg_stb_i: std_logic;
signal core_reg_we_i: std_logic;
signal core_reg_sel_i: std_logic_vector(3 downto 0);
signal core_reg_adr_i: std_logic_vector(11 downto 0);
signal core_reg_data_i: word;
signal core_reg_ack_o: std_logic;
signal core_reg_err_o: std_logic;
signal core_reg_data_o: word;
begin
cpu_map: entity work.luz_cpu(luz_cpu_arc)
generic map
(
RESET_ADDRESS => MEM_ADDR_START
)
port map
(
clk => clk,
reset_n => reset_n,
cyc_o => cpu_cyc_o,
stb_o => cpu_stb_o,
we_o => cpu_we_o,
sel_o => cpu_sel_o,
adr_o => cpu_adr_o,
data_o => cpu_data_o,
ack_i => cpu_ack_i,
err_i => cpu_err_i,
data_i => cpu_data_i,
irq_i => cpu_irq_i,
halt => cpu_halt,
ifetch => cpu_ifetch,
core_reg_read_sel => cpu_core_reg_read_sel,
core_reg_read_data => cpu_core_reg_read_data,
core_reg_write_sel => cpu_core_reg_write_sel,
core_reg_write_strobe => cpu_core_reg_write_strobe,
core_reg_write_data => cpu_core_reg_write_data
);
memorymapper_map: entity work.memorymapper(memorymapper_arc)
port map
(
clk => clk,
reset_n => reset_n,
cpu_cyc_o => cpu_cyc_o,
cpu_stb_o => cpu_stb_o,
cpu_we_o => cpu_we_o,
cpu_sel_o => cpu_sel_o,
cpu_adr_o => cpu_adr_o,
cpu_data_o => cpu_data_o,
cpu_ack_i => cpu_ack_i,
cpu_err_i => cpu_err_i,
cpu_data_i => cpu_data_i,
mem_cyc_i => mem_cyc_i,
mem_stb_i => mem_stb_i,
mem_we_i => mem_we_i,
mem_sel_i => mem_sel_i,
mem_adr_i => mem_adr_i,
mem_data_i => mem_data_i,
mem_ack_o => mem_ack_o,
mem_err_o => mem_err_o,
mem_data_o => mem_data_o,
core_reg_cyc_i => core_reg_cyc_i,
core_reg_stb_i => core_reg_stb_i,
core_reg_we_i => core_reg_we_i,
core_reg_sel_i => core_reg_sel_i,
core_reg_adr_i => core_reg_adr_i,
core_reg_data_i => core_reg_data_i,
core_reg_ack_o => core_reg_ack_o,
core_reg_err_o => core_reg_err_o,
core_reg_data_o => core_reg_data_o
);
core_regs_map: entity work.core_regs(core_regs_arc)
port map
(
clk => clk,
reset_n => reset_n,
read_port_sel => cpu_core_reg_read_sel,
read_port_out => cpu_core_reg_read_data,
write_port_sel => cpu_core_reg_write_sel,
write_port_wr => cpu_core_reg_write_strobe,
write_port_in => cpu_core_reg_write_data,
ack_o => core_reg_ack_o,
err_o => core_reg_err_o,
cyc_i => core_reg_cyc_i,
stb_i => core_reg_stb_i,
we_i => core_reg_we_i,
sel_i => core_reg_sel_i,
adr_i => core_reg_adr_i,
data_o => core_reg_data_o,
data_i => core_reg_data_i
);
user_memory_map: entity work.user_memory(user_memory_arc)
port map
(
clk => clk,
reset_n => reset_n,
cyc_i => mem_cyc_i,
stb_i => mem_stb_i,
we_i => mem_we_i,
sel_i => mem_sel_i,
adr_i => mem_adr_i,
data_i => mem_data_i,
data_o => mem_data_o,
ack_o => mem_ack_o,
err_o => mem_err_o
);
end;
| unlicense |
EJDomi/pixel-dtb-firmware-readout-chain-master | dtb/ram_init.vhd | 2 | 14501 | -- megafunction wizard: %RAM initializer%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMEM_INIT
-- ============================================================
-- File Name: ram_init.vhd
-- Megafunction Name(s):
-- ALTMEM_INIT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altmem_init CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone III" INIT_TO_ZERO="YES" NUMWORDS=256 PORT_ROM_DATA_READY="PORT_UNUSED" ROM_READ_LATENCY=1 WIDTH=8 WIDTHAD=8 clock dataout init init_busy ram_address ram_wren
--VERSION_BEGIN 12.1SP1 cbx_altmem_init 2013:01:31:18:04:58:SJ cbx_altsyncram 2013:01:31:18:04:59:SJ cbx_cycloneii 2013:01:31:18:04:59:SJ cbx_lpm_add_sub 2013:01:31:18:04:59:SJ cbx_lpm_compare 2013:01:31:18:04:59:SJ cbx_lpm_counter 2013:01:31:18:04:59:SJ cbx_lpm_decode 2013:01:31:18:04:59:SJ cbx_lpm_mux 2013:01:31:18:04:59:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:04:59:SJ cbx_stratixii 2013:01:31:18:04:59:SJ cbx_stratixiii 2013:01:31:18:05:00:SJ cbx_stratixv 2013:01:31:18:05:00:SJ cbx_util_mgl 2013:01:31:18:04:59:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_compare 2 lpm_counter 2 reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ram_init_meminit_m6k IS
PORT
(
clock : IN STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
init : IN STD_LOGIC;
init_busy : OUT STD_LOGIC;
ram_address : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
ram_wren : OUT STD_LOGIC
);
END ram_init_meminit_m6k;
ARCHITECTURE RTL OF ram_init_meminit_m6k IS
SIGNAL capture_init : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL prev_state : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_prev_state_w_lg_w_q_range41w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_prev_state_w_lg_w_q_range40w42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_prev_state_w_q_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_prev_state_w_q_range41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_d : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL state_reg : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_state_reg_sclr : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL wire_state_reg_sload : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL wire_state_reg_w_lg_w_q_range2w7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_lg_w_q_range1w3w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_lg_w_q_range22w24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_lg_w_q_range31w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_q_range1w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_q_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_q_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_state_reg_w_q_range31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_cmpr_aeb : STD_LOGIC;
SIGNAL wire_addr_cmpr_alb : STD_LOGIC;
SIGNAL wire_addr_cmpr_datab : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_wait_cmpr_aeb : STD_LOGIC;
SIGNAL wire_wait_cmpr_alb : STD_LOGIC;
SIGNAL wire_gnd_vector : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_addr_ctr_cnt_en : STD_LOGIC;
SIGNAL wire_addr_ctr_q : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_wait_ctr_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_wait_ctr_sclr : STD_LOGIC;
SIGNAL wire_w_lg_ram_addr_state44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_init38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL addrct_eq_numwords : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL addrct_lt_numwords : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL clken : STD_LOGIC;
SIGNAL done_state : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL idle_state : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL ram_addr_state : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL ram_write_state : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL reset_state_machine : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL state_machine_clken : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL waitct_eq_latency : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL waitct_lt_latency : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT lpm_counter
GENERIC
(
lpm_avalue : STRING := "0";
lpm_direction : STRING := "DEFAULT";
lpm_modulus : NATURAL := 0;
lpm_port_updown : STRING := "PORT_CONNECTIVITY";
lpm_pvalue : STRING := "0";
lpm_svalue : STRING := "0";
lpm_width : NATURAL;
lpm_type : STRING := "lpm_counter"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aload : IN STD_LOGIC := '0';
aset : IN STD_LOGIC := '0';
cin : IN STD_LOGIC := '1';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
cnt_en : IN STD_LOGIC := '1';
cout : OUT STD_LOGIC;
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
eq : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
sclr : IN STD_LOGIC := '0';
sload : IN STD_LOGIC := '0';
sset : IN STD_LOGIC := '0';
updown : IN STD_LOGIC := '1'
);
END COMPONENT;
BEGIN
wire_gnd_vector <= "0";
wire_w_lg_init38w(0) <= init OR capture_init(0);
addrct_eq_numwords(0) <= wire_addr_cmpr_aeb;
addrct_lt_numwords(0) <= wire_addr_cmpr_alb;
clken <= '1';
dataout <= (OTHERS => '0');
done_state(0) <= (state_reg(1) AND state_reg(0));
idle_state(0) <= ((NOT state_reg(1)) AND wire_state_reg_w_lg_w_q_range1w3w(0));
init_busy <= capture_init(0);
ram_addr_state(0) <= ((NOT state_reg(1)) AND state_reg(0));
ram_address <= wire_addr_ctr_q;
ram_wren <= ((NOT prev_state(1)) AND prev_state(0));
ram_write_state(0) <= wire_state_reg_w_lg_w_q_range2w7w(0);
reset_state_machine(0) <= (ram_write_state(0) AND addrct_lt_numwords(0));
state_machine_clken(0) <= (clken AND (((idle_state(0) AND capture_init(0)) OR (done_state(0) AND waitct_eq_latency(0))) OR (capture_init(0) AND (((NOT (ram_addr_state(0) AND waitct_lt_latency(0))) OR (ram_addr_state(0) AND waitct_eq_latency(0))) OR (ram_write_state(0) AND addrct_eq_numwords(0))))));
waitct_eq_latency(0) <= wire_wait_cmpr_aeb;
waitct_lt_latency(0) <= wire_wait_cmpr_alb;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN capture_init(0) <= (wire_w_lg_init38w(0) AND (NOT done_state(0)));
END IF;
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN
IF (clken = '1') THEN prev_state <= state_reg;
END IF;
END IF;
END PROCESS;
wire_prev_state_w_lg_w_q_range41w43w(0) <= wire_prev_state_w_q_range41w(0) AND wire_prev_state_w_lg_w_q_range40w42w(0);
wire_prev_state_w_lg_w_q_range40w42w(0) <= NOT wire_prev_state_w_q_range40w(0);
wire_prev_state_w_q_range40w(0) <= prev_state(0);
wire_prev_state_w_q_range41w(0) <= prev_state(1);
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN
IF (state_machine_clken(0) = '1') THEN
IF (wire_state_reg_sclr(0) = '1') THEN state_reg(0) <= '0';
ELSIF (wire_state_reg_sload(0) = '1') THEN state_reg(0) <= '1';
ELSE state_reg(0) <= wire_state_reg_d(0);
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF (clock = '1' AND clock'event) THEN
IF (state_machine_clken(0) = '1') THEN
IF (wire_state_reg_sclr(1) = '1') THEN state_reg(1) <= '0';
ELSIF (wire_state_reg_sload(1) = '1') THEN state_reg(1) <= '1';
ELSE state_reg(1) <= wire_state_reg_d(1);
END IF;
END IF;
END IF;
END PROCESS;
wire_state_reg_d <= ( wire_state_reg_w_lg_w_q_range31w33w & wire_state_reg_w_lg_w_q_range22w24w);
wire_state_reg_sclr <= ( reset_state_machine & "0");
wire_state_reg_sload <= ( "0" & reset_state_machine);
wire_state_reg_w_lg_w_q_range2w7w(0) <= wire_state_reg_w_q_range2w(0) AND wire_state_reg_w_lg_w_q_range1w3w(0);
wire_state_reg_w_lg_w_q_range1w3w(0) <= NOT wire_state_reg_w_q_range1w(0);
wire_state_reg_w_lg_w_q_range22w24w(0) <= NOT wire_state_reg_w_q_range22w(0);
wire_state_reg_w_lg_w_q_range31w33w(0) <= wire_state_reg_w_q_range31w(0) XOR wire_state_reg_w_q_range22w(0);
wire_state_reg_w_q_range1w(0) <= state_reg(0);
wire_state_reg_w_q_range2w(0) <= state_reg(1);
wire_state_reg_w_q_range22w(0) <= state_reg(0);
wire_state_reg_w_q_range31w(0) <= state_reg(1);
wire_addr_cmpr_datab <= (OTHERS => '1');
addr_cmpr : lpm_compare
GENERIC MAP (
LPM_WIDTH => 8
)
PORT MAP (
aeb => wire_addr_cmpr_aeb,
alb => wire_addr_cmpr_alb,
dataa => wire_addr_ctr_q,
datab => wire_addr_cmpr_datab
);
wait_cmpr : lpm_compare
GENERIC MAP (
LPM_WIDTH => 1
)
PORT MAP (
aeb => wire_wait_cmpr_aeb,
alb => wire_wait_cmpr_alb,
dataa => wire_wait_ctr_q,
datab => wire_gnd_vector
);
wire_addr_ctr_cnt_en <= wire_prev_state_w_lg_w_q_range41w43w(0);
addr_ctr : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 256,
lpm_port_updown => "PORT_UNUSED",
lpm_width => 8
)
PORT MAP (
clk_en => clken,
clock => clock,
cnt_en => wire_addr_ctr_cnt_en,
q => wire_addr_ctr_q,
sclr => idle_state(0)
);
wire_wait_ctr_sclr <= wire_w_lg_ram_addr_state44w(0);
wire_w_lg_ram_addr_state44w(0) <= NOT ram_addr_state(0);
wait_ctr : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 1,
lpm_port_updown => "PORT_UNUSED",
lpm_width => 1
)
PORT MAP (
clk_en => clken,
clock => clock,
cnt_en => ram_addr_state(0),
q => wire_wait_ctr_q,
sclr => wire_wait_ctr_sclr
);
END RTL; --ram_init_meminit_m6k
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ram_init IS
PORT
(
clock : IN STD_LOGIC ;
init : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
init_busy : OUT STD_LOGIC ;
ram_address : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
ram_wren : OUT STD_LOGIC
);
END ram_init;
ARCHITECTURE RTL OF ram_init IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC ;
COMPONENT ram_init_meminit_m6k
PORT (
clock : IN STD_LOGIC ;
dataout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
init : IN STD_LOGIC ;
init_busy : OUT STD_LOGIC ;
ram_address : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
ram_wren : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
dataout <= sub_wire0(7 DOWNTO 0);
init_busy <= sub_wire1;
ram_address <= sub_wire2(7 DOWNTO 0);
ram_wren <= sub_wire3;
ram_init_meminit_m6k_component : ram_init_meminit_m6k
PORT MAP (
clock => clock,
init => init,
dataout => sub_wire0,
init_busy => sub_wire1,
ram_address => sub_wire2,
ram_wren => sub_wire3
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: INIT_FILE STRING "UNUSED"
-- Retrieval info: CONSTANT: INIT_TO_ZERO STRING "YES"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmem_init"
-- Retrieval info: CONSTANT: NUMWORDS NUMERIC "256"
-- Retrieval info: CONSTANT: PORT_ROM_DATA_READY STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: ROM_READ_LATENCY NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTHAD NUMERIC "8"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: USED_PORT: dataout 0 0 8 0 OUTPUT NODEFVAL "dataout[7..0]"
-- Retrieval info: CONNECT: dataout 0 0 8 0 @dataout 0 0 8 0
-- Retrieval info: USED_PORT: init 0 0 0 0 INPUT NODEFVAL "init"
-- Retrieval info: CONNECT: @init 0 0 0 0 init 0 0 0 0
-- Retrieval info: USED_PORT: init_busy 0 0 0 0 OUTPUT NODEFVAL "init_busy"
-- Retrieval info: CONNECT: init_busy 0 0 0 0 @init_busy 0 0 0 0
-- Retrieval info: USED_PORT: ram_address 0 0 8 0 OUTPUT NODEFVAL "ram_address[7..0]"
-- Retrieval info: CONNECT: ram_address 0 0 8 0 @ram_address 0 0 8 0
-- Retrieval info: USED_PORT: ram_wren 0 0 0 0 OUTPUT NODEFVAL "ram_wren"
-- Retrieval info: CONNECT: ram_wren 0 0 0 0 @ram_wren 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init_inst.vhd TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.inc TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_init.cmp TRUE TRUE
-- Retrieval info: LIB_FILE: lpm
| unlicense |
TWW12/lzw | final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_2048_0/bram_2048_0_stub.vhdl | 2 | 1477 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:18 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_2048_0/bram_2048_0_stub.vhdl
-- Design : bram_2048_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bram_2048_0 is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
end bram_2048_0;
architecture stub of bram_2048_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[10:0],dina[19:0],douta[19:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
| unlicense |
Lyrositor/insa | 3if/ac/tp-ac_1/counter.vhdl | 1 | 1562 | -- counter
-- An N-bit counter, with reset functionality.
library ieee;
use ieee.std_logic_1164.all;
library work;
entity counter is
generic(n: integer);
port(
clk, reset: in std_logic;
count: out std_logic_vector(n-1 downto 0)
);
end entity;
architecture behaviorial of counter is
component adder is
generic(n: integer);
port(
x: in std_logic_vector(n-1 downto 0);
y: in std_logic_vector(n-1 downto 0);
cin: in std_logic;
s: out std_logic_vector(n-1 downto 0);
cout: out std_logic
);
end component;
component register_n is
generic(n: integer);
port(
clk, enable, reset: in std_logic;
d: in std_logic_vector(n-1 downto 0);
q: out std_logic_vector(n-1 downto 0)
);
end component;
signal adder_to_register: std_logic_vector(n-1 downto 0);
signal cout: std_logic;
signal enable: std_logic;
signal temp_count: std_logic_vector(n-1 downto 0);
signal zero: std_logic_vector(n-1 downto 0);
begin
zero <= (n-1 downto 0 => '0');
adder_instance: adder
generic map(n => n)
port map(x => temp_count, y => zero, s => adder_to_register, cin => '1', cout => cout);
register_bits_instance: register_n
generic map(n => n)
port map(clk => clk, enable => '1', reset => reset, d => adder_to_register, q => temp_count);
clock_process: process(clk)
begin
count <= temp_count;
end process;
end;
| unlicense |
hgunicamp/Mips8B | src_test/tests/simulacoes/test_Mips_Processor-j.vhdl | 1 | 3264 | -- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity test_processor is
End Entity test_processor;
Architecture test_general of test_processor is
Component Mips8B is
Port(Reset_n: In Std_Logic;
Clock: In Std_Logic;
MAddr: Out Std_Logic_Vector(7 downto 0);
MCmd: Out Std_Logic_Vector(1 downto 0);
MData: Out Std_Logic_Vector(7 downto 0);
SData: In Std_Logic_Vector(7 downto 0);
SCmdAccept: In Std_Logic);
End Component Mips8B;
Type Memory_Array is Array(Natural Range <>) of Std_Logic_Vector(7 downto 0);
Use Work.MIPS8B_Base.ocpIDLE_little;
Use Work.MIPS8B_Base.ocpWR_little;
Use Work.MIPS8B_Base.ocpRD_little;
Use Work.MIPS8B_Base.ocpNULL_little;
Use Work.MIPS8B_Base.ocpDVA_little;
Signal Reset_n: Std_Logic;
Signal Clock: Std_Logic := '0';
Signal Clock_Mem: Std_Logic := '0';
Signal MAddr: Std_Logic_Vector(7 downto 0);
Signal MCmd: Std_Logic_Vector(1 downto 0);
Signal MData: Std_Logic_Vector(7 downto 0);
Signal SData: Std_Logic_Vector(7 downto 0);
Signal SCmdAccept: Std_Logic;
Begin
Reset_n <= '1', '0' after 20 ns, '1' after 40 ns;
Clock <= not Clock after 10 ns;
Clock_Mem <= not Clock_Mem after 15 ns;
Memory: Process
Variable int_SCmdAccept: Std_Logic;
Variable address: Unsigned(7 downto 0);
Variable mem_int: Memory_Array(0 to 255) := (
"00001000", "00000000", "00000000", "00000100",
"00001000", "00000000", "00000000", "00000101",
"00001000", "00000000", "00000000", "00000110",
"00100000", "00000111", "00000000", "01001101",
"00001000", "00000000", "00000000", "00000001",
"00001000", "00000000", "00000000", "00000010",
"00001000", "00000000", "00000000", "00000111",
"00001000", "00000000", "00000000", "00001000",
Others => "00000000");
Begin
Wait Until Clock_Mem'Event and Clock_Mem='1';
Case MCmd is
When ocpWR_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
mem_int(to_integer(address)) := MData;
Else
int_SCmdAccept := ocpNULL_little;
End If;
SData <= "ZZZZZZZZ";
When ocpRD_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
SData <= mem_int(to_integer(address));
Else
int_SCmdAccept := ocpNULL_little;
End If;
When Others =>
int_SCmdAccept := ocpNULL_little;
SData <= "ZZZZZZZZ";
End Case;
SCmdAccept <= int_SCmdAccept;
End Process Memory;
DUV: Mips8B
Port Map( Reset_n => Reset_n,
Clock => Clock,
MAddr => MAddr,
MCmd => MCmd,
MData => MData,
SData => SData,
SCmdAccept => SCmdAccept);
End Architecture test_general;
Configuration general_test of test_processor is
For test_general
For DUV: Mips8B Use Configuration Work.Mips8B_struct_conf;
End For;
End For;
End Configuration general_test;
| unlicense |
frznchckn/polarbear | hw/cores/uart/hdl/vhdl/cntr.vhd | 1 | 1021 | --------------------------------------------------------------------------------
--|
--| Filename : cntr
--| Author : R. Friesenhahn
--| Origin Date : 20130906
--|
--------------------------------------------------------------------------------
--|
--| Abstract
--|
--|
--|
--------------------------------------------------------------------------------
--|
--| Modification History
--|
--|
--|
--------------------------------------------------------------------------------
--|
--| References
--|
--|
--|
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cntr is
generic (
CntrWidth : integer := 8
);
port (
Clk : in std_ulogic;
Rst : in std_ulogic;
En : in std_ulogic;
Clr : in std_ulogic;
CritValue : in std_ulogic_vector(CntrWidth-1 downto 0);
CntrValue : out std_ulogic_vector(CntrWidth-1 downto 0);
CntReached : out std_ulogic
);
end cntr;
| unlicense |
jza00425/SingleCycleARM | lab2/work/arm_core/_primary.vhd | 3 | 598 | library verilog;
use verilog.vl_types.all;
entity arm_core is
port(
inst_addr : out vl_logic_vector(29 downto 0);
mem_addr : out vl_logic_vector(29 downto 0);
mem_data_in : out vl_logic_vector(31 downto 0);
mem_write_en : out vl_logic_vector(3 downto 0);
halted : out vl_logic;
clk : in vl_logic;
rst_b : in vl_logic;
inst : in vl_logic_vector(31 downto 0);
mem_data_out : in vl_logic_vector(31 downto 0)
);
end arm_core;
| unlicense |
sgomez118/ASM-Software-Management | laravel/public/bootstrap/ace-builds-master/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| unlicense |
medevo/howdoi | VHDL/subtract_unsigned.vhd | 1 | 772 | -- How do I subtract two std_logic_vectors unsigned
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity alu is
Port ( in1 : in std_logic_vector(15 downto 0);
in2 : in std_logic_vector(15 downto 0);
clk : in STD_LOGIC; -- Just in case, this design is async
result : out std_logic_vector(15 downto 0));
end alu;
architecture Behavioral of alu is
begin
process(clk,in1,in2)
variable tmp_s_16 : SIGNED (15 downto 0);
variable tmp_l_16 : std_logic_vector(15 downto 0);
tmp_s_16 := x"0000";
tmp_l_16 := x"0000";
-- Unsigned Subtract
tmp_l_16 := STD_LOGIC_VECTOR(unsigned(in1) - unsigned(in2));
tmp_s_16 := signed(tmp_l_16);
result <= std_logic_vector(tmp_s_16);
end process;
end Behavioral; | unlicense |
simonspa/pixel-dtb-firmware | dtb/gl_dff4m.vhd | 2 | 3907 | -- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: gl_dff4m.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY gl_dff4m IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END gl_dff4m;
ARCHITECTURE SYN OF gl_dff4m IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 4
)
PORT MAP (
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL data[3..0]
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q 0 0 4 0
-- Retrieval info: CONNECT: @data 0 0 4 0 data 0 0 4 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff4m.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff4m.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff4m.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff4m.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL gl_dff4m_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part3/lpm_constant2.vhd | 1 | 3509 | -- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant2.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant2 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END lpm_constant2;
ARCHITECTURE SYN OF lpm_constant2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(0 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I2",
lpm_type => "LPM_CONSTANT",
lpm_width => 1
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "I2"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=I2"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]"
-- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part4/lpm_constant0.vhd | 2 | 3509 | -- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant0.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant0 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END lpm_constant0;
ARCHITECTURE SYN OF lpm_constant0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(0 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=i3",
lpm_type => "LPM_CONSTANT",
lpm_width => 1
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "i3"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=i3"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]"
-- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense |
simonspa/pixel-dtb-firmware | dtb/lpm_counter0.vhd | 2 | 4431 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter0.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter0 IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END lpm_counter0;
ARCHITECTURE SYN OF lpm_counter0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (29 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(29 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 30
)
PORT MAP (
aclr => aclr,
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "30"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense |
simonspa/pixel-dtb-firmware | dtb/ip/spi_master/spi_master_if.vhd | 3 | 5140 | --*****************************************************************************
--* Copyright (C) 2012 by Michael Fischer
--*
--* All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* 1. Redistributions of source code must retain the above copyright
--* notice, this list of conditions and the following disclaimer.
--* 2. Redistributions in binary form must reproduce the above copyright
--* notice, this list of conditions and the following disclaimer in the
--* documentation and/or other materials provided with the distribution.
--* 3. Neither the name of the author nor the names of its contributors may
--* be used to endorse or promote products derived from this software
--* without specific prior written permission.
--*
--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
--* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
--* SUCH DAMAGE.
--*
--*****************************************************************************
--* History:
--*
--* 26.08.2012 mifi First Version
--*****************************************************************************
--*****************************************************************************
--* DEFINE: Library *
--*****************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--*****************************************************************************
--* DEFINE: Entity *
--*****************************************************************************
entity spi_master_if is
port (
--
-- Avalon Slave bus
--
clk : in std_logic := '0';
reset : in std_logic := '0';
chipselect : in std_logic := '0';
address : in std_logic_vector(2 downto 0) := (others => '0');
write : in std_logic := '0';
writedata : in std_logic_vector(15 downto 0) := (others => '0');
read : in std_logic := '0';
readdata : out std_logic_vector(15 downto 0);
--
-- External bus
--
cs : out std_logic;
sclk : out std_logic;
mosi : out std_logic;
miso : in std_logic := '0'
);
end entity spi_master_if;
--*****************************************************************************
--* DEFINE: Architecture *
--*****************************************************************************
architecture syn of spi_master_if is
--
-- Define all constants here
--
--
-- Define all components which are included here
--
component spi_master_core is
port (
--
-- Avalon Slave bus
--
clk : in std_logic := '0';
reset : in std_logic := '0';
chipselect : in std_logic := '0';
address : in std_logic_vector(2 downto 0) := (others => '0');
write : in std_logic := '0';
writedata : in std_logic_vector(15 downto 0) := (others => '0');
read : in std_logic := '0';
readdata : out std_logic_vector(15 downto 0);
--
-- External bus
--
cs : out std_logic;
sclk : out std_logic;
mosi : out std_logic;
miso : in std_logic := '0'
);
end component spi_master_core;
--
-- Define all local signals (like static data) here
--
begin
inst_spi : spi_master_core
port map (
clk => clk,
reset => reset,
chipselect => chipselect,
address => address,
write => write,
writedata => writedata,
read => read,
readdata => readdata,
cs => cs,
sclk => sclk,
mosi => mosi,
miso => miso
);
end architecture syn;
-- *** EOF ***
| unlicense |
simonspa/pixel-dtb-firmware | dtb/lpm_counter3.vhd | 2 | 4425 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter3.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter3 IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END lpm_counter3;
ARCHITECTURE SYN OF lpm_counter3 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(1 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 2
)
PORT MAP (
aclr => aclr,
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL q[1..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense |
simonspa/pixel-dtb-firmware | dtb/ip/delay_out/prbs31x3.vhd | 3 | 2639 | -- pseudo random bit sequence with 31-bit register
-- CLK: max speed given by 2 random bits each clock cycle
-- RESET: reset the internal register all to 1
-- SPEED: the speed of the output
-- "11" output each clock cycle two random bits on Y
-- "10" output each clock cycle the same random bit on Y
-- "01" output every second clock cycle the same random bit on Y
-- "00" output every fourth clock cycle the same random bit on Y
-------------------------------------------------------------------
entity PRBS31 is
port (CLK: in bit;
RESET: in bit;
EN: in bit;
SPEED: in bit_vector(1 downto 0);
Y: out bit_vector(1 downto 0));
end PRBS31;
entity DIVIDER_FSM is
port (CLK: in bit;
SPEED: in bit_vector(1 downto 0);
Y: out bit);
end DIVIDER_FSM;
architecture PRBS31_ARCH of PRBS31 is
signal CIN: bit; -- Internal FF enable signal for Shift register
component DIVIDER_FSM is port(CLK: in bit; SPEED: in bit_vector(1 downto 0); Y: out bit); end component;
begin
-- CLOCK DIVIDER FSM
I0: DIVIDER_FSM port map(CLK,SPEED,CIN);
process(CLK,RESET)
variable REG: bit_vector(30 downto 0) := (others => '1');
begin
if RESET='1' then
REG := (others => '1');
elsif CLK'event and CLK='1' then
if EN='0' then
REG := (others => '1');
elsif CIN='1' then
if SPEED="11" then
REG := REG(28 downto 0) & (REG(30) xor REG(27)) & (REG(29) xor REG(26));
else
REG := REG(29 downto 0) & (REG(30) xor REG(27));
end if;
end if;
end if;
case SPEED is
when "11" => Y <= REG(30 downto 29);
when others => Y <= REG(30) & REG(30);
end case;
end process;
end PRBS31_ARCH;
architecture DIVIDER_FSM_ARCH of DIVIDER_FSM is
begin
FSM: process(CLK)
variable STATE: bit_vector(1 downto 0) := (others => '0');
variable DECISION: bit_vector(3 downto 0);
begin
-- change state
if CLK'event and CLK='1' then
DECISION := STATE & SPEED;
case DECISION is
when "1100" => STATE := "00";
when "0000" | "1101" => STATE := "01";
when "0001" | "0100" => STATE := "10";
when others => STATE := "11";
end case;
end if;
-- output depending on state
case STATE is
when "11" => Y <= '1';
when others => Y <= '0';
end case;
end process FSM;
end DIVIDER_FSM_ARCH;
| unlicense |
simonspa/pixel-dtb-firmware | dtb/g_or2x4.vhd | 2 | 4025 | -- megafunction wizard: %LPM_OR%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_or
-- ============================================================
-- File Name: g_or2x4.vhd
-- Megafunction Name(s):
-- lpm_or
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY g_or2x4 IS
PORT
(
data0x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END g_or2x4;
ARCHITECTURE SYN OF g_or2x4 IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_2D (1 DOWNTO 0, 3 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
sub_wire3 <= data0x(3 DOWNTO 0);
result <= sub_wire0(3 DOWNTO 0);
sub_wire1 <= data1x(3 DOWNTO 0);
sub_wire2(1, 0) <= sub_wire1(0);
sub_wire2(1, 1) <= sub_wire1(1);
sub_wire2(1, 2) <= sub_wire1(2);
sub_wire2(1, 3) <= sub_wire1(3);
sub_wire2(0, 0) <= sub_wire3(0);
sub_wire2(0, 1) <= sub_wire3(1);
sub_wire2(0, 2) <= sub_wire3(2);
sub_wire2(0, 3) <= sub_wire3(3);
lpm_or_component : lpm_or
GENERIC MAP (
lpm_size => 2,
lpm_type => "LPM_OR",
lpm_width => 4
)
PORT MAP (
data => sub_wire2,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CompactSymbol NUMERIC "0"
-- Retrieval info: PRIVATE: GateFunction NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: InputAsBus NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WidthInput NUMERIC "4"
-- Retrieval info: PRIVATE: nInput NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_OR"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: data0x 0 0 4 0 INPUT NODEFVAL data0x[3..0]
-- Retrieval info: USED_PORT: data1x 0 0 4 0 INPUT NODEFVAL data1x[3..0]
-- Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL result[3..0]
-- Retrieval info: CONNECT: @data 1 0 4 0 data0x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 1 4 0 data1x 0 0 4 0
-- Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL g_or2x4.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL g_or2x4.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL g_or2x4.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL g_or2x4.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL g_or2x4_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab1/part6a/char_7seg.vhd | 4 | 805 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY char_7seg IS
PORT ( C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Display : OUT STD_LOGIC_VECTOR(0 TO 6));
END char_7seg;
ARCHITECTURE Behavior OF char_7seg IS
BEGIN -- Behavior
-- from our truth table
-- B=C(0), A=C(1)
Display(0) <= C(0); -- SEG A
Display(1) <= ((NOT C(1)) AND (NOT C(0))) OR (C(1) AND C(0)); -- SEG B
Display(2) <= ((NOT C(1)) AND (NOT C(0))) OR (C(1) AND C(0)); -- SEG C
Display(3) <= C(1); -- SEG D
Display(4) <= C(1) AND C(0); -- SEG E
Display(5) <= C(0); -- SEG F
Display(6) <= C(1) AND C(0); -- SEG G
END Behavior; | unlicense |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part4/adder.vhd | 3 | 401 | library ieee;
USE ieee.std_logic_1164.all;
ENTITY adder IS
PORT (b : IN STD_LOGIC;
a : IN STD_LOGIC;
ci : IN STD_LOGIC;
co : OUT STD_LOGIC;
s : OUT STD_LOGIC) ;
END adder;
ARCHITECTURE Behavior OF adder IS
BEGIN
s <= (ci AND NOT a AND NOT b) OR (NOT ci AND a AND NOT b) OR (NOT ci AND NOT a AND b) OR (ci AND a AND b);
co <= (ci AND a) OR (ci AND b) OR (a AND b) ;
END Behavior; | unlicense |
OrganicMonkeyMotion/fpga_experiments | small_board/LABS/digital_logic/vhdl/lab2/part5/lpm_constant1.vhd | 2 | 3515 | -- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant1.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant1 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END lpm_constant1;
ARCHITECTURE SYN OF lpm_constant1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(0 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 0,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=i2",
lpm_type => "LPM_CONSTANT",
lpm_width => 1
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "i2"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=i2"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: result 0 0 1 0 OUTPUT NODEFVAL "result[0..0]"
-- Retrieval info: CONNECT: result 0 0 1 0 @result 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| unlicense |
idinev/Desilog | examples/unittests/sub_unit/autogen/desilog.vhd | 4 | 868 | -----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package desilog is
subtype u8 is unsigned( 7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype u32 is unsigned(31 downto 0);
subtype u64 is unsigned(63 downto 0);
subtype u2 is unsigned( 1 downto 0);
subtype u4 is unsigned( 3 downto 0);
type string_ptr is access string;
--function str(a : unsigned) return string;
--function str(a : integer) return string;
function dg_boolToBit(bval : boolean) return std_ulogic;
end package;
package body desilog is
function dg_boolToBit(bval : boolean) return std_ulogic is begin
if bval then
return '1';
else
return '0';
end if;
end function;
end;
| unlicense |
psi46/pixel-dtb-firmware | dtb/ip/spi_master/spi_master_if.vhd | 3 | 5140 | --*****************************************************************************
--* Copyright (C) 2012 by Michael Fischer
--*
--* All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* 1. Redistributions of source code must retain the above copyright
--* notice, this list of conditions and the following disclaimer.
--* 2. Redistributions in binary form must reproduce the above copyright
--* notice, this list of conditions and the following disclaimer in the
--* documentation and/or other materials provided with the distribution.
--* 3. Neither the name of the author nor the names of its contributors may
--* be used to endorse or promote products derived from this software
--* without specific prior written permission.
--*
--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
--* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
--* SUCH DAMAGE.
--*
--*****************************************************************************
--* History:
--*
--* 26.08.2012 mifi First Version
--*****************************************************************************
--*****************************************************************************
--* DEFINE: Library *
--*****************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--*****************************************************************************
--* DEFINE: Entity *
--*****************************************************************************
entity spi_master_if is
port (
--
-- Avalon Slave bus
--
clk : in std_logic := '0';
reset : in std_logic := '0';
chipselect : in std_logic := '0';
address : in std_logic_vector(2 downto 0) := (others => '0');
write : in std_logic := '0';
writedata : in std_logic_vector(15 downto 0) := (others => '0');
read : in std_logic := '0';
readdata : out std_logic_vector(15 downto 0);
--
-- External bus
--
cs : out std_logic;
sclk : out std_logic;
mosi : out std_logic;
miso : in std_logic := '0'
);
end entity spi_master_if;
--*****************************************************************************
--* DEFINE: Architecture *
--*****************************************************************************
architecture syn of spi_master_if is
--
-- Define all constants here
--
--
-- Define all components which are included here
--
component spi_master_core is
port (
--
-- Avalon Slave bus
--
clk : in std_logic := '0';
reset : in std_logic := '0';
chipselect : in std_logic := '0';
address : in std_logic_vector(2 downto 0) := (others => '0');
write : in std_logic := '0';
writedata : in std_logic_vector(15 downto 0) := (others => '0');
read : in std_logic := '0';
readdata : out std_logic_vector(15 downto 0);
--
-- External bus
--
cs : out std_logic;
sclk : out std_logic;
mosi : out std_logic;
miso : in std_logic := '0'
);
end component spi_master_core;
--
-- Define all local signals (like static data) here
--
begin
inst_spi : spi_master_core
port map (
clk => clk,
reset => reset,
chipselect => chipselect,
address => address,
write => write,
writedata => writedata,
read => read,
readdata => readdata,
cs => cs,
sclk => sclk,
mosi => mosi,
miso => miso
);
end architecture syn;
-- *** EOF ***
| unlicense |
psi46/pixel-dtb-firmware | dtb/deser400/PhSeROM.vhd | 1 | 5976 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: PhSeROM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY PhSeROM IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
rden : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END PhSeROM;
ARCHITECTURE SYN OF phserom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
BEGIN
q <= sub_wire0(4 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "./deser400/PhaseSelectErr.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 8,
width_a => 5,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
rden_a => rden,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "./deser400/PhaseSelectErr.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "5"
-- Retrieval info: PRIVATE: rden NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./deser400/PhaseSelectErr.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL "q[4..0]"
-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 5 0 @q_a 0 0 5 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PhSeROM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| unlicense |
jza00425/ARM_Pipelining | lab3/sim/work/arm_wb_stage/_primary.vhd | 1 | 595 | library verilog;
use verilog.vl_types.all;
entity arm_wb_stage is
port(
clk : in vl_logic;
MEMWB_data_read_from_mem: in vl_logic_vector(31 downto 0);
MEMWB_rd_data : in vl_logic_vector(31 downto 0);
MEMWB_rd_we : in vl_logic;
MEMWB_rd_data_sel: in vl_logic;
MEMWB_des_reg_num: in vl_logic_vector(3 downto 0);
WB_data : out vl_logic_vector(31 downto 0);
WB_rd_we : out vl_logic;
WB_des_reg_num : out vl_logic_vector(3 downto 0)
);
end arm_wb_stage;
| unlicense |
jza00425/ARM_Pipelining | lab3/sim/work/register/_primary.vhd | 1 | 425 | library verilog;
use verilog.vl_types.all;
entity \register\ is
generic(
WIDTH : integer := 32;
RESET_VALUE : integer := 0
);
port(
d : in vl_logic_vector;
clk : in vl_logic;
rst_b : in vl_logic;
enable : in vl_logic;
q : out vl_logic_vector
);
end \register\;
| unlicense |
jza00425/ARM_Pipelining | lab3/sim/work/arm_control/_primary.vhd | 1 | 1039 | library verilog;
use verilog.vl_types.all;
entity arm_control is
port(
inst : in vl_logic_vector(31 downto 0);
cpsr_out : in vl_logic_vector(31 downto 0);
rd_we : out vl_logic;
pc_we : out vl_logic;
cpsr_we : out vl_logic;
rd_sel : out vl_logic;
rd_data_sel : out vl_logic;
halted : out vl_logic;
is_imm : out vl_logic;
mem_write_en : out vl_logic_vector(3 downto 0);
ld_byte_or_word : out vl_logic;
alu_or_mac : out vl_logic;
up_down : out vl_logic;
mac_sel : out vl_logic;
mask_of_real_read_reg: out vl_logic_vector(2 downto 0);
read_reg_num : out vl_logic;
alu_sel : out vl_logic_vector(3 downto 0);
cpsr_mask : out vl_logic_vector(3 downto 0);
is_alu_for_mem_addr: out vl_logic
);
end arm_control;
| unlicense |
sahandKashani/TRDB-D5M | DE0-Nano/hw/hdl/cmos_sensor_input/hdl/cmos_sensor_input_constants.vhd | 5 | 9119 | library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
package cmos_sensor_input_constants is
constant CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH : positive := 32;
-- register offsets
constant CMOS_SENSOR_INPUT_CONFIG_OFST : std_logic_vector(1 downto 0) := "00"; -- RW
constant CMOS_SENSOR_INPUT_COMMAND_OFST : std_logic_vector(1 downto 0) := "01"; -- WO
constant CMOS_SENSOR_INPUT_STATUS_OFST : std_logic_vector(1 downto 0) := "10"; -- RO
constant CMOS_SENSOR_INPUT_FRAME_INFO_OFST : std_logic_vector(1 downto 0) := "11"; -- RO
-- CONFIG register
constant CMOS_SENSOR_INPUT_CONFIG_IRQ_BIT_OFST : natural := 0;
constant CMOS_SENSOR_INPUT_CONFIG_IRQ_WIDTH : positive := 1;
constant CMOS_SENSOR_INPUT_CONFIG_IRQ_LOW_BIT_OFST : natural := CMOS_SENSOR_INPUT_CONFIG_IRQ_BIT_OFST;
constant CMOS_SENSOR_INPUT_CONFIG_IRQ_HIGH_BIT_OFST : natural := CMOS_SENSOR_INPUT_CONFIG_IRQ_LOW_BIT_OFST + CMOS_SENSOR_INPUT_CONFIG_IRQ_WIDTH - 1;
constant CMOS_SENSOR_INPUT_CONFIG_IRQ_DISABLE : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_IRQ_WIDTH - 1 downto 0) := "0";
constant CMOS_SENSOR_INPUT_CONFIG_IRQ_ENABLE : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_IRQ_WIDTH - 1 downto 0) := "1";
constant CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_BIT_OFST : natural := CMOS_SENSOR_INPUT_CONFIG_IRQ_HIGH_BIT_OFST + 1;
constant CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH : positive := 2;
constant CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_LOW_BIT_OFST : natural := CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_BIT_OFST;
constant CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_HIGH_BIT_OFST : natural := CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_LOW_BIT_OFST + CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1;
constant CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_RGGB : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1 downto 0) := "00";
constant CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_BGGR : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1 downto 0) := "01";
constant CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_GRBG : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1 downto 0) := "10";
constant CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_GBRG : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1 downto 0) := "11";
-- COMMAND register
constant CMOS_SENSOR_INPUT_COMMAND_BIT_OFST : natural := 0;
constant CMOS_SENSOR_INPUT_COMMAND_WIDTH : positive := CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH;
constant CMOS_SENSOR_INPUT_COMMAND_LOW_BIT_OFST : natural := CMOS_SENSOR_INPUT_COMMAND_BIT_OFST;
constant CMOS_SENSOR_INPUT_COMMAND_HIGH_BIT_OFST : natural := CMOS_SENSOR_INPUT_COMMAND_LOW_BIT_OFST + CMOS_SENSOR_INPUT_COMMAND_WIDTH - 1;
constant CMOS_SENSOR_INPUT_COMMAND_GET_FRAME_INFO : std_logic_vector(CMOS_SENSOR_INPUT_COMMAND_WIDTH - 1 downto 0) := X"00000000";
constant CMOS_SENSOR_INPUT_COMMAND_SNAPSHOT : std_logic_vector(CMOS_SENSOR_INPUT_COMMAND_WIDTH - 1 downto 0) := X"00000001";
constant CMOS_SENSOR_INPUT_COMMAND_IRQ_ACK : std_logic_vector(CMOS_SENSOR_INPUT_COMMAND_WIDTH - 1 downto 0) := X"00000002";
constant CMOS_SENSOR_INPUT_COMMAND_STOP_AND_RESET : std_logic_vector(CMOS_SENSOR_INPUT_COMMAND_WIDTH - 1 downto 0) := X"00000003";
-- STATUS register
constant CMOS_SENSOR_INPUT_STATUS_STATE_BIT_OFST : natural := 0;
constant CMOS_SENSOR_INPUT_STATUS_STATE_WIDTH : positive := 1;
constant CMOS_SENSOR_INPUT_STATUS_STATE_LOW_BIT_OFST : natural := CMOS_SENSOR_INPUT_STATUS_STATE_BIT_OFST;
constant CMOS_SENSOR_INPUT_STATUS_STATE_HIGH_BIT_OFST : natural := CMOS_SENSOR_INPUT_STATUS_STATE_LOW_BIT_OFST + CMOS_SENSOR_INPUT_STATUS_STATE_WIDTH - 1;
constant CMOS_SENSOR_INPUT_STATUS_STATE_IDLE : std_logic_vector(CMOS_SENSOR_INPUT_STATUS_STATE_WIDTH - 1 downto 0) := "0";
constant CMOS_SENSOR_INPUT_STATUS_STATE_BUSY : std_logic_vector(CMOS_SENSOR_INPUT_STATUS_STATE_WIDTH - 1 downto 0) := "1";
constant CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_BIT_OFST : natural := CMOS_SENSOR_INPUT_STATUS_STATE_HIGH_BIT_OFST + 1;
constant CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_WIDTH : positive := 1;
constant CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_LOW_BIT_OFST : natural := CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_BIT_OFST;
constant CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_HIGH_BIT_OFST : natural := CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_LOW_BIT_OFST + CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_WIDTH - 1;
constant CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_NO_OVERFLOW : std_logic_vector(CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_WIDTH - 1 downto 0) := "0";
constant CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_OVERFLOW : std_logic_vector(CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_WIDTH - 1 downto 0) := "1";
constant CMOS_SENSOR_INPUT_STATUS_FIFO_USEDW_BIT_OFST : natural := CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_HIGH_BIT_OFST + 1;
-- max fifo depth is 1024 elements (based on _hw.tcl), so need 11 bits to represent 1024
constant CMOS_SENSOR_INPUT_STATUS_FIFO_USEDW_WIDTH : positive := 11;
constant CMOS_SENSOR_INPUT_STATUS_FIFO_USEDW_LOW_BIT_OFST : natural := CMOS_SENSOR_INPUT_STATUS_FIFO_USEDW_BIT_OFST;
constant CMOS_SENSOR_INPUT_STATUS_FIFO_USEDW_HIGH_BIT_0FST : natural := CMOS_SENSOR_INPUT_STATUS_FIFO_USEDW_LOW_BIT_OFST + CMOS_SENSOR_INPUT_STATUS_FIFO_USEDW_WIDTH - 1;
-- FRAME_INFO register
constant CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_WIDTH_BIT_OFST : natural := 0;
-- takes up half the space of the bus width --> max frame width is 65535
constant CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_WIDTH_WIDTH : positive := CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH / 2;
constant CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_WIDTH_LOW_BIT_OFST : natural := CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_WIDTH_BIT_OFST;
constant CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_WIDTH_HIGH_BIT_OFST : natural := CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_WIDTH_LOW_BIT_OFST + CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_WIDTH_WIDTH - 1;
constant CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_HEIGHT_BIT_OFST : natural := CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_WIDTH_HIGH_BIT_OFST + 1;
-- takes up half the space of the bus width --> max frame height is 65535
constant CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_HEIGHT_WIDTH : positive := CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH / 2;
constant CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_HEIGHT_LOW_BIT_OFST : natural := CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_HEIGHT_BIT_OFST;
constant CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_HEIGHT_HIGH_BIT_OFST : natural := CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_HEIGHT_LOW_BIT_OFST + CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_HEIGHT_WIDTH - 1;
function ceil_log2(num : positive) return natural;
function floor_div(numerator : positive; denominator : positive) return natural;
function bit_width(num : positive) return positive;
function max(left : positive; right : positive) return positive;
end package cmos_sensor_input_constants;
package body cmos_sensor_input_constants is
function ceil_log2(num : positive) return natural is
begin
return integer(ceil(log2(real(num))));
end function ceil_log2;
function floor_div(numerator : positive; denominator : positive) return natural is
begin
return integer(floor(real(numerator) / real(denominator)));
end function floor_div;
function bit_width(num : positive) return positive is
begin
return ceil_log2(num + 1);
end function bit_width;
function max(left : positive; right : positive) return positive is
begin
if left > right then
return left;
else
return right;
end if;
end max;
end package body cmos_sensor_input_constants;
| unlicense |
sahandKashani/TRDB-D5M | DE0-Nano/hw/hdl/i2c/hdl/i2c_clkgen.vhd | 5 | 2023 | --------------------------------------------------------------------
-- i2c_clkgen.vhd -- I2C base clock generator
-- with clock stretching feature
-- generate 1 pulse every clk_cnt clk cycles, for 1 clk duration
--------------------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.2 alpha
-- History :
-- 20-apr-2002 CG 0.1 Initial alpha release
-- 27-apr-2002 CG 0.2 minor cosmetic changes
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_clkgen is
port(
signal clk : in std_logic;
signal rst : in std_logic;
-- count used for dividing clk signal
signal clk_cnt : in std_logic_vector(7 downto 0);
-- I2C clock output generated
signal sclk : out std_logic;
-- I2C clock line SCL (used for clock stretching)
signal scl_in : in std_logic;
signal scl_out : in std_logic
);
end i2c_clkgen;
architecture behavioral of i2c_clkgen is
signal clk_ctr : unsigned(7 downto 0);
signal clk_wait : std_logic;
signal i_clk_out : std_logic;
begin
sclk <= i_clk_out;
process(clk, rst)
begin
if (rst = '1') then
clk_ctr <= (others => '0');
i_clk_out <= '1';
elsif (rising_edge(clk)) then
if (clk_ctr >= unsigned(clk_cnt)) then
clk_ctr <= (others => '0');
i_clk_out <= '1';
else
if (clk_wait = '0') then
clk_ctr <= clk_ctr + 1;
end if;
i_clk_out <= '0';
end if;
end if;
end process;
-- clk_wait <= '1' when (scl_out = '1' and scl_in = '0') else '0'; -- problem rencontres avec ce mode
clk_wait <= '0';
end behavioral;
| unlicense |
sahandKashani/HDL-IP-cores | cmos_sensor_input/hdl/cmos_sensor_input_sc_fifo.vhd | 5 | 4445 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_sc_fifo is
generic(
DATA_WIDTH : positive;
FIFO_DEPTH : positive;
DEVICE_FAMILY : string
);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
read : in std_logic;
write : in std_logic;
empty : out std_logic;
full : out std_logic;
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 1 downto 0);
overflow : out std_logic
);
end cmos_sensor_input_sc_fifo;
architecture rtl of cmos_sensor_input_sc_fifo is
component scfifo
generic(
add_ram_output_register : string;
intended_device_family : string;
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
underflow_checking : string;
use_eab : string
);
port(
clock : in std_logic;
data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
rdreq : in std_logic;
sclr : in std_logic;
wrreq : in std_logic;
empty : out std_logic;
full : out std_logic;
q : out std_logic_vector(DATA_WIDTH - 1 downto 0);
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0)
);
end component;
signal scfifo_clock : std_logic;
signal scfifo_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_rdreq : std_logic;
signal scfifo_sclr : std_logic;
signal scfifo_wrreq : std_logic;
signal scfifo_empty : std_logic;
signal scfifo_full : std_logic;
signal scfifo_q : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_usedw : std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0);
signal reg_overflow : std_logic;
begin
FIFO_OVERFLOW : process(clk, reset)
begin
if reset = '1' then
reg_overflow <= '0';
elsif rising_edge(clk) then
if clr = '1' then
reg_overflow <= '0';
else
reg_overflow <= reg_overflow or (write and scfifo_full);
end if;
end if;
end process;
OUTPUTS : process(reg_overflow, scfifo_empty, scfifo_full, scfifo_q, scfifo_usedw)
begin
data_out <= scfifo_q;
empty <= scfifo_empty;
full <= scfifo_full;
overflow <= reg_overflow;
if scfifo_full = '1' then
usedw <= std_logic_vector(to_unsigned(FIFO_DEPTH, usedw'length));
elsif scfifo_empty = '1' then
usedw <= std_logic_vector(to_unsigned(0, usedw'length));
else
usedw <= std_logic_vector(resize(unsigned(scfifo_usedw), usedw'length));
end if;
end process;
-- scfifo connections ------------------------------------------------------
scfifo_clock <= clk;
scfifo_data <= data_in;
scfifo_rdreq <= read and not scfifo_empty;
scfifo_sclr <= clr;
scfifo_wrreq <= write and not scfifo_full;
scfifo_component : scfifo
generic map(
add_ram_output_register => "OFF",
intended_device_family => DEVICE_FAMILY,
lpm_numwords => FIFO_DEPTH,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => DATA_WIDTH,
lpm_widthu => bit_width(FIFO_DEPTH) - 1,
overflow_checking => "OFF",
underflow_checking => "OFF",
use_eab => "ON"
)
port map(
clock => scfifo_clock,
data => scfifo_data,
rdreq => scfifo_rdreq,
sclr => scfifo_sclr,
wrreq => scfifo_wrreq,
empty => scfifo_empty,
full => scfifo_full,
q => scfifo_q,
usedw => scfifo_usedw
);
end rtl;
| unlicense |
sahandKashani/HDL-IP-cores | i2c/hdl/i2c_core.vhd | 5 | 21685 | ------------------------------------------------------
-- i2c_core.vhd - I2C core V2 logic
------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.4 alpha
-- History :
-- 20-mar-2002 CG 0.1 initial alpha release
-- 22-mar-2002 CG 0.2 complete rewrite
-- 27-mar-2002 CG 0.3 minor corrections
-- 02-apr-2002 CG 0.4 sync. of outputs
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_core is
port(
-- I2C signals
sda_in : in std_logic;
scl_in : in std_logic;
sda_out : out std_logic;
scl_out : out std_logic;
-- interface signals
clk : in std_logic;
rst : in std_logic;
sclk : in std_logic;
ack_in : in std_logic;
ack_out : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
cmd_start : in std_logic;
cmd_stop : in std_logic;
cmd_read : in std_logic;
cmd_write : in std_logic;
cmd_done_ack : in std_logic;
cmd_done : out std_logic;
busy : out std_logic
-- debug signals
-- state : out std_logic_vector(5 downto 0)
);
end i2c_core;
architecture behavorial of i2c_core is
type state_type is (
s_Reset, s_Idle, s_Done, s_DoneAck,
s_Start_A, s_Start_B, s_Start_C, s_Start_D,
s_Stop_A, s_Stop_B, s_Stop_C,
s_Rd_A, s_Rd_B, s_Rd_C, s_Rd_D, s_Rd_E, s_Rd_F,
s_RdAck_A, s_RdAck_B, s_RdAck_C, s_RdAck_D, s_RdAck_E,
s_Wr_A, s_Wr_B, s_Wr_C, s_Wr_D, s_Wr_E,
s_WrAck_A, s_WrAck_B, s_WrAck_C, s_WrAck_D
);
-- data output register
signal i_dout_ld : std_logic;
signal i_dout : std_logic_vector(7 downto 0);
-- ack output register
signal i_ack_out_ld : std_logic;
signal i_ack_out : std_logic;
-- data input bit
signal i_data_in : std_logic;
-- bit counter
signal i_ctr : unsigned(2 downto 0);
signal i_ctr_incr : std_logic;
signal i_ctr_clr : std_logic;
signal p_state : state_type;
signal n_state : state_type;
signal i_scl_out : std_logic;
signal i_sda_out : std_logic;
signal i_sclk_en : std_logic;
signal i_cmd_done : std_logic;
signal i_cmd_go : std_logic;
signal i_busy : std_logic;
begin
-- syncronize output signals
output_sync : process(clk, rst)
begin
if (rst = '1') then
scl_out <= '1';
sda_out <= '1';
data_out <= (others => '0');
ack_out <= '0';
busy <= '0';
cmd_done <= '0';
elsif (rising_edge(clk)) then
scl_out <= i_scl_out;
sda_out <= i_sda_out;
data_out <= i_dout;
ack_out <= i_ack_out;
busy <= i_busy;
cmd_done <= i_cmd_done;
end if;
end process output_sync;
-- select current bit
data_input_selector : process(i_ctr, data_in)
begin
case i_ctr is
when "000" => i_data_in <= data_in(7);
when "001" => i_data_in <= data_in(6);
when "010" => i_data_in <= data_in(5);
when "011" => i_data_in <= data_in(4);
when "100" => i_data_in <= data_in(3);
when "101" => i_data_in <= data_in(2);
when "110" => i_data_in <= data_in(1);
when "111" => i_data_in <= data_in(0);
when others => null;
end case;
end process data_input_selector;
-- indicate start of command
i_cmd_go <= (cmd_read OR cmd_write) AND NOT i_busy;
-- i2c bit counter
counter : process(clk, rst)
begin
if (rst = '1') then
i_ctr <= (others => '0');
elsif (rising_edge(clk)) then
if (i_ctr_clr = '1') then
i_ctr <= (others => '0');
elsif (i_ctr_incr = '1') then
i_ctr <= i_ctr + 1;
end if;
end if;
end process counter;
-- data output register
dout_reg : process(clk, rst)
begin
if (rst = '1') then
i_dout <= (others => '0');
elsif (rising_edge(clk)) then
if (i_dout_ld = '1') then
case i_ctr is
when "000" => i_dout(7) <= sda_in;
when "001" => i_dout(6) <= sda_in;
when "010" => i_dout(5) <= sda_in;
when "011" => i_dout(4) <= sda_in;
when "100" => i_dout(3) <= sda_in;
when "101" => i_dout(2) <= sda_in;
when "110" => i_dout(1) <= sda_in;
when "111" => i_dout(0) <= sda_in;
when others => null;
end case;
end if;
end if;
end process dout_reg;
-- ack bit output register
ack_out_reg : process(clk, rst)
begin
if (rst = '1') then
i_ack_out <= '0';
elsif (rising_edge(clk)) then
if (i_ack_out_ld = '1') then
i_ack_out <= sda_in;
end if;
end if;
end process ack_out_reg;
-- i2c send / receive byte
i2c_sync : process(rst, clk)
begin
if (rst = '1') then
p_state <= s_Reset;
elsif (rising_edge(clk)) then
if ((sclk = '1' and i_sclk_en = '1') or i_sclk_en = '0') then
p_state <= n_state;
end if;
end if;
end process i2c_sync;
i2c_comb : process(p_state, sda_in, scl_in, i_cmd_go, i_ctr, ack_in, i_data_in, cmd_start, cmd_stop, cmd_write, cmd_read, cmd_done_ack)
begin
n_state <= p_state;
--n_state <= p_state;
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
--i_dout_ld <= '0';
--i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
--state <= "111111";
case p_state is
when s_Reset =>
--state <= "000000";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Idle;
when s_Idle =>
--state <= "000001";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '1';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (i_cmd_go = '1') then
if (cmd_start = '1') then
-- do a START
n_state <= s_Start_A;
elsif (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
end if;
when s_Start_A =>
--state <= "001000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= scl_in;
n_state <= s_Start_B;
when s_Start_B =>
--state <= "001001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Start_C;
when s_Start_C =>
--state <= "001010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Start_D;
when s_Start_D =>
--state <= "001011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
if (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
when s_Rd_A =>
--state <= "010000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_B;
when s_Rd_B =>
--state <= "010001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_C;
when s_Rd_C =>
--state <= "010010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '1';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_D;
when s_Rd_D =>
--state <= "010011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_E;
when s_Rd_E =>
--state <= "010100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKOUT
n_state <= s_WrAck_A;
else
-- increment bit counter
n_state <= s_Rd_F;
end if;
when s_Rd_F =>
--state <= "010101";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_A;
when s_WrAck_A =>
--state <= "011000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
n_state <= s_WrAck_B;
when s_WrAck_B =>
--state <= "011001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_C;
when s_WrAck_C =>
--state <= "011010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_D;
when s_WrAck_D =>
--state <= "011011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
-- do a STOP ?
if (cmd_stop = '1') then
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Wr_A =>
--state <= "100000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_B;
when s_Wr_B =>
--state <= "100001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_C;
when s_Wr_C =>
--state <= "100010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_D;
when s_Wr_D =>
--state <= "100011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKIN
n_state <= s_RdAck_A;
else
-- increment bit counter
n_state <= s_Wr_E;
end if;
when s_Wr_E =>
--state <= "100100";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_A;
when s_RdAck_A =>
--state <= "101000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_RdAck_B;
when s_RdAck_B =>
--state <= "101001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_C;
when s_RdAck_C =>
--state <= "101010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '1';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_D;
when s_RdAck_D =>
--state <= "101011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_E;
when s_RdAck_E =>
--state <= "101100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (cmd_stop = '1') then
-- do a STOP
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Stop_A =>
--state <= "111000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
n_state <= s_Stop_B;
when s_Stop_B =>
--state <= "111001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Stop_C;
when s_Stop_C =>
--state <= "111010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Done;
when s_Done =>
--state <= "000010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
n_state <= s_DoneAck;
when s_DoneAck =>
--state <= "000011";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (cmd_done_ack = '1') then
n_state <= s_Idle;
end if;
end case;
end process i2c_comb;
end behavorial;
| unlicense |
sahandKashani/HDL-IP-cores | cmos_sensor_input/hdl/cmos_sensor_input.vhd | 5 | 26442 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input is
generic(
PIX_DEPTH : positive;
SAMPLE_EDGE : string;
MAX_WIDTH : positive range 2 to 65535; -- does not support images with only 1 column (in order for start_of_frame and end_of_frame not to overlap)
MAX_HEIGHT : positive range 1 to 65535; -- but any height is supported
OUTPUT_WIDTH : positive;
FIFO_DEPTH : positive;
DEVICE_FAMILY : string;
DEBAYER_ENABLE : boolean;
PACKER_ENABLE : boolean
);
port(
clk : in std_logic;
reset : in std_logic;
-- cmos sensor
frame_valid : in std_logic;
line_valid : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
-- Avalon-ST Src
ready : in std_logic;
valid : out std_logic;
data_out : out std_logic_vector(OUTPUT_WIDTH - 1 downto 0);
-- Avalon-MM Slave
addr : in std_logic_vector(1 downto 0);
read : in std_logic;
write : in std_logic;
rddata : out std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
wrdata : in std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
-- Avalon Interrupt Sender
irq : out std_logic
);
end entity cmos_sensor_input;
architecture rtl of cmos_sensor_input is
constant PIX_DEPTH_RGB : positive := 3 * PIX_DEPTH;
constant FIFO_DATA_WIDTH : positive := OUTPUT_WIDTH + 1;
constant FIFO_END_OF_FRAME_BIT_OFST : positive := OUTPUT_WIDTH; -- sc_fifo_data(FIFO_END_OF_FRAME_BIT_OFST) = end_of_frame
-- avalon_mm_slave ---------------------------------------------------------
signal avalon_mm_slave_clk_in : std_logic;
signal avalon_mm_slave_reset_in : std_logic;
signal avalon_mm_slave_addr_in : std_logic_vector(1 downto 0);
signal avalon_mm_slave_read_in : std_logic;
signal avalon_mm_slave_write_in : std_logic;
signal avalon_mm_slave_rddata_out : std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
signal avalon_mm_slave_wrdata_in : std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
signal avalon_mm_slave_irq_out : std_logic;
signal avalon_mm_slave_idle_in : std_logic;
signal avalon_mm_slave_snapshot_out : std_logic;
signal avalon_mm_slave_get_frame_info_out : std_logic;
signal avalon_mm_slave_irq_en_out : std_logic;
signal avalon_mm_slave_irq_ack_out : std_logic;
signal avalon_mm_slave_wait_irq_ack_in : std_logic;
signal avalon_mm_slave_frame_width_in : std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
signal avalon_mm_slave_frame_height_in : std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
signal avalon_mm_slave_debayer_pattern_out : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1 downto 0);
signal avalon_mm_slave_fifo_usedw_in : std_logic_vector(bit_width(FIFO_DEPTH) - 1 downto 0);
signal avalon_mm_slave_fifo_overflow_in : std_logic;
signal avalon_mm_slave_stop_and_reset_out : std_logic;
-- synchronizer ------------------------------------------------------------
signal synchronizer_clk_in : std_logic;
signal synchronizer_reset_in : std_logic;
signal synchronizer_frame_valid_in_in : std_logic;
signal synchronizer_line_valid_in_in : std_logic;
signal synchronizer_data_in_in : std_logic_vector(PIX_DEPTH - 1 downto 0);
signal synchronizer_frame_valid_out_out : std_logic;
signal synchronizer_line_valid_out_out : std_logic;
signal synchronizer_data_out_out : std_logic_vector(PIX_DEPTH - 1 downto 0);
-- sampler -----------------------------------------------------------------
signal sampler_clk_in : std_logic;
signal sampler_reset_in : std_logic;
signal sampler_stop_and_reset_in : std_logic;
signal sampler_idle_out : std_logic;
signal sampler_wait_irq_ack_out : std_logic;
signal sampler_irq_en_in : std_logic;
signal sampler_irq_ack_in : std_logic;
signal sampler_snapshot_in : std_logic;
signal sampler_get_frame_info_in : std_logic;
signal sampler_frame_width_out : std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
signal sampler_frame_height_out : std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
signal sampler_frame_valid_in : std_logic;
signal sampler_line_valid_in : std_logic;
signal sampler_data_in_in : std_logic_vector(PIX_DEPTH - 1 downto 0);
signal sampler_valid_out_out : std_logic;
signal sampler_data_out_out : std_logic_vector(PIX_DEPTH - 1 downto 0);
signal sampler_start_of_frame_out_out : std_logic;
signal sampler_end_of_frame_out_out : std_logic;
signal sampler_fifo_overflow_in : std_logic;
signal sampler_end_of_frame_in_in : std_logic;
signal sampler_end_of_frame_in_ack_out : std_logic;
-- debayer -----------------------------------------------------------------
signal debayer_clk_in : std_logic;
signal debayer_reset_in : std_logic;
signal debayer_stop_and_reset_in : std_logic;
signal debayer_debayer_pattern_in : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1 downto 0);
signal debayer_valid_in_in : std_logic;
signal debayer_data_in_in : std_logic_vector(PIX_DEPTH - 1 downto 0);
signal debayer_start_of_frame_in_in : std_logic;
signal debayer_end_of_frame_in_in : std_logic;
signal debayer_valid_out_out : std_logic;
signal debayer_data_out_out : std_logic_vector(PIX_DEPTH_RGB - 1 downto 0);
signal debayer_start_of_frame_out_out : std_logic;
signal debayer_end_of_frame_out_out : std_logic;
-- packer_raw --------------------------------------------------------------
signal packer_raw_clk_in : std_logic;
signal packer_raw_reset_in : std_logic;
signal packer_raw_stop_and_reset_in : std_logic;
signal packer_raw_valid_in_in : std_logic;
signal packer_raw_data_in_in : std_logic_vector(PIX_DEPTH - 1 downto 0);
signal packer_raw_start_of_frame_in_in : std_logic;
signal packer_raw_end_of_frame_in_in : std_logic;
signal packer_raw_valid_out_out : std_logic;
signal packer_raw_data_out_out : std_logic_vector(OUTPUT_WIDTH - 1 downto 0);
signal packer_raw_end_of_frame_out_out : std_logic;
-- packer_rgb --------------------------------------------------------------
signal packer_rgb_clk_in : std_logic;
signal packer_rgb_reset_in : std_logic;
signal packer_rgb_stop_and_reset_in : std_logic;
signal packer_rgb_valid_in_in : std_logic;
signal packer_rgb_data_in_in : std_logic_vector(PIX_DEPTH_RGB - 1 downto 0);
signal packer_rgb_start_of_frame_in_in : std_logic;
signal packer_rgb_end_of_frame_in_in : std_logic;
signal packer_rgb_valid_out_out : std_logic;
signal packer_rgb_data_out_out : std_logic_vector(OUTPUT_WIDTH - 1 downto 0);
signal packer_rgb_end_of_frame_out_out : std_logic;
-- sc_fifo -----------------------------------------------------------------
signal sc_fifo_clk_in : std_logic;
signal sc_fifo_reset_in : std_logic;
signal sc_fifo_clr_in : std_logic;
signal sc_fifo_data_in_in : std_logic_vector(FIFO_DATA_WIDTH - 1 downto 0);
signal sc_fifo_data_out_out : std_logic_vector(FIFO_DATA_WIDTH - 1 downto 0);
signal sc_fifo_read_in : std_logic;
signal sc_fifo_write_in : std_logic;
signal sc_fifo_empty_out : std_logic;
signal sc_fifo_full_out : std_logic;
signal sc_fifo_usedw_out : std_logic_vector(bit_width(FIFO_DEPTH) - 1 downto 0);
signal sc_fifo_overflow_out : std_logic;
-- avalon_st_source --------------------------------------------------------
signal avalon_st_source_clk_in : std_logic;
signal avalon_st_source_reset_in : std_logic;
signal avalon_st_source_stop_and_reset_in : std_logic;
signal avalon_st_source_ready_in : std_logic;
signal avalon_st_source_valid_out : std_logic;
signal avalon_st_source_data_out : std_logic_vector(OUTPUT_WIDTH - 1 downto 0);
signal avalon_st_source_fifo_read_out : std_logic;
signal avalon_st_source_fifo_empty_in : std_logic;
signal avalon_st_source_fifo_data_in : std_logic_vector(OUTPUT_WIDTH - 1 downto 0);
signal avalon_st_source_fifo_end_of_frame_in : std_logic;
signal avalon_st_source_fifo_overflow_in : std_logic;
signal avalon_st_source_end_of_frame_out_out : std_logic;
signal avalon_st_source_end_of_frame_out_ack_in : std_logic;
begin
valid <= avalon_st_source_valid_out;
data_out <= avalon_st_source_data_out;
rddata <= avalon_mm_slave_rddata_out;
irq <= avalon_mm_slave_irq_out;
cmos_sensor_input_avalon_mm_slave_inst : entity work.cmos_sensor_input_avalon_mm_slave
generic map(DEBAYER_ENABLE => DEBAYER_ENABLE,
FIFO_DEPTH => FIFO_DEPTH,
MAX_WIDTH => MAX_WIDTH,
MAX_HEIGHT => MAX_HEIGHT)
port map(clk => avalon_mm_slave_clk_in,
reset => avalon_mm_slave_reset_in,
addr => avalon_mm_slave_addr_in,
read => avalon_mm_slave_read_in,
write => avalon_mm_slave_write_in,
rddata => avalon_mm_slave_rddata_out,
wrdata => avalon_mm_slave_wrdata_in,
irq => avalon_mm_slave_irq_out,
idle => avalon_mm_slave_idle_in,
snapshot => avalon_mm_slave_snapshot_out,
get_frame_info => avalon_mm_slave_get_frame_info_out,
irq_en => avalon_mm_slave_irq_en_out,
irq_ack => avalon_mm_slave_irq_ack_out,
wait_irq_ack => avalon_mm_slave_wait_irq_ack_in,
frame_width => avalon_mm_slave_frame_width_in,
frame_height => avalon_mm_slave_frame_height_in,
debayer_pattern => avalon_mm_slave_debayer_pattern_out,
fifo_usedw => avalon_mm_slave_fifo_usedw_in,
fifo_overflow => avalon_mm_slave_fifo_overflow_in,
stop_and_reset => avalon_mm_slave_stop_and_reset_out);
cmos_sensor_input_synchronizer_inst : entity work.cmos_sensor_input_synchronizer
generic map(PIX_DEPTH => PIX_DEPTH,
SAMPLE_EDGE => SAMPLE_EDGE)
port map(clk => synchronizer_clk_in,
reset => synchronizer_reset_in,
frame_valid_in => synchronizer_frame_valid_in_in,
line_valid_in => synchronizer_line_valid_in_in,
data_in => synchronizer_data_in_in,
frame_valid_out => synchronizer_frame_valid_out_out,
line_valid_out => synchronizer_line_valid_out_out,
data_out => synchronizer_data_out_out);
cmos_sensor_input_sampler_inst : entity work.cmos_sensor_input_sampler
generic map(PIX_DEPTH => PIX_DEPTH,
MAX_WIDTH => MAX_WIDTH,
MAX_HEIGHT => MAX_HEIGHT)
port map(clk => sampler_clk_in,
reset => sampler_reset_in,
stop_and_reset => sampler_stop_and_reset_in,
idle => sampler_idle_out,
wait_irq_ack => sampler_wait_irq_ack_out,
irq_en => sampler_irq_en_in,
irq_ack => sampler_irq_ack_in,
snapshot => sampler_snapshot_in,
get_frame_info => sampler_get_frame_info_in,
frame_width => sampler_frame_width_out,
frame_height => sampler_frame_height_out,
frame_valid => sampler_frame_valid_in,
line_valid => sampler_line_valid_in,
data_in => sampler_data_in_in,
valid_out => sampler_valid_out_out,
data_out => sampler_data_out_out,
start_of_frame_out => sampler_start_of_frame_out_out,
end_of_frame_out => sampler_end_of_frame_out_out,
fifo_overflow => sampler_fifo_overflow_in,
end_of_frame_in => sampler_end_of_frame_in_in,
end_of_frame_in_ack => sampler_end_of_frame_in_ack_out);
debayer_inst : if DEBAYER_ENABLE generate
cmos_sensor_input_debayer_inst : entity work.cmos_sensor_input_debayer
generic map(PIX_DEPTH_RAW => PIX_DEPTH,
PIX_DEPTH_RGB => PIX_DEPTH_RGB,
MAX_WIDTH => MAX_WIDTH)
port map(clk => debayer_clk_in,
reset => debayer_reset_in,
stop_and_reset => debayer_stop_and_reset_in,
debayer_pattern => debayer_debayer_pattern_in,
valid_in => debayer_valid_in_in,
data_in => debayer_data_in_in,
start_of_frame_in => debayer_start_of_frame_in_in,
end_of_frame_in => debayer_end_of_frame_in_in,
valid_out => debayer_valid_out_out,
data_out => debayer_data_out_out,
start_of_frame_out => debayer_start_of_frame_out_out,
end_of_frame_out => debayer_end_of_frame_out_out);
end generate debayer_inst;
packer_inst : if PACKER_ENABLE generate
packer_raw : if not DEBAYER_ENABLE generate
cmos_sensor_input_packer_inst : entity work.cmos_sensor_input_packer
generic map(PIX_DEPTH => PIX_DEPTH,
PACK_WIDTH => OUTPUT_WIDTH)
port map(clk => packer_raw_clk_in,
reset => packer_raw_reset_in,
stop_and_reset => packer_raw_stop_and_reset_in,
valid_in => packer_raw_valid_in_in,
data_in => packer_raw_data_in_in,
start_of_frame_in => packer_raw_start_of_frame_in_in,
end_of_frame_in => packer_raw_end_of_frame_in_in,
valid_out => packer_raw_valid_out_out,
data_out => packer_raw_data_out_out,
end_of_frame_out => packer_raw_end_of_frame_out_out);
end generate packer_raw;
packer_rgb : if DEBAYER_ENABLE generate
cmos_sensor_input_packer_inst : entity work.cmos_sensor_input_packer
generic map(PIX_DEPTH => PIX_DEPTH_RGB,
PACK_WIDTH => OUTPUT_WIDTH)
port map(clk => packer_rgb_clk_in,
reset => packer_rgb_reset_in,
stop_and_reset => packer_rgb_stop_and_reset_in,
valid_in => packer_rgb_valid_in_in,
data_in => packer_rgb_data_in_in,
start_of_frame_in => packer_rgb_start_of_frame_in_in,
end_of_frame_in => packer_rgb_end_of_frame_in_in,
valid_out => packer_rgb_valid_out_out,
data_out => packer_rgb_data_out_out,
end_of_frame_out => packer_rgb_end_of_frame_out_out);
end generate packer_rgb;
end generate packer_inst;
cmos_sensor_input_sc_fifo_inst : entity work.cmos_sensor_input_sc_fifo
generic map(DATA_WIDTH => FIFO_DATA_WIDTH,
FIFO_DEPTH => FIFO_DEPTH,
DEVICE_FAMILY => DEVICE_FAMILY)
port map(clk => sc_fifo_clk_in,
reset => sc_fifo_reset_in,
clr => sc_fifo_clr_in,
data_in => sc_fifo_data_in_in,
data_out => sc_fifo_data_out_out,
read => sc_fifo_read_in,
write => sc_fifo_write_in,
empty => sc_fifo_empty_out,
full => sc_fifo_full_out,
usedw => sc_fifo_usedw_out,
overflow => sc_fifo_overflow_out);
cmos_sensor_input_avalon_st_source_inst : entity work.cmos_sensor_input_avalon_st_source
generic map(DATA_WIDTH => OUTPUT_WIDTH)
port map(clk => avalon_st_source_clk_in,
reset => avalon_st_source_reset_in,
stop_and_reset => avalon_st_source_stop_and_reset_in,
ready => avalon_st_source_ready_in,
valid => avalon_st_source_valid_out,
data => avalon_st_source_data_out,
fifo_read => avalon_st_source_fifo_read_out,
fifo_empty => avalon_st_source_fifo_empty_in,
fifo_data => avalon_st_source_fifo_data_in,
fifo_end_of_frame => avalon_st_source_fifo_end_of_frame_in,
fifo_overflow => avalon_st_source_fifo_overflow_in,
end_of_frame_out => avalon_st_source_end_of_frame_out_out,
end_of_frame_out_ack => avalon_st_source_end_of_frame_out_ack_in);
TOP_LEVEL_INTERNALS_CONNECTIONS : process(addr, avalon_mm_slave_debayer_pattern_out, avalon_mm_slave_get_frame_info_out, avalon_mm_slave_irq_ack_out, avalon_mm_slave_irq_en_out, avalon_mm_slave_snapshot_out, avalon_mm_slave_stop_and_reset_out, avalon_st_source_end_of_frame_out_out, avalon_st_source_fifo_read_out, clk, data_in, debayer_data_out_out, debayer_end_of_frame_out_out, debayer_start_of_frame_out_out, debayer_valid_out_out, frame_valid, line_valid, packer_raw_data_out_out, packer_raw_end_of_frame_out_out, packer_raw_valid_out_out, packer_rgb_data_out_out, packer_rgb_end_of_frame_out_out, packer_rgb_valid_out_out, read, ready, reset, sampler_data_out_out, sampler_end_of_frame_in_ack_out, sampler_end_of_frame_out_out, sampler_frame_height_out, sampler_frame_width_out, sampler_idle_out, sampler_start_of_frame_out_out, sampler_valid_out_out, sampler_wait_irq_ack_out, sc_fifo_data_out_out, sc_fifo_empty_out, sc_fifo_overflow_out, sc_fifo_usedw_out, synchronizer_data_out_out, synchronizer_frame_valid_out_out, synchronizer_line_valid_out_out, wrdata, write)
begin
-- always existing top-level connections -------------------------------
avalon_mm_slave_clk_in <= clk;
avalon_mm_slave_reset_in <= reset;
avalon_mm_slave_addr_in <= addr;
avalon_mm_slave_read_in <= read;
avalon_mm_slave_write_in <= write;
avalon_mm_slave_wrdata_in <= wrdata;
avalon_mm_slave_idle_in <= sampler_idle_out;
avalon_mm_slave_wait_irq_ack_in <= sampler_wait_irq_ack_out;
avalon_mm_slave_frame_width_in <= sampler_frame_width_out;
avalon_mm_slave_frame_height_in <= sampler_frame_height_out;
avalon_mm_slave_fifo_usedw_in <= sc_fifo_usedw_out;
avalon_mm_slave_fifo_overflow_in <= sc_fifo_overflow_out;
synchronizer_clk_in <= clk;
synchronizer_reset_in <= reset;
synchronizer_frame_valid_in_in <= frame_valid;
synchronizer_line_valid_in_in <= line_valid;
synchronizer_data_in_in <= data_in;
sampler_clk_in <= clk;
sampler_reset_in <= reset;
sampler_stop_and_reset_in <= avalon_mm_slave_stop_and_reset_out;
sampler_irq_en_in <= avalon_mm_slave_irq_en_out;
sampler_irq_ack_in <= avalon_mm_slave_irq_ack_out;
sampler_snapshot_in <= avalon_mm_slave_snapshot_out;
sampler_get_frame_info_in <= avalon_mm_slave_get_frame_info_out;
sampler_frame_valid_in <= synchronizer_frame_valid_out_out;
sampler_line_valid_in <= synchronizer_line_valid_out_out;
sampler_data_in_in <= synchronizer_data_out_out;
sampler_fifo_overflow_in <= sc_fifo_overflow_out;
sampler_end_of_frame_in_in <= avalon_st_source_end_of_frame_out_out;
debayer_clk_in <= clk;
debayer_reset_in <= reset;
debayer_stop_and_reset_in <= avalon_mm_slave_stop_and_reset_out;
debayer_debayer_pattern_in <= avalon_mm_slave_debayer_pattern_out;
packer_raw_clk_in <= clk;
packer_raw_reset_in <= reset;
packer_raw_stop_and_reset_in <= avalon_mm_slave_stop_and_reset_out;
packer_rgb_clk_in <= clk;
packer_rgb_reset_in <= reset;
packer_rgb_stop_and_reset_in <= avalon_mm_slave_stop_and_reset_out;
sc_fifo_clk_in <= clk;
sc_fifo_reset_in <= reset;
sc_fifo_clr_in <= avalon_mm_slave_stop_and_reset_out;
sc_fifo_read_in <= avalon_st_source_fifo_read_out;
avalon_st_source_clk_in <= clk;
avalon_st_source_reset_in <= reset;
avalon_st_source_stop_and_reset_in <= avalon_mm_slave_stop_and_reset_out;
avalon_st_source_ready_in <= ready;
avalon_st_source_fifo_empty_in <= sc_fifo_empty_out;
avalon_st_source_fifo_data_in <= sc_fifo_data_out_out(avalon_st_source_fifo_data_in'range);
avalon_st_source_fifo_end_of_frame_in <= sc_fifo_data_out_out(FIFO_END_OF_FRAME_BIT_OFST);
avalon_st_source_fifo_overflow_in <= sc_fifo_overflow_out;
avalon_st_source_end_of_frame_out_ack_in <= sampler_end_of_frame_in_ack_out;
-- default values for "configurable" signals ---------------------------
debayer_valid_in_in <= '0';
debayer_data_in_in <= (others => '0');
debayer_start_of_frame_in_in <= '0';
debayer_end_of_frame_in_in <= '0';
packer_raw_valid_in_in <= '0';
packer_raw_data_in_in <= (others => '0');
packer_raw_start_of_frame_in_in <= '0';
packer_raw_end_of_frame_in_in <= '0';
packer_rgb_valid_in_in <= '0';
packer_rgb_data_in_in <= (others => '0');
packer_rgb_start_of_frame_in_in <= '0';
packer_rgb_end_of_frame_in_in <= '0';
sc_fifo_write_in <= '0';
sc_fifo_data_in_in <= (others => '0');
if not DEBAYER_ENABLE and not PACKER_ENABLE then
sc_fifo_write_in <= sampler_valid_out_out;
sc_fifo_data_in_in <= std_logic_vector(resize(unsigned(sampler_data_out_out), FIFO_DATA_WIDTH));
sc_fifo_data_in_in(FIFO_END_OF_FRAME_BIT_OFST) <= sampler_end_of_frame_out_out;
elsif not DEBAYER_ENABLE and PACKER_ENABLE then
packer_raw_valid_in_in <= sampler_valid_out_out;
packer_raw_data_in_in <= sampler_data_out_out;
packer_raw_start_of_frame_in_in <= sampler_start_of_frame_out_out;
packer_raw_end_of_frame_in_in <= sampler_end_of_frame_out_out;
sc_fifo_write_in <= packer_raw_valid_out_out;
sc_fifo_data_in_in <= std_logic_vector(resize(unsigned(packer_raw_data_out_out), FIFO_DATA_WIDTH));
sc_fifo_data_in_in(FIFO_END_OF_FRAME_BIT_OFST) <= packer_raw_end_of_frame_out_out;
elsif DEBAYER_ENABLE and not PACKER_ENABLE then
debayer_valid_in_in <= sampler_valid_out_out;
debayer_data_in_in <= sampler_data_out_out;
debayer_start_of_frame_in_in <= sampler_start_of_frame_out_out;
debayer_end_of_frame_in_in <= sampler_end_of_frame_out_out;
sc_fifo_write_in <= debayer_valid_out_out;
sc_fifo_data_in_in <= std_logic_vector(resize(unsigned(debayer_data_out_out), FIFO_DATA_WIDTH));
sc_fifo_data_in_in(FIFO_END_OF_FRAME_BIT_OFST) <= debayer_end_of_frame_out_out;
elsif DEBAYER_ENABLE and PACKER_ENABLE then
debayer_valid_in_in <= sampler_valid_out_out;
debayer_data_in_in <= sampler_data_out_out;
debayer_start_of_frame_in_in <= sampler_start_of_frame_out_out;
debayer_end_of_frame_in_in <= sampler_end_of_frame_out_out;
packer_rgb_valid_in_in <= debayer_valid_out_out;
packer_rgb_data_in_in <= debayer_data_out_out;
packer_rgb_start_of_frame_in_in <= debayer_start_of_frame_out_out;
packer_rgb_end_of_frame_in_in <= debayer_end_of_frame_out_out;
sc_fifo_write_in <= packer_rgb_valid_out_out;
sc_fifo_data_in_in <= std_logic_vector(resize(unsigned(packer_rgb_data_out_out), FIFO_DATA_WIDTH));
sc_fifo_data_in_in(FIFO_END_OF_FRAME_BIT_OFST) <= packer_rgb_end_of_frame_out_out;
end if;
end process;
end architecture rtl;
| unlicense |
sahandKashani/HDL-IP-cores | cmos_sensor_output_generator/hdl/cmos_sensor_output_generator.vhd | 1 | 17153 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_output_generator_constants.all;
entity cmos_sensor_output_generator is
generic(
PIX_DEPTH : positive;
MAX_WIDTH : positive;
MAX_HEIGHT : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- Avalon-MM slave
addr : in std_logic_vector(2 downto 0);
read : in std_logic;
write : in std_logic;
rddata : out std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
wrdata : in std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
frame_valid : out std_logic;
line_valid : out std_logic;
data : out std_logic_vector(PIX_DEPTH - 1 downto 0)
);
end entity cmos_sensor_output_generator;
architecture rtl of cmos_sensor_output_generator is
constant CONFIG_REG_WIDTH : positive := bit_width(max(MAX_WIDTH, MAX_HEIGHT));
-- MM_WRITE
signal reg_frame_width_config : unsigned(CONFIG_REG_WIDTH - 1 downto 0);
signal reg_frame_height_config : unsigned(CONFIG_REG_WIDTH - 1 downto 0);
signal reg_frame_frame_blank_config : unsigned(CONFIG_REG_WIDTH - 1 downto 0);
signal reg_frame_line_blank_config : unsigned(CONFIG_REG_WIDTH - 1 downto 0);
signal reg_line_line_blank_config : unsigned(CONFIG_REG_WIDTH - 1 downto 0);
signal reg_line_frame_blank_config : unsigned(CONFIG_REG_WIDTH - 1 downto 0);
signal reg_start : std_logic;
signal reg_stop : std_logic;
-- STATE_LOGIC & NEXT_STATE_LOGIC
type state_type is (STATE_IDLE, STATE_FRAME_FRAME_BLANK, STATE_FRAME_LINE_BLANK, STATE_VALID, STATE_LINE_LINE_BLANK, STATE_LINE_FRAME_BLANK);
signal reg_state, next_reg_state : state_type;
signal reg_frame_width_counter, next_reg_frame_width_counter : unsigned(reg_frame_width_config'range);
signal reg_frame_height_counter, next_reg_frame_height_counter : unsigned(reg_frame_height_config'range);
signal reg_frame_frame_blank_counter, next_reg_frame_frame_blank_counter : unsigned(reg_frame_frame_blank_config'range);
signal reg_frame_line_blank_counter, next_reg_frame_line_blank_counter : unsigned(reg_frame_line_blank_config'range);
signal reg_line_line_blank_counter, next_reg_line_line_blank_counter : unsigned(reg_line_line_blank_config'range);
signal reg_line_frame_blank_counter, next_reg_line_frame_blank_counter : unsigned(reg_line_frame_blank_config'range);
begin
MM_WRITE : process(clk, reset)
begin
if reset = '1' then
reg_frame_width_config <= to_unsigned(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_MIN, reg_frame_width_config'length);
reg_frame_height_config <= to_unsigned(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_MIN, reg_frame_height_config'length);
reg_frame_frame_blank_config <= to_unsigned(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_MIN, reg_frame_frame_blank_config'length);
reg_frame_line_blank_config <= to_unsigned(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_MIN, reg_frame_line_blank_config'length);
reg_line_line_blank_config <= to_unsigned(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_MIN, reg_line_line_blank_config'length);
reg_line_frame_blank_config <= to_unsigned(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_MIN, reg_line_frame_blank_config'length);
reg_start <= '0';
reg_stop <= '0';
elsif rising_edge(clk) then
reg_start <= '0';
reg_stop <= '0';
if write = '1' then
case addr is
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_OFST =>
if reg_state = STATE_IDLE then
reg_frame_width_config <= unsigned(wrdata(reg_frame_width_config'range));
end if;
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_OFST =>
if reg_state = STATE_IDLE then
reg_frame_height_config <= unsigned(wrdata(reg_frame_height_config'range));
end if;
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_OFST =>
if reg_state = STATE_IDLE then
reg_frame_frame_blank_config <= unsigned(wrdata(reg_frame_frame_blank_config'range));
end if;
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_OFST =>
if reg_state = STATE_IDLE then
reg_frame_line_blank_config <= unsigned(wrdata(reg_frame_line_blank_config'range));
end if;
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_OFST =>
if reg_state = STATE_IDLE then
reg_line_line_blank_config <= unsigned(wrdata(reg_line_line_blank_config'range));
end if;
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_OFST =>
if reg_state = STATE_IDLE then
reg_line_frame_blank_config <= unsigned(wrdata(reg_line_frame_blank_config'range));
end if;
when CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_OFST =>
if wrdata(CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_WIDTH - 1 downto 0) = CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_START then
if reg_state = STATE_IDLE then
reg_start <= '1';
end if;
elsif wrdata(CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_WIDTH - 1 downto 0) = CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_STOP then
if reg_state /= STATE_IDLE then
reg_stop <= '1';
end if;
end if;
when others =>
end case;
end if;
end if;
end process;
MM_READ : process(clk, reset)
begin
if reset = '1' then
rddata <= (others => '0');
elsif rising_edge(clk) then
rddata <= (others => '0');
if read = '1' then
case addr is
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_OFST =>
rddata <= std_logic_vector(resize(reg_frame_width_config, rddata'length));
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_OFST =>
rddata <= std_logic_vector(resize(reg_frame_height_config, rddata'length));
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_OFST =>
rddata <= std_logic_vector(resize(reg_frame_frame_blank_config, rddata'length));
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_OFST =>
rddata <= std_logic_vector(resize(reg_frame_line_blank_config, rddata'length));
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_OFST =>
rddata <= std_logic_vector(resize(reg_line_line_blank_config, rddata'length));
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_OFST =>
rddata <= std_logic_vector(resize(reg_line_frame_blank_config, rddata'length));
when CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_OFST =>
if reg_state = STATE_IDLE then
rddata <= CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_IDLE;
else
rddata <= CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_BUSY;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
STATE_LOGIC : process(clk, reset)
begin
if reset = '1' then
reg_state <= STATE_IDLE;
reg_frame_width_counter <= (others => '0');
reg_frame_height_counter <= (others => '0');
reg_frame_frame_blank_counter <= (others => '0');
reg_frame_line_blank_counter <= (others => '0');
reg_line_line_blank_counter <= (others => '0');
reg_line_frame_blank_counter <= (others => '0');
elsif rising_edge(clk) then
reg_state <= next_reg_state;
reg_frame_width_counter <= next_reg_frame_width_counter;
reg_frame_height_counter <= next_reg_frame_height_counter;
reg_frame_frame_blank_counter <= next_reg_frame_frame_blank_counter;
reg_frame_line_blank_counter <= next_reg_frame_line_blank_counter;
reg_line_line_blank_counter <= next_reg_line_line_blank_counter;
reg_line_frame_blank_counter <= next_reg_line_frame_blank_counter;
end if;
end process;
NEXT_STATE_LOGIC : process(reg_frame_frame_blank_config, reg_frame_frame_blank_counter, reg_frame_height_config, reg_frame_height_counter, reg_frame_line_blank_config, reg_frame_line_blank_counter, reg_frame_width_config, reg_frame_width_counter, reg_line_frame_blank_config, reg_line_frame_blank_counter, reg_line_line_blank_config, reg_line_line_blank_counter, reg_start, reg_state, reg_stop)
begin
next_reg_state <= reg_state;
next_reg_frame_width_counter <= reg_frame_width_counter;
next_reg_frame_height_counter <= reg_frame_height_counter;
next_reg_frame_frame_blank_counter <= reg_frame_frame_blank_counter;
next_reg_frame_line_blank_counter <= reg_frame_line_blank_counter;
next_reg_line_line_blank_counter <= reg_line_line_blank_counter;
next_reg_line_frame_blank_counter <= reg_line_frame_blank_counter;
frame_valid <= '0';
line_valid <= '0';
data <= (others => '0');
case reg_state is
when STATE_IDLE =>
if reg_start = '1' then
if reg_frame_line_blank_config > 0 then
next_reg_state <= STATE_FRAME_LINE_BLANK;
next_reg_frame_line_blank_counter <= to_unsigned(1, next_reg_frame_line_blank_counter'length);
elsif reg_frame_line_blank_config = 0 then
next_reg_state <= STATE_VALID;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= to_unsigned(1, next_reg_frame_height_counter'length);
end if;
end if;
when STATE_FRAME_FRAME_BLANK =>
next_reg_frame_frame_blank_counter <= reg_frame_frame_blank_counter + 1;
if reg_stop = '1' then
next_reg_state <= STATE_IDLE;
else
if reg_frame_frame_blank_counter = reg_frame_frame_blank_config then
if reg_frame_line_blank_config > 0 then
next_reg_state <= STATE_FRAME_LINE_BLANK;
next_reg_frame_line_blank_counter <= to_unsigned(1, next_reg_frame_line_blank_counter'length);
elsif reg_frame_line_blank_config = 0 then
next_reg_state <= STATE_VALID;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= to_unsigned(1, next_reg_frame_height_counter'length);
end if;
end if;
end if;
when STATE_FRAME_LINE_BLANK =>
frame_valid <= '1';
next_reg_frame_line_blank_counter <= reg_frame_line_blank_counter + 1;
if reg_stop = '1' then
next_reg_state <= STATE_IDLE;
else
if reg_frame_line_blank_counter = reg_frame_line_blank_config then
next_reg_state <= STATE_VALID;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= to_unsigned(1, next_reg_frame_height_counter'length);
end if;
end if;
when STATE_VALID =>
frame_valid <= '1';
line_valid <= '1';
data <= std_logic_vector(resize((reg_frame_height_counter - 1) * reg_frame_width_config + (reg_frame_width_counter - 1), data'length));
-- if reg_frame_height_counter(0) = '0' and reg_frame_width_counter(0) = '0' then -- upper right
-- data <= std_logic_vector(to_unsigned(1, data'length));
-- end if;
--
-- if reg_frame_height_counter(0) = '0' and reg_frame_width_counter(0) = '1' then -- upper left
-- data <= std_logic_vector(to_unsigned(2, data'length));
-- end if;
--
-- if reg_frame_height_counter(0) = '1' and reg_frame_width_counter(0) = '0' then -- lower right
-- data <= std_logic_vector(to_unsigned(2, data'length));
-- end if;
--
-- if reg_frame_height_counter(0) = '1' and reg_frame_width_counter(0) = '1' then -- lower left
-- data <= std_logic_vector(to_unsigned(3, data'length));
-- end if;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
if reg_stop = '1' then
next_reg_state <= STATE_IDLE;
else
if reg_frame_width_counter = reg_frame_width_config then
if reg_frame_height_counter < reg_frame_height_config then
next_reg_state <= STATE_LINE_LINE_BLANK;
next_reg_line_line_blank_counter <= to_unsigned(1, next_reg_line_line_blank_counter'length);
elsif reg_frame_height_counter = reg_frame_height_config then
if reg_line_frame_blank_config > 0 then
next_reg_state <= STATE_LINE_FRAME_BLANK;
next_reg_line_frame_blank_counter <= to_unsigned(1, next_reg_line_frame_blank_counter'length);
elsif reg_line_frame_blank_config = 0 then
next_reg_state <= STATE_FRAME_FRAME_BLANK;
next_reg_frame_frame_blank_counter <= to_unsigned(1, next_reg_frame_frame_blank_counter'length);
end if;
end if;
end if;
end if;
when STATE_LINE_LINE_BLANK =>
frame_valid <= '1';
next_reg_line_line_blank_counter <= reg_line_line_blank_counter + 1;
if reg_stop = '1' then
next_reg_state <= STATE_IDLE;
else
if reg_line_line_blank_counter = reg_line_line_blank_config then
next_reg_state <= STATE_VALID;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= reg_frame_height_counter + 1;
end if;
end if;
when STATE_LINE_FRAME_BLANK =>
frame_valid <= '1';
next_reg_line_frame_blank_counter <= reg_line_frame_blank_counter + 1;
if reg_stop = '1' then
next_reg_state <= STATE_IDLE;
else
if reg_line_frame_blank_counter = reg_line_frame_blank_config then
next_reg_state <= STATE_FRAME_FRAME_BLANK;
next_reg_frame_frame_blank_counter <= to_unsigned(1, next_reg_frame_frame_blank_counter'length);
end if;
end if;
end case;
end process;
end architecture rtl;
| unlicense |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/register16_with_we.vhd | 1 | 1327 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:45:34 10/22/2015
-- Design Name:
-- Module Name: register16_with_we - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity register16_with_we is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
d : in STD_LOGIC_VECTOR (15 downto 0);
q : out STD_LOGIC_VECTOR (15 downto 0);
we : in STD_LOGIC);
end register16_with_we;
architecture Behavioral of register16_with_we is
-- Intermediate Signals --
begin
process (clk, reset)
begin
if reset = '1' then
q <= "0000000000010011";
elsif rising_edge(clk) and we = '1' then
q <= d;
end if;
end process;
end Behavioral;
| unlicense |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/tb_control_unit.vhd | 1 | 2541 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:42:07 10/22/2015
-- Design Name:
-- Module Name: C:/Users/Colton/Nibble_Knowledge_CPU/tb_control_unit.vhd
-- Project Name: Nibble_Knowledge_CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: control_unit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_control_unit IS
END tb_control_unit;
ARCHITECTURE behavior OF tb_control_unit IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT control_unit
PORT(
clk : IN std_logic;
reset : IN std_logic;
hlt : IN std_logic;
exe : OUT std_logic;
op_en : OUT std_logic;
mem_en : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal hlt : std_logic := '0';
--Outputs
signal exe : std_logic;
signal op_en : std_logic;
signal mem_en : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: control_unit PORT MAP (
clk => clk,
reset => reset,
hlt => hlt,
exe => exe,
op_en => op_en,
mem_en => mem_en
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
-- Let counter run
wait for clk_period*50;
-- CPU hlts
hlt <= '1';
wait for clk_period;
hlt <= '0';
wait;
end process;
END;
| unlicense |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/tb_alu_complete.vhd | 1 | 4285 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:10:20 10/22/2015
-- Design Name:
-- Module Name: C:/Users/Bailey/OneDrive/Documents/Engineering/Courses/4th Year/ENEL 500/CPU_ALU/tb_alu_complete.vhd
-- Project Name: CPU_ALU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: alu_complete
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_alu_complete IS
END tb_alu_complete;
ARCHITECTURE behavior OF tb_alu_complete IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alu_complete
PORT(
exe : IN std_logic;
OP_EN : IN std_logic;
data_in : IN std_logic_vector(3 downto 0);
WE : OUT std_logic;
JMP : OUT std_logic;
STR: OUT std_logic;
data_out : OUT std_logic_vector(3 downto 0);
clk : IN std_logic;
rst : IN std_logic
);
END COMPONENT;
--Inputs
signal exe : std_logic := '0';
signal OP_EN : std_logic := '0';
signal data_in : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal WE : std_logic;
signal JMP : std_logic;
signal data_out : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alu_complete PORT MAP (
exe => exe,
OP_EN => OP_EN,
data_in => data_in,
WE => WE,
JMP => JMP,
data_out => data_out,
clk => clk,
rst => rst
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
wait for clk_period*10;
--Test LOD:
OP_EN <= '1';
data_in <= "0001";
wait for clk_period;
OP_EN <= '0';
data_in <= "1011";
wait for clk_period*4;
exe <= '1';
wait for clk_period;
exe <= '0';
--Test STR:
OP_EN <= '1';
data_in <= "0010";
wait for clk_period;
OP_EN <= '0';
data_in <= "1111";
wait for clk_period*4;
exe <= '1';
wait for clk_period;
exe <= '0';
--Test ADD:
OP_EN <= '1';
data_in <= "0011";
wait for clk_period;
OP_EN <= '0';
data_in <= "1111";
wait for clk_period*4;
exe <= '1';
wait for clk_period;
exe <= '0';
--Test NND:
OP_EN <= '1';
data_in <= "0101";
wait for clk_period;
OP_EN <= '0';
data_in <= "1111";
wait for clk_period*4;
exe <= '1';
wait for clk_period;
exe <= '0';
--Test JMP, first LOD 0
OP_EN <= '1';
data_in <= "0001";
wait for clk_period;
OP_EN <= '0';
data_in <= "0000";
wait for clk_period*4;
exe <= '1';
wait for clk_period;
exe <= '0';
--Then JMP
OP_EN <= '1';
data_in <= "0111";
wait for clk_period;
OP_EN <= '0';
data_in <= "0000";
wait for clk_period*4;
exe <= '1';
wait for clk_period;
exe <= '0';
--HLT
OP_EN <= '1';
data_in <= "0000";
wait for clk_period;
OP_EN <= '0';
data_in <= "0000";
wait for clk_period*4;
exe <= '1';
wait for clk_period;
exe <= '0';
--CXA
OP_EN <= '1';
data_in <= "0110";
wait for clk_period;
OP_EN <= '0';
data_in <= "0000";
wait for clk_period*4;
exe <= '1';
wait for clk_period;
exe <= '0';
wait;
end process;
END;
| unlicense |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/tb_control_unit_V2.vhd | 1 | 2664 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:21:23 11/01/2015
-- Design Name:
-- Module Name: C:/Users/Colton/Desktop/Nibble_Knowledge_CPU/tb_control_unit_V2.vhd
-- Project Name: Nibble_Knowledge_CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: control_unit_V2
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_control_unit_V2 IS
END tb_control_unit_V2;
ARCHITECTURE behavior OF tb_control_unit_V2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT control_unit_V2
PORT(
clk : IN std_logic;
reset : IN std_logic;
hlt : IN std_logic;
op_en : OUT std_logic;
mem_en : OUT std_logic;
pc_en : OUT std_logic;
exe : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal hlt : std_logic := '0';
--Outputs
signal op_en : std_logic;
signal mem_en : std_logic;
signal pc_en : std_logic;
signal exe : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: control_unit_V2 PORT MAP (
clk => clk,
reset => reset,
hlt => hlt,
op_en => op_en,
mem_en => mem_en,
pc_en => pc_en,
exe => exe
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*50;
-- insert stimulus here
hlt <= '1';
wait for clk_period;
hlt <= '0';
wait for clk_period;
wait;
end process;
END;
| unlicense |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/four_bit_full_adder.vhd | 1 | 1847 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:42:09 10/21/2015
-- Design Name:
-- Module Name: four_bit_full_adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity four_bit_full_adder is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
y : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
msb_cin: out STD_LOGIC;
sum : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end four_bit_full_adder;
architecture Behavioral of four_bit_full_adder is
--Use the one bit adder
component one_bit_full_adder
Port( x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
--Internal Signals
signal i_carry: STD_LOGIC_VECTOR(2 downto 0);
begin
cell_1: one_bit_full_adder
port map(x(0), y(0), cin, sum(0), i_carry(0));
cell_2: one_bit_full_adder
port map(x(1), y(1), i_carry(0), sum(1), i_carry(1));
cell_3: one_bit_full_adder
port map(x(2), y(2), i_carry(1), sum(2), i_carry(2));
cell_4: one_bit_full_adder
port map(x(3), y(3), i_carry(2), sum(3), cout);
--Used for XORb
msb_cin <= i_carry(2);
end Behavioral;
| unlicense |
PiJoules/Zybo-Vision-Processing | hdmi_passthrough_720p.srcs/sources_1/ipshared/digilentinc.com/dvi2rgb_v1_4/4f0fd262/src/InputSERDES.vhd | 15 | 10056 | -------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
| unlicense |
PiJoules/Zybo-Vision-Processing | hdmi_passthrough_720p.srcs/sources_1/bd/design_1/ip/design_1_dvi2rgb_0_0/synth/design_1_dvi2rgb_0_0.vhd | 1 | 7037 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: digilentinc.com:ip:dvi2rgb:1.4
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_dvi2rgb_0_0 IS
PORT (
TMDS_Clk_p : IN STD_LOGIC;
TMDS_Clk_n : IN STD_LOGIC;
TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
RefClk : IN STD_LOGIC;
aRst : IN STD_LOGIC;
vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
vid_pVDE : OUT STD_LOGIC;
vid_pHSync : OUT STD_LOGIC;
vid_pVSync : OUT STD_LOGIC;
PixelClk : OUT STD_LOGIC;
aPixelClkLckd : OUT STD_LOGIC;
DDC_SDA_I : IN STD_LOGIC;
DDC_SDA_O : OUT STD_LOGIC;
DDC_SDA_T : OUT STD_LOGIC;
DDC_SCL_I : IN STD_LOGIC;
DDC_SCL_O : OUT STD_LOGIC;
DDC_SCL_T : OUT STD_LOGIC;
pRst : IN STD_LOGIC
);
END design_1_dvi2rgb_0_0;
ARCHITECTURE design_1_dvi2rgb_0_0_arch OF design_1_dvi2rgb_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dvi2rgb_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT dvi2rgb IS
GENERIC (
kEmulateDDC : BOOLEAN;
kRstActiveHigh : BOOLEAN;
kClkRange : INTEGER;
kIDLY_TapValuePs : INTEGER;
kIDLY_TapWidth : INTEGER
);
PORT (
TMDS_Clk_p : IN STD_LOGIC;
TMDS_Clk_n : IN STD_LOGIC;
TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
RefClk : IN STD_LOGIC;
aRst : IN STD_LOGIC;
aRst_n : IN STD_LOGIC;
vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
vid_pVDE : OUT STD_LOGIC;
vid_pHSync : OUT STD_LOGIC;
vid_pVSync : OUT STD_LOGIC;
PixelClk : OUT STD_LOGIC;
SerialClk : OUT STD_LOGIC;
aPixelClkLckd : OUT STD_LOGIC;
DDC_SDA_I : IN STD_LOGIC;
DDC_SDA_O : OUT STD_LOGIC;
DDC_SDA_T : OUT STD_LOGIC;
DDC_SCL_I : IN STD_LOGIC;
DDC_SCL_O : OUT STD_LOGIC;
DDC_SCL_T : OUT STD_LOGIC;
pRst : IN STD_LOGIC;
pRst_n : IN STD_LOGIC
);
END COMPONENT dvi2rgb;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_dvi2rgb_0_0_arch: ARCHITECTURE IS "dvi2rgb,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_dvi2rgb_0_0_arch : ARCHITECTURE IS "design_1_dvi2rgb_0_0,dvi2rgb,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_P";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_N";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_P";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_N";
ATTRIBUTE X_INTERFACE_INFO OF RefClk: SIGNAL IS "xilinx.com:signal:clock:1.0 RefClk CLK";
ATTRIBUTE X_INTERFACE_INFO OF vid_pData: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB DATA";
ATTRIBUTE X_INTERFACE_INFO OF vid_pVDE: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF vid_pHSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF vid_pVSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF PixelClk: SIGNAL IS "xilinx.com:signal:clock:1.0 PixelClk CLK";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_I";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_O";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_T";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_I";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_O";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_T";
BEGIN
U0 : dvi2rgb
GENERIC MAP (
kEmulateDDC => true,
kRstActiveHigh => true,
kClkRange => 2,
kIDLY_TapValuePs => 78,
kIDLY_TapWidth => 5
)
PORT MAP (
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
TMDS_Data_p => TMDS_Data_p,
TMDS_Data_n => TMDS_Data_n,
RefClk => RefClk,
aRst => aRst,
aRst_n => '1',
vid_pData => vid_pData,
vid_pVDE => vid_pVDE,
vid_pHSync => vid_pHSync,
vid_pVSync => vid_pVSync,
PixelClk => PixelClk,
aPixelClkLckd => aPixelClkLckd,
DDC_SDA_I => DDC_SDA_I,
DDC_SDA_O => DDC_SDA_O,
DDC_SDA_T => DDC_SDA_T,
DDC_SCL_I => DDC_SCL_I,
DDC_SCL_O => DDC_SCL_O,
DDC_SCL_T => DDC_SCL_T,
pRst => pRst,
pRst_n => '1'
);
END design_1_dvi2rgb_0_0_arch;
| unlicense |
TWW12/lzw | final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_2/bram_1024_2_sim_netlist.vhdl | 1 | 50604 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:55 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_2/bram_1024_2_sim_netlist.vhdl
-- Design : bram_1024_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_2_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_2_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bram_1024_2_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bram_1024_2_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000001F0000001B00000017000000130000000F0000000B0000000700000003",
INIT_01 => X"0000011F0000011B00000117000001130000010F0000010B0000010700000103",
INIT_02 => X"0000021F0000021B00000217000002130000020F0000020B0000020700000203",
INIT_03 => X"0000031F0000031B00000317000003130000030F0000030B0000030700000303",
INIT_04 => X"0000041F0000041B00000417000004130000040F0000040B0000040700000403",
INIT_05 => X"0000051F0000051B00000517000005130000050F0000050B0000050700000503",
INIT_06 => X"0000061F0000061B00000617000006130000060F0000060B0000060700000603",
INIT_07 => X"0000071F0000071B00000717000007130000070F0000070B0000070700000703",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 29) => B"000",
DIADI(28 downto 24) => dina(19 downto 15),
DIADI(23 downto 21) => B"000",
DIADI(20 downto 16) => dina(14 downto 10),
DIADI(15 downto 13) => B"000",
DIADI(12 downto 8) => dina(9 downto 5),
DIADI(7 downto 5) => B"000",
DIADI(4 downto 0) => dina(4 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\,
DOADO(30) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\,
DOADO(29) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\,
DOADO(28 downto 24) => douta(19 downto 15),
DOADO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\,
DOADO(22) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\,
DOADO(21) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\,
DOADO(20 downto 16) => douta(14 downto 10),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\,
DOADO(12 downto 8) => douta(9 downto 5),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\,
DOADO(4 downto 0) => douta(4 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_2_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_2_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bram_1024_2_blk_mem_gen_prim_width;
architecture STRUCTURE of bram_1024_2_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bram_1024_2_blk_mem_gen_prim_wrapper_init
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_2_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_2_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bram_1024_2_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bram_1024_2_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.bram_1024_2_blk_mem_gen_prim_width
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_2_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_2_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bram_1024_2_blk_mem_gen_top;
architecture STRUCTURE of bram_1024_2_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bram_1024_2_blk_mem_gen_generic_cstr
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_2_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_2_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bram_1024_2_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bram_1024_2_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bram_1024_2_blk_mem_gen_top
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_2_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 19 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 19 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "bram_1024_2.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "bram_1024_2.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bram_1024_2_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_1024_2_blk_mem_gen_v8_3_5 : entity is "yes";
end bram_1024_2_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bram_1024_2_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bram_1024_2_blk_mem_gen_v8_3_5_synth
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_2 is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bram_1024_2 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bram_1024_2 : entity is "bram_1024_2,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_1024_2 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bram_1024_2 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bram_1024_2;
architecture STRUCTURE of bram_1024_2 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bram_1024_2.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bram_1024_2.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bram_1024_2_blk_mem_gen_v8_3_5
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9 downto 0) => B"0000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(19 downto 0) => dina(19 downto 0),
dinb(19 downto 0) => B"00000000000000000000",
douta(19 downto 0) => douta(19 downto 0),
doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(19 downto 0) => B"00000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| unlicense |
TWW12/lzw | ip_repo/axi_compression_1.0/src/dictionary_2.vhd | 4 | 4750 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity dictionary_2 is
port (
clk : in std_logic;
rst : in std_logic;
start_search : in std_logic;
search_entry : in std_logic_vector(19 downto 0);
--Write enable & entries
wr_en : in std_logic;
wr_entry : in std_logic_vector(19 downto 0);
--Outputs
prefix : out std_logic_vector(11 downto 0);
entry_found : out std_logic;
search_completed : out std_logic;
dictionary_full : out std_logic);
end dictionary_2;
architecture Behavioral of dictionary_2 is
signal wr_addr_shift : std_logic_vector(11 downto 0);
signal search_completed_i : std_logic;
signal full : std_logic;
signal wr_addr : std_logic_vector(11 downto 0);
signal wr_addr_block0 : std_logic_vector(11 downto 0);
signal wr_addr_block1 : std_logic_vector(11 downto 0);
signal block0_wr_en : std_logic;
signal block0_prefix : std_logic_vector(10 downto 0);
signal block0_prefix_shift : std_logic_vector(11 downto 0);
signal block0_entry_found : std_logic;
signal block0_search_completed : std_logic;
signal block1_wr_en : std_logic;
signal block1_prefix : std_logic_vector(10 downto 0);
signal block1_entry_found : std_logic;
signal block1_search_completed : std_logic;
signal halt_search : std_logic;
begin
wr_addr_shift(11 downto 1) <= wr_addr(10 downto 0);
wr_addr_shift(0) <= '0';
block0_prefix_shift(11 downto 1) <= block0_prefix;
block0_prefix_shift(0) <= '0';
--Combines all signals from blocks
search_completed <= search_completed_i;
process(clk,rst)
begin
if rst = '1' then
block1_wr_en <= '0';
block0_wr_en <= '0';
search_completed_i <= '0';
entry_found <= '0';
prefix <= x"000";
elsif rising_edge(clk) then
block1_wr_en <= not wr_addr(0) and wr_en;
block0_wr_en <= wr_addr(0) and wr_en;
search_completed_i <= block0_search_completed or block1_search_completed;
entry_found <= block0_entry_found or block1_entry_found;
if block0_entry_found = '1' then
if block0_prefix_shift = x"000" then
prefix <= x"001";
else
prefix <= std_logic_vector(unsigned(block0_prefix_shift)-to_unsigned(1,12));
end if;
elsif block1_entry_found = '1' then
prefix(11 downto 1) <= block1_prefix;
prefix(0) <= '0';
end if;
end if;
end process;
U_BLOCK_0 : entity work.dictionary_block_2
generic map (block_num => 0)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
halt_search => search_completed_i,
wr_en => block0_wr_en,
wr_addr => wr_addr(11 downto 1),
wr_entry => wr_entry,
prefix => block0_prefix,
entry_found => block0_entry_found,
search_completed => block0_search_completed);
U_BLOCK_1 : entity work.dictionary_block_2
generic map (block_num => 1)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => block1_wr_en,
wr_addr => wr_addr(11 downto 1),
wr_entry => wr_entry,
halt_search => search_completed_i,
prefix => block1_prefix,
entry_found => block1_entry_found,
search_completed => block1_search_completed);
--write proc
dictionary_full <= full;
process(clk,rst)
begin
if rst = '1' then
wr_addr <= std_logic_vector(to_unsigned(254,12));
wr_addr_block0 <= std_logic_vector(to_unsigned(127,12));
wr_addr_block1 <= std_logic_vector(to_unsigned(127,12));
full <= '0';
elsif rising_edge(clk) then
if wr_en = '1' and full = '0' then
wr_addr <= std_logic_vector(to_unsigned(1,12)+unsigned(wr_addr));
wr_addr_block0 <= std_logic_vector(unsigned(wr_addr_shift)-to_unsigned(1,12));
wr_addr_block1 <= wr_addr_shift;
end if;
--last entry written should increment counter to "1000...000"
if wr_addr(11) = '1' then
full <= '1';
end if;
end if;
end process;
end Behavioral;
| unlicense |
TWW12/lzw | final_project/lzw_compression/lzw_compression.ipdefs/axi_compression_1.0_0_0/src/bram_4096/bram_4096_stub.vhdl | 3 | 1463 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 08:57:14 2017
-- Host : Shaun running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/Shaun/Desktop/ip_repo/axi_compression_1.0/src/bram_4096/bram_4096_stub.vhdl
-- Design : bram_4096
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bram_4096 is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
end bram_4096;
architecture stub of bram_4096 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[11:0],dina[19:0],douta[19:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
| unlicense |
TWW12/lzw | ip_repo/axi_compression_1.0/src/output_fifo/output_fifo_sim_netlist.vhdl | 2 | 164294 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 09:06:21 2017
-- Host : Shaun running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/Shaun/Desktop/ip_repo/axi_compression_1.0/src/output_fifo/output_fifo_sim_netlist.vhdl
-- Design : output_fifo
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end output_fifo_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of output_fifo_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\ : STD_LOGIC;
signal tmp_ram_regce : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 4) => Q(9 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 4) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(3 downto 0) => B"0000",
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 14) => B"00",
DIADI(13 downto 8) => din(11 downto 6),
DIADI(7 downto 6) => B"00",
DIADI(5 downto 0) => din(5 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_16\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_17\,
DOBDO(13 downto 8) => dout(11 downto 6),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_24\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_25\,
DOBDO(5 downto 0) => dout(5 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\,
ENARDEN => WEA(0),
ENBWREN => tmp_ram_rd_en,
REGCEAREGCE => '0',
REGCEB => tmp_ram_regce,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => srst,
WEA(1) => WEA(0),
WEA(0) => WEA(0),
WEBWE(3 downto 0) => B"0000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => srst,
I1 => ram_rd_en_d1,
O => tmp_ram_regce
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare is
port (
ram_full_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
\out\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare : entity is "compare";
end output_fifo_compare;
architecture STRUCTURE of output_fifo_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFC0FFC05500FFC0"
)
port map (
I0 => comp0,
I1 => wr_en,
I2 => comp1,
I3 => \out\,
I4 => rd_en,
I5 => ram_empty_fb_i_reg,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare_0 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare_0 : entity is "compare";
end output_fifo_compare_0;
architecture STRUCTURE of output_fifo_compare_0 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare_1 is
port (
ram_empty_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare_1 : entity is "compare";
end output_fifo_compare_1;
architecture STRUCTURE of output_fifo_compare_1 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gcc0.gc0.count_d1_reg[6]\,
S(2) => \gcc0.gc0.count_d1_reg[4]\,
S(1) => \gcc0.gc0.count_d1_reg[2]\,
S(0) => \gcc0.gc0.count_d1_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gcc0.gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCF0FCF05050FCF0"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
I4 => wr_en,
I5 => ram_full_fb_i_reg,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_compare_2 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_compare_2 : entity is "compare";
end output_fifo_compare_2;
architecture STRUCTURE of output_fifo_compare_2 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_rd_bin_cntr : entity is "rd_bin_cntr";
end output_fifo_rd_bin_cntr;
architecture STRUCTURE of output_fifo_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair0";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
I2 => \^q\(7),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(7),
I3 => \^q\(8),
O => plusOp(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(7),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
I4 => \^q\(9),
O => plusOp(9)
);
\gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[9]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(0),
R => srst
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(1),
R => srst
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(2),
R => srst
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(3),
R => srst
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(4),
R => srst
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(5),
R => srst
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(6),
R => srst
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(7),
R => srst
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(8),
R => srst
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(9),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9),
R => srst
);
\gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
Q => \^q\(0),
S => srst
);
\gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(1),
Q => \^q\(1),
R => srst
);
\gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(2),
Q => \^q\(2),
R => srst
);
\gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(3),
Q => \^q\(3),
R => srst
);
\gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(4),
Q => \^q\(4),
R => srst
);
\gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(5),
Q => \^q\(5),
R => srst
);
\gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(6),
Q => \^q\(6),
R => srst
);
\gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(7),
Q => \^q\(7),
R => srst
);
\gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(8),
Q => \^q\(8),
R => srst
);
\gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(9),
Q => \^q\(9),
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_wr_bin_cntr is
port (
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_wr_bin_cntr : entity is "wr_bin_cntr";
end output_fifo_wr_bin_cntr;
architecture STRUCTURE of output_fifo_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gcc0.gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gcc0.gc0.count[9]_i_1\ : label is "soft_lutpair4";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
I5 => p_12_out(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gcc0.gc0.count[9]_i_2_n_0\,
I1 => p_12_out(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gcc0.gc0.count[9]_i_2_n_0\,
I1 => p_12_out(6),
I2 => p_12_out(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(6),
I1 => \gcc0.gc0.count[9]_i_2_n_0\,
I2 => p_12_out(7),
I3 => p_12_out(8),
O => \plusOp__0\(8)
);
\gcc0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(7),
I1 => \gcc0.gc0.count[9]_i_2_n_0\,
I2 => p_12_out(6),
I3 => p_12_out(8),
I4 => p_12_out(9),
O => \plusOp__0\(9)
);
\gcc0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => p_12_out(5),
I1 => p_12_out(3),
I2 => p_12_out(1),
I3 => p_12_out(0),
I4 => p_12_out(2),
I5 => p_12_out(4),
O => \gcc0.gc0.count[9]_i_2_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(0),
Q => \^q\(0),
R => srst
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(1),
Q => \^q\(1),
R => srst
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(2),
Q => \^q\(2),
R => srst
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(3),
Q => \^q\(3),
R => srst
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(4),
Q => \^q\(4),
R => srst
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(5),
Q => \^q\(5),
R => srst
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(6),
Q => \^q\(6),
R => srst
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(7),
Q => \^q\(7),
R => srst
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(8),
Q => \^q\(8),
R => srst
);
\gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(9),
Q => \^q\(9),
R => srst
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
Q => p_12_out(0),
S => srst
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(1),
Q => p_12_out(1),
R => srst
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(2),
Q => p_12_out(2),
R => srst
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(3),
Q => p_12_out(3),
R => srst
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(4),
Q => p_12_out(4),
R => srst
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(5),
Q => p_12_out(5),
R => srst
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(6),
Q => p_12_out(6),
R => srst
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(7),
Q => p_12_out(7),
R => srst
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(8),
Q => p_12_out(8),
R => srst
);
\gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(9),
Q => p_12_out(9),
R => srst
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_reg[9]\(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => ram_empty_i_reg
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_reg[9]\(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => ram_empty_i_reg_0
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_reg[9]\(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => p_12_out(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => ram_empty_i_reg_1
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_reg[9]\(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => p_12_out(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => ram_empty_i_reg_2
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_reg[9]\(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => p_12_out(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => v1_reg_1(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => ram_empty_i_reg_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end output_fifo_blk_mem_gen_prim_width;
architecture STRUCTURE of output_fifo_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.output_fifo_blk_mem_gen_prim_wrapper
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_rd_status_flags_ss : entity is "rd_status_flags_ss";
end output_fifo_rd_status_flags_ss;
architecture STRUCTURE of output_fifo_rd_status_flags_ss is
signal c1_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => ram_empty_fb_i,
I1 => rd_en,
I2 => srst,
O => tmp_ram_rd_en
);
c1: entity work.output_fifo_compare_1
port map (
comp1 => comp1,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => ram_empty_fb_i,
ram_empty_i_reg => c1_n_0,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
wr_en => wr_en
);
c2: entity work.output_fifo_compare_2
port map (
comp1 => comp1,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
\gbm.gregce.ram_rd_en_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_fb_i,
S => srst
);
ram_empty_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_i,
S => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_wr_status_flags_ss : entity is "wr_status_flags_ss";
end output_fifo_wr_status_flags_ss;
architecture STRUCTURE of output_fifo_wr_status_flags_ss is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c0: entity work.output_fifo_compare
port map (
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en
);
c1: entity work.output_fifo_compare_0
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_fb_i,
R => srst
);
ram_full_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_i,
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end output_fifo_blk_mem_gen_generic_cstr;
architecture STRUCTURE of output_fifo_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.output_fifo_blk_mem_gen_prim_width
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_rd_logic : entity is "rd_logic";
end output_fifo_rd_logic;
architecture STRUCTURE of output_fifo_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\grss.rsts\: entity work.output_fifo_rd_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en
);
rpntr: entity work.output_fifo_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0),
E(0) => \^e\(0),
Q(9 downto 0) => Q(9 downto 0),
clk => clk,
srst => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
WEA : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_wr_logic : entity is "wr_logic";
end output_fifo_wr_logic;
architecture STRUCTURE of output_fifo_wr_logic is
signal \^wea\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
WEA(0) <= \^wea\(0);
\gwss.wsts\: entity work.output_fifo_wr_status_flags_ss
port map (
E(0) => \^wea\(0),
clk => clk,
full => full,
\out\ => \out\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
rd_en => rd_en,
srst => srst,
v1_reg(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \c1/v1_reg\(4 downto 0),
wr_en => wr_en
);
wpntr: entity work.output_fifo_wr_bin_cntr
port map (
E(0) => \^wea\(0),
Q(9 downto 0) => Q(9 downto 0),
clk => clk,
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => \gc0.count_reg[9]\(9 downto 0),
ram_empty_i_reg => ram_empty_i_reg,
ram_empty_i_reg_0 => ram_empty_i_reg_0,
ram_empty_i_reg_1 => ram_empty_i_reg_1,
ram_empty_i_reg_2 => ram_empty_i_reg_2,
ram_empty_i_reg_3 => ram_empty_i_reg_3,
srst => srst,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_1(4 downto 0) => \c1/v1_reg\(4 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_top : entity is "blk_mem_gen_top";
end output_fifo_blk_mem_gen_top;
architecture STRUCTURE of output_fifo_blk_mem_gen_top is
begin
\valid.cstr\: entity work.output_fifo_blk_mem_gen_generic_cstr
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_v8_3_5_synth is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end output_fifo_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of output_fifo_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.output_fifo_blk_mem_gen_top
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_blk_mem_gen_v8_3_5 is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
ram_rd_en_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
end output_fifo_blk_mem_gen_v8_3_5;
architecture STRUCTURE of output_fifo_blk_mem_gen_v8_3_5 is
begin
inst_blk_mem_gen: entity work.output_fifo_blk_mem_gen_v8_3_5_synth
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_memory is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_memory : entity is "memory";
end output_fifo_memory;
architecture STRUCTURE of output_fifo_memory is
signal ram_rd_en_d1 : STD_LOGIC;
begin
\gbm.gbmg.gbmgc.ngecc.bmg\: entity work.output_fifo_blk_mem_gen_v8_3_5
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
ram_rd_en_d1 => ram_rd_en_d1,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\gbm.gregce.ram_rd_en_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => E(0),
Q => ram_rd_en_d1,
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end output_fifo_fifo_generator_ramfifo;
architecture STRUCTURE of output_fifo_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_18\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_19\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_20\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_21\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_22\ : STD_LOGIC;
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.output_fifo_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(9 downto 0) => p_0_out(9 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(9 downto 0) => rd_pntr_plus1(9 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_18\,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_19\,
\gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_20\,
\gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_21\,
\gcc0.gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_22\,
\out\ => p_2_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.output_fifo_wr_logic
port map (
Q(9 downto 0) => p_11_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
full => full,
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_18\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_19\,
ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_20\,
ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_21\,
ram_empty_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_22\,
rd_en => rd_en,
srst => srst,
v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.output_fifo_memory
port map (
E(0) => \gntv_or_sync_fifo.gl0.rd_n_2\,
Q(9 downto 0) => p_11_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_top : entity is "fifo_generator_top";
end output_fifo_fifo_generator_top;
architecture STRUCTURE of output_fifo_fifo_generator_top is
begin
\grf.rf\: entity work.output_fifo_fifo_generator_ramfifo
port map (
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_v13_1_3_synth is
port (
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth";
end output_fifo_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of output_fifo_fifo_generator_v13_1_3_synth is
begin
\gconvfifo.rf\: entity work.output_fifo_fifo_generator_top
port map (
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo_fifo_generator_v13_1_3 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of output_fifo_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 12;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of output_fifo_fifo_generator_v13_1_3 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 12;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of output_fifo_fifo_generator_v13_1_3 : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of output_fifo_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of output_fifo_fifo_generator_v13_1_3 : entity is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of output_fifo_fifo_generator_v13_1_3 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of output_fifo_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of output_fifo_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of output_fifo_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of output_fifo_fifo_generator_v13_1_3 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of output_fifo_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3";
end output_fifo_fifo_generator_v13_1_3;
architecture STRUCTURE of output_fifo_fifo_generator_v13_1_3 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.output_fifo_fifo_generator_v13_1_3_synth
port map (
clk => clk,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity output_fifo is
port (
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 11 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of output_fifo : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of output_fifo : entity is "output_fifo,fifo_generator_v13_1_3,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of output_fifo : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of output_fifo : entity is "fifo_generator_v13_1_3,Vivado 2016.4";
end output_fifo;
architecture STRUCTURE of output_fifo is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 12;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 12;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 2;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 1;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.output_fifo_fifo_generator_v13_1_3
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(11 downto 0) => din(11 downto 0),
dout(11 downto 0) => dout(11 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => '0',
rd_data_count(9 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => '0',
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => srst,
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(9 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
| unlicense |
TWW12/lzw | ip_repo/axi_compression_1.0/src/dictionary_4.vhd | 4 | 7518 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity dictionary_4 is
port (
clk : in std_logic;
rst : in std_logic;
start_search : in std_logic;
search_entry : in std_logic_vector(19 downto 0);
--Write enable & entries
wr_en : in std_logic;
wr_entry : in std_logic_vector(19 downto 0);
--Outputs
prefix : out std_logic_vector(11 downto 0);
entry_found : out std_logic;
search_completed : out std_logic;
dictionary_full : out std_logic);
end dictionary_4;
architecture Behavioral of dictionary_4 is
signal wr_addr_shift : std_logic_vector(11 downto 0);
signal search_completed_i : std_logic;
signal full : std_logic;
signal wr_addr : std_logic_vector(11 downto 0);
signal halt_search : std_logic;
signal block0_wr_en : std_logic;
signal block0_prefix : std_logic_vector(9 downto 0);
signal block0_entry_found : std_logic;
signal block0_search_completed : std_logic;
signal block1_wr_en : std_logic;
signal block1_prefix : std_logic_vector(9 downto 0);
signal block1_entry_found : std_logic;
signal block1_search_completed : std_logic;
signal block2_wr_en : std_logic;
signal block2_prefix : std_logic_vector(9 downto 0);
signal block2_entry_found : std_logic;
signal block2_search_completed : std_logic;
signal block3_wr_en : std_logic;
signal block3_prefix : std_logic_vector(9 downto 0);
signal block3_entry_found : std_logic;
signal block3_search_completed : std_logic;
--Registered signals to improve timing
signal r_block0_wr_en : std_logic;
signal r_block1_wr_en : std_logic;
signal r_block2_wr_en : std_logic;
signal r_block3_wr_en : std_logic;
signal r_start_search : std_logic;
signal r_search_entry : std_logic_vector(19 downto 0);
signal r_wr_addr : std_logic_vector(11 downto 0);
signal r_wr_entry : std_logic_vector(19 downto 0);
begin
process(clk,rst)
begin
if rst = '1' then
r_block0_wr_en <= '0';
r_block1_wr_en <= '0';
r_block2_wr_en <= '0';
r_block3_wr_en <= '0';
r_wr_addr <= (others => '0');
r_wr_entry <= (others => '0');
elsif rising_edge(clk) then
r_wr_addr <= wr_addr;
r_wr_entry <= wr_entry;
r_block0_wr_en <= block0_wr_en;
r_block1_wr_en <= block1_wr_en;
r_block2_wr_en <= block2_wr_en;
r_block3_wr_en <= block3_wr_en;
end if;
end process;
wr_addr_shift(11 downto 2) <= wr_addr(9 downto 0);
wr_addr_shift(1 downto 0) <= "00";
--Combines all signals from blocks
search_completed <= search_completed_i;
process(clk,rst)
begin
if rst = '1' then
block1_wr_en <= '0';
block0_wr_en <= '0';
block2_wr_en <= '0';
block3_wr_en <= '0';
search_completed_i <= '0';
entry_found <= '0';
prefix <= x"000";
elsif rising_edge(clk) then
block3_wr_en <= not wr_addr(0) and wr_addr(1) and wr_en;
block0_wr_en <= wr_addr(0) and wr_addr(1) and wr_en;
block1_wr_en <= not wr_addr(0) and not wr_addr(1) and wr_en;
block2_wr_en <= wr_addr(0) and not wr_addr(1) and wr_en;
search_completed_i <= block0_search_completed or block1_search_completed or block2_search_completed or block3_search_completed;
entry_found <= block0_entry_found or block1_entry_found or block2_entry_found or block3_entry_found;
if block0_entry_found = '1' then
if block0_prefix = "0000000000" then
prefix <= x"001";
else
prefix(11 downto 2) <= std_logic_vector(unsigned(block0_prefix)-to_unsigned(1,10));
prefix(1 downto 0) <= "01";
end if;
elsif block1_entry_found = '1' then
prefix(11 downto 2) <= std_logic_vector(unsigned(block1_prefix)-to_unsigned(1,10));
prefix(1 downto 0) <= "10";
elsif block2_entry_found = '1' then
prefix(11 downto 2) <= std_logic_vector(unsigned(block2_prefix)-to_unsigned(1,10));
prefix(1 downto 0) <= "11";
elsif block3_entry_found = '1' then
prefix(11 downto 2) <= block3_prefix;
prefix(1 downto 0) <= "00";
end if;
end if;
end process;
U_BLOCK_0 : entity work.dictionary_block_4
generic map (block_num => 0)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
halt_search => search_completed_i,
wr_en => r_block0_wr_en,
wr_addr => r_wr_addr(11 downto 2),
wr_entry => r_wr_entry,
prefix => block0_prefix,
entry_found => block0_entry_found,
search_completed => block0_search_completed);
U_BLOCK_1 : entity work.dictionary_block_4
generic map (block_num => 1)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => r_block1_wr_en,
wr_addr => r_wr_addr(11 downto 2),
wr_entry => r_wr_entry,
halt_search => search_completed_i,
prefix => block1_prefix,
entry_found => block1_entry_found,
search_completed => block1_search_completed);
U_BLOCK_2 : entity work.dictionary_block_4
generic map (block_num => 2)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => r_block2_wr_en,
wr_addr => r_wr_addr(11 downto 2),
wr_entry => r_wr_entry,
halt_search => search_completed_i,
prefix => block2_prefix,
entry_found => block2_entry_found,
search_completed => block2_search_completed);
U_BLOCK_3 : entity work.dictionary_block_4
generic map (block_num => 3)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => r_block3_wr_en,
wr_addr => r_wr_addr(11 downto 2),
wr_entry => r_wr_entry,
halt_search => search_completed_i,
prefix => block3_prefix,
entry_found => block3_entry_found,
search_completed => block3_search_completed);
--write proc
dictionary_full <= full;
process(clk,rst)
begin
if rst = '1' then
wr_addr <= std_logic_vector(to_unsigned(254,12));
full <= '0';
elsif rising_edge(clk) then
if wr_en = '1' and full = '0' then
wr_addr <= std_logic_vector(to_unsigned(1,12)+unsigned(wr_addr));
end if;
--last entry written should increment counter to "1000...000"
if wr_addr(11) = '1' then
full <= '1';
end if;
end if;
end process;
end Behavioral;
| unlicense |
TWW12/lzw | final_project/lzw_compression/lzw_compression.srcs/sources_1/bd/design_1/ipshared/f3c4/src/dictionary_4.vhd | 4 | 7518 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity dictionary_4 is
port (
clk : in std_logic;
rst : in std_logic;
start_search : in std_logic;
search_entry : in std_logic_vector(19 downto 0);
--Write enable & entries
wr_en : in std_logic;
wr_entry : in std_logic_vector(19 downto 0);
--Outputs
prefix : out std_logic_vector(11 downto 0);
entry_found : out std_logic;
search_completed : out std_logic;
dictionary_full : out std_logic);
end dictionary_4;
architecture Behavioral of dictionary_4 is
signal wr_addr_shift : std_logic_vector(11 downto 0);
signal search_completed_i : std_logic;
signal full : std_logic;
signal wr_addr : std_logic_vector(11 downto 0);
signal halt_search : std_logic;
signal block0_wr_en : std_logic;
signal block0_prefix : std_logic_vector(9 downto 0);
signal block0_entry_found : std_logic;
signal block0_search_completed : std_logic;
signal block1_wr_en : std_logic;
signal block1_prefix : std_logic_vector(9 downto 0);
signal block1_entry_found : std_logic;
signal block1_search_completed : std_logic;
signal block2_wr_en : std_logic;
signal block2_prefix : std_logic_vector(9 downto 0);
signal block2_entry_found : std_logic;
signal block2_search_completed : std_logic;
signal block3_wr_en : std_logic;
signal block3_prefix : std_logic_vector(9 downto 0);
signal block3_entry_found : std_logic;
signal block3_search_completed : std_logic;
--Registered signals to improve timing
signal r_block0_wr_en : std_logic;
signal r_block1_wr_en : std_logic;
signal r_block2_wr_en : std_logic;
signal r_block3_wr_en : std_logic;
signal r_start_search : std_logic;
signal r_search_entry : std_logic_vector(19 downto 0);
signal r_wr_addr : std_logic_vector(11 downto 0);
signal r_wr_entry : std_logic_vector(19 downto 0);
begin
process(clk,rst)
begin
if rst = '1' then
r_block0_wr_en <= '0';
r_block1_wr_en <= '0';
r_block2_wr_en <= '0';
r_block3_wr_en <= '0';
r_wr_addr <= (others => '0');
r_wr_entry <= (others => '0');
elsif rising_edge(clk) then
r_wr_addr <= wr_addr;
r_wr_entry <= wr_entry;
r_block0_wr_en <= block0_wr_en;
r_block1_wr_en <= block1_wr_en;
r_block2_wr_en <= block2_wr_en;
r_block3_wr_en <= block3_wr_en;
end if;
end process;
wr_addr_shift(11 downto 2) <= wr_addr(9 downto 0);
wr_addr_shift(1 downto 0) <= "00";
--Combines all signals from blocks
search_completed <= search_completed_i;
process(clk,rst)
begin
if rst = '1' then
block1_wr_en <= '0';
block0_wr_en <= '0';
block2_wr_en <= '0';
block3_wr_en <= '0';
search_completed_i <= '0';
entry_found <= '0';
prefix <= x"000";
elsif rising_edge(clk) then
block3_wr_en <= not wr_addr(0) and wr_addr(1) and wr_en;
block0_wr_en <= wr_addr(0) and wr_addr(1) and wr_en;
block1_wr_en <= not wr_addr(0) and not wr_addr(1) and wr_en;
block2_wr_en <= wr_addr(0) and not wr_addr(1) and wr_en;
search_completed_i <= block0_search_completed or block1_search_completed or block2_search_completed or block3_search_completed;
entry_found <= block0_entry_found or block1_entry_found or block2_entry_found or block3_entry_found;
if block0_entry_found = '1' then
if block0_prefix = "0000000000" then
prefix <= x"001";
else
prefix(11 downto 2) <= std_logic_vector(unsigned(block0_prefix)-to_unsigned(1,10));
prefix(1 downto 0) <= "01";
end if;
elsif block1_entry_found = '1' then
prefix(11 downto 2) <= std_logic_vector(unsigned(block1_prefix)-to_unsigned(1,10));
prefix(1 downto 0) <= "10";
elsif block2_entry_found = '1' then
prefix(11 downto 2) <= std_logic_vector(unsigned(block2_prefix)-to_unsigned(1,10));
prefix(1 downto 0) <= "11";
elsif block3_entry_found = '1' then
prefix(11 downto 2) <= block3_prefix;
prefix(1 downto 0) <= "00";
end if;
end if;
end process;
U_BLOCK_0 : entity work.dictionary_block_4
generic map (block_num => 0)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
halt_search => search_completed_i,
wr_en => r_block0_wr_en,
wr_addr => r_wr_addr(11 downto 2),
wr_entry => r_wr_entry,
prefix => block0_prefix,
entry_found => block0_entry_found,
search_completed => block0_search_completed);
U_BLOCK_1 : entity work.dictionary_block_4
generic map (block_num => 1)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => r_block1_wr_en,
wr_addr => r_wr_addr(11 downto 2),
wr_entry => r_wr_entry,
halt_search => search_completed_i,
prefix => block1_prefix,
entry_found => block1_entry_found,
search_completed => block1_search_completed);
U_BLOCK_2 : entity work.dictionary_block_4
generic map (block_num => 2)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => r_block2_wr_en,
wr_addr => r_wr_addr(11 downto 2),
wr_entry => r_wr_entry,
halt_search => search_completed_i,
prefix => block2_prefix,
entry_found => block2_entry_found,
search_completed => block2_search_completed);
U_BLOCK_3 : entity work.dictionary_block_4
generic map (block_num => 3)
port map(
clk => clk,
rst => rst,
start_search => start_search,
search_entry => search_entry,
wr_en => r_block3_wr_en,
wr_addr => r_wr_addr(11 downto 2),
wr_entry => r_wr_entry,
halt_search => search_completed_i,
prefix => block3_prefix,
entry_found => block3_entry_found,
search_completed => block3_search_completed);
--write proc
dictionary_full <= full;
process(clk,rst)
begin
if rst = '1' then
wr_addr <= std_logic_vector(to_unsigned(254,12));
full <= '0';
elsif rising_edge(clk) then
if wr_en = '1' and full = '0' then
wr_addr <= std_logic_vector(to_unsigned(1,12)+unsigned(wr_addr));
end if;
--last entry written should increment counter to "1000...000"
if wr_addr(11) = '1' then
full <= '1';
end if;
end if;
end process;
end Behavioral;
| unlicense |
TWW12/lzw | ip_repo/axi_compression_1.0/src/bram_1024_2/misc/blk_mem_gen_v8_3.vhd | 45 | 8325 | library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_3_5 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_3_5;
architecture xilinx of blk_mem_gen_v8_3_5 is
begin
end
architecture xilinx;
| unlicense |
TWW12/lzw | final_project_sim/lzw/lzw.cache/ip/04a7882d00f7897d/bram_1024_3_stub.vhdl | 1 | 1611 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:54 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_1024_3_stub.vhdl
-- Design : bram_1024_3
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[9:0],dina[19:0],douta[19:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
| unlicense |
TWW12/lzw | final_project_sim/lzw/lzw.cache/ip/42f801f2e04cbe7d/bram_1024_0_stub.vhdl | 1 | 1611 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:54 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_1024_0_stub.vhdl
-- Design : bram_1024_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[9:0],dina[19:0],douta[19:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
| unlicense |
TWW12/lzw | final_project_sim/lzw/lzw.ip_user_files/ip/bram_1024_1/bram_1024_1_stub.vhdl | 2 | 1475 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:14 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_1/bram_1024_1_stub.vhdl
-- Design : bram_1024_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bram_1024_1 is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
end bram_1024_1;
architecture stub of bram_1024_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[9:0],dina[19:0],douta[19:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
| unlicense |
TWW12/lzw | ip_repo/axi_compression_1.0/src/input_fifo/synth/input_fifo.vhd | 2 | 38764 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY input_fifo IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END input_fifo;
ARCHITECTURE input_fifo_arch OF input_fifo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF input_fifo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF input_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF input_fifo_arch : ARCHITECTURE IS "input_fifo,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF input_fifo_arch: ARCHITECTURE IS "input_fifo,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=11,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=8,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_" &
"FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=1kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1023,C_PROG_FULL_THRESH_NE" &
"GATE_VAL=1022,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=11,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=11,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TY" &
"PE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C" &
"_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH" &
"=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_I" &
"NJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_" &
"PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_P" &
"ROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL" &
"_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 11,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 8,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "1kx18",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1023,
C_PROG_FULL_THRESH_NEGATE_VAL => 1022,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 11,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 11,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END input_fifo_arch;
| unlicense |
TWW12/lzw | ip_repo/axi_compression_1.0/src/bram_1024_0/synth/bram_1024_0.vhd | 4 | 14457 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_1024_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_1024_0;
ARCHITECTURE bram_1024_0_arch OF bram_1024_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_1024_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_1024_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_1024_0_arch : ARCHITECTURE IS "bram_1024_0,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_1024_0_arch: ARCHITECTURE IS "bram_1024_0,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_1024_0.mi" &
"f,C_INIT_FILE=bram_1024_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=1024,C_READ_DEPTH_A=1024,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=1024,C_READ_DEPTH_B=1024,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.74095 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_1024_0.mif",
C_INIT_FILE => "bram_1024_0.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 1024,
C_READ_DEPTH_A => 1024,
C_ADDRA_WIDTH => 10,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 1024,
C_READ_DEPTH_B => 1024,
C_ADDRB_WIDTH => 10,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.74095 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_1024_0_arch;
| unlicense |
sahandKashani/TRDB_D5M | DE0-Nano/hw/hdl/cmos_sensor_input/hdl/cmos_sensor_input_sc_fifo.vhd | 5 | 4445 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_sc_fifo is
generic(
DATA_WIDTH : positive;
FIFO_DEPTH : positive;
DEVICE_FAMILY : string
);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
read : in std_logic;
write : in std_logic;
empty : out std_logic;
full : out std_logic;
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 1 downto 0);
overflow : out std_logic
);
end cmos_sensor_input_sc_fifo;
architecture rtl of cmos_sensor_input_sc_fifo is
component scfifo
generic(
add_ram_output_register : string;
intended_device_family : string;
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
underflow_checking : string;
use_eab : string
);
port(
clock : in std_logic;
data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
rdreq : in std_logic;
sclr : in std_logic;
wrreq : in std_logic;
empty : out std_logic;
full : out std_logic;
q : out std_logic_vector(DATA_WIDTH - 1 downto 0);
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0)
);
end component;
signal scfifo_clock : std_logic;
signal scfifo_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_rdreq : std_logic;
signal scfifo_sclr : std_logic;
signal scfifo_wrreq : std_logic;
signal scfifo_empty : std_logic;
signal scfifo_full : std_logic;
signal scfifo_q : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_usedw : std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0);
signal reg_overflow : std_logic;
begin
FIFO_OVERFLOW : process(clk, reset)
begin
if reset = '1' then
reg_overflow <= '0';
elsif rising_edge(clk) then
if clr = '1' then
reg_overflow <= '0';
else
reg_overflow <= reg_overflow or (write and scfifo_full);
end if;
end if;
end process;
OUTPUTS : process(reg_overflow, scfifo_empty, scfifo_full, scfifo_q, scfifo_usedw)
begin
data_out <= scfifo_q;
empty <= scfifo_empty;
full <= scfifo_full;
overflow <= reg_overflow;
if scfifo_full = '1' then
usedw <= std_logic_vector(to_unsigned(FIFO_DEPTH, usedw'length));
elsif scfifo_empty = '1' then
usedw <= std_logic_vector(to_unsigned(0, usedw'length));
else
usedw <= std_logic_vector(resize(unsigned(scfifo_usedw), usedw'length));
end if;
end process;
-- scfifo connections ------------------------------------------------------
scfifo_clock <= clk;
scfifo_data <= data_in;
scfifo_rdreq <= read and not scfifo_empty;
scfifo_sclr <= clr;
scfifo_wrreq <= write and not scfifo_full;
scfifo_component : scfifo
generic map(
add_ram_output_register => "OFF",
intended_device_family => DEVICE_FAMILY,
lpm_numwords => FIFO_DEPTH,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => DATA_WIDTH,
lpm_widthu => bit_width(FIFO_DEPTH) - 1,
overflow_checking => "OFF",
underflow_checking => "OFF",
use_eab => "ON"
)
port map(
clock => scfifo_clock,
data => scfifo_data,
rdreq => scfifo_rdreq,
sclr => scfifo_sclr,
wrreq => scfifo_wrreq,
empty => scfifo_empty,
full => scfifo_full,
q => scfifo_q,
usedw => scfifo_usedw
);
end rtl;
| unlicense |
sahandKashani/TRDB_D5M | DE1-SoC/hw/hdl/DE1_SoC_TRDB_D5M_top_level.vhd | 2 | 10224 | -- #############################################################################
-- DE1_SoC_TRDB_D5M_top_level.vhd
--
-- BOARD : DE1-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.6
-- Creation date : 04/02/2015
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE1_SoC_TRDB_D5M_top_level is
port(
---- ADC
--ADC_CS_n : out std_logic;
--ADC_DIN : out std_logic;
--ADC_DOUT : in std_logic;
--ADC_SCLK : out std_logic;
---- Audio
--AUD_ADCDAT : in std_logic;
--AUD_ADCLRCK : inout std_logic;
--AUD_BCLK : inout std_logic;
--AUD_DACDAT : out std_logic;
--AUD_DACLRCK : inout std_logic;
--AUD_XCK : out std_logic;
-- CLOCK
CLOCK_50 : in std_logic;
--CLOCK2_50 : in std_logic;
--CLOCK3_50 : in std_logic;
--CLOCK4_50 : in std_logic;
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_LDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_WE_N : out std_logic;
---- I2C for Audio and Video-In
--FPGA_I2C_SCLK : out std_logic;
--FPGA_I2C_SDAT : inout std_logic;
---- SEG7
--HEX0_N : out std_logic_vector(6 downto 0);
--HEX1_N : out std_logic_vector(6 downto 0);
--HEX2_N : out std_logic_vector(6 downto 0);
--HEX3_N : out std_logic_vector(6 downto 0);
--HEX4_N : out std_logic_vector(6 downto 0);
--HEX5_N : out std_logic_vector(6 downto 0);
---- IR
--IRDA_RXD : in std_logic;
--IRDA_TXD : out std_logic;
---- KEY_N
--KEY_N : in std_logic_vector(3 downto 0);
---- LED
--LEDR : out std_logic_vector(9 downto 0);
---- PS2
--PS2_CLK : inout std_logic;
--PS2_CLK2 : inout std_logic;
--PS2_DAT : inout std_logic;
--PS2_DAT2 : inout std_logic;
---- SW
--SW : in std_logic_vector(9 downto 0);
---- Video-In
--TD_CLK27 : inout std_logic;
--TD_DATA : out std_logic_vector(7 downto 0);
--TD_HS : out std_logic;
--TD_RESET_N : out std_logic;
--TD_VS : out std_logic;
---- VGA
--VGA_B : out std_logic_vector(7 downto 0);
--VGA_BLANK_N : out std_logic;
--VGA_CLK : out std_logic;
--VGA_G : out std_logic_vector(7 downto 0);
--VGA_HS : out std_logic;
--VGA_R : out std_logic_vector(7 downto 0);
--VGA_SYNC_N : out std_logic;
--VGA_VS : out std_logic;
-- GPIO_0
GPIO_0_D5M_D : in std_logic_vector(11 downto 0);
GPIO_0_D5M_FVAL : in std_logic;
GPIO_0_D5M_LVAL : in std_logic;
GPIO_0_D5M_PIXCLK : in std_logic;
GPIO_0_D5M_RESET_N : out std_logic;
GPIO_0_D5M_SCLK : inout std_logic;
GPIO_0_D5M_SDATA : inout std_logic;
GPIO_0_D5M_STROBE : in std_logic;
GPIO_0_D5M_TRIGGER : out std_logic;
GPIO_0_D5M_XCLKIN : out std_logic
---- GPIO_1
--GPIO_1 : inout std_logic_vector(35 downto 0);
---- HPS
--HPS_CONV_USB_N : inout std_logic;
--HPS_DDR3_ADDR : out std_logic_vector(14 downto 0);
--HPS_DDR3_BA : out std_logic_vector(2 downto 0);
--HPS_DDR3_CAS_N : out std_logic;
--HPS_DDR3_CK_N : out std_logic;
--HPS_DDR3_CK_P : out std_logic;
--HPS_DDR3_CKE : out std_logic;
--HPS_DDR3_CS_N : out std_logic;
--HPS_DDR3_DM : out std_logic_vector(3 downto 0);
--HPS_DDR3_DQ : inout std_logic_vector(31 downto 0);
--HPS_DDR3_DQS_N : inout std_logic_vector(3 downto 0);
--HPS_DDR3_DQS_P : inout std_logic_vector(3 downto 0);
--HPS_DDR3_ODT : out std_logic;
--HPS_DDR3_RAS_N : out std_logic;
--HPS_DDR3_RESET_N : out std_logic;
--HPS_DDR3_RZQ : in std_logic;
--HPS_DDR3_WE_N : out std_logic;
--HPS_ENET_GTX_CLK : out std_logic;
--HPS_ENET_INT_N : inout std_logic;
--HPS_ENET_MDC : out std_logic;
--HPS_ENET_MDIO : inout std_logic;
--HPS_ENET_RX_CLK : in std_logic;
--HPS_ENET_RX_DATA : in std_logic_vector(3 downto 0);
--HPS_ENET_RX_DV : in std_logic;
--HPS_ENET_TX_DATA : out std_logic_vector(3 downto 0);
--HPS_ENET_TX_EN : out std_logic;
--HPS_FLASH_DATA : inout std_logic_vector(3 downto 0);
--HPS_FLASH_DCLK : out std_logic;
--HPS_FLASH_NCSO : out std_logic;
--HPS_GSENSOR_INT : inout std_logic;
--HPS_I2C_CONTROL : inout std_logic;
--HPS_I2C1_SCLK : inout std_logic;
--HPS_I2C1_SDAT : inout std_logic;
--HPS_I2C2_SCLK : inout std_logic;
--HPS_I2C2_SDAT : inout std_logic;
--HPS_KEY_N : inout std_logic;
--HPS_LED : inout std_logic;
--HPS_LTC_GPIO : inout std_logic;
--HPS_SD_CLK : out std_logic;
--HPS_SD_CMD : inout std_logic;
--HPS_SD_DATA : inout std_logic_vector(3 downto 0);
--HPS_SPIM_CLK : out std_logic;
--HPS_SPIM_MISO : in std_logic;
--HPS_SPIM_MOSI : out std_logic;
--HPS_SPIM_SS : inout std_logic;
--HPS_UART_RX : in std_logic;
--HPS_UART_TX : out std_logic;
--HPS_USB_CLKOUT : in std_logic;
--HPS_USB_DATA : inout std_logic_vector(7 downto 0);
--HPS_USB_DIR : in std_logic;
--HPS_USB_NXT : in std_logic;
--HPS_USB_STP : out std_logic
);
end entity DE1_SoC_TRDB_D5M_top_level;
architecture rtl of DE1_SoC_TRDB_D5M_top_level is
component system is
port(
clk_clk : in std_logic := 'X';
reset_reset_n : in std_logic := 'X';
sdram_clk_clk : out std_logic;
sdram_controller_addr : out std_logic_vector(12 downto 0);
sdram_controller_ba : out std_logic_vector(1 downto 0);
sdram_controller_cas_n : out std_logic;
sdram_controller_cke : out std_logic;
sdram_controller_cs_n : out std_logic;
sdram_controller_dq : inout std_logic_vector(15 downto 0) := (others => 'X');
sdram_controller_dqm : out std_logic_vector(1 downto 0);
sdram_controller_ras_n : out std_logic;
sdram_controller_we_n : out std_logic;
trdb_d5m_xclkin_clk : out std_logic;
trdb_d5m_cmos_sensor_frame_valid : in std_logic := 'X';
trdb_d5m_cmos_sensor_line_valid : in std_logic := 'X';
trdb_d5m_cmos_sensor_data : in std_logic_vector(11 downto 0) := (others => 'X');
trdb_d5m_i2c_scl : inout std_logic := 'X';
trdb_d5m_i2c_sda : inout std_logic := 'X';
trdb_d5m_pixclk_clk : in std_logic := 'X'
);
end component system;
begin
GPIO_0_D5M_RESET_N <= '1';
GPIO_0_D5M_TRIGGER <= '0';
system_inst : component system
port map(
clk_clk => CLOCK_50,
reset_reset_n => '1',
sdram_clk_clk => DRAM_CLK,
sdram_controller_addr => DRAM_ADDR,
sdram_controller_ba => DRAM_BA,
sdram_controller_cas_n => DRAM_CAS_N,
sdram_controller_cke => DRAM_CKE,
sdram_controller_cs_n => DRAM_CS_N,
sdram_controller_dq => DRAM_DQ,
sdram_controller_dqm(1) => DRAM_UDQM,
sdram_controller_dqm(0) => DRAM_LDQM,
sdram_controller_ras_n => DRAM_RAS_N,
sdram_controller_we_n => DRAM_WE_N,
trdb_d5m_xclkin_clk => GPIO_0_D5M_XCLKIN,
trdb_d5m_cmos_sensor_frame_valid => GPIO_0_D5M_FVAL,
trdb_d5m_cmos_sensor_line_valid => GPIO_0_D5M_LVAL,
trdb_d5m_cmos_sensor_data => GPIO_0_D5M_D,
trdb_d5m_i2c_scl => GPIO_0_D5M_SCLK,
trdb_d5m_i2c_sda => GPIO_0_D5M_SDATA,
trdb_d5m_pixclk_clk => GPIO_0_D5M_PIXCLK
);
end;
| unlicense |
sahandKashani/TRDB_D5M | DE0-Nano/hw/hdl/cmos_sensor_input/hdl/cmos_sensor_input_avalon_mm_slave.vhd | 5 | 9061 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_avalon_mm_slave is
generic(
DEBAYER_ENABLE : boolean;
FIFO_DEPTH : positive;
MAX_WIDTH : positive;
MAX_HEIGHT : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- Avalon-MM Slave
addr : in std_logic_vector(1 downto 0);
read : in std_logic;
write : in std_logic;
rddata : out std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
wrdata : in std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
-- Avalon Interrupt Sender
irq : out std_logic;
-- sampler
idle : in std_logic;
snapshot : out std_logic;
get_frame_info : out std_logic;
irq_en : out std_logic;
irq_ack : out std_logic;
wait_irq_ack : in std_logic;
frame_width : in std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
frame_height : in std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
-- debayer
debayer_pattern : out std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1 downto 0);
-- fifo
fifo_usedw : in std_logic_vector(bit_width(FIFO_DEPTH) - 1 downto 0);
fifo_overflow : in std_logic;
-- sampler / debayer / packer / fifo / st_source
stop_and_reset : out std_logic
);
end entity cmos_sensor_input_avalon_mm_slave;
architecture rtl of cmos_sensor_input_avalon_mm_slave is
-- MM_WRITE
signal reg_snapshot : std_logic;
signal reg_get_frame_info : std_logic;
signal reg_irq_en : std_logic;
signal reg_irq_ack : std_logic;
signal reg_debayer_pattern : std_logic_vector(debayer_pattern'range);
signal reg_stop_and_reset : std_logic;
begin
-- registered outputs
irq <= wait_irq_ack;
irq_en <= reg_irq_en;
irq_ack <= reg_irq_ack;
snapshot <= reg_snapshot;
get_frame_info <= reg_get_frame_info;
debayer_pattern <= reg_debayer_pattern;
stop_and_reset <= reg_stop_and_reset;
MM_WRITE : process(clk, reset)
variable wrdata_config_irq : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_IRQ_WIDTH - 1 downto 0);
variable wrdata_config_debayer_pattern : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1 downto 0);
variable wrdata_command : std_logic_vector(CMOS_SENSOR_INPUT_COMMAND_WIDTH - 1 downto 0);
begin
if reset = '1' then
reg_snapshot <= '0';
reg_get_frame_info <= '0';
reg_irq_en <= '0';
reg_irq_ack <= '0';
reg_debayer_pattern <= CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_RGGB;
reg_stop_and_reset <= '0';
elsif rising_edge(clk) then
reg_snapshot <= '0';
reg_get_frame_info <= '0';
reg_irq_ack <= '0';
reg_stop_and_reset <= '0';
if write = '1' then
case addr is
when CMOS_SENSOR_INPUT_CONFIG_OFST =>
-- prevent changing config when unit is running
if idle = '1' then
wrdata_config_irq := wrdata(CMOS_SENSOR_INPUT_CONFIG_IRQ_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_IRQ_LOW_BIT_OFST);
wrdata_config_debayer_pattern := wrdata(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_LOW_BIT_OFST);
-- irq
if wrdata_config_irq = CMOS_SENSOR_INPUT_CONFIG_IRQ_ENABLE then
reg_irq_en <= '1';
elsif wrdata_config_irq = CMOS_SENSOR_INPUT_CONFIG_IRQ_DISABLE then
reg_irq_en <= '0';
end if;
-- debayer
reg_debayer_pattern <= (others => '0'); -- needed to avoid latch generation if DEBAYER_ENABLE = false
if DEBAYER_ENABLE then
reg_debayer_pattern <= wrdata_config_debayer_pattern;
end if;
end if;
when CMOS_SENSOR_INPUT_COMMAND_OFST =>
wrdata_command := wrdata(CMOS_SENSOR_INPUT_COMMAND_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_COMMAND_LOW_BIT_OFST);
if wrdata_command = CMOS_SENSOR_INPUT_COMMAND_SNAPSHOT then
-- only allow state change when unit is idle
if idle = '1' then
reg_snapshot <= '1';
end if;
elsif wrdata_command = CMOS_SENSOR_INPUT_COMMAND_GET_FRAME_INFO then
-- only allow frame info to change when unit is idle
if idle = '1' then
reg_get_frame_info <= '1';
end if;
elsif wrdata_command = CMOS_SENSOR_INPUT_COMMAND_IRQ_ACK then
-- will only accept an irq acknowledgement if irq is enabled
if reg_irq_en = '1' then
reg_irq_ack <= '1';
end if;
elsif wrdata_command = CMOS_SENSOR_INPUT_COMMAND_STOP_AND_RESET then
reg_stop_and_reset <= '1';
end if;
when others =>
null;
end case;
end if;
end if;
end process;
MM_READ : process(clk, reset)
begin
if reset = '1' then
rddata <= (others => '0');
elsif rising_edge(clk) then
rddata <= (others => '0');
if read = '1' then
case addr is
when CMOS_SENSOR_INPUT_CONFIG_OFST =>
if reg_irq_en = '1' then
rddata(CMOS_SENSOR_INPUT_CONFIG_IRQ_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_IRQ_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_CONFIG_IRQ_ENABLE;
else
rddata(CMOS_SENSOR_INPUT_CONFIG_IRQ_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_IRQ_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_CONFIG_IRQ_DISABLE;
end if;
if DEBAYER_ENABLE then
rddata(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_LOW_BIT_OFST) <= reg_debayer_pattern;
end if;
when CMOS_SENSOR_INPUT_STATUS_OFST =>
if idle = '1' then
rddata(CMOS_SENSOR_INPUT_STATUS_STATE_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_STATUS_STATE_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_STATUS_STATE_IDLE;
else
rddata(CMOS_SENSOR_INPUT_STATUS_STATE_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_STATUS_STATE_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_STATUS_STATE_BUSY;
end if;
if fifo_overflow = '1' then
rddata(CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_OVERFLOW;
else
rddata(CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_LOW_BIT_OFST) <= CMOS_SENSOR_INPUT_STATUS_FIFO_OVFL_NO_OVERFLOW;
end if;
rddata(CMOS_SENSOR_INPUT_STATUS_FIFO_USEDW_HIGH_BIT_0FST downto CMOS_SENSOR_INPUT_STATUS_FIFO_USEDW_LOW_BIT_OFST) <= std_logic_vector(resize(unsigned(fifo_usedw), CMOS_SENSOR_INPUT_STATUS_FIFO_USEDW_WIDTH));
when CMOS_SENSOR_INPUT_FRAME_INFO_OFST =>
rddata(CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_WIDTH_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_WIDTH_LOW_BIT_OFST) <= std_logic_vector(resize(unsigned(frame_width), CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_WIDTH_WIDTH));
rddata(CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_HEIGHT_HIGH_BIT_OFST downto CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_HEIGHT_LOW_BIT_OFST) <= std_logic_vector(resize(unsigned(frame_height), CMOS_SENSOR_INPUT_FRAME_INFO_FRAME_HEIGHT_WIDTH));
when others =>
null;
end case;
end if;
end if;
end process;
end architecture rtl;
| unlicense |
sahandKashani/TRDB_D5M | DE0-Nano/hw/hdl/DE0_Nano_TRDB_D5M_top_level.vhd | 2 | 5936 | -- #############################################################################
-- DE0_Nano_TRDB_D5M_top_level.vhd
--
-- BOARD : DE0-Nano from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.3
-- Creation date : 21/06/2015
--
-- Syntax Rule : GROUP_NAME_N[bit]
--
-- GROUP : specify a particular interface (ex: SDR_)
-- NAME : signal name (ex: CONFIG, D, ...)
-- bit : signal index
-- _N : to specify an active-low signal
-- #############################################################################
library ieee;
use ieee.std_logic_1164.all;
entity DE0_Nano_TRDB_D5M_top_level is
port(
-- CLOCK
CLOCK_50 : in std_logic;
-- LED
-- LED : out std_logic_vector(7 downto 0);
-- KEY_N
-- KEY_N : in std_logic_vector(1 downto 0);
-- SW
-- SW : in std_logic_vector(3 downto 0);
-- SDRAM
DRAM_ADDR : out std_logic_vector(12 downto 0);
DRAM_BA : out std_logic_vector(1 downto 0);
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
DRAM_DQ : inout std_logic_vector(15 downto 0);
DRAM_DQM : out std_logic_vector(1 downto 0);
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- EPCS
-- EPCS_ASDO : out std_logic;
-- EPCS_DATA0 : in std_logic;
-- EPCS_DCLK : out std_logic;
-- EPCS_NCSO : out std_logic;
-- Accelerometer and EEPROM
-- G_SENSOR_CS_N : out std_logic;
-- G_SENSOR_INT : in std_logic;
-- I2C_SCLK : out std_logic;
-- I2C_SDAT : inout std_logic;
-- ADC
-- ADC_CS_N : out std_logic;
-- ADC_SADDR : out std_logic;
-- ADC_SCLK : out std_logic;
-- ADC_SDAT : in std_logic;
-- 2x13 GPIO Header
-- GPIO_2 : inout std_logic_vector(12 downto 0);
-- GPIO_2_IN : in std_logic_vector(2 downto 0);
-- GPIO_0
GPIO_0_D5M_D : in std_logic_vector(11 downto 0);
GPIO_0_D5M_FVAL : in std_logic;
GPIO_0_D5M_LVAL : in std_logic;
GPIO_0_D5M_PIXCLK : in std_logic;
GPIO_0_D5M_RESET_N : out std_logic;
GPIO_0_D5M_SCLK : inout std_logic;
GPIO_0_D5M_SDATA : inout std_logic;
GPIO_0_D5M_STROBE : in std_logic;
GPIO_0_D5M_TRIGGER : out std_logic;
GPIO_0_D5M_XCLKIN : out std_logic
-- GPIO_1
-- GPIO_1 : inout std_logic_vector(33 downto 0);
-- GPIO_1_IN : in std_logic_vector(1 downto 0)
);
end entity DE0_Nano_TRDB_D5M_top_level;
architecture rtl of DE0_Nano_TRDB_D5M_top_level is
component system is
port(
clk_clk : in std_logic := 'X';
reset_reset_n : in std_logic := 'X';
sdram_clk_clk : out std_logic;
sdram_controller_addr : out std_logic_vector(12 downto 0);
sdram_controller_ba : out std_logic_vector(1 downto 0);
sdram_controller_cas_n : out std_logic;
sdram_controller_cke : out std_logic;
sdram_controller_cs_n : out std_logic;
sdram_controller_dq : inout std_logic_vector(15 downto 0) := (others => 'X');
sdram_controller_dqm : out std_logic_vector(1 downto 0);
sdram_controller_ras_n : out std_logic;
sdram_controller_we_n : out std_logic;
trdb_d5m_xclkin_clk : out std_logic;
trdb_d5m_cmos_sensor_frame_valid : in std_logic := 'X';
trdb_d5m_cmos_sensor_line_valid : in std_logic := 'X';
trdb_d5m_cmos_sensor_data : in std_logic_vector(11 downto 0) := (others => 'X');
trdb_d5m_i2c_scl : inout std_logic := 'X';
trdb_d5m_i2c_sda : inout std_logic := 'X';
trdb_d5m_pixclk_clk : in std_logic := 'X'
);
end component system;
begin
GPIO_0_D5M_RESET_N <= '1';
GPIO_0_D5M_TRIGGER <= '0';
system_inst : component system
port map(
clk_clk => CLOCK_50,
reset_reset_n => '1',
sdram_clk_clk => DRAM_CLK,
sdram_controller_addr => DRAM_ADDR,
sdram_controller_ba => DRAM_BA,
sdram_controller_cas_n => DRAM_CAS_N,
sdram_controller_cke => DRAM_CKE,
sdram_controller_cs_n => DRAM_CS_N,
sdram_controller_dq => DRAM_DQ,
sdram_controller_dqm => DRAM_DQM,
sdram_controller_ras_n => DRAM_RAS_N,
sdram_controller_we_n => DRAM_WE_N,
trdb_d5m_xclkin_clk => GPIO_0_D5M_XCLKIN,
trdb_d5m_cmos_sensor_frame_valid => GPIO_0_D5M_FVAL,
trdb_d5m_cmos_sensor_line_valid => GPIO_0_D5M_LVAL,
trdb_d5m_cmos_sensor_data => GPIO_0_D5M_D,
trdb_d5m_i2c_scl => GPIO_0_D5M_SCLK,
trdb_d5m_i2c_sda => GPIO_0_D5M_SDATA,
trdb_d5m_pixclk_clk => GPIO_0_D5M_PIXCLK
);
end;
| unlicense |
ricardo-jasinski/vhdl-game-engine | hdl/testbench/tbu_assert_pkg.vhd | 1 | 4334 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.float_pkg.all;
use work.tbu_text_out_pkg.all;
package tbu_assert_pkg is
constant REAL_DELTA_MAX: real := 0.001;
constant FLOAT_DELTA_MAX: real := 0.001;
procedure assert_that(msg: string; expr: boolean);
procedure assert_that(msg: string; expr: std_logic);
procedure assert_that(msg: string; actual, expected: std_logic_vector);
procedure assert_that(msg: string; actual, expected: unsigned);
procedure assert_that(msg: string; actual, expected, tolerance: real := REAL_DELTA_MAX);
procedure assert_that(msg: string; actual, expected: float; tolerance: real := FLOAT_DELTA_MAX);
procedure describe(function_name: string);
procedure should(msg: string; expr: boolean);
end;
package body tbu_assert_pkg is
procedure assert_that(msg: string; expr: boolean) is begin
assert expr report "error in test case '" & msg & "'" severity failure;
put("- " & msg);
end;
procedure assert_that(msg: string; expr: std_logic) is begin
assert_that(msg, ?? expr);
end;
function character_from_std_ulogic(value: std_ulogic) return character is
type conversion_array_type is array (std_ulogic) of character;
constant CONVERSION_ARRAY: conversion_array_type := (
'U' => 'U', 'X' => 'X', '0' => '0', '1' => '1',
'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-'
);
begin
return CONVERSION_ARRAY(value);
end;
function string_from_std_logic_vector(vector : std_logic_vector) return string is
variable vector_string : string(1 to vector'length);
begin
for i in vector'range loop
vector_string(i + 1) := character_from_std_ulogic(vector(i));
end loop;
return vector_string;
end;
procedure assert_that(msg : string; actual, expected: std_logic_vector) is
begin
put("- " & msg);
if (actual /= expected) then
report "error in test case '" & msg & "'" & LF & " " &
"actual: " & string_from_std_logic_vector(actual) & ", " &
"expected: " & string_from_std_logic_vector(expected)
severity failure;
end if;
end procedure;
procedure assert_that(msg : string; actual, expected: unsigned) is
begin
put("- " & msg);
if (actual /= expected) then
report "error in test case '" & msg & "'" & LF & " " &
"actual: " & to_string(actual) & ", " &
"expected: " & to_string(expected)
severity failure;
end if;
end procedure;
procedure assert_that(msg : string; actual, expected, tolerance: real := REAL_DELTA_MAX) is begin
put("- " & msg);
-- we need to check with "<=" because the default comparison result for
-- metavalues is 'false'; otherwise, whenever a value were 'X' the test would pass
if (abs(actual - expected) <= tolerance) then
return;
end if;
report "error in test case '" & msg & "'" & LF & " " &
"actual: " & to_string(actual) & ", " &
"expected: " & to_string(expected)
severity failure;
end procedure;
procedure assert_that(msg: string; actual, expected: float; tolerance: real := FLOAT_DELTA_MAX) is begin
put("- " & msg);
-- we need to check with "<=" because the default comparison result for
-- metavalues is 'false'; otherwise, whenever a value were 'X' the test would pass
if (abs(actual - expected) <= tolerance) then
return;
end if;
report "error in test case '" & msg & "'" & LF & " " &
"actual: " & to_string(to_real(actual)) & ", " &
"expected: " & to_string(to_real(expected))
severity failure;
end procedure;
procedure describe(function_name: string) is begin
put("Function " & function_name & " should:");
end;
procedure should(msg: string; expr: boolean) is begin
assert expr report "error in test case '" & msg & "'" severity failure;
put("- " & msg);
end;
end;
| unlicense |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/game/adventure_demo/resource_data_pkg.vhd | 1 | 11009 | use work.sprites_pkg.all;
use work.graphics_types_pkg.all;
use work.resource_handles_pkg.all;
use work.resource_handles_helper_pkg.all;
use work.npc_pkg.all;
package resource_data_pkg is
-- Here we define all the sprites used in the game
constant GAME_SPRITES: sprite_init_array_type := (
(SPRITE_PLAYER, bitmap_handle => BITMAP_SORCERER),
(SPRITE_AXE, bitmap_handle => BITMAP_AXE ),
(SPRITE_ARCHER, bitmap_handle => BITMAP_ARCHER ),
(SPRITE_CHEST, bitmap_handle => BITMAP_CHEST ),
(SPRITE_GHOST, bitmap_handle => BITMAP_GHOST ),
(SPRITE_SCORPION, bitmap_handle => BITMAP_SCORPION),
(SPRITE_ORYX_11, bitmap_handle => BITMAP_ORYX_11 ),
(SPRITE_ORYX_12, bitmap_handle => BITMAP_ORYX_12 ),
(SPRITE_ORYX_21, bitmap_handle => BITMAP_ORYX_21 ),
(SPRITE_ORYX_22, bitmap_handle => BITMAP_ORYX_22 ),
(SPRITE_BAT, bitmap_handle => BITMAP_BAT ),
(SPRITE_REAPER, bitmap_handle => BITMAP_REAPER )
);
constant GAME_COLLISIONS: sprite_collision_init_array_type := (
( COLLISION_PLAYER_GHOST, SPRITE_PLAYER, SPRITE_GHOST ),
( COLLISION_PLAYER_SCORPION, SPRITE_PLAYER, SPRITE_SCORPION ),
( COLLISION_PLAYER_ORYX, SPRITE_PLAYER, SPRITE_ORYX_11 ),
( COLLISION_PLAYER_CHEST, SPRITE_PLAYER, SPRITE_CHEST ),
( COLLISION_PLAYER_REAPER, SPRITE_PLAYER, SPRITE_REAPER )
);
-- Define the Non-Player Characters (NPCs) used in the game. NPCs have
-- their positions updated automatically; the user logic is responsible for
-- reading their positions and assigning them to the corresponding sprites
constant GAME_NPCS: npc_init_array_type := (
-- Ghost, moves around the chest in a diamond-shaped path
( NPC_GHOST,
make_npc_bouncer(
initial_position => (144, 64),
allowed_region => (128, 64, 160, 96),
initial_speed => (1, 1)
)),
-- Scorpion, moves horizontally accross the screen
( NPC_SCORPION,
make_npc_bouncer(
initial_position => (0, 128),
initial_speed => (1, 0)
)),
-- Bat, moves horizontally
( NPC_BAT,
make_npc_bouncer(
initial_position => (160, 160),
allowed_region => (0, 160, 300, 164),
initial_speed => (1, 1)
)),
-- Oryx, tries to kill the player with its sword
( NPC_ORYX,
make_npc_follower(
initial_position => (300, 220),
slowdown_factor => 2
)),
-- Archer, tries to hide behind the player
( NPC_ARCHER,
make_npc_follower(
initial_position => (0, 0),
slowdown_factor => 1
)),
-- Reaper, stays near the player
( NPC_REAPER,
make_npc_follower(
initial_position => (300, 64),
slowdown_factor => 4
))
);
-- Here we define the actual bitmaps for each sprite in the game. This is
-- the second step to add a new sprite in the game.
constant GAME_BITMAPS: bitmap_init_array_type := (
(
handle => BITMAP_SORCERER,
bitmap => (
(23, 23, 24, 24, 23, 0, 20, 20),
( 0, 23, 24, 24, 23, 23, 0, 20),
(23, 23, 57, 34, 57, 34, 0, 61),
( 0, 23, 23, 57, 57, 57, 0, 20),
(23, 23, 24, 24, 24, 23, 23, 57),
(57, 20, 20, 20, 19, 20, 0, 20),
( 0, 23, 23, 23, 23, 23, 0, 20),
(23, 19, 23, 23, 23, 19, 0, 19)
)
),
(
handle => BITMAP_AXE,
bitmap => (
( 0, 0, 0, 0, 0, 0, 0, 0),
( 0, 0, 0, 18, 0, 0, 37, 0),
( 0, 0, 0, 0, 18, 18, 0, 0),
( 0, 0, 0, 0, 18, 18, 18, 19),
( 0, 0, 0, 37, 0, 18, 19, 19),
( 0, 0, 37, 0, 0, 19, 19, 0),
( 0, 37, 0, 0, 0, 0, 0, 0),
(37, 0, 0, 0, 0, 0, 0, 0)
)
),
(
handle => BITMAP_ARCHER,
bitmap => (
(29, 29, 30, 30, 29, 0, 25, 0),
( 0, 29, 30, 30, 30, 29, 0, 25),
( 0, 29, 57, 34, 57, 34, 0, 25),
( 0, 3, 57, 57, 57, 57, 0, 25),
(44, 29, 30, 30, 30, 29, 29, 57),
(57, 37, 38, 38, 19, 37, 0, 41),
( 0, 29, 29, 29, 29, 29, 0, 25),
( 0, 37, 0, 0, 0, 37, 38, 0)
)
),
(
handle => BITMAP_CHEST,
bitmap => (
( 0, 0, 0, 0, 0, 0, 0, 0),
( 0, 38, 38, 38, 38, 38, 38, 0),
(38, 2, 2, 2, 2, 38, 2, 38),
(38, 38, 38, 38, 38, 38, 38, 38),
(38, 1, 46, 1, 22, 38, 22, 38),
(38, 21, 21, 1, 22, 37, 22, 38),
(37, 37, 37, 37, 37, 37, 37, 37),
( 0, 0, 0, 0, 0, 0, 0, 0)
)
),
(
handle => BITMAP_GHOST,
bitmap => (
( 0, 0, 0, 53, 53, 53, 20, 0),
( 0, 0, 53, 53, 24, 53, 24, 0),
( 0, 0, 53, 53, 53, 53, 53, 0),
( 0, 53, 53, 53, 53, 34, 53, 53),
( 0, 0, 53, 53, 53, 34, 20, 0),
(53, 0, 53, 53, 53, 53, 20, 0),
( 0, 53, 53, 53, 53, 53, 20, 0),
( 0, 0, 53, 53, 53, 20, 0, 0)
)
),
(
handle => BITMAP_SCORPION,
bitmap => (
( 0, 18, 18, 18, 0, 0, 0, 0),
(18, 0, 0, 17, 17, 0, 0, 0),
(18, 0, 0, 0, 17, 0, 0, 0),
(18, 0, 0, 0, 0, 0, 0, 0),
(18, 18, 0, 0, 0, 0, 0, 0),
(17, 18, 18, 18, 18, 24, 18, 24),
( 0, 17, 18, 18, 18, 18, 18, 18),
(17, 0, 17, 0, 17, 0, 17, 0)
)
),
(
handle => BITMAP_ORYX_11,
bitmap => (
( 0, 20, 0, 0, 20, 0, 0, 0),
(20, 20, 0, 20, 0, 0, 34, 34),
(20, 20, 0, 20, 0, 34, 17, 17),
(20, 20, 0, 0, 20, 34, 17, 17),
(20, 20, 0, 0, 0, 33, 24, 34),
(20, 20, 0, 0, 34, 33, 33, 34),
(34, 34, 0, 34, 33, 34, 33, 34),
(17, 34, 17, 34, 17, 33, 34, 33)
)
),
(
handle => BITMAP_ORYX_12,
bitmap => (
( 0, 0, 0, 20, 0, 0, 0, 0),
(34, 34, 0, 0, 20, 0, 0, 0),
(33, 33, 34, 0, 20, 0, 0, 0),
(34, 33, 34, 20, 0, 0, 0, 0),
(34, 24, 33, 0, 0, 0, 0, 0),
(34, 33, 33, 34, 0, 0, 0, 0),
(34, 33, 34, 34, 34, 34, 34, 34),
(33, 34, 17, 34, 18, 18, 18, 34)
)
),
(
handle => BITMAP_ORYX_21,
bitmap => (
(17, 34, 17, 34, 33, 17, 17, 34),
(34, 34, 0, 0, 34, 34, 34, 33),
(34, 0, 0, 0, 0, 34, 33, 33),
( 0, 0, 0, 0, 34, 17, 34, 34),
( 0, 0, 0, 34, 17, 34, 34, 17),
( 0, 0, 0, 34, 34, 34, 0, 33),
( 0, 0, 0, 34, 34, 34, 0, 0),
( 0, 0, 34, 34, 34, 34, 0, 0)
)
),
(
handle => BITMAP_ORYX_22,
bitmap => (
(34, 17, 17, 34, 18, 18, 20, 34),
(33, 34, 34, 34, 18, 20, 20, 34),
(33, 33, 34, 34, 18, 18, 20, 34),
(34, 34, 17, 34, 18, 18, 20, 34),
(17, 34, 34, 17, 34, 18, 18, 34),
(33, 0, 34, 34, 34, 34, 34, 34),
( 0, 0, 34, 34, 34, 0, 0, 0),
( 0, 0, 34, 34, 34, 34, 0, 0)
)
),
(
handle => BITMAP_BAT,
bitmap => (
( 0, 0, 0, 17, 0, 17, 0, 0),
( 0, 17, 0, 17, 17, 17, 0, 17),
(17, 17, 0, 46, 17, 46, 0, 17),
(17, 17, 17, 17, 17, 17, 17, 17),
(17, 17, 17, 17, 17, 17, 17, 17),
(17, 17, 0, 17, 17, 0, 17, 17),
(17, 0, 0, 17, 0, 0, 0, 17),
( 0, 0, 0, 0, 0, 0, 0, 0)
)
),
( handle => BITMAP_REAPER,
bitmap => (
(34, 34, 34, 19, 19, 19, 19, 19),
( 0, 34, 19, 33, 33, 33, 0, 38),
( 0, 34, 34, 23, 53, 23, 0, 38),
( 0, 34, 34, 53, 53, 53, 0, 38),
(34, 34, 34, 34, 34, 34, 34, 53),
(53, 34, 34, 34, 34, 34, 0, 38),
( 0, 34, 34, 34, 34, 34, 0, 38),
(34, 34, 34, 34, 34, 34, 34, 38)
)),
( handle => BITMAP_FOREST_TILE,
bitmap => (
(11, 11, 11, 11, 12, 1, 11, 11),
(12, 1, 11, 11, 11, 12, 11, 11),
(11, 12, 11, 11, 11, 11, 11, 11),
(11, 11, 11, 12, 11, 11, 11, 11),
(11, 11, 11, 11, 12, 11, 11, 11),
(11, 11, 11, 11, 11, 11, 1, 11),
(11, 12, 11, 11, 11, 11, 12, 11),
(11, 11, 12, 11, 11, 11, 11, 11)
)),
(
handle => BITMAP_GAME_OVER_TILE,
bitmap => (
(22, 46, 22, 46, 22, 46, 22, 22),
(22, 22, 46, 26, 26, 26, 46, 22),
(22, 46, 26, 53, 53, 53, 25, 22),
(22, 26, 53, 53, 53, 53, 53, 42),
(22, 42, 53, 53, 34, 53, 34, 23),
(22, 22, 23, 36, 53, 34, 53, 23),
(22, 22, 22, 23, 36, 36, 36, 23),
(22, 22, 22, 22, 24, 23, 23, 22)
)
),
(
handle => BITMAP_GAME_WON_TILE,
bitmap => (
( 7, 7, 38, 38, 38, 38, 38, 7),
( 7, 7, 38, 46, 46, 1, 38, 17),
( 7, 7, 46, 26, 46, 46, 38, 17),
( 7, 46, 26, 46, 26, 46, 38, 7),
(38, 38, 38, 38, 38, 38, 38, 7),
(38, 1, 46, 2, 38, 2, 38, 7),
(38, 2, 1, 2, 38, 2, 38, 7),
(38, 38, 38, 38, 38, 38, 7, 7)
)
)
);
end;
| unlicense |
Nibble-Knowledge/peripheral-ethernet | vhdl-serial/rs232.vhd | 1 | 6525 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:09:52 02/06/2016
-- Design Name:
-- Module Name: rs232 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rs232 is
Port ( clk32mhz : in STD_LOGIC;
reset : in STD_LOGIC;
--RS232 connections
td : in STD_LOGIC;
--dtr : in STD_LOGIC;
--rts : in STD_LOGIC;
rd : out STD_LOGIC;
--cts : out STD_LOGIC;
--CPU connections
clk_cpu : in STD_LOGIC;
cpu_read : in STD_LOGIC;
cpu_write : in STD_LOGIC;
cpu_cs : in STD_LOGIC;
cpu_parity : in STD_LOGIC;
cpu_data : inout STD_LOGIC_VECTOR(3 downto 0);
cpu_ready : out STD_LOGIC;
--RAM connections
ram_data : inout STD_LOGIC_VECTOR(7 downto 0);
ram_addr : out STD_LOGIC_VECTOR(14 downto 0);
ram_r1w0 : out STD_LOGIC;
debug : out std_logic
);
end rs232;
architecture Behavioral of rs232 is
component clock_divider is
Generic ( TICK : integer := 3333 );
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_uart : out STD_LOGIC);
end component;
signal clk_uart : std_logic;
signal clock_cpu : std_logic;
component pc2periph is
Port ( clk_uart : in STD_LOGIC; --Clock set to the baud rate
reset : in STD_LOGIC;
rs232_td : in STD_LOGIC; --Data transmitted from PC
--rs232_rts : in STD_LOGIC; --Request from PC to transmit data
mem_inuse : in STD_LOGIC;
rs232_cts : out STD_LOGIC; --Response to PC that the peripheral is ready to accept data
ram_addr : out STD_LOGIC_VECTOR (14 downto 0);
ram_data : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal pcin_cts : std_logic; --we need this because when CTS is high, RAM is in use by this component
signal pcin_addr : std_logic_vector(14 downto 0);
signal pcin_data : std_logic_vector(7 downto 0);
component periph2pc is
Port ( clk_uart : in STD_LOGIC;
reset : in STD_LOGIC;
--rs232_dtr : in STD_LOGIC;
buff : in STD_LOGIC_VECTOR (7 downto 0);
buffok : in STD_LOGIC;
clrbuff : out STD_LOGIC;
rs232_rd : out STD_LOGIC);
end component;
signal pcout_buff : std_logic_vector(7 downto 0);
signal pcout_clrbuff : std_logic;
component periph2cpu is
Port ( clk_cpu : in STD_LOGIC;
reset : in STD_LOGIC;
in_meminuse : in STD_LOGIC;
cpu_read : in STD_LOGIC;
curmem : in STD_LOGIC_VECTOR (14 downto 0);
ram_data : in STD_LOGIC_VECTOR (7 downto 0);
cpu_ready : out STD_LOGIC;
out_meminuse : out STD_LOGIC;
cpu_data : out STD_LOGIC_VECTOR (3 downto 0);
ram_addr : out STD_LOGIC_VECTOR (14 downto 0);
debug : out std_logic);
end component;
signal cpuout_read : std_logic;
signal cpuout_data : std_logic_vector(7 downto 0);
signal cpuout_ready : std_logic := '0';
signal cpuout_meminuse : std_logic;
signal cpuout_cpudata : std_logic_vector(3 downto 0);
signal cpuout_addr : std_logic_vector(14 downto 0);
component cpu2periph is
Port ( clk_cpu : in STD_LOGIC;
reset : in STD_LOGIC;
cpu_write : in STD_LOGIC;
cpu_data : in STD_LOGIC_VECTOR (3 downto 0);
--established : in STD_LOGIC;
buffok : in STD_LOGIC;
setbuff : out STD_LOGIC;
pcbuff : out STD_LOGIC_VECTOR (7 downto 0);
cpu_ready : out STD_LOGIC;
debug : out std_logic);
end component;
signal cpuin_write : std_logic;
signal cpuin_data : std_logic_vector(3 downto 0);
signal cpuin_setbuff : std_logic;
signal cpuin_ready : std_logic;
--Simple latch for BUFFOK
signal buffok : std_logic;
begin
CLKDIV: clock_divider
generic map (
TICK => 3333
)
port map (
clk => clk32mhz,
reset => reset,
clk_uart => clk_uart
);
CPUCLK: clock_divider
generic map (
TICK => 32
)
port map (
clk => clk32mhz,
reset => reset,
clk_uart => clock_cpu
);
PCIN: component pc2periph
port map (
clk_uart => clk_uart,
reset => reset,
rs232_td => td,
--rs232_rts => rts,
mem_inuse => cpuout_meminuse,
rs232_cts => pcin_cts,
ram_addr => pcin_addr,
ram_data => pcin_data
);
PCOUT: component periph2pc
port map (
clk_uart => clk_uart,
reset => reset,
--rs232_dtr => dtr,
buff => pcout_buff,
buffok => buffok,
clrbuff => pcout_clrbuff,
rs232_rd => rd
);
CPUOUT: component periph2cpu
port map (
clk_cpu => clock_cpu,
reset => reset,
in_meminuse => pcin_cts,
cpu_read => cpuout_read,
curmem => pcin_addr,
ram_data => cpuout_data,
cpu_ready => cpuout_ready,
out_meminuse => cpuout_meminuse,
cpu_data => cpuout_cpudata,
ram_addr => cpuout_addr,
debug => open
);
CPUIN: component cpu2periph
port map (
clk_cpu => clock_cpu,
reset => reset,
cpu_write => cpuin_write,
cpu_data => cpuin_data,
--established => dtr,
buffok => buffok,
setbuff => cpuin_setbuff,
pcbuff => pcout_buff,
cpu_ready => cpuin_ready,
debug => debug
);
--Map RS232 signals
--cts <= pcin_cts;
--Map CPU signals
cpuout_read <= cpu_read and not cpu_cs;
cpuin_write <= cpu_write and not cpu_cs;
cpu_ready <= cpuout_ready when (cpuout_read = '1') else cpuin_ready when (cpuin_write = '1') else 'Z';
cpu_data <= cpuout_cpudata when (cpuout_read = '1') else (others => 'Z');
cpuin_data <= cpu_data when (cpuin_write = '1');
--Map RAM signals
ram_data <= pcin_data when (pcin_cts = '1') else (others => 'Z') when (cpuout_meminuse = '1' or reset = '1');
cpuout_data <= ram_data when (cpuout_meminuse = '1');
ram_addr <= pcin_addr when (pcin_cts = '1') else cpuout_addr when (cpuout_meminuse = '1') else (others => '0') when (reset = '1');
ram_r1w0 <= not pcin_cts;
--BUFFOK latch
buffok <= '0' when (pcout_clrbuff = '1' or reset = '1') else '1' when (cpuin_setbuff = '1');
end Behavioral; | unlicense |
Nibble-Knowledge/peripheral-ide | IDE/IDE_READ/mux_out.vhd | 1 | 1516 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:25:44 11/12/2015
-- Design Name:
-- Module Name: mux_out - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux_out is
port( mux_in: in std_logic_vector(15 downto 0); -- data read from hard drive
mux_enable: in std_logic_vector (2 downto 0);
mux_out: out std_logic_vector(3 downto 0) -- data to cpu
);
end mux_out;
architecture Behavioral of mux_out is
begin
process(mux_in, mux_enable)
begin
case mux_enable is
when "001" => mux_out <= mux_in (15 downto 12);
when "010" => mux_out <= mux_in (11 downto 8); --when Re_ld "0010";
when "011" => mux_out <= mux_in (7 downto 4); --when Re_ld "0011";
when "100" => mux_out <= mux_in (3 downto 0); --when Re_ld "0100";
when others => mux_out <= "ZZZZ";
end case;
end process;
end Behavioral;
| unlicense |
Nibble-Knowledge/peripheral-ide | IDE/IDE3_write/sixteen_bit_reg.vhd | 1 | 1353 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:19:23 11/11/2015
-- Design Name:
-- Module Name: sixteen_bit_reg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sixteen_bit_reg is
port( s_clk: in std_logic;
s_rst: in std_logic;
s_ld: in std_logic;
s_reg_in: in std_logic_vector(15 downto 0);
s_reg_out: out std_logic_vector(15 downto 0)
);
end sixteen_bit_reg;
architecture Behavioral of sixteen_bit_reg is
begin
process(s_clk, s_rst, s_ld)
begin
if s_rst = '1' then
s_reg_out<=(others=>'0');
elsif (s_clk'event and s_clk='1') and (s_ld='1') then
s_reg_out <= s_reg_in;
end if;
end process;
end Behavioral;
| unlicense |
eliben/luz-cpu | experimental/luz_uc/luz_uc_testbench/peripherals/memory/memory_onchip_wb_tb.vhd | 2 | 2798 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory_onchip_wb_tb is
end;
architecture memory_onchip_wb_tb_arc of memory_onchip_wb_tb is
constant ADDR_WIDTH: natural := 8;
signal clk: std_logic := '0';
signal reset_n: std_logic;
signal ack_o: std_logic;
signal cyc_i: std_logic;
signal stb_i: std_logic;
signal we_i: std_logic;
signal sel_i: std_logic_vector(3 downto 0);
signal adr_i: std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal data_i: std_logic_vector(31 downto 0);
signal data_o: std_logic_vector(31 downto 0);
signal access_error: std_logic;
constant WR: std_logic := '1';
constant RD: std_logic := '0';
begin
clk <= not clk after 10 ns;
reset_n <= '0', '1' after 105 ns;
process
procedure mem_access( adr: std_logic_vector(ADDR_WIDTH - 1 downto 0);
sel: std_logic_vector(3 downto 0);
we: std_logic;
data: std_logic_vector(31 downto 0) := x"00000000") is
begin
stb_i <= '1';
cyc_i <= '1';
we_i <= we;
sel_i <= sel;
adr_i <= adr;
data_i <= data;
wait until rising_edge(clk);
wait for 1 ns;
stb_i <= '0';
cyc_i <= '0';
wait for 1 ns;
end procedure mem_access;
begin
cyc_i <= '0';
stb_i <= '0';
we_i <= '0';
sel_i <= (others => '0');
adr_i <= (others => '0');
data_i <= (others => '0');
wait for 203 ns;
mem_access(x"03", x"F", RD, x"ABCDFAEC");
--~ mem_access(x"04", x"8", WR, x"12345678");
--~ mem_access(x"03", x"3", RD);
mem_access(x"04", x"f", RD);
--~ mem_access(x"03", x"6", RD);
--~ mem_access(x"03", x"8", RD);
wait;
end process;
uut: entity work.sim_memory_onchip_wb(sim_memory_onchip_wb_arc)
generic map
(
ADDR_WIDTH => ADDR_WIDTH,
MEMORY_IMAGE_FILE => "bin2hex.hex",
PRINT_INITIALIZATION => false
)
port map
(
clk => clk,
reset_n => reset_n,
ack_o => ack_o,
cyc_i => cyc_i,
stb_i => stb_i,
we_i => we_i,
sel_i => sel_i,
adr_i => adr_i,
data_i => data_i,
data_o => data_o,
access_error => access_error
);
end;
| unlicense |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/control.vhd | 1 | 3476 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
entity hazard_control_block is
port (
dest_reg_en : in std_logic;
dest_reg : in std_logic_vector(3 downto 0);
src_reg1_en : std_logic;
src_reg1 : in std_logic_vector(3 downto 0);
src_reg2_en : in std_logic;
src_reg2 : in std_logic_vector(3 downto 0);
handlerPC : in std_logic_vector(7 downto 0);
nop : inout std_logic;
interrupt_happened : in std_logic;
interrupt_handled : in std_logic;
src_select : out std_logic_vector(1 downto 0);
PC : inout std_logic_vector(7 downto 0);
branch : in std_logic;
branch_addr : in std_logic_vector(7 downto 0);
operation : in std_logic_vector(4 downto 0);
clk, rst : in std_logic;
PC2handler : out std_logic_vector(7 downto 0)
);
end entity;
architecture behav of hazard_control_block is
signal prev_dest_reg_en : std_logic;
signal prev_dest_reg : std_logic_vector(3 downto 0);
signal state : std_logic_vector(1 downto 0);
signal temp_pc : std_logic_vector(7 downto 0);
begin
process(clk, rst)
begin
if (rst = '1') then
report "Control Block Reset";
PC <= X"00";
nop <= '0';
prev_dest_reg_en <= '0';
state <= "00";
elsif (rising_edge(clk)) then
if (state = "00") then
if (branch = '1') then
PC <= branch_addr;
elsif (nop = '1') then
PC <= PC - 1;
else
PC <= PC + 1;
end if;
else
PC <= X"00";
temp_pc <= handlerPC;
end if;
elsif falling_edge(clk) then
report "prev_dest_reg_en: " & integer'image(conv_integer(prev_dest_reg_en)) & "prev_dest_reg: " & integer'image(conv_integer(prev_dest_reg));
report "src_reg1_en: " & integer'image(conv_integer(src_reg1_en)) & "src_reg1: " & integer'image(conv_integer(src_reg1));
report "src_reg2_en: " & integer'image(conv_integer(src_reg2_en)) & "src_reg2: " & integer'image(conv_integer(src_reg2));
if (state = "00") then
nop <= '0';
src_select <= "00";
if ((src_reg1_en = '1') and (prev_dest_reg_en = '1')) then
report "Source reg 1 enable & Prev dest reg en";
if (src_reg1 = prev_dest_reg) then
report "Src reg 1, prev dest reg 1";
src_select(0) <= '1';
end if;
end if;
if ((src_reg2_en = '1') and (prev_dest_reg_en = '1')) then
report "Source reg 2 enable & prev dest reg enable";
if (src_reg2 = prev_dest_reg) then
report "Source reg 2, prev dest reg 2";
src_select(1) <= '1';
end if;
end if;
if (dest_reg_en = '1') then
report "dest reg enable1";
prev_dest_reg_en <= '1';
prev_dest_reg <= dest_reg;
else
prev_dest_reg_en <= '0';
end if;
if (branch = '1') then
nop <= '1';
end if;
if (interrupt_happened = '1' and interrupt_handled = '0') then
state <= "01";
nop <= '1';
end if;
PC2handler <= PC;
else
PC <= X"00";
nop <= '0';
if (interrupt_happened = '0' and interrupt_handled = '1') then
PC <= temp_pc;
state <= "00";
end if;
end if;
end if;
end process;
end architecture;
| unlicense |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/scratch_pad.vhd | 1 | 1283 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
entity scratch_pad is
port (
data_in1, data_in2 : in std_logic_vector(7 downto 0);
raddr_write1, raddr_write2 : in std_logic_vector(3 downto 0);
data_out : out std_logic_vector(7 downto 0);
raddr_read : in std_logic_vector(3 downto 0);
re, we, clk : in std_logic
);
end entity;
architecture behav of scratch_pad is
type mem_array is array(15 downto 0) of std_logic_vector(7 downto 0);
signal mem_data : mem_array;
begin
process (clk)
begin
if (rising_edge(clk) and (we = '1')) then
mem_data(conv_integer(raddr_write1)) <= data_in1;
report "Scratch Pad write addr: " & integer'image(conv_integer(raddr_write1)) & " data: " & integer'image(conv_integer(data_in1));
mem_data(conv_integer(raddr_write2)) <= data_in2;
report "Scratch Pad write addr: " & integer'image(conv_integer(raddr_write2)) & " data: " & integer'image(conv_integer(data_in2));
elsif (falling_edge(clk) and (re = '1')) then
data_out <= mem_data(conv_integer(raddr_read));
report "Scratch Pad read addr: " & integer'image(conv_integer(raddr_read)) & " data: " & integer'image(conv_integer(mem_data(conv_integer(raddr_read))));
end if;
end process;
end architecture;
| unlicense |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/select.vhd | 1 | 3960 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity selectresult is
port(
mem_result : in std_logic_vector(7 downto 0);
alu_result : in std_logic_vector(7 downto 0);
select_op : in std_logic_vector(1 downto 0);
result_out : out std_logic_vector(7 downto 0));
end selectresult;
architecture mixed of selectresult is
begin
process(select_op, mem_result, alu_result)
begin
case select_op is
when "10" =>
result_out <= mem_result;
when others =>
result_out <= alu_result;
end case;
end process;
end mixed;
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity datamux is
port(
alu_memdata:in std_logic_vector(7 downto 0);
intrhandler_data:in std_logic_vector(7 downto 0);
sel: in std_logic;
data_out: out std_logic_vector(7 downto 0));
end datamux;
architecture mixed of datamux is
begin
process(alu_memdata, sel, intrhandler_data)
begin
case sel is
when '1' =>
data_out <= intrhandler_data;
when others =>
data_out <= alu_memdata;
end case;
end process;
end mixed;
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity writemux is
port(
dec_wr:in std_logic_vector(3 downto 0);
intr_wr:in std_logic_vector(3 downto 0);
sel: in std_logic;
wr_out: out std_logic_vector(3 downto 0));
end writemux;
architecture mixed of writemux is
begin
process(dec_wr, intr_wr, sel)
begin
case sel is
when '1' =>
wr_out <= intr_wr;
when others =>
wr_out <= dec_wr;
end case;
end process;
end mixed;
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
entity readmux is
port(
dec_raddr1:in std_logic_vector(3 downto 0);
dec_raddr2:in std_logic_vector(3 downto 0);
intr_raddr1:in std_logic_vector(3 downto 0);
intr_raddr2:in std_logic_vector(3 downto 0);
sel: in std_logic;
out_raddr1: out std_logic_vector(3 downto 0);
out_raddr2: out std_logic_vector(3 downto 0));
end readmux;
architecture mixed of readmux is
begin
process(dec_raddr1, dec_raddr2, intr_raddr1, intr_raddr2, sel)
begin
case sel is
when '1' =>
out_raddr1 <= intr_raddr1;
out_raddr2 <= intr_raddr2;
when others =>
out_raddr1 <= dec_raddr1;
out_raddr2 <= dec_raddr2;
end case;
end process;
end mixed;
-------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity enable_mux is
port (
processor_en, sel : in std_logic;
en_out : out std_logic
);
end entity;
architecture behav of enable_mux is
begin
process(processor_en, sel)
begin
case sel is
when '1' =>
en_out <= '1';
when others =>
en_out <= processor_en;
end case;
end process;
end architecture;
| unlicense |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/ALU_mem.vhd | 1 | 3010 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ALU_ram is
port(
clk,rst : in std_logic;
reg_addr : in std_logic_vector(3 downto 0);
mem_addr : in std_logic_vector(7 downto 0);
result : in std_logic_vector(7 downto 0);
operand : in std_logic_vector(1 downto 0);
reg_addr_out : out std_logic_vector(3 downto 0);
reg_data_out : out std_logic_vector(7 downto 0);
reg_write_enable : out std_logic;
mem_re, mem_we : out std_logic;
mem_read_out : out std_logic_vector(7 downto 0)
);
end ALU_ram;
architecture mixed of ALU_ram is
component ram is
generic(
data_width : natural := 8;
addr_width : natural := 8);
port(
clk,rst : in std_logic;
data : in std_logic_vector(data_width-1 downto 0);
write_addr : in std_logic_vector(addr_width-1 downto 0);
read_addr : in std_logic_vector(addr_width-1 downto 0);
w_enable : inout std_logic;
r_enable : inout std_logic;
data_out : out std_logic_vector(data_width-1 downto 0));
end component;
signal mem_write_addr : std_logic_vector(7 downto 0);
signal mem_read_addr : std_logic_vector(7 downto 0);
signal mem_result : std_logic_vector(7 downto 0);
signal mem_write_enable : std_logic;
signal mem_read_enable : std_logic;
signal mem_data_out : std_logic_vector(7 downto 0);
begin
c0: ram port map(clk, rst, mem_result, mem_write_addr, mem_read_addr, mem_write_enable, mem_read_enable, mem_data_out);
--For Debug
mem_re <= mem_read_enable;
mem_we <= mem_write_enable;
mem_read_out <= mem_data_out;
process(reg_addr, mem_addr, result, operand)
begin
case operand is
when "00" => --no op
mem_write_addr <= "00000000";
mem_read_addr <= "00000000";
mem_result <= "00000000";
mem_write_enable <= '0';
mem_read_enable <= '0';
mem_data_out <= "00000000";
reg_addr_out <= "0000";
reg_data_out <= "00000000";
reg_write_enable <= '0';
when "01" => --R <= ALU
mem_write_enable <= '0';
mem_read_enable <= '0';
reg_addr_out <= reg_addr;
reg_data_out <= result;
reg_write_enable <= '1';
when "10" => --R <= Mem
mem_read_addr <= mem_addr;
mem_read_enable <= '1';
mem_write_enable <= '0';
reg_addr_out <= reg_addr;
reg_write_enable <= '1';
reg_data_out <= mem_data_out;
when "11" => --Mem <= R
mem_write_addr <= mem_addr;
mem_write_enable <= '1';
mem_read_enable <= '0';
reg_write_enable <= '0';
mem_result <= result;
when others =>
mem_write_addr <= "00000000";
mem_read_addr <= "00000000";
mem_result <= "00000000";
mem_write_enable <= '0';
mem_read_enable <= '0';
mem_data_out <= "00000000";
reg_addr_out <= "0000";
reg_data_out <= "00000000";
reg_write_enable <= '0';
end case;
end process;
end mixed;
| unlicense |
azeemshaikh38/PipelinedProcessorWithInterrupts | Processor/pipe_top.vhd | 1 | 18286 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity pipe_top is
port(
clk, rst : in std_logic;
interrupt_reg_data : in std_logic_vector(7 downto 0);
interrupt_reg_we : std_logic
);
end pipe_top;
architecture top of pipe_top is
component fetch_mem is
port(
clk, rst : in std_logic;
read_addr : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(15 downto 0));
end component;
component fetch2decode_reg is
port(
clk, rst : in std_logic;
noop : in std_logic;
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0));
end component;
component decode is
port(
din: in std_logic_vector(15 downto 0);
reg_rd_en : out std_logic;
Raddr1:out std_logic_vector(3 downto 0);
Raddr2:out std_logic_vector(3 downto 0);
memaddr: out std_logic_vector(7 downto 0);
operation:out std_logic_vector(4 downto 0);
dest_reg_en: out std_logic;
dest_reg: out std_logic_vector(3 downto 0);
src_reg1_en: out std_logic;
src_reg1: out std_logic_vector(3 downto 0);
src_reg2_en: out std_logic;
src_reg2: out std_logic_vector(3 downto 0);
return_from_interrupt : out std_logic
);
end component;
component decode2alu_reg is
port(
clk, rst: in std_logic;
noop : in std_logic;
A_in : in std_logic_vector(7 downto 0);
B_in : in std_logic_vector(7 downto 0);
operation_in : in std_logic_vector(4 downto 0);
Raddr1_in : in std_logic_vector(3 downto 0);
Raddr2_in : in std_logic_vector(3 downto 0);
Memaddr_in : in std_logic_vector(7 downto 0);
src_select: in std_logic_vector(1 downto 0);
ALU_result: in std_logic_vector(7 downto 0);
A_out : out std_logic_vector(7 downto 0);
B_out : out std_logic_vector(7 downto 0);
operation_out : out std_logic_vector(4 downto 0);
Raddr1_out : out std_logic_vector(3 downto 0);
Raddr2_out : out std_logic_vector(3 downto 0);
Memaddr_out : out std_logic_vector(7 downto 0));
end component;
component ALU is
port (
A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
operation : in std_logic_vector(4 downto 0);
Raddr1 : in std_logic_vector(3 downto 0);
Raddr2 : in std_logic_vector(3 downto 0);
Memaddr_in : in std_logic_vector(7 downto 0);
MemAddr_out : out std_logic_vector(7 downto 0);
Raddr : out std_logic_vector(3 downto 0);
op : out std_logic_vector(1 downto 0);
result : out std_logic_vector(7 downto 0);
branch : out std_logic;
branch_offset : out std_logic_vector(7 downto 0);
mem_rd_en : out std_logic;
reg_wr_en : out std_logic;
mem_wr_en : out std_logic);
end component;
component ram is
port(
data : in std_logic_vector(7 downto 0);
write_addr : in std_logic_vector(7 downto 0);
read_addr : in std_logic_vector(7 downto 0);
w_enable : in std_logic;
r_enable : in std_logic;
clk, rst : in std_logic;
data_out : out std_logic_vector(7 downto 0));
end component;
component alu2register_reg is
port(
clk, rst : in std_logic;
raddr_in : in std_logic_vector(3 downto 0);
op_in : in std_logic_vector(1 downto 0);
result_in : in std_logic_vector(7 downto 0);
reg_wr_en_in : in std_logic;
raddr_out : out std_logic_vector(3 downto 0);
op_out : out std_logic_vector(1 downto 0);
result_out : out std_logic_vector(7 downto 0);
reg_wr_en_out : out std_logic
);
end component;
component register_bank is
port(
clk,rst : in std_logic;
data : in std_logic_vector(7 downto 0);
write_addr : in std_logic_vector(3 downto 0);
read_addr1 : in std_logic_vector(3 downto 0);
read_addr2 : in std_logic_vector(3 downto 0);
w_enable : in std_logic;
r_enable : in std_logic;
data_out1 : out std_logic_vector(7 downto 0);
data_out2 : out std_logic_vector(7 downto 0));
end component;
component hazard_control_block is
port (
dest_reg_en : in std_logic;
dest_reg : in std_logic_vector(3 downto 0);
src_reg1_en : std_logic;
src_reg1 : in std_logic_vector(3 downto 0);
src_reg2_en : in std_logic;
src_reg2 : in std_logic_vector(3 downto 0);
handlerPC : in std_logic_vector(7 downto 0);
nop : inout std_logic;
interrupt_happened : in std_logic;
interrupt_handled : in std_logic;
src_select : out std_logic_vector(1 downto 0);
PC : inout std_logic_vector(7 downto 0);
branch : in std_logic;
branch_addr : in std_logic_vector(7 downto 0);
operation : in std_logic_vector(4 downto 0);
clk, rst : in std_logic;
PC2handler : out std_logic_vector(7 downto 0)
);
end component;
component selectresult is
port(
mem_result : in std_logic_vector(7 downto 0);
alu_result : in std_logic_vector(7 downto 0);
select_op : in std_logic_vector(1 downto 0);
result_out : out std_logic_vector(7 downto 0));
end component;
component interrupt_handler is
port (
data_in1, data_in2 : in std_logic_vector(7 downto 0);
raddr1, raddr2 : inout std_logic_vector(3 downto 0);
raddr_write : out std_logic_vector(3 downto 0);
reg_re, reg_we : out std_logic;
data_out : out std_logic_vector(7 downto 0);
PC_in : in std_logic_vector(7 downto 0);
PC_out : out std_logic_vector(7 downto 0);
interrupt_reg_data : in std_logic_vector(7 downto 0);
interrupt_reg_we : in std_logic;
interrupt_or_return_happened, interrupt_or_return_handled : out std_logic;
return_opcode : in std_logic;
clk, rst : in std_logic
);
end component;
component datamux is
port(
alu_memdata:in std_logic_vector(7 downto 0);
intrhandler_data:in std_logic_vector(7 downto 0);
sel: in std_logic;
data_out: out std_logic_vector(7 downto 0));
end component;
component writemux is
port(
dec_wr:in std_logic_vector(3 downto 0);
intr_wr:in std_logic_vector(3 downto 0);
sel: in std_logic;
wr_out: out std_logic_vector(3 downto 0));
end component;
component readmux is
port(
dec_raddr1:in std_logic_vector(3 downto 0);
dec_raddr2:in std_logic_vector(3 downto 0);
intr_raddr1:in std_logic_vector(3 downto 0);
intr_raddr2:in std_logic_vector(3 downto 0);
sel: in std_logic;
out_raddr1: out std_logic_vector(3 downto 0);
out_raddr2: out std_logic_vector(3 downto 0));
end component;
component enable_mux is
port (
processor_en, sel : in std_logic;
en_out : out std_logic
);
end component;
signal fetch2decodereg_instr : std_logic_vector(15 downto 0);
signal decodereg2decode_instr : std_logic_vector(15 downto 0);
signal decode2regbank_re : std_logic;
signal decode2regbank_raddr1 : std_logic_vector(3 downto 0);
signal decode2regbank_raddr2 : std_logic_vector(3 downto 0);
signal decode2alureg_memaddr : std_logic_vector(7 downto 0);
signal decode2alureg_operation : std_logic_vector(4 downto 0);
signal decode2control_destregen : std_logic;
signal decode2control_destreg : std_logic_vector(3 downto 0);
signal decode2control_srcreg1en : std_logic;
signal decode2control_srcreg1 : std_logic_vector(3 downto 0);
signal decode2control_srcreg2en: std_logic;
signal decode2control_srcreg2: std_logic_vector(3 downto 0);
signal regbank2alureg_ain : std_logic_vector(7 downto 0);
signal regbank2alureg_bin : std_logic_vector(7 downto 0);
signal alureg2alu_aout : std_logic_vector(7 downto 0);
signal alureg2alu_bout : std_logic_vector(7 downto 0);
signal alureg2alu_operationout : std_logic_vector(4 downto 0);
signal alureg2alu_raddr1out : std_logic_vector(3 downto 0);
signal alureg2alu_raddr2out : std_logic_vector(3 downto 0);
signal alureg2alu_memaddrout : std_logic_vector(7 downto 0);
signal alu2mem_memaddrout : std_logic_vector(7 downto 0);
signal alu2mem_memrden : std_logic;
signal alu2mem_memwren : std_logic;
signal alu2mem_result : std_logic_vector(7 downto 0);
signal alu2reg_result : std_logic_vector(7 downto 0);
signal alu2reg_op : std_logic_vector(1 downto 0);
signal alu2reg_regwren : std_logic;
signal alu2reg_raddr : std_logic_vector(3 downto 0);
signal alu2control_branch : std_logic;
signal alu2control_branchoffset : std_logic_vector(7 downto 0);
signal alu2control_operation : std_logic_vector(4 downto 0);
signal control2fetch_pc : std_logic_vector(7 downto 0);
signal control2decodealu_noop : std_logic;
--signal control2alu_noop : std_logic;
signal decode2alureg_raddr1 : std_logic_vector(3 downto 0);
signal decode2alureg_raddr2 : std_logic_vector(3 downto 0);
signal regreg2register_raddr : std_logic_vector(3 downto 0);
signal regreg2register_wre : std_logic;
signal regreg2register_op : std_logic_vector(1 downto 0);
signal regreg2select_aluresult : std_logic_vector(7 downto 0);
signal mem2select_result : std_logic_vector(7 downto 0);
signal select2regbank_data : std_logic_vector(7 downto 0);
signal control2decodealureg_srcselect : std_logic_vector(1 downto 0);
signal interhandler2readaddrmux_raddr1, interhandler2readaddrmux_raddr2 : std_logic_vector(3 downto 0);
signal intrhandler2readaddrmux_re, intrhandler2writeaddrmux_we : std_logic;
signal intrhandler2writedatamux_data : std_logic_vector(7 downto 0);
signal control2intrhandler_PC : std_logic_vector(7 downto 0);
signal intrhandler2control_PC : std_logic_vector(7 downto 0);
signal intrhandler2control_happened, intrhandler2control_handled : std_logic;
signal intrmux2regbank_data : std_logic_vector(7 downto 0);
signal intrmux2regbank_writeaddr : std_logic_vector(3 downto 0);
signal intrmux2regbank_raddr1, intrmux2regbank_raddr2 : std_logic_vector(3 downto 0);
signal intrmux2regbank_we, intrmux2regbank_re : std_logic;
signal intrhandler2readraddrmux_re : std_logic;
signal decode2intrhandler_return : std_logic;
signal intrhandler2regbank_writeaddr : std_logic_vector(3 downto 0);
signal fetch2intrhandler_return : std_logic;
begin
fetch2intrhandler_return <= (fetch2decodereg_instr(15) and fetch2decodereg_instr(14) and fetch2decodereg_instr(13) and fetch2decodereg_instr(12));
fetch : fetch_mem port map(
clk => clk,
rst => rst,
read_addr => control2fetch_pc,
data_out => fetch2decodereg_instr);
decodereg : fetch2decode_reg port map(
clk => clk,
rst => rst,
noop => control2decodealu_noop,
data_in => fetch2decodereg_instr,
data_out => decodereg2decode_instr);
decoder : decode port map(
din => decodereg2decode_instr,
reg_rd_en => decode2regbank_re,
Raddr1 => decode2regbank_raddr1,
Raddr2 => decode2regbank_raddr2,
memaddr => decode2alureg_memaddr,
operation => decode2alureg_operation,
dest_reg_en => decode2control_destregen,
dest_reg => decode2control_destreg,
src_reg1_en => decode2control_srcreg1en,
src_reg1 => decode2control_srcreg1,
src_reg2_en => decode2control_srcreg2en,
src_reg2 => decode2control_srcreg2,
return_from_interrupt => decode2intrhandler_return);
decode2alureg : decode2alu_reg port map(
clk => clk,
rst => rst,
noop => control2decodealu_noop,
A_in => regbank2alureg_ain,
B_in => regbank2alureg_bin,
operation_in => decode2alureg_operation,
Raddr1_in => decode2regbank_raddr1,
Raddr2_in => decode2regbank_raddr2,
Memaddr_in => decode2alureg_memaddr,
src_select => control2decodealureg_srcselect,
ALU_result => select2regbank_data,
A_out => alureg2alu_aout,
B_out => alureg2alu_bout,
operation_out => alureg2alu_operationout,
Raddr1_out => alureg2alu_raddr1out,
Raddr2_out => alureg2alu_raddr2out,
Memaddr_out => alureg2alu_memaddrout);
control : hazard_control_block port map(
dest_reg_en => decode2control_destregen,
dest_reg => decode2control_destreg,
src_reg1_en => decode2control_srcreg1en,
src_reg1 => decode2control_srcreg1,
src_reg2_en => decode2control_srcreg2en,
src_reg2 => decode2control_srcreg2,
handlerPC => intrhandler2control_PC,
nop => control2decodealu_noop,
interrupt_happened => intrhandler2control_happened,
interrupt_handled => intrhandler2control_handled,
src_select => control2decodealureg_srcselect,
PC => control2fetch_pc,
branch => alu2control_branch,
branch_addr => alu2control_branchoffset,
operation => alu2control_operation,
clk => clk,
PC2handler => control2intrhandler_PC,
rst => rst);
alupart : ALU port map(
A => alureg2alu_aout,
B => alureg2alu_bout,
operation => alureg2alu_operationout,
Raddr1 => alureg2alu_raddr1out,
Raddr2 => alureg2alu_raddr2out,
Memaddr_in => alureg2alu_memaddrout,
MemAddr_out => alu2mem_memaddrout,
Raddr => alu2reg_raddr,
op => alu2reg_op,
result => alu2reg_result,
branch => alu2control_branch,
branch_offset => alu2control_branchoffset,
mem_rd_en => alu2mem_memrden,
reg_wr_en => alu2reg_regwren,
mem_wr_en => alu2mem_memwren);
aluregister : alu2register_reg port map(
clk => clk,
rst => rst,
raddr_in => alu2reg_raddr,
op_in => alu2reg_op,
result_in => alu2reg_result,
reg_wr_en_in => alu2reg_regwren,
raddr_out => regreg2register_raddr,
op_out => regreg2register_op,
result_out => regreg2select_aluresult,
reg_wr_en_out => regreg2register_wre);
ram_init : ram port map(
data => alu2reg_result,
write_addr => alu2mem_memaddrout,
read_addr => alu2mem_memaddrout,
w_enable => alu2mem_memwren,
r_enable => alu2mem_memrden,
clk => clk,
rst => rst,
data_out => mem2select_result);
registerbank : register_bank port map(
clk => clk,
rst => rst,
data => intrmux2regbank_data,
write_addr => intrmux2regbank_writeaddr,
read_addr1 => intrmux2regbank_raddr1,
read_addr2 => intrmux2regbank_raddr2,
w_enable => intrmux2regbank_we,
r_enable => intrmux2regbank_re,
data_out1 => regbank2alureg_ain,
data_out2 => regbank2alureg_bin);
interrupt_handler1 : interrupt_handler
port map (
data_in1 => regbank2alureg_ain,
data_in2 => regbank2alureg_bin,
raddr1 => interhandler2readaddrmux_raddr1,
raddr2 => interhandler2readaddrmux_raddr2,
raddr_write => intrhandler2regbank_writeaddr,
reg_re => intrhandler2readraddrmux_re,
reg_we => intrhandler2writeaddrmux_we,
data_out => intrhandler2writedatamux_data,
PC_in => control2intrhandler_PC,
PC_out => intrhandler2control_PC,
interrupt_reg_data => interrupt_reg_data,
interrupt_reg_we => interrupt_reg_we,
interrupt_or_return_happened => intrhandler2control_happened,
interrupt_or_return_handled => intrhandler2control_handled,
return_opcode => fetch2intrhandler_return,
clk => clk,
rst => rst
);
resultselect : selectresult port map(
mem_result => mem2select_result,
alu_result => regreg2select_aluresult,
select_op => regreg2register_op,
result_out => select2regbank_data);
regbank_writedata_mux : datamux
port map (
alu_memdata => select2regbank_data,
intrhandler_data => intrhandler2writedatamux_data,
sel => intrhandler2writeaddrmux_we,
data_out => intrmux2regbank_data);
regbank_writeaddr_mux : writemux
port map (
dec_wr => alu2reg_raddr,
intr_wr => intrhandler2regbank_writeaddr,
sel => intrhandler2writeaddrmux_we,
wr_out => intrmux2regbank_writeaddr);
regbank_readaddr_mux : readmux
port map(
dec_raddr1 => decode2regbank_raddr1,
dec_raddr2 => decode2regbank_raddr2,
intr_raddr1 => interhandler2readaddrmux_raddr1,
intr_raddr2 => interhandler2readaddrmux_raddr2,
sel => intrhandler2readraddrmux_re,
out_raddr1 => intrmux2regbank_raddr1,
out_raddr2 => intrmux2regbank_raddr2);
read_en_mux : enable_mux
port map (
processor_en => decode2regbank_re,
sel => intrhandler2readraddrmux_re,
en_out => intrmux2regbank_re
);
write_en_mux : enable_mux
port map (
processor_en => alu2reg_regwren,
sel => intrhandler2writeaddrmux_we,
en_out => intrmux2regbank_we
);
end top;
| unlicense |
EJDomi/pixel-dtb-firmware-readout-chain-master | dtb/ram_dq_INST_ma.vhd | 2 | 7075 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ram_dq_INST_ma.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 12.1 Build 243 01/31/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ram_dq_INST_ma IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ram_dq_INST_ma;
ARCHITECTURE SYN OF ram_dq_inst_ma IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_ma",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 8,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "N_ma"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=N_ma"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ma.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ma.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ma.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ma.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_dq_INST_ma_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| unlicense |
TWW12/lzw | final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_3/bram_1024_3_sim_netlist.vhdl | 1 | 50604 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:18:55 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_3/bram_1024_3_sim_netlist.vhdl
-- Design : bram_1024_3
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_3_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bram_1024_3_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bram_1024_3_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 29) => B"000",
DIADI(28 downto 24) => dina(19 downto 15),
DIADI(23 downto 21) => B"000",
DIADI(20 downto 16) => dina(14 downto 10),
DIADI(15 downto 13) => B"000",
DIADI(12 downto 8) => dina(9 downto 5),
DIADI(7 downto 5) => B"000",
DIADI(4 downto 0) => dina(4 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21\,
DOADO(30) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22\,
DOADO(29) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23\,
DOADO(28 downto 24) => douta(19 downto 15),
DOADO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29\,
DOADO(22) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30\,
DOADO(21) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31\,
DOADO(20 downto 16) => douta(14 downto 10),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39\,
DOADO(12 downto 8) => douta(9 downto 5),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\,
DOADO(4 downto 0) => douta(4 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85\,
DOPADOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86\,
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_3_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bram_1024_3_blk_mem_gen_prim_width;
architecture STRUCTURE of bram_1024_3_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bram_1024_3_blk_mem_gen_prim_wrapper_init
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_3_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bram_1024_3_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bram_1024_3_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.bram_1024_3_blk_mem_gen_prim_width
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_3_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bram_1024_3_blk_mem_gen_top;
architecture STRUCTURE of bram_1024_3_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bram_1024_3_blk_mem_gen_generic_cstr
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_3_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bram_1024_3_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bram_1024_3_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bram_1024_3_blk_mem_gen_top
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_3_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 19 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 19 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "bram_1024_3.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "bram_1024_3.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bram_1024_3_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_1024_3_blk_mem_gen_v8_3_5 : entity is "yes";
end bram_1024_3_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bram_1024_3_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bram_1024_3_blk_mem_gen_v8_3_5_synth
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bram_1024_3 is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bram_1024_3 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bram_1024_3 : entity is "bram_1024_3,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bram_1024_3 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bram_1024_3 : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bram_1024_3;
architecture STRUCTURE of bram_1024_3 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.74095 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bram_1024_3.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bram_1024_3.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 1024;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bram_1024_3_blk_mem_gen_v8_3_5
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9 downto 0) => B"0000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(19 downto 0) => dina(19 downto 0),
dinb(19 downto 0) => B"00000000000000000000",
douta(19 downto 0) => douta(19 downto 0),
doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(19 downto 0) => B"00000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
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