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hoangt/PoC | src/mem/ocram/altera/ocram_tdp_altera.vhdl | 2 | 5318 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Instantiate true dual-port memory on Altera FPGAs.
--
-- Description:
-- ------------------------------------
-- Quartus synthesis does not infer this RAM type correctly.
-- Instead, altsyncram is instantiated directly.
--
-- For further documentation see module "ocram_tdp"
-- (src/mem/ocram/ocram_tdp.vhdl).
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library altera_mf;
use altera_mf.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
entity ocram_tdp_altera is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk1 : in std_logic;
clk2 : in std_logic;
ce1 : in std_logic;
ce2 : in std_logic;
we1 : in std_logic;
we2 : in std_logic;
a1 : in unsigned(A_BITS-1 downto 0);
a2 : in unsigned(A_BITS-1 downto 0);
d1 : in std_logic_vector(D_BITS-1 downto 0);
d2 : in std_logic_vector(D_BITS-1 downto 0);
q1 : out std_logic_vector(D_BITS-1 downto 0);
q2 : out std_logic_vector(D_BITS-1 downto 0)
);
end ocram_tdp_altera;
architecture rtl of ocram_tdp_altera is
component altsyncram
generic (
address_aclr_a : STRING;
address_aclr_b : STRING;
address_reg_b : STRING;
indata_aclr_a : STRING;
indata_aclr_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_aclr_a : STRING;
wrcontrol_aclr_b : STRING;
wrcontrol_wraddress_reg_b : STRING);
port (
clocken0 : IN STD_LOGIC;
clocken1 : IN STD_LOGIC;
wren_a : IN STD_LOGIC;
clock0 : IN STD_LOGIC;
wren_b : IN STD_LOGIC;
clock1 : IN STD_LOGIC;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_b-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0)
);
end component;
constant DEPTH : positive := 2**A_BITS;
constant INIT_FILE : STRING := ite((str_length(FILENAME) = 0), "UNUSED", FILENAME);
signal a1_sl : std_logic_vector(A_BITS-1 downto 0);
signal a2_sl : std_logic_vector(A_BITS-1 downto 0);
begin
a1_sl <= std_logic_vector(a1);
a2_sl <= std_logic_vector(a2);
mem : altsyncram
generic map (
address_aclr_a => "NONE",
address_aclr_b => "NONE",
address_reg_b => "CLOCK1",
indata_aclr_a => "NONE",
indata_aclr_b => "NONE",
indata_reg_b => "CLOCK1",
init_file => INIT_FILE,
intended_device_family => "Stratix",
lpm_type => "altsyncram",
numwords_a => DEPTH,
numwords_b => DEPTH,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => A_BITS,
widthad_b => A_BITS,
width_a => D_BITS,
width_b => D_BITS,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_aclr_a => "NONE",
wrcontrol_aclr_b => "NONE",
wrcontrol_wraddress_reg_b => "CLOCK1"
)
port map (
clock0 => clk1,
clock1 => clk2,
clocken0 => ce1,
clocken1 => ce2,
wren_a => we1,
wren_b => we2,
address_a => a1_sl,
address_b => a2_sl,
data_a => d1,
data_b => d2,
q_a => q1,
q_b => q2
);
end rtl;
| apache-2.0 |
IAIK/ascon_hardware | caesar_hardware_api_v_1_0_3/ASCON_ASCON/src_rtl/CipherCore.vhd | 1 | 26280 | -------------------------------------------------------------------------------
--! @file CipherCore.vhd
--! @author Hannes Gross
--! @brief Generic Ascon-128(a) implementation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.AEAD_pkg.all;
entity CipherCore is
generic (
-- Ascon related generics
RATE : integer := 64; -- Selects:
-- (64) -> Ascon128
-- (128)-> Acon128a
UNROLED_ROUNDS : integer := 1; -- Ascon128: 1, 2, 3, or 6 rounds
-- Ascon128a: 1, 2, or 4 rounds
ROUNDS_A : integer := 12; -- Number of rounds for initialization
-- and finalization
ROUNDS_B : integer := 6; -- Num permutation rounds for data for
-- (6) -> Ascon128
-- (8) -> Ascon128a
--- Interface generics:
-- Reset behavior
G_ASYNC_RSTN : boolean := false; --! Async active low reset
-- Block size (bits)
G_DBLK_SIZE : integer := 128; --! Data
G_KEY_SIZE : integer := 32; --! Key
G_TAG_SIZE : integer := 128; --! Tag
-- The number of bits required to hold block size expressed in
-- bytes = log2_ceil(G_DBLK_SIZE/8)
G_LBS_BYTES : integer := 4;
G_MAX_LEN : integer := SINGLE_PASS_MAX
);
port (
--! Global
clk : in std_logic;
rst : in std_logic;
--! PreProcessor (data)
key : in std_logic_vector(G_KEY_SIZE -1 downto 0);
bdi : in std_logic_vector(G_DBLK_SIZE -1 downto 0);
--! PreProcessor (controls)
key_ready : out std_logic;
key_valid : in std_logic;
key_update : in std_logic;
decrypt : in std_logic;
bdi_ready : out std_logic;
bdi_valid : in std_logic;
bdi_type : in std_logic_vector(3 -1 downto 0);
bdi_partial : in std_logic;
bdi_eot : in std_logic;
bdi_eoi : in std_logic;
bdi_size : in std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
bdi_valid_bytes : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
bdi_pad_loc : in std_logic_vector(G_DBLK_SIZE/8 -1 downto 0);
--! PostProcessor
bdo : out std_logic_vector(G_DBLK_SIZE -1 downto 0);
bdo_valid : out std_logic;
bdo_ready : in std_logic;
bdo_size : out std_logic_vector(G_LBS_BYTES+1 -1 downto 0);
msg_auth_done : out std_logic;
msg_auth_valid : out std_logic
);
end entity CipherCore;
architecture structure of CipherCore is
-- Constants
constant CONST_UNROLED_R : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(UNROLED_ROUNDS, 8));
constant CONST_ROUNDS_A : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_A, 8));
constant CONST_ROUNDS_B : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_B, 8));
constant CONST_ROUNDS_AmR: std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(ROUNDS_A-UNROLED_ROUNDS, 4));
constant CONST_ROUNDS_BmR: std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(ROUNDS_B-UNROLED_ROUNDS, 4));
constant CONST_RATE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(RATE, 8));
constant STATE_WORD_SIZE : integer := 64;
constant KEY_SIZE : integer := 128;
constant CONST_KEY_SIZE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(KEY_SIZE, 8));
-- Segment Type Encoding
constant TYPE_AD : std_logic_vector(2 downto 0) := "000";
constant TYPE_PTCT : std_logic_vector(2 downto 0) := "010";
constant TYPE_TAG : std_logic_vector(2 downto 0) := "100";
constant TYPE_LEN : std_logic_vector(2 downto 0) := "101";
constant TYPE_NONCE : std_logic_vector(2 downto 0) := "110";
-- FSM state definition
type state_t is (STATE_IDLE,
STATE_UPDATE_KEY,
STATE_WRITE_NONCE_0,
STATE_WRITE_NONCE_1,
STATE_INITIALIZATION,
STATE_PERMUTATION,
STATE_FINALIZATION,
STATE_WAIT_FOR_INPUT,
STATE_PROCESS_TAG_0,
STATE_PROCESS_TAG_1);
-- FSM next and present state signals
signal State_DN,State_DP : state_t;
-- Ascon's state registers
signal X0_DN, X0_DP : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal X1_DN, X1_DP : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal X2_DN, X2_DP : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal X3_DN, X3_DP : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
signal X4_DN, X4_DP : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
-- Key register
signal Keyreg_DN : std_logic_vector(KEY_SIZE-1 downto 0);
signal Keyreg_DP : std_logic_vector(KEY_SIZE-1 downto 0);
-- Round counter
signal RoundCounter_DN : std_logic_vector(3 downto 0);
signal RoundCounter_DP : std_logic_vector(3 downto 0);
signal DisableRoundCounter_S : std_logic;
-- Additional control logic registers
signal IsFirstPTCT_DN, IsFirstPTCT_DP : std_logic;
signal IsDecryption_DN, IsDecryption_DP : std_logic;
-- Helper function, rotates a state word
function ROTATE_STATE_WORD (
word : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
constant rotate : integer)
return std_logic_vector is
begin -- ROTATE_STATE_WORD
return word(ROTATE-1 downto 0) & word(STATE_WORD_SIZE-1 downto ROTATE);
end ROTATE_STATE_WORD;
begin
-----------------------------------------------------------------------------
-- State operations (permutation, data loading, et cetera)
state_opeartions_p : process (IsDecryption_DP, IsFirstPTCT_DP,
Keyreg_DP, RoundCounter_DP,
RoundCounter_DP, State_DN,
State_DP, X0_DP,
X1_DP, X2_DP, X3_DP,
X4_DP, bdi,
bdi, bdi_eot, bdi_type,
bdi_valid, bdi_valid_bytes, decrypt) is
-- Roudn permutation input, intermediates, and output
variable P0_DV, P1_DV, P2_DV, P3_DV, P4_DV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable R0_DV, R1_DV, R2_DV, R3_DV, R4_DV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable S0_DV, S1_DV, S2_DV, S3_DV, S4_DV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable T0_DV, T1_DV, T2_DV, T3_DV, T4_DV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
variable U0_DV, U1_DV, U2_DV, U3_DV, U4_DV : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
-- Round constant
variable RoundConst_DV : std_logic_vector(63 downto 0);
-- Second part of tag comparison
variable TagCompResult_DV : std_logic_vector(RATE-1 downto 0);
begin -- process state_opeartions_p
--- Default values:
-- State variable X0-X4 --> keep current value
X0_DN <= X0_DP; X1_DN <= X1_DP; X2_DN <= X2_DP; X3_DN <= X3_DP; X4_DN <= X4_DP;
-- Permutation input --> use current state as default input
P0_DV := X0_DP; P1_DV := X1_DP; P2_DV := X2_DP; P3_DV := X3_DP; P4_DV := X4_DP;
-- Reset informational signals, when perfoming initialization
if State_DP = STATE_INITIALIZATION then
IsFirstPTCT_DN <= '1';
IsDecryption_DN <= decrypt;
else -- otherwise just keep value
IsFirstPTCT_DN <= IsFirstPTCT_DP;
IsDecryption_DN <= IsDecryption_DP;
end if;
--- P0,[P1] MUX: When data input is ready --> select P0,[P1] accordingly
if State_DP = STATE_WAIT_FOR_INPUT and (bdi_valid = '1') then
-- Encryption
if (IsDecryption_DP = '0') or (bdi_type = TYPE_AD) then
if RATE = 128 then -- Ascon128a variant
P0_DV := X0_DP xor bdi(RATE-1 downto RATE-64);
P1_DV := X1_DP xor bdi(63 downto 0);
else
P0_DV := X0_DP xor bdi;
end if;
-- Decryption
else
-- We need to take care of the number of valid bytes!
for i in 7 downto 0 loop
if RATE = 128 then -- Ascon128a variant
-- P1 xor input data ...
P0_DV(i*8 + 7 downto i*8) := bdi(i*8 + 7 + 64 downto i*8 + 64);
P1_DV(i*8 + 7 downto i*8) := bdi(i*8 + 7 downto i*8);
-- if invalid byte then use additionally xor X1
if bdi_valid_bytes(i) = '0' then
P1_DV(i*8 + 7 downto i*8) := P1_DV(i*8 + 7 downto i*8) xor X1_DP(i*8 + 7 downto i*8);
end if;
-- if invalid byte then use additionally xor X0
if bdi_valid_bytes(i+8) = '0' then
P0_DV(i*8 + 7 downto i*8) := P0_DV(i*8 + 7 downto i*8) xor X0_DP(i*8 + 7 downto i*8);
end if;
else -- Ascon128 variant
-- P0 xor input data ...
P0_DV(i*8 + 7 downto i*8) := bdi(i*8 + 7 downto i*8);
-- if invalid byte then use additionally xor X0
if bdi_valid_bytes(i) = '0' then
P0_DV(i*8 + 7 downto i*8) := P0_DV(i*8 + 7 downto i*8) xor X0_DP(i*8 + 7 downto i*8);
end if;
end if;
end loop; -- i
end if;
--- P1[2]-4 MUX:
-- if performing FINALIZATION next
if State_DN = STATE_FINALIZATION then
-- TODO: when 128a variant write P2
-- Add key before permutation
if RATE = 64 then -- Ascon128 variant
P1_DV := P1_DV xor Keyreg_DP(127 downto 64);
P2_DV := P2_DV xor Keyreg_DP(63 downto 0);
else -- Ascon128a variant
P2_DV := P2_DV xor Keyreg_DP(127 downto 64);
P3_DV := P3_DV xor Keyreg_DP(63 downto 0);
end if;
-- If first PT/CT never processed (empty AD + PT/CT case)
if (IsFirstPTCT_DP = '1') then
P4_DV(0) := not P4_DV(0); -- Add 0*||1
end if;
-- if performing PERMUTATION next
elsif ((bdi_valid = '1') and not ((bdi_type = TYPE_TAG) or
(bdi_type = TYPE_PTCT and bdi_eot = '1'))) then
-- ... and first round of PT/CT calculation
if (bdi_type = TYPE_PTCT) and (IsFirstPTCT_DP = '1') then
IsFirstPTCT_DN <= '0'; -- SET first PT/CT performed
P4_DV(0) := not P4_DV(0); -- Add 0*||1
end if;
end if;
end if;
-- Unroled round permutation
for r in 0 to UNROLED_ROUNDS-1 loop
-- Calculate round constant
RoundConst_DV := (others => '0'); -- set to zero
RoundConst_DV(7 downto 0) := not std_logic_vector(unsigned(RoundCounter_DP(3 downto 0)) + r) &
std_logic_vector(unsigned(RoundCounter_DP(3 downto 0)) + r);
R0_DV := P0_DV xor P4_DV;
R1_DV := P1_DV;
R2_DV := P2_DV xor P1_DV xor RoundConst_DV;
R3_DV := P3_DV;
R4_DV := P4_DV xor P3_DV;
S0_DV := R0_DV xor (not R1_DV and R2_DV);
S1_DV := R1_DV xor (not R2_DV and R3_DV);
S2_DV := R2_DV xor (not R3_DV and R4_DV);
S3_DV := R3_DV xor (not R4_DV and R0_DV);
S4_DV := R4_DV xor (not R0_DV and R1_DV);
T0_DV := S0_DV xor S4_DV;
T1_DV := S1_DV xor S0_DV;
T2_DV := not S2_DV;
T3_DV := S3_DV xor S2_DV;
T4_DV := S4_DV;
U0_DV := T0_DV xor ROTATE_STATE_WORD(T0_DV, 19) xor ROTATE_STATE_WORD(T0_DV, 28);
U1_DV := T1_DV xor ROTATE_STATE_WORD(T1_DV, 61) xor ROTATE_STATE_WORD(T1_DV, 39);
U2_DV := T2_DV xor ROTATE_STATE_WORD(T2_DV, 1) xor ROTATE_STATE_WORD(T2_DV, 6);
U3_DV := T3_DV xor ROTATE_STATE_WORD(T3_DV, 10) xor ROTATE_STATE_WORD(T3_DV, 17);
U4_DV := T4_DV xor ROTATE_STATE_WORD(T4_DV, 7) xor ROTATE_STATE_WORD(T4_DV, 41);
P0_DV := U0_DV;
P1_DV := U1_DV;
P2_DV := U2_DV;
P3_DV := U3_DV;
P4_DV := U4_DV;
end loop;
-- Do tag comparison when doing decryption in PROCESS TAG states
msg_auth_done <= '0'; --default
msg_auth_valid <= '0';
if IsDecryption_DP = '1' then
if (State_DP = STATE_PROCESS_TAG_0) then
-- valid data for comparison ready?
if bdi_valid = '1' then
if RATE = 128 then -- Ascon128a variant
-- signal we are done with comparison
msg_auth_done <= '1';
-- tags equal?
TagCompResult_DV := (X3_DP & X4_DP) xor Keyreg_DP;
if (TagCompResult_DV = bdi) then
msg_auth_valid <= '1';
end if;
else -- Ascon128 variant
X3_DN <= X3_DP xor Keyreg_DP(127 downto 64) xor bdi;
end if;
end if;
elsif (State_DP = STATE_PROCESS_TAG_1) then
-- debug
if RATE = 64 then -- Ascon128 variant
-- valid data for comparison ready?
if bdi_valid = '1' then
-- signal we are done with comparison
msg_auth_done <= '1';
-- Check if tags are equal
TagCompResult_DV := (X4_DP xor Keyreg_DP(63 downto 0) xor bdi);
if (X3_DP & TagCompResult_DV) = x"00000000000000000000000000000000" then
msg_auth_valid <= '1';
end if;
end if;
end if;
end if;
end if;
--- State X0...4 MUX: select input of state registers
case State_DP is
-- WRITE_NONCE_0 --> and init state
when STATE_WRITE_NONCE_0 =>
-- ready to receive
if (bdi_valid = '1') then
-- fill X0 with IV
X0_DN <= CONST_KEY_SIZE & CONST_RATE & CONST_ROUNDS_A & CONST_ROUNDS_B & x"00000000";
X1_DN <= Keyreg_DP(127 downto 64);
X2_DN <= Keyreg_DP(63 downto 0);
if RATE = 128 then -- Ascon128a variant
X3_DN <= bdi(RATE-1 downto RATE-64);
X4_DN <= bdi( 63 downto 0);
else -- Ascon128 variant
X3_DN <= bdi(63 downto 0);
end if;
end if;
-- WRITE_NONCE_1 --> second part of nonce
when STATE_WRITE_NONCE_1 =>
-- ready to receive
if (bdi_valid = '1') then
X4_DN <= bdi;
end if;
-- INITIALIZATION, PERMUTATION, FINALIZATION --> apply round transformation
when STATE_PERMUTATION | STATE_INITIALIZATION | STATE_FINALIZATION =>
X0_DN <= P0_DV; X1_DN <= P1_DV; X2_DN <= P2_DV;
-- Add key after initialization
if (State_DP = STATE_INITIALIZATION and RoundCounter_DP = CONST_ROUNDS_AmR) then
X3_DN <= P3_DV xor Keyreg_DP(127 downto 64);
X4_DN <= P4_DV xor Keyreg_DP(63 downto 0);
else
X3_DN <= P3_DV;
X4_DN <= P4_DV;
end if;
-- WAIT FOR INPUT --> apply round transformation when input is ready
when STATE_WAIT_FOR_INPUT =>
if bdi_valid = '1' then
-- State <= permutation output
X0_DN <= P0_DV; X1_DN <= P1_DV; X2_DN <= P2_DV; X3_DN <= P3_DV; X4_DN <= P4_DV;
end if;
when others => null;
end case;
end process state_opeartions_p;
-----------------------------------------------------------------------------
-- Update key register --> simple shift register
key_update_p: process (Keyreg_DP, State_DP, key, key_valid) is
begin -- process key_update_p
Keyreg_DN <= Keyreg_DP; -- default
key_ready <= '0';
-- only update key while in the update state
if State_DP = STATE_UPDATE_KEY then
key_ready <= '1'; -- always ready
-- shift register and insert new key data
if key_valid = '1' then
Keyreg_DN <= Keyreg_DP (KEY_SIZE-G_KEY_SIZE-1 downto 0) & key;
end if;
end if;
end process key_update_p;
-----------------------------------------------------------------------------
-- Input logic --> controlling input interface signals
input_logic_p: process (State_DP, bdi_type, bdi_valid) is
begin -- process input_logic_p
bdi_ready <= '1'; -- default, ready
-- We are busy when...
if State_DP = STATE_IDLE or
State_DP = STATE_UPDATE_KEY or
State_DP = STATE_INITIALIZATION or
State_DP = STATE_PERMUTATION or
(State_DP = STATE_PROCESS_TAG_0 and IsDecryption_DP = '0') or
(State_DP = STATE_PROCESS_TAG_1 and IsDecryption_DP = '0') or
State_DP = STATE_FINALIZATION then
-- signal busyness
bdi_ready <= '0';
end if;
end process input_logic_p;
-----------------------------------------------------------------------------
-- Output logic --> controlling output interface signals
output_logic_p: process (Keyreg_DP,
State_DP, X0_DP, X1_DP, X3_DP, X4_DP, bdi,
bdi, bdi_size,
bdi_type, bdi_valid, bdo_ready) is
begin -- process output_logic_p
bdo_valid <= '0'; -- default, nothing to output
if RATE = 128 then -- Ascon128a variant
bdo(RATE-1 downto RATE-64) <= X0_DP xor bdi(RATE-1 downto RATE-64);
bdo(63 downto 0) <= X1_DP xor bdi(63 downto 0);
else -- Ascon128 variant
bdo <= X0_DP xor bdi;
end if;
-- Wait for output to be ready
if bdo_ready = '1' then
-- waiting for output of PT/CT and there is something to output (size > 0)?
if (State_DP = STATE_WAIT_FOR_INPUT) then
if (bdi_valid = '1') and (bdi_type = TYPE_PTCT) and (bdi_size /= (bdi_size'range => '0')) then
bdo_valid <= '1';
end if;
-- output Tag part 1
elsif State_DP = STATE_PROCESS_TAG_0 then
bdo_valid <= '1';
if RATE = 128 then -- Ascon128a variant
bdo(RATE-1 downto RATE-64) <= X3_DP xor Keyreg_DP(127 downto 64);
bdo(63 downto 0) <= X4_DP xor Keyreg_DP(63 downto 0);
else -- Ascon128 variant
bdo <= X3_DP xor Keyreg_DP(127 downto 64);
end if;
-- output Tag part 2
elsif State_DP = STATE_PROCESS_TAG_1 then
bdo_valid <= '1';
bdo <= X4_DP xor Keyreg_DP(63 downto 0);
end if;
end if;
end process output_logic_p;
-----------------------------------------------------------------------------
-- Next state logic
fsm_comb_p: process (IsDecryption_DP, RoundCounter_DP, State_DP, bdi_eot,
bdi_type, bdi_valid, bdo_ready, key_update, key_valid) is
begin -- process fsm_comb_p
State_DN <= State_DP; -- default
-- FSM state transfers
case State_DP is
-- IDLE
when STATE_IDLE =>
-- preprocessor forces key update
if (key_update = '1') then
State_DN <= STATE_UPDATE_KEY;
-- skip key update and start writing the nonce
elsif (bdi_valid = '1') and (bdi_type = TYPE_NONCE) then
State_DN <= STATE_WRITE_NONCE_0;
end if;
-- UPDATE_KEY
when STATE_UPDATE_KEY =>
-- when key is invalid we assume the key update is finished
if (key_valid = '0' and key_update = '0') then
-- go back to IDLE
State_DN <= STATE_IDLE;
end if;
-- WRITE_NONCE_0 (Part 1)
when STATE_WRITE_NONCE_0 =>
-- write first part of nonce
if (bdi_valid = '1') then
if RATE = 128 then -- Ascon128a variant
State_DN <= STATE_INITIALIZATION;
else
State_DN <= STATE_WRITE_NONCE_1;
end if;
end if;
-- WRITE_NONCE_1 (Part 2)
when STATE_WRITE_NONCE_1 =>
-- write second part of nonce
if (bdi_valid = '1') then
State_DN <= STATE_INITIALIZATION;
end if;
-- INITIALIZATION
when STATE_INITIALIZATION =>
if RoundCounter_DP = CONST_ROUNDS_AmR then
State_DN <= STATE_WAIT_FOR_INPUT;
end if;
-- PERMUTATION
when STATE_PERMUTATION =>
if RoundCounter_DP = CONST_ROUNDS_BmR then
State_DN <= STATE_WAIT_FOR_INPUT;
end if;
-- FINALIZATION
when STATE_FINALIZATION =>
if RoundCounter_DP = CONST_ROUNDS_AmR then
State_DN <= STATE_PROCESS_TAG_0;
end if;
-- PROCESS TAG PART 1
when STATE_PROCESS_TAG_0 =>
-- encryption -> wait for output stream to be ready
if (IsDecryption_DP = '0') then
if (bdo_ready = '1') then
if RATE = 128 then -- Ascon128a variant
State_DN <= STATE_IDLE;
else -- Ascon128 variant
State_DN <= STATE_PROCESS_TAG_1;
end if;
end if;
else
-- decryption -> wait for tag for comparison
if (bdi_valid = '1') then
if RATE = 128 then -- Ascon128a variant
State_DN <= STATE_IDLE;
else -- Ascon128 variant
State_DN <= STATE_PROCESS_TAG_1;
end if;
end if;
end if;
-- PROCESS TAG PART 2
when STATE_PROCESS_TAG_1 =>
-- encryption -> wait for output stream to be ready
if (IsDecryption_DP = '0') then
if (bdo_ready = '1') then
State_DN <= STATE_IDLE;
end if;
else
-- decryption -> wait for tag for comparison
if (bdi_valid = '1') then
State_DN <= STATE_IDLE;
end if;
end if;
-- WAIT_FOR_INPUT
when STATE_WAIT_FOR_INPUT =>
-- input is ready so process
if (bdi_valid = '1') then
-- if its a tag or last PT/CT then...
if (bdi_type = TYPE_TAG) or
(bdi_type = TYPE_PTCT and bdi_eot = '1')then
State_DN <= STATE_FINALIZATION;
else -- process AD or PT/CT
-- PERMUTATION state is unnecessary if we fully unroll
if (UNROLED_ROUNDS /= ROUNDS_B) then
State_DN <= STATE_PERMUTATION;
end if;
end if;
end if;
when others => null;
end case;
end process fsm_comb_p;
-----------------------------------------------------------------------------
-- Round counter realization
round_counter_p: process (DisableRoundCounter_S, RoundCounter_DP, State_DP,
bdi_valid) is
variable CounterVal_DV : integer;
begin -- process round_counter_p
RoundCounter_DN <= RoundCounter_DP; -- default
-- Enable counter during ...
if (State_DP = STATE_PERMUTATION) or
(State_DP = STATE_INITIALIZATION) or
(State_DP = STATE_FINALIZATION) or
(State_DP = STATE_WAIT_FOR_INPUT and bdi_valid = '1') then
-- Counter += #unroled rounds
CounterVal_DV := to_integer(unsigned(RoundCounter_DP)) + UNROLED_ROUNDS; -- increment
-- Overrun detection --> set back to 0
if (CounterVal_DV >= ROUNDS_A) or (State_DP = STATE_PERMUTATION and CounterVal_DV >= ROUNDS_B) then
CounterVal_DV := 0;
end if;
-- set next counter register value
RoundCounter_DN <= std_logic_vector(to_unsigned(CounterVal_DV, RoundCounter_DN'length));
else -- Disable round counter and set it to zero
RoundCounter_DN <= (others => '0');
end if;
end process round_counter_p;
-----------------------------------------------------------------------------
-- Process for all registers in design
gen_register_with_asynchronous_reset : if G_ASYNC_RSTN = false generate
register_process_p : process (clk, rst) is
begin -- process register_process_p
if rst = '1' then -- asynchronous reset (active high)
State_DP <= STATE_IDLE;
X0_DP <= (others => '0');
X1_DP <= (others => '0');
X2_DP <= (others => '0');
X3_DP <= (others => '0');
X4_DP <= (others => '0');
Keyreg_DP <= (others => '0');
RoundCounter_DP <= (others => '0');
IsFirstPTCT_DP <= '1';
IsDecryption_DP <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
State_DP <= State_DN;
X0_DP <= X0_DN;
X1_DP <= X1_DN;
X2_DP <= X2_DN;
X3_DP <= X3_DN;
X4_DP <= X4_DN;
Keyreg_DP <= Keyreg_DN;
RoundCounter_DP <= RoundCounter_DN;
IsFirstPTCT_DP <= IsFirstPTCT_DN;
IsDecryption_DP <= IsDecryption_DN;
end if;
end process register_process_p;
end generate gen_register_with_asynchronous_reset;
-- else generate with synchronous reset
gen_register_with_synchronous_reset : if G_ASYNC_RSTN = true generate
register_process_p : process (clk, rst) is
begin -- process register_process_p
if clk'event and clk = '1' then -- rising clock edge
if rst = '1' then -- synchronous reset (active high)
State_DP <= STATE_IDLE;
X0_DP <= (others => '0');
X1_DP <= (others => '0');
X2_DP <= (others => '0');
X3_DP <= (others => '0');
X4_DP <= (others => '0');
Keyreg_DP <= (others => '0');
RoundCounter_DP <= (others => '0');
IsFirstPTCT_DP <= '1';
IsDecryption_DP <= '0';
else
State_DP <= State_DN;
X0_DP <= X0_DN;
X1_DP <= X1_DN;
X2_DP <= X2_DN;
X3_DP <= X3_DN;
X4_DP <= X4_DN;
Keyreg_DP <= Keyreg_DN;
RoundCounter_DP <= RoundCounter_DN;
IsFirstPTCT_DP <= IsFirstPTCT_DN;
IsDecryption_DP <= IsDecryption_DN;
end if;
end if;
end process register_process_p;
end generate gen_register_with_synchronous_reset;
end structure;
| apache-2.0 |
hoangt/PoC | src/bus/stream/stream_Source.vhdl | 2 | 4991 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: A generic buffer module for the PoC.Stream protocol.
--
-- Description:
-- ------------------------------------
-- This module implements a generic buffer (FifO) for the PoC.Stream protocol.
-- It is generic in DATA_BITS and in META_BITS as well as in FifO depths for
-- data and meta information.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.stream.all;
entity stream_Source is
generic (
TESTcaseS : T_SIM_STREAM_FRAMEGROUP_VECTOR_8
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- Control interface
Enable : in STD_LOGIC;
-- OUT Port
Out_Valid : out STD_LOGIC;
Out_Data : out T_SLV_8;
Out_SOF : out STD_LOGIC;
Out_EOF : out STD_LOGIC;
Out_Ack : in STD_LOGIC
);
end entity;
architecture rtl of stream_Source is
constant MAX_CYCLES : NATURAL := 10 * 1000;
constant MAX_ERRORS : NATURAL := 50;
-- dummy signals for iSIM
signal FrameGroupNumber_us : UNSIGNED(log2ceilnz(TESTcaseS'length) - 1 downto 0) := (others => '0');
begin
process
variable Cycles : NATURAL := 0;
variable Errors : NATURAL := 0;
variable FrameGroupNumber : NATURAL := 0;
variable WordIndex : NATURAL := 0;
variable CurFG : T_SIM_STREAM_FRAMEGROUP_8;
begin
-- set interface to default values
Out_Valid <= '0';
Out_Data <= (others => 'U');
Out_SOF <= '0';
Out_EOF <= '0';
-- wait for global enable signal
wait until (Enable = '1');
-- synchronize to clock
wait until rising_edge(Clock);
-- for each testcase in list
for TestcaseIndex in 0 to TESTcaseS'length - 1 loop
-- initialize per loop
Cycles := 0;
Errors := 0;
CurFG := TESTcaseS(TestcaseIndex);
-- continue with next frame if current is disabled
assert FALSE report "active=" & to_string(CurFG.Active) severity WARNING;
next when CurFG.Active = FALSE;
-- write dummy signals for iSIM
FrameGroupNumber := TestcaseIndex;
FrameGroupNumber_us <= to_unsigned(FrameGroupNumber, FrameGroupNumber_us'length);
-- PrePause
for i in 1 to CurFG.PrePause loop
wait until rising_edge(Clock);
end LOOP;
WordIndex := 0;
-- infinite loop
loop
-- check for to many simulation cycles
assert (Cycles < MAX_CYCLES) report "MAX_CYCLES reached: framegroup=" & INTEGER'image(to_integer(FrameGroupNumber_us)) severity FAILURE;
-- ASSERT (Errors < MAX_ERRORS) report "MAX_ERRORS reached" severity FAILURE;
Cycles := Cycles + 1;
wait until rising_edge(Clock);
-- write frame data to interface
Out_Valid <= CurFG.Data(WordIndex).Valid;
Out_Data <= CurFG.Data(WordIndex).Data;
Out_SOF <= CurFG.Data(WordIndex).SOF;
Out_EOF <= CurFG.Data(WordIndex).EOF;
wait until falling_edge(Clock);
-- go to next word if interface counterpart has accepted the current word
if (Out_Ack = '1') then
WordIndex := WordIndex + 1;
end if;
-- check if framegroup end is reached => exit LOOP
assert FALSE report "WordIndex=" & INTEGER'image(WordIndex) severity WARNING;
exit when ((WordIndex /= 0) AND (CurFG.Data(WordIndex - 1).EOFG = TRUE));
end loop;
-- PostPause
for i in 1 to CurFG.PostPause loop
wait until rising_edge(Clock);
end loop;
assert FALSE report "new round" severity WARNING;
end loop;
-- set interface to default values
wait until rising_edge(Clock);
Out_Valid <= '0';
Out_Data <= (others => 'U');
Out_SOF <= '0';
Out_EOF <= '0';
end process;
end architecture;
| apache-2.0 |
hoangt/PoC | src/comm/remote/remote_terminal_control.vhdl | 2 | 19045 | -- EMACS settings: -*- tab-width:2 -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-------------------------------------------------------------------------------
-- Description: Simple terminal interface to monitor and manipulate
-- basic IO components such as buttons, slide switches, LED
-- and hexadecimal displays.
--
-- A typical transport would be a UART connection using a terminal application.
-- A command line starts with a single letter identifying the addressed
-- resource type:
--
-- R .. Reset - strobed input to the design
-- P .. Pulse - strobed input to the design
-- S .. Switch - stateful input to the design
-- L .. Light - (bit) output from the design
-- D .. Digit - (hex) output from the design
--
-- This letter may be followed by a hexadecimal input vector, which triggers
--
-- R - a strobe on the corresponding inputs,
-- P - a strobe on the corresponding inputs, and
-- S - a state toggle of the corresponding inputs.
--
-- The input vector is ignored for outputs from the design.
-- The command line may contain an arbitrary amount of spaces.
--
-- The terminal interface will echo with:
--
-- <resource character>[<bit count>'<hex output vector>]
--
-- The <bit count> and <hex output vector> will only be present if, at least,
-- a single instance of the addressed resource type is available.
-- In particular, the resource characters of lines starting with other than
-- the listed resource types will simply be echoed.
-- The <bit count> describes how many bits of the addressed resource are
-- available, which may be used to explore the resources using a command line
-- with no or a zero input argument. The <bit count> is typically provided in
-- decimal (default) but may be changed to hexadecimal through the generic
-- parameter COUNT_DECIMAL.
-- The <hex output vector> acknowledges the input (R and P) and informs about
-- the current state (S, L and D).
--
-- Example:
-- > L
-- L10'21D
-- > D
-- D8'5E
-- > A
-- A
-- > S
-- S6'00
-- > S3A
-- S6'3A
-- > S 1
-- S6'3B
-- > P8
-- P4'8
-- > P
-- P4'0
-- Authors: Thomas B. Preußer <[email protected]>
-------------------------------------------------------------------------------
-- Copyright 2007-2014 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library poc;
use poc.functions.all;
entity remote_terminal_control is
generic (
RESET_COUNT : natural;
PULSE_COUNT : natural;
SWITCH_COUNT : natural;
LIGHT_COUNT : natural;
DIGIT_COUNT : natural;
COUNT_DECIMAL : boolean := true
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- UART Connectivity
idat : in std_logic_vector(6 downto 0);
istb : in std_logic;
odat : out std_logic_vector(6 downto 0);
ordy : in std_logic;
oput : out std_logic;
-- Control Outputs
resets : out std_logic_vector(imax(RESET_COUNT -1, 0) downto 0);
pulses : out std_logic_vector(imax(PULSE_COUNT -1, 0) downto 0);
switches : out std_logic_vector(imax(SWITCH_COUNT-1, 0) downto 0);
-- Monitor Inputs
lights : in std_logic_vector(imax( LIGHT_COUNT-1, 0) downto 0);
digits : in std_logic_vector(imax(4*DIGIT_COUNT-1, 0) downto 0)
);
end remote_terminal_control;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of remote_terminal_control is
type tKind is (KIND_NONE,
KIND_RESET, KIND_PULSE, KIND_SWITCH,
KIND_LIGHT, KIND_DIGIT);
--constant KIND_NONE : natural := 0;
--constant KIND_RESET : natural := 1;
--constant KIND_PULSE : natural := 2;
--constant KIND_SWITCH : natural := 3;
--constant KIND_LIGHT : natural := 4;
--constant KIND_DIGIT : natural := 5;
--subtype tKind is natural range KIND_NONE to KIND_DIGIT;
subtype tActual is tKind range KIND_RESET to KIND_DIGIT;
subtype tInput is tActual range KIND_RESET to KIND_SWITCH;
subtype tOutput is tActual range KIND_LIGHT to KIND_DIGIT;
-----------------------------------------------------------------------------
-- Counts
type tCounts is array(tKind range<>) of natural;
constant COUNTS : tCounts := (0,
RESET_COUNT, PULSE_COUNT, SWITCH_COUNT,
LIGHT_COUNT, 4*DIGIT_COUNT);
function max_count(arr : tCounts) return natural is
-- Without this copy of arr, ISE (as of version 14.7) will choke.
variable a : tCounts(arr'range) := (others => 0);
variable res : natural;
begin
a(arr'range) := arr;
res := 0;
for i in a'range loop
if a(i) > res then
res := a(i);
end if;
end loop;
return res;
end max_count;
constant PAR_BITS : natural := max_count(COUNTS(tInput));
constant RES_BITS : natural := max_count(COUNTS(tActual));
constant ECO_BITS : natural := 4*((RES_BITS+3)/4);
function log10ceil(x : natural) return positive is
variable scale, res : positive;
begin
scale := 10;
res := 1;
while x >= scale loop
scale := 10*scale;
res := res+1;
end loop;
return res;
end log10ceil;
function makeCntBits return positive is
begin
if COUNT_DECIMAL then
return 4*log10ceil(RES_BITS);
end if;
return log2ceil(RES_BITS);
end makeCntBits;
constant CNT_BITS : positive := makeCntBits;
subtype tOutCount is unsigned(CNT_BITS-1 downto 0);
type tOutCounts is array(tKind range<>) of tOutCount;
function makeOutCounts return tOutCounts is
variable res : tOutCounts(COUNTS'range);
variable ele : tOutCount;
variable rmd : natural;
begin
for i in COUNTS'range loop
if COUNT_DECIMAL then
rmd := COUNTS(i);
for j in 0 to ele'length/4-1 loop
ele(4*j+3 downto 4*j) := to_unsigned(rmd mod 10, 4);
rmd := rmd/10;
end loop;
else
ele := to_unsigned(COUNTS(i), CNT_BITS);
end if;
res(i) := ele;
end loop;
return res;
end;
constant OUT_COUNTS : tOutCounts(COUNTS'range) := makeOutCounts;
subtype tCode is std_logic_vector(4 downto 0);
type tCodes is array(tKind range<>) of tCode;
constant CODES : tCodes(tActual) := ("10010", "10000", "10011", "01100", "00100");
type tStrobes is array(tKind range<>) of boolean;
constant STROBES : tStrobes(tInput) := (true, true, false);
signal BufVld : std_logic := '0';
signal BufCmd : std_logic_vector(4 downto 0) := (others => '-');
signal BufCnt : unsigned(CNT_BITS-1 downto 0) := (others => '-');
signal BufEco : std_logic_vector(0 to ECO_BITS-1) := (others => '-');
signal BufAck : std_logic;
begin
-- Reading the UART input stream
blkReader: block
type tState is (Idle, Command);
signal State : tState := Idle;
signal NextState : tState;
signal Cmd : std_logic_vector(4 downto 0) := (others => '-');
signal Arg : std_logic_vector(PAR_BITS-1 downto 0) := (others => '-');
signal Sel : tKind := KIND_NONE;
signal Load : std_logic;
signal Shift : std_logic;
signal Commit : std_logic;
subtype tEcho is std_logic_vector(0 to ECO_BITS-1);
type tEchos is array(tKind range<>) of tEcho;
signal echos : tEchos(tKind);
function leftAlignedBCD(x : std_logic_vector) return tEcho is
constant MY_BITS : positive := 4*((x'length+3)/4);
variable res : tEcho;
begin
res := (others => '-');
res(0 to 3) := x"0";
res(MY_BITS-x'length to MY_BITS-1) := x;
return res;
end leftAlignedBCD;
begin
-- State Registers
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
State <= Idle;
Cmd <= (others => '-');
Arg <= (others => '-');
else
State <= NextState;
if Load = '1' then
Cmd <= idat(4 downto 0);
Arg <= (others => '0');
Sel <= KIND_NONE;
for i in CODES'range loop
if CODES(i) = idat(4 downto 0) then
Sel <= i;
end if;
end loop;
elsif Shift = '1' then
Arg <= Arg(Arg'left-4 downto 0) &
std_logic_vector(unsigned(idat(3 downto 0)) + (idat(6)&"00"&idat(6)));
end if;
end if;
end if;
end process;
-- Common Reader State Machine
process(State, istb, idat)
begin
NextState <= State;
Load <= '0';
Shift <= '0';
Commit <= '0';
if istb = '1' then
case State is
when Idle =>
if idat(6) = '1' then
Load <= '1';
NextState <= Command;
end if;
when Command =>
if idat(6) = '1' or (idat(5) = '1' and idat(4) = '1') then
Shift <= '1';
elsif idat(6) = '0' and idat(5) = '0' and idat(4) = '0' then
Commit <= '1';
NextState <= Idle;
end if;
end case;
end if;
end process;
echos(KIND_NONE) <= (others => '-');
-- Generate Control Inputs
genInputs: for i in tInput generate
-- Control not used
genNone: if COUNTS(i) = 0 generate
genReset: if i = KIND_RESET generate
resets <= "X";
end generate genReset;
genPulse: if i = KIND_PULSE generate
pulses <= "X";
end generate genPulse;
genSwitch: if i = KIND_SWITCH generate
switches <= "X";
end generate genSwitch;
echos(i) <= (others => '-');
end generate genNone;
-- Controls available
genAvail: if COUNTS(i) > 0 generate
signal Outputs : std_logic_vector(COUNTS(i)-1 downto 0) := (others => '0');
signal onxt : std_logic_vector(Outputs'range);
begin
-- Output Computation: Strobed
genStrobed: if STROBES(i) generate
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Outputs <= (others => '0');
else
if Commit = '1' and Sel = i then
Outputs <= onxt;
else
Outputs <= (others => '0');
end if;
end if;
end if;
end process;
onxt <= Arg(Outputs'range);
end generate genStrobed;
-- Output Computation: State
genState: if not STROBES(i) generate
process(clk)
begin
if rising_edge(clk) then
if Commit = '1' and Sel = i then
Outputs <= onxt;
end if;
end if;
end process;
onxt <= Outputs xor Arg(Outputs'range);
end generate genState;
echos(i) <= leftAlignedBCD(onxt);
-- Assign to Output Pins
genReset: if i = KIND_RESET generate
resets <= Outputs;
end generate genReset;
genPulse: if i = KIND_PULSE generate
pulses <= Outputs;
end generate genPulse;
genSwitch: if i = KIND_SWITCH generate
switches <= Outputs;
end generate genSwitch;
end generate genAvail;
end generate genInputs;
process(lights, digits)
begin
echos(KIND_LIGHT) <= (others => '-');
echos(KIND_DIGIT) <= (others => '-');
if LIGHT_COUNT > 0 then
echos(KIND_LIGHT) <= leftAlignedBCD(lights);
end if;
if DIGIT_COUNT > 0 then
echos(KIND_DIGIT) <= leftAlignedBCD(digits);
end if;
end process;
-- Build Data Record for Writer
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
BufVld <= '0';
BufCmd <= (others => '-');
BufCnt <= (others => '-');
BufEco <= (others => '-');
else
if Commit = '1' then
BufVld <= '1';
BufCmd <= Cmd;
BufCnt <= OUT_COUNTS(Sel);
BufEco <= echos(Sel);
elsif BufAck = '1' then
BufVld <= '0';
BufCmd <= (others => '-');
BufCnt <= (others => '-');
BufEco <= (others => '-');
end if;
end if;
end if;
end process;
end block blkReader;
blkWrite: block
type tState is (Idle, OutCommand, OutCount, OutTick, OutEcho, OutEOL);
signal State : tState := Idle;
signal NextState : tState;
signal OutCmd : std_logic_vector(4 downto 0) := (others => '-');
signal OutCnt : unsigned(4*((BufCnt'length+3)/4)-1 downto 0) := (others => '-');
signal OutEco : std_logic_vector(0 to ECO_BITS-1) := (others => '-');
signal Locked : std_logic := '-';
signal NextLocked : std_logic;
signal OutCntDone : std_logic;
signal OutCntDecr : unsigned(2 downto 0);
signal NextOutCnt : unsigned(OutCnt'length downto 0);
signal ShiftCnt : std_logic;
signal ShiftEco : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
State <= Idle;
OutCmd <= (others => '-');
OutCnt <= (others => '-');
OutEco <= (others => '-');
Locked <= '-';
else
State <= NextState;
if BufAck = '1' then
OutCmd <= BufCmd;
OutCnt <= (others => '0');
OutCnt(BufCnt'length-1 downto 0) <= unsigned(BufCnt);
OutEco <= BufEco;
Locked <= '0';
else
-- OutCnt Register
if OutCnt'length > 4 and ShiftCnt = '1' then
OutCnt <= OutCnt(OutCnt'left-4 downto 0) & OutCnt(OutCnt'left downto OutCnt'left-3);
else
OutCnt <= NextOutCnt(OutCnt'range);
end if;
Locked <= NextLocked;
-- OutEco Register
if ShiftEco = '1' then
OutEco <= OutEco(4 to OutEco'right) & "----";
end if;
end if;
end if;
end if;
end process;
NextLocked <= 'X' when Is_x(std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3))) else
'1' when OutCnt(OutCnt'left downto OutCnt'left-3) /= x"0" else
Locked;
genSingleDig: if OutCnt'length = 4 generate
OutCntDone <= '1';
end generate;
genMultiDig: if OutCnt'length > 4 generate
signal Cnt : unsigned(log2ceil(OutCnt'length/4)-1 downto 0) := (others => '-');
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
Cnt <= (others => '-');
else
if BufAck = '1' then
Cnt <= (others => '0');
elsif ShiftCnt = '1' then
Cnt <= Cnt + 1;
end if;
end if;
end if;
end process;
OutCntDone <= 'X' when Is_X(std_logic_vector(Cnt)) else
'1' when (Cnt or not to_unsigned(OutCnt'length/4-1, Cnt'length)) = (Cnt'range => '1') else
'0';
end generate;
genDec: if COUNT_DECIMAL generate
process(OutCnt, OutCntDecr)
variable sub : unsigned(2 downto 0);
variable d : unsigned(4 downto 0);
begin
sub := OutCntDecr;
for i in 0 to OutCnt'length/4-1 loop
d := ('0'&OutCnt(4*i+3 downto 4*i)) - sub;
if d(4) = '0' then
NextOutCnt(4*i+3 downto 4*i) <= d(3 downto 0);
sub := to_unsigned(0, sub'length);
else
NextOutCnt(4*i+3 downto 4*i) <= d(3 downto 0) - 6;
sub := to_unsigned(1, sub'length);
end if;
end loop;
NextOutCnt(OutCnt'length) <= sub(0);
end process;
end generate genDec;
genHex: if not COUNT_DECIMAL generate
NextOutCnt <= ('0'&OutCnt) - OutCntDecr;
end generate genHex;
process(State, ordy, BufVld, OutCmd, OutCnt, OutEco, OutCntDone, NextLocked, NextOutCnt)
begin
NextState <= State;
BufAck <= '0';
ShiftCnt <= '0';
ShiftEco <= '0';
OutCntDecr <= (others => '0');
odat <= (others => '-');
oput <= '0';
case State is
when Idle =>
if BufVld = '1' then
BufAck <= '1';
NextState <= OutCommand;
end if;
when OutCommand =>
odat <= "10" & OutCmd;
oput <= '1';
if ordy = '1' then
NextState <= OutCount;
end if;
when OutCount =>
if COUNT_DECIMAL or OutCnt(OutCnt'left downto OutCnt'left-3) < 10 then
odat <= "011" & std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3));
else
odat <= "100" & std_logic_vector(OutCnt(OutCnt'left downto OutCnt'left-3)+7);
end if;
oput <= NextLocked;
if ordy = '1' then
ShiftCnt <= '1';
if OutCntDone = '1' then
if NextLocked = '1' then
NextState <= OutTick;
else
NextState <= OutEOL;
end if;
end if;
end if;
when OutTick =>
odat <= "0100111";
oput <= '1';
if ordy = '1' then
OutCntDecr <= to_unsigned(1, OutCntDecr'length);
NextState <= OutEcho;
end if;
when OutEcho =>
if unsigned(OutEco(0 to 3)) < 10 then
odat <= "011" & OutEco(0 to 3);
else
odat <= "100" & std_logic_vector(unsigned(OutEco(0 to 3))+7);
end if;
oput <= '1';
if ordy = '1' then
ShiftEco <= '1';
OutCntDecr <= "100";
if NextOutCnt(OutCnt'length) = '1' then
NextState <= OutEOL;
end if;
end if;
when OutEOL =>
odat <= "0001010";
oput <= '1';
if ordy = '1' then
NextState <= Idle;
end if;
end case;
end process;
end block blkWrite;
end rtl;
| apache-2.0 |
hoangt/PoC | tb/common/simulation.v08.vhdl | 4 | 12321 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
package simulation is
-- predefined constants to ease testvector concatenation
constant U8 : T_SLV_8 := (others => 'U');
constant U16 : T_SLV_16 := (others => 'U');
constant U24 : T_SLV_24 := (others => 'U');
constant U32 : T_SLV_32 := (others => 'U');
constant D8 : T_SLV_8 := (others => '-');
constant D16 : T_SLV_16 := (others => '-');
constant D24 : T_SLV_24 := (others => '-');
constant D32 : T_SLV_32 := (others => '-');
-- Testbench Status Management
-- ===========================================================================
-- VHDL'08: Provide a protected tSimStatus type that may be used for
-- other purposes as well. For compatibility with the VHDL'93
-- implementation, the plain procedure implementation is also
-- provided on top of a package private instance of this type.
type T_TB_STATUS is protected
-- The status is changed to failed. If a message is provided, it is
-- reported as an error.
procedure simFail(msg : in string := "");
-- If the passed condition has evaluated false, the status is marked
-- as failed. In this case, the optional message will be reported as
-- an error if provided.
procedure simAssert(cond : in boolean; msg : in string := "");
-- Prints the final status. Unless simFail() or simAssert() with a
-- false condition have been called before, a successful completion
-- will be indicated, a failure otherwise.
procedure simReport;
end protected;
type T_SIM_STATUS is protected
procedure stop;
impure function isStopped return BOOLEAN;
end protected;
-- The testbench is marked as failed. If a message is provided, it is
-- reported as an error.
procedure tbFail(msg : in string := "");
-- If the passed condition has evaluated false, the testbench is marked
-- as failed. In this case, the optional message will be reported as an
-- error if one was provided.
procedure tbAssert(cond : in boolean; msg : in string := "");
-- Prints out the overall testbench result as defined by the automated
-- testbench process. Unless tbFail() or tbAssert() with a false condition
-- have been called before, a successful completion will be reported, a
-- failure otherwise.
procedure tbPrintResult;
-- clock generation
-- ===========================================================================
subtype T_DutyCycle is REAL range 0.0 to 1.0;
procedure simStop;
impure function simIsStopped return BOOLEAN;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5);
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5);
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN);
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0');
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8);
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16);
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24);
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32);
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48);
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64);
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC;
end;
use std.TextIO.all;
package body simulation is
-- Testbench Status Management
-- ===========================================================================
type T_TB_STATUS is protected body
-- Internal state variable to log a failure condition for final reporting.
-- Once de-asserted, this variable will never return to a value of true.
variable pass : boolean := true;
procedure simFail(msg : in string := "") is
begin
if msg'length > 0 then
report msg severity error;
end if;
pass := false;
end;
procedure simAssert(cond : in boolean; msg : in string := "") is
begin
if not cond then
simFail(msg);
end if;
end;
procedure simReport is
variable l : line;
begin
write(l, string'("SIMULATION RESULT = "));
if pass then
write(l, string'("PASSED"));
else
write(l, string'("FAILED"));
end if;
writeline(output, l);
end;
end protected body;
type T_SIM_STATUS is protected body
variable stopped : BOOLEAN := FALSE;
procedure stop is
begin
stopped := TRUE;
end procedure;
impure function isStopped return BOOLEAN is
begin
return stopped;
end function;
end protected body;
-- The default global tSimStatus object.
shared variable tbStatus : T_TB_STATUS;
shared variable simStatus : T_SIM_STATUS;
-- legacy procedures
-- ===========================================================================
procedure tbFail(msg : in string := "") is
begin
tbStatus.simFail(msg);
end;
procedure tbAssert(cond : in boolean; msg : in string := "") is
begin
tbStatus.simAssert(cond, msg);
end;
procedure tbPrintResult is
begin
tbStatus.simReport;
end procedure;
-- clock generation
-- ===========================================================================
procedure simStop is
begin
simStatus.stop;
end procedure;
impure function simIsStopped return BOOLEAN is
begin
return simStatus.isStopped;
end function;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is
constant Period : TIME := to_time(Frequency);
begin
simGenerateClock(Clock, Period, DutyCycle);
end procedure;
procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is
constant TIME_HIGH : TIME := Period * DutyCycle;
constant TIME_LOW : TIME := Period - TIME_HIGH;
begin
Clock <= '0';
while (not simStatus.isStopped) loop
wait for TIME_LOW;
Clock <= '1';
wait for TIME_HIGH;
Clock <= '0';
end loop;
end procedure;
-- waveform generation
-- ===========================================================================
procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is
variable State : BOOLEAN := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is
variable State : STD_LOGIC := InitialValue;
begin
Wave <= State;
for i in Waveform'range loop
wait for Waveform(i);
State := not State;
Wave <= State;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is
begin
Wave <= InitialValue;
for i in Waveform'range loop
wait for Waveform(i).Delay;
Wave <= Waveform(i).Value;
end loop;
end procedure;
function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is
begin
return (0 => Pause, 1 => ResetPulse);
end function;
end package body;
| apache-2.0 |
hoangt/PoC | src/arith/arith_sqrt.vhdl | 2 | 3744 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================================================================================================
-- Description: Iterative Square Root Extractor.
-- Its computation requires (N+1)/2 steps for an argument bit width of N.
--
-- Authors: Thomas B. Preußer
-- ============================================================================================================================================================
-- Copyright 2007-2014 Technische Universität Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity arith_sqrt is
generic (
N : positive -- := 8 -- Bit Width of Argument
);
port (
-- Global Control
rst : in std_logic; -- Reset (synchronous)
clk : in std_logic; -- Clock
-- Inputs
arg : in std_logic_vector(N-1 downto 0); -- Radicand
start : in std_logic; -- Start Strobe
-- Outputs
sqrt : out std_logic_vector((N-1)/2 downto 0); -- Result
rdy : out std_logic -- Ready / Done
);
end arith_sqrt;
architecture rtl of arith_sqrt is
-- Number of Iteration Steps = Number of Result Digits
constant STEPS : positive := (N+1)/2;
-- Intern Registers
signal Rmd : unsigned(N+STEPS-1 downto 0); -- Remainder / Result
signal Vld : unsigned(STEPS-1 downto 0); -- Result Flags
signal Res : unsigned(STEPS-1 downto 0); -- Extracted Result
-- Tentative Difference
signal diff : unsigned(STEPS+1 downto 0);
begin -- rtl
-- Registers
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
-- Only clear Ready, everything else: '-'
Rmd <= (others => '-');
Vld <= (others => '-');
Vld(Vld'left) <= '0';
else
if start = '1' then
-- Initilize Computation
Rmd <= (Rmd'left downto N => '0') & unsigned(arg);
Vld <= (others => '1');
elsif Vld(Vld'left) = '1' then
-- Computation Step
-- New Residue
Rmd(N-1 downto 0) <= Rmd(N-3 downto 0) & '-' & not diff(diff'left); -- just shift lower bits
if diff(diff'left) = '1' then
-- Sub failed: just shift upper Part
Rmd(Rmd'left downto N) <= Rmd(Rmd'left-2 downto N-2);
else
-- Sub succeeded: replace by shifted Difference
Rmd(Rmd'left downto N) <= diff(diff'left-2 downto 0);
end if;
-- Validate Result Digit
Vld <= Vld(Vld'left-1 downto 0) & '0';
end if;
end if;
end if;
end process;
-- Extract Result
genRes: for i in Res'range generate
Res(i) <= Rmd(2*i) and not Vld(i);
end generate;
-- Tentative Subtraction: 4*rmd - (4*res+1)
diff <= Rmd(Rmd'left downto N-2) + ('1' & not Res(STEPS-2 downto 0) & "11");
-- Ouputs
sqrt <= std_logic_vector(Res);
rdy <= not Vld(Vld'left);
end rtl;
| apache-2.0 |
hoangt/PoC | tb/misc/stat/stat_Minimum_tb.vhdl | 2 | 6179 | -- EMACS settings: -*- tab-width:2 -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-------------------------------------------------------------------------------
-- Authors: Patrick Lehmann
--
-- Description: Testbench for stat_Minimum.
--
-------------------------------------------------------------------------------
-- Copyright 2007-2015 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use poC.utils.all;
use poC.vectors.all;
entity stat_Minimum_tb is
end entity;
architecture tb of stat_Minimum_tb is
-- component generics
constant VALUES : T_NATVEC := (
113, 106, 126, 239, 146, 72, 51, 210, 44, 56, 10, 126, 7, 7, 22, 18,
128, 217, 106, 210, 58, 71, 213, 206, 169, 213, 90, 27, 166, 159, 83, 116,
246, 208, 105, 64, 112, 12, 110, 10, 5, 100, 12, 231, 191, 235, 27, 143,
162, 178, 136, 149, 92, 221, 122, 44, 143, 169, 72, 182, 232, 26, 46, 135,
223, 144, 129, 48, 148, 208, 156, 119, 109, 98, 207, 208, 62, 232, 17, 183,
189, 197, 115, 237, 25, 183, 27, 27, 89, 64, 170, 192, 189, 177, 28, 228,
56, 127, 10, 49, 108, 229, 244, 204, 25, 20, 42, 243, 16, 163, 232, 161,
154, 139, 243, 38, 160, 59, 113, 42, 120, 104, 208, 87, 40, 213, 179, 181,
73, 228, 155, 184, 224, 218, 77, 210, 202, 161, 215, 7, 143, 34, 13, 175,
81, 12, 40, 53, 184, 240, 71, 247, 17, 218, 179, 7, 23, 159, 166, 61,
90, 111, 172, 37, 11, 50, 186, 186, 64, 36, 85, 249, 93, 108, 148, 89,
93, 35, 7, 30, 175, 129, 247, 83, 160, 157, 170, 9, 41, 73, 189, 45,
244, 157, 166, 35, 111, 226, 167, 34, 76, 104, 239, 151, 157, 71, 156, 159,
72, 93, 163, 237, 153, 139, 135, 211, 113, 92, 126, 103, 130, 180, 147, 240,
96, 42, 7, 185, 191, 115, 227, 117, 118, 224, 204, 74, 140, 98, 176, 92,
3, 13, 187, 198, 160, 201, 141, 108, 24, 205, 171, 22, 102, 66, 153, 146,
206, 248, 58, 117, 67, 220, 217, 206, 115, 48, 122, 179, 184, 63, 74, 18,
166, 37, 103, 119, 242, 198, 82, 144, 151, 149, 164, 235, 193, 207, 18, 55,
74, 61, 118, 141, 42, 61, 28, 32, 46, 230, 85, 114, 82, 212, 173, 210,
134, 156, 106, 67, 212, 36, 153, 10, 168, 164, 216, 168, 59, 231, 15, 157,
33, 69, 107, 126, 195, 182, 225, 107, 12, 73, 76, 15, 116, 218, 64, 188,
225, 203, 104, 40, 104, 200, 92, 40, 158, 110, 222, 128, 95, 110, 223, 64,
218, 178, 84, 16, 108, 50, 18, 202, 180, 249, 58, 142, 210, 141, 144, 200,
102, 30, 192, 106, 130, 224, 56, 82, 226, 69, 218, 88, 209, 100, 15, 152,
100, 14, 46, 188, 136, 51, 83, 178, 188, 152, 110, 105, 145, 199, 80, 19,
215, 25, 29, 67, 167, 119, 184, 243, 124, 5, 39, 41, 81, 179, 242, 83,
236, 155, 45, 198, 97, 206, 67, 54, 197, 17, 168, 227, 117, 200, 186, 29,
239, 201, 122, 187, 74, 197, 234, 230, 80, 53, 66, 133, 14, 44, 99, 11,
160, 29, 118, 239, 157, 131, 172, 12, 207, 224, 119, 153, 201, 206, 128, 173,
69, 12, 51, 129, 60, 57, 12, 42, 171, 64, 121, 46, 143, 184, 42, 156,
167, 160, 70, 91, 85, 196, 122, 110, 32, 113, 229, 99, 81, 84, 32, 123,
174, 142, 66, 5, 242, 220, 200, 105, 20, 79, 71, 95, 13, 128, 119, 26
);
type T_RESULT is record
Minimum : NATURAL;
Count : POSITIVE;
end record;
type T_RESULT_VECTOR is array(NATURAL range <>) of T_RESULT;
constant RESULT : T_RESULT_VECTOR := (
(Minimum => 3, Count => 1),
(Minimum => 5, Count => 3),
(Minimum => 7, Count => 6),
(Minimum => 9, Count => 1),
(Minimum => 10, Count => 4),
(Minimum => 11, Count => 2),
(Minimum => 12, Count => 7),
(Minimum => 13, Count => 3)
);
constant DEPTH : POSITIVE := RESULT'length;
constant DATA_BITS : POSITIVE := 8;
constant COUNTER_BITS : POSITIVE := 16;
-- component ports
signal Clock : STD_LOGIC := '1';
signal Reset : STD_LOGIC := '0';
signal Enable : STD_LOGIC := '0';
signal DataIn : STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
signal Valids : STD_LOGIC_VECTOR(DEPTH - 1 downto 0);
signal Minimums : T_SLM(DEPTH - 1 downto 0, DATA_BITS - 1 downto 0);
signal Counts : T_SLM(DEPTH - 1 downto 0, COUNTER_BITS - 1 downto 0);
signal Minimums_slvv : T_SLVV_8(DEPTH - 1 downto 0);
signal Counts_slvv : T_SLVV_4(DEPTH - 1 downto 0);
begin
-- component instantiation
DUT: entity PoC.stat_Minimum
generic map (
DEPTH => DEPTH,
DATA_BITS => DATA_BITS,
COUNTER_BITS => COUNTER_BITS
)
port map (
Clock => Clock,
Reset => Reset,
Enable => Enable,
DataIn => DataIn,
Valids => Valids,
Minimums => Minimums,
Counts => Counts
);
Minimums_slvv <= to_slvv_8(Minimums);
Counts_slvv <= to_slvv_4(Counts);
process
procedure cycle is
begin
Clock <= '1';
wait for 5 ns;
Clock <= '0';
wait for 5 ns;
end cycle;
variable good : BOOLEAN;
begin
cycle;
Reset <= '1';
cycle;
Reset <= '0';
cycle;
cycle;
Enable <= '1';
for i in VALUES'range loop
--Enable <= to_sl(VALUES(i) /= 35);
DataIn <= to_slv(VALUES(i), DataIn'length);
cycle;
end loop;
cycle;
-- test result after all cycles
good := (slv_and(Valids) = '1');
for i in RESULT'range loop
good := good and (RESULT(i).Minimum = unsigned(Minimums_slvv(i))) and (RESULT(i).Count = unsigned(Counts_slvv(i)));
end loop;
assert (good = TRUE)
report "Test failed."
severity note;
assert (good = FALSE)
report "Test passed."
severity note;
wait;
end process;
end;
| apache-2.0 |
hoangt/PoC | src/bus/stream/stream_DeMux.vhdl | 2 | 6302 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: A generic buffer module for the PoC.Stream protocol.
--
-- Description:
-- ------------------------------------
-- This module implements a generic buffer (FifO) for the PoC.Stream protocol.
-- It is generic in DATA_BITS and in META_BITS as well as in FifO depths for
-- data and meta information.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS of ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
entity Stream_DeMux is
generic (
portS : POSITIVE := 2;
DATA_BITS : POSITIVE := 8;
META_BITS : NATURAL := 8;
META_REV_BITS : NATURAL := 2
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- Control interface
DeMuxControl : in STD_LOGIC_VECTOR(portS - 1 downto 0);
-- IN Port
In_Valid : in STD_LOGIC;
In_Data : in STD_LOGIC_VECTOR(DATA_BITS - 1 downto 0);
In_Meta : in STD_LOGIC_VECTOR(META_BITS - 1 downto 0);
In_Meta_rev : out STD_LOGIC_VECTOR(META_REV_BITS - 1 downto 0);
In_SOF : in STD_LOGIC;
In_EOF : in STD_LOGIC;
In_Ack : out STD_LOGIC;
-- OUT Ports
Out_Valid : out STD_LOGIC_VECTOR(portS - 1 downto 0);
Out_Data : out T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0);
Out_Meta : out T_SLM(portS - 1 downto 0, META_BITS - 1 downto 0);
Out_Meta_rev : in T_SLM(portS - 1 downto 0, META_REV_BITS - 1 downto 0);
Out_SOF : out STD_LOGIC_VECTOR(portS - 1 downto 0);
Out_EOF : out STD_LOGIC_VECTOR(portS - 1 downto 0);
Out_Ack : in STD_LOGIC_VECTOR(portS - 1 downto 0)
);
end;
architecture rtl of Stream_DeMux is
attribute KEEP : BOOLEAN;
attribute FSM_ENCODING : STRING;
subtype T_CHANNEL_INDEX is NATURAL range 0 to portS - 1;
type T_STATE is (ST_IDLE, ST_DATAFLOW, ST_DISCARD_FRAME);
signal State : T_STATE := ST_IDLE;
signal NextState : T_STATE;
signal Is_SOF : STD_LOGIC;
signal Is_EOF : STD_LOGIC;
signal In_Ack_i : STD_LOGIC;
signal Out_Valid_i : STD_LOGIC;
signal DiscardFrame : STD_LOGIC;
signal ChannelPointer_rst : STD_LOGIC;
signal ChannelPointer_en : STD_LOGIC;
signal ChannelPointer : STD_LOGIC_VECTOR(portS - 1 downto 0);
signal ChannelPointer_d : STD_LOGIC_VECTOR(portS - 1 downto 0) := (others => '0');
signal ChannelPointer_bin : UNSIGNED(log2ceilnz(portS) - 1 downto 0);
signal idx : T_CHANNEL_INDEX;
signal Out_Data_i : T_SLM(portS - 1 downto 0, DATA_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave)
signal Out_Meta_i : T_SLM(portS - 1 downto 0, META_BITS - 1 downto 0) := (others => (others => 'Z')); -- necessary default assignment 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave)
begin
In_Ack_i <= slv_or(Out_Ack and ChannelPointer);
DiscardFrame <= slv_nor(DeMuxControl);
Is_SOF <= In_Valid and In_SOF;
Is_EOF <= In_Valid and In_EOF;
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
State <= ST_IDLE;
else
State <= NextState;
end if;
end if;
end process;
process(State, In_Ack_i, In_Valid, Is_SOF, Is_EOF, DiscardFrame, DeMuxControl, ChannelPointer_d)
begin
NextState <= State;
ChannelPointer_rst <= Is_EOF;
ChannelPointer_en <= '0';
ChannelPointer <= ChannelPointer_d;
In_Ack <= '0';
Out_Valid_i <= '0';
case State is
when ST_IDLE =>
ChannelPointer <= DeMuxControl;
if (Is_SOF = '1') then
if (DiscardFrame = '0') then
ChannelPointer_en <= '1';
In_Ack <= In_Ack_i;
Out_Valid_i <= '1';
NextState <= ST_DATAFLOW;
else
In_Ack <= '1';
NextState <= ST_DISCARD_FRAME;
end if;
end if;
when ST_DATAFLOW =>
In_Ack <= In_Ack_i;
Out_Valid_i <= In_Valid;
ChannelPointer <= ChannelPointer_d;
if (Is_EOF = '1') then
NextState <= ST_IDLE;
end if;
when ST_DISCARD_FRAME =>
In_Ack <= '1';
if (Is_EOF = '1') then
NextState <= ST_IDLE;
end if;
end case;
end process;
process(Clock)
begin
if rising_edge(Clock) then
if ((Reset or ChannelPointer_rst) = '1') then
ChannelPointer_d <= (others => '0');
else
if (ChannelPointer_en = '1') then
ChannelPointer_d <= DeMuxControl;
end if;
end if;
end if;
end process;
ChannelPointer_bin <= onehot2bin(ChannelPointer_d);
idx <= to_integer(ChannelPointer_bin);
In_Meta_rev <= get_row(Out_Meta_rev, idx);
genOutput : for i in 0 to portS - 1 generate
Out_Valid(i) <= Out_Valid_i and ChannelPointer(i);
assign_row(Out_Data_i, In_Data, i);
assign_row(Out_Meta_i, In_Meta, i);
Out_SOF(i) <= In_SOF;
Out_EOF(i) <= In_EOF;
end generate;
Out_Data <= Out_Data_i;
Out_Meta <= Out_Meta_i;
end architecture;
| apache-2.0 |
IAIK/ascon_hardware | caesar_hardware_api/HDL/AEAD/src_rtl_hs/AEAD.vhd | 1 | 2982 | -------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Entity of authenticated encryption unit.
--! User should modify the default generics based on the
--! design requirements of a target archtiecture of the
--! implemented cipher.
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity AEAD is
generic (
--! I/O size (bits)
G_W : integer := 32; --! Public data input
G_SW : integer := 32; --! Secret data input
--! Reset behavior
G_ASYNC_RSTN : boolean := False; --! Async active low reset
--! Special features parameters
G_ENABLE_PAD : boolean := False; --! Enable padding
G_CIPH_EXP : boolean := False; --! Ciphertext expansion
G_REVERSE_CIPH : boolean := False; --! Reversed ciphertext
G_MERGE_TAG : boolean := False; --! Merge tag with data segment
--! Block size (bits)
G_ABLK_SIZE : integer := 128; --! Associated data
G_DBLK_SIZE : integer := 128; --! Data
G_KEY_SIZE : integer := 128; --! Key
G_TAG_SIZE : integer := 128; --! Tag
--! Padding options
G_PAD_STYLE : integer := 0; --! Pad style
G_PAD_AD : integer := 1; --! Padding behavior for AD
G_PAD_D : integer := 1 --! Padding behavior for Data
);
port (
--! Global ports
clk : in std_logic;
rst : in std_logic;
--! Publica data ports
pdi_data : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Secret data ports
sdi_data : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out ports
do_data : out std_logic_vector(G_W -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD; | apache-2.0 |
hoangt/PoC | src/xil/xil_Reconfigurator.vhdl | 2 | 6716 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Reconfiguration engine for DRP enabled Xilinx primtives
--
-- Description:
-- ------------------------------------
-- Many complex primitives in a Xilinx device offer a Dynamic Reconfiguration
-- Port (DRP) to reconfigure the primitive at runtime without reconfiguring then
-- whole FPGA.
-- This module is a DRP master that can be preconfigured at compile time with
-- different configuration sets. The configuration sets are mapped into a ROM.
-- The user can select a stored configuration with 'ConfigSelect' and sending a
-- strobe to 'Reconfig'. The Operation completes with an other strobe on
-- 'ReconfigDone'.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.xil.all;
entity xil_Reconfigurator is
generic (
DEBUG : BOOLEAN := FALSE; --
CLOCK_FREQ : FREQ := 100 MHz; --
CONFIG_ROM : in T_XIL_DRP_CONFIG_ROM := (0 downto 0 => C_XIL_DRP_CONFIG_SET_EMPTY) --
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Reconfig : in STD_LOGIC; --
ReconfigDone : out STD_LOGIC; --
ConfigSelect : in STD_LOGIC_VECTOR(log2ceilnz(CONFIG_ROM'length) - 1 downto 0); --
DRP_en : out STD_LOGIC; --
DRP_Address : out T_XIL_DRP_ADDRESS; --
DRP_we : out STD_LOGIC; --
DRP_DataIn : in T_XIL_DRP_DATA; --
DRP_DataOut : out T_XIL_DRP_DATA; --
DRP_Ack : in STD_LOGIC --
);
end;
architecture rtl of xil_Reconfigurator is
attribute KEEP : BOOLEAN;
attribute FSM_ENCODING : STRING;
attribute signal_ENCODING : STRING;
type T_STATE is (
ST_IDLE,
ST_READ_BEGIN, ST_READ_WAIT,
ST_WRITE_BEGIN, ST_WRITE_WAIT,
ST_DONE
);
-- DualConfiguration - Statemachine
signal State : T_STATE := ST_IDLE;
signal NextState : T_STATE;
attribute FSM_ENCODING of State : signal is ite(DEBUG, "gray", "speed1");
signal DataBuffer_en : STD_LOGIC;
signal DataBuffer_d : T_XIL_DRP_DATA := (others => '0');
signal ROM_Entry : T_XIL_DRP_CONFIG;
signal ROM_LastConfigWord : STD_LOGIC;
constant CONFIGINDEX_BITS : POSITIVE := log2ceilnz(CONFIG_ROM'length);
signal ConfigIndex_rst : STD_LOGIC;
signal ConfigIndex_en : STD_LOGIC;
signal ConfigIndex_us : UNSIGNED(CONFIGINDEX_BITS - 1 downto 0);
attribute KEEP OF ROM_LastConfigWord : signal IS DEBUG;
begin
-- configuration ROM
blkCONFIG_ROM : block
signal SetIndex : inTEGER range 0 to CONFIG_ROM'high;
signal RowIndex : T_XIL_DRP_CONFIG_INDEX;
attribute KEEP OF SetIndex : signal IS DEBUG;
attribute KEEP OF RowIndex : signal IS DEBUG;
begin
SetIndex <= to_index(ConfigSelect, CONFIG_ROM'high);
RowIndex <= to_index(ConfigIndex_us, T_XIL_DRP_CONFIG_INDEX'high);
ROM_Entry <= CONFIG_ROM(SetIndex).Configs(RowIndex);
ROM_LastConfigWord <= to_sl(RowIndex = CONFIG_ROM(SetIndex).LastIndex);
end block;
-- configuration index counter
process(Clock)
begin
if rising_edge(Clock) then
if ((Reset or ConfigIndex_rst) = '1') then
ConfigIndex_us <= (others => '0');
else
if (ConfigIndex_en = '1') then
ConfigIndex_us <= ConfigIndex_us + 1;
end if;
end if;
end if;
end process;
-- data buffer for DRP configuration words
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
DataBuffer_d <= (others => '0');
else
if (DataBuffer_en = '1') then
DataBuffer_d <= ((DRP_DataIn and not ROM_Entry.Mask) or
(ROM_Entry.Data and ROM_Entry.Mask));
end if;
end if;
end if;
end process;
-- assign DRP signals
DRP_Address <= ROM_Entry.Address;
DRP_DataOut <= DataBuffer_d;
-- DRP read-modify-write statemachine
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
State <= ST_IDLE;
else
State <= NextState;
end if;
end if;
end process;
process(State, Reconfig, ROM_LastConfigWord, DRP_Ack )
begin
NextState <= State;
ReconfigDone <= '0';
-- Dynamic Reconfiguration Port
DRP_en <= '0';
DRP_we <= '0';
-- internal modules
ConfigIndex_rst <= '0';
ConfigIndex_en <= '0';
DataBuffer_en <= '0';
case State is
when ST_IDLE =>
if (Reconfig = '1') then
ConfigIndex_rst <= '1';
NextState <= ST_READ_BEGIN;
end if;
when ST_READ_BEGIN =>
DRP_en <= '1';
DRP_we <= '0';
NextState <= ST_READ_WAIT;
when ST_READ_WAIT =>
if (DRP_Ack = '1') then
DataBuffer_en <= '1';
NextState <= ST_WRITE_BEGIN;
end if;
when ST_WRITE_BEGIN =>
DRP_en <= '1';
DRP_we <= '1';
NextState <= ST_WRITE_WAIT;
when ST_WRITE_WAIT =>
if (DRP_Ack = '1') then
if (ROM_LastConfigWord = '1') then
NextState <= ST_DONE;
ELSE
ConfigIndex_en <= '1';
NextState <= ST_READ_BEGIN;
end if;
end if;
when ST_DONE =>
ReconfigDone <= '1';
NextState <= ST_IDLE;
end case;
end process;
end;
| apache-2.0 |
IAIK/ascon_hardware | generic_implementation/ascon_fast_bus.vhdl | 1 | 10795 | -------------------------------------------------------------------------------
-- Title : Bus logic of Ascon module
-- Project :
-------------------------------------------------------------------------------
-- File : ascon_fast_bus.vhdl
-- Author : Hannes Gross <[email protected]>
-- Company :
-- Created : 2016-05-25
-- Last update: 2016-06-14
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Copyright 2014 Graz University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-25 1.0 Hannes Gross created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ascon is
generic (
UNROLED_ROUNDS : integer := 1; --1,2,3,6
KEY_SIZE : integer := 128;
DATA_BLOCK_SIZE : integer := 64;
ROUNDS_A : integer := 12;
ROUNDS_B : integer := 6;
DATA_BUS_WIDTH : integer := 32;
ADDR_BUS_WIDTH : integer := 8);
port (
ClkxCI : in std_logic;
RstxRBI : in std_logic;
CSxSI : in std_logic; -- active-high chip select
WExSI : in std_logic; -- active-high write enable
AddressxDI : in std_logic_vector(ADDR_BUS_WIDTH-1 downto 0);
DataWritexDI : in std_logic_vector(DATA_BUS_WIDTH-1 downto 0);
DataReadxDO : out std_logic_vector(DATA_BUS_WIDTH-1 downto 0));
end entity ascon;
architecture structural of ascon is
constant CONTROL_STATE_SIZE : integer := 4;
constant STATE_WORD_SIZE : integer := 64;
constant CONST_UNROLED_R : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(UNROLED_ROUNDS, 8));
constant CONST_KEY_SIZE : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(KEY_SIZE, 8));
constant CONST_ROUNDS_A : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_A, 8));
constant CONST_ROUNDS_B : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(ROUNDS_B, 8));
signal CP_InitxSP, CP_InitxSn : std_logic;
signal CP_AssociatexSP, CP_AssociatexSN : std_logic;
signal CP_EncryptxSP, CP_EncryptxSN : std_logic;
signal CP_DecryptxSP, CP_DecryptxSN : std_logic;
signal CP_FinalEncryptxSP, CP_FinalEncryptxSN : std_logic;
signal CP_FinalDecryptxSP, CP_FinalDecryptxSN : std_logic;
signal KeyxDP, KeyxDN : std_logic_vector(KEY_SIZE-1 downto 0);
signal DP_WriteNoncexS : std_logic;
signal DP_WriteIODataxS : std_logic;
signal CP_DonexS, CP_InitxS, CP_AssociatexSI : std_logic;
signal CP_EncryptxS, CP_DecryptxS, CP_FinalEncryptxS : std_logic;
signal CP_FinalDecryptxS : std_logic;
signal IODataxD : std_logic_vector(DATA_BLOCK_SIZE-1 downto 0);
signal StatexD : std_logic_vector(5*STATE_WORD_SIZE-1 downto 0);
alias State0xD : std_logic_vector(STATE_WORD_SIZE-1 downto 0) is StatexD(64*1 -1 downto 64*0);
alias State1xD : std_logic_vector(STATE_WORD_SIZE-1 downto 0) is StatexD(64*2 -1 downto 64*1);
alias State2xD : std_logic_vector(STATE_WORD_SIZE-1 downto 0) is StatexD(64*3 -1 downto 64*2);
alias State3xD : std_logic_vector(STATE_WORD_SIZE-1 downto 0) is StatexD(64*4 -1 downto 64*3);
alias State4xD : std_logic_vector(STATE_WORD_SIZE-1 downto 0) is StatexD(64*5 -1 downto 64*4);
function ZEROS (
constant WIDTH : natural)
return std_logic_vector is
variable x : std_logic_vector(WIDTH-1 downto 0);
begin -- ZEROS
x := (others => '0');
return x;
end ZEROS;
function ROTATE_STATE_WORD (
word : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
constant rotate : integer)
return std_logic_vector is
variable x : std_logic_vector(STATE_WORD_SIZE-1 downto 0);
begin -- ROTATE_STATE_WORD
x := word(ROTATE-1 downto 0) & word(STATE_WORD_SIZE-1 downto ROTATE);
return x;
end ROTATE_STATE_WORD;
begin -- architecture structural
-- purpose: Defines all registers
-- type : sequential
-- inputs : ClkxCI, RstxRBI, *xDN signals
-- outputs: *xDP signals
RegisterProc : process (ClkxCI, RstxRBI) is
begin -- process RegisterProc
if RstxRBI = '0' then -- asynchronous reset (active low)
KeyxDP <= (others => '0');
CP_InitxSP <= '0';
CP_AssociatexSP <= '0';
CP_EncryptxSP <= '0';
CP_DecryptxSP <= '0';
CP_FinalEncryptxSP <= '0';
CP_FinalDecryptxSP <= '0';
elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
KeyxDP <= KeyxDN;
CP_InitxSP <= CP_InitxSN;
CP_AssociatexSP <= CP_AssociatexSN;
CP_EncryptxSP <= CP_EncryptxSN;
CP_DecryptxSP <= CP_DecryptxSN;
CP_FinalEncryptxSP <= CP_FinalEncryptxSN;
CP_FinalDecryptxSP <= CP_FinalDecryptxSN;
end if;
end process RegisterProc;
-- purpose: Glue the internal registers with the bus
-- type : combinational
DataBusLogicProc : process (AddressxDI, CP_AssociatexSP,
CP_DecryptxSP, CP_DonexS, CP_EncryptxSP,
CP_FinalDecryptxSP, CP_FinalEncryptxSP,
CP_InitxSP, CSxSI, DataWritexDI, DataWritexDI(0),
DataWritexDI, IODataxD, KeyxDP,
State3xD,
State4xD,
WExSI) is
variable AddressxDV : integer;
variable index : integer;
begin -- process DataBusLogicProc
KeyxDN <= KeyxDP;
AddressxDV := to_integer(unsigned(AddressxDI));
index := 0;
DataReadxDO <= (others => '0');
DP_WriteNoncexS <= '0';
DP_WriteIODataxS <= '0';
CP_InitxSN <= CP_InitxSP;
CP_AssociatexSN <= CP_AssociatexSP;
CP_EncryptxSN <= CP_EncryptxSP;
CP_DecryptxSN <= CP_DecryptxSP;
CP_FinalEncryptxSN <= CP_FinalEncryptxSP;
CP_FinalDecryptxSN <= CP_FinalDecryptxSP;
if CP_DonexS = '1' then
CP_InitxSN <= '0';
CP_AssociatexSN <= '0';
CP_EncryptxSN <= '0';
CP_DecryptxSN <= '0';
CP_FinalEncryptxSN <= '0';
CP_FinalDecryptxSN <= '0';
end if;
if CSxSI = '1' then
if WExSI = '1' then
-- synchronous write
if AddressxDV = 2 then
-- command register
CP_InitxSN <= DataWritexDI(0);
CP_AssociatexSN <= DataWritexDI(1);
CP_EncryptxSN <= DataWritexDI(2);
CP_DecryptxSN <= DataWritexDI(3);
CP_FinalEncryptxSN <= DataWritexDI(4);
CP_FinalDecryptxSN <= DataWritexDI(5);
elsif (AddressxDV >= 4) and (AddressxDV < 8) then
-- write the key
index := to_integer(unsigned(AddressxDI(1 downto 0)));
KeyxDN((index+1)*DATA_BUS_WIDTH-1 downto index*DATA_BUS_WIDTH) <= DataWritexDI;
elsif (AddressxDV >= 8) and (AddressxDV < 12) then
-- write the nonce
DP_WriteNoncexS <= '1';
--elsif (AddressxDV >= 12) and (AddressxDV < 14) then
-- -- write the data to de/encrypt and associated data
-- DP_WriteIODataxS <= '1';
end if;
else
-- asynchronous read
if AddressxDV = 0 then
DataReadxDO <= x"deadbeef";
elsif AddressxDV = 1 then
-- status register
-- returns 1 if busy
DataReadxDO(0) <= CP_InitxSP or CP_AssociatexSP or CP_EncryptxSP or CP_DecryptxSP or CP_FinalEncryptxSP or CP_FinalDecryptxSP;
elsif (AddressxDV >= 12) and (AddressxDV < 14) then
-- read the de/encrypted data and associated data
index := to_integer(unsigned(AddressxDI(0 downto 0)));
DataReadxDO <= IODataxD((index+1)*DATA_BUS_WIDTH-1 downto index*DATA_BUS_WIDTH);
elsif (AddressxDV >= 16) and (AddressxDV < 20) then
-- read the tag
if DATA_BUS_WIDTH = 64 then
if AddressxDI(1 downto 0) = "00" then
DataReadxDO <= State4xD;
elsif AddressxDI(1 downto 0) = "01" then
DataReadxDO <= State3xD;
end if;
else -- 128 bit variant
DataReadxDO <= State3xD & State4xD;
end if;
end if;
end if;
end if;
end process DataBusLogicProc;
ascon_core_1: entity work.ascon_core
generic map (
UNROLED_ROUNDS => UNROLED_ROUNDS,
KEY_SIZE => KEY_SIZE,
DATA_BLOCK_SIZE => DATA_BLOCK_SIZE,
ROUNDS_A => ROUNDS_A,
ROUNDS_B => ROUNDS_B,
DATA_BUS_WIDTH => DATA_BUS_WIDTH,
ADDR_BUS_WIDTH => ADDR_BUS_WIDTH)
port map (
ClkxCI => ClkxCI,
RstxRBI => RstxRBI,
AddressxDI => AddressxDI,
DP_WriteNoncexSI => DP_WriteNoncexS,
DataWritexDI => DataWritexDI,
KeyxDI => KeyxDP,
DP_WriteIODataxSI => DP_WriteIODataxS,
IODataxDO => IODataxD,
CP_DonexSO => CP_DonexS,
CP_InitxSI => CP_InitxSP,
CP_AssociatexSI => CP_AssociatexSP,
CP_EncryptxSI => CP_EncryptxSP,
CP_DecryptxSI => CP_DecryptxSP,
CP_FinalEncryptxSI => CP_FinalEncryptxSP,
CP_FinalDecryptxSI => CP_FinalDecryptxSP,
StatexDO => StatexD);
end architecture structural;
| apache-2.0 |
Paebbels/PicoBlaze-Library | vhdl/Device/pb_Scaler_Device.vhdl | 1 | 7455 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Scaler (8/16/24/32/40 bit) Device for PicoBlaze
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity pb_Scaler_Device is
generic (
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE;
BITS : POSITIVE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- PicoBlaze interface
Address : in T_SLV_8;
WriteStrobe : in STD_LOGIC;
WriteStrobe_K : in STD_LOGIC;
ReadStrobe : in STD_LOGIC;
DataIn : in T_SLV_8;
DataOut : out T_SLV_8;
Interrupt : out STD_LOGIC;
Interrupt_Ack : in STD_LOGIC;
Message : out T_SLV_8
);
end entity;
architecture rtl of pb_Scaler_Device is
constant REG_RW_A0 : STD_LOGIC_VECTOR(2 downto 0) := "000";
constant REG_RW_A1 : STD_LOGIC_VECTOR(2 downto 0) := "001";
constant REG_RW_A2 : STD_LOGIC_VECTOR(2 downto 0) := "010";
constant REG_RW_A3 : STD_LOGIC_VECTOR(2 downto 0) := "011";
constant REG_RW_A4 : STD_LOGIC_VECTOR(2 downto 0) := "100";
constant REG_WO_MULT : STD_LOGIC_VECTOR(2 downto 0) := "101";
constant REG_WO_DIV : STD_LOGIC_VECTOR(2 downto 0) := "110";
constant REG_RO_STATUS : STD_LOGIC_VECTOR(2 downto 0) := "111";
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
constant BYTES : POSITIVE := div_ceil(BITS, 8);
constant BITS_A : NATURAL := log2ceil(BYTES);
signal Reg_Scaler : STD_LOGIC_VECTOR(BITS - 1 downto 0) := x"0000000000";
signal Reg_Mult : T_SLV_8 := x"00";
signal Reg_Div : T_SLV_8 := x"00";
function getVALUES return T_POSVEC is
variable Result : T_POSVEC(0 to 255);
begin
Result(0) := 1;
for i in 1 to Result'high loop
Result(I) := I;
end loop;
return Result;
end function;
constant MULTS : T_POSVEC := getVALUES;
constant DIVS : T_POSVEC := getVALUES;
signal MultDiv_Start : STD_LOGIC;
signal MultDiv_Start_d : STD_LOGIC := '0';
signal MultDiv_Done : STD_LOGIC;
signal MultDiv_Done_d : STD_LOGIC := '0';
signal MultDiv_Done_re : STD_LOGIC;
signal MultDiv_Result : STD_LOGIC_VECTOR(BITS - 1 downto 0);
begin
assert (BITS = 40)
-- assert ((BITS = 8) or (BITS = 16) or (BITS = 24) or (BITS = 32) or (BITS = 40))
report "Multiplier size is not supported. Supported sizes: 8, 16, 24, 32, 40. BITS=" & INTEGER'image(BITS)
severity failure;
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset,
-- PicoBlaze interface
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Address => Address,
In_Data => DataIn,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_Data => AdrDec_Data
);
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Reg_Scaler <= (others => '0');
Reg_Mult <= (others => '0');
Reg_Div <= (others => '0');
else
if (AdrDec_we = '1') then
case AdrDec_WriteAddress(2 downto 0) IS
when REG_WO_MULT => Reg_Mult <= AdrDec_Data;
when REG_WO_DIV => Reg_Div <= AdrDec_Data;
when REG_RW_A0 => Reg_Scaler(7 downto 0) <= AdrDec_Data;
when REG_RW_A1 => Reg_Scaler(15 downto 8) <= AdrDec_Data;
when REG_RW_A2 => Reg_Scaler(23 downto 16) <= AdrDec_Data;
when REG_RW_A3 => Reg_Scaler(31 downto 24) <= AdrDec_Data;
when REG_RW_A4 => Reg_Scaler(39 downto 32) <= AdrDec_Data;
when others => null;
end case;
elsif (MultDiv_Done_re = '1') then
Reg_Scaler <= MultDiv_Result;
end if;
end if;
end if;
end process;
MultDiv_Start <= AdrDec_we and to_sl(AdrDec_WriteAddress(2 downto 0) = REG_WO_DIV);
MultDiv_Start_d <= MultDiv_Start when rising_edge(Clock);
MultDiv_Done_d <= MultDiv_Done when rising_edge(Clock);
MultDiv_Done_re <= not MultDiv_Done_d and MultDiv_Done;
MultDiv : entity PoC.arith_scaler
generic map (
MULS => MULTS, -- The set of multipliers to choose from in scaling operations.
DIVS => DIVS -- The set of divisors to choose from in scaling operations.
)
port map (
clk => Clock,
rst => Reset,
start => MultDiv_Start_d,
arg => Reg_Scaler,
msel => Reg_Mult,
dsel => Reg_Div,
done => MultDiv_Done,
res => MultDiv_Result
);
process(AdrDec_re, AdrDec_ReadAddress, Reg_Scaler, MultDiv_Done_d)
variable Reg_Scaler_slvv : T_SLVV_8(4 downto 0);
begin
Reg_Scaler_slvv := to_slvv_8(Reg_Scaler);
DataOut <= Reg_Scaler_slvv(to_index(AdrDec_ReadAddress(2 downto 0), Reg_Scaler_slvv'length - 1));
if (AdrDec_ReadAddress(2 downto 0) = REG_RO_STATUS) then
DataOut <= "0000000" & MultDiv_Done_d;
end if;
end process;
Interrupt <= MultDiv_Done_re;
Message <= x"00";
end;
| apache-2.0 |
project-oak/silveroak | investigations/tutorials/and2/and2.vhdl | 1 | 1057 | --
-- Copyright 2019 The Project Oak Authors
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
package and2_package is
component and2 is
port(signal a : in bit;
signal b : bit;
signal c : out bit);
end component and2;
end package and2_package;
entity and2 is
port(signal a : in bit;
signal b : bit;
signal c : out bit);
end entity and2;
architecture behavioural of and2 is
begin
and2_behaviour : process (a, b) is
begin
c <= a and b;
end process and2_behaviour;
end architecture behavioural; | apache-2.0 |
nsensfel/tabellion | data/test/combinational_processes/valid_unsupported.vhd | 1 | 1492 | library IEEE;
use IEEE.std_logic_1164.all;
entity valid is
port
(
ip0, ip1, ip2, ip3: in std_logic;
op0, op1, op2, op3: out std_logic
);
end;
architecture RTL of valid is
signal s0, s1, s2, s3 : std_logic;
begin
-- Add some vectors.
-- Add some enums.
s0 <= s1;
s0 <= (s1 and s2);
process (s0, s1)
begin
case s1 is
when '0' =>
op0 <= s0;
when others =>
op0 <= s1;
end case;
end process;
process (s0, s1)
begin
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
end case;
end process;
process (s0, s1)
begin
op2 <= '0';
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
op2 <= '1';
end case;
end process;
process (s0, s1, s2)
begin
op2 <= '0';
case s1 is
when '0' =>
if (s2 = '0')
then
op0 <= s0;
else
op0 <= s1;
end if;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
op2 <= '1';
end case;
end process;
with ip0 select
s1 <=
ip1 when '0',
ip2 when '1',
ip3 when others;
end;
| apache-2.0 |
Paebbels/PicoBlaze-Library | vhdl/pb_Devices.pkg.vhdl | 1 | 34368 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and
-- functions associated to the L_PicoBlaze namespace
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
use STD.TextIO.all;
library IEEE;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_TEXTIO.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
package pb_Devices is
-- ===========================================================================
-- PicoBlaze bus descriptions
-- ===========================================================================
constant C_PB_BUSSES : T_PB_BUS_VECTOR := (
0 => pb_CreateBus("Any", "Any", ""),
1 => pb_CreateBus("Intern", "Intern", "Any"),
2 => pb_CreateBus("Extern", "Extern", "Any")
);
-- ===========================================================================
-- PicoBlaze device descriptions
-- ===========================================================================
constant PB_DEV_RESET : T_PB_DEVICE;
constant PB_DEV_ROM : T_PB_DEVICE;
constant PB_DEV_INTERRUPT : T_PB_DEVICE;
constant PB_DEV_INTERRUPT8 : T_PB_DEVICE;
constant PB_DEV_INTERRUPT16 : T_PB_DEVICE;
constant PB_DEV_TIMER : T_PB_DEVICE;
constant PB_DEV_MULTIPLIER : T_PB_DEVICE;
constant PB_DEV_MULTIPLIER8 : T_PB_DEVICE;
constant PB_DEV_MULTIPLIER16 : T_PB_DEVICE;
constant PB_DEV_MULTIPLIER24 : T_PB_DEVICE;
constant PB_DEV_MULTIPLIER32 : T_PB_DEVICE;
constant PB_DEV_ACCUMULATOR16 : T_PB_DEVICE;
constant PB_DEV_DIVIDER : T_PB_DEVICE;
constant PB_DEV_DIVIDER8 : T_PB_DEVICE;
constant PB_DEV_DIVIDER16 : T_PB_DEVICE;
constant PB_DEV_DIVIDER24 : T_PB_DEVICE;
constant PB_DEV_DIVIDER32 : T_PB_DEVICE;
-- constant PB_DEV_SCALER16 : T_PB_DEVICE;
-- constant PB_DEV_SCALER32 : T_PB_DEVICE;
constant PB_DEV_SCALER40 : T_PB_DEVICE;
constant PB_DEV_CONVERTER_BCD : T_PB_DEVICE;
constant PB_DEV_CONVERTER_BCD24 : T_PB_DEVICE;
constant PB_DEV_GPIO : T_PB_DEVICE;
constant PB_DEV_BIT_BANGING_IO : T_PB_DEVICE;
constant PB_DEV_BIT_BANGING_IO8 : T_PB_DEVICE;
constant PB_DEV_BIT_BANGING_IO16 : T_PB_DEVICE;
constant PB_DEV_LCDISPLAY : T_PB_DEVICE;
constant PB_DEV_UART : T_PB_DEVICE;
-- constant PB_DEV_UARTSTREAM : T_PB_DEVICE;
constant PB_DEV_IICCONTROLLER : T_PB_DEVICE;
-- constant PB_DEV_MDIOCONTROLLER : T_PB_DEVICE;
constant PB_DEV_DRP : T_PB_DEVICE;
constant PB_DEV_FREQM : T_PB_DEVICE;
constant PB_DEV_BCDCOUNTER : T_PB_DEVICE;
end package;
package body pb_Devices is
-- ===========================================================================
-- PicoBlaze device descriptions
-- ===========================================================================
-- Reset Circuit
-- ---------------------------------------------------------------------------
constant PB_DEV_RESET_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
0 => pb_CreateRegisterField("Reset", "Reset", 8)
);
constant PB_DEV_RESET : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Reset Circuit",
DeviceShort => "Reset",
Registers => (
pb_CreateRegisterWK("Reset", 0, PB_DEV_RESET_FIELDS, "Reset", 0)),
RegisterFields => PB_DEV_RESET_FIELDS
);
-- Instruction ROM
-- ---------------------------------------------------------------------------
constant PB_DEV_ROM_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
0 => pb_CreateRegisterField("PageNumber", "PageNumber", 3)
);
constant PB_DEV_ROM : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Instruction ROM",
DeviceShort => "InstROM",
Registers => (
pb_CreateRegisterRWK("PageNumber", 0, PB_DEV_ROM_FIELDS, "PageNumber", 5)),
RegisterFields => PB_DEV_ROM_FIELDS
);
-- InterruptController
-- ---------------------------------------------------------------------------
constant PB_DEV_INTERRUPT8_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Interrupt Enable", "IntEnable", 8) &
pb_CreateWriteOnlyField("Interrupt Disable", "IntDisable", 8) &
pb_CreateReadOnlyField("Interrupt Enable Mask", "IntMask", 8) &
pb_CreateReadOnlyField("Interrupt Source", "IntSource", 8)
);
constant PB_DEV_INTERRUPT16_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Interrupt Enable", "IntEnable", 16) &
pb_CreateWriteOnlyField("Interrupt Disable", "IntDisable", 16) &
pb_CreateReadOnlyField("Interrupt Enable Mask", "IntMask", 16) &
pb_CreateReadOnlyField("Interrupt Source", "IntSource", 8)
);
constant PB_DEV_INTERRUPT8 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Interrupt Controller (8 ports)",
DeviceShort => "IntC8",
Registers => (
pb_CreateRegisterWK("IntEnable0", 0, PB_DEV_INTERRUPT8_FIELDS, "IntEnable", 0) &
pb_CreateRegisterWK("IntDisable0", 1, PB_DEV_INTERRUPT8_FIELDS, "IntDisable", 0) &
pb_CreateRegisterRO("IntMask0", 0, PB_DEV_INTERRUPT8_FIELDS, "IntMask", 0) &
pb_CreateRegisterRO("IntSource", 1, PB_DEV_INTERRUPT8_FIELDS, "IntSource", 0)),
RegisterFields => PB_DEV_INTERRUPT8_FIELDS
);
constant PB_DEV_INTERRUPT16 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Interrupt Controller (16 ports)",
DeviceShort => "IntC16",
Registers => (
pb_CreateRegisterWK("IntEnable0", 0, PB_DEV_INTERRUPT16_FIELDS, "IntEnable", 0) &
pb_CreateRegisterWK("IntEnable1", 1, PB_DEV_INTERRUPT16_FIELDS, "IntEnable", 8) &
pb_CreateRegisterWK("IntDisable0", 2, PB_DEV_INTERRUPT16_FIELDS, "IntDisable", 0) &
pb_CreateRegisterWK("IntDisable1", 3, PB_DEV_INTERRUPT16_FIELDS, "IntDisable", 8) &
pb_CreateRegisterRO("IntMask0", 0, PB_DEV_INTERRUPT16_FIELDS, "IntMask", 0) &
pb_CreateRegisterRO("IntMask1", 1, PB_DEV_INTERRUPT16_FIELDS, "IntMask", 8) &
pb_CreateRegisterRO("IntSource", 2, PB_DEV_INTERRUPT16_FIELDS, "IntSource", 0)),
RegisterFields => PB_DEV_INTERRUPT16_FIELDS
);
-- Timer
-- ---------------------------------------------------------------------------
constant PB_DEV_TIMER_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Control", "Control", 8) &
pb_CreateWriteOnlyField("Max Value", "MaxValue", 16) &
pb_CreateReadOnlyField("Current Value", "CurValue", 16)
);
constant PB_DEV_TIMER : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Timer",
DeviceShort => "Timer",
Registers => (
pb_CreateRegisterWK("Control", 0, PB_DEV_TIMER_FIELDS, "Control", 0) &
pb_CreateRegisterWO("MaxValue0", 2, PB_DEV_TIMER_FIELDS, "MaxValue", 0) &
pb_CreateRegisterWO("MaxValue1", 3, PB_DEV_TIMER_FIELDS, "MaxValue", 8) &
pb_CreateRegisterRO("CurValue0", 2, PB_DEV_TIMER_FIELDS, "CurValue", 0) &
pb_CreateRegisterRO("CurValue1", 3, PB_DEV_TIMER_FIELDS, "CurValue", 8)),
RegisterFields => PB_DEV_TIMER_FIELDS,
CreatesInterrupt => TRUE
);
-- Multiplier (8/16/24/32 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_MULTIPLIER8_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 8) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 8) &
pb_CreateReadOnlyField("Result R", "Result", 16)
);
constant PB_DEV_MULTIPLIER16_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 16) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 16) &
pb_CreateReadOnlyField("Result R", "Result", 32)
);
constant PB_DEV_MULTIPLIER24_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 24) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 24) &
pb_CreateReadOnlyField("Result R", "Result", 48)
);
constant PB_DEV_MULTIPLIER32_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 32) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 32) &
pb_CreateReadOnlyField("Result R", "Result", 64)
);
constant PB_DEV_MULTIPLIER8 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Multiplier (8 bit)",
DeviceShort => "Mult8",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_MULTIPLIER8_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandB0", 2, PB_DEV_MULTIPLIER8_FIELDS, "OperandB", 0) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_MULTIPLIER8_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_MULTIPLIER8_FIELDS, "Result", 8)),
RegisterFields => PB_DEV_MULTIPLIER8_FIELDS
);
constant PB_DEV_MULTIPLIER16 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Multiplier (16 bit)",
DeviceShort => "Mult16",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_MULTIPLIER16_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_MULTIPLIER16_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandB0", 2, PB_DEV_MULTIPLIER16_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 3, PB_DEV_MULTIPLIER16_FIELDS, "OperandB", 8) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_MULTIPLIER16_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_MULTIPLIER16_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_MULTIPLIER16_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Result3", 3, PB_DEV_MULTIPLIER16_FIELDS, "Result", 24)),
RegisterFields => PB_DEV_MULTIPLIER16_FIELDS
);
constant PB_DEV_MULTIPLIER24 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Multiplier (24 bit)",
DeviceShort => "Mult24",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_MULTIPLIER24_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_MULTIPLIER24_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_MULTIPLIER24_FIELDS, "OperandA", 16) &
pb_CreateRegisterWO("OperandB0", 3, PB_DEV_MULTIPLIER24_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 4, PB_DEV_MULTIPLIER24_FIELDS, "OperandB", 8) &
pb_CreateRegisterWO("OperandB2", 5, PB_DEV_MULTIPLIER24_FIELDS, "OperandB", 16) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_MULTIPLIER24_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_MULTIPLIER24_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_MULTIPLIER24_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Result3", 3, PB_DEV_MULTIPLIER24_FIELDS, "Result", 24) &
pb_CreateRegisterRO("Result4", 4, PB_DEV_MULTIPLIER24_FIELDS, "Result", 32) &
pb_CreateRegisterRO("Result5", 5, PB_DEV_MULTIPLIER24_FIELDS, "Result", 40)),
RegisterFields => PB_DEV_MULTIPLIER24_FIELDS
);
constant PB_DEV_MULTIPLIER32 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Multiplier (32 bit)",
DeviceShort => "Mult32",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_MULTIPLIER32_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_MULTIPLIER32_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_MULTIPLIER32_FIELDS, "OperandA", 16) &
pb_CreateRegisterWO("OperandA3", 3, PB_DEV_MULTIPLIER32_FIELDS, "OperandA", 24) &
pb_CreateRegisterWO("OperandB0", 4, PB_DEV_MULTIPLIER32_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 5, PB_DEV_MULTIPLIER32_FIELDS, "OperandB", 8) &
pb_CreateRegisterWO("OperandB2", 6, PB_DEV_MULTIPLIER32_FIELDS, "OperandB", 16) &
pb_CreateRegisterWO("OperandB3", 7, PB_DEV_MULTIPLIER32_FIELDS, "OperandB", 24) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_MULTIPLIER32_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_MULTIPLIER32_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_MULTIPLIER32_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Result3", 3, PB_DEV_MULTIPLIER32_FIELDS, "Result", 24) &
pb_CreateRegisterRO("Result4", 4, PB_DEV_MULTIPLIER32_FIELDS, "Result", 32) &
pb_CreateRegisterRO("Result5", 5, PB_DEV_MULTIPLIER32_FIELDS, "Result", 40) &
pb_CreateRegisterRO("Result6", 6, PB_DEV_MULTIPLIER32_FIELDS, "Result", 48) &
pb_CreateRegisterRO("Result7", 7, PB_DEV_MULTIPLIER32_FIELDS, "Result", 56)),
RegisterFields => PB_DEV_MULTIPLIER32_FIELDS
);
-- Accumulator (16 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_ACCUMULATOR16_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operation", "Operation", 8) &
pb_CreateWriteOnlyField("Operand A", "OperandA", 16) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 16) &
pb_CreateWriteOnlyField("Operand C", "OperandC", 16) &
pb_CreateReadOnlyField("Result R", "Result", 16)
);
constant PB_DEV_ACCUMULATOR16 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Accumulator (16 bit)",
DeviceShort => "Accu16",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_ACCUMULATOR16_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_ACCUMULATOR16_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandB0", 2, PB_DEV_ACCUMULATOR16_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 3, PB_DEV_ACCUMULATOR16_FIELDS, "OperandB", 8) &
pb_CreateRegisterWO("OperandC0", 2, PB_DEV_ACCUMULATOR16_FIELDS, "OperandC", 0) &
pb_CreateRegisterWO("OperandC1", 3, PB_DEV_ACCUMULATOR16_FIELDS, "OperandC", 8) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_ACCUMULATOR16_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_ACCUMULATOR16_FIELDS, "Result", 8)),
RegisterFields => PB_DEV_ACCUMULATOR16_FIELDS
);
-- Divider (8/16/24/32 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_DIVIDER8_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 8) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 8) &
pb_CreateReadOnlyField("Result R", "Result", 8) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_DIVIDER16_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 16) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 16) &
pb_CreateReadOnlyField("Result R", "Result", 16) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_DIVIDER24_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 24) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 24) &
pb_CreateReadOnlyField("Result R", "Result", 24) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_DIVIDER32_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 32) &
pb_CreateWriteOnlyField("Operand B", "OperandB", 32) &
pb_CreateReadOnlyField("Result R", "Result", 32) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_DIVIDER8 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Divider (8 bit)",
DeviceShort => "Div8",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_DIVIDER8_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandB0", 2, PB_DEV_DIVIDER8_FIELDS, "OperandB", 0) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_DIVIDER8_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Status", 3, PB_DEV_DIVIDER8_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_DIVIDER8_FIELDS,
CreatesInterrupt => TRUE
);
constant PB_DEV_DIVIDER16 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Divider (16 bit)",
DeviceShort => "Div16",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_DIVIDER16_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_DIVIDER16_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandB0", 2, PB_DEV_DIVIDER16_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 3, PB_DEV_DIVIDER16_FIELDS, "OperandB", 8) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_DIVIDER16_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_DIVIDER16_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Status", 3, PB_DEV_DIVIDER16_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_DIVIDER16_FIELDS,
CreatesInterrupt => TRUE
);
constant PB_DEV_DIVIDER24 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Divider (24 bit)",
DeviceShort => "Div24",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_DIVIDER24_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_DIVIDER24_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_DIVIDER24_FIELDS, "OperandA", 16) &
pb_CreateRegisterWO("OperandB0", 3, PB_DEV_DIVIDER24_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 4, PB_DEV_DIVIDER24_FIELDS, "OperandB", 8) &
pb_CreateRegisterWO("OperandB2", 5, PB_DEV_DIVIDER24_FIELDS, "OperandB", 16) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_DIVIDER24_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_DIVIDER24_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_DIVIDER24_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Status", 5, PB_DEV_DIVIDER24_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_DIVIDER24_FIELDS,
CreatesInterrupt => TRUE
);
constant PB_DEV_DIVIDER32 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Divider (32 bit)",
DeviceShort => "Div32",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_DIVIDER32_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_DIVIDER32_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_DIVIDER32_FIELDS, "OperandA", 16) &
pb_CreateRegisterWO("OperandA3", 3, PB_DEV_DIVIDER32_FIELDS, "OperandA", 24) &
pb_CreateRegisterWO("OperandB0", 4, PB_DEV_DIVIDER32_FIELDS, "OperandB", 0) &
pb_CreateRegisterWO("OperandB1", 5, PB_DEV_DIVIDER32_FIELDS, "OperandB", 8) &
pb_CreateRegisterWO("OperandB2", 6, PB_DEV_DIVIDER32_FIELDS, "OperandB", 16) &
pb_CreateRegisterWO("OperandB3", 7, PB_DEV_DIVIDER32_FIELDS, "OperandB", 24) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_DIVIDER32_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_DIVIDER32_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_DIVIDER32_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Result3", 3, PB_DEV_DIVIDER32_FIELDS, "Result", 24) &
pb_CreateRegisterRO("Status", 7, PB_DEV_DIVIDER32_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_DIVIDER32_FIELDS,
CreatesInterrupt => TRUE
);
-- Scaler (40 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_SCALER40_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand A", "OperandA", 40) &
pb_CreateWriteOnlyField("Multiplicator", "Mult", 8) &
pb_CreateWriteOnlyField("Divisor", "Div", 8) &
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Result R", "Result", 40) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_SCALER40 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Scaler (40 bit)",
DeviceShort => "Scaler40",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_SCALER40_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_SCALER40_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_SCALER40_FIELDS, "OperandA", 16) &
pb_CreateRegisterWO("OperandA3", 3, PB_DEV_SCALER40_FIELDS, "OperandA", 24) &
pb_CreateRegisterWO("OperandA4", 4, PB_DEV_SCALER40_FIELDS, "OperandA", 32) &
pb_CreateRegisterWO("Mult", 5, PB_DEV_SCALER40_FIELDS, "Mult", 0) &
pb_CreateRegisterWO("Div", 6, PB_DEV_SCALER40_FIELDS, "Div", 0) &
pb_CreateRegisterWO("Command", 7, PB_DEV_SCALER40_FIELDS, "Command", 0) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_SCALER40_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_SCALER40_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_SCALER40_FIELDS, "Result", 16) &
pb_CreateRegisterRO("Result3", 3, PB_DEV_SCALER40_FIELDS, "Result", 24) &
pb_CreateRegisterRO("Result4", 4, PB_DEV_SCALER40_FIELDS, "Result", 32) &
pb_CreateRegisterRO("Status", 7, PB_DEV_SCALER40_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_SCALER40_FIELDS,
CreatesInterrupt => TRUE
);
-- Converter Bin2BCD (24 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_CONVERTER_BCD24_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Operand", "OperandA", 24) &
pb_CreateReadOnlyField("Result", "Result", 28) &
pb_CreateReadOnlyField("Status", "Status", 4)
);
constant PB_DEV_CONVERTER_BCD24 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Converter Bin2BCD (24 bit)",
DeviceShort => "ConvBCD24",
Registers => (
pb_CreateRegisterWO("OperandA0", 0, PB_DEV_CONVERTER_BCD24_FIELDS, "OperandA", 0) &
pb_CreateRegisterWO("OperandA1", 1, PB_DEV_CONVERTER_BCD24_FIELDS, "OperandA", 8) &
pb_CreateRegisterWO("OperandA2", 2, PB_DEV_CONVERTER_BCD24_FIELDS, "OperandA", 16) &
pb_CreateRegisterRO("Result0", 0, PB_DEV_CONVERTER_BCD24_FIELDS, "Result", 0) &
pb_CreateRegisterRO("Result1", 1, PB_DEV_CONVERTER_BCD24_FIELDS, "Result", 8) &
pb_CreateRegisterRO("Result2", 2, PB_DEV_CONVERTER_BCD24_FIELDS, "Result", 16) &
-- pb_CreateRegisterRO("Result3", 3, PB_DEV_CONVERTER_BCD24_FIELDS, "Result", 24) &
pb_CreateRegisterRO("Status", 3, PB_DEV_CONVERTER_BCD24_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_CONVERTER_BCD24_FIELDS,
CreatesInterrupt => TRUE
);
-- General Purpose I/O
-- ---------------------------------------------------------------------------
constant PB_DEV_GPIO_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateRegisterField("GPIO DataOut", "DataOut", 8) &
pb_CreateReadOnlyField("GPIO DataIn", "DataIn", 8) &
pb_CreateWriteOnlyField("Interrupt Enable", "IntEnable", 8)
);
constant PB_DEV_GPIO : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "General Purpose I/O",
DeviceShort => "GPIO",
Registers => (
pb_CreateRegisterRWK("DataOut", 0, PB_DEV_GPIO_FIELDS, "DataOut", 0) &
pb_CreateRegisterRO("DataIn", 1, PB_DEV_GPIO_FIELDS, "DataIn", 0) &
pb_CreateRegisterWO("IntEnable", 1, PB_DEV_GPIO_FIELDS, "IntEnable", 0)),
RegisterFields => PB_DEV_GPIO_FIELDS,
CreatesInterrupt => TRUE
);
-- Bit Banging I/O (8 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_BIT_BANGING_IO8_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("BBIO Set", "Set", 8) &
pb_CreateWriteOnlyField("BBIO Clear", "Clear", 8) &
pb_CreateReadOnlyField("BBIO DataOut", "DataOut", 8) &
pb_CreateReadOnlyField("BBIO DataIn", "DataIn", 8)
);
constant PB_DEV_BIT_BANGING_IO8 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Bit Banging I/O",
DeviceShort => "BBIO8",
Registers => (
pb_CreateRegisterWK("Set", 0, PB_DEV_BIT_BANGING_IO8_FIELDS, "Set", 0) &
pb_CreateRegisterWK("Clear", 1, PB_DEV_BIT_BANGING_IO8_FIELDS, "Clear", 0) &
pb_CreateRegisterRO("DataOut", 0, PB_DEV_BIT_BANGING_IO8_FIELDS, "DataOut", 0) &
pb_CreateRegisterRO("DataIn", 1, PB_DEV_BIT_BANGING_IO8_FIELDS, "DataIn", 0)),
RegisterFields => PB_DEV_BIT_BANGING_IO8_FIELDS
);
-- Bit Banging I/O (16 bit)
-- ---------------------------------------------------------------------------
constant PB_DEV_BIT_BANGING_IO16_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("BBIO Set", "Set", 16) &
pb_CreateWriteOnlyField("BBIO Clear", "Clear", 16) &
pb_CreateReadOnlyField("BBIO DataOut", "DataOut", 16) &
pb_CreateReadOnlyField("BBIO DataIn", "DataIn", 16)
);
constant PB_DEV_BIT_BANGING_IO16 : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "Bit Banging I/O",
DeviceShort => "BBIO16",
Registers => (
pb_CreateRegisterWK("Set0", 0, PB_DEV_BIT_BANGING_IO16_FIELDS, "Set", 0) &
pb_CreateRegisterWK("Set1", 1, PB_DEV_BIT_BANGING_IO16_FIELDS, "Set", 8) &
pb_CreateRegisterWK("Clear0", 2, PB_DEV_BIT_BANGING_IO16_FIELDS, "Clear", 0) &
pb_CreateRegisterWK("Clear1", 3, PB_DEV_BIT_BANGING_IO16_FIELDS, "Clear", 8) &
pb_CreateRegisterRO("DataOut0", 0, PB_DEV_BIT_BANGING_IO16_FIELDS, "DataOut", 0) &
pb_CreateRegisterRO("DataOut1", 1, PB_DEV_BIT_BANGING_IO16_FIELDS, "DataOut", 8) &
pb_CreateRegisterRO("DataIn0", 2, PB_DEV_BIT_BANGING_IO16_FIELDS, "DataIn", 0) &
pb_CreateRegisterRO("DataIn1", 3, PB_DEV_BIT_BANGING_IO16_FIELDS, "DataIn", 8)),
RegisterFields => PB_DEV_BIT_BANGING_IO16_FIELDS
);
-- LC-Display
-- ---------------------------------------------------------------------------
constant PB_DEV_LCDISPLAY_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateWriteOnlyField("Data", "Data", 8)
);
constant PB_DEV_LCDISPLAY : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "LC Display Controller",
DeviceShort => "LCD",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_LCDISPLAY_FIELDS, "Command", 0) &
pb_CreateRegisterWO("DataOut", 1, PB_DEV_LCDISPLAY_FIELDS, "Data", 0) &
pb_CreateRegisterKO("DataOut", 1, PB_DEV_LCDISPLAY_FIELDS, "Data", 0)),
RegisterFields => PB_DEV_LCDISPLAY_FIELDS
);
-- UART
-- ---------------------------------------------------------------------------
constant PB_DEV_UART_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Status", "Status", 8) &
pb_CreateWriteOnlyField("FIFO DataOut", "DataOut", 8) &
pb_CreateReadOnlyField("FIFO DataIn", "DataIn", 8)
);
constant PB_DEV_UART : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "UART",
DeviceShort => "UART",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_UART_FIELDS, "Command", 0) &
pb_CreateRegisterRO("Status", 0, PB_DEV_UART_FIELDS, "Status", 0) &
pb_CreateRegisterWO("DataOut", 1, PB_DEV_UART_FIELDS, "DataOut", 0) &
pb_CreateRegisterKO("DataOut", 1, PB_DEV_UART_FIELDS, "DataOut", 0) &
pb_CreateRegisterRO("DataIn", 1, PB_DEV_UART_FIELDS, "DataIn", 0)),
RegisterFields => PB_DEV_UART_FIELDS,
CreatesInterrupt => TRUE
);
-- UARTStream
-- ---------------------------------------------------------------------------
constant PB_DEV_UARTSTREAM_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
0 => pb_CreateRegisterField("Dummy", "Dummy", 8)
);
-- constant PB_DEV_UARTSTREAM : T_PB_DEVICE := pb_CreateDevice(
-- DeviceName => "UARTStream",
-- DeviceShort => "UARTStream",
-- Registers => ((
-- 0 => pb_CreateRegister("Dummy", 0, PB_DEV_UARTSTREAM_FIELDS, "Dummy", 0))
-- ),
-- RegisterFields => PB_DEV_UARTSTREAM_FIELDS,
-- CreatesInterrupt => TRUE
-- );
-- I2C Controller
-- ---------------------------------------------------------------------------
constant PB_DEV_IICCONTROLLER_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Status", "Status", 8) &
pb_CreateRegisterField("Device Address [7:1]", "DeviceAddress", 8) &
pb_CreateRegisterField("RX Length [3:0]", "RXLength", 8) &
pb_CreateWriteOnlyField("TX_FIFO", "TX_FIFO", 8) &
pb_CreateReadOnlyField("RX_FIFO", "RX_FIFO", 8)
);
constant PB_DEV_IICCONTROLLER : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "I2C Controller",
DeviceShort => "IICCtrl",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_IICCONTROLLER_FIELDS, "Command", 0) &
pb_CreateRegisterRO("Status", 0, PB_DEV_IICCONTROLLER_FIELDS, "Status", 0) &
pb_CreateRegisterRW("DeviceAddress", 1, PB_DEV_IICCONTROLLER_FIELDS, "DeviceAddress", 0) &
pb_CreateRegisterRW("Length", 2, PB_DEV_IICCONTROLLER_FIELDS, "RXLength", 0) &
pb_CreateRegisterWO("TX_FIFO", 3, PB_DEV_IICCONTROLLER_FIELDS, "TX_FIFO", 0) &
pb_CreateRegisterRO("RX_FIFO", 3, PB_DEV_IICCONTROLLER_FIELDS, "RX_FIFO", 0)),
RegisterFields => PB_DEV_IICCONTROLLER_FIELDS,
CreatesInterrupt => TRUE
);
-- MDIO Controller
-- ---------------------------------------------------------------------------
constant PB_DEV_MDIOCONTROLLER_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
0 => pb_CreateRegisterField("Dummy", "Dummy", 8)
);
-- constant PB_DEV_MDIOCONTROLLER : T_PB_DEVICE := pb_CreateDevice(
-- DeviceName => "MDIO Controller",
-- DeviceShort => "MDIOCtrl",
-- Registers => ((
-- 0 => pb_CreateRegister("Dummy", 0, PB_DEV_MDIOCONTROLLER_FIELDS, "Dummy", 0))
-- ),
-- RegisterFields => PB_DEV_MDIOCONTROLLER_FIELDS,
-- CreatesInterrupt => FALSE
-- );
-- Dynamic Reconfiguration Port
-- ---------------------------------------------------------------------------
constant PB_DEV_DRP_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Status", "Status", 8) &
pb_CreateRegisterField("Address", "Address", 8) &
pb_CreateRegisterField("Data", "Data", 16) &
pb_CreateWriteOnlyField("Mask Register Set", "MaskRegSet", 16) &
pb_CreateWriteOnlyField("Mask Register Clear", "MaskRegClr", 16)
);
constant PB_DEV_DRP : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "PicoBlaze to DRP Adapter",
DeviceShort => "DRP",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_DRP_FIELDS, "Command", 0) &
pb_CreateRegisterRO("Status", 0, PB_DEV_DRP_FIELDS, "Status", 0) &
pb_CreateRegisterRW("Address", 1, PB_DEV_DRP_FIELDS, "Address", 0) &
pb_CreateRegisterRW("Data0", 2, PB_DEV_DRP_FIELDS, "Data", 0) &
pb_CreateRegisterRW("Data1", 3, PB_DEV_DRP_FIELDS, "Data", 0) &
pb_CreateRegisterWO("MaskRegSet0", 4, PB_DEV_DRP_FIELDS, "MaskRegSet", 0) &
pb_CreateRegisterWO("MaskRegSet1", 5, PB_DEV_DRP_FIELDS, "MaskRegSet", 0) &
pb_CreateRegisterWO("MaskRegClr0", 6, PB_DEV_DRP_FIELDS, "MaskRegClr", 0) &
pb_CreateRegisterWO("MaskRegClr1", 7, PB_DEV_DRP_FIELDS, "MaskRegClr", 0)),
RegisterFields => PB_DEV_DRP_FIELDS
);
-- Frequency Measurement
-- ---------------------------------------------------------------------------
constant PB_DEV_FREQM_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Frequency Counter", "FreqCntValue", 24) &
pb_CreateReadOnlyField("Status", "Status", 8)
);
constant PB_DEV_FREQM : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "FrequencyMeasurement",
DeviceShort => "FreqM",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_FREQM_FIELDS, "Command", 0) &
pb_CreateRegisterRO("FreqCntValue0", 0, PB_DEV_FREQM_FIELDS, "FreqCntValue", 0) &
pb_CreateRegisterRO("FreqCntValue1", 1, PB_DEV_FREQM_FIELDS, "FreqCntValue", 0) &
pb_CreateRegisterRO("FreqCntValue2", 2, PB_DEV_FREQM_FIELDS, "FreqCntValue", 0) &
pb_CreateRegisterRO("Status", 3, PB_DEV_FREQM_FIELDS, "Status", 0)),
RegisterFields => PB_DEV_FREQM_FIELDS
);
-- BCD Counter
-- ---------------------------------------------------------------------------
constant PB_DEV_BCDCOUNTER_FIELDS : T_PB_REGISTER_FIELD_VECTOR := (
pb_CreateWriteOnlyField("Command", "Command", 8) &
pb_CreateReadOnlyField("Value", "Value", 32)
);
constant PB_DEV_BCDCOUNTER : T_PB_DEVICE := pb_CreateDevice(
DeviceName => "BCD Counter",
DeviceShort => "BCDCnt",
Registers => (
pb_CreateRegisterWO("Command", 0, PB_DEV_BCDCOUNTER_FIELDS, "Command", 0) &
pb_CreateRegisterRO("Value0", 0, PB_DEV_BCDCOUNTER_FIELDS, "Value", 0) &
pb_CreateRegisterRO("Value1", 1, PB_DEV_BCDCOUNTER_FIELDS, "Value", 8) &
pb_CreateRegisterRO("Value2", 2, PB_DEV_BCDCOUNTER_FIELDS, "Value", 16) &
pb_CreateRegisterRO("Value3", 3, PB_DEV_BCDCOUNTER_FIELDS, "Value", 24)),
RegisterFields => PB_DEV_BCDCOUNTER_FIELDS
);
-- define aliases
constant PB_DEV_INTERRUPT : T_PB_DEVICE := pb_CreateDeviceAlias(PB_DEV_INTERRUPT16, "IntC");
constant PB_DEV_MULTIPLIER : T_PB_DEVICE := pb_CreateDeviceAlias(PB_DEV_MULTIPLIER32, "Mult");
constant PB_DEV_DIVIDER : T_PB_DEVICE := pb_CreateDeviceAlias(PB_DEV_DIVIDER32, "Div");
constant PB_DEV_CONVERTER_BCD : T_PB_DEVICE := pb_CreateDeviceAlias(PB_DEV_CONVERTER_BCD24, "ConvBCD");
constant PB_DEV_BIT_BANGING_IO : T_PB_DEVICE := pb_CreateDeviceAlias(PB_DEV_BIT_BANGING_IO8, "BBIO");
end package body;
| apache-2.0 |
Paebbels/PicoBlaze-Library | vhdl/UART6_RX.vhdl | 1 | 17215 | --
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- UART Receiver with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- This module was made for use with Spartan-6 Generation Devices and is also ideally
-- suited for use with Virtex-6 and 7-Series devices.
--
-- Version 1 - 31st March 2011.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the
-- implementation. The Unisim Library is used to define Xilinx primitives. It is also
-- used during simulation.
-- The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for
--
entity uart_rx6 is
Port ( serial_in : in std_logic;
en_16_x_baud : in std_logic;
data_out : out std_logic_vector(7 downto 0);
buffer_read : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end uart_rx6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for uart_rx6 - constrained
--
architecture rtl of uart_rx6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in uart_rx6
--
-------------------------------------------------------------------------------------------
--
signal pointer_value : std_logic_vector(3 downto 0);
signal pointer : std_logic_vector(3 downto 0);
signal en_pointer : std_logic;
signal zero : std_logic;
signal full_int : std_logic;
signal data_present_value : std_logic;
signal data_present_int : std_logic;
signal sample_value : std_logic;
signal sample : std_logic;
signal sample_dly_value : std_logic;
signal sample_dly : std_logic;
signal stop_bit_value : std_logic;
signal stop_bit : std_logic;
signal data_value : std_logic_vector(7 downto 0);
signal data : std_logic_vector(7 downto 0);
signal run_value : std_logic;
signal run : std_logic;
signal start_bit_value : std_logic;
signal start_bit : std_logic;
signal div_value : std_logic_vector(3 downto 0);
signal div : std_logic_vector(3 downto 0);
signal div_carry : std_logic;
signal sample_input_value : std_logic;
signal sample_input : std_logic;
signal buffer_write_value : std_logic;
signal buffer_write : std_logic;
--
-------------------------------------------------------------------------------------------
--
-- Attributes to guide mapping of logic into Slices.
-------------------------------------------------------------------------------------------
--
--
attribute hblknm : string;
attribute hblknm of pointer3_lut : label is "uart_rx6_1";
attribute hblknm of pointer3_flop : label is "uart_rx6_1";
attribute hblknm of pointer2_lut : label is "uart_rx6_1";
attribute hblknm of pointer2_flop : label is "uart_rx6_1";
attribute hblknm of pointer01_lut : label is "uart_rx6_1";
attribute hblknm of pointer1_flop : label is "uart_rx6_1";
attribute hblknm of pointer0_flop : label is "uart_rx6_1";
attribute hblknm of data_present_lut : label is "uart_rx6_1";
attribute hblknm of data_present_flop : label is "uart_rx6_1";
--
attribute hblknm of data01_lut : label is "uart_rx6_2";
attribute hblknm of data0_flop : label is "uart_rx6_2";
attribute hblknm of data1_flop : label is "uart_rx6_2";
attribute hblknm of data23_lut : label is "uart_rx6_2";
attribute hblknm of data2_flop : label is "uart_rx6_2";
attribute hblknm of data3_flop : label is "uart_rx6_2";
attribute hblknm of data45_lut : label is "uart_rx6_2";
attribute hblknm of data4_flop : label is "uart_rx6_2";
attribute hblknm of data5_flop : label is "uart_rx6_2";
attribute hblknm of data67_lut : label is "uart_rx6_2";
attribute hblknm of data6_flop : label is "uart_rx6_2";
attribute hblknm of data7_flop : label is "uart_rx6_2";
--
attribute hblknm of div01_lut : label is "uart_rx6_3";
attribute hblknm of div23_lut : label is "uart_rx6_3";
attribute hblknm of div0_flop : label is "uart_rx6_3";
attribute hblknm of div1_flop : label is "uart_rx6_3";
attribute hblknm of div2_flop : label is "uart_rx6_3";
attribute hblknm of div3_flop : label is "uart_rx6_3";
attribute hblknm of sample_input_lut : label is "uart_rx6_3";
attribute hblknm of sample_input_flop : label is "uart_rx6_3";
attribute hblknm of full_lut : label is "uart_rx6_3";
--
attribute hblknm of sample_lut : label is "uart_rx6_4";
attribute hblknm of sample_flop : label is "uart_rx6_4";
attribute hblknm of sample_dly_flop : label is "uart_rx6_4";
attribute hblknm of stop_bit_lut : label is "uart_rx6_4";
attribute hblknm of stop_bit_flop : label is "uart_rx6_4";
attribute hblknm of buffer_write_flop : label is "uart_rx6_4";
attribute hblknm of start_bit_lut : label is "uart_rx6_4";
attribute hblknm of start_bit_flop : label is "uart_rx6_4";
attribute hblknm of run_lut : label is "uart_rx6_4";
attribute hblknm of run_flop : label is "uart_rx6_4";
--
--
-------------------------------------------------------------------------------------------
--
-- Start of uart_rx6 circuit description
--
-------------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of storage_srl : label is "uart_rx6_5";
begin
storage_srl: SRL16E
generic map (INIT => X"0000")
port map( D => data(i),
CE => buffer_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => data_out(i) );
end generate data_width_loop;
pointer3_lut: LUT6
generic map (INIT => X"FF00FE00FF80FF00")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(3));
pointer3_flop: FDR
port map ( D => pointer_value(3),
Q => pointer(3),
R => buffer_reset,
C => clk);
pointer2_lut: LUT6
generic map (INIT => X"F0F0E1E0F878F0F0")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(2));
pointer2_flop: FDR
port map ( D => pointer_value(2),
Q => pointer(2),
R => buffer_reset,
C => clk);
pointer01_lut: LUT6_2
generic map (INIT => X"CC9060CCAA5050AA")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => en_pointer,
I3 => buffer_write,
I4 => buffer_read,
I5 => '1',
O5 => pointer_value(0),
O6 => pointer_value(1));
pointer1_flop: FDR
port map ( D => pointer_value(1),
Q => pointer(1),
R => buffer_reset,
C => clk);
pointer0_flop: FDR
port map ( D => pointer_value(0),
Q => pointer(0),
R => buffer_reset,
C => clk);
data_present_lut: LUT6_2
generic map (INIT => X"F4FCF4FC040004C0")
port map( I0 => zero,
I1 => data_present_int,
I2 => buffer_write,
I3 => buffer_read,
I4 => full_int,
I5 => '1',
O5 => en_pointer,
O6 => data_present_value);
data_present_flop: FDR
port map ( D => data_present_value,
Q => data_present_int,
R => buffer_reset,
C => clk);
full_lut: LUT6_2
generic map (INIT => X"0001000080000000")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => '1',
I5 => '1',
O5 => full_int,
O6 => zero);
sample_lut: LUT6_2
generic map (INIT => X"CCF00000AACC0000")
port map( I0 => serial_in,
I1 => sample,
I2 => sample_dly,
I3 => en_16_x_baud,
I4 => '1',
I5 => '1',
O5 => sample_value,
O6 => sample_dly_value);
sample_flop: FD
port map ( D => sample_value,
Q => sample,
C => clk);
sample_dly_flop: FD
port map ( D => sample_dly_value,
Q => sample_dly,
C => clk);
stop_bit_lut: LUT6_2
generic map (INIT => X"CAFFCAFF0000C0C0")
port map( I0 => stop_bit,
I1 => sample,
I2 => sample_input,
I3 => run,
I4 => data(0),
I5 => '1',
O5 => buffer_write_value,
O6 => stop_bit_value);
buffer_write_flop: FD
port map ( D => buffer_write_value,
Q => buffer_write,
C => clk);
stop_bit_flop: FD
port map ( D => stop_bit_value,
Q => stop_bit,
C => clk);
data01_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(0),
I1 => data(1),
I2 => data(2),
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(0),
O6 => data_value(1));
data0_flop: FD
port map ( D => data_value(0),
Q => data(0),
C => clk);
data1_flop: FD
port map ( D => data_value(1),
Q => data(1),
C => clk);
data23_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(2),
I1 => data(3),
I2 => data(4),
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(2),
O6 => data_value(3));
data2_flop: FD
port map ( D => data_value(2),
Q => data(2),
C => clk);
data3_flop: FD
port map ( D => data_value(3),
Q => data(3),
C => clk);
data45_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(4),
I1 => data(5),
I2 => data(6),
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(4),
O6 => data_value(5));
data4_flop: FD
port map ( D => data_value(4),
Q => data(4),
C => clk);
data5_flop: FD
port map ( D => data_value(5),
Q => data(5),
C => clk);
data67_lut: LUT6_2
generic map (INIT => X"F0CCFFFFCCAAFFFF")
port map( I0 => data(6),
I1 => data(7),
I2 => stop_bit,
I3 => sample_input,
I4 => run,
I5 => '1',
O5 => data_value(6),
O6 => data_value(7));
data6_flop: FD
port map ( D => data_value(6),
Q => data(6),
C => clk);
data7_flop: FD
port map ( D => data_value(7),
Q => data(7),
C => clk);
run_lut: LUT6
generic map (INIT => X"2F2FAFAF0000FF00")
port map( I0 => data(0),
I1 => start_bit,
I2 => sample_input,
I3 => sample_dly,
I4 => sample,
I5 => run,
O => run_value);
run_flop: FD
port map ( D => run_value,
Q => run,
C => clk);
start_bit_lut: LUT6
generic map (INIT => X"222200F000000000")
port map( I0 => start_bit,
I1 => sample_input,
I2 => sample_dly,
I3 => sample,
I4 => run,
I5 => '1',
O => start_bit_value);
start_bit_flop: FD
port map ( D => start_bit_value,
Q => start_bit,
C => clk);
div01_lut: LUT6_2
generic map (INIT => X"6C0000005A000000")
port map( I0 => div(0),
I1 => div(1),
I2 => en_16_x_baud,
I3 => run,
I4 => '1',
I5 => '1',
O5 => div_value(0),
O6 => div_value(1));
div0_flop: FD
port map ( D => div_value(0),
Q => div(0),
C => clk);
div1_flop: FD
port map ( D => div_value(1),
Q => div(1),
C => clk);
div23_lut: LUT6_2
generic map (INIT => X"6CCC00005AAA0000")
port map( I0 => div(2),
I1 => div(3),
I2 => div_carry,
I3 => en_16_x_baud,
I4 => run,
I5 => '1',
O5 => div_value(2),
O6 => div_value(3));
div2_flop: FD
port map ( D => div_value(2),
Q => div(2),
C => clk);
div3_flop: FD
port map ( D => div_value(3),
Q => div(3),
C => clk);
sample_input_lut: LUT6_2
generic map (INIT => X"0080000088888888")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => '1',
O5 => div_carry,
O6 => sample_input_value);
sample_input_flop: FD
port map ( D => sample_input_value,
Q => sample_input,
C => clk);
-- assign internal signals to outputs
buffer_full <= full_int;
buffer_half_full <= pointer(3);
buffer_data_present <= data_present_int;
end;
-------------------------------------------------------------------------------------------
--
-- END OF FILE uart_rx6.vhd
--
-------------------------------------------------------------------------------------------
| apache-2.0 |
Paebbels/PicoBlaze-Library | vhdl/Device/pb_InstructionROM_Device.vhdl | 1 | 15785 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Wrapper module for up to 8 PicoBlaze ROM pages. All ROMs are
-- reprogrammable via JTAG_Loader
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- -----------------------------------------------------------------------------
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.components.all;
use PoC.ocram.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
use L_PicoBlaze.pb_comp.all;
entity pb_InstructionROM_Device is
generic (
PAGES : POSITIVE := 1;
SOURCE_DIRECTORY : STRING := "";
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE;
ENABLE_JTAG_LOADER : BOOLEAN := FALSE
);
port (
Clock : in STD_LOGIC;
Fetch : in STD_LOGIC;
InstructionPointer : in T_PB_ADDRESS;
Instruction : out T_PB_INSTRUCTION;
Reboot : out STD_LOGIC;
-- PicoBlaze interface
Address : in T_SLV_8;
WriteStrobe : in STD_LOGIC;
WriteStrobe_K : in STD_LOGIC;
ReadStrobe : in STD_LOGIC;
DataIn : in T_SLV_8;
DataOut : out T_SLV_8;
Interrupt : out STD_LOGIC;
Interrupt_Ack : in STD_LOGIC;
Message : out T_SLV_8;
PageNumber : out STD_LOGIC_VECTOR(2 downto 0)
);
end;
architecture rtl of pb_InstructionROM_Device is
type T_PB_INSTRUCTION_VECTOR is array (NATURAL range <>) of T_PB_INSTRUCTION;
function reverse(vec : T_PB_INSTRUCTION_VECTOR) return T_PB_INSTRUCTION_VECTOR is
variable res : T_PB_INSTRUCTION_VECTOR(vec'range);
begin
for i in vec'low to vec'high loop
res(vec'low + (vec'high - i)) := vec(i);
end loop;
return res;
end function;
constant ENABLE_LOADER : BOOLEAN := ite((VENDOR = VENDOR_XILINX), ENABLE_JTAG_LOADER, FALSE);
constant FILENAME_PATTERN : STRING := ite((VENDOR = VENDOR_ALTERA), "main_Page#.mif", "main_Page#.hex");
constant REG_RW_PAGE_NUMBER : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
signal Reg_PageNumber : T_SLV_8 := (others => '0');
signal Reg_PageNumber_us : UNSIGNED(log2ceilnz(PAGES) - 1 downto 0) := (others => '0');
signal Page_Instructions : T_PB_INSTRUCTION_VECTOR(PAGES - 1 downto 0);
signal Pages_DataOut : T_PB_INSTRUCTION_VECTOR(PAGES - 1 downto 0);
signal JTAGLoader_Clock : STD_LOGIC;
signal JTAGLoader_Enable : STD_LOGIC_VECTOR(PAGES - 1 downto 0);
signal JTAGLoader_Address : T_PB_ADDRESS;
signal JTAGLoader_WriteEnable : STD_LOGIC;
signal JTAGLoader_DataOut : T_PB_INSTRUCTION;
signal JTAGLoader_PB_Reset : STD_LOGIC_VECTOR(PAGES - 1 downto 0);
signal Page_n_rst : STD_LOGIC;
signal Page_0_rst : STD_LOGIC;
signal Page_n_rst_d : STD_LOGIC := '0';
signal Page_0_rst_d : STD_LOGIC := '0';
signal Page_n_rst_re : STD_LOGIC;
signal Page_0_rst_fe : STD_LOGIC;
signal Reset_r : STD_LOGIC := '0';
begin
assert (PAGES <= 8) report "This ROM and JTAGLoader6 support 8 pages maximum." severity FAILURE;
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset_r,
-- PicoBlaze interface
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Address => Address,
In_Data => DataIn,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_Data => AdrDec_Data
);
-- Registers
process(Clock)
begin
if rising_edge(Clock) then
if (Reset_r = '1') then
Reg_PageNumber <= (others => '0');
elsif (AdrDec_we = '1') then
case AdrDec_WriteAddress(0 downto 0) is
when REG_RW_PAGE_NUMBER => Reg_PageNumber <= AdrDec_Data;
when others => null;
end case;
end if;
end if;
end process;
process(AdrDec_re, AdrDec_ReadAddress, Reg_PageNumber)
begin
case AdrDec_ReadAddress(0 downto 0) IS
when REG_RW_PAGE_NUMBER => DataOut <= Reg_PageNumber;
when others => DataOut <= Reg_PageNumber;
end case;
end process;
Interrupt <= '0';
Message <= x"00";
--
PageNumber <= Reg_PageNumber(PageNumber'range);
Reg_PageNumber_us <= unsigned(Reg_PageNumber(Reg_PageNumber_us'range));
Instruction <= Page_Instructions(to_index(Reg_PageNumber_us, Page_Instructions'length));
-- Reset control: keep PB in reset while programming, release after last ROM is written => reboot
Page_n_rst <= JTAGLoader_PB_Reset(PAGES - 1);
Page_0_rst <= JTAGLoader_PB_Reset(0);
Page_n_rst_d <= Page_n_rst when rising_edge(Clock);
Page_0_rst_d <= Page_0_rst when rising_edge(Clock);
Page_n_rst_re <= not Page_n_rst_d and Page_n_rst;
Page_0_rst_fe <= Page_0_rst_d and not Page_0_rst;
Reset_r <= ffrs(q => Reset_r, set => Page_n_rst_re, rst => Page_0_rst_fe) when rising_edge(Clock);
Reboot <= Reset_r;
genTemplate : if (str_length(SOURCE_DIRECTORY) = 0) generate
genPage0 : if (TRUE) generate
constant PAGE_NUMBER : NATURAL := 0;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page0
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage1 : if (PAGES > 1) generate
constant PAGE_NUMBER : NATURAL := 1;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page1
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage2 : if (PAGES > 2) generate
constant PAGE_NUMBER : NATURAL := 2;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page2
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage3 : if (PAGES > 3) generate
constant PAGE_NUMBER : NATURAL := 3;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page3
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage4 : if (PAGES > 4) generate
constant PAGE_NUMBER : NATURAL := 4;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page4
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage5 : if (PAGES > 5) generate
constant PAGE_NUMBER : NATURAL := 5;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page5
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage6 : if (PAGES > 6) generate
constant PAGE_NUMBER : NATURAL := 6;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page6
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage7 : if (PAGES > 7) generate
constant PAGE_NUMBER : NATURAL := 7;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page7
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
end generate;
genLoadFile : if (str_length(SOURCE_DIRECTORY) /= 0) generate
genPages : for i in 0 to PAGES - 1 generate
constant FILENAME : STRING := SOURCE_DIRECTORY & str_replace(FILENAME_PATTERN, "#", INTEGER'image(i));
signal Port1_Address : UNSIGNED(InstructionPointer'range);
signal Port2_Address : UNSIGNED(JTAGLoader_Address'range);
begin
assert PB_VERBOSE report "Loading ROM file: '" & FILENAME & "'" severity NOTE;
genOCROM : if (ENABLE_LOADER = FALSE) generate
Port1_Address <= unsigned(InstructionPointer);
genericMemory : ocrom_sp
generic map (
A_BITS => 12,
D_BITS => 18,
FILENAME => FILENAME
)
port map (
clk => Clock,
ce => Fetch,
a => Port1_Address,
q => Page_Instructions(i)
);
end generate;
genOCRAM : if (ENABLE_LOADER = TRUE) generate
Port1_Address <= unsigned(InstructionPointer);
Port2_Address <= unsigned(JTAGLoader_Address);
genericMemory : ocram_tdp
generic map (
A_BITS => 12,
D_BITS => 18,
FILENAME => FILENAME
)
port map (
clk1 => Clock,
ce1 => Fetch,
we1 => '0',
a1 => Port1_Address,
d1 => (others => '0'),
q1 => Page_Instructions(i),
clk2 => JTAGLoader_Clock,
ce2 => JTAGLoader_Enable(i),
we2 => JTAGLoader_WriteEnable,
a2 => Port2_Address,
d2 => JTAGLoader_DataOut,
q2 => Pages_DataOut(i)
);
end generate;
end generate;
end generate;
genNoJTAGLoader : if (ENABLE_LOADER = FALSE) generate
JTAGLoader_Clock <= '0';
JTAGLoader_Enable <= (others => '0');
JTAGLoader_Address <= (others => '0');
JTAGLoader_WriteEnable <= '0';
JTAGLoader_DataOut <= (others => '0');
end generate;
genJTAGLoader : if (ENABLE_LOADER = TRUE) generate
signal WorkAround_Enable : STD_LOGIC_VECTOR(PAGES - 1 downto 0);
signal WorkAround_DataIn : T_PB_INSTRUCTION_VECTOR(PAGES - 1 downto 0);
begin
JTAGLoader : JTAGLoader6
generic map (
C_NUM_PICOBLAZE => PAGES,
C_ADDR_WIDTH => (others => T_PB_ADDRESS'length)
)
port map (
jtag_clk => JTAGLoader_Clock,
jtag_en => WorkAround_Enable,
jtag_din => JTAGLoader_DataOut,
jtag_addr => JTAGLoader_Address,
jtag_we => JTAGLoader_WriteEnable,
jtag_dout_0 => WorkAround_DataIn(imin(PAGES - 1, 0)),
jtag_dout_1 => WorkAround_DataIn(imin(PAGES - 1, 1)),
jtag_dout_2 => WorkAround_DataIn(imin(PAGES - 1, 2)),
jtag_dout_3 => WorkAround_DataIn(imin(PAGES - 1, 3)),
jtag_dout_4 => WorkAround_DataIn(imin(PAGES - 1, 4)),
jtag_dout_5 => WorkAround_DataIn(imin(PAGES - 1, 5)),
jtag_dout_6 => WorkAround_DataIn(imin(PAGES - 1, 6)),
jtag_dout_7 => WorkAround_DataIn(imin(PAGES - 1, 7)),
picoblaze_reset => JTAGLoader_PB_Reset
);
-- work around for a bug in JTAGLoader.exe
WorkAround_DataIn <= reverse(Pages_DataOut);
JTAGLoader_Enable <= reverse(WorkAround_Enable);
end generate;
end;
| apache-2.0 |
vikene/vhdl | Gates and drivers/XNORGATE.vhd | 1 | 294 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY XNORGATE IS
PORT(A,B:IN STD_LOGIC;
C:OUT STD_LOGIC);
END XNORGATE;
ARCHITECTURE XNORG OF XNORGATE IS
BEGIN
C <= A XNOR B;
END XNORG;
| apache-2.0 |
Paebbels/PicoBlaze-Library | netlist/XC5VLX50T-1FF1136/CSP_DRP_ILA.vhdl | 1 | 1130 | -------------------------------------------------------------------------------
-- Copyright (c) 2014 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : CSP_DRP_ILA.vhd
-- /___/ /\ Timestamp : Wed Nov 12 20:38:34 Mitteleuropäische Zeit 2014
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CSP_DRP_ILA IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
DATA: in std_logic_vector(69 downto 0);
TRIG0: in std_logic_vector(9 downto 0);
TRIG1: in std_logic_vector(11 downto 0);
TRIG_OUT: out std_logic);
END CSP_DRP_ILA;
ARCHITECTURE CSP_DRP_ILA_a OF CSP_DRP_ILA IS
BEGIN
END CSP_DRP_ILA_a;
| apache-2.0 |
nsensfel/tabellion | data/test/CNE_01100/invalid.vhd | 1 | 694 | library IEEE;
use IEEE.std_logic_1164.all;
entity invalid is
port
(
i_ip0: in std_logic;
i_clock: in std_logic;
i_o: in std_logic;
i_o_reset: in std_logic;
i_o_b_reset: in std_logic;
i_i_reset: in std_logic;
o_ip0: out std_logic;
o_clock: out std_logic;
o_o: out std_logic;
o_i_reset: out std_logic;
o_o_reset: out std_logic;
o_o_b_reset: out std_logic;
b_ip0: inout std_logic;
b_clock: inout std_logic;
b_o: inout std_logic;
b_i_reset: inout std_logic;
b_o_reset: inout std_logic;
b_b_o_reset: inout std_logic
);
end;
architecture RTL of invalid is
begin
end architecture;
| apache-2.0 |
Paebbels/PicoBlaze-Library | vhdl/Device/pb_InterruptController_Device.vhdl | 1 | 10811 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: PicoBlaze Interrupt Controller with up to 32 ports.
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.components.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
entity pb_InterruptController_Device is
generic (
DEBUG : BOOLEAN := FALSE;
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE;
PORTS : POSITIVE := 4
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- PicoBlaze interface
Address : in T_SLV_8;
WriteStrobe : in STD_LOGIC;
WriteStrobe_K : in STD_LOGIC;
ReadStrobe : in STD_LOGIC;
DataIn : in T_SLV_8;
DataOut : out T_SLV_8;
Interrupt : out STD_LOGIC;
Interrupt_Ack : in STD_LOGIC;
Message : out T_SLV_8;
-- PicoBlaze interrupt interface (direct coupled)
PB_Interrupt : out STD_LOGIC;
PB_Interrupt_Ack : in STD_LOGIC;
-- Interrupt source interface
Dev_Interrupt : in STD_LOGIC_VECTOR(PORTS - 1 downto 0);
Dev_Interrupt_Ack : out STD_LOGIC_VECTOR(PORTS - 1 downto 0);
Dev_Interrupt_Message : in T_SLVV_8(PORTS - 1 downto 0)
);
end entity;
architecture rtl of pb_InterruptController_Device is
attribute KEEP : BOOLEAN;
constant REQUIRED_REG_BYTES : POSITIVE := div_ceil(PORTS, 8);
-- Regarding REQUIRED_REG_BYTES, the position of the enable/disable marker bit is moved from LSB to MSB
-- Example 1:
-- REQUIRED_REG_BYTES = 1
-- -> no bit is required to address the register in the field, because it's only one byte
-- => enable/disable bit is located at bit 0
--
-- Example 2:
-- REQUIRED_REG_BYTES = 3
-- -> 2 bits are required to address 3 registers in the field [23:0]
-- -> [1:0] is used to address the correct byte/register
-- => enable/disable bit is located at bit 2
constant BIT_EN_DIS : NATURAL := log2ceil(REQUIRED_REG_BYTES);
constant BIT_VEC_MES : NATURAL := log2ceil(REQUIRED_REG_BYTES);
constant REG_WO_ENABLE_BIT_VALUE : STD_LOGIC := '0';
constant REG_WO_DISABLE_BIT_VALUE : STD_LOGIC := '1';
constant REG_RO_VECTOR_BIT_VALUE : STD_LOGIC := '0';
constant REG_RO_MESSAGE_BIT_VALUE : STD_LOGIC := '1';
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
signal Reg_InterruptEnable_slvv : T_SLVV_8(REQUIRED_REG_BYTES - 1 downto 0) := (others => (others => '0'));
signal Reg_InterruptEnable : STD_LOGIC_VECTOR((REQUIRED_REG_BYTES * 8) - 1 downto 0);
type T_STATE is (ST_IDLE, ST_INTERRUPT_PENDING, ST_INTERRUPT_MESSAGE);
signal State : T_STATE := ST_IDLE;
signal NextState : T_STATE;
signal Interrupt_re : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
signal InterruptPending_r : STD_LOGIC_VECTOR(PORTS - 1 downto 0) := (others => '0');
signal InterruptMessages_d : T_SLVV_8(PORTS - 1 downto 0) := (others => (others => '0'));
signal InterruptRequestsOpen : STD_LOGIC;
signal InterruptRequestVector : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
signal InterruptSource_Read : STD_LOGIC;
signal FSM_DataOut : T_SLV_8;
signal FSM_Arbitrate : STD_LOGIC;
signal FSM_InterruptClearVector : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
signal Arb_GrantVector : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
signal Arb_GrantVector_bin : STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0);
attribute KEEP of FSM_Arbitrate : signal is DEBUG;
attribute KEEP of Arb_GrantVector : signal is DEBUG;
attribute KEEP of InterruptRequestVector : signal is DEBUG;
begin
assert (PORTS <= 32)
report "InterruptController supports only up to 32 interrupt sources!"
severity failure;
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset,
-- PicoBlaze interface
In_Address => Address,
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Data => DataIn,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_Data => AdrDec_Data
);
process(Clock, AdrDec_WriteAddress)
variable index : NATURAL;
begin
index := to_index(AdrDec_WriteAddress(BIT_EN_DIS - 1 downto 0));
if rising_edge(Clock) then
if (Reset = '1') then
Reg_InterruptEnable_slvv <= (others => (others => '0'));
elsif (AdrDec_we = '1') then
case AdrDec_WriteAddress(BIT_EN_DIS) is
when REG_WO_ENABLE_BIT_VALUE => Reg_InterruptEnable_slvv(index) <= Reg_InterruptEnable_slvv(index) or AdrDec_Data;
when REG_WO_DISABLE_BIT_VALUE => Reg_InterruptEnable_slvv(index) <= Reg_InterruptEnable_slvv(index) and not AdrDec_Data;
when others => null;
end case;
end if;
end if;
end process;
process(AdrDec_re, AdrDec_ReadAddress, Reg_InterruptEnable_slvv, FSM_DataOut)
variable index : NATURAL;
begin
index := to_index(AdrDec_ReadAddress(BIT_VEC_MES - 1 downto 0));
DataOut <= FSM_DataOut;
case AdrDec_ReadAddress(BIT_VEC_MES) is
when REG_RO_VECTOR_BIT_VALUE => DataOut <= Reg_InterruptEnable_slvv(index);
when REG_RO_MESSAGE_BIT_VALUE => DataOut <= FSM_DataOut;
when others => DataOut <= (others => 'X');
end case;
InterruptSource_Read <= AdrDec_re and to_sl(AdrDec_ReadAddress(BIT_VEC_MES) = REG_RO_MESSAGE_BIT_VALUE);
end process;
Interrupt <= '0';
Message <= x"00";
genPort : for i in 0 to PORTS - 1 generate
signal Interrupt_d : STD_LOGIC := '0';
begin
Interrupt_d <= Dev_Interrupt(i) when rising_edge(Clock);
Interrupt_re(i) <= not Interrupt_d and Dev_Interrupt(i);
-- RS-FFs to latch the interrupt signal and the message
InterruptPending_r(i) <= ffrs(q => InterruptPending_r(i), rst => (Reset or FSM_InterruptClearVector(i)), set => Interrupt_re(i)) when rising_edge(Clock);
InterruptMessages_d(i) <= ffdre(q => InterruptMessages_d(i), d => Dev_Interrupt_Message(i), rst => (Reset or FSM_InterruptClearVector(i)), en => Interrupt_re(i)) when rising_edge(Clock);
end generate;
Reg_InterruptEnable <= to_slv(Reg_InterruptEnable_slvv);
InterruptRequestVector <= InterruptPending_r and Reg_InterruptEnable(InterruptPending_r'range);
InterruptRequestsOpen <= slv_or(InterruptRequestVector and not FSM_InterruptClearVector);
Arb : entity PoC.bus_Arbiter
generic map (
STRATEGY => "RR",
PORTS => PORTS,
WEIGHTS => (0 to PORTS - 1 => 1),
OUTPUT_REG => FALSE
)
port map (
Clock => Clock,
Reset => Reset,
Arbitrate => FSM_Arbitrate,
Request_Vector => InterruptRequestVector,
Grant_Vector => Arb_GrantVector,
Grant_Index => Arb_GrantVector_bin
);
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
State <= ST_IDLE;
else
State <= NextState;
end if;
end if;
end process;
process(State, InterruptRequestsOpen, Arb_GrantVector, Arb_GrantVector_bin, PB_Interrupt_Ack, InterruptSource_Read, InterruptMessages_d)
begin
NextState <= State;
PB_Interrupt <= InterruptRequestsOpen;
FSM_DataOut <= resize(Arb_GrantVector_bin, FSM_DataOut'length);
Dev_Interrupt_Ack <= (others => '0');
FSM_Arbitrate <= '0';
FSM_InterruptClearVector <= (others => '0');
case State is
when ST_IDLE =>
if (InterruptRequestsOpen = '1') then
FSM_Arbitrate <= '1';
NextState <= ST_INTERRUPT_PENDING;
end if;
when ST_INTERRUPT_PENDING =>
FSM_DataOut <= resize(Arb_GrantVector_bin, FSM_DataOut'length);
if (InterruptSource_Read = '1') then
NextState <= ST_INTERRUPT_MESSAGE;
end if;
when ST_INTERRUPT_MESSAGE =>
FSM_DataOut <= InterruptMessages_d(to_index(Arb_GrantVector_bin));
if (PB_Interrupt_Ack = '1') then
FSM_InterruptClearVector <= Arb_GrantVector;
Dev_Interrupt_Ack <= Arb_GrantVector;
if (InterruptRequestsOpen = '1') then
FSM_Arbitrate <= '1';
NextState <= ST_INTERRUPT_PENDING;
else
NextState <= ST_IDLE;
end if;
end if;
end case;
end process;
end;
| apache-2.0 |
Paebbels/PicoBlaze-Library | netlist/XC7VX485T-2FFG1761/CSP_PB_Tracer_ILA.vhdl | 1 | 1261 | -------------------------------------------------------------------------------
-- Copyright (c) 2015 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : CSP_PB_Tracer_ILA.vhd
-- /___/ /\ Timestamp : Tue Jun 09 21:49:29 Mitteleuropäische Sommerzeit 2015
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CSP_PB_Tracer_ILA IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
DATA: in std_logic_vector(62 downto 0);
TRIG0: in std_logic_vector(14 downto 0);
TRIG1: in std_logic_vector(7 downto 0);
TRIG2: in std_logic_vector(5 downto 0);
TRIG3: in std_logic_vector(15 downto 0);
TRIG_OUT: out std_logic);
END CSP_PB_Tracer_ILA;
ARCHITECTURE CSP_PB_Tracer_ILA_a OF CSP_PB_Tracer_ILA IS
BEGIN
END CSP_PB_Tracer_ILA_a;
| apache-2.0 |
nsensfel/tabellion | data/test/combinational_processes/valid.vhd | 1 | 3097 | library IEEE;
use IEEE.std_logic_1164.all;
entity valid is
port
(
ip0, ip1, ip2, ip3: in std_logic;
op0, op1, op2, op3: out std_logic
);
end;
architecture RTL of valid is
type enum_t is (V0, V1, V2, V3);
signal s0, s1, s2, s3: std_logic;
signal st0: enum_t;
signal n0, n1, n2, n3: natural range 0 to 3;
begin
s0 <= s1; -- $SOL:0:0$
s0 <= (s1 and s2); -- $SOL:1:0$
process (s0, s1) -- $SOL:2:0$
begin
case s1 is
when '0' =>
op0 <= s0;
when others =>
op0 <= s1;
end case;
end process;
process (s0, s1) -- $SOL:3:0$
begin
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
end case;
end process;
process (s0, s1) -- $SOL:4:0$
begin
op2 <= '0';
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
op2 <= '1';
end case;
end process;
process (s0, s1, s2) -- $SOL:5:0$
begin
op2 <= '0';
case s1 is
when '0' =>
if (s2 = '0')
then
op0 <= s0;
else
op0 <= s1;
end if;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
op2 <= '1';
end case;
end process;
with ip0 select -- $SOL:6:0$
s1 <=
ip1 when '0',
ip2 when '1',
ip3 when others;
with st0 select -- $SOL:7:0$
s2 <=
ip1 when V0,
ip2 when V1,
ip3 when V2,
s1 when V3;
with st0 select -- $SOL:8:0$
s2 <=
ip1 when V0,
ip2 when V1,
ip3 when others;
process (s0, s1, s2, s3) -- $SOL:9:0$
begin
case st0 is
when V3 =>
op0 <= s0;
when V2 =>
op0 <= s1;
when V1 =>
op0 <= s2;
when V0 =>
op0 <= s3;
end case;
end process;
process (s0, s1, s2, s3) -- $SOL:10:0$
begin
case st0 is
when V3 =>
op0 <= s0;
when V2 =>
op0 <= s1;
when others =>
op0 <= s2;
end case;
end process;
process (n0, n2) -- $SOL:11:0$
begin
case n0 is
when 0 =>
n1 <= 0;
when 1 to 2 =>
n1 <= n2;
when 3 =>
n1 <= 2;
end case;
end process;
process (n0, n2) -- $SOL:12:0$
begin
case n0 is
when 0 =>
n1 <= 0;
when 1 =>
n1 <= n3;
when 2 =>
n1 <= n2;
when 3 =>
n1 <= 2;
end case;
end process;
process (n0, n3) -- $SOL:13:0$
begin
case n0 is
when 0 =>
n1 <= 0;
when 1 =>
n1 <= n3;
when others =>
n1 <= n3;
end case;
end process;
end;
| apache-2.0 |
mithro/vhdl-triple-buffer | hdl/triple_buffer_arbiter_tb.vhd | 1 | 8306 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:39:58 07/06/2014
-- Design Name:
-- Module Name: /home/tansell/foss/buffer/hdl/triple_buffer_arbiter_tb.vhd
-- Project Name: buffer
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: triple_buffer_arbiter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY triple_buffer_arbiter_tb IS
END triple_buffer_arbiter_tb;
ARCHITECTURE behavior OF triple_buffer_arbiter_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT triple_buffer_arbiter
generic (
offset : integer;
size : integer;
addr : integer := 32);
PORT(
input_clk : IN std_logic;
output_clk : IN std_logic;
input_addr : OUT unsigned(7 downto 0);
output_addr : OUT unsigned(7 downto 0);
rst : IN std_logic);
END COMPONENT;
--Inputs
signal input_clk : std_logic := '0';
signal output_clk : std_logic := '0';
signal rst : std_logic := '0';
signal evt : std_logic := '0';
--Outputs
signal input_addr : unsigned(7 downto 0);
signal expected_input_addr : unsigned(7 downto 0);
signal output_addr : unsigned(7 downto 0);
signal expected_output_addr : unsigned(7 downto 0);
-- Clock period definitions
constant addr_delay : time := 5 ns;
constant buffer0_addr : unsigned(7 downto 0) := to_unsigned(100, 8);
constant buffer1_addr : unsigned(7 downto 0) := to_unsigned(120, 8);
constant buffer2_addr : unsigned(7 downto 0) := to_unsigned(140, 8);
BEGIN
evt <= rst or input_clk or output_clk;
-- Instantiate the Unit Under Test (UUT)
uut: triple_buffer_arbiter
GENERIC MAP (
offset => 100,
size => 20,
addr => 8)
PORT MAP (
input_clk => input_clk,
output_clk => output_clk,
input_addr => input_addr,
output_addr => output_addr,
rst => rst);
-- Stimulus process
stim_proc: process
procedure Reset is
begin
wait for 35 ns;
expected_input_addr <= "UUUUUUUU";
expected_output_addr <= "UUUUUUUU";
rst <= '1';
wait for 1 ns;
rst <= '0';
wait for 35 ns;
end procedure;
procedure ExpectedInputAddr(
constant expected_value : unsigned(7 downto 0)) is
begin
wait for 5 ns;
input_clk <= '1';
wait for addr_delay;
expected_input_addr <= expected_value;
end procedure;
procedure ExpectedInputClear is
begin
wait for 5 ns;
input_clk <= '0';
expected_input_addr <= "UUUUUUUU";
end procedure;
procedure ExpectedOutputAddr(
constant expected_value : unsigned(7 downto 0)) is
begin
wait for 5 ns;
output_clk <= '1';
wait for addr_delay;
expected_output_addr <= expected_value;
end procedure;
procedure ExpectedOutputClear is
begin
wait for 5 ns;
output_clk <= '0';
expected_output_addr <= "UUUUUUUU";
end procedure;
begin
Reset;
-- Write starts, should go to buffer0
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
-- Write starts, should go to buffer1
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
-- Write starts, should go to buffer2
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
-- Write starts, should go to buffer0
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
-------------------------------------------------------------------
-- Finished the initial write tests
Reset;
-------------------------------------------------------------------
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
-- Read, should get the last input_addr
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
-- Make sure read keeps getting the same addr
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
-- Advance the input buffer
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
-- Read should have advanced to the next addr
ExpectedOutputAddr(buffer1_addr);
ExpectedOutputClear;
ExpectedOutputAddr(buffer1_addr);
ExpectedOutputClear;
-- Go around the buffer
----
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
--
ExpectedOutputAddr(buffer2_addr);
ExpectedOutputClear;
ExpectedOutputAddr(buffer2_addr);
ExpectedOutputClear;
----
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
--
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
----
Reset;
-- Write starts, should go to buffer0
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
ExpectedInputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedOutputAddr(buffer1_addr);
ExpectedOutputClear;
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedOutputAddr(buffer2_addr);
ExpectedOutputClear;
ExpectedOutputAddr(buffer2_addr);
ExpectedOutputClear;
ExpectedInputClear;
ExpectedOutputAddr(buffer0_addr);
ExpectedOutputClear;
-------------------------------------------------------------------
-- Finished the initial read tests
Reset;
-------------------------------------------------------------------
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
-- Start reading from the first buffer, make sure the writer bounced
-- between the two remaining buffers
ExpectedOutputAddr(buffer0_addr);
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
-- Release the reader, should write to buffer0 now
ExpectedOutputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
-- Try again, except reading from buffer2
ExpectedOutputAddr(buffer2_addr);
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedOutputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer2_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer1_addr);
ExpectedInputClear;
ExpectedInputAddr(buffer0_addr);
ExpectedInputClear;
--
Reset;
wait;
end process;
END;
| apache-2.0 |
davelab6/fontdirectory.github.io | static/bower_components/ace-builds/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_xadc_wiz_0_0/system_xadc_wiz_0_0_axi_xadc.vhd | 1 | 50598 |
-------------------------------------------------------------------------------
-- system_xadc_wiz_0_0_axi_xadc.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010, 2013 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
-------------------------------------------------------------------------------
-- File : system_xadc_wiz_0_0_axi_xadc.vhd
-- Version : v3.0
-- Description : XADC macro with AXI bus interface
-- Standard : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- axi_xadc.vhd
-- -system_xadc_wiz_0_0_xadc_core_drp.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_arith.unsigned;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.and_reduce;
use IEEE.std_logic_misc.or_reduce;
library work;
use work.system_xadc_wiz_0_0_ipif_pkg.all;
use work.system_xadc_wiz_0_0_soft_reset;
use work.system_xadc_wiz_0_0_ipif_pkg.calc_num_ce;
use work.system_xadc_wiz_0_0_ipif_pkg.INTEGER_ARRAY_TYPE;
use work.system_xadc_wiz_0_0_ipif_pkg.SLV64_ARRAY_TYPE;
use work.system_xadc_wiz_0_0_ipif_pkg.INTR_POS_EDGE_DETECT;
use work.system_xadc_wiz_0_0_proc_common_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
--------------------
-- AXI LITE Generics
--------------------
-- C_BASEADDR -- Base Address
-- C_HIGHADDR -- high address
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_FAMILY -- Target FPGA family, Virtex 6 only
-- C_INCLUDE_INTR -- inclusion of interrupt
-- C_SIM_MONITOR_FILE -- simulation file
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-------------------------------------------------------------------------------
-- Note: the unused signals in the port name lists are not listed here.
-------------------------------------------------------------------------------
-- SYSMON EXTERNAL INTERFACE -- INPUT Signals
-------------------------------------------------------------------------------
-- VAUXN -- Sixteen auxiliary analog input pairs
-- VAUXP -- low bandwidth differential analog inputs
-- CONVST -- Conversion start signal for event-driven sampling mode
-------------------------------------------------------------------------------
-- SYSMON EXTERNAL INTERFACE -- OUTPUT Signals
-------------------------------------------------------------------------------
-- ip2intc_irpt -- Interrupt to processor
-- alarm_out -- SYSMON alarm output signals of the hard macro
-------------------------------------------------------------------------------
entity system_xadc_wiz_0_0_axi_xadc is
generic
(
-----------------------------------------
-- C_BASEADDR : std_logic_vector := X"FFFF_FFFF";
-- C_HIGHADDR : std_logic_vector := X"0000_0000";
-----------------------------------------
-- AXI slave single block generics
C_INSTANCE : string := "system_xadc_wiz_0_0_axi_xadc";
C_FAMILY : string := "virtex7";
C_S_AXI_ADDR_WIDTH : integer range 2 to 32 := 11;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-----------------------------------------
-- SYSMON Generics
C_INCLUDE_INTR : integer range 0 to 1 := 1;
C_SIM_MONITOR_FILE : string := "design.txt"
);
port
(
-- System interface
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- AXI Write address channel signals
s_axi_awaddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- AXI Write data channel signals
s_axi_wdata : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_wstrb : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- AXI Write response channel signals
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- AXI Read address channel signals
s_axi_araddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- AXI Read address channel signals
s_axi_rdata : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Input to the system from the axi_xadc core
ip2intc_irpt : out std_logic;
-- XADC External interface signals
-- Conversion start control signal for Event driven mode
vauxp0 : in STD_LOGIC; -- Auxiliary Channel 0
vauxn0 : in STD_LOGIC;
vauxp1 : in STD_LOGIC; -- Auxiliary Channel 1
vauxn1 : in STD_LOGIC;
vauxp2 : in STD_LOGIC; -- Auxiliary Channel 2
vauxn2 : in STD_LOGIC;
vauxp4 : in STD_LOGIC; -- Auxiliary Channel 4
vauxn4 : in STD_LOGIC;
vauxp5 : in STD_LOGIC; -- Auxiliary Channel 5
vauxn5 : in STD_LOGIC;
vauxp6 : in STD_LOGIC; -- Auxiliary Channel 6
vauxn6 : in STD_LOGIC;
vauxp7 : in STD_LOGIC; -- Auxiliary Channel 7
vauxn7 : in STD_LOGIC;
vauxp9 : in STD_LOGIC; -- Auxiliary Channel 9
vauxn9 : in STD_LOGIC;
vauxp10 : in STD_LOGIC; -- Auxiliary Channel 10
vauxn10 : in STD_LOGIC;
vauxp12 : in STD_LOGIC; -- Auxiliary Channel 12
vauxn12 : in STD_LOGIC;
vauxp13 : in STD_LOGIC; -- Auxiliary Channel 13
vauxn13 : in STD_LOGIC;
vauxp14 : in STD_LOGIC; -- Auxiliary Channel 14
vauxn14 : in STD_LOGIC;
vauxp15 : in STD_LOGIC; -- Auxiliary Channel 15
vauxn15 : in STD_LOGIC;
busy_out : out STD_LOGIC; -- ADC Busy signal
channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
eoc_out : out STD_LOGIC; -- End of Conversion Signal
eos_out : out STD_LOGIC; -- End of Sequence Signal
alarm_out : out STD_LOGIC_VECTOR (7 downto 0); -- OR'ed output of all the Alarms
temp_out : out std_logic_vector(11 downto 0);
vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair
vn_in : in STD_LOGIC
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of s_axi_aclk : signal is "10000";
ATTRIBUTE MAX_FANOUT of s_axi_aresetn : signal is "10000";
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
ATTRIBUTE HDL : string;
ATTRIBUTE HDL of system_xadc_wiz_0_0_axi_xadc : entity is "VHDL";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE of system_xadc_wiz_0_0_axi_xadc : entity is "PERIPHERAL";
ATTRIBUTE IP_GROUP : string;
ATTRIBUTE IP_GROUP of system_xadc_wiz_0_0_axi_xadc : entity is "LOGICORE";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS of s_axi_aclk : signal is "Clk";
ATTRIBUTE SIGIS of s_axi_aresetn : signal is "Rst";
ATTRIBUTE SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
-----------------------------------------------------------------
-- end of PSFUtil MPD attributes
-----------------------------------------------------------------
end entity system_xadc_wiz_0_0_axi_xadc;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of system_xadc_wiz_0_0_axi_xadc is
component system_xadc_wiz_0_0_xadc_core_drp
generic
(
----------------
C_S_AXI_ADDR_WIDTH : integer;
C_S_AXI_DATA_WIDTH : integer;
C_FAMILY : string;
----------------
CE_NUMBERS : integer;
IP_INTR_NUM : integer;
C_SIM_MONITOR_FILE : string ;
----------------
MUX_ADDR_NO : integer
);
port
(
-- IP Interconnect (IPIC) port signals ---------
Bus2IP_Clk : in std_logic;
Bus2IP_Rst : in std_logic;
-- Bus 2 IP IPIC interface
Bus2IP_RdCE : in std_logic_vector(0 to CE_NUMBERS-1);
Bus2IP_WrCE : in std_logic_vector(0 to CE_NUMBERS-1);
Bus2IP_Addr : in std_logic_vector(0 to (C_S_AXI_ADDR_WIDTH-1));
Bus2IP_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
-- IP 2 Bus IPIC interface
Sysmon_IP2Bus_Data : out std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
Sysmon_IP2Bus_WrAck : out std_logic;
Sysmon_IP2Bus_RdAck : out std_logic;
---------------- interrupt interface with the system -----------
Interrupt_status : out std_logic_vector(0 to IP_INTR_NUM-1);
---------------- sysmon macro interface -------------------
vauxp0 : in STD_LOGIC; -- Auxiliary Channel 0
vauxn0 : in STD_LOGIC;
vauxp1 : in STD_LOGIC; -- Auxiliary Channel 1
vauxn1 : in STD_LOGIC;
vauxp2 : in STD_LOGIC; -- Auxiliary Channel 2
vauxn2 : in STD_LOGIC;
vauxp4 : in STD_LOGIC; -- Auxiliary Channel 4
vauxn4 : in STD_LOGIC;
vauxp5 : in STD_LOGIC; -- Auxiliary Channel 5
vauxn5 : in STD_LOGIC;
vauxp6 : in STD_LOGIC; -- Auxiliary Channel 6
vauxn6 : in STD_LOGIC;
vauxp7 : in STD_LOGIC; -- Auxiliary Channel 7
vauxn7 : in STD_LOGIC;
vauxp9 : in STD_LOGIC; -- Auxiliary Channel 9
vauxn9 : in STD_LOGIC;
vauxp10 : in STD_LOGIC; -- Auxiliary Channel 10
vauxn10 : in STD_LOGIC;
vauxp12 : in STD_LOGIC; -- Auxiliary Channel 12
vauxn12 : in STD_LOGIC;
vauxp13 : in STD_LOGIC; -- Auxiliary Channel 13
vauxn13 : in STD_LOGIC;
vauxp14 : in STD_LOGIC; -- Auxiliary Channel 14
vauxn14 : in STD_LOGIC;
vauxp15 : in STD_LOGIC; -- Auxiliary Channel 15
vauxn15 : in STD_LOGIC;
busy_out : out STD_LOGIC; -- ADC Busy signal
channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
eoc_out : out STD_LOGIC; -- End of Conversion Signal
eos_out : out STD_LOGIC; -- End of Sequence Signal
alarm_out : out STD_LOGIC_VECTOR (7 downto 0);
temp_out : out std_logic_vector(11 downto 0);
vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair
vn_in : in STD_LOGIC
);
end component;
-------------------------------------------------------------------------------
-- Function Declarations starts
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function: add_intr_ard_addr_range_array
-------------------------------------------------------------------------------
-- Add the interrupt base and high address to ARD_ADDR_RANGE_ARRAY, if
-- C_INCLUDE_INTR is = 1
-------------------------------------------------------------------------------
function add_intr_ard_addr_range_array
(include_intr : integer;
USER_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE;
INTR_USER_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
)
return SLV64_ARRAY_TYPE is
begin
if include_intr = 1 then
return INTR_USER_ARD_ADDR_RANGE_ARRAY;
else
return USER_ARD_ADDR_RANGE_ARRAY;
end if;
end function add_intr_ard_addr_range_array;
-------------------------------------------------------------------------------
-- Function: add_intr_ce_range_array
-------------------------------------------------------------------------------
-- This function is used to add the 16 interrupts in the NUM_CE range array, if
-- C_INCLUDE_INTR is = 1
-------------------------------------------------------------------------------
function add_intr_ce_range_array
(include_intr : integer;
USER_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE;
INTR_USER_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
)
return INTEGER_ARRAY_TYPE is
begin
if include_intr = 1 then
return INTR_USER_ARD_NUM_CE_ARRAY;
else
return USER_ARD_NUM_CE_ARRAY;
end if;
end function add_intr_ce_range_array;
-------------------------------------------------------------------------------
-- Function Declaration ends
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declaration Starts
-------------------------------------------------------------------------------
-- AXI lite parameters
constant C_BASEADDR : std_logic_vector := X"0000_0000";
--constant C_BASEADDR : std_logic_vector := X"FFFF_FFFF";
constant C_HIGHADDR : std_logic_vector := X"0000_0000";
constant C_S_AXI_SYSMON_MIN_SIZE : std_logic_vector(31 downto 0):= X"000003FF";
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 64;
--constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_S_AXI_ADDR_WIDTH-1)
-- := (others => '0');
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-32-1) := (others => '0');
constant INTERRUPT_NO : natural := 17; -- changed from 10 to 17 for adding
-- falling edge interrupts
constant C_INTR_CE_NUM : integer := 16; -- this is fixed for interrupt controller
constant MUX_ADDR_NO : integer := 5; -- added for XADC
-------------------------------------------------------------------------------
-- The local register array contains
-- 1. Software Reset Register (SRR), -- address C_BASEADDR + 0x00
-- 2. Status Register (SR), -- address C_BASEADDR + 0x04
-- 3. Alarm Output Status Register (AOSR), -- address C_BASEADDR + 0x08
-- 4. CONVST Register (CONVSTR), -- address C_BASEADDR + 0x0C
-- 5. SYSMON Reset Register (SYSMONRR). -- address C_BASEADDR + 0x10
-- All registers are 32 bit width and their addresses are at word boundry.
-------------------------------------------------------------------------------
constant LOCAL_REG_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant LOCAL_REG_HIGHADDR : std_logic_vector := C_BASEADDR or X"0000001F";
-------------------------------------------------------------------------------
-- The interrupt registers to be added if C_INCLUDE_INTR = 1
-------------------------------------------------------------------------------
constant INTR_BASEADDR : std_logic_vector := C_BASEADDR or X"00000040";
constant INTR_HIGHADDR : std_logic_vector := C_BASEADDR or x"0000007F";
-------------------------------------------------------------------------------
-- The address range is devided in the range of Status & Control registers
-- there are total 128 registers. First 64 are the status and remaning 64 are
-- control registers
-------------------------------------------------------------------------------
constant REG_FILE_BASEADDR : std_logic_vector := C_BASEADDR or X"00000200";
constant REG_FILE_HIGHADDR : std_logic_vector := C_BASEADDR or X"000003FF";
-------------------------------------------------------------------------------
--The address ranges for the registers are defined in USER_ARD_ADDR_RANGE_ARRAY
-------------------------------------------------------------------------------
constant USER_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & LOCAL_REG_BASEADDR,
ZERO_ADDR_PAD & LOCAL_REG_HIGHADDR,
ZERO_ADDR_PAD & REG_FILE_BASEADDR,
ZERO_ADDR_PAD & REG_FILE_HIGHADDR
);
constant INTR_USER_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & LOCAL_REG_BASEADDR,
ZERO_ADDR_PAD & LOCAL_REG_HIGHADDR,
ZERO_ADDR_PAD & INTR_BASEADDR,
ZERO_ADDR_PAD & INTR_HIGHADDR,
ZERO_ADDR_PAD & REG_FILE_BASEADDR,
ZERO_ADDR_PAD & REG_FILE_HIGHADDR
);
-------------------------------------------------------------------------------
-- The USER_ARD_ADDR_RANGE_ARRAY is subset of ARD_ADDR_RANGE_ARRAY based on the
-- C_INCLUDE_INTR parameter value.
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
add_intr_ard_addr_range_array(
C_INCLUDE_INTR,
USER_ARD_ADDR_RANGE_ARRAY,
INTR_USER_ARD_ADDR_RANGE_ARRAY
);
-------------------------------------------------------------------------------
--The total 128 DRP register address space is divided in two 64 register arrays
--The status and control registers are equally divided in the range to generate
--the chip enable signals.
--There are some local alarm registers, conversion start registers, ip reset
--registers present in the design.
--the no. of CE's required is defined in USER_ARD_NUM_CE_ARRAY array
-------------------------------------------------------------------------------
constant USER_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 8, -- 5 chip enable + 3 dummy
-- CS_0 & CE_0 => SRR -- Addr = 00
-- CS_0 & CE_1 => SR -- Addr = 04
-- CS_0 & CE_2 => AOSR -- Addr = 08
-- CS_0 & CE_3 => CONVSTR -- Addr = 0C
-- CS_0 & CE_4 => SYSMONRR -- Addr = 10
-- CS_0 & CE_5 => dummy -- Addr = 14
-- CS_0 & CE_6 => dummy -- Addr = 18
-- CS_0 & CE_7 => dummy -- Addr = 1C
1 => 1--, -- 1 chip enable
-- CS_1 & CE_8 => 1 CE required to access DRP
);
constant INTR_USER_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 8, -- 5 chip enable + 3 dummy
-- CS_0 & CE_0 => SRR -- Addr = 00
-- CS_0 & CE_1 => SR -- Addr = 04
-- CS_0 & CE_2 => AOSR -- Addr = 08
-- CS_0 & CE_3 => CONVSTR -- Addr = 0C
-- CS_0 & CE_4 => SYSMONRR -- Addr = 10
-- CS_0 & CE_5 => dummy -- Addr = 14
-- CS_0 & CE_6 => dummy -- Addr = 18
-- CS_0 & CE_7 => dummy -- Addr = 1C
1 => 16, -- 16 chip enable
-- CS_1 & CE_15 => GIER -- Addr = 5C
-- CS_1 & CE_16 => IPISR -- Addr = 60
-- CS_1 & CE_18 => IPIER -- Addr = 68
-- Following commented code is for reference with execution of above function
2 => 1 -- 1 chip enable -- addr = 200 to 3FF
-- CS_2 & CE_24 => 1 CE required to access DRP
);
-------------------------------------------------------------------------------
-- The USER_ARD_NUM_CE_ARRAY is subset of ARD_NUM_CE_ARRAY based on the
-- C_INCLUDE_INTR parameter value.
-------------------------------------------------------------------------------
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
add_intr_ce_range_array(
C_INCLUDE_INTR,
USER_ARD_NUM_CE_ARRAY,
INTR_USER_ARD_NUM_CE_ARRAY
);
-------------------------------------------------------------------------------
-- Eight interrupts
-------------------------------------------------------------------------------
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to INTERRUPT_NO-1):=
(
others => INTR_POS_EDGE_DETECT
);
-------------------------------------------------------------------------------
-- Calculating index for interrupt logic
-------------------------------------------------------------------------------
constant SWRESET : natural := 0;
constant INTR_LO : natural := 0;
constant INTR_HI : natural := 15;
constant CS_NUMBERS : integer :=((ARD_ADDR_RANGE_ARRAY'LENGTH/2));
constant RD_CE_NUMBERS : integer :=(calc_num_ce(ARD_NUM_CE_ARRAY));
constant WR_CE_NUMBERS : integer :=(calc_num_ce(ARD_NUM_CE_ARRAY));
constant IP_INTR_MODE_ARRAY_NUM : integer := IP_INTR_MODE_ARRAY'length;
constant RDCE_WRCE_SYSMON_CORE : integer := 9;
--------------------------------------------------------------------------------
-- Constant Declaration Ends
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Signal and Type Declarations
--------------------------------------------------------------------------------
--bus2ip signals
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
---
signal bus2ip_rdce : std_logic_vector((RD_CE_NUMBERS-1)downto 0);
signal bus2ip_rdce_int : std_logic_vector(0 to (RD_CE_NUMBERS-1));
signal bus2ip_rdce_xadc_core : std_logic_vector(0 to (RDCE_WRCE_SYSMON_CORE-1));
---
signal bus2ip_wrce : std_logic_vector((WR_CE_NUMBERS-1)downto 0);
signal bus2ip_wrce_int : std_logic_vector(0 to (WR_CE_NUMBERS-1));
signal bus2ip_wrce_xadc_core : std_logic_vector(0 to (RDCE_WRCE_SYSMON_CORE-1));
---
signal bus2ip_addr : std_logic_vector((C_S_AXI_ADDR_WIDTH-1)downto 0);
signal bus2ip_addr_int : std_logic_vector(0 to (C_S_AXI_ADDR_WIDTH-1));
---
signal bus2ip_be : std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
signal bus2ip_be_int : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH/8)-1);
---
signal bus2ip_data : std_logic_vector(((C_S_AXI_DATA_WIDTH)-1)downto 0);
signal bus2ip_data_int : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
-- ip2bus signals
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1)downto 0)
:= (others => '0');
signal ip2bus_data_int : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
signal ip2bus_data_int1 : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
---
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
signal ip2bus_wrack_int1 : std_logic;
signal ip2bus_rdack_int1 : std_logic;
signal ip2bus_error_int1 : std_logic;
signal xadc_ip2bus_data : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
signal xadc_ip2bus_wrack : std_logic;
signal xadc_ip2bus_rdack : std_logic;
-- signal xadc_ip2bus_error : std_logic;
signal interrupt_status_i : std_logic_vector(0 to (IP_INTR_MODE_ARRAY_NUM-1));
signal intr_ip2bus_data : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
signal intr_ip2bus_wrack : std_logic;
signal intr_ip2bus_rdack : std_logic;
signal intr_ip2bus_error : std_logic;
-- Software Reset Signals
signal reset2ip_reset : std_logic := '0';
signal rst_ip2bus_wrack : std_logic;
signal rst_ip2bus_error : std_logic;
signal rst_ip2bus_rdack : std_logic;
signal rst_ip2bus_rdack_d1 : std_logic;
-- following signals are used to impleemnt the register access rule
signal and_reduce_be : std_logic;
signal partial_reg_access_error : std_logic;
signal bus2ip_reset_active_low : std_logic;
signal bus2ip_reset_active_high: std_logic;
--------------------------------------------
signal dummy_local_reg_rdack_d1 : std_logic;
signal dummy_local_reg_rdack : std_logic;
signal dummy_local_reg_wrack_d1 : std_logic;
signal dummy_local_reg_wrack : std_logic;
signal bus2ip_rdce_intr : std_logic_vector(INTR_LO to INTR_HI);
signal bus2ip_wrce_intr : std_logic_vector(INTR_LO to INTR_HI);
-------------------------------------------------------------------------------
-- Architecture begins
-------------------------------------------------------------------------------
begin
--------------------------------------------
-- INSTANTIATE AXI SLAVE SINGLE
--------------------------------------------
AXI_LITE_IPIF_I : entity work.system_xadc_wiz_0_0_axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_SYSMON_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
s_axi_aclk => s_axi_aclk, -- in
s_axi_aresetn => s_axi_aresetn, -- in
s_axi_awaddr => s_axi_awaddr, -- in
s_axi_awvalid => s_axi_awvalid, -- in
s_axi_awready => s_axi_awready, -- out
s_axi_wdata => s_axi_wdata, -- in
s_axi_wstrb => s_axi_wstrb, -- in
s_axi_wvalid => s_axi_wvalid, -- in
s_axi_wready => s_axi_wready, -- out
s_axi_bresp => s_axi_bresp, -- out
s_axi_bvalid => s_axi_bvalid, -- out
s_axi_bready => s_axi_bready, -- in
s_axi_araddr => s_axi_araddr, -- in
s_axi_arvalid => s_axi_arvalid, -- in
s_axi_arready => s_axi_arready, -- out
s_axi_rdata => s_axi_rdata, -- out
s_axi_rresp => s_axi_rresp, -- out
s_axi_rvalid => s_axi_rvalid, -- out
s_axi_rready => s_axi_rready, -- in
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- out
Bus2IP_Resetn => bus2ip_reset_active_low, -- out
Bus2IP_Addr => bus2ip_addr, -- out
Bus2IP_RNW => open, -- out
Bus2IP_BE => bus2ip_be, -- out
Bus2IP_CS => open, -- out
Bus2IP_RdCE => bus2ip_rdce, -- out
Bus2IP_WrCE => bus2ip_wrce, -- out
Bus2IP_Data => bus2ip_data, -- out
IP2Bus_Data => ip2bus_data, -- in
IP2Bus_WrAck => ip2bus_wrack, -- in
IP2Bus_RdAck => ip2bus_rdack, -- in
IP2Bus_Error => ip2bus_error -- in
);
-------------------------------------------------------------------------------
-------------------------------
bus2ip_rdce_int <= bus2ip_rdce;
-------------------------------
bus2ip_wrce_int <= bus2ip_wrce;
-------------------------------
ip2bus_data <= ip2bus_data_int;
-------------------------------
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset_active_high <= not(bus2ip_reset_active_low);
end if;
end process REG_RESET_FROM_IPIF;
----------------------
-------------------------------------------------------------------------------
-------------------- when interrupt is used.
RDCE_WRCE_GEN_I: if (C_INCLUDE_INTR = 1) generate
-----------------
--------
begin
--------
bus2ip_rdce_intr <= bus2ip_rdce_int -- (25-16=8) to (25-2=23)
(((RD_CE_NUMBERS-C_INTR_CE_NUM)-1)to (RD_CE_NUMBERS-2));
bus2ip_wrce_intr <= bus2ip_wrce_int -- (25-16=8) to (25-2=23)
(((WR_CE_NUMBERS-C_INTR_CE_NUM)-1)to (WR_CE_NUMBERS-2));
bus2ip_rdce_xadc_core <= bus2ip_rdce_int -- 0 to ((25-16=8)-2)=7
((RD_CE_NUMBERS-RD_CE_NUMBERS)to
((RD_CE_NUMBERS-C_INTR_CE_NUM)-2)
)
& -- 24 = last rdce
bus2ip_rdce_int(RD_CE_NUMBERS-1);
bus2ip_wrce_xadc_core <= bus2ip_wrce_int -- 0 to ((25-16=8)-1)=7
((WR_CE_NUMBERS-WR_CE_NUMBERS)to
((WR_CE_NUMBERS-C_INTR_CE_NUM)-2)
)
& -- 24 = last wrce
bus2ip_wrce_int(WR_CE_NUMBERS-1);
end generate RDCE_WRCE_GEN_I;
-----------------------------
-------------------------------------------------------------------------------
-------------------- when interrupt is NOT used.
RDCE_WRCE_NOT_GEN_I: if (C_INCLUDE_INTR = 0) generate
-----------------
--------
begin
--------
bus2ip_rdce_xadc_core <= bus2ip_rdce_int;
bus2ip_wrce_xadc_core <= bus2ip_wrce_int;
end generate RDCE_WRCE_NOT_GEN_I;
---------------------------------
-------------------------------------------------------------------------------
--------------------------------------------
-- XADC_CORE_I: INSTANTIATE XADC CORE
--------------------------------------------
AXI_XADC_CORE_I : system_xadc_wiz_0_0_xadc_core_drp
generic map
(
---------------- -------------------------
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_FAMILY => C_FAMILY,
---------------- -------------------------
CE_NUMBERS => RDCE_WRCE_SYSMON_CORE,
IP_INTR_NUM => IP_INTR_MODE_ARRAY_NUM,
C_SIM_MONITOR_FILE => C_SIM_MONITOR_FILE,
------------------ -------------------------
MUX_ADDR_NO => MUX_ADDR_NO
)
port map
(
-- IP Interconnect (IPIC) port signals ---------
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Rst => reset2ip_reset,
Bus2IP_RdCE => bus2ip_rdce_xadc_core,
Bus2IP_WrCE => bus2ip_wrce_xadc_core,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
-- ip2bus signals ------------------------------
Sysmon_IP2Bus_Data => xadc_ip2bus_data,
Sysmon_IP2Bus_WrAck => xadc_ip2bus_wrack,
Sysmon_IP2Bus_RdAck => xadc_ip2bus_rdack,
Interrupt_status => interrupt_status_i,
--- external interface signals ------------------
vauxp0 => vauxp0,
vauxn0 => vauxn0,
vauxp1 => vauxp1,
vauxn1 => vauxn1,
vauxp2 => vauxp2,
vauxn2 => vauxn2,
vauxp4 => vauxp4,
vauxn4 => vauxn4,
vauxp5 => vauxp5,
vauxn5 => vauxn5,
vauxp6 => vauxp6,
vauxn6 => vauxn6,
vauxp7 => vauxp7,
vauxn7 => vauxn7,
vauxp9 => vauxp9,
vauxn9 => vauxn9,
vauxp10 => vauxp10,
vauxn10 => vauxn10,
vauxp12 => vauxp12,
vauxn12 => vauxn12,
vauxp13 => vauxp13,
vauxn13 => vauxn13,
vauxp14 => vauxp14,
vauxn14 => vauxn14,
vauxp15 => vauxp15,
vauxn15 => vauxn15,
busy_out => busy_out,
channel_out => channel_out,
eoc_out => eoc_out,
eos_out => eos_out,
alarm_out => alarm_out,
temp_out => temp_out,
vp_in => vp_in,
vn_in => vn_in
);
----------------------------------------------------------
-- SOFT_RESET_I: INSTANTIATE SOFTWARE RESET REGISTER (SRR)
----------------------------------------------------------
SOFT_RESET_I: entity work.system_xadc_wiz_0_0_soft_reset
generic map
(
C_SIPIF_DWIDTH => C_S_AXI_DATA_WIDTH,
-- Width of triggered reset in Bus Clocks
C_RESET_WIDTH => 16
)
port map
(
-- Inputs From the AXI Slave Single Bus
Bus2IP_Reset => bus2ip_reset_active_high, -- in
Bus2IP_Clk => bus2ip_clk, -- in
Bus2IP_WrCE => bus2ip_wrce_int(SWRESET), -- in
Bus2IP_Data => bus2ip_data, -- in
Bus2IP_BE => bus2ip_be, -- in
-- Final Device Reset Output
Reset2IP_Reset => reset2ip_reset, -- out
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck => rst_ip2bus_wrack, -- out
Reset2Bus_Error => rst_ip2bus_error, -- out
Reset2Bus_ToutSup => open -- out
);
------------------------------------------------------------
-- INSTANTIATE INTERRUPT CONTROLLER MODULE (IPISR,IPIER,GIER)
------------------------------------------------------------
-- INTR_CTRLR_GEN_I: Generate logic to be used to pass signals,
-------------------- when interrupt is used.
INTR_CTRLR_GEN_I: if (C_INCLUDE_INTR = 1) generate
-----------------
--------
signal bus2ip_rdce_intr_int : std_logic_vector(INTR_LO to INTR_HI);
signal bus2ip_wrce_intr_int : std_logic_vector(INTR_LO to INTR_HI);
signal dummy_bus2ip_rdce_intr : std_logic;
signal dummy_bus2ip_wrce_intr : std_logic;
signal dummy_intr_reg_rdack_d1: std_logic;
signal dummy_intr_reg_rdack : std_logic;
signal dummy_intr_reg_wrack_d1: std_logic;
signal dummy_intr_reg_wrack : std_logic;
--------
begin
--------
bus2ip_rdce_intr_int <= "0000000" &
bus2ip_rdce_intr(7 to 8) &
"0" &
bus2ip_rdce_intr(10) &
"00000";
bus2ip_wrce_intr_int <= "0000000" &
bus2ip_wrce_intr(7 to 8) &
"0" &
bus2ip_wrce_intr(10) &
"00000";
dummy_bus2ip_rdce_intr <= or_reduce(bus2ip_rdce_intr(0 to 6)) or
bus2ip_rdce_intr(9) or
or_reduce(bus2ip_rdce_intr(11 to 15));
dummy_bus2ip_wrce_intr <= or_reduce(bus2ip_wrce_intr(0 to 6)) or
bus2ip_wrce_intr(9) or
or_reduce(bus2ip_wrce_intr(11 to 15));
---------------------------------------------
DUMMY_INTR_RD_WR_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (bus2ip_clk'event and bus2ip_clk = '1') then
if (reset2ip_reset = RESET_ACTIVE) then
dummy_intr_reg_rdack_d1 <= '0';
dummy_intr_reg_rdack <= '0';
dummy_intr_reg_wrack_d1 <= '0';
dummy_intr_reg_wrack <= '0';
else
dummy_intr_reg_rdack_d1 <= dummy_bus2ip_rdce_intr;
dummy_intr_reg_rdack <= dummy_bus2ip_rdce_intr and
(not dummy_intr_reg_rdack_d1);
dummy_intr_reg_wrack_d1 <= dummy_bus2ip_wrce_intr;
dummy_intr_reg_wrack <= dummy_bus2ip_wrce_intr and
(not dummy_intr_reg_wrack_d1);
end if;
end if;
end process DUMMY_INTR_RD_WR_ACK_GEN_PROCESS;
---------------------------------------------
INTERRUPT_CONTROL_I: entity work.system_xadc_wiz_0_0_interrupt_control
generic map
(
C_NUM_CE => C_INTR_CE_NUM,
C_NUM_IPIF_IRPT_SRC => 1, -- Set to 1 to avoid null array
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_PENCODER => FALSE,
-- Specifies device ISC hierarchy
C_INCLUDE_DEV_ISC => FALSE,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => reset2ip_reset,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Interrupt_RdCE => bus2ip_rdce_intr_int,
Interrupt_WrCE => bus2ip_wrce_intr_int,
IPIF_Reg_Interrupts => "00", -- Tie off the unused reg intr's
IPIF_Lvl_Interrupts => "0", -- Tie off the dummy lvl intr
IP2Bus_IntrEvent => interrupt_status_i,
Intr2Bus_DevIntr => ip2intc_irpt,
Intr2Bus_DBus => intr_ip2bus_data,
Intr2Bus_WrAck => intr_ip2bus_wrack,
Intr2Bus_RdAck => intr_ip2bus_rdack,
Intr2Bus_Error => intr_ip2bus_error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
ip2bus_wrack_int1 <= xadc_ip2bus_wrack or
rst_ip2bus_wrack or
intr_ip2bus_wrack or
dummy_intr_reg_wrack or
dummy_local_reg_wrack;
ip2bus_rdack_int1 <= xadc_ip2bus_rdack or
rst_ip2bus_rdack or
intr_ip2bus_rdack or
dummy_intr_reg_rdack or
dummy_local_reg_rdack;
ip2bus_error_int1 <= rst_ip2bus_error or
intr_ip2bus_error or
partial_reg_access_error;
ip2bus_data_int1 <= xadc_ip2bus_data or
intr_ip2bus_data;
process (Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset = '1') then
ip2bus_wrack <= '0';
ip2bus_rdack <= '0';
ip2bus_error <= '0';
ip2bus_data_int <= (others => '0');
else
ip2bus_wrack <= ip2bus_wrack_int1;
ip2bus_rdack <= ip2bus_rdack_int1;
ip2bus_error <= ip2bus_error_int1;
ip2bus_data_int <= ip2bus_data_int1;
end if;
end if;
end process;
end generate INTR_CTRLR_GEN_I;
------------------------------
-------------------------------------------------------------------------------
-- NO_INTR_CTRLR_GEN_I: Generate logic to be used to pass signals,
----------------------- when interrupt is not used.
NO_INTR_CTRLR_GEN_I : if (C_INCLUDE_INTR = 0) generate
-----
begin
-----
ip2bus_wrack_int1 <= xadc_ip2bus_wrack or
rst_ip2bus_wrack or
dummy_local_reg_wrack;
ip2bus_rdack_int1 <= xadc_ip2bus_rdack or
rst_ip2bus_rdack or
dummy_local_reg_rdack;
ip2bus_error_int1 <= rst_ip2bus_error or
partial_reg_access_error;
ip2bus_data_int1 <= xadc_ip2bus_data;
ip2intc_irpt <= '0';
process (Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset = '1') then
ip2bus_wrack <= '0';
ip2bus_rdack <= '0';
ip2bus_error <= '0';
ip2bus_data_int <= (others => '0');
else
ip2bus_wrack <= ip2bus_wrack_int1;
ip2bus_rdack <= ip2bus_rdack_int1;
ip2bus_error <= ip2bus_error_int1;
ip2bus_data_int <= ip2bus_data_int1;
end if;
end if;
end process;
end generate NO_INTR_CTRLR_GEN_I;
---------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- SW_RESET_REG_READ_ACK_GEN_PROCESS:IMPLEMENT READ ACK LOGIC FOR SOFTWARE
-- RESET MODULE. This is dummy read as read is
-- not allowed on reset core.
------------------------------------------------------------
SW_RESET_REG_READ_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (bus2ip_clk'event and bus2ip_clk = '1') then
if (reset2ip_reset = RESET_ACTIVE) then
rst_ip2bus_rdack_d1 <= '0';
rst_ip2bus_rdack <= '0';
else
rst_ip2bus_rdack_d1 <= bus2ip_rdce_int(SWRESET);
rst_ip2bus_rdack <= bus2ip_rdce_int(SWRESET) and
(not rst_ip2bus_rdack_d1);
end if;
end if;
end process SW_RESET_REG_READ_ACK_GEN_PROCESS;
---------------------------------------------
-------------------------------------------------------------------------------
-- Logic for generation of error signal for partial word access byte enables
and_reduce_be <= and_reduce(bus2ip_be);
partial_reg_access_error <= (not and_reduce_be) and
(xadc_ip2bus_rdack or
xadc_ip2bus_wrack);
-------------------------------------------------------------------------------
--------------------------------------------------------------
---- SW_RESET_REG_READ_ACK_GEN_PROCESS:Implement read ack logic for dummy register
---- holes. This is dummy read as read/write is
---- not returning any value. In local registers.
--------------------------------------------------------------
DUMMY_REG_READ_WRITE_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (bus2ip_clk'event and bus2ip_clk = '1') then
if (reset2ip_reset = RESET_ACTIVE) then
dummy_local_reg_rdack_d1 <= '0';
dummy_local_reg_rdack <= '0';
dummy_local_reg_wrack_d1 <= '0';
dummy_local_reg_wrack <= '0';
else
dummy_local_reg_rdack_d1 <= or_reduce(bus2ip_rdce_int(5 to 7));
dummy_local_reg_rdack <= or_reduce(bus2ip_rdce_int(5 to 7)) and
(not dummy_local_reg_rdack_d1);
dummy_local_reg_wrack_d1 <= or_reduce(bus2ip_wrce_int(5 to 7));
dummy_local_reg_wrack <= or_reduce(bus2ip_wrce_int(5 to 7)) and
(not dummy_local_reg_wrack_d1);
end if;
end if;
end process DUMMY_REG_READ_WRITE_ACK_GEN_PROCESS;
-----------------------------------------------
end architecture imp;
| apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_dlmb_v10_0/system_dlmb_v10_0_sim_netlist.vhdl | 1 | 7200 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:45:00 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_dlmb_v10_0 -prefix
-- system_dlmb_v10_0_ system_ilmb_v10_0_sim_netlist.vhdl
-- Design : system_ilmb_v10_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_dlmb_v10_0_lmb_v10 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
attribute C_EXT_RESET_HIGH : integer;
attribute C_EXT_RESET_HIGH of system_dlmb_v10_0_lmb_v10 : entity is 1;
attribute C_LMB_AWIDTH : integer;
attribute C_LMB_AWIDTH of system_dlmb_v10_0_lmb_v10 : entity is 32;
attribute C_LMB_DWIDTH : integer;
attribute C_LMB_DWIDTH of system_dlmb_v10_0_lmb_v10 : entity is 32;
attribute C_LMB_NUM_SLAVES : integer;
attribute C_LMB_NUM_SLAVES of system_dlmb_v10_0_lmb_v10 : entity is 1;
end system_dlmb_v10_0_lmb_v10;
architecture STRUCTURE of system_dlmb_v10_0_lmb_v10 is
signal \^m_abus\ : STD_LOGIC_VECTOR ( 0 to 31 );
signal \^m_addrstrobe\ : STD_LOGIC;
signal \^m_be\ : STD_LOGIC_VECTOR ( 0 to 3 );
signal \^m_dbus\ : STD_LOGIC_VECTOR ( 0 to 31 );
signal \^m_readstrobe\ : STD_LOGIC;
signal \^m_writestrobe\ : STD_LOGIC;
signal \^sl_ce\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sl_dbus\ : STD_LOGIC_VECTOR ( 0 to 31 );
signal \^sl_ready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sl_ue\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sl_wait\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of POR_FF_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_FF_I : label is "FDS";
begin
LMB_ABus(0 to 31) <= \^m_abus\(0 to 31);
LMB_AddrStrobe <= \^m_addrstrobe\;
LMB_BE(0 to 3) <= \^m_be\(0 to 3);
LMB_CE <= \^sl_ce\(0);
LMB_ReadDBus(0 to 31) <= \^sl_dbus\(0 to 31);
LMB_ReadStrobe <= \^m_readstrobe\;
LMB_Ready <= \^sl_ready\(0);
LMB_UE <= \^sl_ue\(0);
LMB_Wait <= \^sl_wait\(0);
LMB_WriteDBus(0 to 31) <= \^m_dbus\(0 to 31);
LMB_WriteStrobe <= \^m_writestrobe\;
\^m_abus\(0 to 31) <= M_ABus(0 to 31);
\^m_addrstrobe\ <= M_AddrStrobe;
\^m_be\(0 to 3) <= M_BE(0 to 3);
\^m_dbus\(0 to 31) <= M_DBus(0 to 31);
\^m_readstrobe\ <= M_ReadStrobe;
\^m_writestrobe\ <= M_WriteStrobe;
\^sl_ce\(0) <= Sl_CE(0);
\^sl_dbus\(0 to 31) <= Sl_DBus(0 to 31);
\^sl_ready\(0) <= Sl_Ready(0);
\^sl_ue\(0) <= Sl_UE(0);
\^sl_wait\(0) <= Sl_Wait(0);
POR_FF_I: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => LMB_Clk,
CE => '1',
D => '0',
Q => LMB_Rst,
S => SYS_Rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_dlmb_v10_0 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_dlmb_v10_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_dlmb_v10_0 : entity is "system_ilmb_v10_0,lmb_v10,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_dlmb_v10_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_dlmb_v10_0 : entity is "lmb_v10,Vivado 2016.4";
end system_dlmb_v10_0;
architecture STRUCTURE of system_dlmb_v10_0 is
attribute C_EXT_RESET_HIGH : integer;
attribute C_EXT_RESET_HIGH of U0 : label is 1;
attribute C_LMB_AWIDTH : integer;
attribute C_LMB_AWIDTH of U0 : label is 32;
attribute C_LMB_DWIDTH : integer;
attribute C_LMB_DWIDTH of U0 : label is 32;
attribute C_LMB_NUM_SLAVES : integer;
attribute C_LMB_NUM_SLAVES of U0 : label is 1;
begin
U0: entity work.system_dlmb_v10_0_lmb_v10
port map (
LMB_ABus(0 to 31) => LMB_ABus(0 to 31),
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_BE(0 to 3) => LMB_BE(0 to 3),
LMB_CE => LMB_CE,
LMB_Clk => LMB_Clk,
LMB_ReadDBus(0 to 31) => LMB_ReadDBus(0 to 31),
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_Ready => LMB_Ready,
LMB_Rst => LMB_Rst,
LMB_UE => LMB_UE,
LMB_Wait => LMB_Wait,
LMB_WriteDBus(0 to 31) => LMB_WriteDBus(0 to 31),
LMB_WriteStrobe => LMB_WriteStrobe,
M_ABus(0 to 31) => M_ABus(0 to 31),
M_AddrStrobe => M_AddrStrobe,
M_BE(0 to 3) => M_BE(0 to 3),
M_DBus(0 to 31) => M_DBus(0 to 31),
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
SYS_Rst => SYS_Rst,
Sl_CE(0) => Sl_CE(0),
Sl_DBus(0 to 31) => Sl_DBus(0 to 31),
Sl_Ready(0) => Sl_Ready(0),
Sl_UE(0) => Sl_UE(0),
Sl_Wait(0) => Sl_Wait(0)
);
end STRUCTURE;
| apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_rst_mig_7series_0_83M_0/sim/system_rst_mig_7series_0_83M_0.vhd | 1 | 5883 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_10;
USE proc_sys_reset_v5_0_10.proc_sys_reset;
ENTITY system_rst_mig_7series_0_83M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_rst_mig_7series_0_83M_0;
ARCHITECTURE system_rst_mig_7series_0_83M_0_arch OF system_rst_mig_7series_0_83M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_mig_7series_0_83M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END system_rst_mig_7series_0_83M_0_arch;
| apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ipshared/04b4/hdl/proc_sys_reset_v5_0_vh_rfs.vhd | 8 | 69537 | -------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_10.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
-------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0_2;
--use lib_cdc_v1_0_2.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
use proc_sys_reset_v5_0_10.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_10.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_10.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
| apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_axi_gpio_0_0/sim/system_axi_gpio_0_0.vhd | 1 | 9295 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END system_axi_gpio_0_0;
ARCHITECTURE system_axi_gpio_0_0_arch OF system_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 20,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_0_0_arch;
| apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_rst_clk_wiz_1_100M_0/system_rst_clk_wiz_1_100M_0_sim_netlist.vhdl | 1 | 32658 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:44:30 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_rst_clk_wiz_1_100M_0/system_rst_clk_wiz_1_100M_0_sim_netlist.vhdl
-- Design : system_rst_clk_wiz_1_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_clk_wiz_1_100M_0_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
aux_reset_in : in STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_clk_wiz_1_100M_0_cdc_sync : entity is "cdc_sync";
end system_rst_clk_wiz_1_100M_0_cdc_sync;
architecture STRUCTURE of system_rst_clk_wiz_1_100M_0_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_clk_wiz_1_100M_0_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_clk_wiz_1_100M_0_cdc_sync_0 : entity is "cdc_sync";
end system_rst_clk_wiz_1_100M_0_cdc_sync_0;
architecture STRUCTURE of system_rst_clk_wiz_1_100M_0_cdc_sync_0 is
signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_clk_wiz_1_100M_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_clk_wiz_1_100M_0_upcnt_n : entity is "upcnt_n";
end system_rst_clk_wiz_1_100M_0_upcnt_n;
architecture STRUCTURE of system_rst_clk_wiz_1_100M_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_clk_wiz_1_100M_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_clk_wiz_1_100M_0_lpf : entity is "lpf";
end system_rst_clk_wiz_1_100M_0_lpf;
architecture STRUCTURE of system_rst_clk_wiz_1_100M_0_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of POR_SRL_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.system_rst_clk_wiz_1_100M_0_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.system_rst_clk_wiz_1_100M_0_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_clk_wiz_1_100M_0_sequence_psr is
port (
Core : out STD_LOGIC;
bsr : out STD_LOGIC;
pr : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_clk_wiz_1_100M_0_sequence_psr : entity is "sequence_psr";
end system_rst_clk_wiz_1_100M_0_sequence_psr;
architecture STRUCTURE of system_rst_clk_wiz_1_100M_0_sequence_psr is
signal \^core\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^bsr\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^pr\ : STD_LOGIC;
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Core <= \^core\;
bsr <= \^bsr\;
pr <= \^pr\;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^core\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^core\,
S => lpf_int
);
SEQ_COUNTER: entity work.system_rst_clk_wiz_1_100M_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^core\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_clk_wiz_1_100M_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is "artix7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_rst_clk_wiz_1_100M_0_proc_sys_reset : entity is "proc_sys_reset";
end system_rst_clk_wiz_1_100M_0_proc_sys_reset;
architecture STRUCTURE of system_rst_clk_wiz_1_100M_0_proc_sys_reset is
signal Core : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal bsr : STD_LOGIC;
signal lpf_int : STD_LOGIC;
signal pr : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no";
attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.system_rst_clk_wiz_1_100M_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.system_rst_clk_wiz_1_100M_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4,
Core => Core,
bsr => bsr,
lpf_int => lpf_int,
pr => pr,
slowest_sync_clk => slowest_sync_clk
);
mb_reset_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core,
Q => mb_reset,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rst_clk_wiz_1_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rst_clk_wiz_1_100M_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rst_clk_wiz_1_100M_0 : entity is "system_rst_clk_wiz_1_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rst_clk_wiz_1_100M_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rst_clk_wiz_1_100M_0 : entity is "proc_sys_reset,Vivado 2016.4";
end system_rst_clk_wiz_1_100M_0;
architecture STRUCTURE of system_rst_clk_wiz_1_100M_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.system_rst_clk_wiz_1_100M_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
| apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_axi_uartlite_0_0/sim/system_axi_uartlite_0_0.vhd | 1 | 8178 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_uartlite:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_uartlite_v2_0_15;
USE axi_uartlite_v2_0_15.axi_uartlite;
ENTITY system_axi_uartlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END system_axi_uartlite_0_0;
ARCHITECTURE system_axi_uartlite_0_0_arch OF system_axi_uartlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_uartlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_uartlite IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_BAUDRATE : INTEGER;
C_DATA_BITS : INTEGER;
C_USE_PARITY : INTEGER;
C_ODD_PARITY : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END COMPONENT axi_uartlite;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF rx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD";
ATTRIBUTE X_INTERFACE_INFO OF tx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD";
BEGIN
U0 : axi_uartlite
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => 32,
C_BAUDRATE => 9600,
C_DATA_BITS => 8,
C_USE_PARITY => 0,
C_ODD_PARITY => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
interrupt => interrupt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
rx => rx,
tx => tx
);
END system_axi_uartlite_0_0_arch;
| apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_axi_gpio_pullup_0/system_axi_gpio_pullup_0_stub.vhdl | 1 | 2495 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:47:11 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_pullup_0/system_axi_gpio_pullup_0_stub.vhdl
-- Design : system_axi_gpio_pullup_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_axi_gpio_pullup_0 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end system_axi_gpio_pullup_0;
architecture stub of system_axi_gpio_pullup_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[1:0],gpio_io_o[1:0],gpio_io_t[1:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2016.4";
begin
end;
| apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_dlmb_v10_0/synth/system_dlmb_v10_0.vhd | 1 | 9019 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_v10:3.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_v10_v3_0_9;
USE lmb_v10_v3_0_9.lmb_v10;
ENTITY system_dlmb_v10_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END system_dlmb_v10_0;
ARCHITECTURE system_dlmb_v10_0_arch OF system_dlmb_v10_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_dlmb_v10_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_v10 IS
GENERIC (
C_LMB_NUM_SLAVES : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_LMB_AWIDTH : INTEGER;
C_EXT_RESET_HIGH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END COMPONENT lmb_v10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_dlmb_v10_0_arch: ARCHITECTURE IS "lmb_v10,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_dlmb_v10_0_arch : ARCHITECTURE IS "system_dlmb_v10_0,lmb_v10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_dlmb_v10_0_arch: ARCHITECTURE IS "system_dlmb_v10_0,lmb_v10,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_v10,x_ipVersion=3.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_LMB_NUM_SLAVES=1,C_LMB_DWIDTH=32,C_LMB_AWIDTH=32,C_EXT_RESET_HIGH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST";
ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS";
ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT";
ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE";
BEGIN
U0 : lmb_v10
GENERIC MAP (
C_LMB_NUM_SLAVES => 1,
C_LMB_DWIDTH => 32,
C_LMB_AWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
PORT MAP (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
END system_dlmb_v10_0_arch;
| apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ipshared/162e/hdl/lmb_v10_v3_0_vh_rfs.vhd | 1 | 9113 | -------------------------------------------------------------------------------
-- lmb_v10.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: lmb_v10.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_v10.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
--
-- History:
-- goran 2002-01-30 First Version
-- paulo 2002-04-10 Renamed C_NUM_SLAVES to C_LMB_NUM_SLAVES
-- roland 2010-02-13 UE, CE and Wait signals added
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer := 4;
C_LMB_DWIDTH : integer := 32;
C_LMB_AWIDTH : integer := 32;
C_EXT_RESET_HIGH : integer := 1
);
port (
-- Global Ports
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
-- LMB master signals
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
-- LMB slave signals
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
-- LMB output signals
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end entity lmb_v10;
library unisim;
use unisim.all;
architecture IMP of lmb_v10 is
component FDS is
port(
Q : out std_logic;
D : in std_logic;
C : in std_logic;
S : in std_logic);
end component FDS;
signal sys_rst_i : std_logic;
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Driving the reset signal
-----------------------------------------------------------------------------
SYS_RST_PROC : process (SYS_Rst) is
variable sys_rst_input : std_logic;
begin
if C_EXT_RESET_HIGH = 0 then
sys_rst_input := not SYS_Rst;
else
sys_rst_input := SYS_Rst;
end if;
sys_rst_i <= sys_rst_input;
end process SYS_RST_PROC;
POR_FF_I : FDS
port map (
Q => LMB_Rst,
D => '0',
C => LMB_Clk,
S => sys_rst_i);
-----------------------------------------------------------------------------
-- Drive all Master to Slave signals
-----------------------------------------------------------------------------
LMB_ABus <= M_ABus;
LMB_ReadStrobe <= M_ReadStrobe;
LMB_WriteStrobe <= M_WriteStrobe;
LMB_AddrStrobe <= M_AddrStrobe;
LMB_BE <= M_BE;
LMB_WriteDBus <= M_DBus;
-----------------------------------------------------------------------------
-- Drive all the Slave to Master signals
-----------------------------------------------------------------------------
Ready_ORing : process (Sl_Ready) is
variable i : std_logic;
begin -- process Ready_ORing
i := '0';
for S in Sl_Ready'range loop
i := i or Sl_Ready(S);
end loop; -- S
LMB_Ready <= i;
end process Ready_ORing;
Wait_ORing : process (Sl_Wait) is
variable i : std_logic;
begin -- process Wait_ORing
i := '0';
for S in Sl_Wait'range loop
i := i or Sl_Wait(S);
end loop; -- S
LMB_Wait <= i;
end process Wait_ORing;
SI_UE_ORing : process (Sl_UE) is
variable i : std_logic;
begin -- process UE_ORing
i := '0';
for S in Sl_UE'range loop
i := i or Sl_UE(S);
end loop; -- S
LMB_UE <= i;
end process SI_UE_ORing;
SI_CE_ORing : process (Sl_CE) is
variable i : std_logic;
begin -- process CE_ORing
i := '0';
for S in Sl_CE'range loop
i := i or Sl_CE(S);
end loop; -- S
LMB_CE <= i;
end process SI_CE_ORing;
DBus_Oring : process (Sl_Ready, Sl_DBus) is
variable Res : std_logic_vector(0 to C_LMB_DWIDTH-1);
variable Tmp : std_logic_vector(Sl_DBus'range);
variable tmp_or : std_logic;
begin -- process DBus_Oring
if (C_LMB_NUM_SLAVES = 1) then
LMB_ReadDBus <= Sl_DBus;
else
-- First gating all data signals with their resp. ready signal
for I in 0 to C_LMB_NUM_SLAVES-1 loop
for J in 0 to C_LMB_DWIDTH-1 loop
tmp(I*C_LMB_DWIDTH + J) := Sl_Ready(I) and Sl_DBus(I*C_LMB_DWIDTH + J);
end loop; -- J
end loop; -- I
-- then oring the tmp signals together
for J in 0 to C_LMB_DWIDTH-1 loop
tmp_or := '0';
for I in 0 to C_LMB_NUM_SLAVES-1 loop
tmp_or := tmp_or or tmp(I*C_LMB_DWIDTH + j);
end loop; -- J
res(J) := tmp_or;
end loop; -- I
LMB_ReadDBus <= Res;
end if;
end process DBus_Oring;
end architecture IMP;
| apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_ilmb_v10_0/system_ilmb_v10_0_sim_netlist.vhdl | 1 | 7332 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:45:00 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_ilmb_v10_0/system_ilmb_v10_0_sim_netlist.vhdl
-- Design : system_ilmb_v10_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ilmb_v10_0_lmb_v10 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
attribute C_EXT_RESET_HIGH : integer;
attribute C_EXT_RESET_HIGH of system_ilmb_v10_0_lmb_v10 : entity is 1;
attribute C_LMB_AWIDTH : integer;
attribute C_LMB_AWIDTH of system_ilmb_v10_0_lmb_v10 : entity is 32;
attribute C_LMB_DWIDTH : integer;
attribute C_LMB_DWIDTH of system_ilmb_v10_0_lmb_v10 : entity is 32;
attribute C_LMB_NUM_SLAVES : integer;
attribute C_LMB_NUM_SLAVES of system_ilmb_v10_0_lmb_v10 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ilmb_v10_0_lmb_v10 : entity is "lmb_v10";
end system_ilmb_v10_0_lmb_v10;
architecture STRUCTURE of system_ilmb_v10_0_lmb_v10 is
signal \^m_abus\ : STD_LOGIC_VECTOR ( 0 to 31 );
signal \^m_addrstrobe\ : STD_LOGIC;
signal \^m_be\ : STD_LOGIC_VECTOR ( 0 to 3 );
signal \^m_dbus\ : STD_LOGIC_VECTOR ( 0 to 31 );
signal \^m_readstrobe\ : STD_LOGIC;
signal \^m_writestrobe\ : STD_LOGIC;
signal \^sl_ce\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sl_dbus\ : STD_LOGIC_VECTOR ( 0 to 31 );
signal \^sl_ready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sl_ue\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sl_wait\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of POR_FF_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_FF_I : label is "FDS";
begin
LMB_ABus(0 to 31) <= \^m_abus\(0 to 31);
LMB_AddrStrobe <= \^m_addrstrobe\;
LMB_BE(0 to 3) <= \^m_be\(0 to 3);
LMB_CE <= \^sl_ce\(0);
LMB_ReadDBus(0 to 31) <= \^sl_dbus\(0 to 31);
LMB_ReadStrobe <= \^m_readstrobe\;
LMB_Ready <= \^sl_ready\(0);
LMB_UE <= \^sl_ue\(0);
LMB_Wait <= \^sl_wait\(0);
LMB_WriteDBus(0 to 31) <= \^m_dbus\(0 to 31);
LMB_WriteStrobe <= \^m_writestrobe\;
\^m_abus\(0 to 31) <= M_ABus(0 to 31);
\^m_addrstrobe\ <= M_AddrStrobe;
\^m_be\(0 to 3) <= M_BE(0 to 3);
\^m_dbus\(0 to 31) <= M_DBus(0 to 31);
\^m_readstrobe\ <= M_ReadStrobe;
\^m_writestrobe\ <= M_WriteStrobe;
\^sl_ce\(0) <= Sl_CE(0);
\^sl_dbus\(0 to 31) <= Sl_DBus(0 to 31);
\^sl_ready\(0) <= Sl_Ready(0);
\^sl_ue\(0) <= Sl_UE(0);
\^sl_wait\(0) <= Sl_Wait(0);
POR_FF_I: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => LMB_Clk,
CE => '1',
D => '0',
Q => LMB_Rst,
S => SYS_Rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ilmb_v10_0 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ilmb_v10_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ilmb_v10_0 : entity is "system_ilmb_v10_0,lmb_v10,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ilmb_v10_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ilmb_v10_0 : entity is "lmb_v10,Vivado 2016.4";
end system_ilmb_v10_0;
architecture STRUCTURE of system_ilmb_v10_0 is
attribute C_EXT_RESET_HIGH : integer;
attribute C_EXT_RESET_HIGH of U0 : label is 1;
attribute C_LMB_AWIDTH : integer;
attribute C_LMB_AWIDTH of U0 : label is 32;
attribute C_LMB_DWIDTH : integer;
attribute C_LMB_DWIDTH of U0 : label is 32;
attribute C_LMB_NUM_SLAVES : integer;
attribute C_LMB_NUM_SLAVES of U0 : label is 1;
begin
U0: entity work.system_ilmb_v10_0_lmb_v10
port map (
LMB_ABus(0 to 31) => LMB_ABus(0 to 31),
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_BE(0 to 3) => LMB_BE(0 to 3),
LMB_CE => LMB_CE,
LMB_Clk => LMB_Clk,
LMB_ReadDBus(0 to 31) => LMB_ReadDBus(0 to 31),
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_Ready => LMB_Ready,
LMB_Rst => LMB_Rst,
LMB_UE => LMB_UE,
LMB_Wait => LMB_Wait,
LMB_WriteDBus(0 to 31) => LMB_WriteDBus(0 to 31),
LMB_WriteStrobe => LMB_WriteStrobe,
M_ABus(0 to 31) => M_ABus(0 to 31),
M_AddrStrobe => M_AddrStrobe,
M_BE(0 to 3) => M_BE(0 to 3),
M_DBus(0 to 31) => M_DBus(0 to 31),
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
SYS_Rst => SYS_Rst,
Sl_CE(0) => Sl_CE(0),
Sl_DBus(0 to 31) => Sl_DBus(0 to 31),
Sl_Ready(0) => Sl_Ready(0),
Sl_UE(0) => Sl_UE(0),
Sl_Wait(0) => Sl_Wait(0)
);
end STRUCTURE;
| apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_axi_gpio_pullup_0/synth/system_axi_gpio_pullup_0.vhd | 1 | 10051 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY system_axi_gpio_pullup_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END system_axi_gpio_pullup_0;
ARCHITECTURE system_axi_gpio_pullup_0_arch OF system_axi_gpio_pullup_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_gpio_pullup_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_gpio_pullup_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_gpio_pullup_0_arch : ARCHITECTURE IS "system_axi_gpio_pullup_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_axi_gpio_pullup_0_arch: ARCHITECTURE IS "system_axi_gpio_pullup_0,axi_gpio,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=13,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=2,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "artix7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 2,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END system_axi_gpio_pullup_0_arch;
| apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_axi_quad_spi_shield_0/sim/system_axi_quad_spi_shield_0.vhd | 1 | 15796 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_2_10;
USE axi_quad_spi_v3_2_10.axi_quad_spi;
ENTITY system_axi_quad_spi_shield_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END system_axi_quad_spi_shield_0;
ARCHITECTURE system_axi_quad_spi_shield_0_arch OF system_axi_quad_spi_shield_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_quad_spi_shield_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
Async_Clk : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_UC_FAMILY : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_DUAL_QUAD_MODE : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_USE_STARTUP_EXT : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
C_SHARED_STARTUP : INTEGER;
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
C_LSB_STUP : INTEGER
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
io0_1_i : IN STD_LOGIC;
io0_1_o : OUT STD_LOGIC;
io0_1_t : OUT STD_LOGIC;
io1_1_i : IN STD_LOGIC;
io1_1_o : OUT STD_LOGIC;
io1_1_t : OUT STD_LOGIC;
io2_1_i : IN STD_LOGIC;
io2_1_o : OUT STD_LOGIC;
io2_1_t : OUT STD_LOGIC;
io3_1_i : IN STD_LOGIC;
io3_1_o : OUT STD_LOGIC;
io3_1_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ss_1_i : IN STD_LOGIC;
ss_1_o : OUT STD_LOGIC;
ss_1_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
clk : IN STD_LOGIC;
gsr : IN STD_LOGIC;
gts : IN STD_LOGIC;
keyclearb : IN STD_LOGIC;
usrcclkts : IN STD_LOGIC;
usrdoneo : IN STD_LOGIC;
usrdonets : IN STD_LOGIC;
pack : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
Async_Clk => 0,
C_FAMILY => "artix7",
C_SELECT_XPM => 0,
C_SUB_FAMILY => "artix7",
C_INSTANCE => "axi_quad_spi_inst",
C_SPI_MEM_ADDR_BITS => 24,
C_TYPE_OF_AXI4_INTERFACE => 0,
C_XIP_MODE => 0,
C_UC_FAMILY => 0,
C_FIFO_DEPTH => 16,
C_SCK_RATIO => 16,
C_DUAL_QUAD_MODE => 0,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 0,
C_USE_STARTUP => 0,
C_USE_STARTUP_EXT => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 1,
C_SHARED_STARTUP => 0,
C_S_AXI4_BASEADDR => X"FFFFFFFF",
C_S_AXI4_HIGHADDR => X"00000000",
C_LSB_STUP => 0
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi4_aclk => '0',
s_axi4_aresetn => '0',
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => '0',
io3_i => '0',
io0_1_i => '0',
io1_1_i => '0',
io2_1_i => '0',
io3_1_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
ss_1_i => '0',
clk => '0',
gsr => '0',
gts => '0',
keyclearb => '0',
usrcclkts => '0',
usrdoneo => '1',
usrdonets => '0',
pack => '0',
ip2intc_irpt => ip2intc_irpt
);
END system_axi_quad_spi_shield_0_arch;
| apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_axi_gpio_led_0/system_axi_gpio_led_0_sim_netlist.vhdl | 1 | 136743 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:47:50 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_led_0/system_axi_gpio_led_0_sim_netlist.vhdl
-- Design : system_axi_gpio_led_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
\ip2bus_data_i_D1_reg[20]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 3 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 11 );
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg_Rst : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
is_read : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO2_DBus_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 3 downto 0 );
\Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
rst_reg : in STD_LOGIC;
gpio2_io_t : in STD_LOGIC_VECTOR ( 11 downto 0 );
\Dual.gpio2_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
start2 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_address_decoder : entity is "address_decoder";
end system_axi_gpio_led_0_address_decoder;
architecture STRUCTURE of system_axi_gpio_led_0_address_decoder is
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[10]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[11]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[5]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[7]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[8]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[9]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[3]_i_1\ : label is "soft_lutpair3";
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
\Dual.READ_REG2_GEN[0].GPIO2_DBus_i[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(11),
I1 => \Dual.gpio2_Data_In_reg[0]\(11),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(0)
);
\Dual.READ_REG2_GEN[10].GPIO2_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(1),
I1 => \Dual.gpio2_Data_In_reg[0]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(10)
);
\Dual.READ_REG2_GEN[11].GPIO2_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => gpio_xferAck_Reg,
I2 => bus2ip_rnw_i_reg,
I3 => GPIO_xferAck_i,
O => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[11].GPIO2_DBus_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(0),
I1 => \Dual.gpio2_Data_In_reg[0]\(0),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(11)
);
\Dual.READ_REG2_GEN[1].GPIO2_DBus_i[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(10),
I1 => \Dual.gpio2_Data_In_reg[0]\(10),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(1)
);
\Dual.READ_REG2_GEN[2].GPIO2_DBus_i[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(9),
I1 => \Dual.gpio2_Data_In_reg[0]\(9),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(2)
);
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(8),
I1 => \Dual.gpio2_Data_In_reg[0]\(8),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(3)
);
\Dual.READ_REG2_GEN[4].GPIO2_DBus_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(7),
I1 => \Dual.gpio2_Data_In_reg[0]\(7),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(4)
);
\Dual.READ_REG2_GEN[5].GPIO2_DBus_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(6),
I1 => \Dual.gpio2_Data_In_reg[0]\(6),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(5)
);
\Dual.READ_REG2_GEN[6].GPIO2_DBus_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(5),
I1 => \Dual.gpio2_Data_In_reg[0]\(5),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(6)
);
\Dual.READ_REG2_GEN[7].GPIO2_DBus_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(4),
I1 => \Dual.gpio2_Data_In_reg[0]\(4),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(7)
);
\Dual.READ_REG2_GEN[8].GPIO2_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(3),
I1 => \Dual.gpio2_Data_In_reg[0]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(8)
);
\Dual.READ_REG2_GEN[9].GPIO2_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(2),
I1 => \Dual.gpio2_Data_In_reg[0]\(2),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(9)
);
\Dual.READ_REG_GEN[0].GPIO_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(3),
I1 => \Dual.gpio_Data_In_reg[0]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(0)
);
\Dual.READ_REG_GEN[1].GPIO_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(2),
I1 => \Dual.gpio_Data_In_reg[0]\(2),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(1)
);
\Dual.READ_REG_GEN[2].GPIO_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(1),
I1 => \Dual.gpio_Data_In_reg[0]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(2)
);
\Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(0),
I1 => \Dual.gpio_Data_In_reg[0]\(0),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(3)
);
\Dual.gpio2_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00001000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => rst_reg,
O => \Dual.gpio2_Data_Out_reg[0]\(0)
);
\Dual.gpio2_Data_Out[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(1),
O => D(1)
);
\Dual.gpio2_Data_Out[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(0),
O => D(0)
);
\Dual.gpio2_Data_Out[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(7),
O => D(7)
);
\Dual.gpio2_Data_Out[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(6),
O => D(6)
);
\Dual.gpio2_Data_Out[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(5),
O => D(5)
);
\Dual.gpio2_Data_Out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(4),
O => D(4)
);
\Dual.gpio2_Data_Out[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(3),
O => D(3)
);
\Dual.gpio2_Data_Out[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(2),
O => D(2)
);
\Dual.gpio2_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF10000000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => rst_reg,
O => \Dual.gpio2_OE_reg[0]\(0)
);
\Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000100"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => rst_reg,
O => \Dual.gpio_Data_Out_reg[0]\(0)
);
\Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(11),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => s_axi_wdata(3),
O => D(11)
);
\Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(10),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => s_axi_wdata(2),
O => D(10)
);
\Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(9),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => s_axi_wdata(1),
O => D(9)
);
\Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(8),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => s_axi_wdata(0),
O => D(8)
);
\Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00040000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => rst_reg,
O => E(0)
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000E0000"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => start2,
I2 => \^s_axi_wready\,
I3 => \^s_axi_arready\,
I4 => s_axi_aresetn,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\ip2bus_data_i_D1[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(11),
O => \ip2bus_data_i_D1_reg[20]\(11)
);
\ip2bus_data_i_D1[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(10),
O => \ip2bus_data_i_D1_reg[20]\(10)
);
\ip2bus_data_i_D1[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(9),
O => \ip2bus_data_i_D1_reg[20]\(9)
);
\ip2bus_data_i_D1[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(8),
O => \ip2bus_data_i_D1_reg[20]\(8)
);
\ip2bus_data_i_D1[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(7),
O => \ip2bus_data_i_D1_reg[20]\(7)
);
\ip2bus_data_i_D1[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(6),
O => \ip2bus_data_i_D1_reg[20]\(6)
);
\ip2bus_data_i_D1[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(5),
O => \ip2bus_data_i_D1_reg[20]\(5)
);
\ip2bus_data_i_D1[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(4),
O => \ip2bus_data_i_D1_reg[20]\(4)
);
\ip2bus_data_i_D1[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABAAAAAAA8AAAAAA"
)
port map (
I0 => GPIO2_DBus_i(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => bus2ip_rnw_i_reg,
I5 => GPIO_DBus_i(3),
O => \ip2bus_data_i_D1_reg[20]\(3)
);
\ip2bus_data_i_D1[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABAAAAAAA8AAAAAA"
)
port map (
I0 => GPIO2_DBus_i(2),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => bus2ip_rnw_i_reg,
I5 => GPIO_DBus_i(2),
O => \ip2bus_data_i_D1_reg[20]\(2)
);
\ip2bus_data_i_D1[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABAAAAAAA8AAAAAA"
)
port map (
I0 => GPIO2_DBus_i(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => bus2ip_rnw_i_reg,
I5 => GPIO_DBus_i(1),
O => \ip2bus_data_i_D1_reg[20]\(1)
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABAAAAAAA8AAAAAA"
)
port map (
I0 => GPIO2_DBus_i(0),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => bus2ip_rnw_i_reg,
I5 => GPIO_DBus_i(0),
O => \ip2bus_data_i_D1_reg[20]\(0)
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_read,
I5 => ip2bus_rdack_i_D1,
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_write_reg,
I5 => ip2bus_wrack_i_D1,
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_cdc_sync is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_cdc_sync : entity is "cdc_sync";
end system_axi_gpio_led_0_cdc_sync;
architecture STRUCTURE of system_axi_gpio_led_0_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_gpio_led_0_cdc_sync__parameterized0\ is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_gpio_led_0_cdc_sync__parameterized0\ : entity is "cdc_sync";
end \system_axi_gpio_led_0_cdc_sync__parameterized0\;
architecture STRUCTURE of \system_axi_gpio_led_0_cdc_sync__parameterized0\ is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_10 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_11 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_5 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_6 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_7 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_8 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_9 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_10 : STD_LOGIC;
signal s_level_out_bus_d2_11 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d2_5 : STD_LOGIC;
signal s_level_out_bus_d2_6 : STD_LOGIC;
signal s_level_out_bus_d2_7 : STD_LOGIC;
signal s_level_out_bus_d2_8 : STD_LOGIC;
signal s_level_out_bus_d2_9 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_10 : STD_LOGIC;
signal s_level_out_bus_d3_11 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal s_level_out_bus_d3_5 : STD_LOGIC;
signal s_level_out_bus_d3_6 : STD_LOGIC;
signal s_level_out_bus_d3_7 : STD_LOGIC;
signal s_level_out_bus_d3_8 : STD_LOGIC;
signal s_level_out_bus_d3_9 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_10,
Q => s_level_out_bus_d2_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_11,
Q => s_level_out_bus_d2_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_5,
Q => s_level_out_bus_d2_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_6,
Q => s_level_out_bus_d2_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_7,
Q => s_level_out_bus_d2_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_8,
Q => s_level_out_bus_d2_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_9,
Q => s_level_out_bus_d2_9,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_10,
Q => s_level_out_bus_d3_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_11,
Q => s_level_out_bus_d3_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_5,
Q => s_level_out_bus_d3_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_6,
Q => s_level_out_bus_d3_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_7,
Q => s_level_out_bus_d3_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_8,
Q => s_level_out_bus_d3_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_9,
Q => s_level_out_bus_d3_9,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_10,
Q => scndry_vect_out(10),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_11,
Q => scndry_vect_out(11),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => scndry_vect_out(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_5,
Q => scndry_vect_out(5),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_6,
Q => scndry_vect_out(6),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_7,
Q => scndry_vect_out(7),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_8,
Q => scndry_vect_out(8),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_9,
Q => scndry_vect_out(9),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(10),
Q => s_level_out_bus_d1_cdc_to_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(11),
Q => s_level_out_bus_d1_cdc_to_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(5),
Q => s_level_out_bus_d1_cdc_to_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(6),
Q => s_level_out_bus_d1_cdc_to_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(7),
Q => s_level_out_bus_d1_cdc_to_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(8),
Q => s_level_out_bus_d1_cdc_to_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(9),
Q => s_level_out_bus_d1_cdc_to_9,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_GPIO_Core is
port (
GPIO2_DBus_i : out STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
Read_Reg_Rst : in STD_LOGIC;
Read_Reg2_In : in STD_LOGIC_VECTOR ( 0 to 11 );
s_axi_aclk : in STD_LOGIC;
Read_Reg_In : in STD_LOGIC_VECTOR ( 0 to 3 );
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_GPIO_Core : entity is "GPIO_Core";
end system_axi_gpio_led_0_GPIO_Core;
architecture STRUCTURE of system_axi_gpio_led_0_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal gpio2_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 11 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 3 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair9";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Dual.INPUT_DOUBLE_REGS4\: entity work.system_axi_gpio_led_0_cdc_sync
port map (
gpio_io_i(3 downto 0) => gpio_io_i(3 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(3) => gpio_io_i_d2(0),
scndry_vect_out(2) => gpio_io_i_d2(1),
scndry_vect_out(1) => gpio_io_i_d2(2),
scndry_vect_out(0) => gpio_io_i_d2(3)
);
\Dual.INPUT_DOUBLE_REGS5\: entity work.\system_axi_gpio_led_0_cdc_sync__parameterized0\
port map (
gpio2_io_i(11 downto 0) => gpio2_io_i(11 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(11) => gpio2_io_i_d2(0),
scndry_vect_out(10) => gpio2_io_i_d2(1),
scndry_vect_out(9) => gpio2_io_i_d2(2),
scndry_vect_out(8) => gpio2_io_i_d2(3),
scndry_vect_out(7) => gpio2_io_i_d2(4),
scndry_vect_out(6) => gpio2_io_i_d2(5),
scndry_vect_out(5) => gpio2_io_i_d2(6),
scndry_vect_out(4) => gpio2_io_i_d2(7),
scndry_vect_out(3) => gpio2_io_i_d2(8),
scndry_vect_out(2) => gpio2_io_i_d2(9),
scndry_vect_out(1) => gpio2_io_i_d2(10),
scndry_vect_out(0) => gpio2_io_i_d2(11)
);
\Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(0),
Q => GPIO2_DBus_i(11),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[10].GPIO2_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(10),
Q => GPIO2_DBus_i(1),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[11].GPIO2_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(11),
Q => GPIO2_DBus_i(0),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[1].GPIO2_DBus_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(1),
Q => GPIO2_DBus_i(10),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[2].GPIO2_DBus_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(2),
Q => GPIO2_DBus_i(9),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(3),
Q => GPIO2_DBus_i(8),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[4].GPIO2_DBus_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(4),
Q => GPIO2_DBus_i(7),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[5].GPIO2_DBus_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(5),
Q => GPIO2_DBus_i(6),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[6].GPIO2_DBus_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(6),
Q => GPIO2_DBus_i(5),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[7].GPIO2_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(7),
Q => GPIO2_DBus_i(4),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[8].GPIO2_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(8),
Q => GPIO2_DBus_i(3),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[9].GPIO2_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(9),
Q => GPIO2_DBus_i(2),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(0),
Q => GPIO_DBus_i(3),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(1),
Q => GPIO_DBus_i(2),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(2),
Q => GPIO_DBus_i(1),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(3),
Q => GPIO_DBus_i(0),
R => Read_Reg_Rst
);
\Dual.gpio2_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(0),
Q => Q(11),
R => '0'
);
\Dual.gpio2_Data_In_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(10),
Q => Q(1),
R => '0'
);
\Dual.gpio2_Data_In_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(11),
Q => Q(0),
R => '0'
);
\Dual.gpio2_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(1),
Q => Q(10),
R => '0'
);
\Dual.gpio2_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(2),
Q => Q(9),
R => '0'
);
\Dual.gpio2_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(3),
Q => Q(8),
R => '0'
);
\Dual.gpio2_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(4),
Q => Q(7),
R => '0'
);
\Dual.gpio2_Data_In_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(5),
Q => Q(6),
R => '0'
);
\Dual.gpio2_Data_In_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(6),
Q => Q(5),
R => '0'
);
\Dual.gpio2_Data_In_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(7),
Q => Q(4),
R => '0'
);
\Dual.gpio2_Data_In_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(8),
Q => Q(3),
R => '0'
);
\Dual.gpio2_Data_In_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(9),
Q => Q(2),
R => '0'
);
\Dual.gpio2_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(11),
Q => gpio2_io_o(11),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(1),
Q => gpio2_io_o(1),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(0),
Q => gpio2_io_o(0),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(10),
Q => gpio2_io_o(10),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(9),
Q => gpio2_io_o(9),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(8),
Q => gpio2_io_o(8),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(7),
Q => gpio2_io_o(7),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(6),
Q => gpio2_io_o(6),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(5),
Q => gpio2_io_o(5),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(4),
Q => gpio2_io_o(4),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(3),
Q => gpio2_io_o(3),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(2),
Q => gpio2_io_o(2),
R => SS(0)
);
\Dual.gpio2_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(11),
Q => gpio2_io_t(11),
S => SS(0)
);
\Dual.gpio2_OE_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(1),
Q => gpio2_io_t(1),
S => SS(0)
);
\Dual.gpio2_OE_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(0),
Q => gpio2_io_t(0),
S => SS(0)
);
\Dual.gpio2_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(10),
Q => gpio2_io_t(10),
S => SS(0)
);
\Dual.gpio2_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(9),
Q => gpio2_io_t(9),
S => SS(0)
);
\Dual.gpio2_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(8),
Q => gpio2_io_t(8),
S => SS(0)
);
\Dual.gpio2_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(7),
Q => gpio2_io_t(7),
S => SS(0)
);
\Dual.gpio2_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(6),
Q => gpio2_io_t(6),
S => SS(0)
);
\Dual.gpio2_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(5),
Q => gpio2_io_t(5),
S => SS(0)
);
\Dual.gpio2_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(4),
Q => gpio2_io_t(4),
S => SS(0)
);
\Dual.gpio2_OE_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(3),
Q => gpio2_io_t(3),
S => SS(0)
);
\Dual.gpio2_OE_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(2),
Q => gpio2_io_t(2),
S => SS(0)
);
\Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(3),
R => '0'
);
\Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(2),
R => '0'
);
\Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(1),
R => '0'
);
\Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(0),
R => '0'
);
\Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(11),
Q => gpio_io_o(3),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(10),
Q => gpio_io_o(2),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(9),
Q => gpio_io_o(1),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(8),
Q => gpio_io_o(0),
R => SS(0)
);
\Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(11),
Q => gpio_io_t(3),
S => SS(0)
);
\Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(10),
Q => gpio_io_t(2),
S => SS(0)
);
\Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(9),
Q => gpio_io_t(1),
S => SS(0)
);
\Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(8),
Q => gpio_io_t(0),
S => SS(0)
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => SS(0)
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_cs,
I2 => \^gpio_xferack_reg\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => SS(0)
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_slave_attachment is
port (
bus2ip_rnw_i_reg_0 : out STD_LOGIC;
\ip2bus_data_i_D1_reg[31]\ : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
\ip2bus_data_i_D1_reg[20]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 3 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 11 );
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg_Rst : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO2_DBus_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_t : in STD_LOGIC_VECTOR ( 11 downto 0 );
\Dual.gpio2_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aresetn : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\ip2bus_data_i_D1_reg[20]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_slave_attachment : entity is "slave_attachment";
end system_axi_gpio_led_0_slave_attachment;
architecture STRUCTURE of system_axi_gpio_led_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal \^bus2ip_rnw_i_reg_0\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal \^ip2bus_data_i_d1_reg[31]\ : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair6";
begin
bus2ip_rnw_i_reg_0 <= \^bus2ip_rnw_i_reg_0\;
\ip2bus_data_i_D1_reg[31]\ <= \^ip2bus_data_i_d1_reg[31]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.system_axi_gpio_led_0_address_decoder
port map (
D(11 downto 0) => D(11 downto 0),
\Dual.gpio2_Data_In_reg[0]\(11 downto 0) => \Dual.gpio2_Data_In_reg[0]\(11 downto 0),
\Dual.gpio2_Data_Out_reg[0]\(0) => \Dual.gpio2_Data_Out_reg[0]\(0),
\Dual.gpio2_OE_reg[0]\(0) => \Dual.gpio2_OE_reg[0]\(0),
\Dual.gpio_Data_In_reg[0]\(3 downto 0) => Q(3 downto 0),
\Dual.gpio_Data_Out_reg[0]\(0) => \Dual.gpio_Data_Out_reg[0]\(0),
E(0) => E(0),
GPIO2_DBus_i(11 downto 0) => GPIO2_DBus_i(11 downto 0),
GPIO_DBus_i(3 downto 0) => GPIO_DBus_i(3 downto 0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
Q(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
Read_Reg2_In(0 to 11) => Read_Reg2_In(0 to 11),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
Read_Reg_Rst => Read_Reg_Rst,
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5),
\bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6),
bus2ip_rnw_i_reg => \^ip2bus_data_i_d1_reg[31]\,
gpio2_io_t(11 downto 0) => gpio2_io_t(11 downto 0),
gpio_io_t(3 downto 0) => gpio_io_t(3 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[20]\(11 downto 0) => \ip2bus_data_i_D1_reg[20]\(11 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
rst_reg => \^bus2ip_rnw_i_reg_0\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(11 downto 0) => s_axi_wdata(11 downto 0),
s_axi_wready => \^s_axi_wready\,
start2 => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(0),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(0),
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(1),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(1),
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(2),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(2),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(6),
R => \^bus2ip_rnw_i_reg_0\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(5),
R => \^bus2ip_rnw_i_reg_0\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \bus2ip_addr_i[8]_i_1_n_0\,
Q => bus2ip_addr(0),
R => \^bus2ip_rnw_i_reg_0\
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_arvalid,
I1 => state(0),
I2 => state(1),
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => bus2ip_rnw_i06_out,
Q => \^ip2bus_data_i_d1_reg[31]\,
R => \^bus2ip_rnw_i_reg_0\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state[1]_i_2_n_0\,
I2 => state(1),
I3 => state(0),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^bus2ip_rnw_i_reg_0\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000FFFF10000000"
)
port map (
I0 => state(1),
I1 => s_axi_arvalid,
I2 => s_axi_wvalid,
I3 => s_axi_awvalid,
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => state(1),
I5 => state(0),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^bus2ip_rnw_i_reg_0\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => p_1_in
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_1_in,
Q => \^bus2ip_rnw_i_reg_0\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(0),
Q => s_axi_rdata(0),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(10),
Q => s_axi_rdata(10),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(11),
Q => s_axi_rdata(11),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(1),
Q => s_axi_rdata(1),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(2),
Q => s_axi_rdata(2),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(3),
Q => s_axi_rdata(3),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(4),
Q => s_axi_rdata(4),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(5),
Q => s_axi_rdata(5),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(6),
Q => s_axi_rdata(6),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(7),
Q => s_axi_rdata(7),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(8),
Q => s_axi_rdata(8),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(9),
Q => s_axi_rdata(9),
R => \^bus2ip_rnw_i_reg_0\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^bus2ip_rnw_i_reg_0\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(0),
I4 => state(1),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^bus2ip_rnw_i_reg_0\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFFAACC"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_arvalid,
I2 => \state[1]_i_2_n_0\,
I3 => state(1),
I4 => state(0),
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2E2E2E2ECCCCFFCC"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(1),
I2 => \state[1]_i_2_n_0\,
I3 => \state[1]_i_3_n_0\,
I4 => s_axi_arvalid,
I5 => state(0),
O => \state[1]_i_1_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => state(0),
R => \^bus2ip_rnw_i_reg_0\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => state(1),
R => \^bus2ip_rnw_i_reg_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
\ip2bus_data_i_D1_reg[20]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 3 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 11 );
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg_Rst : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO2_DBus_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_t : in STD_LOGIC_VECTOR ( 11 downto 0 );
\Dual.gpio2_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aresetn : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\ip2bus_data_i_D1_reg[20]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_axi_gpio_led_0_axi_lite_ipif;
architecture STRUCTURE of system_axi_gpio_led_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_axi_gpio_led_0_slave_attachment
port map (
D(11 downto 0) => D(11 downto 0),
\Dual.gpio2_Data_In_reg[0]\(11 downto 0) => \Dual.gpio2_Data_In_reg[0]\(11 downto 0),
\Dual.gpio2_Data_Out_reg[0]\(0) => \Dual.gpio2_Data_Out_reg[0]\(0),
\Dual.gpio2_OE_reg[0]\(0) => \Dual.gpio2_OE_reg[0]\(0),
\Dual.gpio_Data_Out_reg[0]\(0) => \Dual.gpio_Data_Out_reg[0]\(0),
E(0) => E(0),
GPIO2_DBus_i(11 downto 0) => GPIO2_DBus_i(11 downto 0),
GPIO_DBus_i(3 downto 0) => GPIO_DBus_i(3 downto 0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
Q(3 downto 0) => Q(3 downto 0),
Read_Reg2_In(0 to 11) => Read_Reg2_In(0 to 11),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_rnw_i_reg_0 => bus2ip_reset,
gpio2_io_t(11 downto 0) => gpio2_io_t(11 downto 0),
gpio_io_t(3 downto 0) => gpio_io_t(3 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[20]\(11 downto 0) => \ip2bus_data_i_D1_reg[20]\(11 downto 0),
\ip2bus_data_i_D1_reg[20]_0\(11 downto 0) => \ip2bus_data_i_D1_reg[20]_0\(11 downto 0),
\ip2bus_data_i_D1_reg[31]\ => bus2ip_rnw,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(11 downto 0) => s_axi_rdata(11 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(11 downto 0) => s_axi_wdata(11 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_gpio_led_0_axi_gpio : entity is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of system_axi_gpio_led_0_axi_gpio : entity is 12;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of system_axi_gpio_led_0_axi_gpio : entity is 4;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of system_axi_gpio_led_0_axi_gpio : entity is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_gpio_led_0_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_gpio_led_0_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of system_axi_gpio_led_0_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of system_axi_gpio_led_0_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_led_0_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of system_axi_gpio_led_0_axi_gpio : entity is "LOGICORE";
end system_axi_gpio_led_0_axi_gpio;
architecture STRUCTURE of system_axi_gpio_led_0_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_14 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_15 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_16 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_18 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_35 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_36 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_49 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_50 : STD_LOGIC;
signal GPIO2_DBus_i : STD_LOGIC_VECTOR ( 20 to 31 );
signal GPIO_DBus : STD_LOGIC_VECTOR ( 11 downto 0 );
signal GPIO_DBus_i : STD_LOGIC_VECTOR ( 28 to 31 );
signal GPIO_xferAck_i : STD_LOGIC;
signal Read_Reg2_In : STD_LOGIC_VECTOR ( 0 to 11 );
signal Read_Reg_In : STD_LOGIC_VECTOR ( 0 to 3 );
signal Read_Reg_Rst : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio2_Data_In : STD_LOGIC_VECTOR ( 0 to 11 );
signal \^gpio2_io_t\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 3 );
signal gpio_core_1_n_19 : STD_LOGIC;
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
gpio2_io_t(11 downto 0) <= \^gpio2_io_t\(11 downto 0);
gpio_io_t(3 downto 0) <= \^gpio_io_t\(3 downto 0);
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11 downto 0) <= \^s_axi_rdata\(11 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.system_axi_gpio_led_0_axi_lite_ipif
port map (
D(11 downto 8) => p_0_out(3 downto 0),
D(7) => AXI_LITE_IPIF_I_n_11,
D(6) => AXI_LITE_IPIF_I_n_12,
D(5) => AXI_LITE_IPIF_I_n_13,
D(4) => AXI_LITE_IPIF_I_n_14,
D(3) => AXI_LITE_IPIF_I_n_15,
D(2) => AXI_LITE_IPIF_I_n_16,
D(1) => AXI_LITE_IPIF_I_n_17,
D(0) => AXI_LITE_IPIF_I_n_18,
\Dual.gpio2_Data_In_reg[0]\(11) => gpio2_Data_In(0),
\Dual.gpio2_Data_In_reg[0]\(10) => gpio2_Data_In(1),
\Dual.gpio2_Data_In_reg[0]\(9) => gpio2_Data_In(2),
\Dual.gpio2_Data_In_reg[0]\(8) => gpio2_Data_In(3),
\Dual.gpio2_Data_In_reg[0]\(7) => gpio2_Data_In(4),
\Dual.gpio2_Data_In_reg[0]\(6) => gpio2_Data_In(5),
\Dual.gpio2_Data_In_reg[0]\(5) => gpio2_Data_In(6),
\Dual.gpio2_Data_In_reg[0]\(4) => gpio2_Data_In(7),
\Dual.gpio2_Data_In_reg[0]\(3) => gpio2_Data_In(8),
\Dual.gpio2_Data_In_reg[0]\(2) => gpio2_Data_In(9),
\Dual.gpio2_Data_In_reg[0]\(1) => gpio2_Data_In(10),
\Dual.gpio2_Data_In_reg[0]\(0) => gpio2_Data_In(11),
\Dual.gpio2_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_50,
\Dual.gpio2_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_49,
\Dual.gpio_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_36,
E(0) => AXI_LITE_IPIF_I_n_35,
GPIO2_DBus_i(11) => GPIO2_DBus_i(20),
GPIO2_DBus_i(10) => GPIO2_DBus_i(21),
GPIO2_DBus_i(9) => GPIO2_DBus_i(22),
GPIO2_DBus_i(8) => GPIO2_DBus_i(23),
GPIO2_DBus_i(7) => GPIO2_DBus_i(24),
GPIO2_DBus_i(6) => GPIO2_DBus_i(25),
GPIO2_DBus_i(5) => GPIO2_DBus_i(26),
GPIO2_DBus_i(4) => GPIO2_DBus_i(27),
GPIO2_DBus_i(3) => GPIO2_DBus_i(28),
GPIO2_DBus_i(2) => GPIO2_DBus_i(29),
GPIO2_DBus_i(1) => GPIO2_DBus_i(30),
GPIO2_DBus_i(0) => GPIO2_DBus_i(31),
GPIO_DBus_i(3) => GPIO_DBus_i(28),
GPIO_DBus_i(2) => GPIO_DBus_i(29),
GPIO_DBus_i(1) => GPIO_DBus_i(30),
GPIO_DBus_i(0) => GPIO_DBus_i(31),
GPIO_xferAck_i => GPIO_xferAck_i,
Q(3) => gpio_Data_In(0),
Q(2) => gpio_Data_In(1),
Q(1) => gpio_Data_In(2),
Q(0) => gpio_Data_In(3),
Read_Reg2_In(0 to 11) => Read_Reg2_In(0 to 11),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio2_io_t(11 downto 0) => \^gpio2_io_t\(11 downto 0),
gpio_io_t(3 downto 0) => \^gpio_io_t\(3 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[20]\(11 downto 0) => GPIO_DBus(11 downto 0),
\ip2bus_data_i_D1_reg[20]_0\(11 downto 0) => ip2bus_data_i_D1(11 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(11 downto 0) => \^s_axi_rdata\(11 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(11 downto 0) => s_axi_wdata(11 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
gpio_core_1: entity work.system_axi_gpio_led_0_GPIO_Core
port map (
D(11 downto 8) => p_0_out(3 downto 0),
D(7) => AXI_LITE_IPIF_I_n_11,
D(6) => AXI_LITE_IPIF_I_n_12,
D(5) => AXI_LITE_IPIF_I_n_13,
D(4) => AXI_LITE_IPIF_I_n_14,
D(3) => AXI_LITE_IPIF_I_n_15,
D(2) => AXI_LITE_IPIF_I_n_16,
D(1) => AXI_LITE_IPIF_I_n_17,
D(0) => AXI_LITE_IPIF_I_n_18,
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(3) => gpio_Data_In(0),
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(2) => gpio_Data_In(1),
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(1) => gpio_Data_In(2),
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(0) => gpio_Data_In(3),
E(0) => AXI_LITE_IPIF_I_n_36,
GPIO2_DBus_i(11) => GPIO2_DBus_i(20),
GPIO2_DBus_i(10) => GPIO2_DBus_i(21),
GPIO2_DBus_i(9) => GPIO2_DBus_i(22),
GPIO2_DBus_i(8) => GPIO2_DBus_i(23),
GPIO2_DBus_i(7) => GPIO2_DBus_i(24),
GPIO2_DBus_i(6) => GPIO2_DBus_i(25),
GPIO2_DBus_i(5) => GPIO2_DBus_i(26),
GPIO2_DBus_i(4) => GPIO2_DBus_i(27),
GPIO2_DBus_i(3) => GPIO2_DBus_i(28),
GPIO2_DBus_i(2) => GPIO2_DBus_i(29),
GPIO2_DBus_i(1) => GPIO2_DBus_i(30),
GPIO2_DBus_i(0) => GPIO2_DBus_i(31),
GPIO_DBus_i(3) => GPIO_DBus_i(28),
GPIO_DBus_i(2) => GPIO_DBus_i(29),
GPIO_DBus_i(1) => GPIO_DBus_i(30),
GPIO_DBus_i(0) => GPIO_DBus_i(31),
GPIO_xferAck_i => GPIO_xferAck_i,
Q(11) => gpio2_Data_In(0),
Q(10) => gpio2_Data_In(1),
Q(9) => gpio2_Data_In(2),
Q(8) => gpio2_Data_In(3),
Q(7) => gpio2_Data_In(4),
Q(6) => gpio2_Data_In(5),
Q(5) => gpio2_Data_In(6),
Q(4) => gpio2_Data_In(7),
Q(3) => gpio2_Data_In(8),
Q(2) => gpio2_Data_In(9),
Q(1) => gpio2_Data_In(10),
Q(0) => gpio2_Data_In(11),
Read_Reg2_In(0 to 11) => Read_Reg2_In(0 to 11),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
Read_Reg_Rst => Read_Reg_Rst,
SS(0) => bus2ip_reset,
bus2ip_cs => bus2ip_cs,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg(0) => AXI_LITE_IPIF_I_n_35,
bus2ip_rnw_i_reg_0(0) => AXI_LITE_IPIF_I_n_50,
bus2ip_rnw_i_reg_1(0) => AXI_LITE_IPIF_I_n_49,
gpio2_io_i(11 downto 0) => gpio2_io_i(11 downto 0),
gpio2_io_o(11 downto 0) => gpio2_io_o(11 downto 0),
gpio2_io_t(11 downto 0) => \^gpio2_io_t\(11 downto 0),
gpio_io_i(3 downto 0) => gpio_io_i(3 downto 0),
gpio_io_o(3 downto 0) => gpio_io_o(3 downto 0),
gpio_io_t(3 downto 0) => \^gpio_io_t\(3 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_19,
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(11),
Q => ip2bus_data_i_D1(11),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(10),
Q => ip2bus_data_i_D1(10),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(9),
Q => ip2bus_data_i_D1(9),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(8),
Q => ip2bus_data_i_D1(8),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(7),
Q => ip2bus_data_i_D1(7),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(6),
Q => ip2bus_data_i_D1(6),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(5),
Q => ip2bus_data_i_D1(5),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(4),
Q => ip2bus_data_i_D1(4),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(3),
Q => ip2bus_data_i_D1(3),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(2),
Q => ip2bus_data_i_D1(2),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(1),
Q => ip2bus_data_i_D1(1),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_19,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_gpio_led_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_gpio_led_0 : entity is "system_axi_gpio_led_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_led_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_gpio_led_0 : entity is "axi_gpio,Vivado 2016.4";
end system_axi_gpio_led_0;
architecture STRUCTURE of system_axi_gpio_led_0 is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 12;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 4;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.system_axi_gpio_led_0_axi_gpio
port map (
gpio2_io_i(11 downto 0) => gpio2_io_i(11 downto 0),
gpio2_io_o(11 downto 0) => gpio2_io_o(11 downto 0),
gpio2_io_t(11 downto 0) => gpio2_io_t(11 downto 0),
gpio_io_i(3 downto 0) => gpio_io_i(3 downto 0),
gpio_io_o(3 downto 0) => gpio_io_o(3 downto 0),
gpio_io_t(3 downto 0) => gpio_io_t(3 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| apache-2.0 |
alainmarcel/Surelog | third_party/tests/ariane/fpga/src/apb_uart/src/uart_baudgen.vhd | 5 | 2234 | --
-- UART Baudrate generator
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART baudrate generator
entity uart_baudgen is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable
CLEAR : in std_logic; -- Reset generator (synchronization)
DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider
BAUDTICK : out std_logic -- 16xBaudrate tick
);
end uart_baudgen;
architecture rtl of uart_baudgen is
-- Signals
signal iCounter : unsigned(15 downto 0);
begin
-- Baudrate counter
BG_COUNT: process (CLK, RST)
begin
if (RST = '1') then
iCounter <= (others => '0');
BAUDTICK <= '0';
elsif (CLK'event and CLK = '1') then
if (CLEAR = '1') then
iCounter <= (others => '0');
elsif (CE = '1') then
iCounter <= iCounter + 1;
end if;
BAUDTICK <= '0';
if (iCounter = unsigned(DIVIDER)) then
iCounter <= (others => '0');
BAUDTICK <= '1';
end if;
end if;
end process;
end rtl;
| apache-2.0 |
alainmarcel/Surelog | third_party/tests/YosysTestSuite/sva/basic05.vhd | 11 | 473 | library ieee;
use ieee.std_logic_1164.all;
entity demo is
port (
clock : in std_logic;
ctrl : in std_logic;
x : out std_logic
);
end entity;
architecture rtl of demo is
signal read : std_logic := '0';
signal write : std_logic := '0';
signal ready : std_logic := '0';
begin
process (clock) begin
if (rising_edge(clock)) then
read <= not ctrl;
write <= ctrl;
ready <= write;
end if;
end process;
x <= read xor write xor ready;
end architecture;
| apache-2.0 |
Paebbels/PicoBlaze-Examples | vhdl/ExampleDesign/IICBus.vhdl | 1 | 12491 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Module: I2C Bus
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY PoC;
USE PoC.config.ALL;
USE PoC.utils.ALL;
USE PoC.vectors.ALL;
USE PoC.physical.ALL;
USE PoC.io.ALL;
ENTITY IICBus IS
GENERIC (
DEBUG : BOOLEAN := FALSE;
CLOCK_FREQ : FREQ := 100.0 MHz
);
PORT (
Clock : IN STD_LOGIC;
Reset : IN STD_LOGIC;
PUC_IICMaster_Request : IN STD_LOGIC;
PUC_IICMaster_Grant : OUT STD_LOGIC;
PUC_IICMaster_Command : IN T_IO_IIC_COMMAND;
PUC_IICMaster_Status : OUT T_IO_IIC_STATUS;
PUC_IICMaster_Error : OUT T_IO_IIC_ERROR;
PUC_IICMaster_Address : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
PUC_IICMaster_WP_Valid : IN STD_LOGIC;
PUC_IICMaster_WP_Data : IN T_SLV_8;
PUC_IICMaster_WP_Last : IN STD_LOGIC;
PUC_IICMaster_WP_Ack : OUT STD_LOGIC;
PUC_IICMaster_RP_Valid : OUT STD_LOGIC;
PUC_IICMaster_RP_Data : OUT T_SLV_8;
PUC_IICMaster_RP_Last : OUT STD_LOGIC;
PUC_IICMaster_RP_Ack : IN STD_LOGIC;
SFP_IICMaster_Request : IN STD_LOGIC;
SFP_IICMaster_Grant : OUT STD_LOGIC;
SFP_IICMaster_Command : IN T_IO_IIC_COMMAND;
SFP_IICMaster_Status : OUT T_IO_IIC_STATUS;
SFP_IICMaster_Error : OUT T_IO_IIC_ERROR;
SFP_IICMaster_Address : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
SFP_IICMaster_WP_Valid : IN STD_LOGIC;
SFP_IICMaster_WP_Data : IN T_SLV_8;
SFP_IICMaster_WP_Last : IN STD_LOGIC;
SFP_IICMaster_WP_Ack : OUT STD_LOGIC;
SFP_IICMaster_RP_Valid : OUT STD_LOGIC;
SFP_IICMaster_RP_Data : OUT T_SLV_8;
SFP_IICMaster_RP_Last : OUT STD_LOGIC;
SFP_IICMaster_RP_Ack : IN STD_LOGIC;
PB_IICMaster_Request : IN STD_LOGIC;
PB_IICMaster_Grant : OUT STD_LOGIC;
PB_IICMaster_Command : IN T_IO_IIC_COMMAND;
PB_IICMaster_Status : OUT T_IO_IIC_STATUS;
PB_IICMaster_Error : OUT T_IO_IIC_ERROR;
PB_IICMaster_Address : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
PB_IICMaster_WP_Valid : IN STD_LOGIC;
PB_IICMaster_WP_Data : IN T_SLV_8;
PB_IICMaster_WP_Last : IN STD_LOGIC;
PB_IICMaster_WP_Ack : OUT STD_LOGIC;
PB_IICMaster_RP_Valid : OUT STD_LOGIC;
PB_IICMaster_RP_Data : OUT T_SLV_8;
PB_IICMaster_RP_Last : OUT STD_LOGIC;
PB_IICMaster_RP_Ack : IN STD_LOGIC;
IIC_SerialClock_i : IN STD_LOGIC;
IIC_SerialClock_o : OUT STD_LOGIC;
IIC_SerialClock_t : OUT STD_LOGIC;
IIC_SerialData_i : IN STD_LOGIC;
IIC_SerialData_o : OUT STD_LOGIC;
IIC_SerialData_t : OUT STD_LOGIC;
IICSwitch_Reset : OUT STD_LOGIC
);
END;
ARCHITECTURE rtl OF IICBus IS
ATTRIBUTE KEEP : BOOLEAN;
CONSTANT IIC_BUSMODE : T_IO_IIC_BUSMODE := IO_IIC_BUSMODE_STANDARDMODE; -- 100 kHz
CONSTANT IICBUS_ADDRESS_BITS : POSITIVE := 7;
CONSTANT IICBUS_DATA_BITS : POSITIVE := 8;
CONSTANT IICSWITCH_ADDRESS : T_SLV_8 := x"00";
CONSTANT IICSWITCH_UNUSED_LIST : T_NATVEC := (1, 2, 3, 5, 6, 7);
-- 0 => 1, 1 => 2, 2 => 3,
-- 3 => 5, 4 => 6, 5 => 7
-- );
CONSTANT ADD_BYPASS_PORT : BOOLEAN := TRUE;
CONSTANT PORTS : POSITIVE := 9;
SIGNAL IICMasters_Request : STD_LOGIC_VECTOR(PORTS - 1 DOWNTO 0);
SIGNAL IICSwitch_Grant : STD_LOGIC_VECTOR(PORTS - 1 DOWNTO 0);
SIGNAL IICMasters_Command : T_IO_IIC_COMMAND_VECTOR(PORTS - 1 DOWNTO 0);
SIGNAL IICSwitch_Status : T_IO_IIC_STATUS_VECTOR(PORTS - 1 DOWNTO 0);
SIGNAL IICMasters_Error : T_IO_IIC_ERROR_VECTOR(PORTS - 1 DOWNTO 0);
SIGNAL IICMasters_Address : T_SLM(PORTS - 1 DOWNTO 0, IICBUS_ADDRESS_BITS - 1 DOWNTO 0) := (OTHERS => (OTHERS => 'Z'));
SIGNAL IICMasters_WP_Valid : STD_LOGIC_VECTOR(PORTS - 1 DOWNTO 0);
SIGNAL IICMasters_WP_Data : T_SLM(PORTS - 1 DOWNTO 0, IICBUS_DATA_BITS - 1 DOWNTO 0) := (OTHERS => (OTHERS => 'Z'));
SIGNAL IICMasters_WP_Last : STD_LOGIC_VECTOR(PORTS - 1 DOWNTO 0);
SIGNAL IICSwitch_WP_Ack : STD_LOGIC_VECTOR(PORTS - 1 DOWNTO 0);
SIGNAL IICSwitch_RP_Valid : STD_LOGIC_VECTOR(PORTS - 1 DOWNTO 0);
SIGNAL IICSwitch_RP_Data : T_SLM(PORTS - 1 DOWNTO 0, IICBUS_DATA_BITS - 1 DOWNTO 0);-- := (OTHERS => (OTHERS => 'Z'));
SIGNAL IICSwitch_RP_Last : STD_LOGIC_VECTOR(PORTS - 1 DOWNTO 0);
SIGNAL IICMasters_RP_Ack : STD_LOGIC_VECTOR(PORTS - 1 DOWNTO 0);
SIGNAL IICSwitch_IICC_Request : STD_LOGIC;
SIGNAL IICC_IICSwitch_Grant : STD_LOGIC;
SIGNAL IICSwitch_IICC_Command : T_IO_IIC_COMMAND;
SIGNAL IICC_IICSwitch_Status : T_IO_IIC_STATUS;
SIGNAL IICC_IICSwitch_Error : T_IO_IIC_ERROR;
SIGNAL IICSWITCH_IICC_Address : STD_LOGIC_VECTOR(IICBUS_ADDRESS_BITS - 1 DOWNTO 0);
SIGNAL IICSwitch_IICC_Valid : STD_LOGIC;
SIGNAL IICSwitch_IICC_Data : STD_LOGIC_VECTOR(IICBUS_DATA_BITS - 1 DOWNTO 0);
SIGNAL IICSwitch_IICC_Last : STD_LOGIC;
SIGNAL IICC_IICSwitch_Ack : STD_LOGIC;
SIGNAL IICC_IICSwitch_Valid : STD_LOGIC;
SIGNAL IICC_IICSwitch_Data : STD_LOGIC_VECTOR(IICBUS_DATA_BITS - 1 DOWNTO 0);
SIGNAL IICC_IICSwitch_Last : STD_LOGIC;
SIGNAL IICSwitch_IICC_Ack : STD_LOGIC;
BEGIN
-- I2C 8-Channel Switch Ports
-- ==========================================================================
-- Port 0 - programmable user clock
IICMasters_Request(0) <= PUC_IICMaster_Request;
PUC_IICMaster_Grant <= IICSwitch_Grant(0);
IICMasters_Command(0) <= PUC_IICMaster_Command;
PUC_IICMaster_Status <= IICSwitch_Status(0);
PUC_IICMaster_Error <= IICMasters_Error(0);
assign_row(IICMasters_Address, PUC_IICMaster_Address, 0);
IICMasters_WP_Valid(0) <= PUC_IICMaster_WP_Valid;
assign_row(IICMasters_WP_Data, PUC_IICMaster_WP_Data, 0);
IICMasters_WP_Last(0) <= PUC_IICMaster_WP_Last;
PUC_IICMaster_WP_Ack <= IICSwitch_WP_Ack(0);
PUC_IICMaster_RP_Valid <= IICSwitch_RP_Valid(0);
PUC_IICMaster_RP_Data <= get_row(IICSwitch_RP_Data, 0);
PUC_IICMaster_RP_Last <= IICSwitch_RP_Last(0);
IICMasters_RP_Ack(0) <= PUC_IICMaster_RP_Ack;
-- Port 4 - SFP+ cage
IICMasters_Request(4) <= SFP_IICMaster_Request;
SFP_IICMaster_Grant <= IICSwitch_Grant(4);
IICMasters_Command(4) <= SFP_IICMaster_Command;
SFP_IICMaster_Status <= IICSwitch_Status(4);
SFP_IICMaster_Error <= IICMasters_Error(4);
assign_row(IICMasters_Address, SFP_IICMaster_Address, 4);
IICMasters_WP_Valid(4) <= SFP_IICMaster_WP_Valid;
assign_row(IICMasters_WP_Data, SFp_IICMaster_WP_Data, 4);
IICMasters_WP_Last(4) <= SFP_IICMaster_WP_Last;
SFP_IICMaster_WP_Ack <= IICSwitch_WP_Ack(4);
SFP_IICMaster_RP_Valid <= IICSwitch_RP_Valid(4);
SFP_IICMaster_RP_Data <= get_row(IICSwitch_RP_Data, 4);
SFP_IICMaster_RP_Last <= IICSwitch_RP_Last(4);
IICMasters_RP_Ack(4) <= SFP_IICMaster_RP_Ack;
-- Port 8 (bypass) - MicroControllerAdapter
IICMasters_Request(8) <= PB_IICMaster_Request;
PB_IICMaster_Grant <= IICSwitch_Grant(8);
IICMasters_Command(8) <= PB_IICMaster_Command;
PB_IICMaster_Status <= IICSwitch_Status(8);
PB_IICMaster_Error <= IICMasters_Error(8);
assign_row(IICMasters_Address, PB_IICMaster_Address, 8);
IICMasters_WP_Valid(8) <= PB_IICMaster_WP_Valid;
assign_row(IICMasters_WP_Data, PB_IICMaster_WP_Data, 8);
IICMasters_WP_Last(8) <= PB_IICMaster_WP_Last;
PB_IICMaster_WP_Ack <= IICSwitch_WP_Ack(8);
PB_IICMaster_RP_Valid <= IICSwitch_RP_Valid(8);
PB_IICMaster_RP_Data <= get_row(IICSwitch_RP_Data, 8);
PB_IICMaster_RP_Last <= IICSwitch_RP_Last(8);
IICMasters_RP_Ack(8) <= PB_IICMaster_RP_Ack;
-- unused ports
genUnused : FOR I IN IICSWITCH_UNUSED_LIST'range GENERATE
IICMasters_Request( IICSWITCH_UNUSED_LIST(I)) <= '0';
IICMasters_Command( IICSWITCH_UNUSED_LIST(I)) <= IO_IIC_CMD_NONE;
IICMasters_WP_Valid(IICSWITCH_UNUSED_LIST(I)) <= '0';
IICMasters_WP_Last( IICSWITCH_UNUSED_LIST(I)) <= '0';
IICMasters_RP_Ack( IICSWITCH_UNUSED_LIST(I)) <= '0';
assign_row(IICMasters_Address, (0 TO IICBUS_ADDRESS_BITS - 1 => '0'), IICSWITCH_UNUSED_LIST(I));
assign_row(IICMasters_WP_Data, (0 TO IICBUS_DATA_BITS - 1 => '0'), IICSWITCH_UNUSED_LIST(I));
END GENERATE;
IICSwitch : ENTITY PoC.iic_IICSwitch_PCA9548A
GENERIC MAP (
DEBUG => DEBUG,
ALLOW_MEALY_TRANSITION => FALSE,
SWITCH_ADDRESS => IICSWITCH_ADDRESS,
ADD_BYPASS_PORT => ADD_BYPASS_PORT,
ADDRESS_BITS => IICBUS_ADDRESS_BITS,
DATA_BITS => IICBUS_DATA_BITS
)
PORT MAP (
Clock => Clock,
Reset => Reset,
-- IICSwitch interface ports
Request => IICMasters_Request,
Grant => IICSwitch_Grant,
Command => IICMasters_Command,
Status => IICSwitch_Status,
Error => IICMasters_Error,
Address => IICMasters_Address,
WP_Valid => IICMasters_WP_Valid,
WP_Data => IICMasters_WP_Data,
WP_Last => IICMasters_WP_Last,
WP_Ack => IICSwitch_WP_Ack,
RP_Valid => IICSwitch_RP_Valid,
RP_Data => IICSwitch_RP_Data,
RP_Last => IICSwitch_RP_Last,
RP_Ack => IICMasters_RP_Ack,
-- IICController master interface
IICC_Request => IICSwitch_IICC_Request,
IICC_Grant => IICC_IICSwitch_Grant,
IICC_Command => IICSwitch_IICC_Command,
IICC_Status => IICC_IICSwitch_Status,
IICC_Error => IICC_IICSwitch_Error,
IICC_Address => IICSWITCH_IICC_Address,
IICC_WP_Valid => IICSwitch_IICC_Valid,
IICC_WP_Data => IICSwitch_IICC_Data,
IICC_WP_Last => IICSwitch_IICC_Last,
IICC_WP_Ack => IICC_IICSwitch_Ack,
IICC_RP_Valid => IICC_IICSwitch_Valid,
IICC_RP_Data => IICC_IICSwitch_Data,
IICC_RP_Last => IICC_IICSwitch_Last,
IICC_RP_Ack => IICSwitch_IICC_Ack,
IICSwitch_Reset => IICSwitch_Reset
);
IICC : ENTITY PoC.iic_IICController
GENERIC MAP (
DEBUG => DEBUG,
ALLOW_MEALY_TRANSITION => FALSE,
CLOCK_FREQ => CLOCK_FREQ,
IIC_BUSMODE => IIC_BUSMODE,
IIC_ADDRESS => x"01",
ADDRESS_BITS => IICBUS_ADDRESS_BITS,
DATA_BITS => IICBUS_DATA_BITS
)
PORT MAP (
Clock => Clock,
Reset => Reset,
-- IICController master interface
Master_Request => IICSwitch_IICC_Request,
Master_Grant => IICC_IICSwitch_Grant,
Master_Command => IICSwitch_IICC_Command,
Master_Status => IICC_IICSwitch_Status,
Master_Error => IICC_IICSwitch_Error,
Master_Address => IICSWITCH_IICC_Address,
Master_WP_Valid => IICSwitch_IICC_Valid,
Master_WP_Data => IICSwitch_IICC_Data,
Master_WP_Last => IICSwitch_IICC_Last,
Master_WP_Ack => IICC_IICSwitch_Ack,
Master_RP_Valid => IICC_IICSwitch_Valid,
Master_RP_Data => IICC_IICSwitch_Data,
Master_RP_Last => IICC_IICSwitch_Last,
Master_RP_Ack => IICSwitch_IICC_Ack,
-- tristate interface
SerialClock_i => IIC_SerialClock_i,
SerialClock_o => IIC_SerialClock_o,
SerialClock_t => IIC_SerialClock_t,
SerialData_i => IIC_SerialData_i,
SerialData_o => IIC_SerialData_o,
SerialData_t => IIC_SerialData_t
);
END;
| apache-2.0 |
Paebbels/PicoBlaze-Examples | netlist/XC6SLX45-3CSG324/CSP_ControlVIO.vhdl | 1 | 1086 | -------------------------------------------------------------------------------
-- Copyright (c) 2015 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application: XILINX CORE Generator
-- / / Filename : CSP_ControlVIO.vhd
-- /___/ /\ Timestamp : Fri Jun 26 19:02:38 Mitteleuropäische Sommerzeit 2015
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CSP_ControlVIO IS
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
SYNC_IN: in std_logic_vector(7 downto 0);
SYNC_OUT: out std_logic_vector(7 downto 0));
END CSP_ControlVIO;
ARCHITECTURE CSP_ControlVIO_a OF CSP_ControlVIO IS
BEGIN
END CSP_ControlVIO_a;
| apache-2.0 |
flink-project/flinkvhdl | axiComponents/subDevices/fqdDevice/hdl/fqdDevice.vhd | 1 | 5895 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fqdDevice is
generic (
-- Users to add parameters here
unique_id : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
number_of_fqds: INTEGER RANGE 0 TO 64 := 1;--number of fqds which will be generated
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_ID_WIDTH : integer := 1;
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 12
);
port (
-- Users to add ports here
islv_enc_A : IN STD_LOGIC_VECTOR(number_of_fqds-1 DOWNTO 0);
islv_enc_B : IN STD_LOGIC_VECTOR(number_of_fqds-1 DOWNTO 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awid : in std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awlen : in std_logic_vector(7 downto 0);
s00_axi_awsize : in std_logic_vector(2 downto 0);
s00_axi_awburst : in std_logic_vector(1 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wlast : in std_logic;
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bid : out std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_arid : in std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arlen : in std_logic_vector(7 downto 0);
s00_axi_arsize : in std_logic_vector(2 downto 0);
s00_axi_arburst : in std_logic_vector(1 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rid : out std_logic_vector(C_S00_AXI_ID_WIDTH-1 downto 0);
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rlast : out std_logic;
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end fqdDevice;
architecture arch_imp of fqdDevice is
-- component declaration
component fqdDevice_S00_AXI is
generic (
unique_id : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
number_of_fqds: INTEGER RANGE 0 TO 16 := 1;--number of fqds which will be generated
C_S_AXI_ID_WIDTH : integer := 1;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 12
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
islv_enc_A : IN STD_LOGIC_VECTOR(number_of_fqds-1 DOWNTO 0);
islv_enc_B : IN STD_LOGIC_VECTOR(number_of_fqds-1 DOWNTO 0)
);
end component fqdDevice_S00_AXI;
begin
-- Instantiation of Axi Bus Interface S00_AXI
fqdDevice_S00_AXI_inst : fqdDevice_S00_AXI
generic map (
unique_id => unique_id,
number_of_fqds => number_of_fqds,
C_S_AXI_ID_WIDTH => C_S00_AXI_ID_WIDTH,
C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH
)
port map (
S_AXI_ACLK => s00_axi_aclk,
S_AXI_ARESETN => s00_axi_aresetn,
S_AXI_AWID => s00_axi_awid,
S_AXI_AWADDR => s00_axi_awaddr,
S_AXI_AWLEN => s00_axi_awlen,
S_AXI_AWSIZE => s00_axi_awsize,
S_AXI_AWBURST => s00_axi_awburst,
S_AXI_AWVALID => s00_axi_awvalid,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WDATA => s00_axi_wdata,
S_AXI_WSTRB => s00_axi_wstrb,
S_AXI_WLAST => s00_axi_wlast,
S_AXI_WVALID => s00_axi_wvalid,
S_AXI_WREADY => s00_axi_wready,
S_AXI_BID => s00_axi_bid,
S_AXI_BRESP => s00_axi_bresp,
S_AXI_BVALID => s00_axi_bvalid,
S_AXI_BREADY => s00_axi_bready,
S_AXI_ARID => s00_axi_arid,
S_AXI_ARADDR => s00_axi_araddr,
S_AXI_ARLEN => s00_axi_arlen,
S_AXI_ARSIZE => s00_axi_arsize,
S_AXI_ARBURST => s00_axi_arburst,
S_AXI_ARVALID => s00_axi_arvalid,
S_AXI_ARREADY => s00_axi_arready,
S_AXI_RID => s00_axi_rid,
S_AXI_RDATA => s00_axi_rdata,
S_AXI_RRESP => s00_axi_rresp,
S_AXI_RLAST => s00_axi_rlast,
S_AXI_RVALID => s00_axi_rvalid,
S_AXI_RREADY => s00_axi_rready,
islv_enc_A => islv_enc_A,
islv_enc_B => islv_enc_B
);
-- Add user logic here
-- User logic ends
end arch_imp;
| apache-2.0 |
flink-project/flinkvhdl | avalonComponents/busInterfaces/eim_slave_to_avalon_master/src/eim_slave_to_avalon_master.m.vhd | 4 | 7097 | -------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE eim_slave_to_avalon_master_pkg IS
COMPONENT eim_slave_to_avalon_master IS
GENERIC(
TRANSFER_WIDTH : INTEGER := 16
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
--eim_interface
islv_address : IN STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
ioslv_data : INOUT STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
isl_cs_n : IN STD_LOGIC;
isl_we_n : IN STD_LOGIC;
isl_oe_n : IN STD_LOGIC;
osl_data_ack : OUT STD_LOGIC;
--avalon master
oslv_address : OUT STD_LOGIC_VECTOR (TRANSFER_WIDTH-1 DOWNTO 0);
oslv_read : OUT STD_LOGIC;
islv_readdata : IN STD_LOGIC_VECTOR (TRANSFER_WIDTH-1 DOWNTO 0);
oslv_write : OUT STD_LOGIC;
oslv_writedata : OUT STD_LOGIC_VECTOR (TRANSFER_WIDTH-1 DOWNTO 0);
islv_waitrequest: IN STD_LOGIC
);
END COMPONENT eim_slave_to_avalon_master;
END PACKAGE eim_slave_to_avalon_master_pkg;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.eim_slave_to_avalon_master_pkg.ALL;
USE work.eim_slave_pkg.ALL;
ENTITY eim_slave_to_avalon_master IS
GENERIC(
TRANSFER_WIDTH : INTEGER := 16
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
--eim_interface
islv_address : IN STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
ioslv_data : INOUT STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
isl_cs_n : IN STD_LOGIC;
isl_we_n : IN STD_LOGIC;
isl_oe_n : IN STD_LOGIC;
osl_data_ack : OUT STD_LOGIC;
--avalon master
oslv_address : OUT STD_LOGIC_VECTOR (TRANSFER_WIDTH-1 DOWNTO 0);
oslv_read : OUT STD_LOGIC;
islv_readdata : IN STD_LOGIC_VECTOR (TRANSFER_WIDTH-1 DOWNTO 0);
oslv_write : OUT STD_LOGIC;
oslv_writedata : OUT STD_LOGIC_VECTOR (TRANSFER_WIDTH-1 DOWNTO 0);
islv_waitrequest: IN STD_LOGIC
);
END ENTITY eim_slave_to_avalon_master;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF eim_slave_to_avalon_master IS
TYPE t_states IS ( idle,wait_for_read_data,wait_for_write_done);
TYPE t_internal_register IS RECORD
state : t_states;
slv_read_data : STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
sl_read_data_valid : STD_LOGIC;
avalon_address : STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
avalon_writedata : STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
read : STD_LOGIC;
write : STD_LOGIC;
END RECORD;
SIGNAL ri, ri_next : t_internal_register;
SIGNAL slv_address_out : STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
SIGNAL sl_read_not_write : STD_LOGIC;
SIGNAL sl_got_address : STD_LOGIC;
SIGNAL slv_write_data : STD_LOGIC_VECTOR(TRANSFER_WIDTH-1 DOWNTO 0);
SIGNAL sl_got_write_data : STD_LOGIC;
BEGIN
my_eim : eim_slave
GENERIC MAP(TRANSFER_WIDTH)
PORT MAP(isl_clk,isl_reset_n,islv_address,isl_cs_n,isl_we_n,isl_oe_n,osl_data_ack,ioslv_data,slv_address_out,sl_read_not_write,sl_got_address,ri.slv_read_data,ri.sl_read_data_valid,slv_write_data,sl_got_write_data);
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,sl_got_address,sl_read_not_write,slv_address_out,islv_waitrequest,islv_readdata)
VARIABLE vi: t_internal_register;
BEGIN
-- keep variables stable
vi:=ri;
vi.sl_read_data_valid := '0';
CASE vi.state IS
WHEN idle =>
IF sl_got_address = '1' THEN
vi.avalon_address := slv_address_out;
IF sl_read_not_write = '1' THEN --read transfer;
vi.read := '1';
vi.state := wait_for_read_data;
END IF;
END IF;
IF sl_got_write_data = '1' THEN
vi.avalon_writedata := slv_write_data;
vi.write := '1';
vi.state := wait_for_write_done;
END IF;
WHEN wait_for_read_data =>
IF islv_waitrequest = '0' THEN
vi.slv_read_data := islv_readdata;
vi.sl_read_data_valid := '1';
vi.read := '0';
vi.state := idle;
END IF;
WHEN wait_for_write_done =>
IF islv_waitrequest = '0' THEN
vi.write := '0';
vi.state := idle;
END IF;
WHEN OTHERS =>
vi.state := idle;
END CASE;
--reset signal
IF isl_reset_n = '0' THEN
vi.state := idle;
vi.slv_read_data := (OTHERS => '0');
vi.sl_read_data_valid := '0';
vi.avalon_address := (OTHERS => '0');
vi.avalon_writedata := (OTHERS => '0');
vi.read := '0';
vi.write:= '0';
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
oslv_address <= ri.avalon_address;
oslv_read <= ri.read;
oslv_write <= ri.write;
oslv_writedata <= ri.avalon_writedata;
END ARCHITECTURE rtl;
| apache-2.0 |
todaychi/hue | tools/ace-editor/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| apache-2.0 |
flink-project/flinkvhdl | avalonComponents/busInterfaces/spi_slave_to_avalon_master/sim/spi_slave_to_avalon_master_tb_16.vhd | 1 | 4301 | -------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
USE work.spi_slave_to_avalon_master_pkg.ALL;
ENTITY spi_slave_to_avalon_master_tb IS
END ENTITY spi_slave_to_avalon_master_tb;
ARCHITECTURE sim OF spi_slave_to_avalon_master_tb IS
CONSTANT main_period : TIME := 8 ns; -- 125MHz
CONSTANT spi_period : TIME := 40 ns; -- 25MHz
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '1';
SIGNAL sl_sclk : STD_LOGIC := '0';
SIGNAL sl_ss : STD_LOGIC := '1';
SIGNAL sl_mosi : STD_LOGIC := '0';
SIGNAL sl_miso : STD_LOGIC := '0';
SIGNAL slv_address : STD_LOGIC_VECTOR (31 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_read : STD_LOGIC:= '0';
SIGNAL slv_write : STD_LOGIC:= '0';
SIGNAL slv_readdata : STD_LOGIC_VECTOR(31 DOWNTO 0):= (OTHERS =>'1');
SIGNAL slv_writedata : STD_LOGIC_VECTOR(31 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_waitrequest : STD_LOGIC:= '0';
BEGIN
--create component
my_unit_under_test : spi_slave_to_avalon_master
GENERIC MAP(
TRANSFER_WIDTH => 16,
CPOL => '0',
CPHA => '0',
SSPOL => '0'
)
PORT MAP(
isl_clk => sl_clk,
isl_reset_n => sl_reset_n,
isl_sclk => sl_sclk,
isl_ss => sl_ss,
isl_mosi => sl_mosi,
osl_miso => sl_miso,
oslv_address => slv_address,
oslv_read => slv_read,
islv_readdata => slv_readdata,
oslv_write => slv_write,
oslv_writedata => slv_writedata,
islv_waitrequest => slv_waitrequest
);
sl_clk <= NOT sl_clk after main_period/2;
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '1';
WAIT FOR 100*main_period;
sl_reset_n <= '0';
WAIT FOR 100*main_period;
sl_reset_n <= '1';
WAIT FOR 100*main_period;
--write transfer whit only 1's
sl_mosi <='1';
FOR u IN 0 TO 3 LOOP
sl_ss <= '0';
WAIT FOR spi_period;
FOR i IN 0 TO 31 LOOP
sl_sclk <= NOT sl_sclk;
WAIT FOR spi_period;
END LOOP;
WAIT FOR 10*main_period;
sl_sclk <= '0';
sl_ss <= '1';
WAIT FOR 100*main_period;
END LOOP;
sl_mosi <= '0';
WAIT FOR 1000*main_period;
--read transfer on address 0x0FFFFFF
sl_mosi <='0';
FOR u IN 0 TO 3 LOOP
sl_ss <= '0';
IF(u /= 0) THEN
sl_mosi <='1';
END IF;
WAIT FOR spi_period;
FOR i IN 0 TO 31 LOOP
sl_sclk <= NOT sl_sclk;
WAIT FOR spi_period;
END LOOP;
WAIT FOR 10*main_period;
sl_sclk <= '0';
sl_ss <= '1';
WAIT FOR 100*main_period;
END LOOP;
sl_mosi <= '0';
WAIT FOR 1000*main_period;
WAIT FOR 1000*main_period;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
END ARCHITECTURE sim;
| apache-2.0 |
flink-project/flinkvhdl | functionalBlocks/dacad5668/src/dacad5668.m.vhd | 4 | 8301 | -------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE dacad5668_pkg IS
CONSTANT NUMBER_OF_CHANNELS : INTEGER := 8;
CONSTANT RESOLUTION : INTEGER := 16;
TYPE t_value_regs IS ARRAY(NUMBER_OF_CHANNELS -1 DOWNTO 0) OF STD_LOGIC_VECTOR(RESOLUTION-1 DOWNTO 0);
COMPONENT dacad5668 IS
GENERIC(
BASE_CLK : INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 8000000; --Max 50MHz
INTERNAL_REFERENCE : STD_LOGIC := '0' -- '0' = external reference, '1' internal reference
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
it_set_values : IN t_value_regs;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC
);
END COMPONENT dacad5668;
END PACKAGE dacad5668_pkg;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.dacad5668_pkg.ALL;
USE work.spi_master_pkg.ALL;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
ENTITY dacad5668 IS
GENERIC(
BASE_CLK : INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000; --Max 50MHz
INTERNAL_REFERENCE : STD_LOGIC := '0' -- '0' = external reference, '1' internal reference
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
it_set_values : IN t_value_regs;
osl_LDAC_n : OUT STD_LOGIC;
osl_CLR_n : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC
);
END ENTITY dacad5668;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF dacad5668 IS
CONSTANT SS_HOLD_CYCLES : INTEGER := 40; -- minimum 15ns see datasheet
CONSTANT CHANNEL_COUNT_WIDTH : INTEGER := 4;
CONSTANT TRANSFER_WIDTH : INTEGER := 32;
--COMMAND CODES
CONSTANT WRITE_AND_UPDATE_CHANNEL_N : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT SETUP_INTERNAL_REF : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";
TYPE t_states IS (idle,wait_for_transfer_to_finish,wait_for_next_transfer,set_internal_reference,keep_clear_low,wait_after_reset);
TYPE t_internal_register IS RECORD
state :t_states;
tx_data : STD_LOGIC_VECTOR(TRANSFER_WIDTH -1 DOWNTO 0);
tx_start : STD_LOGIC;
channel_count : UNSIGNED(CHANNEL_COUNT_WIDTH-1 DOWNTO 0);
cycle_count : UNSIGNED(6 DOWNTO 0);
LDAC_n : STD_LOGIC;
CLR_n : STD_LOGIC;
END RECORD;
SIGNAL slv_rx_data : STD_LOGIC_VECTOR(TRANSFER_WIDTH -1 DOWNTO 0);
SIGNAL sl_rx_done : STD_LOGIC;
SIGNAL ri, ri_next : t_internal_register;
BEGIN
my_spi_master : spi_master
GENERIC MAP(
BASE_CLK => BASE_CLK,
SCLK_FREQUENCY => SCLK_FREQUENCY,
CS_SETUP_CYLES => SS_HOLD_CYCLES,
TRANSFER_WIDTH => TRANSFER_WIDTH, -- 32 bit per transfer see data sheet
NR_OF_SS => 1, -- only one ss is needed
CPOL => '0', -- sckl inactive high
CPHA => '1', -- data is captured on the tailing edge see data sheet
MSBFIRST => '1', -- MSB first
SSPOL => '0' -- zero active see data sheet
)
PORT MAP(
isl_clk => isl_clk,
isl_reset_n => isl_reset_n,
islv_tx_data => ri.tx_data,
isl_tx_start => ri.tx_start,
oslv_rx_data => slv_rx_data,
osl_rx_done => sl_rx_done,
islv_ss_activ(0) => '1',
osl_sclk => osl_sclk,
oslv_Ss(0) => oslv_Ss,
osl_mosi => osl_mosi,
isl_miso => '0'
);
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,sl_rx_done,slv_rx_data,it_set_values)
VARIABLE vi: t_internal_register;
BEGIN
-- keep variables stable
vi:=ri;
--standard values
vi.tx_start := '0';
vi.LDAC_n := '0';
vi.CLR_n := '1';
CASE vi.state IS
WHEN keep_clear_low =>
vi.CLR_n := '0';
IF vi.cycle_count = 10 THEN
vi.state := wait_after_reset;
vi.cycle_count := (OTHERS => '0');
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN wait_after_reset =>
IF vi.cycle_count = 100 THEN
vi.state := set_internal_reference;
vi.cycle_count := (OTHERS => '0');
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN set_internal_reference =>
vi.tx_data := (OTHERS => '0');
vi.tx_data(TRANSFER_WIDTH -5 DOWNTO TRANSFER_WIDTH-8) := SETUP_INTERNAL_REF;
vi.tx_data(0) := INTERNAL_REFERENCE;
vi.tx_start := '1';
vi.state := wait_for_transfer_to_finish;
WHEN idle =>
vi.tx_data := (OTHERS => '0');
vi.tx_data(TRANSFER_WIDTH -5 DOWNTO TRANSFER_WIDTH-8) := WRITE_AND_UPDATE_CHANNEL_N;
vi.tx_data(TRANSFER_WIDTH -9 DOWNTO TRANSFER_WIDTH-12) := STD_LOGIC_VECTOR(vi.channel_count);
vi.tx_data(TRANSFER_WIDTH -13 DOWNTO TRANSFER_WIDTH-28) := it_set_values(to_integer(vi.channel_count));
vi.tx_start := '1';
vi.state := wait_for_transfer_to_finish;
WHEN wait_for_transfer_to_finish =>
IF sl_rx_done = '1' THEN
vi.state := wait_for_next_transfer;
vi.cycle_count := (OTHERS => '0');
END IF;
WHEN wait_for_next_transfer =>
IF vi.cycle_count = 100 THEN
vi.cycle_count := to_unsigned(0,7);
IF vi.channel_count = NUMBER_OF_CHANNELS -1 THEN
vi.channel_count := to_unsigned(0,CHANNEL_COUNT_WIDTH);
ELSE
vi.channel_count := vi.channel_count + 1;
END IF;
vi.state := idle;
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN OTHERS =>
vi.state := idle;
END CASE;
--reset
IF isl_reset_n = '0' THEN
vi.state := keep_clear_low;
vi.tx_data := (OTHERS => '0');
vi.tx_start := '0';
vi.channel_count := to_unsigned(0,CHANNEL_COUNT_WIDTH);
vi.cycle_count := (OTHERS => '0');
vi.CLR_n := '0';
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
osl_LDAC_n <= ri.LDAC_n;
osl_CLR_N <= ri.CLR_n;
END ARCHITECTURE rtl;
| apache-2.0 |
flink-project/flinkvhdl | functionalBlocks/fqd/sim/fqd_rtl_tb.vhd | 1 | 3369 | -------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.fqd_pkg.ALL;
ENTITY fqd_rtl_tb IS
END ENTITY fqd_rtl_tb;
ARCHITECTURE sim OF fqd_rtl_tb IS
--Sumulation Parameter:
CONSTANT main_period : TIME := 8 ns; -- 125MHz
CONSTANT velocity : REAL := 20000.0;--500.0; --1/s
CONSTANT direction : INTEGER := 1; -- forwards:1 backwards: -1
CONSTANT enc_tick_per_turn : REAL := 512.0;
CONSTANT wait_time : TIME := (1.0/velocity/enc_tick_per_turn/4.0)*1sec;
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '0';
SIGNAL sl_enc_A : STD_LOGIC := '0';
SIGNAL sl_enc_B : STD_LOGIC := '0';
SIGNAL usig_pos : UNSIGNED(15 DOWNTO 0) := (OTHERS => '0');
BEGIN
--create component
my_unit_under_test : fqd PORT MAP(
isl_clk => sl_clk,
isl_reset_n => sl_reset_n,
isl_enc_A => sl_enc_A,
isl_enc_B => sl_enc_B,
ousig_pos => usig_pos
);
sl_clk <= NOT sl_clk after main_period/2;
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '0';
WAIT FOR 2*main_period;
sl_reset_n <= '1';
WAIT FOR 1000*main_period;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
enc_sim : PROCESS
BEGIN
WHILE TRUE LOOP
IF direction >= 0 THEN
sl_enc_A <= '1';
WAIT FOR wait_time;
sl_enc_B <= '1';
WAIT FOR wait_time;
sl_enc_A <= '0';
WAIT FOR wait_time;
sl_enc_B <= '0';
WAIT FOR wait_time;
ELSE
sl_enc_B <= '1';
WAIT FOR wait_time;
sl_enc_A <= '1';
WAIT FOR wait_time;
sl_enc_B <= '0';
WAIT FOR wait_time;
sl_enc_A <= '0';
WAIT FOR wait_time;
END IF;
END LOOP;
END PROCESS enc_sim;
END ARCHITECTURE sim;
| apache-2.0 |
flink-project/flinkvhdl | functionalBlocks/adc128S102/src/adc128S102.m.vhd | 1 | 7312 | -------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
-------------------------------------------------------------------------------
-- PACKAGE DEFINITION
-------------------------------------------------------------------------------
PACKAGE adc128S102_pkg IS
CONSTANT NUMBER_OF_CHANNELS : INTEGER := 8;
CONSTANT RESOLUTION : INTEGER := 12;
TYPE t_value_regs IS ARRAY(NUMBER_OF_CHANNELS -1 DOWNTO 0) OF STD_LOGIC_VECTOR(RESOLUTION-1 DOWNTO 0);
COMPONENT adc128S102 IS
GENERIC(
BASE_CLK : INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 8000000 --Min 0.8 Mhz, max 16Mhz
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
ot_values : OUT t_value_regs;
osl_sclk : OUT STD_LOGIC;
osl_ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC
);
END COMPONENT adc128S102;
END PACKAGE adc128S102_pkg;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.adc128S102_pkg.ALL;
USE work.spi_master_pkg.ALL;
-------------------------------------------------------------------------------
-- ENTITIY
-------------------------------------------------------------------------------
ENTITY adc128S102 IS
GENERIC(
BASE_CLK : INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 8000000 --Min 0.8 Mhz, max 16Mhz
);
PORT(
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
ot_values : OUT t_value_regs;
osl_sclk : OUT STD_LOGIC;
osl_ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC
);
END ENTITY adc128S102;
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF adc128S102 IS
CONSTANT SS_HOLD_FREQUENCY : INTEGER := 100000000; -- (10ns)^-1 see data sheet for this value
CONSTANT SS_HOLD_CYCLES : INTEGER := BASE_CLK/SS_HOLD_FREQUENCY + 2; -- add 2 to be sure and have a minimum number of cycles
CONSTANT TRANSFER_WIDTH : INTEGER := 16;
CONSTANT CHANNEL_COUNT_WIDTH : INTEGER := integer(ceil(log2(real(NUMBER_OF_CHANNELS))));
TYPE t_states IS (idle,wait_for_data,store_data,wait_for_next_transfer);
TYPE t_internal_register IS RECORD
state :t_states;
tx_data : STD_LOGIC_VECTOR(TRANSFER_WIDTH -1 DOWNTO 0);
tx_start : STD_LOGIC;
channel_count : UNSIGNED(CHANNEL_COUNT_WIDTH-1 DOWNTO 0);
values : t_value_regs;
cycle_count : UNSIGNED(6 DOWNTO 0);
END RECORD;
SIGNAL slv_rx_data : STD_LOGIC_VECTOR(TRANSFER_WIDTH -1 DOWNTO 0);
SIGNAL sl_rx_done : STD_LOGIC;
SIGNAL ri, ri_next : t_internal_register;
BEGIN
my_spi_master : spi_master
GENERIC MAP(
BASE_CLK => BASE_CLK,
SCLK_FREQUENCY => SCLK_FREQUENCY,
CS_SETUP_CYLES => SS_HOLD_CYCLES,
TRANSFER_WIDTH => 16, -- 16 bit per transfer see data sheet
NR_OF_SS => 1, -- only one ss is needed
CPOL => '1', -- sckl inactive high see data sheet
CPHA => '1', -- data is captured on the leading edge see data sheet
MSBFIRST => '1', -- MSB first
SSPOL => '0' -- zero active see data sheet
)
PORT MAP(
isl_clk => isl_clk,
isl_reset_n => isl_reset_n,
islv_tx_data => ri.tx_data,
isl_tx_start => ri.tx_start,
oslv_rx_data => slv_rx_data,
osl_rx_done => sl_rx_done,
islv_ss_activ(0) => '1',
osl_sclk => osl_sclk,
oslv_ss(0) => osl_ss,
osl_mosi => osl_mosi,
isl_miso => isl_miso
);
--------------------------------------------
-- combinatorial process
--------------------------------------------
comb_process: PROCESS(ri, isl_reset_n,sl_rx_done,slv_rx_data)
VARIABLE vi: t_internal_register;
BEGIN
-- keep variables stable
vi:=ri;
--standard values
vi.tx_start := '0';
CASE vi.state IS
WHEN idle =>
vi.tx_data := (OTHERS => '0');
vi.tx_data(TRANSFER_WIDTH -3 DOWNTO TRANSFER_WIDTH-5) := STD_LOGIC_VECTOR(vi.channel_count);
vi.tx_start := '1';
vi.state := wait_for_data;
WHEN wait_for_data =>
IF sl_rx_done = '1' THEN
vi.state := store_data;
END IF;
WHEN store_data =>
IF vi.channel_count = to_unsigned(0,CHANNEL_COUNT_WIDTH) THEN
vi.values(NUMBER_OF_CHANNELS-1) := slv_rx_data(RESOLUTION-1 DOWNTO 0);
ELSE
vi.values(to_integer(vi.channel_count)-1) := slv_rx_data(RESOLUTION-1 DOWNTO 0);
END IF;
IF vi.channel_count >= NUMBER_OF_CHANNELS-1 THEN
vi.channel_count := to_unsigned(0,CHANNEL_COUNT_WIDTH);
ELSE
vi.channel_count := vi.channel_count + 1;
END IF;
vi.state := wait_for_next_transfer;
WHEN wait_for_next_transfer =>
IF vi.cycle_count = 50 THEN
vi.cycle_count := to_unsigned(0,7);
vi.state := idle;
ELSE
vi.cycle_count := vi.cycle_count + 1;
END IF;
WHEN OTHERS =>
vi.state := idle;
END CASE;
--reset
IF isl_reset_n = '0' THEN
vi.state := idle;
vi.tx_data := (OTHERS => '0');
vi.tx_start := '0';
vi.channel_count := to_unsigned(0,CHANNEL_COUNT_WIDTH);
FOR i IN 0 TO NUMBER_OF_CHANNELS-1 LOOP
vi.values(i) := (OTHERS => '0');
END LOOP;
vi.cycle_count := (OTHERS => '0');
END IF;
-- setting outputs
ri_next <= vi;
END PROCESS comb_process;
--------------------------------------------
-- registered process
--------------------------------------------
reg_process: PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_process;
ot_values <= ri.values;
END ARCHITECTURE rtl;
| apache-2.0 |
flink-project/flinkvhdl | avalonComponents/busInterfaces/mpc5200_local_plus_bus_to_avalon/src/mpc5200b_lpb_to_avalon.vhd | 1 | 7780 | LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--############################################################################
--
-- Änderung : Tristate Buffer Generation auf dieser Ebene, nicht im Top Design
--
--############################################################################
ENTITY lpb_mpc5200b_to_avalon IS
GENERIC
(
LPBADDRWIDTH : INTEGER := 32;
LPBDATAWIDTH : INTEGER := 32;
LPBTSIZEWIDTH : INTEGER := 3;
LPBCSWIDTH : INTEGER := 2;
LPBBANKWIDTH : INTEGER := 2
);
PORT
(
-- Avalon Fundametal Signals
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
waitrequest : IN STD_LOGIC;
-- Avalon Address/Data Interface
address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
read : OUT STD_LOGIC;
readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
write : OUT STD_LOGIC;
writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
-- Avalon SIGNAL (OTHERS)
byteenable : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
-- MPC5200 address/data interface
lpb_ad : INOUT STD_LOGIC_VECTOR ((LPBDATAWIDTH-1) DOWNTO 0);
-- LocalPlus Bus Chip Selects AND other signals
lpb_cs_n : IN STD_LOGIC_VECTOR ((LPBCSWIDTH-1) DOWNTO 0);
lpb_oe_n : IN STD_LOGIC;
lpb_ack_n : OUT STD_LOGIC;
lpb_ale_n : IN STD_LOGIC;
lpb_rdwr_n : IN STD_LOGIC;
lpb_ts_n : IN STD_LOGIC
);
END lpb_mpc5200b_to_avalon;
---------------------------------------------------------
-- reset SIGNAL einbauen
---------------------------------------------------------
ARCHITECTURE avalon_master OF lpb_mpc5200b_to_avalon IS
SIGNAL lpb_adr_q : STD_LOGIC_VECTOR((LPBADDRWIDTH-1) DOWNTO 0);
SIGNAL lpb_data_q : STD_LOGIC_VECTOR((LPBDATAWIDTH-1) DOWNTO 0);
SIGNAL lpb_tsize_q : STD_LOGIC_VECTOR ((LPBTSIZEWIDTH-1) DOWNTO 0);
SIGNAL lpb_data_en : STD_LOGIC;
SIGNAL lpb_start : STD_LOGIC;
SIGNAL lpb_rd : STD_LOGIC;
SIGNAL lpb_wr : STD_LOGIC;
SIGNAL lpb_ack_i : STD_LOGIC;
SIGNAL lpb_start_en : STD_LOGIC;
SIGNAL lpb_ad_o : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL lpb_ad_en : STD_LOGIC;
type state IS (init, act, rst);
SIGNAL avalonstate : state;
BEGIN
--activation of FPGA with only one chip select SIGNAL
lpb_rd <= (NOT lpb_cs_n(0) AND NOT lpb_oe_n);
lpb_wr <= (NOT lpb_cs_n(0) AND NOT lpb_rdwr_n);
-- external ack SIGNAL gets internal value
lpb_ack_n <= NOT lpb_ack_i;
-- ############################# MPC interface functions ##############################
-- tristate buffer generation
lpb_data_switching : PROCESS(lpb_ad_o, lpb_ad_en, reset_n)
BEGIN
IF reset_n = '0' THEN
lpb_ad <= (OTHERS => 'Z');
ELSIF lpb_ad_en = '1' THEN
lpb_ad <= lpb_ad_o;
ELSE
lpb_ad <= (OTHERS => 'Z');
END IF;
END PROCESS;
-- mpc_address_latching : necessary because of multiplexed bus system
-- latching of addresses at falling edge of clk
lpb_address_latching : PROCESS (clk, reset_n)
BEGIN
IF reset_n = '0' THEN
lpb_adr_q <= (OTHERS => '0');
lpb_tsize_q <= (OTHERS => '0');
ELSIF rising_edge(clk) THEN
IF lpb_ale_n = '0' THEN
lpb_adr_q <= lpb_ad((LPBADDRWIDTH-1) DOWNTO 0);
lpb_tsize_q <= lpb_ad((LPBDATAWIDTH-2) DOWNTO (LPBDATAWIDTH-4));
END IF;
END IF;
END PROCESS lpb_address_latching;
-- lpb_write_data_latching
-- latching of data of the lpb bus at write cycle
lpb_write_data_latching : PROCESS (clk, reset_n)
BEGIN
IF reset_n = '0' THEN
lpb_data_q <= (OTHERS => '0');
lpb_data_en <= '0';
lpb_start <= '0';
ELSE
IF rising_edge (clk) THEN
IF lpb_ts_n = '0' AND lpb_start = '0' THEN
--lpb_start <= '1'; -- for 66MHz we can start here
lpb_start_en <= '1';
ELSE
--lpb_start <= '0';
lpb_start_en <= '0';
END IF;
-- needable for 33MHz support, for 66MHz we can start erlier
IF lpb_start_en = '1' THEN
lpb_start <= '1';
ELSE
lpb_start <= '0';
END IF;
IF lpb_ts_n = '0' AND lpb_rdwr_n = '0' THEN
lpb_data_en <= '1'; -- wait 1 clock cycle for data ready
END IF;
IF lpb_data_en = '1' THEN
lpb_data_q <= lpb_ad;
lpb_data_en <= '0';
END IF;
END IF;
END IF;
END PROCESS lpb_write_data_latching;
-- lpb_read_data_switching
-- reading of data of avalon register AND applying at the LPB bus
lpb_read_data_switching : PROCESS (clk, reset_n)
BEGIN
IF reset_n = '0' THEN
lpb_ad_o <= (OTHERS => '0');
lpb_ad_en <= '0';
ELSIF rising_edge(clk) THEN
IF lpb_rd = '1' AND lpb_ack_i = '0' THEN
CASE lpb_tsize_q IS
WHEN "001" => lpb_ad_o <= (readdata(7 DOWNTO 0) & readdata(15 DOWNTO 8) & readdata(23 DOWNTO 16) & readdata(31 DOWNTO 24));
WHEN "010" => lpb_ad_o <= (readdata(15 DOWNTO 0) & readdata(31 DOWNTO 16));
WHEN OTHERS => lpb_ad_o <= readdata;
END CASE;
lpb_ad_en <= '1';
ELSE
lpb_ad_en <= '0';
END IF;
END IF;
END PROCESS lpb_read_data_switching;
-- mpc_ack_generation : necessary to shorten the controller cycle of the mpc
-- genaration of ack SIGNAL at falling edge of local plus bus clock
lpb_ack_generation : PROCESS (clk, reset_n)
BEGIN
IF reset_n = '0' THEN
lpb_ack_i <= '0';
ELSIF rising_edge(clk) THEN
IF avalonstate = act THEN
lpb_ack_i <= (NOT waitrequest AND NOT lpb_ack_i);
ELSE
lpb_ack_i <= '0';
END IF;
END IF;
END PROCESS lpb_ack_generation;
-- ############################ wishbone read/write state machine ######################
-- state machine for reading/writing avalon bus
lpb_to_avalon : PROCESS (reset_n, clk)
BEGIN
IF reset_n = '0' THEN
avalonstate <= init;
ELSIF rising_edge(clk)THEN
CASE avalonstate IS
WHEN init => IF lpb_start = '1' THEN -- start avalon master statemachine
avalonstate <= act;
END IF;
WHEN act => IF waitrequest = '0' THEN -- wait for no waitrequest
avalonstate <= rst;
END IF;
WHEN rst => avalonstate <= init;
WHEN OTHERS => avalonstate <= init;
END CASE;
END IF;
END PROCESS lpb_to_avalon;
avalon_bus : PROCESS (reset_n, clk)
BEGIN
IF reset_n = '0' THEN
ELSIF rising_edge(clk) THEN
IF avalonstate = init AND lpb_start = '1' THEN
address <= lpb_adr_q;
write <= lpb_wr; -- avalon SIGNAL generation we
read <= lpb_rd;
CASE lpb_tsize_q IS -- swap bytes for little endian access
WHEN "100" => byteenable <= "1111";
writedata <= lpb_data_q;
WHEN "010" => CASE lpb_adr_q(1 DOWNTO 0) IS
WHEN "00" => byteenable <= "0011";
writedata(15 DOWNTO 0) <= lpb_data_q(31 DOWNTO 16);
WHEN "10" => byteenable <= "1100";
writedata <= lpb_data_q;
WHEN OTHERS => byteenable <= "1111";
writedata <= lpb_data_q;
END CASE;
WHEN "001" => CASE lpb_adr_q(1 DOWNTO 0) IS
WHEN "00" => byteenable <= "0001";
writedata(7 DOWNTO 0) <= lpb_data_q(31 DOWNTO 24);
WHEN "01" => byteenable <= "0010";
writedata(15 DOWNTO 8) <= lpb_data_q(31 DOWNTO 24);
WHEN "10" => byteenable <= "0100";
writedata(23 DOWNTO 16) <= lpb_data_q(31 DOWNTO 24);
WHEN "11" => byteenable <= "1000";
writedata <= lpb_data_q;
END CASE;
WHEN OTHERS =>byteenable <= "1111";
writedata <= lpb_data_q;
END CASE;
END IF;
IF avalonstate = act THEN
--readdata_q <= readdata;
IF waitrequest = '0' THEN
read <= '0';
write <= '0';
address <= (OTHERS => '0');
writedata <= (OTHERS => '0');
END IF;
END IF;
END IF;
END PROCESS avalon_bus;
END avalon_master; | apache-2.0 |
flink-project/flinkvhdl | avalonComponents/subDevices/mpu9250_interface/sim/mpu9250_interface_tb.vhd | 1 | 5929 | -------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
USE work.mpu9250_interface_pkg.ALL;
USE work.mpu9250_pkg.ALL;
ENTITY mpu9250_interface_tb IS
END ENTITY mpu9250_interface_tb;
ARCHITECTURE sim OF mpu9250_interface_tb IS
CONSTANT main_period : TIME := 4 ns; -- 250MHz
CONSTANT unique_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := x"00AFFE00";
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '1';
SIGNAL slv_avs_address : STD_LOGIC_VECTOR (c_mpu9250_interface_address_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL sl_avs_read : STD_LOGIC:= '0';
SIGNAL sl_avs_write : STD_LOGIC:= '0';
SIGNAL slv_avs_write_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_avs_read_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_avs_byteenable : STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0):= (OTHERS =>'1');
SIGNAL sl_sclk : STD_LOGIC:= '0';
SIGNAL slv_cs_n : STD_LOGIC:= '0';
SIGNAL isl_sdo : STD_LOGIC:= '1';
SIGNAL osl_sdi : STD_LOGIC:= '0';
BEGIN
--create component
my_unit_under_test : mpu9250_interface
GENERIC MAP(
BASE_CLK => 33000000,
SCLK_FREQUENCY => 100000,
UNIQUE_ID => unique_id
)
PORT MAP(
isl_clk => sl_clk,
isl_reset_n => sl_reset_n,
islv_avs_address => slv_avs_address,
isl_avs_read => sl_avs_read,
isl_avs_write => sl_avs_write,
islv_avs_write_data => slv_avs_write_data,
islv_avs_byteenable => slv_avs_byteenable,
oslv_avs_read_data => slv_avs_read_data,
osl_sclk => sl_sclk,
oslv_cs_n => slv_cs_n,
isl_sdo => isl_sdo,
osl_sdi => osl_sdi
);
sl_clk <= NOT sl_clk after main_period/2;
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '0';
WAIT FOR 100*main_period;
sl_reset_n <= '1';
WAIT FOR main_period/2;
--test id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_typdef_address,c_mpu9250_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = c_mpu9250_interface_version
REPORT "Interface Version Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_interface_version_length+c_fLink_subtype_length-1 DOWNTO c_fLink_interface_version_length) = c_mpu9250_subtype_id
REPORT "Subtype ID Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_avs_data_width-1 DOWNTO c_fLink_interface_version_length+c_fLink_interface_version_length) = STD_LOGIC_VECTOR(to_unsigned(c_fLink_sensor_id,c_fLink_id_length))
REPORT "Type ID Missmatch" SEVERITY FAILURE;
--test mem size register register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_mem_size_address,c_mpu9250_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT to_integer(UNSIGNED(slv_avs_read_data)) = 4*INTEGER(2**c_mpu9250_interface_address_width)
REPORT "Memory Size Error: "&INTEGER'IMAGE(4*INTEGER(2**1))&"/"&INTEGER'IMAGE(to_integer(UNSIGNED(slv_avs_read_data))) SEVERITY FAILURE;
--test uniqu id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_unique_id_address,c_mpu9250_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data = unique_id
REPORT "Unique Id Error" SEVERITY FAILURE;
--test number of channels register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_channels_address,c_mpu9250_interface_address_width));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = STD_LOGIC_VECTOR(to_unsigned(1,c_fLink_interface_version_length))
REPORT "Number of Channels Error" SEVERITY FAILURE;
WAIT FOR 100000*main_period;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
END ARCHITECTURE sim; | apache-2.0 |
OgacNS94/C-3PU | vhdl_files/Mux_2_to_1_4bit.vhd | 1 | 1138 | --
-- Copyright 2016 Ognjen Glamocanin
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_2_to_1_4bit is
port(
x1: in std_logic_vector (3 downto 0);
x2: in std_logic_vector (3 downto 0);
sel: in std_logic;
y: out std_logic_vector (3 downto 0)
);
end entity mux_2_to_1_4bit;
architecture behavioral of mux_2_to_1_4bit is
begin
mux: process (x1, x2, sel) is
begin
case sel is
when '0' => y <= x1;
when others => y <= x2;
end case;
end process;
end architecture behavioral; | apache-2.0 |
SKravitsky/ECEC412 | Mux32.vhd | 1 | 284 | library ieee;
use ieee.std_logic_1164.all;
entity Mux32 is
port(
x, y: in std_logic_vector (31 downto 0);
sel: in std_logic;
z: out std_logic_vector(31 downto 0)
);
end Mux32;
architecture Structural of Mux32 is
begin
z <= y when sel = '1' else x;
end Structural;
| apache-2.0 |
SKravitsky/ECEC412 | IR.vhd | 1 | 463 | library ieee;
use ieee.std_logic_1164.ALL;
entity IR is
port (
x: in std_logic_vector(31 downto 0);
clk, IRWrite: in std_logic;
y: out std_logic_vector(31 downto 0)
);
end IR;
architecture Structural of IR is
signal temp: std_logic_vector(31 downto 0) := X"00000000";
begin
y <= temp;
process(clk)
begin
if rising_edge(clk) then
if IRWRite = '1' then
temp <= x;
end if;
end if;
end process;
end Structural;
| apache-2.0 |
SKravitsky/ECEC412 | IFIDRegister.vhd | 1 | 593 | library ieee;
use ieee.std_logic_1164.all;
entity IFIDRegister is
port(
clk: in std_logic;
AddressIn, InstructionIn: in std_logic_vector(31 downto 0);
AddressOut, InstructionOut: out std_logic_vector(31 downto 0)
);
end IFIDRegister;
architecture Structural of IFIDRegister is
signal Address, Instruction: std_logic_vector(31 downto 0) := X"00000000";
begin
AddressOut <= Address;
InstructionOut <= Instruction;
process(clk)
begin
if rising_edge(clk) then
Address <= AddressIn;
Instruction <= InstructionIn;
end if;
end process;
end Structural;
| apache-2.0 |
SKravitsky/ECEC412 | PC.vhd | 1 | 482 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PC is
port(
clk: in std_logic;
AddressIn: in std_logic_vector(31 downto 0);
AddressOut: out std_logic_vector(31 downto 0)
);
end PC;
architecture Behavioral of PC is
begin
process(clk)
variable temp: std_logic_vector(31 downto 0) := X"00000000";
begin
AddressOut <= temp;
if falling_edge(clk) then
temp := AddressIn;
else
end if;
end process;
end Behavioral;
| apache-2.0 |
jcowgill/cs-dacs-robot | Common/DataChangeDetectorTest.vhd | 1 | 1530 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY DataChangeDetectorTest IS
END DataChangeDetectorTest;
ARCHITECTURE behavioral OF DataChangeDetectorTest IS
COMPONENT DataChangeDetector
PORT ( SEND : OUT STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR (5 DOWNTO 0));
END COMPONENT;
SIGNAL SEND : STD_LOGIC;
SIGNAL CLR : STD_LOGIC;
SIGNAL CLK : STD_LOGIC;
SIGNAL DATA : STD_LOGIC_VECTOR (5 DOWNTO 0);
BEGIN
UUT: DataChangeDetector PORT MAP(
SEND => SEND,
CLR => CLR,
CLK => CLK,
DATA => DATA
);
clk_process : PROCESS
BEGIN
-- Clock signal (4 MHz)
CLK <= '0';
WAIT FOR 125ns;
CLK <= '1';
WAIT FOR 125ns;
END PROCESS;
tb_process : PROCESS
BEGIN
-- Reset
CLR <= '1';
WAIT FOR 1000ns;
CLR <= '0';
-- Send some data down
DATA <= "000000"; WAIT FOR 1000ns;
DATA <= "000001"; WAIT FOR 1000ns;
DATA <= "000010"; WAIT FOR 1000ns;
DATA <= "000011"; WAIT FOR 1000ns;
DATA <= "000100"; WAIT FOR 1000ns;
DATA <= "000101"; WAIT FOR 1000ns;
DATA <= "000110"; WAIT FOR 1000ns;
DATA <= "000111"; WAIT FOR 1000ns;
DATA <= "000000"; WAIT FOR 500ns;
DATA <= "000001"; WAIT FOR 1000ns;
DATA <= "000000"; WAIT FOR 1000ns;
WAIT;
END PROCESS;
END;
| apache-2.0 |
jcowgill/cs-dacs-robot | Common/AsyncRxTest.vhd | 1 | 1367 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY AsyncRxTest IS
END AsyncRxTest;
ARCHITECTURE behavioral OF AsyncRxTest IS
COMPONENT AsyncRx
PORT ( Q : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
UPDATE : OUT STD_LOGIC;
RX : IN STD_LOGIC;
CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC);
END COMPONENT;
SIGNAL Q : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL UPDATE : STD_LOGIC;
SIGNAL RX : STD_LOGIC;
SIGNAL CLK : STD_LOGIC;
SIGNAL CLR : STD_LOGIC;
BEGIN
UUT: AsyncRx PORT MAP(
Q => Q,
UPDATE => UPDATE,
RX => RX,
CLK => CLK,
CLR => CLR
);
clk_process : PROCESS
BEGIN
-- Clock signal (4 MHz)
CLK <= '0';
WAIT FOR 125ns;
CLK <= '1';
WAIT FOR 125ns;
END PROCESS;
tb_process : PROCESS
BEGIN
-- Reset
CLR <= '1';
WAIT FOR 1000ns;
CLR <= '0';
-- Send some crap over
WAIT FOR 2000ns;
RX <= '1'; WAIT FOR 1us;
RX <= '0'; WAIT FOR 4us;
RX <= '1'; WAIT FOR 4us;
RX <= '0'; WAIT FOR 4us;
RX <= '0'; WAIT FOR 4us;
RX <= '0'; WAIT FOR 4us;
RX <= '1'; WAIT FOR 4us;
RX <= '1'; WAIT;
END PROCESS;
END;
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/zero_detect.vhd | 1 | 13395 | `protect begin_protected
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`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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CoZ4v86pTPk9jHDJGDs=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8176)
`protect data_block
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| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_lite_ipif_v2_0/82c7a66d/hdl/src/vhdl/axi_lite_ipif.vhd | 7 | 14662 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v2.0
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.clog2;
use proc_common_v4_0.proc_common_pkg.max2;
use proc_common_v4_0.family_support.all;
use proc_common_v4_0.ipif_pkg.all;
library axi_lite_ipif_v2_0;
use axi_lite_ipif_v2_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v2_0.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/blk_mem_gen_v8_2/f2a44852/hdl/blk_mem_gen_v8_2_pkg.vhd | 11 | 123927 | `protect begin_protected
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`protect end_protected
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/updn_cntr.vhd | 5 | 10193 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5808)
`protect data_block
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`protect end_protected
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/result_mux_bit.vhd | 1 | 13849 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect key_block
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| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/compare_vectors_f.vhd | 15 | 10255 | -------------------------------------------------------------------------------
-- $Id: compare_vectors_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- compare_vectors_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: compare_vectors_f.vhd
--
-- Description: Compare vectors Vec1 and Vec2 for equality: Eq <= Vec1 = Vec2
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- compare_vectors_f.vhd
-- -- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- FLO 04/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- number of bits to compare
-- C_FAMILY -- target FPGA family
--
-- Definition of Ports:
-- Vec1 -- first standard_logic_vector input
-- Vec2 -- second standard_logic_vector input
-- Eq -- Vec1 = Vec2-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
entity compare_vectors_f is
generic (
C_WIDTH : natural;
C_FAMILY : string := "nofamily"
);
port (
Vec1 : in std_logic_vector(0 to C_WIDTH-1);
Vec2 : in std_logic_vector(0 to C_WIDTH-1);
Eq : out std_logic
);
end entity compare_vectors_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of compare_vectors_f is
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS<2 -- Native LUT not big enough.
or 2*C_WIDTH <= NLS; -- Just one LUT
-- needed.
function lut_val(V1, V2 : std_logic_vector) return std_logic is
variable r : std_logic := '1';
begin
for i in V1'range loop
r := r and bo2sl(V1(i) = V2(i));
end loop;
return r; -- Return V1=V2
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin --architecture
STRUCTURAL_A_GEN: if USE_INFERRED = false generate
constant BPL : positive := NLS / 2; -- Bits per LUT is the native lut
-- size divided by two.
constant NUMLUTS : positive := (C_WIDTH+(BPL-1))/BPL; -- NUMLUTS will be
-- greater than or equal to 2 because of how USE_INFERRED
-- is declared.
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout: std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '1';
PER_LUT_GEN: for i in NUMLUTS - 1 downto 0 generate
constant NI : natural := NUMLUTS-1-i; -- Used to place high-order,
-- low-index bits at the top of carry chain.
constant BTL : positive := min(BPL, C_WIDTH-NI*BPL);
-- Number of comparison bit positions at this LUT. (For the LUT at
-- the bottom of the carry chain this may be less than BPL.)
begin
lutout(i) <= lut_val(V1 => Vec1(NI*BPL to NI*BPL+BTL-1),
V2 => Vec2(NI*BPL to NI*BPL+BTL-1)
); -- Corres. sections of Vec1 and Vec2 are equal
--
MUXCY_I : component MUXCY
port map (CI=>cyout(i),
DI=> '0',
S=>lutout(i),
O=>cyout(i+1));
end generate;
Eq <= cyout(NUMLUTS);
end generate;
INFERRED_GEN: if USE_INFERRED = true generate
Eq <= '1' when Vec1 = Vec2 else '0';
end generate;
end imp;
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/carry_and.vhd | 1 | 9849 | `protect begin_protected
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5552)
`protect data_block
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`protect end_protected
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/pc_bit.vhd | 1 | 15425 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9680)
`protect data_block
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`protect end_protected
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/common/wr_pf_as.vhd | 5 | 27402 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
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`protect end_protected
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/operand_select_bit.vhd | 1 | 27118 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18336)
`protect data_block
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`protect end_protected
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/gen_srlfifo.vhd | 1 | 14303 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8848)
`protect data_block
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| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/builtin/bin_cntr.vhd | 5 | 8597 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect end_protected
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/dc_ss_fwft.vhd | 5 | 9156 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5040)
`protect data_block
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`protect end_protected
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/shift_logic.vhd | 1 | 36111 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 24992)
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`protect end_protected
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/ram_module.vhd | 1 | 76228 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 54688)
`protect data_block
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| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/816dc01c/hdl/vhdl/checkbit_handler.vhd | 1 | 22877 | -------------------------------------------------------------------------------
-- $Id: checkbit_handler.vhd,v 1.1.2.2 2010/09/06 09:01:24 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
-------------------------------------------------------------------------------
-- Filename: gen_checkbits.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:
-- gen_checkbits.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.2.2 $
-- Date: $Date: 2010/09/06 09:01:24 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity checkbit_handler is
generic (
C_ENCODE : boolean := true;
C_USE_LUT6 : boolean := true);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic
);
end entity checkbit_handler;
library unisim;
use unisim.vcomponents.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
architecture IMP of checkbit_handler is
component XOR18 is
generic (
C_USE_LUT6 : boolean);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end component XOR18;
component Parity is
generic (
C_USE_LUT6 : boolean;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic);
end component Parity;
component ParityEnable
generic (
C_USE_LUT6 : boolean;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Enable : in std_logic;
Res : out std_logic);
end component ParityEnable;
signal data_chk0 : std_logic_vector(0 to 17);
signal data_chk1 : std_logic_vector(0 to 17);
signal data_chk2 : std_logic_vector(0 to 17);
signal data_chk3 : std_logic_vector(0 to 14);
signal data_chk4 : std_logic_vector(0 to 14);
signal data_chk5 : std_logic_vector(0 to 5);
begin -- architecture IMP
data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30);
data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) &
DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) &
DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31);
data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31);
data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25);
data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31);
-- Encode bits for writing data
Encode_Bits : if (C_ENCODE) generate
signal data_chk3_i : std_logic_vector(0 to 17);
signal data_chk4_i : std_logic_vector(0 to 17);
signal data_chk6 : std_logic_vector(0 to 17);
begin
------------------------------------------------------------------------------------------------
-- Checkbit 0 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I0 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk0, -- [in std_logic_vector(0 to 17)]
res => CheckOut(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 1 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I1 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk1, -- [in std_logic_vector(0 to 17)]
res => CheckOut(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 2 built up using XOR18
------------------------------------------------------------------------------------------------
XOR18_I2 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk2, -- [in std_logic_vector(0 to 17)]
res => CheckOut(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 3 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & "000";
XOR18_I3 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk3_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 4 built up using XOR18
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & "000";
XOR18_I4 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk4_i, -- [in std_logic_vector(0 to 17)]
res => CheckOut(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 5 built up from 1 LUT6
------------------------------------------------------------------------------------------------
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => CheckOut(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) &
DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) &
DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29);
XOR18_I6 : XOR18
generic map (
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
InA => data_chk6, -- [in std_logic_vector(0 to 17)]
res => CheckOut(6)); -- [out std_logic]
-- Unused
Syndrome <= (others => '0');
UE <= '0';
CE <= '0';
end generate Encode_Bits;
--------------------------------------------------------------------------------------------------
-- Decode bits to get syndrome and UE/CE signals
--------------------------------------------------------------------------------------------------
Decode_Bits : if (not C_ENCODE) generate
signal syndrome_i : std_logic_vector(0 to 6);
signal chk0_1 : std_logic_vector(0 to 3);
signal chk1_1 : std_logic_vector(0 to 3);
signal chk2_1 : std_logic_vector(0 to 3);
signal data_chk3_i : std_logic_vector(0 to 15);
signal chk3_1 : std_logic_vector(0 to 1);
signal data_chk4_i : std_logic_vector(0 to 15);
signal chk4_1 : std_logic_vector(0 to 1);
signal data_chk5_i : std_logic_vector(0 to 6);
signal data_chk6 : std_logic_vector(0 to 38);
signal chk6_1 : std_logic_vector(0 to 5);
signal syndrome_3_to_5 : std_logic_vector(3 to 5);
signal syndrome_3_to_5_multi : std_logic;
signal syndrome_3_to_5_zero : std_logic;
signal ue_i_0 : std_logic;
signal ue_i_1 : std_logic;
begin
------------------------------------------------------------------------------------------------
-- Syndrome bit 0 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk0_1(3) <= CheckIn(0);
Parity_chk0_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(0)); -- [out std_logic]
Parity_chk0_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(1)); -- [out std_logic]
Parity_chk0_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(2)); -- [out std_logic]
Parity_chk0_4 : ParityEnable
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 1 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk1_1(3) <= CheckIn(1);
Parity_chk1_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(0)); -- [out std_logic]
Parity_chk1_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(1)); -- [out std_logic]
Parity_chk1_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(2)); -- [out std_logic]
Parity_chk1_4 : ParityEnable
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 2 built up from 3 LUT6 and 1 LUT4
------------------------------------------------------------------------------------------------
chk2_1(3) <= CheckIn(2);
Parity_chk2_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(0)); -- [out std_logic]
Parity_chk2_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(1)); -- [out std_logic]
Parity_chk2_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(2)); -- [out std_logic]
Parity_chk2_4 : ParityEnable
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 3 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & CheckIn(3);
Parity_chk3_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(0)); -- [out std_logic]
Parity_chk3_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(1)); -- [out std_logic]
Parity_chk3_3 : ParityEnable
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Enable => Enable_ECC, -- [in std_logic]
Res => syndrome_i(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 4 built up from 2 LUT8 and 1 LUT2
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & CheckIn(4);
Parity_chk4_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(0)); -- [out std_logic]
Parity_chk4_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(1)); -- [out std_logic]
Parity_chk4_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => chk4_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 5 built up from 1 LUT7
------------------------------------------------------------------------------------------------
data_chk5_i <= data_chk5 & CheckIn(5);
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk5_i, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 6 built up from 3 LUT7 and 4 LUT6
------------------------------------------------------------------------------------------------
data_chk6 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) &
DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) &
DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) &
DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) &
DataIn(29) & DataIn(30) & DataIn(31) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) &
CheckIn(1) & CheckIn(0) & CheckIn(6);
Parity_chk6_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(0)); -- [out std_logic]
Parity_chk6_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(1)); -- [out std_logic]
Parity_chk6_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(2)); -- [out std_logic]
Parity_chk6_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(3)); -- [out std_logic]
Parity_chk6_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(4)); -- [out std_logic]
Parity_chk6_6 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk6(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk6_1(5)); -- [out std_logic]
Parity_chk6_7 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => chk6_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(6)); -- [out std_logic]
Syndrome <= syndrome_i;
syndrome_3_to_5 <= (chk3_1(0) xor chk3_1(1)) & (chk4_1(0) xor chk4_1(1)) & syndrome_i(5);
syndrome_3_to_5_zero <= '1' when syndrome_3_to_5 = "000" else '0';
syndrome_3_to_5_multi <= '1' when (syndrome_3_to_5 = "111" or
syndrome_3_to_5 = "011" or
syndrome_3_to_5 = "101") else
'0';
CE <= '0' when (Enable_ECC = '0') else
(syndrome_i(6) or CE_Q) when (syndrome_3_to_5_multi = '0') else
CE_Q;
ue_i_0 <= '0' when (Enable_ECC = '0') else
'1' when (syndrome_3_to_5_zero = '0') or (syndrome_i(0 to 2) /= "000") else
UE_Q;
ue_i_1 <= '0' when (Enable_ECC = '0') else
(syndrome_3_to_5_multi or UE_Q);
Use_LUT6: if (C_USE_LUT6) generate
UE_MUXF7 : MUXF7
port map (
I0 => ue_i_0,
I1 => ue_i_1,
S => syndrome_i(6),
O => UE);
end generate Use_LUT6;
Use_RTL: if (not C_USE_LUT6) generate
UE <= ue_i_1 when syndrome_i(6) = '1' else ue_i_0;
end generate Use_RTL;
-- Unused
CheckOut <= (others => '0');
end generate Decode_Bits;
end architecture IMP;
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/common/synchronizer_ff.vhd | 5 | 8637 | `protect begin_protected
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`protect end_protected
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/wr_dc_as.vhd | 5 | 10866 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6304)
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| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/blk_mem_gen_wrapper.vhd | 1 | 33899 | -------------------------------------------------------------------------------
-- $Id: blk_mem_gen_wrapper.vhd,v 1.1.2.69 2010/12/17 19:23:25 dougt Exp $
-------------------------------------------------------------------------------
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009. 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: blk_mem_gen_wrapper.vhd
-- Version: v1.00a
-- Description:
-- This wrapper file performs the direct call to Block Memory Generator
-- during design implementation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- blk_mem_gen_wrapper.vhd
-- |
-- |-- blk_mem_gen_v2_7
-- |
-- |-- blk_mem_gen_v6_2
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: MW
-- Revision: $Revision: 1.1.2.69 $
-- Date: $7/11/2008$
--
-- History:
-- MW 7/11/2008 Initial Version
-- MSH 2/26/2009 Add new blk_mem_gen version
--
-- DET 4/8/2009 EDK 11.2
-- ~~~~~~
-- - Added blk_mem_gen_v3_2 instance callout
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the the Blk Mem Gen version from blk_mem_gen_v3_2
-- to blk_mem_gen_v3_3 (for the S6/V6 IfGen case)
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the the Blk Mem Gen version from blk_mem_gen_v3_3
-- to blk_mem_gen_v4_1 (for the S6/V6 IfGen case)
-- ^^^^^^
--
-- DET 3/17/2010 Initial
-- ~~~~~~
-- -- Per CR554253
-- - Incorporated changes to comment out FLOP_DELAY parameter from the
-- blk_mem_gen_v4_1 instance. This parameter is on the XilinxCoreLib
-- model for blk_mem_gen_v4_1 but is declared as a TIME type for the
-- vhdl version and an integer for the verilog.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added constants FAM_IS_V6_OR_S6 and FAM_IS_NOT_V6_OR_S6.
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/27/2010 EDK 12.4
-- ~~~~~~
-- -- Per CR573867
-- - Added the the Blk Mem Gen version blk_mem_gen_v4_3 for the S6/V6
-- and later build case.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated to blk_mem_gen V5.2.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated to blk_mem_gen V6.1
-- ^^^^^^
--
-- DET 12/17/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR587494
-- - Regressed back to blk_mem_gen V5.2
-- ^^^^^^
--
-- DET 3/2/2011 EDk 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use blk_mem_gen_v6_2 for s6, v6, and later.
-- ^^^^^^
--
-- DET 3/3/2011 EDK 13.2
-- ~~~~~~
-- - Removed C_ELABORATION_DIR parameter from the blk_mem_gen_v6_2
-- instance.
-- ^^^^^^
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
--Library XilinxCoreLib;
-- synopsys translate_on
library blk_mem_gen_v8_2;
library proc_common_v4_0;
use blk_mem_gen_v8_2.all;
--use proc_common_v4_0.coregen_comp_defs.all;
use proc_common_v4_0.family_support.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity blk_mem_gen_wrapper is
generic
(
-- Device Family
c_family : string := "virtex5";
-- "Virtex2"
-- "Virtex4"
-- "Virtex5"
c_xdevicefamily : string := "virtex5";
-- Finest Resolution Device Family
-- "Virtex2"
-- "Virtex2-Pro"
-- "Virtex4"
-- "Virtex5"
-- "Spartan-3A"
-- "Spartan-3A DSP"
c_elaboration_dir : string := "";
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity blk_mem_gen_wrapper;
architecture implementation of blk_mem_gen_wrapper is
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_AWREADY : STD_LOGIC;
signal S_AXI_WREADY : STD_LOGIC;
signal S_AXI_BID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_BVALID : STD_LOGIC;
signal S_AXI_ARREADY : STD_LOGIC;
signal S_AXI_RID : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal S_AXI_RDATA : STD_LOGIC_VECTOR(c_write_width_b-1 DOWNTO 0);
signal S_AXI_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal S_AXI_RLAST : STD_LOGIC;
signal S_AXI_RVALID : STD_LOGIC;
signal S_AXI_SBITERR : STD_LOGIC;
signal S_AXI_DBITERR : STD_LOGIC;
signal S_AXI_RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal S_AXI_WSTRB : STD_LOGIC_VECTOR(c_wea_width-1 downto 0);
signal S_AXI_WDATA : STD_LOGIC_VECTOR(c_write_width_a-1 downto 0);
begin
S_AXI_WSTRB <= (others => '0');
S_AXI_WDATA <= (others => '0');
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising clock edge to issue assertion
Wait until clka = '1';
wait until clka = '0';
Wait until clka = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait; -- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low
douta <= (others => '0'); -- : out std_logic_vector(c_read_width_a-1 downto 0);
doutb <= (others => '0'); -- : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr <= '0' ; -- : out std_logic;
sbiterr <= '0' ; -- : out std_logic
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the Block Memeory using blk_mem_gen 5.2.
-- This is for new cores designed and tested with FPGA
-- Families of Virtex-6, Spartan-6 and later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen Block Memory Generator Call module
-- for new IP BRAM implementations.
--
-------------------------------------------------------------------------------
I_TRUE_DUAL_PORT_BLK_MEM_GEN : entity blk_mem_gen_v8_2.blk_mem_gen_v8_2
generic map
(
--C_CORENAME => c_corename ,
-- Device Family
C_FAMILY => FAMILY_TO_USE ,
C_XDEVICEFAMILY => c_xdevicefamily ,
C_ELABORATION_DIR => c_elaboration_dir ,
------------------
C_INTERFACE_TYPE => 0 ,
C_USE_BRAM_BLOCK => 0 ,
C_AXI_TYPE => 0 ,
C_AXI_SLAVE_TYPE => 0 ,
C_HAS_AXI_ID => 0 ,
C_AXI_ID_WIDTH => 4 ,
------------------
-- Memory Specific Configurations
C_MEM_TYPE => c_mem_type ,
C_BYTE_SIZE => c_byte_size ,
C_ALGORITHM => c_algorithm ,
C_PRIM_TYPE => c_prim_type ,
C_LOAD_INIT_FILE => c_load_init_file ,
C_INIT_FILE_NAME => c_init_file_name ,
C_INIT_FILE => "" ,
C_USE_DEFAULT_DATA => c_use_default_data ,
C_DEFAULT_DATA => c_default_data ,
-- Port A Specific Configurations
--C_RST_TYPE => "SYNC" , --Removed in version v8_2
C_HAS_RSTA => c_has_ssra ,
C_RST_PRIORITY_A => "CE" ,
C_RSTRAM_A => 0 ,
C_INITA_VAL => c_sinita_val ,
C_HAS_ENA => c_has_ena ,
C_HAS_REGCEA => c_has_regcea ,
C_USE_BYTE_WEA => c_use_byte_wea ,
C_WEA_WIDTH => c_wea_width ,
C_WRITE_MODE_A => c_write_mode_a ,
C_WRITE_WIDTH_A => c_write_width_a ,
C_READ_WIDTH_A => c_read_width_a ,
C_WRITE_DEPTH_A => c_write_depth_a ,
C_READ_DEPTH_A => c_read_depth_a ,
C_ADDRA_WIDTH => c_addra_width ,
-- Port B Specific Configurations
C_HAS_RSTB => c_has_ssrb ,
C_RST_PRIORITY_B => "CE" ,
C_RSTRAM_B => 0 ,
C_INITB_VAL => c_sinitb_val ,
C_HAS_ENB => c_has_enb ,
C_HAS_REGCEB => c_has_regceb ,
C_USE_BYTE_WEB => c_use_byte_web ,
C_WEB_WIDTH => c_web_width ,
C_WRITE_MODE_B => c_write_mode_b ,
C_WRITE_WIDTH_B => c_write_width_b ,
C_READ_WIDTH_B => c_read_width_b ,
C_WRITE_DEPTH_B => c_write_depth_b ,
C_READ_DEPTH_B => c_read_depth_b ,
C_ADDRB_WIDTH => c_addrb_width ,
C_HAS_MEM_OUTPUT_REGS_A => c_has_mem_output_regs_a ,
C_HAS_MEM_OUTPUT_REGS_B => c_has_mem_output_regs_b ,
C_HAS_MUX_OUTPUT_REGS_A => c_has_mux_output_regs_a ,
C_HAS_MUX_OUTPUT_REGS_B => c_has_mux_output_regs_b ,
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0 ,
-- Other Miscellaneous Configurations
C_MUX_PIPELINE_STAGES => c_mux_pipeline_stages ,
C_USE_SOFTECC => 0 ,
C_USE_ECC => c_use_ecc ,
C_EN_ECC_PIPE => 0 ,
-- Simulation Behavior Options
C_HAS_INJECTERR => 0 ,
C_SIM_COLLISION_CHECK => c_sim_collision_check ,
C_COMMON_CLK => c_common_clk ,
C_DISABLE_WARN_BHV_COLL => c_disable_warn_bhv_coll ,
C_EN_SLEEP_PIN => 0 ,
C_DISABLE_WARN_BHV_RANGE => c_disable_warn_bhv_range
)
port map
(
CLKA => clka ,
RSTA => ssra ,
ENA => ena ,
REGCEA => regcea ,
WEA => wea ,
ADDRA => addra ,
DINA => dina ,
DOUTA => douta ,
CLKB => clkb ,
RSTB => ssrb ,
ENB => enb ,
REGCEB => regceb ,
WEB => web ,
ADDRB => addrb ,
DINB => dinb ,
DOUTB => doutb ,
INJECTSBITERR => '0' , -- input
INJECTDBITERR => '0' , -- input
SBITERR => sbiterr ,
DBITERR => dbiterr ,
RDADDRECC => RDADDRECC , -- output
ECCPIPECE => '0' ,
SLEEP => '0' ,
-- AXI BMG Input and Output Port Declarations -- new for v6.2
-- new for v6.2
-- AXI Global Signals -- new for v6.2
S_AClk => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_ARESETN => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Write (write side) -- new for v6.2
S_AXI_AWID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_AWREADY => S_AXI_AWREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_WDATA => S_AXI_WDATA , -- : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WSTRB => S_AXI_WSTRB , -- : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WLAST => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WREADY => S_AXI_WREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BID => S_AXI_BID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_BRESP => S_AXI_BRESP , -- : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2
S_AXI_BVALID => S_AXI_BVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Read (Write side) -- new for v6.2
S_AXI_ARID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_ARREADY => S_AXI_ARREADY , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RID => S_AXI_RID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_RDATA => S_AXI_RDATA , -- : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2
S_AXI_RRESP => S_AXI_RRESP , -- : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2
S_AXI_RLAST => S_AXI_RLAST , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RVALID => S_AXI_RVALID , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Sideband Signals -- new for v6.2
S_AXI_INJECTSBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_INJECTDBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_SBITERR => S_AXI_SBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_DBITERR => S_AXI_DBITERR , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RDADDRECC => S_AXI_RDADDRECC -- : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2
);
end generate FAMILY_SUPPORTED;
end implementation;
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_intc_v4_1/28e93d3e/hdl/src/vhdl/shared_ram_ivar.vhd | 1 | 8750 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: byte_data_ram.vhd
-- Version: v3.0
-- Description: This file is a DPRAM which got used in the design for the
-- endpoint configuration and status register space along with
-- default endpoint buffer space & end point 1-7 buffer space
-- using the generics (C_DPRAM_DEPTH and C_ADDR_LINES)
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- Structure:
-- -- axi_usb2_device.vhd
-- -- axi_slave_burst.vhd
-- -- usbcore.v
-- -- ipic_if.vhd
-- -- byte_data_ram.vhd
-------------------------------------------------------------------------------
-- Author: PBB
-- History:
-- PBB 07/01/10 initial release
-- ^^^^^^^
-- ^^^^^^^
-- SK 10/10/12
--
-- 1. Added cascade mode support in v1.03.a version of the core
-- 2. Updated major version of the core
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.family.all;
library axi_intc_v4_1;
use axi_intc_v4_1.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_WIDTH -- Data width
-- C_DPRAM_DEPTH -- Depth of the DPRAM
-- C_ADDR_LINES -- No of Address lines
-- C_IVR_RESET_VALUE -- Reset values of IVR registers in RAM
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Addra -- Port-A address
-- Addrb -- Port-B address
-- Clka -- Port-A clock
-- Clkb -- Port-B clock
-- Dina -- Port-A data input
-- Dinb -- Port-B data input
-- Ena -- Port-A chip enable
-- Enb -- Port-B chip enable
-- Wea -- Port-A write enable
-- Web -- Port-B write enable
-- Douta -- Port-A data output
-- Doutb -- Port-B data output
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shared_ram_ivar IS
generic
(
C_WIDTH : integer := 32;
C_DPRAM_DEPTH : integer range 16 to 4096 := 16;
C_ADDR_LINES : integer range 0 to 15 := 4;
-- IVR Reset value parameter
C_IVAR_RESET_VALUE : std_logic_vector(31 downto 0) :=
"00000000000000000000000000010000"
);
port
(
Addra : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Addrb : in std_logic_VECTOR((C_ADDR_LINES - 1) downto 0);
Clka : in std_logic;
Clkb : in std_logic;
Dina : in std_logic_VECTOR((C_WIDTH-1) downto 0);
Wea : in std_logic;
Douta : out std_logic_VECTOR((C_WIDTH-1) downto 0);
Doutb : out std_logic_VECTOR((C_WIDTH-1) downto 0)
);
end shared_ram_ivar;
architecture byte_data_ram_a of shared_ram_ivar is
type ramType is array (0 to C_DPRAM_DEPTH-1) of std_logic_vector
((C_WIDTH-1) downto 0);
--shared variable ram: ramType := (others => (others => '0'));
signal ram: ramType := (others => C_IVAR_RESET_VALUE);
attribute ram_style : string;
attribute ram_style of ram : signal is "distributed";
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- DPRAM Port A Interface
-------------------------------------------------------------------------------
PORT_A_PROCESS: process(Clka)
begin
if Clka'event and Clka = '1' then
if (Wea = '1') then
ram(conv_integer(Addra)) <= Dina;
end if;
Douta <= ram(conv_integer(Addra));
end if;
end process;
-------------------------------------------------------------------------------
-- DPRAM Port B Interface
-------------------------------------------------------------------------------
PORT_B_PROCESS: process(Clkb)
begin
if Clkb'event and Clkb = '1' then
Doutb <= ram(conv_integer(Addrb));
end if;
end process;
end byte_data_ram_a;
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/rd_status_flags_as.vhd | 5 | 15251 | `protect begin_protected
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`protect end_protected
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/ld_arith_reg.vhd | 15 | 15091 | -------------------------------------------------------------------------------
-- $Id: ld_arith_reg.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 08/01 -- First version
--
-- FO 11/14/01 -- Cosmetic improvements
--
-- FO 02/22/02 -- Switched from MUXCY_L primitive to MUXCY.
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end ld_arith_reg;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <= '0' when C_ADD_SUB_NOT else OP;
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
-- Adder case
------------------------------------------------------------------------
Q_I_GEN_ADD: if C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case
------------------------------------------------------------------------
Q_I_GEN_SUB: if not C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= LOAD or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/816dc01c/hdl/vhdl/pselect_mask.vhd | 1 | 7196 | -------------------------------------------------------------------------------
-- $Id: pselect_mask.vhd,v 1.1.2.2 2010/09/06 09:01:24 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: pselect_mask.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.2.2 $
-- Date: $Date: 2010/09/06 09:01:24 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library Unisim;
use Unisim.all;
entity pselect_mask is
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 31) := "00000000000000100000000000000000";
C_MASK : std_logic_vector(0 to 31) := "00000000000001111100000000000000"
);
port (
A : in std_logic_vector(0 to C_AW-1);
Valid : in std_logic;
CS : out std_logic
);
end entity pselect_mask;
library unisim;
use unisim.all;
architecture imp of pselect_mask is
function Nr_Of_Ones (S : std_logic_vector) return natural is
variable tmp : natural := 0;
begin -- function Nr_Of_Ones
for I in S'range loop
if (S(I) = '1') then
tmp := tmp + 1;
end if;
end loop; -- I
return tmp;
end function Nr_Of_Ones;
function fix_AB (B : boolean; I : integer) return integer is
begin -- function fix_AB
if (not B) then
return I + 1;
else
return I;
end if;
end function fix_AB;
constant Nr : integer := Nr_Of_Ones(C_MASK);
constant Use_CIN : boolean := ((Nr mod 4) = 0);
constant AB : integer := fix_AB(Use_CIN, Nr);
attribute INIT : string;
constant NUM_LUTS : integer := (AB-1)/4+1;
-- function to initialize LUT within pselect
type int4 is array (3 downto 0) of integer;
function pselect_init_lut(i : integer;
AB : integer;
NUM_LUTS : integer;
C_AW : integer;
C_BAR : std_logic_vector(0 to 31))
return bit_vector is
variable init_vector : bit_vector(15 downto 0) := X"0001";
variable j : integer := 0;
variable val_in : int4;
begin
for j in 0 to 3 loop
if i < NUM_LUTS-1 or j <= ((AB-1) mod 4) then
val_in(j) := conv_integer(C_BAR(i*4+j));
else val_in(j) := 0;
end if;
end loop;
init_vector := To_bitvector(conv_std_logic_vector(2**(val_in(3)*8+
val_in(2)*4+val_in(1)*2+val_in(0)*1),16));
return init_vector;
end pselect_init_lut;
signal A_Bus : std_logic_vector(0 to AB);
signal BAR : std_logic_vector(0 to AB);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
Make_Busses : process (A,Valid) is
variable tmp : natural;
begin -- process Make_Busses
tmp := 0;
A_Bus <= (others => '0');
BAR <= (others => '0');
for I in C_MASK'range loop
if (C_MASK(I) = '1') then
A_Bus(tmp) <= A(I);
BAR(tmp) <= C_BAR(I);
tmp := tmp + 1;
end if;
end loop; -- I
if (not Use_CIN) then
BAR(tmp) <= '1';
A_Bus(tmp) <= Valid;
end if;
end process Make_Busses;
CS <= Valid when A_Bus=BAR else '0';
end imp;
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/builtin/logic_builtin.vhd | 5 | 30579 | `protect begin_protected
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`protect end_protected
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/816dc01c/hdl/vhdl/lmb_bram_if_cntlr.vhd | 1 | 50495 | -------------------------------------------------------------------------------
-- $Id: lmb_bram_if_cntlr.vhd,v 1.1.2.13 2010/11/25 12:28:48 stefana Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: lmb_bram_if_cntlr.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_bram_if_cntlr
-- lmb_mux
-- correct_one_bit
-- xor18.vhd
-- axi_interface
-------------------------------------------------------------------------------
-- Author: rolandp
-- Revision: $Revision: 1.1.2.13 $
-- Date: $Date: 2010/11/25 12:28:48 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.all;
entity lmb_bram_if_cntlr is
generic (
C_FAMILY : string := "Virtex7";
C_HIGHADDR : std_logic_vector(0 to 31) := X"00000000";
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_ECC : integer := 0;
C_INTERCONNECT : integer := 1;
C_FAULT_INJECT : integer := 0;
C_CE_FAILING_REGISTERS : integer := 0;
C_UE_FAILING_REGISTERS : integer := 0;
C_ECC_STATUS_REGISTERS : integer := 0;
C_ECC_ONOFF_REGISTER : integer := 0;
C_ECC_ONOFF_RESET_VALUE : integer := 1;
C_CE_COUNTER_WIDTH : integer := 0;
C_WRITE_ACCESS : integer := 2;
C_NUM_LMB : integer := 1;
-- AXI generics
C_S_AXI_CTRL_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_CTRL_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
C_S_AXI_CTRL_DATA_WIDTH : integer := 32);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus
LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : in std_logic;
LMB_ReadStrobe : in std_logic;
LMB_WriteStrobe : in std_logic;
LMB_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : out std_logic;
Sl_Wait : out std_logic;
Sl_UE : out std_logic;
Sl_CE : out std_logic;
-- Supplementary LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- Supplementary LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- Supplementary LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- ports to data memory block
BRAM_Rst_A : out std_logic;
BRAM_Clk_A : out std_logic;
BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1);
BRAM_EN_A : out std_logic;
BRAM_WEN_A : out std_logic_vector(0 to (C_LMB_DWIDTH+8*C_ECC)/8-1);
BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
-- AXI Interface
S_AXI_CTRL_ACLK : in std_logic;
S_AXI_CTRL_ARESETN : in std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WSTRB : in std_logic_vector((C_S_AXI_CTRL_DATA_WIDTH/8)-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- Interrupt and error signals
UE : out std_logic;
CE : out std_logic;
Interrupt : out std_logic);
end lmb_bram_if_cntlr;
library unisim;
use unisim.vcomponents.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
architecture imp of lmb_bram_if_cntlr is
------------------------------------------------------------------------------
-- component declarations
------------------------------------------------------------------------------
component lmb_mux is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_NUM_LMB : integer := 1);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus 0
LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB0_AddrStrobe : in std_logic;
LMB0_ReadStrobe : in std_logic;
LMB0_WriteStrobe : in std_logic;
LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl0_Ready : out std_logic;
Sl0_Wait : out std_logic;
Sl0_UE : out std_logic;
Sl0_CE : out std_logic;
-- LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- Muxed LMB Bus
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : out std_logic;
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : in std_logic;
Sl_Wait : in std_logic;
Sl_UE : in std_logic;
Sl_CE : in std_logic;
lmb_select : out std_logic);
end component lmb_mux;
component axi_interface
generic (
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end component;
component checkbit_handler is
generic (
C_ENCODE : boolean;
C_USE_LUT6 : boolean);
port (
DataIn : in std_logic_vector(0 to 31);
CheckIn : in std_logic_vector(0 to 6);
CheckOut : out std_logic_vector(0 to 6);
Syndrome : out std_logic_vector(0 to 6);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic);
end component checkbit_handler;
component Correct_One_Bit
generic (
C_USE_LUT6 : boolean;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end component Correct_One_Bit;
constant C_USE_LUT6 : boolean := Family_To_LUT_Size(String_To_Family(C_FAMILY,false)) = 6;
constant C_HAS_FAULT_INJECT : boolean := C_FAULT_INJECT = 1;
constant C_HAS_CE_FAILING_REGISTERS : boolean := C_CE_FAILING_REGISTERS = 1;
constant C_HAS_UE_FAILING_REGISTERS : boolean := C_UE_FAILING_REGISTERS = 1;
constant C_HAS_ECC_STATUS_REGISTERS : boolean := C_ECC_STATUS_REGISTERS = 1;
constant C_HAS_ECC_ONOFF_REGISTER : boolean := C_ECC_ONOFF_REGISTER = 1;
constant C_HAS_CE_COUNTER : boolean := C_CE_COUNTER_WIDTH /= 0;
constant C_BUS_NEEDED : boolean := C_HAS_FAULT_INJECT or
C_HAS_CE_FAILING_REGISTERS or
C_HAS_UE_FAILING_REGISTERS or
C_HAS_ECC_STATUS_REGISTERS or
C_HAS_ECC_ONOFF_REGISTER or
C_HAS_CE_COUNTER;
constant C_AXI : integer := 2;
constant C_HAS_AXI : boolean := C_ECC = 1 and C_INTERCONNECT = C_AXI and C_BUS_NEEDED;
constant C_ECC_WIDTH : integer := 7;
-- Intermediate signals to handle multiple LMB ports
signal LMB_ABus_i : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal LMB_WriteDBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal LMB_AddrStrobe_i : std_logic;
signal LMB_ReadStrobe_i : std_logic;
signal LMB_WriteStrobe_i : std_logic;
signal LMB_BE_i : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
signal Sl_DBus_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal Sl_Ready_i : std_logic;
signal Sl_Wait_i : std_logic;
signal Sl_UE_i : std_logic;
signal Sl_CE_i : std_logic;
signal lmb_select : std_logic;
signal lmb_as : std_logic;
signal lmb_we : std_logic_vector(0 to 3);
signal Sl_Rdy : std_logic;
signal bram_din_a_i : std_logic_vector(0 to C_LMB_DWIDTH+8*C_ECC-1);
begin
-----------------------------------------------------------------------------
-- Cleaning incoming data from BRAM from 'U' for simulation purpose
-- This is added since simulation model for BRAM will not initialize
-- undefined memory locations with zero.
-- Added as a work-around until this is fixed in the simulation model.
-----------------------------------------------------------------------------
Cleaning_machine: process (BRAM_Din_A) is
begin -- process Cleaning_machine
-- Default assignments
bram_din_a_i <= BRAM_Din_A;
-- pragma translate_off
bram_din_a_i <= To_StdLogicVector(To_bitvector(BRAM_Din_A));
-- pragma translate_on
end process Cleaning_machine;
lmb_mux_I : lmb_mux
generic map (
C_BASEADDR => C_BASEADDR,
C_MASK => C_MASK,
C_MASK1 => C_MASK1,
C_MASK2 => C_MASK2,
C_MASK3 => C_MASK3,
C_LMB_AWIDTH => C_LMB_AWIDTH,
C_LMB_DWIDTH => C_LMB_DWIDTH,
C_NUM_LMB => C_NUM_LMB)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
LMB0_ABus => LMB_ABus,
LMB0_WriteDBus => LMB_WriteDBus,
LMB0_AddrStrobe => LMB_AddrStrobe,
LMB0_ReadStrobe => LMB_ReadStrobe,
LMB0_WriteStrobe => LMB_WriteStrobe,
LMB0_BE => LMB_BE,
Sl0_DBus => Sl_DBus,
Sl0_Ready => Sl_Ready,
Sl0_Wait => Sl_Wait,
Sl0_UE => Sl_UE,
Sl0_CE => Sl_CE,
LMB1_ABus => LMB1_ABus,
LMB1_WriteDBus => LMB1_WriteDBus,
LMB1_AddrStrobe => LMB1_AddrStrobe,
LMB1_ReadStrobe => LMB1_ReadStrobe,
LMB1_WriteStrobe => LMB1_WriteStrobe,
LMB1_BE => LMB1_BE,
Sl1_DBus => Sl1_DBus,
Sl1_Ready => Sl1_Ready,
Sl1_Wait => Sl1_Wait,
Sl1_UE => Sl1_UE,
Sl1_CE => Sl1_CE,
LMB2_ABus => LMB2_ABus,
LMB2_WriteDBus => LMB2_WriteDBus,
LMB2_AddrStrobe => LMB2_AddrStrobe,
LMB2_ReadStrobe => LMB2_ReadStrobe,
LMB2_WriteStrobe => LMB2_WriteStrobe,
LMB2_BE => LMB2_BE,
Sl2_DBus => Sl2_DBus,
Sl2_Ready => Sl2_Ready,
Sl2_Wait => Sl2_Wait,
Sl2_UE => Sl2_UE,
Sl2_CE => Sl2_CE,
LMB3_ABus => LMB3_ABus,
LMB3_WriteDBus => LMB3_WriteDBus,
LMB3_AddrStrobe => LMB3_AddrStrobe,
LMB3_ReadStrobe => LMB3_ReadStrobe,
LMB3_WriteStrobe => LMB3_WriteStrobe,
LMB3_BE => LMB3_BE,
Sl3_DBus => Sl3_DBus,
Sl3_Ready => Sl3_Ready,
Sl3_Wait => Sl3_Wait,
Sl3_UE => Sl3_UE,
Sl3_CE => Sl3_CE,
LMB_ABus => LMB_ABus_i,
LMB_WriteDBus => LMB_WriteDBus_i,
LMB_AddrStrobe => LMB_AddrStrobe_i,
LMB_ReadStrobe => LMB_ReadStrobe_i,
LMB_WriteStrobe => LMB_WriteStrobe_i,
LMB_BE => LMB_BE_i,
Sl_DBus => Sl_DBus_i,
Sl_Ready => Sl_Ready_i,
Sl_Wait => Sl_Wait_i,
Sl_UE => Sl_UE_i,
Sl_CE => Sl_CE_i,
lmb_select => lmb_select);
BRAM_Rst_A <= '0';
BRAM_Clk_A <= LMB_Clk;
lmb_we(0) <= LMB_BE_i(0) and LMB_WriteStrobe_i and lmb_select;
lmb_we(1) <= LMB_BE_i(1) and LMB_WriteStrobe_i and lmb_select;
lmb_we(2) <= LMB_BE_i(2) and LMB_WriteStrobe_i and lmb_select;
lmb_we(3) <= LMB_BE_i(3) and LMB_WriteStrobe_i and lmb_select;
No_ECC : if (C_ECC = 0) generate
begin
BRAM_EN_A <= LMB_AddrStrobe_i;
BRAM_WEN_A <= lmb_we;
BRAM_Dout_A <= LMB_WriteDBus_i;
Sl_DBus_i <= bram_din_a_i;
BRAM_Addr_A <= LMB_ABus_i;
-- only used wen ECC enabled, tie to constant inactive
Sl_Wait_i <= '0';
Sl_UE_i <= '0';
Sl_CE_i <= '0';
UE <= '0';
CE <= '0';
Interrupt <= '0';
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
Sl_Rdy <= lmb_select;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy and lmb_as;
end generate No_ECC;
ECC : if (C_ECC = 1) generate
constant NO_WRITES : integer := 0;
constant ONLY_WORD : integer := 1;
constant ALL_WRITES : integer := 2;
signal enable_ecc : std_logic;
-- On/Off Register
constant C_ECC_ONOFF : natural := 31;
constant C_ECC_ONOFF_WIDTH : natural := 1;
signal ECC_EnableCheckingReg : std_logic_vector(32-C_ECC_ONOFF_WIDTH to 31);
-- Fault Inject Registers
signal FaultInjectData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal FaultInjectECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Signals for read modify write operation when byte/half-word write
signal write_access : std_logic;
signal full_word_write_access : std_logic;
signal IsWordWrite : std_logic;
signal RdModifyWr_Read : std_logic; -- Read cycle in read modify write sequence
signal RdModifyWr_Modify : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Modify_i : std_logic; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic; -- Write cycle in read modify write sequence
signal LMB_ABus_Q : std_logic_vector(0 to C_LMB_AWIDTH-1);
-- Read ECC
signal Syndrome : std_logic_vector(0 to C_ECC_WIDTH-1);
signal CorrectedRdData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CorrectedRdData_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_Q : std_logic;
signal UE_Q : std_logic;
-- Enable and address same for both data and ECC BRAM
signal bram_en : std_logic;
signal bram_addr : std_logic_vector(0 to C_LMB_AWIDTH-1);
subtype syndrome_bits is std_logic_vector(0 to 6);
type correct_data_table_type is array(natural range 0 to 31) of syndrome_bits;
constant correct_data_table : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
begin
-- Enable BRAMs when access on LMB and in the second cycle in a read/modify write
bram_en <= '1' when LMB_AddrStrobe_i = '1' or RdModifyWr_Write = '1' else
'0';
BRAM_EN_A <= bram_en;
IsWordWrite <= LMB_WriteStrobe_i when (LMB_BE_i = "1111") else '0';
-- ECC checking enable during access and when checking is turned on
enable_ecc <= ECC_EnableCheckingReg(C_ECC_ONOFF) and Sl_Wait_i and not(full_word_write_access);
-----------------------------------------------------------------------------
-- Writes are pipelined in MB with 5 stage pipeline
-----------------------------------------------------------------------------
Ready_Handling : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
Sl_Rdy <= '0';
lmb_as <= '0';
else
-- Directly drive ready on valid read access or on valid word write access
-- otherwise drive ready when we have written the new data on a
-- readmodifywrite sequence
Sl_Rdy <= ((LMB_AddrStrobe_i and lmb_select) and (LMB_ReadStrobe_i or IsWordWrite))
or RdModifyWr_Write;
lmb_as <= LMB_AddrStrobe_i;
end if;
end if;
end process Ready_Handling;
Sl_Ready_i <= Sl_Rdy;
Wait_Handling: process (LMB_Clk) is
begin -- process Wait_Handling
if (LMB_Clk'event and LMB_Clk = '1') then -- rising clock edge
if (LMB_Rst = '1') then
Sl_Wait_i <= '0';
elsif (LMB_AddrStrobe_i = '1') then
Sl_Wait_i <= lmb_select;
elsif (Sl_Rdy = '1') then
Sl_Wait_i <= '0';
end if;
end if;
end process Wait_Handling;
-- Generate ECC bits for checking data read from BRAM
checkbit_handler_I1 : checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
DataIn => bram_din_a_i(0 to 31), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(33 to 39), -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Enable_ECC => enable_ecc, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i); -- [out std_logic]
-- Discrete error signals
UE <= Sl_UE_i and Sl_Ready_i;
CE <= Sl_CE_i and Sl_Ready_i;
-- Correct Data
Gen_Correct_Data: for I in 0 to 31 generate
Correct_One_Bit_I : Correct_One_Bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table(I))
port map (
DIn => bram_din_a_i(I),
Syndrome => Syndrome,
DCorr => CorrectedRdData(I));
end generate Gen_Correct_Data;
-- Drive corrected read data on LMB
Sl_DBus_i <= CorrectedRdData;
-- Remember address and writestrobe
AddressReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if LMB_Rst = '1' then
LMB_ABus_Q <= (others => '0');
write_access <= '0';
full_word_write_access <= '0';
elsif LMB_AddrStrobe_i = '1' then
LMB_ABus_Q <= LMB_ABus_i;
write_access <= LMB_WriteStrobe_i;
full_word_write_access <= LMB_BE_i(0) and LMB_BE_i(1) and LMB_BE_i(2) and LMB_BE_i(3) and LMB_WriteStrobe_i;
end if;
end if;
end process AddressReg;
bram_addr <= LMB_ABus_Q when RdModifyWr_Write = '1' else
LMB_ABus_i;
BRAM_Addr_A <= bram_addr;
Do_Writes : if (C_WRITE_ACCESS /= NO_WRITES) generate
signal WrData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal WrECC : std_logic_vector(0 to C_ECC_WIDTH-1);
constant null7 : std_logic_vector(0 to 6) := "0000000";
begin
DO_BYTE_HALFWORD_WRITES : if (C_WRITE_ACCESS = ALL_WRITES) generate
signal wrdata_i : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal writeDBus_Q : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal lmb_be_q : std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
begin
-- Remember correctable/uncorrectable error from read in read modify write
CorrReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if RdModifyWr_Modify = '1' then -- Remember error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
elsif RdModifyWr_Write = '1' then -- Keep the signals one more cycle
CE_Q <= CE_Q;
UE_Q <= UE_Q;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CorrReg;
-- Remember byte write enables one clock cycle to properly mux bytes to write,
-- with read data in read/modify write operation
-- Write in Read/Write always 1 cycle after Read
StoreLMB_WE : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
RdModifyWr_Modify_i <= RdModifyWr_Read;
RdModifyWr_Write <= RdModifyWr_Modify;
CorrectedRdData_Q <= CorrectedRdData;
end if;
end process StoreLMB_WE;
RdModifyWr_Modify <= RdModifyWr_Modify_i and lmb_as;
RdModifyWr_Read <= '1' when lmb_we /= "1111" and lmb_we /= "0000" and (C_WRITE_ACCESS = ALL_WRITES) else
'0';
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation
StoreWriteDBus : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
WriteDBus_Q <= (others => '0');
lmb_be_q <= (others => '0');
elsif (LMB_AddrStrobe_i = '1') then
WriteDBus_Q <= LMB_WriteDBus_i;
lmb_be_q <= LMB_BE_i;
end if;
end if;
end process StoreWriteDBus;
wrdata_i <= WriteDBus_Q when RdModifyWr_Write = '1' else LMB_WriteDBus_i;
-- Select BRAM data to write from LMB on 32-bit word access or a mix of
-- read data and LMB write data for read/modify write operations
WrData(0 to 7) <= wrdata_i(0 to 7) when ((RdModifyWr_Write = '0' and LMB_BE_i(0) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(0) = '1')) else
CorrectedRdData_Q(0 to 7);
WrData(8 to 15) <= wrdata_i(8 to 15) when ((RdModifyWr_Write = '0' and LMB_BE_i(1) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(1) = '1')) else
CorrectedRdData_Q(8 to 15);
WrData(16 to 23) <= wrdata_i(16 to 23) when ((RdModifyWr_Write = '0' and LMB_BE_i(2) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(2) = '1')) else
CorrectedRdData_Q(16 to 23);
WrData(24 to 31) <= wrdata_i(24 to 31) when ((RdModifyWr_Write = '0' and LMB_BE_i(3) = '1') or
(RdModifyWr_Write = '1' and lmb_be_q(3) = '1')) else
CorrectedRdData_Q(24 to 31);
end generate DO_BYTE_HALFWORD_WRITES;
DO_Only_Word_Writes : if (C_WRITE_ACCESS = ONLY_WORD) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
WrData <= LMB_WriteDBus_i;
CE_Q <= '0';
UE_Q <= '0';
end generate DO_Only_Word_Writes;
-- Generate BRAM WEN, which will always be all 1's due to read modify write
-- for non 32-bit word access
WrDataSel : process(IsWordWrite, lmb_select, RdModifyWr_Modify, RdModifyWr_Write, UE_Q)
begin
if (RdModifyWr_Modify = '1') then
BRAM_WEN_A <= (others => '0');
elsif (RdModifyWr_Write = '1') then
if (UE_Q = '0') then
BRAM_WEN_A <= (others => '1'); -- byte or half word write, and not UE
else
BRAM_WEN_A <= (others => '0');
end if;
elsif (IsWordWrite = '1') then -- word write
BRAM_WEN_A <= (others => lmb_select);
else
BRAM_WEN_A <= (others => '0');
end if;
end process WrDataSel;
-- Generate ECC bits for writing into BRAM
checkbit_handler_I2 : checkbit_handler
generic map (
C_ENCODE => true, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open); -- [out std_logic]
-- Drive BRAM write data and inject fault if applicable
BRAM_Dout_A(0 to 31) <= WrData xor FaultInjectData;
BRAM_Dout_A(32 to 39) <= ('0' & WrECC) xor ('0' & FaultInjectECC);
end generate Do_Writes;
No_Write_Accesses : if (C_WRITE_ACCESS = NO_WRITES) generate
RdModifyWr_Write <= '0';
RdModifyWr_Read <= '0';
RdModifyWr_Modify <= '0';
CorrectedRdData_Q <= (others => '0');
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
CE_Q <= '0';
UE_Q <= '0';
BRAM_WEN_A <= (others => '0');
end generate No_Write_Accesses;
Has_AXI : if C_HAS_AXI generate
-- Register accesses
-- Register addresses use word address, i.e 2 LSB don't care
-- Don't decode MSB, i.e. mirroring of registers in address space of module
-- Don't decode unmapped addresses
-- Data registers occupy 32 words to accommodate up to 1024-bit words in other IPs
-- ECC registers occupy 16 words to accomodate up to 512-bit ECC in other IPs
-- Address registers occupy 2 words to accommodate 64-bit address in other IPs
constant C_REGADDR_WIDTH : integer := 8;
constant C_ECC_StatusReg : std_logic_vector := "00000000"; -- 0x000 ECC_STATUS
constant C_ECC_EnableIRQReg : std_logic_vector := "00000001"; -- 0x004 ECC_EN_IRQ
constant C_ECC_OnOffReg : std_logic_vector := "00000010"; -- 0x008 ECC_ONOFF
constant C_CE_CounterReg : std_logic_vector := "00000011"; -- 0x00C CE_CNT
constant C_CE_FailingData : std_logic_vector := "01000000"; -- 0x100 CE_FFD[31:0]
constant C_CE_FailingECC : std_logic_vector := "01100000"; -- 0x180 CE_FFE
constant C_CE_FailingAddress : std_logic_vector := "01110000"; -- 0x1C0 CE_FFA[31:0]
constant C_UE_FailingData : std_logic_vector := "10000000"; -- 0x200 UE_FFD[31:0]
constant C_UE_FailingECC : std_logic_vector := "10100000"; -- 0x280 UE_FFE
constant C_UE_FailingAddress : std_logic_vector := "10110000"; -- 0x2C0 UE_FFA[31:0]
constant C_FaultInjectData : std_logic_vector := "11000000"; -- 0x300 FI_D[31:0]
constant C_FaultInjectECC : std_logic_vector := "11100000"; -- 0x380 FI_ECC
-- ECC Status register bit positions
constant C_ECC_STATUS_CE : natural := 30;
constant C_ECC_STATUS_UE : natural := 31;
constant C_ECC_STATUS_WIDTH : natural := 2;
constant C_ECC_ENABLE_IRQ_CE : natural := 30;
constant C_ECC_ENABLE_IRQ_UE : natural := 31;
constant C_ECC_ENABLE_IRQ_WIDTH : natural := 2;
-- Read and write data to internal registers
constant C_DWIDTH : integer := 32;
signal RegWrData : std_logic_vector(0 to C_DWIDTH-1);
signal RegRdData : std_logic_vector(0 to C_DWIDTH-1);
signal RegAddr : std_logic_vector(0 to C_REGADDR_WIDTH-1);
signal RegWr : std_logic;
-- Correctable Error First Failing Register
signal CE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal CE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal CE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- Uncorrectable Error First Failing Register
signal UE_FailingAddress : std_logic_vector(0 to C_LMB_AWIDTH-1);
signal UE_FailingData : std_logic_vector(0 to C_LMB_DWIDTH-1);
signal UE_FailingECC : std_logic_vector(32-C_ECC_WIDTH to 31);
-- ECC Status and Control register
signal ECC_StatusReg : std_logic_vector(32-C_ECC_STATUS_WIDTH to 31);
signal ECC_EnableIRQReg : std_logic_vector(32-C_ECC_ENABLE_IRQ_WIDTH to 31);
-- Correctable Error Counter
signal CE_CounterReg : std_logic_vector(32-C_CE_COUNTER_WIDTH to 31);
signal sample_registers : std_logic;
begin
sample_registers <= lmb_as and not full_word_write_access;
-- Implement fault injection registers
Fault_Inject : if C_HAS_FAULT_INJECT and (C_WRITE_ACCESS /= NO_WRITES) generate
begin
FaultInjectDataReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
elsif RegWr = '1' and RegAddr = C_FaultInjectData then
FaultInjectData <= RegWrData;
elsif RegWr = '1' and RegAddr = C_FaultInjectECC then
FaultInjectECC <= RegWrData(FaultInjectECC'range);
elsif (Sl_Rdy = '1') and (write_access = '1') then -- One shoot, clear after first LMB write
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end if;
end if;
end process FaultInjectDataReg;
end generate Fault_Inject;
No_Fault_Inject : if not C_HAS_FAULT_INJECT or (C_WRITE_ACCESS = NO_WRITES) generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
end generate No_Fault_Inject;
-- Implement Correctable Error First Failing Register
CE_Failing_Registers : if C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
elsif Sl_CE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_CE) = '0' then
CE_FailingAddress <= LMB_ABus_Q;
CE_FailingData <= bram_din_a_i(CE_FailingData'range);
CE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process CE_FailingReg;
end generate CE_Failing_Registers;
No_CE_Failing_Registers : if not C_HAS_CE_FAILING_REGISTERS generate
begin
CE_FailingAddress <= (others => '0');
CE_FailingData <= (others => '0');
CE_FailingECC <= (others => '0');
end generate No_CE_Failing_Registers;
-- Implement Unorrectable Error First Failing Register
UE_Failing_Registers : if C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
elsif Sl_UE_i = '1' and sample_registers = '1' and ECC_StatusReg(C_ECC_STATUS_UE) = '0' then
UE_FailingAddress <= LMB_ABus_Q;
UE_FailingData <= bram_din_a_i(UE_FailingData'range);
UE_FailingECC <= bram_din_a_i(33 to 33+C_ECC_WIDTH-1);
end if;
end if;
end process UE_FailingReg;
end generate UE_Failing_Registers;
No_UE_Failing_Registers : if not C_HAS_UE_FAILING_REGISTERS generate
begin
UE_FailingAddress <= (others => '0');
UE_FailingData <= (others => '0');
UE_FailingECC <= (others => '0');
end generate No_UE_Failing_Registers;
ECC_Status_Registers : if C_HAS_ECC_STATUS_REGISTERS generate
begin
StatusReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_StatusReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_StatusReg then
-- CE Interrupt status bit
if RegWrData(C_ECC_STATUS_CE) = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '0'; -- Clear when write '1'
end if;
-- UE Interrupt status bit
if RegWrData(C_ECC_STATUS_UE) = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '0'; -- Clear when write '1'
end if;
else
if Sl_CE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_CE) <= '1'; -- Set when CE occurs
end if;
if Sl_UE_i = '1' and sample_registers = '1' then
ECC_StatusReg(C_ECC_STATUS_UE) <= '1'; -- Set when UE occurs
end if;
end if;
end if;
end process StatusReg;
EnableIRQReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ECC_EnableIRQReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_ECC_EnableIRQReg then
-- CE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE) <= RegWrData(C_ECC_ENABLE_IRQ_CE);
-- UE Interrupt enable bit
ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE) <= RegWrData(C_ECC_ENABLE_IRQ_UE);
end if;
end if;
end process EnableIRQReg;
Interrupt <= (ECC_StatusReg(C_ECC_STATUS_CE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_CE)) or
(ECC_StatusReg(C_ECC_STATUS_UE) and ECC_EnableIRQReg(C_ECC_ENABLE_IRQ_UE));
end generate ECC_Status_Registers;
No_ECC_Status_Registers : if not C_HAS_ECC_STATUS_REGISTERS generate
begin
ECC_EnableIRQReg <= (others => '0');
ECC_StatusReg <= (others => '0');
Interrupt <= '0';
end generate No_ECC_Status_Registers;
ECC_OnOff_Register : if C_HAS_ECC_ONOFF_REGISTER generate
begin
OnOffReg : process(LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
if C_ECC_ONOFF_RESET_VALUE = 0 then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '0';
else
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end if;
elsif RegWr = '1' and RegAddr = C_ECC_OnOffReg then
ECC_EnableCheckingReg(C_ECC_ONOFF) <= RegWrData(C_ECC_ONOFF);
end if;
end if;
end process OnOffReg;
end generate ECC_OnOff_Register;
No_ECC_OnOff_Register : if not C_HAS_ECC_ONOFF_REGISTER generate
begin
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_ECC_OnOff_Register;
CE_Counter : if C_HAS_CE_COUNTER generate
-- One extra bit compare to CE_CounterReg to handle carry bit
signal CE_CounterReg_plus_1 : std_logic_vector(31-C_CE_COUNTER_WIDTH to 31);
begin
CountReg : process(LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
CE_CounterReg <= (others => '0');
elsif RegWr = '1' and RegAddr = C_CE_CounterReg then
CE_CounterReg <= RegWrData(CE_CounterReg'range);
elsif Sl_CE_i = '1' and
sample_registers = '1' and
CE_CounterReg_plus_1(CE_CounterReg_plus_1'left) = '0' then
CE_CounterReg <= CE_CounterReg_plus_1(32-C_CE_COUNTER_WIDTH to 31);
end if;
end if;
end process CountReg;
CE_CounterReg_plus_1 <= std_logic_vector(unsigned(('0' & CE_CounterReg)) + 1);
end generate CE_Counter;
No_CE_Counter : if not C_HAS_CE_COUNTER generate
begin
CE_CounterReg <= (others => '0');
end generate No_CE_Counter;
SelRegRdData : process (RegAddr,
ECC_StatusReg, ECC_EnableIRQReg, ECC_EnableCheckingReg, CE_CounterReg,
CE_FailingAddress, CE_FailingData, CE_FailingECC,
UE_FailingAddress, UE_FailingData, UE_FailingECC)
begin
RegRdData <= (others => '0');
case RegAddr is
when C_ECC_StatusReg => RegRdData(ECC_StatusReg'range) <= ECC_StatusReg;
when C_ECC_EnableIRQReg => RegRdData(ECC_EnableIRQReg'range) <= ECC_EnableIRQReg;
when C_ECC_OnOffReg => RegRdData(ECC_EnableCheckingReg'range) <= ECC_EnableCheckingReg;
when C_CE_CounterReg => RegRdData(CE_CounterReg'range) <= CE_CounterReg;
when C_CE_FailingAddress => RegRdData(CE_FailingAddress'range) <= CE_FailingAddress;
when C_CE_FailingData => RegRdData(CE_FailingData'range) <= CE_FailingData;
when C_CE_FailingECC => RegRdData(CE_FailingECC'range) <= CE_FailingECC;
when C_UE_FailingAddress => RegRdData(UE_FailingAddress'range) <= UE_FailingAddress;
when C_UE_FailingData => RegRdData(UE_FailingData'range) <= UE_FailingData;
when C_UE_FailingECC => RegRdData(UE_FailingECC'range) <= UE_FailingECC;
when others => RegRdData <= (others => '0');
end case;
end process SelRegRdData;
AXI : if C_HAS_AXI generate
begin
axi_I : axi_interface
generic map(
C_S_AXI_BASEADDR => C_S_AXI_CTRL_BASEADDR,
C_S_AXI_HIGHADDR => C_S_AXI_CTRL_HIGHADDR,
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH,
C_REGADDR_WIDTH => C_REGADDR_WIDTH,
C_DWIDTH => C_DWIDTH)
port map (
LMB_Clk => LMB_Clk,
LMB_Rst => LMB_Rst,
S_AXI_AWADDR => S_AXI_CTRL_AWADDR,
S_AXI_AWVALID => S_AXI_CTRL_AWVALID,
S_AXI_AWREADY => S_AXI_CTRL_AWREADY,
S_AXI_WDATA => S_AXI_CTRL_WDATA,
S_AXI_WSTRB => S_AXI_CTRL_WSTRB,
S_AXI_WVALID => S_AXI_CTRL_WVALID,
S_AXI_WREADY => S_AXI_CTRL_WREADY,
S_AXI_BRESP => S_AXI_CTRL_BRESP,
S_AXI_BVALID => S_AXI_CTRL_BVALID,
S_AXI_BREADY => S_AXI_CTRL_BREADY,
S_AXI_ARADDR => S_AXI_CTRL_ARADDR,
S_AXI_ARVALID => S_AXI_CTRL_ARVALID,
S_AXI_ARREADY => S_AXI_CTRL_ARREADY,
S_AXI_RDATA => S_AXI_CTRL_RDATA,
S_AXI_RRESP => S_AXI_CTRL_RRESP,
S_AXI_RVALID => S_AXI_CTRL_RVALID,
S_AXI_RREADY => S_AXI_CTRL_RREADY,
RegWr => RegWr,
RegWrData => RegWrData,
RegAddr => RegAddr,
RegRdData => RegRdData);
end generate AXI;
end generate Has_AXI;
No_AXI : if not C_HAS_AXI generate
begin
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
Interrupt <= '0';
ECC_EnableCheckingReg(C_ECC_ONOFF) <= '1';
end generate No_AXI;
end generate ECC;
No_AXI_ECC : if not C_HAS_AXI generate
begin
S_AXI_CTRL_AWREADY <= '0';
S_AXI_CTRL_WREADY <= '0';
S_AXI_CTRL_BRESP <= (others => '0');
S_AXI_CTRL_BVALID <= '0';
S_AXI_CTRL_ARREADY <= '0';
S_AXI_CTRL_RDATA <= (others => '0');
S_AXI_CTRL_RRESP <= (others => '0');
S_AXI_CTRL_RVALID <= '0';
end generate No_AXI_ECC;
end architecture imp;
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/or_muxcy.vhd | 15 | 10538 | -------------------------------------------------------------------------------
-- $Id: or_muxcy.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy.vhd
--
-- Description: This file is used to OR together consecutive bits within
-- sections of a bus.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 04/06/01 -- First version
--
-- ALS 05/18/01
-- ^^^^^^
-- Added use of carry chain muxes if number of bits is > 4
-- ~~~~~~
-- BLT 05/23/01
-- ^^^^^^
-- Removed pad_4 function, replaced with arithmetic expression
-- ~~~~~~
-- BLT 05/24/01
-- ^^^^^^
-- Removed Sig input, removed C_START_BIT and C_BUS_SIZE
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Unisim library contains Xilinx primitives
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BITS -- number of bits to OR in bus section
--
-- Definition of Ports:
-- input In_Bus -- bus containing bits to be ORd
-- output Or_out -- OR result
--
-------------------------------------------------------------------------------
entity or_muxcy is
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy;
architecture implementation of or_muxcy is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Pad the number of bits to OR to the next multiple of 4
constant NUM_BITS_PAD : integer := ((C_NUM_BITS-1)/4+1)*4;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- define output of OR chain
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Carry Chain muxes are used to implement OR of 4 bits or more
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
begin
-- If the number of bits to OR is 4 or less, a simple LUT can be used
LESSTHAN4_GEN: if C_NUM_BITS < 5 generate
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to C_NUM_BITS-1) := (others => '0');
begin
BIT_LOOP: for i in 0 to C_NUM_BITS-1 generate
FIRST: if i = 0 generate
or_tmp(i) <= In_bus(0);
end generate FIRST;
REST: if i /= 0 generate
or_tmp(i) <= or_tmp(i-1) or In_bus(i);
end generate REST;
end generate BIT_LOOP;
Or_out <= or_tmp(C_NUM_BITS-1);
end generate LESSTHAN4_GEN;
-- If the number of bits to OR is 4 or more, then use LUTs and
-- carry chain. Pad the number of bits to the nearest multiple of 4
MORETHAN4_GEN: if C_NUM_BITS >= 5 generate
-- define output of LUTs
signal lut_out : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
-- define padded input bus
signal in_bus_pad : std_logic_vector(0 to NUM_BITS_PAD-1) := (others => '0');
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
begin
-- pad input bus
in_bus_pad(0 to C_NUM_BITS-1) <= In_bus(0 to C_NUM_BITS-1);
OR_GENERATE: for i in 0 to NUM_BITS_PAD/4-1 generate
lut_out(i) <= not( in_bus_pad(i*4) or
in_bus_pad(i*4+1) or
in_bus_pad(i*4+2) or
in_bus_pad(i*4+3) );
FIRST: if i = 0 generate
FIRSTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => '0' , --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate FIRST;
REST: if i /= 0 generate
RESTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => or_tmp(i-1), --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate REST;
end generate OR_GENERATE;
Or_out <= or_tmp(NUM_BITS_PAD/4-1);
end generate MORETHAN4_GEN;
end implementation;
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/ramfifo/fifo_generator_ramfifo.vhd | 5 | 80159 | `protect begin_protected
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57600)
`protect data_block
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`protect end_protected
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/wb_mux_gti.vhd | 1 | 34470 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23776)
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| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/lmb_bram_if_cntlr_v4_0/816dc01c/hdl/vhdl/axi_interface.vhd | 1 | 9447 | -------------------------------------------------------------------------------
-- $Id: axi_interface.vhd,v 1.1.2.3 2010/10/11 08:21:49 rolandp Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: axi_interface.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_interface.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-- Revision: $Revision: 1.1.2.3 $
-- Date: $Date: 2010/10/11 08:21:49 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity axi_interface is
generic (
-- AXI4-Lite slave generics
C_S_AXI_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_S_AXI_HIGHADDR : std_logic_vector := X"0000_0000";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_REGADDR_WIDTH : integer := 5; -- Address bits including register offset.
C_DWIDTH : integer := 32); -- Width of data bus.
port (
LMB_Clk : in std_logic;
LMB_Rst : in std_logic;
-- AXI4-Lite SLAVE SINGLE INTERFACE
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- lmb_bram_if_cntlr signals
RegWr : out std_logic;
RegWrData : out std_logic_vector(0 to C_DWIDTH - 1);
RegAddr : out std_logic_vector(0 to C_REGADDR_WIDTH-1);
RegRdData : in std_logic_vector(0 to C_DWIDTH - 1));
end entity axi_interface;
library unisim;
use unisim.vcomponents.all;
architecture IMP of axi_interface is
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal new_write_access : std_logic;
signal new_read_access : std_logic;
signal ongoing_write : std_logic;
signal ongoing_read : std_logic;
signal S_AXI_RVALID_i : std_logic;
signal RegRdData_i : std_logic_vector(C_DWIDTH - 1 downto 0);
begin -- architecture IMP
-----------------------------------------------------------------------------
-- Handling the AXI4-Lite bus interface (AR/AW/W)
-----------------------------------------------------------------------------
-- Detect new transaction.
-- Only allow one access at a time
new_write_access <= not (ongoing_read or ongoing_write) and S_AXI_AWVALID and S_AXI_WVALID;
new_read_access <= not (ongoing_read or ongoing_write) and S_AXI_ARVALID and not new_write_access;
-- Acknowledge new transaction.
S_AXI_AWREADY <= new_write_access;
S_AXI_WREADY <= new_write_access;
S_AXI_ARREADY <= new_read_access;
-- Store register address and write data
Reg: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
RegAddr <= (others => '0');
RegWrData <= (others => '0');
elsif new_write_access = '1' then
RegAddr <= S_AXI_AWADDR(C_REGADDR_WIDTH-1+2 downto 2);
RegWrData <= S_AXI_WDATA(C_DWIDTH-1 downto 0);
elsif new_read_access = '1' then
RegAddr <= S_AXI_ARADDR(C_REGADDR_WIDTH-1+2 downto 2);
end if;
end if;
end process Reg;
-- Handle write access.
WriteAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_write <= '0';
elsif new_write_access = '1' then
ongoing_write <= '1';
elsif ongoing_write = '1' and S_AXI_BREADY = '1' then
ongoing_write <= '0';
end if;
RegWr <= new_write_access;
end if;
end process WriteAccess;
S_AXI_BVALID <= ongoing_write;
S_AXI_BRESP <= (others => '0');
-- Handle read access
ReadAccess: process (LMB_Clk) is
begin
if LMB_Clk'event and LMB_Clk = '1' then
if LMB_Rst = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
elsif new_read_access = '1' then
ongoing_read <= '1';
S_AXI_RVALID_i <= '0';
elsif ongoing_read = '1' then
if S_AXI_RREADY = '1' and S_AXI_RVALID_i = '1' then
ongoing_read <= '0';
S_AXI_RVALID_i <= '0';
else
S_AXI_RVALID_i <= '1'; -- Asserted one cycle after ongoing_read to match S_AXI_RDDATA
end if;
end if;
end if;
end process ReadAccess;
S_AXI_RVALID <= S_AXI_RVALID_i;
S_AXI_RRESP <= (others => '0');
Not_All_Bits_Are_Used: if (C_DWIDTH < C_S_AXI_DATA_WIDTH) generate
begin
S_AXI_RDATA(C_S_AXI_DATA_WIDTH-1 downto C_S_AXI_DATA_WIDTH - C_DWIDTH) <= (others=>'0');
end generate Not_All_Bits_Are_Used;
RegRdData_i <= RegRdData; -- Swap to - downto
S_AXI_RDATA_DFF : for I in C_DWIDTH - 1 downto 0 generate
begin
S_AXI_RDATA_FDRE : FDRE
port map (
Q => S_AXI_RDATA(I),
C => LMB_Clk,
CE => ongoing_read,
D => RegRdData_i(I),
R => LMB_Rst);
end generate S_AXI_RDATA_DFF;
end architecture IMP;
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/axi_master_burst_v2_0/1af76933/hdl/src/vhdl/axi_master_burst_rddata_cntl.vhd | 1 | 60335 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_rddata_cntl.vhd
--
-- Description:
-- This file implements the AXI Master Burst Read Data Controller module.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_rddata_cntl.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0$
-- Date: $1/19/2011$
--
-- History:
--
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from DataMover v2_00_a axi_datamover_rddata_cntl.vhd
-- ^^^^^^
--
-- DET 1/19/2011 Initial
-- ~~~~~~
-- -- See CR590244 for DataMover
-- - Added additional check on the pop of the status coelscing register.
-- THis is needed to handle the case of a simultaneous push and pop of
-- the coelescing register.
-- ^^^^^^
--
-- DET 2/15/2011 Initial for EDk 13.2
-- ~~~~~~
-- -- Per CR593812
-- - Modifications to remove unused features to improve Code coverage.
-- Used "-- coverage off" and "-- coverage on" strings.
-- ^^^^^^
-- ~~~~~~
-- Fixed CR #688186
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_master_burst_v2_0;
use axi_master_burst_v2_0.axi_master_burst_rdmux;
use axi_master_burst_v2_0.axi_master_burst_fifo;
-------------------------------------------------------------------------------
entity axi_master_burst_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
C_MMAP_DWIDTH : Integer range 32 to 256 := 32;
C_STREAM_DWIDTH : Integer range 8 to 256 := 32;
C_TAG_WIDTH : Integer range 1 to 8 := 4;
C_FAMILY : String := "virtex7"
);
port (
-- Clock input
primary_aclk : in std_logic;
-- Primary synchronization clock for the Master side
-- interface and internal logic. It is also used
-- for the User interface synchronization when
-- C_STSCMD_IS_ASYNC = 0.
-- Reset input
mmap_reset : in std_logic;
-- Reset used for the internal master logic
-- Soft Shutdown internal interface ---------------------------
rst2data_stop_request : in std_logic;
-- Active high soft stop request to modules
data2addr_stop_req : Out std_logic;
-- Active high signal requesting the Address Controller
-- to stop posting commands to the AXI Read Address Channel
data2rst_stop_cmplt : Out std_logic;
-- Active high indication that the Data Controller has completed
-- any pending transfers committed by the Address Controller
-- after a stop has been requested by the Reset module.
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt : out std_logic;
-- Active high indication that the Data Controller has completed
-- a single read data transfer on the AXI4 Read Data Channel.
-- This signal escentially echos the assertion of rlast received
-- from the AXI4.
-- AXI Read Data Channel I/O ----------------------------------
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0);
-- AXI Read data input
mm2s_rresp : In std_logic_vector(1 downto 0);
-- AXI Read response input
mm2s_rlast : In std_logic;
-- AXI Read LAST input
mm2s_rvalid : In std_logic;
-- AXI Read VALID input
mm2s_rready : Out std_logic;
-- AXI Read data READY output
-- MM2S DRE Control -------------------------------------------
mm2s_dre_new_align : Out std_logic;
-- Active high signal indicating new DRE aligment required
mm2s_dre_use_autodest : Out std_logic;
-- Active high signal indicating to the DRE to use an auto-
-- calculated desination alignment based on the last transfer
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0);
-- Bit field indicating the byte lane of the first valid data byte
-- being sent to the DRE
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0);
-- Bit field indicating the desired byte lane of the first valid data byte
-- to be output by the DRE
mm2s_dre_flush : Out std_logic;
-- Active high signal indicating to the DRE to flush the current
-- contents to the output register in preparation of a new alignment
-- that will be comming on the next transfer input
-- AXI Master Stream ------------------------------------------
mm2s_strm_wvalid : Out std_logic;
-- AXI Stream VALID Output
mm2s_strm_wready : In Std_logic;
-- AXI Stream READY input
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0);
-- AXI Stream data output
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- AXI Stream STRB output
mm2s_strm_wlast : Out std_logic;
-- AXI Stream LAST output
-- Command Calculator Interface --------------------------
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- The next command tag
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0);
-- The next command start address LSbs to use for the read data
-- mux (only used if Stream data width is 8 or 16 bits).
mstr2data_len : In std_logic_vector(7 downto 0);
-- The LEN value output to the Address Channel
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- The starting strobe value to use for the first stream data beat
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- The endiing (LAST) strobe value to use for the last stream
-- data beat
mstr2data_drr : In std_logic;
-- The starting tranfer of a sequence of transfers
mstr2data_eof : In std_logic;
-- The endiing tranfer of a sequence of transfers
mstr2data_sequential : In std_logic;
-- The next sequential tranfer of a sequence of transfers
-- spawned from a single parent command
mstr2data_calc_error : In std_logic;
-- Indication if the next command in the calculation pipe
-- has a calculation error
mstr2data_cmd_cmplt : In std_logic;
-- The indication to the Data Channel that the current
-- sub-command output is the last one compiled from the
-- parent command pulled from the Command FIFO
mstr2data_cmd_valid : In std_logic;
-- The next command valid indication to the Data Channel
-- Controller for the AXI MMap
data2mstr_cmd_ready : Out std_logic ;
-- Indication from the Data Channel Controller that the
-- command is being accepted on the AXI Address Channel
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0);
-- The source (input) alignment for the DRE
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0);
-- The destinstion (output) alignment for the DRE
-- Address Controller Interface --------------------------
addr2data_addr_posted : In std_logic ;
-- Indication from the Address Channel Controller to the
-- Data Controller that an address has been posted to the
-- AXI Address Channel
-- Data Controller General Halted Status
data2all_dcntlr_halted : Out std_logic;
-- When asserted, this indicates the data controller has satisfied
-- all pending transfers queued by the Address Controller and is halted.
-- Output Stream Skid Buffer Halt control
data2skid_halt : Out std_logic;
-- The data controller asserts this output for 1 primary clock period
-- The pulse commands the MM2S Stream skid buffer to tun off outputs
-- at the next tlast transmission.
-- Read Status Controller Interface --------------------------
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- The propagated command tag from the Command Calculator
data2rsc_calc_err : Out std_logic ;
-- Indication that the current command out from the Cntl FIFO
-- has a propagated calculation error from the Command Calculator
data2rsc_okay : Out std_logic ;
-- Indication that the AXI Read transfer completed with OK status
data2rsc_decerr : Out std_logic ;
-- Indication that the AXI Read transfer completed with decode error status
data2rsc_slverr : Out std_logic ;
-- Indication that the AXI Read transfer completed with slave error status
data2rsc_cmd_cmplt : Out std_logic ;
-- Indication by the Data Channel Controller that the
-- corresponding status is the last status for a parent command
-- pulled from the command FIFO
rsc2data_ready : in std_logic;
-- Handshake bit from the Read Status Controller Module indicating
-- that the it is ready to accept a new Read status transfer
data2rsc_valid : Out std_logic ;
-- Handshake bit output to the Read Status Controller Module
-- indicating that the Data Controller has valid tag and status
-- indicators to transfer
rsc2mstr_halt_pipe : In std_logic
-- Status Flag indicating the Status Controller needs to stall the command
-- execution pipe due to a Status flow issue or internal error. Generally
-- this will occur if the Status FIFO is not being serviced fast enough to
-- keep ahead of the command execution.
);
end entity axi_master_burst_rddata_cntl;
architecture implementation of axi_master_burst_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
-- coverage off
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
mm2s_rready <= sig_data2mmap_ready;
sig_mmap2data_valid <= mm2s_rvalid ;
sig_mmap2data_last <= mm2s_rlast and
mm2s_rvalid ;--Added to FIX CR#688186 -- 19-11-2012
-- Read Status Block interface
data2rsc_valid <= sig_coelsc_reg_full ;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
data2rsc_cmd_cmplt <= sig_coelsc_cmd_cmplt_reg ;
-- AXI MM2S Stream Channel Port assignments
mm2s_strm_wvalid <= (mm2s_rvalid and
sig_advance_pipe) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error
mm2s_strm_wlast <= (mm2s_rlast and
mm2s_rvalid and --Added to FIX CR#688186 -- 19-11-2012
sig_next_eof_reg) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error;
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1')
When (sig_halt_reg = '1') -- Force tstrb high on a Halt
else sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Read Transfer Completed Status output
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
-- Internal logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RD_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a read data
-- transfer has completed. This is an echo of a rlast assertion
-- and a qualified data beat on the AXI4 Read Data Channel
-- inputs.
--
-------------------------------------------------------------
IMP_RD_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_rd_xfer_cmplt <= '0';
else
sig_rd_xfer_cmplt <= sig_mmap2data_last and
sig_good_mmap_dbeat;
end if;
end if;
end process IMP_RD_CMPLT_FLAG;
-- General flag for advancing the MMap Read and the Stream
-- data pipelines
sig_advance_pipe <= sig_addr_chan_rdy and
sig_dqual_rdy and
not(sig_coelsc_reg_full) and -- new status back-pressure term
not(sig_calc_error_reg);
-- test for Kevin's status throttle case
sig_data2mmap_ready <= (mm2s_strm_wready or
sig_halt_reg) and -- Ignore the Stream ready on a Halt request
sig_advance_pipe;
sig_good_mmap_dbeat <= sig_data2mmap_ready and
sig_mmap2data_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_mmap2data_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
------------------------------------------------------------
-- Instance: I_READ_MUX
--
-- Description:
-- Instance of the MM2S Read Data Channel Read Mux
--
------------------------------------------------------------
I_READ_MUX : entity axi_master_burst_v2_0.axi_master_burst_rdmux
generic map (
C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH, -- : Integer range 1 to 32 := 5;
C_MMAP_DWIDTH => C_MMAP_DWIDTH , -- : Integer range 32 to 256 := 32;
C_STREAM_DWIDTH => C_STREAM_DWIDTH -- : Integer range 8 to 256 := 32
)
port map (
mmap_read_data_in => mm2s_rdata , -- : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0);
mux_data_out => mm2s_strm_wdata , -- : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0);
mstr2data_saddr_lsb => sig_addr_lsb_reg -- : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0)
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an incoming read data channel
-- has been received. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
mstr2data_dre_src_align &
mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_SRC_STRT_INDEX);
sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_DEST_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_master_burst_v2_0.axi_master_burst_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
-- Flag indicating that there are no posted commands to AXI
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0';
sig_next_cmd_cmplt_reg <= '0';
sig_next_sequential_reg <= '0';
sig_next_calc_error_reg <= '0';
sig_next_dre_src_align_reg <= (others => '0');
sig_next_dre_dest_align_reg <= (others => '0');
sig_dqual_reg_empty <= '1';
sig_dqual_reg_full <= '0';
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Read Data Mux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1' and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
----- Address posted Counter logic --------------------------------
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a register for the Address
-- Posted FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detirmination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
else
null; -- hols current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds and
(sig_calc_error_reg or
rst2data_stop_request);
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
--
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------ Read Response Status Logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_NEW_CMD_PULSE
--
-- Process Description:
-- Generate a 1 Clock wide pulse when a new command has been
-- loaded into the Command Register
--
-------------------------------------------------------------
LD_NEW_CMD_PULSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_ld_new_cmd_reg <= '1';
else
null; -- hold State
end if;
end if;
end process LD_NEW_CMD_PULSE;
sig_pop_coelsc_reg <= sig_coelsc_reg_full and
sig_rsc2data_ready ;
sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
not(sig_coelsc_reg_full)) or
(sig_ld_new_cmd_reg and
sig_calc_error_reg) ;
sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
sig_calc_error_reg;
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When mm2s_rresp = DECERR
Else '0';
sig_slverr <= '1'
When mm2s_rresp = SLVERR
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: RD_RESP_COELESC_REG
--
-- Process Description:
-- Implement the Read error/status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status Controller.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_cmd_cmplt_reg <= '0';
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_interr_reg <= sig_calc_error_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr or
sig_calc_error_reg );
sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DRE
--
-- If Generate Description:
-- Ties off DRE Control signals to logic low when DRE is
-- omitted from the MM2S functionality.
--
--
------------------------------------------------------------
GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
begin
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
end generate GEN_NO_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE_CNTLS
--
-- If Generate Description:
-- Implements the DRE Control logic when MM2S DRE is enabled.
--
-- - The DRE needs to have forced alignment at a SOF assertion
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
-- local signals
signal lsig_s_h_dre_autodest : std_logic := '0';
signal lsig_s_h_dre_new_align : std_logic := '0';
begin
mm2s_dre_new_align <= lsig_s_h_dre_new_align;
-- Autodest is asserted on a new parent command and the
-- previous parent command was not delimited with a EOF
mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
-- Assign the DRE Source and Destination Alignments
-- Only used when mm2s_dre_new_align is asserted
mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
-- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- asserted and the next transfer is not sequential and not the last
-- transfer of a packet.
mm2s_dre_flush <= mm2s_rlast and
mm2s_rvalid and --Added to FIX CR#688186 -- 19-11-2012
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_NEW_ALIGN
--
-- Process Description:
-- Generates the new alignment command flag to the DRE.
--
-------------------------------------------------------------
IMP_S_H_NEW_ALIGN : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_new_align <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_new_align <= '1';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_new_align <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_NEW_ALIGN;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_AUTODEST
--
-- Process Description:
-- Generates the control for the DRE indicating whether the
-- DRE destination alignment should be derived from the write
-- strobe stat of the last completed data-beat to the AXI
-- stream output.
--
-------------------------------------------------------------
IMP_S_H_AUTODEST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_autodest <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_autodest <= '0';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (lsig_s_h_dre_new_align = '1' and
sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_autodest <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_AUTODEST;
end generate GEN_INCLUDE_DRE_CNTLS;
------- Soft Shutdown Logic -------------------------------
-- Assign the output port skid buf control
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the output
-- stream skid buffer to shut down its outputs
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
-- coverage off
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
-- coverage on
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/924f3d25/hdl/common/shft_wrapper.vhd | 5 | 13889 | `protect begin_protected
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| apache-2.0 |
mkotormus/G3_OrchestraConductorDemo | src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/proc_common_v4_0/bb615326/hdl/src/vhdl/srl_fifo2.vhd | 15 | 14428 | -------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
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-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo2.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo2.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.all;
entity srl_fifo2 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo2;
architecture imp of srl_fifo2 is
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic;
-- I1 : in std_logic;
-- I2 : in std_logic;
-- I3 : in std_logic);
-- end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
| apache-2.0 |
Stederr/ESCOM | Arquitectura de Computadoras/Practica05_ArquitecturaGenericaFinal/generic0x.vhd | 1 | 3586 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity generic0x is
port(
clka:in std_logic;
codop0x: in std_logic_vector ( 3 downto 0 );
PortA0x: in std_logic_vector ( 7 downto 0 );
PortB0x: in std_logic_vector ( 7 downto 0 );
out0x: out std_logic_vector ( 7 downto 0 );
sinFlag0x: in std_logic ;
enable: in std_logic ;
en2: in std_logic ;
outFlag0x: out std_logic );
end;
architecture generic0 of generic0x is
signal sPortA0x , sPortB0x: std_logic_vector(7 downto 0);
begin
pgen0x : process (clka, enable, sinFlag0x)
variable aux: bit:='0';
begin
if (clka'event and clka = '1') then
if (sinFlag0x = '1' or enable ='0') then
sPortA0x <= PortA0x;
sPortB0x <= PortB0x;
outFlag0x <= '0';
elsif (enable = '1') then
case codop0x is
--xor
when "0000" =>
out0x <= sPortA0x xor sPortB0x;
outFlag0x <= '1';
--AND
when "0001" =>
out0x <= sPortA0x and sPortB0x;
outFlag0x <= '1';
--NAND
when "0010" =>
out0x <= not (sPortA0x and sPortB0x);
outFlag0x <= '1';
--NOR
when "0011" =>
out0x <= sPortA0x nor sPortB0x;
outFlag0x <= '1';
--or
when "0100" =>
out0x<= sPortA0x or sPortB0x;
outFlag0x <= '1';
--xnor
when "0101" =>
out0x <= sPortA0x xnor sPortB0x;
outFlag0x <= '1';
--not
when "0110" =>
out0x <= not(sPortA0x);
outFlag0x <= '1';
--com2
when "0111" =>
out0x <= not(sPortA0x) + 1;
outFlag0x <= '1';
--suma
when "1000" =>
out0x <= sPortA0x + sPortB0x;
outFlag0x <= '1';
--resta
when "1001" =>
out0x <= sPortA0x - sPortB0x;
outFlag0x <= '1';
--shiftr
when "1010" =>
if (aux = '0' and en2 = '0') then
aux:='1';
sPortA0x(7) <= '0';
sPortA0x(6 downto 0) <= sPortA0x(7 downto 1);
out0x <= sPortA0x;
outFlag0x <= '1';
elsif (en2 = '1') then
aux:='0';
end if;
--shiftl
when "1011" =>
sPortA0x(0) <= '0';
sPortA0x(7 downto 1) <= sPortA0x(6 downto 0);
out0x <= sPortA0x;
outFlag0x <= '1';
--rotr
when "1100" =>
sPortA0x(7) <= sPortA0x(0);
sPortA0x(6 downto 0) <= sPortA0x(7 downto 1);
out0x <= sPortA0x;
outFlag0x <= '1';
--rotl
when "1101" =>
sPortA0x(0) <= sPortA0x(7);
sPortA0x(7 downto 1) <= sPortA0x(6 downto 0);
out0x <= sPortA0x;
outFlag0x <= '1';
when "1110" =>
if (sPortA0x < sPortB0x) then
out0x <= "00000001";
elsif(sPortA0x = sPortB0x) then
out0x <= "00000010";
elsif(sPortA0x > sPortB0x) then
out0x <= "00000100";
end if;
outFlag0x <= '1';
when others => NULL;
end case;
else
out0x <= (others => 'Z');
outFlag0x <= 'Z';
end if;
end if;
end process pgen0x;
end generic0;
| apache-2.0 |
Stederr/ESCOM | Arquitectura de Computadoras/Practica02_SumadorRestador4Bits/or.vhd | 1 | 371 | library ieee;
use ieee.std_logic_1164.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
-- Entidad
entity eww is
port(
entrada1_or: in std_logic;
entrada2_or: in std_logic;
salida_or: out std_logic);
end;
-- Arquitectura
architecture aww of eww is
begin
salida_or <= entrada1_or OR entrada2_or;
end aww;
| apache-2.0 |
Stederr/ESCOM | Arquitectura de Computadoras/Practica06_SumadorRestador8Bits/topfa00txt.vhd | 1 | 806 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use packagefa00.all;
entity topfa00 is
port(
C00: in std_logic ;
A00: in std_logic ;
B00: in std_logic ;
S00: out std_logic ;
C01: out std_logic );
end;
architecture topfa0 of topfa00 is
signal Sint1, Cint1, Cint2: std_logic;
begin
U00: topha00 port map(A0 => A00,
B0 => B00,
S0 => Sint1,
C0 => Cint1);
U01: topha00 port map(A0 => C00,
B0 => Sint1,
S0 => S00,
C0 => Cint2);
U02: or00 port map(Ao => Cint2,
Bo => Cint1,
Yo => C01);
end topfa0;
| apache-2.0 |
Stederr/ESCOM | Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/package8bita00.vhd | 1 | 780 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package package8bita00 is
component xora00
port (Ax: in std_logic;
Bx: in std_logic;
Yx: out std_logic);
end component;
component topfaa00
port (A00: in std_logic;
B00: in std_logic;
C00: in std_logic;
C01: out std_logic;
S00: out std_logic);
end component;
component xnora00
port (Anx: in std_logic;
Bnx: in std_logic;
Ynx: out std_logic);
end component;
component anda00
port (Aa: in std_logic;
Ba: in std_logic;
Ya: out std_logic);
end component;
end package8bita00;
| apache-2.0 |
Stederr/ESCOM | Arquitectura de Computadoras/Practica02_Semisumador4Bits/top_sumadormedio.vhd | 1 | 903 | library ieee;
use ieee.std_logic_1164.all;
use pack_sum_medio.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
-- Entidad
entity eTopSumMedio is
port(
entrada1_tsm: in std_logic;
entrada2_tsm: in std_logic;
resultado_tsm: out std_logic;
acarreo_tsm: out std_logic);
attribute loc: string;
attribute loc of entrada1_tsm: signal is "p125";
attribute loc of entrada2_tsm: signal is "p124";
attribute loc of resultado_tsm: signal is "p4";
attribute loc of acarreo_tsm: signal is "p5";
end;
-- Arquitectura
architecture aTopSumMedio of eTopSumMedio is
begin
U1: eAnd port map(
entrada1_and => entrada1_tsm,
entrada2_and => entrada2_tsm,
salida_and => acarreo_tsm);
U2: eXor port map(
entrada1_xor => entrada1_tsm,
entrada2_xor => entrada2_tsm,
salida_xor => resultado_tsm);
end aTopSumMedio;
| apache-2.0 |
Stederr/ESCOM | Arquitectura de Computadoras/Practica06_SumadorRestador8Bits/nxor00txt.vhd | 1 | 299 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nxor00 is
port(
Anx: in std_logic ;
Bnx: in std_logic ;
Ynx: out std_logic );
end;
architecture nxor0 of nxor00 is
begin
Ynx <= not(Anx xor Bnx);
end nxor0;
| apache-2.0 |
Stederr/ESCOM | Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/uc00.vhd | 1 | 2121 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity uc00 is
port(
clkuc: in std_logic ;
inFlaguc: in std_logic ;
inFlaguc2: in std_logic ;
enable: in std_logic ;
inuc: in std_logic_vector ( 7 downto 0 );
outuc: out std_logic_vector ( 7 downto 0 );
outFlaguc: out std_logic );
end;
architecture uc0 of uc00 is
begin
puc: process(clkuc, enable, inuc)
begin
if(clkuc = '1' and enable = '1') then
outFlaguc <= '1';
outuc <= inuc;
else
outFlaguc <= '0';
outuc <= (others => '0');
end if;
end process puc;
--puc: process(clkuc, inFlaguc, enable)
-- begin
-- if (clkuc'event and clkuc = '1') then
-- if (inFlaguc = '0' and inFlaguc2 = '0') then
-- if (enable = '1') then
-- outuc <= inuc;
-- outFlaguc <= '1';
-- else
-- outuc <= (others => 'Z');
-- outFlaguc <= 'Z';
-- end if;
-- elsif (inFlaguc = '0' and inFlaguc2 = '1') then
-- if (enable = '1') then
-- outuc <= (others => 'Z');
-- outFlaguc <= 'Z';
-- else
-- outuc <= (others => 'Z');
-- outFlaguc <= 'Z';
-- end if;
-- elsif (inFlaguc = '1' and inFlaguc2 = '0') then
-- if (enable = '1') then
-- outuc <= inuc;
-- outFlaguc <= '1';
-- else
-- outuc <= (others => 'Z');
-- outFlaguc <= 'Z';
-- end if;
-- elsif (inFlaguc = '1' and inFlaguc2 = '1') then
-- if (enable = '1') then
-- outuc <= (others => 'Z');
-- outFlaguc <= 'Z';
-- else
-- outuc <= (others => 'Z');
-- outFlaguc <= 'Z';
-- end if;
-- end if;
-- end if;
-- end process puc;
end uc0;
| apache-2.0 |
Stederr/ESCOM | Arquitectura de Computadoras/Practica02_SumadorRestador4Bits/top_sumador.vhd | 1 | 2704 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use pack_sum.all;
-- IPN - ESCOM
-- Arquitectura de Computadoras
-- ww ww ww - 3CM9
-- ww.com/arquitectura
-- Entidad
entity eTopSum is
port(
carry: in std_logic;
entradas1: in std_logic_vector(3 downto 0);
entradas2: in std_logic_vector(3 downto 0);
salidas: out std_logic_vector(3 downto 0);
overflow: out std_logic);
attribute loc: string;
attribute loc of carry: signal is "p104";
attribute loc of entradas1: signal is "p125, p124, p123, p122";
attribute loc of entradas2: signal is "p121, p120, p117, p110";
attribute loc of salidas: signal is "p21, p22, p23, p24";
attribute loc of overflow: signal is "p12";
end;
-- Arquitectura
architecture aTopSum of eTopSum is
signal sb, cs, sa: std_logic_vector(3 downto 0);
signal sao: std_logic;
begin
U6: eXor port map(
entrada1_xor => carry,
entrada2_xor => entradas2(0),
salida_xor => sb(0));
U7: eXor port map(
entrada1_xor => carry,
entrada2_xor => entradas2(1),
salida_xor => sb(1));
U8: eXor port map(
entrada1_xor => carry,
entrada2_xor => entradas2(2),
salida_xor => sb(2));
U9: eXor port map(
entrada1_xor => carry,
entrada2_xor => entradas2(3),
salida_xor => sb(3));
U10: eTopSumCompleto port map(
acarreoI_tsc => carry,
entrada1_tsc => entradas1(0),
entrada2_tsc => sb(0),
acarreoO_tsc => cs(0),
resultado_tsc => sa(0));
U11: eTopSumCompleto port map(
acarreoI_tsc => cs(0),
entrada1_tsc => entradas1(1),
entrada2_tsc => sb(1),
acarreoO_tsc => cs(1),
resultado_tsc => sa(1));
U12: eTopSumCompleto port map(
acarreoI_tsc => cs(1),
entrada1_tsc => entradas1(2),
entrada2_tsc => sb(2),
acarreoO_tsc => cs(2),
resultado_tsc => sa(2));
U13: eTopSumCompleto port map(
acarreoI_tsc => cs(2),
entrada1_tsc => entradas1(3),
entrada2_tsc => sb(3),
acarreoO_tsc => cs(3),
resultado_tsc => sa(3));
U14: eAnd port map(
entrada1_and => sao,
entrada2_and => sa(0),
salida_and => salidas(0));
U15: eAnd port map(
entrada1_and => sao,
entrada2_and => sa(1),
salida_and => salidas(1));
U16: eAnd port map(
entrada1_and => sao,
entrada2_and => sa(2),
salida_and => salidas(2));
U17: eAnd port map(
entrada1_and => sao,
entrada2_and => sa(3),
salida_and => salidas(3));
U18: eXnor port map(
entrada1_xnor => cs(3),
entrada2_xnor => cs(2),
salida_xnor => sao);
U19: eXor port map(
entrada1_xor => cs(3),
entrada2_xor => cs(2),
salida_xor => overflow);
end aTopSum;
| apache-2.0 |
Stederr/ESCOM | Arquitectura de Computadoras/Practica05_ArquitecturaGenericaMultiAportes/not00.vhd | 1 | 1278 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity not00 is
port(
clkn: in std_logic ;
codopn: in std_logic_vector ( 3 downto 0 );
inFlagn: in std_logic;
portAn: in std_logic_vector ( 7 downto 0 );
outn: out std_logic_vector ( 7 downto 0 );
outFlagn: out std_logic );
end;
architecture not0 of not00 is
begin
pnot: process(codopn, portAn)
begin
if(codopn = "0011") then
outn <= not portAn;
outFlagn <= '1';
else
outn <= (others => 'Z');
outFlagn <= 'Z';
end if;
end process pnot;
-- pnot: process(clkn, codopn, inFlagn)
-- --variable auxn: bit:='0';
-- begin
-- if (clkn = '1') then
----clkn'event and
-- if (codopn = "0011") then
-- --if (inFlagn = '1') then
-- --if (auxn = '0') then
-- --auxn:= '1';
-- outn <= not(portAn);
-- outFlagn <= '1';
-- --end if;
-- --else
-- --outFlagn <= '0';
-- --end if;
-- else
-- outn <= (others => 'Z');
-- outFlagn <= 'Z';
-- --auxn:='0';
-- end if;
-- end if;
-- end process pnot;
end not0;
| apache-2.0 |
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