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// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:46 12/20/2010
// Design Name:
// Module Name: clk_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
/*!
* <b>Module:</b>ahci_fsm
* @file ahci_fsm.v
* @date 2016-01-10
* @author Andrey Filippov
*
* @brief AHCI host+port0 state machine
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_fsm.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ahci_fsm.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*/
`timescale 1ns/1ps
module ahci_fsm
/*#(
// parameter PREFETCH_ALWAYS = 0,
parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen
// parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen
parameter ADDRESS_BITS = 10 // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
) */
(
input hba_rst, // @posedge mclk
input mclk, // for command/status
input was_hba_rst, // last reset was hba reset (not counting system reset)
input was_port_rst, // last reset was port reset
// Writing FSM program memory
input aclk,
input arst,
input [17:0] pgm_ad, // @aclk, address/data to program the AHCI FSM
input pgm_wa, // @aclk, address strobe to program the AHCI FSM
input pgm_wd, // @aclk, data strobe to program the AHCI FSM
// direct communication with transposrt, link and phy layers
input [1:0] phy_ready, // goes up after comreset,cominit, align, ..., showing speed
output syncesc_send, // Send sync escape
input syncesc_send_done, // "SYNC escape until the interface is quiescent..."
output comreset_send, // Not possible yet?
input cominit_got, // asynchronously jumps to P:Cominit state
output set_offline, // electrically idle
// input x_rdy_collision, // X_RDY/X_RDY collision on interface
output send_R_OK, // Should it be originated in this layer SM?
output send_R_ERR,
// Other signals....
// Communication with ahci_ctrl_stat (some are not needed)
// update register inputs (will write to register memory current value of the corresponding register)
output pfsm_started, // H: FSM done, P: FSM started (enable sensing pcmd_st_cleared)
// update register inputs (will write to register memory current value of the corresponding register)
// Removing - such updates are always done when startimng new state
/// input update_pending,
output update_all, // =fsm_jump[0]
input update_busy, // valid same cycle as update_all
// output update_gis, // these following individual may be unneeded - just use universal update_all
// output update_pis,
// output update_ssts,
// output update_serr,
// output update_pcmd,
// output update_pci,
/// input st01_pending, // software turned PxCMD.ST from 0 to 1 - detected in the loop
/// input st10_pending, // software turned PxCMD.ST from 1 to 0 - generates port reset
/// output st_pending_reset,// reset both st01_pending and st10_pending
// PxCMD
/// output pcmd_clear_icc, // clear PxCMD.ICC field
/// output pcmd_esp, // external SATA port (just forward value)
/// input pcmd_cr, // command list run - current
output pcmd_cr_set, // command list run set
output pcmd_cr_reset, // command list run reset
// output pcmd_fr, // ahci_fis_receive:get_fis_busy
/// output pcmd_clear_bsy_drq, // == ahci_fis_receive:clear_bsy_drq
// Command List override, not yet implemented (optional), keeping @SuppressWarnings VEditor
input pcmd_clo, //RW1, causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit
/// output pcmd_clear_st, // RW clear ST (start) bit Seems it is software controlled only
input pcmd_st, // current value
input pcmd_st_cleared,// ST bit cleared by software;
//clear_bsy_drq
// Interrupt inputs
output sirq_TFE, // RWC: Task File Error Status
output sirq_IF, // RWC: Interface Fatal Error Status (sect. 6.1.2)
output sirq_INF, // RWC: Interface Non-Fatal Error Status (sect. 6.1.2)
output sirq_OF, // RWC: Overflow Status
output sirq_PRC, // RO: PhyRdy changed Status
output sirq_PC, // RO: Port Connect Change Status
output sirq_DP, // RWC: Descriptor Processed with "I" bit on
output sirq_UF, // RO: Unknown FIS
output sirq_SDB, // RWC: Set Device Bits Interrupt - Set Device bits FIS with 'I' bit set
output sirq_DS, // RWC: DMA Setup FIS Interrupt - DMA Setup FIS received with 'I' bit set
output sirq_PS, // RWC: PIO Setup FIS Interrupt - PIO Setup FIS received with 'I' bit set
output sirq_DHR, // RWC: D2H Register FIS Interrupt - D2H Register FIS received with 'I' bit set
// SCR1:SError (only inputs that are not available in sirq_* ones
//sirq_PC,
//sirq_UF
// 5.3.2.3 P:NotRunning.8 - can not be implemented now, keeping @SuppressWarnings VEditor
input serr_diag_X, // value of PxSERR.DIAG.X
// SCR0: SStatus
output ssts_ipm_dnp, // device not present or communication not established
output ssts_ipm_active, // device in active state
output ssts_ipm_part, // device in partial state
output ssts_ipm_slumb, // device in slumber state
output ssts_ipm_devsleep, // device in DevSleep state
output ssts_spd_dnp, // device not present or communication not established
output ssts_spd_gen1, // Gen 1 rate negotiated
output ssts_spd_gen2, // Gen 2 rate negotiated
output ssts_spd_gen3, // Gen 3 rate negotiated
output ssts_det_ndnp, // no device detected, phy communication not established
output ssts_det_dnp, // device detected, but phy communication not established
output ssts_det_dp, // device detected, phy communication established
output ssts_det_offline, // device detected, phy communication established
input [3:0] ssts_det, // current value of PxSSTS.DET
// SCR2:SControl (written by software only)
/// input [3:0] sctl_ipm, // Interface power management transitions allowed
/// input [3:0] sctl_spd, // Interface maximal speed
input [3:0] sctl_det, // Device detection initialization requested
input sctl_det_changed, // Software had written new value to sctl_det
output sctl_det_reset, // clear sctl_det_changed
output hba_rst_done, // reset GHC.HR and other bits
output pxci0_clear, // PxCI clear
input pxci0, // pxCI current value
// inputs from the DMA engine
/// input dma_prd_done, // output (finished next prd)
output dma_prd_irq_clear, // reset pending prd_irq
input dma_prd_irq_pend, // prd interrupt pending. This is just a condition for irq - actual will be generated after FIS OK
input dma_cmd_busy, // output reg (DMA engine is processing PRDs)
/// input dma_cmd_done, // output (last PRD is over)
output dma_cmd_abort, // try to abort a command
input dma_abort_done, // if abort is not needed, will generate dma_abort_done just next cycle
// Communication with ahci_fis_receive (some are unused)
// Debug features
input fis_first_invalid, // Some data available from FIFO, but not FIS head
output fis_first_flush, // Skip FIFO data until empty or FIS head
input fis_first_vld, // fis_first contains valid FIS header, reset by 'get_*'
input [7:0] fis_type, // FIS type (low byte in the first FIS DWORD), valid with 'fis_first_vld'
input [7:0] bist_bits, // bits that define built-in self test
// Receiving FIS
output get_dsfis,
output get_psfis,
output get_rfis,
output get_sdbfis,
output get_ufis,
output get_data_fis,
output get_ignore, // ignore whatever FIS (use for DMA activate too?)
// input get_fis_busy, // busy processing FIS
input get_fis_done, // done processing FIS (see fis_ok, fis_err, fis_ferr)
input fis_ok, // FIS done, checksum OK reset by starting a new get FIS
input fis_err, // FIS done, checksum ERROR reset by starting a new get FIS
input fis_ferr, // FIS done, fatal error - FIS too long
input fis_extra, // more data got from FIS than DMA can accept. Does not deny fis_ok. May have latency
output set_update_sig, // when set, enables get_sig (and resets itself)
/// input pUpdateSig, // state variable
/// input sig_available, // device signature available
output update_sig, // update signature
// next commands use register address/data/we for 1 clock cycle - after next to command (commnd - t0, we - t2)
output update_err_sts,// update PxTFD.STS and PxTFD.ERR from the last received regs d2h
output update_pio, // update PxTFD.STS and PxTFD.ERR from pio_* (entry PIO:Update)
output update_prdbc, // update PRDBC in registers
output clear_bsy_drq, // clear PxTFD.STS.BSY and PxTFD.STS.DRQ, update
output clear_bsy_set_drq, // clear PxTFD.STS.BSY and sets PxTFD.STS.DRQ, update
output set_bsy, // set PxTFD.STS.BSY, update
output set_sts_7f, // set PxTFD.STS = 0x7f, update
output set_sts_80, // set PxTFD.STS = 0x80 (may be combined with set_sts_7f), update
output clear_xfer_cntr, // clear pXferCntr (is it needed as a separate input)?
output decr_dwcr, // decrement DMA Xfer counter after read // need pulse to 'update_prdbc' to write to registers
output decr_dwcw, // decrement DMA Xfer counter after write // need pulse to 'update_prdbc' to write to registers
// output [11:0] decr_DXC_dw, // decrement value (in DWORDs)
input pxcmd_fre, // control bit enables saving FIS to memory
input pPioXfer, // state variable
input [7:0] tfd_sts, // Current PxTFD status field (updated after regFIS and SDB - certain fields)
// tfd_sts[7] - BSY, tfd_sts[3] - DRQ, tfd_sts[0] - ERR
/// input [7:0] tfd_err, // Current PxTFD error field (updated after regFIS and SDB)
input fis_i, // value of "I" field in received regsD2H or SDB FIS
/// input sdb_n, // value of "N" field in received SDB FIS
input dma_a, // value of "A" field in received DMA Setup FIS
/// input dma_d, // value of "D" field in received DMA Setup FIS
input pio_i, // value of "I" field in received PIO Setup FIS
input pio_d, // value of "D" field in received PIO Setup FIS
/// input [7:0] pio_es, // value of PIO E_Status
/// input sactive0, // bit 0 of sActive DWORD received in SDB FIS
// Using even word count (will be rounded up), partial DWORD (last) will be handled by PRD length if needed
/// input [31:2] xfer_cntr, // transfer counter in words for both DMA (31 bit) and PIO (lower 15 bits), updated after decr_dwc
input xfer_cntr_zero,// valid next cycle
// Communication with ahci_fis_transmit
// Command pulses to execute states
output fetch_cmd, // Enter p:FetchCmd, fetch command header (from the register memory, prefetch command FIS)
// wait for either fetch_cmd_busy == 0 or pCmdToIssue ==1 after fetch_cmd
output cfis_xmit, // transmit command (wait for dma_ct_busy == 0)
output dx_xmit, // send FIS header DWORD, (just 0x46), then forward DMA data
// transmit until error, 2048DWords or pDmaXferCnt
output atapi_xmit, // tarsmit ATAPI command FIS
input xmit_done,
// input xmit_busy,
output clearCmdToIssue, // From CFIS:SUCCESS
input pCmdToIssue, // AHCI port variable
// output dmaCntrZero, // DMA counter is zero - would be a duplicate to the one in receive module and dwords_sent output
// input syncesc_recv, // These two inputs interrupt transmit
// input xmit_err, //
input [ 2:0] dx_err, // bit 0 - syncesc_recv, 1 - R_ERR (was xmit_err), 2 - X_RDY/X_RDY collision (valid @ xmit_err and later, reset by new command)
/// input [15:0] ch_prdtl, // Physical region descriptor table length (in entries, 0 is 0)
input ch_c, // Clear busy upon R_OK for this FIS
input ch_b, // Built-in self test command
input ch_r, // reset - may need to send SYNC escape before this command
input ch_p, // prefetchable - only used with non-zero PRDTL or ATAPI bit set
input ch_w, // Write: system memory -> device
input ch_a, // ATAPI: 1 means device should send PIO setup FIS for ATAPI command
input unsolicited_en, // enable processing of cominit_got and PxERR.DIAG.W interrupts from
// this bit is reset at reset, set when PxSSTS.DET==3 or PxSCTL.DET==4
output reg [ 9:0] last_jump_addr // debug feature
/// input [4:0] ch_cfl, // length of the command FIS in DW, 0 means none. 0 and 1 - illegal,
// maximal is 16 (0x10)
/// input [11:0] dwords_sent // number of DWORDs transmitted (up to 2048)
);
`include "includes/ahci_localparams.vh" // @SuppressThisWarning VEditor : Unused localparams
`include "includes/fis_types.vh" // @SuppressThisWarning VEditor : Some localparams unused
// Reset addresses - later use generated
localparam LABEL_POR = 11'h000;
localparam LABEL_HBA_RST = 11'h002;
localparam LABEL_PORT_RST = 11'h004;
localparam LABEL_COMINIT = 11'h006;
localparam LABEL_ST_CLEARED = 11'h008;
wire tfd_bsy = tfd_sts[7];
wire tfd_drq = tfd_sts[3];
wire tfd_sts_err = tfd_sts[0];
reg [ 9:0] pgm_waddr;
// wire pgm_ren;
// wire pgm_regen;
wire cond_met_w; // calculated from signals and program conditions decoder
reg [ 9:0] pgm_jump_addr;
reg [ 9:0] pgm_addr;
wire [17:0] pgm_data;
reg was_rst;
// reg jump_r;
reg [2:0] fsm_jump;
wire fsm_next;
// reg fsm_next_r;
reg fsm_actions; // processing actions
reg dis_actions; // disable actions during async jump
reg fsm_act_busy;
reg [1:0] fsm_transitions; // processing transitions
reg fsm_preload; // read first sequence data (2 cycles for regen)
// wire [7:0] precond_w = pgm_data[17:10]; // select what to use - cond_met_w valis after precond_w, same time as conditions
// reg [7:0] conditions;
// wire pre_jump_w = (|async_pend_r) ? async_ackn : |(cond_met_w & fsm_transitions[1]);
wire pre_jump_w = (|async_pend_r) ? async_ackn : (cond_met_w & fsm_transitions[1]);
wire fsm_act_done_w = get_fis_done ||
xmit_done ||
(syncesc_send_pend && syncesc_send_done) ||
dma_abort_done ||
asynq_rq; // cominit_got || pcmd_st_cleared
reg fsm_act_done; // made later by 1 cycle so the new conditions are latched // TODO:check is enough ? Adding 1 extra
reg fsm_act_pre_done;
wire fsm_wait_act_w = pgm_data[16]; // this action requires waiting for done
wire fsm_last_act_w = pgm_data[17];
wire fsm_pre_act_w = !dis_actions && fsm_actions && fsm_next; // use it as CS for generated actions (registered)
reg [1:0] async_pend_r; // waiting to process cominit_got
reg async_from_st; // change to multi-bit if there will be more sources for async transitions
// wire asynq_rq = (cominit_got && unsolicited_cominit_en) || pcmd_st_cleared;
wire asynq_rq = (cominit_got && unsolicited_en) || pcmd_st_cleared;
// OK to wait for some time fsm_act_busy is supposed to never hang up
wire async_ackn = !fsm_preload && async_pend_r[0] && ((fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]); // OK to process async jump
// reg x_rdy_collision_pend;
reg syncesc_send_pend; // waiting for 'syncesc_send' confiramtion 'syncesc_send_done'
reg [1:0] phy_ready_prev; // previous state of phy_ready / speed
reg phy_ready_chng_r; // pulse when phy_ready changes
wire phy_ready_chng_w = !hba_rst && !was_rst && (phy_ready != phy_ready_prev);
reg was_last_action_r; // delay last action if it was fsm_wait_act;
wire fsm_transitions_w = // next will be transitions processing
(fsm_last_act_w && fsm_actions && fsm_next && !fsm_wait_act_w) ||
(fsm_act_busy && fsm_act_done && was_last_action_r);
wire conditions_ce = // copy all conditions to the register so they will not change while iterating through them
!fsm_transitions_w && !fsm_transitions[0];
// reg unsolicited_cominit_en; // allow unsolicited COMINITs
// wire en_cominit; // en_cominit
// New variable:
reg pisn32; // pIssueSlot != 32
wire clear_pisn32; // additional clear when in P:NotRunning state
assign fsm_next = (fsm_preload || (fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]) && !async_pend_r[0]; // quiet if received cominit is pending
assign update_all = fsm_jump[0];
assign ssts_ipm_dnp = phy_ready_chng_r && (phy_ready_prev == 0); // device not present or communication not established
assign ssts_ipm_active = phy_ready_chng_r && (phy_ready_prev != 0); // device in active state
assign ssts_ipm_part = 0; // device in partial state
assign ssts_ipm_slumb = 0; // device in slumber state
assign ssts_ipm_devsleep = 0; // device in DevSleep state
assign ssts_spd_dnp = phy_ready_chng_r && (phy_ready_prev == 0); // device not present or communication not established
assign ssts_spd_gen1 = phy_ready_chng_r && (phy_ready_prev == 1); // Gen 1 rate negotiated
assign ssts_spd_gen2 = phy_ready_chng_r && (phy_ready_prev == 2); // Gen 2 rate negotiated
assign ssts_spd_gen3 = phy_ready_chng_r && (phy_ready_prev == 3); // Gen 3 rate negotiated
assign ssts_det_ndnp = phy_ready_chng_r && (phy_ready_prev == 0); // no device detected, phy communication not established
// assign ssts_det_dnp = 0; // device detected, but phy communication not established
assign ssts_det_dp = phy_ready_chng_r && (phy_ready_prev != 0); // device detected, phy communication established
assign sirq_OF = 0; // RWC: Overflow Status (buffer overrun - should not happen, add?)
assign sirq_PRC = phy_ready_chng_r; // RO: PhyRdy changed Status
// Writing to the FSM program memory
always @ (posedge aclk) begin
if (arst) pgm_waddr <= 0;
else if (pgm_wa) pgm_waddr <= pgm_ad[ 9:0];
else if (pgm_wd) pgm_waddr <= pgm_waddr + 1;
end
always @ (posedge mclk) begin
if (hba_rst || pxci0_clear || clear_pisn32) pisn32 <= 0;
else if (fetch_cmd) pisn32 <= 1;
end
always @ (posedge mclk) begin
/// if (hba_rst) unsolicited_cominit_en <= !was_port_rst;
// else if (en_cominit || comreset_send) unsolicited_cominit_en <= en_cominit;
if (hba_rst) pgm_jump_addr <= (was_hba_rst || was_port_rst) ? (was_hba_rst? LABEL_HBA_RST:LABEL_PORT_RST) : LABEL_POR;
// else if (async_pend_r[1]) pgm_jump_addr <= async_from_st? LABEL_ST_CLEARED : LABEL_COMINIT;
else if (async_pend_r[0]) pgm_jump_addr <= async_from_st? LABEL_ST_CLEARED : LABEL_COMINIT;
else if (fsm_transitions[0] && (!cond_met_w || !fsm_transitions[1])) pgm_jump_addr <= pgm_data[9:0];
was_rst <= hba_rst;
/// fsm_act_done <= fsm_act_done_w; // delay by 1 clock cycle
fsm_act_pre_done <= fsm_act_done_w; // delay by 1 clock cycle
fsm_act_done <= fsm_act_pre_done; // TODO - verify delay by 2 is needed to latch
fsm_jump <= {fsm_jump[1:0], pre_jump_w | (was_rst & ~hba_rst)};
if (fsm_jump[0]) pgm_addr <= pgm_jump_addr;
else if (fsm_next) pgm_addr <= pgm_addr + 1;
if (fsm_jump[0]) last_jump_addr <= pgm_jump_addr; // debug feature
// if (hba_rst) conditions <= 0;
// if (fsm_transitions[0]) conditions <= precond_w;
if (hba_rst) fsm_actions <= 0;
else if (fsm_jump[2]) fsm_actions <= 1;
else if (fsm_last_act_w && fsm_next) fsm_actions <= 0;
if (hba_rst) dis_actions <= 0;
else if (|async_pend_r) dis_actions <= 1;
else if (fsm_jump[2]) dis_actions <= 0;
if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w;
//// if (hba_rst || pre_jump_w) fsm_transitions <= 0;
/// 2016.12.07 jumps were not disabled after async transitions, they came from the previously executed code
if (hba_rst || pre_jump_w || dis_actions) fsm_transitions <= 0;
else if (fsm_transitions_w) fsm_transitions <= 1;
// else if ((fsm_last_act_w && fsm_actions && fsm_next && !fsm_wait_act_w) ||
// (fsm_act_busy && fsm_act_done && was_last_action_r) ) fsm_transitions <= 1;
else fsm_transitions <= {fsm_transitions[0],fsm_transitions[0]};
if (hba_rst) fsm_preload <= 0;
else fsm_preload <= |fsm_jump[1:0];
if (hba_rst) fsm_act_busy <= 0;
else if (fsm_pre_act_w) fsm_act_busy <= fsm_wait_act_w;
else if (fsm_act_done) fsm_act_busy <= 0;
if (hba_rst) async_from_st <= 0;
else if (pcmd_st_cleared) async_from_st <= 1;
else if (asynq_rq) async_from_st <= 0;
if (hba_rst) async_pend_r <= 0;
/// else async_pend_r <= {async_pend_r[0], asynq_rq | (async_pend_r[0] & ~async_ackn)};
else async_pend_r <= {async_pend_r[0], (asynq_rq | async_pend_r[0]) & ~async_ackn};
// if (hba_rst || pcmd_cr_set) x_rdy_collision_pend <= 0;
// else if (x_rdy_collision) x_rdy_collision_pend <= 1;
if (hba_rst || syncesc_send_done) syncesc_send_pend <= 0;
else if (syncesc_send) syncesc_send_pend <= 1;
if (was_rst && !hba_rst && !was_hba_rst && !was_port_rst) phy_ready_prev <= 0;
else if (phy_ready_chng_w) phy_ready_prev <= phy_ready;
phy_ready_chng_r <= phy_ready_chng_w;
end
ram18p_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(4),
.LOG2WIDTH_RD(4)
`include "includes/ahxi_fsm_code.vh"
) fsm_pgm_mem_i (
.rclk (mclk), // input
.raddr (pgm_addr), // input[10:0]
.ren (fsm_next), // input
.regen (fsm_next), // input
.data_out (pgm_data), // output[17:0]
.wclk (aclk), // input
.waddr (pgm_waddr), // input[10:0]
.we (pgm_wd), // input
.web (4'hf), // input[7:0]
.data_in (pgm_ad) // input[17:0]
);
action_decoder action_decoder_i (
.clk (mclk), // input
.enable (fsm_pre_act_w), // input
.data (pgm_data[10:0]), // input[10:0]
// CTRL_STAT
.PXSERR_DIAG_X (sirq_PC), // output reg
.SIRQ_DHR (sirq_DHR), // output reg
.SIRQ_DP (sirq_DP), // output reg
.SIRQ_DS (sirq_DS), // output reg
.SIRQ_IF (sirq_IF), // output reg
.SIRQ_INF (sirq_INF), // output reg
.SIRQ_PS (sirq_PS), // output reg
.SIRQ_SDB (sirq_SDB), // output reg
.SIRQ_TFE (sirq_TFE), // output reg
.SIRQ_UF (sirq_UF), // output reg
.PFSM_STARTED (pfsm_started), // output reg
.PCMD_CR_CLEAR (pcmd_cr_reset), // output reg
.PCMD_CR_SET (pcmd_cr_set), // output reg
.PXCI0_CLEAR (pxci0_clear), // output reg
.PXSSTS_DET_1 (ssts_det_dnp), // output reg
.SSTS_DET_OFFLINE (ssts_det_offline), // output reg
.SCTL_DET_CLEAR (sctl_det_reset), // output reg
.HBA_RST_DONE (hba_rst_done), // output reg
// FIS RECEIVE
.SET_UPDATE_SIG (set_update_sig), // output reg
.UPDATE_SIG (update_sig), // output reg
.UPDATE_ERR_STS (update_err_sts), // output reg
.UPDATE_PIO (update_pio), // output reg
.UPDATE_PRDBC (update_prdbc), // output reg
.CLEAR_BSY_DRQ (clear_bsy_drq), // output reg
.CLEAR_BSY_SET_DRQ (clear_bsy_set_drq), // output reg
.SET_BSY (set_bsy), // output reg
.SET_STS_7F (set_sts_7f), // output reg
.SET_STS_80 (set_sts_80), // output reg
.XFER_CNTR_CLEAR (clear_xfer_cntr), // output reg
.DECR_DWCR (decr_dwcr), // output reg
.DECR_DWCW (decr_dwcw), // output reg
.FIS_FIRST_FLUSH (fis_first_flush), // output reg
// FIS_TRANSMIT
.CLEAR_CMD_TO_ISSUE (clearCmdToIssue), // output reg
// DMA
.DMA_ABORT (dma_cmd_abort), // output reg
.DMA_PRD_IRQ_CLEAR (dma_prd_irq_clear), // output reg
// SATA TRANSPORT/LINK/PHY
.XMIT_COMRESET (comreset_send), // output reg
.SEND_SYNC_ESC (syncesc_send), // output reg
.SET_OFFLINE (set_offline), // output reg
.R_OK (send_R_OK), // output reg
.R_ERR (send_R_ERR), // output reg
// .EN_COMINIT (en_cominit), // output reg
.EN_COMINIT (clear_pisn32), // output reg
// FIS TRANSMIT/WAIT DONE
.FETCH_CMD (fetch_cmd), // output reg
.ATAPI_XMIT (atapi_xmit), // output reg
.CFIS_XMIT (cfis_xmit), // output reg
.DX_XMIT (dx_xmit), // output reg
//FIS RECEIVE/WAIT DONE
.GET_DATA_FIS (get_data_fis), // output reg
.GET_DSFIS (get_dsfis), // output reg
.GET_IGNORE (get_ignore), // output reg
.GET_PSFIS (get_psfis), // output reg
.GET_RFIS (get_rfis), // output reg
.GET_SDBFIS (get_sdbfis), // output reg
.GET_UFIS (get_ufis) // output reg
);
// Condition inputs may be registered if needed
condition_mux condition_mux_i (
.clk (mclk), // input
.ce (conditions_ce), // input
.sel (pgm_data[17:10]), // input[7:0]
.condition (cond_met_w), // output
//COMPOSITE
.ST_NB_ND (pcmd_st && !tfd_bsy &&!tfd_drq), // input PxCMD.ST & !PxTFD.STS.BSY & !PxTFD.STS.DRQ
// .PXCI0_NOT_CMDTOISSUE (pxci0 && !pCmdToIssue), // input pxci0 && !pCmdToIssue was pIssueSlot==32, -> p:SelectCmd
.PXCI0_NOT_CMDTOISSUE (pxci0 && !pisn32), // input pxci0 && !pCmdToIssue was pIssueSlot==32, -> p:SelectCmd
.PCTI_CTBAR_XCZ (pCmdToIssue && xfer_cntr_zero && ch_r ), // input pCmdToIssue && ch_r && xfer_cntr_zero
.PCTI_XCZ (pCmdToIssue && xfer_cntr_zero), // input pCmdToIssue && xfer_cntr_zero
.NST_D2HR (!pcmd_st && (fis_type == FIS_D2HR)), // input !ST && (FIS == FIS_D2HR) TODO: does it mean either BSY or DRQ are 1?
.NPD_NCA (!pio_d && !ch_a), // input pio_d = 0 && ch_a == 0
.CHW_DMAA (ch_w && dma_a), // input ch_w && dma_a
// CTRL_STAT
.SCTL_DET_CHANGED_TO_4 (sctl_det_changed && (sctl_det == 4)), // input (requires sctl_det_reset after)
.SCTL_DET_CHANGED_TO_1 (sctl_det_changed && (sctl_det == 1)), // input (requires sctl_det_reset after)
.PXSSTS_DET_NE_3 (ssts_det != 3), // input ssts_det!=3, // device detected, phy communication not established
.PXSSTS_DET_EQ_1 (ssts_det == 1), // input
.NPCMD_FRE (!pxcmd_fre), // input !pcmd_fre (docs: goto P:NotRunning, but we need to clear FIFO)
// FIS RECEIVE
.FIS_OK (fis_ok), // input
.FIS_ERR (fis_err), // input
.FIS_FERR (fis_ferr), // input
.FIS_EXTRA (fis_extra), // input
.FIS_FIRST_INVALID (fis_first_invalid), // input
.FR_D2HR (fis_first_vld && (fis_type == FIS_D2HR)), // input fis_first_vld & fis_type == 0x34 (D2H Register)
.FIS_DATA (fis_first_vld && (fis_type == FIS_DATA)), // input fis_first_vld && (fis_type == 'h46)
.FIS_ANY (fis_first_vld), // input
.NB_ND_D2HR_PIO (((fis_type == FIS_D2HR) || (fis_type == FIS_PIOS)) && !tfd_bsy && !tfd_drq), // input ((FIS == FIS_D2HR) || (FIS == FIS_PIOS)) && !PxTFD.STS.BSY & !PxTFD.STS.DRQ
.D2HR ( fis_type == FIS_D2HR), // input FIS == FIS_D2HR
.SDB ( fis_type == FIS_SDB), // input
.DMA_ACT ( fis_type == FIS_DMAA), // input
.DMA_SETUP ( fis_type == FIS_DMAS), // input
.BIST_ACT_FE (( fis_type == FIS_BIST) && (|bist_bits)), // input FIS == FIS_BIST && |bist_bits
.BIST_ACT (( fis_type == FIS_BIST)), // input FIS == FIS_BIST# && !(|bist_bits)
.PIO_SETUP ( fis_type == FIS_PIOS), // input
.NB_ND (!tfd_bsy &&!tfd_drq), // input PxTFD.STS.BSY =’0’ and PxTFD.STS.DRQ =’0’
.TFD_STS_ERR ( tfd_sts_err), // input tfd_sts[0]
.FIS_I (fis_i), // input
.PIO_I (pio_i), // input
.NPD (!pio_d), // input pio_d = 0 , "ch_a == 1" is not needed
.PIOX (pPioXfer), // input
.XFER0 (xfer_cntr_zero && !dma_cmd_busy), // input xfer_cntr_zero
.PIOX_XFER0 (pPioXfer && xfer_cntr_zero &&!dma_cmd_busy), // input pPioXfer && xfer_cntr_zero
// FIS_TRANSMIT
.CTBAA_CTBAP (ch_a && ch_p), // input
.CTBAP (ch_p), // input
.CTBA_B (ch_b), // input
.CTBA_C (ch_c), // input
.TX_ERR (dx_err[1]), // input dx_err[1] (reset by new command)
.SYNCESC_ERR (dx_err[0]), // input
// DMA
.DMA_PRD_IRQ_PEND (dma_prd_irq_pend), // input
// SATA TRANSPORT/LINK/PHY
.X_RDY_COLLISION (dx_err[2]) //x_rdy_collision_pend) // input
);
/*
output update_all,
input update_busy, // valid same cycle as update_all
Notes:
Implement sync esc request/ackn in TL (available in LL)
*/
endmodule
|
`timescale 1ns / 1ps
`include "WcaPortDefs.h" //grab register addresses.
`define BURST_ZERO 9'h0
// Name: WcaUsbFx3IF.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaUsbFx3IF(
input clk_in, //Interface Clock Input
input reset, //resets the interfaces.
//Cypress Interface
input flagA, //Flag A -- Current Thread Full
input flagB, //Flag B -- Current Thread Empty
input flagC, //Flag C
input flagD, //Flag D
//output nEpSwitch, // Thread assert switch
output nSlcs, //FX-3 Chip Select (assert low), must be zero to control the Fx-3
output nPktEnd, //Packet end signal (active low) to write a short packet to FX3 slave FIFO.
output [NBITS_ADDR-1:0] addr, // [1:0] 2 bit addressing mode, [4:0] 5 bit address mode.
output nSlWr, //Fx-3 Write Strobe (active low) assert to perform write transfers from FPGA to FX3 FIFO
output nSlRd, //Fx-3 Read Strobe (active low) assert to perform read transfers to FPGA from FX3 FIFO
output nSlOe, //Fx-3 Output Enable (active low) assert causes FX-3 to drive data. Asserts before Read
output clk, //Data bus clock.
inout [31:0] data, //32bit data bus.
inout [3:0] gpio, //Available GPIO Lines
//Port Interface
inout [31:0] pifData, // 32 bit port interface data bus.
input [(NBITS_ADDR+1):0] pifCtrl, // {addr[NBITS_ADDR:0], iocmd[1:0] }
output [6:0] pifStatus // I/O Status {fifo_full[0], fifo_empty[0], ioBusy, ioState[2:0], clk}
);
parameter NBITS_ADDR = 2;
parameter [9:0] BURST_COUNT = 9'h80; //default 128 (80h) DWORDS (512 bytes) USB 2.0, can increase to 256 (100h) DWORDS
// (1024 bytes) for optimal USB 3.0 performance.
`define LATENCY_ZERO 2'h0
`define LATENCY_ONE 2'h1
//Registers and wires
reg nSlCs_i = 1'b1 ;
reg nPktEnd_i = 1'b1 ;
reg nSlRd_i = 1'b1;
reg nSlOe_i = 1'b1;
reg nSlWr_i = 1'b1 ;
reg [2:0] ioState = `PIFSTAT_IDLE;
reg ioBusy = 1'b0; //indicates IO State machine is busy.
//Counters for state machine.
reg [8:0] ctBurst = `BURST_ZERO; //Burst is maximum 512 (4 byte samples) = 2048 bytes
reg [1:0] ctLatency = `LATENCY_ZERO;
//**************************************************
// Status and Control
//**************************************************
//Set up iostatus.
assign pifStatus[6] = flagA; //Current Thread Full
assign pifStatus[5] = flagB; //Current Thread Empty
assign pifStatus[4] = ioBusy; //Current Thread Empty
assign pifStatus[3:1] = ioState;
WcaPassthrough pthruClk(.a(clk_in), .b(pifStatus[0]));
//Set up address.
assign addr = pifCtrl[NBITS_ADDR+1:2];
//**************************************************
// Burst I/O State Machine
//**************************************************
assign nSlcs = nSlCs_i;
assign nPktEnd = nPktEnd_i;
assign nSlRd = nSlRd_i;
assign nSlOe = nSlOe_i;
assign nSlWr = nSlWr_i;
always @(posedge clk_in)
begin: PIFSTAT_State_Machine
if( reset)
begin
ioBusy <= 1'b0;
ioState <= `PIFSTAT_IDLE;
end
else
//State machine Generates FX3 Slave interface signals.
case (ioState)
`PIFSTAT_IDLE:
begin
nPktEnd_i <= 1'b1;
nSlOe_i <= 1'b1;
nSlRd_i <= 1'b1;
nSlWr_i <= 1'b1;
nSlCs_i <= 1'b0;
ctBurst <= `BURST_ZERO;
ioBusy <= 1'b0;
//FLAG A denotes full/empty (active low) on the current thread (full==write, empty==read);
//If command is read and not empty buffer, start read op.
if( (pifCtrl[1:0] == `PIFCMD_READ) && flagA) ioState <= `PIFSTAT_READ_BEGIN;
//If command is write and not full buffer, start write op.
else if( (pifCtrl[1:0] == `PIFCMD_WRITE) && flagA) ioState <= `PIFSTAT_WRITE_BEGIN;
//else stay in this state.
else ioState <= `PIFSTAT_IDLE;
end
`PIFSTAT_READ_BEGIN:
begin
nPktEnd_i <= 1'b1;
nSlOe_i <= 1'b0;
nSlRd_i <= 1'b0;
nSlWr_i <= 1'b1;
nSlCs_i <= 1'b0;
ctBurst <= `BURST_ZERO;
if(~ioBusy)
begin
ioBusy <= 1'b1; //Now doing a read, can't interrupt.
ctLatency <= `READ_BEGIN_CYCLES; //2 cycles latency -1.
end
else //Stay in Begin Read until we passed latency.
begin
ctLatency <= ctLatency - `LATENCY_ONE;
ioBusy <= 1'b1;
if( ctLatency == `LATENCY_ZERO) ioState <= `PIFSTAT_READ;
else ioState <= `PIFSTAT_READ_BEGIN;
end
end
`PIFSTAT_READ: //Read a burst of data.
begin
nPktEnd_i <= 1'b1;
nSlOe_i <= 1'b0;
nSlRd_i <= 1'b0;
nSlWr_i <= 1'b1;
nSlCs_i <= 1'b0;
ioBusy <= 1'b1;
if( ctBurst < BURST_COUNT- 9'h1)
begin
ctBurst <= ctBurst + 9'h1;
ioState <= `PIFSTAT_READ;
end
else //Transition to Idle.
begin
ioState <= `PIFSTAT_WAITEND;
ctLatency <= `READ_WAIT_END_CYCLES;
end
end
`PIFSTAT_WRITE_BEGIN:
begin
nPktEnd_i <= 1'b1;
nSlOe_i <= 1'b1;
nSlRd_i <= 1'b1;
nSlWr_i <= 1'b0;
nSlCs_i <= 1'b0;
ctBurst <= `BURST_ZERO;
ioState <= `PIFSTAT_WRITE;
ioBusy <= 1'b1;
/*
if( ~ioBusy)
begin
ioBusy <= 1'b1; //Now doing a Write, can't interrupt.
ctLatency = `LATENCY_ZERO;
end
else //Stay in Begin Write until we passed latency.
begin
ctLatency <= ctLatency - `LATENCY_ONE;
ioBusy <= 1'b1;
if( ctLatency == `LATENCY_ZERO) ioState <= PIFSTAT_WRITE;
else ioState <= PIFSTAT_WRITE_BEGIN;
end
*/
end
`PIFSTAT_WRITE: //Write a burst of data.
begin
nPktEnd_i <= 1'b1;
nSlOe_i <= 1'b1;
nSlRd_i <= 1'b1;
nSlCs_i <= 1'b0;
ioBusy <= 1'b1;
if( ctBurst < BURST_COUNT- 9'h1)
begin
ctBurst <= ctBurst + 9'h1;
nSlWr_i <= 1'b0;
ioState <= `PIFSTAT_WRITE;
end
else //Transition to Idle.
begin
ioState <= `PIFSTAT_WAITEND;
ctLatency <= `WRITE_WAIT_END_CYCLES;
nSlWr_i <= 1'b1;
end
end
`PIFSTAT_WAITEND:
begin
nPktEnd_i <= 1'b1;
nSlOe_i <= 1'b1;
nSlRd_i <= 1'b1;
nSlWr_i <= 1'b1;
nSlCs_i <= 1'b0;
ctBurst <= `BURST_ZERO;
ioBusy <= 1'b1;
if( ctLatency == `LATENCY_ZERO) ioState <= `PIFSTAT_IDLE;
else ctLatency <= ctLatency - `LATENCY_ONE;
end
default:
begin
ioBusy <= 1'b0;
ioState <= `PIFSTAT_IDLE;
end
endcase
end
//Tie the GPIO to high impedance since they are not used.
assign gpio = 4'bz;
//************************************
// CLOCK BUFFER
//************************************
//Buffer the clock output so internal clock is not driving output pin.
ODDR2 oddr_clk
(
.D0(1'b1),
.D1(1'b0),
.C0 (clk_in),
.C1(~clk_in),
.Q(clk)
);
//************************************
// Data Bus
//************************************
//Map the input signals to the internal busses.
//assign rbusData
WcaPassthrough #(.width(32)) pthruData(.a(data), .b(pifData));
endmodule
|
`include "bsg_defines.v"
module test_case #(parameter width_p, parameter banks_p) (input clk_i, input go_i, output finish_o);
reg [width_p-1:0] lo;
reg [width_p:0] in_r;
wire [$clog2((2**width_p+banks_p-1)/banks_p)-1:0] index_lo;
wire [`BSG_SAFE_CLOG2(banks_p)-1:0] bank_lo;
// bsg_nonsynth_clock_gen #(.cycle_time_p(5)) clkgen (.o(clk));
bsg_hash_bank #(.banks_p(banks_p), .width_p(width_p))
hashme (/* .clk,*/
.i( in_r[width_p-1:0] ),
// .i({in_r[1:0],in_r[5:2]}),
.bank_o(bank_lo),
.index_o(index_lo)
);
bsg_hash_bank_reverse #(.banks_p(banks_p), .width_p(width_p))
unhashme (/* .clk,*/
.o( lo ),
// .i({in_r[1:0],in_r[5:2]}),
.bank_i(bank_lo),
.index_i(index_lo)
);
initial in_r = 0;
reg finish_r;
initial finish_r = 0;
always @(posedge clk_i)
begin
if (!finish_r & go_i)
begin
in_r <= in_r + 1;
finish_r <= in_r[width_p];
end
end
assign finish_o = finish_r;
always @(negedge clk_i)
begin
// $display ("%b -> %b %b -> %b", in_r, bucket_lo, index_lo,lo);
if (lo != in_r[width_p-1:0])
$display("(%3d,%3d) MISMATCH: %b -> %b %b -> %b",width_p,banks_p,in_r[width_p-1:0],bank_lo, index_lo, lo);
else
if (!finish_r & go_i)
$display("(%3d,%3d) match: %b -> %b %b -> %b",width_p,banks_p,in_r[width_p-1:0],bank_lo, index_lo, lo);
end
endmodule // test_case
module tb(input clk_i);
localparam tests_p = 10;
wire [tests_p-1:0] finish_lo;
test_case #(6,1) tc61 (.clk_i,.finish_o(finish_lo[0]),.go_i(1));
test_case #(6,2) tc62 (.clk_i,.finish_o(finish_lo[1]),.go_i(finish_lo[0]));
test_case #(6,3) tc63 (.clk_i,.finish_o(finish_lo[2]),.go_i(finish_lo[1]));
test_case #(6,4) tc64 (.clk_i,.finish_o(finish_lo[3]),.go_i(finish_lo[2]));
test_case #(6,6) tc66 (.clk_i,.finish_o(finish_lo[4]),.go_i(finish_lo[3]));
test_case #(6,7) tc67 (.clk_i,.finish_o(finish_lo[5]),.go_i(finish_lo[4]));
test_case #(8,7) tc87 (.clk_i,.finish_o(finish_lo[6]),.go_i(finish_lo[5]));
test_case #(6,8) tc68 (.clk_i,.finish_o(finish_lo[7]),.go_i(finish_lo[6]));
test_case #(6,12) tc612 (.clk_i,.finish_o(finish_lo[8]),.go_i(finish_lo[7]));
test_case #(8,15) tc815 (.clk_i,.finish_o(finish_lo[9]),.go_i(finish_lo[8]));
always @(*)
if (&finish_lo)
$finish();
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : bd_mig_7series_0_0.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Wrapper module for the user design top level file. This module can be
// instantiated in the system and interconnect as shown in example design
// (example_top module).
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module bd_mig_7series_0_0 (
// Inouts
inout [15:0] ddr2_dq,
inout [1:0] ddr2_dqs_n,
inout [1:0] ddr2_dqs_p,
// Outputs
output [12:0] ddr2_addr,
output [2:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [0:0] ddr2_ck_p,
output [0:0] ddr2_ck_n,
output [0:0] ddr2_cke,
output [0:0] ddr2_cs_n,
output [1:0] ddr2_dm,
output [0:0] ddr2_odt,
// Inputs
// Single-ended system clock
input sys_clk_i,
// Single-ended iodelayctrl clk (reference clock)
input clk_ref_i,
// user interface signals
output ui_clk,
output ui_clk_sync_rst,
output ui_addn_clk_0,
output ui_addn_clk_1,
output ui_addn_clk_2,
output ui_addn_clk_3,
output ui_addn_clk_4,
output mmcm_locked,
input aresetn,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
// Slave Interface Write Address Ports
input [3:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input [0:0] s_axi_awlock,
input [3:0] s_axi_awcache,
input [2:0] s_axi_awprot,
input [3:0] s_axi_awqos,
input s_axi_awvalid,
output s_axi_awready,
// Slave Interface Write Data Ports
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
// Slave Interface Write Response Ports
input s_axi_bready,
output [3:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
// Slave Interface Read Address Ports
input [3:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input [0:0] s_axi_arlock,
input [3:0] s_axi_arcache,
input [2:0] s_axi_arprot,
input [3:0] s_axi_arqos,
input s_axi_arvalid,
output s_axi_arready,
// Slave Interface Read Data Ports
input s_axi_rready,
output [3:0] s_axi_rid,
output [31:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
output init_calib_complete,
input sys_rst
);
// Start of IP top instance
bd_mig_7series_0_0_mig u_bd_mig_7series_0_0_mig (
// Memory interface ports
.ddr2_addr (ddr2_addr),
.ddr2_ba (ddr2_ba),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_ck_n (ddr2_ck_n),
.ddr2_ck_p (ddr2_ck_p),
.ddr2_cke (ddr2_cke),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_dq (ddr2_dq),
.ddr2_dqs_n (ddr2_dqs_n),
.ddr2_dqs_p (ddr2_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_dm (ddr2_dm),
.ddr2_odt (ddr2_odt),
// Application interface ports
.ui_clk (ui_clk),
.ui_clk_sync_rst (ui_clk_sync_rst),
.ui_addn_clk_0 (ui_addn_clk_0),
.ui_addn_clk_1 (ui_addn_clk_1),
.ui_addn_clk_2 (ui_addn_clk_2),
.ui_addn_clk_3 (ui_addn_clk_3),
.ui_addn_clk_4 (ui_addn_clk_4),
.mmcm_locked (mmcm_locked),
.aresetn (aresetn),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (s_axi_awqos),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (s_axi_arqos),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// System Clock Ports
.sys_clk_i (sys_clk_i),
// Reference Clock Ports
.clk_ref_i (clk_ref_i),
.sys_rst (sys_rst)
);
// End of IP top instance
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: Modulo de decisión del firewall 2014-07 $
//
// Module: decision.v
// Project: FIREWALL DDOS
// Description: Modulo encargado de realizar la decision en los
// paquetes que ingresan de acuerdo a los resultados de comparacion
// de las 2 TCAM implementadas.
//
// FUNCIONAMIENTO:
// Se tienen tres buffers FIFO, dos para los resultados de la comparación
// uno para el paquete completo.
// Primeramente se concatenan resultados para la comparacion en un registro de 2 bits
// comp_c <= {rtcam_usr,rtcam_bl}
// La decicion de descarte de los paquetes sigue la siguiente lógica
// comp_c val_dec Decision(ACCEPT ALL) Decision(DENY_ALL)
// 00 0 PASS DENY
// 01 1 DENY DENY
// 10 2 PASS PASS
// 11 3 DENY DENY
// Como se puede observar en la tabla se realiza el analisis para los casos
// en los que la politica del FIREWALL sea ACCEPT ALL o DENY ALL
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module decision
#(
parameter DATA_WIDTH = 64,
parameter DATA_WIDTH_TCAM = 1,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter UDP_REG_SRC_WIDTH = 2
)
(
// Interfaz con los sub-modulos TCAM y con Input Arbiter
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
input in_data_usr,
// input in_ctrl_rtcam_usr,
input in_wr_usr,
output in_rdy_usr,
input in_data_bl,
// input in_ctrl_rtcam_bl,
input in_wr_bl,
output in_rdy_bl,
// Interfaz con OUTPUT PORT LOOKUP
output [DATA_WIDTH-1:0] out_data,
output [CTRL_WIDTH-1:0] out_ctrl,
output out_wr,
input out_rdy,
// --- Register interface
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
// misc
input reset,
input clk
);
// Define the log2 function
`LOG2_FUNC
//------------------------- Signals-------------------------------
wire [DATA_WIDTH-1:0] in_fifo_data;
wire [CTRL_WIDTH-1:0] in_fifo_ctrl;
wire in_fifo_nearly_full;
wire in_fifo_empty;
reg in_fifo_rd_en;
reg out_wr_int;
wire in_fifo_data_usr;
wire in_fifo_rd_en_usr;
wire in_fifo_nearly_full_usr;
wire in_fifo_empty_usr;
reg in_fifo_rd_en_usr;
reg out_wr_int_usr;
wire in_fifo_data_bl;
wire in_fifo_rd_en_bl;
wire in_fifo_nearly_full_bl;
wire in_fifo_empty_bl;
reg in_fifo_rd_en_bl;
reg out_wr_int_bl;
//------------------------- Local assignments -------------------------------
assign in_rdy = !in_fifo_nearly_full;
assign out_wr = out_wr_int;
assign out_data = in_fifo_data;
assign out_ctrl = in_fifo_ctrl;
assing in_rdy_usr = !in_fifo_nearly_full_usr;
assing out_wr_usr = out_wr_int_usr;
assign out_data_usr = in_fifo_data_usr;
assing in_rdy_bl = !in_fifo_nearly_full_bl;
assing out_wr_usr = out_wr_int_bl;
assign out_data_usr = in_fifo_data_bl;
//------------------------- Modules-------------------------------
// Buffer para los paquetes
fallthrough_small_fifo #(
.WIDTH(CTRL_WIDTH+DATA_WIDTH),
.MAX_DEPTH_BITS(4)
) input_fifo (
.din ({in_ctrl, in_data}), // Data in
.wr_en (in_wr), // Write enable
.rd_en (in_fifo_rd_en), // Read the next word
.dout ({in_fifo_ctrl, in_fifo_data}),
.full (),
.nearly_full (in_fifo_nearly_full),
.prog_full (),
.empty (in_fifo_empty),
.reset (reset),
.clk (clk)
);
// Buffer para resultados TCAM_USR
small_fifo #(
.WIDTH(DATA_WIDTH_TCAM),
.MAX_DEPTH_BITS(4)
) tcam_usr_input_fifo (
.din (in_data_rtcam_usr), // Data in
.wr_en (in_wr_rtcam_usr), // Write enable
.rd_en (in_fifo_rd_en_usr), // Read the next word
.dout (in_fifo_data_usr),
.full (),
.prog_full (),
.nearly_full (in_fifo_nearly_full_usr),
.empty (in_fifo_empty_usr),
.reset (reset),
.clk (clk)
);
// Buffer para resultados TCAM_BL
small_fifo #(
.WIDTH(DATA_WIDTH_TCAM),
.MAX_DEPTH_BITS(4)
) tcam_bl_input_fifo (
.din (in_data_rtcam_bl), // Data in
.wr_en (in_wr_rtcam_bl), // Write enable
.rd_en (in_fifo_rd_en_bl), // Read the next word
.dout (in_fifo_data_bl),
.full (),
.prog_full (),
.nearly_full (in_fifo_nearly_full_bl),
.empty (in_fifo_empty_bl),
.reset (reset),
.clk (clk)
);
// Registros genericos
generic_regs
#(
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.TAG (0), // Tag -- eg. MODULE_TAG
.REG_ADDR_WIDTH (1), // Width of block addresses
.NUM_COUNTERS (0), // Number of counters
.NUM_SOFTWARE_REGS (0), // Number of sw regs
.NUM_HARDWARE_REGS (0) // Number of hw regs
) module_regs (
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
.reg_req_out (reg_req_out),
.reg_ack_out (reg_ack_out),
.reg_rd_wr_L_out (reg_rd_wr_L_out),
.reg_addr_out (reg_addr_out),
.reg_data_out (reg_data_out),
.reg_src_out (reg_src_out),
// --- counters interface
.counter_updates (),
.counter_decrement(),
// --- SW regs interface
.software_regs (),
// --- HW regs interface
.hardware_regs (),
.clk (clk),
.reset (reset)
);
//------------------------- Logic-------------------------------
always @(*) begin
// Default values
out_wr_int = 0;
in_fifo_rd_en = 0;
if (!in_fifo_empty && out_rdy) begin
out_wr_int = 1;
in_fifo_rd_en = 1;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2015/09/22 09:30:47
// Design Name:
// Module Name: null_filter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module null_filter(
vid_pData_I,
vid_pHSync_I,
vid_pVSync_I,
vid_pVDE_I,
PixelClk_I,
vid_pData_O,
vid_pHSync_O,
vid_pVSync_O,
vid_pVDE_O,
PixelClk_O
);
input [23:0] vid_pData_I;
input vid_pHSync_I;
input vid_pVSync_I;
input vid_pVDE_I;
input PixelClk_I;
output [23:0] vid_pData_O;
output vid_pHSync_O;
output vid_pVSync_O;
output vid_pVDE_O;
output PixelClk_O;
assign vid_pData_O = vid_pData_I;
assign vid_pVSync_O = vid_pVSync_I;
assign vid_pHSync_O = vid_pHSync_I;
assign vid_pVDE_O = vid_pVDE_I;
assign PixelClk_O = PixelClk_I;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 12.4
// \ \ Application : xaw2verilog
// / / Filename : master_clk.v
// /___/ /\ Timestamp : 05/02/2013 05:55:56
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle C:/Users/rodriguj/Documents/proyectos_xilinx/ula_replacement_tests/test3/ipcore_dir/master_clk.xaw -st master_clk.v
//Design Name: master_clk
//Device: xc3s100e-4vq100
//
// Module master_clk
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI
// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 3.20 ns
`timescale 1ns / 1ps
module master_clk(CLKIN_IN,
CLKDV_OUT,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT);
input CLKIN_IN;
output CLKDV_OUT;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
wire CLKDV_BUF;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(5.0), .CLKFX_DIVIDE(25),
.CLKFX_MULTIPLY(7), .CLKIN_DIVIDE_BY_2("TRUE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(CLKDV_BUF),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(),
.PSDONE(),
.STATUS());
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32OI_4_V
`define SKY130_FD_SC_HD__A32OI_4_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a32oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a32oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a32oi_4 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32OI_4_V
|
//pf_hi_tester.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x800000000000C594
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:pf_hi_tester
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x0F
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/12/29
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:3
*/
module pf_hi_tester (
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int
//output o_wbs_int
);
//Local Parameters
localparam ADDR_0 = 32'h00000000;
localparam ADDR_1 = 32'h00000001;
localparam ADDR_2 = 32'h00000002;
//Local Registers/Wires
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
24'h0000FF: begin
o_wbs_int <= 0;
end
24'h001000: begin
o_wbs_int <= i_wbs_dat[0];
end
default: begin
end
endcase
end
else begin
//read request
o_wbs_dat <= i_wbs_adr;
end
o_wbs_ack <= 1;
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221OI_4_V
`define SKY130_FD_SC_MS__A221OI_4_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221oi_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221OI_4_V
|
/**
* fillbox_act.v: fillbox accelarator controle logic
*/
module fillbox_act (
input wire [27:0] vram,
input wire [9:0] width,
input wire [9:0] height,
input wire start,
output wire done,
// AXI4 stuff
input wire clk,
input wire bready,
output reg [27:0] awaddr,
output reg burst_start,
output reg [7:0] awlen,
output reg [3:0] wstrb
);
// X/Y axis state machine
parameter IDLE = 2'h0,
START = 2'h1,
WAIT = 2'h2;
localparam SCREEN_WIDTH = 28'd1280;
reg [27:0] vram_y = 0;
reg [10:0] offset = 0;
reg [10:0] delta = 0;
reg [9:0] width_work = 0;
reg [9:0] height_work = 0;
reg [9:0] expected_count = 0;
reg [9:0] real_count = 0;
reg [1:0] state_x = IDLE, state_y = IDLE;
reg start_x = 0;
reg end_x = 0;
reg done_ff1 = 0;
reg done_ff2 = 0;
wire [27:0] awaddr_tmp = vram_y + {17'b0, offset};
assign done = done_ff1 && ~done_ff2;
// end of accelarator action
always @(posedge clk) begin
done_ff2 <= done_ff1;
done_ff1 <= (width_work == 10'd0 && height_work == 10'd0 && expected_count == real_count);
awaddr <= {awaddr_tmp[27:2], 2'b0};
end
// real access count
always @(posedge clk) begin
if (start_x == 'b0)
real_count <= 10'd0;
else if (bready)
real_count <= real_count + 10'd1;
else
real_count <= real_count;
end
// Y axis action
always @(posedge clk) begin
case (state_y)
IDLE:
begin
if (start) begin
state_y <= START;
height_work <= height;
vram_y <= vram;
end
else begin
state_y <= state_y;
height_work <= height_work;
vram_y <= vram_y;
end
start_x <= 'b0;
end
START:
begin
if (height_work == 10'd0) begin
state_y <= IDLE;
height_work <= 10'd0;
vram_y <= vram_y;
start_x <= 'b0;
end
else begin
state_y <= WAIT;
height_work <= height_work;
vram_y <= vram_y;
start_x <= 'b1;
end
end
WAIT:
begin
if (end_x) begin
state_y <= START;
height_work <= height_work - 10'd1;
vram_y <= vram_y + SCREEN_WIDTH;
start_x <= 'b0;
end
else begin
state_y <= state_y;
height_work <= height_work;
vram_y <= vram_y;
start_x <= start_x;
end
end
default:
begin
state_y <= IDLE;
height_work <= height_work;
vram_y <= vram_y;
start_x <= 'b0;
end
endcase
end
// X axis action
always @(posedge clk) begin
if (start_x == 'b0) begin
end_x <= 'b0;
expected_count = 10'd0;
width_work <= 10'd0;
offset <= 11'd0;
delta <= 11'd0;
burst_start <= 'b0;
awlen <= 8'd0;
wstrb <= 4'b0000;
state_x <= IDLE;
end
else begin
case (state_x)
IDLE:
begin
end_x <= 'b0;
expected_count <= 10'd0;
width_work <= width;
offset <= 11'd0;
delta <= 11'd0;
burst_start <= 'b0;
awlen <= 8'd0;
wstrb <= 4'b0000;
state_x <= START;
end
START:
begin
if (width_work == 10'd0) begin
end_x <= 'b1;
expected_count <= expected_count;
width_work <= width_work;
offset <= offset;
delta <= delta;
burst_start <= 'b0;
awlen <= awlen;
wstrb <= wstrb;
state_x <= IDLE;
end
else begin
if (awaddr_tmp[1]) begin
// address not divisable by 4
// width_work greater than 0
width_work <= width_work - 10'd1;
delta <= 11'd2;
wstrb <= 4'b1100;
awlen <= 8'd0;
end
else if (width_work == 10'd1) begin
// address divisable by 4
// width_work equal to 1
width_work <= width_work - 10'd1;
delta <= 11'd2;
wstrb <= 4'b0011;
awlen <= 8'd0;
end
else if (awaddr_tmp[2] || width_work <= 10'd3) begin
// address not divisable by 8
// width_work greater than 1, less than 4
width_work <= width_work - 10'd2;
delta <= 11'd4;
wstrb <= 4'b1111;
awlen <= 8'd0;
end
else if (awaddr_tmp[3] || width_work <= 10'd7) begin
// address not divisable by 16
// width_work greater than 3, less than 8
width_work <= width_work - 10'd4;
delta <= 11'd8;
wstrb <= 4'b1111;
awlen <= 8'd1;
end
else if (awaddr_tmp[4] || width_work <= 10'd15) begin
// address not divisable by 32
// width_work greater than 7, less than 16
width_work <= width_work - 10'd8;
delta <= 11'd16;
wstrb <= 4'b1111;
awlen <= 8'd3;
end
else if (awaddr_tmp[5] || width_work <= 10'd31) begin
// address not divisable by 64
// width_work greater thean 15, less than 32
width_work <= width_work - 10'd16;
delta <= 11'd32;
wstrb <= 4'b1111;
awlen <= 8'd7;
end
else begin
// address divisable by 64
// width_work greater than 31
width_work <= width_work - 10'd32;
delta <= 11'd64;
wstrb <= 4'b1111;
awlen <= 8'd15;
end
end_x <= 'b0;
expected_count <= expected_count + 10'd1;
offset <= offset;
burst_start <= 'b1;
state_x <= WAIT;
end
end
WAIT:
begin
if (bready) begin
offset <= offset + delta;
delta <= 11'd0;
state_x <= START;
end
else begin
offset <= offset;
delta <= delta;
state_x <= state_x;
end
awlen <= awlen;
wstrb <= wstrb;
burst_start <= 'b0;
end_x <= 'b0;
expected_count <= expected_count;
width_work <= width_work;
end
default:
begin
end_x <= 'b0;
expected_count <= expected_count;
width_work <= width_work;
offset <= offset;
delta <= delta;
burst_start <= 'b0;
awlen <= awlen;
wstrb <= wstrb;
state_x <= IDLE;
end
endcase
end
end
endmodule
|
module L1_Cache
#(
parameter addr_width = 32,
parameter cpu_data_width = 32,
parameter mem_data_width = 256
)
(
input clk,
input rst,
// cpu side
input [addr_width-1:0] cache_addr,
input cache_cs,
input cache_we,
output cache_ack,
input [cpu_data_width-1:0] cache_data_i,
output [cpu_data_width-1:0] cache_data_o,
// external memory side
output [addr_width-1:0] dram_addr,
output dram_cs,
output dram_we,
input dram_ack,
input [mem_data_width-1:0] dram_data_o,
output [mem_data_width-1:0] dram_data_i
);
// address from CPU
wire [21:0] addr_tag;
wire [4:0] addr_index;
wire [4:0] addr_offset;
wire [2:0] block_offset = addr_offset[4:2];
// data from SRAM
wire sram_valid;
wire sram_dirty;
wire [21:0] sram_tag;
// tag SRAM related values
wire cache_hit;
// assign the internal bus, todo: parametrized
assign addr_tag = cache_addr[31:10];
assign addr_index = cache_addr[9:5];
assign addr_offset = cache_addr[4:0];
assign sram_valid = tag_storage.data_o[23];
assign sram_dirty = tag_storage.data_o[22];
assign sram_tag = tag_storage.data_o[21:0];
assign cache_hit = ((addr_tag == sram_tag) && sram_valid) ? 1'b1 : 1'b0;
assign dram_addr = {sram_tag, addr_index, 5'b0};
assign dram_data_i = data_storage.data_o;
L1_Cache_Controller controller (
.clk (clk),
.rst (rst),
// interface to CPU
.cache_cs (cache_cs),
.cache_we (cache_we),
.cache_ack (cache_ack),
// interface to internal components
.cache_hit (cache_hit),
.sram_we (),
.cache_valid (sram_valid),
.cache_dirty_i (sram_dirty),
.cache_dirty_o (),
.sram_data_sel (),
// interface to DRAM
.dram_cs (dram_cs),
.dram_we (dram_we),
.dram_ack (dram_ack)
);
SRAM #(.addr_width(5), .data_width(24), .mem_size(32)) tag_storage
(
.clk (clk),
.addr_i (addr_index),
.cs (1'b1),
.we (controller.sram_we),
.data_i ({1'b1, controller.cache_dirty_o, addr_tag}),
.data_o ()
);
Decoder_3to8 decoder (
.sel (block_offset),
.out ()
);
Multiplexer4Way write_data_b1 (
.data_1 (data_storage.data_o[255:224]),
.data_2 (data_storage.data_o[255:224]),
.data_3 (cache_data_i),
.data_4 (dram_data_o[255:224]),
.sel ({decoder.out[0], controller.sram_data_sel}),
.data_o (data_storage.data_i[255:224])
);
Multiplexer4Way write_data_b2 (
.data_1 (data_storage.data_o[223:192]),
.data_2 (data_storage.data_o[223:192]),
.data_3 (cache_data_i),
.data_4 (dram_data_o[223:192]),
.sel ({decoder.out[1], controller.sram_data_sel}),
.data_o (data_storage.data_i[223:192])
);
Multiplexer4Way write_data_b3 (
.data_1 (data_storage.data_o[191:160]),
.data_2 (data_storage.data_o[191:160]),
.data_3 (cache_data_i),
.data_4 (dram_data_o[191:160]),
.sel ({decoder.out[2], controller.sram_data_sel}),
.data_o (data_storage.data_i[191:160])
);
Multiplexer4Way write_data_b4 (
.data_1 (data_storage.data_o[159:128]),
.data_2 (data_storage.data_o[159:128]),
.data_3 (cache_data_i),
.data_4 (dram_data_o[159:128]),
.sel ({decoder.out[3], controller.sram_data_sel}),
.data_o (data_storage.data_i[159:128])
);
Multiplexer4Way write_data_b5 (
.data_1 (data_storage.data_o[127:96]),
.data_2 (data_storage.data_o[127:96]),
.data_3 (cache_data_i),
.data_4 (dram_data_o[127:96]),
.sel ({decoder.out[4], controller.sram_data_sel}),
.data_o (data_storage.data_i[127:96])
);
Multiplexer4Way write_data_b6 (
.data_1 (data_storage.data_o[95:64]),
.data_2 (data_storage.data_o[95:64]),
.data_3 (cache_data_i),
.data_4 (dram_data_o[95:64]),
.sel ({decoder.out[5], controller.sram_data_sel}),
.data_o (data_storage.data_i[95:64])
);
Multiplexer4Way write_data_b7 (
.data_1 (data_storage.data_o[63:32]),
.data_2 (data_storage.data_o[63:32]),
.data_3 (cache_data_i),
.data_4 (dram_data_o[63:32]),
.sel ({decoder.out[6], controller.sram_data_sel}),
.data_o (data_storage.data_i[63:32])
);
Multiplexer4Way write_data_b8 (
.data_1 (data_storage.data_o[31:0]),
.data_2 (data_storage.data_o[31:0]),
.data_3 (cache_data_i),
.data_4 (dram_data_o[31:0]),
.sel ({decoder.out[7], controller.sram_data_sel}),
.data_o (data_storage.data_i[31:0])
);
SRAM #(.addr_width(5), .data_width(256), .mem_size(32)) data_storage
(
.clk (clk),
.addr_i (addr_index),
.cs (1'b1),
.we (controller.sram_we),
.data_i (),
.data_o ()
);
Multiplexer8Way read_data (
.data_1 (data_storage.data_o[255:224]),
.data_2 (data_storage.data_o[223:192]),
.data_3 (data_storage.data_o[191:160]),
.data_4 (data_storage.data_o[159:128]),
.data_5 (data_storage.data_o[127:96]),
.data_6 (data_storage.data_o[95:64]),
.data_7 (data_storage.data_o[63:32]),
.data_8 (data_storage.data_o[31:0]),
.sel (block_offset),
.data_o (cache_data_o)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A41O_FUNCTIONAL_PP_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41O_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__XOR2_FUNCTIONAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR2_FUNCTIONAL_PP_V
|
///////////////////////////////////////////////////////////////////////////////
// (c) Copyright 2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
///////////////////////////////////////////////////////////////////////////////
//
// STANDARD CC MODULE
//
//
// Description: This module drives the Aurora module's Clock Compensation
// interface. Clock Compensation sequences are generated according
// to the requirements in the Aurora Protocol specification.
//
// This module supports Aurora Modules with any number of
// 2-byte lanes and no User Flow Control.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ps
(* core_generation_info = "aur1,aurora_8b10b_v5_1,{backchannel_mode=Sidebands, c_aurora_lanes=4, c_column_used=left, c_gt_clock_1=GTPD7, c_gt_clock_2=None, c_gt_loc_1=X, c_gt_loc_10=X, c_gt_loc_11=X, c_gt_loc_12=X, c_gt_loc_13=3, c_gt_loc_14=4, c_gt_loc_15=1, c_gt_loc_16=2, c_gt_loc_17=X, c_gt_loc_18=X, c_gt_loc_19=X, c_gt_loc_2=X, c_gt_loc_20=X, c_gt_loc_21=X, c_gt_loc_22=X, c_gt_loc_23=X, c_gt_loc_24=X, c_gt_loc_25=X, c_gt_loc_26=X, c_gt_loc_27=X, c_gt_loc_28=X, c_gt_loc_29=X, c_gt_loc_3=X, c_gt_loc_30=X, c_gt_loc_31=X, c_gt_loc_32=X, c_gt_loc_33=X, c_gt_loc_34=X, c_gt_loc_35=X, c_gt_loc_36=X, c_gt_loc_37=X, c_gt_loc_38=X, c_gt_loc_39=X, c_gt_loc_4=X, c_gt_loc_40=X, c_gt_loc_41=X, c_gt_loc_42=X, c_gt_loc_43=X, c_gt_loc_44=X, c_gt_loc_45=X, c_gt_loc_46=X, c_gt_loc_47=X, c_gt_loc_48=X, c_gt_loc_5=X, c_gt_loc_6=X, c_gt_loc_7=X, c_gt_loc_8=X, c_gt_loc_9=X, c_lane_width=2, c_line_rate=3.125, c_nfc=false, c_nfc_mode=IMM, c_refclk_frequency=156.25, c_simplex=false, c_simplex_mode=TX, c_stream=true, c_ufc=false, flow_mode=None, interface_mode=Streaming, dataflow_config=Duplex,}" *)
module aur1_STANDARD_CC_MODULE
(
RESET,
//Clock Compensation Control Interface
WARN_CC,
DO_CC,
//System Interface
PLL_NOT_LOCKED,
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
//Clock Compensation Control Interface
output WARN_CC;
output DO_CC;
//System Interface
input PLL_NOT_LOCKED;
input USER_CLK;
input RESET;
//**************************** External Register Declarations*************************
reg WARN_CC;
reg DO_CC;
//************************** Internal Register Declarations **************************
reg [0:9] prepare_count_r;
reg [0:5] cc_count_r;
reg reset_r;
reg [0:11] count_13d_srl_r;
reg count_13d_flop_r;
reg [0:14] count_16d_srl_r;
reg count_16d_flop_r;
reg [0:22] count_24d_srl_r;
reg count_24d_flop_r;
//*********************************Wire Declarations**********************************
wire enable_cc_c;
wire start_cc_c;
wire inner_count_done_r;
wire middle_count_done_c;
wire cc_idle_count_done_c;
//*********************************Main Body of Code**********************************
//________________________Clock Correction State Machine__________________________
assign enable_cc_c = !RESET;
// The clock correction state machine is a counter with three sections. The first
// section counts out the idle period before a clock correction occurs. The second
// section counts out a period when NFC and UFC operations should not be attempted
// because they will not be completed. The last section counts out the cycles of
// the clock correction sequence.
// The inner count for the CC counter counts to 13. It is implemented using
// an SRL16 and a flop
// The SRL counts 12 bits of the count
always @(posedge USER_CLK)
if(RESET)
count_13d_srl_r <= `DLY 12'b000000000000;
else
count_13d_srl_r <= `DLY {count_13d_flop_r, count_13d_srl_r[0:10]};
// The inner count is done when a 1 reaches the end of the SRL
assign inner_count_done_r = count_13d_srl_r[11];
// The flop extends the shift register to 13 bits for counting. It is held at
// zero while channel up is low to clear the register, and is seeded with a
// single 1 when channel up transitions from 0 to 1
always @(posedge USER_CLK)
if(RESET)
count_13d_flop_r <= `DLY 1'b0;
else if(enable_cc_c && reset_r)
count_13d_flop_r <= `DLY 1'b1;
else
count_13d_flop_r <= `DLY inner_count_done_r;
// The middle count for the CC counter counts to 16. Its count increments only
// when the inner count is done. It is implemented using an SRL16 and a flop
// The SRL counts 15 bits of the count. It is enabled only when the inner count
// is done
always @(posedge USER_CLK)
if(RESET)
count_16d_srl_r <= `DLY 15'b000000000000000;
else if(inner_count_done_r|| !enable_cc_c)
count_16d_srl_r <= `DLY {count_16d_flop_r, count_16d_srl_r[0:13]};
// The middle count is done when a 1 reaches the end of the SRL and the inner
// count finishes
assign middle_count_done_c = inner_count_done_r && count_16d_srl_r[14];
// The flop extends the shift register to 16 bits for counting. It is held at
// zero while channel up is low to clear the register, and is seeded with a
// single 1 when channel up transitions from 0 to 1
always @(posedge USER_CLK)
if(RESET)
count_16d_flop_r <= `DLY 1'b0;
else if(enable_cc_c && reset_r)
count_16d_flop_r <= `DLY 1'b1;
else if(inner_count_done_r)
count_16d_flop_r <= `DLY middle_count_done_c;
// The outer count (aka the cc idle count) is done when it reaches 24. Its count
// increments only when the middle count is done. It is implemented with 2 SRL16s
// and a flop
// The SRL counts 23 bits of the count. It is enabled only when the middle count is
// done
always @(posedge USER_CLK)
if(RESET)
count_24d_srl_r <= `DLY 23'b00000000000000000000000;
else if(middle_count_done_c || !enable_cc_c)
count_24d_srl_r <= `DLY {count_24d_flop_r, count_24d_srl_r[0:21]};
// The cc idle count is done when a 1 reaches the end of the SRL and the middle count finishes
assign cc_idle_count_done_c = middle_count_done_c & count_24d_srl_r[22];
// The flop extends the shift register to 24 bits for counting. It is held at
// zero while channel up is low to clear the register, and is seeded with a single
// 1 when channel up transitions from 0 to 1
always @(posedge USER_CLK)
if(RESET)
count_24d_flop_r <= `DLY 1'b0;
else if(enable_cc_c && reset_r)
count_24d_flop_r <= `DLY 1'b1;
else if(middle_count_done_c)
count_24d_flop_r <= `DLY cc_idle_count_done_c;
// For simulation, initialize prepare count to all zeros to simulate an SRL16
// after configuration. The circuit will also work is the init value includes
// ones.
initial
prepare_count_r = 10'b0000000000;
// Because UFC and CC sequences are not allowed to preempt one another, there
// there is a warning signal to indicate an impending CC sequence. This signal
// is used to prevent UFC messages from starting.
// For 4 lanes we use a 4-cycle count.
always @(posedge USER_CLK)
if(RESET)
prepare_count_r <= `DLY 10'b0000000000;
else
prepare_count_r <= `DLY {6'd0,cc_idle_count_done_c,prepare_count_r[6:8]};
// The state machine stays in the prepare_cc state from when the cc idle
// count finishes, to when the prepare count has finished. While in this
// state, UFC operations cannot start, which prevents them from having to
// be pre-empted by CC sequences.
always @(posedge USER_CLK)
if(RESET) WARN_CC <= `DLY 1'b0;
else if(cc_idle_count_done_c) WARN_CC <= `DLY 1'b1;
else if(prepare_count_r[9]) WARN_CC <= `DLY 1'b0;
// For simulation, init to zeros, to simulate an SRL after configuration. The circuit
// will also operate if the SRL is not initialized to all zeros
initial
cc_count_r = 6'b000000;
// Track the state of channel up on the previous cycle. We use this signal to determine
// when to seed the shift register counters with ones
always @(posedge USER_CLK)
reset_r <= `DLY RESET;
//Do a CC after enable_cc_c is asserted or CC_warning is complete.
assign start_cc_c = prepare_count_r[9] || (enable_cc_c && reset_r);
// This SRL counter keeps track of the number of cycles spent in the CC
// sequence. It starts counting when the prepare_cc state ends, and
// finishes counting after 6 cycles have passed.
always @(posedge USER_CLK)
if(RESET)
cc_count_r <= `DLY 6'b000000;
else
cc_count_r <= `DLY {(!enable_cc_c|prepare_count_r[9]),cc_count_r[0:4]};
// The TX_LL module stays in the do_cc state for 6 cycles. It starts
// when the prepare_cc state ends.
always @(posedge USER_CLK)
if(RESET) DO_CC <= `DLY 1'b0;
else if(start_cc_c) DO_CC <= `DLY 1'b1;
else if(cc_count_r) DO_CC <= `DLY 1'b1;
else DO_CC <= `DLY 1'b0;
endmodule
|
//======================================================================
//
// trng_debug_ctrl.v
// -----------------
// Debug and control module in the Cryptech TRNG.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module trng_debug_ctrl(
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error,
// Debug and control ports
output wire csprng_debug_mode,
output wire [4 : 0] csprng_num_rounds,
output wire csprng_reseed,
input wire csprng_error,
output wire security_error
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter ADDR_NAME0 = 8'h00;
parameter ADDR_NAME1 = 8'h01;
parameter ADDR_VERSION = 8'h02;
parameter CORE_NAME0 = 32'h73686132; // "sha2"
parameter CORE_NAME1 = 32'h2d323536; // "-512"
parameter CORE_VERSION = 32'h302e3830; // "0.80"
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
reg tmp_error;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign error = tmp_error;
//----------------------------------------------------------------
// core instantiation.
//----------------------------------------------------------------
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin
if (!reset_n)
begin
end
else
begin
end
end // reg_update
//----------------------------------------------------------------
// api_logic
//
// Implementation of the api logic. If cs is enabled will either
// try to write to or read from the internal registers.
//----------------------------------------------------------------
always @*
begin : api_logic
tmp_read_data = 32'h00000000;
tmp_error = 0;
if (cs)
begin
if (we)
begin
case (address)
// Write operations.
default:
begin
tmp_error = 1;
end
endcase // case (address)
end // if (we)
else
begin
case (address)
// Read operations.
ADDR_NAME0:
begin
tmp_read_data = CORE_NAME0;
end
ADDR_NAME1:
begin
tmp_read_data = CORE_NAME1;
end
ADDR_VERSION:
begin
tmp_read_data = CORE_VERSION;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end
end
end // addr_decoder
endmodule // trng_debug_ctrl
//======================================================================
// EOF trng_debug_ctrl.v
//======================================================================
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP_FUNCTIONAL_V
/**
* busdrivernovlp: Bus driver, enable gates pulldown only (pmoshvt
* devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__busdrivernovlp (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP_FUNCTIONAL_V
|
module ARM_CU_ALU( input MFC , Reset , Clk , MEMSTORE,MEMLOAD, input [31:0] MEMDAT, output [7:0] MEMADD, output MFA,READ_WRITE,WORD_BYTE);
wire[31:0] IR;
wire IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode;
wire [3:0] CU;
reg [19:0] RSLCT;
wire [31:0] Rn,Rm,Rs,PCout,Out;
wire [3:0] SRIN, _SRIN,SROUT;
wire SR29_OUT,S;
wire[31:0] _B;
//ControlUnit (output reg IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD,output reg[4:0] opcode, output[3:0] CU, input MFC, Reset,Clk);
ControlUnit cu(IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SROUT);
always@(IR or CU)
begin
RSLCT = {CU,IR[15:8],IR[3:0], IR[19:16]};
end
//RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
RegisterFile RF(Out,Out,RSLCT,Clk, Reset, PCLOAD, RFLOAD,IR_CU, Rn,Rm,Rs,PCout);
//assign S = IR[20]&SRENABLED;
assign _SRIN = {SROUT[3],SROUT[2],SR29_OUT,SROUT[0]};
//ARM_ALU(input wire [31:0] A,B,input wire[4:0] OP,input wire [3:0] FLAGS,output wire [31:0] Out,output wire [3:0] FLAGS_OUT, input wire S,ALU_OUT,);
ARM_ALU alu(Rn,_B, opcode, _SRIN, Out,SRIN,IR[20],ALUSTORE);
//BarrelShifter(input [31] Rs,Rm,IR,input SR29_IN,output SR29_OUT,output [31:0] Out);
BarrelShifter bs(Rs,Rm,IR,SROUT[1],SR29_OUT,_B);
//IR
//module Register(input [31:0] IN,input Clk, Reset,Load,output [31:0] OUT);
Register IRR( .IN(Out),
.Clk(Clk),
.Reset(Reset),
.Load(IRLOAD),
.OUT(IR));
//MBR
//Register2Buff(inout [31:0] IN,IN2,input Clk, Reset,Load,Load2,Store,Store2);
Register2Buff register(
.IN(Out),
.IN2(MEMDAT),
.Clk(Clk),
.Reset(Reset),
.Load(MBRLOAD),
.Load2(MEMLOAD),
.Store(MBRSTORE),
.Store2(MEMSTORE));
//MAR
//module Register(input [31:0] IN,input Clk, Reset,Load,output [31:0] OUT);
Register MAR( .IN(Out),
.Clk(Clk),
.Reset(Reset),
.Load(MARLOAD),
.OUT(MEMADD));
//SR
//module Register(input [31:0] IN,input Clk, Reset,Load,output [31:0] OUT);
Register SR( .IN(SRIN),
.Clk(Clk),
.Reset(Reset),
.Load(IR[20]),
.OUT(SROUT));
endmodule
//iverilog ARM_ALU.v BarrelShifter.v Buffer32_32.v controlunit6.v Decoder4x16.v Multiplexer2x1_32b.v Register.v Register2.v RegisterFile.v Register2Buff.v ARM_CU_ALU.v
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:12.0
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module shd_fifo (
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input wire rst;
input wire wr_clk;
input wire rd_clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [255 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [255 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(256),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(256),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex7"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(511),
.C_PROG_FULL_THRESH_NEGATE_VAL(510),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(9),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(1'D0),
.rst(rst),
.srst(1'D0),
.wr_clk(wr_clk),
.wr_rst(1'D0),
.rd_clk(rd_clk),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(9'B0),
.prog_empty_thresh_assert(9'B0),
.prog_empty_thresh_negate(9'B0),
.prog_full_thresh(9'B0),
.prog_full_thresh_assert(9'B0),
.prog_full_thresh_negate(9'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(),
.rd_rst_busy(),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 02 02:49:15 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_sim_netlist.v
// Design : design_1_processing_system7_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
SDIO0_WP,
UART0_TX,
UART0_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_I" *) input I2C0_SDA_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_O" *) output I2C0_SDA_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_T" *) output I2C0_SDA_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_I" *) input I2C0_SCL_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_O" *) output I2C0_SCL_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_T" *) output I2C0_SCL_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *) input SDIO0_WP;
(* X_INTERFACE_INFO = "xilinx.com:interface:uart:1.0 UART_0 TxD" *) output UART0_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:uart:1.0 UART_0 RxD" *) input UART0_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) input [0:0]IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire [0:0]IRQ_F2P;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_WP;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire UART0_RX;
wire UART0_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
PULLUP pullup_MIO_0
(.O(MIO[0]));
PULLUP pullup_MIO_9
(.O(MIO[9]));
PULLUP pullup_MIO_10
(.O(MIO[10]));
PULLUP pullup_MIO_11
(.O(MIO[11]));
PULLUP pullup_MIO_12
(.O(MIO[12]));
PULLUP pullup_MIO_13
(.O(MIO[13]));
PULLUP pullup_MIO_14
(.O(MIO[14]));
PULLUP pullup_MIO_15
(.O(MIO[15]));
PULLUP pullup_MIO_46
(.O(MIO[46]));
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "0" *)
(* C_GP1_EN_MODIFIABLE_TXN = "0" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg400" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={} bidis={0} ioBank={} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(I2C0_SCL_I),
.I2C0_SCL_O(I2C0_SCL_O),
.I2C0_SCL_T(I2C0_SCL_T),
.I2C0_SDA_I(I2C0_SDA_I),
.I2C0_SDA_O(I2C0_SDA_O),
.I2C0_SDA_T(I2C0_SDA_T),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(IRQ_F2P),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(SDIO0_WP),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(UART0_RX),
.UART0_TX(UART0_TX),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "0" *) (* C_GP1_EN_MODIFIABLE_TXN = "0" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg400" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={3} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={UART} ioStandard={} bidis={0} ioBank={} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]M_AXI_GP1_ARCACHE;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]M_AXI_GP1_AWCACHE;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(M_AXI_GP0_AWCACHE),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(M_AXI_GP1_AWCACHE),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*------------------------------------------------------------------------------
Purpose
Pipeline: ñontrol sequence of instructions. All instructions have two stages:
1) Fetch;
2) Execute.
Branch instructions may have additional stage:
3) Memory issue instruction of branch address.
Memory instructions additional stages defined by Wishbone interface and
pipeline will be stallen (pl_stall_mem) until ending memory operation.
Multiply and divide instructions stall pipeline (pl_stall_multdiv) until
endinding of calculation.
------------------------------------------------------------------------------*/
module mips_pipeline (
input clk,
input rst,
input pl_stall_mem,
input pl_stall_branch,
input pl_stall_multdiv,
input pl_stall_eret,
input exception,
output[5:0] ifield_fstage_opcode,
output[4:0] ifield_fstage_d,
output[4:0] ifield_fstage_t,
output[4:0] ifield_fstage_s,
output[4:0] ifield_fstage_shift,
output[5:0] ifield_fstage_func,
input pmem_cmdok,
input[31:0] pmem_cmd,
input pmem_branch_ended,
input alu_multdiv_ready,
output reg pl_cause_bd,
output reg pl_pcpause
);
reg[31:0] pl_instr_fstage;
reg[31:0] pl_instr_fstage_d;
reg[1:0] cpu_state;
reg[1:0] cpu_state_d;
reg pl_pcpause_d;
reg instr_next;
reg instr_next_d;
reg pl_branch_excpt;
reg pl_branch_excpt_d;
reg branch_stall_was;
reg branch_stall_was_d;
localparam NORMAL= 2'b00,
STALL_BRANCH= 2'b01,
STALL_MEM= 2'b10,
STALL_MULTDIV= 2'b11;
assign ifield_fstage_opcode= pl_instr_fstage_d[31:26];
assign ifield_fstage_s= pl_instr_fstage_d[25:21];
assign ifield_fstage_t= pl_instr_fstage_d[20:16];
assign ifield_fstage_d= pl_instr_fstage_d[15:11];
assign ifield_fstage_shift= pl_instr_fstage_d[10:6];
assign ifield_fstage_func= pl_instr_fstage_d[5:0];
always @*
begin
pl_instr_fstage= pmem_cmd;
cpu_state= NORMAL;
instr_next= instr_next_d;
pl_pcpause= pl_pcpause_d;
branch_stall_was= branch_stall_was_d;
pl_cause_bd= 1'b0;
pl_branch_excpt= pl_branch_excpt_d;
case(cpu_state_d)
NORMAL:
begin
pl_pcpause= 1'b0;
branch_stall_was= 1'b0;
if(exception | ((pl_stall_eret | pl_stall_branch) & !pl_stall_mem))
begin
instr_next= !pmem_cmdok & !(pl_stall_eret | exception);
//DELAY SLOT HOW NOP
pl_instr_fstage= pl_stall_eret | exception | !pmem_cmdok ? 32'd0 :
pmem_cmd;
cpu_state= STALL_BRANCH;
end
else if(pl_stall_mem | pl_stall_multdiv)
begin
pl_pcpause= 1'b1;
pl_instr_fstage= pl_instr_fstage_d;
cpu_state= pl_stall_mem ? STALL_MEM : STALL_MULTDIV;
end
else if(!pmem_cmdok) pl_instr_fstage= 32'd0;
end
STALL_BRANCH:
begin
branch_stall_was= 1'b1;
if(pmem_cmdok)
begin
instr_next= 1'b0;
pl_branch_excpt= 1'b0;
end
if(exception | ((pl_stall_eret | pl_stall_branch) & !pl_stall_mem))
begin
pl_instr_fstage= 32'd0;
pl_cause_bd= 1'b1;
pl_branch_excpt= 1'b1;
cpu_state= STALL_BRANCH;
end
else if(pl_stall_mem | pl_stall_multdiv)
begin
pl_pcpause= 1'b1;
pl_instr_fstage= pl_instr_fstage_d;
cpu_state= pl_stall_mem ? STALL_MEM : STALL_MULTDIV;
end
else
begin
pl_instr_fstage= (instr_next_d | pmem_branch_ended) &
pmem_cmdok & !pl_branch_excpt_d ? pmem_cmd : 32'd0;
cpu_state= pmem_branch_ended & !pl_branch_excpt_d ? NORMAL : STALL_BRANCH;
end
end
STALL_MEM:
begin
if(exception | ((pl_stall_eret | pl_stall_branch) & !pl_stall_mem))
begin
pl_pcpause= 1'b0;
if(branch_stall_was_d) pl_cause_bd= 1'b1;
instr_next= !pmem_cmdok & !(pl_stall_eret | exception);
//DELAY SLOT HOW NOP
pl_instr_fstage= pl_stall_eret | exception | !pmem_cmdok ? 32'd0 :
pmem_cmd;
cpu_state= STALL_BRANCH;
end
else if(pl_stall_mem | pl_stall_multdiv)
begin
pl_pcpause= 1'b1;
pl_instr_fstage= pl_instr_fstage_d;
cpu_state= pl_stall_mem ? STALL_MEM : STALL_MULTDIV;
end
else
begin
pl_pcpause= 1'b0;
pl_instr_fstage= pmem_cmdok ? pmem_cmd : 32'd0;
end
end
STALL_MULTDIV:
begin
if(exception)
begin
if(branch_stall_was_d) pl_cause_bd= 1'b1;
instr_next= !pmem_cmdok & !(pl_stall_eret | exception);
//DELAY SLOT HOW NOP
pl_instr_fstage= pl_stall_eret | exception | !pmem_cmdok ? 32'd0 :
pmem_cmd;
cpu_state= STALL_BRANCH;
end
else
begin
if(!alu_multdiv_ready)
begin
pl_pcpause= 1'b1;
pl_instr_fstage= pl_instr_fstage_d;
cpu_state= STALL_MULTDIV;
end
else
begin
pl_pcpause= 1'b0;
pl_instr_fstage= pmem_cmdok ? pmem_cmd : 32'd0;
end
end
end
endcase
end
always @(posedge clk)
begin
if(rst)
begin
instr_next_d<= 1'b0;
pl_pcpause_d<= 1'b0;
pl_branch_excpt_d<= 1'b0;
branch_stall_was_d<= 1'b0;
pl_instr_fstage_d<= 32'd0;
cpu_state_d<= NORMAL;
end
else
begin
instr_next_d<= instr_next;
pl_pcpause_d<= pl_pcpause;
pl_branch_excpt_d<= pl_branch_excpt;
branch_stall_was_d<= branch_stall_was;
pl_instr_fstage_d<= pl_instr_fstage;
cpu_state_d<= cpu_state;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAH_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__FAH_BEHAVIORAL_PP_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAH_BEHAVIORAL_PP_V
|
extern "C" int Initialize(int num_of_cu, int iter);
extern "C" int getTotalWavefronts();
extern "C" int ScheduleWavefront();
extern "C" void DescheduleWavefront(int cuid, int wfTag);
extern "C" int getCuId();
//extern "C" int getWgId();
//extern "C" int getWfId();
extern "C" int getWfTag();
extern "C" int getWfCnt();
extern "C" int getWfNumThrds();
extern "C" int getVregBase();
extern "C" int getVregSize();
extern "C" int getSregBase();
extern "C" int getSregSize();
extern "C" int getLdsBase();
extern "C" int getLdsSize();
extern "C" int getSetVregs();
extern "C" int getVregKey(int index, int thrd);
extern "C" int getVregValue(int index, int thrd);
extern "C" int getSetSregs();
extern "C" int getSregKey(int index);
extern "C" int getSregValue(int index);
extern "C" void setVregValue(int cuid, int thrd, int vreg, int bitnum, int value);
extern "C" void setSregValue(int cuid, int sreg, int bitnum, int value);
extern "C" int getPC();
module gpu_tb();
parameter NUMOFCU = 1;
//parameter NUM_OF_ENTRIES_IMEM = 20; // number of entries to print
reg clk;
reg rst;
reg [15:0] ldssize;
reg [9:0] vregsize;
reg [8:0] sregsize;
reg[31:0] sregVal, vregVal;
integer cycle_count;
integer killtime;
integer clockperiod;
integer half_clockperiod;
integer deassert_reset;
integer m, n;
integer x, y, z;
integer thrds, setVregs, setSregs;
integer sregKey, vregKey;
integer cuid;
integer a;
integer wf_rem, iter, kern;
reg [(NUMOFCU-1):0] dispatch2cu_wf_dispatch;
reg [3:0] dispatch2cu_wg_wf_count;
reg [5:0] dispatch2cu_wf_size_dispatch;
reg [8:0] dispatch2cu_sgpr_base_dispatch;
reg [9:0] dispatch2cu_vgpr_base_dispatch;
reg [14:0] dispatch2cu_wf_tag_dispatch;
reg [15:0] dispatch2cu_lds_base_dispatch;
reg [31:0] dispatch2cu_start_pc_dispatch;
wire [(NUMOFCU - 1):0] mem2lsu_ack, buff2fetchwave_ack;
wire [(NUMOFCU*7 - 1):0] mem2lsu_tag_resp;
wire [(NUMOFCU*32 - 1):0] buff2wave_instr;
wire [(NUMOFCU*39 - 1):0] buff2wave_tag;
wire [31:0] mem2lsu_rd_data;
wire [NUMOFCU-1:0] cu2dispatch_wf_done, lsu2mem_gm_or_lds, fetch2buff_rd_en, issue2tracemon_barrier_retire_en,
issue2tracemon_waitcnt_retire_en, wave2decode_instr_valid, salu2sgpr_instr_done,
salu2exec_wr_exec_en, salu2exec_wr_vcc_en, salu2exec_wr_scc_en, salu2exec_wr_scc_value,
simd0_2vgpr_instr_done, simd1_2vgpr_instr_done, simd2_2vgpr_instr_done,
simd3_2vgpr_instr_done, simd0_2exec_wr_vcc_en, simd0_2vgpr_wr_en, simd1_2exec_wr_vcc_en,
simd1_2vgpr_wr_en, simd2_2exec_wr_vcc_en, simd2_2vgpr_wr_en, simd3_2exec_wr_vcc_en,
simd3_2vgpr_wr_en, simf0_2vgpr_instr_done, simf1_2vgpr_instr_done, simf2_2vgpr_instr_done,
simf3_2vgpr_instr_done, simf0_2exec_wr_vcc_en, simf0_2vgpr_wr_en, simf1_2exec_wr_vcc_en,
simf1_2vgpr_wr_en, simf2_2exec_wr_vcc_en, simf2_2vgpr_wr_en, simf3_2exec_wr_vcc_en,
simf3_2vgpr_wr_en, simd0_2sgpr_wr_en, simd1_2sgpr_wr_en, simd2_2sgpr_wr_en,
simd3_2sgpr_wr_en, simf0_2sgpr_wr_en, simf1_2sgpr_wr_en, simf2_2sgpr_wr_en,
simf3_2sgpr_wr_en, lsu2sgpr_instr_done, lsu2vgpr_instr_done, issue2fetchwave_wf_done_en,
salu2fetchwaveissue_branch_en, salu2fetchwaveissue_branch_taken, decode2tracemon_colldone,
decode2issue_valid, lsu2tracemon_gm_or_lds, fetch2tracemon_dispatch, lsu2tracemon_idle,
salu2exec_wr_m0_en, decode2issue_barrier;
wire [NUMOFCU*2 - 1:0] salu2tracemon_exec_word_sel, salu2tracemon_vcc_word_sel,
salu2sgpr_dest_wr_en;
wire [NUMOFCU*4 - 1:0] lsu2sgpr_dest_wr_en;
wire lsu2mem_rd_en, lsu2mem_wr_en, lsu2vgpr_dest_wr_en;
wire [NUMOFCU*6 - 1:0] issue2tracemon_waitcnt_retire_wfid, wave2decode_wfid, salu2sgpr_instr_done_wfid,
simd0_2vgpr_instr_done_wfid, simd1_2vgpr_instr_done_wfid, simd2_2vgpr_instr_done_wfid,
simd3_2vgpr_instr_done_wfid, simf0_2vgpr_instr_done_wfid, simf1_2vgpr_instr_done_wfid,
simf2_2vgpr_instr_done_wfid, simf3_2vgpr_instr_done_wfid, lsu2sgpr_instr_done_wfid,
lsu2vgpr_instr_done_wfid, issue2fetchwave_wf_done_wf_id, salu2fetchwaveissue_branch_wfid,
decode2issue_wfid, fetch2tracemon_new_wfid;
wire [NUMOFCU*7 - 1:0] lsu2mem_tag_req;
wire [NUMOFCU*9 - 1:0] wave2decode_sgpr_base, salu2sgpr_dest_addr, simd0_2sgpr_wr_addr,
simd1_2sgpr_wr_addr, simd2_2sgpr_wr_addr, simd3_2sgpr_wr_addr, simf0_2sgpr_wr_addr,
simf1_2sgpr_wr_addr, simf2_2sgpr_wr_addr, simf3_2sgpr_wr_addr, lsu2sgpr_dest_addr;
wire [NUMOFCU*10 - 1:0] wave2decode_vgpr_base, simd0_2vgpr_dest_addr, simd1_2vgpr_dest_addr,
simd2_2vgpr_dest_addr, simd3_2vgpr_dest_addr, simf0_2vgpr_dest_addr,
simf1_2vgpr_dest_addr, simf2_2vgpr_dest_addr, simf3_2vgpr_dest_addr,
lsu2vgpr_dest_addr;
wire [NUMOFCU*15 - 1:0] cu2dispatch_wf_tag_done, fetch2tracemon_wf_tag;
wire [NUMOFCU*16 - 1:0] wave2decode_lds_base, rfa2execvgprsgpr_select_fu;
wire [NUMOFCU*32 - 1:0] fetch2buff_addr, simd0_2tracemon_retire_pc, simd1_2tracemon_retire_pc,
simd2_2tracemon_retire_pc, simd3_2tracemon_retire_pc, simf0_2tracemon_retire_pc,
simf1_2tracemon_retire_pc, simf2_2tracemon_retire_pc, simf3_2tracemon_retire_pc,
salu2tracemon_retire_pc, lsu2tracemon_retire_pc, issue2tracemon_barrier_retire_pc,
issue2tracemon_waitcnt_retire_pc, salu2fetch_branch_pc_value, decode2issue_instr_pc,
salu2exec_wr_m0_value;
wire [NUMOFCU*39 - 1:0] fetch2buff_tag;
wire [NUMOFCU*40 - 1:0] issue2tracemon_barrier_retire_wf_bitmap;
wire [NUMOFCU*64 - 1:0] lsu2mem_wr_mask, salu2exec_wr_exec_value, salu2exec_wr_vcc_value,
salu2sgpr_dest_data, simd0_2exec_wr_vcc_value, simd0_2vgpr_wr_mask,
simd1_2exec_wr_vcc_value, simd1_2vgpr_wr_mask, simd2_2exec_wr_vcc_value,
simd2_2vgpr_wr_mask, simd3_2exec_wr_vcc_value, simd3_2vgpr_wr_mask,
simf0_2exec_wr_vcc_value, simf0_2vgpr_wr_mask, simf1_2exec_wr_vcc_value,
simf1_2vgpr_wr_mask, simf2_2exec_wr_vcc_value, simf2_2vgpr_wr_mask,
simf3_2exec_wr_vcc_value, simf3_2vgpr_wr_mask, simd0_2sgpr_wr_data,
simd1_2sgpr_wr_data, simd2_2sgpr_wr_data, simd3_2sgpr_wr_data, simf0_2sgpr_wr_data,
simf1_2sgpr_wr_data, simf2_2sgpr_wr_data, simf3_2sgpr_wr_data, lsu2vgpr_dest_wr_mask,
decode2tracemon_collinstr;
wire [NUMOFCU*128 - 1:0] lsu2sgpr_dest_data;
wire [NUMOFCU*2048 - 1:0] simd0_2vgpr_dest_data, simd1_2vgpr_dest_data,
simd2_2vgpr_dest_data, simd3_2vgpr_dest_data, simf0_2vgpr_dest_data,
simf1_2vgpr_dest_data, simf2_2vgpr_dest_data, simf3_2vgpr_dest_data;
wire [31:0] lsu2mem_wr_data,lsu2mem_addr;
wire [2047:0] lsu2vgpr_dest_data;
// signals not a part of compute unit
// from memory to tracemon
wire [NUMOFCU*4 - 1:0] mem2tracemon_store_en;
wire [NUMOFCU*2048 - 1:0] mem2tracemon_addr;
wire [NUMOFCU*2048 - 1:0] mem2tracemon_store_data;
compute_unit DUT[(NUMOFCU-1):0] (
.dispatch2cu_wf_dispatch(dispatch2cu_wf_dispatch),
.dispatch2cu_wf_tag_dispatch(dispatch2cu_wf_tag_dispatch),
.dispatch2cu_start_pc_dispatch(dispatch2cu_start_pc_dispatch),
.dispatch2cu_vgpr_base_dispatch(dispatch2cu_vgpr_base_dispatch),
.dispatch2cu_sgpr_base_dispatch(dispatch2cu_sgpr_base_dispatch),
.dispatch2cu_lds_base_dispatch(dispatch2cu_lds_base_dispatch),
.dispatch2cu_wf_size_dispatch(dispatch2cu_wf_size_dispatch),
.dispatch2cu_wg_wf_count(dispatch2cu_wg_wf_count),
.mem2lsu_rd_data(mem2lsu_rd_data),
.mem2lsu_tag_resp(mem2lsu_tag_resp),
.mem2lsu_ack(mem2lsu_ack),
.buff2fetchwave_ack(buff2fetchwave_ack),
.buff2wave_instr(buff2wave_instr),
.buff2wave_tag(buff2wave_tag),
.cu2dispatch_wf_tag_done(cu2dispatch_wf_tag_done),
.cu2dispatch_wf_done(cu2dispatch_wf_done),
.lsu2mem_rd_en(lsu2mem_rd_en),
.lsu2mem_wr_en(lsu2mem_wr_en),
.lsu2mem_addr(lsu2mem_addr),
.lsu2mem_wr_data(lsu2mem_wr_data),
.lsu2mem_tag_req(lsu2mem_tag_req),
.lsu2mem_wr_mask(lsu2mem_wr_mask),
.lsu2mem_gm_or_lds(lsu2mem_gm_or_lds),
.fetch2buff_rd_en(fetch2buff_rd_en),
.fetch2buff_addr(fetch2buff_addr),
.fetch2buff_tag(fetch2buff_tag),
.simd0_2tracemon_retire_pc(simd0_2tracemon_retire_pc),
.simd1_2tracemon_retire_pc(simd1_2tracemon_retire_pc),
.simd2_2tracemon_retire_pc(simd2_2tracemon_retire_pc),
.simd3_2tracemon_retire_pc(simd3_2tracemon_retire_pc),
.simf0_2tracemon_retire_pc(simf0_2tracemon_retire_pc),
.simf1_2tracemon_retire_pc(simf1_2tracemon_retire_pc),
.simf2_2tracemon_retire_pc(simf2_2tracemon_retire_pc),
.simf3_2tracemon_retire_pc(simf3_2tracemon_retire_pc),
.salu2tracemon_retire_pc(salu2tracemon_retire_pc),
.salu2tracemon_exec_word_sel(salu2tracemon_exec_word_sel),
.salu2tracemon_vcc_word_sel(salu2tracemon_vcc_word_sel),
.lsu2tracemon_retire_pc(lsu2tracemon_retire_pc),
//.lsu2tracemon_addr(mem2tracemon_addr),
.lsu2tracemon_store_data(mem2tracemon_store_data),
.lsu2tracemon_idle(lsu2tracemon_idle),
.issue2tracemon_barrier_retire_en(issue2tracemon_barrier_retire_en),
.issue2tracemon_barrier_retire_wf_bitmap(issue2tracemon_barrier_retire_wf_bitmap),
.issue2tracemon_barrier_retire_pc(issue2tracemon_barrier_retire_pc),
.issue2tracemon_waitcnt_retire_en(issue2tracemon_waitcnt_retire_en),
.issue2tracemon_waitcnt_retire_wfid(issue2tracemon_waitcnt_retire_wfid),
.issue2tracemon_waitcnt_retire_pc(issue2tracemon_waitcnt_retire_pc),
.wave2decode_instr_valid(wave2decode_instr_valid),
.wave2decode_sgpr_base(wave2decode_sgpr_base),
.wave2decode_vgpr_base(wave2decode_vgpr_base),
.wave2decode_lds_base(wave2decode_lds_base),
.wave2decode_wfid(wave2decode_wfid),
.salu2sgpr_instr_done(salu2sgpr_instr_done),
.salu2sgpr_instr_done_wfid(salu2sgpr_instr_done_wfid),
.salu2exec_wr_exec_en(salu2exec_wr_exec_en),
.salu2exec_wr_exec_value(salu2exec_wr_exec_value),
.salu2exec_wr_vcc_en(salu2exec_wr_vcc_en),
.salu2exec_wr_vcc_value(salu2exec_wr_vcc_value),
.salu2exec_wr_scc_en(salu2exec_wr_scc_en),
.salu2exec_wr_scc_value(salu2exec_wr_scc_value),
.salu2sgpr_dest_wr_en(salu2sgpr_dest_wr_en),
.salu2sgpr_dest_addr(salu2sgpr_dest_addr),
.salu2sgpr_dest_data(salu2sgpr_dest_data),
.simd0_2vgpr_instr_done(simd0_2vgpr_instr_done),
.simd0_2vgpr_instr_done_wfid(simd0_2vgpr_instr_done_wfid),
.simd1_2vgpr_instr_done(simd1_2vgpr_instr_done),
.simd1_2vgpr_instr_done_wfid(simd1_2vgpr_instr_done_wfid),
.simd2_2vgpr_instr_done(simd2_2vgpr_instr_done),
.simd2_2vgpr_instr_done_wfid(simd2_2vgpr_instr_done_wfid),
.simd3_2vgpr_instr_done(simd3_2vgpr_instr_done),
.simd3_2vgpr_instr_done_wfid(simd3_2vgpr_instr_done_wfid),
.simd0_2exec_wr_vcc_en(simd0_2exec_wr_vcc_en),
.simd0_2exec_wr_vcc_value(simd0_2exec_wr_vcc_value),
.simd0_2vgpr_wr_en(simd0_2vgpr_wr_en),
.simd0_2vgpr_dest_addr(simd0_2vgpr_dest_addr),
.simd0_2vgpr_dest_data(simd0_2vgpr_dest_data),
.simd0_2vgpr_wr_mask(simd0_2vgpr_wr_mask),
.simd1_2exec_wr_vcc_en(simd1_2exec_wr_vcc_en),
.simd1_2exec_wr_vcc_value(simd1_2exec_wr_vcc_value),
.simd1_2vgpr_wr_en(simd1_2vgpr_wr_en),
.simd1_2vgpr_dest_addr(simd1_2vgpr_dest_addr),
.simd1_2vgpr_dest_data(simd1_2vgpr_dest_data),
.simd1_2vgpr_wr_mask(simd1_2vgpr_wr_mask),
.simd2_2exec_wr_vcc_en(simd2_2exec_wr_vcc_en),
.simd2_2exec_wr_vcc_value(simd2_2exec_wr_vcc_value),
.simd2_2vgpr_wr_en(simd2_2vgpr_wr_en),
.simd2_2vgpr_dest_addr(simd2_2vgpr_dest_addr),
.simd2_2vgpr_dest_data(simd2_2vgpr_dest_data),
.simd2_2vgpr_wr_mask(simd2_2vgpr_wr_mask),
.simd3_2exec_wr_vcc_en(simd3_2exec_wr_vcc_en),
.simd3_2exec_wr_vcc_value(simd3_2exec_wr_vcc_value),
.simd3_2vgpr_wr_en(simd3_2vgpr_wr_en),
.simd3_2vgpr_dest_addr(simd3_2vgpr_dest_addr),
.simd3_2vgpr_dest_data(simd3_2vgpr_dest_data),
.simd3_2vgpr_wr_mask(simd3_2vgpr_wr_mask),
.simf0_2vgpr_instr_done(simf0_2vgpr_instr_done),
.simf0_2vgpr_instr_done_wfid(simf0_2vgpr_instr_done_wfid),
.simf1_2vgpr_instr_done(simf1_2vgpr_instr_done),
.simf1_2vgpr_instr_done_wfid(simf1_2vgpr_instr_done_wfid),
.simf2_2vgpr_instr_done(simf2_2vgpr_instr_done),
.simf2_2vgpr_instr_done_wfid(simf2_2vgpr_instr_done_wfid),
.simf3_2vgpr_instr_done(simf3_2vgpr_instr_done),
.simf3_2vgpr_instr_done_wfid(simf3_2vgpr_instr_done_wfid),
.simf0_2exec_wr_vcc_en(simf0_2exec_wr_vcc_en),
.simf0_2exec_wr_vcc_value(simf0_2exec_wr_vcc_value),
.simf0_2vgpr_wr_en(simf0_2vgpr_wr_en),
.simf0_2vgpr_dest_addr(simf0_2vgpr_dest_addr),
.simf0_2vgpr_dest_data(simf0_2vgpr_dest_data),
.simf0_2vgpr_wr_mask(simf0_2vgpr_wr_mask),
.simf1_2exec_wr_vcc_en(simf1_2exec_wr_vcc_en),
.simf1_2exec_wr_vcc_value(simf1_2exec_wr_vcc_value),
.simf1_2vgpr_wr_en(simf1_2vgpr_wr_en),
.simf1_2vgpr_dest_addr(simf1_2vgpr_dest_addr),
.simf1_2vgpr_dest_data(simf1_2vgpr_dest_data),
.simf1_2vgpr_wr_mask(simf1_2vgpr_wr_mask),
.simf2_2exec_wr_vcc_en(simf2_2exec_wr_vcc_en),
.simf2_2exec_wr_vcc_value(simf2_2exec_wr_vcc_value),
.simf2_2vgpr_wr_en(simf2_2vgpr_wr_en),
.simf2_2vgpr_dest_addr(simf2_2vgpr_dest_addr),
.simf2_2vgpr_dest_data(simf2_2vgpr_dest_data),
.simf2_2vgpr_wr_mask(simf2_2vgpr_wr_mask),
.simf3_2exec_wr_vcc_en(simf3_2exec_wr_vcc_en),
.simf3_2exec_wr_vcc_value(simf3_2exec_wr_vcc_value),
.simf3_2vgpr_wr_en(simf3_2vgpr_wr_en),
.simf3_2vgpr_dest_addr(simf3_2vgpr_dest_addr),
.simf3_2vgpr_dest_data(simf3_2vgpr_dest_data),
.simf3_2vgpr_wr_mask(simf3_2vgpr_wr_mask),
.simd0_2sgpr_wr_addr(simd0_2sgpr_wr_addr),
.simd0_2sgpr_wr_en(simd0_2sgpr_wr_en),
.simd0_2sgpr_wr_data(simd0_2sgpr_wr_data),
.simd1_2sgpr_wr_addr(simd1_2sgpr_wr_addr),
.simd1_2sgpr_wr_en(simd1_2sgpr_wr_en),
.simd1_2sgpr_wr_data(simd1_2sgpr_wr_data),
.simd2_2sgpr_wr_addr(simd2_2sgpr_wr_addr),
.simd2_2sgpr_wr_en(simd2_2sgpr_wr_en),
.simd2_2sgpr_wr_data(simd2_2sgpr_wr_data),
.simd3_2sgpr_wr_addr(simd3_2sgpr_wr_addr),
.simd3_2sgpr_wr_en(simd3_2sgpr_wr_en),
.simd3_2sgpr_wr_data(simd3_2sgpr_wr_data),
.simf0_2sgpr_wr_addr(simf0_2sgpr_wr_addr),
.simf0_2sgpr_wr_en(simf0_2sgpr_wr_en),
.simf0_2sgpr_wr_data(simf0_2sgpr_wr_data),
.simf1_2sgpr_wr_addr(simf1_2sgpr_wr_addr),
.simf1_2sgpr_wr_en(simf1_2sgpr_wr_en),
.simf1_2sgpr_wr_data(simf1_2sgpr_wr_data),
.simf2_2sgpr_wr_addr(simf2_2sgpr_wr_addr),
.simf2_2sgpr_wr_en(simf2_2sgpr_wr_en),
.simf2_2sgpr_wr_data(simf2_2sgpr_wr_data),
.simf3_2sgpr_wr_addr(simf3_2sgpr_wr_addr),
.simf3_2sgpr_wr_en(simf3_2sgpr_wr_en),
.simf3_2sgpr_wr_data(simf3_2sgpr_wr_data),
.lsu2sgpr_instr_done(lsu2sgpr_instr_done),
.lsu2sgpr_instr_done_wfid(lsu2sgpr_instr_done_wfid),
.lsu2sgpr_dest_wr_en(lsu2sgpr_dest_wr_en),
.lsu2sgpr_dest_addr(lsu2sgpr_dest_addr),
.lsu2sgpr_dest_data(lsu2sgpr_dest_data),
.lsu2vgpr_instr_done(lsu2vgpr_instr_done),
.lsu2vgpr_dest_data(lsu2vgpr_dest_data),
.lsu2vgpr_dest_addr(lsu2vgpr_dest_addr),
.lsu2vgpr_dest_wr_mask(lsu2vgpr_dest_wr_mask),
.lsu2vgpr_instr_done_wfid(lsu2vgpr_instr_done_wfid),
.lsu2vgpr_dest_wr_en(lsu2vgpr_dest_wr_en),
.issue2fetchwave_wf_done_en(issue2fetchwave_wf_done_en),
.issue2fetchwave_wf_done_wf_id(issue2fetchwave_wf_done_wf_id),
.salu2fetchwaveissue_branch_wfid(salu2fetchwaveissue_branch_wfid),
.salu2fetchwaveissue_branch_en(salu2fetchwaveissue_branch_en),
.salu2fetchwaveissue_branch_taken(salu2fetchwaveissue_branch_taken),
.salu2fetch_branch_pc_value(salu2fetch_branch_pc_value),
.rfa2execvgprsgpr_select_fu(rfa2execvgprsgpr_select_fu),
.decode2tracemon_collinstr(decode2tracemon_collinstr),
.decode2tracemon_colldone(decode2tracemon_colldone),
.decode2issue_valid(decode2issue_valid),
.decode2issue_instr_pc(decode2issue_instr_pc),
.decode2issue_wfid(decode2issue_wfid),
.lsu2tracemon_gm_or_lds(lsu2tracemon_gm_or_lds),
.fetch2tracemon_dispatch(fetch2tracemon_dispatch),
.fetch2tracemon_wf_tag(fetch2tracemon_wf_tag),
.fetch2tracemon_new_wfid(fetch2tracemon_new_wfid),
.salu2exec_wr_m0_en(salu2exec_wr_m0_en),
.salu2exec_wr_m0_value(salu2exec_wr_m0_value),
.decode2issue_barrier(decode2issue_barrier),
.clk(clk),
.rst(rst)
);
instr_buffer #(.NUMOFCU(NUMOFCU)) instr_buffer0 (
// Instruction buffer - modeled by the testbench.
.clk(clk),
.rst(rst),
// Inputs
.fetch_rd_en(fetch2buff_rd_en),
.fetch_addr(fetch2buff_addr),
.fetch_tag(fetch2buff_tag),
// Outputs
.fetchwave_ack(buff2fetchwave_ack),
.wave_instr(buff2wave_instr),
.wave_tag(buff2wave_tag)
);
memory #(.NUMOFCU(NUMOFCU)) memory0 (
// Memory module - will be implemented by the testbench
.clk(clk),
.rst(rst),
// Inputs
.gm_or_lds(lsu2mem_gm_or_lds),
.rd_en(lsu2mem_rd_en),
.wr_en(lsu2mem_wr_en),
.addresses(lsu2mem_addr),
.wr_data(lsu2mem_wr_data),
.input_tag(lsu2mem_tag_req),
//.wr_mask(lsu2mem_wr_mask),
// Outputs
.rd_data(mem2lsu_rd_data),
.output_tag(mem2lsu_tag_resp),
.ack(mem2lsu_ack)
//.tracemon_addr(mem2tracemon_addr),
//.tracemon_store_data(mem2tracemon_store_data),
//.tracemon_store_en(mem2tracemon_store_en)
);
// initial begin
// //$monitor("read happened %b", lsu2mem_rd_en);
// //$monitor("write happened %b", lsu2mem_wr_en);
// //$monitor("retire happened %b", DUT[0].lsu0.mem_ctrl.retire);
// //$monitor("sgpr happened %b", DUT[0].lsu0.sgpr_dest_wr_en);
// $monitor("sgpr addr %b", DUT[0].lsu0.sgpr_dest_addr);
// end
initial begin
//$monitor("read happened %b", lsu2mem_rd_en);
//$monitor("write happened %b", lsu2mem_wr_en);
//$monitor("retire happened %b", DUT[0].lsu0.mem_ctrl.retire);
//$monitor("sgpr happened %b", DUT[0].lsu0.sgpr_dest_wr_en);
//$monitor("sgpr data %h", DUT[0].lsu0.flops_mem_wb.flop_rd_data);
//$monitor("sgpr addr %h", DUT[0].lsu2mem_addr);
//$monitor("exec addr %h", DUT[0].lsu0.exec_exec_value);
//$monitor("sgpr addr %h", DUT[0].lsu0.addr_calc.out_ld_st_addr);
//$monitor("sgpr data %h", DUT[0].lsu0.flops_mem_wb.flop_rd_data);
end
//SAIF flow
`ifdef SAIF
initial begin
$set_gate_level_monitoring("rtl_on", "mda");
$set_toggle_region(gpu_tb.DUT[0]);
#0;
$toggle_start;
end
`endif
//waveforms
initial begin
if ($test$plusargs("dump_waveforms")) begin
$vcdpluson(0,gpu_tb);
if ($test$plusargs("dump_glitches")) begin
$vcdplusdeltacycleon;
$vcdplusglitchon;
end
end
end
genvar tg;
generate
for (tg=0; tg < NUMOFCU; tg=tg+1) begin : TT
tracemon #(.CUID(tg)) tracemon0 (
// Dummy unit to aid testbench
.issue2tracemon_barrier_retire_en(issue2tracemon_barrier_retire_en),
.issue2tracemon_barrier_retire_wf_bitmap(issue2tracemon_barrier_retire_wf_bitmap),
.issue2tracemon_barrier_retire_pc(issue2tracemon_barrier_retire_pc),
.issue2tracemon_waitcnt_retire_en(issue2tracemon_waitcnt_retire_en),
.issue2tracemon_waitcnt_retire_wfid(issue2tracemon_waitcnt_retire_wfid),
.issue2tracemon_waitcnt_retire_pc(issue2tracemon_waitcnt_retire_pc),
.simd0_2tracemon_retire_pc(simd0_2tracemon_retire_pc),
.simd1_2tracemon_retire_pc(simd1_2tracemon_retire_pc),
.simd2_2tracemon_retire_pc(simd2_2tracemon_retire_pc),
.simd3_2tracemon_retire_pc(simd3_2tracemon_retire_pc),
.simf0_2tracemon_retire_pc(simf0_2tracemon_retire_pc),
.simf1_2tracemon_retire_pc(simf1_2tracemon_retire_pc),
.simf2_2tracemon_retire_pc(simf2_2tracemon_retire_pc),
.simf3_2tracemon_retire_pc(simf3_2tracemon_retire_pc),
.lsu2mem_rd_en(lsu2mem_rd_en),
.lsu2mem_wr_en(lsu2mem_wr_en),
.lsu2tracemon_retire_pc(lsu2tracemon_retire_pc),
.salu2tracemon_retire_pc(salu2tracemon_retire_pc),
.salu2tracemon_exec_word_sel(salu2tracemon_exec_word_sel),
.salu2tracemon_vcc_word_sel(salu2tracemon_vcc_word_sel),
.wave2decode_instr_valid(wave2decode_instr_valid),
.wave2decode_sgpr_base(wave2decode_sgpr_base),
.wave2decode_vgpr_base(wave2decode_vgpr_base),
.wave2decode_lds_base(wave2decode_lds_base),
.wave2decode_wfid(wave2decode_wfid),
.salu2sgpr_instr_done(salu2sgpr_instr_done),
.salu2sgpr_instr_done_wfid(salu2sgpr_instr_done_wfid),
.salu2exec_wr_exec_en(salu2exec_wr_exec_en),
.salu2exec_wr_exec_value(salu2exec_wr_exec_value),
.salu2exec_wr_vcc_en(salu2exec_wr_vcc_en),
.salu2exec_wr_vcc_value(salu2exec_wr_vcc_value),
.salu2exec_wr_scc_en(salu2exec_wr_scc_en),
.salu2exec_wr_scc_value(salu2exec_wr_scc_value),
.salu2sgpr_dest_wr_en(salu2sgpr_dest_wr_en),
.salu2sgpr_dest_addr(salu2sgpr_dest_addr),
.salu2sgpr_dest_data(salu2sgpr_dest_data),
.salu2fetchwaveissue_branch_wfid(salu2fetchwaveissue_branch_wfid),
.salu2fetchwaveissue_branch_en(salu2fetchwaveissue_branch_en),
.salu2fetchwaveissue_branch_taken(salu2fetchwaveissue_branch_taken),
.salu2fetch_branch_pc_value(salu2fetch_branch_pc_value),
.simd0_2vgpr_instr_done(simd0_2vgpr_instr_done),
.simd0_2vgpr_instr_done_wfid(simd0_2vgpr_instr_done_wfid),
.simd1_2vgpr_instr_done(simd1_2vgpr_instr_done),
.simd1_2vgpr_instr_done_wfid(simd1_2vgpr_instr_done_wfid),
.simd2_2vgpr_instr_done(simd2_2vgpr_instr_done),
.simd2_2vgpr_instr_done_wfid(simd2_2vgpr_instr_done_wfid),
.simd3_2vgpr_instr_done(simd3_2vgpr_instr_done),
.simd3_2vgpr_instr_done_wfid(simd3_2vgpr_instr_done_wfid),
.simd0_2exec_wr_vcc_en(simd0_2exec_wr_vcc_en),
.simd0_2exec_wr_vcc_value(simd0_2exec_wr_vcc_value),
.simd0_2vgpr_wr_en(simd0_2vgpr_wr_en),
.simd0_2vgpr_dest_addr(simd0_2vgpr_dest_addr),
.simd0_2vgpr_dest_data(simd0_2vgpr_dest_data),
.simd0_2vgpr_wr_mask(simd0_2vgpr_wr_mask),
.simd1_2exec_wr_vcc_en(simd1_2exec_wr_vcc_en),
.simd1_2exec_wr_vcc_value(simd1_2exec_wr_vcc_value),
.simd1_2vgpr_wr_en(simd1_2vgpr_wr_en),
.simd1_2vgpr_dest_addr(simd1_2vgpr_dest_addr),
.simd1_2vgpr_dest_data(simd1_2vgpr_dest_data),
.simd1_2vgpr_wr_mask(simd1_2vgpr_wr_mask),
.simd2_2exec_wr_vcc_en(simd2_2exec_wr_vcc_en),
.simd2_2exec_wr_vcc_value(simd2_2exec_wr_vcc_value),
.simd2_2vgpr_wr_en(simd2_2vgpr_wr_en),
.simd2_2vgpr_dest_addr(simd2_2vgpr_dest_addr),
.simd2_2vgpr_dest_data(simd2_2vgpr_dest_data),
.simd2_2vgpr_wr_mask(simd2_2vgpr_wr_mask),
.simd3_2exec_wr_vcc_en(simd3_2exec_wr_vcc_en),
.simd3_2exec_wr_vcc_value(simd3_2exec_wr_vcc_value),
.simd3_2vgpr_wr_en(simd3_2vgpr_wr_en),
.simd3_2vgpr_dest_addr(simd3_2vgpr_dest_addr),
.simd3_2vgpr_dest_data(simd3_2vgpr_dest_data),
.simd3_2vgpr_wr_mask(simd3_2vgpr_wr_mask),
.simf0_2vgpr_instr_done(simf0_2vgpr_instr_done),
.simf0_2vgpr_instr_done_wfid(simf0_2vgpr_instr_done_wfid),
.simf1_2vgpr_instr_done(simf1_2vgpr_instr_done),
.simf1_2vgpr_instr_done_wfid(simf1_2vgpr_instr_done_wfid),
.simf2_2vgpr_instr_done(simf2_2vgpr_instr_done),
.simf2_2vgpr_instr_done_wfid(simf2_2vgpr_instr_done_wfid),
.simf3_2vgpr_instr_done(simf3_2vgpr_instr_done),
.simf3_2vgpr_instr_done_wfid(simf3_2vgpr_instr_done_wfid),
.simf0_2exec_wr_vcc_en(simf0_2exec_wr_vcc_en),
.simf0_2exec_wr_vcc_value(simf0_2exec_wr_vcc_value),
.simf0_2vgpr_wr_en(simf0_2vgpr_wr_en),
.simf0_2vgpr_dest_addr(simf0_2vgpr_dest_addr),
.simf0_2vgpr_dest_data(simf0_2vgpr_dest_data),
.simf0_2vgpr_wr_mask(simf0_2vgpr_wr_mask),
.simf1_2exec_wr_vcc_en(simf1_2exec_wr_vcc_en),
.simf1_2exec_wr_vcc_value(simf1_2exec_wr_vcc_value),
.simf1_2vgpr_wr_en(simf1_2vgpr_wr_en),
.simf1_2vgpr_dest_addr(simf1_2vgpr_dest_addr),
.simf1_2vgpr_dest_data(simf1_2vgpr_dest_data),
.simf1_2vgpr_wr_mask(simf1_2vgpr_wr_mask),
.simf2_2exec_wr_vcc_en(simf2_2exec_wr_vcc_en),
.simf2_2exec_wr_vcc_value(simf2_2exec_wr_vcc_value),
.simf2_2vgpr_wr_en(simf2_2vgpr_wr_en),
.simf2_2vgpr_dest_addr(simf2_2vgpr_dest_addr),
.simf2_2vgpr_dest_data(simf2_2vgpr_dest_data),
.simf2_2vgpr_wr_mask(simf2_2vgpr_wr_mask),
.simf3_2exec_wr_vcc_en(simf3_2exec_wr_vcc_en),
.simf3_2exec_wr_vcc_value(simf3_2exec_wr_vcc_value),
.simf3_2vgpr_wr_en(simf3_2vgpr_wr_en),
.simf3_2vgpr_dest_addr(simf3_2vgpr_dest_addr),
.simf3_2vgpr_dest_data(simf3_2vgpr_dest_data),
.simf3_2vgpr_wr_mask(simf3_2vgpr_wr_mask),
.simd0_2sgpr_wr_addr(simd0_2sgpr_wr_addr),
.simd0_2sgpr_wr_en(simd0_2sgpr_wr_en),
.simd0_2sgpr_wr_data(simd0_2sgpr_wr_data),
.simd1_2sgpr_wr_addr(simd1_2sgpr_wr_addr),
.simd1_2sgpr_wr_en(simd1_2sgpr_wr_en),
.simd1_2sgpr_wr_data(simd1_2sgpr_wr_data),
.simd2_2sgpr_wr_addr(simd2_2sgpr_wr_addr),
.simd2_2sgpr_wr_en(simd2_2sgpr_wr_en),
.simd2_2sgpr_wr_data(simd2_2sgpr_wr_data),
.simd3_2sgpr_wr_addr(simd3_2sgpr_wr_addr),
.simd3_2sgpr_wr_en(simd3_2sgpr_wr_en),
.simd3_2sgpr_wr_data(simd3_2sgpr_wr_data),
.simf0_2sgpr_wr_addr(simf0_2sgpr_wr_addr),
.simf0_2sgpr_wr_en(simf0_2sgpr_wr_en),
.simf0_2sgpr_wr_data(simf0_2sgpr_wr_data),
.simf1_2sgpr_wr_addr(simf1_2sgpr_wr_addr),
.simf1_2sgpr_wr_en(simf1_2sgpr_wr_en),
.simf1_2sgpr_wr_data(simf1_2sgpr_wr_data),
.simf2_2sgpr_wr_addr(simf2_2sgpr_wr_addr),
.simf2_2sgpr_wr_en(simf2_2sgpr_wr_en),
.simf2_2sgpr_wr_data(simf2_2sgpr_wr_data),
.simf3_2sgpr_wr_addr(simf3_2sgpr_wr_addr),
.simf3_2sgpr_wr_en(simf3_2sgpr_wr_en),
.simf3_2sgpr_wr_data(simf3_2sgpr_wr_data),
.lsu2sgpr_instr_done(lsu2sgpr_instr_done),
.lsu2sgpr_instr_done_wfid(lsu2sgpr_instr_done_wfid),
.lsu2sgpr_dest_wr_en(lsu2sgpr_dest_wr_en),
.lsu2sgpr_dest_addr(lsu2sgpr_dest_addr),
.lsu2sgpr_dest_data(lsu2sgpr_dest_data),
.lsu2vgpr_instr_done(lsu2vgpr_instr_done),
.lsu2vgpr_dest_data(lsu2vgpr_dest_data),
.lsu2vgpr_dest_addr(lsu2vgpr_dest_addr),
.lsu2vgpr_dest_wr_mask(lsu2vgpr_dest_wr_mask),
.lsu2vgpr_instr_done_wfid(lsu2vgpr_instr_done_wfid),
.lsu2vgpr_dest_wr_en(lsu2vgpr_dest_wr_en),
.issue2fetchwave_wf_done_en(issue2fetchwave_wf_done_en),
.issue2fetchwave_wf_done_wf_id(issue2fetchwave_wf_done_wf_id),
//.mem2tracemon_addr(mem2tracemon_addr),lsu2mem_addr
.mem2tracemon_addr(lsu2mem_addr),
.mem2tracemon_store_data(mem2tracemon_store_data),
.mem2tracemon_store_en(mem2tracemon_store_en),
.decode2tracemon_collinstr(decode2tracemon_collinstr),
.decode2tracemon_colldone(decode2tracemon_colldone),
.decode2issue_instr_pc(decode2issue_instr_pc),
.decode2issue_valid(decode2issue_valid),
.decode2issue_wfid(decode2issue_wfid),
.rfa2execvgprsgpr_select_fu(rfa2execvgprsgpr_select_fu),
.lsu2tracemon_gm_or_lds(lsu2tracemon_gm_or_lds),
.lsu2tracemon_idle(lsu2tracemon_idle),
.fetch2tracemon_dispatch(fetch2tracemon_dispatch),
.fetch2tracemon_wf_tag(fetch2tracemon_wf_tag),
.fetch2tracemon_new_wfid(fetch2tracemon_new_wfid),
.salu2exec_wr_m0_en(salu2exec_wr_m0_en),
.salu2exec_wr_m0_value(salu2exec_wr_m0_value),
.decode2issue_barrier(decode2issue_barrier),
.clk(clk),
.rst(rst),
.kernel_id(iter-1)
);
end
endgenerate
//genvar pg;
//generate
// for (pg=0; pg < NUMOFCU; pg=pg+1) begin : PT
// profiler #(.CUID(pg)) profiler0 (
// // unit to aid in profiling
// .salu2sgpr_instr_done(salu2sgpr_instr_done),
// .salu2fetchwaveissue_branch_en(salu2fetchwaveissue_branch_en),
// .simd0_2vgpr_instr_done(DUT[pg].simd0_2rfa_queue_entry_valid),
// .simd1_2vgpr_instr_done(DUT[pg].simd1_2rfa_queue_entry_valid),
// .simd2_2vgpr_instr_done(DUT[pg].simd2_2rfa_queue_entry_valid),
// .simd3_2vgpr_instr_done(DUT[pg].simd3_2rfa_queue_entry_valid),
// .simf0_2vgpr_instr_done(DUT[pg].simf0_2rfa_queue_entry_valid),
// .simf1_2vgpr_instr_done(DUT[pg].simf1_2rfa_queue_entry_valid),
// .simf2_2vgpr_instr_done(DUT[pg].simf2_2rfa_queue_entry_valid),
// .simf3_2vgpr_instr_done(DUT[pg].simf3_2rfa_queue_entry_valid),
// .rfa2execvgprsgpr_select_fu(rfa2execvgprsgpr_select_fu),
// .lsu2vgpr_instr_done(lsu2vgpr_instr_done),
// .lsu2sgpr_instr_done(lsu2sgpr_instr_done),
// .salu_alu_select(DUT[pg].issue2salu_alu_select),
// .simd0_alu_select(DUT[pg].issue2simd0_alu_select),
// .simd1_alu_select(DUT[pg].issue2simd1_alu_select),
// .simd2_alu_select(DUT[pg].issue2simd2_alu_select),
// .simd3_alu_select(DUT[pg].issue2simd3_alu_select),
// .simf0_alu_select(DUT[pg].issue2simf0_alu_select),
// .simf1_alu_select(DUT[pg].issue2simf1_alu_select),
// .simf2_alu_select(DUT[pg].issue2simf2_alu_select),
// .simf3_alu_select(DUT[pg].issue2simf3_alu_select),
// .lsu_select(DUT[pg].issue2lsu_lsu_select),
// .clk(clk)
// );
// end
//endgenerate
initial begin
$display("Starting");
cycle_count = 0;
//instr_count = 0;
end
initial begin
clk = 0;
while (1) begin
`ifdef GATES
$value$plusargs("CLOCKPERIOD=%d",clockperiod);
half_clockperiod = clockperiod / 2;
deassert_reset = (clockperiod * 12) + half_clockperiod + (half_clockperiod / 2);
#half_clockperiod;
if(clk == 1'b0)
begin
$display("GATES MONITOR %m : Posedge of CLK at time %t", $time);
end
`else
#2; //Period is 4 clock ticks or 4ns for rtl
`endif
clk = ~clk;
end
end
initial begin
rst = 1;
`ifdef GATES
#1;
#(deassert_reset-1);
`else
#51; //Period is 4 clock ticks; So reset is deasserted after 12.75 clock periods
`endif
rst = 0;
end
initial begin
iter = 0;
wf_rem = 0;
// maximum simulation time
$value$plusargs("KILLTIME=%d",killtime);
$display("gpu_tb.v: Setting simulation time limit of #%d", killtime);
#killtime;
$display("gpu_tb.v: Simulation terminated. Maximum simulation time of #%d reached!", killtime);
terminate();
end
always @(posedge clk) begin
if (wf_rem <= 0) begin
$display ("--------------------------------------");
$display("Initializing kernel: %d", iter);
$display ("--------------------------------------");
kern = Initialize(NUMOFCU, iter);
if (kern <= 0) terminate();
#0;
wf_rem = getTotalWavefronts();
$display ("--------------------------------------");
$display("Number of wavefronts: %d", wf_rem);
$display ("--------------------------------------");
$readmemh("instr.mem", instr_buffer0.instr_memory);
$readmemh("data.mem", memory0.data_memory);
iter = iter + 1;
end
end
always @ (posedge clk) begin
if (rst) begin
// check <= 1'b0;
dispatch2cu_wf_dispatch <= 'b0;
end
end
always @ (posedge clk) begin
cycle_count = cycle_count + 1;
if (!rst) begin
if (ScheduleWavefront()==1'b1) begin
#1
thrds = getWfNumThrds();
setVregs = getSetVregs();
setSregs = getSetSregs();
cuid = getCuId();
// set vregs
for (x = 0; x < setVregs; x++) begin
vregKey = getVregKey(x, 0);
for (y = 0; y < thrds; y++) begin
vregVal = getVregValue(x, y);
// set the vregister
for(a = 0; a < 32; a++) begin
setVregValue(cuid, y, vregKey, a, vregVal[a]);
//DUT[cuid].vgpr0.reg_file.bank[y].word[vregKey].bits[a].dff_0.state = vregVal[a];
end
end
end
// set sregs
for (z = 0; z < setSregs; z++) begin
sregKey = getSregKey(z);
sregVal = getSregValue(z);
// set the sregister
for(a = 0; a < 32; a++) begin
setSregValue(cuid, sregKey, a, sregVal[a]);
//DUT[cuid].sgpr0.sgpr_reg_file.word[sregKey].bits[a].dff_0.state = sregVal[a];
end
end
dispatch2cu_vgpr_base_dispatch <= getVregBase();
dispatch2cu_sgpr_base_dispatch <= getSregBase();
dispatch2cu_lds_base_dispatch <= getLdsBase();
vregsize <= getVregSize();
sregsize <= getSregSize();
ldssize <= getLdsSize();
dispatch2cu_start_pc_dispatch <= getPC();
dispatch2cu_wf_size_dispatch <= getWfNumThrds() - 1;
dispatch2cu_wf_tag_dispatch <= getWfTag();
dispatch2cu_wg_wf_count <= getWfCnt();
for (m = 0; m < NUMOFCU; m++) begin
// $display("CUID: %d",getCuId());
if(m==getCuId()) dispatch2cu_wf_dispatch[m] <= 1'b1;
else dispatch2cu_wf_dispatch[m] <= 1'b0;
// $display("m: %d dispatch2cu_wf_dispatch: %d",m,dispatch2cu_wf_dispatch[m]);
end
end
else begin
for ( m = 0; m < NUMOFCU; m++) begin
dispatch2cu_vgpr_base_dispatch <= 10'bx;
dispatch2cu_sgpr_base_dispatch <= 9'bx;
dispatch2cu_lds_base_dispatch <= 16'bx;
vregsize <= 10'bx;
sregsize <= 9'bx;
ldssize <= 16'bx;
dispatch2cu_start_pc_dispatch <= 32'bx;
dispatch2cu_wf_size_dispatch <= 6'bx;
dispatch2cu_wf_tag_dispatch <= 11'bx;
dispatch2cu_wf_dispatch[m] <= 1'b0;
end
end
if(|{dispatch2cu_wf_dispatch, cu2dispatch_wf_done})
$display ("--------------------------------------");
for(n=0; n<NUMOFCU; n++) begin
if(|{dispatch2cu_wf_dispatch[n], cu2dispatch_wf_done[n]})
$display ("Time: %g CU: %d Dispatch: %b cu2dispatch_wf_done: %b", $time, n, dispatch2cu_wf_dispatch[n], cu2dispatch_wf_done[n]);
end
if(|dispatch2cu_wf_dispatch) begin
$display ("VGPR_Size value: %d", vregsize);
$display ("SREG_Size value: %d", sregsize);
$display ("LDS_Size value: %d", ldssize);
$display ("PC value: %d", dispatch2cu_start_pc_dispatch);
$display ("WFID: %d", dispatch2cu_wf_tag_dispatch);
end
end
end
always @ (posedge clk) begin
for(n=0; n<NUMOFCU; n++) begin
if (cu2dispatch_wf_done[n]) begin
DescheduleWavefront(n, cu2dispatch_wf_tag_done[((n * 15) + 14)-:15]); // cuid
$display("Descheduled WFID: %d from CU: %d", cu2dispatch_wf_tag_done[((n * 15) + 14)-:15], n);
$display ("--------------------------------------");
wf_rem = wf_rem - 1;
$display("Wavefronts remaining : %d", wf_rem);
end
end
end
//fault_injection fault_injector(.clk(clk));
integer loop;
task terminate;
begin
`ifdef SAIF
$toggle_stop;
$toggle_report("backward.saif",1.0e-9,"gpu_tb.DUT[0]");
`endif
// for(loop = 0; loop<1000; loop=loop+1) begin
// $display("tracemon my %d: %h",loop, memory0.data_memory[loop]);
// end
$finish;
end
endtask
endmodule
|
/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Wishbone DRP shim
*/
module wb_drp #
(
parameter ADDR_WIDTH = 16
)
(
input wire clk,
input wire rst,
/*
* Wishbone interface
*/
input wire [ADDR_WIDTH-1:0] wb_adr_i, // ADR_I() address
input wire [15:0] wb_dat_i, // DAT_I() data in
output wire [15:0] wb_dat_o, // DAT_O() data out
input wire wb_we_i, // WE_I write enable input
input wire wb_stb_i, // STB_I strobe input
output wire wb_ack_o, // ACK_O acknowledge output
input wire wb_cyc_i, // CYC_I cycle input
/*
* DRP interface
*/
output wire [ADDR_WIDTH-1:0] drp_addr,
output wire [15:0] drp_do,
input wire [15:0] drp_di,
output wire drp_en,
output wire drp_we,
input wire drp_rdy
);
reg cycle = 1'b0;
assign drp_addr = wb_adr_i;
assign drp_do = wb_dat_i;
assign wb_dat_o = drp_di;
assign drp_en = wb_cyc_i & wb_stb_i & ~cycle;
assign drp_we = wb_cyc_i & wb_stb_i & wb_we_i & ~cycle;
assign wb_ack_o = drp_rdy;
always @(posedge clk) begin
cycle <= wb_cyc_i & wb_stb_i & ~drp_rdy;
if (rst) begin
cycle <= 1'b0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP2_BEHAVIORAL_PP_V
/**
* busdrivernovlp2: Bus driver, enable gates pulldown only (pmos
* devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__busdrivernovlp2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP2_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__TAPVGND_FUNCTIONAL_PP_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__NOR2_BEHAVIORAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR2_BEHAVIORAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_PP_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_BEHAVIORAL_PP_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Nov 01 12:03:22 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
probe29, probe30)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[8:0],probe20[7:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[0:0],probe25[7:0],probe26[3:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[7:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
input [8:0]probe19;
input [7:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [0:0]probe24;
input [7:0]probe25;
input [3:0]probe26;
input [0:0]probe27;
input [0:0]probe28;
input [0:0]probe29;
input [7:0]probe30;
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: biossd.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module biossd (
address,
clock,
q);
input [11:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "./src/rom/biossd.rif"
`else
altsyncram_component.init_file = "./src/rom/biossd.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./src/rom/biossd.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./src/rom/biossd.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[11..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL biossd.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL biossd.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL biossd.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL biossd.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL biossd_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL biossd_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL biossd_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL biossd_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD3_FUNCTIONAL_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD3_FUNCTIONAL_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd3 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD3_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_V
/**
* lpflow_inputisolatch: Latching input isolator with inverted enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_lp/sky130_fd_sc_hd__udp_dlatch_lp.v"
`celldefine
module sky130_fd_sc_hd__lpflow_inputisolatch (
Q ,
D ,
SLEEP_B
);
// Module ports
output Q ;
input D ;
input SLEEP_B;
// Local signals
wire buf_Q;
// Name Output Other arguments
sky130_fd_sc_hd__udp_dlatch$lP dlatch0 (buf_Q , D, SLEEP_B );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDLCLKP_SYMBOL_V
`define SKY130_FD_SC_MS__SDLCLKP_SYMBOL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDLCLKP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTP_SYMBOL_V
`define SKY130_FD_SC_LP__DFRTP_SYMBOL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTP_SYMBOL_V
|
/***********************************************************************
AVR ATtX5 CPU for Lattuino
This file is part FPGA Libre project http://fpgalibre.sf.net/
Description:
This module implements the CPU for Lattuino (iCE40HX4K Lattice FPGA
available in the Kéfir I board).
To Do:
-
Author:
- Salvador E. Tropea, salvador inti.gob.ar
------------------------------------------------------------------------------
Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar>
Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial
Distributed under the GPL v2 or newer license
------------------------------------------------------------------------------
Design unit: Lattuino_1
File name: lattuino_1.v
Note: None
Limitations: None known
Errors: None known
Library: work
Dependencies: IEEE.std_logic_1164
avr.Micros
miniuart.UART
CapSense.Devices
work.WBDevInterconPkg
work.CPUConfig
lattice.components
Target FPGA: iCE40HX4K-TQ144
Language: Verilog
Wishbone: None
Synthesis tools: Lattice iCECube2 2016.02.27810
Simulation tools: GHDL [Sokcho edition] (0.2x)
Text editor: SETEdit 0.5.x
***********************************************************************/
module Lattuino_1
(
input CLK, // CPU clock
input RESET_P2, // Reset
// Buil-in LEDs
output LED1,
output LED2,
output LED3,
output LED4,
// CapSense buttons
inout BTN1,
inout BTN2,
inout BTN3,
inout BTN4,
// Arduino UNO I/O
inout ARDU00,
inout ARDU01,
inout ARDU02,
inout ARDU03,
inout ARDU04,
inout ARDU05,
inout ARDU06,
inout ARDU07,
inout ARDU08,
inout ARDU09,
inout ARDU10, // SS
inout ARDU11, // MOSI
inout ARDU12, // MISO
inout ARDU13, // SCK
// A/D Interface
output AD_CS,
output AD_Din,
input AD_Dout,
output AD_Clk,
// SPI memory
output SS_B,
output SDO,
input SDI,
output SCK,
// ISP SPI
//input ISP_RESET;
output ISP_SCK,
output ISP_MOSI,
input ISP_MISO,
// UART
output Milk_RXD, // to UART Tx
input Milk_TXD, // to UART Rx
input Milk_DTR); // UART DTR
`include "cpuconfig.v"
localparam integer BRDIVISOR=F_CLK/BAUD_RATE/4.0+0.5;
localparam integer CNT_PRESC=F_CLK/1e6; // Counter prescaler (1 µs)
localparam EXPLICIT_TBUF=0; // Manually instantiate tri-state buffers (old yosys+arachne)
localparam DEBUG_SPI=0;
localparam DEBUG_INT=0;
wire [15:0] pc; // PROM address
wire [ROM_ADDR_W-1:0] pcsv; // PROM address
wire [15:0] inst; // PROM data
wire [15:0] inst_w; // PROM data
wire we;
wire rst;
wire rst1;
reg rst2=0;
wire [6:0] portb_in;
wire [6:0] portb_out;
wire [6:0] portb_oe;
wire [7:0] portd_in;
wire [7:0] portd_out;
wire [7:0] portd_oe;
wire [3:0] btns; // Capsense buttons
wire discharge;
wire rst_btn;
wire [1:0] pin_irq; // Pin interrupts INT0/1
wire [2:0] dev_irq; // Device interrupts
wire [2:0] dev_ack; // Device ACK
// WISHBONE signals:
// cpu
wire [7:0] cpu_dati;
wire cpu_acki;
wire [7:0] cpu_dato;
wire cpu_weo;
wire [7:0] cpu_adro;
wire cpu_cyco;
wire cpu_stbo;
// rs2
wire [7:0] rs2_dato;
wire rs2_acko;
wire [7:0] rs2_dati;
wire rs2_wei;
wire [0:0] rs2_adri;
wire rs2_stbi;
// ad
wire [7:0] ad_dato;
wire ad_acko;
wire [7:0] ad_dati;
wire ad_wei;
wire [0:0] ad_adri;
wire ad_stbi;
// tmr
wire [7:0] tmr_dato;
wire tmr_acko;
wire [7:0] tmr_dati;
wire tmr_wei;
wire [2:0] tmr_adri;
wire tmr_stbi;
// t16
wire [7:0] t16_dato;
wire t16_acko;
wire [7:0] t16_dati;
wire t16_wei;
wire [0:0] t16_adri;
wire t16_stbi;
wire [5:0] pwm;
wire [5:0] pwm_ena;
wire t16_irq;
wire t16_ack;
wire inttx;
wire intrx;
reg dtr_r;
wire dtr_reset;
// SPI
wire spi_sck;
wire mosi;
wire miso;
wire spi_ena; // The CPU enabled the SPI pins
// PLL
wire clk_spi; // SPI core clock
wire clk_sys; // CPU clock
wire pll_lock;
///////////////////////////////////////////////////////////
// RESET logic --
// Power-On Reset + External pin + CapSense 4 + UART DTR --
///////////////////////////////////////////////////////////
assign rst1=!RESET_P2;
assign rst=rst1 | ~rst2 | rst_btn | dtr_reset;
always @(posedge clk_sys)
begin : do_reset
if (!rst2 && pll_lock)
rst2 <= 1;
end // do_reset
// The DTR reset is triggered by a falling edge at DTR
always @(posedge clk_sys)
begin : do_sample_dtr
dtr_r <= Milk_DTR;
end // do_sample_dtr
assign dtr_reset=dtr_r && !Milk_DTR;
assign rst_btn=ENABLE_B1_RESET ? btns[0] : 0;
// Built-in LEDs
assign LED1=portb_out[6]; // pin IO14
assign LED2=pwm[0];
assign LED3=0; // btns[2];
assign LED4=rst_btn;
// Arduino IOx pins:
wire [13:0] ardu;
assign ardu[ 0]=portd_out[0];
assign ardu[ 1]=portd_out[1];
assign ardu[ 2]=portd_out[2];
assign ardu[ 3]=pwm_ena[0] && ENA_PWM0 ? pwm[0] : portd_out[3];
assign ardu[ 4]=portd_out[4];
assign ardu[ 5]=pwm_ena[1] && ENA_PWM1 ? pwm[1] : portd_out[5];
assign ardu[ 6]=pwm_ena[2] && ENA_PWM2 ? pwm[2] : portd_out[6];
assign ardu[ 7]=portd_out[7];
assign ardu[ 8]=portb_out[0];
assign ardu[ 9]=pwm_ena[3] && ENA_PWM3 ? pwm[3] : portb_out[1];
assign ardu[10]=pwm_ena[4] && ENA_PWM4 ? pwm[4] : portb_out[2];
assign ardu[11]=pwm_ena[5] && ENA_PWM5 && !spi_ena ? pwm[5] :
(spi_ena ? mosi : portb_out[3]);
assign ardu[12]=portb_out[4];
assign ardu[13]=spi_ena ? spi_sck : portb_out[5];
wire [13:0] ardu_oe;
// PB4 reverts to input when SPI is enabled
wire miso_oe;
assign miso_oe=portb_oe[4] & ~spi_ena;
assign ardu_oe={portb_oe[5],miso_oe,portb_oe[3:0],portd_oe};
wire [13:0] ardu_in;
generate
if (EXPLICIT_TBUF)
begin
SB_IO
#(.PIN_TYPE(6'b1010_01),
.PULLUP(1'b0))
io_pins [13:0]
(.PACKAGE_PIN({ARDU13,ARDU12,ARDU11,ARDU10,ARDU09,ARDU08,ARDU07,ARDU06,ARDU05,ARDU04,ARDU03,ARDU02,ARDU01,ARDU00}),
.OUTPUT_ENABLE(ardu_oe),
.D_OUT_0(ardu),
.D_IN_0(ardu_in));
assign {portb_in[5:0],portd_in}=ardu_in;
assign miso=ardu_in[12];
end
else
begin
assign ARDU00=ardu_oe[ 0] ? ardu[ 0] : 1'bZ;
assign ARDU01=ardu_oe[ 1] ? ardu[ 1] : 1'bZ;
assign ARDU02=ardu_oe[ 2] ? ardu[ 2] : 1'bZ;
assign ARDU03=ardu_oe[ 3] ? ardu[ 3] : 1'bZ;
assign ARDU04=ardu_oe[ 4] ? ardu[ 4] : 1'bZ;
assign ARDU05=ardu_oe[ 5] ? ardu[ 5] : 1'bZ;
assign ARDU06=ardu_oe[ 6] ? ardu[ 6] : 1'bZ;
assign ARDU07=ardu_oe[ 7] ? ardu[ 7] : 1'bZ;
assign ARDU08=ardu_oe[ 8] ? ardu[ 8] : 1'bZ;
assign ARDU09=ardu_oe[ 9] ? ardu[ 9] : 1'bZ;
assign ARDU10=ardu_oe[10] ? ardu[10] : 1'bZ;
assign ARDU11=ardu_oe[11] ? ardu[11] : 1'bZ;
assign ARDU12=ardu_oe[12] ? ardu[12] : 1'bZ;
assign ARDU13=ardu_oe[13] ? ardu[13] : 1'bZ;
assign portd_in[0]=ARDU00;
assign portd_in[1]=ARDU01;
assign portd_in[2]=ARDU02;
assign portd_in[3]=ARDU03;
assign portd_in[4]=ARDU04;
assign portd_in[5]=ARDU05;
assign portd_in[6]=ARDU06;
assign portd_in[7]=ARDU07;
assign portb_in[0]=ARDU08;
assign portb_in[1]=ARDU09;
assign portb_in[2]=ARDU10;
assign portb_in[3]=ARDU11;
assign portb_in[4]=ARDU12;
assign portb_in[5]=ARDU13;
assign miso =ARDU12;
assign ardu_in={ARDU13,ARDU12,ARDU11,ARDU10,ARDU09,ARDU08,ARDU07,ARDU06,ARDU05,ARDU04,ARDU03,ARDU02,ARDU01,ARDU00};
end
endgenerate
// This is not 100% Arduino, here we fix SPI regardless spi_ena
//ISP_SCK =spi_sck;
//ARDU12 =ISP_MISO;
//ISP_MOSI=mosi;
generate
if (DEBUG_INT)
begin : do_int_btns
// Debug connection to CapSense
assign pin_irq[0]=btns[1];
assign pin_irq[1]=btns[2];
end
else
begin : do_int_pins
// INT0/1 pins (PD2 and PD3)
assign pin_irq[0]=ENA_INT0 ? ardu_in[2] : 0;
assign pin_irq[1]=ENA_INT1 ? ardu_in[3] : 0;
end
endgenerate
// Device interrupts
assign dev_irq[0]=intrx; // UART Rx
assign dev_irq[1]=inttx; // UART Tx
assign dev_irq[2]=t16_irq; // 16 bits Timer
assign t16_ack=dev_ack[2];
generate
if (DEBUG_SPI)
begin : do_debug_spi
assign SS_B=portb_out[2];
assign SCK =spi_sck;
assign miso=SDI;
assign SDO =mosi;
end
else
begin : do_arduino_spi
assign SS_B=1; // Disable the SPI memory
assign SCK =0;
assign SDO =0;
end
endgenerate
ATtX5
#(
.ENA_WB(1), .ENA_SPM(1), .ENA_PORTB(1), .ENA_PORTC(0),
.ENA_PORTD(1), .PORTB_SIZE(7), .PORTC_SIZE(6),
.PORTD_SIZE(8),.RESET_JUMP(RESET_JUMP), .ENA_IRQ_CTRL(1),
.RAM_ADDR_W(RAM_ADDR_W), .ENA_SPI(ENABLE_SPI))
micro
(
.rst_i(rst), .clk_i(clk_sys), .clk2x_i(clk_spi),
.pc_o(pc), .inst_i(inst), .ena_i(1), .portc_i(),
.portb_i(portb_in), .pgm_we_o(we), .inst_o(inst_w),
.portd_i(portd_in), .pin_irq_i(pin_irq), .dev_irq_i(dev_irq),
.dev_ack_o(dev_ack), .portb_o(portb_out), .portd_o(portd_out),
.portb_oe_o(portb_oe), .portd_oe_o(portd_oe),
// SPI
.spi_ena_o(spi_ena), .sclk_o(spi_sck), .miso_i(miso), .mosi_o(mosi),
// WISHBONE
.wb_adr_o(cpu_adro), .wb_dat_o(cpu_dato), .wb_dat_i(cpu_dati),
.wb_stb_o(cpu_stbo), .wb_we_o(cpu_weo), .wb_ack_i(cpu_acki),
// Debug
.dbg_stop_i(0), .dbg_rf_fake_i(0), .dbg_rr_data_i(0),
.dbg_rd_data_i(0));
assign cpu_cyco=0;
assign pcsv=pc[ROM_ADDR_W-1:0];
// Program memory (1/2/4Kx16) (2/4/8 kiB)
generate
if (ROM_ADDR_W==10)
begin : pm_2k
lattuino_1_blPM_2 #(.WORD_SIZE(16), .ADDR_W(ROM_ADDR_W)) PM_Inst2
(.clk_i(clk_sys), .addr_i(pcsv), .data_o(inst),
.data_i(inst_w), .we_i(we));
end
else if (ROM_ADDR_W==11)
begin : pm_4k
lattuino_1_blPM_4 #(.WORD_SIZE(16), .ADDR_W(ROM_ADDR_W)) PM_Inst4
(.clk_i(clk_sys), .addr_i(pcsv), .data_o(inst),
.data_i(inst_w), .we_i(we));
end
else if (ROM_ADDR_W==12)
begin : pm_8k
lattuino_1_blPM_8 #(.WORD_SIZE(16), .ADDR_W(ROM_ADDR_W)) PM_Inst8
(.clk_i(clk_sys), .addr_i(pcsv), .data_o(inst),
.data_i(inst_w), .we_i(we));
end
endgenerate
///////////////////////
// WISHBONE Intercon //
///////////////////////
WBDevIntercon intercon
(// WISHBONE master port(s)
// cpu
.cpu_dat_o(cpu_dati),
.cpu_ack_o(cpu_acki),
.cpu_dat_i(cpu_dato),
.cpu_we_i(cpu_weo),
.cpu_adr_i(cpu_adro),
.cpu_cyc_i(cpu_cyco),
.cpu_stb_i(cpu_stbo),
// WISHBONE slave port(s)
// rs2
.rs2_dat_i(rs2_dato),
.rs2_ack_i(rs2_acko),
.rs2_dat_o(rs2_dati),
.rs2_we_o(rs2_wei),
.rs2_adr_o(rs2_adri),
.rs2_stb_o(rs2_stbi),
// ad
.ad_dat_i(ad_dato),
.ad_ack_i(ad_acko),
.ad_dat_o(ad_dati),
.ad_we_o(ad_wei),
.ad_adr_o(ad_adri),
.ad_stb_o(ad_stbi),
// tmr
.tmr_dat_i(tmr_dato),
.tmr_ack_i(tmr_acko),
.tmr_dat_o(tmr_dati),
.tmr_we_o(tmr_wei),
.tmr_adr_o(tmr_adri),
.tmr_stb_o(tmr_stbi),
// t16
.t16_dat_i(t16_dato),
.t16_ack_i(t16_acko),
.t16_dat_o(t16_dati),
.t16_we_o(t16_wei),
.t16_adr_o(t16_adri),
.t16_stb_o(t16_stbi),
// clock and reset
.wb_clk_i(clk_sys),
.wb_rst_i(rst));
///////////////////
// WISHBONE UART //
///////////////////
UART_C
#(.BRDIVISOR(BRDIVISOR),
.WIP_ENABLE(1),
.AUX_ENABLE(0))
the_uart
(// WISHBONE signals
.wb_clk_i(clk_sys), .wb_rst_i(rst), .wb_adr_i(rs2_adri),
.wb_dat_i(rs2_dati), .wb_dat_o(rs2_dato), .wb_we_i(rs2_wei),
.wb_stb_i(rs2_stbi), .wb_ack_o(rs2_acko),
// Process signals
.inttx_o(inttx), .intrx_o(intrx), .br_clk_i(1),
.txd_pad_o(Milk_RXD), .rxd_pad_i(Milk_TXD));
////////////////////////////
// WISHBONE time counters //
////////////////////////////
TMCounter
#(.CNT_PRESC(CNT_PRESC), .ENA_TMR(ENA_TIME_CNT))
the_counter
(// WISHBONE signals
.wb_clk_i(clk_sys), .wb_rst_i(rst), .wb_adr_i(tmr_adri),
.wb_dat_o(tmr_dato), .wb_stb_i(tmr_stbi), .wb_ack_o(tmr_acko),
.wb_dat_i(tmr_dati), .wb_we_i(tmr_wei),
// PWMs
.pwm_o(pwm), .pwm_e_o(pwm_ena));
//////////////////////////////
// WISHBONE 16 bits counter //
//////////////////////////////
TM16bits
#(.CNT_PRESC(CNT_PRESC), .ENA_TMR(ENA_TMR16))
the_tm16bits
(// Wishbone signals
.wb_clk_i(clk_sys), .wb_rst_i(rst), .wb_adr_i(t16_adri),
.wb_dat_o(t16_dato), .wb_stb_i(t16_stbi), .wb_ack_o(t16_acko),
.wb_dat_i(t16_dati), .wb_we_i(t16_wei),
// IRQ
.irq_req_o(t16_irq), .irq_ack_i(t16_ack));
//////////////////
// WISHBONE A/D //
//////////////////
AD_Conv
#(.ENABLE(ENABLE_AD))
the_ad
(// WISHBONE signals
.wb_clk_i(clk_sys), .wb_rst_i(rst), .wb_adr_i(ad_adri),
.wb_dat_o(ad_dato), .wb_stb_i(ad_stbi), .wb_ack_o(ad_acko),
.wb_dat_i(ad_dati), .wb_we_i(ad_wei),
// A/D
.ad_ncs_o(AD_CS), .ad_clk_o(AD_Clk), .ad_din_o(AD_Din),
.ad_dout_i(AD_Dout),.spi_ena_i(0));
//////////////////////
// Botones CapSense //
//////////////////////
wire [3:0] capsense_in;
CapSense_Sys
#(.N(4), .FREQUENCY(CNT_PRESC), .DIRECT(0))
CS
(.clk_i(clk_sys),
.rst_i(0),
.capsense_i(capsense_in),
.capsense_o(discharge),
.buttons_o(btns), .debug_o());
generate
if (EXPLICIT_TBUF)
begin
SB_IO
#(.PIN_TYPE(6'b1010_01),
.PULLUP(1'b0))
buts [3:0]
(.PACKAGE_PIN({BTN4,BTN3,BTN2,BTN1}),
.OUTPUT_ENABLE(discharge),
.D_OUT_0(4'b0),
.D_IN_0(capsense_in));
end
else
begin
assign BTN1=discharge ? 1'b0 : 1'bZ;
assign BTN2=discharge ? 1'b0 : 1'bZ;
assign BTN3=discharge ? 1'b0 : 1'bZ;
assign BTN4=discharge ? 1'b0 : 1'bZ;
assign capsense_in={BTN4,BTN3,BTN2,BTN1};
end
endgenerate
generate
if (ENA_2xSCK)
begin : do_2xSPI
// *************************************************************************
// PLL: 48 MHz clock from 24 MHz clock
// *************************************************************************
SB_PLL40_2F_PAD
#(// Feedback (all defaults)
.FEEDBACK_PATH("SIMPLE"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
// .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.SHIFTREG_DIV_MODE(2'b0), // 0 --> Divide by 4, 1 --> Divide by 7), 3 --> Divide by 5
.FDA_FEEDBACK(4'b0),
// .FDA_RELATIVE(0),
.PLLOUT_SELECT_PORTA("GENCLK"),
.PLLOUT_SELECT_PORTB("GENCLK_HALF"),
// Freq. Multiplier (DIVF+1)/((2**DIVQ)*(DIVR+1))=32/16=2
.DIVF(7'b0011111), // 31
.DIVR(4'b0),
.DIVQ(3'b100), // 4
.FILTER_RANGE(3'b010), // Not documented!
// Output clock gates (for low power modes)
.ENABLE_ICEGATE_PORTA(1'b0),
.ENABLE_ICEGATE_PORTB(1'b0)
// Test Mode Parameter
// .TEST_MODE(0),
// EXTERNAL_DIVIDE_FACTOR(1) -- Not Used by model, Added for PLL config GUI
)
PLL1
(.PACKAGEPIN(CLK), // Clock pin from GBx
.PLLOUTCOREA(), // Clock A (to logic)
.PLLOUTGLOBALA(clk_spi), // Clock A (to global lines)
.PLLOUTCOREB(), // Clock B (to logic)
.PLLOUTGLOBALB(clk_sys), // Clock B (to global lines)
.EXTFEEDBACK(), // External feedback (not used here)
.DYNAMICDELAY(), // Dynamic delay (not used here)
.LOCK(pll_lock), // PLL is locked
.BYPASS(1'b0), // Bypass enable
.RESETB(1'b1), // /Reset
.LATCHINPUTVALUE(), // Clock gate enable
// Test Pins (not documented)
.SDO(), .SDI(), .SCLK());
end
else
begin : do_1xSPI
assign clk_spi =CLK;
assign clk_sys =CLK;
assign pll_lock=1;
end
endgenerate
endmodule // Lattuino_1
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVN_8_V
`define SKY130_FD_SC_HDLL__EINVN_8_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvn_8 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__einvn_8 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVN_8_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_LP_V
`define SKY130_FD_SC_LP__O32A_LP_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_lp (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_lp (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_LP_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_f2i(
input sys_clk,
input alu_rst,
input [31:0] a,
input valid_i,
output reg [31:0] r,
output reg valid_o
);
wire a_sign = a[31];
wire [7:0] a_expn = a[30:23];
wire [23:0] a_mant = {1'b1, a[22:0]};
reg [30:0] shifted;
always @(*) begin
if(a_expn >= 8'd150)
shifted = a_mant << (a_expn - 8'd150);
else
shifted = a_mant >> (8'd150 - a_expn);
end
always @(posedge sys_clk) begin
if(alu_rst)
valid_o <= 1'b0;
else
valid_o <= valid_i;
if(a_sign)
r <= 32'd0 - {1'b0, shifted};
else
r <= {1'b0, shifted};
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BAI_BLACKBOX_V
`define SKY130_FD_SC_MS__O21BAI_BLACKBOX_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BAI_BLACKBOX_V
|
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module DE0_NANO(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY,
//////////// SDRAM //////////
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_DQM,
DRAM_RAS_N,
DRAM_WE_N,
//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
GPIO,
GPIO_IN
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//////////// KEY //////////
input [1:0] KEY;
//////////// SDRAM //////////
output [12:0] DRAM_ADDR;
output [1:0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15:0] DRAM_DQ;
output [1:0] DRAM_DQM;
output DRAM_RAS_N;
output DRAM_WE_N;
//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
inout [33:0] GPIO;
input [1:0] GPIO_IN;
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
endmodule
|
module auto_module
( input my_clk,
input my_rst_n,
output manually_listed,
/*AUTOINOUTMODPORT("automodport_if" "pure_mp")*/
// Beginning of automatic in/out/inouts (from modport)
output out_pure,
input in_pure,
// End of automatics
//ex: input in_pure;
//ex: output out_pure;
/*AUTOINOUTMODPORT("automodport_if" "req_mon_mp")*/
// Beginning of automatic in/out/inouts (from modport)
input req_val,
input [63:0] req_dat,
input req_credit,
// End of automatics
//ex: input req_credit, // To auto_i of auto_intf.sv
//ex: input [63:0] req_data, // To auto_i of auto_intf.sv
//ex: input req_val, // To auto_i of auto_intf.sv
/*AUTOINOUTMODPORT("automodport_if" "rsp_drv_mp")*/
// Beginning of automatic in/out/inouts (from modport)
output [1:0] rsp_cmd,
output [63:0] rsp_data,
input rsp_credit
// End of automatics
//ex: output [1:0] rsp_cmd, // From auto_i of auto_intf.sv
//ex: input rsp_credit, // To auto_i of auto_intf.sv
//ex: output [63:0] rsp_data // From auto_i of auto_intf.sv
);
auto_intf auto_i
(// Inputs
.clk (my_clk),
.rst_n (my_rst_n));
/*AUTOASSIGNMODPORT("automodport_if" "req_mon_mp" "auto_i" )*/
// Beginning of automatic assignments from modport
assign auto_i.manually_listed = manually_listed;
assign auto_i.req_credit = req_credit;
assign auto_i.req_dat = req_dat;
assign auto_i.req_val = req_val;
// End of automatics
//ex: assign auto_i.req_credit = req_credit;
//ex: assign auto_i.req_data = req_data;
//ex: assign auto_i.req_val = req_val;
/*AUTOASSIGNMODPORT("automodport_if" "rsp_drv_mp" "auto_i" )*/
// Beginning of automatic assignments from modport
assign rsp_cmd = auto_i.rsp_cmd;
assign rsp_data = auto_i.rsp_data;
assign auto_i.rsp_credit = rsp_credit;
// End of automatics
//ex: assign rsp_cmd = auto_i.rsp_cmd;
//ex: assign rsp_data = auto_i.rsp_data;
//ex: assign auto_i.rsp_credit = rsp_credit;
/*AUTOASSIGNMODPORT("automodport_if" "r.*" "auto_i" )*/
// Beginning of automatic assignments from modport
assign rsp_cmd = auto_i.rsp_cmd;
assign rsp_data = auto_i.rsp_data;
assign auto_i.manually_listed = manually_listed;
assign auto_i.req_credit = req_credit;
assign auto_i.req_dat = req_dat;
assign auto_i.req_val = req_val;
assign auto_i.rsp_credit = rsp_credit;
// End of automatics
initial begin
`cn_set_intf(virtual auto_intf.req_mon_mp, "auto_pkg::auto_intf", "req_mon_vi", auto_i.req_mon_mp );
`cn_set_intf(virtual auto_intf.rsp_drv_mp, "auto_pkg::auto_intf", "rsp_drv_vi", auto_i.rsp_drv_mp );
end
endmodule
|
`timescale 1ns/10ps
module PressCountSim;
reg clock0;
reg clock180;
reg reset;
reg countu;
reg countd;
wire [7:0] nr_presses;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#5000 $finish;
end
initial begin
#0 clock0 = 1;
forever #2 clock0 = ~clock0;
end
initial begin
#0 clock180 = 0;
forever #2 clock180 = ~clock180;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0 countu = 0;
countd = 0;
#12 countu = 1;
#5 countu = 0;
#43 countu = 1;
#5 countu = 0;
#124 countd = 1;
#233 countd = 0;
#4 countu = 1;
#100 countu = 0;
#4 countu = 1;
#100 countu = 0;
end
PressCount
presscount (.clock0(clock0),
.clock180(clock180),
.reset(reset),
.countu(countu),
.countd(countd),
.nr_presses(nr_presses));
endmodule // PressCountSim
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_MUX_2TO1_SYMBOL_V
`define SKY130_FD_SC_MS__UDP_MUX_2TO1_SYMBOL_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_mux_2to1 (
//# {{data|Data Signals}}
input A0,
input A1,
output X ,
//# {{control|Control Signals}}
input S
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_MUX_2TO1_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBEC_P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__PROBEC_P_BEHAVIORAL_PP_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__probec_p (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBEC_P_BEHAVIORAL_PP_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module usdrx1_spi (
spi_afe_csn,
spi_clk_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_afe_sdio,
spi_clk_sdio);
// 4 wire
input [ 3:0] spi_afe_csn;
input spi_clk_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_afe_sdio;
inout spi_clk_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire [ 1:0] spi_csn_3_s;
wire spi_csn_s;
wire spi_enable_s;
wire spi_afe_miso_s;
wire spi_clk_miso_s;
// check on rising edge and change on falling edge
assign spi_csn_3_s[1] = & spi_afe_csn;
assign spi_csn_3_s[0] = spi_clk_csn;
assign spi_csn_s = & spi_csn_3_s;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (((spi_count == 6'd16) && (spi_csn_3_s[1] == 1'b0)) ||
((spi_count == 6'd16) && (spi_csn_3_s[0] == 1'b0))) begin
spi_enable <= spi_rd_wr_n;
end
end
end
assign spi_miso = ((spi_afe_miso_s & ~spi_csn_3_s[1]) |
(spi_clk_miso_s & ~spi_csn_3_s[0]));
// io buffers
assign spi_afe_miso_s = spi_afe_sdio;
assign spi_afe_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
assign spi_clk_miso_s = spi_clk_sdio;
assign spi_clk_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi;
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4_TB_V
`define SKY130_FD_SC_HDLL__OR4_TB_V
/**
* or4: 4-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hdll__or4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4_TB_V
|
module SysPLL(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire sdr_clk,
// interface 'outclk1'
output wire sys_clk,
// interface 'outclk2'
output wire vga_clk,
output wire pit_clk,
// interface 'locked'
output wire locked
);
wire [4:0] sub_wire0;
wire [0:0] sub_wire7 = 1'h0;
wire [0:0] sub_wire5;
wire [3:3] sub_wire4 = sub_wire0[3:3];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
assign sdr_clk = sub_wire1;
assign sys_clk = sub_wire2;
assign vga_clk = sub_wire3;
assign pit_clk = sub_wire4;
assign sub_wire5 = refclk;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.inclk (sub_wire6),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (locked),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "-2727",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 2,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "0",
altpll_component.clk3_divide_by = 25000000,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 596529,
altpll_component.clk3_phase_shift = "0",
altpll_component.compensate_clock = "CLK1",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll1",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
|
module spi_slave(
input clk,
input rst,
input ss,
input mosi,
output miso,
input sck,
output done,
input [7:0] din,
input din_update,
output [7:0] dout
);
reg mosi_d, mosi_q;
reg ss_d, ss_q;
reg sck_d, sck_q;
reg sck_old_d, sck_old_q;
reg [7:0] data_d, data_q;
reg done_d, done_q;
reg [2:0] bit_ct_d, bit_ct_q;
reg [7:0] dout_d, dout_q;
reg miso_d, miso_q;
assign miso = miso_q;
assign done = done_q;
assign dout = dout_q;
always @(*) begin
ss_d = ss;
mosi_d = mosi;
miso_d = miso_q;
sck_d = sck;
sck_old_d = sck_q;
data_d = data_q;
done_d = 1'b0;
bit_ct_d = bit_ct_q;
dout_d = dout_q;
if (ss_q) begin
bit_ct_d = 3'b0;
data_d = din;
miso_d = data_q[7];
end else begin
if (!sck_old_q && sck_q) begin // rising edge
miso_d = data_q[7];
data_d = {data_q[6:0], mosi_q};
bit_ct_d = bit_ct_q + 1'b1;
if (bit_ct_q == 3'b111) begin
dout_d = {data_q[6:0], mosi_q};
done_d = 1'b1;
data_d = din;
end
end else if (din_update) begin
data_d = din;
end
end
end
always @(posedge clk) begin
if (rst) begin
done_q <= 1'b0;
bit_ct_q <= 3'b0;
dout_q <= 8'b0;
miso_q <= 1'b1;
end else begin
done_q <= done_d;
bit_ct_q <= bit_ct_d;
dout_q <= dout_d;
miso_q <= miso_d;
end
sck_q <= sck_d;
mosi_q <= mosi_d;
ss_q <= ss_d;
data_q <= data_d;
sck_old_q <= sck_old_d;
end
endmodule
|
//-----------------------------------------------------
// Design Name : hw1_A
// File Name : hw1_A.v
// Function : This program designs a single mux-based bus.
// Coder : hydai
//-----------------------------------------------------
module hw1_A (
input [15:0] data,
input [6:0] control,
input clk,
input rst_n,
output reg [15:0] R0,
output reg [15:0] R1,
output reg [15:0] R2,
output reg [15:0] R3
);
reg [15:0] tmpData;
reg [15:0] T0, T1, T2, T3;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
R0 <= 0;
R1 <= 0;
R2 <= 0;
R3 <= 0;
end else begin
R0 <= (control[0])?(tmpData):R0;
R1 <= (control[1])?(tmpData):R1;
R2 <= (control[2])?(tmpData):R2;
R3 <= (control[3])?(tmpData):R3;
end // end of if-else block
end // end of always
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
tmpData <= 0;
end // end of if (!rst_n)
case (control[6:4])
3'b000: tmpData <= R0;
3'b001: tmpData <= R1;
3'b010: tmpData <= R2;
3'b011: tmpData <= R3;
3'b111: tmpData <= data;
default: tmpData <= 0;
endcase // end of case (control)
end // end of always
endmodule // endmodule of hw1_A
|
/*******************************************************************************
* Module: dly_16
* Date:2014-05-30
* Author: Andrey Filippov
* Description: Synchronous delay by 1-16 clock cycles with reset (will map to primitives)
*
* Copyright (c) 2014 Elphel, Inc.
* dly_16.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dly_16.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module dly_16 #(
parameter WIDTH=1
)(
input clk,
input rst,
input [3:0] dly,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
generate
genvar i;
for (i=0; i < WIDTH; i=i+1) begin: bit_block
dly01_16 dly01_16_i (
.clk(clk), // input
.rst(rst), // input
.dly(dly), // input[3:0]
.din(din[i]), // input
.dout(dout[i]) // output reg
);
end
endgenerate
endmodule
|
// system_acl_iface_acl_kernel_interface_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_interface_mm_interconnect_0 (
input wire kernel_clk_out_clk_clk, // kernel_clk_out_clk.clk
input wire address_span_extender_0_reset_reset_bridge_in_reset_reset, // address_span_extender_0_reset_reset_bridge_in_reset.reset
input wire kernel_cra_reset_reset_bridge_in_reset_reset, // kernel_cra_reset_reset_bridge_in_reset.reset
input wire [29:0] address_span_extender_0_expanded_master_address, // address_span_extender_0_expanded_master.address
output wire address_span_extender_0_expanded_master_waitrequest, // .waitrequest
input wire [0:0] address_span_extender_0_expanded_master_burstcount, // .burstcount
input wire [3:0] address_span_extender_0_expanded_master_byteenable, // .byteenable
input wire address_span_extender_0_expanded_master_read, // .read
output wire [31:0] address_span_extender_0_expanded_master_readdata, // .readdata
output wire address_span_extender_0_expanded_master_readdatavalid, // .readdatavalid
input wire address_span_extender_0_expanded_master_write, // .write
input wire [31:0] address_span_extender_0_expanded_master_writedata, // .writedata
output wire [29:0] kernel_cra_s0_address, // kernel_cra_s0.address
output wire kernel_cra_s0_write, // .write
output wire kernel_cra_s0_read, // .read
input wire [63:0] kernel_cra_s0_readdata, // .readdata
output wire [63:0] kernel_cra_s0_writedata, // .writedata
output wire [0:0] kernel_cra_s0_burstcount, // .burstcount
output wire [7:0] kernel_cra_s0_byteenable, // .byteenable
input wire kernel_cra_s0_readdatavalid, // .readdatavalid
input wire kernel_cra_s0_waitrequest, // .waitrequest
output wire kernel_cra_s0_debugaccess // .debugaccess
);
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest; // address_span_extender_0_expanded_master_agent:av_waitrequest -> address_span_extender_0_expanded_master_translator:uav_waitrequest
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata; // address_span_extender_0_expanded_master_agent:av_readdata -> address_span_extender_0_expanded_master_translator:uav_readdata
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess; // address_span_extender_0_expanded_master_translator:uav_debugaccess -> address_span_extender_0_expanded_master_agent:av_debugaccess
wire [29:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address; // address_span_extender_0_expanded_master_translator:uav_address -> address_span_extender_0_expanded_master_agent:av_address
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read; // address_span_extender_0_expanded_master_translator:uav_read -> address_span_extender_0_expanded_master_agent:av_read
wire [3:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable; // address_span_extender_0_expanded_master_translator:uav_byteenable -> address_span_extender_0_expanded_master_agent:av_byteenable
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid; // address_span_extender_0_expanded_master_agent:av_readdatavalid -> address_span_extender_0_expanded_master_translator:uav_readdatavalid
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock; // address_span_extender_0_expanded_master_translator:uav_lock -> address_span_extender_0_expanded_master_agent:av_lock
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write; // address_span_extender_0_expanded_master_translator:uav_write -> address_span_extender_0_expanded_master_agent:av_write
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata; // address_span_extender_0_expanded_master_translator:uav_writedata -> address_span_extender_0_expanded_master_agent:av_writedata
wire [2:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount; // address_span_extender_0_expanded_master_translator:uav_burstcount -> address_span_extender_0_expanded_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> address_span_extender_0_expanded_master_agent:rp_valid
wire [100:0] rsp_mux_src_data; // rsp_mux:src_data -> address_span_extender_0_expanded_master_agent:rp_data
wire rsp_mux_src_ready; // address_span_extender_0_expanded_master_agent:rp_ready -> rsp_mux:src_ready
wire [0:0] rsp_mux_src_channel; // rsp_mux:src_channel -> address_span_extender_0_expanded_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> address_span_extender_0_expanded_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> address_span_extender_0_expanded_master_agent:rp_endofpacket
wire [63:0] kernel_cra_s0_agent_m0_readdata; // kernel_cra_s0_translator:uav_readdata -> kernel_cra_s0_agent:m0_readdata
wire kernel_cra_s0_agent_m0_waitrequest; // kernel_cra_s0_translator:uav_waitrequest -> kernel_cra_s0_agent:m0_waitrequest
wire kernel_cra_s0_agent_m0_debugaccess; // kernel_cra_s0_agent:m0_debugaccess -> kernel_cra_s0_translator:uav_debugaccess
wire [29:0] kernel_cra_s0_agent_m0_address; // kernel_cra_s0_agent:m0_address -> kernel_cra_s0_translator:uav_address
wire [7:0] kernel_cra_s0_agent_m0_byteenable; // kernel_cra_s0_agent:m0_byteenable -> kernel_cra_s0_translator:uav_byteenable
wire kernel_cra_s0_agent_m0_read; // kernel_cra_s0_agent:m0_read -> kernel_cra_s0_translator:uav_read
wire kernel_cra_s0_agent_m0_readdatavalid; // kernel_cra_s0_translator:uav_readdatavalid -> kernel_cra_s0_agent:m0_readdatavalid
wire kernel_cra_s0_agent_m0_lock; // kernel_cra_s0_agent:m0_lock -> kernel_cra_s0_translator:uav_lock
wire [63:0] kernel_cra_s0_agent_m0_writedata; // kernel_cra_s0_agent:m0_writedata -> kernel_cra_s0_translator:uav_writedata
wire kernel_cra_s0_agent_m0_write; // kernel_cra_s0_agent:m0_write -> kernel_cra_s0_translator:uav_write
wire [3:0] kernel_cra_s0_agent_m0_burstcount; // kernel_cra_s0_agent:m0_burstcount -> kernel_cra_s0_translator:uav_burstcount
wire kernel_cra_s0_agent_rf_source_valid; // kernel_cra_s0_agent:rf_source_valid -> kernel_cra_s0_agent_rsp_fifo:in_valid
wire [137:0] kernel_cra_s0_agent_rf_source_data; // kernel_cra_s0_agent:rf_source_data -> kernel_cra_s0_agent_rsp_fifo:in_data
wire kernel_cra_s0_agent_rf_source_ready; // kernel_cra_s0_agent_rsp_fifo:in_ready -> kernel_cra_s0_agent:rf_source_ready
wire kernel_cra_s0_agent_rf_source_startofpacket; // kernel_cra_s0_agent:rf_source_startofpacket -> kernel_cra_s0_agent_rsp_fifo:in_startofpacket
wire kernel_cra_s0_agent_rf_source_endofpacket; // kernel_cra_s0_agent:rf_source_endofpacket -> kernel_cra_s0_agent_rsp_fifo:in_endofpacket
wire kernel_cra_s0_agent_rsp_fifo_out_valid; // kernel_cra_s0_agent_rsp_fifo:out_valid -> kernel_cra_s0_agent:rf_sink_valid
wire [137:0] kernel_cra_s0_agent_rsp_fifo_out_data; // kernel_cra_s0_agent_rsp_fifo:out_data -> kernel_cra_s0_agent:rf_sink_data
wire kernel_cra_s0_agent_rsp_fifo_out_ready; // kernel_cra_s0_agent:rf_sink_ready -> kernel_cra_s0_agent_rsp_fifo:out_ready
wire kernel_cra_s0_agent_rsp_fifo_out_startofpacket; // kernel_cra_s0_agent_rsp_fifo:out_startofpacket -> kernel_cra_s0_agent:rf_sink_startofpacket
wire kernel_cra_s0_agent_rsp_fifo_out_endofpacket; // kernel_cra_s0_agent_rsp_fifo:out_endofpacket -> kernel_cra_s0_agent:rf_sink_endofpacket
wire address_span_extender_0_expanded_master_agent_cp_valid; // address_span_extender_0_expanded_master_agent:cp_valid -> router:sink_valid
wire [100:0] address_span_extender_0_expanded_master_agent_cp_data; // address_span_extender_0_expanded_master_agent:cp_data -> router:sink_data
wire address_span_extender_0_expanded_master_agent_cp_ready; // router:sink_ready -> address_span_extender_0_expanded_master_agent:cp_ready
wire address_span_extender_0_expanded_master_agent_cp_startofpacket; // address_span_extender_0_expanded_master_agent:cp_startofpacket -> router:sink_startofpacket
wire address_span_extender_0_expanded_master_agent_cp_endofpacket; // address_span_extender_0_expanded_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [100:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [0:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire kernel_cra_s0_agent_rp_valid; // kernel_cra_s0_agent:rp_valid -> router_001:sink_valid
wire [136:0] kernel_cra_s0_agent_rp_data; // kernel_cra_s0_agent:rp_data -> router_001:sink_data
wire kernel_cra_s0_agent_rp_ready; // router_001:sink_ready -> kernel_cra_s0_agent:rp_ready
wire kernel_cra_s0_agent_rp_startofpacket; // kernel_cra_s0_agent:rp_startofpacket -> router_001:sink_startofpacket
wire kernel_cra_s0_agent_rp_endofpacket; // kernel_cra_s0_agent:rp_endofpacket -> router_001:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [100:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [0:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [100:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [0:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> kernel_cra_s0_cmd_width_adapter:in_valid
wire [100:0] cmd_mux_src_data; // cmd_mux:src_data -> kernel_cra_s0_cmd_width_adapter:in_data
wire cmd_mux_src_ready; // kernel_cra_s0_cmd_width_adapter:in_ready -> cmd_mux:src_ready
wire [0:0] cmd_mux_src_channel; // cmd_mux:src_channel -> kernel_cra_s0_cmd_width_adapter:in_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> kernel_cra_s0_cmd_width_adapter:in_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> kernel_cra_s0_cmd_width_adapter:in_endofpacket
wire kernel_cra_s0_cmd_width_adapter_src_valid; // kernel_cra_s0_cmd_width_adapter:out_valid -> kernel_cra_s0_agent:cp_valid
wire [136:0] kernel_cra_s0_cmd_width_adapter_src_data; // kernel_cra_s0_cmd_width_adapter:out_data -> kernel_cra_s0_agent:cp_data
wire kernel_cra_s0_cmd_width_adapter_src_ready; // kernel_cra_s0_agent:cp_ready -> kernel_cra_s0_cmd_width_adapter:out_ready
wire [0:0] kernel_cra_s0_cmd_width_adapter_src_channel; // kernel_cra_s0_cmd_width_adapter:out_channel -> kernel_cra_s0_agent:cp_channel
wire kernel_cra_s0_cmd_width_adapter_src_startofpacket; // kernel_cra_s0_cmd_width_adapter:out_startofpacket -> kernel_cra_s0_agent:cp_startofpacket
wire kernel_cra_s0_cmd_width_adapter_src_endofpacket; // kernel_cra_s0_cmd_width_adapter:out_endofpacket -> kernel_cra_s0_agent:cp_endofpacket
wire router_001_src_valid; // router_001:src_valid -> kernel_cra_s0_rsp_width_adapter:in_valid
wire [136:0] router_001_src_data; // router_001:src_data -> kernel_cra_s0_rsp_width_adapter:in_data
wire router_001_src_ready; // kernel_cra_s0_rsp_width_adapter:in_ready -> router_001:src_ready
wire [0:0] router_001_src_channel; // router_001:src_channel -> kernel_cra_s0_rsp_width_adapter:in_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> kernel_cra_s0_rsp_width_adapter:in_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> kernel_cra_s0_rsp_width_adapter:in_endofpacket
wire kernel_cra_s0_rsp_width_adapter_src_valid; // kernel_cra_s0_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
wire [100:0] kernel_cra_s0_rsp_width_adapter_src_data; // kernel_cra_s0_rsp_width_adapter:out_data -> rsp_demux:sink_data
wire kernel_cra_s0_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> kernel_cra_s0_rsp_width_adapter:out_ready
wire [0:0] kernel_cra_s0_rsp_width_adapter_src_channel; // kernel_cra_s0_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
wire kernel_cra_s0_rsp_width_adapter_src_startofpacket; // kernel_cra_s0_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
wire kernel_cra_s0_rsp_width_adapter_src_endofpacket; // kernel_cra_s0_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
wire kernel_cra_s0_agent_rdata_fifo_src_valid; // kernel_cra_s0_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [65:0] kernel_cra_s0_agent_rdata_fifo_src_data; // kernel_cra_s0_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire kernel_cra_s0_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> kernel_cra_s0_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> kernel_cra_s0_agent:rdata_fifo_sink_valid
wire [65:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> kernel_cra_s0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // kernel_cra_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> kernel_cra_s0_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) address_span_extender_0_expanded_master_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.uav_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (address_span_extender_0_expanded_master_address), // avalon_anti_master_0.address
.av_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.av_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.av_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.av_read (address_span_extender_0_expanded_master_read), // .read
.av_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.av_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.av_write (address_span_extender_0_expanded_master_write), // .write
.av_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) kernel_cra_s0_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (kernel_cra_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.uav_read (kernel_cra_s0_agent_m0_read), // .read
.uav_write (kernel_cra_s0_agent_m0_write), // .write
.uav_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.uav_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.uav_lock (kernel_cra_s0_agent_m0_lock), // .lock
.uav_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.av_address (kernel_cra_s0_address), // avalon_anti_slave_0.address
.av_write (kernel_cra_s0_write), // .write
.av_read (kernel_cra_s0_read), // .read
.av_readdata (kernel_cra_s0_readdata), // .readdata
.av_writedata (kernel_cra_s0_writedata), // .writedata
.av_burstcount (kernel_cra_s0_burstcount), // .burstcount
.av_byteenable (kernel_cra_s0_byteenable), // .byteenable
.av_readdatavalid (kernel_cra_s0_readdatavalid), // .readdatavalid
.av_waitrequest (kernel_cra_s0_waitrequest), // .waitrequest
.av_debugaccess (kernel_cra_s0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_CACHE_H (95),
.PKT_CACHE_L (92),
.PKT_THREAD_ID_H (88),
.PKT_THREAD_ID_L (88),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_TRANS_EXCLUSIVE (71),
.PKT_TRANS_LOCK (70),
.PKT_BEGIN_BURST (84),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (72),
.PKT_ADDR_H (65),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (66),
.PKT_TRANS_POSTED (67),
.PKT_TRANS_WRITE (68),
.PKT_TRANS_READ (69),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.ST_DATA_W (101),
.ST_CHANNEL_W (1),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_expanded_master_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // av.address
.av_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.av_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (address_span_extender_0_expanded_master_agent_cp_valid), // cp.valid
.cp_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.cp_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (address_span_extender_0_expanded_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (136),
.PKT_ORI_BURST_SIZE_L (134),
.PKT_RESPONSE_STATUS_H (133),
.PKT_RESPONSE_STATUS_L (132),
.PKT_BURST_SIZE_H (115),
.PKT_BURST_SIZE_L (113),
.PKT_TRANS_LOCK (106),
.PKT_BEGIN_BURST (120),
.PKT_PROTECTION_H (127),
.PKT_PROTECTION_L (125),
.PKT_BURSTWRAP_H (112),
.PKT_BURSTWRAP_L (112),
.PKT_BYTE_CNT_H (111),
.PKT_BYTE_CNT_L (108),
.PKT_ADDR_H (101),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (102),
.PKT_TRANS_POSTED (103),
.PKT_TRANS_WRITE (104),
.PKT_TRANS_READ (105),
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_SRC_ID_H (122),
.PKT_SRC_ID_L (122),
.PKT_DEST_ID_H (123),
.PKT_DEST_ID_L (123),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (1),
.ST_DATA_W (137),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) kernel_cra_s0_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (kernel_cra_s0_agent_m0_address), // m0.address
.m0_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (kernel_cra_s0_agent_m0_lock), // .lock
.m0_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (kernel_cra_s0_agent_m0_read), // .read
.m0_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.m0_write (kernel_cra_s0_agent_m0_write), // .write
.rp_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (kernel_cra_s0_agent_rp_ready), // .ready
.rp_valid (kernel_cra_s0_agent_rp_valid), // .valid
.rp_data (kernel_cra_s0_agent_rp_data), // .data
.rp_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.cp_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.cp_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (kernel_cra_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (kernel_cra_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (kernel_cra_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (kernel_cra_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (138),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) kernel_cra_s0_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (kernel_cra_s0_agent_rf_source_data), // in.data
.in_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.in_ready (kernel_cra_s0_agent_rf_source_ready), // .ready
.in_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (kernel_cra_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router router (
.sink_ready (address_span_extender_0_expanded_master_agent_cp_ready), // sink.ready
.sink_valid (address_span_extender_0_expanded_master_agent_cp_valid), // .valid
.sink_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.sink_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router_001 router_001 (
.sink_ready (kernel_cra_s0_agent_rp_ready), // sink.ready
.sink_valid (kernel_cra_s0_agent_rp_valid), // .valid
.sink_data (kernel_cra_s0_agent_rp_data), // .data
.sink_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux cmd_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_mux cmd_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux rsp_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.sink_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.sink_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_rsp_mux rsp_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (65),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (75),
.IN_PKT_BYTE_CNT_L (72),
.IN_PKT_TRANS_COMPRESSED_READ (66),
.IN_PKT_TRANS_WRITE (68),
.IN_PKT_BURSTWRAP_H (76),
.IN_PKT_BURSTWRAP_L (76),
.IN_PKT_BURST_SIZE_H (79),
.IN_PKT_BURST_SIZE_L (77),
.IN_PKT_RESPONSE_STATUS_H (97),
.IN_PKT_RESPONSE_STATUS_L (96),
.IN_PKT_TRANS_EXCLUSIVE (71),
.IN_PKT_BURST_TYPE_H (81),
.IN_PKT_BURST_TYPE_L (80),
.IN_PKT_ORI_BURST_SIZE_L (98),
.IN_PKT_ORI_BURST_SIZE_H (100),
.IN_ST_DATA_W (101),
.OUT_PKT_ADDR_H (101),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (111),
.OUT_PKT_BYTE_CNT_L (108),
.OUT_PKT_TRANS_COMPRESSED_READ (102),
.OUT_PKT_BURST_SIZE_H (115),
.OUT_PKT_BURST_SIZE_L (113),
.OUT_PKT_RESPONSE_STATUS_H (133),
.OUT_PKT_RESPONSE_STATUS_L (132),
.OUT_PKT_TRANS_EXCLUSIVE (107),
.OUT_PKT_BURST_TYPE_H (117),
.OUT_PKT_BURST_TYPE_L (116),
.OUT_PKT_ORI_BURST_SIZE_L (134),
.OUT_PKT_ORI_BURST_SIZE_H (136),
.OUT_ST_DATA_W (137),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_cmd_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_src_valid), // sink.valid
.in_channel (cmd_mux_src_channel), // .channel
.in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_src_ready), // .ready
.in_data (cmd_mux_src_data), // .data
.out_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (101),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (111),
.IN_PKT_BYTE_CNT_L (108),
.IN_PKT_TRANS_COMPRESSED_READ (102),
.IN_PKT_TRANS_WRITE (104),
.IN_PKT_BURSTWRAP_H (112),
.IN_PKT_BURSTWRAP_L (112),
.IN_PKT_BURST_SIZE_H (115),
.IN_PKT_BURST_SIZE_L (113),
.IN_PKT_RESPONSE_STATUS_H (133),
.IN_PKT_RESPONSE_STATUS_L (132),
.IN_PKT_TRANS_EXCLUSIVE (107),
.IN_PKT_BURST_TYPE_H (117),
.IN_PKT_BURST_TYPE_L (116),
.IN_PKT_ORI_BURST_SIZE_L (134),
.IN_PKT_ORI_BURST_SIZE_H (136),
.IN_ST_DATA_W (137),
.OUT_PKT_ADDR_H (65),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (75),
.OUT_PKT_BYTE_CNT_L (72),
.OUT_PKT_TRANS_COMPRESSED_READ (66),
.OUT_PKT_BURST_SIZE_H (79),
.OUT_PKT_BURST_SIZE_L (77),
.OUT_PKT_RESPONSE_STATUS_H (97),
.OUT_PKT_RESPONSE_STATUS_L (96),
.OUT_PKT_TRANS_EXCLUSIVE (71),
.OUT_PKT_BURST_TYPE_H (81),
.OUT_PKT_BURST_TYPE_L (80),
.OUT_PKT_ORI_BURST_SIZE_L (98),
.OUT_PKT_ORI_BURST_SIZE_H (100),
.OUT_ST_DATA_W (101),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_rsp_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_001_src_valid), // sink.valid
.in_channel (router_001_src_channel), // .channel
.in_startofpacket (router_001_src_startofpacket), // .startofpacket
.in_endofpacket (router_001_src_endofpacket), // .endofpacket
.in_ready (router_001_src_ready), // .ready
.in_data (router_001_src_data), // .data
.out_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (66),
.inUsePackets (0),
.inDataWidth (66),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (66),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (kernel_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (kernel_cra_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (kernel_cra_s0_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
endmodule
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: SDRAM_clock.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module SDRAM_clock (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "166.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "166.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "SDRAM_clock.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "83"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_clock.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_clock.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_clock.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_clock.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_clock.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_clock_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_clock_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
`timescale 1ns / 1ps
`define BCR_ADDR (23'b000_10_00_0_0_011_1_0_0_00_01_0_001)
// || | | ||| | | || | |||
// Address BCR -+' | | ||| | | || | |||
// Synchronous -------' | ||| | | || | |||
// Variable latency ---------' ||| | | || | |||
// Latency Counter (4 cycles) -----------''' | | || | |||
// ram_wait_i is active-high ---------------' | || | |||
// ram_wait_i asserted during delay ---------------' || | |||
// Default Drive Strength (1/2) ------------------------'' | |||
// Burst wraps within burst length ------------------------' |||
// Burst length is 4 words -----------------------------'''
module ramcon(
input reset_i,
input clk2x_i,
output [22:0] ram_adr_o,
inout [15:0] ram_dq_io,
output ram_ce_on,
output ram_adv_on,
output ram_oe_on,
output ram_we_on,
output ram_ub_on,
output ram_lb_on,
output ram_cre_o,
output ram_clk_o,
input ram_wait_i,
output wb_ack_o,
output [15:0] wb_dat_o,
input [15:0] wb_dat_i,
input [23:1] wb_adr_i,
input [1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
input wb_we_i,
output reset_o
);
wire ram_en_q;
wire ram_adv_o, ram_ce_o, ram_oe_o, ram_we_o, ram_be_valid;
wire dato_dq, dq_dati;
wire nt0, nt1, nt2, nt3, nt4, nt5;
reg t0, t1, t2, t3, t4, t5;
reg cfg;
wire cfg_o, adr_bcrcfg, clk_en;
// PSRAM power-on timing. Do not let the dogs out until
// the PSRAM chip has gone through its boot-up sequence.
// Wait 150us minimum, and to be conservative, a little
// extra. I've arbitrarily selected 32ms, assuming 50MHz
// input on clk2x_i.
reg [14:0] resetCounter;
always @(posedge clk2x_i) begin
if(reset_i) begin
resetCounter <= 0;
end
else begin
if(resetCounter[14]) begin
resetCounter <= resetCounter;
end
else begin
resetCounter <= resetCounter + 1;
end
end
end
wire reset_sans_cfg = ~resetCounter[14];
assign reset_o = reset_sans_cfg | cfg;
// Bus bridge random logic.
reg [15:0] wb_dat_or;
assign ram_adr_o = adr_bcrcfg ? `BCR_ADDR : wb_adr_i;
assign wb_dat_o = wb_dat_or;
always @(negedge clk2x_i) begin
if(dato_dq) wb_dat_or <= ram_dq_io;
end
assign ram_dq_io = dq_dati ? wb_dat_i : 16'hzzzz;
assign ram_clk_o = ~clk2x_i & clk_en;
// Bus bridge state Machine.
kseq ks(
.t5(t5),
.t4(t4),
.t3(t3),
.t2(t2),
.t1(t1),
.wb_we_i(wb_we_i),
.t0(t0),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.reset_i(reset_sans_cfg),
.wb_ack_o(wb_ack_o),
.dato_dq(dato_dq),
.dq_dati(dq_dati),
.ram_oe_o(ram_oe_o),
.ram_we_o(ram_we_o),
.ram_ce_o(ram_ce_o),
.ram_adv_o(ram_adv_o),
.ram_be_valid(ram_be_valid),
.nt5(nt5),
.nt4(nt4),
.nt3(nt3),
.nt2(nt2),
.nt1(nt1),
.nt0(nt0),
.adr_bcrcfg(adr_bcrcfg),
.ram_cre_o(ram_cre_o),
.cfg_o(cfg_o),
.cfg(cfg),
.clk_en(clk_en),
.ram_wait_i(ram_wait_i)
);
assign ram_adv_on = reset_sans_cfg | ~ram_adv_o;
assign ram_ce_on = reset_sans_cfg | ~ram_ce_o;
assign ram_oe_on = reset_sans_cfg | ~ram_oe_o;
assign ram_we_on = reset_sans_cfg | ~ram_we_o;
assign ram_ub_on = reset_sans_cfg | ~(ram_be_valid & wb_sel_i[1]);
assign ram_lb_on = reset_sans_cfg | ~(ram_be_valid & wb_sel_i[0]);
always @(posedge clk2x_i) begin
t0 <= nt0;
t1 <= nt1;
t2 <= nt2;
t3 <= nt3;
t4 <= nt4;
t5 <= nt5;
cfg <= cfg_o;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_1_V
`define SKY130_FD_SC_HD__NAND3_1_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR2_PP_SYMBOL_V
`define SKY130_FD_SC_LS__XNOR2_PP_SYMBOL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xnor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR2_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX4_TB_V
`define SKY130_FD_SC_LS__MUX4_TB_V
/**
* mux4: 4-input multiplexer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__mux4.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 A0 = 1'b1;
#240 A1 = 1'b1;
#260 A2 = 1'b1;
#280 A3 = 1'b1;
#300 S0 = 1'b1;
#320 S1 = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 A0 = 1'b0;
#440 A1 = 1'b0;
#460 A2 = 1'b0;
#480 A3 = 1'b0;
#500 S0 = 1'b0;
#520 S1 = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 S1 = 1'b1;
#720 S0 = 1'b1;
#740 A3 = 1'b1;
#760 A2 = 1'b1;
#780 A1 = 1'b1;
#800 A0 = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 S1 = 1'bx;
#920 S0 = 1'bx;
#940 A3 = 1'bx;
#960 A2 = 1'bx;
#980 A1 = 1'bx;
#1000 A0 = 1'bx;
end
sky130_fd_sc_ls__mux4 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX4_TB_V
|
`timescale 1ns / 1ps
/*******************************************************************************
* Engineer: Robin zhang
* Create Date: 2016.09.10
* Module Name: spi_slave
*******************************************************************************/
module spi_slave(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_status;
reg[2:0] sckr;
reg[2:0] sselr;
reg[1:0] mosir;
reg[2:0] bitcnt;
reg[7:0] bytecnt;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
reg[7:0] received_memory;
reg [7:0] byte_data_sent;
reg [7:0] cnt;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire ssel_startmessage;
wire ssel_endmessage;
wire mosi_data;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sckr <= 3'h0;
else
sckr <= {sckr[1:0],sck};
end
assign sck_risingedge = (sckr[2:1] == 2'b01) ? 1'b1 : 1'b0;
assign sck_fallingedge = (sckr[2:1] == 2'b10) ? 1'b1 : 1'b0;
/*******************************************************************************
*detect starts at falling edge and stops at rising edge of ssel
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sselr <= 3'h0;
else
sselr <= {sselr[1:0],ssel};
end
assign ssel_active = (~sselr[1]) ? 1'b1 : 1'b0; // SSEL is active low
assign ssel_startmessage = (sselr[2:1]==2'b10) ? 1'b1 : 1'b0; // message starts at falling edge
assign ssel_endmessage = (sselr[2:1]==2'b01) ? 1'b1 : 1'b0; // message stops at rising edge
/*******************************************************************************
*read from mosi
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
mosir <= 2'h0;
else
mosir <={mosir[0],mosi};
end
assign mosi_data = mosir[1];
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
bitcnt <= 3'b000;
byte_data_received <= 8'h0;
end
else begin
if(~ssel_active)
bitcnt <= 3'b000;
else begin
if(sck_risingedge)begin
bitcnt <= bitcnt + 3'b001;
byte_data_received <= {byte_data_received[6:0], mosi_data};
end
else begin
bitcnt <= bitcnt;
byte_data_received <= byte_data_received;
end
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_received <= 1'b0;
else
byte_received <= ssel_active && sck_risingedge && (bitcnt==3'b111);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
bytecnt <= 8'h0;
received_memory <= 8'h0;
end
else begin
if(byte_received) begin
bytecnt <= bytecnt + 1'b1;
received_memory <= (byte_data_received == bytecnt) ? (received_memory + 1'b1) : received_memory;
end
else begin
bytecnt <= bytecnt;
received_memory <= received_memory;
end
end
end
/*******************************************************************************
*SPI slave send date
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt<= 8'h0;
else begin
if(byte_received)
cnt<=cnt+8'h1; // count the messages
else
cnt<=cnt;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_data_sent <= 8'h0;
else begin
if(ssel_active && sck_fallingedge) begin
if(bitcnt==3'b001)
byte_data_sent <= cnt; // after that, we send 0s
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
else
byte_data_sent <= byte_data_sent;
end
end
assign miso = byte_data_sent[7]; // send MSB first
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
recived_status <= 1'b0;
else
recived_status <= (received_memory == 8'd64) ? 1'b1 : 1'b0;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_merge_enc.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module ecc_merge_enc
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
mc_wrdata, mc_wrdata_mask,
// Inputs
clk, rst, wr_data, wr_data_mask, rd_merge_data, h_rows, raw_not_ecc
);
input clk;
input rst;
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask;
input [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data_r;
reg [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask_r;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data_r;
always @(posedge clk) wr_data_r <= #TCQ wr_data;
always @(posedge clk) wr_data_mask_r <= #TCQ wr_data_mask;
always @(posedge clk) rd_merge_data_r <= #TCQ rd_merge_data;
// Merge new data with memory read data.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] merged_data;
genvar h;
genvar i;
generate
for (h=0; h<2*nCK_PER_CLK; h=h+1) begin : merge_data_outer
for (i=0; i<DATA_WIDTH/8; i=i+1) begin : merge_data_inner
assign merged_data[h*PAYLOAD_WIDTH+i*8+:8] =
wr_data_mask_r[h*DATA_WIDTH/8+i]
? rd_merge_data_r[h*DATA_WIDTH+i*8+:8]
: wr_data_r[h*PAYLOAD_WIDTH+i*8+:8];
end
if (PAYLOAD_WIDTH > DATA_WIDTH)
assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]=
wr_data_r[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH];
end
endgenerate
// Generate ECC and overlay onto mc_wrdata.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK-1:0] raw_not_ecc;
reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r;
always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc;
output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata;
genvar j;
integer k;
generate
for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word
always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin
mc_wrdata[j*DQ_WIDTH+:DQ_WIDTH] =
{{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}},
merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]};
for (k=0; k<ECC_WIDTH; k=k+1)
if (~raw_not_ecc_r[j])
mc_wrdata[j*DQ_WIDTH+CODE_WIDTH-k-1] =
^(merged_data[j*PAYLOAD_WIDTH+:DATA_WIDTH] &
h_rows[k*CODE_WIDTH+:DATA_WIDTH]);
end
end
endgenerate
// Set all DRAM masks to zero.
output wire[2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask;
assign mc_wrdata_mask = {2*nCK_PER_CLK*DQ_WIDTH/8{1'b0}};
endmodule
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module ALU16(A, B, sel, out);
input [15:0] A, B;
input [2:0] sel;
output [15:0] out;
assign less = 1'b0;;
//Still need to account for less
wire [15:0] c;
wire set;
alu_slice a1(A[0], B[0], sel[2], set, sel, c[0], out[0]);
alu_slice a2(A[1], B[1], c[0], less, sel, c[1], out[1]);
alu_slice a3(A[2], B[2], c[1], less, sel, c[2], out[2]);
alu_slice a4(A[3], B[3], c[2], less, sel, c[3], out[3]);
alu_slice a5(A[4], B[4], c[3], less, sel, c[4], out[4]);
alu_slice a6(A[5], B[5], c[4], less, sel, c[5], out[5]);
alu_slice a7(A[6], B[6], c[5], less, sel, c[6], out[6]);
alu_slice a8(A[7], B[7], c[6], less, sel, c[7], out[7]);
alu_slice a9(A[8], B[8], c[7], less, sel, c[8], out[8]);
alu_slice a10(A[9], B[9], c[8], less, sel, c[9], out[9]);
alu_slice a11(A[10], B[10], c[9], less, sel, c[10], out[10]);
alu_slice a12(A[11], B[11], c[10], less, sel, c[11], out[11]);
alu_slice a13(A[12], B[12], c[11], less, sel, c[12], out[12]);
alu_slice a14(A[13], B[13], c[12], less, sel, c[13], out[13]);
alu_slice a15(A[14], B[14], c[13], less, sel, c[14], out[14]);
alu_slice_msb a16(A[15], B[15], c[14], less, sel, c[15], out[15],set);
endmodule
|
module image_to_ppfifo #(
parameter BUFFER_SIZE = 10
)(
input clk,
input rst,
input i_enable,
input i_hsync, // vga hsync signal
input i_vsync, // vga vsync signal
input [2:0] i_red, // vga red signal
input [2:0] i_green, // vga green signal
input [1:0] i_blue, // vga blue signal
output reg o_frame_finished,
//Memory FIFO Interface
output o_rfifo_ready,
input i_rfifo_activate,
input i_rfifo_strobe,
output [31:0] o_rfifo_data,
output [23:0] o_rfifo_size
);
//Local Parameters
localparam IDLE = 4'h0;
localparam PROCESS_IMAGE = 4'h1;
//Registers/Wires
reg r_prev_vsync;
wire w_neg_edge_vsync;
//ppfifo interface
wire [1:0] w_write_ready;
reg [1:0] r_write_activate;
wire [23:0] w_write_fifo_size;
reg r_write_strobe;
reg [23:0] r_write_count;
reg [31:0] r_write_data;
//Submodules
ppfifo p2m
#(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (BUFFER_SIZE )
)fifo (
//universal input
.reset (rst ),
//write side
.write_clock (clk ),
.write_ready (w_write_ready ),
.write_activate (r_write_activate ),
.write_fifo_size (w_write_fifo_size ),
.write_strobe (r_write_strobe ),
.write_data (r_write_data ),
// .inactive (w_inactive ),
//read side
.read_clock (clk ),
.read_strobe (i_rfifo_strobe ),
.read_ready (o_rfifo_ready ),
.read_activate (i_rfifo_activate ),
.read_count (o_rfifo_size ),
.read_data (o_rfifo_data )
);
//Asynchronous Logic
assign w_neg_edge_vsync = (r_prev_vsync & !i_vsync);
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
r_write_activate <= 0;
r_write_strobe <= 0;
r_write_count <= 0;
r_write_data <= 0;
o_frame_finished <= 0;
r_prev_vsync <= 0;
end
else begin
o_frame_finished <= 0;
r_write_strobe <= 0;
if (i_enable && (r_write_activate == 0) && (w_write_ready > 0)) begin
r_write_count <= 0;
if (w_write_ready[0]) begin
r_write_activate[0] <= 1;
end
else begin
r_write_activate[1] <= 1;
end
end
if (i_enable && (r_write_activate > 0)) begin
if (i_hsync) begin
r_write_data <= {24'h000000, i_red, i_green, i_blue};
r_write_strobe <= 1;
r_write_count <= r_write_count + 1;
if (r_write_count >= w_write_fifo_size - 1) begin
r_write_activate <= 0;
end
end
else if (!i_hsync) begin
r_write_activate <= 0;
end
if (w_neg_edge_vsync) begin
o_frame_finished <= 1;
end
end
r_prev_vsync <= i_vsync;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221O_1_V
`define SKY130_FD_SC_MS__A221O_1_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221o_1 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221O_1_V
|
// The cordic algorithm
// This will be a pipelined design that processes
// one angle rotation per clock cycle. There is
// one rotation per input bit.
// Rotation angle must be between -pi/2 to pi/2
// Angle is stated in I3Q13 as it must accomodate +- 1.57...
// Output is approx 1.64 times larger than reality due to
// the scale factor, which is sum(1 / sqrt(1 + 2^-i)^2) over
// i in 0->Width. It's 1.6467602581210652 to more exact
module cordic(
clk,
xI, // Input X value
yI, // Input Y Value
angle, // Rotation angle in radians
xO,
yO
);
// Bitness of all relevant buses
parameter WIDTH = 16;
parameter ANGLE_WIDTH = 32;
parameter ATAN_INITIAL_FILE = "../mems/atan16_32.hex";
// Inputs
/* verilator lint_off UNUSED */
input clk;
input signed[WIDTH-1:0] xI, yI;
input signed[ANGLE_WIDTH-1:0] angle;
/* verilator lint_on UNUSED */
// Outputs
output signed[WIDTH-1:0] xO, yO;
// Pipeline
reg signed[WIDTH-1:0] x_pl[WIDTH:0]; // X pipeline stages
reg signed[WIDTH-1:0] y_pl[WIDTH:0]; // Y pipeline stages
reg signed[ANGLE_WIDTH-1:0] a_pl[WIDTH:0]; // Angle pipeline stages
// atan_lut[i] is the result of atan(x) w/ x = 2^-i in radians
reg[ANGLE_WIDTH-1:0] atan_lut[WIDTH-1:0];
initial begin
$readmemh(ATAN_INITIAL_FILE, atan_lut);
end
// Result depends on angle > 0 for +/-
// xO = xI -/+ (yI >> i)
// yO = yI +/- (xI >> i)
wire[1:0] quadrant;
assign quadrant = angle[31:30];
integer i;
always @(posedge clk) begin
// Preprocess angle before entering pipeline.
case (quadrant)
2'b00, // Tangent is fine in this quadrants, no reflection
2'b11: begin
x_pl[0] <= xI;
y_pl[0] <= yI;
a_pl[0] <= angle;
end
2'b01: begin
x_pl[0] <= -yI;
y_pl[0] <= xI;
a_pl[0] <= {2'b00, angle[29:0]};
end
2'b10: begin
x_pl[0] <= yI;
y_pl[0] <= -xI;
a_pl[0] <= {2'b11, angle[29:0]};
end
endcase
// Generate pipeline stages. Might need to break this up if it synths to something awful.
// Will probably need an alway @(*) block if so to hold the combinational parts.
for(i = 0; i < WIDTH; i = i + 1) begin
x_pl[i+1] <= (a_pl[i] > 0) ? x_pl[i] - (y_pl[i] >>> i) : x_pl[i] + (y_pl[i] >>> i);
y_pl[i+1] <= (a_pl[i] > 0) ? y_pl[i] + (x_pl[i] >>> i) : y_pl[i] - (x_pl[i] >>> i);
a_pl[i+1] <= (a_pl[i] > 0) ? a_pl[i] - atan_lut[i] : a_pl[i] + atan_lut[i];
end
end
// Set the output. That sure looks like it means x[0] doesn't it? But it's xO...utput.
assign xO = x_pl[WIDTH-1];
assign yO = y_pl[WIDTH-1];
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Tue Sep 17 19:44:40 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_gcd_0_0/gcd_zynq_snick_gcd_0_0_stub.v
// Design : gcd_zynq_snick_gcd_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "gcd,Vivado 2018.2" *)
module gcd_zynq_snick_gcd_0_0(s_axi_gcd_bus_AWADDR,
s_axi_gcd_bus_AWVALID, s_axi_gcd_bus_AWREADY, s_axi_gcd_bus_WDATA, s_axi_gcd_bus_WSTRB,
s_axi_gcd_bus_WVALID, s_axi_gcd_bus_WREADY, s_axi_gcd_bus_BRESP, s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_BREADY, s_axi_gcd_bus_ARADDR, s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_ARREADY, s_axi_gcd_bus_RDATA, s_axi_gcd_bus_RRESP, s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RREADY, ap_clk, ap_rst_n, interrupt)
/* synthesis syn_black_box black_box_pad_pin="s_axi_gcd_bus_AWADDR[5:0],s_axi_gcd_bus_AWVALID,s_axi_gcd_bus_AWREADY,s_axi_gcd_bus_WDATA[31:0],s_axi_gcd_bus_WSTRB[3:0],s_axi_gcd_bus_WVALID,s_axi_gcd_bus_WREADY,s_axi_gcd_bus_BRESP[1:0],s_axi_gcd_bus_BVALID,s_axi_gcd_bus_BREADY,s_axi_gcd_bus_ARADDR[5:0],s_axi_gcd_bus_ARVALID,s_axi_gcd_bus_ARREADY,s_axi_gcd_bus_RDATA[31:0],s_axi_gcd_bus_RRESP[1:0],s_axi_gcd_bus_RVALID,s_axi_gcd_bus_RREADY,ap_clk,ap_rst_n,interrupt" */;
input [5:0]s_axi_gcd_bus_AWADDR;
input s_axi_gcd_bus_AWVALID;
output s_axi_gcd_bus_AWREADY;
input [31:0]s_axi_gcd_bus_WDATA;
input [3:0]s_axi_gcd_bus_WSTRB;
input s_axi_gcd_bus_WVALID;
output s_axi_gcd_bus_WREADY;
output [1:0]s_axi_gcd_bus_BRESP;
output s_axi_gcd_bus_BVALID;
input s_axi_gcd_bus_BREADY;
input [5:0]s_axi_gcd_bus_ARADDR;
input s_axi_gcd_bus_ARVALID;
output s_axi_gcd_bus_ARREADY;
output [31:0]s_axi_gcd_bus_RDATA;
output [1:0]s_axi_gcd_bus_RRESP;
output s_axi_gcd_bus_RVALID;
input s_axi_gcd_bus_RREADY;
input ap_clk;
input ap_rst_n;
output interrupt;
endmodule
|
`timescale 1ns/10ps
module soc_system_pll_pwm(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("25.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("125.500000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__probe_p (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
);
// Module ports
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBE_P_BEHAVIORAL_PP_V
|
Require Import Coq.Lists.List.
Require Import Coq.omega.Omega.
Require Import Coq.Arith.Peano_dec.
Require Import Coq.Classes.Morphisms.
Require Import Crypto.Tactics.VerdiTactics.
Require Import Coq.Numbers.Natural.Peano.NPeano.
Require Import Crypto.Util.NatUtil.
Require Export Crypto.Util.FixCoqMistakes.
Create HintDb distr_length discriminated.
Create HintDb simpl_set_nth discriminated.
Create HintDb simpl_update_nth discriminated.
Create HintDb simpl_nth_default discriminated.
Create HintDb simpl_nth_error discriminated.
Create HintDb simpl_firstn discriminated.
Create HintDb simpl_skipn discriminated.
Create HintDb simpl_fold_right discriminated.
Create HintDb simpl_sum_firstn discriminated.
Create HintDb pull_nth_error discriminated.
Create HintDb push_nth_error discriminated.
Create HintDb pull_nth_default discriminated.
Create HintDb push_nth_default discriminated.
Create HintDb pull_firstn discriminated.
Create HintDb push_firstn discriminated.
Create HintDb pull_skipn discriminated.
Create HintDb push_skipn discriminated.
Create HintDb pull_update_nth discriminated.
Create HintDb push_update_nth discriminated.
Create HintDb znonzero discriminated.
Hint Rewrite
@app_length
@rev_length
@map_length
@seq_length
@fold_left_length
@split_length_l
@split_length_r
@firstn_length
@combine_length
@prod_length
: distr_length.
Hint Extern 1 => progress autorewrite with distr_length in * : distr_length.
Ltac distr_length := autorewrite with distr_length in *;
try solve [simpl in *; omega].
Module Export List.
Local Set Implicit Arguments.
Import ListNotations.
(** From the 8.6 Standard Library *)
Section Elts.
Variable A : Type.
(** Results about [nth_error] *)
Lemma nth_error_In l n (x : A) : nth_error l n = Some x -> In x l.
Proof.
revert n. induction l as [|a l IH]; intros [|n]; simpl; try easy.
- injection 1; auto.
- eauto.
Qed.
End Elts.
Section Map.
Variables (A : Type) (B : Type).
Variable f : A -> B.
Lemma map_cons (x:A)(l:list A) : map f (x::l) = (f x) :: (map f l).
Proof.
reflexivity.
Qed.
End Map.
Lemma in_seq len start n :
In n (seq start len) <-> start <= n < start+len.
Proof.
revert start. induction len; simpl; intros.
- rewrite <- plus_n_O. split;[easy|].
intros (H,H'). apply (Lt.lt_irrefl _ (Lt.le_lt_trans _ _ _ H H')).
- rewrite IHlen, <- plus_n_Sm; simpl; split.
* intros [H|H]; subst; intuition auto with arith.
* intros (H,H'). destruct (Lt.le_lt_or_eq _ _ H); intuition.
Qed.
Section Facts.
Variable A : Type.
Theorem length_zero_iff_nil (l : list A):
length l = 0 <-> l=[].
Proof.
split; [now destruct l | now intros ->].
Qed.
End Facts.
Section Repeat.
Variable A : Type.
Fixpoint repeat (x : A) (n: nat ) :=
match n with
| O => []
| S k => x::(repeat x k)
end.
Theorem repeat_length x n:
length (repeat x n) = n.
Proof.
induction n as [| k Hrec]; simpl; rewrite ?Hrec; reflexivity.
Qed.
Theorem repeat_spec n x y:
In y (repeat x n) -> y=x.
Proof.
induction n as [|k Hrec]; simpl; destruct 1; auto.
Qed.
End Repeat.
Section Cutting.
Variable A : Type.
Local Notation firstn := (@firstn A).
Lemma firstn_nil n: firstn n [] = [].
Proof. induction n; now simpl. Qed.
Lemma firstn_cons n a l: firstn (S n) (a::l) = a :: (firstn n l).
Proof. now simpl. Qed.
Lemma firstn_all l: firstn (length l) l = l.
Proof. induction l as [| ? ? H]; simpl; [reflexivity | now rewrite H]. Qed.
Lemma firstn_all2 n: forall (l:list A), (length l) <= n -> firstn n l = l.
Proof. induction n as [|k iHk].
- intro. inversion 1 as [H1|?].
rewrite (length_zero_iff_nil l) in H1. subst. now simpl.
- destruct l as [|x xs]; simpl.
* now reflexivity.
* simpl. intro H. apply Peano.le_S_n in H. f_equal. apply iHk, H.
Qed.
Lemma firstn_O l: firstn 0 l = [].
Proof. now simpl. Qed.
Lemma firstn_le_length n: forall l:list A, length (firstn n l) <= n.
Proof.
induction n as [|k iHk]; simpl; [auto | destruct l as [|x xs]; simpl].
- auto with arith.
- apply le_n_S, iHk.
Qed.
Lemma firstn_length_le: forall l:list A, forall n:nat,
n <= length l -> length (firstn n l) = n.
Proof. induction l as [|x xs Hrec].
- simpl. intros n H. apply le_n_0_eq in H. rewrite <- H. now simpl.
- destruct n.
* now simpl.
* simpl. intro H. apply le_S_n in H. now rewrite (Hrec n H).
Qed.
Lemma firstn_app n:
forall l1 l2,
firstn n (l1 ++ l2) = (firstn n l1) ++ (firstn (n - length l1) l2).
Proof. induction n as [|k iHk]; intros l1 l2.
- now simpl.
- destruct l1 as [|x xs].
* unfold List.firstn at 2, length. now rewrite 2!app_nil_l, <- minus_n_O.
* rewrite <- app_comm_cons. simpl. f_equal. apply iHk.
Qed.
Lemma firstn_app_2 n:
forall l1 l2,
firstn ((length l1) + n) (l1 ++ l2) = l1 ++ firstn n l2.
Proof. induction n as [| k iHk];intros l1 l2.
- unfold List.firstn at 2. rewrite <- plus_n_O, app_nil_r.
rewrite firstn_app. rewrite <- minus_diag_reverse.
unfold List.firstn at 2. rewrite app_nil_r. apply firstn_all.
- destruct l2 as [|x xs].
* simpl. rewrite app_nil_r. apply firstn_all2. auto with arith.
* rewrite firstn_app. assert (H0 : (length l1 + S k - length l1) = S k).
auto with arith.
rewrite H0, firstn_all2; [reflexivity | auto with arith].
Qed.
Lemma firstn_firstn:
forall l:list A,
forall i j : nat,
firstn i (firstn j l) = firstn (min i j) l.
Proof. induction l as [|x xs Hl].
- intros. simpl. now rewrite ?firstn_nil.
- destruct i.
* intro. now simpl.
* destruct j.
+ now simpl.
+ simpl. f_equal. apply Hl.
Qed.
End Cutting.
End List.
Hint Rewrite @firstn_skipn : simpl_firstn.
Hint Rewrite @firstn_skipn : simpl_skipn.
Hint Rewrite @firstn_nil @firstn_cons @List.firstn_all @firstn_O @firstn_app_2 @List.firstn_firstn : push_firstn.
Hint Rewrite @firstn_nil @firstn_cons @List.firstn_all @firstn_O @firstn_app_2 @List.firstn_firstn : simpl_firstn.
Hint Rewrite @firstn_app : push_firstn.
Hint Rewrite <- @firstn_cons @firstn_app @List.firstn_firstn : pull_firstn.
Hint Rewrite @firstn_all2 @removelast_firstn @firstn_removelast using omega : push_firstn.
Hint Rewrite @firstn_all2 @removelast_firstn @firstn_removelast using omega : simpl_firstn.
Local Arguments value / _ _.
Local Arguments error / _.
Definition sum_firstn l n := fold_right Z.add 0%Z (firstn n l).
Fixpoint map2 {A B C} (f : A -> B -> C) (la : list A) (lb : list B) : list C :=
match la with
| nil => nil
| a :: la' => match lb with
| nil => nil
| b :: lb' => f a b :: map2 f la' lb'
end
end.
(* xs[n] := f xs[n] *)
Fixpoint update_nth {T} n f (xs:list T) {struct n} :=
match n with
| O => match xs with
| nil => nil
| x'::xs' => f x'::xs'
end
| S n' => match xs with
| nil => nil
| x'::xs' => x'::update_nth n' f xs'
end
end.
(* xs[n] := x *)
Definition set_nth {T} n x (xs:list T)
:= update_nth n (fun _ => x) xs.
Definition splice_nth {T} n (x:T) xs := firstn n xs ++ x :: skipn (S n) xs.
Hint Unfold splice_nth.
Ltac boring :=
simpl; intuition auto with zarith datatypes;
repeat match goal with
| [ H : _ |- _ ] => rewrite H; clear H
| [ |- appcontext[match ?pf with end] ] => solve [ case pf ]
| _ => progress autounfold in *
| _ => progress autorewrite with core
| _ => progress simpl in *
| _ => progress intuition auto with zarith datatypes
end; eauto.
Ltac boring_list :=
repeat match goal with
| _ => progress boring
| _ => progress autorewrite with distr_length simpl_nth_default simpl_update_nth simpl_set_nth simpl_nth_error in *
end.
Lemma nth_default_cons : forall {T} (x u0 : T) us, nth_default x (u0 :: us) 0 = u0.
Proof. auto. Qed.
Hint Rewrite @nth_default_cons : simpl_nth_default.
Hint Rewrite @nth_default_cons : push_nth_default.
Lemma nth_default_cons_S : forall {A} us (u0 : A) n d,
nth_default d (u0 :: us) (S n) = nth_default d us n.
Proof. boring. Qed.
Hint Rewrite @nth_default_cons_S : simpl_nth_default.
Hint Rewrite @nth_default_cons_S : push_nth_default.
Lemma nth_default_nil : forall {T} n (d : T), nth_default d nil n = d.
Proof. induction n; boring. Qed.
Hint Rewrite @nth_default_nil : simpl_nth_default.
Hint Rewrite @nth_default_nil : push_nth_default.
Lemma nth_error_nil_error : forall {A} n, nth_error (@nil A) n = None.
Proof. induction n; boring. Qed.
Hint Rewrite @nth_error_nil_error : simpl_nth_error.
Ltac nth_tac' :=
intros; simpl in *; unfold error,value in *; repeat progress (match goal with
| [ |- context[nth_error nil ?n] ] => rewrite nth_error_nil_error
| [ H: ?x = Some _ |- context[match ?x with Some _ => ?a | None => ?a end ] ] => destruct x
| [ H: ?x = None _ |- context[match ?x with Some _ => ?a | None => ?a end ] ] => destruct x
| [ |- context[match ?x with Some _ => ?a | None => ?a end ] ] => destruct x
| [ |- context[match nth_error ?xs ?i with Some _ => _ | None => _ end ] ] => case_eq (nth_error xs i); intros
| [ |- context[(if lt_dec ?a ?b then _ else _) = _] ] => destruct (lt_dec a b)
| [ |- context[_ = (if lt_dec ?a ?b then _ else _)] ] => destruct (lt_dec a b)
| [ H: context[(if lt_dec ?a ?b then _ else _) = _] |- _ ] => destruct (lt_dec a b)
| [ H: context[_ = (if lt_dec ?a ?b then _ else _)] |- _ ] => destruct (lt_dec a b)
| [ H: _ /\ _ |- _ ] => destruct H
| [ H: Some _ = Some _ |- _ ] => injection H; clear H; intros; subst
| [ H: None = Some _ |- _ ] => inversion H
| [ H: Some _ = None |- _ ] => inversion H
| [ |- Some _ = Some _ ] => apply f_equal
end); eauto; try (autorewrite with list in *); try omega; eauto.
Lemma nth_error_map : forall A B (f:A->B) i xs y,
nth_error (map f xs) i = Some y ->
exists x, nth_error xs i = Some x /\ f x = y.
Proof.
induction i; destruct xs; nth_tac'.
Qed.
Lemma nth_error_seq : forall i start len,
nth_error (seq start len) i =
if lt_dec i len
then Some (start + i)
else None.
induction i; destruct len; nth_tac'; erewrite IHi; nth_tac'.
Qed.
Lemma nth_error_error_length : forall A i (xs:list A), nth_error xs i = None ->
i >= length xs.
Proof.
induction i; destruct xs; nth_tac'; try specialize (IHi _ H); omega.
Qed.
Lemma nth_error_value_length : forall A i (xs:list A) x, nth_error xs i = Some x ->
i < length xs.
Proof.
induction i; destruct xs; nth_tac'; try specialize (IHi _ _ H); omega.
Qed.
Lemma nth_error_length_error : forall A i (xs:list A),
i >= length xs ->
nth_error xs i = None.
Proof.
induction i; destruct xs; nth_tac'; rewrite IHi by omega; auto.
Qed.
Hint Resolve nth_error_length_error.
Hint Rewrite @nth_error_length_error using omega : simpl_nth_error.
Lemma map_nth_default : forall (A B : Type) (f : A -> B) n x y l,
(n < length l) -> nth_default y (map f l) n = f (nth_default x l n).
Proof.
intros.
unfold nth_default.
erewrite map_nth_error.
reflexivity.
nth_tac'.
pose proof (nth_error_error_length A n l H0).
omega.
Qed.
Lemma map_nil : forall A B (f : A -> B), map f nil = nil.
Proof. reflexivity. Qed.
(* Note: this is a duplicate of a lemma that exists in 8.5, included for
8.4 support *)
Lemma In_nth : forall {A} (x : A) d xs, In x xs ->
exists i, i < length xs /\ nth i xs d = x.
Proof.
induction xs; intros;
match goal with H : In _ _ |- _ => simpl in H; destruct H end.
+ subst. exists 0. simpl; split; auto || omega.
+ destruct IHxs as [i [ ]]; auto.
exists (S i).
split; auto; simpl; try omega.
Qed.
Hint Rewrite @map_nth_default using omega : push_nth_default.
Ltac nth_tac :=
repeat progress (try nth_tac'; try (match goal with
| [ H: nth_error (map _ _) _ = Some _ |- _ ] => destruct (nth_error_map _ _ _ _ _ _ H); clear H
| [ H: nth_error (seq _ _) _ = Some _ |- _ ] => rewrite nth_error_seq in H
| [H: nth_error _ _ = None |- _ ] => specialize (nth_error_error_length _ _ _ H); intro; clear H
end)).
Lemma app_cons_app_app : forall T xs (y:T) ys, xs ++ y :: ys = (xs ++ (y::nil)) ++ ys.
Proof. induction xs; boring. Qed.
Lemma unfold_set_nth {T} n x
: forall xs,
@set_nth T n x xs
= match n with
| O => match xs with
| nil => nil
| x'::xs' => x::xs'
end
| S n' => match xs with
| nil => nil
| x'::xs' => x'::set_nth n' x xs'
end
end.
Proof.
induction n; destruct xs; reflexivity.
Qed.
Lemma simpl_set_nth_0 {T} x
: forall xs,
@set_nth T 0 x xs
= match xs with
| nil => nil
| x'::xs' => x::xs'
end.
Proof. intro; rewrite unfold_set_nth; reflexivity. Qed.
Lemma simpl_set_nth_S {T} x n
: forall xs,
@set_nth T (S n) x xs
= match xs with
| nil => nil
| x'::xs' => x'::set_nth n x xs'
end.
Proof. intro; rewrite unfold_set_nth; reflexivity. Qed.
Hint Rewrite @simpl_set_nth_S @simpl_set_nth_0 : simpl_set_nth.
Lemma update_nth_ext {T} f g n
: forall xs, (forall x, nth_error xs n = Some x -> f x = g x)
-> @update_nth T n f xs = @update_nth T n g xs.
Proof.
induction n; destruct xs; simpl; intros H;
try rewrite IHn; try rewrite H;
try congruence; trivial.
Qed.
Global Instance update_nth_Proper {T}
: Proper (eq ==> pointwise_relation _ eq ==> eq ==> eq) (@update_nth T).
Proof. repeat intro; subst; apply update_nth_ext; trivial. Qed.
Lemma update_nth_id_eq_specific {T} f n
: forall (xs : list T) (H : forall x, nth_error xs n = Some x -> f x = x),
update_nth n f xs = xs.
Proof.
induction n; destruct xs; simpl; intros;
try rewrite IHn; try rewrite H; unfold value in *;
try congruence; assumption.
Qed.
Hint Rewrite @update_nth_id_eq_specific using congruence : simpl_update_nth.
Lemma update_nth_id_eq : forall {T} f (H : forall x, f x = x) n (xs : list T),
update_nth n f xs = xs.
Proof. intros; apply update_nth_id_eq_specific; trivial. Qed.
Hint Rewrite @update_nth_id_eq using congruence : simpl_update_nth.
Lemma update_nth_id : forall {T} n (xs : list T),
update_nth n (fun x => x) xs = xs.
Proof. intros; apply update_nth_id_eq; trivial. Qed.
Hint Rewrite @update_nth_id : simpl_update_nth.
Lemma nth_update_nth : forall m {T} (xs:list T) (n:nat) (f:T -> T),
nth_error (update_nth m f xs) n =
if eq_nat_dec n m
then option_map f (nth_error xs n)
else nth_error xs n.
Proof.
induction m.
{ destruct n, xs; auto. }
{ destruct xs, n; intros; simpl; auto;
[ | rewrite IHm ]; clear IHm;
edestruct eq_nat_dec; reflexivity. }
Qed.
Hint Rewrite @nth_update_nth : push_nth_error.
Hint Rewrite <- @nth_update_nth : pull_nth_error.
Lemma length_update_nth : forall {T} i f (xs:list T), length (update_nth i f xs) = length xs.
Proof.
induction i, xs; boring.
Qed.
Hint Rewrite @length_update_nth : distr_length.
(** TODO: this is in the stdlib in 8.5; remove this when we move to 8.5-only *)
Lemma nth_error_None : forall (A : Type) (l : list A) (n : nat), nth_error l n = None <-> length l <= n.
Proof.
intros A l n.
destruct (le_lt_dec (length l) n) as [H|H];
split; intro H';
try omega;
try (apply nth_error_length_error in H; tauto);
try (apply nth_error_error_length in H'; omega).
Qed.
(** TODO: this is in the stdlib in 8.5; remove this when we move to 8.5-only *)
Lemma nth_error_Some : forall (A : Type) (l : list A) (n : nat), nth_error l n <> None <-> n < length l.
Proof. intros; rewrite nth_error_None; split; omega. Qed.
Lemma nth_set_nth : forall m {T} (xs:list T) (n:nat) x,
nth_error (set_nth m x xs) n =
if eq_nat_dec n m
then (if lt_dec n (length xs) then Some x else None)
else nth_error xs n.
Proof.
intros; unfold set_nth; rewrite nth_update_nth.
destruct (nth_error xs n) eqn:?, (lt_dec n (length xs)) as [p|p];
rewrite <- nth_error_Some in p;
solve [ reflexivity
| exfalso; apply p; congruence ].
Qed.
Hint Rewrite @nth_set_nth : push_nth_error.
Lemma length_set_nth : forall {T} i x (xs:list T), length (set_nth i x xs) = length xs.
Proof. intros; apply length_update_nth. Qed.
Hint Rewrite @length_set_nth : distr_length.
Lemma nth_error_length_exists_value : forall {A} (i : nat) (xs : list A),
(i < length xs)%nat -> exists x, nth_error xs i = Some x.
Proof.
induction i, xs; boring; try omega.
Qed.
Lemma nth_error_length_not_error : forall {A} (i : nat) (xs : list A),
nth_error xs i = None -> (i < length xs)%nat -> False.
Proof.
intros.
destruct (nth_error_length_exists_value i xs); intuition; congruence.
Qed.
Lemma nth_error_value_eq_nth_default : forall {T} i (x : T) xs,
nth_error xs i = Some x -> forall d, nth_default d xs i = x.
Proof.
unfold nth_default; boring.
Qed.
Hint Rewrite @nth_error_value_eq_nth_default using eassumption : simpl_nth_default.
Lemma skipn0 : forall {T} (xs:list T), skipn 0 xs = xs.
Proof. auto. Qed.
Lemma destruct_repeat : forall {A} xs y, (forall x : A, In x xs -> x = y) ->
xs = nil \/ exists xs', xs = y :: xs' /\ (forall x : A, In x xs' -> x = y).
Proof.
destruct xs; intros; try tauto.
right.
exists xs; split.
+ f_equal; auto using in_eq.
+ intros; auto using in_cons.
Qed.
Lemma splice_nth_equiv_update_nth : forall {T} n f d (xs:list T),
splice_nth n (f (nth_default d xs n)) xs =
if lt_dec n (length xs)
then update_nth n f xs
else xs ++ (f d)::nil.
Proof.
induction n, xs; boring_list.
do 2 break_if; auto; omega.
Qed.
Lemma splice_nth_equiv_update_nth_update : forall {T} n f d (xs:list T),
n < length xs ->
splice_nth n (f (nth_default d xs n)) xs = update_nth n f xs.
Proof.
intros.
rewrite splice_nth_equiv_update_nth.
break_if; auto; omega.
Qed.
Lemma splice_nth_equiv_update_nth_snoc : forall {T} n f d (xs:list T),
n >= length xs ->
splice_nth n (f (nth_default d xs n)) xs = xs ++ (f d)::nil.
Proof.
intros.
rewrite splice_nth_equiv_update_nth.
break_if; auto; omega.
Qed.
Definition IMPOSSIBLE {T} : list T. exact nil. Qed.
Ltac remove_nth_error :=
repeat match goal with
| _ => exfalso; solve [ eauto using @nth_error_length_not_error ]
| [ |- context[match nth_error ?ls ?n with _ => _ end] ]
=> destruct (nth_error ls n) eqn:?
end.
Lemma update_nth_equiv_splice_nth: forall {T} n f (xs:list T),
update_nth n f xs =
if lt_dec n (length xs)
then match nth_error xs n with
| Some v => splice_nth n (f v) xs
| None => IMPOSSIBLE
end
else xs.
Proof.
induction n; destruct xs; intros;
autorewrite with simpl_update_nth simpl_nth_default in *; simpl in *;
try (erewrite IHn; clear IHn); auto.
repeat break_match; remove_nth_error; try reflexivity; try omega.
Qed.
Lemma splice_nth_equiv_set_nth : forall {T} n x (xs:list T),
splice_nth n x xs =
if lt_dec n (length xs)
then set_nth n x xs
else xs ++ x::nil.
Proof. intros; rewrite splice_nth_equiv_update_nth with (f := fun _ => x); auto. Qed.
Lemma splice_nth_equiv_set_nth_set : forall {T} n x (xs:list T),
n < length xs ->
splice_nth n x xs = set_nth n x xs.
Proof. intros; rewrite splice_nth_equiv_update_nth_update with (f := fun _ => x); auto. Qed.
Lemma splice_nth_equiv_set_nth_snoc : forall {T} n x (xs:list T),
n >= length xs ->
splice_nth n x xs = xs ++ x::nil.
Proof. intros; rewrite splice_nth_equiv_update_nth_snoc with (f := fun _ => x); auto. Qed.
Lemma set_nth_equiv_splice_nth: forall {T} n x (xs:list T),
set_nth n x xs =
if lt_dec n (length xs)
then splice_nth n x xs
else xs.
Proof.
intros; unfold set_nth; rewrite update_nth_equiv_splice_nth with (f := fun _ => x); auto.
repeat break_match; remove_nth_error; trivial.
Qed.
Lemma combine_update_nth : forall {A B} n f g (xs:list A) (ys:list B),
combine (update_nth n f xs) (update_nth n g ys) =
update_nth n (fun xy => (f (fst xy), g (snd xy))) (combine xs ys).
Proof.
induction n; destruct xs, ys; simpl; try rewrite IHn; reflexivity.
Qed.
(* grumble, grumble, [rewrite] is bad at inferring the identity function, and constant functions *)
Ltac rewrite_rev_combine_update_nth :=
let lem := match goal with
| [ |- appcontext[update_nth ?n (fun xy => (@?f xy, @?g xy)) (combine ?xs ?ys)] ]
=> let f := match (eval cbv [fst] in (fun y x => f (x, y))) with
| fun _ => ?f => f
end in
let g := match (eval cbv [snd] in (fun x y => g (x, y))) with
| fun _ => ?g => g
end in
constr:(@combine_update_nth _ _ n f g xs ys)
end in
rewrite <- lem.
Lemma combine_update_nth_l : forall {A B} n (f : A -> A) xs (ys:list B),
combine (update_nth n f xs) ys =
update_nth n (fun xy => (f (fst xy), snd xy)) (combine xs ys).
Proof.
intros ??? f xs ys.
etransitivity; [ | apply combine_update_nth with (g := fun x => x) ].
rewrite update_nth_id; reflexivity.
Qed.
Lemma combine_update_nth_r : forall {A B} n (g : B -> B) (xs:list A) (ys:list B),
combine xs (update_nth n g ys) =
update_nth n (fun xy => (fst xy, g (snd xy))) (combine xs ys).
Proof.
intros ??? g xs ys.
etransitivity; [ | apply combine_update_nth with (f := fun x => x) ].
rewrite update_nth_id; reflexivity.
Qed.
Lemma combine_set_nth : forall {A B} n (x:A) xs (ys:list B),
combine (set_nth n x xs) ys =
match nth_error ys n with
| None => combine xs ys
| Some y => set_nth n (x,y) (combine xs ys)
end.
Proof.
intros; unfold set_nth; rewrite combine_update_nth_l.
nth_tac;
[ repeat rewrite_rev_combine_update_nth; apply f_equal2
| assert (nth_error (combine xs ys) n = None)
by (apply nth_error_None; rewrite combine_length; omega * ) ];
autorewrite with simpl_update_nth; reflexivity.
Qed.
Lemma nth_error_value_In : forall {T} n xs (x:T),
nth_error xs n = Some x -> In x xs.
Proof.
induction n; destruct xs; nth_tac.
Qed.
Lemma In_nth_error_value : forall {T} xs (x:T),
In x xs -> exists n, nth_error xs n = Some x.
Proof.
induction xs; nth_tac; break_or_hyp.
- exists 0; reflexivity.
- edestruct IHxs; eauto. exists (S x0). eauto.
Qed.
Lemma nth_value_index : forall {T} i xs (x:T),
nth_error xs i = Some x -> In i (seq 0 (length xs)).
Proof.
induction i; destruct xs; nth_tac; right.
rewrite <- seq_shift; apply in_map; eapply IHi; eauto.
Qed.
Lemma nth_error_app : forall {T} n (xs ys:list T), nth_error (xs ++ ys) n =
if lt_dec n (length xs)
then nth_error xs n
else nth_error ys (n - length xs).
Proof.
induction n; destruct xs; nth_tac;
rewrite IHn; destruct (lt_dec n (length xs)); trivial; omega.
Qed.
Lemma nth_default_app : forall {T} n x (xs ys:list T), nth_default x (xs ++ ys) n =
if lt_dec n (length xs)
then nth_default x xs n
else nth_default x ys (n - length xs).
Proof.
intros.
unfold nth_default.
rewrite nth_error_app.
destruct (lt_dec n (length xs)); auto.
Qed.
Hint Rewrite @nth_default_app : push_nth_default.
Lemma combine_truncate_r : forall {A B} (xs : list A) (ys : list B),
combine xs ys = combine xs (firstn (length xs) ys).
Proof.
induction xs; destruct ys; boring.
Qed.
Lemma combine_truncate_l : forall {A B} (xs : list A) (ys : list B),
combine xs ys = combine (firstn (length ys) xs) ys.
Proof.
induction xs; destruct ys; boring.
Qed.
Lemma combine_app_samelength : forall {A B} (xs xs':list A) (ys ys':list B),
length xs = length ys ->
combine (xs ++ xs') (ys ++ ys') = combine xs ys ++ combine xs' ys'.
Proof.
induction xs, xs', ys, ys'; boring; omega.
Qed.
Lemma skipn_nil : forall {A} n, skipn n nil = @nil A.
Proof. destruct n; auto. Qed.
Hint Rewrite @skipn_nil : simpl_skipn.
Hint Rewrite @skipn_nil : push_skipn.
Lemma skipn_0 : forall {A} xs, @skipn A 0 xs = xs.
Proof. reflexivity. Qed.
Hint Rewrite @skipn_0 : simpl_skipn.
Hint Rewrite @skipn_0 : push_skipn.
Lemma skipn_cons_S : forall {A} n x xs, @skipn A (S n) (x::xs) = @skipn A n xs.
Proof. reflexivity. Qed.
Hint Rewrite @skipn_cons_S : simpl_skipn.
Hint Rewrite @skipn_cons_S : push_skipn.
Lemma skipn_app : forall {A} n (xs ys : list A),
skipn n (xs ++ ys) = skipn n xs ++ skipn (n - length xs) ys.
Proof.
induction n, xs, ys; boring.
Qed.
Hint Rewrite @skipn_app : push_skipn.
Lemma firstn_app_inleft : forall {A} n (xs ys : list A), (n <= length xs)%nat ->
firstn n (xs ++ ys) = firstn n xs.
Proof.
induction n, xs, ys; boring; try omega.
Qed.
Hint Rewrite @firstn_app_inleft using solve [ distr_length ] : simpl_firstn.
Hint Rewrite @firstn_app_inleft using solve [ distr_length ] : push_firstn.
Lemma skipn_app_inleft : forall {A} n (xs ys : list A), (n <= length xs)%nat ->
skipn n (xs ++ ys) = skipn n xs ++ ys.
Proof.
induction n, xs, ys; boring; try omega.
Qed.
Hint Rewrite @skipn_app_inleft using solve [ distr_length ] : push_skipn.
Lemma firstn_map : forall {A B} (f : A -> B) n (xs : list A), firstn n (map f xs) = map f (firstn n xs).
Proof. induction n, xs; boring. Qed.
Hint Rewrite @firstn_map : push_firstn.
Hint Rewrite <- @firstn_map : pull_firstn.
Lemma skipn_map : forall {A B} (f : A -> B) n (xs : list A), skipn n (map f xs) = map f (skipn n xs).
Proof. induction n, xs; boring. Qed.
Hint Rewrite @skipn_map : push_skipn.
Hint Rewrite <- @skipn_map : pull_skipn.
Lemma firstn_all : forall {A} n (xs:list A), n = length xs -> firstn n xs = xs.
Proof.
induction n, xs; boring; omega.
Qed.
Hint Rewrite @firstn_all using solve [ distr_length ] : simpl_firstn.
Hint Rewrite @firstn_all using solve [ distr_length ] : push_firstn.
Lemma skipn_all : forall {T} n (xs:list T),
(n >= length xs)%nat ->
skipn n xs = nil.
Proof.
induction n, xs; boring; omega.
Qed.
Hint Rewrite @skipn_all using solve [ distr_length ] : simpl_skipn.
Hint Rewrite @skipn_all using solve [ distr_length ] : push_skipn.
Lemma firstn_app_sharp : forall {A} n (l l': list A),
length l = n ->
firstn n (l ++ l') = l.
Proof.
intros.
rewrite firstn_app_inleft; auto using firstn_all; omega.
Qed.
Hint Rewrite @firstn_app_sharp using solve [ distr_length ] : simpl_firstn.
Hint Rewrite @firstn_app_sharp using solve [ distr_length ] : push_firstn.
Lemma skipn_app_sharp : forall {A} n (l l': list A),
length l = n ->
skipn n (l ++ l') = l'.
Proof.
intros.
rewrite skipn_app_inleft; try rewrite skipn_all; auto; omega.
Qed.
Hint Rewrite @skipn_app_sharp using solve [ distr_length ] : simpl_skipn.
Hint Rewrite @skipn_app_sharp using solve [ distr_length ] : push_skipn.
Lemma skipn_length : forall {A} n (xs : list A),
length (skipn n xs) = (length xs - n)%nat.
Proof.
induction n, xs; boring.
Qed.
Hint Rewrite @skipn_length : distr_length.
Lemma fold_right_cons : forall {A B} (f:B->A->A) a b bs,
fold_right f a (b::bs) = f b (fold_right f a bs).
Proof.
reflexivity.
Qed.
Hint Rewrite @fold_right_cons : simpl_fold_right.
Lemma length_cons : forall {T} (x:T) xs, length (x::xs) = S (length xs).
reflexivity.
Qed.
Hint Rewrite @length_cons : distr_length.
Lemma cons_length : forall A (xs : list A) a, length (a :: xs) = S (length xs).
Proof.
auto.
Qed.
Lemma length0_nil : forall {A} (xs : list A), length xs = 0%nat -> xs = nil.
Proof.
induction xs; boring; discriminate.
Qed.
Lemma length_snoc : forall {T} xs (x:T),
length xs = pred (length (xs++x::nil)).
Proof.
boring; simpl_list; boring.
Qed.
Lemma firstn_combine : forall {A B} n (xs:list A) (ys:list B),
firstn n (combine xs ys) = combine (firstn n xs) (firstn n ys).
Proof.
induction n, xs, ys; boring.
Qed.
Hint Rewrite @firstn_combine : push_firstn.
Hint Rewrite <- @firstn_combine : pull_firstn.
Lemma combine_nil_r : forall {A B} (xs:list A),
combine xs (@nil B) = nil.
Proof.
induction xs; boring.
Qed.
Lemma skipn_combine : forall {A B} n (xs:list A) (ys:list B),
skipn n (combine xs ys) = combine (skipn n xs) (skipn n ys).
Proof.
induction n, xs, ys; boring.
rewrite combine_nil_r; reflexivity.
Qed.
Hint Rewrite @skipn_combine : push_skipn.
Hint Rewrite <- @skipn_combine : pull_skipn.
Lemma break_list_last: forall {T} (xs:list T),
xs = nil \/ exists xs' y, xs = xs' ++ y :: nil.
Proof.
destruct xs using rev_ind; auto.
right; do 2 eexists; auto.
Qed.
Lemma break_list_first: forall {T} (xs:list T),
xs = nil \/ exists x xs', xs = x :: xs'.
Proof.
destruct xs; auto.
right; do 2 eexists; auto.
Qed.
Lemma list012 : forall {T} (xs:list T),
xs = nil
\/ (exists x, xs = x::nil)
\/ (exists x xs' y, xs = x::xs'++y::nil).
Proof.
destruct xs; auto.
right.
destruct xs using rev_ind. {
left; eexists; auto.
} {
right; repeat eexists; auto.
}
Qed.
Lemma nil_length0 : forall {T}, length (@nil T) = 0%nat.
Proof.
auto.
Qed.
Hint Rewrite @nil_length0 : distr_length.
Lemma nth_error_Some_nth_default : forall {T} i x (l : list T), (i < length l)%nat ->
nth_error l i = Some (nth_default x l i).
Proof.
intros ? ? ? ? i_lt_length.
destruct (nth_error_length_exists_value _ _ i_lt_length) as [k nth_err_k].
unfold nth_default.
rewrite nth_err_k.
reflexivity.
Qed.
Lemma update_nth_cons : forall {T} f (u0 : T) us, update_nth 0 f (u0 :: us) = (f u0) :: us.
Proof. reflexivity. Qed.
Hint Rewrite @update_nth_cons : simpl_update_nth.
Lemma set_nth_cons : forall {T} (x u0 : T) us, set_nth 0 x (u0 :: us) = x :: us.
Proof. intros; apply update_nth_cons. Qed.
Hint Rewrite @set_nth_cons : simpl_set_nth.
Lemma cons_update_nth : forall {T} n f (y : T) us,
y :: update_nth n f us = update_nth (S n) f (y :: us).
Proof.
induction n; boring.
Qed.
Hint Rewrite <- @cons_update_nth : simpl_update_nth.
Lemma update_nth_nil : forall {T} n f, update_nth n f (@nil T) = @nil T.
Proof.
induction n; boring.
Qed.
Hint Rewrite @update_nth_nil : simpl_update_nth.
Lemma cons_set_nth : forall {T} n (x y : T) us,
y :: set_nth n x us = set_nth (S n) x (y :: us).
Proof. intros; apply cons_update_nth. Qed.
Hint Rewrite <- @cons_set_nth : simpl_set_nth.
Lemma set_nth_nil : forall {T} n (x : T), set_nth n x nil = nil.
Proof. intros; apply update_nth_nil. Qed.
Hint Rewrite @set_nth_nil : simpl_set_nth.
Lemma skipn_nth_default : forall {T} n us (d : T), (n < length us)%nat ->
skipn n us = nth_default d us n :: skipn (S n) us.
Proof.
induction n; destruct us; intros; nth_tac.
rewrite (IHn us d) at 1 by omega.
nth_tac.
Qed.
Lemma nth_default_out_of_bounds : forall {T} n us (d : T), (n >= length us)%nat ->
nth_default d us n = d.
Proof.
induction n; unfold nth_default; nth_tac; destruct us; nth_tac.
assert (n >= length us)%nat by omega.
pose proof (nth_error_length_error _ n us H1).
rewrite H0 in H2.
congruence.
Qed.
Hint Rewrite @nth_default_out_of_bounds using omega : simpl_nth_default.
Ltac nth_error_inbounds :=
match goal with
| [ |- context[match nth_error ?xs ?i with Some _ => _ | None => _ end ] ] =>
case_eq (nth_error xs i);
match goal with
| [ |- forall _, nth_error xs i = Some _ -> _ ] =>
let x := fresh "x" in
let H := fresh "H" in
intros x H;
repeat progress erewrite H;
repeat progress erewrite (nth_error_value_eq_nth_default i xs x); auto
| [ |- nth_error xs i = None -> _ ] =>
let H := fresh "H" in
intros H;
destruct (nth_error_length_not_error _ _ H);
try solve [distr_length]
end;
idtac
end.
Ltac set_nth_inbounds :=
match goal with
| [ |- context[set_nth ?i ?x ?xs] ] =>
rewrite (set_nth_equiv_splice_nth i x xs);
destruct (lt_dec i (length xs));
match goal with
| [ H : ~ (i < (length xs))%nat |- _ ] => destruct H
| [ H : (i < (length xs))%nat |- _ ] => try solve [distr_length]
end
end.
Ltac update_nth_inbounds :=
match goal with
| [ |- context[update_nth ?i ?f ?xs] ] =>
rewrite (update_nth_equiv_splice_nth i f xs);
destruct (lt_dec i (length xs));
match goal with
| [ H : ~ (i < (length xs))%nat |- _ ] => destruct H
| [ H : (i < (length xs))%nat |- _ ] => remove_nth_error; try solve [distr_length]
end
end.
Ltac nth_inbounds := nth_error_inbounds || set_nth_inbounds || update_nth_inbounds.
Definition nth_dep {A} (ls : list A) (n : nat) (pf : n < length ls) : A.
Proof.
refine (match nth_error ls n as v return nth_error ls n = v -> A with
| Some v => fun _ => v
| None => fun bad => match _ : False with end
end eq_refl).
apply (proj1 (@nth_error_None _ _ _)) in bad; instantiate; generalize dependent (length ls); clear.
abstract (intros; omega).
Defined.
Lemma nth_error_nth_dep {A} ls n pf : nth_error ls n = Some (@nth_dep A ls n pf).
Proof.
unfold nth_dep.
generalize dependent (@nth_error_None A ls n).
edestruct nth_error; boring.
Qed.
Lemma nth_default_nth_dep {A} d ls n pf : nth_default d ls n = @nth_dep A ls n pf.
Proof.
unfold nth_dep.
generalize dependent (@nth_error_None A ls n).
destruct (nth_error ls n) eqn:?; boring.
erewrite nth_error_value_eq_nth_default by eassumption; reflexivity.
Qed.
Lemma nth_default_in_bounds : forall {T} (d' d : T) n us, (n < length us)%nat ->
nth_default d us n = nth_default d' us n.
Proof.
intros; erewrite !nth_default_nth_dep; reflexivity.
Grab Existential Variables.
assumption.
Qed.
Hint Resolve @nth_default_in_bounds : simpl_nth_default.
Lemma cons_eq_head : forall {T} (x y:T) xs ys, x::xs = y::ys -> x=y.
Proof.
intros; solve_by_inversion.
Qed.
Lemma cons_eq_tail : forall {T} (x y:T) xs ys, x::xs = y::ys -> xs=ys.
Proof.
intros; solve_by_inversion.
Qed.
Lemma map_nth_default_always {A B} (f : A -> B) (n : nat) (x : A) (l : list A)
: nth_default (f x) (map f l) n = f (nth_default x l n).
Proof.
revert n; induction l; simpl; intro n; destruct n; [ try reflexivity.. ].
nth_tac.
Qed.
Hint Rewrite @map_nth_default_always : push_nth_default.
Lemma fold_right_and_True_forall_In_iff : forall {T} (l : list T) (P : T -> Prop),
(forall x, In x l -> P x) <-> fold_right and True (map P l).
Proof.
induction l; intros; simpl; try tauto.
rewrite <- IHl.
intuition (subst; auto).
Qed.
Lemma fold_right_invariant : forall {A} P (f: A -> A -> A) l x,
P x -> (forall y, In y l -> forall z, P z -> P (f y z)) ->
P (fold_right f x l).
Proof.
induction l; intros ? ? step; auto.
simpl.
apply step; try apply in_eq.
apply IHl; auto.
intros y in_y_l.
apply (in_cons a) in in_y_l.
auto.
Qed.
Lemma In_firstn : forall {T} n l (x : T), In x (firstn n l) -> In x l.
Proof.
induction n; destruct l; boring.
Qed.
Lemma In_skipn : forall {T} n l (x : T), In x (skipn n l) -> In x l.
Proof.
induction n; destruct l; boring.
Qed.
Lemma firstn_firstn : forall {A} m n (l : list A), (n <= m)%nat ->
firstn n (firstn m l) = firstn n l.
Proof.
induction m; destruct n; intros; try omega; auto.
destruct l; auto.
simpl.
f_equal.
apply IHm; omega.
Qed.
Hint Rewrite @firstn_firstn using omega : push_firstn.
Lemma firstn_succ : forall {A} (d : A) n l, (n < length l)%nat ->
firstn (S n) l = (firstn n l) ++ nth_default d l n :: nil.
Proof.
induction n; destruct l; rewrite ?(@nil_length0 A); intros; try omega.
+ rewrite nth_default_cons; auto.
+ simpl.
rewrite nth_default_cons_S.
rewrite <-IHn by (rewrite cons_length in *; omega).
reflexivity.
Qed.
Lemma update_nth_out_of_bounds : forall {A} n f xs, n >= length xs -> @update_nth A n f xs = xs.
Proof.
induction n; destruct xs; simpl; try congruence; try omega; intros.
rewrite IHn by omega; reflexivity.
Qed.
Hint Rewrite @update_nth_out_of_bounds using omega : simpl_update_nth.
Lemma update_nth_nth_default_full : forall {A} (d:A) n f l i,
nth_default d (update_nth n f l) i =
if lt_dec i (length l) then
if (eq_nat_dec i n) then f (nth_default d l i)
else nth_default d l i
else d.
Proof.
induction n; (destruct l; simpl in *; [ intros; destruct i; simpl; try reflexivity; omega | ]);
intros; repeat break_if; subst; try destruct i;
repeat first [ progress break_if
| progress subst
| progress boring
| progress autorewrite with simpl_nth_default
| omega ].
Qed.
Hint Rewrite @update_nth_nth_default_full : push_nth_default.
Lemma update_nth_nth_default : forall {A} (d:A) n f l i, (0 <= i < length l)%nat ->
nth_default d (update_nth n f l) i =
if (eq_nat_dec i n) then f (nth_default d l i) else nth_default d l i.
Proof. intros; rewrite update_nth_nth_default_full; repeat break_if; boring. Qed.
Hint Rewrite @update_nth_nth_default using (omega || distr_length; omega) : push_nth_default.
Lemma set_nth_nth_default_full : forall {A} (d:A) n v l i,
nth_default d (set_nth n v l) i =
if lt_dec i (length l) then
if (eq_nat_dec i n) then v
else nth_default d l i
else d.
Proof. intros; apply update_nth_nth_default_full; assumption. Qed.
Hint Rewrite @set_nth_nth_default_full : push_nth_default.
Lemma set_nth_nth_default : forall {A} (d:A) n x l i, (0 <= i < length l)%nat ->
nth_default d (set_nth n x l) i =
if (eq_nat_dec i n) then x else nth_default d l i.
Proof. intros; apply update_nth_nth_default; assumption. Qed.
Hint Rewrite @set_nth_nth_default using (omega || distr_length; omega) : push_nth_default.
Lemma nth_default_preserves_properties : forall {A} (P : A -> Prop) l n d,
(forall x, In x l -> P x) -> P d -> P (nth_default d l n).
Proof.
intros; rewrite nth_default_eq.
destruct (nth_in_or_default n l d); auto.
congruence.
Qed.
Lemma nth_default_preserves_properties_length_dep :
forall {A} (P : A -> Prop) l n d,
(forall x, In x l -> n < (length l) -> P x) -> ((~ n < length l) -> P d) -> P (nth_default d l n).
Proof.
intros.
destruct (lt_dec n (length l)).
+ rewrite nth_default_eq; auto using nth_In.
+ rewrite nth_default_out_of_bounds by omega.
auto.
Qed.
Lemma nth_error_first : forall {T} (a b : T) l,
nth_error (a :: l) 0 = Some b -> a = b.
Proof.
intros; simpl in *.
unfold value in *.
congruence.
Qed.
Lemma nth_error_exists_first : forall {T} l (x : T) (H : nth_error l 0 = Some x),
exists l', l = x :: l'.
Proof.
induction l; try discriminate; eexists.
apply nth_error_first in H.
subst; eauto.
Qed.
Lemma list_elementwise_eq : forall {T} (l1 l2 : list T),
(forall i, nth_error l1 i = nth_error l2 i) -> l1 = l2.
Proof.
induction l1, l2; intros; try reflexivity;
pose proof (H 0%nat) as Hfirst; simpl in Hfirst; inversion Hfirst.
f_equal.
apply IHl1.
intros i; specialize (H (S i)).
boring.
Qed.
Lemma sum_firstn_all_succ : forall n l, (length l <= n)%nat ->
sum_firstn l (S n) = sum_firstn l n.
Proof.
unfold sum_firstn; intros.
autorewrite with push_firstn; reflexivity.
Qed.
Hint Rewrite @sum_firstn_all_succ using omega : simpl_sum_firstn.
Lemma sum_firstn_all : forall n l, (length l <= n)%nat ->
sum_firstn l n = sum_firstn l (length l).
Proof.
unfold sum_firstn; intros.
autorewrite with push_firstn; reflexivity.
Qed.
Hint Rewrite @sum_firstn_all using omega : simpl_sum_firstn.
Lemma sum_firstn_succ_default : forall l i,
sum_firstn l (S i) = (nth_default 0 l i + sum_firstn l i)%Z.
Proof.
unfold sum_firstn; induction l, i;
intros; autorewrite with simpl_nth_default simpl_firstn simpl_fold_right in *;
try reflexivity.
rewrite IHl; omega.
Qed.
Hint Rewrite @sum_firstn_succ_default : simpl_sum_firstn.
Lemma sum_firstn_0 : forall xs,
sum_firstn xs 0 = 0%Z.
Proof.
destruct xs; reflexivity.
Qed.
Hint Rewrite @sum_firstn_0 : simpl_sum_firstn.
Lemma sum_firstn_succ : forall l i x,
nth_error l i = Some x ->
sum_firstn l (S i) = (x + sum_firstn l i)%Z.
Proof.
intros; rewrite sum_firstn_succ_default.
erewrite nth_error_value_eq_nth_default by eassumption; reflexivity.
Qed.
Hint Rewrite @sum_firstn_succ using congruence : simpl_sum_firstn.
Lemma sum_firstn_succ_cons : forall x xs i,
sum_firstn (x :: xs) (S i) = (x + sum_firstn xs i)%Z.
Proof.
unfold sum_firstn; simpl; reflexivity.
Qed.
Hint Rewrite @sum_firstn_succ_cons : simpl_sum_firstn.
Lemma sum_firstn_nil : forall i,
sum_firstn nil i = 0%Z.
Proof. destruct i; reflexivity. Qed.
Hint Rewrite @sum_firstn_nil : simpl_sum_firstn.
Lemma sum_firstn_succ_default_rev : forall l i,
sum_firstn l i = (sum_firstn l (S i) - nth_default 0 l i)%Z.
Proof.
intros; rewrite sum_firstn_succ_default; omega.
Qed.
Lemma sum_firstn_succ_rev : forall l i x,
nth_error l i = Some x ->
sum_firstn l i = (sum_firstn l (S i) - x)%Z.
Proof.
intros; erewrite sum_firstn_succ by eassumption; omega.
Qed.
Lemma sum_firstn_nonnegative : forall n l, (forall x, In x l -> 0 <= x)%Z
-> (0 <= sum_firstn l n)%Z.
Proof.
induction n as [|n IHn]; destruct l as [|? l]; autorewrite with simpl_sum_firstn; simpl; try omega.
{ specialize (IHn l).
destruct n; simpl; autorewrite with simpl_sum_firstn simpl_nth_default in *;
intuition auto with zarith. }
Qed.
Hint Resolve sum_firstn_nonnegative : znonzero.
Lemma sum_firstn_app : forall xs ys n,
sum_firstn (xs ++ ys) n = (sum_firstn xs n + sum_firstn ys (n - length xs))%Z.
Proof.
induction xs; simpl.
{ intros ys n; autorewrite with simpl_sum_firstn; simpl.
f_equal; omega. }
{ intros ys [|n]; autorewrite with simpl_sum_firstn; simpl; [ reflexivity | ].
rewrite IHxs; omega. }
Qed.
Lemma sum_firstn_app_sum : forall xs ys n,
sum_firstn (xs ++ ys) (length xs + n) = (sum_firstn xs (length xs) + sum_firstn ys n)%Z.
Proof.
intros; rewrite sum_firstn_app; autorewrite with simpl_sum_firstn.
do 2 f_equal; omega.
Qed.
Hint Rewrite @sum_firstn_app_sum : simpl_sum_firstn.
Lemma nth_error_skipn : forall {A} n (l : list A) m,
nth_error (skipn n l) m = nth_error l (n + m).
Proof.
induction n; destruct l; boring.
apply nth_error_nil_error.
Qed.
Hint Rewrite @nth_error_skipn : push_nth_error.
Lemma nth_default_skipn : forall {A} (l : list A) d n m, nth_default d (skipn n l) m = nth_default d l (n + m).
Proof.
cbv [nth_default]; intros.
rewrite nth_error_skipn.
reflexivity.
Qed.
Hint Rewrite @nth_default_skipn : push_nth_default.
Lemma sum_firstn_skipn : forall l n m, sum_firstn l (n + m) = (sum_firstn l n + sum_firstn (skipn n l) m)%Z.
Proof.
induction m; intros.
+ rewrite sum_firstn_0. autorewrite with natsimplify. omega.
+ rewrite <-plus_n_Sm, !sum_firstn_succ_default.
rewrite nth_default_skipn.
omega.
Qed.
Lemma sum_firstn_prefix_le' : forall l n m, (forall x, In x l -> (0 <= x)%Z) ->
(sum_firstn l n <= sum_firstn l (n + m))%Z.
Proof.
intros.
rewrite sum_firstn_skipn.
pose proof (sum_firstn_nonnegative m (skipn n l)) as Hskipn_nonneg.
match type of Hskipn_nonneg with
?P -> _ => assert P as Q; [ | specialize (Hskipn_nonneg Q); omega ] end.
intros x HIn_skipn.
apply In_skipn in HIn_skipn.
auto.
Qed.
Lemma sum_firstn_prefix_le : forall l n m, (forall x, In x l -> (0 <= x)%Z) ->
(n <= m)%nat ->
(sum_firstn l n <= sum_firstn l m)%Z.
Proof.
intros.
replace m with (n + (m - n))%nat by omega.
auto using sum_firstn_prefix_le'.
Qed.
Lemma sum_firstn_pos_lt_succ : forall l n m, (forall x, In x l -> (0 <= x)%Z) ->
(n < length l)%nat ->
(sum_firstn l n < sum_firstn l (S m))%Z ->
(n <= m)%nat.
Proof.
intros.
destruct (le_dec n m); auto.
replace n with (m + (n - m))%nat in H1 by omega.
rewrite sum_firstn_skipn in H1.
rewrite sum_firstn_succ_default in *.
match goal with H : (?a + ?b < ?c + ?a)%Z |- _ => assert (b < c)%Z by omega end.
destruct (lt_dec m (length l)). {
rewrite skipn_nth_default with (d := 0%Z) in H2 by assumption.
replace (n - m)%nat with (S (n - S m))%nat in H2 by omega.
rewrite sum_firstn_succ_cons in H2.
pose proof (sum_firstn_nonnegative (n - S m) (skipn (S m) l)).
match type of H3 with
?P -> _ => assert P as Q; [ | specialize (H3 Q); omega ] end.
intros ? A.
apply In_skipn in A.
apply H in A.
omega.
} {
rewrite skipn_all, nth_default_out_of_bounds in H2 by omega.
rewrite sum_firstn_nil in H2; omega.
}
Qed.
Definition NotSum {T} (xs : list T) (v : nat) := True.
Ltac NotSum :=
lazymatch goal with
| [ |- NotSum ?xs (length ?xs + _)%nat ] => fail
| [ |- NotSum _ _ ] => exact I
end.
Lemma sum_firstn_app_hint : forall xs ys n, NotSum xs n ->
sum_firstn (xs ++ ys) n = (sum_firstn xs n + sum_firstn ys (n - length xs))%Z.
Proof. auto using sum_firstn_app. Qed.
Hint Rewrite sum_firstn_app_hint using solve [ NotSum ] : simpl_sum_firstn.
Lemma nth_default_map2 : forall {A B C} (f : A -> B -> C) ls1 ls2 i d d1 d2,
nth_default d (map2 f ls1 ls2) i =
if lt_dec i (min (length ls1) (length ls2))
then f (nth_default d1 ls1 i) (nth_default d2 ls2 i)
else d.
Proof.
induction ls1, ls2.
+ cbv [map2 length min].
intros.
break_if; try omega.
apply nth_default_nil.
+ cbv [map2 length min].
intros.
break_if; try omega.
apply nth_default_nil.
+ cbv [map2 length min].
intros.
break_if; try omega.
apply nth_default_nil.
+ simpl.
destruct i.
- intros. rewrite !nth_default_cons.
break_if; auto; omega.
- intros. rewrite !nth_default_cons_S.
rewrite IHls1 with (d1 := d1) (d2 := d2).
repeat break_if; auto; omega.
Qed.
Lemma map2_cons : forall A B C (f : A -> B -> C) ls1 ls2 a b,
map2 f (a :: ls1) (b :: ls2) = f a b :: map2 f ls1 ls2.
Proof.
reflexivity.
Qed.
Lemma map2_nil_l : forall A B C (f : A -> B -> C) ls2,
map2 f nil ls2 = nil.
Proof.
reflexivity.
Qed.
Lemma map2_nil_r : forall A B C (f : A -> B -> C) ls1,
map2 f ls1 nil = nil.
Proof.
destruct ls1; reflexivity.
Qed.
Local Hint Resolve map2_nil_r map2_nil_l.
Opaque map2.
Lemma map2_length : forall A B C (f : A -> B -> C) ls1 ls2,
length (map2 f ls1 ls2) = min (length ls1) (length ls2).
Proof.
induction ls1, ls2; intros; try solve [cbv; auto].
rewrite map2_cons, !length_cons, IHls1.
auto.
Qed.
Ltac simpl_list_lengths := repeat match goal with
| H : appcontext[length (@nil ?A)] |- _ => rewrite (@nil_length0 A) in H
| H : appcontext[length (_ :: _)] |- _ => rewrite length_cons in H
| |- appcontext[length (@nil ?A)] => rewrite (@nil_length0 A)
| |- appcontext[length (_ :: _)] => rewrite length_cons
end.
Lemma map2_app : forall A B C (f : A -> B -> C) ls1 ls2 ls1' ls2',
(length ls1 = length ls2) ->
map2 f (ls1 ++ ls1') (ls2 ++ ls2') = map2 f ls1 ls2 ++ map2 f ls1' ls2'.
Proof.
induction ls1, ls2; intros; rewrite ?map2_nil_r, ?app_nil_l; try congruence;
simpl_list_lengths; try omega.
rewrite <-!app_comm_cons, !map2_cons.
rewrite IHls1; auto.
Qed.
Lemma firstn_update_nth {A}
: forall f m n (xs : list A), firstn m (update_nth n f xs) = update_nth n f (firstn m xs).
Proof.
induction m; destruct n, xs;
autorewrite with simpl_firstn simpl_update_nth;
congruence.
Qed.
Hint Rewrite @firstn_update_nth : push_firstn.
Hint Rewrite @firstn_update_nth : pull_update_nth.
Hint Rewrite <- @firstn_update_nth : pull_firstn.
Hint Rewrite <- @firstn_update_nth : push_update_nth.
Require Import Coq.Lists.SetoidList.
Global Instance Proper_nth_default : forall A eq,
Proper (eq==>eqlistA eq==>Logic.eq==>eq) (nth_default (A:=A)).
Proof.
do 5 intro; subst; induction 1.
+ repeat intro; rewrite !nth_default_nil; assumption.
+ repeat intro; subst; destruct y0; rewrite ?nth_default_cons, ?nth_default_cons_S; auto.
Qed.
Lemma fold_right_andb_true_map_iff A (ls : list A) f
: List.fold_right andb true (List.map f ls) = true <-> forall i, List.In i ls -> f i = true.
Proof.
induction ls; simpl; [ | rewrite Bool.andb_true_iff, IHls ]; try tauto.
intuition (congruence || eauto).
Qed.
Lemma Forall2_forall_iff : forall {A} R (xs ys : list A) d, length xs = length ys ->
(Forall2 R xs ys <-> (forall i, (i < length xs)%nat -> R (nth_default d xs i) (nth_default d ys i))).
Proof.
split; intros.
+ revert xs ys H H0 H1.
induction i; intros; destruct H0; distr_length; autorewrite with push_nth_default; auto.
eapply IHi; auto. omega.
+ revert xs ys H H0; induction xs; intros; destruct ys; distr_length; econstructor.
- specialize (H0 0%nat).
autorewrite with push_nth_default in *; auto.
apply H0; omega.
- apply IHxs; try omega.
intros.
specialize (H0 (S i)).
autorewrite with push_nth_default in *; auto.
apply H0; omega.
Qed.
Lemma nth_default_firstn : forall {A} (d : A) l i n,
nth_default d (firstn n l) i = if le_dec n (length l)
then if lt_dec i n then nth_default d l i else d
else nth_default d l i.
Proof.
induction n; intros; break_if; autorewrite with push_nth_default; auto; try omega.
+ rewrite (firstn_succ d) by omega.
autorewrite with push_nth_default; repeat (break_if; distr_length);
rewrite Min.min_l in * by omega; try omega.
- apply IHn; omega.
- replace i with n in * by omega.
rewrite Nat.sub_diag.
autorewrite with push_nth_default; auto.
- rewrite nth_default_out_of_bounds; distr_length; auto.
+ rewrite firstn_all2 by omega.
auto.
Qed.
Hint Rewrite @nth_default_firstn : push_nth_default.
Lemma nth_error_repeat {T} x n i v : nth_error (@repeat T x n) i = Some v -> v = x.
Proof.
revert n x v; induction i as [|i IHi]; destruct n; simpl in *; eauto; congruence.
Qed.
Hint Rewrite repeat_length : distr_length.
Lemma repeat_spec_iff : forall {A} (ls : list A) x n,
(length ls = n /\ forall y, In y ls -> y = x) <-> ls = repeat x n.
Proof.
split; [ revert A ls x n | intro; subst; eauto using repeat_length, repeat_spec ].
induction ls, n; simpl; intros; intuition try congruence.
f_equal; auto.
Qed.
Lemma repeat_spec_eq : forall {A} (ls : list A) x n,
length ls = n
-> (forall y, In y ls -> y = x)
-> ls = repeat x n.
Proof.
intros; apply repeat_spec_iff; auto.
Qed.
Lemma tl_repeat {A} x n : tl (@repeat A x n) = repeat x (pred n).
Proof. destruct n; reflexivity. Qed.
Lemma firstn_repeat : forall {A} x n k, firstn k (@repeat A x n) = repeat x (min k n).
Proof. induction n, k; boring. Qed.
Hint Rewrite @firstn_repeat : push_firstn.
Lemma skipn_repeat : forall {A} x n k, skipn k (@repeat A x n) = repeat x (n - k).
Proof. induction n, k; boring. Qed.
Hint Rewrite @skipn_repeat : push_skipn.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND2_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__TAPVGND2_PP_BLACKBOX_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND2_PP_BLACKBOX_V
|
// megafunction wizard: %ALTFP_CONVERT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_CONVERT
// ============================================================
// File Name: int16_float32.v
// Megafunction Name(s):
// ALTFP_CONVERT
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
//altfp_convert CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" OPERATION="INT2FLOAT" ROUNDING="TO_NEAREST" WIDTH_DATA=16 WIDTH_EXP_INPUT=8 WIDTH_EXP_OUTPUT=8 WIDTH_INT=16 WIDTH_MAN_INPUT=23 WIDTH_MAN_OUTPUT=23 WIDTH_RESULT=32 clock dataa result
//VERSION_BEGIN 14.1 cbx_altbarrel_shift 2014:12:03:18:16:05:SJ cbx_altfp_convert 2014:12:03:18:16:05:SJ cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_altsyncram 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_abs 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_compare 2014:12:03:18:16:05:SJ cbx_lpm_decode 2014:12:03:18:16:05:SJ cbx_lpm_divide 2014:12:03:18:16:05:SJ cbx_lpm_mux 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ cbx_stratixiii 2014:12:03:18:16:05:SJ cbx_stratixv 2014:12:03:18:16:05:SJ cbx_util_mgl 2014:12:03:18:16:05:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" PIPELINE=2 SHIFTDIR="LEFT" SHIFTTYPE="LOGICAL" WIDTH=16 WIDTHDIST=4 aclr clk_en clock data distance result
//VERSION_BEGIN 14.1 cbx_altbarrel_shift 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//synthesis_resources = reg 36
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int16_float32_altbarrel_shift_gof
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [15:0] data;
input [3:0] distance;
output [15:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] dir_pipe;
reg [15:0] sbit_piper1d;
reg [15:0] sbit_piper2d;
reg sel_pipec2r1d;
reg sel_pipec3r1d;
wire [4:0] dir_w;
wire direction_w;
wire [7:0] pad_w;
wire [79:0] sbit_w;
wire [3:0] sel_w;
wire [63:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 2'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[3], dir_w[1]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 16'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[31:16];
// synopsys translate_off
initial
sbit_piper2d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper2d <= 16'b0;
else if (clk_en == 1'b1) sbit_piper2d <= smux_w[63:48];
// synopsys translate_off
initial
sel_pipec2r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec2r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec2r1d <= distance[2];
// synopsys translate_off
initial
sel_pipec3r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec3r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec3r1d <= distance[3];
assign
dir_w = {dir_pipe[1], dir_w[2], dir_pipe[0], dir_w[0], direction_w},
direction_w = 1'b0,
pad_w = {8{1'b0}},
result = sbit_w[79:64],
sbit_w = {sbit_piper2d, smux_w[47:32], sbit_piper1d, smux_w[15:0], data},
sel_w = {sel_pipec3r1d, sel_pipec2r1d, distance[1:0]},
smux_w = {((({16{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[55:48], pad_w[7:0]}) | ({16{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[63:56]})) | ({16{(~ sel_w[3])}} & sbit_w[63:48])), ((({16{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[43:32], pad_w[3:0]}) | ({16{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[47:36]})) | ({16{(~ sel_w[2])}} & sbit_w[47:32])), ((({16{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[29:16], pad_w[1:0]}) | ({16{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[31:18]})) | ({16{(~ sel_w[1])}} & sbit_w[31:16])), ((({16{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[14:0], pad_w[0]}) | ({16{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[15:1]})) | ({16{(~ sel_w[0])}} & sbit_w[15:0]))};
endmodule //int16_float32_altbarrel_shift_gof
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int16_float32_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //int16_float32_altpriority_encoder_3v7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int16_float32_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //int16_float32_altpriority_encoder_3e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int16_float32_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder10_q;
wire [0:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
int16_float32_altpriority_encoder_3v7 altpriority_encoder10
(
.data(data[1:0]),
.q(wire_altpriority_encoder10_q));
int16_float32_altpriority_encoder_3e8 altpriority_encoder11
(
.data(data[3:2]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
assign
q = {(~ wire_altpriority_encoder11_zero), ((wire_altpriority_encoder11_zero & wire_altpriority_encoder10_q) | ((~ wire_altpriority_encoder11_zero) & wire_altpriority_encoder11_q))};
endmodule //int16_float32_altpriority_encoder_6v7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int16_float32_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder12_q;
wire wire_altpriority_encoder12_zero;
wire [0:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
int16_float32_altpriority_encoder_3e8 altpriority_encoder12
(
.data(data[1:0]),
.q(wire_altpriority_encoder12_q),
.zero(wire_altpriority_encoder12_zero));
int16_float32_altpriority_encoder_3e8 altpriority_encoder13
(
.data(data[3:2]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
assign
q = {(~ wire_altpriority_encoder13_zero), ((wire_altpriority_encoder13_zero & wire_altpriority_encoder12_q) | ((~ wire_altpriority_encoder13_zero) & wire_altpriority_encoder13_q))},
zero = (wire_altpriority_encoder12_zero & wire_altpriority_encoder13_zero);
endmodule //int16_float32_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int16_float32_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder8_q;
wire [1:0] wire_altpriority_encoder9_q;
wire wire_altpriority_encoder9_zero;
int16_float32_altpriority_encoder_6v7 altpriority_encoder8
(
.data(data[3:0]),
.q(wire_altpriority_encoder8_q));
int16_float32_altpriority_encoder_6e8 altpriority_encoder9
(
.data(data[7:4]),
.q(wire_altpriority_encoder9_q),
.zero(wire_altpriority_encoder9_zero));
assign
q = {(~ wire_altpriority_encoder9_zero), (({2{wire_altpriority_encoder9_zero}} & wire_altpriority_encoder8_q) | ({2{(~ wire_altpriority_encoder9_zero)}} & wire_altpriority_encoder9_q))};
endmodule //int16_float32_altpriority_encoder_bv7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 14.1 cbx_altpriority_encoder 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int16_float32_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
wire [1:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
int16_float32_altpriority_encoder_6e8 altpriority_encoder14
(
.data(data[3:0]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero));
int16_float32_altpriority_encoder_6e8 altpriority_encoder15
(
.data(data[7:4]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
assign
q = {(~ wire_altpriority_encoder15_zero), (({2{wire_altpriority_encoder15_zero}} & wire_altpriority_encoder14_q) | ({2{(~ wire_altpriority_encoder15_zero)}} & wire_altpriority_encoder15_q))},
zero = (wire_altpriority_encoder14_zero & wire_altpriority_encoder15_zero);
endmodule //int16_float32_altpriority_encoder_be8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int16_float32_altpriority_encoder_rb6
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder6_q;
wire [2:0] wire_altpriority_encoder7_q;
wire wire_altpriority_encoder7_zero;
int16_float32_altpriority_encoder_bv7 altpriority_encoder6
(
.data(data[7:0]),
.q(wire_altpriority_encoder6_q));
int16_float32_altpriority_encoder_be8 altpriority_encoder7
(
.data(data[15:8]),
.q(wire_altpriority_encoder7_q),
.zero(wire_altpriority_encoder7_zero));
assign
q = {(~ wire_altpriority_encoder7_zero), (({3{wire_altpriority_encoder7_zero}} & wire_altpriority_encoder6_q) | ({3{(~ wire_altpriority_encoder7_zero)}} & wire_altpriority_encoder7_q))};
endmodule //int16_float32_altpriority_encoder_rb6
//synthesis_resources = lpm_add_sub 2 lpm_compare 1 reg 155
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int16_float32_altfp_convert_bqm
(
clock,
dataa,
result) ;
input clock;
input [15:0] dataa;
output [31:0] result;
wire [15:0] wire_altbarrel_shift5_result;
wire [3:0] wire_altpriority_encoder2_q;
reg [7:0] exponent_bus_pre_reg;
reg [7:0] exponent_bus_pre_reg2;
reg [7:0] exponent_bus_pre_reg3;
reg [14:0] mag_int_a_reg;
reg [14:0] mag_int_a_reg2;
reg [23:0] mantissa_pre_round_reg;
reg [3:0] priority_encoder_reg;
reg [31:0] result_reg;
reg sign_int_a_reg1;
reg sign_int_a_reg2;
reg sign_int_a_reg3;
reg sign_int_a_reg4;
reg sign_int_a_reg5;
wire [14:0] wire_add_sub1_result;
wire [7:0] wire_add_sub3_result;
wire wire_cmpr4_alb;
wire aclr;
wire [7:0] bias_value_w;
wire clk_en;
wire [7:0] const_bias_value_add_width_int_w;
wire [7:0] exceptions_value;
wire [7:0] exponent_bus;
wire [7:0] exponent_bus_pre;
wire [7:0] exponent_output_w;
wire [7:0] exponent_rounded;
wire [7:0] exponent_zero_w;
wire [14:0] int_a;
wire [14:0] int_a_2s;
wire [14:0] invert_int_a;
wire [3:0] leading_zeroes;
wire [14:0] mag_int_a;
wire [22:0] mantissa_bus;
wire [23:0] mantissa_pre_round;
wire [23:0] mantissa_rounded;
wire max_neg_value_selector;
wire [7:0] max_neg_value_w;
wire [7:0] minus_leading_zero;
wire [15:0] prio_mag_int_a;
wire [31:0] result_w;
wire [14:0] shifted_mag_int_a;
wire sign_bus;
wire sign_int_a;
wire [3:0] zero_padding_w;
int16_float32_altbarrel_shift_gof altbarrel_shift5
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({1'b0, mag_int_a_reg2}),
.distance(leading_zeroes),
.result(wire_altbarrel_shift5_result));
int16_float32_altpriority_encoder_rb6 altpriority_encoder2
(
.data(prio_mag_int_a),
.q(wire_altpriority_encoder2_q));
// synopsys translate_off
initial
exponent_bus_pre_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg <= 8'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg <= exponent_bus_pre_reg2;
// synopsys translate_off
initial
exponent_bus_pre_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg2 <= 8'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg2 <= exponent_bus_pre_reg3;
// synopsys translate_off
initial
exponent_bus_pre_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg3 <= 8'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg3 <= exponent_bus_pre;
// synopsys translate_off
initial
mag_int_a_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg <= 15'b0;
else if (clk_en == 1'b1) mag_int_a_reg <= mag_int_a;
// synopsys translate_off
initial
mag_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg2 <= 15'b0;
else if (clk_en == 1'b1) mag_int_a_reg2 <= mag_int_a_reg;
// synopsys translate_off
initial
mantissa_pre_round_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mantissa_pre_round_reg <= 24'b0;
else if (clk_en == 1'b1) mantissa_pre_round_reg <= mantissa_pre_round;
// synopsys translate_off
initial
priority_encoder_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) priority_encoder_reg <= 4'b0;
else if (clk_en == 1'b1) priority_encoder_reg <= wire_altpriority_encoder2_q;
// synopsys translate_off
initial
result_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) result_reg <= 32'b0;
else if (clk_en == 1'b1) result_reg <= result_w;
// synopsys translate_off
initial
sign_int_a_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg1 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg1 <= sign_int_a;
// synopsys translate_off
initial
sign_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg2 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg2 <= sign_int_a_reg1;
// synopsys translate_off
initial
sign_int_a_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg3 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg3 <= sign_int_a_reg2;
// synopsys translate_off
initial
sign_int_a_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg4 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg4 <= sign_int_a_reg3;
// synopsys translate_off
initial
sign_int_a_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg5 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg5 <= sign_int_a_reg4;
lpm_add_sub add_sub1
(
.cout(),
.dataa(invert_int_a),
.datab(15'b000000000000001),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "ADD",
add_sub1.lpm_width = 15,
add_sub1.lpm_type = "lpm_add_sub",
add_sub1.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub3
(
.cout(),
.dataa(const_bias_value_add_width_int_w),
.datab(minus_leading_zero),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_width = 8,
add_sub3.lpm_type = "lpm_add_sub",
add_sub3.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_compare cmpr4
(
.aeb(),
.agb(),
.ageb(),
.alb(wire_cmpr4_alb),
.aleb(),
.aneb(),
.dataa(exponent_output_w),
.datab(bias_value_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr4.lpm_representation = "UNSIGNED",
cmpr4.lpm_width = 8,
cmpr4.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
bias_value_w = 8'b01111111,
clk_en = 1'b1,
const_bias_value_add_width_int_w = 8'b10001101,
exceptions_value = (({8{(~ max_neg_value_selector)}} & exponent_zero_w) | ({8{max_neg_value_selector}} & max_neg_value_w)),
exponent_bus = exponent_rounded,
exponent_bus_pre = (({8{(~ wire_cmpr4_alb)}} & exponent_output_w) | ({8{wire_cmpr4_alb}} & exceptions_value)),
exponent_output_w = wire_add_sub3_result,
exponent_rounded = exponent_bus_pre_reg,
exponent_zero_w = {8{1'b0}},
int_a = dataa[14:0],
int_a_2s = wire_add_sub1_result,
invert_int_a = (~ int_a),
leading_zeroes = (~ priority_encoder_reg),
mag_int_a = (({15{(~ sign_int_a)}} & int_a) | ({15{sign_int_a}} & int_a_2s)),
mantissa_bus = mantissa_rounded[22:0],
mantissa_pre_round = {shifted_mag_int_a[14:0], {9{1'b0}}},
mantissa_rounded = mantissa_pre_round_reg,
max_neg_value_selector = (wire_cmpr4_alb & sign_int_a_reg2),
max_neg_value_w = 8'b10001110,
minus_leading_zero = {zero_padding_w, leading_zeroes},
prio_mag_int_a = {mag_int_a_reg, 1'b1},
result = result_reg,
result_w = {sign_bus, exponent_bus, mantissa_bus},
shifted_mag_int_a = wire_altbarrel_shift5_result[14:0],
sign_bus = sign_int_a_reg5,
sign_int_a = dataa[15],
zero_padding_w = {4{1'b0}};
endmodule //int16_float32_altfp_convert_bqm
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module int16_float32 (
clock,
dataa,
result);
input clock;
input [15:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
int16_float32_altfp_convert_bqm int16_float32_altfp_convert_bqm_component (
.clock (clock),
.dataa (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_convert"
// Retrieval info: CONSTANT: OPERATION STRING "INT2FLOAT"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_DATA NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_EXP_INPUT NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_EXP_OUTPUT NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_INT NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_MAN_INPUT NUMERIC "23"
// Retrieval info: CONSTANT: WIDTH_MAN_OUTPUT NUMERIC "23"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL int16_float32.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL int16_float32.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL int16_float32.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int16_float32_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int16_float32_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int16_float32.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int16_float32.cmp TRUE TRUE
// Retrieval info: LIB_FILE: lpm
|
// Full Adder rtl
module full_adder (a0, b0, c0, a1, b1, c_out, s_out, s2, s3);
// Inputs_top
input a0;
input b0;
input c0;
input a1;
input b1;
// End of inputs_top
// Outputs_top
output c_out;
output s_out;
output s2;
output d1;
output s3;
// End of outputs_top
// Wires
wire c1;
wire c2;
wire s1;
wire d1;
wire c3;
// Some assignments
assign carry_out = c1 | c2;
assign s_out = s1;
//assign d_out = d1;
// Instantiating two half-adders to make the circuit.
// Module instantiation
half_adder u1_half_adder (
// Inputs
.in_x(a0),
.in_y(b0),
// End of inputs
// Outputs
.out_sum(s0),
.out_carry(c1)
// End of outputs
);
// Module instantiation
half_adder u2_half_adder (
// Inputs
.in_x(s0),
.in_y(c0),
// End of inputs
// Outputs
.out_sum(s1),
.out_carry(c2)
// End of outputs
);
// Module instantiation
test1 test1 (
// Inputs
.in_1(s1),
.in_2(s0),
.in_3(a1),
.in_4(b1),
// End of inputs
// Outputs
.out_1(s2),
.out_2(d1),
.out_3(c3)
// End of outputs
);
// Module instantiation
test2 test2 (
// Inputs
.in_1(d1),
.in_2(c3),
.in_3(b1),
// End of inputs
// Outputs
.out_1(s3)
// End of outputs
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__HA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__HA_BEHAVIORAL_PP_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire xor0_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__HA_BEHAVIORAL_PP_V
|
(* src = "../../verilog/adt7310.v:1", top = 1 *)
module ADT7310 (
(* intersynth_port = "Reset_n_i", src = "../../verilog/adt7310.v:3" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/adt7310.v:5" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/adt7310.v:7" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/adt7310.v:9" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "Outputs_o", src = "../../verilog/adt7310.v:11" *)
output ADT7310CS_n_o,
(* intersynth_conntype = "Byte", intersynth_port = "SPI_DataOut", src = "../../verilog/adt7310.v:13" *)
input[7:0] SPI_Data_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_Write", src = "../../verilog/adt7310.v:15" *)
output SPI_Write_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_ReadNext", src = "../../verilog/adt7310.v:17" *)
output SPI_ReadNext_o,
(* intersynth_conntype = "Byte", intersynth_port = "SPI_DataIn", src = "../../verilog/adt7310.v:19" *)
output[7:0] SPI_Data_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_FIFOFull", src = "../../verilog/adt7310.v:21" *)
input SPI_FIFOFull_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_FIFOEmpty", src = "../../verilog/adt7310.v:23" *)
input SPI_FIFOEmpty_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_Transmission", src = "../../verilog/adt7310.v:25" *)
input SPI_Transmission_i,
(* intersynth_conntype = "Word", intersynth_param = "SPICounterPresetH_i", src = "../../verilog/adt7310.v:27" *)
input[15:0] SPICounterPresetH_i,
(* intersynth_conntype = "Word", intersynth_param = "SPICounterPresetL_i", src = "../../verilog/adt7310.v:29" *)
input[15:0] SPICounterPresetL_i,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/adt7310.v:31" *)
input[15:0] Threshold_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPreset_i", src = "../../verilog/adt7310.v:33" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/adt7310.v:35" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_CPOL", src = "../../verilog/adt7310.v:37" *)
output SPI_CPOL_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_CPHA", src = "../../verilog/adt7310.v:39" *)
output SPI_CPHA_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_LSBFE", src = "../../verilog/adt7310.v:41" *)
output SPI_LSBFE_o
);
wire \$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2459 ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:12" *)
wire [15:0] \$techmap\SPIFSM_1.$extract$\Counter32_RV1_Timer$2533.DH_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:13" *)
wire [15:0] \$techmap\SPIFSM_1.$extract$\Counter32_RV1_Timer$2533.DL_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:14" *)
wire \$techmap\SPIFSM_1.$extract$\Counter32_RV1_Timer$2533.Overflow_s ;
wire \$techmap\SPIFSM_1.$procmux$297_CMP ;
wire \$techmap\SPIFSM_1.$procmux$302_CMP ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:8" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:7" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.D_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:11" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:10" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:9" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Zero_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:14" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2532.D_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:15" *)
wire \$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2532.Overflow_s ;
(* src = "../../verilog/spifsm.v:45" *)
wire \SPIFSM_1.SPI_FSM_TimerEnable ;
(* src = "../../verilog/spifsm.v:43" *)
wire \SPIFSM_1.SPI_FSM_TimerOvfl ;
(* src = "../../verilog/spifsm.v:44" *)
wire \SPIFSM_1.SPI_FSM_TimerPreset ;
(* src = "../../verilog/spifsm.v:47" *)
wire \SPIFSM_1.SPI_FSM_Wr0 ;
(* src = "../../verilog/spifsm.v:46" *)
wire \SPIFSM_1.SPI_FSM_Wr1 ;
(* keep = 1, src = "../../verilog/adt7310.v:56" *)
wire [7:0] SPIFSM_Byte0_s;
(* keep = 1, src = "../../verilog/adt7310.v:58" *)
wire [7:0] SPIFSM_Byte1_s;
(* keep = 1, src = "../../verilog/adt7310.v:54" *)
wire SPIFSM_Done_s;
(* keep = 1, src = "../../verilog/adt7310.v:52" *)
wire SPIFSM_Start_s;
(* src = "../../verilog/sensorfsm.v:39" *)
wire [15:0] \SensorFSM_1.AbsDiffResult ;
(* src = "../../verilog/sensorfsm.v:33" *)
wire \SensorFSM_1.SensorFSM_StoreNewValue ;
(* src = "../../verilog/sensorfsm.v:31" *)
wire \SensorFSM_1.SensorFSM_TimerEnable ;
(* src = "../../verilog/sensorfsm.v:29" *)
wire \SensorFSM_1.SensorFSM_TimerOvfl ;
(* src = "../../verilog/sensorfsm.v:30" *)
wire \SensorFSM_1.SensorFSM_TimerPreset ;
(* src = "../../verilog/sensorfsm.v:37" *)
wire [15:0] \SensorFSM_1.SensorValue ;
wire SPIFSM_1_Out11_s;
wire SPIFSM_1_Out12_s;
wire SPIFSM_1_Out13_s;
wire SPIFSM_1_Out14_s;
wire SPIFSM_1_CfgMode_s;
wire SPIFSM_1_CfgClk_s;
wire SPIFSM_1_CfgShift_s;
wire SPIFSM_1_CfgDataIn_s;
wire SPIFSM_1_CfgDataOut_s;
wire SensorFSM_1_Out5_s;
wire SensorFSM_1_Out6_s;
wire SensorFSM_1_Out7_s;
wire SensorFSM_1_Out8_s;
wire SensorFSM_1_Out9_s;
wire SensorFSM_1_CfgMode_s;
wire SensorFSM_1_CfgClk_s;
wire SensorFSM_1_CfgShift_s;
wire SensorFSM_1_CfgDataIn_s;
wire SensorFSM_1_CfgDataOut_s;
Byte2Word \$extract$\Byte2Word$2543 (
.H_i(SPIFSM_Byte1_s),
.L_i(SPIFSM_Byte0_s),
.Y_o(\SensorFSM_1.SensorValue )
);
ByteMuxQuad \$techmap\SPIFSM_1.$extract$\ByteMuxQuad$2539 (
.A_i(8'b00001000),
.B_i(8'b11111111),
.C_i(8'b01010000),
.D_i(8'b00100000),
.SAB_i(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2459 ),
.SC_i(\$techmap\SPIFSM_1.$procmux$297_CMP ),
.SD_i(\$techmap\SPIFSM_1.$procmux$302_CMP ),
.Y_o(SPI_Data_o)
);
ByteRegister \$techmap\SPIFSM_1.$extract$\ByteRegister$2536 (
.Clk_i(Clk_i),
.D_i(SPI_Data_i),
.Enable_i(\SPIFSM_1.SPI_FSM_Wr0 ),
.Q_o(SPIFSM_Byte0_s),
.Reset_n_i(Reset_n_i)
);
ByteRegister \$techmap\SPIFSM_1.$extract$\ByteRegister$2537 (
.Clk_i(Clk_i),
.D_i(SPI_Data_i),
.Enable_i(\SPIFSM_1.SPI_FSM_Wr1 ),
.Q_o(SPIFSM_Byte1_s),
.Reset_n_i(Reset_n_i)
);
(* src = "../../../../counter32/verilog/counter32_rv1.v:19" *)
Counter32 \$techmap\SPIFSM_1.$extract$\Counter32_RV1_Timer$2533.ThisCounter (
.Clk_i(Clk_i),
.DH_o(\$techmap\SPIFSM_1.$extract$\Counter32_RV1_Timer$2533.DH_s ),
.DL_o(\$techmap\SPIFSM_1.$extract$\Counter32_RV1_Timer$2533.DL_s ),
.Direction_i(1'b1),
.Enable_i(\SPIFSM_1.SPI_FSM_TimerEnable ),
.Overflow_o(\$techmap\SPIFSM_1.$extract$\Counter32_RV1_Timer$2533.Overflow_s ),
.PresetValH_i(SPICounterPresetH_i),
.PresetValL_i(SPICounterPresetL_i),
.Preset_i(\SPIFSM_1.SPI_FSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\SPIFSM_1.SPI_FSM_TimerOvfl )
);
SPIFSM SPIFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(\SPIFSM_1.SPI_FSM_TimerOvfl ),
.In1_i(SPI_Transmission_i),
.In2_i(SPIFSM_Start_s),
.In3_i(1'b0),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.Out0_o(\$techmap\SPIFSM_1.$procmux$297_CMP ),
.Out1_o(\$techmap\SPIFSM_1.$procmux$302_CMP ),
.Out2_o(\SPIFSM_1.SPI_FSM_Wr0 ),
.Out3_o(\SPIFSM_1.SPI_FSM_Wr1 ),
.Out4_o(\$techmap\SPIFSM_1.$auto$opt_reduce.cc:126:opt_mux$2459 ),
.Out5_o(\SPIFSM_1.SPI_FSM_TimerEnable ),
.Out6_o(\SPIFSM_1.SPI_FSM_TimerPreset ),
.Out7_o(ADT7310CS_n_o),
.Out8_o(SPIFSM_Done_s),
.Out9_o(SPI_Write_o),
.Out10_o(SPI_ReadNext_o),
.Out11_o(SPIFSM_1_Out11_s),
.Out12_o(SPIFSM_1_Out12_s),
.Out13_o(SPIFSM_1_Out13_s),
.Out14_o(SPIFSM_1_Out14_s),
.CfgMode_i(SPIFSM_1_CfgMode_s),
.CfgClk_i(SPIFSM_1_CfgClk_s),
.CfgShift_i(SPIFSM_1_CfgShift_s),
.CfgDataIn_i(SPIFSM_1_CfgDataIn_s),
.CfgDataOut_o(SPIFSM_1_CfgDataOut_s)
);
AbsDiff \$techmap\SensorFSM_1.$extract$\AbsDiff$2534 (
.A_i(\SensorFSM_1.SensorValue ),
.B_i(SensorValue_o),
.D_o(\SensorFSM_1.AbsDiffResult )
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:13" *)
AddSubCmp \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.ThisAddSubCmp (
.A_i(\SensorFSM_1.AbsDiffResult ),
.AddOrSub_i(1'b1),
.B_i(Threshold_i),
.Carry_i(1'b0),
.Carry_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Carry_s ),
.D_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.D_s ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Overflow_s ),
.Sign_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Sign_s ),
.Zero_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Zero_s )
);
(* src = "../../../../counter/verilog/counter_rv1.v:20" *)
Counter \$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2532.ThisCounter (
.Clk_i(Clk_i),
.D_o(\$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2532.D_s ),
.Direction_i(1'b1),
.Enable_i(\SensorFSM_1.SensorFSM_TimerEnable ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\Counter_RV1_Timer$2532.Overflow_s ),
.PresetVal_i(PeriodCounterPreset_i),
.Preset_i(\SensorFSM_1.SensorFSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\SensorFSM_1.SensorFSM_TimerOvfl )
);
WordRegister \$techmap\SensorFSM_1.$extract$\WordRegister$2535 (
.Clk_i(Clk_i),
.D_i(\SensorFSM_1.SensorValue ),
.Enable_i(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Q_o(SensorValue_o),
.Reset_n_i(Reset_n_i)
);
SensorFSM SensorFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(Enable_i),
.In1_i(SPIFSM_Done_s),
.In2_i(\SensorFSM_1.SensorFSM_TimerOvfl ),
.In3_i(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Carry_s ),
.In4_i(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2538.Zero_s ),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.In8_i(1'b0),
.In9_i(1'b0),
.Out0_o(SPIFSM_Start_s),
.Out1_o(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Out2_o(\SensorFSM_1.SensorFSM_TimerEnable ),
.Out3_o(\SensorFSM_1.SensorFSM_TimerPreset ),
.Out4_o(CpuIntr_o),
.Out5_o(SensorFSM_1_Out5_s),
.Out6_o(SensorFSM_1_Out6_s),
.Out7_o(SensorFSM_1_Out7_s),
.Out8_o(SensorFSM_1_Out8_s),
.Out9_o(SensorFSM_1_Out9_s),
.CfgMode_i(SensorFSM_1_CfgMode_s),
.CfgClk_i(SensorFSM_1_CfgClk_s),
.CfgShift_i(SensorFSM_1_CfgShift_s),
.CfgDataIn_i(SensorFSM_1_CfgDataIn_s),
.CfgDataOut_o(SensorFSM_1_CfgDataOut_s)
);
assign SPI_CPHA_o = 1'b1;
assign SPI_CPOL_o = 1'b1;
assign SPI_LSBFE_o = 1'b0;
assign SPIFSM_1_CfgMode_s = 1'b0;
assign SPIFSM_1_CfgClk_s = 1'b0;
assign SPIFSM_1_CfgShift_s = 1'b0;
assign SPIFSM_1_CfgDataIn_s = 1'b0;
assign SensorFSM_1_CfgMode_s = 1'b0;
assign SensorFSM_1_CfgClk_s = 1'b0;
assign SensorFSM_1_CfgShift_s = 1'b0;
assign SensorFSM_1_CfgDataIn_s = 1'b0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__MUX4_FUNCTIONAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_4to2/sky130_fd_sc_hd__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_hd__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX4_FUNCTIONAL_PP_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 20:13:38 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1,
OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2, SIGN_FLAG_SHT2,
OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2,
SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n1037, n1038, n1039, n1040,
n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050,
n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060,
n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070,
n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080,
n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090,
n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100,
n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1628, n1629, n1630, n1631, n1632,
n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642,
n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652,
n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662,
n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672,
n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682,
n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692,
n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1822, n1823, n1824,
DP_OP_15J75_123_4372_n11, DP_OP_15J75_123_4372_n10,
DP_OP_15J75_123_4372_n9, DP_OP_15J75_123_4372_n8,
DP_OP_15J75_123_4372_n7, DP_OP_15J75_123_4372_n6, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987,
n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997,
n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007,
n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017,
n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027,
n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037,
n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047,
n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057,
n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067,
n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077,
n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087,
n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097,
n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107,
n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117,
n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127,
n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137,
n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147,
n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157,
n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167,
n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177,
n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187,
n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197,
n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207,
n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217,
n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227,
n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237,
n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247,
n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257,
n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267,
n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287,
n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297,
n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307,
n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317,
n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327,
n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337,
n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347,
n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357,
n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367,
n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377,
n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387,
n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397,
n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407,
n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417,
n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427,
n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437,
n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447,
n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457,
n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467,
n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477,
n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487,
n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497,
n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507,
n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517,
n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527,
n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537,
n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547,
n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557,
n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567,
n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577,
n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587,
n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597,
n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607,
n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617,
n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627,
n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637,
n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647,
n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657,
n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667,
n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677,
n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687,
n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697,
n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707,
n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717,
n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727,
n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737,
n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747,
n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757,
n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767,
n2768, n2769, n2770, n2771, n2773, n2774, n2775, n2776, n2777, n2778,
n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788,
n2789, n2790, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799,
n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809,
n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819,
n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829,
n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839,
n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849,
n2850, n2851, n2852, n2854, n2855, n2856, n2857, n2858, n2859, n2860,
n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870,
n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880,
n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890,
n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900,
n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910,
n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920,
n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930,
n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940,
n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950,
n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960,
n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970,
n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980,
n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990,
n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000,
n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010,
n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020,
n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030,
n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040,
n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050,
n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060,
n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070,
n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080,
n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090,
n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100,
n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110,
n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122,
n3123, n3124, n3125, n3126, n3127, n3128, n3130, n3131, n3132, n3133,
n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143,
n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153,
n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163,
n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173,
n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183,
n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193,
n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203,
n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213,
n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223,
n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233,
n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243,
n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3253, n3254,
n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264,
n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274,
n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284,
n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294,
n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304,
n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314,
n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3530;
wire [1:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [63:0] intDY_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [62:0] DMP_SHT1_EWSW;
wire [51:1] DmP_mant_SHT1_SW;
wire [5:1] Shift_amount_SHT1_EWR;
wire [54:0] Raw_mant_NRM_SWR;
wire [34:0] Data_array_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [5:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [5:0] LZD_output_NRM2_EW;
wire [5:1] exp_rslt_NRM2_EW1;
wire [62:0] DMP_SFG;
wire [45:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n1822), .CK(clk), .RN(n3507), .Q(
n1832), .QN(n1997) );
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n1819), .CK(clk), .RN(n3471), .QN(
n1865) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1751), .CK(clk), .RN(n3492), .Q(
intAS) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(n3468), .CK(clk), .RN(n3494), .Q(ready) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_52_ ( .D(n1683), .CK(clk), .RN(n3486), .QN(
n1841) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_38_ ( .D(n1669), .CK(clk), .RN(n3477), .Q(
Data_array_SWR[20]), .QN(n3456) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_37_ ( .D(n1668), .CK(clk), .RN(n3486), .Q(
Data_array_SWR[19]), .QN(n3455) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_36_ ( .D(n1667), .CK(clk), .RN(n3477), .Q(
Data_array_SWR[18]), .QN(n3457) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_35_ ( .D(n1666), .CK(clk), .RN(n3478), .QN(
n1836) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_34_ ( .D(n1665), .CK(clk), .RN(n3477), .QN(
n1834) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_33_ ( .D(n1664), .CK(clk), .RN(n3477), .QN(
n1838) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_32_ ( .D(n1663), .CK(clk), .RN(n3477), .QN(
n1837) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_31_ ( .D(n1662), .CK(clk), .RN(n3517), .QN(
n1828) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_30_ ( .D(n1661), .CK(clk), .RN(n3478), .QN(
n1869) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_28_ ( .D(n1659), .CK(clk), .RN(n3478), .QN(
n1874) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1653), .CK(clk), .RN(n3478), .QN(
n1879) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1651), .CK(clk), .RN(n3478), .QN(
n1878) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1649), .CK(clk), .RN(n3477), .QN(
n1830) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1646), .CK(clk), .RN(n3517), .QN(
n1831) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1645), .CK(clk), .RN(n3477), .QN(
n1842) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1644), .CK(clk), .RN(n3478), .QN(
n1844) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1643), .CK(clk), .RN(n3477), .QN(
n1843) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1642), .CK(clk), .RN(n3477), .QN(
n1845) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1641), .CK(clk), .RN(n3477), .QN(
n1846) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1640), .CK(clk), .RN(n3494), .QN(
n1847) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1639), .CK(clk), .RN(n3477), .QN(
n1848) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1634), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[3]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_45_ ( .D(n1676), .CK(clk), .RN(n3482), .QN(
n1839) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1625), .CK(clk), .RN(n3484),
.QN(n1840) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1624), .CK(clk), .RN(n3525),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1623), .CK(clk), .RN(n3496),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1622), .CK(clk), .RN(n3519),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1621), .CK(clk), .RN(n3484),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(n1620), .CK(clk), .RN(n3522),
.Q(Shift_amount_SHT1_EWR[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n1619), .CK(clk), .RN(n3514), .Q(
final_result_ieee[52]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n1618), .CK(clk), .RN(n3508), .Q(
final_result_ieee[53]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n1617), .CK(clk), .RN(n3514), .Q(
final_result_ieee[54]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n1616), .CK(clk), .RN(n3508), .Q(
final_result_ieee[55]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n1615), .CK(clk), .RN(n3484), .Q(
final_result_ieee[56]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n1614), .CK(clk), .RN(n3521), .Q(
final_result_ieee[57]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n1613), .CK(clk), .RN(n3511), .Q(
final_result_ieee[58]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n1612), .CK(clk), .RN(n3484), .Q(
final_result_ieee[59]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n1611), .CK(clk), .RN(n3521), .Q(
final_result_ieee[60]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n1610), .CK(clk), .RN(n3510), .Q(
final_result_ieee[61]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n1609), .CK(clk), .RN(n3511), .Q(
final_result_ieee[62]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n1608), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n1607), .CK(clk), .RN(n3513), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n1606), .CK(clk), .RN(n3486), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n1605), .CK(clk), .RN(n3482), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n1604), .CK(clk), .RN(n3512), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n1603), .CK(clk), .RN(n3485), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n1602), .CK(clk), .RN(n3511), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n1601), .CK(clk), .RN(n3511), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n1600), .CK(clk), .RN(n3522), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n1599), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n1598), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n1597), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n1596), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n1595), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n1594), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n1593), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n1592), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n1591), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n1590), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n1589), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n1588), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n1587), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n1586), .CK(clk), .RN(n3491), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(n1585), .CK(clk), .RN(n3483), .Q(
DMP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(n1584), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(n1583), .CK(clk), .RN(n3483), .Q(
DMP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(n1582), .CK(clk), .RN(n3511), .Q(
DMP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n1581), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n1580), .CK(clk), .RN(n3483), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n1579), .CK(clk), .RN(n3488), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n1578), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_31_ ( .D(n1577), .CK(clk), .RN(n3482), .Q(
DMP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_32_ ( .D(n1576), .CK(clk), .RN(n3491), .Q(
DMP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_33_ ( .D(n1575), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_34_ ( .D(n1574), .CK(clk), .RN(n3530), .Q(
DMP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_35_ ( .D(n1573), .CK(clk), .RN(n3485), .Q(
DMP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_36_ ( .D(n1572), .CK(clk), .RN(n3530), .Q(
DMP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_37_ ( .D(n1571), .CK(clk), .RN(n3488), .Q(
DMP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_38_ ( .D(n1570), .CK(clk), .RN(n3530), .Q(
DMP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_39_ ( .D(n1569), .CK(clk), .RN(n3483), .Q(
DMP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_40_ ( .D(n1568), .CK(clk), .RN(n3511), .Q(
DMP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_41_ ( .D(n1567), .CK(clk), .RN(n3514), .Q(
DMP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_42_ ( .D(n1566), .CK(clk), .RN(n3518), .Q(
DMP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_43_ ( .D(n1565), .CK(clk), .RN(n3516), .Q(
DMP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_44_ ( .D(n1564), .CK(clk), .RN(n3503), .Q(
DMP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_45_ ( .D(n1563), .CK(clk), .RN(n3530), .Q(
DMP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_46_ ( .D(n1562), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_47_ ( .D(n1561), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_48_ ( .D(n1560), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_49_ ( .D(n1559), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_50_ ( .D(n1558), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_51_ ( .D(n1557), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[51]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_58_ ( .D(n1550), .CK(clk), .RN(n3506), .Q(
DMP_EXP_EWSW[58]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_59_ ( .D(n1549), .CK(clk), .RN(n3479), .Q(
DMP_EXP_EWSW[59]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_60_ ( .D(n1548), .CK(clk), .RN(n3503), .Q(
DMP_EXP_EWSW[60]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_61_ ( .D(n1547), .CK(clk), .RN(n3475), .Q(
DMP_EXP_EWSW[61]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_62_ ( .D(n1546), .CK(clk), .RN(n3497), .Q(
DMP_EXP_EWSW[62]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1545), .CK(clk), .RN(n3498), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1544), .CK(clk), .RN(n3492), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1543), .CK(clk), .RN(n3525), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1542), .CK(clk), .RN(n3505), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1541), .CK(clk), .RN(n3472), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1539), .CK(clk), .RN(n3506), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1538), .CK(clk), .RN(n3490), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1536), .CK(clk), .RN(n3500), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1535), .CK(clk), .RN(n3517), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n1534), .CK(clk), .RN(n3481), .Q(
DMP_SFG[2]), .QN(n3466) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1533), .CK(clk), .RN(n3496), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1532), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1530), .CK(clk), .RN(n3524), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1529), .CK(clk), .RN(n3499), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n1528), .CK(clk), .RN(n3510), .QN(n1849) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1527), .CK(clk), .RN(n3500), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1526), .CK(clk), .RN(n3522), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1524), .CK(clk), .RN(n3518), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1523), .CK(clk), .RN(n3493), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n1522), .CK(clk), .RN(n3515), .QN(n1880) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1521), .CK(clk), .RN(n3504), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1520), .CK(clk), .RN(n3482), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1518), .CK(clk), .RN(n3492), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1517), .CK(clk), .RN(n3524), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1515), .CK(clk), .RN(n3518), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1514), .CK(clk), .RN(n3483), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1512), .CK(clk), .RN(n3483), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1511), .CK(clk), .RN(n3483), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1509), .CK(clk), .RN(n3483), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1508), .CK(clk), .RN(n3483), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1506), .CK(clk), .RN(n3483), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1505), .CK(clk), .RN(n3483), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1503), .CK(clk), .RN(n3483), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1502), .CK(clk), .RN(n3510), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1500), .CK(clk), .RN(n3521), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1499), .CK(clk), .RN(n3484), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1497), .CK(clk), .RN(n3513), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1496), .CK(clk), .RN(n3512), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1494), .CK(clk), .RN(n3511), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1493), .CK(clk), .RN(n3510), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1491), .CK(clk), .RN(n3521), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1490), .CK(clk), .RN(n3508), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1488), .CK(clk), .RN(n3508), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1487), .CK(clk), .RN(n3480), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1485), .CK(clk), .RN(n3478), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1484), .CK(clk), .RN(n3477), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1482), .CK(clk), .RN(n3494), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1481), .CK(clk), .RN(n3487), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1479), .CK(clk), .RN(n3521), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1478), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1476), .CK(clk), .RN(n3522), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1475), .CK(clk), .RN(n3486), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1473), .CK(clk), .RN(n3485), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1472), .CK(clk), .RN(n3522), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1470), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1469), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1467), .CK(clk), .RN(n3522), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1466), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1464), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1463), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1461), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1460), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1458), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1457), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1455), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1454), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1452), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1451), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1449), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[31]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1448), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1446), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[32]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1445), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1443), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[33]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1442), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1440), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[34]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1439), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1437), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[35]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1436), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1434), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[36]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1433), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1431), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[37]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1430), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1428), .CK(clk), .RN(n3489), .Q(
DMP_SHT1_EWSW[38]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1427), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1425), .CK(clk), .RN(n3489), .Q(
DMP_SHT1_EWSW[39]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1424), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1422), .CK(clk), .RN(n3489), .Q(
DMP_SHT1_EWSW[40]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1421), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1419), .CK(clk), .RN(n3489), .Q(
DMP_SHT1_EWSW[41]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1418), .CK(clk), .RN(n3490), .Q(
DMP_SHT2_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1416), .CK(clk), .RN(n3490), .Q(
DMP_SHT1_EWSW[42]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1415), .CK(clk), .RN(n3490), .Q(
DMP_SHT2_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1413), .CK(clk), .RN(n3490), .Q(
DMP_SHT1_EWSW[43]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1412), .CK(clk), .RN(n3490), .Q(
DMP_SHT2_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1410), .CK(clk), .RN(n3490), .Q(
DMP_SHT1_EWSW[44]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1409), .CK(clk), .RN(n3490), .Q(
DMP_SHT2_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1407), .CK(clk), .RN(n3490), .Q(
DMP_SHT1_EWSW[45]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1406), .CK(clk), .RN(n3523), .Q(
DMP_SHT2_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1404), .CK(clk), .RN(n3491), .Q(
DMP_SHT1_EWSW[46]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1403), .CK(clk), .RN(n3523), .Q(
DMP_SHT2_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1401), .CK(clk), .RN(n3491), .Q(
DMP_SHT1_EWSW[47]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1400), .CK(clk), .RN(n3523), .Q(
DMP_SHT2_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1398), .CK(clk), .RN(n3491), .Q(
DMP_SHT1_EWSW[48]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1397), .CK(clk), .RN(n3523), .Q(
DMP_SHT2_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1395), .CK(clk), .RN(n3491), .Q(
DMP_SHT1_EWSW[49]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1394), .CK(clk), .RN(n3487), .Q(
DMP_SHT2_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1392), .CK(clk), .RN(n3523), .Q(
DMP_SHT1_EWSW[50]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1391), .CK(clk), .RN(n3516), .Q(
DMP_SHT2_EWSW[50]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1389), .CK(clk), .RN(n3491), .Q(
DMP_SHT1_EWSW[51]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1388), .CK(clk), .RN(n3530), .Q(
DMP_SHT2_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_52_ ( .D(n1386), .CK(clk), .RN(n3523), .Q(
DMP_SHT1_EWSW[52]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_52_ ( .D(n1385), .CK(clk), .RN(n3530), .Q(
DMP_SHT2_EWSW[52]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_52_ ( .D(n1384), .CK(clk), .RN(n3520), .Q(
DMP_SFG[52]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1383), .CK(clk), .RN(n3491), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_53_ ( .D(n1381), .CK(clk), .RN(n3493), .Q(
DMP_SHT1_EWSW[53]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_53_ ( .D(n1380), .CK(clk), .RN(n3515), .Q(
DMP_SHT2_EWSW[53]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_53_ ( .D(n1379), .CK(clk), .RN(n3504), .Q(
DMP_SFG[53]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1378), .CK(clk), .RN(n3482), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_54_ ( .D(n1376), .CK(clk), .RN(n3492), .Q(
DMP_SHT1_EWSW[54]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(n1375), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[54]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_54_ ( .D(n1374), .CK(clk), .RN(n3518), .Q(
DMP_SFG[54]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1373), .CK(clk), .RN(n3493), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_55_ ( .D(n1371), .CK(clk), .RN(n3515), .Q(
DMP_SHT1_EWSW[55]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_55_ ( .D(n1370), .CK(clk), .RN(n3504), .Q(
DMP_SHT2_EWSW[55]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_55_ ( .D(n1369), .CK(clk), .RN(n3482), .Q(
DMP_SFG[55]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1368), .CK(clk), .RN(n3492), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_56_ ( .D(n1366), .CK(clk), .RN(n3515), .Q(
DMP_SHT1_EWSW[56]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_56_ ( .D(n1365), .CK(clk), .RN(n3504), .Q(
DMP_SHT2_EWSW[56]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_56_ ( .D(n1364), .CK(clk), .RN(n3482), .Q(
DMP_SFG[56]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1363), .CK(clk), .RN(n3492), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_57_ ( .D(n1361), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[57]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_57_ ( .D(n1360), .CK(clk), .RN(n3518), .Q(
DMP_SHT2_EWSW[57]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_57_ ( .D(n1359), .CK(clk), .RN(n3493), .Q(
DMP_SFG[57]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1358), .CK(clk), .RN(n3515), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_58_ ( .D(n1356), .CK(clk), .RN(n3504), .Q(
DMP_SHT1_EWSW[58]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_58_ ( .D(n1355), .CK(clk), .RN(n3482), .Q(
DMP_SHT2_EWSW[58]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_58_ ( .D(n1354), .CK(clk), .RN(n3492), .Q(
DMP_SFG[58]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1353), .CK(clk), .RN(n3501), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_59_ ( .D(n1351), .CK(clk), .RN(n3515), .Q(
DMP_SHT1_EWSW[59]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(n1350), .CK(clk), .RN(n3504), .Q(
DMP_SHT2_EWSW[59]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_59_ ( .D(n1349), .CK(clk), .RN(n3482), .Q(
DMP_SFG[59]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1348), .CK(clk), .RN(n3492), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_60_ ( .D(n1346), .CK(clk), .RN(n3478), .Q(
DMP_SHT1_EWSW[60]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_60_ ( .D(n1345), .CK(clk), .RN(n3515), .Q(
DMP_SHT2_EWSW[60]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_60_ ( .D(n1344), .CK(clk), .RN(n3493), .Q(
DMP_SFG[60]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n1343), .CK(clk), .RN(n3504), .Q(
DMP_exp_NRM_EW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_61_ ( .D(n1341), .CK(clk), .RN(n3482), .Q(
DMP_SHT1_EWSW[61]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_61_ ( .D(n1340), .CK(clk), .RN(n3492), .Q(
DMP_SHT2_EWSW[61]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_61_ ( .D(n1339), .CK(clk), .RN(n3507), .Q(
DMP_SFG[61]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n1338), .CK(clk), .RN(n3493), .Q(
DMP_exp_NRM_EW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_62_ ( .D(n1336), .CK(clk), .RN(n3510), .Q(
DMP_SHT1_EWSW[62]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_62_ ( .D(n1335), .CK(clk), .RN(n3517), .Q(
DMP_SHT2_EWSW[62]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_62_ ( .D(n1334), .CK(clk), .RN(n3487), .Q(
DMP_SFG[62]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n1333), .CK(clk), .RN(n3523), .Q(
DMP_exp_NRM_EW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n1331), .CK(clk), .RN(n3517), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1330), .CK(clk), .RN(n3523),
.QN(n1850) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n1329), .CK(clk), .RN(n3487), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n1327), .CK(clk), .RN(n3517), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n3487), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n1323), .CK(clk), .RN(n3517), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1322), .CK(clk), .RN(n3489),
.QN(n1852) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n1321), .CK(clk), .RN(n3488), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1320), .CK(clk), .RN(n3521),
.QN(n1851) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n1319), .CK(clk), .RN(n3517), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n1317), .CK(clk), .RN(n3490), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1316), .CK(clk), .RN(n3517),
.QN(n1884) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n1315), .CK(clk), .RN(n3487), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n1313), .CK(clk), .RN(n3523), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n1311), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n1309), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n1307), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1306), .CK(clk), .RN(n3494),
.QN(n1891) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n1305), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n1303), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n1301), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1300), .CK(clk), .RN(n3494),
.QN(n1888) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n1299), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n1297), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n1295), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n1293), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1292), .CK(clk), .RN(n3495),
.QN(n1892) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n1291), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n1289), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1288), .CK(clk), .RN(n3495),
.QN(n1893) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n1287), .CK(clk), .RN(n3474), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n1285), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(n1283), .CK(clk), .RN(n3520), .Q(
DmP_EXP_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(n1282), .CK(clk), .RN(n3513),
.QN(n1885) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(n1281), .CK(clk), .RN(n3512), .Q(
DmP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(n1279), .CK(clk), .RN(n3530), .Q(
DmP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(n1277), .CK(clk), .RN(n3524), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_28_ ( .D(n1275), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(n1273), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(n1272), .CK(clk), .RN(n3496),
.QN(n1894) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_30_ ( .D(n1271), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_31_ ( .D(n1269), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_32_ ( .D(n1267), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_33_ ( .D(n1265), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(n1263), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_35_ ( .D(n1261), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_36_ ( .D(n1259), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(n1258), .CK(clk), .RN(n3497),
.QN(n1889) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_37_ ( .D(n1257), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_38_ ( .D(n1255), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_39_ ( .D(n1253), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_40_ ( .D(n1251), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(n1250), .CK(clk), .RN(n3498),
.QN(n1881) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_41_ ( .D(n1249), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(n1246), .CK(clk), .RN(n3498),
.QN(n1882) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_43_ ( .D(n1245), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_44_ ( .D(n1243), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(n1242), .CK(clk), .RN(n3498),
.QN(n1883) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_45_ ( .D(n1241), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_46_ ( .D(n1239), .CK(clk), .RN(n3482), .Q(
DmP_EXP_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(n1238), .CK(clk), .RN(n3486),
.QN(n1890) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_47_ ( .D(n1237), .CK(clk), .RN(n3523), .Q(
DmP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(n1235), .CK(clk), .RN(n3509), .Q(
DmP_EXP_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(n1234), .CK(clk), .RN(n3488),
.QN(n1895) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_49_ ( .D(n1233), .CK(clk), .RN(n3516), .Q(
DmP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_50_ ( .D(n1231), .CK(clk), .RN(n3493), .Q(
DmP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_51_ ( .D(n1229), .CK(clk), .RN(n3516), .Q(
DmP_EXP_EWSW[51]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1221), .CK(clk), .RN(n3500), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1220), .CK(clk), .RN(n3495), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1219), .CK(clk), .RN(n3499), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1218), .CK(clk), .RN(n3500), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1217), .CK(clk), .RN(n3495), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1216), .CK(clk), .RN(n3499), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1215), .CK(clk), .RN(n3500),
.Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1214), .CK(clk), .RN(n3496), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1213), .CK(clk), .RN(n3499), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1212), .CK(clk), .RN(n3500), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1210), .CK(clk), .RN(n3509), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1209), .CK(clk), .RN(n3499), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1208), .CK(clk), .RN(n3500), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1207), .CK(clk), .RN(n3495), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1206), .CK(clk), .RN(n3499),
.Q(SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n1205), .CK(clk), .RN(n3500), .Q(
final_result_ieee[63]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n1185), .CK(clk), .RN(n3502),
.QN(n1855) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(n1161), .CK(clk), .RN(n3508),
.Q(LZD_output_NRM2_EW[5]), .QN(n3406) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(n1155), .CK(clk), .RN(n3514),
.Q(LZD_output_NRM2_EW[4]), .QN(n3403) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1151), .CK(clk), .RN(n3508),
.Q(LZD_output_NRM2_EW[1]), .QN(n3371) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(n1148), .CK(clk), .RN(n3508),
.Q(LZD_output_NRM2_EW[3]), .QN(n3394) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1141), .CK(clk), .RN(n3472), .QN(
n1875) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(n1137), .CK(clk), .RN(n3514),
.Q(LZD_output_NRM2_EW[2]), .QN(n3395) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1134), .CK(clk), .RN(n3476), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n1133), .CK(clk), .RN(n3475), .Q(
final_result_ieee[42]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1128), .CK(clk), .RN(n3497), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1127), .CK(clk), .RN(n3476), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1126), .CK(clk), .RN(n3475), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(n1125), .CK(clk), .RN(n3503), .Q(
final_result_ieee[36]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1124), .CK(clk), .RN(n3473), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1123), .CK(clk), .RN(n3505), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1121), .CK(clk), .RN(n3503), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(n1120), .CK(clk), .RN(n3472), .Q(
final_result_ieee[40]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1119), .CK(clk), .RN(n3474), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1118), .CK(clk), .RN(n3506), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1117), .CK(clk), .RN(n3472), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(n1116), .CK(clk), .RN(n3472), .Q(
final_result_ieee[38]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1115), .CK(clk), .RN(n3505), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1114), .CK(clk), .RN(n3505), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n1113), .CK(clk), .RN(n3507), .Q(
final_result_ieee[41]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1112), .CK(clk), .RN(n3471), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n1111), .CK(clk), .RN(n3469), .Q(
final_result_ieee[44]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1110), .CK(clk), .RN(n3507), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1109), .CK(clk), .RN(n3471), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1108), .CK(clk), .RN(n3469), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1107), .CK(clk), .RN(n3507), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(n1106), .CK(clk), .RN(n3471), .Q(
final_result_ieee[39]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n1105), .CK(clk), .RN(n3469), .Q(
final_result_ieee[43]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1104), .CK(clk), .RN(n3507), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n1103), .CK(clk), .RN(n3471), .Q(
final_result_ieee[46]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1102), .CK(clk), .RN(n3469), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(n1101), .CK(clk), .RN(n3514), .Q(
final_result_ieee[32]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1100), .CK(clk), .RN(n3508), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(n1099), .CK(clk), .RN(n3530), .Q(
final_result_ieee[34]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1098), .CK(clk), .RN(n3514), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1097), .CK(clk), .RN(n3508), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1096), .CK(clk), .RN(n3530), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1095), .CK(clk), .RN(n3514), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(n1094), .CK(clk), .RN(n3508), .Q(
final_result_ieee[37]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n1093), .CK(clk), .RN(n3530), .Q(
final_result_ieee[45]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1092), .CK(clk), .RN(n3514), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(n1091), .CK(clk), .RN(n3508), .Q(
final_result_ieee[33]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1090), .CK(clk), .RN(n3514), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n1089), .CK(clk), .RN(n3509), .Q(
final_result_ieee[48]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1088), .CK(clk), .RN(n3509), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1087), .CK(clk), .RN(n3509), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1086), .CK(clk), .RN(n3509), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1085), .CK(clk), .RN(n3509), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(n1084), .CK(clk), .RN(n3509), .Q(
final_result_ieee[35]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n1083), .CK(clk), .RN(n3509), .Q(
final_result_ieee[47]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1082), .CK(clk), .RN(n3509), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1081), .CK(clk), .RN(n3509), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n1080), .CK(clk), .RN(n3509), .Q(
final_result_ieee[49]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n1079), .CK(clk), .RN(n3509), .Q(
final_result_ieee[50]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n1078), .CK(clk), .RN(n3509), .Q(
final_result_ieee[51]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1075), .CK(clk), .RN(n3513), .Q(
DmP_mant_SFG_SWR[16]), .QN(n1989) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1074), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[17]), .QN(n1990) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1073), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[18]), .QN(n1992) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1072), .CK(clk), .RN(n3510), .Q(
DmP_mant_SFG_SWR[19]), .QN(n1993) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1071), .CK(clk), .RN(n3521), .Q(
DmP_mant_SFG_SWR[20]), .QN(n1994) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1070), .CK(clk), .RN(n3484), .Q(
DmP_mant_SFG_SWR[21]), .QN(n1971) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1059), .CK(clk), .RN(n3521), .Q(
DmP_mant_SFG_SWR[32]), .QN(n1973) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1058), .CK(clk), .RN(n3484), .Q(
DmP_mant_SFG_SWR[33]), .QN(n1974) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1057), .CK(clk), .RN(n3513), .Q(
DmP_mant_SFG_SWR[34]), .QN(n1975) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1056), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[35]), .QN(n1976) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1055), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[36]), .QN(n1977) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1053), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[38]), .QN(n1981) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1048), .CK(clk), .RN(n3521),
.QN(n1856) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1047), .CK(clk), .RN(n3484),
.QN(n1859) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1045), .CK(clk), .RN(n3510),
.QN(n1864) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1044), .CK(clk), .RN(n3484),
.QN(n1866) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1043), .CK(clk), .RN(n3510),
.QN(n1867) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1042), .CK(clk), .RN(n3513),
.QN(n1868) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1041), .CK(clk), .RN(n3510),
.QN(n1870) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1040), .CK(clk), .RN(n3521),
.QN(n1871) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1039), .CK(clk), .RN(n3484),
.QN(n1876) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1038), .CK(clk), .RN(n3513),
.QN(n1877) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1037), .CK(clk), .RN(n3512),
.QN(n1886) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(n1760), .CK(clk), .RN(n3473),
.Q(intDX_EWSW[55]), .QN(n3465) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(n1762), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[53]), .QN(n3464) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1135), .CK(clk), .RN(n3475), .Q(
Raw_mant_NRM_SWR[10]), .QN(n3460) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n1192), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[26]), .QN(n3454) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1742), .CK(clk), .RN(n3530),
.Q(intDY_EWSW[7]), .QN(n3453) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1719), .CK(clk), .RN(n3514),
.Q(intDY_EWSW[30]), .QN(n3452) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1748), .CK(clk), .RN(n3511),
.Q(intDY_EWSW[1]), .QN(n3449) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(n1705), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[44]), .QN(n3445) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(n1713), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[36]), .QN(n3442) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(n1715), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[34]), .QN(n3441) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(n1711), .CK(clk), .RN(n3497),
.Q(intDY_EWSW[38]), .QN(n3440) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(n1710), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[39]), .QN(n3438) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(n1712), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[37]), .QN(n3437) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1814), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[1]), .QN(n3433) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(n1688), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[61]), .QN(n3432) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_54_ ( .D(n1685), .CK(clk), .RN(n3517), .Q(
Data_array_SWR[34]), .QN(n3429) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n1684), .CK(clk), .RN(n3477), .Q(
Data_array_SWR[33]), .QN(n3428) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_51_ ( .D(n1682), .CK(clk), .RN(n3477), .Q(
Data_array_SWR[32]), .QN(n3427) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1733), .CK(clk), .RN(n3488),
.Q(intDY_EWSW[16]), .QN(n3425) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(n1701), .CK(clk), .RN(n3479),
.Q(intDY_EWSW[48]), .QN(n3422) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(n1717), .CK(clk), .RN(n3522),
.Q(intDY_EWSW[32]), .QN(n3421) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1721), .CK(clk), .RN(n3485),
.Q(intDY_EWSW[28]), .QN(n3420) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1745), .CK(clk), .RN(n3488),
.Q(intDY_EWSW[4]), .QN(n3413) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1728), .CK(clk), .RN(n3508),
.Q(intDY_EWSW[21]), .QN(n3411) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1736), .CK(clk), .RN(n3530),
.Q(intDY_EWSW[13]), .QN(n3410) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1739), .CK(clk), .RN(n3517),
.Q(intDY_EWSW[10]), .QN(n3408) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(n1756), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[59]), .QN(n3404) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1797), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[18]), .QN(n3402) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1789), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[26]), .QN(n3401) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1794), .CK(clk), .RN(n3469),
.Q(intDX_EWSW[21]), .QN(n3400) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1200), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[18]), .QN(n3399) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1199), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[19]), .QN(n3398) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(n1764), .CK(clk), .RN(n3472),
.Q(intDX_EWSW[51]), .QN(n3397) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n1183), .CK(clk), .RN(n3530), .Q(
Raw_mant_NRM_SWR[35]), .QN(n3396) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(n1758), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[57]), .QN(n3393) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1807), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[8]), .QN(n3392) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(n1766), .CK(clk), .RN(n3473),
.Q(intDX_EWSW[49]), .QN(n3391) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1798), .CK(clk), .RN(n3469),
.Q(intDX_EWSW[17]), .QN(n3390) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1790), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[25]), .QN(n3389) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(n1770), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[45]), .QN(n3388) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n1629), .CK(clk), .RN(n3479),
.Q(shift_value_SHT2_EWR[3]), .QN(n3386) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1802), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[13]), .QN(n3384) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1786), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[29]), .QN(n3383) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(n1774), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[41]), .QN(n3382) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(n1779), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[36]), .QN(n3381) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1793), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[22]), .QN(n3380) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1785), .CK(clk), .RN(n3472),
.Q(intDX_EWSW[30]), .QN(n3379) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1795), .CK(clk), .RN(n3471),
.Q(intDX_EWSW[20]), .QN(n3378) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1787), .CK(clk), .RN(n3472),
.Q(intDX_EWSW[28]), .QN(n3377) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(n1781), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[34]), .QN(n3375) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(n1773), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[42]), .QN(n3374) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(n1782), .CK(clk), .RN(n3472),
.Q(intDX_EWSW[33]), .QN(n3373) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1812), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[3]), .QN(n3372) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1804), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[11]), .QN(n3369) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1801), .CK(clk), .RN(n3471),
.Q(intDX_EWSW[14]), .QN(n3368) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1803), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[12]), .QN(n3367) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(n1769), .CK(clk), .RN(n3474),
.Q(intDX_EWSW[46]), .QN(n3366) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n1628), .CK(clk), .RN(n3501),
.Q(shift_value_SHT2_EWR[4]), .QN(n3363) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n1191), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[27]), .QN(n3362) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(n1761), .CK(clk), .RN(n3472),
.Q(intDX_EWSW[54]), .QN(n3358) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1718), .CK(clk), .RN(n3485),
.Q(intDY_EWSW[31]), .QN(n3348) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1734), .CK(clk), .RN(n3486),
.Q(intDY_EWSW[15]), .QN(n3346) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(n1714), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[35]), .QN(n3342) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(n1716), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[33]), .QN(n3341) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1720), .CK(clk), .RN(n3522),
.Q(intDY_EWSW[29]), .QN(n3339) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1744), .CK(clk), .RN(n3519),
.Q(intDY_EWSW[5]), .QN(n3334) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n3471), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n3332) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1146), .CK(clk), .RN(n3472), .Q(
Raw_mant_NRM_SWR[7]), .QN(n3330) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1153), .CK(clk), .RN(n3504), .Q(
Raw_mant_NRM_SWR[2]), .QN(n3328) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1796), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[19]), .QN(n3325) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1788), .CK(clk), .RN(n3473),
.Q(intDX_EWSW[27]), .QN(n3324) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(n1765), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[50]), .QN(n3322) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1792), .CK(clk), .RN(n3469),
.Q(intDX_EWSW[23]), .QN(n3321) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1784), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[31]), .QN(n3320) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(n1780), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[35]), .QN(n3319) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(n1772), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[43]), .QN(n3318) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1142), .CK(clk), .RN(n3505), .Q(
Raw_mant_NRM_SWR[9]), .QN(n3317) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1800), .CK(clk), .RN(n3471),
.Q(intDX_EWSW[15]), .QN(n3316) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(n1759), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[56]), .QN(n3314) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1131), .CK(clk), .RN(n3476), .Q(
Raw_mant_NRM_SWR[8]), .QN(n3311) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n1178), .CK(clk), .RN(n3472), .Q(
Raw_mant_NRM_SWR[40]), .QN(n3364) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n1176), .CK(clk), .RN(n3506), .Q(
Raw_mant_NRM_SWR[42]), .QN(n3365) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1144), .CK(clk), .RN(n3505), .Q(
Raw_mant_NRM_SWR[4]), .QN(n3323) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(n1687), .CK(clk), .RN(n3522),
.Q(intDY_EWSW[62]), .QN(n3448) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(n1704), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[45]), .QN(n3439) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1726), .CK(clk), .RN(n3508),
.Q(intDY_EWSW[23]), .QN(n3347) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(n1626), .CK(clk), .RN(n3492),
.Q(shift_value_SHT2_EWR[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1198), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1810), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n1171), .CK(clk), .RN(n3473), .Q(
Raw_mant_NRM_SWR[47]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1195), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[23]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n1189), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[29]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1194), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1159), .CK(clk), .RN(n3492), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1652), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_26_ ( .D(n1657), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1152), .CK(clk), .RN(n3474), .Q(
Raw_mant_NRM_SWR[3]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1655), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(n1777), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[38]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_29_ ( .D(n1660), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(n1771), .CK(clk), .RN(n3473),
.Q(intDX_EWSW[44]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(n1768), .CK(clk), .RN(n3474),
.Q(intDX_EWSW[47]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n1179), .CK(clk), .RN(n3472), .Q(
Raw_mant_NRM_SWR[39]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(n1778), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[37]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(n1763), .CK(clk), .RN(n3473),
.Q(intDX_EWSW[52]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(n1775), .CK(clk), .RN(n3474),
.Q(intDX_EWSW[40]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(n1767), .CK(clk), .RN(n3474),
.Q(intDX_EWSW[48]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1805), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[10]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n1186), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[32]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n1173), .CK(clk), .RN(n3506), .Q(
Raw_mant_NRM_SWR[45]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1808), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[7]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1799), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[16]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(n1783), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[32]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1813), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1791), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n1182), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[36]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1202), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n1190), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[28]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n1175), .CK(clk), .RN(n3473), .Q(
Raw_mant_NRM_SWR[43]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1203), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1654), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1149), .CK(clk), .RN(n3503), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1140), .CK(clk), .RN(n3506), .Q(
Raw_mant_NRM_SWR[6]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n1180), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[38]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n1169), .CK(clk), .RN(n3503), .Q(
Raw_mant_NRM_SWR[49]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1201), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_39_ ( .D(n1670), .CK(clk), .RN(n3496), .Q(
Data_array_SWR[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1815), .CK(clk), .RN(n3471),
.Q(intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(n1753), .CK(clk), .RN(n3520),
.Q(intDX_EWSW[62]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(n1754), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[61]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n1166), .CK(clk), .RN(n3480), .Q(
Raw_mant_NRM_SWR[52]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n1824), .CK(clk), .RN(
n3469), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1193), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[25]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n1177), .CK(clk), .RN(n3506), .Q(
Raw_mant_NRM_SWR[41]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1197), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_47_ ( .D(n1678), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[28]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_49_ ( .D(n1680), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[30]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_41_ ( .D(n1672), .CK(clk), .RN(n3519), .Q(
Data_array_SWR[23]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_40_ ( .D(n1671), .CK(clk), .RN(n3525), .Q(
Data_array_SWR[22]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_42_ ( .D(n1673), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[24]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n1630), .CK(clk), .RN(n3509),
.Q(shift_value_SHT2_EWR[2]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n1188), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[30]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n1181), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[37]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n1510), .CK(clk), .RN(n3483), .Q(
DMP_SFG[10]) );
DFFSX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n1978), .CK(clk), .SN(n3469), .Q(
n3463), .QN(n3528) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n1513), .CK(clk), .RN(n3483), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n1537), .CK(clk), .RN(n3524), .Q(
DMP_SFG[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(n1266), .CK(clk), .RN(n3496),
.Q(DmP_mant_SHT1_SW[32]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(n1284), .CK(clk), .RN(n3481),
.Q(DmP_mant_SHT1_SW[23]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1302), .CK(clk), .RN(n3494),
.Q(DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1310), .CK(clk), .RN(n3494),
.Q(DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(n1260), .CK(clk), .RN(n3497),
.Q(DmP_mant_SHT1_SW[35]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(n1270), .CK(clk), .RN(n3496),
.Q(DmP_mant_SHT1_SW[30]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(n1274), .CK(clk), .RN(n3496),
.Q(DmP_mant_SHT1_SW[28]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(n1278), .CK(clk), .RN(n3518),
.Q(DmP_mant_SHT1_SW[26]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1296), .CK(clk), .RN(n3495),
.Q(DmP_mant_SHT1_SW[17]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(n1752), .CK(clk), .RN(n3520),
.Q(intDX_EWSW[63]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n1507), .CK(clk), .RN(n3483), .Q(
DMP_SFG[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1519), .CK(clk), .RN(n3493), .Q(
DMP_SFG[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n1525), .CK(clk), .RN(n3504), .Q(
DMP_SFG[5]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1723), .CK(clk), .RN(n3514),
.Q(intDY_EWSW[26]), .QN(n3419) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1147), .CK(clk), .RN(n3503), .Q(
DmP_mant_SFG_SWR[5]) );
DFFSX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1873), .CK(clk), .SN(n3499), .Q(
n3467), .QN(n3526) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1290), .CK(clk), .RN(n3495),
.Q(DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(n1254), .CK(clk), .RN(n3497),
.Q(DmP_mant_SHT1_SW[38]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(n1264), .CK(clk), .RN(n3496),
.Q(DmP_mant_SHT1_SW[33]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(n1268), .CK(clk), .RN(n3496),
.Q(DmP_mant_SHT1_SW[31]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(n1276), .CK(clk), .RN(n3499),
.Q(DmP_mant_SHT1_SW[27]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1286), .CK(clk), .RN(n3474),
.Q(DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1294), .CK(clk), .RN(n3495),
.Q(DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1308), .CK(clk), .RN(n3494),
.Q(DmP_mant_SHT1_SW[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n1516), .CK(clk), .RN(n3515), .Q(
DMP_SFG[8]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_52_ ( .D(n1227), .CK(clk), .RN(n3499), .Q(
DmP_EXP_EWSW[52]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1298), .CK(clk), .RN(n3495),
.Q(DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(n1262), .CK(clk), .RN(n3497),
.Q(DmP_mant_SHT1_SW[34]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(n1280), .CK(clk), .RN(n3518),
.Q(DmP_mant_SHT1_SW[25]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1304), .CK(clk), .RN(n3494),
.Q(DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1312), .CK(clk), .RN(n3517), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1318), .CK(clk), .RN(n3484), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1324), .CK(clk), .RN(n3517), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1638), .CK(clk), .RN(n3494), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1326), .CK(clk), .RN(n3519), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1314), .CK(clk), .RN(n3521), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1635), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1636), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1637), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[6]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_57_ ( .D(n1551), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[57]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1328), .CK(clk), .RN(n3490), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1060), .CK(clk), .RN(n3510), .Q(
DmP_mant_SFG_SWR[31]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1061), .CK(clk), .RN(n3513), .Q(
DmP_mant_SFG_SWR[30]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1062), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[29]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1063), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[28]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1064), .CK(clk), .RN(n3521), .Q(
DmP_mant_SFG_SWR[27]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1065), .CK(clk), .RN(n3484), .Q(
DmP_mant_SFG_SWR[26]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1066), .CK(clk), .RN(n3510), .Q(
DmP_mant_SFG_SWR[25]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1067), .CK(clk), .RN(n3513), .Q(
DmP_mant_SFG_SWR[24]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1068), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n1540), .CK(clk), .RN(n3479), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1132), .CK(clk), .RN(n3476), .Q(
DmP_mant_SFG_SWR[8]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1139), .CK(clk), .RN(n3506), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1143), .CK(clk), .RN(n3473), .Q(
DmP_mant_SFG_SWR[7]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1145), .CK(clk), .RN(n3506), .Q(
DmP_mant_SFG_SWR[4]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1150), .CK(clk), .RN(n3474), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1154), .CK(clk), .RN(n3515), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1046), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[45]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1157), .CK(clk), .RN(n3493), .Q(
DmP_mant_SFG_SWR[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1160), .CK(clk), .RN(n3504), .Q(
DmP_mant_SFG_SWR[1]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_27_ ( .D(n1658), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n1167), .CK(clk), .RN(n3518), .Q(
Raw_mant_NRM_SWR[51]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_51_ ( .D(n1387), .CK(clk), .RN(n3520), .Q(
DMP_SFG[51]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_50_ ( .D(n1390), .CK(clk), .RN(n3520), .Q(
DMP_SFG[50]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_49_ ( .D(n1393), .CK(clk), .RN(n3520), .Q(
DMP_SFG[49]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_48_ ( .D(n1396), .CK(clk), .RN(n3491), .Q(
DMP_SFG[48]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_47_ ( .D(n1399), .CK(clk), .RN(n3523), .Q(
DMP_SFG[47]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_46_ ( .D(n1402), .CK(clk), .RN(n3491), .Q(
DMP_SFG[46]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_45_ ( .D(n1405), .CK(clk), .RN(n3523), .Q(
DMP_SFG[45]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_44_ ( .D(n1408), .CK(clk), .RN(n3490), .Q(
DMP_SFG[44]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_43_ ( .D(n1411), .CK(clk), .RN(n3490), .Q(
DMP_SFG[43]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_42_ ( .D(n1414), .CK(clk), .RN(n3490), .Q(
DMP_SFG[42]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_41_ ( .D(n1417), .CK(clk), .RN(n3490), .Q(
DMP_SFG[41]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_40_ ( .D(n1420), .CK(clk), .RN(n3489), .Q(
DMP_SFG[40]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_39_ ( .D(n1423), .CK(clk), .RN(n3489), .Q(
DMP_SFG[39]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n1468), .CK(clk), .RN(n3486), .Q(
DMP_SFG[24]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n1471), .CK(clk), .RN(n3485), .Q(
DMP_SFG[23]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n1474), .CK(clk), .RN(n3522), .Q(
DMP_SFG[22]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n1477), .CK(clk), .RN(n3486), .Q(
DMP_SFG[21]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n1480), .CK(clk), .RN(n3489), .Q(
DMP_SFG[20]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n1483), .CK(clk), .RN(n3490), .Q(
DMP_SFG[19]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n1486), .CK(clk), .RN(n3523), .Q(
DMP_SFG[18]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n1489), .CK(clk), .RN(n3484), .Q(
DMP_SFG[17]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n1492), .CK(clk), .RN(n3511), .Q(
DMP_SFG[16]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n1495), .CK(clk), .RN(n3521), .Q(
DMP_SFG[15]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n1498), .CK(clk), .RN(n3484), .Q(
DMP_SFG[14]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n1501), .CK(clk), .RN(n3510), .Q(
DMP_SFG[13]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n1504), .CK(clk), .RN(n3483), .Q(
DMP_SFG[12]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1632), .CK(clk), .RN(n3491), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1633), .CK(clk), .RN(n3525), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1631), .CK(clk), .RN(n3485), .Q(
Data_array_SWR[0]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n1184), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[34]), .QN(n1887) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1731), .CK(clk), .RN(n3491),
.Q(intDY_EWSW[18]), .QN(n3416) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1730), .CK(clk), .RN(n3530),
.Q(intDY_EWSW[19]), .QN(n3336) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n1170), .CK(clk), .RN(n3474), .Q(
Raw_mant_NRM_SWR[48]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1811), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[4]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(n1776), .CK(clk), .RN(n3474),
.Q(intDX_EWSW[39]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1806), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[9]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n1187), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[31]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1204), .CK(clk), .RN(n3500), .Q(
Raw_mant_NRM_SWR[14]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1648), .CK(clk), .RN(n3477), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1647), .CK(clk), .RN(n3523), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1650), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[10]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n1165), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[53]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1809), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[6]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1196), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[22]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_44_ ( .D(n1675), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[26]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_46_ ( .D(n1677), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_43_ ( .D(n1674), .CK(clk), .RN(n3488), .Q(
Data_array_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_50_ ( .D(n1681), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[31]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_48_ ( .D(n1679), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[29]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n1164), .CK(clk), .RN(n3492), .Q(
Raw_mant_NRM_SWR[54]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n1174), .CK(clk), .RN(n3472), .Q(
Raw_mant_NRM_SWR[44]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(n1248), .CK(clk), .RN(n3498),
.Q(DmP_mant_SHT1_SW[41]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(n1244), .CK(clk), .RN(n3498),
.Q(DmP_mant_SHT1_SW[43]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(n1240), .CK(clk), .RN(n3498),
.Q(DmP_mant_SHT1_SW[45]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(n1232), .CK(clk), .RN(n3519),
.Q(DmP_mant_SHT1_SW[49]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(n1236), .CK(clk), .RN(n3520),
.Q(DmP_mant_SHT1_SW[47]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(n1256), .CK(clk), .RN(n3497),
.Q(DmP_mant_SHT1_SW[37]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(n1252), .CK(clk), .RN(n3497),
.Q(DmP_mant_SHT1_SW[39]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n1531), .CK(clk), .RN(n3481), .Q(
DMP_SFG[3]), .QN(n3461) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(n1228), .CK(clk), .RN(n3487),
.Q(DmP_mant_SHT1_SW[51]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(n1230), .CK(clk), .RN(n3516),
.Q(DmP_mant_SHT1_SW[50]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1136), .CK(clk), .RN(n3475), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1130), .CK(clk), .RN(n3498), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1122), .CK(clk), .RN(n3506), .Q(
DmP_mant_SFG_SWR[12]), .QN(n1986) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1741), .CK(clk), .RN(n3530),
.Q(intDY_EWSW[8]), .QN(n3414) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1377), .CK(clk), .RN(n3514), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1372), .CK(clk), .RN(n3493), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1367), .CK(clk), .RN(n3504), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1362), .CK(clk), .RN(n3515), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1357), .CK(clk), .RN(n3482), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n1465), .CK(clk), .RN(n3522), .Q(
DMP_SFG[25]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n1462), .CK(clk), .RN(n3522), .Q(
DMP_SFG[26]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n1459), .CK(clk), .RN(n3522), .Q(
DMP_SFG[27]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n1456), .CK(clk), .RN(n3522), .Q(
DMP_SFG[28]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n1453), .CK(clk), .RN(n3487), .Q(
DMP_SFG[29]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n1450), .CK(clk), .RN(n3487), .Q(
DMP_SFG[30]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_31_ ( .D(n1447), .CK(clk), .RN(n3487), .Q(
DMP_SFG[31]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_32_ ( .D(n1444), .CK(clk), .RN(n3487), .Q(
DMP_SFG[32]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_33_ ( .D(n1441), .CK(clk), .RN(n3487), .Q(
DMP_SFG[33]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_34_ ( .D(n1438), .CK(clk), .RN(n3487), .Q(
DMP_SFG[34]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_35_ ( .D(n1435), .CK(clk), .RN(n3487), .Q(
DMP_SFG[35]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_36_ ( .D(n1432), .CK(clk), .RN(n3487), .Q(
DMP_SFG[36]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_37_ ( .D(n1429), .CK(clk), .RN(n3489), .Q(
DMP_SFG[37]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_38_ ( .D(n1426), .CK(clk), .RN(n3489), .Q(
DMP_SFG[38]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_57_ ( .D(n1222), .CK(clk), .RN(n3499), .Q(
DmP_EXP_EWSW[57]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(n1686), .CK(clk), .RN(n3525),
.Q(intDY_EWSW[63]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1077), .CK(clk), .RN(n3521), .Q(
DmP_mant_SFG_SWR[14]), .QN(n1987) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1051), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[40]), .QN(n1983) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1050), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[41]), .QN(n1984) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1076), .CK(clk), .RN(n3484), .Q(
DmP_mant_SFG_SWR[15]), .QN(n1988) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1069), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[22]), .QN(n1972) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1054), .CK(clk), .RN(n3510), .Q(
DmP_mant_SFG_SWR[37]), .QN(n1979) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1052), .CK(clk), .RN(n3513), .Q(
DmP_mant_SFG_SWR[39]), .QN(n1982) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1049), .CK(clk), .RN(n3521), .Q(
DmP_mant_SFG_SWR[42]), .QN(n1985) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1158), .CK(clk), .RN(n3508),
.Q(LZD_output_NRM2_EW[0]), .QN(n1995) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n1172), .CK(clk), .RN(n3505), .Q(
Raw_mant_NRM_SWR[46]), .QN(n3376) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1332), .CK(clk), .RN(n3482),
.Q(DMP_exp_NRM2_EW[10]), .QN(n3459) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1337), .CK(clk), .RN(n3492), .Q(
DMP_exp_NRM2_EW[9]), .QN(n3435) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1342), .CK(clk), .RN(n3480), .Q(
DMP_exp_NRM2_EW[8]), .QN(n3436) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1352), .CK(clk), .RN(n3493), .Q(
DMP_exp_NRM2_EW[6]), .QN(n3405) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1382), .CK(clk), .RN(n3530), .Q(
DMP_exp_NRM2_EW[0]), .QN(n3370) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1156), .CK(clk), .RN(n3515), .Q(
Raw_mant_NRM_SWR[0]), .QN(n3329) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1138), .CK(clk), .RN(n3525), .Q(
Raw_mant_NRM_SWR[11]), .QN(n3308) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1129), .CK(clk), .RN(n3476), .Q(
Raw_mant_NRM_SWR[12]), .QN(n3327) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1162), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[13]), .QN(n3315) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n1823), .CK(clk), .RN(
n3507), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n3431) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_52_ ( .D(n1556), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[52]), .QN(n3458) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(n1755), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[60]), .QN(n3385) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(n1757), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[58]), .QN(n3326) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(n1691), .CK(clk), .RN(n3499),
.Q(intDY_EWSW[58]), .QN(n3424) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(n1692), .CK(clk), .RN(n3501),
.Q(intDY_EWSW[57]), .QN(n3409) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(n1709), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[40]), .QN(n3443) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(n1694), .CK(clk), .RN(n3479),
.Q(intDY_EWSW[55]), .QN(n3309) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(n1696), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[53]), .QN(n3313) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(n1693), .CK(clk), .RN(n3497),
.Q(intDY_EWSW[56]), .QN(n3310) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(n1699), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[50]), .QN(n3447) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(n1689), .CK(clk), .RN(n3498),
.Q(intDY_EWSW[60]), .QN(n3423) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(n1690), .CK(clk), .RN(n3524),
.Q(intDY_EWSW[59]), .QN(n3340) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(n1698), .CK(clk), .RN(n3503),
.Q(intDY_EWSW[51]), .QN(n3350) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(n1702), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[47]), .QN(n3349) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(n1695), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[54]), .QN(n3312) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(n1700), .CK(clk), .RN(n3498),
.Q(intDY_EWSW[49]), .QN(n3430) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(n1707), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[42]), .QN(n3444) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(n1708), .CK(clk), .RN(n3492),
.Q(intDY_EWSW[41]), .QN(n3343) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1743), .CK(clk), .RN(n3487),
.Q(intDY_EWSW[6]), .QN(n3352) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1746), .CK(clk), .RN(n3488),
.Q(intDY_EWSW[3]), .QN(n3331) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1747), .CK(clk), .RN(n3520),
.Q(intDY_EWSW[2]), .QN(n3412) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1749), .CK(clk), .RN(n3520),
.Q(intDY_EWSW[0]), .QN(n3333) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(n1697), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[52]), .QN(n3434) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(n1703), .CK(clk), .RN(n3505),
.Q(intDY_EWSW[46]), .QN(n3446) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(n1706), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[43]), .QN(n3344) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_56_ ( .D(n1552), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[56]), .QN(n3359) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_55_ ( .D(n1553), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[55]), .QN(n3354) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_54_ ( .D(n1554), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[54]), .QN(n3355) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_53_ ( .D(n1555), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[53]), .QN(n3351) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_54_ ( .D(n1225), .CK(clk), .RN(n3499), .Q(
DmP_EXP_EWSW[54]), .QN(n3353) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_56_ ( .D(n1223), .CK(clk), .RN(n3500), .Q(
DmP_EXP_EWSW[56]), .QN(n3357) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_55_ ( .D(n1224), .CK(clk), .RN(n3530), .Q(
DmP_EXP_EWSW[55]), .QN(n3360) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_53_ ( .D(n1226), .CK(clk), .RN(n3499), .Q(
DmP_EXP_EWSW[53]), .QN(n3356) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1722), .CK(clk), .RN(n3525),
.Q(intDY_EWSW[27]), .QN(n3338) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1724), .CK(clk), .RN(n3517),
.Q(intDY_EWSW[25]), .QN(n3337) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1725), .CK(clk), .RN(n3514),
.Q(intDY_EWSW[24]), .QN(n3418) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1727), .CK(clk), .RN(n3500),
.Q(intDY_EWSW[22]), .QN(n3451) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1729), .CK(clk), .RN(n3489),
.Q(intDY_EWSW[20]), .QN(n3417) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1732), .CK(clk), .RN(n3523),
.Q(intDY_EWSW[17]), .QN(n3335) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1735), .CK(clk), .RN(n3491),
.Q(intDY_EWSW[14]), .QN(n3450) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1737), .CK(clk), .RN(n3484),
.Q(intDY_EWSW[12]), .QN(n3415) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1738), .CK(clk), .RN(n3523),
.Q(intDY_EWSW[11]), .QN(n3345) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1740), .CK(clk), .RN(n3510),
.Q(intDY_EWSW[9]), .QN(n3407) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1656), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_42_ ( .D(n1247), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[42]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1163), .CK(clk), .RN(n3477), .Q(
DmP_mant_SFG_SWR[13]), .QN(n1980) );
ADDFX1TS DP_OP_15J75_123_4372_U11 ( .A(n3371), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J75_123_4372_n11), .CO(DP_OP_15J75_123_4372_n10), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J75_123_4372_U10 ( .A(n3395), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J75_123_4372_n10), .CO(DP_OP_15J75_123_4372_n9), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J75_123_4372_U9 ( .A(n3394), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J75_123_4372_n9), .CO(DP_OP_15J75_123_4372_n8), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J75_123_4372_U8 ( .A(n3403), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J75_123_4372_n8), .CO(DP_OP_15J75_123_4372_n7), .S(
exp_rslt_NRM2_EW1[4]) );
ADDFX1TS DP_OP_15J75_123_4372_U7 ( .A(n3406), .B(DMP_exp_NRM2_EW[5]), .CI(
DP_OP_15J75_123_4372_n7), .CO(DP_OP_15J75_123_4372_n6), .S(
exp_rslt_NRM2_EW1[5]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1347), .CK(clk), .RN(n3518), .Q(
DMP_exp_NRM2_EW[7]), .QN(n3426) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n1168), .CK(clk), .RN(n3472), .Q(
Raw_mant_NRM_SWR[50]), .QN(n3387) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n1817), .CK(clk), .RN(n3469), .Q(
Shift_reg_FLAGS_7[1]), .QN(n1969) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1750), .CK(clk), .RN(n3521),
.Q(left_right_SHT2), .QN(n3361) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n1818), .CK(clk), .RN(n3469), .Q(
n1825), .QN(n3527) );
DFFSX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n1991), .CK(clk), .SN(n3471), .Q(
n3462), .QN(busy) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n1816), .CK(clk), .RN(n3507), .Q(
Shift_reg_FLAGS_7[0]), .QN(n1996) );
AOI222X1TS U1859 ( .A0(n2157), .A1(n3239), .B0(n3140), .B1(n3223), .C0(n3141), .C1(n3222), .Y(n3284) );
CMPR32X2TS U1860 ( .A(DMP_SFG[8]), .B(n3109), .C(n3108), .CO(n3101), .S(
n3110) );
CMPR32X2TS U1861 ( .A(n2981), .B(DMP_SFG[51]), .C(n2980), .CO(n2982), .S(
n2979) );
AOI222X1TS U1862 ( .A0(Raw_mant_NRM_SWR[41]), .A1(n2673), .B0(n2707), .B1(
n1922), .C0(n2644), .C1(DmP_mant_SHT1_SW[11]), .Y(n2578) );
AOI222X1TS U1863 ( .A0(Raw_mant_NRM_SWR[40]), .A1(n2673), .B0(n2707), .B1(
DmP_mant_SHT1_SW[13]), .C0(n2644), .C1(n1922), .Y(n2713) );
CMPR32X2TS U1864 ( .A(n2978), .B(DMP_SFG[50]), .C(n2977), .CO(n2980), .S(
n2976) );
CMPR32X2TS U1865 ( .A(n2975), .B(DMP_SFG[49]), .C(n2974), .CO(n2977), .S(
n2973) );
CMPR32X2TS U1866 ( .A(n2972), .B(DMP_SFG[48]), .C(n2971), .CO(n2974), .S(
n2001) );
CMPR32X2TS U1867 ( .A(n2969), .B(DMP_SFG[47]), .C(n2968), .CO(n2971), .S(
n2970) );
CMPR32X2TS U1868 ( .A(n2966), .B(DMP_SFG[46]), .C(n2965), .CO(n2968), .S(
n2967) );
CMPR32X2TS U1869 ( .A(n2963), .B(DMP_SFG[45]), .C(n2962), .CO(n2965), .S(
n2964) );
CMPR32X2TS U1870 ( .A(n2003), .B(DMP_SFG[44]), .C(n2002), .CO(n2962), .S(
n2004) );
CMPR32X2TS U1871 ( .A(n2960), .B(DMP_SFG[43]), .C(n2959), .CO(n2002), .S(
n2961) );
CMPR32X2TS U1872 ( .A(n2957), .B(DMP_SFG[42]), .C(n2956), .CO(n2959), .S(
n2958) );
CMPR32X2TS U1873 ( .A(n2954), .B(DMP_SFG[41]), .C(n2953), .CO(n2956), .S(
n2955) );
CMPR32X2TS U1874 ( .A(n2099), .B(DMP_SFG[17]), .C(n2098), .CO(n2898), .S(
n2100) );
CMPR32X2TS U1875 ( .A(n2096), .B(DMP_SFG[16]), .C(n2095), .CO(n2098), .S(
n2097) );
NOR2BX1TS U1876 ( .AN(n2762), .B(Raw_mant_NRM_SWR[34]), .Y(n2066) );
NOR2X1TS U1877 ( .A(n1857), .B(Raw_mant_NRM_SWR[35]), .Y(n2762) );
INVX4TS U1878 ( .A(n2554), .Y(n2570) );
OAI211XLTS U1879 ( .A0(n2596), .A1(n2570), .B0(n2595), .C0(n2594), .Y(n1656)
);
OAI211XLTS U1880 ( .A0(n2689), .A1(n2716), .B0(n2688), .C0(n2687), .Y(n1650)
);
OAI211XLTS U1881 ( .A0(n2629), .A1(n2716), .B0(n2564), .C0(n2563), .Y(n1637)
);
OAI211XLTS U1882 ( .A0(n2604), .A1(n2690), .B0(n2603), .C0(n2602), .Y(n1673)
);
OAI211XLTS U1883 ( .A0(n2682), .A1(n2716), .B0(n2660), .C0(n2659), .Y(n1670)
);
OAI211XLTS U1884 ( .A0(n2638), .A1(n2690), .B0(n2637), .C0(n2636), .Y(n1660)
);
OAI211XLTS U1885 ( .A0(n2725), .A1(n2670), .B0(n2552), .C0(n2551), .Y(n1682)
);
OAI211XLTS U1886 ( .A0(n2613), .A1(n2670), .B0(n2612), .C0(n2611), .Y(n1646)
);
OAI211XLTS U1887 ( .A0(n2617), .A1(n2570), .B0(n2598), .C0(n2597), .Y(n1665)
);
AOI2BB2XLTS U1888 ( .B0(Raw_mant_NRM_SWR[48]), .B1(n1826), .A0N(n2639),
.A1N(n2724), .Y(n2640) );
OAI211X1TS U1889 ( .A0(n2639), .A1(n2670), .B0(n2543), .C0(n2542), .Y(n1638)
);
AO22X1TS U1890 ( .A0(n3090), .A1(n2984), .B0(n3088), .B1(
Raw_mant_NRM_SWR[54]), .Y(n1164) );
INVX4TS U1891 ( .A(n1854), .Y(n1914) );
OR2X2TS U1892 ( .A(n2548), .B(n2777), .Y(n1854) );
NOR3X2TS U1893 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .C(n2058),
.Y(n2084) );
ADDFX1TS U1894 ( .A(n2009), .B(DMP_SFG[40]), .CI(n2008), .CO(n2953), .S(
n2010) );
NOR3X4TS U1895 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[7]), .C(n2055),
.Y(n2728) );
ADDFX1TS U1896 ( .A(n2951), .B(DMP_SFG[39]), .CI(n2950), .CO(n2008), .S(
n2952) );
NOR2X2TS U1897 ( .A(Raw_mant_NRM_SWR[10]), .B(n2027), .Y(n2727) );
ADDFX1TS U1898 ( .A(n2006), .B(DMP_SFG[38]), .CI(n2005), .CO(n2950), .S(
n2007) );
ADDFX1TS U1899 ( .A(n2948), .B(DMP_SFG[37]), .CI(n2947), .CO(n2005), .S(
n2949) );
ADDFX1TS U1900 ( .A(n2945), .B(DMP_SFG[36]), .CI(n2944), .CO(n2947), .S(
n2946) );
ADDFX1TS U1901 ( .A(n2942), .B(DMP_SFG[35]), .CI(n2941), .CO(n2944), .S(
n2943) );
ADDFX1TS U1902 ( .A(n2939), .B(DMP_SFG[34]), .CI(n2938), .CO(n2941), .S(
n2940) );
OAI211XLTS U1903 ( .A0(n1857), .A1(n3396), .B0(n2082), .C0(n2081), .Y(n2083)
);
ADDFX1TS U1904 ( .A(n2184), .B(DMP_SFG[33]), .CI(n2183), .CO(n2938), .S(
n2185) );
NOR2BX2TS U1905 ( .AN(n2053), .B(Raw_mant_NRM_SWR[15]), .Y(n2760) );
ADDFX1TS U1906 ( .A(n2936), .B(DMP_SFG[32]), .CI(n2935), .CO(n2183), .S(
n2937) );
ADDFX1TS U1907 ( .A(n2933), .B(DMP_SFG[31]), .CI(n2932), .CO(n2935), .S(
n2934) );
ADDFX1TS U1908 ( .A(n2930), .B(DMP_SFG[30]), .CI(n2929), .CO(n2932), .S(
n2931) );
INVX1TS U1909 ( .A(n2067), .Y(n2759) );
NAND2XLTS U1910 ( .A(n1857), .B(n1966), .Y(n1963) );
ADDFX1TS U1911 ( .A(n2927), .B(DMP_SFG[29]), .CI(n2926), .CO(n2929), .S(
n2928) );
ADDFX1TS U1912 ( .A(n2924), .B(DMP_SFG[28]), .CI(n2923), .CO(n2926), .S(
n2925) );
ADDFX1TS U1913 ( .A(n2920), .B(DMP_SFG[27]), .CI(n2919), .CO(n2923), .S(
n2922) );
ADDFX1TS U1914 ( .A(n2917), .B(DMP_SFG[26]), .CI(n2916), .CO(n2919), .S(
n2918) );
ADDFX1TS U1915 ( .A(n2133), .B(DMP_SFG[25]), .CI(n2132), .CO(n2916), .S(
n2134) );
ADDFX1TS U1916 ( .A(n2102), .B(DMP_SFG[24]), .CI(n2101), .CO(n2132), .S(
n2103) );
ADDFX1TS U1917 ( .A(n2914), .B(DMP_SFG[23]), .CI(n2913), .CO(n2101), .S(
n2915) );
ADDFX1TS U1918 ( .A(n2911), .B(DMP_SFG[22]), .CI(n2910), .CO(n2913), .S(
n2912) );
ADDFX1TS U1919 ( .A(n2908), .B(DMP_SFG[21]), .CI(n2907), .CO(n2910), .S(
n2909) );
ADDFX1TS U1920 ( .A(n2905), .B(DMP_SFG[20]), .CI(n2904), .CO(n2907), .S(
n2906) );
ADDFX1TS U1921 ( .A(n2902), .B(DMP_SFG[19]), .CI(n2901), .CO(n2904), .S(
n2903) );
ADDFX1TS U1922 ( .A(n2899), .B(DMP_SFG[18]), .CI(n2898), .CO(n2901), .S(
n2900) );
CLKINVX1TS U1923 ( .A(n2047), .Y(n2048) );
BUFX3TS U1924 ( .A(n2336), .Y(n2365) );
ADDFX1TS U1925 ( .A(n2896), .B(DMP_SFG[15]), .CI(n2895), .CO(n2095), .S(
n2897) );
ADDFX1TS U1926 ( .A(n2893), .B(DMP_SFG[14]), .CI(n2892), .CO(n2895), .S(
n2894) );
OAI211X1TS U1927 ( .A0(DMP_SFG[11]), .A1(n1896), .B0(DMP_SFG[10]), .C0(n3133), .Y(n2000) );
CLKINVX6TS U1928 ( .A(n2549), .Y(n2623) );
NOR2X2TS U1929 ( .A(Raw_mant_NRM_SWR[48]), .B(n2011), .Y(n2080) );
INVX3TS U1930 ( .A(n3117), .Y(n2142) );
CLKINVX6TS U1931 ( .A(n3232), .Y(n2127) );
CLKINVX6TS U1932 ( .A(n2128), .Y(n2159) );
NAND2X4TS U1933 ( .A(n1913), .B(n1996), .Y(n2852) );
INVX1TS U1934 ( .A(n2732), .Y(n2734) );
CLKBUFX2TS U1935 ( .A(Data_array_SWR[20]), .Y(n1935) );
CLKBUFX2TS U1936 ( .A(Data_array_SWR[18]), .Y(n1934) );
NOR2X6TS U1937 ( .A(shift_value_SHT2_EWR[2]), .B(n3386), .Y(n3080) );
OAI211X1TS U1938 ( .A0(n2709), .A1(n2724), .B0(n2676), .C0(n2675), .Y(n1676)
);
OAI211X1TS U1939 ( .A0(n2691), .A1(n2570), .B0(n2681), .C0(n2680), .Y(n1666)
);
OAI211X1TS U1940 ( .A0(n2608), .A1(n2690), .B0(n2600), .C0(n2599), .Y(n1671)
);
OAI211X1TS U1941 ( .A0(n2706), .A1(n2716), .B0(n2705), .C0(n2704), .Y(n1654)
);
OAI211X1TS U1942 ( .A0(n2698), .A1(n2716), .B0(n2697), .C0(n2696), .Y(n1641)
);
OAI211X1TS U1943 ( .A0(n2664), .A1(n2570), .B0(n2654), .C0(n2653), .Y(n1659)
);
OAI211X1TS U1944 ( .A0(n2634), .A1(n2690), .B0(n2633), .C0(n2632), .Y(n1681)
);
OAI211X1TS U1945 ( .A0(n2716), .A1(n2652), .B0(n2651), .C0(n2650), .Y(n1683)
);
OAI211X1TS U1946 ( .A0(n2702), .A1(n2570), .B0(n2701), .C0(n2700), .Y(n1663)
);
OAI211X1TS U1947 ( .A0(n2647), .A1(n2690), .B0(n2646), .C0(n2645), .Y(n1664)
);
OAI211X1TS U1948 ( .A0(n2607), .A1(n2670), .B0(n2606), .C0(n2605), .Y(n1651)
);
OAI211X1TS U1949 ( .A0(n2717), .A1(n2716), .B0(n2715), .C0(n2714), .Y(n1645)
);
OAI211X1TS U1950 ( .A0(n2586), .A1(n2690), .B0(n2585), .C0(n2584), .Y(n1677)
);
OAI211X1TS U1951 ( .A0(n2635), .A1(n2690), .B0(n2619), .C0(n2618), .Y(n1662)
);
OAI211X1TS U1952 ( .A0(n2699), .A1(n2716), .B0(n2666), .C0(n2665), .Y(n1661)
);
OAI211X1TS U1953 ( .A0(n2720), .A1(n2570), .B0(n2711), .C0(n2710), .Y(n1678)
);
OAI211X1TS U1954 ( .A0(n2686), .A1(n2716), .B0(n2663), .C0(n2662), .Y(n1648)
);
OAI211X1TS U1955 ( .A0(n2703), .A1(n2716), .B0(n2669), .C0(n2668), .Y(n1652)
);
OAI211X1TS U1956 ( .A0(n2685), .A1(n2716), .B0(n2684), .C0(n2683), .Y(n1672)
);
OAI211X1TS U1957 ( .A0(n2674), .A1(n2716), .B0(n2672), .C0(n2671), .Y(n1674)
);
OAI211X1TS U1958 ( .A0(n2626), .A1(n2670), .B0(n2625), .C0(n2624), .Y(n1655)
);
OAI211X1TS U1959 ( .A0(n2622), .A1(n2670), .B0(n2621), .C0(n2620), .Y(n1653)
);
OAI211X1TS U1960 ( .A0(n2694), .A1(n2724), .B0(n2693), .C0(n2692), .Y(n1668)
);
OAI211X1TS U1961 ( .A0(n2614), .A1(n2690), .B0(n2610), .C0(n2609), .Y(n1669)
);
OAI211X1TS U1962 ( .A0(n2658), .A1(n2570), .B0(n2657), .C0(n2656), .Y(n1657)
);
OAI211X1TS U1963 ( .A0(n2583), .A1(n2690), .B0(n2580), .C0(n2579), .Y(n1679)
);
OAI211X1TS U1964 ( .A0(n2601), .A1(n2690), .B0(n2572), .C0(n2571), .Y(n1675)
);
OAI211X1TS U1965 ( .A0(n2578), .A1(n2670), .B0(n2577), .C0(n2576), .Y(n1644)
);
OAI211X1TS U1966 ( .A0(n2589), .A1(n2716), .B0(n2566), .C0(n2565), .Y(n1647)
);
OAI211X1TS U1967 ( .A0(n2713), .A1(n2716), .B0(n2556), .C0(n2555), .Y(n1643)
);
BUFX4TS U1968 ( .A(n2570), .Y(n2724) );
OAI211X1TS U1969 ( .A0(n2642), .A1(n2716), .B0(n2561), .C0(n2560), .Y(n1634)
);
OAI211X1TS U1970 ( .A0(n2593), .A1(n2670), .B0(n2547), .C0(n2546), .Y(n1635)
);
OAI211X1TS U1971 ( .A0(n2539), .A1(n2670), .B0(n2538), .C0(n2537), .Y(n1632)
);
OAI211X1TS U1972 ( .A0(n2575), .A1(n2716), .B0(n2569), .C0(n2568), .Y(n1640)
);
INVX4TS U1973 ( .A(n1854), .Y(n1826) );
AND2X4TS U1974 ( .A(n2548), .B(n2667), .Y(n2559) );
OAI211X2TS U1975 ( .A0(Raw_mant_NRM_SWR[29]), .A1(n2766), .B0(n2062), .C0(
n2061), .Y(n2548) );
AOI222X1TS U1976 ( .A0(Raw_mant_NRM_SWR[28]), .A1(n2673), .B0(n2623), .B1(
DmP_mant_SHT1_SW[25]), .C0(n2644), .C1(n1921), .Y(n2655) );
AOI222X1TS U1977 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2673), .B0(n2623), .B1(
DmP_mant_SHT1_SW[16]), .C0(n2644), .C1(n1920), .Y(n2661) );
AOI222X1TS U1978 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n2631), .B0(n2707), .B1(
DmP_mant_SHT1_SW[9]), .C0(n2630), .C1(DmP_mant_SHT1_SW[8]), .Y(n2695)
);
AOI222X1TS U1979 ( .A0(Raw_mant_NRM_SWR[39]), .A1(n2673), .B0(n2677), .B1(
DmP_mant_SHT1_SW[14]), .C0(n2644), .C1(DmP_mant_SHT1_SW[13]), .Y(n2613) );
AOI222X1TS U1980 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n2631), .B0(n2707), .B1(
DmP_mant_SHT1_SW[3]), .C0(n2630), .C1(DmP_mant_SHT1_SW[2]), .Y(n2593)
);
AOI222X1TS U1981 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n2678), .B0(
Raw_mant_NRM_SWR[16]), .B1(n2667), .C0(n2623), .C1(n1918), .Y(n2691)
);
AOI222X1TS U1982 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[39]), .C0(n2644), .C1(DmP_mant_SHT1_SW[38]), .Y(n2608) );
AOI222X1TS U1983 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n2678), .B0(
Raw_mant_NRM_SWR[14]), .B1(n2087), .C0(n2623), .C1(
DmP_mant_SHT1_SW[38]), .Y(n2694) );
AOI222X1TS U1984 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n2673), .B0(
Raw_mant_NRM_SWR[6]), .B1(n2087), .C0(n2707), .C1(n1917), .Y(n2709) );
AOI222X1TS U1985 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[31]), .B1(n2708), .C0(n2623), .C1(
DmP_mant_SHT1_SW[22]), .Y(n2703) );
AOI222X1TS U1986 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n2667), .B0(n1950), .B1(
n2708), .C0(n2623), .C1(DmP_mant_SHT1_SW[20]), .Y(n2689) );
AOI222X1TS U1987 ( .A0(Raw_mant_NRM_SWR[46]), .A1(n2631), .B0(n2677), .B1(
n1924), .C0(n2630), .C1(DmP_mant_SHT1_SW[6]), .Y(n2629) );
AOI222X1TS U1988 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2678), .B0(n2707), .B1(
DmP_mant_SHT1_SW[30]), .C0(n2630), .C1(n1919), .Y(n2635) );
AOI222X1TS U1989 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[32]), .C0(n2630), .C1(DmP_mant_SHT1_SW[31]), .Y(n2647) );
AOI222X1TS U1990 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n2678), .B0(n2707), .B1(
DmP_mant_SHT1_SW[34]), .C0(n2630), .C1(DmP_mant_SHT1_SW[33]), .Y(n2679) );
AOI222X1TS U1991 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2631), .B0(n2707), .B1(
DmP_mant_SHT1_SW[6]), .C0(n2644), .C1(n1923), .Y(n2639) );
AOI222X1TS U1992 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n2678), .B0(
Raw_mant_NRM_SWR[23]), .B1(n2667), .C0(n2707), .C1(n1919), .Y(n2664)
);
AOI222X1TS U1993 ( .A0(Raw_mant_NRM_SWR[35]), .A1(n2673), .B0(
Raw_mant_NRM_SWR[34]), .B1(n2087), .C0(n2707), .C1(
DmP_mant_SHT1_SW[18]), .Y(n2686) );
AOI222X1TS U1994 ( .A0(Raw_mant_NRM_SWR[49]), .A1(n2631), .B0(n2677), .B1(
n1925), .C0(n2557), .C1(DmP_mant_SHT1_SW[3]), .Y(n2642) );
NAND3X1TS U1995 ( .A(n2084), .B(Raw_mant_NRM_SWR[1]), .C(n3328), .Y(n2736)
);
INVX1TS U1996 ( .A(n2728), .Y(n2729) );
AO21X1TS U1997 ( .A0(n3311), .A1(n3330), .B0(n2055), .Y(n2056) );
NAND3X1TS U1998 ( .A(n2020), .B(n2041), .C(n2746), .Y(n2021) );
NAND2X2TS U1999 ( .A(n2727), .B(n3317), .Y(n2055) );
NAND2X2TS U2000 ( .A(n2726), .B(n3308), .Y(n2027) );
NOR2X2TS U2001 ( .A(Raw_mant_NRM_SWR[12]), .B(n2771), .Y(n2726) );
OAI211X1TS U2002 ( .A0(n3362), .A1(n2072), .B0(n2071), .C0(n2737), .Y(n2073)
);
NAND2X2TS U2003 ( .A(n2070), .B(n3315), .Y(n2771) );
INVX1TS U2004 ( .A(n2043), .Y(n2060) );
NOR2X2TS U2005 ( .A(Raw_mant_NRM_SWR[16]), .B(n2043), .Y(n2053) );
NAND2X2TS U2006 ( .A(n2732), .B(n2733), .Y(n2043) );
CLKAND2X2TS U2007 ( .A(n1964), .B(n1965), .Y(n1966) );
NAND2BX2TS U2008 ( .AN(Raw_mant_NRM_SWR[21]), .B(n2014), .Y(n2067) );
NOR3BX2TS U2009 ( .AN(n2024), .B(Raw_mant_NRM_SWR[23]), .C(
Raw_mant_NRM_SWR[22]), .Y(n2014) );
NAND2XLTS U2010 ( .A(n2024), .B(Raw_mant_NRM_SWR[22]), .Y(n2768) );
NOR2BX2TS U2011 ( .AN(n2046), .B(Raw_mant_NRM_SWR[24]), .Y(n2024) );
NAND2XLTS U2012 ( .A(Raw_mant_NRM_SWR[25]), .B(n2019), .Y(n2746) );
OR2X4TS U2013 ( .A(n2884), .B(n2876), .Y(n2146) );
NOR2X2TS U2014 ( .A(Raw_mant_NRM_SWR[26]), .B(n2026), .Y(n2019) );
INVX1TS U2015 ( .A(n2748), .Y(n2065) );
NAND2BX2TS U2016 ( .AN(Raw_mant_NRM_SWR[30]), .B(n2025), .Y(n2748) );
NOR3X2TS U2017 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[31]), .C(
n2064), .Y(n2025) );
INVX1TS U2018 ( .A(n2064), .Y(n2761) );
NAND2BX2TS U2019 ( .AN(n1950), .B(n2066), .Y(n2064) );
BUFX4TS U2020 ( .A(n2384), .Y(n1827) );
OR2X2TS U2021 ( .A(Raw_mant_NRM_SWR[36]), .B(n2047), .Y(n1857) );
NAND2X1TS U2022 ( .A(n2013), .B(n2745), .Y(n2047) );
NAND2X2TS U2023 ( .A(n2873), .B(n2326), .Y(n2336) );
OAI32X4TS U2024 ( .A0(n3128), .A1(n3127), .A2(n3126), .B0(n3232), .B1(n3128),
.Y(n3155) );
ADDFX1TS U2025 ( .A(DMP_SFG[13]), .B(n2890), .CI(n2889), .CO(n2892), .S(
n2891) );
ADDFX1TS U2026 ( .A(DMP_SFG[12]), .B(n2887), .CI(n2886), .CO(n2889), .S(
n2888) );
NOR2X6TS U2027 ( .A(left_right_SHT2), .B(n2127), .Y(n2156) );
INVX4TS U2028 ( .A(n2648), .Y(n2644) );
CLKINVX3TS U2029 ( .A(n3201), .Y(n2168) );
CLKBUFX2TS U2030 ( .A(Data_array_SWR[19]), .Y(n1936) );
INVX6TS U2031 ( .A(rst), .Y(n3530) );
NOR2BX2TS U2032 ( .AN(n2760), .B(Raw_mant_NRM_SWR[14]), .Y(n2070) );
NAND2X2TS U2033 ( .A(n2728), .B(n2731), .Y(n2058) );
AOI2BB2XLTS U2034 ( .B0(n3075), .B1(DmP_mant_SFG_SWR[25]), .A0N(
DmP_mant_SFG_SWR[25]), .A1N(n3076), .Y(n2914) );
AOI2BB2XLTS U2035 ( .B0(n3075), .B1(DmP_mant_SFG_SWR[28]), .A0N(
DmP_mant_SFG_SWR[28]), .A1N(n3076), .Y(n2917) );
NOR3X1TS U2036 ( .A(Raw_mant_NRM_SWR[44]), .B(Raw_mant_NRM_SWR[46]), .C(
Raw_mant_NRM_SWR[45]), .Y(n2023) );
AOI222X1TS U2037 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n2708), .B0(n2707), .B1(
DmP_mant_SHT1_SW[49]), .C0(n2644), .C1(n1916), .Y(n2634) );
AOI222X1TS U2038 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n2708), .B0(n2677), .B1(
DmP_mant_SHT1_SW[47]), .C0(n2644), .C1(n1917), .Y(n2583) );
AOI222X1TS U2039 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n2708), .B0(n2707), .B1(
DmP_mant_SHT1_SW[45]), .C0(n2644), .C1(n1928), .Y(n2586) );
AOI2BB2XLTS U2040 ( .B0(n1999), .B1(DmP_mant_SFG_SWR[30]), .A0N(
DmP_mant_SFG_SWR[30]), .A1N(n3075), .Y(n2924) );
AOI222X1TS U2041 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[43]), .C0(n2644), .C1(n1929), .Y(n2601) );
AOI222X1TS U2042 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n2678), .B0(n2707), .B1(
DmP_mant_SHT1_SW[41]), .C0(n2644), .C1(n1930), .Y(n2604) );
AOI222X1TS U2043 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n2708), .B0(
Raw_mant_NRM_SWR[4]), .B1(n2087), .C0(n2677), .C1(n1916), .Y(n2720) );
AOI222X1TS U2044 ( .A0(Raw_mant_NRM_SWR[28]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[29]), .B1(n2708), .C0(n2677), .C1(n1921), .Y(n2706)
);
AOI222X1TS U2045 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[28]), .C0(n2630), .C1(DmP_mant_SHT1_SW[27]), .Y(n2638) );
AOI2BB2XLTS U2046 ( .B0(n1999), .B1(DmP_mant_SFG_SWR[24]), .A0N(
DmP_mant_SFG_SWR[24]), .A1N(n3075), .Y(n2911) );
AOI2BB2XLTS U2047 ( .B0(n1999), .B1(DmP_mant_SFG_SWR[27]), .A0N(
DmP_mant_SFG_SWR[27]), .A1N(n3075), .Y(n2133) );
AOI222X1TS U2048 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n2678), .B0(
Raw_mant_NRM_SWR[2]), .B1(n2667), .C0(DmP_mant_SHT1_SW[50]), .C1(n2707), .Y(n2725) );
AOI222X1TS U2049 ( .A0(Raw_mant_NRM_SWR[41]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[42]), .B1(n2708), .C0(n2677), .C1(
DmP_mant_SHT1_SW[11]), .Y(n2698) );
AOI222X1TS U2050 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[38]), .B1(n2708), .C0(n2623), .C1(n1920), .Y(n2717)
);
AOI222X1TS U2051 ( .A0(Raw_mant_NRM_SWR[34]), .A1(n2673), .B0(n2707), .B1(
n1938), .C0(n2630), .C1(DmP_mant_SHT1_SW[18]), .Y(n2607) );
AOI222X1TS U2052 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n2673), .B0(n2677), .B1(
n1937), .C0(n2630), .C1(DmP_mant_SHT1_SW[20]), .Y(n2622) );
AOI222X1TS U2053 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n2673), .B0(n2677), .B1(
DmP_mant_SHT1_SW[23]), .C0(n2630), .C1(DmP_mant_SHT1_SW[22]), .Y(n2626) );
AOI222X1TS U2054 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[26]), .B1(n2708), .C0(n2677), .C1(
DmP_mant_SHT1_SW[27]), .Y(n2658) );
AOI222X1TS U2055 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n2087), .B0(
Raw_mant_NRM_SWR[22]), .B1(n2708), .C0(n2707), .C1(
DmP_mant_SHT1_SW[31]), .Y(n2699) );
AOI222X1TS U2056 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n2087), .B0(
Raw_mant_NRM_SWR[20]), .B1(n2708), .C0(n2677), .C1(
DmP_mant_SHT1_SW[33]), .Y(n2702) );
CLKINVX6TS U2057 ( .A(n2810), .Y(n2719) );
NAND2BXLTS U2058 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n2221) );
NAND2X1TS U2059 ( .A(n2023), .B(n2080), .Y(n2012) );
NAND2BXLTS U2060 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2269) );
AO22XLTS U2061 ( .A0(n3336), .A1(intDX_EWSW[19]), .B0(n3416), .B1(
intDX_EWSW[18]), .Y(n1872) );
NOR2BX2TS U2062 ( .AN(n2075), .B(Raw_mant_NRM_SWR[42]), .Y(n2015) );
NAND2BXLTS U2063 ( .AN(intDY_EWSW[62]), .B(intDX_EWSW[62]), .Y(n2266) );
NAND2BXLTS U2064 ( .AN(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n2264) );
AOI31XLTS U2065 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n2733), .A2(n3399), .B0(
n2083), .Y(n2085) );
AOI211X1TS U2066 ( .A0(shift_value_SHT2_EWR[5]), .A1(n1898), .B0(n3047),
.C0(n3046), .Y(n3244) );
AOI211X1TS U2067 ( .A0(shift_value_SHT2_EWR[5]), .A1(n1899), .B0(n3063),
.C0(n3062), .Y(n3214) );
AO21XLTS U2068 ( .A0(n1957), .A1(n3125), .B0(n3104), .Y(n1833) );
OAI31X1TS U2069 ( .A0(n2765), .A1(n2764), .A2(Raw_mant_NRM_SWR[48]), .B0(
n2763), .Y(n2767) );
NAND4X1TS U2070 ( .A(n2052), .B(n2051), .C(n2050), .D(n2049), .Y(n2756) );
OAI21XLTS U2071 ( .A0(Raw_mant_NRM_SWR[35]), .A1(Raw_mant_NRM_SWR[36]), .B0(
n2048), .Y(n2049) );
AOI2BB2XLTS U2072 ( .B0(n3075), .B1(DmP_mant_SFG_SWR[31]), .A0N(
DmP_mant_SFG_SWR[31]), .A1N(n3076), .Y(n2927) );
AOI222X1TS U2073 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n2673), .B0(n2623), .B1(
DmP_mant_SHT1_SW[26]), .C0(n2630), .C1(DmP_mant_SHT1_SW[25]), .Y(n2596) );
AOI2BB2XLTS U2074 ( .B0(n3076), .B1(DmP_mant_SFG_SWR[29]), .A0N(
DmP_mant_SFG_SWR[29]), .A1N(n1999), .Y(n2920) );
AOI2BB2XLTS U2075 ( .B0(n3076), .B1(DmP_mant_SFG_SWR[23]), .A0N(
DmP_mant_SFG_SWR[23]), .A1N(n1999), .Y(n2908) );
AOI222X1TS U2076 ( .A0(n3036), .A1(DMP_SFG[1]), .B0(n3036), .B1(n3035), .C0(
DMP_SFG[1]), .C1(n3035), .Y(n3064) );
BUFX4TS U2077 ( .A(n2793), .Y(n2804) );
AOI2BB2XLTS U2078 ( .B0(n3076), .B1(DmP_mant_SFG_SWR[26]), .A0N(
DmP_mant_SFG_SWR[26]), .A1N(n1999), .Y(n2102) );
OAI211X1TS U2079 ( .A0(n1858), .A1(n3197), .B0(n3196), .C0(n3195), .Y(n3272)
);
OAI211X1TS U2080 ( .A0(n1858), .A1(n3242), .B0(n3193), .C0(n3192), .Y(n3264)
);
OAI211X1TS U2081 ( .A0(n3153), .A1(n3197), .B0(n3152), .C0(n3151), .Y(n3271)
);
OAI211X1TS U2082 ( .A0(n3153), .A1(n3242), .B0(n3147), .C0(n3146), .Y(n3265)
);
OAI211X1TS U2083 ( .A0(n1897), .A1(n3197), .B0(n3144), .C0(n3143), .Y(n3269)
);
OAI211X1TS U2084 ( .A0(n1897), .A1(n3242), .B0(n3139), .C0(n3138), .Y(n3267)
);
AO22XLTS U2085 ( .A0(n2760), .A1(Raw_mant_NRM_SWR[14]), .B0(
Raw_mant_NRM_SWR[20]), .B1(n2759), .Y(n2775) );
NAND4XLTS U2086 ( .A(n2086), .B(n2769), .C(n2031), .D(n2050), .Y(n2032) );
NAND4BXLTS U2087 ( .AN(n2738), .B(n2737), .C(n2736), .D(n2735), .Y(n2739) );
OAI31X1TS U2088 ( .A0(Raw_mant_NRM_SWR[16]), .A1(Raw_mant_NRM_SWR[14]), .A2(
n2734), .B0(n2733), .Y(n2735) );
BUFX4TS U2089 ( .A(n3462), .Y(n2859) );
BUFX6TS U2090 ( .A(n1933), .Y(n2386) );
AOI222X1TS U2091 ( .A0(Raw_mant_NRM_SWR[43]), .A1(n2673), .B0(n2707), .B1(
DmP_mant_SHT1_SW[10]), .C0(n2630), .C1(DmP_mant_SHT1_SW[9]), .Y(n2575)
);
AOI222X1TS U2092 ( .A0(Raw_mant_NRM_SWR[36]), .A1(n2673), .B0(n2623), .B1(
DmP_mant_SHT1_SW[17]), .C0(n2630), .C1(DmP_mant_SHT1_SW[16]), .Y(n2589) );
AOI222X1TS U2093 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[35]), .C0(n2630), .C1(DmP_mant_SHT1_SW[34]), .Y(n2617) );
NAND3XLTS U2094 ( .A(Raw_mant_NRM_SWR[0]), .B(n2777), .C(n2549), .Y(n2652)
);
AO22XLTS U2095 ( .A0(n2808), .A1(Data_Y[63]), .B0(n2807), .B1(intDY_EWSW[63]), .Y(n1686) );
AO22XLTS U2096 ( .A0(n3297), .A1(DMP_SHT2_EWSW[38]), .B0(n2861), .B1(
DMP_SFG[38]), .Y(n1426) );
AO22XLTS U2097 ( .A0(n3292), .A1(DMP_SHT2_EWSW[37]), .B0(n2861), .B1(
DMP_SFG[37]), .Y(n1429) );
AO22XLTS U2098 ( .A0(n2858), .A1(DMP_SHT2_EWSW[36]), .B0(n2857), .B1(
DMP_SFG[36]), .Y(n1432) );
AO22XLTS U2099 ( .A0(n3297), .A1(DMP_SHT2_EWSW[35]), .B0(n2857), .B1(
DMP_SFG[35]), .Y(n1435) );
AO22XLTS U2100 ( .A0(n3292), .A1(DMP_SHT2_EWSW[34]), .B0(n2857), .B1(
DMP_SFG[34]), .Y(n1438) );
AO22XLTS U2101 ( .A0(n2858), .A1(DMP_SHT2_EWSW[33]), .B0(n2857), .B1(
DMP_SFG[33]), .Y(n1441) );
AO22XLTS U2102 ( .A0(n3297), .A1(DMP_SHT2_EWSW[32]), .B0(n2857), .B1(
DMP_SFG[32]), .Y(n1444) );
AO22XLTS U2103 ( .A0(n3292), .A1(DMP_SHT2_EWSW[31]), .B0(n2857), .B1(
DMP_SFG[31]), .Y(n1447) );
AO22XLTS U2104 ( .A0(n2858), .A1(DMP_SHT2_EWSW[30]), .B0(n2857), .B1(
DMP_SFG[30]), .Y(n1450) );
AO22XLTS U2105 ( .A0(n3292), .A1(DMP_SHT2_EWSW[29]), .B0(n2857), .B1(
DMP_SFG[29]), .Y(n1453) );
AO22XLTS U2106 ( .A0(n3297), .A1(DMP_SHT2_EWSW[28]), .B0(n2857), .B1(
DMP_SFG[28]), .Y(n1456) );
AO22XLTS U2107 ( .A0(n2858), .A1(DMP_SHT2_EWSW[27]), .B0(n2857), .B1(
DMP_SFG[27]), .Y(n1459) );
AO22XLTS U2108 ( .A0(n3297), .A1(DMP_SHT2_EWSW[26]), .B0(n2857), .B1(
DMP_SFG[26]), .Y(n1462) );
AO22XLTS U2109 ( .A0(n3292), .A1(DMP_SHT2_EWSW[25]), .B0(n2857), .B1(
DMP_SFG[25]), .Y(n1465) );
AO22XLTS U2110 ( .A0(n3261), .A1(n3154), .B0(n3130), .B1(
DmP_mant_SFG_SWR[11]), .Y(n1130) );
AO22XLTS U2111 ( .A0(n3261), .A1(n3113), .B0(n3130), .B1(
DmP_mant_SFG_SWR[10]), .Y(n1136) );
AO22XLTS U2112 ( .A0(n2880), .A1(DmP_EXP_EWSW[50]), .B0(n2877), .B1(
DmP_mant_SHT1_SW[50]), .Y(n1230) );
AO22XLTS U2113 ( .A0(n2880), .A1(DmP_EXP_EWSW[51]), .B0(n2877), .B1(
DmP_mant_SHT1_SW[51]), .Y(n1228) );
AO22XLTS U2114 ( .A0(n2880), .A1(DmP_EXP_EWSW[39]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[39]), .Y(n1252) );
AO22XLTS U2115 ( .A0(n2880), .A1(DmP_EXP_EWSW[37]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[37]), .Y(n1256) );
AO22XLTS U2116 ( .A0(n2880), .A1(DmP_EXP_EWSW[47]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[47]), .Y(n1236) );
AO22XLTS U2117 ( .A0(n2880), .A1(DmP_EXP_EWSW[49]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[49]), .Y(n1232) );
AO22XLTS U2118 ( .A0(n2880), .A1(DmP_EXP_EWSW[45]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[45]), .Y(n1240) );
AO22XLTS U2119 ( .A0(n2880), .A1(DmP_EXP_EWSW[43]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[43]), .Y(n1244) );
AO22XLTS U2120 ( .A0(n2880), .A1(DmP_EXP_EWSW[41]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[41]), .Y(n1248) );
AO22XLTS U2121 ( .A0(n1825), .A1(n2958), .B0(n3088), .B1(
Raw_mant_NRM_SWR[44]), .Y(n1174) );
AOI2BB2XLTS U2122 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n1914), .A0N(n2634), .A1N(
n2570), .Y(n2579) );
AOI2BB2XLTS U2123 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n1914), .A0N(n2649), .A1N(
n2724), .Y(n2632) );
AOI2BB2XLTS U2124 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[43]), .A0N(n2685),
.A1N(n2670), .Y(n2671) );
AOI2BB2XLTS U2125 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n1914), .A0N(n2583), .A1N(
n2724), .Y(n2584) );
AOI2BB2XLTS U2126 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n1914), .A0N(n2586), .A1N(
n2570), .Y(n2571) );
AO22XLTS U2127 ( .A0(n3090), .A1(n2906), .B0(n2921), .B1(
Raw_mant_NRM_SWR[22]), .Y(n1196) );
AO22XLTS U2128 ( .A0(n2805), .A1(Data_X[6]), .B0(n2797), .B1(intDX_EWSW[6]),
.Y(n1809) );
AO22XLTS U2129 ( .A0(n1825), .A1(n2979), .B0(n3088), .B1(
Raw_mant_NRM_SWR[53]), .Y(n1165) );
AOI2BB2XLTS U2130 ( .B0(n2721), .B1(n1938), .A0N(n2686), .A1N(n2719), .Y(
n2687) );
AOI2BB2XLTS U2131 ( .B0(n2718), .B1(DmP_mant_SHT1_SW[14]), .A0N(n2717),
.A1N(n2719), .Y(n2565) );
AOI2BB2XLTS U2132 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[17]), .A0N(n2661),
.A1N(n2719), .Y(n2662) );
AO22XLTS U2133 ( .A0(n1825), .A1(n2928), .B0(n3088), .B1(
Raw_mant_NRM_SWR[31]), .Y(n1187) );
AO22XLTS U2134 ( .A0(n2805), .A1(Data_X[9]), .B0(n2797), .B1(intDX_EWSW[9]),
.Y(n1806) );
AO22XLTS U2135 ( .A0(n2793), .A1(Data_X[39]), .B0(n2795), .B1(intDX_EWSW[39]), .Y(n1776) );
AO22XLTS U2136 ( .A0(n2805), .A1(Data_X[4]), .B0(n2803), .B1(intDX_EWSW[4]),
.Y(n1811) );
AO22XLTS U2137 ( .A0(n3090), .A1(n2967), .B0(n3088), .B1(
Raw_mant_NRM_SWR[48]), .Y(n1170) );
AOI2BB2XLTS U2138 ( .B0(n2718), .B1(DmP_mant_SHT1_SW[23]), .A0N(n2706),
.A1N(n2719), .Y(n2594) );
AO22XLTS U2139 ( .A0(n2858), .A1(DMP_SHT2_EWSW[12]), .B0(n2864), .B1(
DMP_SFG[12]), .Y(n1504) );
AO22XLTS U2140 ( .A0(n3297), .A1(DMP_SHT2_EWSW[13]), .B0(n2864), .B1(
DMP_SFG[13]), .Y(n1501) );
AO22XLTS U2141 ( .A0(n3297), .A1(DMP_SHT2_EWSW[14]), .B0(n2861), .B1(
DMP_SFG[14]), .Y(n1498) );
AO22XLTS U2142 ( .A0(n3292), .A1(DMP_SHT2_EWSW[15]), .B0(n2857), .B1(
DMP_SFG[15]), .Y(n1495) );
AO22XLTS U2143 ( .A0(n3292), .A1(DMP_SHT2_EWSW[16]), .B0(n3307), .B1(
DMP_SFG[16]), .Y(n1492) );
AO22XLTS U2144 ( .A0(n2858), .A1(DMP_SHT2_EWSW[17]), .B0(n3298), .B1(
DMP_SFG[17]), .Y(n1489) );
AO22XLTS U2145 ( .A0(n3297), .A1(DMP_SHT2_EWSW[18]), .B0(n2852), .B1(
DMP_SFG[18]), .Y(n1486) );
AO22XLTS U2146 ( .A0(n3292), .A1(DMP_SHT2_EWSW[19]), .B0(n2852), .B1(
DMP_SFG[19]), .Y(n1483) );
AO22XLTS U2147 ( .A0(n2858), .A1(DMP_SHT2_EWSW[20]), .B0(n2852), .B1(
DMP_SFG[20]), .Y(n1480) );
AO22XLTS U2148 ( .A0(n3297), .A1(DMP_SHT2_EWSW[21]), .B0(n2861), .B1(
DMP_SFG[21]), .Y(n1477) );
AO22XLTS U2149 ( .A0(n3292), .A1(DMP_SHT2_EWSW[22]), .B0(n2857), .B1(
DMP_SFG[22]), .Y(n1474) );
AO22XLTS U2150 ( .A0(n2858), .A1(DMP_SHT2_EWSW[23]), .B0(n3130), .B1(
DMP_SFG[23]), .Y(n1471) );
AO22XLTS U2151 ( .A0(n3297), .A1(DMP_SHT2_EWSW[24]), .B0(n2861), .B1(
DMP_SFG[24]), .Y(n1468) );
AO22XLTS U2152 ( .A0(n3306), .A1(DMP_SHT2_EWSW[39]), .B0(n2861), .B1(
DMP_SFG[39]), .Y(n1423) );
AO22XLTS U2153 ( .A0(n3306), .A1(DMP_SHT2_EWSW[40]), .B0(n2861), .B1(
DMP_SFG[40]), .Y(n1420) );
AO22XLTS U2154 ( .A0(n3306), .A1(DMP_SHT2_EWSW[41]), .B0(n2861), .B1(
DMP_SFG[41]), .Y(n1417) );
AO22XLTS U2155 ( .A0(n3306), .A1(DMP_SHT2_EWSW[42]), .B0(n2861), .B1(
DMP_SFG[42]), .Y(n1414) );
AO22XLTS U2156 ( .A0(n3306), .A1(DMP_SHT2_EWSW[43]), .B0(n2861), .B1(
DMP_SFG[43]), .Y(n1411) );
AO22XLTS U2157 ( .A0(n3306), .A1(DMP_SHT2_EWSW[44]), .B0(n2861), .B1(
DMP_SFG[44]), .Y(n1408) );
AO22XLTS U2158 ( .A0(n3306), .A1(DMP_SHT2_EWSW[45]), .B0(n2861), .B1(
DMP_SFG[45]), .Y(n1405) );
AO22XLTS U2159 ( .A0(n3306), .A1(DMP_SHT2_EWSW[46]), .B0(n2861), .B1(
DMP_SFG[46]), .Y(n1402) );
AO22XLTS U2160 ( .A0(n3306), .A1(DMP_SHT2_EWSW[47]), .B0(n2861), .B1(
DMP_SFG[47]), .Y(n1399) );
AO22XLTS U2161 ( .A0(n3306), .A1(DMP_SHT2_EWSW[48]), .B0(n3130), .B1(
DMP_SFG[48]), .Y(n1396) );
AO22XLTS U2162 ( .A0(n3306), .A1(DMP_SHT2_EWSW[49]), .B0(n2864), .B1(
DMP_SFG[49]), .Y(n1393) );
AO22XLTS U2163 ( .A0(n3306), .A1(DMP_SHT2_EWSW[50]), .B0(n3295), .B1(
DMP_SFG[50]), .Y(n1390) );
AO22XLTS U2164 ( .A0(n3306), .A1(DMP_SHT2_EWSW[51]), .B0(n2852), .B1(
DMP_SFG[51]), .Y(n1387) );
AO22XLTS U2165 ( .A0(n3024), .A1(n2973), .B0(n3088), .B1(
Raw_mant_NRM_SWR[51]), .Y(n1167) );
OAI211XLTS U2166 ( .A0(n2596), .A1(n2670), .B0(n2582), .C0(n2581), .Y(n1658)
);
AOI2BB2XLTS U2167 ( .B0(Raw_mant_NRM_SWR[26]), .B1(n1826), .A0N(n2638),
.A1N(n2724), .Y(n2581) );
AO22XLTS U2168 ( .A0(n3261), .A1(n3001), .B0(n3130), .B1(DmP_mant_SFG_SWR[1]), .Y(n1160) );
AO22XLTS U2169 ( .A0(n3261), .A1(n3010), .B0(n3130), .B1(DmP_mant_SFG_SWR[0]), .Y(n1157) );
AO22XLTS U2170 ( .A0(n3261), .A1(n3246), .B0(n3307), .B1(DmP_mant_SFG_SWR[2]), .Y(n1154) );
AO22XLTS U2171 ( .A0(n3306), .A1(DMP_SHT2_EWSW[0]), .B0(n3307), .B1(
DMP_SFG[0]), .Y(n1540) );
AO22XLTS U2172 ( .A0(n2866), .A1(DmP_EXP_EWSW[8]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[8]), .Y(n1314) );
AO22XLTS U2173 ( .A0(n2868), .A1(DmP_EXP_EWSW[3]), .B0(n2865), .B1(
DmP_mant_SHT1_SW[3]), .Y(n1324) );
AO22XLTS U2174 ( .A0(n2866), .A1(DmP_EXP_EWSW[6]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1318) );
AO22XLTS U2175 ( .A0(n2867), .A1(DmP_EXP_EWSW[9]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[9]), .Y(n1312) );
AO22XLTS U2176 ( .A0(n2867), .A1(DmP_EXP_EWSW[13]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1304) );
AO22XLTS U2177 ( .A0(n2868), .A1(DmP_EXP_EWSW[25]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[25]), .Y(n1280) );
AO22XLTS U2178 ( .A0(n2878), .A1(DmP_EXP_EWSW[34]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[34]), .Y(n1262) );
AOI222X1TS U2179 ( .A0(n1827), .A1(intDX_EWSW[52]), .B0(DmP_EXP_EWSW[52]),
.B1(n1933), .C0(intDY_EWSW[52]), .C1(n2431), .Y(n2337) );
AO22XLTS U2180 ( .A0(n3297), .A1(DMP_SHT2_EWSW[8]), .B0(n2864), .B1(
DMP_SFG[8]), .Y(n1516) );
AO22XLTS U2181 ( .A0(n2868), .A1(DmP_EXP_EWSW[11]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1308) );
AO22XLTS U2182 ( .A0(n2866), .A1(DmP_EXP_EWSW[18]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[18]), .Y(n1294) );
AO22XLTS U2183 ( .A0(n2867), .A1(DmP_EXP_EWSW[22]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1286) );
AO22XLTS U2184 ( .A0(n2878), .A1(DmP_EXP_EWSW[27]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[27]), .Y(n1276) );
AO22XLTS U2185 ( .A0(n2878), .A1(DmP_EXP_EWSW[31]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[31]), .Y(n1268) );
AO22XLTS U2186 ( .A0(n2878), .A1(DmP_EXP_EWSW[33]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[33]), .Y(n1264) );
AO22XLTS U2187 ( .A0(n2880), .A1(DmP_EXP_EWSW[38]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[38]), .Y(n1254) );
AO22XLTS U2188 ( .A0(n2858), .A1(DMP_SHT2_EWSW[5]), .B0(n2864), .B1(
DMP_SFG[5]), .Y(n1525) );
AO22XLTS U2189 ( .A0(n3292), .A1(DMP_SHT2_EWSW[7]), .B0(n2864), .B1(
DMP_SFG[7]), .Y(n1519) );
AO22XLTS U2190 ( .A0(n2858), .A1(DMP_SHT2_EWSW[11]), .B0(n2864), .B1(
DMP_SFG[11]), .Y(n1507) );
AO22XLTS U2191 ( .A0(n2794), .A1(Data_X[63]), .B0(n2807), .B1(intDX_EWSW[63]), .Y(n1752) );
AO22XLTS U2192 ( .A0(n3528), .A1(DmP_EXP_EWSW[17]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[17]), .Y(n1296) );
AO22XLTS U2193 ( .A0(n3528), .A1(DmP_EXP_EWSW[26]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[26]), .Y(n1278) );
AO22XLTS U2194 ( .A0(n2878), .A1(DmP_EXP_EWSW[28]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[28]), .Y(n1274) );
AO22XLTS U2195 ( .A0(n2878), .A1(DmP_EXP_EWSW[30]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[30]), .Y(n1270) );
AO22XLTS U2196 ( .A0(n2878), .A1(DmP_EXP_EWSW[35]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[35]), .Y(n1260) );
AO22XLTS U2197 ( .A0(n2867), .A1(DmP_EXP_EWSW[10]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[10]), .Y(n1310) );
AO22XLTS U2198 ( .A0(n2868), .A1(DmP_EXP_EWSW[14]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[14]), .Y(n1302) );
AO22XLTS U2199 ( .A0(n2867), .A1(DmP_EXP_EWSW[23]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[23]), .Y(n1284) );
AO22XLTS U2200 ( .A0(n2878), .A1(DmP_EXP_EWSW[32]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[32]), .Y(n1266) );
AO22XLTS U2201 ( .A0(n3297), .A1(DMP_SHT2_EWSW[1]), .B0(n2864), .B1(
DMP_SFG[1]), .Y(n1537) );
AO22XLTS U2202 ( .A0(n3292), .A1(DMP_SHT2_EWSW[9]), .B0(n2864), .B1(
DMP_SFG[9]), .Y(n1513) );
AO22XLTS U2203 ( .A0(n3292), .A1(DMP_SHT2_EWSW[10]), .B0(n2864), .B1(
DMP_SFG[10]), .Y(n1510) );
AO22XLTS U2204 ( .A0(n3136), .A1(n2943), .B0(n3088), .B1(
Raw_mant_NRM_SWR[37]), .Y(n1181) );
AO22XLTS U2205 ( .A0(n1825), .A1(n2925), .B0(n3134), .B1(
Raw_mant_NRM_SWR[30]), .Y(n1188) );
AOI2BB2XLTS U2206 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n1914), .A0N(n2601),
.A1N(n2724), .Y(n2602) );
AOI2BB2XLTS U2207 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n1914), .A0N(n2604),
.A1N(n2724), .Y(n2599) );
AOI2BB2XLTS U2208 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[41]), .A0N(n2682),
.A1N(n2719), .Y(n2683) );
OAI211XLTS U2209 ( .A0(n2725), .A1(n2724), .B0(n2723), .C0(n2722), .Y(n1680)
);
AOI2BB2XLTS U2210 ( .B0(DmP_mant_SHT1_SW[49]), .B1(n2721), .A0N(n2720),
.A1N(n2719), .Y(n2722) );
AOI2BB2XLTS U2211 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[47]), .A0N(n2709),
.A1N(n2719), .Y(n2710) );
AO22XLTS U2212 ( .A0(n3136), .A1(n2903), .B0(n2921), .B1(
Raw_mant_NRM_SWR[21]), .Y(n1197) );
AO22XLTS U2213 ( .A0(n1825), .A1(n2952), .B0(n3527), .B1(
Raw_mant_NRM_SWR[41]), .Y(n1177) );
AO22XLTS U2214 ( .A0(n3024), .A1(n2915), .B0(n2921), .B1(
Raw_mant_NRM_SWR[25]), .Y(n1193) );
AO22XLTS U2215 ( .A0(n3024), .A1(n2976), .B0(n3088), .B1(
Raw_mant_NRM_SWR[52]), .Y(n1166) );
AO22XLTS U2216 ( .A0(n2794), .A1(Data_X[61]), .B0(n2807), .B1(intDX_EWSW[61]), .Y(n1754) );
AO22XLTS U2217 ( .A0(n2794), .A1(Data_X[62]), .B0(n2795), .B1(intDX_EWSW[62]), .Y(n1753) );
AO22XLTS U2218 ( .A0(n2794), .A1(Data_X[0]), .B0(n2807), .B1(intDX_EWSW[0]),
.Y(n1815) );
AOI2BB2XLTS U2219 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[39]), .A0N(n2694),
.A1N(n2719), .Y(n2659) );
AO22XLTS U2220 ( .A0(n1825), .A1(n2897), .B0(n2921), .B1(
Raw_mant_NRM_SWR[17]), .Y(n1201) );
AO22XLTS U2221 ( .A0(n3024), .A1(n2970), .B0(n3088), .B1(
Raw_mant_NRM_SWR[49]), .Y(n1169) );
AO22XLTS U2222 ( .A0(n1825), .A1(n2946), .B0(n3088), .B1(
Raw_mant_NRM_SWR[38]), .Y(n1180) );
AO22XLTS U2223 ( .A0(n3090), .A1(n3089), .B0(n3088), .B1(Raw_mant_NRM_SWR[6]), .Y(n1140) );
AOI2BB2XLTS U2224 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[23]), .A0N(n2703),
.A1N(n2719), .Y(n2704) );
AO22XLTS U2225 ( .A0(n3024), .A1(n2891), .B0(n2921), .B1(
Raw_mant_NRM_SWR[15]), .Y(n1203) );
AO22XLTS U2226 ( .A0(n3136), .A1(n2955), .B0(n3088), .B1(
Raw_mant_NRM_SWR[43]), .Y(n1175) );
AO22XLTS U2227 ( .A0(n3090), .A1(n2918), .B0(n2921), .B1(
Raw_mant_NRM_SWR[28]), .Y(n1190) );
AO22XLTS U2228 ( .A0(n3024), .A1(n2894), .B0(n2921), .B1(
Raw_mant_NRM_SWR[16]), .Y(n1202) );
AO22XLTS U2229 ( .A0(n3090), .A1(n2940), .B0(n3088), .B1(
Raw_mant_NRM_SWR[36]), .Y(n1182) );
AO22XLTS U2230 ( .A0(n2796), .A1(Data_X[24]), .B0(n2131), .B1(intDX_EWSW[24]), .Y(n1791) );
AO22XLTS U2231 ( .A0(n2805), .A1(Data_X[2]), .B0(n2806), .B1(intDX_EWSW[2]),
.Y(n1813) );
AO22XLTS U2232 ( .A0(n2794), .A1(Data_X[32]), .B0(n2795), .B1(intDX_EWSW[32]), .Y(n1783) );
AO22XLTS U2233 ( .A0(n2796), .A1(Data_X[16]), .B0(n2800), .B1(intDX_EWSW[16]), .Y(n1799) );
AO22XLTS U2234 ( .A0(n2805), .A1(Data_X[7]), .B0(n2800), .B1(intDX_EWSW[7]),
.Y(n1808) );
AO22XLTS U2235 ( .A0(n3090), .A1(n2961), .B0(n3088), .B1(
Raw_mant_NRM_SWR[45]), .Y(n1173) );
AO22XLTS U2236 ( .A0(n3024), .A1(n2931), .B0(n3088), .B1(
Raw_mant_NRM_SWR[32]), .Y(n1186) );
AO22XLTS U2237 ( .A0(n2805), .A1(Data_X[10]), .B0(n2802), .B1(intDX_EWSW[10]), .Y(n1805) );
AO22XLTS U2238 ( .A0(n2794), .A1(Data_X[48]), .B0(n2807), .B1(intDX_EWSW[48]), .Y(n1767) );
AO22XLTS U2239 ( .A0(n2793), .A1(Data_X[40]), .B0(n2795), .B1(intDX_EWSW[40]), .Y(n1775) );
AO22XLTS U2240 ( .A0(n2798), .A1(Data_X[52]), .B0(n2807), .B1(intDX_EWSW[52]), .Y(n1763) );
AO22XLTS U2241 ( .A0(n2798), .A1(Data_X[37]), .B0(n2795), .B1(intDX_EWSW[37]), .Y(n1778) );
AO22XLTS U2242 ( .A0(n1825), .A1(n2949), .B0(n3088), .B1(
Raw_mant_NRM_SWR[39]), .Y(n1179) );
AO22XLTS U2243 ( .A0(n2794), .A1(Data_X[47]), .B0(n2807), .B1(intDX_EWSW[47]), .Y(n1768) );
AO22XLTS U2244 ( .A0(n2793), .A1(Data_X[44]), .B0(n2795), .B1(intDX_EWSW[44]), .Y(n1771) );
AOI2BB2XLTS U2245 ( .B0(Raw_mant_NRM_SWR[24]), .B1(n1826), .A0N(n2635),
.A1N(n2724), .Y(n2636) );
AO22XLTS U2246 ( .A0(n2793), .A1(Data_X[38]), .B0(n2795), .B1(intDX_EWSW[38]), .Y(n1777) );
AOI2BB2XLTS U2247 ( .B0(Raw_mant_NRM_SWR[29]), .B1(n1826), .A0N(n2655),
.A1N(n2724), .Y(n2624) );
AOI2BB2XLTS U2248 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[26]), .A0N(n2655),
.A1N(n2670), .Y(n2656) );
AOI2BB2XLTS U2249 ( .B0(n2721), .B1(n1937), .A0N(n2689), .A1N(n2719), .Y(
n2668) );
AO22XLTS U2250 ( .A0(n3024), .A1(n2922), .B0(n2921), .B1(
Raw_mant_NRM_SWR[29]), .Y(n1189) );
AO22XLTS U2251 ( .A0(n3090), .A1(n2909), .B0(n2921), .B1(
Raw_mant_NRM_SWR[23]), .Y(n1195) );
AO22XLTS U2252 ( .A0(n1825), .A1(n2964), .B0(n3088), .B1(
Raw_mant_NRM_SWR[47]), .Y(n1171) );
AO22XLTS U2253 ( .A0(n2805), .A1(Data_X[5]), .B0(n2806), .B1(intDX_EWSW[5]),
.Y(n1810) );
AO22XLTS U2254 ( .A0(n3090), .A1(n2900), .B0(n2921), .B1(
Raw_mant_NRM_SWR[20]), .Y(n1198) );
OAI222X1TS U2255 ( .A0(n2874), .A1(n3464), .B0(n3356), .B1(n2873), .C0(n3313), .C1(n2872), .Y(n1226) );
AO22XLTS U2256 ( .A0(n2790), .A1(n3136), .B0(n2792), .B1(n1913), .Y(n1818)
);
AO22XLTS U2257 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[42]), .B0(n3090), .B1(
n2010), .Y(n1176) );
AO22XLTS U2258 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[40]), .B0(n3090), .B1(
n2007), .Y(n1178) );
AO22XLTS U2259 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[46]), .B0(n3136), .B1(
n2004), .Y(n1172) );
AO22XLTS U2260 ( .A0(n3088), .A1(Raw_mant_NRM_SWR[50]), .B0(n1825), .B1(
n2001), .Y(n1168) );
AO22XLTS U2261 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[35]), .B0(n3024), .B1(
n2185), .Y(n1183) );
OAI21XLTS U2262 ( .A0(n2690), .A1(n2652), .B0(n2534), .Y(n1685) );
AO22XLTS U2263 ( .A0(n3253), .A1(n3301), .B0(final_result_ieee[51]), .B1(
n3225), .Y(n1078) );
AO22XLTS U2264 ( .A0(n3253), .A1(n3300), .B0(final_result_ieee[50]), .B1(
n3240), .Y(n1079) );
AO22XLTS U2265 ( .A0(n3253), .A1(n3299), .B0(final_result_ieee[49]), .B1(
n3225), .Y(n1080) );
AO22XLTS U2266 ( .A0(n3253), .A1(n3246), .B0(final_result_ieee[0]), .B1(
n3240), .Y(n1081) );
AO22XLTS U2267 ( .A0(n3253), .A1(n3245), .B0(final_result_ieee[1]), .B1(
n3225), .Y(n1082) );
AO22XLTS U2268 ( .A0(n3253), .A1(n3294), .B0(final_result_ieee[47]), .B1(
n3240), .Y(n1083) );
AO22XLTS U2269 ( .A0(n3253), .A1(n3215), .B0(final_result_ieee[3]), .B1(
n3225), .Y(n1088) );
AO22XLTS U2270 ( .A0(n3253), .A1(n3296), .B0(final_result_ieee[48]), .B1(
n3240), .Y(n1089) );
AO22XLTS U2271 ( .A0(n3253), .A1(n3212), .B0(final_result_ieee[2]), .B1(
n3225), .Y(n1090) );
AO22XLTS U2272 ( .A0(n3253), .A1(n3290), .B0(final_result_ieee[45]), .B1(
n3240), .Y(n1093) );
AO22XLTS U2273 ( .A0(n3253), .A1(n3272), .B0(final_result_ieee[29]), .B1(
n3240), .Y(n1096) );
AO22XLTS U2274 ( .A0(n3253), .A1(n3264), .B0(final_result_ieee[21]), .B1(
n3225), .Y(n1097) );
AO22XLTS U2275 ( .A0(n3253), .A1(n3187), .B0(final_result_ieee[5]), .B1(
n3240), .Y(n1098) );
AO22XLTS U2276 ( .A0(n3253), .A1(n3291), .B0(final_result_ieee[46]), .B1(
n3225), .Y(n1103) );
AO22XLTS U2277 ( .A0(n3172), .A1(n3171), .B0(final_result_ieee[4]), .B1(
n3240), .Y(n1104) );
AO22XLTS U2278 ( .A0(n3172), .A1(n3288), .B0(final_result_ieee[43]), .B1(
n3225), .Y(n1105) );
AO22XLTS U2279 ( .A0(n3172), .A1(n3270), .B0(final_result_ieee[27]), .B1(
n3240), .Y(n1108) );
AO22XLTS U2280 ( .A0(n3172), .A1(n3266), .B0(final_result_ieee[23]), .B1(
n3225), .Y(n1109) );
AO22XLTS U2281 ( .A0(n3172), .A1(n3160), .B0(final_result_ieee[7]), .B1(
n3240), .Y(n1110) );
AO22XLTS U2282 ( .A0(n3172), .A1(n3289), .B0(final_result_ieee[44]), .B1(
n3225), .Y(n1111) );
AO22XLTS U2283 ( .A0(n3172), .A1(n3157), .B0(final_result_ieee[6]), .B1(
n3240), .Y(n1112) );
AO22XLTS U2284 ( .A0(n3172), .A1(n3154), .B0(final_result_ieee[9]), .B1(
n3225), .Y(n1114) );
AO22XLTS U2285 ( .A0(n3172), .A1(n3271), .B0(final_result_ieee[28]), .B1(
n3240), .Y(n1117) );
AO22XLTS U2286 ( .A0(n3172), .A1(n3269), .B0(final_result_ieee[26]), .B1(
n3225), .Y(n1123) );
AO22XLTS U2287 ( .A0(n3172), .A1(n3267), .B0(final_result_ieee[24]), .B1(
n3240), .Y(n1124) );
AO22XLTS U2288 ( .A0(n3172), .A1(n3287), .B0(final_result_ieee[42]), .B1(
n3225), .Y(n1133) );
AO22XLTS U2289 ( .A0(n3253), .A1(n3113), .B0(final_result_ieee[8]), .B1(
n3240), .Y(n1134) );
AO22XLTS U2290 ( .A0(n3024), .A1(n2934), .B0(n3088), .B1(n1950), .Y(n1185)
);
AO22XLTS U2291 ( .A0(n2880), .A1(DmP_EXP_EWSW[48]), .B0(n2870), .B1(n1916),
.Y(n1234) );
AO22XLTS U2292 ( .A0(n2880), .A1(DmP_EXP_EWSW[46]), .B0(n2870), .B1(n1917),
.Y(n1238) );
AO22XLTS U2293 ( .A0(n2880), .A1(DmP_EXP_EWSW[44]), .B0(n2870), .B1(n1928),
.Y(n1242) );
AO22XLTS U2294 ( .A0(n2880), .A1(DmP_EXP_EWSW[42]), .B0(n2870), .B1(n1929),
.Y(n1246) );
AO22XLTS U2295 ( .A0(n2880), .A1(DmP_EXP_EWSW[40]), .B0(n2870), .B1(n1930),
.Y(n1250) );
AO22XLTS U2296 ( .A0(n2880), .A1(DmP_EXP_EWSW[36]), .B0(n2869), .B1(n1918),
.Y(n1258) );
AO22XLTS U2297 ( .A0(n2880), .A1(DmP_EXP_EWSW[29]), .B0(n2869), .B1(n1919),
.Y(n1272) );
AO22XLTS U2298 ( .A0(n3528), .A1(DmP_EXP_EWSW[21]), .B0(n2869), .B1(n1937),
.Y(n1288) );
AO22XLTS U2299 ( .A0(n2866), .A1(DmP_EXP_EWSW[19]), .B0(n2869), .B1(n1938),
.Y(n1292) );
AO22XLTS U2300 ( .A0(n2868), .A1(DmP_EXP_EWSW[15]), .B0(n2865), .B1(n1920),
.Y(n1300) );
AO22XLTS U2301 ( .A0(n2866), .A1(DmP_EXP_EWSW[12]), .B0(n2879), .B1(n1922),
.Y(n1306) );
AO22XLTS U2302 ( .A0(n2868), .A1(DmP_EXP_EWSW[7]), .B0(n2879), .B1(n1924),
.Y(n1316) );
AO22XLTS U2303 ( .A0(n2867), .A1(DmP_EXP_EWSW[5]), .B0(n2865), .B1(n1923),
.Y(n1320) );
AO22XLTS U2304 ( .A0(n2866), .A1(DmP_EXP_EWSW[4]), .B0(n2865), .B1(n1925),
.Y(n1322) );
AO22XLTS U2305 ( .A0(n2858), .A1(DMP_SHT2_EWSW[6]), .B0(n2864), .B1(n1931),
.Y(n1522) );
AO22XLTS U2306 ( .A0(n3292), .A1(DMP_SHT2_EWSW[4]), .B0(n2864), .B1(n1932),
.Y(n1528) );
AO22XLTS U2307 ( .A0(n2848), .A1(n2822), .B0(n2877), .B1(n1926), .Y(n1625)
);
AOI2BB2XLTS U2308 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[45]), .A0N(n2674),
.A1N(n2719), .Y(n2675) );
OAI211XLTS U2309 ( .A0(n2629), .A1(n2670), .B0(n2628), .C0(n2627), .Y(n1639)
);
AOI2BB2XLTS U2310 ( .B0(Raw_mant_NRM_SWR[45]), .B1(n1826), .A0N(n2695),
.A1N(n2724), .Y(n2627) );
AOI2BB2XLTS U2311 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[10]), .A0N(n2695),
.A1N(n2719), .Y(n2696) );
OAI211XLTS U2312 ( .A0(n2575), .A1(n2690), .B0(n2574), .C0(n2573), .Y(n1642)
);
AOI2BB2XLTS U2313 ( .B0(Raw_mant_NRM_SWR[42]), .B1(n1826), .A0N(n2578),
.A1N(n2570), .Y(n2573) );
AOI2BB2XLTS U2314 ( .B0(n2718), .B1(DmP_mant_SHT1_SW[10]), .A0N(n2698),
.A1N(n2719), .Y(n2555) );
AOI2BB2XLTS U2315 ( .B0(Raw_mant_NRM_SWR[40]), .B1(n1826), .A0N(n2613),
.A1N(n2570), .Y(n2576) );
AOI2BB2XLTS U2316 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[14]), .A0N(n2713),
.A1N(n2719), .Y(n2714) );
AOI2BB2XLTS U2317 ( .B0(Raw_mant_NRM_SWR[38]), .B1(n1826), .A0N(n2661),
.A1N(n2724), .Y(n2611) );
OAI211XLTS U2318 ( .A0(n2589), .A1(n2670), .B0(n2588), .C0(n2587), .Y(n1649)
);
AOI2BB2XLTS U2319 ( .B0(Raw_mant_NRM_SWR[35]), .B1(n1826), .A0N(n2607),
.A1N(n2724), .Y(n2587) );
AOI2BB2XLTS U2320 ( .B0(n1950), .B1(n1826), .A0N(n2622), .A1N(n2724), .Y(
n2605) );
AOI2BB2XLTS U2321 ( .B0(Raw_mant_NRM_SWR[31]), .B1(n1826), .A0N(n2626),
.A1N(n2724), .Y(n2620) );
AOI2BB2XLTS U2322 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[28]), .A0N(n2658),
.A1N(n2690), .Y(n2653) );
AOI2BB2XLTS U2323 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[30]), .A0N(n2664),
.A1N(n2670), .Y(n2665) );
AOI2BB2XLTS U2324 ( .B0(Raw_mant_NRM_SWR[22]), .B1(n1826), .A0N(n2647),
.A1N(n2724), .Y(n2618) );
AOI2BB2XLTS U2325 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[32]), .A0N(n2699),
.A1N(n2719), .Y(n2700) );
AOI2BB2XLTS U2326 ( .B0(Raw_mant_NRM_SWR[20]), .B1(n1914), .A0N(n2679),
.A1N(n2724), .Y(n2645) );
AOI2BB2XLTS U2327 ( .B0(n2718), .B1(DmP_mant_SHT1_SW[32]), .A0N(n2702),
.A1N(n2719), .Y(n2597) );
AOI2BB2XLTS U2328 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[35]), .A0N(n2679),
.A1N(n2719), .Y(n2680) );
OAI211XLTS U2329 ( .A0(n2617), .A1(n2690), .B0(n2616), .C0(n2615), .Y(n1667)
);
AOI2BB2XLTS U2330 ( .B0(Raw_mant_NRM_SWR[17]), .B1(n1914), .A0N(n2614),
.A1N(n2724), .Y(n2615) );
AOI2BB2XLTS U2331 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[37]), .A0N(n2691),
.A1N(n2690), .Y(n2692) );
AOI2BB2XLTS U2332 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1914), .A0N(n2608),
.A1N(n2724), .Y(n2609) );
AOI2BB1XLTS U2333 ( .A0N(n2649), .A1N(n2690), .B0(n2721), .Y(n2650) );
AO22XLTS U2334 ( .A0(n2792), .A1(n2851), .B0(n2790), .B1(n1913), .Y(n1819)
);
OR2X1TS U2335 ( .A(n1872), .B(n1835), .Y(n1829) );
OR2X1TS U2336 ( .A(n1960), .B(n1961), .Y(n1835) );
AO22X1TS U2337 ( .A0(n1999), .A1(DmP_mant_SFG_SWR[13]), .B0(n1980), .B1(
n3037), .Y(n1853) );
OR2X1TS U2338 ( .A(n1967), .B(n1968), .Y(n1858) );
OA22X1TS U2339 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2174), .B0(n3429), .B1(
n3058), .Y(n1860) );
OA22X1TS U2340 ( .A0(shift_value_SHT2_EWR[4]), .A1(n3210), .B0(n3427), .B1(
n3058), .Y(n1861) );
OA22X1TS U2341 ( .A0(shift_value_SHT2_EWR[4]), .A1(n3178), .B0(n3249), .B1(
n3058), .Y(n1862) );
OA22X1TS U2342 ( .A0(shift_value_SHT2_EWR[4]), .A1(n3220), .B0(n3428), .B1(
n3058), .Y(n1863) );
AOI22X1TS U2343 ( .A0(n3307), .A1(n3075), .B0(n2858), .B1(OP_FLAG_SHT2), .Y(
n1873) );
CLKINVX6TS U2344 ( .A(n1832), .Y(n1933) );
BUFX3TS U2345 ( .A(n3486), .Y(n3500) );
INVX4TS U2346 ( .A(n3527), .Y(n3024) );
CLKINVX6TS U2347 ( .A(n3298), .Y(n3261) );
OAI221X1TS U2348 ( .A0(n3338), .A1(intDX_EWSW[27]), .B0(n3419), .B1(
intDX_EWSW[26]), .C0(n2493), .Y(n2496) );
NOR2XLTS U2349 ( .A(n3464), .B(intDY_EWSW[53]), .Y(n2187) );
AOI222X4TS U2350 ( .A0(n2180), .A1(n3303), .B0(n2179), .B1(n3222), .C0(n3009), .C1(n3221), .Y(n3263) );
AOI222X1TS U2351 ( .A0(n2180), .A1(n3239), .B0(n2179), .B1(n2156), .C0(n3009), .C1(n3223), .Y(n3273) );
AOI222X4TS U2352 ( .A0(n3179), .A1(n3239), .B0(n3181), .B1(n2156), .C0(n3182), .C1(n3223), .Y(n3275) );
AOI222X1TS U2353 ( .A0(n3179), .A1(n3361), .B0(n3181), .B1(n3222), .C0(n3182), .C1(n3221), .Y(n3260) );
AOI222X4TS U2354 ( .A0(n3224), .A1(n3239), .B0(n3230), .B1(n2156), .C0(n3231), .C1(n3223), .Y(n3274) );
AOI222X1TS U2355 ( .A0(n3224), .A1(n3303), .B0(n3230), .B1(n3222), .C0(n3231), .C1(n3221), .Y(n3262) );
NAND4X1TS U2356 ( .A(n2086), .B(n2770), .C(n2085), .D(n2736), .Y(n2088) );
OAI21X1TS U2357 ( .A0(n3455), .A1(n3117), .B0(n3091), .Y(n3092) );
OAI211X1TS U2358 ( .A0(n2744), .A1(n2742), .B0(n2041), .C0(n2040), .Y(n2042)
);
NAND2X4TS U2359 ( .A(n2778), .B(Shift_reg_FLAGS_7[0]), .Y(n2784) );
CLKINVX6TS U2360 ( .A(n2799), .Y(n2795) );
BUFX4TS U2361 ( .A(n3516), .Y(n3489) );
BUFX4TS U2362 ( .A(n3525), .Y(n3519) );
BUFX4TS U2363 ( .A(n3516), .Y(n3487) );
BUFX4TS U2364 ( .A(n3499), .Y(n3488) );
INVX2TS U2365 ( .A(n1853), .Y(n1896) );
INVX2TS U2366 ( .A(n1833), .Y(n1897) );
AOI21X2TS U2367 ( .A0(n1956), .A1(n3125), .B0(n3118), .Y(n3153) );
OAI21X1TS U2368 ( .A0(n3457), .A1(n3117), .B0(n3116), .Y(n3118) );
BUFX4TS U2369 ( .A(n3492), .Y(n3498) );
BUFX4TS U2370 ( .A(n3510), .Y(n3522) );
BUFX4TS U2371 ( .A(n3511), .Y(n3486) );
BUFX4TS U2372 ( .A(n3510), .Y(n3485) );
BUFX4TS U2373 ( .A(n3508), .Y(n3495) );
BUFX4TS U2374 ( .A(n3508), .Y(n3480) );
BUFX4TS U2375 ( .A(n3519), .Y(n3494) );
BUFX4TS U2376 ( .A(n3519), .Y(n3517) );
BUFX4TS U2377 ( .A(n3516), .Y(n3490) );
BUFX4TS U2378 ( .A(n3472), .Y(n3491) );
BUFX4TS U2379 ( .A(n3516), .Y(n3523) );
BUFX4TS U2380 ( .A(n3514), .Y(n3496) );
BUFX4TS U2381 ( .A(n3514), .Y(n3509) );
BUFX4TS U2382 ( .A(n3492), .Y(n3497) );
BUFX4TS U2383 ( .A(n3482), .Y(n3483) );
CLKINVX6TS U2384 ( .A(n3056), .Y(n3115) );
BUFX4TS U2385 ( .A(n3485), .Y(n3479) );
BUFX4TS U2386 ( .A(n3485), .Y(n3525) );
BUFX4TS U2387 ( .A(n3481), .Y(n3492) );
BUFX4TS U2388 ( .A(n3509), .Y(n3482) );
BUFX3TS U2389 ( .A(n3480), .Y(n3518) );
BUFX4TS U2390 ( .A(n3530), .Y(n3508) );
BUFX4TS U2391 ( .A(n3530), .Y(n3514) );
BUFX4TS U2392 ( .A(n3491), .Y(n3478) );
BUFX4TS U2393 ( .A(n3491), .Y(n3477) );
BUFX4TS U2394 ( .A(n3517), .Y(n3501) );
BUFX4TS U2395 ( .A(n3522), .Y(n3499) );
XNOR2X2TS U2396 ( .A(DMP_exp_NRM2_EW[8]), .B(n2113), .Y(n2782) );
INVX2TS U2397 ( .A(n1863), .Y(n1898) );
INVX2TS U2398 ( .A(n1862), .Y(n1899) );
XNOR2X2TS U2399 ( .A(DMP_exp_NRM2_EW[0]), .B(n1995), .Y(n2779) );
XNOR2X2TS U2400 ( .A(DMP_exp_NRM2_EW[9]), .B(n2116), .Y(n2783) );
INVX2TS U2401 ( .A(n1860), .Y(n1900) );
INVX2TS U2402 ( .A(n1861), .Y(n1901) );
BUFX4TS U2403 ( .A(n3525), .Y(n3503) );
BUFX4TS U2404 ( .A(n3486), .Y(n3505) );
BUFX4TS U2405 ( .A(n3522), .Y(n3506) );
BUFX4TS U2406 ( .A(n3525), .Y(n3472) );
XNOR2X2TS U2407 ( .A(DMP_exp_NRM2_EW[6]), .B(DP_OP_15J75_123_4372_n6), .Y(
n2780) );
BUFX6TS U2408 ( .A(n2426), .Y(n2455) );
CLKINVX6TS U2409 ( .A(n3468), .Y(n3240) );
CLKINVX6TS U2410 ( .A(n3468), .Y(n3225) );
INVX2TS U2411 ( .A(n1886), .Y(n1902) );
INVX2TS U2412 ( .A(n1877), .Y(n1903) );
INVX2TS U2413 ( .A(n1876), .Y(n1904) );
INVX2TS U2414 ( .A(n1871), .Y(n1905) );
INVX2TS U2415 ( .A(n1870), .Y(n1906) );
INVX2TS U2416 ( .A(n1868), .Y(n1907) );
INVX2TS U2417 ( .A(n1867), .Y(n1908) );
INVX2TS U2418 ( .A(n1866), .Y(n1909) );
INVX2TS U2419 ( .A(n1864), .Y(n1910) );
INVX2TS U2420 ( .A(n1859), .Y(n1911) );
INVX2TS U2421 ( .A(n1856), .Y(n1912) );
INVX2TS U2422 ( .A(n1865), .Y(n1913) );
CLKINVX6TS U2423 ( .A(n2796), .Y(n2807) );
AOI2BB2X2TS U2424 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n3526), .A0N(n2986),
.A1N(DmP_mant_SFG_SWR[11]), .Y(n3099) );
INVX2TS U2425 ( .A(n1875), .Y(n1915) );
CLKINVX6TS U2426 ( .A(n3527), .Y(n3136) );
INVX4TS U2427 ( .A(n3527), .Y(n3090) );
INVX2TS U2428 ( .A(n1895), .Y(n1916) );
INVX2TS U2429 ( .A(n1890), .Y(n1917) );
INVX2TS U2430 ( .A(n1889), .Y(n1918) );
INVX2TS U2431 ( .A(n1894), .Y(n1919) );
INVX2TS U2432 ( .A(n1888), .Y(n1920) );
AOI222X1TS U2433 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n2631), .B0(
DmP_mant_SHT1_SW[50]), .B1(n2644), .C0(n2623), .C1(
DmP_mant_SHT1_SW[51]), .Y(n2649) );
INVX2TS U2434 ( .A(n1885), .Y(n1921) );
INVX2TS U2435 ( .A(n1891), .Y(n1922) );
INVX2TS U2436 ( .A(n1851), .Y(n1923) );
INVX2TS U2437 ( .A(n1884), .Y(n1924) );
INVX2TS U2438 ( .A(n1852), .Y(n1925) );
INVX2TS U2439 ( .A(n1840), .Y(n1926) );
CLKINVX6TS U2440 ( .A(n3307), .Y(n3306) );
BUFX6TS U2441 ( .A(n3295), .Y(n3307) );
INVX2TS U2442 ( .A(n1850), .Y(n1927) );
INVX2TS U2443 ( .A(n1883), .Y(n1928) );
INVX2TS U2444 ( .A(n1882), .Y(n1929) );
INVX2TS U2445 ( .A(n1881), .Y(n1930) );
CLKINVX3TS U2446 ( .A(n2386), .Y(n2873) );
CLKINVX6TS U2447 ( .A(n2859), .Y(n2851) );
BUFX4TS U2448 ( .A(n2623), .Y(n2707) );
BUFX4TS U2449 ( .A(n2623), .Y(n2677) );
BUFX6TS U2450 ( .A(n2063), .Y(n2815) );
BUFX4TS U2451 ( .A(n3516), .Y(n3521) );
BUFX4TS U2452 ( .A(n3499), .Y(n3484) );
BUFX4TS U2453 ( .A(n3516), .Y(n3510) );
BUFX4TS U2454 ( .A(n3499), .Y(n3511) );
BUFX3TS U2455 ( .A(n3518), .Y(n3516) );
INVX2TS U2456 ( .A(n1880), .Y(n1931) );
INVX2TS U2457 ( .A(n1849), .Y(n1932) );
CLKBUFX2TS U2458 ( .A(n1997), .Y(n2845) );
INVX4TS U2459 ( .A(n2798), .Y(n2803) );
INVX4TS U2460 ( .A(n2798), .Y(n2806) );
CLKINVX3TS U2461 ( .A(n2877), .Y(n2850) );
CLKINVX3TS U2462 ( .A(n2877), .Y(n2848) );
BUFX4TS U2463 ( .A(n3481), .Y(n3475) );
BUFX3TS U2464 ( .A(n3517), .Y(n3524) );
CLKINVX6TS U2465 ( .A(left_right_SHT2), .Y(n3303) );
BUFX6TS U2466 ( .A(left_right_SHT2), .Y(n3239) );
INVX4TS U2467 ( .A(n2648), .Y(n2630) );
CLKINVX6TS U2468 ( .A(n3298), .Y(n3285) );
BUFX4TS U2469 ( .A(n2386), .Y(n2453) );
BUFX4TS U2470 ( .A(n2386), .Y(n2442) );
NOR2X8TS U2471 ( .A(n2716), .B(n2648), .Y(n2721) );
INVX3TS U2472 ( .A(n2859), .Y(n2882) );
BUFX4TS U2473 ( .A(n2811), .Y(n2819) );
CLKINVX6TS U2474 ( .A(n2336), .Y(n2435) );
INVX3TS U2475 ( .A(n2859), .Y(n2862) );
INVX3TS U2476 ( .A(n2842), .Y(n2456) );
INVX3TS U2477 ( .A(n2842), .Y(n2449) );
AOI222X4TS U2478 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[37]), .C0(n2630), .C1(n1918), .Y(n2614) );
INVX2TS U2479 ( .A(n1893), .Y(n1937) );
INVX2TS U2480 ( .A(n1892), .Y(n1938) );
INVX2TS U2481 ( .A(n1848), .Y(n1939) );
INVX2TS U2482 ( .A(n1847), .Y(n1940) );
INVX2TS U2483 ( .A(n1846), .Y(n1941) );
INVX2TS U2484 ( .A(n1845), .Y(n1942) );
AOI211X1TS U2485 ( .A0(n2034), .A1(Raw_mant_NRM_SWR[44]), .B0(
Raw_mant_NRM_SWR[48]), .C0(Raw_mant_NRM_SWR[47]), .Y(n2037) );
NOR4X2TS U2486 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .C(
Raw_mant_NRM_SWR[52]), .D(Raw_mant_NRM_SWR[51]), .Y(n2763) );
AOI22X2TS U2487 ( .A0(n1948), .A1(n2159), .B0(Data_array_SWR[29]), .B1(n3189), .Y(n3173) );
AOI22X2TS U2488 ( .A0(Data_array_SWR[34]), .A1(n2159), .B0(
Data_array_SWR[31]), .B1(n3189), .Y(n3213) );
INVX2TS U2489 ( .A(n1839), .Y(n1943) );
INVX2TS U2490 ( .A(n1844), .Y(n1944) );
INVX2TS U2491 ( .A(n1843), .Y(n1945) );
INVX2TS U2492 ( .A(n1831), .Y(n1946) );
INVX2TS U2493 ( .A(n1842), .Y(n1947) );
INVX2TS U2494 ( .A(n1841), .Y(n1948) );
OAI221X1TS U2495 ( .A0(n3453), .A1(intDX_EWSW[7]), .B0(n3352), .B1(
intDX_EWSW[6]), .C0(n2513), .Y(n2520) );
INVX2TS U2496 ( .A(n1836), .Y(n1949) );
INVX2TS U2497 ( .A(n1855), .Y(n1950) );
INVX2TS U2498 ( .A(n1830), .Y(n1951) );
INVX2TS U2499 ( .A(n1838), .Y(n1952) );
INVX2TS U2500 ( .A(n1834), .Y(n1953) );
INVX2TS U2501 ( .A(n1837), .Y(n1954) );
OAI221XLTS U2502 ( .A0(n3407), .A1(intDX_EWSW[9]), .B0(n3425), .B1(
intDX_EWSW[16]), .C0(n2508), .Y(n2509) );
AOI221X1TS U2503 ( .A0(n3440), .A1(intDX_EWSW[38]), .B0(intDX_EWSW[39]),
.B1(n3438), .C0(n2485), .Y(n2488) );
INVX2TS U2504 ( .A(n1828), .Y(n1955) );
AOI222X1TS U2505 ( .A0(intDX_EWSW[4]), .A1(n3413), .B0(intDX_EWSW[5]), .B1(
n3334), .C0(n2213), .C1(n2212), .Y(n2214) );
OAI221X1TS U2506 ( .A0(n3410), .A1(intDX_EWSW[13]), .B0(n3413), .B1(
intDX_EWSW[4]), .C0(n2506), .Y(n2511) );
INVX2TS U2507 ( .A(n1874), .Y(n1956) );
INVX2TS U2508 ( .A(n1869), .Y(n1957) );
INVX2TS U2509 ( .A(n1878), .Y(n1958) );
INVX2TS U2510 ( .A(n1879), .Y(n1959) );
NOR2XLTS U2511 ( .A(n3416), .B(intDX_EWSW[18]), .Y(n1960) );
NOR2XLTS U2512 ( .A(n3336), .B(intDX_EWSW[19]), .Y(n1961) );
NAND2X1TS U2513 ( .A(n1962), .B(n1963), .Y(n2752) );
INVX1TS U2514 ( .A(n2749), .Y(n1964) );
INVX2TS U2515 ( .A(n2750), .Y(n1965) );
NAND2X1TS U2516 ( .A(n1887), .B(n1966), .Y(n1962) );
OAI31X1TS U2517 ( .A0(n2745), .A1(n2744), .A2(n2743), .B0(n2766), .Y(n2750)
);
OAI221X1TS U2518 ( .A0(n3409), .A1(intDX_EWSW[57]), .B0(n3310), .B1(
intDX_EWSW[56]), .C0(n2463), .Y(n2470) );
OAI211XLTS U2519 ( .A0(n2593), .A1(n2570), .B0(n2592), .C0(n2591), .Y(n1633)
);
NOR4X2TS U2520 ( .A(n2188), .B(n2256), .C(n2268), .D(n2260), .Y(n2313) );
NOR2XLTS U2521 ( .A(n3125), .B(n3070), .Y(n1967) );
NOR2XLTS U2522 ( .A(Data_array_SWR[16]), .B(n3070), .Y(n1968) );
OAI211X2TS U2523 ( .A0(intDY_EWSW[20]), .A1(n3378), .B0(n2499), .C0(n2204),
.Y(n2242) );
OAI211X2TS U2524 ( .A0(intDY_EWSW[12]), .A1(n3367), .B0(n2505), .C0(n2205),
.Y(n2233) );
OAI211X2TS U2525 ( .A0(intDY_EWSW[28]), .A1(n3377), .B0(n2491), .C0(n2195),
.Y(n2250) );
XNOR2X2TS U2526 ( .A(DMP_exp_NRM2_EW[10]), .B(n2120), .Y(n2785) );
AOI2BB2X2TS U2527 ( .B0(DmP_mant_SFG_SWR[3]), .B1(n3526), .A0N(n3075), .A1N(
DmP_mant_SFG_SWR[3]), .Y(n3035) );
AOI2BB2X2TS U2528 ( .B0(DmP_mant_SFG_SWR[7]), .B1(n3526), .A0N(n3076), .A1N(
DmP_mant_SFG_SWR[7]), .Y(n3050) );
AOI2BB2X2TS U2529 ( .B0(DmP_mant_SFG_SWR[9]), .B1(n1999), .A0N(n3076), .A1N(
DmP_mant_SFG_SWR[9]), .Y(n3098) );
OAI211XLTS U2530 ( .A0(n2642), .A1(n2670), .B0(n2641), .C0(n2640), .Y(n1636)
);
CLKINVX6TS U2531 ( .A(n3467), .Y(n2986) );
BUFX4TS U2532 ( .A(Shift_reg_FLAGS_7[0]), .Y(n3468) );
BUFX4TS U2533 ( .A(n3513), .Y(n3507) );
AOI222X1TS U2534 ( .A0(n2157), .A1(n3303), .B0(n3140), .B1(n3221), .C0(n3141), .C1(n2156), .Y(n3145) );
AOI222X1TS U2535 ( .A0(n2178), .A1(n3303), .B0(n3148), .B1(n3221), .C0(n3149), .C1(n2156), .Y(n3254) );
AOI222X4TS U2536 ( .A0(n2182), .A1(n3361), .B0(n3163), .B1(n3221), .C0(n3164), .C1(n2156), .Y(n2985) );
AOI222X1TS U2537 ( .A0(n3204), .A1(n3303), .B0(n3203), .B1(n3221), .C0(n3202), .C1(n2156), .Y(n3255) );
AOI222X1TS U2538 ( .A0(n2182), .A1(n3239), .B0(n3163), .B1(n3223), .C0(n3164), .C1(n3222), .Y(n3283) );
AOI222X4TS U2539 ( .A0(n2178), .A1(n3239), .B0(n3148), .B1(n3223), .C0(n3149), .C1(n3222), .Y(n3282) );
AOI222X4TS U2540 ( .A0(n3204), .A1(n3239), .B0(n3203), .B1(n3223), .C0(n3202), .C1(n3222), .Y(n3281) );
BUFX4TS U2541 ( .A(n2145), .Y(n3222) );
BUFX4TS U2542 ( .A(n2798), .Y(n2808) );
BUFX6TS U2543 ( .A(n2799), .Y(n2798) );
INVX3TS U2544 ( .A(n3221), .Y(n3197) );
INVX3TS U2545 ( .A(n3223), .Y(n3242) );
XOR2X1TS U2546 ( .A(DMP_SFG[11]), .B(n2990), .Y(n2991) );
AOI222X4TS U2547 ( .A0(DMP_SFG[9]), .A1(n3099), .B0(DMP_SFG[9]), .B1(n2987),
.C0(n3099), .C1(n2987), .Y(n3131) );
OAI31XLTS U2548 ( .A0(n2847), .A1(n2532), .A2(n2874), .B0(n2531), .Y(n1543)
);
INVX3TS U2549 ( .A(n2395), .Y(n2874) );
INVX3TS U2550 ( .A(n2859), .Y(n2863) );
INVX4TS U2551 ( .A(n3463), .Y(n2880) );
INVX4TS U2552 ( .A(n3295), .Y(n2858) );
BUFX3TS U2553 ( .A(n2852), .Y(n3295) );
INVX2TS U2554 ( .A(n1969), .Y(n1970) );
NAND2X2TS U2555 ( .A(n2088), .B(Shift_reg_FLAGS_7[1]), .Y(n2777) );
NAND2X1TS U2556 ( .A(Shift_reg_FLAGS_7[1]), .B(n2548), .Y(n2776) );
NOR2X1TS U2557 ( .A(Raw_mant_NRM_SWR[37]), .B(Raw_mant_NRM_SWR[38]), .Y(
n2745) );
NAND2X2TS U2558 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n3117) );
AOI22X2TS U2559 ( .A0(Data_array_SWR[30]), .A1(n3115), .B0(
Data_array_SWR[33]), .B1(n3125), .Y(n3243) );
AOI22X2TS U2560 ( .A0(Data_array_SWR[28]), .A1(n3115), .B0(
Data_array_SWR[32]), .B1(n3125), .Y(n3205) );
AOI32X1TS U2561 ( .A0(Raw_mant_NRM_SWR[39]), .A1(n2015), .A2(n3364), .B0(
Raw_mant_NRM_SWR[41]), .B1(n2015), .Y(n2016) );
NAND2BX1TS U2562 ( .AN(Raw_mant_NRM_SWR[41]), .B(n2015), .Y(n2744) );
NOR2BX2TS U2563 ( .AN(n2019), .B(Raw_mant_NRM_SWR[25]), .Y(n2046) );
NOR2X2TS U2564 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3431), .Y(n2786) );
OAI221X1TS U2565 ( .A0(n3432), .A1(intDX_EWSW[61]), .B0(n3423), .B1(
intDX_EWSW[60]), .C0(n2465), .Y(n2468) );
OAI221XLTS U2566 ( .A0(n3333), .A1(intDX_EWSW[0]), .B0(n3414), .B1(
intDX_EWSW[8]), .C0(n2516), .Y(n2517) );
NOR2X1TS U2567 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .Y(n2731)
);
OAI2BB2XLTS U2568 ( .B0(n2058), .B1(n3323), .A0N(n2728), .A1N(
Raw_mant_NRM_SWR[6]), .Y(n2022) );
AOI32X1TS U2569 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n2728), .A2(n3323), .B0(
Raw_mant_NRM_SWR[5]), .B1(n2728), .Y(n2017) );
NOR2BX2TS U2570 ( .AN(n2018), .B(Raw_mant_NRM_SWR[43]), .Y(n2075) );
NOR3X2TS U2571 ( .A(Raw_mant_NRM_SWR[28]), .B(Raw_mant_NRM_SWR[29]), .C(
n2748), .Y(n2045) );
AOI211X1TS U2572 ( .A0(n2060), .A1(Raw_mant_NRM_SWR[16]), .B0(n2756), .C0(
n2740), .Y(n2061) );
OAI221XLTS U2573 ( .A0(n3335), .A1(intDX_EWSW[17]), .B0(n3418), .B1(
intDX_EWSW[24]), .C0(n2501), .Y(n2502) );
OAI221X1TS U2574 ( .A0(n3331), .A1(intDX_EWSW[3]), .B0(n3412), .B1(
intDX_EWSW[2]), .C0(n2515), .Y(n2518) );
OAI221X1TS U2575 ( .A0(n3337), .A1(intDX_EWSW[25]), .B0(n3421), .B1(
intDX_EWSW[32]), .C0(n2494), .Y(n2495) );
AOI211XLTS U2576 ( .A0(intDX_EWSW[16]), .A1(n3425), .B0(n2237), .C0(n2243),
.Y(n2234) );
OAI221X1TS U2577 ( .A0(n3408), .A1(intDX_EWSW[10]), .B0(n3415), .B1(
intDX_EWSW[12]), .C0(n2507), .Y(n2510) );
OAI221X1TS U2578 ( .A0(n3411), .A1(intDX_EWSW[21]), .B0(n3422), .B1(
intDX_EWSW[48]), .C0(n2500), .Y(n2503) );
AOI211X1TS U2579 ( .A0(intDX_EWSW[52]), .A1(n3434), .B0(n2187), .C0(n2302),
.Y(n2304) );
AOI221X1TS U2580 ( .A0(n3434), .A1(intDX_EWSW[52]), .B0(intDX_EWSW[53]),
.B1(n3313), .C0(n2461), .Y(n2473) );
AOI222X1TS U2581 ( .A0(n2435), .A1(intDX_EWSW[52]), .B0(DMP_EXP_EWSW[52]),
.B1(n1933), .C0(intDY_EWSW[52]), .C1(n1827), .Y(n2338) );
NOR3X1TS U2582 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[39]), .C(
n2744), .Y(n2013) );
NOR2X2TS U2583 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[39]), .Y(
n2742) );
AOI211X2TS U2584 ( .A0(intDX_EWSW[44]), .A1(n3445), .B0(n2270), .C0(n2279),
.Y(n2277) );
AOI21X2TS U2585 ( .A0(Data_array_SWR[17]), .A1(n3125), .B0(n3092), .Y(n3168)
);
OAI31X1TS U2586 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2741), .A2(
Raw_mant_NRM_SWR[24]), .B0(n2046), .Y(n2051) );
NOR2X1TS U2587 ( .A(Raw_mant_NRM_SWR[47]), .B(n2012), .Y(n2018) );
OAI221XLTS U2588 ( .A0(n3334), .A1(intDX_EWSW[5]), .B0(n3420), .B1(
intDX_EWSW[28]), .C0(n2514), .Y(n2519) );
NOR3X2TS U2589 ( .A(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[20]), .C(
n2067), .Y(n2733) );
AO22XLTS U2590 ( .A0(n2792), .A1(n2453), .B0(n2877), .B1(n2790), .Y(n1978)
);
AO22XLTS U2591 ( .A0(n2792), .A1(n2877), .B0(n2859), .B1(n2790), .Y(n1991)
);
OAI21XLTS U2592 ( .A0(intDX_EWSW[1]), .A1(n3449), .B0(intDX_EWSW[0]), .Y(
n2208) );
NOR2XLTS U2593 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[45]), .Y(
n2034) );
OAI21XLTS U2594 ( .A0(intDY_EWSW[33]), .A1(n3373), .B0(intDY_EWSW[32]), .Y(
n2287) );
NOR2XLTS U2595 ( .A(Raw_mant_NRM_SWR[52]), .B(Raw_mant_NRM_SWR[51]), .Y(
n2036) );
NOR2XLTS U2596 ( .A(n2270), .B(intDX_EWSW[44]), .Y(n2271) );
OAI21XLTS U2597 ( .A0(intDY_EWSW[29]), .A1(n3383), .B0(intDY_EWSW[28]), .Y(
n2194) );
OAI21XLTS U2598 ( .A0(n3457), .A1(n3056), .B0(n3055), .Y(n3057) );
NOR2XLTS U2599 ( .A(n2115), .B(n2783), .Y(n2118) );
INVX2TS U2600 ( .A(n2035), .Y(n2765) );
OAI21XLTS U2601 ( .A0(n3456), .A1(n3117), .B0(n3103), .Y(n3104) );
OAI211XLTS U2602 ( .A0(n3168), .A1(n2127), .B0(n3094), .C0(n3093), .Y(n3095)
);
NOR2XLTS U2603 ( .A(n2326), .B(n1933), .Y(n2327) );
OAI2BB1X1TS U2604 ( .A0N(Shift_amount_SHT1_EWR[1]), .A1N(n1969), .B0(n2776),
.Y(n2533) );
OAI21XLTS U2605 ( .A0(DmP_EXP_EWSW[55]), .A1(n3354), .B0(n2834), .Y(n2831)
);
OAI21XLTS U2606 ( .A0(n3021), .A1(DMP_SFG[0]), .B0(n3034), .Y(n3022) );
OAI21XLTS U2607 ( .A0(n3445), .A1(n2871), .B0(n2374), .Y(n1243) );
OAI21XLTS U2608 ( .A0(n3437), .A1(n2871), .B0(n2375), .Y(n1257) );
OAI21XLTS U2609 ( .A0(n3452), .A1(n2872), .B0(n2331), .Y(n1271) );
OAI21XLTS U2610 ( .A0(n3347), .A1(n2872), .B0(n2363), .Y(n1285) );
OAI21XLTS U2611 ( .A0(n3340), .A1(n2451), .B0(n2406), .Y(n1549) );
OAI21XLTS U2612 ( .A0(n3343), .A1(n2451), .B0(n2438), .Y(n1567) );
OAI21XLTS U2613 ( .A0(n3338), .A1(n2433), .B0(n2421), .Y(n1581) );
OAI21XLTS U2614 ( .A0(n3410), .A1(n2433), .B0(n2417), .Y(n1595) );
OAI21XLTS U2615 ( .A0(n3333), .A1(n2874), .B0(n2392), .Y(n1608) );
BUFX4TS U2616 ( .A(n3467), .Y(n3037) );
INVX4TS U2617 ( .A(n3467), .Y(n3075) );
INVX4TS U2618 ( .A(n3295), .Y(n3292) );
NOR2XLTS U2619 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1998) );
AOI32X4TS U2620 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1998), .B1(n3431), .Y(n2792)
);
BUFX4TS U2621 ( .A(n2386), .Y(n2529) );
BUFX3TS U2622 ( .A(n3463), .Y(n2877) );
INVX2TS U2623 ( .A(n2792), .Y(n2790) );
BUFX4TS U2624 ( .A(n3527), .Y(n3088) );
AOI2BB2XLTS U2625 ( .B0(n1906), .B1(n2986), .A0N(n2986), .A1N(n1906), .Y(
n2972) );
AOI2BB2XLTS U2626 ( .B0(n1907), .B1(n2986), .A0N(n2986), .A1N(n1907), .Y(
n2969) );
AOI2BB2XLTS U2627 ( .B0(n1908), .B1(n2986), .A0N(n2986), .A1N(n1908), .Y(
n2966) );
AOI2BB2XLTS U2628 ( .B0(n1909), .B1(n2986), .A0N(n2986), .A1N(n1909), .Y(
n2963) );
AOI2BB2XLTS U2629 ( .B0(n1910), .B1(n2986), .A0N(n2986), .A1N(n1910), .Y(
n2003) );
INVX4TS U2630 ( .A(n3467), .Y(n3076) );
AOI2BB2XLTS U2631 ( .B0(DmP_mant_SFG_SWR[45]), .B1(n3076), .A0N(n1999),
.A1N(DmP_mant_SFG_SWR[45]), .Y(n2960) );
AOI2BB2XLTS U2632 ( .B0(n1911), .B1(n3075), .A0N(n2986), .A1N(n1911), .Y(
n2957) );
AOI2BB2XLTS U2633 ( .B0(n1912), .B1(n3076), .A0N(n2986), .A1N(n1912), .Y(
n2954) );
INVX4TS U2634 ( .A(n3467), .Y(n1999) );
AOI22X1TS U2635 ( .A0(n1999), .A1(DmP_mant_SFG_SWR[42]), .B0(n1985), .B1(
n3037), .Y(n2009) );
AOI22X1TS U2636 ( .A0(n3075), .A1(DmP_mant_SFG_SWR[41]), .B0(n1984), .B1(
n3037), .Y(n2951) );
AOI22X1TS U2637 ( .A0(n3076), .A1(DmP_mant_SFG_SWR[40]), .B0(n1983), .B1(
n3037), .Y(n2006) );
AOI22X1TS U2638 ( .A0(n1999), .A1(DmP_mant_SFG_SWR[39]), .B0(n1982), .B1(
n3037), .Y(n2948) );
AOI22X1TS U2639 ( .A0(DmP_mant_SFG_SWR[38]), .A1(n3526), .B0(n3037), .B1(
n1981), .Y(n2945) );
AOI22X1TS U2640 ( .A0(DmP_mant_SFG_SWR[37]), .A1(n3526), .B0(n3037), .B1(
n1979), .Y(n2942) );
AOI22X1TS U2641 ( .A0(DmP_mant_SFG_SWR[36]), .A1(n3526), .B0(n3037), .B1(
n1977), .Y(n2939) );
AOI22X1TS U2642 ( .A0(DmP_mant_SFG_SWR[35]), .A1(n3526), .B0(n3037), .B1(
n1976), .Y(n2184) );
AOI22X1TS U2643 ( .A0(DmP_mant_SFG_SWR[34]), .A1(n3526), .B0(n3037), .B1(
n1975), .Y(n2936) );
AOI22X1TS U2644 ( .A0(DmP_mant_SFG_SWR[33]), .A1(n3526), .B0(n3037), .B1(
n1974), .Y(n2933) );
AOI22X1TS U2645 ( .A0(DmP_mant_SFG_SWR[32]), .A1(n3526), .B0(n3037), .B1(
n1973), .Y(n2930) );
AOI22X1TS U2646 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n3526), .B0(n3467), .B1(
n1972), .Y(n2905) );
AOI22X1TS U2647 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n3075), .B0(n3037), .B1(
n1971), .Y(n2902) );
AOI22X1TS U2648 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n3076), .B0(n3467), .B1(
n1994), .Y(n2899) );
AOI22X1TS U2649 ( .A0(DmP_mant_SFG_SWR[19]), .A1(n1999), .B0(n3467), .B1(
n1993), .Y(n2099) );
AOI22X1TS U2650 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n3075), .B0(n3467), .B1(
n1992), .Y(n2096) );
AOI22X1TS U2651 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n3076), .B0(n3037), .B1(
n1990), .Y(n2896) );
AOI22X1TS U2652 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n1999), .B0(n3037), .B1(
n1989), .Y(n2893) );
AOI22X1TS U2653 ( .A0(n3075), .A1(DmP_mant_SFG_SWR[15]), .B0(n1988), .B1(
n3037), .Y(n2890) );
AOI22X1TS U2654 ( .A0(n3076), .A1(DmP_mant_SFG_SWR[14]), .B0(n1987), .B1(
n3037), .Y(n2887) );
AOI22X2TS U2655 ( .A0(DmP_mant_SFG_SWR[12]), .A1(n3526), .B0(n3467), .B1(
n1986), .Y(n3133) );
OAI2BB1X1TS U2656 ( .A0N(n1896), .A1N(DMP_SFG[11]), .B0(n2000), .Y(n2886) );
BUFX4TS U2657 ( .A(n3527), .Y(n3134) );
NOR2X1TS U2658 ( .A(Shift_reg_FLAGS_7[1]), .B(n2882), .Y(n2063) );
BUFX4TS U2659 ( .A(n2815), .Y(n2712) );
NOR2X2TS U2660 ( .A(Shift_reg_FLAGS_7[1]), .B(n2859), .Y(n2818) );
AOI22X1TS U2661 ( .A0(n2712), .A1(shift_value_SHT2_EWR[3]), .B0(n2818), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n2033) );
NOR2X1TS U2662 ( .A(Raw_mant_NRM_SWR[18]), .B(Raw_mant_NRM_SWR[17]), .Y(
n2732) );
NOR2X1TS U2663 ( .A(Raw_mant_NRM_SWR[50]), .B(Raw_mant_NRM_SWR[49]), .Y(
n2035) );
NAND2X1TS U2664 ( .A(n2035), .B(n2763), .Y(n2011) );
NAND2X2TS U2665 ( .A(n2045), .B(n3362), .Y(n2026) );
NAND2X1TS U2666 ( .A(Raw_mant_NRM_SWR[21]), .B(n2014), .Y(n2751) );
OAI211X1TS U2667 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n2017), .B0(n2751), .C0(
n2016), .Y(n2074) );
AOI32X1TS U2668 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n2727), .A2(n3311), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2727), .Y(n2020) );
NAND2X1TS U2669 ( .A(Raw_mant_NRM_SWR[43]), .B(n2018), .Y(n2041) );
AOI21X1TS U2670 ( .A0(n2024), .A1(Raw_mant_NRM_SWR[23]), .B0(n2021), .Y(
n2086) );
OAI31X1TS U2671 ( .A0(Raw_mant_NRM_SWR[42]), .A1(n2022), .A2(
Raw_mant_NRM_SWR[40]), .B0(n2075), .Y(n2769) );
NOR3BX1TS U2672 ( .AN(n2080), .B(n2023), .C(Raw_mant_NRM_SWR[47]), .Y(n2030)
);
OAI2BB1X1TS U2673 ( .A0N(n2025), .A1N(Raw_mant_NRM_SWR[30]), .B0(n2768), .Y(
n2757) );
OAI2BB2XLTS U2674 ( .B0(n3454), .B1(n2026), .A0N(Raw_mant_NRM_SWR[24]),
.A1N(n2046), .Y(n2029) );
OAI22X1TS U2675 ( .A0(n3311), .A1(n2055), .B0(n3460), .B1(n2027), .Y(n2028)
);
NOR4X1TS U2676 ( .A(n2030), .B(n2757), .C(n2029), .D(n2028), .Y(n2031) );
OAI21X1TS U2677 ( .A0(Raw_mant_NRM_SWR[19]), .A1(Raw_mant_NRM_SWR[20]), .B0(
n2759), .Y(n2050) );
OAI21X1TS U2678 ( .A0(n2074), .A1(n2032), .B0(Shift_reg_FLAGS_7[1]), .Y(
n2758) );
NAND2X1TS U2679 ( .A(n2033), .B(n2758), .Y(n1629) );
NAND2X1TS U2680 ( .A(n2065), .B(Raw_mant_NRM_SWR[28]), .Y(n2766) );
OR2X1TS U2681 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .Y(n2038) );
OAI32X1TS U2682 ( .A0(n2038), .A1(n2037), .A2(n2765), .B0(n2036), .B1(n2038),
.Y(n2039) );
INVX2TS U2683 ( .A(n2039), .Y(n2040) );
INVX2TS U2684 ( .A(n2042), .Y(n2062) );
OR2X1TS U2685 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[31]), .Y(n2044) );
AOI22X1TS U2686 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n2045), .B0(n2761), .B1(
n2044), .Y(n2052) );
INVX2TS U2687 ( .A(n2084), .Y(n2753) );
NOR4X2TS U2688 ( .A(Raw_mant_NRM_SWR[1]), .B(Raw_mant_NRM_SWR[2]), .C(n2753),
.D(n3329), .Y(n2741) );
NOR2XLTS U2689 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .Y(n2059)
);
NAND2X1TS U2690 ( .A(Raw_mant_NRM_SWR[15]), .B(n2053), .Y(n2081) );
AOI32X1TS U2691 ( .A0(n2081), .A1(n3308), .A2(n3327), .B0(n2771), .B1(n2081),
.Y(n2054) );
INVX2TS U2692 ( .A(n2054), .Y(n2057) );
OAI211X1TS U2693 ( .A0(n2059), .A1(n2058), .B0(n2057), .C0(n2056), .Y(n2740)
);
BUFX3TS U2694 ( .A(n2063), .Y(n2811) );
NOR2BX4TS U2695 ( .AN(n2533), .B(n2811), .Y(n2554) );
OR2X1TS U2696 ( .A(Raw_mant_NRM_SWR[28]), .B(n2748), .Y(n2072) );
NOR3BX1TS U2697 ( .AN(Raw_mant_NRM_SWR[31]), .B(Raw_mant_NRM_SWR[32]), .C(
n2064), .Y(n2069) );
AOI22X1TS U2698 ( .A0(n1950), .A1(n2066), .B0(n2065), .B1(
Raw_mant_NRM_SWR[29]), .Y(n2747) );
OAI31X1TS U2699 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n3398), .A2(n2067), .B0(
n2747), .Y(n2068) );
AOI211X1TS U2700 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2080), .B0(n2069), .C0(
n2068), .Y(n2071) );
NAND2X1TS U2701 ( .A(Raw_mant_NRM_SWR[13]), .B(n2070), .Y(n2737) );
AOI211X1TS U2702 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n2726), .B0(n2074), .C0(
n2073), .Y(n2770) );
NAND4XLTS U2703 ( .A(n2742), .B(n2075), .C(Raw_mant_NRM_SWR[37]), .D(n3365),
.Y(n2078) );
AOI21X1TS U2704 ( .A0(Raw_mant_NRM_SWR[49]), .A1(n3387), .B0(
Raw_mant_NRM_SWR[51]), .Y(n2076) );
AOI2BB1XLTS U2705 ( .A0N(Raw_mant_NRM_SWR[52]), .A1N(n2076), .B0(
Raw_mant_NRM_SWR[53]), .Y(n2077) );
OAI22X1TS U2706 ( .A0(Raw_mant_NRM_SWR[38]), .A1(n2078), .B0(
Raw_mant_NRM_SWR[54]), .B1(n2077), .Y(n2079) );
AOI31XLTS U2707 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n2080), .A2(n3376), .B0(
n2079), .Y(n2082) );
INVX2TS U2708 ( .A(n2777), .Y(n2087) );
INVX4TS U2709 ( .A(n2777), .Y(n2667) );
NAND2X1TS U2710 ( .A(n1926), .B(n1969), .Y(n2549) );
AOI22X1TS U2711 ( .A0(Raw_mant_NRM_SWR[51]), .A1(n2667), .B0(n2623), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2090) );
NOR2X2TS U2712 ( .A(n1969), .B(n2088), .Y(n2553) );
BUFX3TS U2713 ( .A(n2553), .Y(n2631) );
NOR2X1TS U2714 ( .A(Shift_reg_FLAGS_7[1]), .B(n1926), .Y(n2557) );
INVX2TS U2715 ( .A(n2557), .Y(n2648) );
AOI22X1TS U2716 ( .A0(Raw_mant_NRM_SWR[52]), .A1(n2631), .B0(n2644), .B1(
n1927), .Y(n2089) );
NAND2X1TS U2717 ( .A(n2090), .B(n2089), .Y(n2590) );
AOI22X1TS U2718 ( .A0(n2815), .A1(Data_array_SWR[0]), .B0(n2554), .B1(n2590),
.Y(n2092) );
AOI22X1TS U2719 ( .A0(Raw_mant_NRM_SWR[54]), .A1(n2631), .B0(
Raw_mant_NRM_SWR[53]), .B1(n1914), .Y(n2091) );
NAND2X1TS U2720 ( .A(n2092), .B(n2091), .Y(n1631) );
BUFX3TS U2721 ( .A(n3499), .Y(n3493) );
BUFX3TS U2722 ( .A(n3518), .Y(n3520) );
BUFX3TS U2723 ( .A(n3485), .Y(n3512) );
BUFX3TS U2724 ( .A(n3516), .Y(n3513) );
BUFX3TS U2725 ( .A(n3495), .Y(n3515) );
BUFX3TS U2726 ( .A(n3519), .Y(n3481) );
BUFX3TS U2727 ( .A(n3512), .Y(n3504) );
BUFX3TS U2728 ( .A(n3512), .Y(n3469) );
BUFX3TS U2729 ( .A(n3530), .Y(n3502) );
BUFX3TS U2730 ( .A(n3525), .Y(n3474) );
BUFX3TS U2731 ( .A(n3481), .Y(n3476) );
BUFX3TS U2732 ( .A(n3491), .Y(n3473) );
BUFX3TS U2733 ( .A(n3520), .Y(n3471) );
BUFX3TS U2734 ( .A(n3473), .Y(n3470) );
AO22XLTS U2735 ( .A0(n1970), .A1(ZERO_FLAG_NRM), .B0(n1969), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n1215) );
AO22XLTS U2736 ( .A0(n1970), .A1(SIGN_FLAG_NRM), .B0(n1969), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n1206) );
BUFX4TS U2737 ( .A(n3527), .Y(n2921) );
AO22XLTS U2738 ( .A0(n1825), .A1(DMP_SFG[57]), .B0(n2921), .B1(
DMP_exp_NRM_EW[5]), .Y(n1358) );
AO22XLTS U2739 ( .A0(n3090), .A1(DMP_SFG[56]), .B0(n2921), .B1(
DMP_exp_NRM_EW[4]), .Y(n1363) );
AO22XLTS U2740 ( .A0(n1825), .A1(ZERO_FLAG_SFG), .B0(n2921), .B1(
ZERO_FLAG_NRM), .Y(n1216) );
AO22XLTS U2741 ( .A0(n3090), .A1(DMP_SFG[59]), .B0(n2921), .B1(
DMP_exp_NRM_EW[7]), .Y(n1348) );
AO22XLTS U2742 ( .A0(n3136), .A1(DMP_SFG[60]), .B0(n2921), .B1(
DMP_exp_NRM_EW[8]), .Y(n1343) );
AO22XLTS U2743 ( .A0(n1825), .A1(DMP_SFG[58]), .B0(n2921), .B1(
DMP_exp_NRM_EW[6]), .Y(n1353) );
AO22XLTS U2744 ( .A0(n3024), .A1(DMP_SFG[62]), .B0(n2921), .B1(
DMP_exp_NRM_EW[10]), .Y(n1333) );
AO22XLTS U2745 ( .A0(n1825), .A1(DMP_SFG[55]), .B0(n2921), .B1(
DMP_exp_NRM_EW[3]), .Y(n1368) );
AO22XLTS U2746 ( .A0(n3024), .A1(SIGN_FLAG_SFG), .B0(n2921), .B1(
SIGN_FLAG_NRM), .Y(n1207) );
AOI2BB2X1TS U2747 ( .B0(n1915), .B1(n3075), .A0N(n2986), .A1N(n1915), .Y(
n3087) );
OAI211XLTS U2748 ( .A0(DMP_SFG[5]), .A1(n3050), .B0(n1932), .C0(n3087), .Y(
n2093) );
OAI2BB1X1TS U2749 ( .A0N(n3050), .A1N(DMP_SFG[5]), .B0(n2093), .Y(n3074) );
AOI2BB2X1TS U2750 ( .B0(DmP_mant_SFG_SWR[8]), .B1(n1999), .A0N(n3075), .A1N(
DmP_mant_SFG_SWR[8]), .Y(n3096) );
AO22XLTS U2751 ( .A0(n3527), .A1(Raw_mant_NRM_SWR[8]), .B0(n3136), .B1(n2094), .Y(n1131) );
AO22XLTS U2752 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[18]), .B0(n3136), .B1(
n2097), .Y(n1200) );
AO22XLTS U2753 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[19]), .B0(n3136), .B1(
n2100), .Y(n1199) );
AO22XLTS U2754 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[26]), .B0(n1825), .B1(
n2103), .Y(n1192) );
INVX2TS U2755 ( .A(DP_OP_15J75_123_4372_n6), .Y(n2104) );
NAND2X1TS U2756 ( .A(n3405), .B(n2104), .Y(n2110) );
INVX2TS U2757 ( .A(n2110), .Y(n2105) );
NAND2X1TS U2758 ( .A(n3426), .B(n2105), .Y(n2113) );
NOR2XLTS U2759 ( .A(n2779), .B(exp_rslt_NRM2_EW1[1]), .Y(n2108) );
INVX2TS U2760 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n2107) );
INVX2TS U2761 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n2106) );
NAND4BXLTS U2762 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n2108), .C(n2107), .D(n2106), .Y(n2109) );
NOR2XLTS U2763 ( .A(n2109), .B(exp_rslt_NRM2_EW1[5]), .Y(n2112) );
XNOR2X1TS U2764 ( .A(DMP_exp_NRM2_EW[7]), .B(n2110), .Y(n2781) );
INVX2TS U2765 ( .A(n2781), .Y(n2124) );
INVX2TS U2766 ( .A(n2780), .Y(n2111) );
NAND4BXLTS U2767 ( .AN(n2782), .B(n2112), .C(n2124), .D(n2111), .Y(n2115) );
INVX2TS U2768 ( .A(n2113), .Y(n2114) );
NAND2X1TS U2769 ( .A(n3436), .B(n2114), .Y(n2116) );
INVX2TS U2770 ( .A(n2116), .Y(n2117) );
NAND2X1TS U2771 ( .A(n3435), .B(n2117), .Y(n2120) );
NOR2BX1TS U2772 ( .AN(n2118), .B(n2785), .Y(n2119) );
INVX2TS U2773 ( .A(n2119), .Y(n2778) );
INVX2TS U2774 ( .A(n2778), .Y(n2884) );
INVX2TS U2775 ( .A(n2120), .Y(n2121) );
CLKAND2X2TS U2776 ( .A(n3459), .B(n2121), .Y(n2126) );
NAND4XLTS U2777 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
n2779), .D(exp_rslt_NRM2_EW1[1]), .Y(n2122) );
NAND4BXLTS U2778 ( .AN(n2122), .B(n2780), .C(exp_rslt_NRM2_EW1[5]), .D(
exp_rslt_NRM2_EW1[4]), .Y(n2123) );
NOR3BXLTS U2779 ( .AN(n2782), .B(n2124), .C(n2123), .Y(n2125) );
NAND4XLTS U2780 ( .A(n2783), .B(n2126), .C(n2785), .D(n2125), .Y(n2883) );
NAND2X1TS U2781 ( .A(n3468), .B(n2883), .Y(n2876) );
INVX4TS U2782 ( .A(n2146), .Y(n3172) );
NAND2X1TS U2783 ( .A(shift_value_SHT2_EWR[2]), .B(n3386), .Y(n2128) );
NOR2X1TS U2784 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n2158) );
INVX2TS U2785 ( .A(n2158), .Y(n3056) );
AOI222X4TS U2786 ( .A0(Data_array_SWR[28]), .A1(n2159), .B0(
Data_array_SWR[25]), .B1(n3115), .C0(Data_array_SWR[32]), .C1(n3080),
.Y(n3156) );
NOR2X2TS U2787 ( .A(n3363), .B(shift_value_SHT2_EWR[5]), .Y(n3232) );
NAND2BX2TS U2788 ( .AN(shift_value_SHT2_EWR[5]), .B(n3363), .Y(n2152) );
NOR2BX1TS U2789 ( .AN(n3080), .B(n2152), .Y(n2147) );
BUFX3TS U2790 ( .A(n2147), .Y(n3198) );
NOR2X1TS U2791 ( .A(n3056), .B(n2152), .Y(n2996) );
BUFX3TS U2792 ( .A(n2996), .Y(n3229) );
AOI22X1TS U2793 ( .A0(n1949), .A1(n3198), .B0(Data_array_SWR[16]), .B1(n3229), .Y(n2130) );
NOR2X1TS U2794 ( .A(n2152), .B(n3117), .Y(n2135) );
BUFX3TS U2795 ( .A(n2135), .Y(n3180) );
NOR2X1TS U2796 ( .A(n2152), .B(n2128), .Y(n2136) );
CLKBUFX3TS U2797 ( .A(n2136), .Y(n3122) );
AOI22X1TS U2798 ( .A0(Data_array_SWR[21]), .A1(n3180), .B0(n1955), .B1(n3122), .Y(n2129) );
OAI211X1TS U2799 ( .A0(n3156), .A1(n2127), .B0(n2130), .C0(n2129), .Y(n3268)
);
AO22XLTS U2800 ( .A0(n3172), .A1(n3268), .B0(final_result_ieee[25]), .B1(
n3240), .Y(n1115) );
AOI22X1TS U2801 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n2786), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n3332), .Y(n2789) );
NAND2X1TS U2802 ( .A(beg_OP), .B(n2789), .Y(n2131) );
INVX2TS U2803 ( .A(n2131), .Y(n2799) );
BUFX4TS U2804 ( .A(n2799), .Y(n2793) );
AO22XLTS U2805 ( .A0(n2793), .A1(Data_X[42]), .B0(n2795), .B1(intDX_EWSW[42]), .Y(n1773) );
AO22XLTS U2806 ( .A0(n2793), .A1(Data_X[41]), .B0(n2795), .B1(intDX_EWSW[41]), .Y(n1774) );
AO22XLTS U2807 ( .A0(n2798), .A1(Data_X[34]), .B0(n2795), .B1(intDX_EWSW[34]), .Y(n1781) );
AO22XLTS U2808 ( .A0(n2793), .A1(Data_X[43]), .B0(n2795), .B1(intDX_EWSW[43]), .Y(n1772) );
AO22XLTS U2809 ( .A0(n2798), .A1(Data_X[35]), .B0(n2795), .B1(intDX_EWSW[35]), .Y(n1780) );
AO22XLTS U2810 ( .A0(n2798), .A1(Data_X[36]), .B0(n2795), .B1(intDX_EWSW[36]), .Y(n1779) );
AO22XLTS U2811 ( .A0(n2803), .A1(intDY_EWSW[55]), .B0(n2793), .B1(Data_Y[55]), .Y(n1694) );
AO22XLTS U2812 ( .A0(n2803), .A1(intDY_EWSW[40]), .B0(n2794), .B1(Data_Y[40]), .Y(n1709) );
AO22XLTS U2813 ( .A0(n2806), .A1(intDY_EWSW[57]), .B0(n2793), .B1(Data_Y[57]), .Y(n1692) );
AO22XLTS U2814 ( .A0(n2806), .A1(intDY_EWSW[58]), .B0(n2793), .B1(Data_Y[58]), .Y(n1691) );
AO22XLTS U2815 ( .A0(n2806), .A1(intDY_EWSW[53]), .B0(n2793), .B1(Data_Y[53]), .Y(n1696) );
AO22XLTS U2816 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[27]), .B0(n3024), .B1(
n2134), .Y(n1191) );
AO22XLTS U2817 ( .A0(n2803), .A1(intDY_EWSW[41]), .B0(n2808), .B1(Data_Y[41]), .Y(n1708) );
AO22XLTS U2818 ( .A0(n2803), .A1(intDY_EWSW[42]), .B0(n2808), .B1(Data_Y[42]), .Y(n1707) );
AOI222X4TS U2819 ( .A0(Data_array_SWR[30]), .A1(n2159), .B0(n1943), .B1(
n3115), .C0(Data_array_SWR[33]), .C1(n3080), .Y(n3169) );
NAND2X2TS U2820 ( .A(n3363), .B(shift_value_SHT2_EWR[5]), .Y(n3201) );
BUFX3TS U2821 ( .A(n2135), .Y(n3228) );
AOI22X1TS U2822 ( .A0(Data_array_SWR[11]), .A1(n3198), .B0(
Data_array_SWR[14]), .B1(n3228), .Y(n2138) );
BUFX3TS U2823 ( .A(n2136), .Y(n3227) );
AOI22X1TS U2824 ( .A0(Data_array_SWR[9]), .A1(n3227), .B0(n1944), .B1(n3229),
.Y(n2137) );
OAI211X1TS U2825 ( .A0(n3169), .A1(n3201), .B0(n2138), .C0(n2137), .Y(n2182)
);
AOI22X1TS U2826 ( .A0(Data_array_SWR[30]), .A1(n3080), .B0(
Data_array_SWR[33]), .B1(n2142), .Y(n2140) );
BUFX4TS U2827 ( .A(n2159), .Y(n3125) );
INVX4TS U2828 ( .A(n3056), .Y(n3189) );
AOI22X1TS U2829 ( .A0(n1943), .A1(n3125), .B0(Data_array_SWR[23]), .B1(n3189), .Y(n2139) );
NAND2X2TS U2830 ( .A(n2140), .B(n2139), .Y(n3163) );
NOR2XLTS U2831 ( .A(n2152), .B(left_right_SHT2), .Y(n2141) );
BUFX3TS U2832 ( .A(n2141), .Y(n3223) );
BUFX3TS U2833 ( .A(n2142), .Y(n3054) );
BUFX4TS U2834 ( .A(n3080), .Y(n3188) );
AOI22X1TS U2835 ( .A0(Data_array_SWR[23]), .A1(n3054), .B0(n1936), .B1(n3188), .Y(n2144) );
AOI22X1TS U2836 ( .A0(n1952), .A1(n3125), .B0(Data_array_SWR[17]), .B1(n3189), .Y(n2143) );
NAND2X1TS U2837 ( .A(n2144), .B(n2143), .Y(n3164) );
NOR2XLTS U2838 ( .A(n3361), .B(n2127), .Y(n2145) );
OAI2BB2XLTS U2839 ( .B0(n3283), .B1(n2146), .A0N(final_result_ieee[39]),
.A1N(n1996), .Y(n1106) );
AOI222X4TS U2840 ( .A0(n1948), .A1(n3188), .B0(Data_array_SWR[29]), .B1(
n2159), .C0(Data_array_SWR[26]), .C1(n3189), .Y(n3137) );
BUFX3TS U2841 ( .A(n2147), .Y(n3226) );
AOI22X1TS U2842 ( .A0(n1945), .A1(n3229), .B0(n1958), .B1(n3226), .Y(n2149)
);
AOI22X1TS U2843 ( .A0(Data_array_SWR[8]), .A1(n3227), .B0(Data_array_SWR[13]), .B1(n3228), .Y(n2148) );
OAI211X1TS U2844 ( .A0(n3137), .A1(n3201), .B0(n2149), .C0(n2148), .Y(n2157)
);
AOI22X1TS U2845 ( .A0(Data_array_SWR[34]), .A1(n2142), .B0(
Data_array_SWR[31]), .B1(n3188), .Y(n2151) );
AOI22X1TS U2846 ( .A0(Data_array_SWR[27]), .A1(n2159), .B0(
Data_array_SWR[24]), .B1(n3115), .Y(n2150) );
NAND2X2TS U2847 ( .A(n2151), .B(n2150), .Y(n3140) );
NOR2XLTS U2848 ( .A(n3361), .B(n2152), .Y(n2153) );
BUFX3TS U2849 ( .A(n2153), .Y(n3221) );
AOI22X1TS U2850 ( .A0(Data_array_SWR[22]), .A1(n2142), .B0(n1934), .B1(n3080), .Y(n2155) );
AOI22X1TS U2851 ( .A0(n1954), .A1(n2159), .B0(n1956), .B1(n3115), .Y(n2154)
);
NAND2X1TS U2852 ( .A(n2155), .B(n2154), .Y(n3141) );
OAI2BB2XLTS U2853 ( .B0(n3145), .B1(n2146), .A0N(final_result_ieee[10]),
.A1N(n1996), .Y(n1121) );
OAI2BB2XLTS U2854 ( .B0(n3284), .B1(n2146), .A0N(final_result_ieee[40]),
.A1N(n1996), .Y(n1120) );
AOI222X4TS U2855 ( .A0(Data_array_SWR[34]), .A1(n3080), .B0(
Data_array_SWR[31]), .B1(n2159), .C0(Data_array_SWR[27]), .C1(n2158),
.Y(n3158) );
AOI22X1TS U2856 ( .A0(n1947), .A1(n3229), .B0(n1959), .B1(n3226), .Y(n2161)
);
AOI22X1TS U2857 ( .A0(Data_array_SWR[15]), .A1(n3180), .B0(n1951), .B1(n3227), .Y(n2160) );
OAI211X1TS U2858 ( .A0(n3158), .A1(n3201), .B0(n2161), .C0(n2160), .Y(n2178)
);
AOI22X1TS U2859 ( .A0(n1948), .A1(n3054), .B0(Data_array_SWR[29]), .B1(n3188), .Y(n2163) );
AOI22X1TS U2860 ( .A0(Data_array_SWR[26]), .A1(n2159), .B0(
Data_array_SWR[22]), .B1(n3189), .Y(n2162) );
NAND2X2TS U2861 ( .A(n2163), .B(n2162), .Y(n3148) );
AOI22X1TS U2862 ( .A0(Data_array_SWR[24]), .A1(n3054), .B0(n1935), .B1(n3080), .Y(n2165) );
AOI22X1TS U2863 ( .A0(n1957), .A1(n3115), .B0(n1953), .B1(n3125), .Y(n2164)
);
NAND2X1TS U2864 ( .A(n2165), .B(n2164), .Y(n3149) );
OAI2BB2XLTS U2865 ( .B0(n3282), .B1(n2146), .A0N(final_result_ieee[38]),
.A1N(n1996), .Y(n1116) );
AOI22X1TS U2866 ( .A0(Data_array_SWR[31]), .A1(n2142), .B0(
Data_array_SWR[27]), .B1(n3188), .Y(n2166) );
OAI21XLTS U2867 ( .A0(n3456), .A1(n3056), .B0(n2166), .Y(n2167) );
AOI21X1TS U2868 ( .A0(Data_array_SWR[24]), .A1(n3125), .B0(n2167), .Y(n2174)
);
AOI22X1TS U2869 ( .A0(Data_array_SWR[15]), .A1(n3227), .B0(n1959), .B1(n3229), .Y(n2171) );
NAND2X1TS U2870 ( .A(n3115), .B(n2168), .Y(n3216) );
OAI2BB2XLTS U2871 ( .B0(n3429), .B1(n3216), .A0N(n1957), .A1N(n3226), .Y(
n2169) );
AOI21X1TS U2872 ( .A0(n1953), .A1(n3228), .B0(n2169), .Y(n2170) );
OAI211X1TS U2873 ( .A0(n2174), .A1(n2127), .B0(n2171), .C0(n2170), .Y(n2180)
);
INVX2TS U2874 ( .A(n3173), .Y(n2179) );
AOI22X1TS U2875 ( .A0(Data_array_SWR[26]), .A1(n3054), .B0(
Data_array_SWR[22]), .B1(n3188), .Y(n2173) );
AOI22X1TS U2876 ( .A0(n1954), .A1(n3115), .B0(n1934), .B1(n3125), .Y(n2172)
);
NAND2X1TS U2877 ( .A(n2173), .B(n2172), .Y(n3009) );
OAI2BB2XLTS U2878 ( .B0(n3273), .B1(n2146), .A0N(final_result_ieee[30]),
.A1N(n1996), .Y(n1127) );
NOR2X2TS U2879 ( .A(shift_value_SHT2_EWR[5]), .B(n3303), .Y(n3236) );
NAND2X1TS U2880 ( .A(shift_value_SHT2_EWR[4]), .B(n3189), .Y(n3058) );
AOI22X1TS U2881 ( .A0(Data_array_SWR[13]), .A1(n3198), .B0(n1958), .B1(n3227), .Y(n2177) );
AOI22X1TS U2882 ( .A0(n1956), .A1(n3180), .B0(Data_array_SWR[8]), .B1(n3229),
.Y(n2176) );
AOI22X1TS U2883 ( .A0(n3232), .A1(n3009), .B0(n2168), .B1(n2179), .Y(n2175)
);
NAND3XLTS U2884 ( .A(n2177), .B(n2176), .C(n2175), .Y(n2181) );
AOI22X1TS U2885 ( .A0(n3236), .A1(n1900), .B0(n3303), .B1(n2181), .Y(n3256)
);
OAI2BB2XLTS U2886 ( .B0(n3256), .B1(n2146), .A0N(final_result_ieee[14]),
.A1N(n1996), .Y(n1126) );
OAI2BB2XLTS U2887 ( .B0(n3254), .B1(n2146), .A0N(final_result_ieee[12]),
.A1N(n1996), .Y(n1119) );
OAI2BB2XLTS U2888 ( .B0(n3263), .B1(n2146), .A0N(final_result_ieee[20]),
.A1N(n1996), .Y(n1128) );
NOR2X2TS U2889 ( .A(shift_value_SHT2_EWR[5]), .B(left_right_SHT2), .Y(n3237)
);
AOI22X1TS U2890 ( .A0(n3239), .A1(n2181), .B0(n3237), .B1(n1900), .Y(n3280)
);
OAI2BB2XLTS U2891 ( .B0(n3280), .B1(n2146), .A0N(final_result_ieee[36]),
.A1N(n1996), .Y(n1125) );
OAI2BB2XLTS U2892 ( .B0(n2985), .B1(n2146), .A0N(final_result_ieee[11]),
.A1N(n1996), .Y(n1107) );
AO22XLTS U2893 ( .A0(n2803), .A1(intDY_EWSW[46]), .B0(n2804), .B1(Data_Y[46]), .Y(n1703) );
AO22XLTS U2894 ( .A0(n2803), .A1(intDY_EWSW[43]), .B0(n2804), .B1(Data_Y[43]), .Y(n1706) );
AO22XLTS U2895 ( .A0(n2806), .A1(intDY_EWSW[45]), .B0(n2804), .B1(Data_Y[45]), .Y(n1704) );
AO22XLTS U2896 ( .A0(n2803), .A1(intDY_EWSW[44]), .B0(n2804), .B1(Data_Y[44]), .Y(n1705) );
BUFX4TS U2897 ( .A(n2793), .Y(n2796) );
AO22XLTS U2898 ( .A0(n2803), .A1(intDY_EWSW[50]), .B0(n2796), .B1(Data_Y[50]), .Y(n1699) );
AO22XLTS U2899 ( .A0(n2806), .A1(intDY_EWSW[56]), .B0(n2796), .B1(Data_Y[56]), .Y(n1693) );
BUFX3TS U2900 ( .A(n2793), .Y(n2801) );
AO22XLTS U2901 ( .A0(n2803), .A1(intDY_EWSW[51]), .B0(n2801), .B1(Data_Y[51]), .Y(n1698) );
AO22XLTS U2902 ( .A0(n2806), .A1(intDY_EWSW[59]), .B0(n2801), .B1(Data_Y[59]), .Y(n1690) );
AO22XLTS U2903 ( .A0(n2806), .A1(intDY_EWSW[62]), .B0(n2801), .B1(Data_Y[62]), .Y(n1687) );
AO22XLTS U2904 ( .A0(n2806), .A1(intDY_EWSW[60]), .B0(n2801), .B1(Data_Y[60]), .Y(n1689) );
AO22XLTS U2905 ( .A0(n2803), .A1(intDY_EWSW[47]), .B0(n2801), .B1(Data_Y[47]), .Y(n1702) );
AO22XLTS U2906 ( .A0(n2806), .A1(intDY_EWSW[61]), .B0(n2801), .B1(Data_Y[61]), .Y(n1688) );
AO22XLTS U2907 ( .A0(n2803), .A1(intDY_EWSW[48]), .B0(n2801), .B1(Data_Y[48]), .Y(n1701) );
AO22XLTS U2908 ( .A0(n2806), .A1(intDX_EWSW[1]), .B0(n2801), .B1(Data_X[1]),
.Y(n1814) );
INVX4TS U2909 ( .A(n2804), .Y(n2802) );
AO22XLTS U2910 ( .A0(n2793), .A1(Data_X[13]), .B0(n2802), .B1(intDX_EWSW[13]), .Y(n1802) );
INVX4TS U2911 ( .A(n2796), .Y(n2800) );
AO22XLTS U2912 ( .A0(n2793), .A1(Data_X[14]), .B0(n2800), .B1(intDX_EWSW[14]), .Y(n1801) );
OAI21XLTS U2913 ( .A0(n2882), .A1(n3303), .B0(n1969), .Y(n1750) );
AOI2BB2XLTS U2914 ( .B0(beg_OP), .B1(n3332), .A0N(n3332), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2186) );
NAND3XLTS U2915 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3332), .C(
n3431), .Y(n2787) );
OAI21XLTS U2916 ( .A0(n2786), .A1(n2186), .B0(n2787), .Y(n1823) );
OAI22X1TS U2917 ( .A0(n3465), .A1(intDY_EWSW[55]), .B0(intDY_EWSW[54]), .B1(
n3358), .Y(n2302) );
NOR2BX1TS U2918 ( .AN(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n2188) );
NOR2X1TS U2919 ( .A(n3393), .B(intDY_EWSW[57]), .Y(n2256) );
NAND2X1TS U2920 ( .A(n3432), .B(intDX_EWSW[61]), .Y(n2262) );
OAI211X1TS U2921 ( .A0(intDY_EWSW[60]), .A1(n3385), .B0(n2266), .C0(n2262),
.Y(n2268) );
NAND2BXLTS U2922 ( .AN(intDY_EWSW[59]), .B(intDX_EWSW[59]), .Y(n2258) );
OAI21X1TS U2923 ( .A0(intDY_EWSW[58]), .A1(n3326), .B0(n2258), .Y(n2260) );
NOR2X1TS U2924 ( .A(n3391), .B(intDY_EWSW[49]), .Y(n2305) );
NAND2BXLTS U2925 ( .AN(intDY_EWSW[51]), .B(intDX_EWSW[51]), .Y(n2307) );
OAI21X1TS U2926 ( .A0(intDY_EWSW[50]), .A1(n3322), .B0(n2307), .Y(n2311) );
AOI211X1TS U2927 ( .A0(intDX_EWSW[48]), .A1(n3422), .B0(n2305), .C0(n2311),
.Y(n2189) );
NAND3X1TS U2928 ( .A(n2304), .B(n2313), .C(n2189), .Y(n2321) );
NOR2BX1TS U2929 ( .AN(intDX_EWSW[39]), .B(intDY_EWSW[39]), .Y(n2296) );
AOI21X1TS U2930 ( .A0(intDX_EWSW[38]), .A1(n3440), .B0(n2296), .Y(n2295) );
NAND2X1TS U2931 ( .A(n3437), .B(intDX_EWSW[37]), .Y(n2284) );
OAI211X1TS U2932 ( .A0(intDY_EWSW[36]), .A1(n3381), .B0(n2295), .C0(n2284),
.Y(n2286) );
NOR2X1TS U2933 ( .A(n3388), .B(intDY_EWSW[45]), .Y(n2270) );
OAI21X1TS U2934 ( .A0(intDY_EWSW[46]), .A1(n3366), .B0(n2269), .Y(n2279) );
OA22X1TS U2935 ( .A0(n3374), .A1(intDY_EWSW[42]), .B0(n3318), .B1(
intDY_EWSW[43]), .Y(n2275) );
NAND2BXLTS U2936 ( .AN(intDY_EWSW[41]), .B(intDX_EWSW[41]), .Y(n2191) );
NAND2BXLTS U2937 ( .AN(intDY_EWSW[40]), .B(intDX_EWSW[40]), .Y(n2190) );
NAND4XLTS U2938 ( .A(n2277), .B(n2275), .C(n2191), .D(n2190), .Y(n2319) );
NAND2BXLTS U2939 ( .AN(intDY_EWSW[32]), .B(intDX_EWSW[32]), .Y(n2192) );
OA22X1TS U2940 ( .A0(n3375), .A1(intDY_EWSW[34]), .B0(n3319), .B1(
intDY_EWSW[35]), .Y(n2290) );
OAI211XLTS U2941 ( .A0(n3373), .A1(intDY_EWSW[33]), .B0(n2192), .C0(n2290),
.Y(n2193) );
NOR4X1TS U2942 ( .A(n2321), .B(n2286), .C(n2319), .D(n2193), .Y(n2325) );
OA22X1TS U2943 ( .A0(n3379), .A1(intDY_EWSW[30]), .B0(n3320), .B1(
intDY_EWSW[31]), .Y(n2491) );
OAI2BB2XLTS U2944 ( .B0(intDX_EWSW[28]), .B1(n2194), .A0N(intDY_EWSW[29]),
.A1N(n3383), .Y(n2203) );
NAND2BXLTS U2945 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n2197) );
OAI21X1TS U2946 ( .A0(intDY_EWSW[26]), .A1(n3401), .B0(n2197), .Y(n2251) );
NAND2BXLTS U2947 ( .AN(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n2195) );
NOR2X1TS U2948 ( .A(n3389), .B(intDY_EWSW[25]), .Y(n2248) );
NOR2XLTS U2949 ( .A(n2248), .B(intDX_EWSW[24]), .Y(n2196) );
AOI22X1TS U2950 ( .A0(n2196), .A1(intDY_EWSW[24]), .B0(intDY_EWSW[25]), .B1(
n3389), .Y(n2199) );
AOI32X1TS U2951 ( .A0(n3401), .A1(n2197), .A2(intDY_EWSW[26]), .B0(
intDY_EWSW[27]), .B1(n3324), .Y(n2198) );
OAI32X1TS U2952 ( .A0(n2251), .A1(n2250), .A2(n2199), .B0(n2198), .B1(n2250),
.Y(n2202) );
OAI21XLTS U2953 ( .A0(intDY_EWSW[31]), .A1(n3320), .B0(intDY_EWSW[30]), .Y(
n2200) );
OAI2BB2XLTS U2954 ( .B0(intDX_EWSW[30]), .B1(n2200), .A0N(intDY_EWSW[31]),
.A1N(n3320), .Y(n2201) );
AOI211X1TS U2955 ( .A0(n2491), .A1(n2203), .B0(n2202), .C0(n2201), .Y(n2255)
);
OA22X1TS U2956 ( .A0(n3380), .A1(intDY_EWSW[22]), .B0(n3321), .B1(
intDY_EWSW[23]), .Y(n2499) );
NAND2BXLTS U2957 ( .AN(intDY_EWSW[21]), .B(intDX_EWSW[21]), .Y(n2204) );
OA22X1TS U2958 ( .A0(n3368), .A1(intDY_EWSW[14]), .B0(n3316), .B1(
intDY_EWSW[15]), .Y(n2505) );
NAND2BXLTS U2959 ( .AN(intDY_EWSW[13]), .B(intDX_EWSW[13]), .Y(n2205) );
OAI2BB1X1TS U2960 ( .A0N(n3334), .A1N(intDX_EWSW[5]), .B0(intDY_EWSW[4]),
.Y(n2206) );
OAI22X1TS U2961 ( .A0(intDX_EWSW[4]), .A1(n2206), .B0(n3334), .B1(
intDX_EWSW[5]), .Y(n2216) );
OAI2BB1X1TS U2962 ( .A0N(n3453), .A1N(intDX_EWSW[7]), .B0(intDY_EWSW[6]),
.Y(n2207) );
OAI22X1TS U2963 ( .A0(intDX_EWSW[6]), .A1(n2207), .B0(n3453), .B1(
intDX_EWSW[7]), .Y(n2215) );
NAND2BXLTS U2964 ( .AN(intDY_EWSW[2]), .B(intDX_EWSW[2]), .Y(n2210) );
AOI2BB2XLTS U2965 ( .B0(intDX_EWSW[1]), .B1(n3449), .A0N(intDY_EWSW[0]),
.A1N(n2208), .Y(n2209) );
OAI211XLTS U2966 ( .A0(n3372), .A1(intDY_EWSW[3]), .B0(n2210), .C0(n2209),
.Y(n2213) );
OAI21XLTS U2967 ( .A0(intDY_EWSW[3]), .A1(n3372), .B0(intDY_EWSW[2]), .Y(
n2211) );
AOI2BB2XLTS U2968 ( .B0(intDY_EWSW[3]), .B1(n3372), .A0N(intDX_EWSW[2]),
.A1N(n2211), .Y(n2212) );
AOI22X1TS U2969 ( .A0(intDX_EWSW[7]), .A1(n3453), .B0(intDX_EWSW[6]), .B1(
n3352), .Y(n2513) );
OAI32X1TS U2970 ( .A0(n2216), .A1(n2215), .A2(n2214), .B0(n2513), .B1(n2215),
.Y(n2232) );
NAND2BXLTS U2971 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n2220) );
NOR2X1TS U2972 ( .A(n3369), .B(intDY_EWSW[11]), .Y(n2218) );
AOI21X1TS U2973 ( .A0(intDX_EWSW[10]), .A1(n3408), .B0(n2218), .Y(n2223) );
OAI211XLTS U2974 ( .A0(intDY_EWSW[8]), .A1(n3392), .B0(n2220), .C0(n2223),
.Y(n2231) );
OAI21XLTS U2975 ( .A0(intDY_EWSW[13]), .A1(n3384), .B0(intDY_EWSW[12]), .Y(
n2217) );
OAI2BB2XLTS U2976 ( .B0(intDX_EWSW[12]), .B1(n2217), .A0N(intDY_EWSW[13]),
.A1N(n3384), .Y(n2229) );
NOR2XLTS U2977 ( .A(n2218), .B(intDX_EWSW[10]), .Y(n2219) );
AOI22X1TS U2978 ( .A0(intDY_EWSW[11]), .A1(n3369), .B0(intDY_EWSW[10]), .B1(
n2219), .Y(n2225) );
NAND3XLTS U2979 ( .A(n3392), .B(n2220), .C(intDY_EWSW[8]), .Y(n2222) );
AOI21X1TS U2980 ( .A0(n2222), .A1(n2221), .B0(n2233), .Y(n2224) );
OAI2BB2XLTS U2981 ( .B0(n2225), .B1(n2233), .A0N(n2224), .A1N(n2223), .Y(
n2228) );
OAI21XLTS U2982 ( .A0(intDY_EWSW[15]), .A1(n3316), .B0(intDY_EWSW[14]), .Y(
n2226) );
OAI2BB2XLTS U2983 ( .B0(intDX_EWSW[14]), .B1(n2226), .A0N(intDY_EWSW[15]),
.A1N(n3316), .Y(n2227) );
AOI211X1TS U2984 ( .A0(n2505), .A1(n2229), .B0(n2228), .C0(n2227), .Y(n2230)
);
OAI31X1TS U2985 ( .A0(n2233), .A1(n2232), .A2(n2231), .B0(n2230), .Y(n2235)
);
NOR2X1TS U2986 ( .A(n3390), .B(intDY_EWSW[17]), .Y(n2237) );
NAND2BXLTS U2987 ( .AN(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n2239) );
OAI21X1TS U2988 ( .A0(intDY_EWSW[18]), .A1(n3402), .B0(n2239), .Y(n2243) );
NAND3BXLTS U2989 ( .AN(n2242), .B(n2235), .C(n2234), .Y(n2254) );
OAI21XLTS U2990 ( .A0(intDY_EWSW[21]), .A1(n3400), .B0(intDY_EWSW[20]), .Y(
n2236) );
OAI2BB2XLTS U2991 ( .B0(intDX_EWSW[20]), .B1(n2236), .A0N(intDY_EWSW[21]),
.A1N(n3400), .Y(n2247) );
NOR2XLTS U2992 ( .A(n2237), .B(intDX_EWSW[16]), .Y(n2238) );
AOI22X1TS U2993 ( .A0(n2238), .A1(intDY_EWSW[16]), .B0(intDY_EWSW[17]), .B1(
n3390), .Y(n2241) );
AOI32X1TS U2994 ( .A0(n3402), .A1(n2239), .A2(intDY_EWSW[18]), .B0(
intDY_EWSW[19]), .B1(n3325), .Y(n2240) );
OAI32X1TS U2995 ( .A0(n2243), .A1(n2242), .A2(n2241), .B0(n2240), .B1(n2242),
.Y(n2246) );
OAI21XLTS U2996 ( .A0(intDY_EWSW[23]), .A1(n3321), .B0(intDY_EWSW[22]), .Y(
n2244) );
OAI2BB2XLTS U2997 ( .B0(intDX_EWSW[22]), .B1(n2244), .A0N(intDY_EWSW[23]),
.A1N(n3321), .Y(n2245) );
AOI211X1TS U2998 ( .A0(n2499), .A1(n2247), .B0(n2246), .C0(n2245), .Y(n2253)
);
NOR2BX1TS U2999 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n2249) );
OR4X2TS U3000 ( .A(n2251), .B(n2250), .C(n2249), .D(n2248), .Y(n2252) );
AOI32X1TS U3001 ( .A0(n2255), .A1(n2254), .A2(n2253), .B0(n2252), .B1(n2255),
.Y(n2324) );
NOR2XLTS U3002 ( .A(n2256), .B(intDX_EWSW[56]), .Y(n2257) );
AOI22X1TS U3003 ( .A0(intDY_EWSW[57]), .A1(n3393), .B0(intDY_EWSW[56]), .B1(
n2257), .Y(n2261) );
AOI32X1TS U3004 ( .A0(n3326), .A1(n2258), .A2(intDY_EWSW[58]), .B0(
intDY_EWSW[59]), .B1(n3404), .Y(n2259) );
OA21XLTS U3005 ( .A0(n2261), .A1(n2260), .B0(n2259), .Y(n2267) );
NAND3XLTS U3006 ( .A(n3385), .B(n2262), .C(intDY_EWSW[60]), .Y(n2263) );
OAI211XLTS U3007 ( .A0(intDX_EWSW[61]), .A1(n3432), .B0(n2264), .C0(n2263),
.Y(n2265) );
OAI2BB2XLTS U3008 ( .B0(n2268), .B1(n2267), .A0N(n2266), .A1N(n2265), .Y(
n2323) );
NOR2BX1TS U3009 ( .AN(n2269), .B(intDX_EWSW[46]), .Y(n2283) );
AOI22X1TS U3010 ( .A0(intDY_EWSW[45]), .A1(n3388), .B0(intDY_EWSW[44]), .B1(
n2271), .Y(n2280) );
OAI21XLTS U3011 ( .A0(intDY_EWSW[41]), .A1(n3382), .B0(intDY_EWSW[40]), .Y(
n2272) );
OAI2BB2XLTS U3012 ( .B0(intDX_EWSW[40]), .B1(n2272), .A0N(intDY_EWSW[41]),
.A1N(n3382), .Y(n2276) );
OAI21XLTS U3013 ( .A0(intDY_EWSW[43]), .A1(n3318), .B0(intDY_EWSW[42]), .Y(
n2273) );
OAI2BB2XLTS U3014 ( .B0(intDX_EWSW[42]), .B1(n2273), .A0N(intDY_EWSW[43]),
.A1N(n3318), .Y(n2274) );
AOI32X1TS U3015 ( .A0(n2277), .A1(n2276), .A2(n2275), .B0(n2274), .B1(n2277),
.Y(n2278) );
OAI21XLTS U3016 ( .A0(n2280), .A1(n2279), .B0(n2278), .Y(n2282) );
NOR2BX1TS U3017 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2281) );
AOI211XLTS U3018 ( .A0(intDY_EWSW[46]), .A1(n2283), .B0(n2282), .C0(n2281),
.Y(n2320) );
NAND3XLTS U3019 ( .A(n3381), .B(n2284), .C(intDY_EWSW[36]), .Y(n2285) );
OAI21XLTS U3020 ( .A0(intDX_EWSW[37]), .A1(n3437), .B0(n2285), .Y(n2294) );
INVX2TS U3021 ( .A(n2286), .Y(n2292) );
OAI2BB2XLTS U3022 ( .B0(intDX_EWSW[32]), .B1(n2287), .A0N(intDY_EWSW[33]),
.A1N(n3373), .Y(n2291) );
OAI21XLTS U3023 ( .A0(intDY_EWSW[35]), .A1(n3319), .B0(intDY_EWSW[34]), .Y(
n2288) );
OAI2BB2XLTS U3024 ( .B0(intDX_EWSW[34]), .B1(n2288), .A0N(intDY_EWSW[35]),
.A1N(n3319), .Y(n2289) );
AOI32X1TS U3025 ( .A0(n2292), .A1(n2291), .A2(n2290), .B0(n2289), .B1(n2292),
.Y(n2293) );
OAI2BB1X1TS U3026 ( .A0N(n2295), .A1N(n2294), .B0(n2293), .Y(n2300) );
NOR2BX1TS U3027 ( .AN(intDY_EWSW[39]), .B(intDX_EWSW[39]), .Y(n2299) );
NOR3X1TS U3028 ( .A(n3440), .B(n2296), .C(intDX_EWSW[38]), .Y(n2298) );
INVX2TS U3029 ( .A(n2321), .Y(n2297) );
OAI31X1TS U3030 ( .A0(n2300), .A1(n2299), .A2(n2298), .B0(n2297), .Y(n2318)
);
OAI21XLTS U3031 ( .A0(intDY_EWSW[53]), .A1(n3464), .B0(intDY_EWSW[52]), .Y(
n2301) );
AOI2BB2XLTS U3032 ( .B0(intDY_EWSW[53]), .B1(n3464), .A0N(intDX_EWSW[52]),
.A1N(n2301), .Y(n2303) );
NOR2XLTS U3033 ( .A(n2303), .B(n2302), .Y(n2316) );
INVX2TS U3034 ( .A(n2304), .Y(n2310) );
NOR2XLTS U3035 ( .A(n2305), .B(intDX_EWSW[48]), .Y(n2306) );
AOI22X1TS U3036 ( .A0(intDY_EWSW[49]), .A1(n3391), .B0(intDY_EWSW[48]), .B1(
n2306), .Y(n2309) );
AOI32X1TS U3037 ( .A0(n3322), .A1(n2307), .A2(intDY_EWSW[50]), .B0(
intDY_EWSW[51]), .B1(n3397), .Y(n2308) );
OAI32X1TS U3038 ( .A0(n2311), .A1(n2310), .A2(n2309), .B0(n2308), .B1(n2310),
.Y(n2315) );
OAI21XLTS U3039 ( .A0(intDY_EWSW[55]), .A1(n3465), .B0(intDY_EWSW[54]), .Y(
n2312) );
OAI2BB2XLTS U3040 ( .B0(intDX_EWSW[54]), .B1(n2312), .A0N(intDY_EWSW[55]),
.A1N(n3465), .Y(n2314) );
OAI31X1TS U3041 ( .A0(n2316), .A1(n2315), .A2(n2314), .B0(n2313), .Y(n2317)
);
OAI221XLTS U3042 ( .A0(n2321), .A1(n2320), .B0(n2319), .B1(n2318), .C0(n2317), .Y(n2322) );
AOI211X1TS U3043 ( .A0(n2325), .A1(n2324), .B0(n2323), .C0(n2322), .Y(n2326)
);
CLKBUFX2TS U3044 ( .A(n2327), .Y(n2384) );
AOI22X1TS U3045 ( .A0(intDX_EWSW[10]), .A1(n1827), .B0(DmP_EXP_EWSW[10]),
.B1(n2442), .Y(n2328) );
OAI21XLTS U3046 ( .A0(n3408), .A1(n2365), .B0(n2328), .Y(n1311) );
AOI22X1TS U3047 ( .A0(intDX_EWSW[22]), .A1(n1827), .B0(DmP_EXP_EWSW[22]),
.B1(n2453), .Y(n2329) );
OAI21XLTS U3048 ( .A0(n3451), .A1(n2336), .B0(n2329), .Y(n1287) );
BUFX3TS U3049 ( .A(n2336), .Y(n2842) );
BUFX4TS U3050 ( .A(n2842), .Y(n2871) );
AOI22X1TS U3051 ( .A0(intDX_EWSW[26]), .A1(n2384), .B0(DmP_EXP_EWSW[26]),
.B1(n2442), .Y(n2330) );
OAI21XLTS U3052 ( .A0(n3419), .A1(n2871), .B0(n2330), .Y(n1279) );
BUFX4TS U3053 ( .A(n2842), .Y(n2872) );
AOI22X1TS U3054 ( .A0(intDX_EWSW[30]), .A1(n1827), .B0(DmP_EXP_EWSW[30]),
.B1(n2442), .Y(n2331) );
AOI22X1TS U3055 ( .A0(DmP_EXP_EWSW[57]), .A1(n2442), .B0(intDX_EWSW[57]),
.B1(n1827), .Y(n2332) );
OAI21XLTS U3056 ( .A0(n3409), .A1(n2872), .B0(n2332), .Y(n1222) );
AOI22X1TS U3057 ( .A0(intDX_EWSW[28]), .A1(n2384), .B0(DmP_EXP_EWSW[28]),
.B1(n2386), .Y(n2333) );
OAI21XLTS U3058 ( .A0(n3420), .A1(n2872), .B0(n2333), .Y(n1275) );
AOI22X1TS U3059 ( .A0(intDX_EWSW[7]), .A1(n1827), .B0(DmP_EXP_EWSW[7]), .B1(
n2386), .Y(n2334) );
OAI21XLTS U3060 ( .A0(n3453), .A1(n2365), .B0(n2334), .Y(n1317) );
AOI22X1TS U3061 ( .A0(intDX_EWSW[8]), .A1(n1827), .B0(DmP_EXP_EWSW[8]), .B1(
n2453), .Y(n2335) );
OAI21XLTS U3062 ( .A0(n3414), .A1(n2365), .B0(n2335), .Y(n1315) );
INVX4TS U3063 ( .A(n2336), .Y(n2431) );
INVX2TS U3064 ( .A(n2337), .Y(n1227) );
INVX2TS U3065 ( .A(n2338), .Y(n1556) );
BUFX4TS U3066 ( .A(n1827), .Y(n2373) );
AOI22X1TS U3067 ( .A0(intDX_EWSW[15]), .A1(n2373), .B0(DmP_EXP_EWSW[15]),
.B1(n2442), .Y(n2339) );
OAI21XLTS U3068 ( .A0(n3346), .A1(n2365), .B0(n2339), .Y(n1301) );
BUFX4TS U3069 ( .A(n1827), .Y(n2380) );
AOI22X1TS U3070 ( .A0(intDX_EWSW[14]), .A1(n2380), .B0(DmP_EXP_EWSW[14]),
.B1(n2453), .Y(n2340) );
OAI21XLTS U3071 ( .A0(n3450), .A1(n2365), .B0(n2340), .Y(n1303) );
AOI22X1TS U3072 ( .A0(intDX_EWSW[12]), .A1(n2380), .B0(DmP_EXP_EWSW[12]),
.B1(n2453), .Y(n2341) );
OAI21XLTS U3073 ( .A0(n3415), .A1(n2365), .B0(n2341), .Y(n1307) );
AOI22X1TS U3074 ( .A0(intDX_EWSW[51]), .A1(n2373), .B0(DmP_EXP_EWSW[51]),
.B1(n2529), .Y(n2342) );
OAI21XLTS U3075 ( .A0(n3350), .A1(n2842), .B0(n2342), .Y(n1229) );
AOI22X1TS U3076 ( .A0(intDX_EWSW[49]), .A1(n2373), .B0(DmP_EXP_EWSW[49]),
.B1(n2529), .Y(n2343) );
OAI21XLTS U3077 ( .A0(n3430), .A1(n2842), .B0(n2343), .Y(n1233) );
AOI22X1TS U3078 ( .A0(intDX_EWSW[50]), .A1(n2373), .B0(DmP_EXP_EWSW[50]),
.B1(n2529), .Y(n2344) );
OAI21XLTS U3079 ( .A0(n3447), .A1(n2842), .B0(n2344), .Y(n1231) );
AOI22X1TS U3080 ( .A0(intDX_EWSW[35]), .A1(n2380), .B0(DmP_EXP_EWSW[35]),
.B1(n2386), .Y(n2345) );
OAI21XLTS U3081 ( .A0(n3342), .A1(n2872), .B0(n2345), .Y(n1261) );
AOI22X1TS U3082 ( .A0(intDX_EWSW[42]), .A1(n2373), .B0(DmP_EXP_EWSW[42]),
.B1(n2453), .Y(n2346) );
OAI21XLTS U3083 ( .A0(n3444), .A1(n2871), .B0(n2346), .Y(n1247) );
AOI22X1TS U3084 ( .A0(intDX_EWSW[34]), .A1(n2380), .B0(DmP_EXP_EWSW[34]),
.B1(n2386), .Y(n2347) );
OAI21XLTS U3085 ( .A0(n3441), .A1(n2872), .B0(n2347), .Y(n1263) );
AOI22X1TS U3086 ( .A0(intDX_EWSW[45]), .A1(n2373), .B0(DmP_EXP_EWSW[45]),
.B1(n2529), .Y(n2348) );
OAI21XLTS U3087 ( .A0(n3439), .A1(n2871), .B0(n2348), .Y(n1241) );
AOI22X1TS U3088 ( .A0(intDX_EWSW[41]), .A1(n2380), .B0(DmP_EXP_EWSW[41]),
.B1(n2386), .Y(n2349) );
OAI21XLTS U3089 ( .A0(n3343), .A1(n2871), .B0(n2349), .Y(n1249) );
AOI22X1TS U3090 ( .A0(intDX_EWSW[31]), .A1(n2380), .B0(DmP_EXP_EWSW[31]),
.B1(n2386), .Y(n2350) );
OAI21XLTS U3091 ( .A0(n3348), .A1(n2872), .B0(n2350), .Y(n1269) );
AOI22X1TS U3092 ( .A0(intDX_EWSW[43]), .A1(n2373), .B0(DmP_EXP_EWSW[43]),
.B1(n2442), .Y(n2351) );
OAI21XLTS U3093 ( .A0(n3344), .A1(n2871), .B0(n2351), .Y(n1245) );
AOI22X1TS U3094 ( .A0(intDX_EWSW[29]), .A1(n2373), .B0(DmP_EXP_EWSW[29]),
.B1(n2386), .Y(n2352) );
OAI21XLTS U3095 ( .A0(n3339), .A1(n2872), .B0(n2352), .Y(n1273) );
AOI22X1TS U3096 ( .A0(intDX_EWSW[25]), .A1(n2380), .B0(DmP_EXP_EWSW[25]),
.B1(n2845), .Y(n2353) );
OAI21XLTS U3097 ( .A0(n3337), .A1(n2871), .B0(n2353), .Y(n1281) );
AOI22X1TS U3098 ( .A0(intDX_EWSW[33]), .A1(n2380), .B0(DmP_EXP_EWSW[33]),
.B1(n2386), .Y(n2354) );
OAI21XLTS U3099 ( .A0(n3341), .A1(n2872), .B0(n2354), .Y(n1265) );
AOI22X1TS U3100 ( .A0(intDX_EWSW[27]), .A1(n2373), .B0(DmP_EXP_EWSW[27]),
.B1(n2453), .Y(n2355) );
OAI21XLTS U3101 ( .A0(n3338), .A1(n2872), .B0(n2355), .Y(n1277) );
AOI22X1TS U3102 ( .A0(intDX_EWSW[36]), .A1(n2380), .B0(DmP_EXP_EWSW[36]),
.B1(n2386), .Y(n2356) );
OAI21XLTS U3103 ( .A0(n3442), .A1(n2871), .B0(n2356), .Y(n1259) );
AOI22X1TS U3104 ( .A0(intDX_EWSW[46]), .A1(n2373), .B0(DmP_EXP_EWSW[46]),
.B1(n1933), .Y(n2357) );
OAI21XLTS U3105 ( .A0(n3446), .A1(n2871), .B0(n2357), .Y(n1239) );
AOI22X1TS U3106 ( .A0(intDX_EWSW[18]), .A1(n2373), .B0(DmP_EXP_EWSW[18]),
.B1(n2442), .Y(n2358) );
OAI21XLTS U3107 ( .A0(n3416), .A1(n2872), .B0(n2358), .Y(n1295) );
AOI22X1TS U3108 ( .A0(intDX_EWSW[19]), .A1(n2380), .B0(DmP_EXP_EWSW[19]),
.B1(n2845), .Y(n2359) );
OAI21XLTS U3109 ( .A0(n3336), .A1(n2871), .B0(n2359), .Y(n1293) );
AOI22X1TS U3110 ( .A0(intDX_EWSW[17]), .A1(n2380), .B0(DmP_EXP_EWSW[17]),
.B1(n2453), .Y(n2360) );
OAI21XLTS U3111 ( .A0(n3335), .A1(n2872), .B0(n2360), .Y(n1297) );
AOI22X1TS U3112 ( .A0(intDX_EWSW[21]), .A1(n2373), .B0(DmP_EXP_EWSW[21]),
.B1(n1933), .Y(n2361) );
OAI21XLTS U3113 ( .A0(n3411), .A1(n2872), .B0(n2361), .Y(n1289) );
AOI22X1TS U3114 ( .A0(intDX_EWSW[20]), .A1(n2373), .B0(DmP_EXP_EWSW[20]),
.B1(n2529), .Y(n2362) );
OAI21XLTS U3115 ( .A0(n3417), .A1(n2871), .B0(n2362), .Y(n1291) );
AOI22X1TS U3116 ( .A0(intDX_EWSW[23]), .A1(n2373), .B0(DmP_EXP_EWSW[23]),
.B1(n2453), .Y(n2363) );
AOI22X1TS U3117 ( .A0(intDX_EWSW[16]), .A1(n2380), .B0(DmP_EXP_EWSW[16]),
.B1(n2845), .Y(n2364) );
OAI21XLTS U3118 ( .A0(n3425), .A1(n2365), .B0(n2364), .Y(n1299) );
AOI22X1TS U3119 ( .A0(intDX_EWSW[24]), .A1(n2380), .B0(DmP_EXP_EWSW[24]),
.B1(n2529), .Y(n2366) );
OAI21XLTS U3120 ( .A0(n3418), .A1(n2872), .B0(n2366), .Y(n1283) );
AOI22X1TS U3121 ( .A0(intDX_EWSW[48]), .A1(n2373), .B0(DmP_EXP_EWSW[48]),
.B1(n2453), .Y(n2367) );
OAI21XLTS U3122 ( .A0(n3422), .A1(n2842), .B0(n2367), .Y(n1235) );
AOI22X1TS U3123 ( .A0(intDX_EWSW[32]), .A1(n2380), .B0(DmP_EXP_EWSW[32]),
.B1(n2386), .Y(n2368) );
OAI21XLTS U3124 ( .A0(n3421), .A1(n2872), .B0(n2368), .Y(n1267) );
AOI22X1TS U3125 ( .A0(intDX_EWSW[39]), .A1(n2373), .B0(DmP_EXP_EWSW[39]),
.B1(n2386), .Y(n2369) );
OAI21XLTS U3126 ( .A0(n3438), .A1(n2871), .B0(n2369), .Y(n1253) );
AOI22X1TS U3127 ( .A0(intDX_EWSW[47]), .A1(n2373), .B0(DmP_EXP_EWSW[47]),
.B1(n2442), .Y(n2370) );
OAI21XLTS U3128 ( .A0(n3349), .A1(n2871), .B0(n2370), .Y(n1237) );
AOI22X1TS U3129 ( .A0(intDX_EWSW[40]), .A1(n2380), .B0(DmP_EXP_EWSW[40]),
.B1(n2386), .Y(n2371) );
OAI21XLTS U3130 ( .A0(n3443), .A1(n2871), .B0(n2371), .Y(n1251) );
AOI22X1TS U3131 ( .A0(intDX_EWSW[38]), .A1(n2380), .B0(DmP_EXP_EWSW[38]),
.B1(n2386), .Y(n2372) );
OAI21XLTS U3132 ( .A0(n3440), .A1(n2871), .B0(n2372), .Y(n1255) );
AOI22X1TS U3133 ( .A0(intDX_EWSW[44]), .A1(n2373), .B0(DmP_EXP_EWSW[44]),
.B1(n1933), .Y(n2374) );
AOI22X1TS U3134 ( .A0(intDX_EWSW[37]), .A1(n2380), .B0(DmP_EXP_EWSW[37]),
.B1(n2386), .Y(n2375) );
AOI22X1TS U3135 ( .A0(intDX_EWSW[5]), .A1(n1827), .B0(DmP_EXP_EWSW[5]), .B1(
n2453), .Y(n2376) );
OAI21XLTS U3136 ( .A0(n3334), .A1(n2365), .B0(n2376), .Y(n1321) );
AOI22X1TS U3137 ( .A0(intDX_EWSW[4]), .A1(n1827), .B0(DmP_EXP_EWSW[4]), .B1(
n2442), .Y(n2377) );
OAI21XLTS U3138 ( .A0(n3413), .A1(n2365), .B0(n2377), .Y(n1323) );
AOI22X1TS U3139 ( .A0(intDX_EWSW[1]), .A1(n1827), .B0(DmP_EXP_EWSW[1]), .B1(
n2453), .Y(n2378) );
OAI21XLTS U3140 ( .A0(n3449), .A1(n2872), .B0(n2378), .Y(n1329) );
AOI22X1TS U3141 ( .A0(intDX_EWSW[9]), .A1(n1827), .B0(DmP_EXP_EWSW[9]), .B1(
n2442), .Y(n2379) );
OAI21XLTS U3142 ( .A0(n3407), .A1(n2365), .B0(n2379), .Y(n1313) );
AOI22X1TS U3143 ( .A0(intDX_EWSW[13]), .A1(n2380), .B0(DmP_EXP_EWSW[13]),
.B1(n2453), .Y(n2381) );
OAI21XLTS U3144 ( .A0(n3410), .A1(n2365), .B0(n2381), .Y(n1305) );
AOI22X1TS U3145 ( .A0(intDX_EWSW[11]), .A1(n1827), .B0(DmP_EXP_EWSW[11]),
.B1(n2442), .Y(n2382) );
OAI21XLTS U3146 ( .A0(n3345), .A1(n2365), .B0(n2382), .Y(n1309) );
AOI22X1TS U3147 ( .A0(intDX_EWSW[6]), .A1(n2384), .B0(DmP_EXP_EWSW[6]), .B1(
n2442), .Y(n2383) );
OAI21XLTS U3148 ( .A0(n3352), .A1(n2365), .B0(n2383), .Y(n1319) );
AOI22X1TS U3149 ( .A0(intDX_EWSW[3]), .A1(n2384), .B0(DmP_EXP_EWSW[3]), .B1(
n2442), .Y(n2385) );
OAI21XLTS U3150 ( .A0(n3331), .A1(n2336), .B0(n2385), .Y(n1325) );
AOI22X1TS U3151 ( .A0(intDX_EWSW[0]), .A1(n1827), .B0(DmP_EXP_EWSW[0]), .B1(
n2453), .Y(n2387) );
OAI21XLTS U3152 ( .A0(n3333), .A1(n2336), .B0(n2387), .Y(n1331) );
AOI22X1TS U3153 ( .A0(intDX_EWSW[2]), .A1(n1827), .B0(DmP_EXP_EWSW[2]), .B1(
n2529), .Y(n2388) );
OAI21XLTS U3154 ( .A0(n3412), .A1(n2336), .B0(n2388), .Y(n1327) );
CLKBUFX2TS U3155 ( .A(n1827), .Y(n2395) );
AOI22X1TS U3156 ( .A0(intDX_EWSW[58]), .A1(n2449), .B0(DMP_EXP_EWSW[58]),
.B1(n2529), .Y(n2389) );
OAI21XLTS U3157 ( .A0(n3424), .A1(n2874), .B0(n2389), .Y(n1550) );
AOI22X1TS U3158 ( .A0(intDX_EWSW[60]), .A1(n2449), .B0(DMP_EXP_EWSW[60]),
.B1(n2529), .Y(n2390) );
OAI21XLTS U3159 ( .A0(n3423), .A1(n2874), .B0(n2390), .Y(n1548) );
AOI22X1TS U3160 ( .A0(intDX_EWSW[62]), .A1(n2456), .B0(DMP_EXP_EWSW[62]),
.B1(n2845), .Y(n2391) );
OAI21XLTS U3161 ( .A0(n3448), .A1(n2874), .B0(n2391), .Y(n1546) );
AOI22X1TS U3162 ( .A0(intDX_EWSW[0]), .A1(n2431), .B0(DMP_EXP_EWSW[0]), .B1(
n1933), .Y(n2392) );
INVX4TS U3163 ( .A(n2395), .Y(n2433) );
AOI22X1TS U3164 ( .A0(intDX_EWSW[7]), .A1(n2435), .B0(DMP_EXP_EWSW[7]), .B1(
n1933), .Y(n2393) );
OAI21XLTS U3165 ( .A0(n3453), .A1(n2433), .B0(n2393), .Y(n1601) );
INVX4TS U3166 ( .A(n2395), .Y(n2451) );
CLKBUFX2TS U3167 ( .A(n2529), .Y(n2426) );
AOI22X1TS U3168 ( .A0(intDX_EWSW[10]), .A1(n2435), .B0(DMP_EXP_EWSW[10]),
.B1(n2455), .Y(n2394) );
OAI21XLTS U3169 ( .A0(n3408), .A1(n2451), .B0(n2394), .Y(n1598) );
INVX4TS U3170 ( .A(n2395), .Y(n2458) );
AOI22X1TS U3171 ( .A0(intDX_EWSW[31]), .A1(n2456), .B0(DMP_EXP_EWSW[31]),
.B1(n2455), .Y(n2396) );
OAI21XLTS U3172 ( .A0(n3348), .A1(n2458), .B0(n2396), .Y(n1577) );
AOI22X1TS U3173 ( .A0(intDX_EWSW[38]), .A1(n2456), .B0(DMP_EXP_EWSW[38]),
.B1(n2453), .Y(n2397) );
OAI21XLTS U3174 ( .A0(n3440), .A1(n2458), .B0(n2397), .Y(n1570) );
AOI22X1TS U3175 ( .A0(intDX_EWSW[30]), .A1(n2431), .B0(DMP_EXP_EWSW[30]),
.B1(n2455), .Y(n2398) );
OAI21XLTS U3176 ( .A0(n3452), .A1(n2458), .B0(n2398), .Y(n1578) );
AOI22X1TS U3177 ( .A0(intDX_EWSW[4]), .A1(n2435), .B0(DMP_EXP_EWSW[4]), .B1(
n1933), .Y(n2399) );
OAI21XLTS U3178 ( .A0(n3413), .A1(n2451), .B0(n2399), .Y(n1604) );
AOI22X1TS U3179 ( .A0(intDX_EWSW[16]), .A1(n2435), .B0(DMP_EXP_EWSW[16]),
.B1(n2455), .Y(n2400) );
OAI21XLTS U3180 ( .A0(n3425), .A1(n2433), .B0(n2400), .Y(n1592) );
AOI22X1TS U3181 ( .A0(intDX_EWSW[37]), .A1(n2456), .B0(DMP_EXP_EWSW[37]),
.B1(n2455), .Y(n2401) );
OAI21XLTS U3182 ( .A0(n3437), .A1(n2458), .B0(n2401), .Y(n1571) );
AOI22X1TS U3183 ( .A0(intDX_EWSW[61]), .A1(n2449), .B0(DMP_EXP_EWSW[61]),
.B1(n2529), .Y(n2402) );
OAI21XLTS U3184 ( .A0(n3432), .A1(n2451), .B0(n2402), .Y(n1547) );
AOI22X1TS U3185 ( .A0(intDX_EWSW[1]), .A1(n2435), .B0(DMP_EXP_EWSW[1]), .B1(
n1933), .Y(n2403) );
OAI21XLTS U3186 ( .A0(n3449), .A1(n2458), .B0(n2403), .Y(n1607) );
AOI22X1TS U3187 ( .A0(intDX_EWSW[23]), .A1(n2431), .B0(DMP_EXP_EWSW[23]),
.B1(n2455), .Y(n2404) );
OAI21XLTS U3188 ( .A0(n3347), .A1(n2433), .B0(n2404), .Y(n1585) );
AOI22X1TS U3189 ( .A0(intDX_EWSW[5]), .A1(n2435), .B0(DMP_EXP_EWSW[5]), .B1(
n1933), .Y(n2405) );
OAI21XLTS U3190 ( .A0(n3334), .A1(n2458), .B0(n2405), .Y(n1603) );
AOI22X1TS U3191 ( .A0(intDX_EWSW[59]), .A1(n2449), .B0(DMP_EXP_EWSW[59]),
.B1(n2453), .Y(n2406) );
AOI22X1TS U3192 ( .A0(intDX_EWSW[22]), .A1(n2431), .B0(DMP_EXP_EWSW[22]),
.B1(n2455), .Y(n2407) );
OAI21XLTS U3193 ( .A0(n3451), .A1(n2433), .B0(n2407), .Y(n1586) );
AOI22X1TS U3194 ( .A0(intDX_EWSW[14]), .A1(n2435), .B0(DMP_EXP_EWSW[14]),
.B1(n2386), .Y(n2408) );
OAI21XLTS U3195 ( .A0(n3450), .A1(n2458), .B0(n2408), .Y(n1594) );
AOI22X1TS U3196 ( .A0(intDX_EWSW[15]), .A1(n2435), .B0(DMP_EXP_EWSW[15]),
.B1(n2455), .Y(n2409) );
OAI21XLTS U3197 ( .A0(n3346), .A1(n2433), .B0(n2409), .Y(n1593) );
AOI22X1TS U3198 ( .A0(intDX_EWSW[44]), .A1(n2449), .B0(DMP_EXP_EWSW[44]),
.B1(n2442), .Y(n2410) );
OAI21XLTS U3199 ( .A0(n3445), .A1(n2451), .B0(n2410), .Y(n1564) );
AOI22X1TS U3200 ( .A0(intDX_EWSW[48]), .A1(n2449), .B0(DMP_EXP_EWSW[48]),
.B1(n2442), .Y(n2411) );
OAI21XLTS U3201 ( .A0(n3422), .A1(n2451), .B0(n2411), .Y(n1560) );
AOI22X1TS U3202 ( .A0(intDX_EWSW[6]), .A1(n2435), .B0(DMP_EXP_EWSW[6]), .B1(
n1933), .Y(n2412) );
OAI21XLTS U3203 ( .A0(n3352), .A1(n2433), .B0(n2412), .Y(n1602) );
AOI22X1TS U3204 ( .A0(intDX_EWSW[11]), .A1(n2435), .B0(DMP_EXP_EWSW[11]),
.B1(n2455), .Y(n2413) );
OAI21XLTS U3205 ( .A0(n3345), .A1(n2458), .B0(n2413), .Y(n1597) );
AOI22X1TS U3206 ( .A0(intDX_EWSW[3]), .A1(n2435), .B0(DMP_EXP_EWSW[3]), .B1(
n1933), .Y(n2414) );
OAI21XLTS U3207 ( .A0(n3331), .A1(n2433), .B0(n2414), .Y(n1605) );
AOI22X1TS U3208 ( .A0(intDX_EWSW[2]), .A1(n2435), .B0(DMP_EXP_EWSW[2]), .B1(
n1933), .Y(n2415) );
OAI21XLTS U3209 ( .A0(n3412), .A1(n2451), .B0(n2415), .Y(n1606) );
AOI22X1TS U3210 ( .A0(intDX_EWSW[8]), .A1(n2435), .B0(DMP_EXP_EWSW[8]), .B1(
n2426), .Y(n2416) );
OAI21XLTS U3211 ( .A0(n3414), .A1(n2451), .B0(n2416), .Y(n1600) );
AOI22X1TS U3212 ( .A0(intDX_EWSW[13]), .A1(n2435), .B0(DMP_EXP_EWSW[13]),
.B1(n2426), .Y(n2417) );
AOI22X1TS U3213 ( .A0(intDX_EWSW[12]), .A1(n2435), .B0(DMP_EXP_EWSW[12]),
.B1(n2426), .Y(n2418) );
OAI21XLTS U3214 ( .A0(n3415), .A1(n2458), .B0(n2418), .Y(n1596) );
AOI22X1TS U3215 ( .A0(intDX_EWSW[18]), .A1(n2435), .B0(DMP_EXP_EWSW[18]),
.B1(n2455), .Y(n2419) );
OAI21XLTS U3216 ( .A0(n3416), .A1(n2433), .B0(n2419), .Y(n1590) );
AOI22X1TS U3217 ( .A0(intDX_EWSW[9]), .A1(n2435), .B0(DMP_EXP_EWSW[9]), .B1(
n1933), .Y(n2420) );
OAI21XLTS U3218 ( .A0(n3407), .A1(n2451), .B0(n2420), .Y(n1599) );
AOI22X1TS U3219 ( .A0(intDX_EWSW[27]), .A1(n2431), .B0(DMP_EXP_EWSW[27]),
.B1(n2455), .Y(n2421) );
AOI22X1TS U3220 ( .A0(intDX_EWSW[17]), .A1(n2435), .B0(DMP_EXP_EWSW[17]),
.B1(n2455), .Y(n2422) );
OAI21XLTS U3221 ( .A0(n3335), .A1(n2433), .B0(n2422), .Y(n1591) );
AOI22X1TS U3222 ( .A0(intDX_EWSW[19]), .A1(n2431), .B0(DMP_EXP_EWSW[19]),
.B1(n2455), .Y(n2423) );
OAI21XLTS U3223 ( .A0(n3336), .A1(n2433), .B0(n2423), .Y(n1589) );
AOI22X1TS U3224 ( .A0(intDX_EWSW[24]), .A1(n2431), .B0(DMP_EXP_EWSW[24]),
.B1(n2455), .Y(n2424) );
OAI21XLTS U3225 ( .A0(n3418), .A1(n2433), .B0(n2424), .Y(n1584) );
AOI22X1TS U3226 ( .A0(intDX_EWSW[20]), .A1(n2431), .B0(DMP_EXP_EWSW[20]),
.B1(n2426), .Y(n2425) );
OAI21XLTS U3227 ( .A0(n3417), .A1(n2433), .B0(n2425), .Y(n1588) );
AOI22X1TS U3228 ( .A0(intDX_EWSW[21]), .A1(n2431), .B0(DMP_EXP_EWSW[21]),
.B1(n2426), .Y(n2427) );
OAI21XLTS U3229 ( .A0(n3411), .A1(n2433), .B0(n2427), .Y(n1587) );
AOI22X1TS U3230 ( .A0(intDX_EWSW[29]), .A1(n2431), .B0(DMP_EXP_EWSW[29]),
.B1(n2455), .Y(n2428) );
OAI21XLTS U3231 ( .A0(n3339), .A1(n2458), .B0(n2428), .Y(n1579) );
AOI22X1TS U3232 ( .A0(intDX_EWSW[28]), .A1(n2431), .B0(DMP_EXP_EWSW[28]),
.B1(n2455), .Y(n2429) );
OAI21XLTS U3233 ( .A0(n3420), .A1(n2433), .B0(n2429), .Y(n1580) );
AOI22X1TS U3234 ( .A0(intDX_EWSW[25]), .A1(n2431), .B0(DMP_EXP_EWSW[25]),
.B1(n2529), .Y(n2430) );
OAI21XLTS U3235 ( .A0(n3337), .A1(n2433), .B0(n2430), .Y(n1583) );
AOI22X1TS U3236 ( .A0(intDX_EWSW[26]), .A1(n2431), .B0(DMP_EXP_EWSW[26]),
.B1(n2455), .Y(n2432) );
OAI21XLTS U3237 ( .A0(n3419), .A1(n2433), .B0(n2432), .Y(n1582) );
AOI22X1TS U3238 ( .A0(intDX_EWSW[32]), .A1(n2456), .B0(DMP_EXP_EWSW[32]),
.B1(n2455), .Y(n2434) );
OAI21XLTS U3239 ( .A0(n3421), .A1(n2458), .B0(n2434), .Y(n1576) );
AOI22X1TS U3240 ( .A0(DMP_EXP_EWSW[57]), .A1(n2386), .B0(intDX_EWSW[57]),
.B1(n2435), .Y(n2436) );
OAI21XLTS U3241 ( .A0(n3409), .A1(n2451), .B0(n2436), .Y(n1551) );
AOI22X1TS U3242 ( .A0(intDX_EWSW[49]), .A1(n2449), .B0(DMP_EXP_EWSW[49]),
.B1(n1933), .Y(n2437) );
OAI21XLTS U3243 ( .A0(n3430), .A1(n2451), .B0(n2437), .Y(n1559) );
AOI22X1TS U3244 ( .A0(intDX_EWSW[41]), .A1(n2456), .B0(DMP_EXP_EWSW[41]),
.B1(n2453), .Y(n2438) );
AOI22X1TS U3245 ( .A0(intDX_EWSW[46]), .A1(n2449), .B0(DMP_EXP_EWSW[46]),
.B1(n2442), .Y(n2439) );
OAI21XLTS U3246 ( .A0(n3446), .A1(n2451), .B0(n2439), .Y(n1562) );
AOI22X1TS U3247 ( .A0(intDX_EWSW[39]), .A1(n2456), .B0(DMP_EXP_EWSW[39]),
.B1(n2442), .Y(n2440) );
OAI21XLTS U3248 ( .A0(n3438), .A1(n2458), .B0(n2440), .Y(n1569) );
AOI22X1TS U3249 ( .A0(intDX_EWSW[42]), .A1(n2456), .B0(DMP_EXP_EWSW[42]),
.B1(n1933), .Y(n2441) );
OAI21XLTS U3250 ( .A0(n3444), .A1(n2451), .B0(n2441), .Y(n1566) );
AOI22X1TS U3251 ( .A0(intDX_EWSW[50]), .A1(n2449), .B0(DMP_EXP_EWSW[50]),
.B1(n2529), .Y(n2443) );
OAI21XLTS U3252 ( .A0(n3447), .A1(n2458), .B0(n2443), .Y(n1558) );
AOI22X1TS U3253 ( .A0(intDX_EWSW[33]), .A1(n2456), .B0(DMP_EXP_EWSW[33]),
.B1(n2845), .Y(n2444) );
OAI21XLTS U3254 ( .A0(n3341), .A1(n2458), .B0(n2444), .Y(n1575) );
AOI22X1TS U3255 ( .A0(intDX_EWSW[43]), .A1(n2449), .B0(DMP_EXP_EWSW[43]),
.B1(n2529), .Y(n2445) );
OAI21XLTS U3256 ( .A0(n3344), .A1(n2451), .B0(n2445), .Y(n1565) );
AOI22X1TS U3257 ( .A0(intDX_EWSW[51]), .A1(n2449), .B0(DMP_EXP_EWSW[51]),
.B1(n2529), .Y(n2446) );
OAI21XLTS U3258 ( .A0(n3350), .A1(n2451), .B0(n2446), .Y(n1557) );
AOI22X1TS U3259 ( .A0(intDX_EWSW[35]), .A1(n2456), .B0(DMP_EXP_EWSW[35]),
.B1(n2455), .Y(n2447) );
OAI21XLTS U3260 ( .A0(n3342), .A1(n2458), .B0(n2447), .Y(n1573) );
AOI22X1TS U3261 ( .A0(intDX_EWSW[47]), .A1(n2449), .B0(DMP_EXP_EWSW[47]),
.B1(n2529), .Y(n2448) );
OAI21XLTS U3262 ( .A0(n3349), .A1(n2451), .B0(n2448), .Y(n1561) );
AOI22X1TS U3263 ( .A0(intDX_EWSW[45]), .A1(n2456), .B0(DMP_EXP_EWSW[45]),
.B1(n2453), .Y(n2450) );
OAI21XLTS U3264 ( .A0(n3439), .A1(n2451), .B0(n2450), .Y(n1563) );
AOI22X1TS U3265 ( .A0(intDX_EWSW[36]), .A1(n2456), .B0(DMP_EXP_EWSW[36]),
.B1(n2442), .Y(n2452) );
OAI21XLTS U3266 ( .A0(n3442), .A1(n2458), .B0(n2452), .Y(n1572) );
AOI22X1TS U3267 ( .A0(intDX_EWSW[40]), .A1(n2449), .B0(DMP_EXP_EWSW[40]),
.B1(n2529), .Y(n2454) );
OAI21XLTS U3268 ( .A0(n3443), .A1(n2458), .B0(n2454), .Y(n1568) );
AOI22X1TS U3269 ( .A0(intDX_EWSW[34]), .A1(n2456), .B0(DMP_EXP_EWSW[34]),
.B1(n2455), .Y(n2457) );
OAI21XLTS U3270 ( .A0(n3441), .A1(n2458), .B0(n2457), .Y(n1574) );
AOI22X1TS U3271 ( .A0(n3345), .A1(intDX_EWSW[11]), .B0(n3430), .B1(
intDX_EWSW[49]), .Y(n2459) );
OAI221XLTS U3272 ( .A0(n3345), .A1(intDX_EWSW[11]), .B0(n3430), .B1(
intDX_EWSW[49]), .C0(n2459), .Y(n2460) );
AOI221X1TS U3273 ( .A0(intDY_EWSW[1]), .A1(n3433), .B0(n3449), .B1(
intDX_EWSW[1]), .C0(n2460), .Y(n2474) );
OAI22X1TS U3274 ( .A0(n3434), .A1(intDX_EWSW[52]), .B0(n3313), .B1(
intDX_EWSW[53]), .Y(n2461) );
OAI22X1TS U3275 ( .A0(n3447), .A1(intDX_EWSW[50]), .B0(n3350), .B1(
intDX_EWSW[51]), .Y(n2462) );
AOI221X1TS U3276 ( .A0(n3447), .A1(intDX_EWSW[50]), .B0(intDX_EWSW[51]),
.B1(n3350), .C0(n2462), .Y(n2472) );
AOI22X1TS U3277 ( .A0(n3409), .A1(intDX_EWSW[57]), .B0(n3310), .B1(
intDX_EWSW[56]), .Y(n2463) );
AOI22X1TS U3278 ( .A0(n3309), .A1(intDX_EWSW[55]), .B0(n3312), .B1(
intDX_EWSW[54]), .Y(n2464) );
OAI221XLTS U3279 ( .A0(n3309), .A1(intDX_EWSW[55]), .B0(n3312), .B1(
intDX_EWSW[54]), .C0(n2464), .Y(n2469) );
AOI22X1TS U3280 ( .A0(n3432), .A1(intDX_EWSW[61]), .B0(n3423), .B1(
intDX_EWSW[60]), .Y(n2465) );
AOI22X1TS U3281 ( .A0(n3340), .A1(intDX_EWSW[59]), .B0(n3424), .B1(
intDX_EWSW[58]), .Y(n2466) );
OAI221XLTS U3282 ( .A0(n3340), .A1(intDX_EWSW[59]), .B0(n3424), .B1(
intDX_EWSW[58]), .C0(n2466), .Y(n2467) );
NOR4X1TS U3283 ( .A(n2470), .B(n2469), .C(n2468), .D(n2467), .Y(n2471) );
NAND4XLTS U3284 ( .A(n2474), .B(n2473), .C(n2472), .D(n2471), .Y(n2528) );
OAI22X1TS U3285 ( .A0(n3444), .A1(intDX_EWSW[42]), .B0(n3344), .B1(
intDX_EWSW[43]), .Y(n2475) );
AOI221X1TS U3286 ( .A0(n3444), .A1(intDX_EWSW[42]), .B0(intDX_EWSW[43]),
.B1(n3344), .C0(n2475), .Y(n2482) );
OAI22X1TS U3287 ( .A0(n3443), .A1(intDX_EWSW[40]), .B0(n3343), .B1(
intDX_EWSW[41]), .Y(n2476) );
AOI221X1TS U3288 ( .A0(n3443), .A1(intDX_EWSW[40]), .B0(intDX_EWSW[41]),
.B1(n3343), .C0(n2476), .Y(n2481) );
OAI22X1TS U3289 ( .A0(n3446), .A1(intDX_EWSW[46]), .B0(n3349), .B1(
intDX_EWSW[47]), .Y(n2477) );
AOI221X1TS U3290 ( .A0(n3446), .A1(intDX_EWSW[46]), .B0(intDX_EWSW[47]),
.B1(n3349), .C0(n2477), .Y(n2480) );
OAI22X1TS U3291 ( .A0(n3445), .A1(intDX_EWSW[44]), .B0(n3439), .B1(
intDX_EWSW[45]), .Y(n2478) );
AOI221X1TS U3292 ( .A0(n3445), .A1(intDX_EWSW[44]), .B0(intDX_EWSW[45]),
.B1(n3439), .C0(n2478), .Y(n2479) );
NAND4XLTS U3293 ( .A(n2482), .B(n2481), .C(n2480), .D(n2479), .Y(n2527) );
OAI22X1TS U3294 ( .A0(n3441), .A1(intDX_EWSW[34]), .B0(n3342), .B1(
intDX_EWSW[35]), .Y(n2483) );
AOI221X1TS U3295 ( .A0(n3441), .A1(intDX_EWSW[34]), .B0(intDX_EWSW[35]),
.B1(n3342), .C0(n2483), .Y(n2490) );
OAI22X1TS U3296 ( .A0(n3448), .A1(intDX_EWSW[62]), .B0(n3341), .B1(
intDX_EWSW[33]), .Y(n2484) );
AOI221X1TS U3297 ( .A0(n3448), .A1(intDX_EWSW[62]), .B0(intDX_EWSW[33]),
.B1(n3341), .C0(n2484), .Y(n2489) );
OAI22X1TS U3298 ( .A0(n3440), .A1(intDX_EWSW[38]), .B0(n3438), .B1(
intDX_EWSW[39]), .Y(n2485) );
OAI22X1TS U3299 ( .A0(n3442), .A1(intDX_EWSW[36]), .B0(n3437), .B1(
intDX_EWSW[37]), .Y(n2486) );
AOI221X1TS U3300 ( .A0(n3442), .A1(intDX_EWSW[36]), .B0(intDX_EWSW[37]),
.B1(n3437), .C0(n2486), .Y(n2487) );
NAND4XLTS U3301 ( .A(n2490), .B(n2489), .C(n2488), .D(n2487), .Y(n2526) );
OAI221XLTS U3302 ( .A0(n3348), .A1(intDX_EWSW[31]), .B0(n3452), .B1(
intDX_EWSW[30]), .C0(n2491), .Y(n2498) );
AOI22X1TS U3303 ( .A0(n3339), .A1(intDX_EWSW[29]), .B0(n3417), .B1(
intDX_EWSW[20]), .Y(n2492) );
OAI221XLTS U3304 ( .A0(n3339), .A1(intDX_EWSW[29]), .B0(n3417), .B1(
intDX_EWSW[20]), .C0(n2492), .Y(n2497) );
AOI22X1TS U3305 ( .A0(n3338), .A1(intDX_EWSW[27]), .B0(n3419), .B1(
intDX_EWSW[26]), .Y(n2493) );
AOI22X1TS U3306 ( .A0(n3337), .A1(intDX_EWSW[25]), .B0(n3421), .B1(
intDX_EWSW[32]), .Y(n2494) );
NOR4X1TS U3307 ( .A(n2495), .B(n2497), .C(n2496), .D(n2498), .Y(n2524) );
OAI221XLTS U3308 ( .A0(n3347), .A1(intDX_EWSW[23]), .B0(n3451), .B1(
intDX_EWSW[22]), .C0(n2499), .Y(n2504) );
AOI22X1TS U3309 ( .A0(n3411), .A1(intDX_EWSW[21]), .B0(n3422), .B1(
intDX_EWSW[48]), .Y(n2500) );
AOI22X1TS U3310 ( .A0(n3335), .A1(intDX_EWSW[17]), .B0(n3418), .B1(
intDX_EWSW[24]), .Y(n2501) );
NOR4X1TS U3311 ( .A(n2503), .B(n2504), .C(n1829), .D(n2502), .Y(n2523) );
OAI221XLTS U3312 ( .A0(n3346), .A1(intDX_EWSW[15]), .B0(n3450), .B1(
intDX_EWSW[14]), .C0(n2505), .Y(n2512) );
AOI22X1TS U3313 ( .A0(n3410), .A1(intDX_EWSW[13]), .B0(n3413), .B1(
intDX_EWSW[4]), .Y(n2506) );
AOI22X1TS U3314 ( .A0(n3408), .A1(intDX_EWSW[10]), .B0(n3415), .B1(
intDX_EWSW[12]), .Y(n2507) );
AOI22X1TS U3315 ( .A0(n3407), .A1(intDX_EWSW[9]), .B0(n3425), .B1(
intDX_EWSW[16]), .Y(n2508) );
NOR4X1TS U3316 ( .A(n2511), .B(n2512), .C(n2510), .D(n2509), .Y(n2522) );
AOI22X1TS U3317 ( .A0(n3334), .A1(intDX_EWSW[5]), .B0(n3420), .B1(
intDX_EWSW[28]), .Y(n2514) );
AOI22X1TS U3318 ( .A0(n3331), .A1(intDX_EWSW[3]), .B0(n3412), .B1(
intDX_EWSW[2]), .Y(n2515) );
AOI22X1TS U3319 ( .A0(n3333), .A1(intDX_EWSW[0]), .B0(n3414), .B1(
intDX_EWSW[8]), .Y(n2516) );
NOR4X1TS U3320 ( .A(n2520), .B(n2519), .C(n2518), .D(n2517), .Y(n2521) );
NAND4XLTS U3321 ( .A(n2524), .B(n2523), .C(n2522), .D(n2521), .Y(n2525) );
NOR4X1TS U3322 ( .A(n2528), .B(n2527), .C(n2526), .D(n2525), .Y(n2847) );
CLKXOR2X2TS U3323 ( .A(intDY_EWSW[63]), .B(intAS), .Y(n2844) );
INVX2TS U3324 ( .A(n2844), .Y(n2532) );
OAI21XLTS U3325 ( .A0(n2532), .A1(n1933), .B0(n2871), .Y(n2530) );
AOI22X1TS U3326 ( .A0(intDX_EWSW[63]), .A1(n2530), .B0(SIGN_FLAG_EXP), .B1(
n2529), .Y(n2531) );
NOR2X4TS U3327 ( .A(n2533), .B(n2811), .Y(n2810) );
BUFX4TS U3328 ( .A(n2719), .Y(n2690) );
NOR2X8TS U3329 ( .A(n2648), .B(n2719), .Y(n2718) );
AOI21X1TS U3330 ( .A0(n2811), .A1(Data_array_SWR[34]), .B0(n2718), .Y(n2534)
);
AOI22X1TS U3331 ( .A0(Raw_mant_NRM_SWR[53]), .A1(n2631), .B0(n2677), .B1(
n1927), .Y(n2539) );
BUFX4TS U3332 ( .A(n2719), .Y(n2670) );
AOI22X1TS U3333 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n2667), .B0(n2623), .B1(
DmP_mant_SHT1_SW[2]), .Y(n2536) );
AOI22X1TS U3334 ( .A0(Raw_mant_NRM_SWR[51]), .A1(n2631), .B0(n2644), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2535) );
NAND2X1TS U3335 ( .A(n2536), .B(n2535), .Y(n2558) );
AOI22X1TS U3336 ( .A0(n2815), .A1(Data_array_SWR[1]), .B0(n2554), .B1(n2558),
.Y(n2538) );
NAND2X1TS U3337 ( .A(Raw_mant_NRM_SWR[52]), .B(n1914), .Y(n2537) );
AOI22X1TS U3338 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n2667), .B0(n2623), .B1(
DmP_mant_SHT1_SW[8]), .Y(n2541) );
AOI22X1TS U3339 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n2631), .B0(n2644), .B1(
n1924), .Y(n2540) );
NAND2X1TS U3340 ( .A(n2541), .B(n2540), .Y(n2567) );
AOI22X1TS U3341 ( .A0(n2712), .A1(Data_array_SWR[7]), .B0(n2554), .B1(n2567),
.Y(n2543) );
NAND2X1TS U3342 ( .A(Raw_mant_NRM_SWR[46]), .B(n1914), .Y(n2542) );
AOI22X1TS U3343 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2667), .B0(n2623), .B1(
n1923), .Y(n2545) );
AOI22X1TS U3344 ( .A0(Raw_mant_NRM_SWR[48]), .A1(n2631), .B0(n2644), .B1(
n1925), .Y(n2544) );
NAND2X1TS U3345 ( .A(n2545), .B(n2544), .Y(n2562) );
AOI22X1TS U3346 ( .A0(n2819), .A1(Data_array_SWR[4]), .B0(n2554), .B1(n2562),
.Y(n2547) );
NAND2X1TS U3347 ( .A(Raw_mant_NRM_SWR[49]), .B(n1826), .Y(n2546) );
BUFX3TS U3348 ( .A(n2553), .Y(n2678) );
BUFX3TS U3349 ( .A(n2559), .Y(n2643) );
AOI22X1TS U3350 ( .A0(n2811), .A1(Data_array_SWR[32]), .B0(
Raw_mant_NRM_SWR[0]), .B1(n2643), .Y(n2552) );
AOI22X1TS U3351 ( .A0(n2631), .A1(Raw_mant_NRM_SWR[1]), .B0(
DmP_mant_SHT1_SW[51]), .B1(n1969), .Y(n2550) );
NAND2X1TS U3352 ( .A(n2550), .B(n2549), .Y(n2809) );
AOI22X1TS U3353 ( .A0(n2554), .A1(n2809), .B0(DmP_mant_SHT1_SW[49]), .B1(
n2718), .Y(n2551) );
BUFX3TS U3354 ( .A(n2553), .Y(n2673) );
BUFX4TS U3355 ( .A(n2570), .Y(n2716) );
AOI22X1TS U3356 ( .A0(n2712), .A1(n1945), .B0(Raw_mant_NRM_SWR[39]), .B1(
n2559), .Y(n2556) );
BUFX4TS U3357 ( .A(n2553), .Y(n2708) );
AOI22X1TS U3358 ( .A0(n2815), .A1(Data_array_SWR[3]), .B0(n2810), .B1(n2558),
.Y(n2561) );
NAND2X1TS U3359 ( .A(Raw_mant_NRM_SWR[48]), .B(n2643), .Y(n2560) );
AOI22X1TS U3360 ( .A0(n2819), .A1(Data_array_SWR[6]), .B0(n2810), .B1(n2562),
.Y(n2564) );
NAND2X1TS U3361 ( .A(Raw_mant_NRM_SWR[45]), .B(n2559), .Y(n2563) );
AOI22X1TS U3362 ( .A0(n2712), .A1(Data_array_SWR[8]), .B0(
Raw_mant_NRM_SWR[35]), .B1(n2559), .Y(n2566) );
AOI22X1TS U3363 ( .A0(n2712), .A1(n1940), .B0(n2810), .B1(n2567), .Y(n2569)
);
NAND2X1TS U3364 ( .A(Raw_mant_NRM_SWR[42]), .B(n2559), .Y(n2568) );
AOI22X1TS U3365 ( .A0(n2815), .A1(Data_array_SWR[26]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n2643), .Y(n2572) );
AOI22X1TS U3366 ( .A0(n2712), .A1(n1942), .B0(Raw_mant_NRM_SWR[40]), .B1(
n2559), .Y(n2574) );
AOI22X1TS U3367 ( .A0(n2712), .A1(n1944), .B0(Raw_mant_NRM_SWR[38]), .B1(
n2559), .Y(n2577) );
AOI22X1TS U3368 ( .A0(n2811), .A1(Data_array_SWR[29]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n2559), .Y(n2580) );
AOI22X1TS U3369 ( .A0(n2819), .A1(Data_array_SWR[16]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n2643), .Y(n2582) );
AOI22X1TS U3370 ( .A0(n2815), .A1(Data_array_SWR[27]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n2643), .Y(n2585) );
AOI22X1TS U3371 ( .A0(n2712), .A1(n1951), .B0(n1950), .B1(n2559), .Y(n2588)
);
AOI22X1TS U3372 ( .A0(n2712), .A1(Data_array_SWR[2]), .B0(n2810), .B1(n2590),
.Y(n2592) );
NAND2X1TS U3373 ( .A(Raw_mant_NRM_SWR[49]), .B(n2559), .Y(n2591) );
AOI22X1TS U3374 ( .A0(n2819), .A1(Data_array_SWR[14]), .B0(
Raw_mant_NRM_SWR[26]), .B1(n2559), .Y(n2595) );
AOI22X1TS U3375 ( .A0(n2819), .A1(n1953), .B0(Raw_mant_NRM_SWR[17]), .B1(
n2643), .Y(n2598) );
AOI22X1TS U3376 ( .A0(n2815), .A1(Data_array_SWR[22]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n2643), .Y(n2600) );
AOI22X1TS U3377 ( .A0(n2815), .A1(Data_array_SWR[24]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2643), .Y(n2603) );
AOI22X1TS U3378 ( .A0(n2712), .A1(n1958), .B0(Raw_mant_NRM_SWR[31]), .B1(
n2559), .Y(n2606) );
AOI22X1TS U3379 ( .A0(n2815), .A1(n1935), .B0(Raw_mant_NRM_SWR[13]), .B1(
n2643), .Y(n2610) );
AOI22X1TS U3380 ( .A0(n2712), .A1(n1946), .B0(Raw_mant_NRM_SWR[36]), .B1(
n2559), .Y(n2612) );
AOI22X1TS U3381 ( .A0(n2815), .A1(n1934), .B0(Raw_mant_NRM_SWR[15]), .B1(
n2643), .Y(n2616) );
AOI22X1TS U3382 ( .A0(n2819), .A1(n1955), .B0(Raw_mant_NRM_SWR[20]), .B1(
n2643), .Y(n2619) );
AOI22X1TS U3383 ( .A0(n2712), .A1(n1959), .B0(Raw_mant_NRM_SWR[29]), .B1(
n2559), .Y(n2621) );
AOI22X1TS U3384 ( .A0(n2819), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[27]), .B1(n2559), .Y(n2625) );
AOI22X1TS U3385 ( .A0(n2815), .A1(n1939), .B0(Raw_mant_NRM_SWR[43]), .B1(
n2559), .Y(n2628) );
AOI22X1TS U3386 ( .A0(n2811), .A1(Data_array_SWR[31]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n2559), .Y(n2633) );
AOI22X1TS U3387 ( .A0(n2819), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[22]), .B1(n2643), .Y(n2637) );
AOI22X1TS U3388 ( .A0(n2815), .A1(Data_array_SWR[5]), .B0(
Raw_mant_NRM_SWR[46]), .B1(n2559), .Y(n2641) );
AOI22X1TS U3389 ( .A0(n2819), .A1(n1952), .B0(Raw_mant_NRM_SWR[18]), .B1(
n2643), .Y(n2646) );
AOI22X1TS U3390 ( .A0(n2811), .A1(n1948), .B0(Raw_mant_NRM_SWR[1]), .B1(
n1826), .Y(n2651) );
AOI22X1TS U3391 ( .A0(n2819), .A1(n1956), .B0(n2718), .B1(
DmP_mant_SHT1_SW[26]), .Y(n2654) );
AOI22X1TS U3392 ( .A0(n2819), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[27]), .B1(n1914), .Y(n2657) );
AOI222X1TS U3393 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n2087), .B0(
Raw_mant_NRM_SWR[13]), .B1(n2708), .C0(n2623), .C1(n1930), .Y(n2682)
);
AOI22X1TS U3394 ( .A0(n2815), .A1(Data_array_SWR[21]), .B0(n2718), .B1(
DmP_mant_SHT1_SW[37]), .Y(n2660) );
AOI22X1TS U3395 ( .A0(n2712), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[36]), .B1(n1914), .Y(n2663) );
AOI22X1TS U3396 ( .A0(n2819), .A1(n1957), .B0(n2718), .B1(
DmP_mant_SHT1_SW[28]), .Y(n2666) );
AOI22X1TS U3397 ( .A0(n2712), .A1(Data_array_SWR[11]), .B0(n2718), .B1(n1938), .Y(n2669) );
AOI222X1TS U3398 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n2087), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2708), .C0(n2623), .C1(n1928), .Y(n2674) );
AOI22X1TS U3399 ( .A0(n2815), .A1(Data_array_SWR[25]), .B0(n2718), .B1(
DmP_mant_SHT1_SW[41]), .Y(n2672) );
AOI222X1TS U3400 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[11]), .B1(n2708), .C0(n2623), .C1(n1929), .Y(n2685)
);
AOI22X1TS U3401 ( .A0(n2815), .A1(n1943), .B0(n2718), .B1(
DmP_mant_SHT1_SW[43]), .Y(n2676) );
AOI22X1TS U3402 ( .A0(n2815), .A1(n1949), .B0(Raw_mant_NRM_SWR[18]), .B1(
n1914), .Y(n2681) );
AOI22X1TS U3403 ( .A0(n2815), .A1(Data_array_SWR[23]), .B0(n2718), .B1(
DmP_mant_SHT1_SW[39]), .Y(n2684) );
AOI22X1TS U3404 ( .A0(n2712), .A1(Data_array_SWR[10]), .B0(n2718), .B1(
DmP_mant_SHT1_SW[17]), .Y(n2688) );
AOI22X1TS U3405 ( .A0(n2815), .A1(n1936), .B0(n2718), .B1(
DmP_mant_SHT1_SW[35]), .Y(n2693) );
AOI22X1TS U3406 ( .A0(n2712), .A1(n1941), .B0(Raw_mant_NRM_SWR[43]), .B1(
n1826), .Y(n2697) );
AOI22X1TS U3407 ( .A0(n2819), .A1(n1954), .B0(n2718), .B1(
DmP_mant_SHT1_SW[30]), .Y(n2701) );
AOI22X1TS U3408 ( .A0(n2819), .A1(Data_array_SWR[12]), .B0(n2718), .B1(n1937), .Y(n2705) );
AOI22X1TS U3409 ( .A0(n2815), .A1(Data_array_SWR[28]), .B0(n2718), .B1(
DmP_mant_SHT1_SW[45]), .Y(n2711) );
AOI22X1TS U3410 ( .A0(n2712), .A1(n1947), .B0(Raw_mant_NRM_SWR[39]), .B1(
n1914), .Y(n2715) );
AOI22X1TS U3411 ( .A0(n2811), .A1(Data_array_SWR[30]), .B0(
DmP_mant_SHT1_SW[47]), .B1(n2718), .Y(n2723) );
NAND2X1TS U3412 ( .A(n3370), .B(LZD_output_NRM2_EW[0]), .Y(
DP_OP_15J75_123_4372_n11) );
MX2X1TS U3413 ( .A(DMP_exp_NRM2_EW[10]), .B(DMP_exp_NRM_EW[10]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1332) );
MX2X1TS U3414 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM_EW[9]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1337) );
MX2X1TS U3415 ( .A(DMP_exp_NRM2_EW[8]), .B(DMP_exp_NRM_EW[8]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1342) );
MX2X1TS U3416 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1347) );
MX2X1TS U3417 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1352) );
MX2X1TS U3418 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1357) );
MX2X1TS U3419 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n1970),
.Y(n1362) );
MX2X1TS U3420 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n1970),
.Y(n1367) );
MX2X1TS U3421 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n1970),
.Y(n1372) );
MX2X1TS U3422 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n1970),
.Y(n1377) );
MX2X1TS U3423 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1382) );
AOI22X1TS U3424 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n2727), .B0(
Raw_mant_NRM_SWR[10]), .B1(n2726), .Y(n2730) );
AOI32X1TS U3425 ( .A0(n2731), .A1(n2730), .A2(n3328), .B0(n2729), .B1(n2730),
.Y(n2738) );
OAI31X1TS U3426 ( .A0(n2741), .A1(n2740), .A2(n2739), .B0(
Shift_reg_FLAGS_7[1]), .Y(n2820) );
OAI2BB1X1TS U3427 ( .A0N(LZD_output_NRM2_EW[5]), .A1N(n1969), .B0(n2820),
.Y(n1161) );
NOR2XLTS U3428 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[1]), .Y(n2754)
);
INVX2TS U3429 ( .A(n2742), .Y(n2743) );
OAI211XLTS U3430 ( .A0(n3454), .A1(n2748), .B0(n2747), .C0(n2746), .Y(n2749)
);
OAI211XLTS U3431 ( .A0(n2754), .A1(n2753), .B0(n2752), .C0(n2751), .Y(n2755)
);
OAI31X1TS U3432 ( .A0(n2757), .A1(n2756), .A2(n2755), .B0(
Shift_reg_FLAGS_7[1]), .Y(n2816) );
OAI2BB1X1TS U3433 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n1969), .B0(n2816),
.Y(n1155) );
OAI2BB1X1TS U3434 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n1969), .B0(n2758),
.Y(n1148) );
AO22XLTS U3435 ( .A0(n2762), .A1(Raw_mant_NRM_SWR[34]), .B0(
Raw_mant_NRM_SWR[32]), .B1(n2761), .Y(n2764) );
OAI211XLTS U3436 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2768), .B0(n2767), .C0(
n2766), .Y(n2774) );
OAI211XLTS U3437 ( .A0(n3327), .A1(n2771), .B0(n2770), .C0(n2769), .Y(n2773)
);
OAI31X1TS U3438 ( .A0(n2775), .A1(n2774), .A2(n2773), .B0(
Shift_reg_FLAGS_7[1]), .Y(n2813) );
OAI2BB1X1TS U3439 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n1969), .B0(n2813),
.Y(n1137) );
OAI2BB1X1TS U3440 ( .A0N(LZD_output_NRM2_EW[1]), .A1N(n1969), .B0(n2776),
.Y(n1151) );
OAI2BB1X1TS U3441 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n1969), .B0(n2777),
.Y(n1158) );
OA22X1TS U3442 ( .A0(n2784), .A1(n2779), .B0(n3468), .B1(
final_result_ieee[52]), .Y(n1619) );
OA22X1TS U3443 ( .A0(n2784), .A1(exp_rslt_NRM2_EW1[1]), .B0(n3468), .B1(
final_result_ieee[53]), .Y(n1618) );
OA22X1TS U3444 ( .A0(n2784), .A1(exp_rslt_NRM2_EW1[2]), .B0(n3468), .B1(
final_result_ieee[54]), .Y(n1617) );
OA22X1TS U3445 ( .A0(n2784), .A1(exp_rslt_NRM2_EW1[3]), .B0(n3468), .B1(
final_result_ieee[55]), .Y(n1616) );
OA22X1TS U3446 ( .A0(n2784), .A1(exp_rslt_NRM2_EW1[4]), .B0(n3468), .B1(
final_result_ieee[56]), .Y(n1615) );
OA22X1TS U3447 ( .A0(n2784), .A1(exp_rslt_NRM2_EW1[5]), .B0(n3468), .B1(
final_result_ieee[57]), .Y(n1614) );
OA22X1TS U3448 ( .A0(n2784), .A1(n2780), .B0(n3468), .B1(
final_result_ieee[58]), .Y(n1613) );
OA22X1TS U3449 ( .A0(n2784), .A1(n2781), .B0(n3468), .B1(
final_result_ieee[59]), .Y(n1612) );
OA22X1TS U3450 ( .A0(n2784), .A1(n2782), .B0(n3468), .B1(
final_result_ieee[60]), .Y(n1611) );
OA22X1TS U3451 ( .A0(n2784), .A1(n2783), .B0(n3468), .B1(
final_result_ieee[61]), .Y(n1610) );
INVX4TS U3452 ( .A(n2146), .Y(n3253) );
AO22XLTS U3453 ( .A0(n3253), .A1(n2785), .B0(n3225), .B1(
final_result_ieee[62]), .Y(n1609) );
INVX2TS U3454 ( .A(n2786), .Y(n2788) );
AOI22X1TS U3455 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n2788), .B1(n3332), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U3456 ( .A(n2788), .B(n2787), .Y(n1824) );
AO22XLTS U3457 ( .A0(n2790), .A1(n2873), .B0(n2792), .B1(n2789), .Y(n1822)
);
AOI22X1TS U3458 ( .A0(n2792), .A1(n3134), .B0(n1969), .B1(n2790), .Y(n1817)
);
AOI22X1TS U3459 ( .A0(n2792), .A1(n1969), .B0(n3240), .B1(n2790), .Y(n1816)
);
BUFX4TS U3460 ( .A(n2799), .Y(n2794) );
BUFX3TS U3461 ( .A(n2793), .Y(n2805) );
AO22XLTS U3462 ( .A0(n2799), .A1(Data_X[3]), .B0(n2806), .B1(intDX_EWSW[3]),
.Y(n1812) );
INVX4TS U3463 ( .A(n2796), .Y(n2797) );
AO22XLTS U3464 ( .A0(n2805), .A1(Data_X[8]), .B0(n2802), .B1(intDX_EWSW[8]),
.Y(n1807) );
AO22XLTS U3465 ( .A0(n2805), .A1(Data_X[11]), .B0(n2800), .B1(intDX_EWSW[11]), .Y(n1804) );
AO22XLTS U3466 ( .A0(n2805), .A1(Data_X[12]), .B0(n2797), .B1(intDX_EWSW[12]), .Y(n1803) );
AO22XLTS U3467 ( .A0(n2794), .A1(Data_X[15]), .B0(n2802), .B1(intDX_EWSW[15]), .Y(n1800) );
AO22XLTS U3468 ( .A0(n2796), .A1(Data_X[17]), .B0(n2797), .B1(intDX_EWSW[17]), .Y(n1798) );
AO22XLTS U3469 ( .A0(n2796), .A1(Data_X[18]), .B0(n2802), .B1(intDX_EWSW[18]), .Y(n1797) );
AO22XLTS U3470 ( .A0(n2796), .A1(Data_X[19]), .B0(n2803), .B1(intDX_EWSW[19]), .Y(n1796) );
AO22XLTS U3471 ( .A0(n2796), .A1(Data_X[20]), .B0(n2806), .B1(intDX_EWSW[20]), .Y(n1795) );
AO22XLTS U3472 ( .A0(n2796), .A1(Data_X[21]), .B0(n2800), .B1(intDX_EWSW[21]), .Y(n1794) );
AO22XLTS U3473 ( .A0(n2796), .A1(Data_X[22]), .B0(n2797), .B1(intDX_EWSW[22]), .Y(n1793) );
AO22XLTS U3474 ( .A0(n2796), .A1(Data_X[23]), .B0(n2131), .B1(intDX_EWSW[23]), .Y(n1792) );
AO22XLTS U3475 ( .A0(n2796), .A1(Data_X[25]), .B0(n2800), .B1(intDX_EWSW[25]), .Y(n1790) );
AO22XLTS U3476 ( .A0(n2805), .A1(Data_X[26]), .B0(n2797), .B1(intDX_EWSW[26]), .Y(n1789) );
AO22XLTS U3477 ( .A0(n2794), .A1(Data_X[27]), .B0(n2803), .B1(intDX_EWSW[27]), .Y(n1788) );
AO22XLTS U3478 ( .A0(n2794), .A1(Data_X[28]), .B0(n2806), .B1(intDX_EWSW[28]), .Y(n1787) );
AO22XLTS U3479 ( .A0(n2794), .A1(Data_X[29]), .B0(n2803), .B1(intDX_EWSW[29]), .Y(n1786) );
AO22XLTS U3480 ( .A0(n2794), .A1(Data_X[30]), .B0(n2795), .B1(intDX_EWSW[30]), .Y(n1785) );
AO22XLTS U3481 ( .A0(n2794), .A1(Data_X[31]), .B0(n2802), .B1(intDX_EWSW[31]), .Y(n1784) );
AO22XLTS U3482 ( .A0(n2794), .A1(Data_X[33]), .B0(n2795), .B1(intDX_EWSW[33]), .Y(n1782) );
AO22XLTS U3483 ( .A0(n2793), .A1(Data_X[45]), .B0(n2807), .B1(intDX_EWSW[45]), .Y(n1770) );
AO22XLTS U3484 ( .A0(n2793), .A1(Data_X[46]), .B0(n2807), .B1(intDX_EWSW[46]), .Y(n1769) );
AO22XLTS U3485 ( .A0(n2794), .A1(Data_X[49]), .B0(n2807), .B1(intDX_EWSW[49]), .Y(n1766) );
AO22XLTS U3486 ( .A0(n2798), .A1(Data_X[50]), .B0(n2807), .B1(intDX_EWSW[50]), .Y(n1765) );
AO22XLTS U3487 ( .A0(n2798), .A1(Data_X[51]), .B0(n2807), .B1(intDX_EWSW[51]), .Y(n1764) );
AO22XLTS U3488 ( .A0(n2797), .A1(intDX_EWSW[53]), .B0(n2808), .B1(Data_X[53]), .Y(n1762) );
AO22XLTS U3489 ( .A0(n2797), .A1(intDX_EWSW[54]), .B0(n2808), .B1(Data_X[54]), .Y(n1761) );
AO22XLTS U3490 ( .A0(n2797), .A1(intDX_EWSW[55]), .B0(n2808), .B1(Data_X[55]), .Y(n1760) );
AO22XLTS U3491 ( .A0(n2797), .A1(intDX_EWSW[56]), .B0(n2808), .B1(Data_X[56]), .Y(n1759) );
AO22XLTS U3492 ( .A0(n2798), .A1(Data_X[57]), .B0(n2807), .B1(intDX_EWSW[57]), .Y(n1758) );
AO22XLTS U3493 ( .A0(n2798), .A1(Data_X[58]), .B0(n2807), .B1(intDX_EWSW[58]), .Y(n1757) );
AO22XLTS U3494 ( .A0(n2798), .A1(Data_X[59]), .B0(n2807), .B1(intDX_EWSW[59]), .Y(n1756) );
AO22XLTS U3495 ( .A0(n2798), .A1(Data_X[60]), .B0(n2807), .B1(intDX_EWSW[60]), .Y(n1755) );
AO22XLTS U3496 ( .A0(n2794), .A1(add_subt), .B0(n2795), .B1(intAS), .Y(n1751) );
AO22XLTS U3497 ( .A0(n2795), .A1(intDY_EWSW[0]), .B0(n2808), .B1(Data_Y[0]),
.Y(n1749) );
AO22XLTS U3498 ( .A0(n2795), .A1(intDY_EWSW[1]), .B0(n2808), .B1(Data_Y[1]),
.Y(n1748) );
AO22XLTS U3499 ( .A0(n2807), .A1(intDY_EWSW[2]), .B0(n2808), .B1(Data_Y[2]),
.Y(n1747) );
AO22XLTS U3500 ( .A0(n2795), .A1(intDY_EWSW[3]), .B0(n2808), .B1(Data_Y[3]),
.Y(n1746) );
AO22XLTS U3501 ( .A0(n2807), .A1(intDY_EWSW[4]), .B0(n2808), .B1(Data_Y[4]),
.Y(n1745) );
AO22XLTS U3502 ( .A0(n2807), .A1(intDY_EWSW[5]), .B0(n2808), .B1(Data_Y[5]),
.Y(n1744) );
AO22XLTS U3503 ( .A0(n2807), .A1(intDY_EWSW[6]), .B0(n2808), .B1(Data_Y[6]),
.Y(n1743) );
AO22XLTS U3504 ( .A0(n2795), .A1(intDY_EWSW[7]), .B0(n2808), .B1(Data_Y[7]),
.Y(n1742) );
AO22XLTS U3505 ( .A0(n2797), .A1(intDY_EWSW[8]), .B0(n2796), .B1(Data_Y[8]),
.Y(n1741) );
AO22XLTS U3506 ( .A0(n2797), .A1(intDY_EWSW[9]), .B0(n2798), .B1(Data_Y[9]),
.Y(n1740) );
AO22XLTS U3507 ( .A0(n2797), .A1(intDY_EWSW[10]), .B0(n2798), .B1(Data_Y[10]), .Y(n1739) );
AO22XLTS U3508 ( .A0(n2797), .A1(intDY_EWSW[11]), .B0(n2798), .B1(Data_Y[11]), .Y(n1738) );
AO22XLTS U3509 ( .A0(n2797), .A1(intDY_EWSW[12]), .B0(n2804), .B1(Data_Y[12]), .Y(n1737) );
AO22XLTS U3510 ( .A0(n2797), .A1(intDY_EWSW[13]), .B0(n2796), .B1(Data_Y[13]), .Y(n1736) );
AO22XLTS U3511 ( .A0(n2797), .A1(intDY_EWSW[14]), .B0(n2796), .B1(Data_Y[14]), .Y(n1735) );
AO22XLTS U3512 ( .A0(n2797), .A1(intDY_EWSW[15]), .B0(n2798), .B1(Data_Y[15]), .Y(n1734) );
AO22XLTS U3513 ( .A0(n2800), .A1(intDY_EWSW[16]), .B0(n2804), .B1(Data_Y[16]), .Y(n1733) );
AO22XLTS U3514 ( .A0(n2800), .A1(intDY_EWSW[17]), .B0(n2798), .B1(Data_Y[17]), .Y(n1732) );
AO22XLTS U3515 ( .A0(n2800), .A1(intDY_EWSW[18]), .B0(n2804), .B1(Data_Y[18]), .Y(n1731) );
AO22XLTS U3516 ( .A0(n2800), .A1(intDY_EWSW[19]), .B0(n2798), .B1(Data_Y[19]), .Y(n1730) );
AO22XLTS U3517 ( .A0(n2800), .A1(intDY_EWSW[20]), .B0(n2808), .B1(Data_Y[20]), .Y(n1729) );
AO22XLTS U3518 ( .A0(n2800), .A1(intDY_EWSW[21]), .B0(n2804), .B1(Data_Y[21]), .Y(n1728) );
AO22XLTS U3519 ( .A0(n2800), .A1(intDY_EWSW[22]), .B0(n2804), .B1(Data_Y[22]), .Y(n1727) );
AO22XLTS U3520 ( .A0(n2800), .A1(intDY_EWSW[23]), .B0(n2804), .B1(Data_Y[23]), .Y(n1726) );
AO22XLTS U3521 ( .A0(n2800), .A1(intDY_EWSW[24]), .B0(n2804), .B1(Data_Y[24]), .Y(n1725) );
AO22XLTS U3522 ( .A0(n2800), .A1(intDY_EWSW[25]), .B0(n2804), .B1(Data_Y[25]), .Y(n1724) );
AO22XLTS U3523 ( .A0(n2800), .A1(intDY_EWSW[26]), .B0(n2799), .B1(Data_Y[26]), .Y(n1723) );
AO22XLTS U3524 ( .A0(n2800), .A1(intDY_EWSW[27]), .B0(n2804), .B1(Data_Y[27]), .Y(n1722) );
AO22XLTS U3525 ( .A0(n2802), .A1(intDY_EWSW[28]), .B0(n2801), .B1(Data_Y[28]), .Y(n1721) );
AO22XLTS U3526 ( .A0(n2802), .A1(intDY_EWSW[29]), .B0(n2801), .B1(Data_Y[29]), .Y(n1720) );
AO22XLTS U3527 ( .A0(n2802), .A1(intDY_EWSW[30]), .B0(n2804), .B1(Data_Y[30]), .Y(n1719) );
AO22XLTS U3528 ( .A0(n2802), .A1(intDY_EWSW[31]), .B0(n2801), .B1(Data_Y[31]), .Y(n1718) );
AO22XLTS U3529 ( .A0(n2802), .A1(intDY_EWSW[32]), .B0(n2801), .B1(Data_Y[32]), .Y(n1717) );
AO22XLTS U3530 ( .A0(n2802), .A1(intDY_EWSW[33]), .B0(n2801), .B1(Data_Y[33]), .Y(n1716) );
AO22XLTS U3531 ( .A0(n2802), .A1(intDY_EWSW[34]), .B0(n2794), .B1(Data_Y[34]), .Y(n1715) );
AO22XLTS U3532 ( .A0(n2802), .A1(intDY_EWSW[35]), .B0(n2808), .B1(Data_Y[35]), .Y(n1714) );
AO22XLTS U3533 ( .A0(n2802), .A1(intDY_EWSW[36]), .B0(n2794), .B1(Data_Y[36]), .Y(n1713) );
AO22XLTS U3534 ( .A0(n2802), .A1(intDY_EWSW[37]), .B0(n2801), .B1(Data_Y[37]), .Y(n1712) );
AO22XLTS U3535 ( .A0(n2802), .A1(intDY_EWSW[38]), .B0(n2805), .B1(Data_Y[38]), .Y(n1711) );
AO22XLTS U3536 ( .A0(n2802), .A1(intDY_EWSW[39]), .B0(n2799), .B1(Data_Y[39]), .Y(n1710) );
AO22XLTS U3537 ( .A0(n2803), .A1(intDY_EWSW[49]), .B0(n2805), .B1(Data_Y[49]), .Y(n1700) );
AO22XLTS U3538 ( .A0(n2806), .A1(intDY_EWSW[52]), .B0(n2804), .B1(Data_Y[52]), .Y(n1697) );
AO22XLTS U3539 ( .A0(n2806), .A1(intDY_EWSW[54]), .B0(n2805), .B1(Data_Y[54]), .Y(n1695) );
AOI22X1TS U3540 ( .A0(n2811), .A1(Data_array_SWR[33]), .B0(n2810), .B1(n2809), .Y(n2812) );
OAI2BB1X1TS U3541 ( .A0N(Raw_mant_NRM_SWR[0]), .A1N(n1826), .B0(n2812), .Y(
n1684) );
AOI22X1TS U3542 ( .A0(n2819), .A1(shift_value_SHT2_EWR[2]), .B0(
Shift_amount_SHT1_EWR[2]), .B1(n2818), .Y(n2814) );
NAND2X1TS U3543 ( .A(n2814), .B(n2813), .Y(n1630) );
AOI22X1TS U3544 ( .A0(n2815), .A1(shift_value_SHT2_EWR[4]), .B0(n2818), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n2817) );
NAND2X1TS U3545 ( .A(n2817), .B(n2816), .Y(n1628) );
AOI22X1TS U3546 ( .A0(n2819), .A1(shift_value_SHT2_EWR[5]), .B0(n2818), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n2821) );
NAND2X1TS U3547 ( .A(n2821), .B(n2820), .Y(n1626) );
NAND2X1TS U3548 ( .A(DmP_EXP_EWSW[52]), .B(n3458), .Y(n2826) );
OAI21XLTS U3549 ( .A0(DmP_EXP_EWSW[52]), .A1(n3458), .B0(n2826), .Y(n2822)
);
NAND2X1TS U3550 ( .A(DmP_EXP_EWSW[53]), .B(n3351), .Y(n2825) );
OAI21XLTS U3551 ( .A0(DmP_EXP_EWSW[53]), .A1(n3351), .B0(n2825), .Y(n2823)
);
XNOR2X1TS U3552 ( .A(n2826), .B(n2823), .Y(n2824) );
BUFX3TS U3553 ( .A(n2877), .Y(n2849) );
AO22XLTS U3554 ( .A0(n2848), .A1(n2824), .B0(n2849), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n1624) );
AOI22X1TS U3555 ( .A0(DMP_EXP_EWSW[53]), .A1(n3356), .B0(n2826), .B1(n2825),
.Y(n2829) );
NOR2X1TS U3556 ( .A(n3353), .B(DMP_EXP_EWSW[54]), .Y(n2830) );
AOI21X1TS U3557 ( .A0(DMP_EXP_EWSW[54]), .A1(n3353), .B0(n2830), .Y(n2827)
);
XNOR2X1TS U3558 ( .A(n2829), .B(n2827), .Y(n2828) );
AO22XLTS U3559 ( .A0(n2848), .A1(n2828), .B0(n2849), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n1623) );
OAI22X1TS U3560 ( .A0(n2830), .A1(n2829), .B0(DmP_EXP_EWSW[54]), .B1(n3355),
.Y(n2833) );
NAND2X1TS U3561 ( .A(DmP_EXP_EWSW[55]), .B(n3354), .Y(n2834) );
XNOR2X1TS U3562 ( .A(n2833), .B(n2831), .Y(n2832) );
AO22XLTS U3563 ( .A0(n2848), .A1(n2832), .B0(n2849), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n1622) );
AOI22X1TS U3564 ( .A0(DMP_EXP_EWSW[55]), .A1(n3360), .B0(n2834), .B1(n2833),
.Y(n2837) );
NOR2X1TS U3565 ( .A(n3357), .B(DMP_EXP_EWSW[56]), .Y(n2838) );
AOI21X1TS U3566 ( .A0(DMP_EXP_EWSW[56]), .A1(n3357), .B0(n2838), .Y(n2835)
);
XNOR2X1TS U3567 ( .A(n2837), .B(n2835), .Y(n2836) );
AO22XLTS U3568 ( .A0(n2848), .A1(n2836), .B0(n2849), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n1621) );
OAI22X1TS U3569 ( .A0(n2838), .A1(n2837), .B0(DmP_EXP_EWSW[56]), .B1(n3359),
.Y(n2840) );
XNOR2X1TS U3570 ( .A(DmP_EXP_EWSW[57]), .B(DMP_EXP_EWSW[57]), .Y(n2839) );
XOR2XLTS U3571 ( .A(n2840), .B(n2839), .Y(n2841) );
AO22XLTS U3572 ( .A0(n2848), .A1(n2841), .B0(n2849), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n1620) );
OAI222X1TS U3573 ( .A0(n2842), .A1(n3464), .B0(n3351), .B1(n2873), .C0(n3313), .C1(n2874), .Y(n1555) );
OAI222X1TS U3574 ( .A0(n2842), .A1(n3358), .B0(n3355), .B1(n2873), .C0(n3312), .C1(n2874), .Y(n1554) );
OAI222X1TS U3575 ( .A0(n2842), .A1(n3465), .B0(n3354), .B1(n2873), .C0(n3309), .C1(n2874), .Y(n1553) );
OAI222X1TS U3576 ( .A0(n2871), .A1(n3314), .B0(n3359), .B1(n2873), .C0(n3310), .C1(n2874), .Y(n1552) );
OAI21XLTS U3577 ( .A0(n2844), .A1(intDX_EWSW[63]), .B0(n2873), .Y(n2843) );
AOI21X1TS U3578 ( .A0(n2844), .A1(intDX_EWSW[63]), .B0(n2843), .Y(n2846) );
AO21XLTS U3579 ( .A0(OP_FLAG_EXP), .A1(n1997), .B0(n2846), .Y(n1545) );
AO22XLTS U3580 ( .A0(n2847), .A1(n2846), .B0(ZERO_FLAG_EXP), .B1(n1933), .Y(
n1544) );
AO22XLTS U3581 ( .A0(n2848), .A1(DMP_EXP_EWSW[0]), .B0(n2849), .B1(
DMP_SHT1_EWSW[0]), .Y(n1542) );
AO22XLTS U3582 ( .A0(n2851), .A1(DMP_SHT1_EWSW[0]), .B0(n3462), .B1(
DMP_SHT2_EWSW[0]), .Y(n1541) );
AO22XLTS U3583 ( .A0(n2848), .A1(DMP_EXP_EWSW[1]), .B0(n2849), .B1(
DMP_SHT1_EWSW[1]), .Y(n1539) );
AO22XLTS U3584 ( .A0(n2851), .A1(DMP_SHT1_EWSW[1]), .B0(n2859), .B1(
DMP_SHT2_EWSW[1]), .Y(n1538) );
INVX2TS U3585 ( .A(n3295), .Y(n2854) );
BUFX3TS U3586 ( .A(n3295), .Y(n2864) );
AO22XLTS U3587 ( .A0(n2848), .A1(DMP_EXP_EWSW[2]), .B0(n2849), .B1(
DMP_SHT1_EWSW[2]), .Y(n1536) );
AO22XLTS U3588 ( .A0(n2851), .A1(DMP_SHT1_EWSW[2]), .B0(n2859), .B1(
DMP_SHT2_EWSW[2]), .Y(n1535) );
INVX4TS U3589 ( .A(n3295), .Y(n3297) );
AO22XLTS U3590 ( .A0(n2852), .A1(DMP_SFG[2]), .B0(n2858), .B1(
DMP_SHT2_EWSW[2]), .Y(n1534) );
AO22XLTS U3591 ( .A0(n2848), .A1(DMP_EXP_EWSW[3]), .B0(n2849), .B1(
DMP_SHT1_EWSW[3]), .Y(n1533) );
AO22XLTS U3592 ( .A0(n2851), .A1(DMP_SHT1_EWSW[3]), .B0(n2859), .B1(
DMP_SHT2_EWSW[3]), .Y(n1532) );
CLKBUFX2TS U3593 ( .A(n2852), .Y(n3279) );
BUFX4TS U3594 ( .A(n3279), .Y(n3293) );
AO22XLTS U3595 ( .A0(n3293), .A1(DMP_SFG[3]), .B0(n2854), .B1(
DMP_SHT2_EWSW[3]), .Y(n1531) );
AO22XLTS U3596 ( .A0(n2848), .A1(DMP_EXP_EWSW[4]), .B0(n2849), .B1(
DMP_SHT1_EWSW[4]), .Y(n1530) );
AO22XLTS U3597 ( .A0(n2851), .A1(DMP_SHT1_EWSW[4]), .B0(n2859), .B1(
DMP_SHT2_EWSW[4]), .Y(n1529) );
AO22XLTS U3598 ( .A0(n2848), .A1(DMP_EXP_EWSW[5]), .B0(n2849), .B1(
DMP_SHT1_EWSW[5]), .Y(n1527) );
AO22XLTS U3599 ( .A0(n2851), .A1(DMP_SHT1_EWSW[5]), .B0(n2859), .B1(
DMP_SHT2_EWSW[5]), .Y(n1526) );
AO22XLTS U3600 ( .A0(n2850), .A1(DMP_EXP_EWSW[6]), .B0(n2849), .B1(
DMP_SHT1_EWSW[6]), .Y(n1524) );
AO22XLTS U3601 ( .A0(n2851), .A1(DMP_SHT1_EWSW[6]), .B0(n2859), .B1(
DMP_SHT2_EWSW[6]), .Y(n1523) );
AO22XLTS U3602 ( .A0(n2850), .A1(DMP_EXP_EWSW[7]), .B0(n2849), .B1(
DMP_SHT1_EWSW[7]), .Y(n1521) );
AO22XLTS U3603 ( .A0(n2851), .A1(DMP_SHT1_EWSW[7]), .B0(n2859), .B1(
DMP_SHT2_EWSW[7]), .Y(n1520) );
AO22XLTS U3604 ( .A0(n2850), .A1(DMP_EXP_EWSW[8]), .B0(n2849), .B1(
DMP_SHT1_EWSW[8]), .Y(n1518) );
AO22XLTS U3605 ( .A0(n2851), .A1(DMP_SHT1_EWSW[8]), .B0(n2859), .B1(
DMP_SHT2_EWSW[8]), .Y(n1517) );
BUFX3TS U3606 ( .A(n3463), .Y(n2855) );
BUFX3TS U3607 ( .A(n2855), .Y(n2856) );
AO22XLTS U3608 ( .A0(n2850), .A1(DMP_EXP_EWSW[9]), .B0(n2856), .B1(
DMP_SHT1_EWSW[9]), .Y(n1515) );
AO22XLTS U3609 ( .A0(n2851), .A1(DMP_SHT1_EWSW[9]), .B0(n2859), .B1(
DMP_SHT2_EWSW[9]), .Y(n1514) );
AO22XLTS U3610 ( .A0(n2850), .A1(DMP_EXP_EWSW[10]), .B0(n2855), .B1(
DMP_SHT1_EWSW[10]), .Y(n1512) );
AO22XLTS U3611 ( .A0(n2851), .A1(DMP_SHT1_EWSW[10]), .B0(n2859), .B1(
DMP_SHT2_EWSW[10]), .Y(n1511) );
AO22XLTS U3612 ( .A0(n2850), .A1(DMP_EXP_EWSW[11]), .B0(n2855), .B1(
DMP_SHT1_EWSW[11]), .Y(n1509) );
AO22XLTS U3613 ( .A0(n2851), .A1(DMP_SHT1_EWSW[11]), .B0(n3462), .B1(
DMP_SHT2_EWSW[11]), .Y(n1508) );
AO22XLTS U3614 ( .A0(n2850), .A1(DMP_EXP_EWSW[12]), .B0(n2856), .B1(
DMP_SHT1_EWSW[12]), .Y(n1506) );
AO22XLTS U3615 ( .A0(n2851), .A1(DMP_SHT1_EWSW[12]), .B0(n3462), .B1(
DMP_SHT2_EWSW[12]), .Y(n1505) );
AO22XLTS U3616 ( .A0(n2850), .A1(DMP_EXP_EWSW[13]), .B0(n2856), .B1(
DMP_SHT1_EWSW[13]), .Y(n1503) );
AO22XLTS U3617 ( .A0(n2851), .A1(DMP_SHT1_EWSW[13]), .B0(n3462), .B1(
DMP_SHT2_EWSW[13]), .Y(n1502) );
AO22XLTS U3618 ( .A0(n2850), .A1(DMP_EXP_EWSW[14]), .B0(n3463), .B1(
DMP_SHT1_EWSW[14]), .Y(n1500) );
AO22XLTS U3619 ( .A0(n2851), .A1(DMP_SHT1_EWSW[14]), .B0(n3462), .B1(
DMP_SHT2_EWSW[14]), .Y(n1499) );
BUFX3TS U3620 ( .A(n3307), .Y(n2861) );
AO22XLTS U3621 ( .A0(n2850), .A1(DMP_EXP_EWSW[15]), .B0(n2855), .B1(
DMP_SHT1_EWSW[15]), .Y(n1497) );
AO22XLTS U3622 ( .A0(n2851), .A1(DMP_SHT1_EWSW[15]), .B0(n3462), .B1(
DMP_SHT2_EWSW[15]), .Y(n1496) );
BUFX3TS U3623 ( .A(n3307), .Y(n2857) );
AO22XLTS U3624 ( .A0(n2850), .A1(DMP_EXP_EWSW[16]), .B0(n2855), .B1(
DMP_SHT1_EWSW[16]), .Y(n1494) );
AO22XLTS U3625 ( .A0(n2851), .A1(DMP_SHT1_EWSW[16]), .B0(n3462), .B1(
DMP_SHT2_EWSW[16]), .Y(n1493) );
AO22XLTS U3626 ( .A0(n2850), .A1(DMP_EXP_EWSW[17]), .B0(n2855), .B1(
DMP_SHT1_EWSW[17]), .Y(n1491) );
AO22XLTS U3627 ( .A0(n2851), .A1(DMP_SHT1_EWSW[17]), .B0(n3462), .B1(
DMP_SHT2_EWSW[17]), .Y(n1490) );
INVX4TS U3628 ( .A(n2877), .Y(n2866) );
AO22XLTS U3629 ( .A0(n2866), .A1(DMP_EXP_EWSW[18]), .B0(n2855), .B1(
DMP_SHT1_EWSW[18]), .Y(n1488) );
AO22XLTS U3630 ( .A0(n2851), .A1(DMP_SHT1_EWSW[18]), .B0(n3462), .B1(
DMP_SHT2_EWSW[18]), .Y(n1487) );
AO22XLTS U3631 ( .A0(n2866), .A1(DMP_EXP_EWSW[19]), .B0(n2855), .B1(
DMP_SHT1_EWSW[19]), .Y(n1485) );
AO22XLTS U3632 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n3462), .B1(
DMP_SHT2_EWSW[19]), .Y(n1484) );
AO22XLTS U3633 ( .A0(n2866), .A1(DMP_EXP_EWSW[20]), .B0(n2855), .B1(
DMP_SHT1_EWSW[20]), .Y(n1482) );
AO22XLTS U3634 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n3462), .B1(
DMP_SHT2_EWSW[20]), .Y(n1481) );
AO22XLTS U3635 ( .A0(n2866), .A1(DMP_EXP_EWSW[21]), .B0(n2855), .B1(
DMP_SHT1_EWSW[21]), .Y(n1479) );
AO22XLTS U3636 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n3462), .B1(
DMP_SHT2_EWSW[21]), .Y(n1478) );
AO22XLTS U3637 ( .A0(n2866), .A1(DMP_EXP_EWSW[22]), .B0(n2855), .B1(
DMP_SHT1_EWSW[22]), .Y(n1476) );
AO22XLTS U3638 ( .A0(busy), .A1(DMP_SHT1_EWSW[22]), .B0(n3462), .B1(
DMP_SHT2_EWSW[22]), .Y(n1475) );
AO22XLTS U3639 ( .A0(n2866), .A1(DMP_EXP_EWSW[23]), .B0(n2855), .B1(
DMP_SHT1_EWSW[23]), .Y(n1473) );
AO22XLTS U3640 ( .A0(busy), .A1(DMP_SHT1_EWSW[23]), .B0(n3462), .B1(
DMP_SHT2_EWSW[23]), .Y(n1472) );
BUFX3TS U3641 ( .A(n3295), .Y(n3130) );
AO22XLTS U3642 ( .A0(n2866), .A1(DMP_EXP_EWSW[24]), .B0(n2855), .B1(
DMP_SHT1_EWSW[24]), .Y(n1470) );
BUFX4TS U3643 ( .A(n3462), .Y(n2860) );
AO22XLTS U3644 ( .A0(busy), .A1(DMP_SHT1_EWSW[24]), .B0(n2860), .B1(
DMP_SHT2_EWSW[24]), .Y(n1469) );
AO22XLTS U3645 ( .A0(n2866), .A1(DMP_EXP_EWSW[25]), .B0(n2855), .B1(
DMP_SHT1_EWSW[25]), .Y(n1467) );
AO22XLTS U3646 ( .A0(busy), .A1(DMP_SHT1_EWSW[25]), .B0(n2860), .B1(
DMP_SHT2_EWSW[25]), .Y(n1466) );
AO22XLTS U3647 ( .A0(n2866), .A1(DMP_EXP_EWSW[26]), .B0(n2856), .B1(
DMP_SHT1_EWSW[26]), .Y(n1464) );
AO22XLTS U3648 ( .A0(busy), .A1(DMP_SHT1_EWSW[26]), .B0(n2860), .B1(
DMP_SHT2_EWSW[26]), .Y(n1463) );
AO22XLTS U3649 ( .A0(n2866), .A1(DMP_EXP_EWSW[27]), .B0(n2856), .B1(
DMP_SHT1_EWSW[27]), .Y(n1461) );
AO22XLTS U3650 ( .A0(n2862), .A1(DMP_SHT1_EWSW[27]), .B0(n2860), .B1(
DMP_SHT2_EWSW[27]), .Y(n1460) );
AO22XLTS U3651 ( .A0(n2866), .A1(DMP_EXP_EWSW[28]), .B0(n2856), .B1(
DMP_SHT1_EWSW[28]), .Y(n1458) );
AO22XLTS U3652 ( .A0(n2862), .A1(DMP_SHT1_EWSW[28]), .B0(n2860), .B1(
DMP_SHT2_EWSW[28]), .Y(n1457) );
AO22XLTS U3653 ( .A0(n2866), .A1(DMP_EXP_EWSW[29]), .B0(n2856), .B1(
DMP_SHT1_EWSW[29]), .Y(n1455) );
AO22XLTS U3654 ( .A0(n2862), .A1(DMP_SHT1_EWSW[29]), .B0(n2860), .B1(
DMP_SHT2_EWSW[29]), .Y(n1454) );
INVX4TS U3655 ( .A(n2877), .Y(n2868) );
AO22XLTS U3656 ( .A0(n2868), .A1(DMP_EXP_EWSW[30]), .B0(n2856), .B1(
DMP_SHT1_EWSW[30]), .Y(n1452) );
AO22XLTS U3657 ( .A0(n2862), .A1(DMP_SHT1_EWSW[30]), .B0(n2860), .B1(
DMP_SHT2_EWSW[30]), .Y(n1451) );
AO22XLTS U3658 ( .A0(n2868), .A1(DMP_EXP_EWSW[31]), .B0(n2856), .B1(
DMP_SHT1_EWSW[31]), .Y(n1449) );
AO22XLTS U3659 ( .A0(n2862), .A1(DMP_SHT1_EWSW[31]), .B0(n2860), .B1(
DMP_SHT2_EWSW[31]), .Y(n1448) );
AO22XLTS U3660 ( .A0(n2868), .A1(DMP_EXP_EWSW[32]), .B0(n2856), .B1(
DMP_SHT1_EWSW[32]), .Y(n1446) );
AO22XLTS U3661 ( .A0(n2862), .A1(DMP_SHT1_EWSW[32]), .B0(n2860), .B1(
DMP_SHT2_EWSW[32]), .Y(n1445) );
AO22XLTS U3662 ( .A0(n2868), .A1(DMP_EXP_EWSW[33]), .B0(n2856), .B1(
DMP_SHT1_EWSW[33]), .Y(n1443) );
AO22XLTS U3663 ( .A0(n2862), .A1(DMP_SHT1_EWSW[33]), .B0(n2860), .B1(
DMP_SHT2_EWSW[33]), .Y(n1442) );
AO22XLTS U3664 ( .A0(n2868), .A1(DMP_EXP_EWSW[34]), .B0(n2856), .B1(
DMP_SHT1_EWSW[34]), .Y(n1440) );
AO22XLTS U3665 ( .A0(n2862), .A1(DMP_SHT1_EWSW[34]), .B0(n2860), .B1(
DMP_SHT2_EWSW[34]), .Y(n1439) );
AO22XLTS U3666 ( .A0(n2868), .A1(DMP_EXP_EWSW[35]), .B0(n2856), .B1(
DMP_SHT1_EWSW[35]), .Y(n1437) );
AO22XLTS U3667 ( .A0(n2862), .A1(DMP_SHT1_EWSW[35]), .B0(n2860), .B1(
DMP_SHT2_EWSW[35]), .Y(n1436) );
AO22XLTS U3668 ( .A0(n2868), .A1(DMP_EXP_EWSW[36]), .B0(n2856), .B1(
DMP_SHT1_EWSW[36]), .Y(n1434) );
AO22XLTS U3669 ( .A0(n2862), .A1(DMP_SHT1_EWSW[36]), .B0(n2860), .B1(
DMP_SHT2_EWSW[36]), .Y(n1433) );
BUFX3TS U3670 ( .A(n3463), .Y(n2865) );
AO22XLTS U3671 ( .A0(n2868), .A1(DMP_EXP_EWSW[37]), .B0(n3463), .B1(
DMP_SHT1_EWSW[37]), .Y(n1431) );
AO22XLTS U3672 ( .A0(n2862), .A1(DMP_SHT1_EWSW[37]), .B0(n2860), .B1(
DMP_SHT2_EWSW[37]), .Y(n1430) );
AO22XLTS U3673 ( .A0(n2868), .A1(DMP_EXP_EWSW[38]), .B0(n3463), .B1(
DMP_SHT1_EWSW[38]), .Y(n1428) );
AO22XLTS U3674 ( .A0(n2862), .A1(DMP_SHT1_EWSW[38]), .B0(n2860), .B1(
DMP_SHT2_EWSW[38]), .Y(n1427) );
AO22XLTS U3675 ( .A0(n2868), .A1(DMP_EXP_EWSW[39]), .B0(n3463), .B1(
DMP_SHT1_EWSW[39]), .Y(n1425) );
AO22XLTS U3676 ( .A0(n2862), .A1(DMP_SHT1_EWSW[39]), .B0(n2860), .B1(
DMP_SHT2_EWSW[39]), .Y(n1424) );
AO22XLTS U3677 ( .A0(n2868), .A1(DMP_EXP_EWSW[40]), .B0(n3463), .B1(
DMP_SHT1_EWSW[40]), .Y(n1422) );
AO22XLTS U3678 ( .A0(n2863), .A1(DMP_SHT1_EWSW[40]), .B0(n2860), .B1(
DMP_SHT2_EWSW[40]), .Y(n1421) );
AO22XLTS U3679 ( .A0(n2868), .A1(DMP_EXP_EWSW[41]), .B0(n3463), .B1(
DMP_SHT1_EWSW[41]), .Y(n1419) );
AO22XLTS U3680 ( .A0(n2863), .A1(DMP_SHT1_EWSW[41]), .B0(n2860), .B1(
DMP_SHT2_EWSW[41]), .Y(n1418) );
INVX4TS U3681 ( .A(n2865), .Y(n2867) );
AO22XLTS U3682 ( .A0(n2867), .A1(DMP_EXP_EWSW[42]), .B0(n3463), .B1(
DMP_SHT1_EWSW[42]), .Y(n1416) );
AO22XLTS U3683 ( .A0(n2863), .A1(DMP_SHT1_EWSW[42]), .B0(n2860), .B1(
DMP_SHT2_EWSW[42]), .Y(n1415) );
AO22XLTS U3684 ( .A0(n2867), .A1(DMP_EXP_EWSW[43]), .B0(n3463), .B1(
DMP_SHT1_EWSW[43]), .Y(n1413) );
AO22XLTS U3685 ( .A0(n2863), .A1(DMP_SHT1_EWSW[43]), .B0(n2860), .B1(
DMP_SHT2_EWSW[43]), .Y(n1412) );
AO22XLTS U3686 ( .A0(n2867), .A1(DMP_EXP_EWSW[44]), .B0(n3463), .B1(
DMP_SHT1_EWSW[44]), .Y(n1410) );
BUFX4TS U3687 ( .A(n3462), .Y(n2881) );
AO22XLTS U3688 ( .A0(n2863), .A1(DMP_SHT1_EWSW[44]), .B0(n2881), .B1(
DMP_SHT2_EWSW[44]), .Y(n1409) );
AO22XLTS U3689 ( .A0(n2867), .A1(DMP_EXP_EWSW[45]), .B0(n3463), .B1(
DMP_SHT1_EWSW[45]), .Y(n1407) );
AO22XLTS U3690 ( .A0(n2863), .A1(DMP_SHT1_EWSW[45]), .B0(n2881), .B1(
DMP_SHT2_EWSW[45]), .Y(n1406) );
AO22XLTS U3691 ( .A0(n2867), .A1(DMP_EXP_EWSW[46]), .B0(n3463), .B1(
DMP_SHT1_EWSW[46]), .Y(n1404) );
AO22XLTS U3692 ( .A0(n2863), .A1(DMP_SHT1_EWSW[46]), .B0(n2881), .B1(
DMP_SHT2_EWSW[46]), .Y(n1403) );
AO22XLTS U3693 ( .A0(n2867), .A1(DMP_EXP_EWSW[47]), .B0(n3463), .B1(
DMP_SHT1_EWSW[47]), .Y(n1401) );
AO22XLTS U3694 ( .A0(n2863), .A1(DMP_SHT1_EWSW[47]), .B0(n2881), .B1(
DMP_SHT2_EWSW[47]), .Y(n1400) );
BUFX4TS U3695 ( .A(n2877), .Y(n2879) );
AO22XLTS U3696 ( .A0(n2867), .A1(DMP_EXP_EWSW[48]), .B0(n2879), .B1(
DMP_SHT1_EWSW[48]), .Y(n1398) );
AO22XLTS U3697 ( .A0(n2863), .A1(DMP_SHT1_EWSW[48]), .B0(n2881), .B1(
DMP_SHT2_EWSW[48]), .Y(n1397) );
AO22XLTS U3698 ( .A0(n2867), .A1(DMP_EXP_EWSW[49]), .B0(n2879), .B1(
DMP_SHT1_EWSW[49]), .Y(n1395) );
AO22XLTS U3699 ( .A0(n2863), .A1(DMP_SHT1_EWSW[49]), .B0(n2881), .B1(
DMP_SHT2_EWSW[49]), .Y(n1394) );
AO22XLTS U3700 ( .A0(n2867), .A1(DMP_EXP_EWSW[50]), .B0(n2879), .B1(
DMP_SHT1_EWSW[50]), .Y(n1392) );
AO22XLTS U3701 ( .A0(n2862), .A1(DMP_SHT1_EWSW[50]), .B0(n2881), .B1(
DMP_SHT2_EWSW[50]), .Y(n1391) );
AO22XLTS U3702 ( .A0(n2867), .A1(DMP_EXP_EWSW[51]), .B0(n2879), .B1(
DMP_SHT1_EWSW[51]), .Y(n1389) );
AO22XLTS U3703 ( .A0(n2863), .A1(DMP_SHT1_EWSW[51]), .B0(n2881), .B1(
DMP_SHT2_EWSW[51]), .Y(n1388) );
AO22XLTS U3704 ( .A0(n2867), .A1(DMP_EXP_EWSW[52]), .B0(n2879), .B1(
DMP_SHT1_EWSW[52]), .Y(n1386) );
AO22XLTS U3705 ( .A0(n2863), .A1(DMP_SHT1_EWSW[52]), .B0(n2881), .B1(
DMP_SHT2_EWSW[52]), .Y(n1385) );
CLKBUFX2TS U3706 ( .A(n2852), .Y(n3298) );
AO22XLTS U3707 ( .A0(n3261), .A1(DMP_SHT2_EWSW[52]), .B0(n3295), .B1(
DMP_SFG[52]), .Y(n1384) );
AO22XLTS U3708 ( .A0(n3136), .A1(DMP_SFG[52]), .B0(n3088), .B1(
DMP_exp_NRM_EW[0]), .Y(n1383) );
AO22XLTS U3709 ( .A0(n2867), .A1(DMP_EXP_EWSW[53]), .B0(n2879), .B1(
DMP_SHT1_EWSW[53]), .Y(n1381) );
AO22XLTS U3710 ( .A0(n2863), .A1(DMP_SHT1_EWSW[53]), .B0(n3462), .B1(
DMP_SHT2_EWSW[53]), .Y(n1380) );
AO22XLTS U3711 ( .A0(n3261), .A1(DMP_SHT2_EWSW[53]), .B0(n3295), .B1(
DMP_SFG[53]), .Y(n1379) );
AO22XLTS U3712 ( .A0(n3136), .A1(DMP_SFG[53]), .B0(n3527), .B1(
DMP_exp_NRM_EW[1]), .Y(n1378) );
AO22XLTS U3713 ( .A0(n3528), .A1(DMP_EXP_EWSW[54]), .B0(n2879), .B1(
DMP_SHT1_EWSW[54]), .Y(n1376) );
AO22XLTS U3714 ( .A0(n2863), .A1(DMP_SHT1_EWSW[54]), .B0(n3462), .B1(
DMP_SHT2_EWSW[54]), .Y(n1375) );
AO22XLTS U3715 ( .A0(n3261), .A1(DMP_SHT2_EWSW[54]), .B0(n3295), .B1(
DMP_SFG[54]), .Y(n1374) );
AO22XLTS U3716 ( .A0(n3024), .A1(DMP_SFG[54]), .B0(n3527), .B1(
DMP_exp_NRM_EW[2]), .Y(n1373) );
AO22XLTS U3717 ( .A0(n3528), .A1(DMP_EXP_EWSW[55]), .B0(n2879), .B1(
DMP_SHT1_EWSW[55]), .Y(n1371) );
AO22XLTS U3718 ( .A0(n2882), .A1(DMP_SHT1_EWSW[55]), .B0(n2881), .B1(
DMP_SHT2_EWSW[55]), .Y(n1370) );
AO22XLTS U3719 ( .A0(n3261), .A1(DMP_SHT2_EWSW[55]), .B0(n3130), .B1(
DMP_SFG[55]), .Y(n1369) );
AO22XLTS U3720 ( .A0(n3528), .A1(DMP_EXP_EWSW[56]), .B0(n2879), .B1(
DMP_SHT1_EWSW[56]), .Y(n1366) );
AO22XLTS U3721 ( .A0(n2882), .A1(DMP_SHT1_EWSW[56]), .B0(n2881), .B1(
DMP_SHT2_EWSW[56]), .Y(n1365) );
AO22XLTS U3722 ( .A0(n3261), .A1(DMP_SHT2_EWSW[56]), .B0(n2864), .B1(
DMP_SFG[56]), .Y(n1364) );
AO22XLTS U3723 ( .A0(n3528), .A1(DMP_EXP_EWSW[57]), .B0(n2879), .B1(
DMP_SHT1_EWSW[57]), .Y(n1361) );
AO22XLTS U3724 ( .A0(n2882), .A1(DMP_SHT1_EWSW[57]), .B0(n2881), .B1(
DMP_SHT2_EWSW[57]), .Y(n1360) );
AO22XLTS U3725 ( .A0(n3261), .A1(DMP_SHT2_EWSW[57]), .B0(n3130), .B1(
DMP_SFG[57]), .Y(n1359) );
AO22XLTS U3726 ( .A0(n3528), .A1(DMP_EXP_EWSW[58]), .B0(n2865), .B1(
DMP_SHT1_EWSW[58]), .Y(n1356) );
AO22XLTS U3727 ( .A0(n2882), .A1(DMP_SHT1_EWSW[58]), .B0(n2881), .B1(
DMP_SHT2_EWSW[58]), .Y(n1355) );
AO22XLTS U3728 ( .A0(n3261), .A1(DMP_SHT2_EWSW[58]), .B0(n2864), .B1(
DMP_SFG[58]), .Y(n1354) );
AO22XLTS U3729 ( .A0(n3528), .A1(DMP_EXP_EWSW[59]), .B0(n2865), .B1(
DMP_SHT1_EWSW[59]), .Y(n1351) );
AO22XLTS U3730 ( .A0(n2882), .A1(DMP_SHT1_EWSW[59]), .B0(n2881), .B1(
DMP_SHT2_EWSW[59]), .Y(n1350) );
AO22XLTS U3731 ( .A0(n3261), .A1(DMP_SHT2_EWSW[59]), .B0(n3130), .B1(
DMP_SFG[59]), .Y(n1349) );
AO22XLTS U3732 ( .A0(n3528), .A1(DMP_EXP_EWSW[60]), .B0(n2865), .B1(
DMP_SHT1_EWSW[60]), .Y(n1346) );
AO22XLTS U3733 ( .A0(n2882), .A1(DMP_SHT1_EWSW[60]), .B0(n2881), .B1(
DMP_SHT2_EWSW[60]), .Y(n1345) );
AO22XLTS U3734 ( .A0(n3261), .A1(DMP_SHT2_EWSW[60]), .B0(n3130), .B1(
DMP_SFG[60]), .Y(n1344) );
AO22XLTS U3735 ( .A0(n3528), .A1(DMP_EXP_EWSW[61]), .B0(n2865), .B1(
DMP_SHT1_EWSW[61]), .Y(n1341) );
AO22XLTS U3736 ( .A0(n2882), .A1(DMP_SHT1_EWSW[61]), .B0(n2881), .B1(
DMP_SHT2_EWSW[61]), .Y(n1340) );
AO22XLTS U3737 ( .A0(n3261), .A1(DMP_SHT2_EWSW[61]), .B0(n3130), .B1(
DMP_SFG[61]), .Y(n1339) );
AO22XLTS U3738 ( .A0(n3090), .A1(DMP_SFG[61]), .B0(n2921), .B1(
DMP_exp_NRM_EW[9]), .Y(n1338) );
AO22XLTS U3739 ( .A0(n3528), .A1(DMP_EXP_EWSW[62]), .B0(n2865), .B1(
DMP_SHT1_EWSW[62]), .Y(n1336) );
AO22XLTS U3740 ( .A0(n2882), .A1(DMP_SHT1_EWSW[62]), .B0(n2881), .B1(
DMP_SHT2_EWSW[62]), .Y(n1335) );
AO22XLTS U3741 ( .A0(n3261), .A1(DMP_SHT2_EWSW[62]), .B0(n3130), .B1(
DMP_SFG[62]), .Y(n1334) );
AO22XLTS U3742 ( .A0(n3528), .A1(DmP_EXP_EWSW[0]), .B0(n2865), .B1(n1927),
.Y(n1330) );
AO22XLTS U3743 ( .A0(n3528), .A1(DmP_EXP_EWSW[1]), .B0(n2865), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1328) );
AO22XLTS U3744 ( .A0(n3528), .A1(DmP_EXP_EWSW[2]), .B0(n2865), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1326) );
AO22XLTS U3745 ( .A0(n3528), .A1(DmP_EXP_EWSW[16]), .B0(n2865), .B1(
DmP_mant_SHT1_SW[16]), .Y(n1298) );
BUFX3TS U3746 ( .A(n3463), .Y(n2870) );
BUFX4TS U3747 ( .A(n2870), .Y(n2869) );
AO22XLTS U3748 ( .A0(n3528), .A1(DmP_EXP_EWSW[20]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[20]), .Y(n1290) );
AO22XLTS U3749 ( .A0(n3528), .A1(DmP_EXP_EWSW[24]), .B0(n2869), .B1(n1921),
.Y(n1282) );
INVX2TS U3750 ( .A(n3463), .Y(n2878) );
OAI222X1TS U3751 ( .A0(n2874), .A1(n3358), .B0(n3353), .B1(n2873), .C0(n3312), .C1(n2871), .Y(n1225) );
OAI222X1TS U3752 ( .A0(n2874), .A1(n3465), .B0(n3360), .B1(n2873), .C0(n3309), .C1(n2872), .Y(n1224) );
OAI222X1TS U3753 ( .A0(n2874), .A1(n3314), .B0(n3357), .B1(n2873), .C0(n3310), .C1(n2872), .Y(n1223) );
NAND2X1TS U3754 ( .A(n3468), .B(n2884), .Y(n2875) );
OAI2BB1X1TS U3755 ( .A0N(underflow_flag), .A1N(n3225), .B0(n2875), .Y(n1221)
);
OA21XLTS U3756 ( .A0(n3468), .A1(overflow_flag), .B0(n2876), .Y(n1220) );
AO22XLTS U3757 ( .A0(n2878), .A1(ZERO_FLAG_EXP), .B0(n3463), .B1(
ZERO_FLAG_SHT1), .Y(n1219) );
AO22XLTS U3758 ( .A0(n2882), .A1(ZERO_FLAG_SHT1), .B0(n2881), .B1(
ZERO_FLAG_SHT2), .Y(n1218) );
AO22XLTS U3759 ( .A0(n3261), .A1(ZERO_FLAG_SHT2), .B0(n3130), .B1(
ZERO_FLAG_SFG), .Y(n1217) );
AO22XLTS U3760 ( .A0(n3468), .A1(ZERO_FLAG_SHT1SHT2), .B0(n3225), .B1(
zero_flag), .Y(n1214) );
AO22XLTS U3761 ( .A0(n2878), .A1(OP_FLAG_EXP), .B0(n2877), .B1(OP_FLAG_SHT1),
.Y(n1213) );
AO22XLTS U3762 ( .A0(n2882), .A1(OP_FLAG_SHT1), .B0(n2881), .B1(OP_FLAG_SHT2), .Y(n1212) );
AO22XLTS U3763 ( .A0(n2880), .A1(SIGN_FLAG_EXP), .B0(n2879), .B1(
SIGN_FLAG_SHT1), .Y(n1210) );
AO22XLTS U3764 ( .A0(n2882), .A1(SIGN_FLAG_SHT1), .B0(n2881), .B1(
SIGN_FLAG_SHT2), .Y(n1209) );
AO22XLTS U3765 ( .A0(n3261), .A1(SIGN_FLAG_SHT2), .B0(n3130), .B1(
SIGN_FLAG_SFG), .Y(n1208) );
OAI211XLTS U3766 ( .A0(n2884), .A1(SIGN_FLAG_SHT1SHT2), .B0(n3468), .C0(
n2883), .Y(n2885) );
OAI2BB1X1TS U3767 ( .A0N(final_result_ieee[63]), .A1N(n3225), .B0(n2885),
.Y(n1205) );
AO22XLTS U3768 ( .A0(n3527), .A1(Raw_mant_NRM_SWR[14]), .B0(n3090), .B1(
n2888), .Y(n1204) );
AO22XLTS U3769 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[24]), .B0(n3136), .B1(
n2912), .Y(n1194) );
AO22XLTS U3770 ( .A0(n3527), .A1(Raw_mant_NRM_SWR[34]), .B0(n3136), .B1(
n2937), .Y(n1184) );
AOI2BB2XLTS U3771 ( .B0(n1905), .B1(n1999), .A0N(n2986), .A1N(n1905), .Y(
n2975) );
AOI2BB2XLTS U3772 ( .B0(n1904), .B1(n3076), .A0N(n2986), .A1N(n1904), .Y(
n2978) );
AOI2BB2XLTS U3773 ( .B0(n1903), .B1(n1999), .A0N(n2986), .A1N(n1903), .Y(
n2981) );
AOI2BB2XLTS U3774 ( .B0(n1902), .B1(n3076), .A0N(n2986), .A1N(n1902), .Y(
n2983) );
XNOR2X1TS U3775 ( .A(n2983), .B(n2982), .Y(n2984) );
AOI22X1TS U3776 ( .A0(n3285), .A1(n2985), .B0(n3293), .B1(n1980), .Y(n1163)
);
AOI2BB2X1TS U3777 ( .B0(DmP_mant_SFG_SWR[10]), .B1(n2986), .A0N(n2986),
.A1N(DmP_mant_SFG_SWR[10]), .Y(n3109) );
CLKAND2X2TS U3778 ( .A(n3109), .B(DMP_SFG[8]), .Y(n2987) );
INVX2TS U3779 ( .A(n3131), .Y(n2988) );
AOI222X1TS U3780 ( .A0(n3133), .A1(n2988), .B0(n3133), .B1(DMP_SFG[10]),
.C0(n2988), .C1(DMP_SFG[10]), .Y(n2989) );
XOR2XLTS U3781 ( .A(n1896), .B(n2989), .Y(n2990) );
AOI22X1TS U3782 ( .A0(n3090), .A1(n2991), .B0(n3315), .B1(n3134), .Y(n1162)
);
AOI22X1TS U3783 ( .A0(n1943), .A1(n3054), .B0(Data_array_SWR[23]), .B1(n3188), .Y(n2993) );
AOI22X1TS U3784 ( .A0(n1936), .A1(n2159), .B0(n1952), .B1(n3189), .Y(n2992)
);
NAND2X1TS U3785 ( .A(n2993), .B(n2992), .Y(n3231) );
AOI22X1TS U3786 ( .A0(Data_array_SWR[14]), .A1(n3080), .B0(
Data_array_SWR[17]), .B1(n2142), .Y(n2995) );
AOI22X1TS U3787 ( .A0(Data_array_SWR[11]), .A1(n2159), .B0(Data_array_SWR[9]), .B1(n3189), .Y(n2994) );
AOI21X1TS U3788 ( .A0(n2995), .A1(n2994), .B0(n2127), .Y(n3000) );
NAND2X1TS U3789 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n3018) );
BUFX3TS U3790 ( .A(n2996), .Y(n3247) );
AOI22X1TS U3791 ( .A0(n1944), .A1(n3228), .B0(Data_array_SWR[1]), .B1(n3247),
.Y(n2998) );
AOI22X1TS U3792 ( .A0(n1940), .A1(n3198), .B0(Data_array_SWR[5]), .B1(n3227),
.Y(n2997) );
OAI211XLTS U3793 ( .A0(n3243), .A1(n3018), .B0(n2998), .C0(n2997), .Y(n2999)
);
AOI211X1TS U3794 ( .A0(n2168), .A1(n3231), .B0(n3000), .C0(n2999), .Y(n3251)
);
NAND2X1TS U3795 ( .A(left_right_SHT2), .B(n3247), .Y(n3033) );
OAI22X1TS U3796 ( .A0(n3239), .A1(n3251), .B0(n3428), .B1(n3033), .Y(n3001)
);
AOI2BB2XLTS U3797 ( .B0(DmP_mant_SFG_SWR[1]), .B1(n3467), .A0N(n3037), .A1N(
DmP_mant_SFG_SWR[1]), .Y(n3002) );
AOI2BB2XLTS U3798 ( .B0(n3090), .B1(n3002), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n1825), .Y(n1159) );
AOI22X1TS U3799 ( .A0(n1956), .A1(n3054), .B0(Data_array_SWR[13]), .B1(n3188), .Y(n3004) );
AOI22X1TS U3800 ( .A0(Data_array_SWR[8]), .A1(n3115), .B0(n1958), .B1(n3125),
.Y(n3003) );
AOI21X1TS U3801 ( .A0(n3004), .A1(n3003), .B0(n2127), .Y(n3008) );
AOI22X1TS U3802 ( .A0(n1945), .A1(n3180), .B0(Data_array_SWR[0]), .B1(n3247),
.Y(n3006) );
AOI22X1TS U3803 ( .A0(n1939), .A1(n3198), .B0(Data_array_SWR[4]), .B1(n3122),
.Y(n3005) );
OAI211XLTS U3804 ( .A0(n3173), .A1(n3018), .B0(n3006), .C0(n3005), .Y(n3007)
);
AOI211X1TS U3805 ( .A0(n2168), .A1(n3009), .B0(n3008), .C0(n3007), .Y(n3304)
);
OAI22X1TS U3806 ( .A0(n3239), .A1(n3304), .B0(n3429), .B1(n3033), .Y(n3010)
);
AOI2BB2XLTS U3807 ( .B0(DmP_mant_SFG_SWR[0]), .B1(n3467), .A0N(n3467), .A1N(
DmP_mant_SFG_SWR[0]), .Y(n3011) );
AOI22X1TS U3808 ( .A0(n1825), .A1(n3011), .B0(n3329), .B1(n3134), .Y(n1156)
);
AOI22X1TS U3809 ( .A0(Data_array_SWR[27]), .A1(n3054), .B0(
Data_array_SWR[24]), .B1(n3188), .Y(n3013) );
AOI22X1TS U3810 ( .A0(n1953), .A1(n3115), .B0(n1935), .B1(n3125), .Y(n3012)
);
NAND2X1TS U3811 ( .A(n3013), .B(n3012), .Y(n3182) );
AOI22X1TS U3812 ( .A0(n1957), .A1(n3054), .B0(Data_array_SWR[15]), .B1(n3188), .Y(n3015) );
AOI22X1TS U3813 ( .A0(n1959), .A1(n2159), .B0(n1951), .B1(n3189), .Y(n3014)
);
AOI21X1TS U3814 ( .A0(n3015), .A1(n3014), .B0(n2127), .Y(n3020) );
AOI22X1TS U3815 ( .A0(n1947), .A1(n3180), .B0(Data_array_SWR[2]), .B1(n3247),
.Y(n3017) );
AOI22X1TS U3816 ( .A0(n1941), .A1(n3198), .B0(Data_array_SWR[6]), .B1(n3122),
.Y(n3016) );
OAI211XLTS U3817 ( .A0(n3213), .A1(n3018), .B0(n3017), .C0(n3016), .Y(n3019)
);
AOI211X1TS U3818 ( .A0(n2168), .A1(n3182), .B0(n3020), .C0(n3019), .Y(n3250)
);
INVX2TS U3819 ( .A(n1948), .Y(n3249) );
OAI22X1TS U3820 ( .A0(n3239), .A1(n3250), .B0(n3249), .B1(n3033), .Y(n3246)
);
AOI2BB2X1TS U3821 ( .B0(DmP_mant_SFG_SWR[2]), .B1(n3526), .A0N(n3075), .A1N(
DmP_mant_SFG_SWR[2]), .Y(n3021) );
NAND2X1TS U3822 ( .A(n3021), .B(DMP_SFG[0]), .Y(n3034) );
AOI22X1TS U3823 ( .A0(n3024), .A1(n3022), .B0(n3328), .B1(n3134), .Y(n1153)
);
XNOR2X1TS U3824 ( .A(DMP_SFG[1]), .B(n3034), .Y(n3023) );
XNOR2X1TS U3825 ( .A(n3023), .B(n3035), .Y(n3025) );
AOI2BB2XLTS U3826 ( .B0(n1825), .B1(n3025), .A0N(Raw_mant_NRM_SWR[3]), .A1N(
n3136), .Y(n1152) );
AOI22X1TS U3827 ( .A0(Data_array_SWR[28]), .A1(n3054), .B0(
Data_array_SWR[25]), .B1(n3188), .Y(n3026) );
OAI2BB1X1TS U3828 ( .A0N(Data_array_SWR[21]), .A1N(n3125), .B0(n3026), .Y(
n3027) );
AOI21X1TS U3829 ( .A0(n1949), .A1(n3115), .B0(n3027), .Y(n3210) );
AO22XLTS U3830 ( .A0(Data_array_SWR[7]), .A1(n3122), .B0(Data_array_SWR[3]),
.B1(n3247), .Y(n3032) );
AOI22X1TS U3831 ( .A0(n1955), .A1(n3054), .B0(Data_array_SWR[16]), .B1(n3188), .Y(n3030) );
AOI22X1TS U3832 ( .A0(n1946), .A1(n3180), .B0(n1942), .B1(n3226), .Y(n3029)
);
AOI22X1TS U3833 ( .A0(Data_array_SWR[12]), .A1(n2159), .B0(
Data_array_SWR[10]), .B1(n3189), .Y(n3028) );
AOI32X1TS U3834 ( .A0(n3030), .A1(n3029), .A2(n3028), .B0(n2127), .B1(n3029),
.Y(n3031) );
AOI211X1TS U3835 ( .A0(shift_value_SHT2_EWR[5]), .A1(n1901), .B0(n3032),
.C0(n3031), .Y(n3248) );
OAI22X1TS U3836 ( .A0(left_right_SHT2), .A1(n3248), .B0(n3427), .B1(n3033),
.Y(n3245) );
AO22XLTS U3837 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[3]), .B0(n2854), .B1(n3245), .Y(n1150) );
AOI2BB2X1TS U3838 ( .B0(DmP_mant_SFG_SWR[4]), .B1(n3467), .A0N(n3467), .A1N(
DmP_mant_SFG_SWR[4]), .Y(n3065) );
INVX2TS U3839 ( .A(n3034), .Y(n3036) );
AOI2BB2X2TS U3840 ( .B0(DmP_mant_SFG_SWR[5]), .B1(n3467), .A0N(n3037), .A1N(
DmP_mant_SFG_SWR[5]), .Y(n3049) );
AOI2BB2XLTS U3841 ( .B0(DMP_SFG[3]), .B1(n3049), .A0N(n3049), .A1N(
DMP_SFG[3]), .Y(n3038) );
XNOR2X1TS U3842 ( .A(n3039), .B(n3038), .Y(n3040) );
AOI2BB2XLTS U3843 ( .B0(n3024), .B1(n3040), .A0N(Raw_mant_NRM_SWR[5]), .A1N(
n3136), .Y(n1149) );
AOI22X1TS U3844 ( .A0(Data_array_SWR[30]), .A1(n3054), .B0(n1943), .B1(n3188), .Y(n3041) );
OAI21XLTS U3845 ( .A0(n3455), .A1(n3056), .B0(n3041), .Y(n3042) );
AOI21X1TS U3846 ( .A0(Data_array_SWR[23]), .A1(n3125), .B0(n3042), .Y(n3220)
);
AO22XLTS U3847 ( .A0(n1940), .A1(n3122), .B0(Data_array_SWR[5]), .B1(n3247),
.Y(n3047) );
AOI22X1TS U3848 ( .A0(n1952), .A1(n3054), .B0(Data_array_SWR[17]), .B1(n3188), .Y(n3045) );
AOI22X1TS U3849 ( .A0(Data_array_SWR[9]), .A1(n3180), .B0(n1944), .B1(n3226),
.Y(n3044) );
AOI22X1TS U3850 ( .A0(Data_array_SWR[11]), .A1(n3115), .B0(
Data_array_SWR[14]), .B1(n3125), .Y(n3043) );
AOI32X1TS U3851 ( .A0(n3045), .A1(n3044), .A2(n3043), .B0(n2127), .B1(n3044),
.Y(n3046) );
OAI22X1TS U3852 ( .A0(n3243), .A1(n3197), .B0(n3239), .B1(n3244), .Y(n3215)
);
AO22XLTS U3853 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[5]), .B0(n3297), .B1(n3215), .Y(n1147) );
NAND2BXLTS U3854 ( .AN(n3065), .B(DMP_SFG[2]), .Y(n3048) );
AOI222X1TS U3855 ( .A0(n3461), .A1(n3049), .B0(n3461), .B1(n3048), .C0(n3049), .C1(n3048), .Y(n3086) );
XNOR2X1TS U3856 ( .A(DMP_SFG[5]), .B(n3050), .Y(n3051) );
XOR2X1TS U3857 ( .A(n3052), .B(n3051), .Y(n3053) );
AOI22X1TS U3858 ( .A0(n3136), .A1(n3053), .B0(n3330), .B1(n3134), .Y(n1146)
);
AOI22X1TS U3859 ( .A0(Data_array_SWR[29]), .A1(n3054), .B0(
Data_array_SWR[26]), .B1(n3188), .Y(n3055) );
AOI21X1TS U3860 ( .A0(Data_array_SWR[22]), .A1(n3125), .B0(n3057), .Y(n3178)
);
AO22XLTS U3861 ( .A0(n1939), .A1(n3122), .B0(Data_array_SWR[4]), .B1(n3247),
.Y(n3063) );
AOI22X1TS U3862 ( .A0(n1954), .A1(n2142), .B0(n1956), .B1(n3080), .Y(n3061)
);
AOI22X1TS U3863 ( .A0(Data_array_SWR[8]), .A1(n3180), .B0(n1945), .B1(n3226),
.Y(n3060) );
AOI22X1TS U3864 ( .A0(Data_array_SWR[13]), .A1(n2159), .B0(n1958), .B1(n3189), .Y(n3059) );
AOI32X1TS U3865 ( .A0(n3061), .A1(n3060), .A2(n3059), .B0(n2127), .B1(n3060),
.Y(n3062) );
OAI22X1TS U3866 ( .A0(left_right_SHT2), .A1(n3214), .B0(n3213), .B1(n3197),
.Y(n3212) );
AO22XLTS U3867 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[4]), .B0(n2854), .B1(n3212), .Y(n1145) );
CMPR32X2TS U3868 ( .A(n3466), .B(n3065), .C(n3064), .CO(n3039), .S(n3066) );
AOI22X1TS U3869 ( .A0(n3136), .A1(n3066), .B0(n3323), .B1(n3134), .Y(n1144)
);
AOI22X1TS U3870 ( .A0(Data_array_SWR[28]), .A1(n3080), .B0(
Data_array_SWR[32]), .B1(n2142), .Y(n3068) );
AOI22X1TS U3871 ( .A0(Data_array_SWR[25]), .A1(n2159), .B0(
Data_array_SWR[21]), .B1(n3189), .Y(n3067) );
NAND2X2TS U3872 ( .A(n3068), .B(n3067), .Y(n3203) );
AOI22X1TS U3873 ( .A0(Data_array_SWR[12]), .A1(n3115), .B0(n1949), .B1(n2142), .Y(n3069) );
OAI2BB1X1TS U3874 ( .A0N(n1955), .A1N(n3080), .B0(n3069), .Y(n3070) );
AOI22X1TS U3875 ( .A0(n1946), .A1(n3198), .B0(n1942), .B1(n3122), .Y(n3072)
);
AOI22X1TS U3876 ( .A0(Data_array_SWR[10]), .A1(n3180), .B0(Data_array_SWR[7]), .B1(n3247), .Y(n3071) );
OAI211XLTS U3877 ( .A0(n1858), .A1(n2127), .B0(n3072), .C0(n3071), .Y(n3073)
);
AOI21X1TS U3878 ( .A0(n2168), .A1(n3203), .B0(n3073), .Y(n3206) );
OAI22X1TS U3879 ( .A0(left_right_SHT2), .A1(n3206), .B0(n3205), .B1(n3197),
.Y(n3187) );
AO22XLTS U3880 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[7]), .B0(n3292), .B1(n3187), .Y(n1143) );
CMPR32X2TS U3881 ( .A(n1931), .B(n3074), .C(n3096), .CO(n3078), .S(n2094) );
XNOR2X1TS U3882 ( .A(DMP_SFG[7]), .B(n3098), .Y(n3077) );
XOR2X1TS U3883 ( .A(n3078), .B(n3077), .Y(n3079) );
AOI22X1TS U3884 ( .A0(n3136), .A1(n3079), .B0(n3317), .B1(n3134), .Y(n1142)
);
AO22XLTS U3885 ( .A0(n1941), .A1(n3122), .B0(Data_array_SWR[6]), .B1(n3247),
.Y(n3085) );
AOI22X1TS U3886 ( .A0(n1957), .A1(n3080), .B0(n1953), .B1(n2142), .Y(n3083)
);
AOI22X1TS U3887 ( .A0(n1947), .A1(n3198), .B0(n1951), .B1(n3228), .Y(n3082)
);
AOI22X1TS U3888 ( .A0(Data_array_SWR[15]), .A1(n2159), .B0(n1959), .B1(n3189), .Y(n3081) );
AOI32X1TS U3889 ( .A0(n3083), .A1(n3082), .A2(n3081), .B0(n2127), .B1(n3082),
.Y(n3084) );
AOI211X1TS U3890 ( .A0(shift_value_SHT2_EWR[5]), .A1(n1900), .B0(n3085),
.C0(n3084), .Y(n3174) );
OAI22X1TS U3891 ( .A0(n3239), .A1(n3174), .B0(n3173), .B1(n3197), .Y(n3171)
);
AO22XLTS U3892 ( .A0(n3307), .A1(n1915), .B0(n3292), .B1(n3171), .Y(n1141)
);
CMPR32X2TS U3893 ( .A(n1932), .B(n3087), .C(n3086), .CO(n3052), .S(n3089) );
AOI22X1TS U3894 ( .A0(Data_array_SWR[14]), .A1(n3115), .B0(n1952), .B1(n3188), .Y(n3091) );
AOI22X1TS U3895 ( .A0(Data_array_SWR[9]), .A1(n3198), .B0(n1944), .B1(n3122),
.Y(n3094) );
AOI22X1TS U3896 ( .A0(Data_array_SWR[11]), .A1(n3180), .B0(n1940), .B1(n3247), .Y(n3093) );
AOI21X1TS U3897 ( .A0(n2168), .A1(n3163), .B0(n3095), .Y(n3170) );
OAI22X1TS U3898 ( .A0(n3239), .A1(n3170), .B0(n3169), .B1(n3197), .Y(n3160)
);
AO22XLTS U3899 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[9]), .B0(n2854), .B1(n3160), .Y(n1139) );
OAI211XLTS U3900 ( .A0(DMP_SFG[7]), .A1(n3098), .B0(n1931), .C0(n3096), .Y(
n3097) );
OAI2BB1X1TS U3901 ( .A0N(n3098), .A1N(DMP_SFG[7]), .B0(n3097), .Y(n3108) );
XNOR2X1TS U3902 ( .A(DMP_SFG[9]), .B(n3099), .Y(n3100) );
XOR2X1TS U3903 ( .A(n3101), .B(n3100), .Y(n3102) );
AOI22X1TS U3904 ( .A0(n3136), .A1(n3102), .B0(n3308), .B1(n3134), .Y(n1138)
);
AOI22X1TS U3905 ( .A0(n1953), .A1(n3080), .B0(Data_array_SWR[15]), .B1(n3115), .Y(n3103) );
AOI22X1TS U3906 ( .A0(n1947), .A1(n3227), .B0(n1951), .B1(n3226), .Y(n3106)
);
AOI22X1TS U3907 ( .A0(n1941), .A1(n3229), .B0(n1959), .B1(n3228), .Y(n3105)
);
OAI211XLTS U3908 ( .A0(n1897), .A1(n2127), .B0(n3106), .C0(n3105), .Y(n3107)
);
AOI21X1TS U3909 ( .A0(n2168), .A1(n3140), .B0(n3107), .Y(n3114) );
OAI22X1TS U3910 ( .A0(n3239), .A1(n3114), .B0(n3137), .B1(n3197), .Y(n3113)
);
AO22XLTS U3911 ( .A0(n3527), .A1(Raw_mant_NRM_SWR[10]), .B0(n3136), .B1(
n3110), .Y(n1135) );
OAI22X1TS U3912 ( .A0(n3114), .A1(n3303), .B0(n3137), .B1(n3242), .Y(n3287)
);
AOI22X1TS U3913 ( .A0(n1954), .A1(n3188), .B0(Data_array_SWR[13]), .B1(n3115), .Y(n3116) );
AOI22X1TS U3914 ( .A0(Data_array_SWR[8]), .A1(n3198), .B0(n1945), .B1(n3122),
.Y(n3120) );
AOI22X1TS U3915 ( .A0(n1958), .A1(n3180), .B0(n1939), .B1(n3247), .Y(n3119)
);
OAI211XLTS U3916 ( .A0(n3153), .A1(n2127), .B0(n3120), .C0(n3119), .Y(n3121)
);
AOI21X1TS U3917 ( .A0(n2168), .A1(n3148), .B0(n3121), .Y(n3159) );
OAI22X1TS U3918 ( .A0(n3239), .A1(n3159), .B0(n3158), .B1(n3197), .Y(n3157)
);
AO22XLTS U3919 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[8]), .B0(n2858), .B1(n3157), .Y(n1132) );
AOI22X1TS U3920 ( .A0(Data_array_SWR[10]), .A1(n3198), .B0(n1946), .B1(n3122), .Y(n3124) );
AOI22X1TS U3921 ( .A0(Data_array_SWR[12]), .A1(n3180), .B0(n1942), .B1(n3229), .Y(n3123) );
OAI211X1TS U3922 ( .A0(n3156), .A1(n3201), .B0(n3124), .C0(n3123), .Y(n3128)
);
AO22XLTS U3923 ( .A0(Data_array_SWR[21]), .A1(n2142), .B0(n1949), .B1(n3080),
.Y(n3127) );
AO22XLTS U3924 ( .A0(n1955), .A1(n3125), .B0(Data_array_SWR[16]), .B1(n3189),
.Y(n3126) );
OAI22X1TS U3925 ( .A0(n3239), .A1(n3155), .B0(n3156), .B1(n3197), .Y(n3154)
);
XNOR2X1TS U3926 ( .A(DMP_SFG[10]), .B(n3131), .Y(n3132) );
XNOR2X1TS U3927 ( .A(n3133), .B(n3132), .Y(n3135) );
AOI22X1TS U3928 ( .A0(n1825), .A1(n3135), .B0(n3327), .B1(n3134), .Y(n1129)
);
INVX2TS U3929 ( .A(n3137), .Y(n3142) );
AOI22X1TS U3930 ( .A0(n3221), .A1(n3141), .B0(n3222), .B1(n3142), .Y(n3139)
);
NAND2X1TS U3931 ( .A(n2156), .B(n3140), .Y(n3138) );
AOI22X1TS U3932 ( .A0(n3223), .A1(n3141), .B0(n3222), .B1(n3140), .Y(n3144)
);
NAND2X1TS U3933 ( .A(n2156), .B(n3142), .Y(n3143) );
AOI22X1TS U3934 ( .A0(n3285), .A1(n3145), .B0(n1986), .B1(n3293), .Y(n1122)
);
INVX2TS U3935 ( .A(n3158), .Y(n3150) );
AOI22X1TS U3936 ( .A0(n3221), .A1(n3149), .B0(n3222), .B1(n3150), .Y(n3147)
);
NAND2X1TS U3937 ( .A(n2156), .B(n3148), .Y(n3146) );
AO22XLTS U3938 ( .A0(n3172), .A1(n3265), .B0(final_result_ieee[22]), .B1(
n3225), .Y(n1118) );
AOI22X1TS U3939 ( .A0(n3223), .A1(n3149), .B0(n3222), .B1(n3148), .Y(n3152)
);
NAND2X1TS U3940 ( .A(n2156), .B(n3150), .Y(n3151) );
OAI22X1TS U3941 ( .A0(n3156), .A1(n3242), .B0(n3155), .B1(n3303), .Y(n3286)
);
AO22XLTS U3942 ( .A0(n3172), .A1(n3286), .B0(final_result_ieee[41]), .B1(
n3240), .Y(n1113) );
OAI22X1TS U3943 ( .A0(n3159), .A1(n3361), .B0(n3158), .B1(n3242), .Y(n3289)
);
INVX2TS U3944 ( .A(n3169), .Y(n3165) );
AOI22X1TS U3945 ( .A0(n3221), .A1(n3164), .B0(n3222), .B1(n3165), .Y(n3162)
);
NAND2X1TS U3946 ( .A(n2156), .B(n3163), .Y(n3161) );
OAI211X1TS U3947 ( .A0(n3168), .A1(n3242), .B0(n3162), .C0(n3161), .Y(n3266)
);
AOI22X1TS U3948 ( .A0(n3223), .A1(n3164), .B0(n3222), .B1(n3163), .Y(n3167)
);
NAND2X1TS U3949 ( .A(n2156), .B(n3165), .Y(n3166) );
OAI211X1TS U3950 ( .A0(n3168), .A1(n3197), .B0(n3167), .C0(n3166), .Y(n3270)
);
OAI22X1TS U3951 ( .A0(n3170), .A1(n3361), .B0(n3169), .B1(n3242), .Y(n3288)
);
OAI22X1TS U3952 ( .A0(n3174), .A1(n3303), .B0(n3173), .B1(n3242), .Y(n3291)
);
AOI22X1TS U3953 ( .A0(Data_array_SWR[13]), .A1(n3227), .B0(n1958), .B1(n3247), .Y(n3177) );
OAI2BB2XLTS U3954 ( .B0(n3249), .B1(n3216), .A0N(n1956), .A1N(n3226), .Y(
n3175) );
AOI21X1TS U3955 ( .A0(n1954), .A1(n3228), .B0(n3175), .Y(n3176) );
OAI211X1TS U3956 ( .A0(n3178), .A1(n2127), .B0(n3177), .C0(n3176), .Y(n3179)
);
INVX2TS U3957 ( .A(n3213), .Y(n3181) );
BUFX3TS U3958 ( .A(n2146), .Y(n3241) );
OAI2BB2XLTS U3959 ( .B0(n3260), .B1(n3241), .A0N(final_result_ieee[18]),
.A1N(n1996), .Y(n1102) );
OAI2BB2XLTS U3960 ( .B0(n3275), .B1(n3241), .A0N(final_result_ieee[32]),
.A1N(n1996), .Y(n1101) );
AOI22X1TS U3961 ( .A0(Data_array_SWR[15]), .A1(n3198), .B0(n1959), .B1(n3227), .Y(n3185) );
AOI22X1TS U3962 ( .A0(n1957), .A1(n3180), .B0(n1951), .B1(n3229), .Y(n3184)
);
AOI22X1TS U3963 ( .A0(n3232), .A1(n3182), .B0(n2168), .B1(n3181), .Y(n3183)
);
NAND3XLTS U3964 ( .A(n3185), .B(n3184), .C(n3183), .Y(n3186) );
AOI22X1TS U3965 ( .A0(n3236), .A1(n1899), .B0(n3303), .B1(n3186), .Y(n3258)
);
OAI2BB2XLTS U3966 ( .B0(n3258), .B1(n3241), .A0N(final_result_ieee[16]),
.A1N(n1996), .Y(n1100) );
AOI22X1TS U3967 ( .A0(n3239), .A1(n3186), .B0(n3237), .B1(n1899), .Y(n3277)
);
OAI2BB2XLTS U3968 ( .B0(n3277), .B1(n3241), .A0N(final_result_ieee[34]),
.A1N(n1996), .Y(n1099) );
AOI22X1TS U3969 ( .A0(Data_array_SWR[25]), .A1(n2142), .B0(
Data_array_SWR[21]), .B1(n3188), .Y(n3191) );
AOI22X1TS U3970 ( .A0(n1949), .A1(n2159), .B0(n1955), .B1(n3189), .Y(n3190)
);
NAND2X1TS U3971 ( .A(n3191), .B(n3190), .Y(n3202) );
INVX2TS U3972 ( .A(n3205), .Y(n3194) );
AOI22X1TS U3973 ( .A0(n3221), .A1(n3202), .B0(n3222), .B1(n3194), .Y(n3193)
);
NAND2X1TS U3974 ( .A(n2156), .B(n3203), .Y(n3192) );
AOI22X1TS U3975 ( .A0(n3223), .A1(n3202), .B0(n3222), .B1(n3203), .Y(n3196)
);
NAND2X1TS U3976 ( .A(n2156), .B(n3194), .Y(n3195) );
AOI22X1TS U3977 ( .A0(Data_array_SWR[12]), .A1(n3198), .B0(n1946), .B1(n3229), .Y(n3200) );
AOI22X1TS U3978 ( .A0(Data_array_SWR[10]), .A1(n3227), .B0(
Data_array_SWR[16]), .B1(n3228), .Y(n3199) );
OAI211X1TS U3979 ( .A0(n3205), .A1(n3201), .B0(n3200), .C0(n3199), .Y(n3204)
);
OAI2BB2XLTS U3980 ( .B0(n3255), .B1(n3241), .A0N(final_result_ieee[13]),
.A1N(n3225), .Y(n1095) );
OAI2BB2XLTS U3981 ( .B0(n3281), .B1(n3241), .A0N(final_result_ieee[37]),
.A1N(n1996), .Y(n1094) );
OAI22X1TS U3982 ( .A0(n3206), .A1(n3303), .B0(n3205), .B1(n3242), .Y(n3290)
);
AOI22X1TS U3983 ( .A0(Data_array_SWR[12]), .A1(n3227), .B0(
Data_array_SWR[10]), .B1(n3229), .Y(n3209) );
OAI2BB2XLTS U3984 ( .B0(n3427), .B1(n3216), .A0N(Data_array_SWR[16]), .A1N(
n3226), .Y(n3207) );
AOI21X1TS U3985 ( .A0(n1955), .A1(n3228), .B0(n3207), .Y(n3208) );
OAI211X1TS U3986 ( .A0(n3210), .A1(n2127), .B0(n3209), .C0(n3208), .Y(n3211)
);
AOI22X1TS U3987 ( .A0(n3236), .A1(n1901), .B0(n3303), .B1(n3211), .Y(n3259)
);
OAI2BB2XLTS U3988 ( .B0(n3259), .B1(n3241), .A0N(final_result_ieee[17]),
.A1N(n3240), .Y(n1092) );
AOI22X1TS U3989 ( .A0(n3239), .A1(n3211), .B0(n3237), .B1(n1901), .Y(n3276)
);
OAI2BB2XLTS U3990 ( .B0(n3276), .B1(n3241), .A0N(final_result_ieee[33]),
.A1N(n1996), .Y(n1091) );
OAI22X1TS U3991 ( .A0(n3214), .A1(n3303), .B0(n3213), .B1(n3242), .Y(n3296)
);
AOI22X1TS U3992 ( .A0(Data_array_SWR[11]), .A1(n3229), .B0(
Data_array_SWR[14]), .B1(n3227), .Y(n3219) );
OAI2BB2XLTS U3993 ( .B0(n3428), .B1(n3216), .A0N(Data_array_SWR[17]), .A1N(
n3226), .Y(n3217) );
AOI21X1TS U3994 ( .A0(n1952), .A1(n3228), .B0(n3217), .Y(n3218) );
OAI211X1TS U3995 ( .A0(n3220), .A1(n2127), .B0(n3219), .C0(n3218), .Y(n3224)
);
INVX2TS U3996 ( .A(n3243), .Y(n3230) );
OAI2BB2XLTS U3997 ( .B0(n3262), .B1(n3241), .A0N(final_result_ieee[19]),
.A1N(n3225), .Y(n1087) );
OAI2BB2XLTS U3998 ( .B0(n3274), .B1(n3241), .A0N(final_result_ieee[31]),
.A1N(n1996), .Y(n1086) );
AOI22X1TS U3999 ( .A0(Data_array_SWR[11]), .A1(n3227), .B0(
Data_array_SWR[14]), .B1(n3226), .Y(n3235) );
AOI22X1TS U4000 ( .A0(Data_array_SWR[9]), .A1(n3229), .B0(Data_array_SWR[17]), .B1(n3228), .Y(n3234) );
AOI22X1TS U4001 ( .A0(n3232), .A1(n3231), .B0(n2168), .B1(n3230), .Y(n3233)
);
NAND3XLTS U4002 ( .A(n3235), .B(n3234), .C(n3233), .Y(n3238) );
AOI22X1TS U4003 ( .A0(n3236), .A1(n1898), .B0(n3303), .B1(n3238), .Y(n3257)
);
OAI2BB2XLTS U4004 ( .B0(n3257), .B1(n3241), .A0N(final_result_ieee[15]),
.A1N(n1996), .Y(n1085) );
AOI22X1TS U4005 ( .A0(n3239), .A1(n3238), .B0(n3237), .B1(n1898), .Y(n3278)
);
OAI2BB2XLTS U4006 ( .B0(n3278), .B1(n3241), .A0N(final_result_ieee[35]),
.A1N(n3240), .Y(n1084) );
OAI22X1TS U4007 ( .A0(n3244), .A1(n3303), .B0(n3243), .B1(n3242), .Y(n3294)
);
NAND2X1TS U4008 ( .A(n3247), .B(n3303), .Y(n3302) );
OAI22X1TS U4009 ( .A0(n3248), .A1(n3361), .B0(n3427), .B1(n3302), .Y(n3299)
);
OAI22X1TS U4010 ( .A0(n3250), .A1(n3361), .B0(n3249), .B1(n3302), .Y(n3300)
);
OAI22X1TS U4011 ( .A0(n3251), .A1(n3361), .B0(n3428), .B1(n3302), .Y(n3301)
);
AOI22X1TS U4012 ( .A0(n3285), .A1(n3254), .B0(n1987), .B1(n2852), .Y(n1077)
);
AOI22X1TS U4013 ( .A0(n3285), .A1(n3255), .B0(n3293), .B1(n1988), .Y(n1076)
);
AOI22X1TS U4014 ( .A0(n3285), .A1(n3256), .B0(n3293), .B1(n1989), .Y(n1075)
);
AOI22X1TS U4015 ( .A0(n3285), .A1(n3257), .B0(n3293), .B1(n1990), .Y(n1074)
);
AOI22X1TS U4016 ( .A0(n3285), .A1(n3258), .B0(n3293), .B1(n1992), .Y(n1073)
);
AOI22X1TS U4017 ( .A0(n3285), .A1(n3259), .B0(n3293), .B1(n1993), .Y(n1072)
);
AOI22X1TS U4018 ( .A0(n3285), .A1(n3260), .B0(n2852), .B1(n1994), .Y(n1071)
);
AOI22X1TS U4019 ( .A0(n3285), .A1(n3262), .B0(n3279), .B1(n1971), .Y(n1070)
);
AOI22X1TS U4020 ( .A0(n3285), .A1(n3263), .B0(n1972), .B1(n2852), .Y(n1069)
);
AO22XLTS U4021 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[23]), .B0(n2858), .B1(
n3264), .Y(n1068) );
AO22XLTS U4022 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[24]), .B0(n2854), .B1(
n3265), .Y(n1067) );
AO22XLTS U4023 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[25]), .B0(n3297), .B1(
n3266), .Y(n1066) );
AO22XLTS U4024 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[26]), .B0(n2854), .B1(
n3267), .Y(n1065) );
AO22XLTS U4025 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[27]), .B0(n3292), .B1(
n3268), .Y(n1064) );
AO22XLTS U4026 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[28]), .B0(n2854), .B1(
n3269), .Y(n1063) );
AO22XLTS U4027 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[29]), .B0(n3297), .B1(
n3270), .Y(n1062) );
AO22XLTS U4028 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[30]), .B0(n2854), .B1(
n3271), .Y(n1061) );
AO22XLTS U4029 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[31]), .B0(n2854), .B1(
n3272), .Y(n1060) );
AOI22X1TS U4030 ( .A0(n3285), .A1(n3273), .B0(n2852), .B1(n1973), .Y(n1059)
);
AOI22X1TS U4031 ( .A0(n3285), .A1(n3274), .B0(n3279), .B1(n1974), .Y(n1058)
);
AOI22X1TS U4032 ( .A0(n3285), .A1(n3275), .B0(n3279), .B1(n1975), .Y(n1057)
);
AOI22X1TS U4033 ( .A0(n3285), .A1(n3276), .B0(n2852), .B1(n1976), .Y(n1056)
);
AOI22X1TS U4034 ( .A0(n3285), .A1(n3277), .B0(n3279), .B1(n1977), .Y(n1055)
);
AOI22X1TS U4035 ( .A0(n3261), .A1(n3278), .B0(n1979), .B1(n3298), .Y(n1054)
);
AOI22X1TS U4036 ( .A0(n3285), .A1(n3280), .B0(n3279), .B1(n1981), .Y(n1053)
);
AOI22X1TS U4037 ( .A0(n3285), .A1(n3281), .B0(n2852), .B1(n1982), .Y(n1052)
);
AOI22X1TS U4038 ( .A0(n3261), .A1(n3282), .B0(n1983), .B1(n3298), .Y(n1051)
);
AOI22X1TS U4039 ( .A0(n3285), .A1(n3283), .B0(n1984), .B1(n2852), .Y(n1050)
);
AOI22X1TS U4040 ( .A0(n3285), .A1(n3284), .B0(n2852), .B1(n1985), .Y(n1049)
);
AO22XLTS U4041 ( .A0(n3293), .A1(n1912), .B0(n3297), .B1(n3286), .Y(n1048)
);
AO22XLTS U4042 ( .A0(n3293), .A1(n1911), .B0(n2858), .B1(n3287), .Y(n1047)
);
AO22XLTS U4043 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[45]), .B0(n2858), .B1(
n3288), .Y(n1046) );
AO22XLTS U4044 ( .A0(n3293), .A1(n1910), .B0(n3306), .B1(n3289), .Y(n1045)
);
AO22XLTS U4045 ( .A0(n3293), .A1(n1909), .B0(n3292), .B1(n3290), .Y(n1044)
);
AO22XLTS U4046 ( .A0(n3293), .A1(n1908), .B0(n3297), .B1(n3291), .Y(n1043)
);
AO22XLTS U4047 ( .A0(n3295), .A1(n1907), .B0(n3306), .B1(n3294), .Y(n1042)
);
AO22XLTS U4048 ( .A0(n3298), .A1(n1906), .B0(n2858), .B1(n3296), .Y(n1041)
);
AO22XLTS U4049 ( .A0(n3307), .A1(n1905), .B0(n3306), .B1(n3299), .Y(n1040)
);
AO22XLTS U4050 ( .A0(n2852), .A1(n1904), .B0(n3306), .B1(n3300), .Y(n1039)
);
AO22XLTS U4051 ( .A0(n2852), .A1(n1903), .B0(n3306), .B1(n3301), .Y(n1038)
);
OAI22X1TS U4052 ( .A0(n3304), .A1(n3303), .B0(n3429), .B1(n3302), .Y(n3305)
);
AO22XLTS U4053 ( .A0(n3307), .A1(n1902), .B0(n3306), .B1(n3305), .Y(n1037)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk30.tcl_ETAIIN16Q4_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__OR4BB_PP_BLACKBOX_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4BB_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2I_BLACKBOX_V
`define SKY130_FD_SC_MS__MUX2I_BLACKBOX_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__mux2i (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2I_BLACKBOX_V
|
`include "register_file.v"
`define SIZE_DECODE_REG 64
`define DATA_SIZE_8 2'b00
`define DATA_SIZE_16 2'b01
`define DATA_SIZE_32 2'b10
`define DIR_L2R 2'b00
`define DIR_R2L 2'b01
`define DIR_NOP 2'b10
module decoder(
input i_clk,
input i_reset,
input i_ready,
input[31:0] i_data,
output[1:0] o_instr_size);
string mnemonic;
reg[31:0] opcode;
reg[1:0] instr_size;
assign o_instr_size = instr_size;
reg[`SIZE_DECODE_REG-1:0] decode_reg;
reg[`SIZE_DECODE_REG-1:0] decode_tmp_reg;
reg[`SIZE_DECODE_REG-1:0] decode_hold_reg;
reg[3:0] count_bytes_in_hold_reg;
reg[3:0] count_bytes_in_decode_reg;
reg[3:0] count_bytes_instr;
reg[2:0] count_bytes_in_prefix;
reg[2:0] data_size;
reg[2:0] direction;
reg[3:0] minRequiredBytes;
reg isImmediate;
reg hasStartAddress;
reg isRegImplicit;
reg[2:0] implicitRegVal;
reg[31:0] last_address;
reg process_modrm;
string non_modrm = "";
initial begin
decode_reg = `SIZE_DECODE_REG'b0;
decode_tmp_reg = `SIZE_DECODE_REG'b0;
decode_hold_reg = `SIZE_DECODE_REG'b0;
count_bytes_in_hold_reg = 4'h0;
count_bytes_in_decode_reg = 4'h0;
count_bytes_instr = 4'h0;
count_bytes_in_prefix = 3'b0;
data_size = `DATA_SIZE_32;
direction = `DIR_L2R;
isImmediate = 1'b0;
hasStartAddress = 1'b0;
isRegImplicit = 1'b0;
implicitRegVal = 3'b000;
end
always @(i_reset or i_data) begin
if (i_reset) begin
decode_reg = `SIZE_DECODE_REG'b0;
decode_tmp_reg = `SIZE_DECODE_REG'b0;
decode_hold_reg = `SIZE_DECODE_REG'b0;
count_bytes_in_hold_reg = 4'h0;
count_bytes_in_decode_reg = 4'h0;
count_bytes_instr = 4'h0;
count_bytes_in_prefix = 3'b0;
data_size = `DATA_SIZE_32;
direction = `DIR_R2L;
isImmediate = 1'b0;
hasStartAddress = 1'b0;
isRegImplicit = 1'b0;
implicitRegVal = 3'b000;
end
if (!i_reset && i_ready && !hasStartAddress) begin
hasStartAddress <= 1'b1;
last_address <= i_data;
$display("Got address");
end
if (!i_reset && i_ready && hasStartAddress) begin
decode_tmp_reg = i_data;
decode_reg = (decode_hold_reg | (decode_tmp_reg<<(8*count_bytes_in_hold_reg)));
decode_hold_reg = decode_reg; // keep a copy here.
count_bytes_in_decode_reg = count_bytes_in_hold_reg + 4; // Every time we get a 32 bit input from memory
count_bytes_in_hold_reg = count_bytes_in_decode_reg;
count_bytes_instr = 4'h0;
count_bytes_in_prefix = 3'b0;
process_modrm = 1'b1;
non_modrm = "";
direction = `DIR_R2L;
isImmediate = 1'b0;
isRegImplicit = 1'b0;
implicitRegVal = 3'b000;
/******* Start of Prefix Decoding ********/
if (decode_reg[7:0] == 8'hf0) begin // LOCK
count_bytes_in_prefix = 1;
end
decode_reg = (decode_hold_reg >> (8*count_bytes_in_prefix));
if ((decode_reg[7:0] == 8'hf3) || (decode_reg[7:0] == 8'hf2)) begin // String prefixes
count_bytes_in_prefix = count_bytes_in_prefix + 1;
end
decode_reg = (decode_hold_reg >> (8*count_bytes_in_prefix));
case(decode_reg[7:0]) //Segment override TODO: Not handling segment override for now
8'h2e: count_bytes_in_prefix = count_bytes_in_prefix + 1; // CS
8'h36: count_bytes_in_prefix = count_bytes_in_prefix + 1; // SS
8'h3e: count_bytes_in_prefix = count_bytes_in_prefix + 1; // DS
8'h26: count_bytes_in_prefix = count_bytes_in_prefix + 1; // ES
8'h64: count_bytes_in_prefix = count_bytes_in_prefix + 1; // FS
8'h65: count_bytes_in_prefix = count_bytes_in_prefix + 1; // GS
endcase
decode_reg = (decode_hold_reg >> (8*count_bytes_in_prefix));
if (decode_reg[7:0] == 8'h66) begin // Operand Override
count_bytes_in_prefix = count_bytes_in_prefix + 1;
data_size = `DATA_SIZE_16;
end
decode_reg = (decode_hold_reg >> (8*count_bytes_in_prefix));
if (decode_reg[7:0] == 8'h67) begin // Address Override TODO: Not supporting this
count_bytes_in_prefix = count_bytes_in_prefix + 1;
end
decode_reg = (decode_hold_reg >> (8*count_bytes_in_prefix));
/******* End of Prefix Decoding ********/
count_bytes_instr = count_bytes_in_prefix;
if (count_bytes_instr < count_bytes_in_decode_reg) begin // We start the decoding only if we have enough bytes in decode reg
if (decode_reg[7:0] == 8'h0f) begin // 2 Byte opcode
count_bytes_instr = count_bytes_instr + 1;
decode_reg = (decode_hold_reg >> (8*count_bytes_instr));
//TODO: Decode 2 byte opcode..not doing this for now
end
else begin // 1 byte opcode
if ((decode_reg[7:0] == 8'h00) ||
(decode_reg[7:0] == 8'h01) ||
(decode_reg[7:0] == 8'h02) ||
(decode_reg[7:0] == 8'h03) ||
(decode_reg[7:0] == 8'h04) ||
(decode_reg[7:0] == 8'h05) ||
(decode_reg[7:0] == 8'h80) ||
(decode_reg[7:0] == 8'h81) ||
(decode_reg[7:0] == 8'h83)) begin
mnemonic = "add";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h28) ||
(decode_reg[7:0] == 8'h29) ||
(decode_reg[7:0] == 8'h2a) ||
(decode_reg[7:0] == 8'h2b) ||
(decode_reg[7:0] == 8'h2c) ||
(decode_reg[7:0] == 8'h2d) ||
(decode_reg[7:0] == 8'h80) ||
(decode_reg[7:0] == 8'h81) ||
(decode_reg[7:0] == 8'h83)) begin
mnemonic = "sub";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h20) ||
(decode_reg[7:0] == 8'h21) ||
(decode_reg[7:0] == 8'h22) ||
(decode_reg[7:0] == 8'h23) ||
(decode_reg[7:0] == 8'h24) ||
(decode_reg[7:0] == 8'h25) ||
(decode_reg[7:0] == 8'h80) ||
(decode_reg[7:0] == 8'h81) ||
(decode_reg[7:0] == 8'h83)) begin
mnemonic = "and";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h3a) ||
(decode_reg[7:0] == 8'h3b) ||
(decode_reg[7:0] == 8'h3c) ||
(decode_reg[7:0] == 8'h3d) ||
(decode_reg[7:0] == 8'h38) ||
(decode_reg[7:0] == 8'h39) ||
(decode_reg[7:0] == 8'h80) ||
(decode_reg[7:0] == 8'h81) ||
(decode_reg[7:0] == 8'h83)) begin
mnemonic = "cmp";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h30) ||
(decode_reg[7:0] == 8'h31) ||
(decode_reg[7:0] == 8'h32) ||
(decode_reg[7:0] == 8'h33) ||
(decode_reg[7:0] == 8'h34) ||
(decode_reg[7:0] == 8'h35) ||
(decode_reg[7:0] == 8'h80) ||
(decode_reg[7:0] == 8'h81) ||
(decode_reg[7:0] == 8'h83)) begin
mnemonic = "xor";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h86) ||
(decode_reg[7:0] == 8'h87) ||
(decode_reg[7:0] == 8'h90) ||
(decode_reg[7:0] == 8'h91)) begin
mnemonic = "xchg";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h07) ||
(decode_reg[7:0] == 8'h17) ||
(decode_reg[7:0] == 8'h1f) ||
(decode_reg[7:0] == 8'h58) ||
(decode_reg[7:0] == 8'h8f) ||
(decode_reg[7:0] == 8'h0f) ||
(decode_reg[7:4] == 4'h5 && decode_reg[3] == 1'b1)) begin
mnemonic = "pop";// TODO: Some opcode handline is missing here
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[7:4] == 4'h5 && decode_reg[3] == 1'b1) begin
isRegImplicit = 1'b1;
implicitRegVal = decode_reg[2:0];
minRequiredBytes = count_bytes_instr;
end
else if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
else if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
else if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h0e) ||
(decode_reg[7:0] == 8'h16) ||
(decode_reg[7:0] == 8'h1e) ||
(decode_reg[7:0] == 8'h06) ||
(decode_reg[7:0] == 8'h0f) ||
(decode_reg[7:0] == 8'h68) ||
(decode_reg[7:0] == 8'h6A) ||
(decode_reg[7:4] == 4'h5 && decode_reg[3] == 1'b0)) begin
mnemonic = "push";// TODO: Some opcode handline is missing here
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[7:4] == 4'h5 && decode_reg[3] == 1'b0) begin
isRegImplicit = 1'b1;
implicitRegVal = decode_reg[2:0];
minRequiredBytes = count_bytes_instr;
end
else if (decode_reg[7:0] == 8'h68) begin
count_bytes_instr = count_bytes_instr + 4;
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
$sformat(non_modrm, "$0x%x", decode_reg[39:8]);
end
end
else if (decode_reg[7:0] == 8'h6A) begin
count_bytes_instr = count_bytes_instr + 2;
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
$sformat(non_modrm, "$0x%x", decode_reg[23:8]);
end
end
end
else if ((decode_reg[7:0] == 8'hfe) ||
(decode_reg[7:0] == 8'h48)) begin
mnemonic = "dec";// TODO: Some opcode handline is missing here
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'hf6) ||
(decode_reg[7:0] == 8'hf7)) begin
mnemonic = "div";// TODO: Some opcode handline is missing here
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'ha0) ||
(decode_reg[7:0] == 8'ha1) ||
(decode_reg[7:0] == 8'ha2) ||
(decode_reg[7:0] == 8'ha3) ||
(decode_reg[7:0] == 8'hb0) ||
(decode_reg[7:0] == 8'hb8) ||
(decode_reg[7:0] == 8'hc6) ||
(decode_reg[7:0] == 8'hc7) ||
(decode_reg[7:0] == 8'h8a) ||
(decode_reg[7:0] == 8'h8b) ||
(decode_reg[7:0] == 8'h8c) ||
(decode_reg[7:0] == 8'h8e) ||
(decode_reg[7:0] == 8'h88) ||
(decode_reg[7:0] == 8'h89)) begin
mnemonic = "mov";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
/*if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end*/
end
else if (decode_reg[7:0] == 8'h8d) begin
mnemonic = "lea";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'he8) ||
(decode_reg[7:0] == 8'hff) ||
(decode_reg[7:0] == 8'h9a)) begin
mnemonic = "call";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[7:0] == 8'he8) begin
count_bytes_instr = count_bytes_instr + 4;
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
$sformat(non_modrm, "$0x%x", decode_reg[39:8]);
end
end
else begin
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
end
else if ((decode_reg[7:0] == 8'hea) ||
(decode_reg[7:0] == 8'heb) ||
(decode_reg[7:0] == 8'he9)) begin
mnemonic = "jmp"; // TODO: handle 8/16/32 bit jmp for now all are 32
count_bytes_instr = count_bytes_instr + 1;
count_bytes_instr = count_bytes_instr + 4;
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
$sformat(non_modrm, "$0x%x", decode_reg[39:8]);
end
end
else if ((decode_reg[7:0] == 8'hc2) ||
(decode_reg[7:0] == 8'hc3) ||
(decode_reg[7:0] == 8'hca) ||
(decode_reg[7:0] == 8'hcb)) begin
mnemonic = "ret";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[7:0] == 8'hc3 || decode_reg[7:0] == 8'hcb) begin
end
else begin
count_bytes_instr = count_bytes_instr + 2; // 2 byte immediate
$sformat(non_modrm, "$0x%x", decode_reg[23:8]);
end
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
end
else if (decode_reg[7:0] == 8'hf4) begin
mnemonic = "hlt";
count_bytes_instr = count_bytes_instr + 1;
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
end
else begin
$display("Unidentified instr %x", decode_reg);
end
if (isRegImplicit == 1'b1) begin
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
display(last_address, get_code(decode_reg, minRequiredBytes), mnemonic, get_reg(implicitRegVal));
prepare_for_next_instr(decode_reg, decode_hold_reg, minRequiredBytes, count_bytes_in_hold_reg, count_bytes_in_decode_reg, last_address);
end
end
else if (process_modrm) begin
if (count_bytes_instr < count_bytes_in_decode_reg) begin // This means it has the mod/rm byte
minRequiredBytes = (count_bytes_instr + 1 + instruction_length(decode_reg[15:8], data_size, direction, isImmediate));
if (minRequiredBytes <= count_bytes_in_decode_reg) begin
display(last_address, get_code(decode_reg, minRequiredBytes), mnemonic, decode_mod_reg_rm(decode_reg, data_size, direction, isImmediate));
prepare_for_next_instr(decode_reg, decode_hold_reg, minRequiredBytes, count_bytes_in_hold_reg, count_bytes_in_decode_reg, last_address);
end
end
end
else begin
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
display(last_address, get_code(decode_reg, minRequiredBytes), mnemonic, non_modrm);
prepare_for_next_instr(decode_reg, decode_hold_reg, minRequiredBytes, count_bytes_in_hold_reg, count_bytes_in_decode_reg, last_address);
end
end
$display("decode reg curr val %x", decode_reg);
end
end
end
else begin
instr_size <= 1'bx;
end
end
// Shift data in decode register by appropriate bytes and tranfer the same to the hold register to be processed with next instruction
// and simulataneously update the respective byte counters.
task prepare_for_next_instr(
inout[`SIZE_DECODE_REG - 1: 0] decode_reg,
inout[`SIZE_DECODE_REG - 1: 0] decode_hold_reg,
reg[3:0] minRequiredBytes,
inout[3:0] count_bytes_in_hold_reg,
inout[3:0] count_bytes_in_decode_reg,
inout[31:0] last_address);
decode_reg = (decode_hold_reg >> (8*minRequiredBytes));
decode_hold_reg = decode_reg;
count_bytes_in_decode_reg = count_bytes_in_hold_reg - minRequiredBytes; // No need to do this only need to update the hold reg count val
count_bytes_in_hold_reg = count_bytes_in_decode_reg;
last_address = last_address + minRequiredBytes;
endtask
task display(
input[31:0] instr_address,
string bytes,
string opcode,
string operands);
$display("%x:\t%-24s\t %-5s %s", last_address, bytes, opcode, operands);
endtask
function string get_code(input[`SIZE_DECODE_REG-1:0] data, reg[3:0] num_bytes);
string result = "";
string tmpStr = "";
reg[3:0] byte_index;
reg[`SIZE_DECODE_REG-1:0] tmp;
result = "";
for (byte_index = 0; byte_index < num_bytes; byte_index = byte_index + 1) begin
tmp = data >> (byte_index * 8);
tmpStr = result;
$sformat(result, "%s %x", tmpStr, tmp[7:0]);
end
return result;
endfunction
//TODO: Not supporting immediate data mode for 00, 01 and 10 cases
function string decode_mod_reg_rm(input[63:0] data, reg[1:0] data_size, reg[1:0] direction, reg isImmediate); // Assuming instr length 1 byte and 1 byte for mod-rm and max 4 byte displacement
string result = "";
string srcImmediate = "";
case(data[15:14]) // Mod bits
2'b00: begin // Indirect addressing mode
if (data[10:8] == 3'b100) begin // SIB Addressing mode
if (data[23:22] > 0) // scaling present, TODO - verify 32 but displacement
$sformat(result, "%s, (%s, %s*%d+%x)", get_reg(data[13:11], data_size), get_reg(data[18:16], data_size), get_reg(data[21:19], data_size), get_scale(data[23:22]), data[55:24]);
else
$sformat(result, "%s, (%s, %s+%x)", get_reg(data[13:11], data_size), get_reg(data[18:16], data_size), get_reg(data[21:19], data_size), data[55:24]);
end
else if (data[10:8] == 3'b101) begin // Displacement mode
$sformat(result, "%x", data[47:16]);
end
else begin
result = {"(", get_reg(data[10:8], data_size), ")", ", ", get_reg(data[13:11], data_size)};
end
end
2'b01: begin // Same as above but with 8 bit displacement
if (data[10:8] == 3'b100) begin // SIB Addressing mode
if (data[23:22] > 0) // scaling present
$sformat(result, "%s, (%s,%s*%d+%x)", get_reg(data[13:11], data_size), get_reg(data[18:16], data_size), get_reg(data[21:19], data_size), get_scale(data[23:22]), data[31:24]);
else
$sformat(result, "%s, (%s, %s+%x)", get_reg(data[13:11], data_size), get_reg(data[18:16], data_size), get_reg(data[21:19], data_size), data[31:24]);
end
else if (data[10:8] == 3'b101) begin // Displacement mode
$sformat(result, "%x", data[23:16]);
end
else begin
result = {"(", get_reg(data[10:8], data_size), ")", ", ", get_reg(data[13:11], data_size)};
end
end
2'b10: begin // 32-bit Displacement will be added to reg directly, TODO - Verify 32 bit displacement
$sformat(result, "(%s+%x)", get_reg(data[10:8], data_size), data[47:16]);
end
2'b11: begin // Direct addressing
if (isImmediate == 1'b0) begin
result = {get_reg(data[13:11], data_size), ", ", get_reg(data[10:8], data_size)};
end
else begin
if (data_size == `DATA_SIZE_8 || direction == 1'b1) begin
$sformat(srcImmediate, "$0x%x", data[23:16]); // 8 bit immediate data
end
else if (data_size == `DATA_SIZE_16)
$sformat(srcImmediate, "$0x%x", data[31:16]); // 16 bit immediate data
else
$sformat(srcImmediate, "$0x%x", data[47:16]); // 32 bit immediate data
result = {srcImmediate, ",", get_reg(data[10:8], data_size)};
end
end
endcase
return result;
endfunction
function [3:0] get_scale(input[1:0] scale_bits); // Scale value corresponding to scale bits
case(scale_bits)
2'b00: get_scale = 4'h1;
2'b01: get_scale = 4'h2;
2'b10: get_scale = 4'h4;
2'b11: get_scale = 4'h8;
endcase
endfunction
function [3:0] instruction_length(input[7:0] modrm, reg[1:0] data_size, reg[1:0] direction, reg isImmediate); // nstruction length apart from prefix, opcode and mod/rm length
reg[3:0] count_sib = 0;
reg[3:0] count_displacement = 0;
reg[3:0] count_immediate = 0;
count_sib = 0;
count_displacement = 0;
count_immediate = 0;
case(modrm[7:6]) // mod bits
2'b00: begin
if (modrm[2:0] == 3'b100) begin
count_sib = 31'd1;
count_displacement = 31'd4;
end
else if (modrm[2:0] == 3'b101) begin
count_displacement = 31'd4;
end
end
2'b01: begin
if (modrm[2:0] == 3'b100) begin
count_sib = 31'd1;
count_displacement = 31'd1;
end
else if (modrm[2:0] == 3'b101) begin
count_displacement = 31'd1;
end
end
2'b10: begin
count_displacement = 31'd4;
end
2'b11: begin
if (isImmediate == 1'b1) begin
if (data_size == `DATA_SIZE_8 || direction == 1'b1) begin
count_immediate = 1;
end
else if (data_size == `DATA_SIZE_16)
count_immediate = 2;
else
count_immediate = 4;
end
end
endcase
instruction_length = count_sib + count_displacement + count_immediate;
endfunction
function string get_reg(input[2:0] code, input[1:0] data_size = `DATA_SIZE_32);
case (code)
3'b000: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%al";
else if (data_size == `DATA_SIZE_16)
get_reg = "%ax";
else
get_reg = "%eax";
end
3'b001: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%cl";
else if (data_size == `DATA_SIZE_16)
get_reg = "%cx";
else
get_reg = "%ecx";
end
3'b010: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%dl";
else if (data_size == `DATA_SIZE_16)
get_reg = "%dx";
else
get_reg = "%edx";
end
3'b011: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%bl";
else if (data_size == `DATA_SIZE_16)
get_reg = "%bx";
else
get_reg = "%ebx";
end
3'b100: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%ah";
else if (data_size == `DATA_SIZE_16)
get_reg = "%sp";
else
get_reg = "%esp";
end
3'b101: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%ch";
else if (data_size == `DATA_SIZE_16)
get_reg = "%bp";
else
get_reg = "%ebp";
end
3'b110: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%dh";
else if (data_size == `DATA_SIZE_16)
get_reg = "%si";
else
get_reg = "%esi";
end
3'b111: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%bh";
else if (data_size == `DATA_SIZE_16)
get_reg = "%di";
else
get_reg = "%edi";
end
endcase
endfunction
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: t_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.2 Build 209 09/17/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module t_ram (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q);
input aclr;
input clock;
input [26:0] data;
input [14:0] rdaddress;
input rden;
input [14:0] wraddress;
input wren;
output [26:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [26:0] sub_wire0;
wire [26:0] q = sub_wire0[26:0];
altsyncram altsyncram_component (
.aclr0 (aclr),
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.rden_b (rden),
.wren_a (wren),
.q_b (sub_wire0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({27{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "CLEAR0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
/*
`ifdef MODEL_TECH
altsyncram_component.init_file = "../sim/t_ram_test.hex",
`endif //MODEL_TECH
*/
altsyncram_component.intended_device_family = "Arria V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 20480,
altsyncram_component.numwords_b = 20480,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "CLEAR0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 15,
altsyncram_component.widthad_b = 15,
altsyncram_component.width_a = 27,
altsyncram_component.width_b = 27,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "1"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "552960"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "27"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "27"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "27"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "27"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "CLEAR0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "20480"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "20480"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "27"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "27"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 27 0 INPUT NODEFVAL "data[26..0]"
// Retrieval info: USED_PORT: q 0 0 27 0 OUTPUT NODEFVAL "q[26..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 15 0 INPUT NODEFVAL "rdaddress[14..0]"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: USED_PORT: wraddress 0 0 15 0 INPUT NODEFVAL "wraddress[14..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @address_a 0 0 15 0 wraddress 0 0 15 0
// Retrieval info: CONNECT: @address_b 0 0 15 0 rdaddress 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 27 0 data 0 0 27 0
// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 27 0 @q_b 0 0 27 0
// Retrieval info: GEN_FILE: TYPE_NORMAL t_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL t_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL t_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL t_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL t_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL t_ram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1 ns / 1 ps
module axi_slave_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 11
)
(
// Users to add ports here
// Passthrough signals
output wire S_AXI_ACLK,
output wire S_AXI_ARESETN,
output wire [C_S00_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
output wire [2 : 0] S_AXI_AWPROT,
output wire S_AXI_AWVALID,
input wire S_AXI_AWREADY,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
output wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
output wire S_AXI_WVALID,
input wire S_AXI_WREADY,
input wire [1 : 0] S_AXI_BRESP,
input wire S_AXI_BVALID,
output wire S_AXI_BREADY,
output wire [C_S00_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
output wire [2 : 0] S_AXI_ARPROT,
output wire S_AXI_ARVALID,
input wire S_AXI_ARREADY,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
input wire [1 : 0] S_AXI_RRESP,
input wire S_AXI_RVALID,
output wire S_AXI_RREADY,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Add user logic here
assign S_AXI_ACLK = s00_axi_aclk;
assign S_AXI_ARESETN = s00_axi_aresetn;
assign S_AXI_AWADDR = s00_axi_awaddr;
assign S_AXI_AWPROT = s00_axi_awprot;
assign S_AXI_AWVALID = s00_axi_awvalid;
assign s00_axi_awready = S_AXI_AWREADY;
assign S_AXI_WDATA = s00_axi_wdata;
assign S_AXI_WSTRB = s00_axi_wstrb;
assign S_AXI_WVALID = s00_axi_wvalid;
assign s00_axi_wready = S_AXI_WREADY;
assign s00_axi_bresp = S_AXI_BRESP;
assign s00_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s00_axi_bready;
assign S_AXI_ARADDR = s00_axi_araddr;
assign S_AXI_ARPROT = s00_axi_arprot;
assign S_AXI_ARVALID = s00_axi_arvalid;
assign s00_axi_arready = S_AXI_ARREADY;
assign s00_axi_rdata = S_AXI_RDATA;
assign s00_axi_rresp = S_AXI_RRESP;
assign s00_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s00_axi_rready;
// User logic ends
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_2_V
`define SKY130_FD_SC_MS__NAND4B_2_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4b_2 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4b_2 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_2_V
|
/*
* SBN machine with hardwired FSM control
* (c) Volker Strumpen
*
* modified to halt execution
* if result address is C all fff's
* i.e. ff for fwidth=8
* by Martin Polak
*/
module sbn (clk, state, PC, a, b);
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
input clk;
output [2:0] state;
output [fwidth-1:0] PC;
output [dwidth-1:0] a, b;
parameter iwidth = 4 * fwidth;
reg [iwidth-1:0] imem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] dmem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] X, Y;
reg [fwidth-1:0] PC;
reg [iwidth-1:0] IR;
wire [iwidth-1:0] insn;
wire [dwidth-1:0] data, asubb;
wire [fwidth-1:0] addr, PCp1, A, B, C, D;
wire altb, stp;
reg [1:0] da;
reg [2:0] state, nextstate;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;
parameter S6 = 3'b111;
// datapath
assign insn = imem[PC];
assign data = dmem[addr];
assign a = X; // for monitoring
assign b = Y; // for monitoring
assign asubb = X - Y;
assign altb = asubb[dwidth-1];
assign PCp1 = PC + 1;
assign A = IR[(4*fwidth-1):(3*fwidth)];
assign B = IR[(3*fwidth-1):(2*fwidth)];
assign C = IR[(2*fwidth-1):fwidth];
assign D = IR[fwidth-1:0];
assign stp = (C == ~{fwidth{1'b0}}) ? 1 : 0;
assign addr = (da == 2'b00) ? A : ((da == 2'b01) ? B : C);
always @ (posedge clk)
case (state) // action at end of state cycle
S0: begin
IR <= insn;
da <= 2'b00;
end
S1: begin
X <= data;
da <= 2'b01;
end
S2: begin
Y <= data;
da <= 2'b10;
end
S3: begin
dmem[addr] <= asubb;
$display("mw:DMEM,%h,%h", addr, asubb);
end
S4: PC <= D;
S5: PC <= PCp1;
S6: begin
// $display("program caused halt with value %d\n",asubb);
$finish;
end
endcase
// state register
always @ (posedge clk)
state <= nextstate;
// next state logic
always @ (state or altb or stp)
case (state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: if (stp ) nextstate = S6;
else nextstate = S3;
S3: if (altb) nextstate = S4;
else nextstate = S5;
default: nextstate = S0;
endcase
initial begin
$readmemh(%PROG%, imem);
$readmemh(%DATA%, dmem);
PC = 0;
state = 0;
$monitor("%d:%b:%h,%h,%h,%h,%h,%h,%h,%h,%h,%h,%h,%h",
$time, clk, PC, X, Y, A, B, C, D, insn, addr, asubb, PCp1, PC);
end // initial begin
endmodule
module top;
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
parameter maximum = %MAX_STEPS%;
parameter maxmone = maximum - 1;
parameter step = 10;
reg clk;
wire [2:0] state;
wire [fwidth-1:0] pc;
wire [dwidth-1:0] a, b;
sbn #(fwidth,dwidth) mach1 (clk, state, pc, a, b);
initial begin
$display("=== start ===");
clk = 0;
#maxmone $display("=== end ===");
#1 $finish;
end
always
#step clk = ~clk;
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: uart_fifo_64x128.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module uart_fifo_64x128 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] q = sub_wire0[7:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 8,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
(** * PE: Partial Evaluation *)
(* Chapter written and maintained by Chung-chieh Shan *)
(** The [Equiv] chapter introduced constant folding as an example of a
program transformation and proved that it preserves the meaning of
programs. Constant folding operates on manifest constants such as
[ANum] expressions. For example, it simplifies the command [Y ::=
APlus (ANum 3) (ANum 1)] to the command [Y ::= ANum 4]. However,
it does not propagate known constants along data flow. For
example, it does not simplify the sequence
X ::= ANum 3;; Y ::= APlus (AId X) (ANum 1)
to
X ::= ANum 3;; Y ::= ANum 4
because it forgets that [X] is [3] by the time it gets to [Y].
We might naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is like
running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
X ::= ANum 3;; Y ::= AMinus (APlus (AId X) (ANum 1)) (AId Y)
to
X ::= ANum 3;; Y ::= AMinus (ANum 4) (AId Y)
without knowing the initial value of [Y]. *)
Require Import Coq.Bool.Bool.
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import Coq.omega.Omega.
Require Import Coq.Logic.FunctionalExtensionality.
Require Import Coq.Lists.List.
Import ListNotations.
Require Import SfLib.
Require Import Maps.
Require Import Imp.
(* ################################################################# *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(* ================================================================= *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [id -> option nat] (as opposed to the type [id -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [id * nat]
pairs. *)
Definition pe_state := list (id * nat).
(** The idea is that a variable [id] appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
[id] appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:id) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if beq_id V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every [id] to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some [id], then that [pe_state] must map that [id] to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [id] equality. The tactic
compare V V'
means to reason by cases over [beq_id V V'].
In the case where [V = V'], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) :=
let H := fresh "Heq" i j in
destruct (beq_idP i j);
[ subst j | ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
In V (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
- (* [] *) inversion H.
- (* :: *) simpl in H. simpl. compare V V'; auto. Qed.
(** In what follows, we will make heavy use of the [In] property from
the standard library, also defined in [Logic.v]: *)
Print In.
(* ===> Fixpoint In {A:Type} (a: A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end
: forall A : Type, A -> list A -> Prop *)
(** Besides the various lemmas about [In] that we've already come
across, the following one (taken from the standard library) will
also be useful: *)
Check filter_In.
(* ===> filter_In : forall (A : Type) (f : A -> bool) (x : A) (l : list A),
In x (filter f l) <-> In x l /\ f x = true *)
(** If a type [A] has an operator [beq] for testing equality of its
elements, we can compute a boolean [inb beq a l] for testing
whether [In a l] holds or not. *)
Fixpoint inb {A : Type} (beq : A -> A -> bool) (a : A) (l : list A) :=
match l with
| [] => false
| a'::l' => beq a a' || inb beq a l'
end.
(** It is easy to relate [inb] to [In] with the [reflect] property: *)
Lemma inbP : forall A : Type, forall beq : A->A->bool,
(forall a1 a2, reflect (a1 = a2) (beq a1 a2)) ->
forall a l, reflect (In a l) (inb beq a l).
Proof.
intros A beq beqP a l.
induction l as [|a' l' IH].
- constructor. intros [].
- simpl. destruct (beqP a a').
+ subst. constructor. left. reflexivity.
+ simpl. destruct IH; constructor.
* right. trivial.
* intros [H1 | H2]; congruence.
Qed.
(* ================================================================= *)
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| APlus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (ANum 4) (AId Y).
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (APlus (AId X) (ANum 1)) (ANum 3).
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
induction a; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
- (* AId *)
remember (pe_lookup pe_st i) as l. destruct l.
+ (* Some *) rewrite H with (n:=n) by apply Heql. reflexivity.
+ (* None *) reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to just
Y ::= AMinus (ANum 3) (AId Y);; X ::= ANum 4
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
pe_aexp [(X,3)] (AMinus (AId X) (AId Y))
to be equal to [AMinus (ANum 3) (AId Y)] and _not_ the original
expression [AMinus (AId X) (AId Y)]. After all, it would be
incorrect, not just inefficient, to transform
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to
Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
even though the output expressions [AMinus (ANum 3) (AId Y)] and
[AMinus (AId X) (AId Y)] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct'] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_update (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => t_update (pe_update st pe_st) V n
end.
Example test_pe_update:
pe_update (t_update empty_state Y 1) [(X,3);(Z,2)]
= t_update (t_update (t_update empty_state Y 1) Z 2) X 3.
Proof. reflexivity. Qed.
(** Although [pe_update] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_update_correct: forall st pe_st V0,
pe_update st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold t_update.
compare V0 V; auto. rewrite <- beq_id_refl; auto. rewrite false_beq_id; auto. Qed.
(** We can relate [pe_consistent] to [pe_update] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_update_consistent: forall st pe_st,
pe_consistent (pe_update st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_update_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_update: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_update st pe_st V.
Proof. intros st pe_st H V. rewrite pe_update_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_update st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
induction a; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_update_correct. destruct (pe_lookup pe_st i); reflexivity.
Qed.
(* ================================================================= *)
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if leb n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (pe_bexp pe_st b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] (BNot (BLe (AId X) (ANum 3)))
= BFalse.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b,
b = BNot (BLe (AId X) (APlus (AId X) (ANum 1))) ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_update st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
induction b; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a) as a';
remember (pe_aexp pe_st a0) as a0';
assert (Ha: aeval (pe_update st pe_st) a = aeval st a');
assert (Ha0: aeval (pe_update st pe_st) a0 = aeval st a0');
try (subst; apply pe_aexp_correct);
destruct a'; destruct a0'; rewrite Ha; rewrite Ha0;
simpl; try destruct (beq_nat n n0);
try destruct (leb n n0); reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ################################################################# *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
c1 / st \\ c1' / st'
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] \\ (Y ::= AMult (AId Z) (ANum 6)) / [(X,3)]
to hold. The assignment to [X] appears in the final partial state,
not the residual command. *)
(* ================================================================= *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X ::= ANum 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [SKIP].) The second assignment [Y ::= AMult (AId Z)
(APlus (AId X) (AId X))] is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_update] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:id) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if beq_id V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if beq_id V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
- (* [] *) destruct (beq_id V V0); reflexivity.
- (* :: *) simpl. compare V V'.
+ (* equal *) rewrite IHpe_st.
destruct (beq_idP V V0). reflexivity.
rewrite false_beq_id; auto.
+ (* not equal *) simpl. compare V0 V'.
* (* equal *) rewrite false_beq_id; auto.
* (* not equal *) rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:id) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if beq_id V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl.
compare V V0.
- (* equal *) rewrite <- beq_id_refl; auto.
- (* not equal *) rewrite pe_remove_correct.
repeat rewrite false_beq_id; auto.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_update_update_remove: forall st pe_st V n,
t_update (pe_update st pe_st) V n =
pe_update (t_update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality.
intros V0. unfold t_update. rewrite !pe_update_correct.
rewrite pe_remove_correct. destruct (beq_id V V0); reflexivity.
Qed.
Theorem pe_update_update_add: forall st pe_st V n,
t_update (pe_update st pe_st) V n =
pe_update st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold t_update. rewrite !pe_update_correct. rewrite pe_add_correct.
destruct (beq_id V V0); reflexivity. Qed.
(* ================================================================= *)
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [IFB b1 THEN c1 ELSE c2 FI]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [THEN] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [ELSE] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y ::= ANum 4] to the end of the [THEN] branch. So,
the residual program will be something like
SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
SKIP;;
SKIP;;
Y ::= ANum 4
ELSE SKIP FI
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:id) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (beq_nat x y)
| None, None => false
| _, _ => true
end.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:id),
true = pe_disagree_at pe_st1 pe_st2 V ->
In V (map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
apply in_app_iff.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list id) : list id :=
match l with
| [] => []
| x::l =>
x :: filter (fun y => if beq_id x y then false else true) (pe_unique l)
end.
Theorem pe_unique_correct: forall l x,
In x l <-> In x (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. split.
- (* -> *)
intros. inversion H; clear H.
left. assumption.
destruct (beq_idP h x).
left. assumption.
right. apply filter_In. split.
apply IHt. assumption.
rewrite false_beq_id; auto.
- (* <- *)
intros. inversion H; clear H.
left. assumption.
apply filter_In in H0. inversion H0. right. apply IHt. assumption.
Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list id :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
~ In V (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct. rewrite filter_In.
split; intros Heq.
- (* -> *)
intro. destruct H. unfold pe_disagree_at in H0. rewrite Heq in H0.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl in H0. inversion H0.
inversion H0.
- (* <- *)
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
{ (* Proof of assertion *)
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
apply pe_disagree_domain in Heqdisagree.
exfalso. apply Heq. split. assumption. reflexivity. }
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve by inversion.
rewrite negb_false_iff in Hagree.
apply beq_nat_true in Hagree. subst. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_update] only depends on the
[pe_lookup] interpretation of partial states, [pe_update] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_update] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list id) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if inb beq_id V ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
compare V' V.
- rewrite <- beq_id_refl. reflexivity.
- rewrite false_beq_id; try congruence. reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof.
intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
destruct (inbP _ _ beq_idP V (pe_compare pe_st1 pe_st2)).
- reflexivity.
- apply pe_compare_correct. auto. Qed.
Theorem pe_compare_update: forall pe_st1 pe_st2 st,
pe_update st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_update st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_update_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list id) : com :=
match ids with
| [] => SKIP
| V::ids => match pe_lookup pe_st V with
| Some n => (assign pe_st ids;; V ::= ANum n)
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list id) (st:state) : state :=
fun V => if inb beq_id V ids then
match pe_lookup pe_st V with
| Some n => n
| None => st V
end
else st V.
Theorem assign_removes: forall pe_st ids st,
pe_update st pe_st =
pe_update (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_update_correct. rewrite pe_removes_correct. unfold assigned.
destruct (inbP _ _ beq_idP V ids); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
c / st \\ st1 -> (forall V, st1 V = st2 V) -> c / st \\ st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
assign pe_st ids / st \\ assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
- (* [] *) eapply ceval_extensionality. apply E_Skip. reflexivity.
- (* V::ids *)
remember (pe_lookup pe_st V) as lookup. destruct lookup.
+ (* Some *) eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold t_update. compare V V0.
* (* equal *) rewrite <- Heqlookup. rewrite <- beq_id_refl. reflexivity.
* (* not equal *) rewrite false_beq_id; simpl; congruence.
+ (* None *) eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V V0.
* (* equal *) rewrite <- Heqlookup.
rewrite <- beq_id_refl.
destruct (inbP _ _ beq_idP V ids); reflexivity.
* (* not equal *) rewrite false_beq_id; simpl; congruence.
Qed.
(* ================================================================= *)
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '\\' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st \\ SKIP / pe_st
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st \\ SKIP / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st \\ (l ::= a1') / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st \\ c1' / pe_st' ->
c2 / pe_st' \\ c2' / pe_st'' ->
(c1 ;; c2) / pe_st \\ (c1' ;; c2') / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st \\ c2' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st \\ c1' / pe_st1 ->
c2 / pe_st \\ c2' / pe_st2 ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
\\ (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '\\' c1' '/' st'" := (pe_com c1 st c1' st').
Hint Constructors pe_com.
Hint Constructors ceval.
(* ================================================================= *)
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] \\ (SKIP;; Y ::= AMult (AId Z) (ANum 6)) / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
(X ::= ANum 3 ;; IFB BLe (AId X) (ANum 4) THEN X ::= ANum 4 ELSE SKIP FI)
/ [] \\ (SKIP;; SKIP) / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
(X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI) / []
\\ (SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
(SKIP;; SKIP);; (SKIP;; Y ::= ANum 4)
ELSE SKIP;; SKIP FI)
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve by inversion.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(* ================================================================= *)
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '\\' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
c' / st \\ st' ->
pe_update st' pe_st' = st'' ->
c' / pe_st' / st \\ st''
where "c' '/' pe_st' '/' st '\\' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval.
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' ->
forall st st'',
(c / pe_update st pe_st \\ st'') ->
(c' / pe_st' / st \\ st'').
Proof. intros c pe_st pe_st' c' Hpe.
induction Hpe; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
- (* PE_AssStatic *) econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_add.
rewrite -> H. reflexivity.
- (* PE_AssDynamic *) econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_remove.
reflexivity.
- (* PE_Seq *)
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
- (* PE_If *) inversion Heval; subst.
+ (* E'IfTrue *) edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
+ (* E_IfFalse *) edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_update.
rewrite <- assign_removes. eassumption.
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' ->
forall st st'',
(c' / pe_st' / st \\ st'') ->
(c / pe_update st pe_st \\ st'').
Proof. intros c pe_st pe_st' c' Hpe.
induction Hpe;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
- (* PE_AssStatic *) rewrite <- pe_update_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
- (* PE_AssDynamic *) rewrite <- pe_update_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
- (* PE_Seq *) eapply E_Seq; eauto.
- (* PE_IfTrue *) apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
- (* PE_IfFalse *) apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
- (* PE_If *)
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
+ (* E_IfTrue *)
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
+ (* E_IfFalse *)
rewrite -> pe_compare_update.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' ->
forall st st'',
(c / pe_update st pe_st \\ st'') <->
(c' / pe_st' / st \\ st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
- (* -> *) apply pe_com_complete. apply H.
- (* <- *) apply pe_com_sound. apply H.
Qed.
(* ################################################################# *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be, for example,
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y)
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking whether [Y] is even or odd:
X ::= ANum 0;;
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
X ::= AMinus (ANum 1) (AId X)
END
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
IF BLe (ANum 1) (AId Y) THEN
Y ::= AMinus (AId Y) (ANum 1)
ELSE
X ::= ANum 1;; EXIT
FI
END;;
X ::= ANum 0
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '\\' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st \\ SKIP / pe_st / SKIP
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st \\ SKIP / pe_add pe_st l n1 / SKIP
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st \\ (l ::= a1') / pe_remove pe_st l / SKIP
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st \\ c1' / pe_st' / SKIP ->
c2 / pe_st' \\ c2' / pe_st'' / c'' ->
(c1 ;; c2) / pe_st \\ (c1' ;; c2') / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st \\ c2' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st \\ c1' / pe_st1 / c'' ->
c2 / pe_st \\ c2' / pe_st2 / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
\\ (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
(WHILE b1 DO c1 END) / pe_st \\ SKIP / pe_st / SKIP
| PE_WhileLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' \\ c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(WHILE b1 DO c1 END) / pe_st \\ (c1';;c2') / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' \\ c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = SKIP \/ c2'' = WHILE b1 DO c1 END) ->
(WHILE b1 DO c1 END) / pe_st
\\ (IFB pe_bexp pe_st b1
THEN c1';; c2';; assign pe_st'' (pe_compare pe_st pe_st'')
ELSE assign pe_st (pe_compare pe_st pe_st'') FI)
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> BFalse ->
(WHILE b1 DO c1 END) / pe_st \\ SKIP / pe_st / (WHILE b1 DO c1 END)
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
\\ c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
\\ (WHILE BTrue DO SKIP END) / pe_st / SKIP
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(WHILE b1 DO c1 END) / pe_st
\\ SKIP / pe_st / (WHILE BTrue DO SKIP END) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
\\ c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
\\ (WHILE pe_bexp pe_st b1 DO c1';; c2' END) / pe_st / SKIP
where "c1 '/' st '\\' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Hint Constructors pe_com.
(* ================================================================= *)
(** ** Examples *)
Ltac step i :=
(eapply i; intuition eauto; try solve by inversion);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve by inversion ])).
Definition square_loop: com :=
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END.
Example pe_loop_example1:
square_loop / []
\\ (WHILE BLe (ANum 1) (AId X) DO
(Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1));; SKIP
END) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
(X ::= ANum 3;; square_loop) / []
\\ (SKIP;;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
SKIP) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileEnd.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
(Z ::= ANum 3;; subtract_slowly) / []
\\ (SKIP;;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
WHILE BNot (BEq (AId X) (ANum 0)) DO
(SKIP;; X ::= AMinus (AId X) (ANum 1));; SKIP
END;;
SKIP;; Z ::= ANum 0
ELSE SKIP;; Z ::= ANum 1 FI;; SKIP
ELSE SKIP;; Z ::= ANum 2 FI;; SKIP
ELSE SKIP;; Z ::= ANum 3 FI) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
(X ::= ANum 0;;
WHILE BLe (AId X) (ANum 2) DO
X ::= AMinus (ANum 1) (AId X)
END) / [] \\ (SKIP;; WHILE BTrue DO SKIP END) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileLoop.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(* ================================================================= *)
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '\\' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
SKIP / st \\ st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st \\ (t_update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st \\ st' # n1 ->
c2 / st' \\ st'' # n2 ->
(c1 ;; c2) / st \\ st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st \\ st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st \\ st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st \\ st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st \\ st' # n
| E'WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st \\ st # 0
| E'WhileLoop : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st \\ st' # n1 ->
(WHILE b1 DO c1 END) / st' \\ st'' # n2 ->
(WHILE b1 DO c1 END) / st \\ st'' # S (n1 + n2)
where "c1 '/' st '\\' st' # n" := (ceval_count c1 st st' n).
Hint Constructors ceval_count.
Theorem ceval_count_complete: forall c st st',
c / st \\ st' -> exists n, c / st \\ st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st \\ st' # n -> c / st \\ st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. intro. inversion H0. Qed.
Theorem pe_compare_nil_update: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_update st pe_st1 = pe_update st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_update_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '\\' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
c' / st \\ st' ->
c'' / pe_update st' pe_st' \\ st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st \\ st'' # n
where "c' '/' pe_st' '/' c'' '/' st '\\' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st \\ st'' # n' ->
c' / pe_st' / c'' / st \\ st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. omega. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st \\ c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_update st pe_st \\ st'' # n) ->
(c' / pe_st' / c'' / st \\ st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
induction Hpe; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
- (* PE_AssStatic *) econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_add.
rewrite -> H. apply E'Skip. auto.
- (* PE_AssDynamic *) econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_remove.
apply E'Skip. auto.
- (* PE_Seq *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
- (* PE_If *) inversion Heval; subst.
+ (* E'IfTrue *) edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
+ (* E_IfFalse *) edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_update.
rewrite <- assign_removes. eassumption. eassumption.
- (* PE_WhileLoop *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
- (* PE_While *) inversion Heval; subst.
+ (* E_WhileEnd *) econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
+ (* E_WhileLoop *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_update, <- assign_removes. eassumption.
omega.
- (* PE_WhileFixedLoop *) exfalso.
generalize dependent (S (n1 + n2)). intros n.
clear - H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
+ (* E'WhileEnd *) rewrite pe_bexp_correct, H in H7. inversion H7.
+ (* E'WhileLoop *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_update _ _ H0) in H7.
apply H1 in H7; [| omega]. inversion H7.
- (* PE_WhileFixed *) generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
+ (* E'WhileEnd *) rewrite pe_bexp_correct in H8. eauto.
+ (* E'WhileLoop *) rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_update _ _ H1) in H8.
apply H2 in H8; [| omega]. inversion H8.
econstructor; [ eapply E_WhileLoop; eauto | eassumption | omega].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st \\ c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st \\ st'' # n) ->
(c / pe_update st pe_st \\ st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
induction Hpe;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
- (* PE_AssStatic *) rewrite <- pe_update_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
- (* PE_AssDynamic *) rewrite <- pe_update_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
- (* PE_Seq *) eapply E_Seq; eauto.
- (* PE_IfTrue *) apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
- (* PE_IfFalse *) apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
- (* PE_If *) inversion Heval; subst; inversion H7; subst; clear H7.
+ (* E_IfTrue *)
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
+ (* E_IfFalse *)
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_update in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
- (* PE_WhileEnd *) apply E_WhileEnd.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
- (* PE_WhileLoop *) eapply E_WhileLoop.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
- (* PE_While *) inversion Heval; subst.
+ (* E_IfTrue *)
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_update in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileLoop. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
+ (* E_IfFalse *) apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
* (* c2'' = SKIP *) inversion Heval'. subst. apply E_WhileEnd.
rewrite -> pe_bexp_correct. assumption.
* (* c2'' = WHILE b1 DO c1 END *) assumption.
- (* PE_WhileFixedEnd *) eapply ceval_count_sound. apply Heval'.
- (* PE_WhileFixedLoop *)
apply loop_never_stops in Heval. inversion Heval.
- (* PE_WhileFixed *)
clear - H1 IHHpe1 IHHpe2 Heval.
remember (WHILE pe_bexp pe_st b1 DO c1';; c2' END) as c'.
induction Heval;
inversion Heqc'; subst; clear Heqc'.
+ (* E_WhileEnd *) apply E_WhileEnd.
rewrite pe_bexp_correct. assumption.
+ (* E_WhileLoop *)
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileLoop. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_update _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' / SKIP ->
forall st st'',
(c / pe_update st pe_st \\ st'') <->
(exists st', c' / st \\ st' /\ pe_update st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
- (* -> *) intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
- (* <- *) intros [st' [Heval Heq]]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ################################################################# *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [WHILE] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [WHILE] loops, but
that is not possible in general; we do not pursue it here. *)
(* ================================================================= *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : id -> aexp -> block Label -> block Label.
Arguments Goto {Label} _.
Arguments If {Label} _ _ _.
Arguments Assign {Label} _ _ _.
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y (AMinus (AId Y) (ANum 1))
(Assign X (AMinus (ANum 1) (AId X))
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (t_update st i (aeval st a)) k
end.
Example keval_example:
keval empty_state parity_body
= (t_update (t_update empty_state Y 0) X 1, loop).
Proof. reflexivity. Qed.
(* ================================================================= *)
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X (ANum 0) (Goto loop))
| loop => Some (If (BLe (ANum 1) (AId Y)) body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_state entry empty_state done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite t_update_same; auto.
Qed.
(* ================================================================= *)
(** ** Partial Evaluation of Basic Blocks and Flowchart Programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y (AMinus (AId Y) (ANum 1)) (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_update st pe_st) k = (pe_update st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
induction k as [l | b l1 l2 | i a k];
intros st pe_st H.
- (* Goto *) inversion H; reflexivity.
- (* If *)
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
- (* Assign *)
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_update_update_add; apply IHk; apply H];
solve [rewrite pe_update_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_update st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_update st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split.
- (* -> *) intros Heval.
remember (pe_update st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ];
intros st pe_st Heqsto; subst sto.
+ (* E_None *) eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
+ (* E_Some *)
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_]].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
- (* <- *) intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ];
intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
+ (* E_None *) apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
+ (* E_Some *)
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
(** $Date: 2016-05-26 16:17:19 -0400 (Thu, 26 May 2016) $ *)
|
module BRAMFIFO
#(
parameter p1width = 32,
parameter p2depth = 1024,
parameter p3cntr_width = 10
)
(
input CLK,
input RST_N,
input [p1width-1:0] D_IN,
output [p1width-1:0] D_OUT,
input ENQ,
input DEQ,
output EMPTY_N,
output FULL_N,
output [p3cntr_width-1:0] COUNT,
input CLR
);
reg [p3cntr_width-1:0] wptr, wptr_d, wptr_p1; // reg
reg [p3cntr_width-1:0] rptr, rptr_d, rptr_p1; // reg
reg [p3cntr_width-1:0] dcount, dcount_d; // reg
(* ram_style = "block" *) reg [p1width-1:0] mem [p2depth-1:0];
reg [p1width-1:0] mem_d; // comb
reg [p1width-1:0] dout_r; // register
reg inhibit, inhibit_d;
reg mem_wen; // comb
reg nempty, nempty_d;
reg nfull, nfull_d;
always@(posedge CLK) begin
if(RST_N && !CLR) begin
wptr <= wptr_d;
rptr <= rptr_d;
nfull <= nfull_d;
nempty <= nempty_d;
inhibit <= inhibit_d;
dcount <= dcount_d;
if(mem_wen) mem[wptr] <= D_IN;
end
else begin
rptr <= {p3cntr_width{1'b0}};
wptr <= {p3cntr_width{1'b0}};
nfull <= 1'b1;
nempty <= 1'b0;
inhibit <= 1'b0;
dcount <= {p3cntr_width{1'b0}};
end
end
always@(*) begin
wptr_d = wptr;
rptr_d = rptr;
nfull_d = nfull;
nempty_d = nempty;
mem_wen = 1'b0;
inhibit_d = 1'b0;
wptr_p1 = (wptr + 1) % p2depth;
rptr_p1 = (rptr + 1) % p2depth;
dcount_d = dcount;
if(ENQ) begin
wptr_d = wptr_p1;
mem_wen = 1'b1;
end
if(DEQ) begin
rptr_d = rptr_p1;
end
if(ENQ && DEQ) begin
nfull_d = nfull;
nempty_d = nempty;
if(wptr == rptr) inhibit_d = 1'b1;
end
else if(DEQ && !ENQ) begin
nfull_d = 1'b1;
nempty_d = rptr_p1 != wptr;
dcount_d = dcount-1;
end
else if(ENQ && !DEQ) begin
nfull_d = wptr_p1 != rptr;
nempty_d = 1'b1;
dcount_d = dcount+1;
end
end
assign D_OUT = mem[rptr];
assign EMPTY_N = nempty && !inhibit;
assign FULL_N = nfull;
assign COUNT = dcount;
//synopsys translate off
always@(negedge CLK) begin
if(RST_N) begin
if(ENQ && !FULL_N) begin
$display("ERROR, enqueuing to full BRAMFIFO");
$finish(0);
end
if(DEQ && !EMPTY_N) begin
$display("ERROR, dequeuing to empty BRAMFIFO");
$finish(0);
end
end
end
//synopsys translate on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBP_TB_V
`define SKY130_FD_SC_HD__DFBBP_TB_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfbbp.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SET_B = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 RESET_B = 1'b1;
#200 SET_B = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 RESET_B = 1'b0;
#340 SET_B = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SET_B = 1'b1;
#540 RESET_B = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SET_B = 1'bx;
#680 RESET_B = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__dfbbp dut (.D(D), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DLYGATE4SD3_BEHAVIORAL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD3_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_2_V
`define SKY130_FD_SC_LS__FILL_DIODE_2_V
/**
* fill_diode: Fill diode.
*
* Verilog wrapper for fill_diode with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fill_diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_diode_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fill_diode base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_diode_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fill_diode base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_2_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:29:41 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_rst_ps7_0_100M_1/zynq_design_1_rst_ps7_0_100M_1_stub.v
// Design : zynq_design_1_rst_ps7_0_100M_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2017.2" *)
module zynq_design_1_rst_ps7_0_100M_1(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Build 163 10/28/2008 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
c2,
locked);
input inclk0;
output c0;
output c2;
output locked;
wire [5:0] sub_wire0;
wire sub_wire3;
wire [0:0] sub_wire6 = 1'h0;
wire [2:2] sub_wire2 = sub_wire0[2:2];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c2 = sub_wire2;
wire locked = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk2_divide_by = 10,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 13,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.gate_lock_signal = "NO",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.valid_lock_multiplier = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "65.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "10"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "13"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_wave*.jpg FALSE FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*
* ECP5 PicoRV32 demo
*
* Copyright (C) 2017 Clifford Wolf <[email protected]>
* Copyright (C) 2018 David Shah <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`ifdef PICORV32_V
`error "attosoc.v must be read before picorv32.v!"
`endif
`define PICORV32_REGS picosoc_regs
module attosoc (
input clk,
input reset,
output reg [7:0] led
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
if (reset)
reset_cnt <= 0;
else
reset_cnt <= reset_cnt + !resetn;
end
parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // ROM at 0x0
parameter integer ROM_WORDS = 64;
reg [31:0] rom [0:ROM_WORDS-1];
wire [31:0] rom_rdata = rom[mem_addr[31:2]];
initial $readmemh("firmware.hex", rom);
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
wire rom_ready = mem_valid && mem_addr[31:24] == 8'h00;
wire iomem_valid;
wire iomem_ready;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_rdata;
assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
assign iomem_ready = 1'b1;
assign iomem_wstrb = mem_wstrb;
assign iomem_addr = mem_addr;
assign iomem_wdata = mem_wdata;
wire [31:0] spimemio_cfgreg_do;
always @(posedge clk)
if (iomem_valid && iomem_wstrb[0])
led <= iomem_wdata[7:0];
assign mem_ready = (iomem_valid && iomem_ready) || rom_ready;
assign mem_rdata = rom_rdata;
picorv32 #(
.STACKADDR(STACKADDR),
.PROGADDR_RESET(PROGADDR_RESET),
.PROGADDR_IRQ(32'h 0000_0000),
.BARREL_SHIFTER(0),
.COMPRESSED_ISA(0),
.ENABLE_MUL(0),
.ENABLE_DIV(0),
.ENABLE_IRQ(0),
.ENABLE_IRQ_QREGS(0),
.ENABLE_COUNTERS(0),
.TWO_STAGE_SHIFT(0),
.ENABLE_REGS_16_31(0)
) cpu (
.clk (clk ),
.resetn (resetn ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
endmodule
// Implementation note:
// Replace the following two modules with wrappers for your SRAM cells.
module picosoc_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] regs [0:31];
always @(posedge clk)
if (wen) regs[waddr[4:0]] <= wdata;
assign rdata1 = regs[raddr1[4:0]];
assign rdata2 = regs[raddr2[4:0]];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3_SYMBOL_V
`define SKY130_FD_SC_HS__OR3_SYMBOL_V
/**
* or3: 3-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3_SYMBOL_V
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream Ethernet FCS checker (64 bit datapath)
*/
module axis_eth_fcs_check_64
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [63:0] s_axis_tdata,
input wire [7:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tuser,
/*
* AXI output
*/
output wire [63:0] m_axis_tdata,
output wire [7:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire m_axis_tuser,
/*
* Status
*/
output wire busy,
output wire error_bad_fcs
);
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PAYLOAD = 2'd1,
STATE_LAST = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg shift_in;
reg shift_reset;
reg [7:0] last_cycle_tkeep_reg = 8'd0, last_cycle_tkeep_next;
reg last_cycle_tuser_reg = 1'b0, last_cycle_tuser_next;
reg [63:0] s_axis_tdata_d0 = 64'd0;
reg [7:0] s_axis_tkeep_d0 = 8'd0;
reg s_axis_tvalid_d0 = 1'b0;
reg s_axis_tuser_d0 = 1'b0;
reg busy_reg = 1'b0;
reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [31:0] crc_state = 32'hFFFFFFFF;
reg [31:0] crc_state3 = 32'hFFFFFFFF;
wire [31:0] crc_next0;
wire [31:0] crc_next1;
wire [31:0] crc_next2;
wire [31:0] crc_next3;
wire [31:0] crc_next7;
wire crc_valid0 = crc_next0 == ~32'h2144df1c;
wire crc_valid1 = crc_next1 == ~32'h2144df1c;
wire crc_valid2 = crc_next2 == ~32'h2144df1c;
wire crc_valid3 = crc_next3 == ~32'h2144df1c;
// internal datapath
reg [63:0] m_axis_tdata_int;
reg [7:0] m_axis_tkeep_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
assign busy = busy_reg;
assign error_bad_fcs = error_bad_fcs_reg;
wire last_cycle = state_reg == STATE_LAST;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(last_cycle ? s_axis_tdata_d0[39:32] : s_axis_tdata[7:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next0)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(16),
.STYLE("AUTO")
)
eth_crc_16 (
.data_in(last_cycle ? s_axis_tdata_d0[47:32] : s_axis_tdata[15:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next1)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(24),
.STYLE("AUTO")
)
eth_crc_24 (
.data_in(last_cycle ? s_axis_tdata_d0[55:32] : s_axis_tdata[23:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next2)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_32 (
.data_in(last_cycle ? s_axis_tdata_d0[63:32] : s_axis_tdata[31:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next3)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(64),
.STYLE("AUTO")
)
eth_crc_64 (
.data_in(s_axis_tdata[63:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next7)
);
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
shift_in = 1'b0;
shift_reset = 1'b0;
last_cycle_tkeep_next = last_cycle_tkeep_reg;
last_cycle_tuser_next = last_cycle_tuser_reg;
s_axis_tready_next = 1'b0;
m_axis_tdata_int = 64'd0;
m_axis_tkeep_int = 8'd0;
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
error_bad_fcs_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
s_axis_tready_next = m_axis_tready_int_early;
reset_crc = 1'b1;
m_axis_tdata_int = s_axis_tdata_d0;
m_axis_tkeep_int = s_axis_tkeep_d0;
m_axis_tvalid_int = s_axis_tvalid_d0 && s_axis_tvalid;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
if (s_axis_tready && s_axis_tvalid) begin
shift_in = 1'b1;
reset_crc = 1'b0;
update_crc = 1'b1;
if (s_axis_tlast) begin
if (s_axis_tkeep[7:4] == 0) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = s_axis_tuser;
m_axis_tkeep_int = {s_axis_tkeep[3:0], 4'b1111};
if ((s_axis_tkeep[3:0] == 4'b0001 && crc_valid0) ||
(s_axis_tkeep[3:0] == 4'b0011 && crc_valid1) ||
(s_axis_tkeep[3:0] == 4'b0111 && crc_valid2) ||
(s_axis_tkeep[3:0] == 4'b1111 && crc_valid3)) begin
// CRC valid
end else begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
last_cycle_tkeep_next = {4'b0000, s_axis_tkeep[7:4]};
last_cycle_tuser_next = s_axis_tuser;
s_axis_tready_next = 1'b0;
state_next = STATE_LAST;
end
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// transfer payload
s_axis_tready_next = m_axis_tready_int_early;
m_axis_tdata_int = s_axis_tdata_d0;
m_axis_tkeep_int = s_axis_tkeep_d0;
m_axis_tvalid_int = s_axis_tvalid_d0 && s_axis_tvalid;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
if (s_axis_tready && s_axis_tvalid) begin
shift_in = 1'b1;
update_crc = 1'b1;
if (s_axis_tlast) begin
if (s_axis_tkeep[7:4] == 0) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = s_axis_tuser;
m_axis_tkeep_int = {s_axis_tkeep[3:0], 4'b1111};
if ((s_axis_tkeep[3:0] == 4'b0001 && crc_valid0) ||
(s_axis_tkeep[3:0] == 4'b0011 && crc_valid1) ||
(s_axis_tkeep[3:0] == 4'b0111 && crc_valid2) ||
(s_axis_tkeep[3:0] == 4'b1111 && crc_valid3)) begin
// CRC valid
end else begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
last_cycle_tkeep_next = {4'b0000, s_axis_tkeep[7:4]};
last_cycle_tuser_next = s_axis_tuser;
s_axis_tready_next = 1'b0;
state_next = STATE_LAST;
end
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
state_next = STATE_PAYLOAD;
end
end
STATE_LAST: begin
// last cycle
s_axis_tready_next = 1'b0;
m_axis_tdata_int = s_axis_tdata_d0;
m_axis_tkeep_int = last_cycle_tkeep_reg;
m_axis_tvalid_int = s_axis_tvalid_d0;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = last_cycle_tuser_reg;
if ((s_axis_tkeep_d0[7:4] == 4'b0001 && crc_valid0) ||
(s_axis_tkeep_d0[7:4] == 4'b0011 && crc_valid1) ||
(s_axis_tkeep_d0[7:4] == 4'b0111 && crc_valid2) ||
(s_axis_tkeep_d0[7:4] == 4'b1111 && crc_valid3)) begin
// CRC valid
end else begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
if (m_axis_tready_int_reg) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
state_next = STATE_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_axis_tready_reg <= 1'b0;
busy_reg <= 1'b0;
error_bad_fcs_reg <= 1'b0;
s_axis_tvalid_d0 <= 1'b0;
crc_state <= 32'hFFFFFFFF;
crc_state3 <= 32'hFFFFFFFF;
end else begin
state_reg <= state_next;
s_axis_tready_reg <= s_axis_tready_next;
busy_reg <= state_next != STATE_IDLE;
error_bad_fcs_reg <= error_bad_fcs_next;
// datapath
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
crc_state3 <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next7;
crc_state3 <= crc_next3;
end
if (shift_reset) begin
s_axis_tvalid_d0 <= 1'b0;
end else if (shift_in) begin
s_axis_tvalid_d0 <= s_axis_tvalid;
end
end
last_cycle_tkeep_reg <= last_cycle_tkeep_next;
last_cycle_tuser_reg <= last_cycle_tuser_next;
if (shift_in) begin
s_axis_tdata_d0 <= s_axis_tdata;
s_axis_tkeep_d0 <= s_axis_tkeep;
s_axis_tuser_d0 <= s_axis_tuser;
end
end
// output datapath logic
reg [63:0] m_axis_tdata_reg = 64'd0;
reg [7:0] m_axis_tkeep_reg = 8'd0;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg m_axis_tuser_reg = 1'b0;
reg [63:0] temp_m_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_axis_tkeep_reg = 8'd0;
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg temp_m_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = m_axis_tkeep_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = m_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFBBP_TB_V
`define SKY130_FD_SC_HDLL__SDFBBP_TB_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfbbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 SET_B = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 D = 1'b1;
#220 RESET_B = 1'b1;
#240 SCD = 1'b1;
#260 SCE = 1'b1;
#280 SET_B = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 D = 1'b0;
#400 RESET_B = 1'b0;
#420 SCD = 1'b0;
#440 SCE = 1'b0;
#460 SET_B = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 SET_B = 1'b1;
#660 SCE = 1'b1;
#680 SCD = 1'b1;
#700 RESET_B = 1'b1;
#720 D = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 SET_B = 1'bx;
#840 SCE = 1'bx;
#860 SCD = 1'bx;
#880 RESET_B = 1'bx;
#900 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hdll__sdfbbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFBBP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FA_BEHAVIORAL_V
`define SKY130_FD_SC_MS__FA_BEHAVIORAL_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT;
wire or2_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT, and1_out, and0_out);
buf buf0 (COUT , or1_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out);
buf buf1 (SUM , or2_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FA_BEHAVIORAL_V
|
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