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`include "macro.v"
`include "machine/cpu/control.v"
`include "machine/cpu/stages/pc-reg.v"
`include "machine/cpu/stages/if-id-buffer.v"
`include "machine/cpu/stages/id.v"
`include "machine/cpu/regfile/gpr-file.v"
`include "machine/cpu/regfile/hilo-file.v"
`include "machine/cpu/stages/id-ex-buffer.v"
`include "machine/cpu/stages/ex.v"
`include "machine/cpu/stages/ex-div.v"
`include "machine/cpu/stages/ex-mem-buffer.v"
`include "machine/cpu/stages/mem.v"
`include "machine/cpu/stages/mem-wb-buffer.v"
module mips(
input wire clock,
input wire reset,
input wire[`INST_DATA_BUS] rom_data,
input wire[`INST_DATA_BUS] ram_read_data,
output wire[`INST_ADDR_BUS] rom_addr,
output wire rom_chip_enable,
output wire ram_operation,
output wire[`BYTE_SEL_BUS] ram_select_signal,
output wire[`INST_ADDR_BUS] ram_addr,
output wire[`INST_DATA_BUS] ram_write_data,
output wire ram_chip_enable
);
wire[`INST_ADDR_BUS] if_program_counter;
wire[`INST_ADDR_BUS] if_id_program_counter;
wire[`INST_DATA_BUS] if_id_instruction;
wire[`ALU_OPERATOR_BUS] id_alu_operator;
wire[`ALU_CATEGORY_BUS] id_alu_category;
wire[`REGS_DATA_BUS] id_alu_operand1;
wire[`REGS_DATA_BUS] id_alu_operand2;
wire id_write_enable;
wire[`REGS_ADDR_BUS] id_write_addr;
wire[`INST_DATA_BUS] id_instruction;
wire[`ALU_OPERATOR_BUS] id_ex_buffer_alu_operator;
wire[`ALU_CATEGORY_BUS] id_ex_buffer_alu_category;
wire[`REGS_DATA_BUS] id_ex_buffer_alu_operand1;
wire[`REGS_DATA_BUS] id_ex_buffer_alu_operand2;
wire id_ex_buffer_write_enable;
wire[`REGS_ADDR_BUS] id_ex_buffer_write_addr;
wire[`INST_DATA_BUS] id_ex_instruction;
wire ex_write_enable;
wire[`REGS_ADDR_BUS] ex_write_addr;
wire[`REGS_DATA_BUS] ex_write_data;
wire ex_write_hilo_enable;
wire[`REGS_DATA_BUS] ex_write_hi_data;
wire[`REGS_DATA_BUS] ex_write_lo_data;
wire[`REGS_DATA_BUS] ex_to_div_operand1;
wire[`REGS_DATA_BUS] ex_to_div_operand2;
wire ex_to_div_is_start;
wire ex_to_div_is_signed;
wire[`ALU_OPERATOR_BUS] ex_alu_operator;
wire[`REGS_DATA_BUS] ex_alu_operand2;
wire[`REGS_DATA_BUS] ex_ram_addr;
wire[`DOUBLE_REGS_DATA_BUS] ex_div_result;
wire ex_div_is_ended;
wire ex_mem_buffer_write_enable;
wire[`REGS_ADDR_BUS] ex_mem_buffer_write_addr;
wire[`REGS_DATA_BUS] ex_mem_buffer_write_data;
wire ex_mem_buffer_write_hilo_enable;
wire[`REGS_DATA_BUS] ex_mem_buffer_write_hi_data;
wire[`REGS_DATA_BUS] ex_mem_buffer_write_lo_data;
wire[`DOUBLE_REGS_DATA_BUS] ex_mem_last_result;
wire[`CYCLE_BUS] ex_mem_last_cycle;
wire[`ALU_OPERATOR_BUS] ex_mem_alu_operator;
wire[`REGS_DATA_BUS] ex_mem_alu_operand2;
wire[`REGS_DATA_BUS] ex_mem_ram_addr;
wire mem_write_enable;
wire[`REGS_ADDR_BUS] mem_write_addr;
wire[`REGS_DATA_BUS] mem_write_data;
wire mem_write_hilo_enable;
wire[`REGS_DATA_BUS] mem_write_hi_data;
wire[`REGS_DATA_BUS] mem_write_lo_data;
wire mem_wb_buffer_write_enable;
wire[`REGS_ADDR_BUS] mem_wb_buffer_write_addr;
wire[`REGS_DATA_BUS] mem_wb_buffer_write_data;
wire mem_wb_buffer_write_hilo_enable;
wire[`REGS_DATA_BUS] mem_wb_buffer_write_hi_data;
wire[`REGS_DATA_BUS] mem_wb_buffer_write_lo_data;
wire gpr_file_read_enable1;
wire gpr_file_read_enable2;
wire[`REGS_ADDR_BUS] gpr_file_read_addr1;
wire[`REGS_ADDR_BUS] gpr_file_read_addr2;
wire[`REGS_DATA_BUS] gpr_file_read_result1;
wire[`REGS_DATA_BUS] gpr_file_read_result2;
wire[`REGS_DATA_BUS] hilo_file_hi_data;
wire[`REGS_DATA_BUS] hilo_file_lo_data;
wire[`SIGNAL_BUS] stall_signal;
wire stall_from_id;
wire stall_from_ex;
wire[`DOUBLE_REGS_DATA_BUS] ex_current_result;
wire[`CYCLE_BUS] ex_current_cycle;
wire curr_next_is_in_delayslot_connector;
wire id_is_curr_in_delayslot;
wire id_is_next_in_delayslot;
wire id_branch_signal;
wire[`REGS_DATA_BUS] id_branch_target;
wire[`REGS_DATA_BUS] id_return_target;
wire id_ex_is_curr_in_delayslot;
wire[`REGS_DATA_BUS] id_ex_return_target;
pc_reg pc_reg_instance(
.clock(clock),
.reset(reset),
.stall(stall_signal),
.program_counter(if_program_counter),
.chip_enable(rom_chip_enable),
.branch_signal(id_branch_signal),
.branch_target(id_branch_target)
);
assign rom_addr = if_program_counter;
control control_instance(
.reset(reset),
.stall_from_id(stall_from_id),
.stall_from_ex(stall_from_ex),
.stall(stall_signal)
);
if_id_buffer if_id_buffer_instance(
.clock(clock),
.reset(reset),
.stall(stall_signal),
.if_program_counter(if_program_counter),
.if_instruction(rom_data),
.id_program_counter(if_id_program_counter),
.id_instruction(if_id_instruction)
);
gpr_file gpr_file_instance(
.clock(clock),
.reset(reset),
.write_enable(mem_wb_buffer_write_enable),
.write_addr(mem_wb_buffer_write_addr),
.write_data(mem_wb_buffer_write_data),
.read_enable1(gpr_file_read_enable1),
.read_addr1(gpr_file_read_addr1),
.read_data1(gpr_file_read_result1),
.read_enable2(gpr_file_read_enable2),
.read_addr2(gpr_file_read_addr2),
.read_data2(gpr_file_read_result2)
);
hilo_file hilo_file_instance(
.clock(clock),
.reset(reset),
.write_hilo_enable(mem_wb_buffer_write_hilo_enable),
.write_hi_data(mem_wb_buffer_write_hi_data),
.write_lo_data(mem_wb_buffer_write_lo_data),
.hi_data(hilo_file_hi_data),
.lo_data(hilo_file_lo_data)
);
id id_instance(
.reset(reset),
.program_counter(if_id_program_counter),
.instruction(if_id_instruction),
.ex_write_enable(ex_write_enable),
.ex_write_addr(ex_write_addr),
.ex_write_data(ex_write_data),
.mem_write_enable(mem_write_enable),
.mem_write_addr(mem_write_addr),
.mem_write_data(mem_write_data),
.read_result1(gpr_file_read_result1),
.read_result2(gpr_file_read_result2),
.input_is_curr_in_delayslot(curr_next_is_in_delayslot_connector),
.ex_alu_operator(ex_alu_operator),
.broadcast_instruction(id_instruction),
.is_curr_in_delayslot(id_is_curr_in_delayslot),
.is_next_in_delayslot(id_is_next_in_delayslot),
.branch_signal(id_branch_signal),
.branch_target(id_branch_target),
.return_target(id_return_target),
.read_enable1(gpr_file_read_enable1),
.read_enable2(gpr_file_read_enable2),
.read_addr1(gpr_file_read_addr1),
.read_addr2(gpr_file_read_addr2),
.alu_operator(id_alu_operator),
.alu_category(id_alu_category),
.alu_operand1(id_alu_operand1),
.alu_operand2(id_alu_operand2),
.write_enable(id_write_enable),
.write_addr(id_write_addr),
.stall_signal(stall_from_id)
);
id_ex_buffer id_ex_buffer_instance(
.clock(clock),
.reset(reset),
.stall(stall_signal),
.id_operator(id_alu_operator),
.id_category(id_alu_category),
.id_operand1(id_alu_operand1),
.id_operand2(id_alu_operand2),
.id_write_addr(id_write_addr),
.id_write_enable(id_write_enable),
.id_return_target(id_return_target),
.id_is_curr_in_delayslot(id_is_curr_in_delayslot),
.input_is_next_in_delayslot(id_is_next_in_delayslot),
.id_instruction(id_instruction),
.ex_operator(id_ex_buffer_alu_operator),
.ex_category(id_ex_buffer_alu_category),
.ex_operand1(id_ex_buffer_alu_operand1),
.ex_operand2(id_ex_buffer_alu_operand2),
.ex_write_addr(id_ex_buffer_write_addr),
.ex_write_enable(id_ex_buffer_write_enable),
.ex_return_target(id_ex_return_target),
.ex_is_curr_in_delayslot(id_ex_is_curr_in_delayslot),
.is_curr_in_delayslot(curr_next_is_in_delayslot_connector),
.ex_instruction(id_ex_instruction)
);
ex ex_instance(
.reset(reset),
.operand_hi(hilo_file_hi_data),
.operand_lo(hilo_file_lo_data),
.wb_write_hilo_enable(mem_wb_buffer_write_hilo_enable),
.wb_write_hi_data(mem_wb_buffer_write_hi_data),
.wb_write_lo_data(mem_wb_buffer_write_lo_data),
.mem_write_hilo_enable(mem_write_hilo_enable),
.mem_write_hi_data(mem_write_hi_data),
.mem_write_lo_data(mem_write_lo_data),
.ex_div_result(ex_div_result),
.ex_div_is_ended(ex_div_is_ended),
.operator(id_ex_buffer_alu_operator),
.category(id_ex_buffer_alu_category),
.operand1(id_ex_buffer_alu_operand1),
.operand2(id_ex_buffer_alu_operand2),
.input_write_addr(id_ex_buffer_write_addr),
.input_write_enable(id_ex_buffer_write_enable),
.last_result(ex_mem_last_result),
.last_cycle(ex_mem_last_cycle),
.return_target(id_ex_return_target),
.is_curr_in_delayslot(id_ex_is_curr_in_delayslot),
.instruction(id_ex_instruction),
.to_div_operand1(ex_to_div_operand1),
.to_div_operand2(ex_to_div_operand2),
.to_div_is_start(ex_to_div_is_start),
.to_div_is_signed(ex_to_div_is_signed),
.write_hilo_enable(ex_write_hilo_enable),
.write_hi_data(ex_write_hi_data),
.write_lo_data(ex_write_lo_data),
.write_addr(ex_write_addr),
.write_enable(ex_write_enable),
.write_data(ex_write_data),
.current_result(ex_current_result),
.current_cycle(ex_current_cycle),
.stall_signal(stall_from_ex),
.broadcast_alu_operator(ex_alu_operator),
.broadcast_alu_operand2(ex_alu_operand2),
.broadcast_ram_addr(ex_ram_addr)
);
ex_div ex_div_instance(
.clock(clock),
.reset(reset),
.is_signed(ex_to_div_is_signed),
.operand1(ex_to_div_operand1),
.operand2(ex_to_div_operand2),
.is_start(ex_to_div_is_start),
.is_annul(1'b0),
.is_ended(ex_div_is_ended),
.result(ex_div_result)
);
ex_mem_buffer ex_mem_buffer_instance(
.clock(clock),
.reset(reset),
.stall(stall_signal),
.ex_write_enable(ex_write_enable),
.ex_write_addr(ex_write_addr),
.ex_write_data(ex_write_data),
.ex_write_hilo_enable(ex_write_hilo_enable),
.ex_write_hi_data(ex_write_hi_data),
.ex_write_lo_data(ex_write_lo_data),
.ex_current_result(ex_current_result),
.ex_current_cycle(ex_current_cycle),
.ex_alu_operator(ex_alu_operator),
.ex_alu_operand2(ex_alu_operand2),
.ex_ram_addr(ex_ram_addr),
.mem_write_enable(ex_mem_buffer_write_enable),
.mem_write_addr(ex_mem_buffer_write_addr),
.mem_write_data(ex_mem_buffer_write_data),
.mem_write_hilo_enable(ex_mem_buffer_write_hilo_enable),
.mem_write_hi_data(ex_mem_buffer_write_hi_data),
.mem_write_lo_data(ex_mem_buffer_write_lo_data),
.mem_last_result(ex_mem_last_result),
.mem_last_cycle(ex_mem_last_cycle),
.mem_alu_operator(ex_mem_alu_operator),
.mem_alu_operand2(ex_mem_alu_operand2),
.mem_ram_addr(ex_mem_ram_addr)
);
mem mem_instance(
.reset(reset),
.input_write_enable(ex_mem_buffer_write_enable),
.input_write_addr(ex_mem_buffer_write_addr),
.input_write_data(ex_mem_buffer_write_data),
.input_write_hilo_enable(ex_mem_buffer_write_hilo_enable),
.input_write_hi_data(ex_mem_buffer_write_hi_data),
.input_write_lo_data(ex_mem_buffer_write_lo_data),
.input_alu_operator(ex_mem_alu_operator),
.input_alu_operand2(ex_mem_alu_operand2),
.input_ram_addr(ex_mem_ram_addr),
.input_ram_read_data(ram_read_data),
.write_enable(mem_write_enable),
.write_addr(mem_write_addr),
.write_data(mem_write_data),
.write_hilo_enable(mem_write_hilo_enable),
.write_hi_data(mem_write_hi_data),
.write_lo_data(mem_write_lo_data),
.ram_addr(ram_addr),
.ram_operation(ram_operation),
.ram_select_signal(ram_select_signal),
.ram_write_data(ram_write_data),
.ram_chip_enable(ram_chip_enable)
);
mem_wb_buffer mem_wb_buffer_instance(
.clock(clock),
.reset(reset),
.stall(stall_signal),
.mem_write_enable(mem_write_enable),
.mem_write_addr(mem_write_addr),
.mem_write_data(mem_write_data),
.mem_write_hilo_enable(mem_write_hilo_enable),
.mem_write_hi_data(mem_write_hi_data),
.mem_write_lo_data(mem_write_lo_data),
.wb_write_enable(mem_wb_buffer_write_enable),
.wb_write_addr(mem_wb_buffer_write_addr),
.wb_write_data(mem_wb_buffer_write_data),
.wb_write_hilo_enable(mem_wb_buffer_write_hilo_enable),
.wb_write_hi_data(mem_wb_buffer_write_hi_data),
.wb_write_lo_data(mem_wb_buffer_write_lo_data)
);
endmodule // mips
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_4_V
`define SKY130_FD_SC_MS__FILL_4_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fill_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fill_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_4_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:49:04 2016
/////////////////////////////////////////////////////////////
module ACA_II_N32_Q16 ( in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
wire n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72,
n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86,
n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155,
n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166,
n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177,
n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, n188,
n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199,
n200, n201, n202;
OAI21X2TS U2 ( .A0(n177), .A1(n173), .B0(n174), .Y(n167) );
AOI21X2TS U3 ( .A0(n117), .A1(n116), .B0(n115), .Y(n122) );
NAND2X1TS U4 ( .A(in1[9]), .B(in2[9]), .Y(n79) );
OAI21XLTS U5 ( .A0(n72), .A1(n197), .B0(n71), .Y(n73) );
NOR2XLTS U6 ( .A(n23), .B(n26), .Y(n28) );
INVX2TS U7 ( .A(n178), .Y(n180) );
NAND2X1TS U8 ( .A(in1[8]), .B(in2[8]), .Y(n192) );
NOR2XLTS U9 ( .A(n182), .B(n83), .Y(n85) );
OAI21XLTS U10 ( .A0(n22), .A1(n23), .B0(n25), .Y(n19) );
OAI21XLTS U11 ( .A0(n190), .A1(n52), .B0(n187), .Y(n56) );
OAI21X2TS U12 ( .A0(n178), .A1(n201), .B0(n179), .Y(n29) );
XOR2X1TS U13 ( .A(n129), .B(n128), .Y(res[29]) );
NOR2X2TS U14 ( .A(in1[9]), .B(in2[9]), .Y(n99) );
XNOR2X1TS U15 ( .A(n153), .B(n152), .Y(res[23]) );
XOR2X1TS U16 ( .A(n158), .B(n157), .Y(res[22]) );
OAI21X1TS U17 ( .A0(n172), .A1(n168), .B0(n169), .Y(res[32]) );
OAI21X2TS U18 ( .A0(n158), .A1(n154), .B0(n155), .Y(n153) );
XOR2X1TS U19 ( .A(n122), .B(n119), .Y(res[20]) );
OAI21X2TS U20 ( .A0(n129), .A1(n125), .B0(n126), .Y(n144) );
XOR2XLTS U21 ( .A(n195), .B(n194), .Y(res[8]) );
OAI21X2TS U22 ( .A0(n98), .A1(n94), .B0(n95), .Y(n113) );
XOR2XLTS U23 ( .A(n91), .B(n88), .Y(res[18]) );
OAI21X1TS U24 ( .A0(n195), .A1(n191), .B0(n192), .Y(n82) );
XOR2XLTS U25 ( .A(n98), .B(n97), .Y(res[27]) );
XOR2XLTS U26 ( .A(n190), .B(n189), .Y(res[24]) );
OAI21X2TS U27 ( .A0(n91), .A1(n90), .B0(n89), .Y(n117) );
OAI21X1TS U28 ( .A0(n200), .A1(n196), .B0(n197), .Y(n69) );
OAI21X1TS U29 ( .A0(n186), .A1(n182), .B0(n183), .Y(n43) );
XOR2XLTS U30 ( .A(n200), .B(n199), .Y(res[6]) );
XOR2XLTS U31 ( .A(n61), .B(n60), .Y(res[5]) );
OAI21X1TS U32 ( .A0(n190), .A1(n46), .B0(n45), .Y(n51) );
XOR2XLTS U33 ( .A(n186), .B(n185), .Y(res[16]) );
AOI21X2TS U34 ( .A0(n44), .A1(n14), .B0(n13), .Y(n98) );
AOI21X2TS U35 ( .A0(n86), .A1(n85), .B0(n84), .Y(n91) );
XOR2XLTS U36 ( .A(n22), .B(n21), .Y(res[2]) );
OAI21X2TS U37 ( .A0(n99), .A1(n192), .B0(n79), .Y(n100) );
OAI21X1TS U38 ( .A0(n163), .A1(n174), .B0(n164), .Y(n34) );
NOR2X1TS U39 ( .A(n137), .B(n139), .Y(n33) );
INVX2TS U40 ( .A(n141), .Y(n16) );
INVX2TS U41 ( .A(n108), .Y(n132) );
INVX2TS U42 ( .A(n173), .Y(n175) );
INVX2TS U43 ( .A(n163), .Y(n165) );
OAI21X1TS U44 ( .A0(n149), .A1(n155), .B0(n150), .Y(n5) );
OAI21X1TS U45 ( .A0(n123), .A1(n120), .B0(n145), .Y(n7) );
NOR2X1TS U46 ( .A(n121), .B(n123), .Y(n4) );
OR2X2TS U47 ( .A(in1[25]), .B(in2[25]), .Y(n54) );
OR2X2TS U48 ( .A(in1[28]), .B(in2[28]), .Y(n111) );
OR2X2TS U49 ( .A(in1[30]), .B(in2[30]), .Y(n142) );
NAND2X2TS U50 ( .A(in1[10]), .B(in2[10]), .Y(n105) );
OAI21X4TS U51 ( .A0(n122), .A1(n121), .B0(n120), .Y(n148) );
NOR2X1TS U52 ( .A(in1[4]), .B(in2[4]), .Y(n62) );
NOR2X1TS U53 ( .A(n196), .B(n72), .Y(n74) );
AOI21X1TS U54 ( .A0(n84), .A1(n3), .B0(n2), .Y(n10) );
NOR2X2TS U55 ( .A(in1[3]), .B(in2[3]), .Y(n26) );
INVX2TS U56 ( .A(n29), .Y(n22) );
INVX2TS U57 ( .A(n62), .Y(n58) );
INVX2TS U58 ( .A(n78), .Y(n66) );
NOR2X2TS U59 ( .A(in1[7]), .B(in2[7]), .Y(n72) );
INVX2TS U60 ( .A(n102), .Y(n195) );
INVX2TS U61 ( .A(n130), .Y(n131) );
INVX2TS U62 ( .A(n139), .Y(n161) );
INVX2TS U63 ( .A(n86), .Y(n186) );
INVX2TS U64 ( .A(n114), .Y(n115) );
INVX2TS U65 ( .A(n123), .Y(n147) );
AOI21X2TS U66 ( .A0(n148), .A1(n147), .B0(n146), .Y(n158) );
INVX2TS U67 ( .A(n145), .Y(n146) );
INVX2TS U68 ( .A(n52), .Y(n188) );
INVX2TS U69 ( .A(n187), .Y(n12) );
INVX2TS U70 ( .A(n44), .Y(n190) );
INVX2TS U71 ( .A(n110), .Y(n15) );
NOR2X1TS U72 ( .A(n173), .B(n163), .Y(n35) );
INVX2TS U73 ( .A(n64), .Y(n57) );
NOR2X2TS U74 ( .A(in1[14]), .B(in2[14]), .Y(n173) );
INVX2TS U75 ( .A(n159), .Y(n160) );
NOR2X1TS U76 ( .A(in1[24]), .B(in2[24]), .Y(n52) );
INVX2TS U77 ( .A(n23), .Y(n20) );
INVX2TS U78 ( .A(n26), .Y(n17) );
NAND2X1TS U79 ( .A(n58), .B(n64), .Y(n30) );
INVX2TS U80 ( .A(n196), .Y(n198) );
INVX2TS U81 ( .A(n72), .Y(n67) );
INVX2TS U82 ( .A(n191), .Y(n193) );
XOR2XLTS U83 ( .A(n107), .B(n104), .Y(res[10]) );
INVX2TS U84 ( .A(n106), .Y(n103) );
XOR2XLTS U85 ( .A(n138), .B(n135), .Y(res[12]) );
INVX2TS U86 ( .A(n182), .Y(n184) );
INVX2TS U87 ( .A(n83), .Y(n41) );
INVX2TS U88 ( .A(n154), .Y(n156) );
NAND2X1TS U89 ( .A(n49), .B(n48), .Y(n50) );
INVX2TS U90 ( .A(n94), .Y(n96) );
INVX2TS U91 ( .A(n125), .Y(n127) );
AOI21X1TS U92 ( .A0(n133), .A1(n132), .B0(n131), .Y(n138) );
OAI21X2TS U93 ( .A0(n78), .A1(n77), .B0(n76), .Y(n102) );
NOR2X2TS U94 ( .A(in1[21]), .B(in2[21]), .Y(n123) );
NOR2X2TS U95 ( .A(in1[13]), .B(in2[13]), .Y(n139) );
NOR2X2TS U96 ( .A(in1[11]), .B(in2[11]), .Y(n108) );
INVX2TS U97 ( .A(n92), .Y(n116) );
NOR2X2TS U98 ( .A(in1[19]), .B(in2[19]), .Y(n92) );
INVX2TS U99 ( .A(n65), .Y(n59) );
NOR2X2TS U100 ( .A(in1[5]), .B(in2[5]), .Y(n65) );
NOR2X1TS U101 ( .A(n46), .B(n47), .Y(n14) );
NOR2X2TS U102 ( .A(in1[16]), .B(in2[16]), .Y(n182) );
NOR2X1TS U103 ( .A(n191), .B(n99), .Y(n101) );
NOR2X2TS U104 ( .A(in1[8]), .B(in2[8]), .Y(n191) );
INVX2TS U105 ( .A(n121), .Y(n118) );
NOR2X2TS U106 ( .A(in1[20]), .B(in2[20]), .Y(n121) );
INVX2TS U107 ( .A(n90), .Y(n87) );
NOR2X1TS U108 ( .A(n90), .B(n92), .Y(n3) );
NOR2X2TS U109 ( .A(in1[18]), .B(in2[18]), .Y(n90) );
OAI21X2TS U110 ( .A0(n138), .A1(n137), .B0(n136), .Y(n162) );
INVX2TS U111 ( .A(n137), .Y(n134) );
NOR2X2TS U112 ( .A(in1[12]), .B(in2[12]), .Y(n137) );
INVX2TS U113 ( .A(n168), .Y(n170) );
NOR2X1TS U114 ( .A(in1[31]), .B(in2[31]), .Y(n168) );
AOI21X2TS U115 ( .A0(n29), .A1(n28), .B0(n27), .Y(n78) );
OAI21X1TS U116 ( .A0(n45), .A1(n47), .B0(n48), .Y(n13) );
INVX2TS U117 ( .A(n53), .Y(n11) );
INVX2TS U118 ( .A(n99), .Y(n80) );
INVX2TS U119 ( .A(n149), .Y(n151) );
OAI21X2TS U120 ( .A0(n10), .A1(n9), .B0(n8), .Y(n44) );
NAND2X1TS U121 ( .A(n17), .B(n24), .Y(n18) );
NOR2X2TS U122 ( .A(in1[17]), .B(in2[17]), .Y(n83) );
NAND2X1TS U123 ( .A(in1[16]), .B(in2[16]), .Y(n183) );
NAND2X1TS U124 ( .A(in1[17]), .B(in2[17]), .Y(n40) );
OAI21X2TS U125 ( .A0(n83), .A1(n183), .B0(n40), .Y(n84) );
NAND2X1TS U126 ( .A(in1[18]), .B(in2[18]), .Y(n89) );
NAND2X1TS U127 ( .A(in1[19]), .B(in2[19]), .Y(n114) );
OAI21X1TS U128 ( .A0(n92), .A1(n89), .B0(n114), .Y(n2) );
NOR2X2TS U129 ( .A(in1[22]), .B(in2[22]), .Y(n154) );
NOR2X2TS U130 ( .A(in1[23]), .B(in2[23]), .Y(n149) );
NOR2X1TS U131 ( .A(n154), .B(n149), .Y(n6) );
NAND2X1TS U132 ( .A(n4), .B(n6), .Y(n9) );
NAND2X1TS U133 ( .A(in1[20]), .B(in2[20]), .Y(n120) );
NAND2X1TS U134 ( .A(in1[21]), .B(in2[21]), .Y(n145) );
NAND2X1TS U135 ( .A(in1[22]), .B(in2[22]), .Y(n155) );
NAND2X1TS U136 ( .A(in1[23]), .B(in2[23]), .Y(n150) );
AOI21X1TS U137 ( .A0(n7), .A1(n6), .B0(n5), .Y(n8) );
NAND2X1TS U138 ( .A(n188), .B(n54), .Y(n46) );
NOR2X2TS U139 ( .A(in1[26]), .B(in2[26]), .Y(n47) );
NAND2X1TS U140 ( .A(in1[24]), .B(in2[24]), .Y(n187) );
NAND2X1TS U141 ( .A(in1[25]), .B(in2[25]), .Y(n53) );
AOI21X1TS U142 ( .A0(n54), .A1(n12), .B0(n11), .Y(n45) );
NAND2X1TS U143 ( .A(in1[26]), .B(in2[26]), .Y(n48) );
NOR2X1TS U144 ( .A(in1[27]), .B(in2[27]), .Y(n94) );
NAND2X1TS U145 ( .A(in1[27]), .B(in2[27]), .Y(n95) );
NAND2X1TS U146 ( .A(in1[28]), .B(in2[28]), .Y(n110) );
AOI21X1TS U147 ( .A0(n113), .A1(n111), .B0(n15), .Y(n129) );
NOR2X1TS U148 ( .A(in1[29]), .B(in2[29]), .Y(n125) );
NAND2X1TS U149 ( .A(in1[29]), .B(in2[29]), .Y(n126) );
NAND2X1TS U150 ( .A(in1[30]), .B(in2[30]), .Y(n141) );
AOI21X4TS U151 ( .A0(n144), .A1(n142), .B0(n16), .Y(n172) );
NAND2X1TS U152 ( .A(in1[31]), .B(in2[31]), .Y(n169) );
NOR2X1TS U153 ( .A(in1[1]), .B(in2[1]), .Y(n178) );
NAND2X1TS U154 ( .A(in1[0]), .B(in2[0]), .Y(n201) );
NAND2X1TS U155 ( .A(in1[1]), .B(in2[1]), .Y(n179) );
NOR2X2TS U156 ( .A(in1[2]), .B(in2[2]), .Y(n23) );
NAND2X1TS U157 ( .A(in1[2]), .B(in2[2]), .Y(n25) );
NAND2X1TS U158 ( .A(in1[3]), .B(in2[3]), .Y(n24) );
XNOR2X1TS U159 ( .A(n19), .B(n18), .Y(res[3]) );
NAND2X1TS U160 ( .A(n20), .B(n25), .Y(n21) );
OAI21X1TS U161 ( .A0(n26), .A1(n25), .B0(n24), .Y(n27) );
NAND2X1TS U162 ( .A(in1[4]), .B(in2[4]), .Y(n64) );
XNOR2X1TS U163 ( .A(n66), .B(n30), .Y(res[4]) );
NOR2X2TS U164 ( .A(in1[10]), .B(in2[10]), .Y(n106) );
NOR2XLTS U165 ( .A(n106), .B(n108), .Y(n32) );
NAND2X1TS U166 ( .A(in1[11]), .B(in2[11]), .Y(n130) );
OAI21XLTS U167 ( .A0(n108), .A1(n105), .B0(n130), .Y(n31) );
AOI21X1TS U168 ( .A0(n100), .A1(n32), .B0(n31), .Y(n39) );
NOR2X2TS U169 ( .A(in1[15]), .B(in2[15]), .Y(n163) );
NAND2X1TS U170 ( .A(n33), .B(n35), .Y(n38) );
NAND2X1TS U171 ( .A(in1[12]), .B(in2[12]), .Y(n136) );
NAND2X1TS U172 ( .A(in1[13]), .B(in2[13]), .Y(n159) );
OAI21XLTS U173 ( .A0(n139), .A1(n136), .B0(n159), .Y(n36) );
NAND2X1TS U174 ( .A(in1[14]), .B(in2[14]), .Y(n174) );
NAND2X1TS U175 ( .A(in1[15]), .B(in2[15]), .Y(n164) );
AOI21X1TS U176 ( .A0(n36), .A1(n35), .B0(n34), .Y(n37) );
OAI21X2TS U177 ( .A0(n39), .A1(n38), .B0(n37), .Y(n86) );
NAND2X1TS U178 ( .A(n41), .B(n40), .Y(n42) );
XNOR2X1TS U179 ( .A(n43), .B(n42), .Y(res[17]) );
INVX2TS U180 ( .A(n47), .Y(n49) );
XNOR2X1TS U181 ( .A(n51), .B(n50), .Y(res[26]) );
NAND2X1TS U182 ( .A(n54), .B(n53), .Y(n55) );
XNOR2X1TS U183 ( .A(n56), .B(n55), .Y(res[25]) );
AOI21X1TS U184 ( .A0(n66), .A1(n58), .B0(n57), .Y(n61) );
NAND2X1TS U185 ( .A(in1[5]), .B(in2[5]), .Y(n63) );
NAND2X1TS U186 ( .A(n59), .B(n63), .Y(n60) );
NOR2X1TS U187 ( .A(n62), .B(n65), .Y(n70) );
OAI21X1TS U188 ( .A0(n65), .A1(n64), .B0(n63), .Y(n75) );
AOI21X1TS U189 ( .A0(n66), .A1(n70), .B0(n75), .Y(n200) );
NOR2X2TS U190 ( .A(in1[6]), .B(in2[6]), .Y(n196) );
NAND2X1TS U191 ( .A(in1[6]), .B(in2[6]), .Y(n197) );
NAND2X1TS U192 ( .A(in1[7]), .B(in2[7]), .Y(n71) );
NAND2X1TS U193 ( .A(n67), .B(n71), .Y(n68) );
XNOR2X1TS U194 ( .A(n69), .B(n68), .Y(res[7]) );
NAND2X1TS U195 ( .A(n70), .B(n74), .Y(n77) );
AOI21X1TS U196 ( .A0(n75), .A1(n74), .B0(n73), .Y(n76) );
NAND2X1TS U197 ( .A(n80), .B(n79), .Y(n81) );
XNOR2X1TS U198 ( .A(n82), .B(n81), .Y(res[9]) );
NAND2X1TS U199 ( .A(n87), .B(n89), .Y(n88) );
NAND2X1TS U200 ( .A(n116), .B(n114), .Y(n93) );
XNOR2X1TS U201 ( .A(n117), .B(n93), .Y(res[19]) );
NAND2X1TS U202 ( .A(n96), .B(n95), .Y(n97) );
AOI21X4TS U203 ( .A0(n102), .A1(n101), .B0(n100), .Y(n107) );
NAND2X1TS U204 ( .A(n103), .B(n105), .Y(n104) );
OAI21X4TS U205 ( .A0(n107), .A1(n106), .B0(n105), .Y(n133) );
NAND2X1TS U206 ( .A(n132), .B(n130), .Y(n109) );
XNOR2X1TS U207 ( .A(n133), .B(n109), .Y(res[11]) );
NAND2X1TS U208 ( .A(n111), .B(n110), .Y(n112) );
XNOR2X1TS U209 ( .A(n113), .B(n112), .Y(res[28]) );
NAND2X1TS U210 ( .A(n118), .B(n120), .Y(n119) );
NAND2X1TS U211 ( .A(n147), .B(n145), .Y(n124) );
XNOR2X1TS U212 ( .A(n148), .B(n124), .Y(res[21]) );
NAND2X1TS U213 ( .A(n127), .B(n126), .Y(n128) );
NAND2X1TS U214 ( .A(n134), .B(n136), .Y(n135) );
NAND2X1TS U215 ( .A(n161), .B(n159), .Y(n140) );
XNOR2X1TS U216 ( .A(n162), .B(n140), .Y(res[13]) );
NAND2X1TS U217 ( .A(n142), .B(n141), .Y(n143) );
XNOR2X1TS U218 ( .A(n144), .B(n143), .Y(res[30]) );
NAND2X1TS U219 ( .A(n151), .B(n150), .Y(n152) );
NAND2X1TS U220 ( .A(n156), .B(n155), .Y(n157) );
AOI21X4TS U221 ( .A0(n162), .A1(n161), .B0(n160), .Y(n177) );
NAND2X1TS U222 ( .A(n165), .B(n164), .Y(n166) );
XNOR2X1TS U223 ( .A(n167), .B(n166), .Y(res[15]) );
NAND2X1TS U224 ( .A(n170), .B(n169), .Y(n171) );
XOR2X1TS U225 ( .A(n172), .B(n171), .Y(res[31]) );
NAND2X1TS U226 ( .A(n175), .B(n174), .Y(n176) );
XOR2X1TS U227 ( .A(n177), .B(n176), .Y(res[14]) );
NAND2X1TS U228 ( .A(n180), .B(n179), .Y(n181) );
XOR2XLTS U229 ( .A(n181), .B(n201), .Y(res[1]) );
NAND2X1TS U230 ( .A(n184), .B(n183), .Y(n185) );
NAND2X1TS U231 ( .A(n188), .B(n187), .Y(n189) );
NAND2X1TS U232 ( .A(n193), .B(n192), .Y(n194) );
NAND2X1TS U233 ( .A(n198), .B(n197), .Y(n199) );
OR2X1TS U234 ( .A(in1[0]), .B(in2[0]), .Y(n202) );
CLKAND2X2TS U235 ( .A(n202), .B(n201), .Y(res[0]) );
initial $sdf_annotate("ACA_II_N32_Q16_syn.sdf");
endmodule
|
(* Copyright (c) 2008-2010, 2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import String List.
Require Import CpdtTactics DepList.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(** printing ~> $\leadsto$ *)
(** %\chapter{Generic Programming}% *)
(** %\index{generic programming}% _Generic programming_ makes it possible to write functions that operate over different types of data. %\index{parametric polymorphism}%Parametric polymorphism in ML and Haskell is one of the simplest examples. ML-style %\index{module systems}%module systems%~\cite{modules}% and Haskell %\index{type classes}%type classes%~\cite{typeclasses}% are more flexible cases. These language features are often not as powerful as we would like. For instance, while Haskell includes a type class classifying those types whose values can be pretty-printed, per-type pretty-printing is usually either implemented manually or implemented via a %\index{deriving clauses}%[deriving] clause%~\cite{deriving}%, which triggers ad-hoc code generation. Some clever encoding tricks have been used to achieve better within Haskell and other languages, but we can do%\index{datatype-generic programming}% _datatype-generic programming_ much more cleanly with dependent types. Thanks to the expressive power of CIC, we need no special language support.
Generic programming can often be very useful in Coq developments, so we devote this chapter to studying it. In a proof assistant, there is the new possibility of generic proofs about generic programs, which we also devote some space to. *)
(** * Reifying Datatype Definitions *)
(** The key to generic programming with dependent types is%\index{universe types}% _universe types_. This concept should not be confused with the idea of _universes_ from the metatheory of CIC and related languages, which we will study in more detail in the next chapter. Rather, the idea of universe types is to define inductive types that provide _syntactic representations_ of Coq types. We cannot directly write CIC programs that do case analysis on types, but we _can_ case analyze on reified syntactic versions of those types.
Thus, to begin, we must define a syntactic representation of some class of datatypes. In this chapter, our running example will have to do with basic algebraic datatypes, of the kind found in ML and Haskell, but without additional bells and whistles like type parameters and mutually recursive definitions.
The first step is to define a representation for constructors of our datatypes. We use the [Record] command as a shorthand for defining an inductive type with a single constructor, plus projection functions for pulling out any of the named arguments to that constructor. *)
(* EX: Define a reified representation of simple algebraic datatypes. *)
(* begin thide *)
Record constructor : Type := Con {
nonrecursive : Type;
recursive : nat
}.
(** The idea is that a constructor represented as [Con T n] has [n] arguments of the type that we are defining. Additionally, all of the other, non-recursive arguments can be encoded in the type [T]. When there are no non-recursive arguments, [T] can be [unit]. When there are two non-recursive arguments, of types [A] and [B], [T] can be [A * B]. We can generalize to any number of arguments via tupling.
With this definition, it is easy to define a datatype representation in terms of lists of constructors. The intended meaning is that the datatype came from an inductive definition including exactly the constructors in the list. *)
Definition datatype := list constructor.
(** Here are a few example encodings for some common types from the Coq standard library. While our syntax type does not support type parameters directly, we can implement them at the meta level, via functions from types to [datatype]s. *)
Definition Empty_set_dt : datatype := nil.
Definition unit_dt : datatype := Con unit 0 :: nil.
Definition bool_dt : datatype := Con unit 0 :: Con unit 0 :: nil.
Definition nat_dt : datatype := Con unit 0 :: Con unit 1 :: nil.
Definition list_dt (A : Type) : datatype := Con unit 0 :: Con A 1 :: nil.
(** The type [Empty_set] has no constructors, so its representation is the empty list. The type [unit] has one constructor with no arguments, so its one reified constructor indicates no non-recursive data and [0] recursive arguments. The representation for [bool] just duplicates this single argumentless constructor. We get from [bool] to [nat] by changing one of the constructors to indicate 1 recursive argument. We get from [nat] to [list] by adding a non-recursive argument of a parameter type [A].
As a further example, we can do the same encoding for a generic binary tree type. *)
(* end thide *)
Section tree.
Variable A : Type.
Inductive tree : Type :=
| Leaf : A -> tree
| Node : tree -> tree -> tree.
End tree.
(* begin thide *)
Definition tree_dt (A : Type) : datatype := Con A 0 :: Con unit 2 :: nil.
(** Each datatype representation stands for a family of inductive types. For a specific real datatype and a reputed representation for it, it is useful to define a type of _evidence_ that the datatype is compatible with the encoding. *)
Section denote.
Variable T : Type.
(** This variable stands for the concrete datatype that we are interested in. *)
Definition constructorDenote (c : constructor) :=
nonrecursive c -> ilist T (recursive c) -> T.
(** We write that a constructor is represented as a function returning a [T]. Such a function takes two arguments, which pack together the non-recursive and recursive arguments of the constructor. We represent a tuple of all recursive arguments using the length-indexed list type %\index{Gallina terms!ilist}%[ilist] that we met in Chapter 8. *)
Definition datatypeDenote := hlist constructorDenote.
(** Finally, the evidence for type [T] is a %\index{Gallina terms!hlist}%heterogeneous list, including a constructor denotation for every constructor encoding in a datatype encoding. Recall that, since we are inside a section binding [T] as a variable, [constructorDenote] is automatically parameterized by [T]. *)
End denote.
(* end thide *)
(** Some example pieces of evidence should help clarify the convention. First, we define a helpful notation for constructor denotations. %The ASCII \texttt{\textasciitilde{}>} from the notation will be rendered later as $\leadsto$.% *)
Notation "[ v , r ~> x ]" := ((fun v r => x) : constructorDenote _ (Con _ _)).
(* begin thide *)
Definition Empty_set_den : datatypeDenote Empty_set Empty_set_dt :=
HNil.
Definition unit_den : datatypeDenote unit unit_dt :=
[_, _ ~> tt] ::: HNil.
Definition bool_den : datatypeDenote bool bool_dt :=
[_, _ ~> true] ::: [_, _ ~> false] ::: HNil.
Definition nat_den : datatypeDenote nat nat_dt :=
[_, _ ~> O] ::: [_, r ~> S (hd r)] ::: HNil.
Definition list_den (A : Type) : datatypeDenote (list A) (list_dt A) :=
[_, _ ~> nil] ::: [x, r ~> x :: hd r] ::: HNil.
Definition tree_den (A : Type) : datatypeDenote (tree A) (tree_dt A) :=
[v, _ ~> Leaf v] ::: [_, r ~> Node (hd r) (hd (tl r))] ::: HNil.
(* end thide *)
(** Recall that the [hd] and [tl] calls above operate on richly typed lists, where type indices tell us the lengths of lists, guaranteeing the safety of operations like [hd]. The type annotation attached to each definition provides enough information for Coq to infer list lengths at appropriate points. *)
(** * Recursive Definitions *)
(* EX: Define a generic [size] function. *)
(** We built these encodings of datatypes to help us write datatype-generic recursive functions. To do so, we will want a reified representation of a%\index{recursion schemes}% _recursion scheme_ for each type, similar to the [T_rect] principle generated automatically for an inductive definition of [T]. A clever reuse of [datatypeDenote] yields a short definition. *)
(* begin thide *)
Definition fixDenote (T : Type) (dt : datatype) :=
forall (R : Type), datatypeDenote R dt -> (T -> R).
(** The idea of a recursion scheme is parameterized by a type and a reputed encoding of it. The principle itself is polymorphic in a type [R], which is the return type of the recursive function that we mean to write. The next argument is a heterogeneous list of one case of the recursive function definition for each datatype constructor. The [datatypeDenote] function turns out to have just the right definition to express the type we need; a set of function cases is just like an alternate set of constructors where we replace the original type [T] with the function result type [R]. Given such a reified definition, a [fixDenote] invocation returns a function from [T] to [R], which is just what we wanted.
We are ready to write some example functions now. It will be useful to use one new function from the [DepList] library included in the book source. *)
Check hmake.
(** %\vspace{-.15in}% [[
hmake
: forall (A : Type) (B : A -> Type),
(forall x : A, B x) -> forall ls : list A, hlist B ls
]]
The function [hmake] is a kind of [map] alternative that goes from a regular [list] to an [hlist]. We can use it to define a generic size function that counts the number of constructors used to build a value in a datatype. *)
Definition size T dt (fx : fixDenote T dt) : T -> nat :=
fx nat (hmake (B := constructorDenote nat) (fun _ _ r => foldr plus 1 r) dt).
(** Our definition is parameterized over a recursion scheme [fx]. We instantiate [fx] by passing it the function result type and a set of function cases, where we build the latter with [hmake]. The function argument to [hmake] takes three arguments: the representation of a constructor, its non-recursive arguments, and the results of recursive calls on all of its recursive arguments. We only need the recursive call results here, so we call them [r] and bind the other two inputs with wildcards. The actual case body is simple: we add together the recursive call results and increment the result by one (to account for the current constructor). This [foldr] function is an [ilist]-specific version defined in the [DepList] module.
It is instructive to build [fixDenote] values for our example types and see what specialized [size] functions result from them. *)
Definition Empty_set_fix : fixDenote Empty_set Empty_set_dt :=
fun R _ emp => match emp with end.
Eval compute in size Empty_set_fix.
(** %\vspace{-.15in}% [[
= fun emp : Empty_set => match emp return nat with
end
: Empty_set -> nat
]]
Despite all the fanciness of the generic [size] function, CIC's standard computation rules suffice to normalize the generic function specialization to exactly what we would have written manually. *)
Definition unit_fix : fixDenote unit unit_dt :=
fun R cases _ => (hhd cases) tt INil.
Eval compute in size unit_fix.
(** %\vspace{-.15in}% [[
= fun _ : unit => 1
: unit -> nat
]]
Again normalization gives us the natural function definition. We see this pattern repeated for our other example types. *)
Definition bool_fix : fixDenote bool bool_dt :=
fun R cases b => if b
then (hhd cases) tt INil
else (hhd (htl cases)) tt INil.
Eval compute in size bool_fix.
(** %\vspace{-.15in}% [[
= fun b : bool => if b then 1 else 1
: bool -> nat
]]
*)
Definition nat_fix : fixDenote nat nat_dt :=
fun R cases => fix F (n : nat) : R :=
match n with
| O => (hhd cases) tt INil
| S n' => (hhd (htl cases)) tt (ICons (F n') INil)
end.
(** To peek at the [size] function for [nat], it is useful to avoid full computation, so that the recursive definition of addition is not expanded inline. We can accomplish this with proper flags for the [cbv] reduction strategy. *)
Eval cbv beta iota delta -[plus] in size nat_fix.
(** %\vspace{-.15in}% [[
= fix F (n : nat) : nat := match n with
| 0 => 1
| S n' => F n' + 1
end
: nat -> nat
]]
*)
Definition list_fix (A : Type) : fixDenote (list A) (list_dt A) :=
fun R cases => fix F (ls : list A) : R :=
match ls with
| nil => (hhd cases) tt INil
| x :: ls' => (hhd (htl cases)) x (ICons (F ls') INil)
end.
Eval cbv beta iota delta -[plus] in fun A => size (@list_fix A).
(** %\vspace{-.15in}% [[
= fun A : Type =>
fix F (ls : list A) : nat :=
match ls with
| nil => 1
| _ :: ls' => F ls' + 1
end
: forall A : Type, list A -> nat
]]
*)
Definition tree_fix (A : Type) : fixDenote (tree A) (tree_dt A) :=
fun R cases => fix F (t : tree A) : R :=
match t with
| Leaf x => (hhd cases) x INil
| Node t1 t2 => (hhd (htl cases)) tt (ICons (F t1) (ICons (F t2) INil))
end.
Eval cbv beta iota delta -[plus] in fun A => size (@tree_fix A).
(** %\vspace{-.15in}% [[
= fun A : Type =>
fix F (t : tree A) : nat :=
match t with
| Leaf _ => 1
| Node t1 t2 => F t1 + (F t2 + 1)
end
: forall A : Type, tree A -> n
]]
*)
(* end thide *)
(** As our examples show, even recursive datatypes are mapped to normal-looking size functions. *)
(** ** Pretty-Printing *)
(** It is also useful to do generic pretty-printing of datatype values, rendering them as human-readable strings. To do so, we will need a bit of metadata for each constructor. Specifically, we need the name to print for the constructor and the function to use to render its non-recursive arguments. Everything else can be done generically. *)
Record print_constructor (c : constructor) : Type := PI {
printName : string;
printNonrec : nonrecursive c -> string
}.
(** It is useful to define a shorthand for applying the constructor [PI]. By applying it explicitly to an unknown application of the constructor [Con], we help type inference work. *)
Notation "^" := (PI (Con _ _)).
(** As in earlier examples, we define the type of metadata for a datatype to be a heterogeneous list type collecting metadata for each constructor. *)
Definition print_datatype := hlist print_constructor.
(** We will be doing some string manipulation here, so we import the notations associated with strings. *)
Local Open Scope string_scope.
(** Now it is easy to implement our generic printer, using another function from [DepList.] *)
Check hmap.
(** %\vspace{-.15in}% [[
hmap
: forall (A : Type) (B1 B2 : A -> Type),
(forall x : A, B1 x -> B2 x) ->
forall ls : list A, hlist B1 ls -> hlist B2 ls
]]
*)
Definition print T dt (pr : print_datatype dt) (fx : fixDenote T dt) : T -> string :=
fx string (hmap (B1 := print_constructor) (B2 := constructorDenote string)
(fun _ pc x r => printName pc ++ "(" ++ printNonrec pc x
++ foldr (fun s acc => ", " ++ s ++ acc) ")" r) pr).
(** Some simple tests establish that [print] gets the job done. *)
Eval compute in print HNil Empty_set_fix.
(** %\vspace{-.15in}% [[
= fun emp : Empty_set => match emp return string with
end
: Empty_set -> string
]]
*)
Eval compute in print (^ "tt" (fun _ => "") ::: HNil) unit_fix.
(** %\vspace{-.15in}% [[
= fun _ : unit => "tt()"
: unit -> string
]]
*)
Eval compute in print (^ "true" (fun _ => "")
::: ^ "false" (fun _ => "")
::: HNil) bool_fix.
(** %\vspace{-.15in}% [[
= fun b : bool => if b then "true()" else "false()"
: bool -> string
]]
*)
Definition print_nat := print (^ "O" (fun _ => "")
::: ^ "S" (fun _ => "")
::: HNil) nat_fix.
Eval cbv beta iota delta -[append] in print_nat.
(** %\vspace{-.15in}% [[
= fix F (n : nat) : string :=
match n with
| 0%nat => "O" ++ "(" ++ "" ++ ")"
| S n' => "S" ++ "(" ++ "" ++ ", " ++ F n' ++ ")"
end
: nat -> string
]]
*)
Eval simpl in print_nat 0.
(** %\vspace{-.15in}% [[
= "O()"
: string
]]
*)
Eval simpl in print_nat 1.
(** %\vspace{-.15in}% [[
= "S(, O())"
: string
]]
*)
Eval simpl in print_nat 2.
(** %\vspace{-.15in}% [[
= "S(, S(, O()))"
: string
]]
*)
Eval cbv beta iota delta -[append] in fun A (pr : A -> string) =>
print (^ "nil" (fun _ => "")
::: ^ "cons" pr
::: HNil) (@list_fix A).
(** %\vspace{-.15in}% [[
= fun (A : Type) (pr : A -> string) =>
fix F (ls : list A) : string :=
match ls with
| nil => "nil" ++ "(" ++ "" ++ ")"
| x :: ls' => "cons" ++ "(" ++ pr x ++ ", " ++ F ls' ++ ")"
end
: forall A : Type, (A -> string) -> list A -> string
]]
*)
Eval cbv beta iota delta -[append] in fun A (pr : A -> string) =>
print (^ "Leaf" pr
::: ^ "Node" (fun _ => "")
::: HNil) (@tree_fix A).
(** %\vspace{-.15in}% [[
= fun (A : Type) (pr : A -> string) =>
fix F (t : tree A) : string :=
match t with
| Leaf x => "Leaf" ++ "(" ++ pr x ++ ")"
| Node t1 t2 =>
"Node" ++ "(" ++ "" ++ ", " ++ F t1 ++ ", " ++ F t2 ++ ")"
end
: forall A : Type, (A -> string) -> tree A -> string
]]
*)
(* begin hide *)
(* begin thide *)
Definition append' := append.
(* end thide *)
(* end hide *)
(** Some of these simplified terms seem overly complex because we have turned off simplification of calls to [append], which is what uses of the [++] operator desugar to. Selective [++] simplification would combine adjacent string literals, yielding more or less the code we would write manually to implement this printing scheme. *)
(** ** Mapping *)
(** By this point, we have developed enough machinery that it is old hat to define a generic function similar to the list [map] function. *)
Definition map T dt (dd : datatypeDenote T dt) (fx : fixDenote T dt) (f : T -> T)
: T -> T :=
fx T (hmap (B1 := constructorDenote T) (B2 := constructorDenote T)
(fun _ c x r => f (c x r)) dd).
Eval compute in map Empty_set_den Empty_set_fix.
(** %\vspace{-.15in}% [[
= fun (_ : Empty_set -> Empty_set) (emp : Empty_set) =>
match emp return Empty_set with
end
: (Empty_set -> Empty_set) -> Empty_set -> Empty_set
]]
*)
Eval compute in map unit_den unit_fix.
(** %\vspace{-.15in}% [[
= fun (f : unit -> unit) (_ : unit) => f tt
: (unit -> unit) -> unit -> unit
]]
*)
Eval compute in map bool_den bool_fix.
(** %\vspace{-.15in}% [[
= fun (f : bool -> bool) (b : bool) => if b then f true else f false
: (bool -> bool) -> bool -> bool
]]
*)
Eval compute in map nat_den nat_fix.
(** %\vspace{-.15in}% [[
= fun f : nat -> nat =>
fix F (n : nat) : nat :=
match n with
| 0%nat => f 0%nat
| S n' => f (S (F n'))
end
: (nat -> nat) -> nat -> nat
]]
*)
Eval compute in fun A => map (list_den A) (@list_fix A).
(** %\vspace{-.15in}% [[
= fun (A : Type) (f : list A -> list A) =>
fix F (ls : list A) : list A :=
match ls with
| nil => f nil
| x :: ls' => f (x :: F ls')
end
: forall A : Type, (list A -> list A) -> list A -> list A
]]
*)
Eval compute in fun A => map (tree_den A) (@tree_fix A).
(** %\vspace{-.15in}% [[
= fun (A : Type) (f : tree A -> tree A) =>
fix F (t : tree A) : tree A :=
match t with
| Leaf x => f (Leaf x)
| Node t1 t2 => f (Node (F t1) (F t2))
end
: forall A : Type, (tree A -> tree A) -> tree A -> tree A
]]
*)
(** These [map] functions are just as easy to use as those we write by hand. Can you figure out the input-output pattern that [map_nat S] displays in these examples? *)
Definition map_nat := map nat_den nat_fix.
Eval simpl in map_nat S 0.
(** %\vspace{-.15in}% [[
= 1%nat
: nat
]]
*)
Eval simpl in map_nat S 1.
(** %\vspace{-.15in}% [[
= 3%nat
: nat
]]
*)
Eval simpl in map_nat S 2.
(** %\vspace{-.15in}% [[
= 5%nat
: nat
]]
*)
(** We get [map_nat S n] = [2 * n + 1], because the mapping process adds an extra [S] at every level of the inductive tree that defines a natural, including at the last level, the [O] constructor. *)
(** * Proving Theorems about Recursive Definitions *)
(** We would like to be able to prove theorems about our generic functions. To do so, we need to establish additional well-formedness properties that must hold of pieces of evidence. *)
Section ok.
Variable T : Type.
Variable dt : datatype.
Variable dd : datatypeDenote T dt.
Variable fx : fixDenote T dt.
(** First, we characterize when a piece of evidence about a datatype is acceptable. The basic idea is that the type [T] should really be an inductive type with the definition given by [dd]. Semantically, inductive types are characterized by the ability to do induction on them. Therefore, we require that the usual induction principle is true, with respect to the constructors given in the encoding [dd]. *)
Definition datatypeDenoteOk :=
forall P : T -> Prop,
(forall c (m : member c dt) (x : nonrecursive c) (r : ilist T (recursive c)),
(forall i : fin (recursive c), P (get r i))
-> P ((hget dd m) x r))
-> forall v, P v.
(** This definition can take a while to digest. The quantifier over [m : member c dt] is considering each constructor in turn; like in normal induction principles, each constructor has an associated proof case. The expression [hget dd m] then names the constructor we have selected. After binding [m], we quantify over all possible arguments (encoded with [x] and [r]) to the constructor that [m] selects. Within each specific case, we quantify further over [i : fin (recursive c)] to consider all of our induction hypotheses, one for each recursive argument of the current constructor.
We have completed half the burden of defining side conditions. The other half comes in characterizing when a recursion scheme [fx] is valid. The natural condition is that [fx] behaves appropriately when applied to any constructor application. *)
Definition fixDenoteOk :=
forall (R : Type) (cases : datatypeDenote R dt)
c (m : member c dt)
(x : nonrecursive c) (r : ilist T (recursive c)),
fx cases ((hget dd m) x r)
= (hget cases m) x (imap (fx cases) r).
(** As for [datatypeDenoteOk], we consider all constructors and all possible arguments to them by quantifying over [m], [x], and [r]. The lefthand side of the equality that follows shows a call to the recursive function on the specific constructor application that we selected. The righthand side shows an application of the function case associated with constructor [m], applied to the non-recursive arguments and to appropriate recursive calls on the recursive arguments. *)
End ok.
(** We are now ready to prove that the [size] function we defined earlier always returns positive results. First, we establish a simple lemma. *)
(* begin thide *)
Lemma foldr_plus : forall n (ils : ilist nat n),
foldr plus 1 ils > 0.
induction ils; crush.
Qed.
(* end thide *)
Theorem size_positive : forall T dt
(dd : datatypeDenote T dt) (fx : fixDenote T dt)
(dok : datatypeDenoteOk dd) (fok : fixDenoteOk dd fx)
(v : T),
size fx v > 0.
(* begin thide *)
unfold size; intros.
(** [[
============================
fx nat
(hmake
(fun (x : constructor) (_ : nonrecursive x)
(r : ilist nat (recursive x)) => foldr plus 1%nat r) dt) v > 0
]]
Our goal is an inequality over a particular call to [size], with its definition expanded. How can we proceed here? We cannot use [induction] directly, because there is no way for Coq to know that [T] is an inductive type. Instead, we need to use the induction principle encoded in our hypothesis [dok] of type [datatypeDenoteOk dd]. Let us try applying it directly.
[[
apply dok.
]]
%\vspace{-.3in}%
<<
Error: Impossible to unify "datatypeDenoteOk dd" with
"fx nat
(hmake
(fun (x : constructor) (_ : nonrecursive x)
(r : ilist nat (recursive x)) => foldr plus 1%nat r) dt) v > 0".
>>
Matching the type of [dok] with the type of our conclusion requires more than simple first-order unification, so [apply] is not up to the challenge. We can use the %\index{tactics!pattern}%[pattern] tactic to get our goal into a form that makes it apparent exactly what the induction hypothesis is. *)
pattern v.
(** %\vspace{-.15in}%[[
============================
(fun t : T =>
fx nat
(hmake
(fun (x : constructor) (_ : nonrecursive x)
(r : ilist nat (recursive x)) => foldr plus 1%nat r) dt) t > 0) v
]]
*)
apply dok; crush.
(** %\vspace{-.15in}%[[
H : forall i : fin (recursive c),
fx nat
(hmake
(fun (x : constructor) (_ : nonrecursive x)
(r : ilist nat (recursive x)) => foldr plus 1%nat r) dt)
(get r i) > 0
============================
hget
(hmake
(fun (x0 : constructor) (_ : nonrecursive x0)
(r0 : ilist nat (recursive x0)) => foldr plus 1%nat r0) dt) m x
(imap
(fx nat
(hmake
(fun (x0 : constructor) (_ : nonrecursive x0)
(r0 : ilist nat (recursive x0)) =>
foldr plus 1%nat r0) dt)) r) > 0
]]
An induction hypothesis [H] is generated, but we turn out not to need it for this example. We can simplify the goal using a library theorem about the composition of [hget] and [hmake]. *)
rewrite hget_hmake.
(** %\vspace{-.15in}%[[
============================
foldr plus 1%nat
(imap
(fx nat
(hmake
(fun (x0 : constructor) (_ : nonrecursive x0)
(r0 : ilist nat (recursive x0)) =>
foldr plus 1%nat r0) dt)) r) > 0
]]
The lemma we proved earlier finishes the proof. *)
apply foldr_plus.
(** Using hints, we can redo this proof in a nice automated form. *)
Restart.
Hint Rewrite hget_hmake.
Hint Resolve foldr_plus.
unfold size; intros; pattern v; apply dok; crush.
Qed.
(* end thide *)
(** It turned out that, in this example, we only needed to use induction degenerately as case analysis. A more involved theorem may only be proved using induction hypotheses. We will give its proof only in unautomated form and leave effective automation as an exercise for the motivated reader.
In particular, it ought to be the case that generic [map] applied to an identity function is itself an identity function. *)
Theorem map_id : forall T dt
(dd : datatypeDenote T dt) (fx : fixDenote T dt)
(dok : datatypeDenoteOk dd) (fok : fixDenoteOk dd fx)
(v : T),
map dd fx (fun x => x) v = v.
(* begin thide *)
(** Let us begin as we did in the last theorem, after adding another useful library equality as a hint. *)
Hint Rewrite hget_hmap.
unfold map; intros; pattern v; apply dok; crush.
(** %\vspace{-.15in}%[[
H : forall i : fin (recursive c),
fx T
(hmap
(fun (x : constructor) (c : constructorDenote T x)
(x0 : nonrecursive x) (r : ilist T (recursive x)) =>
c x0 r) dd) (get r i) = get r i
============================
hget dd m x
(imap
(fx T
(hmap
(fun (x0 : constructor) (c0 : constructorDenote T x0)
(x1 : nonrecursive x0) (r0 : ilist T (recursive x0)) =>
c0 x1 r0) dd)) r) = hget dd m x r
]]
Our goal is an equality whose two sides begin with the same function call and initial arguments. We believe that the remaining arguments are in fact equal as well, and the [f_equal] tactic applies this reasoning step for us formally. *)
f_equal.
(** %\vspace{-.15in}%[[
============================
imap
(fx T
(hmap
(fun (x0 : constructor) (c0 : constructorDenote T x0)
(x1 : nonrecursive x0) (r0 : ilist T (recursive x0)) =>
c0 x1 r0) dd)) r = r
]]
At this point, it is helpful to proceed by an inner induction on the heterogeneous list [r] of recursive call results. We could arrive at a cleaner proof by breaking this step out into an explicit lemma, but here we will do the induction inline to save space.*)
induction r; crush.
(* begin hide *)
(* begin thide *)
Definition pred' := pred.
(* end thide *)
(* end hide *)
(** The base case is discharged automatically, and the inductive case looks like this, where [H] is the outer IH (for induction over [T] values) and [IHr] is the inner IH (for induction over the recursive arguments).
[[
H : forall i : fin (S n),
fx T
(hmap
(fun (x : constructor) (c : constructorDenote T x)
(x0 : nonrecursive x) (r : ilist T (recursive x)) =>
c x0 r) dd)
(match i in (fin n') return ((fin (pred n') -> T) -> T) with
| First n => fun _ : fin n -> T => a
| Next n idx' => fun get_ls' : fin n -> T => get_ls' idx'
end (get r)) =
match i in (fin n') return ((fin (pred n') -> T) -> T) with
| First n => fun _ : fin n -> T => a
| Next n idx' => fun get_ls' : fin n -> T => get_ls' idx'
end (get r)
IHr : (forall i : fin n,
fx T
(hmap
(fun (x : constructor) (c : constructorDenote T x)
(x0 : nonrecursive x) (r : ilist T (recursive x)) =>
c x0 r) dd) (get r i) = get r i) ->
imap
(fx T
(hmap
(fun (x : constructor) (c : constructorDenote T x)
(x0 : nonrecursive x) (r : ilist T (recursive x)) =>
c x0 r) dd)) r = r
============================
ICons
(fx T
(hmap
(fun (x0 : constructor) (c0 : constructorDenote T x0)
(x1 : nonrecursive x0) (r0 : ilist T (recursive x0)) =>
c0 x1 r0) dd) a)
(imap
(fx T
(hmap
(fun (x0 : constructor) (c0 : constructorDenote T x0)
(x1 : nonrecursive x0) (r0 : ilist T (recursive x0)) =>
c0 x1 r0) dd)) r) = ICons a r
]]
We see another opportunity to apply [f_equal], this time to split our goal into two different equalities over corresponding arguments. After that, the form of the first goal matches our outer induction hypothesis [H], when we give type inference some help by specifying the right quantifier instantiation. *)
f_equal.
apply (H First).
(** %\vspace{-.15in}%[[
============================
imap
(fx T
(hmap
(fun (x0 : constructor) (c0 : constructorDenote T x0)
(x1 : nonrecursive x0) (r0 : ilist T (recursive x0)) =>
c0 x1 r0) dd)) r = r
]]
Now the goal matches the inner IH [IHr]. *)
apply IHr; crush.
(** %\vspace{-.15in}%[[
i : fin n
============================
fx T
(hmap
(fun (x0 : constructor) (c0 : constructorDenote T x0)
(x1 : nonrecursive x0) (r0 : ilist T (recursive x0)) =>
c0 x1 r0) dd) (get r i) = get r i
]]
We can finish the proof by applying the outer IH again, specialized to a different [fin] value. *)
apply (H (Next i)).
Qed.
(* end thide *)
(** The proof involves complex subgoals, but, still, few steps are required, and then we may reuse our work across a variety of datatypes. *)
|
`include "bsg_cache.vh"
module testbench();
import bsg_cache_pkg::*;
// clock/reset
bit clk;
bit reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(20)
) cg (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(0)
,.reset_cycles_hi_p(10)
) rg (
.clk_i(clk)
,.async_reset_o(reset)
);
// parameters
localparam addr_width_p = 30;
localparam data_width_p = 32;
localparam block_size_in_words_p = 8;
localparam sets_p = 128;
localparam ways_p = 8;
localparam mem_size_p = block_size_in_words_p*sets_p*ways_p*4;
integer status;
integer wave;
string checker;
initial begin
status = $value$plusargs("wave=%d",wave);
status = $value$plusargs("checker=%s",checker);
$display("checker=%s", checker);
if (wave) $vcdpluson;
end
`declare_bsg_cache_pkt_s(addr_width_p,data_width_p);
`declare_bsg_cache_dma_pkt_s(addr_width_p);
bsg_cache_pkt_s cache_pkt;
logic v_li;
logic ready_lo;
logic [data_width_p-1:0] cache_data_lo;
logic v_lo;
logic yumi_li;
bsg_cache_dma_pkt_s dma_pkt;
logic dma_pkt_v_lo;
logic dma_pkt_yumi_li;
logic [data_width_p-1:0] dma_data_li;
logic dma_data_v_li;
logic dma_data_ready_lo;
logic [data_width_p-1:0] dma_data_lo;
logic dma_data_v_lo;
logic dma_data_yumi_li;
// DUT
bsg_cache #(
.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.sets_p(sets_p)
,.ways_p(ways_p)
,.amo_support_p(amo_support_level_arithmetic_lp)
) DUT (
.clk_i(clk)
,.reset_i(reset)
,.cache_pkt_i(cache_pkt)
,.v_i(v_li)
,.ready_o(ready_lo)
,.data_o(cache_data_lo)
,.v_o(v_lo)
,.yumi_i(yumi_li)
,.dma_pkt_o(dma_pkt)
,.dma_pkt_v_o(dma_pkt_v_lo)
,.dma_pkt_yumi_i(dma_pkt_yumi_li)
,.dma_data_i(dma_data_li)
,.dma_data_v_i(dma_data_v_li)
,.dma_data_ready_o(dma_data_ready_lo)
,.dma_data_o(dma_data_lo)
,.dma_data_v_o(dma_data_v_lo)
,.dma_data_yumi_i(dma_data_yumi_li)
,.v_we_o()
);
// random yumi generator
bsg_nonsynth_random_yumi_gen #(
.yumi_min_delay_p(`YUMI_MIN_DELAY_P)
,.yumi_max_delay_p(`YUMI_MAX_DELAY_P)
) yumi_gen (
.clk_i(clk)
,.reset_i(reset)
,.v_i(v_lo)
,.yumi_o(yumi_li)
);
// DMA model
bsg_nonsynth_dma_model #(
.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.els_p(mem_size_p)
,.read_delay_p(`DMA_READ_DELAY_P)
,.write_delay_p(`DMA_WRITE_DELAY_P)
,.dma_req_delay_p(`DMA_REQ_DELAY_P)
,.dma_data_delay_p(`DMA_DATA_DELAY_P)
) dma0 (
.clk_i(clk)
,.reset_i(reset)
,.dma_pkt_i(dma_pkt)
,.dma_pkt_v_i(dma_pkt_v_lo)
,.dma_pkt_yumi_o(dma_pkt_yumi_li)
,.dma_data_o(dma_data_li)
,.dma_data_v_o(dma_data_v_li)
,.dma_data_ready_i(dma_data_ready_lo)
,.dma_data_i(dma_data_lo)
,.dma_data_v_i(dma_data_v_lo)
,.dma_data_yumi_o(dma_data_yumi_li)
);
// trace replay
localparam rom_addr_width_lp = 26;
localparam ring_width_lp = `bsg_cache_pkt_width(addr_width_p,data_width_p);
logic [rom_addr_width_lp-1:0] trace_rom_addr;
logic [ring_width_lp+4-1:0] trace_rom_data;
logic tr_v_lo;
logic [ring_width_lp-1:0] tr_data_lo;
logic tr_yumi_li;
logic done;
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_lp)
,.rom_addr_width_p(rom_addr_width_lp)
) trace_replay (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(1'b0)
,.data_i('0)
,.ready_o()
,.v_o(tr_v_lo)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(trace_rom_addr)
,.rom_data_i(trace_rom_data)
,.done_o(done)
,.error_o()
);
bsg_nonsynth_test_rom #(
.filename_p("trace.tr")
,.data_width_p(ring_width_lp+4)
,.addr_width_p(rom_addr_width_lp)
) trom (
.addr_i(trace_rom_addr)
,.data_o(trace_rom_data)
);
assign cache_pkt = tr_data_lo;
assign v_li = tr_v_lo;
assign tr_yumi_li = tr_v_lo & ready_lo;
bind bsg_cache basic_checker_32 #(
.data_width_p(data_width_p)
,.addr_width_p(addr_width_p)
,.mem_size_p($root.testbench.mem_size_p)
) bc (
.*
,.en_i($root.testbench.checker == "basic")
);
// wait for all responses to be received.
integer sent_r, recv_r;
always_ff @ (posedge clk) begin
if (reset) begin
sent_r <= '0;
recv_r <= '0;
end
else begin
if (v_li & ready_lo)
sent_r <= sent_r + 1;
if (v_lo & yumi_li)
recv_r <= recv_r + 1;
end
end
initial begin
wait(done & (sent_r == recv_r));
$display("[BSG_FINISH] Test Successful.");
#500;
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFXTP_TB_V
`define SKY130_FD_SC_HDLL__SDFXTP_TB_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfxtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hdll__sdfxtp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFXTP_TB_V
|
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
`default_nettype none
module nukv_Top_Module_v2 #(
parameter META_WIDTH = 96,
parameter VALUE_WIDTH = 512,
parameter MEMORY_WIDTH = 512,
parameter KEY_WIDTH = 128,
parameter HEADER_WIDTH = 42,
parameter HASHTABLE_MEM_SIZE = 24,
parameter VALUESTORE_MEM_SIZE = 25,
parameter SUPPORT_SCANS = 1,
parameter DECOMPRESS_ENGINES = 0,
parameter CONDITION_EVALS = 4,
parameter REGEX_ENABLED = 1,
parameter IS_SIM = 0
)(
// Clock
input wire clk,
input wire rst,
// Memcached Request Input
input wire [127:0] s_axis_tdata,
input wire s_axis_tvalid,
input wire s_axis_tlast,
output wire s_axis_tready,
// Memcached Response Output
output wire [127:0] m_axis_tdata,
output wire m_axis_tvalid,
output wire m_axis_tlast,
input wire m_axis_tready,
// HashTable DRAM Connection
// ht_rd: Pull Input, 1536b
input wire [511:0] ht_rd_data,
input wire ht_rd_empty,
input wire ht_rd_almost_empty,
output wire ht_rd_read,
// ht_rd_cmd: Push Output, 10b
output wire [63:0] ht_rd_cmd_data,
output wire ht_rd_cmd_valid,
input wire ht_rd_cmd_stall,
// ht_wr: Push Output, 1536b
output wire [511:0] ht_wr_data,
output wire ht_wr_valid,
input wire ht_wr_stall,
// ht_wr_cmd: Push Output, 10b
output wire [63:0] ht_wr_cmd_data,
output wire ht_wr_cmd_valid,
input wire ht_wr_cmd_stall,
// Update DRAM Connection
// upd_rd: Pull Input, 1536b
input wire [MEMORY_WIDTH-1:0] upd_rd_data,
input wire upd_rd_empty,
input wire upd_rd_almost_empty,
output wire upd_rd_read,
// upd_rd_cmd: Push Output, 10b
output wire [63:0] upd_rd_cmd_data,
output wire upd_rd_cmd_valid,
input wire upd_rd_cmd_stall,
// upd_wr: Push Output, 1536b
output wire [511:0] upd_wr_data,
output wire upd_wr_valid,
input wire upd_wr_stall,
// upd_wr_cmd: Push Output, 10b
output wire [63:0] upd_wr_cmd_data,
output wire upd_wr_cmd_valid,
input wire upd_wr_cmd_stall,
output wire [63:0] p_rdcmd_data,
output wire p_rdcmd_valid,
input wire p_rdcmd_ready,
input wire [512-1:0] p_rd_data,
input wire p_rd_valid,
output wire p_rd_ready,
output wire [512-1:0] p_wr_data,
output wire p_wr_valid,
input wire p_wr_ready,
output wire [63:0] p_wrcmd_data,
output wire p_wrcmd_valid,
input wire p_wrcmd_ready,
output wire [63:0] b_rdcmd_data,
output wire b_rdcmd_valid,
input wire b_rdcmd_ready,
input wire [512-1:0] b_rd_data,
input wire b_rd_valid,
output wire b_rd_ready,
output wire [512-1:0] b_wr_data,
output wire b_wr_valid,
input wire b_wr_ready,
output wire [63:0] b_wrcmd_data,
output wire b_wrcmd_valid,
input wire b_wrcmd_ready,
output wire [7:0] debug
);
wire [31:0] rdcmd_data;
wire rdcmd_valid;
wire rdcmd_stall;
wire rdcmd_ready;
wire [31:0] wrcmd_data;
wire wrcmd_valid;
wire wrcmd_stall;
wire wrcmd_ready;
wire [39:0] upd_rdcmd_data;
wire upd_rdcmd_ready;
wire [39:0] upd_wrcmd_data;
wire upd_wrcmd_ready;
wire [15:0] mreq_data;
wire mreq_valid;
wire mreq_ready;
wire [15:0] mreq_data_b;
wire mreq_valid_b;
wire mreq_ready_b;
wire [31:0] malloc_data;
wire malloc_valid;
wire malloc_failed;
wire malloc_ready;
wire [31:0] free_data;
wire [15:0] free_size;
wire free_valid;
wire free_ready;
wire free_wipe;
wire [31:0] malloc_data_b;
wire [31+1:0] malloc_data_full_b;
wire malloc_valid_b;
wire malloc_failed_b;
wire malloc_ready_b;
wire [31+16+1:0] free_data_full_b;
wire [31:0] free_data_b;
wire [15:0] free_size_b;
wire free_valid_b;
wire free_ready_b;
wire free_wipe_b;
wire [63:0] key_data;
wire key_last;
wire key_valid;
wire key_ready;
wire [META_WIDTH-1:0] meta_data;
wire meta_valid;
wire meta_ready;
wire [1+63:0] tohash_data;
wire tohash_valid;
wire tohash_ready;
wire [31:0] fromhash_data;
wire fromhash_valid;
wire fromhash_ready;
wire [63:0] hash_one_data;
wire hash_one_valid;
wire hash_one_ready;
wire[31:0] secondhash_data;
wire secondhash_valid;
wire secondhash_ready;
wire[63:0] hash_two_data;
wire hash_two_valid;
wire hash_two_ready;
reg [KEY_WIDTH-1:0] widekey_assembly;
reg [KEY_WIDTH-1:0] widekey_data;
reg widekey_valid;
wire widekey_ready;
wire [KEY_WIDTH-1:0] widekey_b_data;
wire widekey_b_valid;
wire widekey_b_ready;
wire [META_WIDTH-1:0] meta_b_data;
wire meta_b_valid;
wire meta_b_ready;
wire [KEY_WIDTH+META_WIDTH+64-1:0] keywhash_data;
wire keywhash_valid;
wire keywhash_ready;
wire [KEY_WIDTH+META_WIDTH+64-1:0] towrite_b_data;
wire towrite_b_valid;
wire towrite_b_ready;
wire [KEY_WIDTH+META_WIDTH+64-1:0] writeout_data;
wire writeout_valid;
wire writeout_ready;
wire [KEY_WIDTH+META_WIDTH+HEADER_WIDTH-1:0] writeout_b_data;
wire writeout_b_valid;
wire writeout_b_ready;
wire [KEY_WIDTH+META_WIDTH+HEADER_WIDTH-1:0] fromset_data;
wire fromset_valid;
wire fromset_ready;
wire [KEY_WIDTH+META_WIDTH+HEADER_WIDTH-1:0] fromset_b_data;
wire fromset_b_valid;
wire fromset_b_ready;
wire [KEY_WIDTH+META_WIDTH+64-1:0] towrite_data;
wire towrite_valid;
wire towrite_ready;
wire [KEY_WIDTH+META_WIDTH+64-1:0] writefb_data;
wire writefb_valid;
wire writefb_ready;
wire [KEY_WIDTH+META_WIDTH+64-1:0] writefb_b_data;
wire writefb_b_valid;
wire writefb_b_ready;
wire [KEY_WIDTH+META_WIDTH+64-1:0] feedbwhash_data;
wire feedbwhash_valid;
wire feedbwhash_ready;
wire [VALUE_WIDTH-1:0] value_data;
wire [15:0] value_length;
wire value_last;
wire value_valid;
wire value_ready;
wire value_almost_full;
wire [VALUE_WIDTH+16+1-1:0] value_b_data;
wire [15:0] value_b_length;
wire value_b_last;
wire value_b_valid;
wire value_b_ready;
wire[VALUE_WIDTH-1:0] value_read_data;
wire value_read_valid;
wire value_read_last;
wire value_read_ready;
wire [63:0] setter_rdcmd_data;
wire setter_rdcmd_valid;
wire setter_rdcmd_ready;
wire [63:0] scan_rdcmd_data;
wire scan_rdcmd_valid;
wire scan_rdcmd_ready;
wire scan_kickoff;
wire scan_reading;
reg scan_mode_on;
reg rst_regex_after_scan;
wire [31:0] scan_readsissued;
reg [31:0] scan_readsprocessed;
wire scan_valid;
wire[31:0] scan_addr;
wire[7:0] scan_cnt;
wire scan_ready;
wire pe_cmd_ready;
wire pe_cmd_valid;
wire[15:0] pe_cmd_data;
wire[95:0] pe_cmd_meta;
wire [511:0] value_frompred_data;
wire value_frompred_ready;
wire value_frompred_valid;
wire value_frompred_drop;
wire value_frompred_last;
wire [511:0] value_frompipe_data;
wire value_frompipe_ready;
wire value_frompipe_valid;
wire value_frompipe_drop;
wire value_frompipe_last;
wire [511:0] value_frompred_b_data;
wire value_frompred_b_ready;
wire value_frompred_b_valid;
wire value_read_almostfull_int;
reg scan_pause;
wire sh_in_buf_ready;
wire sh_in_ready;
wire sh_in_valid;
wire sh_in_choice;
wire[63:0] sh_in_data;
wire hash_two_in_ready;
wire write_feedback_channel_ready;
reg[31:0] input_counter;
wire[127:0] input_buf_data;
wire input_buf_last;
wire input_buf_valid;
wire input_buf_ready;
wire clk_faster; // 2*156MHz Clock for regex
wire clkout0;
wire fbclk;
wire fclk_locked;
reg frst = 1;
reg rst_faster = 1;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(10), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(6.400), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
.CLKOUT0_DIVIDE(5),
.CLKOUT1_DIVIDE(1),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.DIVCLK_DIVIDE(1), // Master division value, (1-56)
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
PLLE2_BASE_inst (
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
.CLKOUT0(clk_faster), // 1-bit output: CLKOUT0
.CLKOUT1(), // 1-bit output: CLKOUT1
.CLKOUT2(), // 1-bit output: CLKOUT2
.CLKOUT3(), // 1-bit output: CLKOUT3
.CLKOUT4(), // 1-bit output: CLKOUT4
.CLKOUT5(), // 1-bit output: CLKOUT5
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
.CLKFBOUT(fbclk), // 1-bit output: Feedback clock
.LOCKED(fclk_locked), // 1-bit output: LOCK
.CLKIN1(clk), // 1-bit input: Input clock
// Control Ports: 1-bit (each) input: PLL control ports
.PWRDWN(1'b0), // 1-bit input: Power-down
.RST(1'b0), // 1-bit input: Reset
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
.CLKFBIN(fbclk) // 1-bit input: Feedback clock
);
reg rst_regd;
always @(posedge clk) begin
rst_regd <= rst;
end
reg rst_faster0;
always @(posedge clk_faster) begin
frst <= rst_regd;
rst_faster0 <= frst | ~fclk_locked;
rst_faster <= rst_faster0;
end
nukv_fifogen #(
.DATA_SIZE(129),
.ADDR_BITS(8)
) fifo_inputbuf (
.clk(clk),
.rst(rst),
.s_axis_tdata({s_axis_tdata,s_axis_tlast}),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.m_axis_tdata({input_buf_data,input_buf_last}),
.m_axis_tvalid(input_buf_valid),
.m_axis_tready(input_buf_ready)
);
nukv_RequestSplit #(
.SPECIAL_ARE_UPDATES(0)
)
splitter
(
.clk(clk),
.rst(rst),
.s_axis_tdata(input_buf_data),
.s_axis_tvalid(input_buf_valid),
.s_axis_tready(input_buf_ready),
.s_axis_tlast(input_buf_last),
.key_data(key_data),
.key_valid(key_valid),
.key_last(key_last),
.key_ready(key_ready),
.meta_data(meta_data),
.meta_valid(meta_valid),
.meta_ready(meta_ready),
.value_data(value_data),
.value_valid(value_valid),
.value_length(value_length),
.value_last(value_last),
.value_ready(value_ready),
.value_almost_full(value_almost_full),
.malloc_data(),
.malloc_valid(),
.malloc_ready(1'b1),
._debug()
);
nukv_fifogen #(
.DATA_SIZE(VALUE_WIDTH+16+1),
.ADDR_BITS(10)
) fifo_value (
.clk(clk),
.rst(rst),
.s_axis_tdata({value_last, value_length, value_data}),
.s_axis_tvalid(value_valid),
.s_axis_tready(value_ready),
.s_axis_talmostfull(value_almost_full),
.m_axis_tdata(value_b_data),
.m_axis_tvalid(value_b_valid),
.m_axis_tready(value_b_ready)
);
assign value_b_length = value_b_data[VALUE_WIDTH +: 16];
assign value_b_last = value_b_data[VALUE_WIDTH+16];
nukv_fifogen #(
.DATA_SIZE(META_WIDTH),
.ADDR_BITS(8)
) fifo_meta_delayer (
.clk(clk),
.rst(rst),
.s_axis_tdata(meta_data),
.s_axis_tvalid(meta_valid),
.s_axis_tready(meta_ready),
.m_axis_tdata(meta_b_data),
.m_axis_tvalid(meta_b_valid),
.m_axis_tready(meta_b_ready)
);
wire hash_one_in_ready;
assign key_ready = hash_one_in_ready & widekey_ready;
kvs_ht_Hash_v2 #(
.MEMORY_WIDTH(HASHTABLE_MEM_SIZE)
) hash_number_one (
.clk(clk),
.rst(rst),
.in_valid(key_valid & widekey_ready),
.in_ready(hash_one_in_ready),
.in_data(key_data),
.in_last(key_last),
.out_valid(hash_one_valid),
.out_ready(hash_one_ready | ~hash_one_valid),
.out_data1(hash_one_data[31:0]),
.out_data2(hash_one_data[63:32])
);
always @(posedge clk) begin
if (rst) begin
widekey_data <= 0;
widekey_assembly <= 0;
widekey_valid <= 0;
end
else begin
if (widekey_valid==1 && widekey_ready==1) begin
widekey_valid <= 0;
end
if (widekey_valid==0 && widekey_ready==1 && key_valid==1 && hash_one_in_ready==1) begin
if (widekey_assembly==0) begin
widekey_assembly[63:0] <= key_data;
end else begin
widekey_assembly <= {widekey_assembly[KEY_WIDTH-64-1:0],key_data};
end
if (key_last==1) begin
widekey_data <= {widekey_assembly[KEY_WIDTH-64-1:0],key_data};
widekey_valid <= 1;
widekey_assembly <= 0;
end
end
end
end
nukv_fifogen #(
.DATA_SIZE(KEY_WIDTH),
.ADDR_BITS(6)
) fifo_widekey_delayer (
.clk(clk),
.rst(rst),
.s_axis_tdata(widekey_data),
.s_axis_tvalid(widekey_valid),
.s_axis_tready(widekey_ready),
.m_axis_tdata(widekey_b_data),
.m_axis_tvalid(widekey_b_valid),
.m_axis_tready(widekey_b_ready)
);
assign keywhash_valid = widekey_b_valid & hash_one_valid & meta_b_valid;
assign widekey_b_ready = keywhash_ready & keywhash_valid ;
assign hash_one_ready = keywhash_ready & keywhash_valid;
assign meta_b_ready = keywhash_ready & keywhash_valid;
assign keywhash_data = {hash_one_data,meta_b_data,widekey_b_data};
kvs_ht_Hash_v2 #(
.MEMORY_WIDTH(HASHTABLE_MEM_SIZE)
) hash_number_two (
.clk(clk),
.rst(rst),
.in_valid(writefb_valid & write_feedback_channel_ready),
.in_ready(hash_two_in_ready),
.in_data(writefb_data[63:0]),
.in_last(1'b1),
.out_valid(hash_two_valid),
.out_ready(hash_two_ready | ~hash_two_valid),
.out_data1(hash_two_data[31:0]),
.out_data2(hash_two_data[63:32])
);
assign feedbwhash_data = {hash_two_data, writefb_b_data[KEY_WIDTH+META_WIDTH-1:0]};
assign feedbwhash_valid = writefb_b_valid & hash_two_valid;
assign hash_two_ready = feedbwhash_ready & feedbwhash_valid;
assign writefb_b_ready = feedbwhash_ready & feedbwhash_valid;
nukv_HT_Read_v2 #(
.MEMADDR_WIDTH(HASHTABLE_MEM_SIZE)
)
readmodule
(
.clk(clk),
.rst(rst),
.input_data(keywhash_data),
.input_valid(keywhash_valid),
.input_ready(keywhash_ready),
.feedback_data(feedbwhash_data),
.feedback_valid(feedbwhash_valid),
.feedback_ready(feedbwhash_ready),
.output_data(towrite_data),
.output_valid(towrite_valid),
.output_ready(towrite_ready),
.rdcmd_data(rdcmd_data),
.rdcmd_valid(rdcmd_valid),
.rdcmd_ready(rdcmd_ready)
);
wire[VALUE_WIDTH-1:0] ht_buf_rd_data;
wire ht_buf_rd_ready;
wire ht_buf_rd_valid;
wire ht_rd_ready;
wire ht_rd_almostfull;
wire ht_rd_isvalid;
assign ht_rd_read = ~ht_rd_almostfull & ht_rd_ready & ~ht_rd_empty;
assign ht_rd_isvalid = ~ht_rd_empty & ht_rd_read;
wire[VALUE_WIDTH-1:0] ht_read_data_int;
wire ht_read_valid_int;
wire ht_read_ready_int;
nukv_fifogen #(
.DATA_SIZE(VALUE_WIDTH),
.ADDR_BITS(7)
) fifo_ht_rd (
.clk(clk),
.rst(rst),
.s_axis_tdata(ht_rd_data),
.s_axis_tvalid(ht_rd_isvalid),
.s_axis_tready(ht_rd_ready),
.s_axis_talmostfull(ht_rd_almostfull),
.m_axis_tdata(ht_buf_rd_data),
.m_axis_tvalid(ht_buf_rd_valid),
.m_axis_tready(ht_buf_rd_ready)
//.m_axis_tdata(ht_read_data_int),
//.m_axis_tvalid(ht_read_valid_int),
//.m_axis_tready(ht_read_ready_int)
);
/*
nukv_fifogen #(
.DATA_SIZE(VALUE_WIDTH),
.ADDR_BITS(6)
) fifo_ht_rd2 (
.clk(clk),
.rst(rst),
.s_axis_tdata(ht_read_data_int),
.s_axis_tvalid(ht_read_valid_int),
.s_axis_tready(ht_read_ready_int),
.m_axis_tdata(ht_buf_rd_data),
.m_axis_tvalid(ht_buf_rd_valid),
.m_axis_tready(ht_buf_rd_ready)
);
*/
nukv_fifogen #(
.DATA_SIZE(KEY_WIDTH+META_WIDTH+64),
.ADDR_BITS(6)
) fifo_towrite_delayer (
.clk(clk),
.rst(rst),
.s_axis_tdata(towrite_data),
.s_axis_tvalid(towrite_valid),
.s_axis_tready(towrite_ready),
.m_axis_tdata(towrite_b_data),
.m_axis_tvalid(towrite_b_valid),
.m_axis_tready(towrite_b_ready)
);
nukv_fifogen #(
.DATA_SIZE(KEY_WIDTH+META_WIDTH+64),
.ADDR_BITS(6)
) fifo_feedback_delayer (
.clk(clk),
.rst(rst),
.s_axis_tdata(writefb_data),
.s_axis_tvalid(writefb_valid & write_feedback_channel_ready),
.s_axis_tready(writefb_ready),
.m_axis_tdata(writefb_b_data),
.m_axis_tvalid(writefb_b_valid),
.m_axis_tready(writefb_b_ready)
);
assign write_feedback_channel_ready = writefb_ready & hash_two_in_ready;
nukv_HT_Write_v2 #(
.IS_SIM(IS_SIM),
.MEMADDR_WIDTH(HASHTABLE_MEM_SIZE)
)
writemodule
(
.clk(clk),
.rst(rst),
.input_data(towrite_b_data),
.input_valid(towrite_b_valid),
.input_ready(towrite_b_ready),
.feedback_data(writefb_data),
.feedback_valid(writefb_valid),
.feedback_ready(write_feedback_channel_ready),
.output_data(writeout_data),
.output_valid(writeout_valid),
.output_ready(writeout_ready),
.malloc_req_valid(mreq_valid),
.malloc_req_size (mreq_data),
.malloc_req_ready(mreq_ready),
.malloc_pointer(malloc_data_b),
.malloc_valid(malloc_valid_b),
.malloc_failed(malloc_failed_b),
.malloc_ready(malloc_ready_b),
.free_pointer(free_data),
.free_size(free_size),
.free_valid(free_valid),
.free_ready(free_ready),
.free_wipe(free_wipe),
.rd_data(ht_buf_rd_data),
.rd_valid(ht_buf_rd_valid),
.rd_ready(ht_buf_rd_ready),
.wr_data(ht_wr_data),
.wr_valid(ht_wr_valid),
.wr_ready(~ht_wr_stall),
.wrcmd_data(wrcmd_data),
.wrcmd_valid(wrcmd_valid),
.wrcmd_ready(wrcmd_ready)
);
nukv_fifogen #(
.DATA_SIZE(49),
.ADDR_BITS(6)
) fifo_freepointers (
.clk(clk),
.rst(rst),
.s_axis_tdata({free_wipe,free_data,free_size}),
.s_axis_tvalid(free_valid),
.s_axis_tready(free_ready),
.m_axis_tdata(free_data_full_b),
.m_axis_tvalid(free_valid_b),
.m_axis_tready(free_ready_b)
);
assign free_wipe_b = free_data_full_b[32+16];
assign free_data_b = free_data_full_b[32+16-1:16];
assign free_size_b = free_data_full_b[15:0];
nukv_fifogen #(
.DATA_SIZE(65),
.ADDR_BITS(6)
) fifo_mallocpointers (
.clk(clk),
.rst(rst),
.s_axis_tdata({malloc_failed,malloc_data}),
.s_axis_tvalid(malloc_valid),
.s_axis_tready(malloc_ready),
.m_axis_tdata(malloc_data_full_b),
.m_axis_tvalid(malloc_valid_b),
.m_axis_tready(malloc_ready_b)
);
assign malloc_failed_b = malloc_data_full_b[32];
assign malloc_data_b = malloc_data_full_b[31:0];
wire [31:0] p_rdcmd_data_short;
wire [31:0] p_wrcmd_data_short;
wire [31:0] b_rdcmd_data_short;
wire [7:0] b_rdcmd_cnt;
wire [31:0] b_wrcmd_data_short;
nukv_fifogen #(
.DATA_SIZE(16),
.ADDR_BITS(6)
) fifo_malloc_request (
.clk(clk),
.rst(rst),
.s_axis_tdata(mreq_data),
.s_axis_tvalid(mreq_valid),
.s_axis_tready(mreq_ready),
.m_axis_tdata(mreq_data_b),
.m_axis_tvalid(mreq_valid_b),
.m_axis_tready(mreq_ready_b)
);
/*
wire[511:0] p_rd_data_b;
wire p_rd_ready_b;
wire p_rd_valid_b;
nukv_fifogen #(
.DATA_SIZE(512),
.ADDR_BITS(6)
) fifo_pread_data (
.clk(clk),
.rst(rst),
.s_axis_tdata(p_rd_data),
.s_axis_tvalid(p_rd_valid),
.s_axis_tready(p_rd_ready),
.m_axis_tdata(p_rd_data_b),
.m_axis_tvalid(p_rd_valid_b),
.m_axis_tready(p_rd_ready_b)
);*/
/*
wire[511:0] b_rd_data_b;
wire b_rd_ready_b;
wire b_rd_valid_b;
nukv_fifogen #(
.DATA_SIZE(512),
.ADDR_BITS(6)
) fifo_bread_data (
.clk(clk),
.rst(rst),
.s_axis_tdata(b_rd_data),
.s_axis_tvalid(b_rd_valid),
.s_axis_tready(b_rd_ready),
.m_axis_tdata(b_rd_data_b),
.m_axis_tvalid(b_rd_valid_b),
.m_axis_tready(b_rd_ready_b)
);*/
wire malloc_error_valid;
wire[7:0] malloc_error_state;
nukv_Malloc #(
.IS_SIM(IS_SIM),
.SUPPORT_SCANS(SUPPORT_SCANS),
.MAX_MEMORY_SIZE(VALUESTORE_MEM_SIZE)
)
mallocmodule
(
.clk(clk),
.rst(rst),
.req_data(mreq_data_b),
.req_valid(mreq_valid_b),
.req_ready(mreq_ready_b),
.malloc_pointer(malloc_data),
.malloc_valid(malloc_valid),
.malloc_failed(malloc_failed),
.malloc_ready(malloc_ready),
.free_pointer(free_data_b),
.free_size(free_size_b),
.free_valid(free_valid_b),
.free_ready(free_ready_b),
.free_wipe(free_wipe_b),
.p_rdcmd_data(p_rdcmd_data_short),
.p_rdcmd_valid(p_rdcmd_valid),
.p_rdcmd_ready(p_rdcmd_ready),
.p_rd_data(p_rd_data),
.p_rd_valid(p_rd_valid),
.p_rd_ready(p_rd_ready),
.p_wr_data(p_wr_data),
.p_wr_valid(p_wr_valid),
.p_wr_ready(p_wr_ready),
.p_wrcmd_data(p_wrcmd_data_short),
.p_wrcmd_valid(p_wrcmd_valid),
.p_wrcmd_ready(p_wrcmd_ready),
.b_rdcmd_data(b_rdcmd_data_short),
.b_rdcmd_cnt(b_rdcmd_cnt),
.b_rdcmd_valid(b_rdcmd_valid),
.b_rdcmd_ready(b_rdcmd_ready),
.b_rd_data(b_rd_data),
.b_rd_valid(b_rd_valid),
.b_rd_ready(b_rd_ready),
.b_wr_data(b_wr_data),
.b_wr_valid(b_wr_valid),
.b_wr_ready(b_wr_ready),
.b_wrcmd_data(b_wrcmd_data_short),
.b_wrcmd_valid(b_wrcmd_valid),
.b_wrcmd_ready(b_wrcmd_ready),
.scan_start(scan_kickoff),
.is_scanning(scan_reading),
.scan_numlines(scan_readsissued),
.scan_valid(scan_valid),
.scan_addr(scan_addr),
.scan_cnt(scan_cnt),
.scan_ready(scan_ready),
.scan_pause(SUPPORT_SCANS==1 ? scan_pause : 0),
.error_memory(malloc_error_valid),
.error_state(malloc_error_state)
);
always @(posedge clk) begin
if (SUPPORT_SCANS==1) begin
if (rst) begin
scan_mode_on <= 0;
scan_readsprocessed <= 0;
rst_regex_after_scan <= 0;
end
else begin
rst_regex_after_scan <= 0;
if (scan_mode_on==0 && scan_reading==1) begin
scan_mode_on <= 1;
scan_readsprocessed <= 0;
end
if (scan_mode_on==1 && value_frompred_b_valid==1 && value_frompred_b_ready==1) begin
scan_readsprocessed <= scan_readsprocessed +1;
end
if (scan_mode_on==1 && scan_reading==0 && scan_readsprocessed==scan_readsissued) begin
scan_mode_on <= 0;
rst_regex_after_scan <= 1;
end
end
end else begin
scan_mode_on <= 0;
rst_regex_after_scan <= 0;
end
end
assign scan_ready = scan_rdcmd_ready;
assign scan_rdcmd_valid = scan_valid;
assign scan_rdcmd_data = {scan_cnt, scan_addr};
assign b_rdcmd_data ={24'b000000000000000100000001, b_rdcmd_cnt[7:0], 4'b0000, b_rdcmd_data_short[27:0]};
assign b_wrcmd_data ={24'b000000000000000100000001, 8'b00000001, 4'b0000, b_wrcmd_data_short[27:0]};
assign p_rdcmd_data ={24'b000000000000000100000001, 8'b00000001, 4'b0000, p_rdcmd_data_short[27:0]};
assign p_wrcmd_data ={24'b000000000000000100000001, 8'b00000001, 4'b0000, p_wrcmd_data_short[27:0]};
assign ht_rd_cmd_data ={24'b000000000000000100000001, 8'b00000001, 4'b0000, 4'b0000, rdcmd_data[23:0]};
assign ht_rd_cmd_valid = rdcmd_valid;
assign rdcmd_ready = ~ht_rd_cmd_stall;
assign ht_wr_cmd_data ={24'b000000000000000100000001, 8'b00000001, 4'b0000, 4'b0000, wrcmd_data[23:0]};
assign ht_wr_cmd_valid = wrcmd_valid;
assign wrcmd_ready = ~ht_wr_cmd_stall;
nukv_fifogen #(
.DATA_SIZE(KEY_WIDTH+META_WIDTH+42),
.ADDR_BITS(5)
) fifo_write_to_set (
.clk(clk),
.rst(rst),
.s_axis_tdata({writeout_data[KEY_WIDTH +: META_WIDTH], writeout_data[KEY_WIDTH+META_WIDTH +: 42], writeout_data[KEY_WIDTH-1:0]}),
.s_axis_tvalid(writeout_valid),
.s_axis_tready(writeout_ready),
.m_axis_tdata(writeout_b_data),
.m_axis_tvalid(writeout_b_valid),
.m_axis_tready(writeout_b_ready)
);
wire predconf_valid;
wire predconf_scan;
wire predconf_ready;
wire[96+511:0] predconf_data;
wire predconf_b_valid;
wire predconf_b_scan;
wire predconf_b_ready;
wire[96+511:0] predconf_b_data;
wire[1+511+96:0] predconf_b_fulldata;
assign setter_rdcmd_ready = (scan_mode_on == 1 && SUPPORT_SCANS==1) ? 0 : upd_rdcmd_ready;
assign scan_rdcmd_ready = (scan_mode_on == 1 && SUPPORT_SCANS==1) ? upd_rdcmd_ready : 0;
assign upd_rdcmd_data = (scan_mode_on == 1 && SUPPORT_SCANS==1) ? scan_rdcmd_data : setter_rdcmd_data;
assign upd_rd_cmd_valid = (scan_mode_on == 1 && SUPPORT_SCANS==1) ? scan_rdcmd_valid : setter_rdcmd_valid;
nukv_Value_Set #(.SUPPORT_SCANS(SUPPORT_SCANS))
valuesetter
(
.clk(clk),
.rst(rst),
.input_data(writeout_b_data),
.input_valid(writeout_b_valid),
.input_ready(writeout_b_ready),
.value_data(value_b_data[VALUE_WIDTH-1:0]),
.value_valid(value_b_valid),
.value_ready(value_b_ready),
.output_data(fromset_data),
.output_valid(fromset_valid),
.output_ready(fromset_ready),
.wrcmd_data(upd_wrcmd_data),
.wrcmd_valid(upd_wr_cmd_valid),
.wrcmd_ready(upd_wrcmd_ready),
.wr_data(upd_wr_data),
.wr_valid(upd_wr_valid),
.wr_ready(~upd_wr_stall),
.rdcmd_data(setter_rdcmd_data) ,
.rdcmd_valid(setter_rdcmd_valid),
.rdcmd_ready(setter_rdcmd_ready),
.pe_valid(predconf_valid),
.pe_scan(predconf_scan),
.pe_ready(predconf_ready),
.pe_data(predconf_data),
.scan_start(scan_kickoff),
.scan_mode(scan_mode_on)
);
wire[VALUE_WIDTH-1:0] value_read_data_int;
wire value_read_valid_int;
wire value_read_ready_int;
wire value_read_almostfull_int2;
always @(posedge clk) begin
if (rst) begin
scan_pause <= 0;
end
else begin
if (scan_readsissued>0 && scan_readsissued-scan_readsprocessed> (IS_SIM==1 ? 64 : 200)) begin
scan_pause <= 1;
end else begin
scan_pause <= 0;
end
end
end
wire[511:0] value_read_data_buf;
wire value_read_ready_buf;
wire value_read_valid_buf;
wire upd_ready;
assign upd_rd_read = upd_ready & ~upd_rd_empty;
nukv_fifogen #(
.DATA_SIZE(VALUE_WIDTH),
.ADDR_BITS(9)
) fifo_valuedatafrommemory (
.clk(clk),
.rst(rst),
.s_axis_tdata(upd_rd_data),
.s_axis_tvalid(~upd_rd_empty),
.s_axis_tready(upd_ready),
.s_axis_talmostfull(value_read_almostfull_int2),
.m_axis_tdata(value_read_data_buf),
.m_axis_tvalid(value_read_valid_buf),
.m_axis_tready(value_read_ready_buf)
);
wire toget_ready;
assign fromset_ready = (scan_mode_on==0 || SUPPORT_SCANS==0) ? toget_ready : 0;
assign pe_cmd_ready = (scan_mode_on==0 || SUPPORT_SCANS==0) ? 0 : toget_ready;
nukv_fifogen #(
.DATA_SIZE(KEY_WIDTH+META_WIDTH+HEADER_WIDTH),
.ADDR_BITS(7)
) fifo_output_from_set (
.clk(clk),
.rst(rst),
.s_axis_tdata((scan_mode_on==0 || SUPPORT_SCANS==0) ? fromset_data : {8'b00001111, pe_cmd_meta[0 +: 88], 1'b0, pe_cmd_data[9:0], 159'd0}),
.s_axis_tvalid((scan_mode_on==0 || SUPPORT_SCANS==0) ? fromset_valid : pe_cmd_valid),
.s_axis_tready(toget_ready),
.m_axis_tdata(fromset_b_data),
.m_axis_tvalid(fromset_b_valid),
.m_axis_tready(fromset_b_ready)
);
wire predconf_regex_ready;
wire predconf_pred0_ready;
wire predconf_predother_ready;
assign predconf_b_ready = predconf_regex_ready & predconf_predother_ready;
nukv_fifogen #(
.DATA_SIZE(512+96+1),
.ADDR_BITS(7)
) fifo_output_conf_pe (
.clk(clk),
.rst(rst),
.s_axis_tdata({predconf_data, predconf_scan}),
.s_axis_tvalid(predconf_valid),
.s_axis_tready(predconf_ready),
.m_axis_tdata(predconf_b_fulldata),
.m_axis_tvalid(predconf_b_valid),
.m_axis_tready(predconf_b_ready)
);
assign predconf_b_scan = predconf_b_fulldata[0];
assign predconf_b_data = predconf_b_fulldata[1 +: 512+96];
wire pred_eval_error;
assign value_read_ready_buf = value_read_ready;
assign value_read_valid = value_read_valid_buf;
assign value_read_data = value_read_data_buf;
assign value_read_last = 0;
wire [513:0] regexin_data;
wire regexin_valid;
wire regexin_ready;
wire regexin_prebuf_ready;
wire[511:0] regexconf_data;
wire regexconf_valid;
wire regexconf_ready;
wire regexout_data;
wire regexout_valid;
wire regexout_ready;
wire buffer_violation;
wire before_get_ready;
wire before_get_almfull;
wire condin_ready;
wire cond_valid;
wire cond_ready;
wire cond_drop;
assign buffer_violation = ~cond_ready & before_get_ready;
nukv_Predicate_Eval_Pipeline_v2
#(.SUPPORT_SCANS(SUPPORT_SCANS),
.PIPE_DEPTH(CONDITION_EVALS)
) pred_eval_pipe (
.clk(clk),
.rst(rst),
.pred_data({predconf_b_data[META_WIDTH+MEMORY_WIDTH-1 : META_WIDTH], predconf_b_data[META_WIDTH-1:0]}),
.pred_valid(predconf_b_valid & predconf_b_ready),
.pred_ready(predconf_predother_ready),
.pred_scan((SUPPORT_SCANS==1) ? predconf_b_scan : 0),
.value_data(value_read_data),
.value_last(value_read_last),
.value_drop(0),
.value_valid(value_read_valid),
.value_ready(value_read_ready),
.output_valid(value_frompred_valid),
.output_ready(value_frompred_ready),
.output_data(value_frompred_data),
.output_last(value_frompred_last),
.output_drop(value_frompred_drop),
.scan_on_outside(scan_mode_on),
.cmd_valid(pe_cmd_valid),
.cmd_length(pe_cmd_data),
.cmd_meta(pe_cmd_meta),
.cmd_ready(pe_cmd_ready),
.error_input(pred_eval_error)
);
// REGEX ---------------------------------------------------
wire toregex_ready;
assign value_frompred_ready = toregex_ready & condin_ready & before_get_ready;
fifo_generator_512_shallow_sync
//#(
// .DATA_SIZE(512+1),
// .ADDR_BITS(7)
//)
fifo_toward_regex (
.s_aclk(clk),
.s_aresetn(~rst),
.s_axis_tdata(value_frompred_data),
.s_axis_tvalid(value_frompred_valid & value_frompred_ready),
.s_axis_tready(toregex_ready),
.s_axis_tuser(value_frompred_drop),
.s_axis_tlast(value_frompred_last),
.m_axis_tdata(regexin_data[511:0]),
.m_axis_tvalid(regexin_valid),
.m_axis_tready(regexin_ready),
.m_axis_tuser(regexin_data[513]),
.m_axis_tlast(regexin_data[512])
);
assign regexconf_data[512-48*CONDITION_EVALS-1:0] = predconf_b_data[META_WIDTH+48*CONDITION_EVALS +: (512-48*CONDITION_EVALS)];
assign regexconf_data[511] = scan_mode_on;
assign regexconf_valid = predconf_b_valid & predconf_b_ready;
assign predconf_regex_ready = regexconf_ready;
wire [511:0] regexconf_buf_data;
wire regexconf_buf_valid;
wire regexconf_buf_ready;
//nukv_fifogen_async_clock #(
// .DATA_SIZE(512),
// .ADDR_BITS(7)
//)
fifo_generator_512_shallow_sync
fifo_config_regex (
.s_aclk(clk),
.s_aresetn(~rst),
.s_axis_tdata(regexconf_data),
.s_axis_tvalid(regexconf_valid),
.s_axis_tready(regexconf_ready),
.s_axis_tlast(1'b1),
.m_axis_tdata(regexconf_buf_data),
.m_axis_tvalid(regexconf_buf_valid),
.m_axis_tready(regexconf_buf_ready),
.m_axis_tlast()
);
wire regexout_int_data;
wire regexout_int_valid;
wire regexout_int_ready;
kvs_vs_RegexTop_FastClockInside regex_module (
.clk(clk),
.rst(rst | rst_regex_after_scan),
.fast_clk(clk_faster),
.fast_rst(rst_faster),
.input_data(regexin_data[511:0]),
.input_valid(regexin_valid),
.input_last(regexin_data[512]),
.input_ready(regexin_ready),
.config_data(regexconf_buf_data),
.config_valid(regexconf_buf_valid),
.config_ready(regexconf_buf_ready),
.found_loc(regexout_int_data),
.found_valid(regexout_int_valid),
.found_ready(regexout_int_ready)
);
//nukv_fifogen_async_clock #(
//.DATA_SIZE(1),
// .ADDR_BITS(8)
//)
fifo_generator_1byte_sync
fifo_decision_from_regex (
.s_aclk(clk),
.s_aresetn(~rst),
.s_axis_tdata(regexout_int_data),
.s_axis_tvalid(regexout_int_valid),
.s_axis_tready(regexout_int_ready),
.m_axis_tdata(regexout_data),
.m_axis_tvalid(regexout_valid),
.m_axis_tready(regexout_ready)
);
nukv_fifogen #(
.DATA_SIZE(MEMORY_WIDTH),
.ADDR_BITS(8)
) fifo_value_from_pe (
.clk(clk),
.rst(rst),
.s_axis_tdata(value_frompred_data),
.s_axis_tvalid(value_frompred_valid & value_frompred_ready),
.s_axis_tready(before_get_ready),
.m_axis_tdata(value_frompred_b_data),
.m_axis_tvalid(value_frompred_b_valid),
.m_axis_tready(value_frompred_b_ready)
);
nukv_fifogen #(
.DATA_SIZE(1),
.ADDR_BITS(8)
) fifo_decision_from_pe (
.clk(clk),
.rst(rst),
.s_axis_tdata(value_frompred_drop),
.s_axis_tvalid(value_frompred_valid & value_frompred_ready & value_frompred_last ),
.s_axis_tready(condin_ready),
.m_axis_tdata(cond_drop),
.m_axis_tvalid(cond_valid),
.m_axis_tready(cond_ready)
);
wire[127:0] final_out_data;
wire final_out_valid;
wire final_out_ready;
wire final_out_last;
wire decision_is_valid;
wire decision_is_drop;
wire read_decision;
assign decision_is_valid = cond_valid & regexout_valid;
assign decision_is_drop = cond_drop | ~regexout_data;
assign cond_ready = read_decision & decision_is_valid;
assign regexout_ready = read_decision & decision_is_valid;
nukv_Value_Get #(.SUPPORT_SCANS(SUPPORT_SCANS))
valuegetter
(
.clk(clk),
.rst(rst),
.input_data(fromset_b_data),
.input_valid(fromset_b_valid),
.input_ready(fromset_b_ready),
.value_data(value_frompred_b_data),
.value_valid(value_frompred_b_valid),
.value_ready(value_frompred_b_ready),
.cond_valid(decision_is_valid),
.cond_drop(decision_is_drop),
.cond_ready(read_decision),
.output_data(final_out_data[127:0]),
.output_valid(final_out_valid),
.output_ready(final_out_ready),
.output_last(final_out_last),
.scan_mode(scan_mode_on)
);
assign m_axis_tvalid = (final_out_data[64+:16]==16'h7fff) ? 0 : final_out_valid;
assign m_axis_tlast = final_out_last;
assign m_axis_tdata = final_out_data;
assign final_out_ready = m_axis_tready;
assign upd_rd_cmd_data ={24'b000000000000000100000001, upd_rdcmd_data[39:32], 4'b0000, 3'b001, upd_rdcmd_data[24:0]};
assign upd_rdcmd_ready = ~upd_rd_cmd_stall;
assign upd_wr_cmd_data ={24'b000000000000000100000001, upd_wrcmd_data[39:32], 4'b0000, 3'b001, upd_wrcmd_data[24:0]};
assign upd_wrcmd_ready = ~upd_wr_cmd_stall;
reg[31:0] rdaddr_aux;
reg[191:0] data_aux;
// -------------------------------------------------
/* */
wire [35:0] control0, control1;
reg [255:0] data;
reg [255:0] debug_r;
reg [255:0] debug_r2;
reg [255:0] debug_r3;
wire [63:0] vio_cmd;
reg [63:0] vio_cmd_r;
reg old_scan_mode;
reg [31:0] condcnt;
reg [31:0] regxcnt;
reg [31:0] diffrescnt;
always @(posedge clk) begin
if (rst==1) begin
input_counter<=0;
old_scan_mode <= 0;
condcnt <= 0;
regxcnt <= 0;
end else begin
//if(debug_r[2:0]==3'b111) begin
input_counter<= input_counter+1;
//end
if (value_frompred_valid==1 && value_frompred_ready==1 && value_frompred_last==1 && condin_ready==1) begin
condcnt <= condcnt +1;
end
if (regexout_int_valid==1 && regexout_int_ready==1) begin
regxcnt <= regxcnt+1;
end
end
old_scan_mode <= scan_mode_on;
if (regxcnt > condcnt) begin
diffrescnt <= regxcnt - condcnt;
end
else begin
diffrescnt <= condcnt - regxcnt;
end
//data_aux <= {regexin_data[63:0],diffrescnt};
data_aux <= {value_read_data[0 +: 64], s_axis_tdata[63:0]};
debug_r[0] <= s_axis_tvalid ;
debug_r[1] <= s_axis_tready;
debug_r[2] <= s_axis_tlast;
debug_r[3] <= key_valid ;
debug_r[4] <= key_ready;
debug_r[5] <= meta_valid;
debug_r[6] <= meta_ready;
debug_r[7] <= value_valid;
debug_r[8] <= value_ready;
debug_r[9] <= mreq_valid;
debug_r[10] <= mreq_ready;
debug_r[11] <= keywhash_valid;
debug_r[12] <= keywhash_ready;
debug_r[13] <= feedbwhash_valid;
debug_r[14] <= feedbwhash_ready;
debug_r[15] <= towrite_valid;
debug_r[16] <= towrite_ready;
debug_r[17] <= rdcmd_valid;
debug_r[18] <= rdcmd_ready;
debug_r[19] <= writeout_valid;
debug_r[20] <= writeout_ready;
debug_r[21] <= p_rd_valid;
debug_r[22] <= p_rd_ready;
//debug_r[23] <= (b_rd_data==0 ? 0 : 1);
debug_r[24] <= free_valid;
debug_r[25] <= free_ready;
debug_r[26] <= ht_buf_rd_valid;
debug_r[27] <= ht_buf_rd_ready;
debug_r[28] <= ht_wr_valid;
debug_r[29] <= ht_wr_stall;
debug_r[30] <= wrcmd_valid;
debug_r[31] <= wrcmd_ready;
debug_r[32] <= writeout_b_valid;
debug_r[33] <= writeout_b_ready;
debug_r[34] <= value_b_valid;
debug_r[35] <= value_b_ready;
debug_r[36] <= upd_wr_cmd_valid;
debug_r[37] <= ~upd_wr_cmd_stall;
debug_r[38] <= b_rdcmd_valid;
debug_r[39] <= b_rdcmd_ready;
debug_r[40] <= b_rd_valid;
debug_r[41] <= b_rd_ready;
debug_r[42] <= upd_rd_cmd_valid;
debug_r[43] <= ~upd_rd_cmd_stall;
debug_r[44] <= fromset_b_valid;
debug_r[45] <= fromset_b_ready;
debug_r[46] <= value_read_valid;
debug_r[47] <= value_read_ready;
debug_r[48] <= m_axis_tvalid;
debug_r[49] <= m_axis_tlast;
debug_r[50] <= m_axis_tready;
debug_r[51] <= (old_scan_mode != scan_mode_on) ? 1'b1: 1'b0;
debug_r[52] <= scan_reading;
debug_r[53] <= scan_pause;
debug_r[54] <= value_read_almostfull_int;
debug_r[56] <= pred_eval_error;
//debug_r[57] <= malloc_error_valid;
//debug_r[58] <= malloc_valid;
//debug_r[64 +: 32] <= {malloc_error_state};
// 71 70 69 68 67 66 65 64
debug_r[64 +: 8] <= {value_frompred_b_ready,value_frompred_b_valid,regexout_ready, regexout_valid, cond_ready, cond_valid, regexin_ready, regexin_valid};
//debug_r[96 +: 16] <= diffrescnt[15:0];
debug_r[128 +: 128] <= data_aux;
debug_r2 <= debug_r;
debug_r3 <= debug_r2;
data <= debug_r3;
end
icon icon_inst(
.CONTROL0(control0),
.CONTROL1(control1)
);
vio vio_inst(
.CONTROL(control1),
.CLK(clk),
.SYNC_OUT(vio_cmd)
// .SYNC_OUT()
);
ila_256 ila_256_inst(
.CONTROL(control0),
.CLK(clk),
.TRIG0(data)
);
/**/
endmodule
`default_nettype wire
|
/*
-- ============================================================================
-- FILE NAME : alu.v
-- DESCRIPTION : ËãÐgÕÀíÑÝËã¥æ¥Ë¥Ã¥È
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "cpu.h"
/********** ¥â¥¸¥å©`¥ë **********/
module alu (
input wire [`WordDataBus] in_0, // ÈëÁ¦ 0
input wire [`WordDataBus] in_1, // ÈëÁ¦ 1
input wire [`AluOpBus] op, // ¥ª¥Ú¥ì©`¥·¥ç¥ó
output reg [`WordDataBus] out, // ³öÁ¦
output reg of // ¥ª©`¥Ð¥Õ¥í©`
);
/********** ·ûºÅ¸¶¤Èë³öÁ¦ÐźŠ**********/
wire signed [`WordDataBus] s_in_0 = $signed(in_0); // ·ûºÅ¸¶¤ÈëÁ¦ 0
wire signed [`WordDataBus] s_in_1 = $signed(in_1); // ·ûºÅ¸¶¤ÈëÁ¦ 1
wire signed [`WordDataBus] s_out = $signed(out); // ·ûºÅ¸¶¤³öÁ¦
/********** ËãÐgÕÀíÑÝËã **********/
always @(*) begin
case (op)
`ALU_OP_AND : begin // ÕÀí·e£¨AND£©
out = in_0 & in_1;
end
`ALU_OP_OR : begin // ÕÀíºÍ£¨OR£©
out = in_0 | in_1;
end
`ALU_OP_XOR : begin // ÅÅËûµÄÕÀíºÍ£¨XOR£©
out = in_0 ^ in_1;
end
`ALU_OP_ADDS : begin // ·ûºÅ¸¶¤¼ÓËã
out = in_0 + in_1;
end
`ALU_OP_ADDU : begin // ·ûºÅ¤Ê¤·¼ÓËã
out = in_0 + in_1;
end
`ALU_OP_SUBS : begin // ·ûºÅ¸¶¤pËã
out = in_0 - in_1;
end
`ALU_OP_SUBU : begin // ·ûºÅ¤Ê¤·pËã
out = in_0 - in_1;
end
`ALU_OP_SHRL : begin // ÕÀíÓÒ¥·¥Õ¥È
out = in_0 >> in_1[`ShAmountLoc];
end
`ALU_OP_SHLL : begin // ÕÀí×ó¥·¥Õ¥È
out = in_0 << in_1[`ShAmountLoc];
end
default : begin // ¥Ç¥Õ¥©¥ë¥È (No Operation)
out = in_0;
end
endcase
end
/********** ¥ª©`¥Ð¥Õ¥í©`¥Á¥§¥Ã¥¯ **********/
always @(*) begin
case (op)
`ALU_OP_ADDS : begin // ¼ÓË㥪©`¥Ð¥Õ¥í©`¤Î¥Á¥§¥Ã¥¯
if (((s_in_0 > 0) && (s_in_1 > 0) && (s_out < 0)) ||
((s_in_0 < 0) && (s_in_1 < 0) && (s_out > 0))) begin
of = `ENABLE;
end else begin
of = `DISABLE;
end
end
`ALU_OP_SUBS : begin // pË㥪©`¥Ð¥Õ¥í©`¤Î¥Á¥§¥Ã¥¯
if (((s_in_0 < 0) && (s_in_1 > 0) && (s_out > 0)) ||
((s_in_0 > 0) && (s_in_1 < 0) && (s_out < 0))) begin
of = `ENABLE;
end else begin
of = `DISABLE;
end
end
default : begin // ¥Ç¥Õ¥©¥ë¥È
of = `DISABLE;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2B_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__NOR2B_PP_SYMBOL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor2b (
//# {{data|Data Signals}}
input A ,
input B_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2B_PP_SYMBOL_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
input wire phy_tx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
end
end
//assign led = sw;
assign led = led_reg;
assign phy_reset_n = !rst;
assign uart_txd = 0;
eth_mac_1g_gmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR2"),
.CLOCK_INPUT_STYLE("BUFIO2"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rx_clk(phy_rx_clk),
.gmii_rxd(phy_rxd),
.gmii_rx_dv(phy_rx_dv),
.gmii_rx_er(phy_rx_er),
.gmii_tx_clk(phy_gtx_clk),
.mii_tx_clk(phy_tx_clk),
.gmii_txd(phy_txd),
.gmii_tx_en(phy_tx_en),
.gmii_tx_er(phy_tx_er),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "reg_defines_reference_router.v"
`timescale 1ns/1ps
module small_fifo
#(parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2**MAX_DEPTH_BITS - 1
)
(
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output empty,
input reset,
input clk
);
localparam MAX_DEPTH = 2 ** MAX_DEPTH_BITS;
reg [WIDTH-1:0] queue [MAX_DEPTH - 1 : 0];
reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;
reg [MAX_DEPTH_BITS : 0] depth;
// Sample the data
always @(posedge clk)
begin
if (wr_en)
queue[wr_ptr] <= din;
if (rd_en)
dout <=
// synthesis translate_off
#1
// synthesis translate_on
queue[rd_ptr];
end
always @(posedge clk)
begin
if (reset) begin
rd_ptr <= 'h0;
wr_ptr <= 'h0;
depth <= 'h0;
end
else begin
if (wr_en) wr_ptr <= wr_ptr + 'h1;
if (rd_en) rd_ptr <= rd_ptr + 'h1;
if (wr_en & ~rd_en) depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth + 'h1;
else if (~wr_en & rd_en) depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth - 'h1;
end
end
//assign dout = queue[rd_ptr];
assign full = depth == MAX_DEPTH;
assign prog_full = (depth >= PROG_FULL_THRESHOLD);
assign nearly_full = depth >= MAX_DEPTH-1;
assign empty = depth == 'h0;
// synthesis translate_off
always @(posedge clk)
begin
if (wr_en && depth == MAX_DEPTH && !rd_en)
$display($time, " ERROR: Attempt to write to full FIFO: %m");
if (rd_en && depth == 'h0)
$display($time, " ERROR: Attempt to read an empty FIFO: %m");
end
// synthesis translate_on
endmodule // small_fifo
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_timing_param #
( parameter
CFG_DWIDTH_RATIO = 2,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
// cfg: general
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
// cfg: timing parameters
CFG_PORT_WIDTH_CAS_WR_LAT = 4, // max will be 8 in DDR3
CFG_PORT_WIDTH_ADD_LAT = 3, // max will be 10 in DDR3
CFG_PORT_WIDTH_TCL = 4, // max will be 11 in DDR3
CFG_PORT_WIDTH_TRRD = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TFAW = 6, // 6 - 32 enough?
CFG_PORT_WIDTH_TRFC = 8, // 12-140 enough?
CFG_PORT_WIDTH_TREFI = 13, // 780 - 6240 enough?
CFG_PORT_WIDTH_TRCD = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TRP = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TWR = 4, // 2 - 12 enough?
CFG_PORT_WIDTH_TWTR = 4, // 1 - 10 enough?
CFG_PORT_WIDTH_TRTP = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TRAS = 5, // 4 - 29 enough?
CFG_PORT_WIDTH_TRC = 6, // 8 - 40 enough?
CFG_PORT_WIDTH_TCCD = 3, // max will be 4 in 4n prefetch architecture?
CFG_PORT_WIDTH_TMRD = 3, // 4 - ? enough?
CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10, // max will be 512 in DDR3
CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4, // 3 - ? enough?
CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16, // enough?
CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES = 4, // enough?
CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES = 4, // enough?
// cfg: extra timing parameters
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 4,
// Output - derived timing parameters width
T_PARAM_ACT_TO_RDWR_WIDTH = 6, // temporary
T_PARAM_ACT_TO_PCH_WIDTH = 6, // temporary
T_PARAM_ACT_TO_ACT_WIDTH = 6, // temporary
T_PARAM_RD_TO_RD_WIDTH = 6, // temporary
T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_RD_TO_WR_WIDTH = 6, // temporary
T_PARAM_RD_TO_WR_BC_WIDTH = 6, // temporary
T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_RD_TO_PCH_WIDTH = 6, // temporary
T_PARAM_RD_AP_TO_VALID_WIDTH = 6, // temporary
T_PARAM_WR_TO_WR_WIDTH = 6, // temporary
T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_WR_TO_RD_WIDTH = 6, // temporary
T_PARAM_WR_TO_RD_BC_WIDTH = 6, // temporary
T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_WR_TO_PCH_WIDTH = 6, // temporary
T_PARAM_WR_AP_TO_VALID_WIDTH = 6, // temporary
T_PARAM_PCH_TO_VALID_WIDTH = 6, // temporary
T_PARAM_PCH_ALL_TO_VALID_WIDTH = 6, // temporary
T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = 6, // temporary
T_PARAM_FOUR_ACT_TO_ACT_WIDTH = 6, // temporary
T_PARAM_ARF_TO_VALID_WIDTH = 8, // temporary
T_PARAM_PDN_TO_VALID_WIDTH = 6, // temporary
T_PARAM_SRF_TO_VALID_WIDTH = 10, // temporary
T_PARAM_SRF_TO_ZQ_CAL_WIDTH = 10, // temporary
T_PARAM_ARF_PERIOD_WIDTH = 13, // temporary
T_PARAM_PDN_PERIOD_WIDTH = 16, // temporary
T_PARAM_POWER_SAVING_EXIT_WIDTH = 6, // temporary
T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH = 4 // temporary
)
(
ctl_clk,
ctl_reset_n,
// Input - configuration
cfg_burst_length,
cfg_type,
// Input - memory timing parameter
cfg_cas_wr_lat,
cfg_add_lat,
cfg_tcl,
cfg_trrd,
cfg_tfaw,
cfg_trfc,
cfg_trefi,
cfg_trcd,
cfg_trp,
cfg_twr,
cfg_twtr,
cfg_trtp,
cfg_tras,
cfg_trc,
cfg_tccd,
cfg_tmrd,
cfg_self_rfsh_exit_cycles,
cfg_pdn_exit_cycles,
cfg_auto_pd_cycles,
cfg_power_saving_exit_cycles,
cfg_mem_clk_entry_cycles,
// Input - extra derived timing parameter
cfg_extra_ctl_clk_act_to_rdwr,
cfg_extra_ctl_clk_act_to_pch,
cfg_extra_ctl_clk_act_to_act,
cfg_extra_ctl_clk_rd_to_rd,
cfg_extra_ctl_clk_rd_to_rd_diff_chip,
cfg_extra_ctl_clk_rd_to_wr,
cfg_extra_ctl_clk_rd_to_wr_bc,
cfg_extra_ctl_clk_rd_to_wr_diff_chip,
cfg_extra_ctl_clk_rd_to_pch,
cfg_extra_ctl_clk_rd_ap_to_valid,
cfg_extra_ctl_clk_wr_to_wr,
cfg_extra_ctl_clk_wr_to_wr_diff_chip,
cfg_extra_ctl_clk_wr_to_rd,
cfg_extra_ctl_clk_wr_to_rd_bc,
cfg_extra_ctl_clk_wr_to_rd_diff_chip,
cfg_extra_ctl_clk_wr_to_pch,
cfg_extra_ctl_clk_wr_ap_to_valid,
cfg_extra_ctl_clk_pch_to_valid,
cfg_extra_ctl_clk_pch_all_to_valid,
cfg_extra_ctl_clk_act_to_act_diff_bank,
cfg_extra_ctl_clk_four_act_to_act,
cfg_extra_ctl_clk_arf_to_valid,
cfg_extra_ctl_clk_pdn_to_valid,
cfg_extra_ctl_clk_srf_to_valid,
cfg_extra_ctl_clk_srf_to_zq_cal,
cfg_extra_ctl_clk_arf_period,
cfg_extra_ctl_clk_pdn_period,
// Output - derived timing parameters
t_param_act_to_rdwr,
t_param_act_to_pch,
t_param_act_to_act,
t_param_rd_to_rd,
t_param_rd_to_rd_diff_chip,
t_param_rd_to_wr,
t_param_rd_to_wr_bc,
t_param_rd_to_wr_diff_chip,
t_param_rd_to_pch,
t_param_rd_ap_to_valid,
t_param_wr_to_wr,
t_param_wr_to_wr_diff_chip,
t_param_wr_to_rd,
t_param_wr_to_rd_bc,
t_param_wr_to_rd_diff_chip,
t_param_wr_to_pch,
t_param_wr_ap_to_valid,
t_param_pch_to_valid,
t_param_pch_all_to_valid,
t_param_act_to_act_diff_bank,
t_param_four_act_to_act,
t_param_arf_to_valid,
t_param_pdn_to_valid,
t_param_srf_to_valid,
t_param_srf_to_zq_cal,
t_param_arf_period,
t_param_pdn_period,
t_param_power_saving_exit,
t_param_mem_clk_entry_cycles
);
input ctl_clk;
input ctl_reset_n;
// Input - configuration
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
// Input - memory timing parameter
input [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
input [CFG_PORT_WIDTH_TRRD - 1 : 0] cfg_trrd;
input [CFG_PORT_WIDTH_TFAW - 1 : 0] cfg_tfaw;
input [CFG_PORT_WIDTH_TRFC - 1 : 0] cfg_trfc;
input [CFG_PORT_WIDTH_TREFI - 1 : 0] cfg_trefi;
input [CFG_PORT_WIDTH_TRCD - 1 : 0] cfg_trcd;
input [CFG_PORT_WIDTH_TRP - 1 : 0] cfg_trp;
input [CFG_PORT_WIDTH_TWR - 1 : 0] cfg_twr;
input [CFG_PORT_WIDTH_TWTR - 1 : 0] cfg_twtr;
input [CFG_PORT_WIDTH_TRTP - 1 : 0] cfg_trtp;
input [CFG_PORT_WIDTH_TRAS - 1 : 0] cfg_tras;
input [CFG_PORT_WIDTH_TRC - 1 : 0] cfg_trc;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
input [CFG_PORT_WIDTH_TMRD - 1 : 0] cfg_tmrd;
input [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES - 1 : 0] cfg_self_rfsh_exit_cycles;
input [CFG_PORT_WIDTH_PDN_EXIT_CYCLES - 1 : 0] cfg_pdn_exit_cycles;
input [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] cfg_auto_pd_cycles;
input [CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES - 1 : 0] cfg_power_saving_exit_cycles;
input [CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES - 1 : 0] cfg_mem_clk_entry_cycles;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR - 1 : 0] cfg_extra_ctl_clk_act_to_rdwr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH - 1 : 0] cfg_extra_ctl_clk_act_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD - 1 : 0] cfg_extra_ctl_clk_rd_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR - 1 : 0] cfg_extra_ctl_clk_rd_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH - 1 : 0] cfg_extra_ctl_clk_rd_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_rd_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR - 1 : 0] cfg_extra_ctl_clk_wr_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD - 1 : 0] cfg_extra_ctl_clk_wr_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH - 1 : 0] cfg_extra_ctl_clk_wr_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_wr_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_all_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0] cfg_extra_ctl_clk_act_to_act_diff_bank;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_four_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_arf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pdn_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_srf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL - 1 : 0] cfg_extra_ctl_clk_srf_to_zq_cal;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD - 1 : 0] cfg_extra_ctl_clk_arf_period;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD - 1 : 0] cfg_extra_ctl_clk_pdn_period;
// Output - derived timing parameters
output [T_PARAM_ACT_TO_RDWR_WIDTH - 1 : 0] t_param_act_to_rdwr;
output [T_PARAM_ACT_TO_PCH_WIDTH - 1 : 0] t_param_act_to_pch;
output [T_PARAM_ACT_TO_ACT_WIDTH - 1 : 0] t_param_act_to_act;
output [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
output [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
output [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
output [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
output [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
output [T_PARAM_RD_TO_PCH_WIDTH - 1 : 0] t_param_rd_to_pch;
output [T_PARAM_RD_AP_TO_VALID_WIDTH - 1 : 0] t_param_rd_ap_to_valid;
output [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
output [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
output [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
output [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
output [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
output [T_PARAM_WR_TO_PCH_WIDTH - 1 : 0] t_param_wr_to_pch;
output [T_PARAM_WR_AP_TO_VALID_WIDTH - 1 : 0] t_param_wr_ap_to_valid;
output [T_PARAM_PCH_TO_VALID_WIDTH - 1 : 0] t_param_pch_to_valid;
output [T_PARAM_PCH_ALL_TO_VALID_WIDTH - 1 : 0] t_param_pch_all_to_valid;
output [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
output [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
output [T_PARAM_ARF_TO_VALID_WIDTH - 1 : 0] t_param_arf_to_valid;
output [T_PARAM_PDN_TO_VALID_WIDTH - 1 : 0] t_param_pdn_to_valid;
output [T_PARAM_SRF_TO_VALID_WIDTH - 1 : 0] t_param_srf_to_valid;
output [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal;
output [T_PARAM_ARF_PERIOD_WIDTH - 1 : 0] t_param_arf_period;
output [T_PARAM_PDN_PERIOD_WIDTH - 1 : 0] t_param_pdn_period;
output [T_PARAM_POWER_SAVING_EXIT_WIDTH - 1 : 0] t_param_power_saving_exit;
output [T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH - 1 : 0] t_param_mem_clk_entry_cycles;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// Output
reg [T_PARAM_ACT_TO_RDWR_WIDTH - 1 : 0] t_param_act_to_rdwr;
reg [T_PARAM_ACT_TO_PCH_WIDTH - 1 : 0] t_param_act_to_pch;
reg [T_PARAM_ACT_TO_ACT_WIDTH - 1 : 0] t_param_act_to_act;
reg [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
reg [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
reg [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
reg [T_PARAM_RD_TO_PCH_WIDTH - 1 : 0] t_param_rd_to_pch;
reg [T_PARAM_RD_AP_TO_VALID_WIDTH - 1 : 0] t_param_rd_ap_to_valid;
reg [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
reg [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
reg [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
reg [T_PARAM_WR_TO_PCH_WIDTH - 1 : 0] t_param_wr_to_pch;
reg [T_PARAM_WR_AP_TO_VALID_WIDTH - 1 : 0] t_param_wr_ap_to_valid;
reg [T_PARAM_PCH_TO_VALID_WIDTH - 1 : 0] t_param_pch_to_valid;
reg [T_PARAM_PCH_ALL_TO_VALID_WIDTH - 1 : 0] t_param_pch_all_to_valid;
reg [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
reg [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
reg [T_PARAM_ARF_TO_VALID_WIDTH - 1 : 0] t_param_arf_to_valid;
reg [T_PARAM_PDN_TO_VALID_WIDTH - 1 : 0] t_param_pdn_to_valid;
reg [T_PARAM_SRF_TO_VALID_WIDTH - 1 : 0] t_param_srf_to_valid;
reg [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal;
reg [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal_temp1;
reg [T_PARAM_ARF_PERIOD_WIDTH - 1 : 0] t_param_arf_period;
reg [T_PARAM_PDN_PERIOD_WIDTH - 1 : 0] t_param_pdn_period;
reg [T_PARAM_POWER_SAVING_EXIT_WIDTH - 1 : 0] t_param_power_saving_exit;
reg [T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH - 1 : 0] t_param_mem_clk_entry_cycles;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] temp_wr_to_rd_diff_chip;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Timing Parameter Calculation
//
// Important Note:
//
// - Added "cfg_extra_ctl_clk_*" ports into our timing parameter calculation in order for us to
// tweak the timing parameter gaps in the future without changing the code
//
// - This will be very useful in HIP implementation
//
// - "cfg_extra_ctl_clk_*" must be set in term of controller clock cycles
//
//--------------------------------------------------------------------------------------------------------
// DIV is a divider for our timing parameters, DIV will be '1' in fullrate, '2' in halfrate
// and '4' in quarter rate
localparam DIV = CFG_DWIDTH_RATIO / 2;
// Use the following table to determine the optimum timing parameter
// ==========================================================================================================
// || Controller Rate || Arbiter Type || Command Transition || Remainder DIV || Offset ||
// ==========================================================================================================
// || FR || Don't care || Don't care || Yes || No ||
// ----------------------------------------------------------------------------------------------------------
// || || || Row -> Col || Yes || No ||
// -- -- ROWCOL ---------------------------------------------------------------
// || || || Col -> Row || No || Yes ||
// -- HR -----------------------------------------------------------------------------------
// || || || Row -> Col || No || Yes ||
// -- -- COLROW ---------------------------------------------------------------
// || || || Col -> Row || Yes || No ||
// ----------------------------------------------------------------------------------------------------------
// || || || Row -> Col || Yes* || No ||
// -- -- ROWCOL ---------------------------------------------------------------
// || || || Col -> Row || Yes* || Yes ||
// -- QR -----------------------------------------------------------------------------------
// || || || Row -> Col || Yes* || Yes ||
// -- -- COLROW ---------------------------------------------------------------
// || || || Col -> Row || Yes* || No ||
// ----------------------------------------------------------------------------------------------------------
// Footnote:
// * for calculation with remainder of '3' only
//---------------------------------------------------
// Remainder calculation
//---------------------------------------------------
// We need to remove the extra clock cycle in half and quarter rate
// for two subsequent different commands but remain for two subsequent same commands
// example of two subsequent different commands: ROW-TO-COL, COL-TO-ROW
// example of two subsequent same commands: ROW-TO-ROW, COL-TO-COL
// Self to self command require DIV
localparam DIV_ROW_TO_ROW = DIV;
localparam DIV_COL_TO_COL = DIV;
localparam DIV_SB_TO_SB = DIV;
localparam DIV_ROW_TO_COL = (
(CFG_DWIDTH_RATIO == 2 || CFG_DWIDTH_RATIO == 8) ?
(
DIV // Need DIV in full & quarter rate
) :
(
(CFG_DWIDTH_RATIO == 4) ?
(
(CFG_CTL_ARBITER_TYPE == "ROWCOL") ? DIV : 1 // Only need DIV in ROWCOL arbiter mode
) :
(
DIV // DIV is assigned by default
)
)
);
localparam DIV_COL_TO_ROW = (
(CFG_DWIDTH_RATIO == 2 || CFG_DWIDTH_RATIO == 8) ?
(
DIV // Need DIV in full & quarter rate
) :
(
(CFG_DWIDTH_RATIO == 4) ?
(
(CFG_CTL_ARBITER_TYPE == "COLROW") ? DIV : 1 // Only need DIV in COLROW arbiter mode
) :
(
DIV // DIV is assigned by default
)
)
);
localparam DIV_SB_TO_ROW = DIV_COL_TO_ROW; // Similar to COL_TO_ROW parameter
//---------------------------------------------------
// Remainder offset calculation
//---------------------------------------------------
// In QR, odd number calculation will only need to add extra offset when calculation's remainder is > 2
// Self to self command's remainder offset will be 0
localparam DIV_ROW_TO_ROW_OFFSET = 0;
localparam DIV_COL_TO_COL_OFFSET = 0;
localparam DIV_SB_TO_SB_OFFSET = 0;
localparam DIV_ROW_TO_COL_OFFSET = (CFG_DWIDTH_RATIO == 8) ? 2 : 0;
localparam DIV_COL_TO_ROW_OFFSET = (CFG_DWIDTH_RATIO == 8) ? 2 : 0;
localparam DIV_SB_TO_ROW_OFFSET = DIV_COL_TO_ROW_OFFSET; // Similar to COL_TO_ROW parameter
//---------------------------------------------------
// Offset calculation
//---------------------------------------------------
// We need to offset timing parameter due to HR 1T and QR 2T support
// this is because we can issue a row and column command in one controller clock cycle
// Self to self command doesn't require offset
localparam ROW_TO_ROW_OFFSET = 0;
localparam COL_TO_COL_OFFSET = 0;
localparam SB_TO_SB_OFFSET = 0;
localparam ROW_TO_COL_OFFSET = (
(CFG_DWIDTH_RATIO == 2) ?
(
0 // Offset is not required in full rate
) :
(
(CFG_CTL_ARBITER_TYPE == "ROWCOL") ? 0 : 1 // Need offset in ROWCOL arbiter mode
)
);
localparam COL_TO_ROW_OFFSET = (
(CFG_DWIDTH_RATIO == 2) ?
(
0 // Offset is not required in full rate
) :
(
(CFG_CTL_ARBITER_TYPE == "COLROW") ? 0 : 1 // Need offset in COLROW arbiter mode
)
);
localparam SB_TO_ROW_OFFSET = COL_TO_ROW_OFFSET; // Similar to COL_TO_ROW parameter
//----------------------------------------------------------------------------------------------------
// Common timing parameters, not memory type specific
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
t_param_act_to_rdwr <= 0;
t_param_act_to_pch <= 0;
t_param_act_to_act <= 0;
t_param_pch_to_valid <= 0;
t_param_act_to_act_diff_bank <= 0;
t_param_four_act_to_act <= 0;
t_param_arf_to_valid <= 0;
t_param_pdn_to_valid <= 0;
t_param_srf_to_valid <= 0;
t_param_arf_period <= 0;
t_param_pdn_period <= 0;
t_param_power_saving_exit <= 0;
t_param_mem_clk_entry_cycles <= 0;
end
else
begin
// Set act_to_rdwr to '0' when additive latency is enabled
if (cfg_add_lat >= (cfg_trcd - 1))
t_param_act_to_rdwr <= 0 + ROW_TO_COL_OFFSET + cfg_extra_ctl_clk_act_to_rdwr ;
else
t_param_act_to_rdwr <= ((cfg_trcd - cfg_add_lat) / DIV) + (((cfg_trcd - cfg_add_lat) % DIV_ROW_TO_COL) > DIV_ROW_TO_COL_OFFSET ? 1 : 0) + ROW_TO_COL_OFFSET + cfg_extra_ctl_clk_act_to_rdwr ; // ACT to RD/WR - tRCD
t_param_act_to_pch <= (cfg_tras / DIV) + ((cfg_tras % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_act_to_pch ; // ACT to PCH - tRAS
t_param_act_to_act <= (cfg_trc / DIV) + ((cfg_trc % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_act_to_act ; // ACT to ACT (same bank) - tRC
t_param_pch_to_valid <= (cfg_trp / DIV) + ((cfg_trp % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_to_valid ; // PCH to ACT - tRP
t_param_act_to_act_diff_bank <= (cfg_trrd / DIV) + ((cfg_trrd % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_act_to_act_diff_bank; // ACT to ACT (diff banks) - tRRD
t_param_four_act_to_act <= (cfg_tfaw / DIV) + ((cfg_tfaw % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_four_act_to_act ; // Valid window for 4 ACT - tFAW
t_param_arf_to_valid <= (cfg_trfc / DIV) + ((cfg_trfc % DIV_SB_TO_ROW ) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_arf_to_valid ; // ARF to VALID - tRFC
t_param_pdn_to_valid <= (cfg_pdn_exit_cycles / DIV) + ((cfg_pdn_exit_cycles % DIV_SB_TO_ROW ) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pdn_to_valid ; // PDN to VALID - normally 3 clock cycles
t_param_srf_to_valid <= (cfg_self_rfsh_exit_cycles / DIV) + ((cfg_self_rfsh_exit_cycles % DIV_SB_TO_ROW ) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_srf_to_valid ; // SRF to VALID - normally 200 clock cycles
t_param_arf_period <= (cfg_trefi / DIV) + ((cfg_trefi % DIV_SB_TO_SB ) > DIV_SB_TO_SB_OFFSET ? 1 : 0) + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_arf_period ; // ARF period - tREFI
t_param_pdn_period <= cfg_auto_pd_cycles + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_pdn_period ; // PDN count after TBP is empty - specified by user
t_param_power_saving_exit <= (cfg_power_saving_exit_cycles / DIV) + ((cfg_power_saving_exit_cycles % DIV_SB_TO_SB ) > DIV_SB_TO_SB_OFFSET ? 1 : 0) + SB_TO_SB_OFFSET ; // SRF and PDN exit cycles
t_param_mem_clk_entry_cycles <= (cfg_mem_clk_entry_cycles / DIV) + ((cfg_mem_clk_entry_cycles % DIV_SB_TO_SB ) > DIV_SB_TO_SB_OFFSET ? 1 : 0) + SB_TO_SB_OFFSET ; // SRF and PDN mem clock entry and exit cycles
end
end
//----------------------------------------------------------------------------------------------------
// Memory type specific timing parameters
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
t_param_rd_to_rd <= 0;
t_param_rd_to_rd_diff_chip <= 0;
t_param_rd_to_wr <= 0;
t_param_rd_to_wr_bc <= 0;
t_param_rd_to_wr_diff_chip <= 0;
t_param_rd_to_pch <= 0;
t_param_rd_ap_to_valid <= 0;
t_param_wr_to_wr <= 0;
t_param_wr_to_wr_diff_chip <= 0;
t_param_wr_to_rd <= 0;
t_param_wr_to_rd_bc <= 0;
t_param_wr_to_rd_diff_chip <= 0;
t_param_wr_to_pch <= 0;
t_param_wr_ap_to_valid <= 0;
t_param_pch_all_to_valid <= 0;
t_param_srf_to_zq_cal_temp1 <= 0;
t_param_srf_to_zq_cal <= 0;
temp_wr_to_rd_diff_chip <= 0;
end
else
begin
if (cfg_type == `MMR_TYPE_DDR1)
begin
// DDR
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= (((cfg_burst_length / 2) + cfg_tcl) / DIV) + ((((cfg_burst_length / 2) + cfg_tcl) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL + (BL/2)
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_burst_length / 2) / DIV) + (((cfg_burst_length / 2) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - (BL/2)
t_param_rd_ap_to_valid <= (((cfg_burst_length / 2) + cfg_trp) / DIV) + ((((cfg_burst_length / 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((1 + (cfg_burst_length / 2) + cfg_twtr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twtr) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + tWTR, WL always 1
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= (((cfg_burst_length / 2) + 3) / DIV) + ((((cfg_burst_length / 2) + 3) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - 1 + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((1 + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
else if (cfg_type == `MMR_TYPE_DDR2)
begin
// DDR2
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL - WL + (BL/2) + 1, (RL - WL) will always be '1'
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2)) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2)) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - AL + (BL/2) - 2 + max(tRTP or 2)
t_param_rd_ap_to_valid <= ((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2) + cfg_trp) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twtr) / DIV) + (((cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twtr) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + tWTR
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= (((cfg_burst_length / 2) + 1) / DIV) + ((((cfg_burst_length / 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - WL - RL + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
else if (cfg_type == `MMR_TYPE_DDR3)
begin
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
// Temp value to make sure value is always larger than tCL (guaranteed), else it might create problem in HIP
// BL will alyways be set to 8 and max difference between tCL and tCWL is 3
temp_wr_to_rd_diff_chip <= (cfg_cas_wr_lat + (cfg_burst_length / 2) + 2);
t_param_rd_to_rd <= ((cfg_burst_length / 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - BL/2, not tCCD because there is no burst interrupt support in DDR3
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL - WL + (BL/2) + 2
t_param_rd_to_wr_bc <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 4) + 2) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 4) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - RL - WL + (BL/4) + 2
t_param_rd_to_wr_diff_chip <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_add_lat + max(cfg_trtp, 4)) / DIV) + (((cfg_add_lat + max(cfg_trtp, 4)) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - AL + max(tRTP or 4)
t_param_rd_ap_to_valid <= ((cfg_add_lat + max(cfg_trtp, 4) + cfg_trp) / DIV) + (((cfg_add_lat + max(cfg_trtp, 4) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= ((cfg_burst_length / 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - BL/2, not tCCD because there is no burst interrupt support in DDR3
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) / DIV) + (((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + max(tWTR or 4)
t_param_wr_to_rd_bc <= ((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) / DIV) + (((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - Same as WR to RD
t_param_wr_to_rd_diff_chip <= ((temp_wr_to_rd_diff_chip - cfg_tcl) / DIV) + (((temp_wr_to_rd_diff_chip - cfg_tcl) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - WL - RL + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= (cfg_trp / DIV) + ((cfg_trp % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRP
t_param_srf_to_zq_cal_temp1 <= ((cfg_self_rfsh_exit_cycles / 2) / DIV) + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - SRF exit time divided by 2
t_param_srf_to_zq_cal <= (t_param_arf_to_valid < t_param_srf_to_zq_cal_temp1) ? t_param_srf_to_zq_cal_temp1 : (t_param_arf_to_valid + 10); //Set proper delay for 933MHz
end
else if (cfg_type == `MMR_TYPE_LPDDR1)
begin
// LPDDR
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= (((cfg_burst_length / 2) + cfg_tcl) / DIV) + ((((cfg_burst_length / 2) + cfg_tcl) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL + (BL/2)
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_burst_length / 2) / DIV) + (((cfg_burst_length / 2) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - (BL/2)
t_param_rd_ap_to_valid <= (((cfg_burst_length / 2) + cfg_trp) / DIV) + ((((cfg_burst_length / 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((1 + (cfg_burst_length / 2) + cfg_twtr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twtr) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + tWTR, WL always 1
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= (((cfg_burst_length / 2) + 3) / DIV) + ((((cfg_burst_length / 2) + 3) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - 1 + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((1 + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
else if (cfg_type == `MMR_TYPE_LPDDR2)
begin
// LPDDR2
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
// Temp value to precalculate difference between tCL and tCWL + 2 (dead cycle)
if ((cfg_tcl - cfg_cas_wr_lat) > 2)
begin
temp_wr_to_rd_diff_chip <= 0;
end
else
begin
temp_wr_to_rd_diff_chip <= (cfg_cas_wr_lat + 2) - cfg_tcl;
end
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL - WL + (BL/2) + 2
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2)) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2)) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - AL + (BL/2) - 2 + max(tRTP or 2)
t_param_rd_ap_to_valid <= ((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2) + cfg_trp) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 2) + 1) / DIV) + (((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + max(tWTR or 4)
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= ((temp_wr_to_rd_diff_chip + (cfg_burst_length / 2)) / DIV) + (((temp_wr_to_rd_diff_chip + (cfg_burst_length / 2)) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - WL - RL + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1 + cfg_trp) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1 + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
end
end
// Function to determine max of 2 inputs
localparam MAX_FUNCTION_PORT_WIDTH = (CFG_PORT_WIDTH_TRTP > CFG_PORT_WIDTH_TWTR) ? CFG_PORT_WIDTH_TRTP : CFG_PORT_WIDTH_TWTR;
function [MAX_FUNCTION_PORT_WIDTH - 1 : 0] max;
input [MAX_FUNCTION_PORT_WIDTH - 1 : 0] value1;
input [MAX_FUNCTION_PORT_WIDTH - 1 : 0] value2;
begin
if (value1 > value2)
max = value1;
else
max = value2;
end
endfunction
//--------------------------------------------------------------------------------------------------------
//
// [END] Timing Parameter Calculation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_tck the_NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_sysclk the_NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_phy.sld_instance_index = 0,
// NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_phy.sld_ir_width = 2,
// NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_phy.sld_mfg_id = 70,
// NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_phy.sld_sim_action = "",
// NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_phy.sld_sim_n_scan = 0,
// NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_phy.sld_sim_total_length = 0,
// NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_phy.sld_type_id = 34,
// NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
//-----------------------------------------------------------------------------
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module hi_reader(
ck_1356meg,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
dbg,
subcarrier_frequency, minor_mode
);
input ck_1356meg;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
output dbg;
input [1:0] subcarrier_frequency;
input [3:0] minor_mode;
assign adc_clk = ck_1356meg; // sample frequency is 13,56 MHz
// When we're a reader, we just need to do the BPSK demod; but when we're an
// eavesdropper, we also need to pick out the commands sent by the reader,
// using AM. Do this the same way that we do it for the simulated tag.
reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev;
reg [11:0] has_been_low_for;
always @(negedge adc_clk)
begin
if(& adc_d[7:0]) after_hysteresis <= 1'b1;
else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
if(after_hysteresis)
begin
has_been_low_for <= 7'b0;
end
else
begin
if(has_been_low_for == 12'd4095)
begin
has_been_low_for <= 12'd0;
after_hysteresis <= 1'b1;
end
else
has_been_low_for <= has_been_low_for + 1;
end
end
// Let us report a correlation every 64 samples. I.e.
// one Q/I pair after 4 subcarrier cycles for the 848kHz subcarrier,
// one Q/I pair after 2 subcarrier cycles for the 424kHz subcarriers,
// one Q/I pair for each subcarrier cyle for the 212kHz subcarrier.
// We need a 6-bit counter for the timing.
reg [5:0] corr_i_cnt;
always @(negedge adc_clk)
begin
corr_i_cnt <= corr_i_cnt + 1;
end
// A couple of registers in which to accumulate the correlations. From the 64 samples
// we would add at most 32 times the difference between unmodulated and modulated signal. It should
// be safe to assume that a tag will not be able to modulate the carrier signal by more than 25%.
// 32 * 255 * 0,25 = 2040, which can be held in 11 bits. Add 1 bit for sign.
// Temporary we might need more bits. For the 212kHz subcarrier we could possible add 32 times the
// maximum signal value before a first subtraction would occur. 32 * 255 = 8160 can be held in 13 bits.
// Add one bit for sign -> need 14 bit registers but final result will fit into 12 bits.
reg signed [13:0] corr_i_accum;
reg signed [13:0] corr_q_accum;
// we will report maximum 8 significant bits
reg signed [7:0] corr_i_out;
reg signed [7:0] corr_q_out;
// the amplitude of the subcarrier is sqrt(ci^2 + cq^2).
// approximate by amplitude = max(|ci|,|cq|) + 1/2*min(|ci|,|cq|)
reg [13:0] corr_amplitude, abs_ci, abs_cq, max_ci_cq;
reg [12:0] min_ci_cq_2; // min_ci_cq / 2
always @(*)
begin
if (corr_i_accum[13] == 1'b0)
abs_ci <= corr_i_accum;
else
abs_ci <= -corr_i_accum;
if (corr_q_accum[13] == 1'b0)
abs_cq <= corr_q_accum;
else
abs_cq <= -corr_q_accum;
if (abs_ci > abs_cq)
begin
max_ci_cq <= abs_ci;
min_ci_cq_2 <= abs_cq / 2;
end
else
begin
max_ci_cq <= abs_cq;
min_ci_cq_2 <= abs_ci / 2;
end
corr_amplitude <= max_ci_cq + min_ci_cq_2;
end
// The subcarrier reference signals
reg subcarrier_I;
reg subcarrier_Q;
always @(*)
begin
if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_848_KHZ)
begin
subcarrier_I = ~corr_i_cnt[3];
subcarrier_Q = ~(corr_i_cnt[3] ^ corr_i_cnt[2]);
end
else if (subcarrier_frequency == `FPGA_HF_READER_SUBCARRIER_212_KHZ)
begin
subcarrier_I = ~corr_i_cnt[5];
subcarrier_Q = ~(corr_i_cnt[5] ^ corr_i_cnt[4]);
end
else
begin // 424 kHz
subcarrier_I = ~corr_i_cnt[4];
subcarrier_Q = ~(corr_i_cnt[4] ^ corr_i_cnt[3]);
end
end
// ADC data appears on the rising edge, so sample it on the falling edge
always @(negedge adc_clk)
begin
// These are the correlators: we correlate against in-phase and quadrature
// versions of our reference signal, and keep the (signed) results or the
// resulting amplitude to send out later over the SSP.
if (corr_i_cnt == 6'd0)
begin
if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE)
begin
// send amplitude plus 2 bits reader signal
corr_i_out <= corr_amplitude[13:6];
corr_q_out <= {corr_amplitude[5:0], after_hysteresis_prev_prev, after_hysteresis_prev};
end
else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ)
begin
// Send 7 most significant bits of in phase tag signal (signed), plus 1 bit reader signal
if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
else // truncate to maximum value
if (corr_i_accum[13] == 1'b0)
corr_i_out <= {7'b0111111, after_hysteresis_prev_prev};
else
corr_i_out <= {7'b1000000, after_hysteresis_prev_prev};
// Send 7 most significant bits of quadrature phase tag signal (signed), plus 1 bit reader signal
if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};
else // truncate to maximum value
if (corr_q_accum[13] == 1'b0)
corr_q_out <= {7'b0111111, after_hysteresis_prev};
else
corr_q_out <= {7'b1000000, after_hysteresis_prev};
end
else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE)
begin
// send amplitude
corr_i_out <= {2'b00, corr_amplitude[13:8]};
corr_q_out <= corr_amplitude[7:0];
end
else if (minor_mode == `FPGA_HF_READER_MODE_RECEIVE_IQ)
begin
// Send 8 bits of in phase tag signal
if (corr_i_accum[13:11] == 3'b000 || corr_i_accum[13:11] == 3'b111)
corr_i_out <= corr_i_accum[11:4];
else // truncate to maximum value
if (corr_i_accum[13] == 1'b0)
corr_i_out <= 8'b01111111;
else
corr_i_out <= 8'b10000000;
// Send 8 bits of quadrature phase tag signal
if (corr_q_accum[13:11] == 3'b000 || corr_q_accum[13:11] == 3'b111)
corr_q_out <= corr_q_accum[11:4];
else // truncate to maximum value
if (corr_q_accum[13] == 1'b0)
corr_q_out <= 8'b01111111;
else
corr_q_out <= 8'b10000000;
end
// for each Q/I pair report two reader signal samples when sniffing. Store the 1st.
after_hysteresis_prev_prev <= after_hysteresis;
// Initialize next correlation.
// Both I and Q reference signals are high when corr_i_nct == 0. Therefore need to accumulate.
corr_i_accum <= $signed({1'b0,adc_d});
corr_q_accum <= $signed({1'b0,adc_d});
end
else
begin
if (subcarrier_I)
corr_i_accum <= corr_i_accum + $signed({1'b0,adc_d});
else
corr_i_accum <= corr_i_accum - $signed({1'b0,adc_d});
if (subcarrier_Q)
corr_q_accum <= corr_q_accum + $signed({1'b0,adc_d});
else
corr_q_accum <= corr_q_accum - $signed({1'b0,adc_d});
end
// for each Q/I pair report two reader signal samples when sniffing. Store the 2nd.
if (corr_i_cnt == 6'd32)
after_hysteresis_prev <= after_hysteresis;
// Then the result from last time is serialized and send out to the ARM.
// We get one report each cycle, and each report is 16 bits, so the
// ssp_clk should be the adc_clk divided by 64/16 = 4.
// ssp_clk frequency = 13,56MHz / 4 = 3.39MHz
if (corr_i_cnt[1:0] == 2'b00)
begin
// Don't shift if we just loaded new data, obviously.
if (corr_i_cnt != 6'd0)
begin
corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
corr_q_out[7:1] <= corr_q_out[6:0];
end
end
end
// ssp clock and frame signal for communication to and from ARM
reg ssp_clk;
reg ssp_frame;
always @(negedge adc_clk)
begin
if (corr_i_cnt[1:0] == 2'b00)
ssp_clk <= 1'b1;
if (corr_i_cnt[1:0] == 2'b10)
ssp_clk <= 1'b0;
// set ssp_frame signal for corr_i_cnt = 1..3
// (send one frame with 16 Bits)
if (corr_i_cnt == 6'd1)
ssp_frame <= 1'b1;
if (corr_i_cnt == 6'd5)
ssp_frame <= 1'b0;
end
assign ssp_din = corr_i_out[7];
// a jamming signal
reg jam_signal;
reg [3:0] jam_counter;
always @(negedge adc_clk)
begin
if (corr_i_cnt == 6'd0)
begin
jam_counter <= jam_counter + 1;
jam_signal <= jam_counter[1] ^ jam_counter[3];
end
end
// Antenna drivers
reg pwr_hi, pwr_oe4;
always @(*)
begin
if (minor_mode == `FPGA_HF_READER_MODE_SEND_SHALLOW_MOD)
begin
pwr_hi = ck_1356meg;
pwr_oe4 = ssp_dout;
end
else if (minor_mode == `FPGA_HF_READER_MODE_SEND_FULL_MOD)
begin
pwr_hi = ck_1356meg & ~ssp_dout;
pwr_oe4 = 1'b0;
end
else if (minor_mode == `FPGA_HF_READER_MODE_SEND_JAM)
begin
pwr_hi = ck_1356meg & jam_signal;
pwr_oe4 = 1'b0;
end
else if (minor_mode == `FPGA_HF_READER_MODE_SNIFF_IQ
|| minor_mode == `FPGA_HF_READER_MODE_SNIFF_AMPLITUDE
|| minor_mode == `FPGA_HF_READER_MODE_SNIFF_PHASE)
begin // all off
pwr_hi = 1'b0;
pwr_oe4 = 1'b0;
end
else // receiving from tag
begin
pwr_hi = ck_1356meg;
pwr_oe4 = 1'b0;
end
end
// always on
assign pwr_oe1 = 1'b0;
assign pwr_oe3 = 1'b0;
// Unused.
assign pwr_lo = 1'b0;
assign pwr_oe2 = 1'b0;
// Debug Output
assign dbg = corr_i_cnt[3];
endmodule
|
Require Import Coq.Program.Basics.
Require Import MathClasses.interfaces.canonical_names.
Require Import TypeclassHierarchy.Util.FunctionSetoid.
(* math-classes uses (=) to denote equivalence, but we will use it for equality *)
Infix "=" := eq : type_scope.
Notation "(=)" := eq (only parsing) : mc_scope.
Notation "( x =)" := (eq x) (only parsing) : mc_scope.
Notation "(= x )" := (λ y, eq y x) (only parsing) : mc_scope.
(* Notation "(≠)" := (λ x y, ¬x = y) (only parsing) : mc_scope. *)
(* Notation "x ≠ y":= (¬x = y): type_scope. *)
(* Notation "( x ≠)" := (λ y, x ≠ y) (only parsing) : mc_scope. *)
(* Notation "(≠ x )" := (λ y, y ≠ x) (only parsing) : mc_scope. *)
(**
A functor contains data in such a way that a function can be applied uniformly
across the contained objects.
The functor follows three (classical) laws:
- fmap id = id
- fmap (g ∘ h) = (fmap g) ∘ (fmap h)
We additionally require that fmap is proper with respect to the equivalence
relation on functions, i.e. if f and g are extensionally equal, fmap f and
fmap g are as well.
A lot of the notation (e.g. setoid/extensional equality) is desugared here,
because Coq has trouble inferring the types.
We use Type rather than Set, as Functors must live in Set+1, and we want to be able to compose Functors.
*)
Class Functor (F : Type -> Type) : Type :=
{ fmap : forall {X Y : Type}, (X -> Y) -> F X -> F Y
; fmap_proper :
forall {A B : Type}, Proper ((@extensional_equality A B) ==>
(@extensional_equality (F A) (F B))) (@fmap A B)
; fmap_identity :
forall {A : Type}, @extensional_equality (F A) (F A) (@fmap A A id) id
; fmap_composition :
forall {A B C: Type} (h : A -> B) (g : B -> C),
@extensional_equality (F A) (F C) (@fmap A C (g ∘ h)) (@fmap B C g ∘ @fmap A B h)
}.
Arguments fmap {F} {Functor} {X} {Y} _ _.
(**
An apply is a halfway point between functor and applicative/bind. It's not very
useful in and of itself, but exists to unify the notation between binds and
applicatives.
In addition to the functor laws, an apply follows one more:
- ap g (ap f a) = ap (ap (fmap (∘) g) f) a
*)
Class Apply (F : Type -> Type) : Type :=
{ apply_functor : Functor F
; ap : forall {A B : Type}, F (A -> B) -> F A -> F B
; apply_composition :
forall {A B C : Type} (f : F (A -> B)) (g : F (B -> C)) (a : F A),
@ap B C g (@ap A B f a) = @ap A C (ap (fmap (∘) g) f) a
}.
(**
An applicative is a functor that also allows for both applying functions inside
the functor to arguments inside the functor, and embedding arbitrary objects in
the functor.
In addition to the apply laws, an applicative follows three others:
- ap (pure id) v = v
- ap (pure f) (pure x) = pure (f x)
- ap u (pure y) = ap (pure (fun f => f y)) u
- ap u (ap v w) = ap (pure (∘)) (ap u (ap v w))
As always, lot of the notation (e.g. setoid/extensional equality) is desugared
to reduce the need for (slow and somewhat unreliable) type inference.
In particular, we often have the following let clause:
"app := @ap F applicative_apply" which specializes the "ap" method to the
current functor. If this is confusing, just think of "app" as "ap".
*)
Class Applicative (F : Type -> Type) : Type :=
{ applicative_apply : Apply F
; pure : forall {A : Type}, A -> F A
(* ; pure_proper : *)
(* forall {A B : Type}, Proper (@extensional_equality A (F A)) (@pure A) *)
; ap_identity :
forall {A : Type} (a : F A),
@ap F applicative_apply A A (@pure (A -> A) id) a = a
; ap_homomorphism :
forall {A B : Type} (f : A -> B) (a : A),
let app := @ap F applicative_apply A B
in @app (@pure (A -> B) f) (@pure A a) = @pure B (f a)
; ap_interchange :
forall {A B : Type} (f : F (A -> B)) (a : A),
let app := @ap F applicative_apply
in @app A B f (pure a) = @app (A -> B) B (@pure ((A -> B) -> B) (fun g => g a)) f
; ap_composition :
forall {A B C : Type} (f : F (A -> B)) (g : F (B -> C)) (a : F A),
let app := @ap F applicative_apply
(* TODO: fill in more implicit args. I don't understand the types :( *)
in app B C g (app A B f a) = app A C (ap (ap (pure (∘)) g) f) a
}.
(**
A bind is an apply with an additional operation that takes the output of
one computation and feeds it into the next, composing the two in a chain.
In addition to the apply laws, binds must follow one other:
- bind (bind x f) g = bind x (fun y => bind (f y) g)
*)
Class Bind (F : Type -> Type) : Type :=
{ bind_apply : Apply F
; bind : forall {A B : Type}, F A -> (A -> F B) -> F B
; bind_associative :
forall {A B C : Type} (x : F A) (f : A -> F B) (g : B -> F C),
@bind B C (@bind A B x f) g = @bind A C x (fun y => @bind B C (f y) g)
}.
(**
A monad is a lot of things, but really just an applicative and a bind together.
It supports chaining of functions, and embedding of objects into the type
constructor.
In addition to the laws provided by apply and bind, it has identities:
- bind (pure x) f = f x
- bind x pure = x
*)
Class Monad (M : Type -> Type) : Type :=
{ monad_applicative : Applicative M
; monad_bind : Bind M
; monad_id_left : forall {A B : Type} (f : A -> M B) (x : A), bind (pure x) f = f x
; monad_id_right : forall {A B : Type} (f : A -> M B) (x : M A), bind x pure = x
}.
|
module inout_port(GO, clk, reset, iDATA, oReady, oDATA, SCL, SDA, ACK, ctr);
input GO; // output enable
input clk;
input reset;
input [23:0] iDATA;
output oReady;
output oDATA;
output SCL;
inout SDA;
output ACK;
output [5:0] ctr;
reg a; // output data
wire a_z;
reg b; // input data
wire next_b;
wire ACK;
reg CLK_Disable;
reg RW;
reg END;
assign a_z = a? 1'b1:0;
assign SDA = RW? a_z: 1'bz;
assign SCL = CLK_Disable | ( ( (SD_Counter >= 4) & (SD_Counter <= 31))? ~clk:0);
assign ACK = b;
assign next_b = RW?1:SDA;
// states
//parameter S_START = 2'd0;
//parameter S_SEND = 2'd1;
//parameter S_WAIT = 2'd2;
//parameter S_FIN = 2'd3;
reg [5:0] SD_Counter;
wire [5:0] next_SD_Counter;
wire [5:0] ctr;
reg [23:0] SD;
reg FAIL;
// combinational circuit
assign oReady = END;
assign next_SD_Counter = FAIL?32:SD_Counter + 1;
assign ctr = SD_Counter;
//-----------------------------------
always @(negedge reset or negedge clk )
begin
if (!reset)
begin
SD_Counter = 6'b111111;
end
else begin
if (GO == 1)
begin
SD_Counter = 0;
end
else begin
if (SD_Counter < 6'b111111)
begin
SD_Counter = next_SD_Counter;
end
else
SD_Counter = 6'b111111;
end
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
CLK_Disable = 1;
a = 1;
//b = 1'bz;
END = 1;
RW = 0;
FAIL = 0;
end
else begin
case(SD_Counter)
6'd0: begin
END = 0;
CLK_Disable = 1;
a = 1;
RW = 1;
FAIL = 0;
end
6'd1: begin
SD = iDATA;
RW = 1;
a = 0;
end
6'd2: CLK_Disable = 0;
6'd3: begin
FAIL = 0;
a = SD[23];
end
6'd4: a = SD[22];
6'd5: a = SD[21];
6'd6: a = SD[20];
6'd7: a = SD[19];
6'd8: a = SD[18];
6'd9: a = SD[17];
6'd10: a = SD[16];
6'd11: RW = 0;
6'd12: begin
RW = 1;
if (b != 0)
FAIL = 1;
else FAIL = 0;
a = SD[15];
end
6'd13: a = SD[14];
6'd14: a = SD[13];
6'd15: a = SD[12];
6'd16: a = SD[11];
6'd17: a = SD[10];
6'd18: a = SD[9];
6'd19: a = SD[8];
6'd20: RW = 0;
6'd21: begin
RW = 1;
if (b != 0)
FAIL = 1;
else FAIL = 0;
a = SD[7];
end
6'd22: a = SD[6];
6'd23: a = SD[5];
6'd24: a = SD[4];
6'd25: a = SD[3];
6'd26: a = SD[2];
6'd27: a = SD[1];
6'd28: a = SD[0];
6'd29: RW = 0;
6'd30: begin
RW = 1;
if (b != 0)
FAIL = 1;
else FAIL = 0;
a =0;
end
6'd31: begin
a = 0;
CLK_Disable = 1;
end
6'd32: begin
a = 1;
END = 1;
RW = 0;
end
endcase
end
end
always @(negedge clk) begin
b = RW?next_b:SDA;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311O_SYMBOL_V
`define SKY130_FD_SC_HD__A311O_SYMBOL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a311o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311O_SYMBOL_V
|
/*****************************************************************************/
//
// Module : cae_pers.v
// Last Modified On: 2013/07/22 14:37
// Last Modified By: Osama Attia
//
//-----------------------------------------------------------------------------
//
// Original Author : gedwards
// Created On : Wed Oct 10 09:26:08 2007
// TODO: add author information
//-----------------------------------------------------------------------------
//
// Description : parallelCyGraph personality
//
// Top-level of parallelCyGraph personality. For a complete list of
// optional ports, see
// /opt/convey/pdk/<rev>/<platform>/doc/cae_pers.v
//
//-----------------------------------------------------------------------------
//
// Copyright (c) 2007-2011 : created by Convey Computer Corp. This model is the
// confidential and proprietary property of Convey Computer Corp.
//
/*****************************************************************************/
/* $Id: cae_pers.v,v 1.4.1.4 2012/03/07 15:41:55 ktown Exp ktown $ */
`timescale 1 ns / 1 ps
`include "pdk_fpga_defines.vh"
(* keep_hierarchy = "true" *)
module cae_pers (
input clk_csr,
input clk,
input clk2x,
input i_reset,
input i_csr_reset_n,
input [1:0] i_aeid,
input ppll_reset,
output ppll_locked,
output clk_per,
//
// Dispatch Interface
//
input [31:0] cae_inst,
input [63:0] cae_data,
input cae_inst_vld,
output [17:0] cae_aeg_cnt,
output [15:0] cae_exception,
output [63:0] cae_ret_data,
output cae_ret_data_vld,
output cae_idle,
output cae_stall,
//
// MC Interface(s)
//
output mc0_req_ld_e, mc0_req_ld_o,
output mc0_req_st_e, mc0_req_st_o,
output [1:0] mc0_req_size_e, mc0_req_size_o,
output [47:0] mc0_req_vadr_e, mc0_req_vadr_o,
output [63:0] mc0_req_wrd_rdctl_e, mc0_req_wrd_rdctl_o,
output mc0_rsp_stall_e, mc0_rsp_stall_o,
input mc0_rd_rq_stall_e, mc0_rd_rq_stall_o,
input mc0_wr_rq_stall_e, mc0_wr_rq_stall_o,
input [63:0] mc0_rsp_data_e, mc0_rsp_data_o,
input mc0_rsp_push_e, mc0_rsp_push_o,
input [31:0] mc0_rsp_rdctl_e, mc0_rsp_rdctl_o,
output mc1_req_ld_e, mc1_req_ld_o,
output mc1_req_st_e, mc1_req_st_o,
output [1:0] mc1_req_size_e, mc1_req_size_o,
output [47:0] mc1_req_vadr_e, mc1_req_vadr_o,
output [63:0] mc1_req_wrd_rdctl_e, mc1_req_wrd_rdctl_o,
output mc1_rsp_stall_e, mc1_rsp_stall_o,
input mc1_rd_rq_stall_e, mc1_rd_rq_stall_o,
input mc1_wr_rq_stall_e, mc1_wr_rq_stall_o,
input [63:0] mc1_rsp_data_e, mc1_rsp_data_o,
input mc1_rsp_push_e, mc1_rsp_push_o,
input [31:0] mc1_rsp_rdctl_e, mc1_rsp_rdctl_o,
output mc2_req_ld_e, mc2_req_ld_o,
output mc2_req_st_e, mc2_req_st_o,
output [1:0] mc2_req_size_e, mc2_req_size_o,
output [47:0] mc2_req_vadr_e, mc2_req_vadr_o,
output [63:0] mc2_req_wrd_rdctl_e, mc2_req_wrd_rdctl_o,
output mc2_rsp_stall_e, mc2_rsp_stall_o,
input mc2_rd_rq_stall_e, mc2_rd_rq_stall_o,
input mc2_wr_rq_stall_e, mc2_wr_rq_stall_o,
input [63:0] mc2_rsp_data_e, mc2_rsp_data_o,
input mc2_rsp_push_e, mc2_rsp_push_o,
input [31:0] mc2_rsp_rdctl_e, mc2_rsp_rdctl_o,
output mc3_req_ld_e, mc3_req_ld_o,
output mc3_req_st_e, mc3_req_st_o,
output [1:0] mc3_req_size_e, mc3_req_size_o,
output [47:0] mc3_req_vadr_e, mc3_req_vadr_o,
output [63:0] mc3_req_wrd_rdctl_e, mc3_req_wrd_rdctl_o,
output mc3_rsp_stall_e, mc3_rsp_stall_o,
input mc3_rd_rq_stall_e, mc3_rd_rq_stall_o,
input mc3_wr_rq_stall_e, mc3_wr_rq_stall_o,
input [63:0] mc3_rsp_data_e, mc3_rsp_data_o,
input mc3_rsp_push_e, mc3_rsp_push_o,
input [31:0] mc3_rsp_rdctl_e, mc3_rsp_rdctl_o,
output mc4_req_ld_e, mc4_req_ld_o,
output mc4_req_st_e, mc4_req_st_o,
output [1:0] mc4_req_size_e, mc4_req_size_o,
output [47:0] mc4_req_vadr_e, mc4_req_vadr_o,
output [63:0] mc4_req_wrd_rdctl_e, mc4_req_wrd_rdctl_o,
output mc4_rsp_stall_e, mc4_rsp_stall_o,
input mc4_rd_rq_stall_e, mc4_rd_rq_stall_o,
input mc4_wr_rq_stall_e, mc4_wr_rq_stall_o,
input [63:0] mc4_rsp_data_e, mc4_rsp_data_o,
input mc4_rsp_push_e, mc4_rsp_push_o,
input [31:0] mc4_rsp_rdctl_e, mc4_rsp_rdctl_o,
output mc5_req_ld_e, mc5_req_ld_o,
output mc5_req_st_e, mc5_req_st_o,
output [1:0] mc5_req_size_e, mc5_req_size_o,
output [47:0] mc5_req_vadr_e, mc5_req_vadr_o,
output [63:0] mc5_req_wrd_rdctl_e, mc5_req_wrd_rdctl_o,
output mc5_rsp_stall_e, mc5_rsp_stall_o,
input mc5_rd_rq_stall_e, mc5_rd_rq_stall_o,
input mc5_wr_rq_stall_e, mc5_wr_rq_stall_o,
input [63:0] mc5_rsp_data_e, mc5_rsp_data_o,
input mc5_rsp_push_e, mc5_rsp_push_o,
input [31:0] mc5_rsp_rdctl_e, mc5_rsp_rdctl_o,
output mc6_req_ld_e, mc6_req_ld_o,
output mc6_req_st_e, mc6_req_st_o,
output [1:0] mc6_req_size_e, mc6_req_size_o,
output [47:0] mc6_req_vadr_e, mc6_req_vadr_o,
output [63:0] mc6_req_wrd_rdctl_e, mc6_req_wrd_rdctl_o,
output mc6_rsp_stall_e, mc6_rsp_stall_o,
input mc6_rd_rq_stall_e, mc6_rd_rq_stall_o,
input mc6_wr_rq_stall_e, mc6_wr_rq_stall_o,
input [63:0] mc6_rsp_data_e, mc6_rsp_data_o,
input mc6_rsp_push_e, mc6_rsp_push_o,
input [31:0] mc6_rsp_rdctl_e, mc6_rsp_rdctl_o,
output mc7_req_ld_e, mc7_req_ld_o,
output mc7_req_st_e, mc7_req_st_o,
output [1:0] mc7_req_size_e, mc7_req_size_o,
output [47:0] mc7_req_vadr_e, mc7_req_vadr_o,
output [63:0] mc7_req_wrd_rdctl_e, mc7_req_wrd_rdctl_o,
output mc7_rsp_stall_e, mc7_rsp_stall_o,
input mc7_rd_rq_stall_e, mc7_rd_rq_stall_o,
input mc7_wr_rq_stall_e, mc7_wr_rq_stall_o,
input [63:0] mc7_rsp_data_e, mc7_rsp_data_o,
input mc7_rsp_push_e, mc7_rsp_push_o,
input [31:0] mc7_rsp_rdctl_e, mc7_rsp_rdctl_o,
//
// Write flush
//
output mc0_req_flush_e, mc0_req_flush_o,
input mc0_rsp_flush_cmplt_e, mc0_rsp_flush_cmplt_o,
output mc1_req_flush_e, mc1_req_flush_o,
input mc1_rsp_flush_cmplt_e, mc1_rsp_flush_cmplt_o,
output mc2_req_flush_e, mc2_req_flush_o,
input mc2_rsp_flush_cmplt_e, mc2_rsp_flush_cmplt_o,
output mc3_req_flush_e, mc3_req_flush_o,
input mc3_rsp_flush_cmplt_e, mc3_rsp_flush_cmplt_o,
output mc4_req_flush_e, mc4_req_flush_o,
input mc4_rsp_flush_cmplt_e, mc4_rsp_flush_cmplt_o,
output mc5_req_flush_e, mc5_req_flush_o,
input mc5_rsp_flush_cmplt_e, mc5_rsp_flush_cmplt_o,
output mc6_req_flush_e, mc6_req_flush_o,
input mc6_rsp_flush_cmplt_e, mc6_rsp_flush_cmplt_o,
output mc7_req_flush_e, mc7_req_flush_o,
input mc7_rsp_flush_cmplt_e, mc7_rsp_flush_cmplt_o,
//
// AE-to-AE Interface
//
//`ifdef AE_AE_IF
input [31:0] nxtae_rx_data, prvae_rx_data,
input nxtae_rx_vld, prvae_rx_vld,
output nxtae_rx_stall, prvae_rx_stall,
output [31:0] nxtae_tx_data, prvae_tx_data,
output nxtae_tx_vld, prvae_tx_vld,
input nxtae_tx_stall, prvae_tx_stall,
output [65:0] prvae_nd0_tx_data,
output prvae_nd0_tx_vld,
input prvae_nd0_tx_stall,
input [65:0] nxtae_nd0_rx_data,
input nxtae_nd0_rx_vld,
output nxtae_nd0_rx_stall,
output [65 :0] prvae_nd1_tx_data,
output prvae_nd1_tx_vld,
input prvae_nd1_tx_stall,
input [65 :0] nxtae_nd1_rx_data,
input nxtae_nd1_rx_vld,
output nxtae_nd1_rx_stall,
//`endif
//
// Management/Debug Interface
//
input [3:0] cae_ring_ctl_in,
input [15:0] cae_ring_data_in,
output [3:0] cae_ring_ctl_out,
output [15:0] cae_ring_data_out,
input csr_31_31_intlv_dis
);
initial $display("starting cae personality aeid:%d\n", i_aeid);
`include "pdk_fpga_param.vh"
//
// Local clock generation
//
(* KEEP = "true" *) wire reset_per;
cae_clock clock (
.clk(clk),
.i_reset(i_reset),
.ppll_reset(ppll_reset),
.clk_per(clk_per),
.ppll_locked(ppll_locked),
.reset_per(reset_per)
);
//
// Instruction decode
//
wire [4:0] inst_caep;
wire [17:0] inst_aeg_idx;
instdec dec (
.cae_inst(cae_inst),
.cae_data(cae_data),
.cae_inst_vld(cae_inst_vld),
.inst_val(inst_val),
.inst_caep(inst_caep),
.inst_aeg_wr(inst_aeg_wr),
.inst_aeg_rd(inst_aeg_rd),
.inst_aeg_idx(inst_aeg_idx),
.err_unimpl(err_unimpl)
);
//**************************************************************************
// PERSONALITY SPECIFIC LOGIC
//**************************************************************************
//
// AEG[0..NA-1] Registers
//
localparam NA = 51;
localparam NB = 6; // Number of bits to represent NAEG
assign cae_aeg_cnt = NA;
//output of aeg registers
wire [63:0] w_aeg[NA-1:0];
// CyGraph registers
wire cygraph_enable;
wire cygraph_busy;
wire cygraph_done;
wire [63:0] nq_count;
// SCC intersection registers
wire scc_enable;
wire scc_busy;
wire scc_done;
wire [63:0] scc_nextv;
genvar g;
generate for (g=0; g<NA; g=g+1) begin : g0
reg [63:0] c_aeg, r_aeg;
always @* begin
case (g)
//TODO: add cases for registers to be written to
8: c_aeg = (cygraph_busy || cygraph_done) ? nq_count[63:0] : r_aeg; // c_aeg = cygraph_done ? nq_count[63:0] : r_aeg;
9: c_aeg = (scc_busy || scc_done) ? scc_nextv[63:0] : r_aeg; // c_aeg = scc_done ? scc_nextv[63:0] : r_aeg;
default: c_aeg = r_aeg;
endcase
end
wire c_aeg_we = inst_aeg_wr && inst_aeg_idx[NB-1:0] == g;
always @(posedge clk) begin
if (c_aeg_we) begin
r_aeg <= cae_data;
$display("writing: %x", cae_data);
end
else
r_aeg <= c_aeg;
end
assign w_aeg[g] = r_aeg;
end endgenerate
reg r_ret_val, r_err_unimpl, r_err_aegidx;
reg [63:0] r_ret_data;
wire c_val_aegidx = inst_aeg_idx < NA;
//return logic
always @(posedge clk) begin
r_ret_val <= inst_aeg_rd && c_val_aegidx;
r_ret_data <= w_aeg[inst_aeg_idx[NB-1:0]];
r_err_aegidx <= (inst_aeg_wr || inst_aeg_rd) && !c_val_aegidx;
//TODO: add logic to decide which instructions are implemented -- OSAMA
r_err_unimpl <= err_unimpl || (inst_val && (inst_caep !== 'd0 && inst_caep !== 'd1 /* && inst_caep !== 'd2*/));
end
assign cae_ret_data_vld = r_ret_val;
assign cae_ret_data = r_ret_data;
assign cae_exception[1:0] = {r_err_aegidx, r_err_unimpl};
// ISE can have issues with global wires attached to D(flop)/I(lut) inputs
wire r_reset;
FDSE rst (.C(clk_per),.S(reset_per),.CE(r_reset),.D(!r_reset),.Q(r_reset));
// start triggering CyGraph, SCC_intersection
reg cy_en, scc_en;
reg cy_en_temp, scc_en_temp;
// CyGraph input signals
reg [63:0] cy_n;
reg [63:0] non_zeros;
reg [63:0] graphData;
reg [63:0] graphInfo;
reg [63:0] queue1_address;
reg [63:0] queue2_address;
reg [63:0] current_level;
reg [63:0] cq_count;
reg [63:0] reach_queue;
// SCC input parameters
reg [63:0] scc_results;
reg [63:0] scc_graphInfo;
reg [63:0] scc_rgraphInfo;
reg [63:0] scc_fw_addr;
reg [63:0] scc_fw_count;
reg [63:0] scc_bw_addr;
reg [63:0] scc_bw_count;
reg [63:0] scc_N;
reg [63:0] scc_color;
always @(posedge clk) begin
if(inst_caep == 5'd0 && inst_val) begin
// start logic for custom instruction
$display("@simulation: Hello World from simulated CyGraph ae%d", i_aeid);
cy_en_temp <= 1'b1;
scc_en_temp <= 1'b0;
cy_n <= w_aeg[0];
non_zeros <= w_aeg[1];
graphData <= w_aeg[2];
graphInfo <= w_aeg[3];
queue1_address <= w_aeg[4];
queue2_address <= w_aeg[5];
current_level <= 64'b1; // assign current_level = w_aeg[6];
reach_queue <= w_aeg[6];
cq_count <= w_aeg[7];
$display("@simulation: CyGraph hardware got enabled!");
end
else if(inst_caep == 5'd1 && inst_val) begin
$display("@simulation: Hello World from simulated SCC ae%d", i_aeid);
cy_en_temp <= 1'b0;
scc_en_temp <= 1'b1;
scc_results <= w_aeg[0];
scc_graphInfo <= w_aeg[1];
scc_rgraphInfo <= w_aeg[2];
scc_fw_addr <= w_aeg[3];
scc_fw_count <= w_aeg[4];
scc_bw_addr <= w_aeg[5];
scc_bw_count <= w_aeg[6];
scc_color <= w_aeg[7];
scc_N <= w_aeg[8];
$display("@simulation: SCC Intersection hardware got enabled!");
end
else begin
// $display("@simulation: Unimplemented instruction!");
cy_en_temp <= 1'b0;
scc_en_temp <= 1'b0;
end
cy_en <= cy_en_temp;
scc_en <= scc_en_temp;
end
assign cygraph_enable = cy_en;
assign scc_enable = scc_en;
wire inter_enable = cy_en || cy_en_temp || scc_en || scc_en_temp;
//logic for using cae IMPORTANT. cae_idle should be 0 when executing a custom instruction and 1 otherwise.
//cae_stall should be 1 when when exectuting a custom instruction and 0 otherwise.
// assign cae_idle = 1'b1;
// assign cae_stall = 1'b0;
wire c_caep00, c_caep01;
reg r_caep00, r_caep01;
assign c_caep00 = (inst_caep == 5'd0) && inst_val;
assign c_caep01 = (inst_caep == 5'd1) && inst_val;
always @(posedge clk) begin
r_caep00 <= c_caep00;
r_caep01 <= c_caep01;
end
assign cae_idle = !r_caep00 && !r_caep01 && !cygraph_busy && !scc_busy && !inter_enable;
assign cae_stall = c_caep00 || c_caep01 || r_caep00 || r_caep01 || cygraph_busy || scc_busy || inter_enable;
wire full_reset = r_reset || inst_val;
//
// default state
//
assign cae_ring_ctl_out = cae_ring_ctl_in;
assign cae_ring_data_out = cae_ring_data_in;
assign nxtae_rx_stall = 1'b0;
assign prvae_rx_stall = 1'b0;
// assign nxtae_tx_data = 32'b0;
// assign prvae_tx_data = 32'b0;
// assign nxtae_tx_vld = 1'b0;
// assign prvae_tx_vld = 1'b0;
assign prvae_nd0_tx_data = 66'b0;
assign prvae_nd0_tx_vld = 1'b0;
assign nxtae_nd0_rx_stall = 1'b0;
assign prvae_nd1_tx_data = 66'b0;
assign prvae_nd1_tx_vld = 1'b0;
assign nxtae_nd1_rx_stall = 1'b0;
// assign mc0_req_ld_e = 1'b0;
// assign mc0_req_st_e = 1'b0;
// assign mc0_req_wrd_rdctl_e = 64'd0;
// assign mc0_req_vadr_e = 48'd0;
// assign mc0_req_size_e = 2'd0;
// assign mc0_req_flush_e = 1'b0;
// assign mc0_rsp_stall_e = 1'b0;
// assign mc0_req_ld_o = 1'b0;
// assign mc0_req_st_o = 1'b0;
// assign mc0_req_wrd_rdctl_o = 64'd0;
// assign mc0_req_vadr_o = 48'd0;
// assign mc0_req_size_o = 2'd0;
// assign mc0_req_flush_o = 1'b0;
// assign mc0_rsp_stall_o = 1'b0;
// assign mc1_req_ld_e = 1'b0;
// assign mc1_req_st_e = 1'b0;
// assign mc1_req_wrd_rdctl_e = 64'd0;
// assign mc1_req_vadr_e = 48'd0;
// assign mc1_req_size_e = 2'd0;
// assign mc1_req_flush_e = 1'b0;
// assign mc1_rsp_stall_e = 1'b0;
// assign mc1_req_ld_o = 1'b0;
// assign mc1_req_st_o = 1'b0;
// assign mc1_req_wrd_rdctl_o = 64'd0;
// assign mc1_req_vadr_o = 48'd0;
// assign mc1_req_size_o = 2'd0;
// assign mc1_req_flush_o = 1'b0;
// assign mc1_rsp_stall_o = 1'b0;
// assign mc2_req_ld_e = 1'b0;
// assign mc2_req_st_e = 1'b0;
// assign mc2_req_wrd_rdctl_e = 64'd0;
// assign mc2_req_vadr_e = 48'd0;
// assign mc2_req_size_e = 2'd0;
// assign mc2_req_flush_e = 1'b0;
// assign mc2_rsp_stall_e = 1'b0;
// assign mc2_req_ld_o = 1'b0;
// assign mc2_req_st_o = 1'b0;
// assign mc2_req_wrd_rdctl_o = 64'd0;
// assign mc2_req_vadr_o = 48'd0;
// assign mc2_req_size_o = 2'd0;
// assign mc2_req_flush_o = 1'b0;
// assign mc2_rsp_stall_o = 1'b0;
// assign mc3_req_ld_e = 1'b0;
// assign mc3_req_st_e = 1'b0;
// assign mc3_req_wrd_rdctl_e = 64'd0;
// assign mc3_req_vadr_e = 48'd0;
// assign mc3_req_size_e = 2'd0;
// assign mc3_req_flush_e = 1'b0;
// assign mc3_rsp_stall_e = 1'b0;
// assign mc3_req_ld_o = 1'b0;
// assign mc3_req_st_o = 1'b0;
// assign mc3_req_wrd_rdctl_o = 64'd0;
// assign mc3_req_vadr_o = 48'd0;
// assign mc3_req_size_o = 2'd0;
// assign mc3_req_flush_o = 1'b0;
// assign mc3_rsp_stall_o = 1'b0;
// assign mc4_req_ld_e = 1'b0;
// assign mc4_req_st_e = 1'b0;
// assign mc4_req_wrd_rdctl_e = 64'd0;
// assign mc4_req_vadr_e = 48'd0;
// assign mc4_req_size_e = 2'd0;
// assign mc4_req_flush_e = 1'b0;
// assign mc4_rsp_stall_e = 1'b0;
// assign mc4_req_ld_o = 1'b0;
// assign mc4_req_st_o = 1'b0;
// assign mc4_req_wrd_rdctl_o = 64'd0;
// assign mc4_req_vadr_o = 48'd0;
// assign mc4_req_size_o = 2'd0;
// assign mc4_req_flush_o = 1'b0;
// assign mc4_rsp_stall_o = 1'b0;
// assign mc5_req_ld_e = 1'b0;
// assign mc5_req_st_e = 1'b0;
// assign mc5_req_wrd_rdctl_e = 64'd0;
// assign mc5_req_vadr_e = 48'd0;
// assign mc5_req_size_e = 2'd0;
// assign mc5_req_flush_e = 1'b0;
// assign mc5_rsp_stall_e = 1'b0;
// assign mc5_req_ld_o = 1'b0;
// assign mc5_req_st_o = 1'b0;
// assign mc5_req_wrd_rdctl_o = 64'd0;
// assign mc5_req_vadr_o = 48'd0;
// assign mc5_req_size_o = 2'd0;
// assign mc5_req_flush_o = 1'b0;
// assign mc5_rsp_stall_o = 1'b0;
// assign mc6_req_ld_e = 1'b0;
// assign mc6_req_st_e = 1'b0;
// assign mc6_req_wrd_rdctl_e = 64'd0;
// assign mc6_req_vadr_e = 48'd0;
// assign mc6_req_size_e = 2'd0;
// assign mc6_req_flush_e = 1'b0;
// assign mc6_rsp_stall_e = 1'b0;
// assign mc6_req_ld_o = 1'b0;
// assign mc6_req_st_o = 1'b0;
// assign mc6_req_wrd_rdctl_o = 64'd0;
// assign mc6_req_vadr_o = 48'd0;
// assign mc6_req_size_o = 2'd0;
// assign mc6_req_flush_o = 1'b0;
// assign mc6_rsp_stall_o = 1'b0;
// assign mc7_req_ld_e = 1'b0;
// assign mc7_req_st_e = 1'b0;
// assign mc7_req_wrd_rdctl_e = 64'd0;
// assign mc7_req_vadr_e = 48'd0;
// assign mc7_req_size_e = 2'd0;
// assign mc7_req_flush_e = 1'b0;
// assign mc7_rsp_stall_e = 1'b0;
// assign mc7_req_ld_o = 1'b0;
// assign mc7_req_st_o = 1'b0;
// assign mc7_req_wrd_rdctl_o = 64'd0;
// assign mc7_req_vadr_o = 48'd0;
// assign mc7_req_size_o = 2'd0;
// assign mc7_req_flush_o = 1'b0;
// assign mc7_rsp_stall_o = 1'b0;
// CyGraph BFS arguments
// AE-to-AE interface
wire [31:0] cy_nxtae_tx_data;
wire cy_nxtae_tx_vld;
wire [31:0] cy_prvae_tx_data;
wire cy_prvae_tx_vld;
// MC0 even request port signals
wire cy_mc0_req_ld_e;
wire cy_mc0_req_st_e;
wire [1:0] cy_mc0_req_size_e;
wire [47:0] cy_mc0_req_vadr_e;
wire [63:0] cy_mc0_req_wrd_rdctl_e;
wire cy_mc0_req_flush_e;
// MC0 even response port signals
wire cy_mc0_rsp_stall_e;
// MC0 odd request port signals
wire cy_mc0_req_ld_o;
wire cy_mc0_req_st_o;
wire [1:0] cy_mc0_req_size_o;
wire [47:0] cy_mc0_req_vadr_o;
wire [63:0] cy_mc0_req_wrd_rdctl_o;
wire cy_mc0_req_flush_o;
// MC0 odd response port signals
wire cy_mc0_rsp_stall_o;
// MC1 even request port signals
wire cy_mc1_req_ld_e;
wire cy_mc1_req_st_e;
wire [1:0] cy_mc1_req_size_e;
wire [47:0] cy_mc1_req_vadr_e;
wire [63:0] cy_mc1_req_wrd_rdctl_e;
wire cy_mc1_req_flush_e;
// MC1 even response port signals
wire cy_mc1_rsp_stall_e;
// MC1 odd request port signals
wire cy_mc1_req_ld_o;
wire cy_mc1_req_st_o;
wire [1:0] cy_mc1_req_size_o;
wire [47:0] cy_mc1_req_vadr_o;
wire [63:0] cy_mc1_req_wrd_rdctl_o;
wire cy_mc1_req_flush_o;
// MC1 odd response port signals
wire cy_mc1_rsp_stall_o;
// MC2 even request port signals
wire cy_mc2_req_ld_e;
wire cy_mc2_req_st_e;
wire [1:0] cy_mc2_req_size_e;
wire [47:0] cy_mc2_req_vadr_e;
wire [63:0] cy_mc2_req_wrd_rdctl_e;
wire cy_mc2_req_flush_e;
// MC2 even response port signals
wire cy_mc2_rsp_stall_e;
// MC2 odd request port signals
wire cy_mc2_req_ld_o;
wire cy_mc2_req_st_o;
wire [1:0] cy_mc2_req_size_o;
wire [47:0] cy_mc2_req_vadr_o;
wire [63:0] cy_mc2_req_wrd_rdctl_o;
wire cy_mc2_req_flush_o;
// MC2 odd response port signals
wire cy_mc2_rsp_stall_o;
// MC3 even request port signals
wire cy_mc3_req_ld_e;
wire cy_mc3_req_st_e;
wire [1:0] cy_mc3_req_size_e;
wire [47:0] cy_mc3_req_vadr_e;
wire [63:0] cy_mc3_req_wrd_rdctl_e;
wire cy_mc3_req_flush_e;
// MC3 even response port signals
wire cy_mc3_rsp_stall_e;
// MC3 odd request port signals
wire cy_mc3_req_ld_o;
wire cy_mc3_req_st_o;
wire [1:0] cy_mc3_req_size_o;
wire [47:0] cy_mc3_req_vadr_o;
wire [63:0] cy_mc3_req_wrd_rdctl_o;
wire cy_mc3_req_flush_o;
// MC3 odd response port signals
wire cy_mc3_rsp_stall_o;
// MC4 even request port signals
wire cy_mc4_req_ld_e;
wire cy_mc4_req_st_e;
wire [1:0] cy_mc4_req_size_e;
wire [47:0] cy_mc4_req_vadr_e;
wire [63:0] cy_mc4_req_wrd_rdctl_e;
wire cy_mc4_req_flush_e;
// MC4 even response port signals
wire cy_mc4_rsp_stall_e;
// MC4 odd request port signals
wire cy_mc4_req_ld_o;
wire cy_mc4_req_st_o;
wire [1:0] cy_mc4_req_size_o;
wire [47:0] cy_mc4_req_vadr_o;
wire [63:0] cy_mc4_req_wrd_rdctl_o;
wire cy_mc4_req_flush_o;
// MC4 odd response port signals
wire cy_mc4_rsp_stall_o;
// MC5 even request port signals
wire cy_mc5_req_ld_e;
wire cy_mc5_req_st_e;
wire [1:0] cy_mc5_req_size_e;
wire [47:0] cy_mc5_req_vadr_e;
wire [63:0] cy_mc5_req_wrd_rdctl_e;
wire cy_mc5_req_flush_e;
// MC5 even response port signals
wire cy_mc5_rsp_stall_e;
// MC5 odd request port signals
wire cy_mc5_req_ld_o;
wire cy_mc5_req_st_o;
wire [1:0] cy_mc5_req_size_o;
wire [47:0] cy_mc5_req_vadr_o;
wire [63:0] cy_mc5_req_wrd_rdctl_o;
wire cy_mc5_req_flush_o;
// MC5 odd response port signals
wire cy_mc5_rsp_stall_o;
// MC6 even request port signals
wire cy_mc6_req_ld_e;
wire cy_mc6_req_st_e;
wire [1:0] cy_mc6_req_size_e;
wire [47:0] cy_mc6_req_vadr_e;
wire [63:0] cy_mc6_req_wrd_rdctl_e;
wire cy_mc6_req_flush_e;
// MC6 even response port signals
wire cy_mc6_rsp_stall_e;
// MC6 odd request port signals
wire cy_mc6_req_ld_o;
wire cy_mc6_req_st_o;
wire [1:0] cy_mc6_req_size_o;
wire [47:0] cy_mc6_req_vadr_o;
wire [63:0] cy_mc6_req_wrd_rdctl_o;
wire cy_mc6_req_flush_o;
// MC6 odd response port signals
wire cy_mc6_rsp_stall_o;
// MC7 even request port signals
wire cy_mc7_req_ld_e;
wire cy_mc7_req_st_e;
wire [1:0] cy_mc7_req_size_e;
wire [47:0] cy_mc7_req_vadr_e;
wire [63:0] cy_mc7_req_wrd_rdctl_e;
wire cy_mc7_req_flush_e;
// MC7 even response port signals
wire cy_mc7_rsp_stall_e;
// MC7 odd request port signals
wire cy_mc7_req_ld_o;
wire cy_mc7_req_st_o;
wire [1:0] cy_mc7_req_size_o;
wire [47:0] cy_mc7_req_vadr_o;
wire [63:0] cy_mc7_req_wrd_rdctl_o;
wire cy_mc7_req_flush_o;
// MC7 odd response port signals
wire cy_mc7_rsp_stall_o;
// SCC Intersection arguments
// AE-to-AE interface
wire [31:0] scc_nxtae_tx_data;
wire scc_nxtae_tx_vld;
wire [31:0] scc_prvae_tx_data;
wire scc_prvae_tx_vld;
// MC0 even request port signals
wire scc_mc0_req_ld_e;
wire scc_mc0_req_st_e;
wire [1:0] scc_mc0_req_size_e;
wire [47:0] scc_mc0_req_vadr_e;
wire [63:0] scc_mc0_req_wrd_rdctl_e;
wire scc_mc0_req_flush_e;
// MC0 even response port signals
wire scc_mc0_rsp_stall_e;
// MC0 odd request port signals
wire scc_mc0_req_ld_o;
wire scc_mc0_req_st_o;
wire [1:0] scc_mc0_req_size_o;
wire [47:0] scc_mc0_req_vadr_o;
wire [63:0] scc_mc0_req_wrd_rdctl_o;
wire scc_mc0_req_flush_o;
// MC0 odd response port signals
wire scc_mc0_rsp_stall_o;
// MC1 even request port signals
wire scc_mc1_req_ld_e;
wire scc_mc1_req_st_e;
wire [1:0] scc_mc1_req_size_e;
wire [47:0] scc_mc1_req_vadr_e;
wire [63:0] scc_mc1_req_wrd_rdctl_e;
wire scc_mc1_req_flush_e;
// MC1 even response port signals
wire scc_mc1_rsp_stall_e;
// MC1 odd request port signals
wire scc_mc1_req_ld_o;
wire scc_mc1_req_st_o;
wire [1:0] scc_mc1_req_size_o;
wire [47:0] scc_mc1_req_vadr_o;
wire [63:0] scc_mc1_req_wrd_rdctl_o;
wire scc_mc1_req_flush_o;
// MC1 odd response port signals
wire scc_mc1_rsp_stall_o;
// MC2 even request port signals
wire scc_mc2_req_ld_e;
wire scc_mc2_req_st_e;
wire [1:0] scc_mc2_req_size_e;
wire [47:0] scc_mc2_req_vadr_e;
wire [63:0] scc_mc2_req_wrd_rdctl_e;
wire scc_mc2_req_flush_e;
// MC2 even response port signals
wire scc_mc2_rsp_stall_e;
// MC2 odd request port signals
wire scc_mc2_req_ld_o;
wire scc_mc2_req_st_o;
wire [1:0] scc_mc2_req_size_o;
wire [47:0] scc_mc2_req_vadr_o;
wire [63:0] scc_mc2_req_wrd_rdctl_o;
wire scc_mc2_req_flush_o;
// MC2 odd response port signals
wire scc_mc2_rsp_stall_o;
// MC3 even request port signals
wire scc_mc3_req_ld_e;
wire scc_mc3_req_st_e;
wire [1:0] scc_mc3_req_size_e;
wire [47:0] scc_mc3_req_vadr_e;
wire [63:0] scc_mc3_req_wrd_rdctl_e;
wire scc_mc3_req_flush_e;
// MC3 even response port signals
wire scc_mc3_rsp_stall_e;
// MC3 odd request port signals
wire scc_mc3_req_ld_o;
wire scc_mc3_req_st_o;
wire [1:0] scc_mc3_req_size_o;
wire [47:0] scc_mc3_req_vadr_o;
wire [63:0] scc_mc3_req_wrd_rdctl_o;
wire scc_mc3_req_flush_o;
// MC3 odd response port signals
wire scc_mc3_rsp_stall_o;
// MC4 even request port signals
wire scc_mc4_req_ld_e;
wire scc_mc4_req_st_e;
wire [1:0] scc_mc4_req_size_e;
wire [47:0] scc_mc4_req_vadr_e;
wire [63:0] scc_mc4_req_wrd_rdctl_e;
wire scc_mc4_req_flush_e;
// MC4 even response port signals
wire scc_mc4_rsp_stall_e;
// MC4 odd request port signals
wire scc_mc4_req_ld_o;
wire scc_mc4_req_st_o;
wire [1:0] scc_mc4_req_size_o;
wire [47:0] scc_mc4_req_vadr_o;
wire [63:0] scc_mc4_req_wrd_rdctl_o;
wire scc_mc4_req_flush_o;
// MC4 odd response port signals
wire scc_mc4_rsp_stall_o;
// MC5 even request port signals
wire scc_mc5_req_ld_e;
wire scc_mc5_req_st_e;
wire [1:0] scc_mc5_req_size_e;
wire [47:0] scc_mc5_req_vadr_e;
wire [63:0] scc_mc5_req_wrd_rdctl_e;
wire scc_mc5_req_flush_e;
// MC5 even response port signals
wire scc_mc5_rsp_stall_e;
// MC5 odd request port signals
wire scc_mc5_req_ld_o;
wire scc_mc5_req_st_o;
wire [1:0] scc_mc5_req_size_o;
wire [47:0] scc_mc5_req_vadr_o;
wire [63:0] scc_mc5_req_wrd_rdctl_o;
wire scc_mc5_req_flush_o;
// MC5 odd response port signals
wire scc_mc5_rsp_stall_o;
// MC6 even request port signals
wire scc_mc6_req_ld_e;
wire scc_mc6_req_st_e;
wire [1:0] scc_mc6_req_size_e;
wire [47:0] scc_mc6_req_vadr_e;
wire [63:0] scc_mc6_req_wrd_rdctl_e;
wire scc_mc6_req_flush_e;
// MC6 even response port signals
wire scc_mc6_rsp_stall_e;
// MC6 odd request port signals
wire scc_mc6_req_ld_o;
wire scc_mc6_req_st_o;
wire [1:0] scc_mc6_req_size_o;
wire [47:0] scc_mc6_req_vadr_o;
wire [63:0] scc_mc6_req_wrd_rdctl_o;
wire scc_mc6_req_flush_o;
// MC6 odd response port signals
wire scc_mc6_rsp_stall_o;
// MC7 even request port signals
wire scc_mc7_req_ld_e;
wire scc_mc7_req_st_e;
wire [1:0] scc_mc7_req_size_e;
wire [47:0] scc_mc7_req_vadr_e;
wire [63:0] scc_mc7_req_wrd_rdctl_e;
wire scc_mc7_req_flush_e;
// MC7 even response port signals
wire scc_mc7_rsp_stall_e;
// MC7 odd request port signals
wire scc_mc7_req_ld_o;
wire scc_mc7_req_st_o;
wire [1:0] scc_mc7_req_size_o;
wire [47:0] scc_mc7_req_vadr_o;
wire [63:0] scc_mc7_req_wrd_rdctl_o;
wire scc_mc7_req_flush_o;
// MC7 odd response port signals
wire scc_mc7_rsp_stall_o;
// Instaintaite CyGraph module
cygraph cygraph_inst (
// control signals
.clk (clk_per), // in
.rst (full_reset), // in
.enable (cygraph_enable), // in
.busy (cygraph_busy), // out
.done (cygraph_done), // out
// ae-to-ae signals
.ae_id (i_aeid), // in
.nxtae_rx_data (nxtae_rx_data), // in 32
.nxtae_rx_vld (nxtae_rx_vld), // in
.prvae_rx_data (prvae_rx_data), // in 32
.prvae_rx_vld (prvae_rx_vld), // in
.nxtae_tx_data (cy_nxtae_tx_data), // out 32
.nxtae_tx_vld (cy_nxtae_tx_vld), // out
.prvae_tx_data (cy_prvae_tx_data), // out 32
.prvae_tx_vld (cy_prvae_tx_vld), // out
// Graph Parameters
.n_in (cy_n), // in 64
.non_zeros_in (non_zeros), // in 64
.current_level_in (current_level), // in 64
.cq_count_in (cq_count), // in 64
.nq_count_out (nq_count), // out 64
// Input Graph Pointers (Represented in Custom CSR)
.graphData_in (graphData), // in 64
.graphInfo_in (graphInfo), // in 64
// Queue pointers
.queue1_address_in (queue1_address), // in 64
.queue2_address_in (queue2_address), // in 64
.reach_queue_in (reach_queue), // in 64
// MC0 port signals
.mc0_req_ld (cy_mc0_req_ld_e), // out
.mc0_req_st (cy_mc0_req_st_e), // out
.mc0_req_size (cy_mc0_req_size_e), // out 2
.mc0_req_vaddr (cy_mc0_req_vadr_e), // out 48
.mc0_req_wrd_rdctl (cy_mc0_req_wrd_rdctl_e),// out 64
.mc0_req_flush (cy_mc0_req_flush_e), // out
.mc0_rd_rq_stall (mc0_rd_rq_stall_e), // in
.mc0_wr_rq_stall (mc0_wr_rq_stall_e), // in
.mc0_rsp_push (mc0_rsp_push_e), // in
.mc0_rsp_stall (cy_mc0_rsp_stall_e), // out
.mc0_rsp_data (mc0_rsp_data_e), // in 64
.mc0_rsp_rdctl (mc0_rsp_rdctl_e), // in 32
.mc0_rsp_flush_cmplt (mc0_rsp_flush_cmplt_e), // in
// MC1 port signals
.mc1_req_ld (cy_mc0_req_ld_o), // out
.mc1_req_st (cy_mc0_req_st_o), // out
.mc1_req_size (cy_mc0_req_size_o), // out 2
.mc1_req_vaddr (cy_mc0_req_vadr_o), // out 48
.mc1_req_wrd_rdctl (cy_mc0_req_wrd_rdctl_o),// out 64
.mc1_req_flush (cy_mc0_req_flush_o), // out
.mc1_rd_rq_stall (mc0_rd_rq_stall_o), // in
.mc1_wr_rq_stall (mc0_wr_rq_stall_o), // in
.mc1_rsp_push (mc0_rsp_push_o), // in
.mc1_rsp_stall (cy_mc0_rsp_stall_o), // out
.mc1_rsp_data (mc0_rsp_data_o), // in 64
.mc1_rsp_rdctl (mc0_rsp_rdctl_o), // in 32
.mc1_rsp_flush_cmplt (mc0_rsp_flush_cmplt_o), // in
// MC2 port signals
.mc2_req_ld (cy_mc1_req_ld_e), // out
.mc2_req_st (cy_mc1_req_st_e), // out
.mc2_req_size (cy_mc1_req_size_e), // out 2
.mc2_req_vaddr (cy_mc1_req_vadr_e), // out 48
.mc2_req_wrd_rdctl (cy_mc1_req_wrd_rdctl_e),// out 64
.mc2_req_flush (cy_mc1_req_flush_e), // out
.mc2_rd_rq_stall (mc1_rd_rq_stall_e), // in
.mc2_wr_rq_stall (mc1_wr_rq_stall_e), // in
.mc2_rsp_push (mc1_rsp_push_e), // in
.mc2_rsp_stall (cy_mc1_rsp_stall_e), // out
.mc2_rsp_data (mc1_rsp_data_e), // in 64
.mc2_rsp_rdctl (mc1_rsp_rdctl_e), // in 32
.mc2_rsp_flush_cmplt (mc1_rsp_flush_cmplt_e), // in
// MC3 port signals
.mc3_req_ld (cy_mc1_req_ld_o), // out
.mc3_req_st (cy_mc1_req_st_o), // out
.mc3_req_size (cy_mc1_req_size_o), // out 2
.mc3_req_vaddr (cy_mc1_req_vadr_o), // out 48
.mc3_req_wrd_rdctl (cy_mc1_req_wrd_rdctl_o),// out 64
.mc3_req_flush (cy_mc1_req_flush_o), // out
.mc3_rd_rq_stall (mc1_rd_rq_stall_o), // in
.mc3_wr_rq_stall (mc1_wr_rq_stall_o), // in
.mc3_rsp_push (mc1_rsp_push_o), // in
.mc3_rsp_stall (cy_mc1_rsp_stall_o), // out
.mc3_rsp_data (mc1_rsp_data_o), // in 64
.mc3_rsp_rdctl (mc1_rsp_rdctl_o), // in 32
.mc3_rsp_flush_cmplt (mc1_rsp_flush_cmplt_o), // in
// MC4 port signals
.mc4_req_ld (cy_mc2_req_ld_e), // out
.mc4_req_st (cy_mc2_req_st_e), // out
.mc4_req_size (cy_mc2_req_size_e), // out 2
.mc4_req_vaddr (cy_mc2_req_vadr_e), // out 48
.mc4_req_wrd_rdctl (cy_mc2_req_wrd_rdctl_e),// out 64
.mc4_req_flush (cy_mc2_req_flush_e), // out
.mc4_rd_rq_stall (mc2_rd_rq_stall_e), // in
.mc4_wr_rq_stall (mc2_wr_rq_stall_e), // in
.mc4_rsp_push (mc2_rsp_push_e), // in
.mc4_rsp_stall (cy_mc2_rsp_stall_e), // out
.mc4_rsp_data (mc2_rsp_data_e), // in 64
.mc4_rsp_rdctl (mc2_rsp_rdctl_e), // in 32
.mc4_rsp_flush_cmplt (mc2_rsp_flush_cmplt_e), // in
// MC5 port signals
.mc5_req_ld (cy_mc2_req_ld_o), // out
.mc5_req_st (cy_mc2_req_st_o), // out
.mc5_req_size (cy_mc2_req_size_o), // out 2
.mc5_req_vaddr (cy_mc2_req_vadr_o), // out 48
.mc5_req_wrd_rdctl (cy_mc2_req_wrd_rdctl_o),// out 64
.mc5_req_flush (cy_mc2_req_flush_o), // out
.mc5_rd_rq_stall (mc2_rd_rq_stall_o), // in
.mc5_wr_rq_stall (mc2_wr_rq_stall_o), // in
.mc5_rsp_push (mc2_rsp_push_o), // in
.mc5_rsp_stall (cy_mc2_rsp_stall_o), // out
.mc5_rsp_data (mc2_rsp_data_o), // in 64
.mc5_rsp_rdctl (mc2_rsp_rdctl_o), // in 32
.mc5_rsp_flush_cmplt (mc2_rsp_flush_cmplt_o), // in
// MC6 port signals
.mc6_req_ld (cy_mc3_req_ld_e), // out
.mc6_req_st (cy_mc3_req_st_e), // out
.mc6_req_size (cy_mc3_req_size_e), // out 2
.mc6_req_vaddr (cy_mc3_req_vadr_e), // out 48
.mc6_req_wrd_rdctl (cy_mc3_req_wrd_rdctl_e),// out 64
.mc6_req_flush (cy_mc3_req_flush_e), // out
.mc6_rd_rq_stall (mc3_rd_rq_stall_e), // in
.mc6_wr_rq_stall (mc3_wr_rq_stall_e), // in
.mc6_rsp_push (mc3_rsp_push_e), // in
.mc6_rsp_stall (cy_mc3_rsp_stall_e), // out
.mc6_rsp_data (mc3_rsp_data_e), // in 64
.mc6_rsp_rdctl (mc3_rsp_rdctl_e), // in 32
.mc6_rsp_flush_cmplt (mc3_rsp_flush_cmplt_e), // in
// MC7 port signals
.mc7_req_ld (cy_mc3_req_ld_o), // out
.mc7_req_st (cy_mc3_req_st_o), // out
.mc7_req_size (cy_mc3_req_size_o), // out 2
.mc7_req_vaddr (cy_mc3_req_vadr_o), // out 48
.mc7_req_wrd_rdctl (cy_mc3_req_wrd_rdctl_o),// out 64
.mc7_req_flush (cy_mc3_req_flush_o), // out
.mc7_rd_rq_stall (mc3_rd_rq_stall_o), // in
.mc7_wr_rq_stall (mc3_wr_rq_stall_o), // in
.mc7_rsp_push (mc3_rsp_push_o), // in
.mc7_rsp_stall (cy_mc3_rsp_stall_o), // out
.mc7_rsp_data (mc3_rsp_data_o), // in 64
.mc7_rsp_rdctl (mc3_rsp_rdctl_o), // in 32
.mc7_rsp_flush_cmplt (mc3_rsp_flush_cmplt_o), // in
// MC8 port signals
.mc8_req_ld (cy_mc4_req_ld_e), // out
.mc8_req_st (cy_mc4_req_st_e), // out
.mc8_req_size (cy_mc4_req_size_e), // out 2
.mc8_req_vaddr (cy_mc4_req_vadr_e), // out 48
.mc8_req_wrd_rdctl (cy_mc4_req_wrd_rdctl_e),// out 64
.mc8_req_flush (cy_mc4_req_flush_e), // out
.mc8_rd_rq_stall (mc4_rd_rq_stall_e), // in
.mc8_wr_rq_stall (mc4_wr_rq_stall_e), // in
.mc8_rsp_push (mc4_rsp_push_e), // in
.mc8_rsp_stall (cy_mc4_rsp_stall_e), // out
.mc8_rsp_data (mc4_rsp_data_e), // in 64
.mc8_rsp_rdctl (mc4_rsp_rdctl_e), // in 32
.mc8_rsp_flush_cmplt (mc4_rsp_flush_cmplt_e), // in
// MC9 port signals
.mc9_req_ld (cy_mc4_req_ld_o), // out
.mc9_req_st (cy_mc4_req_st_o), // out
.mc9_req_size (cy_mc4_req_size_o), // out 2
.mc9_req_vaddr (cy_mc4_req_vadr_o), // out 48
.mc9_req_wrd_rdctl (cy_mc4_req_wrd_rdctl_o),// out 64
.mc9_req_flush (cy_mc4_req_flush_o), // out
.mc9_rd_rq_stall (mc4_rd_rq_stall_o), // in
.mc9_wr_rq_stall (mc4_wr_rq_stall_o), // in
.mc9_rsp_push (mc4_rsp_push_o), // in
.mc9_rsp_stall (cy_mc4_rsp_stall_o), // out
.mc9_rsp_data (mc4_rsp_data_o), // in 64
.mc9_rsp_rdctl (mc4_rsp_rdctl_o), // in 32
.mc9_rsp_flush_cmplt (mc4_rsp_flush_cmplt_o), // in
// MC10 port signals
.mc10_req_ld (cy_mc5_req_ld_e), // out
.mc10_req_st (cy_mc5_req_st_e), // out
.mc10_req_size (cy_mc5_req_size_e), // out 2
.mc10_req_vaddr (cy_mc5_req_vadr_e), // out 48
.mc10_req_wrd_rdctl (cy_mc5_req_wrd_rdctl_e),// out 64
.mc10_req_flush (cy_mc5_req_flush_e), // out
.mc10_rd_rq_stall (mc5_rd_rq_stall_e), // in
.mc10_wr_rq_stall (mc5_wr_rq_stall_e), // in
.mc10_rsp_push (mc5_rsp_push_e), // in
.mc10_rsp_stall (cy_mc5_rsp_stall_e), // out
.mc10_rsp_data (mc5_rsp_data_e), // in 64
.mc10_rsp_rdctl (mc5_rsp_rdctl_e), // in 32
.mc10_rsp_flush_cmplt (mc5_rsp_flush_cmplt_e), // in
// MC11 port signals
.mc11_req_ld (cy_mc5_req_ld_o), // out
.mc11_req_st (cy_mc5_req_st_o), // out
.mc11_req_size (cy_mc5_req_size_o), // out 2
.mc11_req_vaddr (cy_mc5_req_vadr_o), // out 48
.mc11_req_wrd_rdctl (cy_mc5_req_wrd_rdctl_o),// out 64
.mc11_req_flush (cy_mc5_req_flush_o), // out
.mc11_rd_rq_stall (mc5_rd_rq_stall_o), // in
.mc11_wr_rq_stall (mc5_wr_rq_stall_o), // in
.mc11_rsp_push (mc5_rsp_push_o), // in
.mc11_rsp_stall (cy_mc5_rsp_stall_o), // out
.mc11_rsp_data (mc5_rsp_data_o), // in 64
.mc11_rsp_rdctl (mc5_rsp_rdctl_o), // in 32
.mc11_rsp_flush_cmplt (mc5_rsp_flush_cmplt_o), // in
// MC12 port signals
.mc12_req_ld (cy_mc6_req_ld_e), // out
.mc12_req_st (cy_mc6_req_st_e), // out
.mc12_req_size (cy_mc6_req_size_e), // out 2
.mc12_req_vaddr (cy_mc6_req_vadr_e), // out 48
.mc12_req_wrd_rdctl (cy_mc6_req_wrd_rdctl_e),// out 64
.mc12_req_flush (cy_mc6_req_flush_e), // out
.mc12_rd_rq_stall (mc6_rd_rq_stall_e), // in
.mc12_wr_rq_stall (mc6_wr_rq_stall_e), // in
.mc12_rsp_push (mc6_rsp_push_e), // in
.mc12_rsp_stall (cy_mc6_rsp_stall_e), // out
.mc12_rsp_data (mc6_rsp_data_e), // in 64
.mc12_rsp_rdctl (mc6_rsp_rdctl_e), // in 32
.mc12_rsp_flush_cmplt (mc6_rsp_flush_cmplt_e), // in
// MC13 port signals
.mc13_req_ld (cy_mc6_req_ld_o), // out
.mc13_req_st (cy_mc6_req_st_o), // out
.mc13_req_size (cy_mc6_req_size_o), // out 2
.mc13_req_vaddr (cy_mc6_req_vadr_o), // out 48
.mc13_req_wrd_rdctl (cy_mc6_req_wrd_rdctl_o),// out 64
.mc13_req_flush (cy_mc6_req_flush_o), // out
.mc13_rd_rq_stall (mc6_rd_rq_stall_o), // in
.mc13_wr_rq_stall (mc6_wr_rq_stall_o), // in
.mc13_rsp_push (mc6_rsp_push_o), // in
.mc13_rsp_stall (cy_mc6_rsp_stall_o), // out
.mc13_rsp_data (mc6_rsp_data_o), // in 64
.mc13_rsp_rdctl (mc6_rsp_rdctl_o), // in 32
.mc13_rsp_flush_cmplt (mc6_rsp_flush_cmplt_o), // in
// MC14 port signals
.mc14_req_ld (cy_mc7_req_ld_e), // out
.mc14_req_st (cy_mc7_req_st_e), // out
.mc14_req_size (cy_mc7_req_size_e), // out 2
.mc14_req_vaddr (cy_mc7_req_vadr_e), // out 48
.mc14_req_wrd_rdctl (cy_mc7_req_wrd_rdctl_e),// out 64
.mc14_req_flush (cy_mc7_req_flush_e), // out
.mc14_rd_rq_stall (mc7_rd_rq_stall_e), // in
.mc14_wr_rq_stall (mc7_wr_rq_stall_e), // in
.mc14_rsp_push (mc7_rsp_push_e), // in
.mc14_rsp_stall (cy_mc7_rsp_stall_e), // out
.mc14_rsp_data (mc7_rsp_data_e), // in 64
.mc14_rsp_rdctl (mc7_rsp_rdctl_e), // in 32
.mc14_rsp_flush_cmplt (mc7_rsp_flush_cmplt_e), // in
// MC15 port signals
.mc15_req_ld (cy_mc7_req_ld_o), // out
.mc15_req_st (cy_mc7_req_st_o), // out
.mc15_req_size (cy_mc7_req_size_o), // out 2
.mc15_req_vaddr (cy_mc7_req_vadr_o), // out 48
.mc15_req_wrd_rdctl (cy_mc7_req_wrd_rdctl_o),// out 64
.mc15_req_flush (cy_mc7_req_flush_o), // out
.mc15_rd_rq_stall (mc7_rd_rq_stall_o), // in
.mc15_wr_rq_stall (mc7_wr_rq_stall_o), // in
.mc15_rsp_push (mc7_rsp_push_o), // in
.mc15_rsp_stall (cy_mc7_rsp_stall_o), // out
.mc15_rsp_data (mc7_rsp_data_o), // in 64
.mc15_rsp_rdctl (mc7_rsp_rdctl_o), // in 32
.mc15_rsp_flush_cmplt (mc7_rsp_flush_cmplt_o) // in
);
// Instaintaite SCC Intersection module
scc scc_inst (
// control signals
.clk (clk_per), // in
.rst (full_reset), // in
.enable (scc_enable), // in
.busy (scc_busy), // out
.done (scc_done), // out
// SCC Parameters
.color_in (scc_color), // in 64
.scc_addr_in (scc_results), // in 64
.nextv_out (scc_nextv), // out 64
// Graph/ReversedGraph Pointers
.n_in (scc_N), // in 64
.graph_info_in (scc_graphInfo), // in 64
.rgraph_info_in (scc_rgraphInfo), // in 64
// Reach queues pointers
.fw_addr_in (scc_fw_addr), // in 64
.fw_count_in (scc_fw_count), // in 64
.bw_addr_in (scc_bw_addr), // in 64
.bw_count_in (scc_bw_count), // in 64
// ae-to-ae signals
.ae_id (i_aeid), // in
.nxtae_rx_data (nxtae_rx_data), // in 32
.nxtae_rx_vld (nxtae_rx_vld), // in
.prvae_rx_data (prvae_rx_data), // in 32
.prvae_rx_vld (prvae_rx_vld), // in
.nxtae_tx_data (scc_nxtae_tx_data), // out 32
.nxtae_tx_vld (scc_nxtae_tx_vld), // out
.prvae_tx_data (scc_prvae_tx_data), // out 32
.prvae_tx_vld (scc_prvae_tx_vld), // out
// MC0 port signals
.mc0_req_ld (scc_mc0_req_ld_e), // out
.mc0_req_st (scc_mc0_req_st_e), // out
.mc0_req_size (scc_mc0_req_size_e), // out 2
.mc0_req_vaddr (scc_mc0_req_vadr_e), // out 48
.mc0_req_wrd_rdctl (scc_mc0_req_wrd_rdctl_e),// out 64
.mc0_req_flush (scc_mc0_req_flush_e), // out
.mc0_rd_rq_stall (mc0_rd_rq_stall_e), // in
.mc0_wr_rq_stall (mc0_wr_rq_stall_e), // in
.mc0_rsp_push (mc0_rsp_push_e), // in
.mc0_rsp_stall (scc_mc0_rsp_stall_e), // out
.mc0_rsp_data (mc0_rsp_data_e), // in 64
.mc0_rsp_rdctl (mc0_rsp_rdctl_e), // in 32
.mc0_rsp_flush_cmplt (mc0_rsp_flush_cmplt_e), // in
// MC1 port signals
.mc1_req_ld (scc_mc0_req_ld_o), // out
.mc1_req_st (scc_mc0_req_st_o), // out
.mc1_req_size (scc_mc0_req_size_o), // out 2
.mc1_req_vaddr (scc_mc0_req_vadr_o), // out 48
.mc1_req_wrd_rdctl (scc_mc0_req_wrd_rdctl_o),// out 64
.mc1_req_flush (scc_mc0_req_flush_o), // out
.mc1_rd_rq_stall (mc0_rd_rq_stall_o), // in
.mc1_wr_rq_stall (mc0_wr_rq_stall_o), // in
.mc1_rsp_push (mc0_rsp_push_o), // in
.mc1_rsp_stall (scc_mc0_rsp_stall_o), // out
.mc1_rsp_data (mc0_rsp_data_o), // in 64
.mc1_rsp_rdctl (mc0_rsp_rdctl_o), // in 32
.mc1_rsp_flush_cmplt (mc0_rsp_flush_cmplt_o), // in
// MC2 port signals
.mc2_req_ld (scc_mc1_req_ld_e), // out
.mc2_req_st (scc_mc1_req_st_e), // out
.mc2_req_size (scc_mc1_req_size_e), // out 2
.mc2_req_vaddr (scc_mc1_req_vadr_e), // out 48
.mc2_req_wrd_rdctl (scc_mc1_req_wrd_rdctl_e),// out 64
.mc2_req_flush (scc_mc1_req_flush_e), // out
.mc2_rd_rq_stall (mc1_rd_rq_stall_e), // in
.mc2_wr_rq_stall (mc1_wr_rq_stall_e), // in
.mc2_rsp_push (mc1_rsp_push_e), // in
.mc2_rsp_stall (scc_mc1_rsp_stall_e), // out
.mc2_rsp_data (mc1_rsp_data_e), // in 64
.mc2_rsp_rdctl (mc1_rsp_rdctl_e), // in 32
.mc2_rsp_flush_cmplt (mc1_rsp_flush_cmplt_e), // in
// MC3 port signals
.mc3_req_ld (scc_mc1_req_ld_o), // out
.mc3_req_st (scc_mc1_req_st_o), // out
.mc3_req_size (scc_mc1_req_size_o), // out 2
.mc3_req_vaddr (scc_mc1_req_vadr_o), // out 48
.mc3_req_wrd_rdctl (scc_mc1_req_wrd_rdctl_o),// out 64
.mc3_req_flush (scc_mc1_req_flush_o), // out
.mc3_rd_rq_stall (mc1_rd_rq_stall_o), // in
.mc3_wr_rq_stall (mc1_wr_rq_stall_o), // in
.mc3_rsp_push (mc1_rsp_push_o), // in
.mc3_rsp_stall (scc_mc1_rsp_stall_o), // out
.mc3_rsp_data (mc1_rsp_data_o), // in 64
.mc3_rsp_rdctl (mc1_rsp_rdctl_o), // in 32
.mc3_rsp_flush_cmplt (mc1_rsp_flush_cmplt_o), // in
// MC4 port signals
.mc4_req_ld (scc_mc2_req_ld_e), // out
.mc4_req_st (scc_mc2_req_st_e), // out
.mc4_req_size (scc_mc2_req_size_e), // out 2
.mc4_req_vaddr (scc_mc2_req_vadr_e), // out 48
.mc4_req_wrd_rdctl (scc_mc2_req_wrd_rdctl_e),// out 64
.mc4_req_flush (scc_mc2_req_flush_e), // out
.mc4_rd_rq_stall (mc2_rd_rq_stall_e), // in
.mc4_wr_rq_stall (mc2_wr_rq_stall_e), // in
.mc4_rsp_push (mc2_rsp_push_e), // in
.mc4_rsp_stall (scc_mc2_rsp_stall_e), // out
.mc4_rsp_data (mc2_rsp_data_e), // in 64
.mc4_rsp_rdctl (mc2_rsp_rdctl_e), // in 32
.mc4_rsp_flush_cmplt (mc2_rsp_flush_cmplt_e), // in
// MC5 port signals
.mc5_req_ld (scc_mc2_req_ld_o), // out
.mc5_req_st (scc_mc2_req_st_o), // out
.mc5_req_size (scc_mc2_req_size_o), // out 2
.mc5_req_vaddr (scc_mc2_req_vadr_o), // out 48
.mc5_req_wrd_rdctl (scc_mc2_req_wrd_rdctl_o),// out 64
.mc5_req_flush (scc_mc2_req_flush_o), // out
.mc5_rd_rq_stall (mc2_rd_rq_stall_o), // in
.mc5_wr_rq_stall (mc2_wr_rq_stall_o), // in
.mc5_rsp_push (mc2_rsp_push_o), // in
.mc5_rsp_stall (scc_mc2_rsp_stall_o), // out
.mc5_rsp_data (mc2_rsp_data_o), // in 64
.mc5_rsp_rdctl (mc2_rsp_rdctl_o), // in 32
.mc5_rsp_flush_cmplt (mc2_rsp_flush_cmplt_o), // in
// MC6 port signals
.mc6_req_ld (scc_mc3_req_ld_e), // out
.mc6_req_st (scc_mc3_req_st_e), // out
.mc6_req_size (scc_mc3_req_size_e), // out 2
.mc6_req_vaddr (scc_mc3_req_vadr_e), // out 48
.mc6_req_wrd_rdctl (scc_mc3_req_wrd_rdctl_e),// out 64
.mc6_req_flush (scc_mc3_req_flush_e), // out
.mc6_rd_rq_stall (mc3_rd_rq_stall_e), // in
.mc6_wr_rq_stall (mc3_wr_rq_stall_e), // in
.mc6_rsp_push (mc3_rsp_push_e), // in
.mc6_rsp_stall (scc_mc3_rsp_stall_e), // out
.mc6_rsp_data (mc3_rsp_data_e), // in 64
.mc6_rsp_rdctl (mc3_rsp_rdctl_e), // in 32
.mc6_rsp_flush_cmplt (mc3_rsp_flush_cmplt_e), // in
// MC7 port signals
.mc7_req_ld (scc_mc3_req_ld_o), // out
.mc7_req_st (scc_mc3_req_st_o), // out
.mc7_req_size (scc_mc3_req_size_o), // out 2
.mc7_req_vaddr (scc_mc3_req_vadr_o), // out 48
.mc7_req_wrd_rdctl (scc_mc3_req_wrd_rdctl_o),// out 64
.mc7_req_flush (scc_mc3_req_flush_o), // out
.mc7_rd_rq_stall (mc3_rd_rq_stall_o), // in
.mc7_wr_rq_stall (mc3_wr_rq_stall_o), // in
.mc7_rsp_push (mc3_rsp_push_o), // in
.mc7_rsp_stall (scc_mc3_rsp_stall_o), // out
.mc7_rsp_data (mc3_rsp_data_o), // in 64
.mc7_rsp_rdctl (mc3_rsp_rdctl_o), // in 32
.mc7_rsp_flush_cmplt (mc3_rsp_flush_cmplt_o), // in
// MC8 port signals
.mc8_req_ld (scc_mc4_req_ld_e), // out
.mc8_req_st (scc_mc4_req_st_e), // out
.mc8_req_size (scc_mc4_req_size_e), // out 2
.mc8_req_vaddr (scc_mc4_req_vadr_e), // out 48
.mc8_req_wrd_rdctl (scc_mc4_req_wrd_rdctl_e),// out 64
.mc8_req_flush (scc_mc4_req_flush_e), // out
.mc8_rd_rq_stall (mc4_rd_rq_stall_e), // in
.mc8_wr_rq_stall (mc4_wr_rq_stall_e), // in
.mc8_rsp_push (mc4_rsp_push_e), // in
.mc8_rsp_stall (scc_mc4_rsp_stall_e), // out
.mc8_rsp_data (mc4_rsp_data_e), // in 64
.mc8_rsp_rdctl (mc4_rsp_rdctl_e), // in 32
.mc8_rsp_flush_cmplt (mc4_rsp_flush_cmplt_e), // in
// MC9 port signals
.mc9_req_ld (scc_mc4_req_ld_o), // out
.mc9_req_st (scc_mc4_req_st_o), // out
.mc9_req_size (scc_mc4_req_size_o), // out 2
.mc9_req_vaddr (scc_mc4_req_vadr_o), // out 48
.mc9_req_wrd_rdctl (scc_mc4_req_wrd_rdctl_o),// out 64
.mc9_req_flush (scc_mc4_req_flush_o), // out
.mc9_rd_rq_stall (mc4_rd_rq_stall_o), // in
.mc9_wr_rq_stall (mc4_wr_rq_stall_o), // in
.mc9_rsp_push (mc4_rsp_push_o), // in
.mc9_rsp_stall (scc_mc4_rsp_stall_o), // out
.mc9_rsp_data (mc4_rsp_data_o), // in 64
.mc9_rsp_rdctl (mc4_rsp_rdctl_o), // in 32
.mc9_rsp_flush_cmplt (mc4_rsp_flush_cmplt_o), // in
// MC10 port signals
.mc10_req_ld (scc_mc5_req_ld_e), // out
.mc10_req_st (scc_mc5_req_st_e), // out
.mc10_req_size (scc_mc5_req_size_e), // out 2
.mc10_req_vaddr (scc_mc5_req_vadr_e), // out 48
.mc10_req_wrd_rdctl (scc_mc5_req_wrd_rdctl_e),// out 64
.mc10_req_flush (scc_mc5_req_flush_e), // out
.mc10_rd_rq_stall (mc5_rd_rq_stall_e), // in
.mc10_wr_rq_stall (mc5_wr_rq_stall_e), // in
.mc10_rsp_push (mc5_rsp_push_e), // in
.mc10_rsp_stall (scc_mc5_rsp_stall_e), // out
.mc10_rsp_data (mc5_rsp_data_e), // in 64
.mc10_rsp_rdctl (mc5_rsp_rdctl_e), // in 32
.mc10_rsp_flush_cmplt (mc5_rsp_flush_cmplt_e), // in
// MC11 port signals
.mc11_req_ld (scc_mc5_req_ld_o), // out
.mc11_req_st (scc_mc5_req_st_o), // out
.mc11_req_size (scc_mc5_req_size_o), // out 2
.mc11_req_vaddr (scc_mc5_req_vadr_o), // out 48
.mc11_req_wrd_rdctl (scc_mc5_req_wrd_rdctl_o),// out 64
.mc11_req_flush (scc_mc5_req_flush_o), // out
.mc11_rd_rq_stall (mc5_rd_rq_stall_o), // in
.mc11_wr_rq_stall (mc5_wr_rq_stall_o), // in
.mc11_rsp_push (mc5_rsp_push_o), // in
.mc11_rsp_stall (scc_mc5_rsp_stall_o), // out
.mc11_rsp_data (mc5_rsp_data_o), // in 64
.mc11_rsp_rdctl (mc5_rsp_rdctl_o), // in 32
.mc11_rsp_flush_cmplt (mc5_rsp_flush_cmplt_o), // in
// MC12 port signals
.mc12_req_ld (scc_mc6_req_ld_e), // out
.mc12_req_st (scc_mc6_req_st_e), // out
.mc12_req_size (scc_mc6_req_size_e), // out 2
.mc12_req_vaddr (scc_mc6_req_vadr_e), // out 48
.mc12_req_wrd_rdctl (scc_mc6_req_wrd_rdctl_e),// out 64
.mc12_req_flush (scc_mc6_req_flush_e), // out
.mc12_rd_rq_stall (mc6_rd_rq_stall_e), // in
.mc12_wr_rq_stall (mc6_wr_rq_stall_e), // in
.mc12_rsp_push (mc6_rsp_push_e), // in
.mc12_rsp_stall (scc_mc6_rsp_stall_e), // out
.mc12_rsp_data (mc6_rsp_data_e), // in 64
.mc12_rsp_rdctl (mc6_rsp_rdctl_e), // in 32
.mc12_rsp_flush_cmplt (mc6_rsp_flush_cmplt_e), // in
// MC13 port signals
.mc13_req_ld (scc_mc6_req_ld_o), // out
.mc13_req_st (scc_mc6_req_st_o), // out
.mc13_req_size (scc_mc6_req_size_o), // out 2
.mc13_req_vaddr (scc_mc6_req_vadr_o), // out 48
.mc13_req_wrd_rdctl (scc_mc6_req_wrd_rdctl_o),// out 64
.mc13_req_flush (scc_mc6_req_flush_o), // out
.mc13_rd_rq_stall (mc6_rd_rq_stall_o), // in
.mc13_wr_rq_stall (mc6_wr_rq_stall_o), // in
.mc13_rsp_push (mc6_rsp_push_o), // in
.mc13_rsp_stall (scc_mc6_rsp_stall_o), // out
.mc13_rsp_data (mc6_rsp_data_o), // in 64
.mc13_rsp_rdctl (mc6_rsp_rdctl_o), // in 32
.mc13_rsp_flush_cmplt (mc6_rsp_flush_cmplt_o), // in
// MC14 port signals
.mc14_req_ld (scc_mc7_req_ld_e), // out
.mc14_req_st (scc_mc7_req_st_e), // out
.mc14_req_size (scc_mc7_req_size_e), // out 2
.mc14_req_vaddr (scc_mc7_req_vadr_e), // out 48
.mc14_req_wrd_rdctl (scc_mc7_req_wrd_rdctl_e),// out 64
.mc14_req_flush (scc_mc7_req_flush_e), // out
.mc14_rd_rq_stall (mc7_rd_rq_stall_e), // in
.mc14_wr_rq_stall (mc7_wr_rq_stall_e), // in
.mc14_rsp_push (mc7_rsp_push_e), // in
.mc14_rsp_stall (scc_mc7_rsp_stall_e), // out
.mc14_rsp_data (mc7_rsp_data_e), // in 64
.mc14_rsp_rdctl (mc7_rsp_rdctl_e), // in 32
.mc14_rsp_flush_cmplt (mc7_rsp_flush_cmplt_e), // in
// MC15 port signals
.mc15_req_ld (scc_mc7_req_ld_o), // out
.mc15_req_st (scc_mc7_req_st_o), // out
.mc15_req_size (scc_mc7_req_size_o), // out 2
.mc15_req_vaddr (scc_mc7_req_vadr_o), // out 48
.mc15_req_wrd_rdctl (scc_mc7_req_wrd_rdctl_o),// out 64
.mc15_req_flush (scc_mc7_req_flush_o), // out
.mc15_rd_rq_stall (mc7_rd_rq_stall_o), // in
.mc15_wr_rq_stall (mc7_wr_rq_stall_o), // in
.mc15_rsp_push (mc7_rsp_push_o), // in
.mc15_rsp_stall (scc_mc7_rsp_stall_o), // out
.mc15_rsp_data (mc7_rsp_data_o), // in 64
.mc15_rsp_rdctl (mc7_rsp_rdctl_o), // in 32
.mc15_rsp_flush_cmplt (mc7_rsp_flush_cmplt_o) // in
);
// intermediate reg signals
reg [31:0] r_nxtae_tx_data;
reg r_nxtae_tx_vld;
reg [31:0] r_prvae_tx_data;
reg r_prvae_tx_vld;
reg r_mc0_req_ld_e;
reg r_mc0_req_st_e;
reg [1:0] r_mc0_req_size_e;
reg [47:0] r_mc0_req_vadr_e;
reg [63:0] r_mc0_req_wrd_rdctl_e;
reg r_mc0_req_flush_e;
reg r_mc0_rsp_stall_e;
reg r_mc0_req_ld_o;
reg r_mc0_req_st_o;
reg [1:0] r_mc0_req_size_o;
reg [47:0] r_mc0_req_vadr_o;
reg [63:0] r_mc0_req_wrd_rdctl_o;
reg r_mc0_req_flush_o;
reg r_mc0_rsp_stall_o;
reg r_mc1_req_ld_e;
reg r_mc1_req_st_e;
reg [1:0] r_mc1_req_size_e;
reg [47:0] r_mc1_req_vadr_e;
reg [63:0] r_mc1_req_wrd_rdctl_e;
reg r_mc1_req_flush_e;
reg r_mc1_rsp_stall_e;
reg r_mc1_req_ld_o;
reg r_mc1_req_st_o;
reg [1:0] r_mc1_req_size_o;
reg [47:0] r_mc1_req_vadr_o;
reg [63:0] r_mc1_req_wrd_rdctl_o;
reg r_mc1_req_flush_o;
reg r_mc1_rsp_stall_o;
reg r_mc2_req_ld_e;
reg r_mc2_req_st_e;
reg [1:0] r_mc2_req_size_e;
reg [47:0] r_mc2_req_vadr_e;
reg [63:0] r_mc2_req_wrd_rdctl_e;
reg r_mc2_req_flush_e;
reg r_mc2_rsp_stall_e;
reg r_mc2_req_ld_o;
reg r_mc2_req_st_o;
reg [1:0] r_mc2_req_size_o;
reg [47:0] r_mc2_req_vadr_o;
reg [63:0] r_mc2_req_wrd_rdctl_o;
reg r_mc2_req_flush_o;
reg r_mc2_rsp_stall_o;
reg r_mc3_req_ld_e;
reg r_mc3_req_st_e;
reg [1:0] r_mc3_req_size_e;
reg [47:0] r_mc3_req_vadr_e;
reg [63:0] r_mc3_req_wrd_rdctl_e;
reg r_mc3_req_flush_e;
reg r_mc3_rsp_stall_e;
reg r_mc3_req_ld_o;
reg r_mc3_req_st_o;
reg [1:0] r_mc3_req_size_o;
reg [47:0] r_mc3_req_vadr_o;
reg [63:0] r_mc3_req_wrd_rdctl_o;
reg r_mc3_req_flush_o;
reg r_mc3_rsp_stall_o;
reg r_mc4_req_ld_e;
reg r_mc4_req_st_e;
reg [1:0] r_mc4_req_size_e;
reg [47:0] r_mc4_req_vadr_e;
reg [63:0] r_mc4_req_wrd_rdctl_e;
reg r_mc4_req_flush_e;
reg r_mc4_rsp_stall_e;
reg r_mc4_req_ld_o;
reg r_mc4_req_st_o;
reg [1:0] r_mc4_req_size_o;
reg [47:0] r_mc4_req_vadr_o;
reg [63:0] r_mc4_req_wrd_rdctl_o;
reg r_mc4_req_flush_o;
reg r_mc4_rsp_stall_o;
reg r_mc5_req_ld_e;
reg r_mc5_req_st_e;
reg [1:0] r_mc5_req_size_e;
reg [47:0] r_mc5_req_vadr_e;
reg [63:0] r_mc5_req_wrd_rdctl_e;
reg r_mc5_req_flush_e;
reg r_mc5_rsp_stall_e;
reg r_mc5_req_ld_o;
reg r_mc5_req_st_o;
reg [1:0] r_mc5_req_size_o;
reg [47:0] r_mc5_req_vadr_o;
reg [63:0] r_mc5_req_wrd_rdctl_o;
reg r_mc5_req_flush_o;
reg r_mc5_rsp_stall_o;
reg r_mc6_req_ld_e;
reg r_mc6_req_st_e;
reg [1:0] r_mc6_req_size_e;
reg [47:0] r_mc6_req_vadr_e;
reg [63:0] r_mc6_req_wrd_rdctl_e;
reg r_mc6_req_flush_e;
reg r_mc6_rsp_stall_e;
reg r_mc6_req_ld_o;
reg r_mc6_req_st_o;
reg [1:0] r_mc6_req_size_o;
reg [47:0] r_mc6_req_vadr_o;
reg [63:0] r_mc6_req_wrd_rdctl_o;
reg r_mc6_req_flush_o;
reg r_mc6_rsp_stall_o;
reg r_mc7_req_ld_e;
reg r_mc7_req_st_e;
reg [1:0] r_mc7_req_size_e;
reg [47:0] r_mc7_req_vadr_e;
reg [63:0] r_mc7_req_wrd_rdctl_e;
reg r_mc7_req_flush_e;
reg r_mc7_rsp_stall_e;
reg r_mc7_req_ld_o;
reg r_mc7_req_st_o;
reg [1:0] r_mc7_req_size_o;
reg [47:0] r_mc7_req_vadr_o;
reg [63:0] r_mc7_req_wrd_rdctl_o;
reg r_mc7_req_flush_o;
reg r_mc7_rsp_stall_o;
// Decide which custom instruction to control the AE-to-AE interface
always @(posedge clk) begin
if (cygraph_busy == 1'b1) begin
r_nxtae_tx_data <= cy_nxtae_tx_data;
r_nxtae_tx_vld <= cy_nxtae_tx_vld;
r_prvae_tx_data <= cy_prvae_tx_data;
r_prvae_tx_vld <= cy_prvae_tx_vld;
r_mc0_req_ld_e <= cy_mc0_req_ld_e;
r_mc0_req_st_e <= cy_mc0_req_st_e;
r_mc0_req_size_e <= cy_mc0_req_size_e;
r_mc0_req_vadr_e <= cy_mc0_req_vadr_e;
r_mc0_req_wrd_rdctl_e <= cy_mc0_req_wrd_rdctl_e;
r_mc0_req_flush_e <= cy_mc0_req_flush_e;
r_mc0_rsp_stall_e <= cy_mc0_rsp_stall_e;
r_mc0_req_ld_o <= cy_mc0_req_ld_o;
r_mc0_req_st_o <= cy_mc0_req_st_o;
r_mc0_req_size_o <= cy_mc0_req_size_o;
r_mc0_req_vadr_o <= cy_mc0_req_vadr_o;
r_mc0_req_wrd_rdctl_o <= cy_mc0_req_wrd_rdctl_o;
r_mc0_req_flush_o <= cy_mc0_req_flush_o;
r_mc0_rsp_stall_o <= cy_mc0_rsp_stall_o;
r_mc1_req_ld_e <= cy_mc1_req_ld_e;
r_mc1_req_st_e <= cy_mc1_req_st_e;
r_mc1_req_size_e <= cy_mc1_req_size_e;
r_mc1_req_vadr_e <= cy_mc1_req_vadr_e;
r_mc1_req_wrd_rdctl_e <= cy_mc1_req_wrd_rdctl_e;
r_mc1_req_flush_e <= cy_mc1_req_flush_e;
r_mc1_rsp_stall_e <= cy_mc1_rsp_stall_e;
r_mc1_req_ld_o <= cy_mc1_req_ld_o;
r_mc1_req_st_o <= cy_mc1_req_st_o;
r_mc1_req_size_o <= cy_mc1_req_size_o;
r_mc1_req_vadr_o <= cy_mc1_req_vadr_o;
r_mc1_req_wrd_rdctl_o <= cy_mc1_req_wrd_rdctl_o;
r_mc1_req_flush_o <= cy_mc1_req_flush_o;
r_mc1_rsp_stall_o <= cy_mc1_rsp_stall_o;
r_mc2_req_ld_e <= cy_mc2_req_ld_e;
r_mc2_req_st_e <= cy_mc2_req_st_e;
r_mc2_req_size_e <= cy_mc2_req_size_e;
r_mc2_req_vadr_e <= cy_mc2_req_vadr_e;
r_mc2_req_wrd_rdctl_e <= cy_mc2_req_wrd_rdctl_e;
r_mc2_req_flush_e <= cy_mc2_req_flush_e;
r_mc2_rsp_stall_e <= cy_mc2_rsp_stall_e;
r_mc2_req_ld_o <= cy_mc2_req_ld_o;
r_mc2_req_st_o <= cy_mc2_req_st_o;
r_mc2_req_size_o <= cy_mc2_req_size_o;
r_mc2_req_vadr_o <= cy_mc2_req_vadr_o;
r_mc2_req_wrd_rdctl_o <= cy_mc2_req_wrd_rdctl_o;
r_mc2_req_flush_o <= cy_mc2_req_flush_o;
r_mc2_rsp_stall_o <= cy_mc2_rsp_stall_o;
r_mc3_req_ld_e <= cy_mc3_req_ld_e;
r_mc3_req_st_e <= cy_mc3_req_st_e;
r_mc3_req_size_e <= cy_mc3_req_size_e;
r_mc3_req_vadr_e <= cy_mc3_req_vadr_e;
r_mc3_req_wrd_rdctl_e <= cy_mc3_req_wrd_rdctl_e;
r_mc3_req_flush_e <= cy_mc3_req_flush_e;
r_mc3_rsp_stall_e <= cy_mc3_rsp_stall_e;
r_mc3_req_ld_o <= cy_mc3_req_ld_o;
r_mc3_req_st_o <= cy_mc3_req_st_o;
r_mc3_req_size_o <= cy_mc3_req_size_o;
r_mc3_req_vadr_o <= cy_mc3_req_vadr_o;
r_mc3_req_wrd_rdctl_o <= cy_mc3_req_wrd_rdctl_o;
r_mc3_req_flush_o <= cy_mc3_req_flush_o;
r_mc3_rsp_stall_o <= cy_mc3_rsp_stall_o;
r_mc4_req_ld_e <= cy_mc4_req_ld_e;
r_mc4_req_st_e <= cy_mc4_req_st_e;
r_mc4_req_size_e <= cy_mc4_req_size_e;
r_mc4_req_vadr_e <= cy_mc4_req_vadr_e;
r_mc4_req_wrd_rdctl_e <= cy_mc4_req_wrd_rdctl_e;
r_mc4_req_flush_e <= cy_mc4_req_flush_e;
r_mc4_rsp_stall_e <= cy_mc4_rsp_stall_e;
r_mc4_req_ld_o <= cy_mc4_req_ld_o;
r_mc4_req_st_o <= cy_mc4_req_st_o;
r_mc4_req_size_o <= cy_mc4_req_size_o;
r_mc4_req_vadr_o <= cy_mc4_req_vadr_o;
r_mc4_req_wrd_rdctl_o <= cy_mc4_req_wrd_rdctl_o;
r_mc4_req_flush_o <= cy_mc4_req_flush_o;
r_mc4_rsp_stall_o <= cy_mc4_rsp_stall_o;
r_mc5_req_ld_e <= cy_mc5_req_ld_e;
r_mc5_req_st_e <= cy_mc5_req_st_e;
r_mc5_req_size_e <= cy_mc5_req_size_e;
r_mc5_req_vadr_e <= cy_mc5_req_vadr_e;
r_mc5_req_wrd_rdctl_e <= cy_mc5_req_wrd_rdctl_e;
r_mc5_req_flush_e <= cy_mc5_req_flush_e;
r_mc5_rsp_stall_e <= cy_mc5_rsp_stall_e;
r_mc5_req_ld_o <= cy_mc5_req_ld_o;
r_mc5_req_st_o <= cy_mc5_req_st_o;
r_mc5_req_size_o <= cy_mc5_req_size_o;
r_mc5_req_vadr_o <= cy_mc5_req_vadr_o;
r_mc5_req_wrd_rdctl_o <= cy_mc5_req_wrd_rdctl_o;
r_mc5_req_flush_o <= cy_mc5_req_flush_o;
r_mc5_rsp_stall_o <= cy_mc5_rsp_stall_o;
r_mc6_req_ld_e <= cy_mc6_req_ld_e;
r_mc6_req_st_e <= cy_mc6_req_st_e;
r_mc6_req_size_e <= cy_mc6_req_size_e;
r_mc6_req_vadr_e <= cy_mc6_req_vadr_e;
r_mc6_req_wrd_rdctl_e <= cy_mc6_req_wrd_rdctl_e;
r_mc6_req_flush_e <= cy_mc6_req_flush_e;
r_mc6_rsp_stall_e <= cy_mc6_rsp_stall_e;
r_mc6_req_ld_o <= cy_mc6_req_ld_o;
r_mc6_req_st_o <= cy_mc6_req_st_o;
r_mc6_req_size_o <= cy_mc6_req_size_o;
r_mc6_req_vadr_o <= cy_mc6_req_vadr_o;
r_mc6_req_wrd_rdctl_o <= cy_mc6_req_wrd_rdctl_o;
r_mc6_req_flush_o <= cy_mc6_req_flush_o;
r_mc6_rsp_stall_o <= cy_mc6_rsp_stall_o;
r_mc7_req_ld_e <= cy_mc7_req_ld_e;
r_mc7_req_st_e <= cy_mc7_req_st_e;
r_mc7_req_size_e <= cy_mc7_req_size_e;
r_mc7_req_vadr_e <= cy_mc7_req_vadr_e;
r_mc7_req_wrd_rdctl_e <= cy_mc7_req_wrd_rdctl_e;
r_mc7_req_flush_e <= cy_mc7_req_flush_e;
r_mc7_rsp_stall_e <= cy_mc7_rsp_stall_e;
r_mc7_req_ld_o <= cy_mc7_req_ld_o;
r_mc7_req_st_o <= cy_mc7_req_st_o;
r_mc7_req_size_o <= cy_mc7_req_size_o;
r_mc7_req_vadr_o <= cy_mc7_req_vadr_o;
r_mc7_req_wrd_rdctl_o <= cy_mc7_req_wrd_rdctl_o;
r_mc7_req_flush_o <= cy_mc7_req_flush_o;
r_mc7_rsp_stall_o <= cy_mc7_rsp_stall_o;
end else begin // if (scc_busy == 1'b1) begin
r_nxtae_tx_data <= scc_nxtae_tx_data;
r_nxtae_tx_vld <= scc_nxtae_tx_vld;
r_prvae_tx_data <= scc_prvae_tx_data;
r_prvae_tx_vld <= scc_prvae_tx_vld;
r_mc0_req_ld_e <= scc_mc0_req_ld_e;
r_mc0_req_st_e <= scc_mc0_req_st_e;
r_mc0_req_size_e <= scc_mc0_req_size_e;
r_mc0_req_vadr_e <= scc_mc0_req_vadr_e;
r_mc0_req_wrd_rdctl_e <= scc_mc0_req_wrd_rdctl_e;
r_mc0_req_flush_e <= scc_mc0_req_flush_e;
r_mc0_rsp_stall_e <= scc_mc0_rsp_stall_e;
r_mc0_req_ld_o <= scc_mc0_req_ld_o;
r_mc0_req_st_o <= scc_mc0_req_st_o;
r_mc0_req_size_o <= scc_mc0_req_size_o;
r_mc0_req_vadr_o <= scc_mc0_req_vadr_o;
r_mc0_req_wrd_rdctl_o <= scc_mc0_req_wrd_rdctl_o;
r_mc0_req_flush_o <= scc_mc0_req_flush_o;
r_mc0_rsp_stall_o <= scc_mc0_rsp_stall_o;
r_mc1_req_ld_e <= scc_mc1_req_ld_e;
r_mc1_req_st_e <= scc_mc1_req_st_e;
r_mc1_req_size_e <= scc_mc1_req_size_e;
r_mc1_req_vadr_e <= scc_mc1_req_vadr_e;
r_mc1_req_wrd_rdctl_e <= scc_mc1_req_wrd_rdctl_e;
r_mc1_req_flush_e <= scc_mc1_req_flush_e;
r_mc1_rsp_stall_e <= scc_mc1_rsp_stall_e;
r_mc1_req_ld_o <= scc_mc1_req_ld_o;
r_mc1_req_st_o <= scc_mc1_req_st_o;
r_mc1_req_size_o <= scc_mc1_req_size_o;
r_mc1_req_vadr_o <= scc_mc1_req_vadr_o;
r_mc1_req_wrd_rdctl_o <= scc_mc1_req_wrd_rdctl_o;
r_mc1_req_flush_o <= scc_mc1_req_flush_o;
r_mc1_rsp_stall_o <= scc_mc1_rsp_stall_o;
r_mc2_req_ld_e <= scc_mc2_req_ld_e;
r_mc2_req_st_e <= scc_mc2_req_st_e;
r_mc2_req_size_e <= scc_mc2_req_size_e;
r_mc2_req_vadr_e <= scc_mc2_req_vadr_e;
r_mc2_req_wrd_rdctl_e <= scc_mc2_req_wrd_rdctl_e;
r_mc2_req_flush_e <= scc_mc2_req_flush_e;
r_mc2_rsp_stall_e <= scc_mc2_rsp_stall_e;
r_mc2_req_ld_o <= scc_mc2_req_ld_o;
r_mc2_req_st_o <= scc_mc2_req_st_o;
r_mc2_req_size_o <= scc_mc2_req_size_o;
r_mc2_req_vadr_o <= scc_mc2_req_vadr_o;
r_mc2_req_wrd_rdctl_o <= scc_mc2_req_wrd_rdctl_o;
r_mc2_req_flush_o <= scc_mc2_req_flush_o;
r_mc2_rsp_stall_o <= scc_mc2_rsp_stall_o;
r_mc3_req_ld_e <= scc_mc3_req_ld_e;
r_mc3_req_st_e <= scc_mc3_req_st_e;
r_mc3_req_size_e <= scc_mc3_req_size_e;
r_mc3_req_vadr_e <= scc_mc3_req_vadr_e;
r_mc3_req_wrd_rdctl_e <= scc_mc3_req_wrd_rdctl_e;
r_mc3_req_flush_e <= scc_mc3_req_flush_e;
r_mc3_rsp_stall_e <= scc_mc3_rsp_stall_e;
r_mc3_req_ld_o <= scc_mc3_req_ld_o;
r_mc3_req_st_o <= scc_mc3_req_st_o;
r_mc3_req_size_o <= scc_mc3_req_size_o;
r_mc3_req_vadr_o <= scc_mc3_req_vadr_o;
r_mc3_req_wrd_rdctl_o <= scc_mc3_req_wrd_rdctl_o;
r_mc3_req_flush_o <= scc_mc3_req_flush_o;
r_mc3_rsp_stall_o <= scc_mc3_rsp_stall_o;
r_mc4_req_ld_e <= scc_mc4_req_ld_e;
r_mc4_req_st_e <= scc_mc4_req_st_e;
r_mc4_req_size_e <= scc_mc4_req_size_e;
r_mc4_req_vadr_e <= scc_mc4_req_vadr_e;
r_mc4_req_wrd_rdctl_e <= scc_mc4_req_wrd_rdctl_e;
r_mc4_req_flush_e <= scc_mc4_req_flush_e;
r_mc4_rsp_stall_e <= scc_mc4_rsp_stall_e;
r_mc4_req_ld_o <= scc_mc4_req_ld_o;
r_mc4_req_st_o <= scc_mc4_req_st_o;
r_mc4_req_size_o <= scc_mc4_req_size_o;
r_mc4_req_vadr_o <= scc_mc4_req_vadr_o;
r_mc4_req_wrd_rdctl_o <= scc_mc4_req_wrd_rdctl_o;
r_mc4_req_flush_o <= scc_mc4_req_flush_o;
r_mc4_rsp_stall_o <= scc_mc4_rsp_stall_o;
r_mc5_req_ld_e <= scc_mc5_req_ld_e;
r_mc5_req_st_e <= scc_mc5_req_st_e;
r_mc5_req_size_e <= scc_mc5_req_size_e;
r_mc5_req_vadr_e <= scc_mc5_req_vadr_e;
r_mc5_req_wrd_rdctl_e <= scc_mc5_req_wrd_rdctl_e;
r_mc5_req_flush_e <= scc_mc5_req_flush_e;
r_mc5_rsp_stall_e <= scc_mc5_rsp_stall_e;
r_mc5_req_ld_o <= scc_mc5_req_ld_o;
r_mc5_req_st_o <= scc_mc5_req_st_o;
r_mc5_req_size_o <= scc_mc5_req_size_o;
r_mc5_req_vadr_o <= scc_mc5_req_vadr_o;
r_mc5_req_wrd_rdctl_o <= scc_mc5_req_wrd_rdctl_o;
r_mc5_req_flush_o <= scc_mc5_req_flush_o;
r_mc5_rsp_stall_o <= scc_mc5_rsp_stall_o;
r_mc6_req_ld_e <= scc_mc6_req_ld_e;
r_mc6_req_st_e <= scc_mc6_req_st_e;
r_mc6_req_size_e <= scc_mc6_req_size_e;
r_mc6_req_vadr_e <= scc_mc6_req_vadr_e;
r_mc6_req_wrd_rdctl_e <= scc_mc6_req_wrd_rdctl_e;
r_mc6_req_flush_e <= scc_mc6_req_flush_e;
r_mc6_rsp_stall_e <= scc_mc6_rsp_stall_e;
r_mc6_req_ld_o <= scc_mc6_req_ld_o;
r_mc6_req_st_o <= scc_mc6_req_st_o;
r_mc6_req_size_o <= scc_mc6_req_size_o;
r_mc6_req_vadr_o <= scc_mc6_req_vadr_o;
r_mc6_req_wrd_rdctl_o <= scc_mc6_req_wrd_rdctl_o;
r_mc6_req_flush_o <= scc_mc6_req_flush_o;
r_mc6_rsp_stall_o <= scc_mc6_rsp_stall_o;
r_mc7_req_ld_e <= scc_mc7_req_ld_e;
r_mc7_req_st_e <= scc_mc7_req_st_e;
r_mc7_req_size_e <= scc_mc7_req_size_e;
r_mc7_req_vadr_e <= scc_mc7_req_vadr_e;
r_mc7_req_wrd_rdctl_e <= scc_mc7_req_wrd_rdctl_e;
r_mc7_req_flush_e <= scc_mc7_req_flush_e;
r_mc7_rsp_stall_e <= scc_mc7_rsp_stall_e;
r_mc7_req_ld_o <= scc_mc7_req_ld_o;
r_mc7_req_st_o <= scc_mc7_req_st_o;
r_mc7_req_size_o <= scc_mc7_req_size_o;
r_mc7_req_vadr_o <= scc_mc7_req_vadr_o;
r_mc7_req_wrd_rdctl_o <= scc_mc7_req_wrd_rdctl_o;
r_mc7_req_flush_o <= scc_mc7_req_flush_o;
r_mc7_rsp_stall_o <= scc_mc7_rsp_stall_o;
// end else begin
// r_nxtae_tx_data <= 32'b0;
// r_nxtae_tx_vld <= 1'b0;
// r_prvae_tx_data <= 32'b0;
// r_prvae_tx_vld <= 1'b0;
// r_mc0_req_ld_e <= 1'b0;
// r_mc0_req_st_e <= 1'b0;
// r_mc0_req_size_e <= 2'd0;
// r_mc0_req_vadr_e <= 48'd0;
// r_mc0_req_wrd_rdctl_e <= 64'd0;
// r_mc0_req_flush_e <= 1'b0;
// r_mc0_rsp_stall_e <= 1'b0;
// r_mc0_req_ld_o <= 1'b0;
// r_mc0_req_st_o <= 1'b0;
// r_mc0_req_size_o <= 2'd0;
// r_mc0_req_vadr_o <= 48'd0;
// r_mc0_req_wrd_rdctl_o <= 64'd0;
// r_mc0_req_flush_o <= 1'b0;
// r_mc0_rsp_stall_o <= 1'b0;
// r_mc1_req_ld_e <= 1'b0;
// r_mc1_req_st_e <= 1'b0;
// r_mc1_req_size_e <= 2'd0;
// r_mc1_req_vadr_e <= 48'd0;
// r_mc1_req_wrd_rdctl_e <= 64'd0;
// r_mc1_req_flush_e <= 1'b0;
// r_mc1_rsp_stall_e <= 1'b0;
// r_mc1_req_ld_o <= 1'b0;
// r_mc1_req_st_o <= 1'b0;
// r_mc1_req_size_o <= 2'd0;
// r_mc1_req_vadr_o <= 48'd0;
// r_mc1_req_wrd_rdctl_o <= 64'd0;
// r_mc1_req_flush_o <= 1'b0;
// r_mc1_rsp_stall_o <= 1'b0;
// r_mc2_req_ld_e <= 1'b0;
// r_mc2_req_st_e <= 1'b0;
// r_mc2_req_size_e <= 2'd0;
// r_mc2_req_vadr_e <= 48'd0;
// r_mc2_req_wrd_rdctl_e <= 64'd0;
// r_mc2_req_flush_e <= 1'b0;
// r_mc2_rsp_stall_e <= 1'b0;
// r_mc2_req_ld_o <= 1'b0;
// r_mc2_req_st_o <= 1'b0;
// r_mc2_req_size_o <= 2'd0;
// r_mc2_req_vadr_o <= 48'd0;
// r_mc2_req_wrd_rdctl_o <= 64'd0;
// r_mc2_req_flush_o <= 1'b0;
// r_mc2_rsp_stall_o <= 1'b0;
// r_mc3_req_ld_e <= 1'b0;
// r_mc3_req_st_e <= 1'b0;
// r_mc3_req_size_e <= 2'd0;
// r_mc3_req_vadr_e <= 48'd0;
// r_mc3_req_wrd_rdctl_e <= 64'd0;
// r_mc3_req_flush_e <= 1'b0;
// r_mc3_rsp_stall_e <= 1'b0;
// r_mc3_req_ld_o <= 1'b0;
// r_mc3_req_st_o <= 1'b0;
// r_mc3_req_size_o <= 2'd0;
// r_mc3_req_vadr_o <= 48'd0;
// r_mc3_req_wrd_rdctl_o <= 64'd0;
// r_mc3_req_flush_o <= 1'b0;
// r_mc3_rsp_stall_o <= 1'b0;
// r_mc4_req_ld_e <= 1'b0;
// r_mc4_req_st_e <= 1'b0;
// r_mc4_req_size_e <= 2'd0;
// r_mc4_req_vadr_e <= 48'd0;
// r_mc4_req_wrd_rdctl_e <= 64'd0;
// r_mc4_req_flush_e <= 1'b0;
// r_mc4_rsp_stall_e <= 1'b0;
// r_mc4_req_ld_o <= 1'b0;
// r_mc4_req_st_o <= 1'b0;
// r_mc4_req_size_o <= 2'd0;
// r_mc4_req_vadr_o <= 48'd0;
// r_mc4_req_wrd_rdctl_o <= 64'd0;
// r_mc4_req_flush_o <= 1'b0;
// r_mc4_rsp_stall_o <= 1'b0;
// r_mc5_req_ld_e <= 1'b0;
// r_mc5_req_st_e <= 1'b0;
// r_mc5_req_size_e <= 2'd0;
// r_mc5_req_vadr_e <= 48'd0;
// r_mc5_req_wrd_rdctl_e <= 64'd0;
// r_mc5_req_flush_e <= 1'b0;
// r_mc5_rsp_stall_e <= 1'b0;
// r_mc5_req_ld_o <= 1'b0;
// r_mc5_req_st_o <= 1'b0;
// r_mc5_req_size_o <= 2'd0;
// r_mc5_req_vadr_o <= 48'd0;
// r_mc5_req_wrd_rdctl_o <= 64'd0;
// r_mc5_req_flush_o <= 1'b0;
// r_mc5_rsp_stall_o <= 1'b0;
// r_mc6_req_ld_e <= 1'b0;
// r_mc6_req_st_e <= 1'b0;
// r_mc6_req_size_e <= 2'd0;
// r_mc6_req_vadr_e <= 48'd0;
// r_mc6_req_wrd_rdctl_e <= 64'd0;
// r_mc6_req_flush_e <= 1'b0;
// r_mc6_rsp_stall_e <= 1'b0;
// r_mc6_req_ld_o <= 1'b0;
// r_mc6_req_st_o <= 1'b0;
// r_mc6_req_size_o <= 2'd0;
// r_mc6_req_vadr_o <= 48'd0;
// r_mc6_req_wrd_rdctl_o <= 64'd0;
// r_mc6_req_flush_o <= 1'b0;
// r_mc6_rsp_stall_o <= 1'b0;
// r_mc7_req_ld_e <= 1'b0;
// r_mc7_req_st_e <= 1'b0;
// r_mc7_req_size_e <= 2'd0;
// r_mc7_req_vadr_e <= 48'd0;
// r_mc7_req_wrd_rdctl_e <= 64'd0;
// r_mc7_req_flush_e <= 1'b0;
// r_mc7_rsp_stall_e <= 1'b0;
// r_mc7_req_ld_o <= 1'b0;
// r_mc7_req_st_o <= 1'b0;
// r_mc7_req_size_o <= 2'd0;
// r_mc7_req_vadr_o <= 48'd0;
// r_mc7_req_wrd_rdctl_o <= 64'd0;
// r_mc7_req_flush_o <= 1'b0;
// r_mc7_rsp_stall_o <= 1'b0;
end
end
// Decide which module to contorl the AE-to-AE interface
assign nxtae_tx_data = r_nxtae_tx_data;
assign nxtae_tx_vld = r_nxtae_tx_vld;
assign prvae_tx_data = r_prvae_tx_data;
assign prvae_tx_vld = r_prvae_tx_vld;
// Decide which module to control the memory
// MC0 even request port signals
assign mc0_req_ld_e = r_mc0_req_ld_e;
assign mc0_req_st_e = r_mc0_req_st_e;
assign mc0_req_size_e = r_mc0_req_size_e;
assign mc0_req_vadr_e = r_mc0_req_vadr_e;
assign mc0_req_wrd_rdctl_e = r_mc0_req_wrd_rdctl_e;
assign mc0_req_flush_e = r_mc0_req_flush_e;
// MC0 even response port signals
assign mc0_rsp_stall_e = r_mc0_rsp_stall_e;
// MC0 odd request port signals
assign mc0_req_ld_o = r_mc0_req_ld_o;
assign mc0_req_st_o = r_mc0_req_st_o;
assign mc0_req_size_o = r_mc0_req_size_o;
assign mc0_req_vadr_o = r_mc0_req_vadr_o;
assign mc0_req_wrd_rdctl_o = r_mc0_req_wrd_rdctl_o;
assign mc0_req_flush_o = r_mc0_req_flush_o;
// MC0 odd response port signals
assign mc0_rsp_stall_o = r_mc0_rsp_stall_o;
// MC1 even request port signals
assign mc1_req_ld_e = r_mc1_req_ld_e;
assign mc1_req_st_e = r_mc1_req_st_e;
assign mc1_req_size_e = r_mc1_req_size_e;
assign mc1_req_vadr_e = r_mc1_req_vadr_e;
assign mc1_req_wrd_rdctl_e = r_mc1_req_wrd_rdctl_e;
assign mc1_req_flush_e = r_mc1_req_flush_e;
// MC1 even response port signals
assign mc1_rsp_stall_e = r_mc1_rsp_stall_e;
// MC1 odd request port signals
assign mc1_req_ld_o = r_mc1_req_ld_o;
assign mc1_req_st_o = r_mc1_req_st_o;
assign mc1_req_size_o = r_mc1_req_size_o;
assign mc1_req_vadr_o = r_mc1_req_vadr_o;
assign mc1_req_wrd_rdctl_o = r_mc1_req_wrd_rdctl_o;
assign mc1_req_flush_o = r_mc1_req_flush_o;
// MC1 odd response port signals
assign mc1_rsp_stall_o = r_mc1_rsp_stall_o;
// MC2 even request port signals
assign mc2_req_ld_e = r_mc2_req_ld_e;
assign mc2_req_st_e = r_mc2_req_st_e;
assign mc2_req_size_e = r_mc2_req_size_e;
assign mc2_req_vadr_e = r_mc2_req_vadr_e;
assign mc2_req_wrd_rdctl_e = r_mc2_req_wrd_rdctl_e;
assign mc2_req_flush_e = r_mc2_req_flush_e;
// MC2 even response port signals
assign mc2_rsp_stall_e = r_mc2_rsp_stall_e;
// MC2 odd request port signals
assign mc2_req_ld_o = r_mc2_req_ld_o;
assign mc2_req_st_o = r_mc2_req_st_o;
assign mc2_req_size_o = r_mc2_req_size_o;
assign mc2_req_vadr_o = r_mc2_req_vadr_o;
assign mc2_req_wrd_rdctl_o = r_mc2_req_wrd_rdctl_o;
assign mc2_req_flush_o = r_mc2_req_flush_o;
// MC2 odd response port signals
assign mc2_rsp_stall_o = r_mc2_rsp_stall_o;
// MC3 even request port signals
assign mc3_req_ld_e = r_mc3_req_ld_e;
assign mc3_req_st_e = r_mc3_req_st_e;
assign mc3_req_size_e = r_mc3_req_size_e;
assign mc3_req_vadr_e = r_mc3_req_vadr_e;
assign mc3_req_wrd_rdctl_e = r_mc3_req_wrd_rdctl_e;
assign mc3_req_flush_e = r_mc3_req_flush_e;
// MC3 even response port signals
assign mc3_rsp_stall_e = r_mc3_rsp_stall_e;
// MC3 odd request port signals
assign mc3_req_ld_o = r_mc3_req_ld_o;
assign mc3_req_st_o = r_mc3_req_st_o;
assign mc3_req_size_o = r_mc3_req_size_o;
assign mc3_req_vadr_o = r_mc3_req_vadr_o;
assign mc3_req_wrd_rdctl_o = r_mc3_req_wrd_rdctl_o;
assign mc3_req_flush_o = r_mc3_req_flush_o;
// MC3 odd response port signals
assign mc3_rsp_stall_o = r_mc3_rsp_stall_o;
// MC4 even request port signals
assign mc4_req_ld_e = r_mc4_req_ld_e;
assign mc4_req_st_e = r_mc4_req_st_e;
assign mc4_req_size_e = r_mc4_req_size_e;
assign mc4_req_vadr_e = r_mc4_req_vadr_e;
assign mc4_req_wrd_rdctl_e = r_mc4_req_wrd_rdctl_e;
assign mc4_req_flush_e = r_mc4_req_flush_e;
// MC4 even response port signals
assign mc4_rsp_stall_e = r_mc4_rsp_stall_e;
// MC4 odd request port signals
assign mc4_req_ld_o = r_mc4_req_ld_o;
assign mc4_req_st_o = r_mc4_req_st_o;
assign mc4_req_size_o = r_mc4_req_size_o;
assign mc4_req_vadr_o = r_mc4_req_vadr_o;
assign mc4_req_wrd_rdctl_o = r_mc4_req_wrd_rdctl_o;
assign mc4_req_flush_o = r_mc4_req_flush_o;
// MC4 odd response port signals
assign mc4_rsp_stall_o = r_mc4_rsp_stall_o;
// MC5 even request port signals
assign mc5_req_ld_e = r_mc5_req_ld_e;
assign mc5_req_st_e = r_mc5_req_st_e;
assign mc5_req_size_e = r_mc5_req_size_e;
assign mc5_req_vadr_e = r_mc5_req_vadr_e;
assign mc5_req_wrd_rdctl_e = r_mc5_req_wrd_rdctl_e;
assign mc5_req_flush_e = r_mc5_req_flush_e;
// MC5 even response port signals
assign mc5_rsp_stall_e = r_mc5_rsp_stall_e;
// MC5 odd request port signals
assign mc5_req_ld_o = r_mc5_req_ld_o;
assign mc5_req_st_o = r_mc5_req_st_o;
assign mc5_req_size_o = r_mc5_req_size_o;
assign mc5_req_vadr_o = r_mc5_req_vadr_o;
assign mc5_req_wrd_rdctl_o = r_mc5_req_wrd_rdctl_o;
assign mc5_req_flush_o = r_mc5_req_flush_o;
// MC5 odd response port signals
assign mc5_rsp_stall_o = r_mc5_rsp_stall_o;
// MC6 even request port signals
assign mc6_req_ld_e = r_mc6_req_ld_e;
assign mc6_req_st_e = r_mc6_req_st_e;
assign mc6_req_size_e = r_mc6_req_size_e;
assign mc6_req_vadr_e = r_mc6_req_vadr_e;
assign mc6_req_wrd_rdctl_e = r_mc6_req_wrd_rdctl_e;
assign mc6_req_flush_e = r_mc6_req_flush_e;
// MC6 even response port signals
assign mc6_rsp_stall_e = r_mc6_rsp_stall_e;
// MC6 odd request port signals
assign mc6_req_ld_o = r_mc6_req_ld_o;
assign mc6_req_st_o = r_mc6_req_st_o;
assign mc6_req_size_o = r_mc6_req_size_o;
assign mc6_req_vadr_o = r_mc6_req_vadr_o;
assign mc6_req_wrd_rdctl_o = r_mc6_req_wrd_rdctl_o;
assign mc6_req_flush_o = r_mc6_req_flush_o;
// MC6 odd response port signals
assign mc6_rsp_stall_o = r_mc6_rsp_stall_o;
// MC7 even request port signals
assign mc7_req_ld_e = r_mc7_req_ld_e;
assign mc7_req_st_e = r_mc7_req_st_e;
assign mc7_req_size_e = r_mc7_req_size_e;
assign mc7_req_vadr_e = r_mc7_req_vadr_e;
assign mc7_req_wrd_rdctl_e = r_mc7_req_wrd_rdctl_e;
assign mc7_req_flush_e = r_mc7_req_flush_e;
// MC7 even response port signals
assign mc7_rsp_stall_e = r_mc7_rsp_stall_e;
// MC7 odd request port signals
assign mc7_req_ld_o = r_mc7_req_ld_o;
assign mc7_req_st_o = r_mc7_req_st_o;
assign mc7_req_size_o = r_mc7_req_size_o;
assign mc7_req_vadr_o = r_mc7_req_vadr_o;
assign mc7_req_wrd_rdctl_o = r_mc7_req_wrd_rdctl_o;
assign mc7_req_flush_o = r_mc7_req_flush_o;
// MC7 odd response port signals
assign mc7_rsp_stall_o = r_mc7_rsp_stall_o;
/* ---------- debug & synopsys off blocks ---------- */
// synopsys translate_off
// Parameters: 1-Severity: Don't Stop, 2-start check only after negedge of reset
//assert_never #(1, 2, "***ERROR ASSERT: unimplemented instruction cracked") a0 (.clk(clk), .reset_n(~reset), .test_expr(r_unimplemented_inst));
// synopsys translate_on
endmodule // cae_pers
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module Loop_loop_height_g8j_rom (
addr0, ce0, q0, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_g8j_rom.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_g8j(
reset,
clk,
address0,
ce0,
q0);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
Loop_loop_height_g8j_rom Loop_loop_height_g8j_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ));
endmodule
|
module soc_system (
adc_ltc2308_0_conduit_end_adc_convst,
adc_ltc2308_0_conduit_end_adc_sck,
adc_ltc2308_0_conduit_end_adc_sdi,
adc_ltc2308_0_conduit_end_adc_sdo,
clk_clk,
hps_0_f2h_cold_reset_req_reset_n,
hps_0_f2h_debug_reset_req_reset_n,
hps_0_f2h_stm_hw_events_stm_hwevents,
hps_0_f2h_warm_reset_req_reset_n,
hps_0_h2f_reset_reset_n,
hps_0_hps_io_hps_io_emac1_inst_TX_CLK,
hps_0_hps_io_hps_io_emac1_inst_TXD0,
hps_0_hps_io_hps_io_emac1_inst_TXD1,
hps_0_hps_io_hps_io_emac1_inst_TXD2,
hps_0_hps_io_hps_io_emac1_inst_TXD3,
hps_0_hps_io_hps_io_emac1_inst_RXD0,
hps_0_hps_io_hps_io_emac1_inst_MDIO,
hps_0_hps_io_hps_io_emac1_inst_MDC,
hps_0_hps_io_hps_io_emac1_inst_RX_CTL,
hps_0_hps_io_hps_io_emac1_inst_TX_CTL,
hps_0_hps_io_hps_io_emac1_inst_RX_CLK,
hps_0_hps_io_hps_io_emac1_inst_RXD1,
hps_0_hps_io_hps_io_emac1_inst_RXD2,
hps_0_hps_io_hps_io_emac1_inst_RXD3,
hps_0_hps_io_hps_io_sdio_inst_CMD,
hps_0_hps_io_hps_io_sdio_inst_D0,
hps_0_hps_io_hps_io_sdio_inst_D1,
hps_0_hps_io_hps_io_sdio_inst_CLK,
hps_0_hps_io_hps_io_sdio_inst_D2,
hps_0_hps_io_hps_io_sdio_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D0,
hps_0_hps_io_hps_io_usb1_inst_D1,
hps_0_hps_io_hps_io_usb1_inst_D2,
hps_0_hps_io_hps_io_usb1_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D4,
hps_0_hps_io_hps_io_usb1_inst_D5,
hps_0_hps_io_hps_io_usb1_inst_D6,
hps_0_hps_io_hps_io_usb1_inst_D7,
hps_0_hps_io_hps_io_usb1_inst_CLK,
hps_0_hps_io_hps_io_usb1_inst_STP,
hps_0_hps_io_hps_io_usb1_inst_DIR,
hps_0_hps_io_hps_io_usb1_inst_NXT,
hps_0_hps_io_hps_io_spim1_inst_CLK,
hps_0_hps_io_hps_io_spim1_inst_MOSI,
hps_0_hps_io_hps_io_spim1_inst_MISO,
hps_0_hps_io_hps_io_spim1_inst_SS0,
hps_0_hps_io_hps_io_uart0_inst_RX,
hps_0_hps_io_hps_io_uart0_inst_TX,
hps_0_hps_io_hps_io_i2c0_inst_SDA,
hps_0_hps_io_hps_io_i2c0_inst_SCL,
hps_0_hps_io_hps_io_i2c1_inst_SDA,
hps_0_hps_io_hps_io_i2c1_inst_SCL,
hps_0_hps_io_hps_io_gpio_inst_GPIO09,
hps_0_hps_io_hps_io_gpio_inst_GPIO35,
hps_0_hps_io_hps_io_gpio_inst_GPIO40,
hps_0_hps_io_hps_io_gpio_inst_GPIO53,
hps_0_hps_io_hps_io_gpio_inst_GPIO54,
hps_0_hps_io_hps_io_gpio_inst_GPIO61,
leds_pio_0_external_connection_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
pll_0_locked_export,
pll_0_outclk2_clk,
reset_reset_n);
output adc_ltc2308_0_conduit_end_adc_convst;
output adc_ltc2308_0_conduit_end_adc_sck;
output adc_ltc2308_0_conduit_end_adc_sdi;
input adc_ltc2308_0_conduit_end_adc_sdo;
input clk_clk;
input hps_0_f2h_cold_reset_req_reset_n;
input hps_0_f2h_debug_reset_req_reset_n;
input [27:0] hps_0_f2h_stm_hw_events_stm_hwevents;
input hps_0_f2h_warm_reset_req_reset_n;
output hps_0_h2f_reset_reset_n;
output hps_0_hps_io_hps_io_emac1_inst_TX_CLK;
output hps_0_hps_io_hps_io_emac1_inst_TXD0;
output hps_0_hps_io_hps_io_emac1_inst_TXD1;
output hps_0_hps_io_hps_io_emac1_inst_TXD2;
output hps_0_hps_io_hps_io_emac1_inst_TXD3;
input hps_0_hps_io_hps_io_emac1_inst_RXD0;
inout hps_0_hps_io_hps_io_emac1_inst_MDIO;
output hps_0_hps_io_hps_io_emac1_inst_MDC;
input hps_0_hps_io_hps_io_emac1_inst_RX_CTL;
output hps_0_hps_io_hps_io_emac1_inst_TX_CTL;
input hps_0_hps_io_hps_io_emac1_inst_RX_CLK;
input hps_0_hps_io_hps_io_emac1_inst_RXD1;
input hps_0_hps_io_hps_io_emac1_inst_RXD2;
input hps_0_hps_io_hps_io_emac1_inst_RXD3;
inout hps_0_hps_io_hps_io_sdio_inst_CMD;
inout hps_0_hps_io_hps_io_sdio_inst_D0;
inout hps_0_hps_io_hps_io_sdio_inst_D1;
output hps_0_hps_io_hps_io_sdio_inst_CLK;
inout hps_0_hps_io_hps_io_sdio_inst_D2;
inout hps_0_hps_io_hps_io_sdio_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D0;
inout hps_0_hps_io_hps_io_usb1_inst_D1;
inout hps_0_hps_io_hps_io_usb1_inst_D2;
inout hps_0_hps_io_hps_io_usb1_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D4;
inout hps_0_hps_io_hps_io_usb1_inst_D5;
inout hps_0_hps_io_hps_io_usb1_inst_D6;
inout hps_0_hps_io_hps_io_usb1_inst_D7;
input hps_0_hps_io_hps_io_usb1_inst_CLK;
output hps_0_hps_io_hps_io_usb1_inst_STP;
input hps_0_hps_io_hps_io_usb1_inst_DIR;
input hps_0_hps_io_hps_io_usb1_inst_NXT;
output hps_0_hps_io_hps_io_spim1_inst_CLK;
output hps_0_hps_io_hps_io_spim1_inst_MOSI;
input hps_0_hps_io_hps_io_spim1_inst_MISO;
output hps_0_hps_io_hps_io_spim1_inst_SS0;
input hps_0_hps_io_hps_io_uart0_inst_RX;
output hps_0_hps_io_hps_io_uart0_inst_TX;
inout hps_0_hps_io_hps_io_i2c0_inst_SDA;
inout hps_0_hps_io_hps_io_i2c0_inst_SCL;
inout hps_0_hps_io_hps_io_i2c1_inst_SDA;
inout hps_0_hps_io_hps_io_i2c1_inst_SCL;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO09;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO35;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO40;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO53;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO54;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO61;
output [7:0] leds_pio_0_external_connection_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
output pll_0_locked_export;
output pll_0_outclk2_clk;
input reset_reset_n;
endmodule
|
// ghrd_10as066n2_axi_bridge_0.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_axi_bridge_0 #(
parameter USE_PIPELINE = 1,
parameter USE_M0_AWID = 1,
parameter USE_M0_AWREGION = 1,
parameter USE_M0_AWLEN = 1,
parameter USE_M0_AWSIZE = 1,
parameter USE_M0_AWBURST = 1,
parameter USE_M0_AWLOCK = 1,
parameter USE_M0_AWCACHE = 1,
parameter USE_M0_AWQOS = 1,
parameter USE_S0_AWREGION = 1,
parameter USE_S0_AWLOCK = 1,
parameter USE_S0_AWCACHE = 1,
parameter USE_S0_AWQOS = 1,
parameter USE_S0_AWPROT = 1,
parameter USE_M0_WSTRB = 1,
parameter USE_S0_WLAST = 1,
parameter USE_M0_BID = 1,
parameter USE_M0_BRESP = 1,
parameter USE_S0_BRESP = 1,
parameter USE_M0_ARID = 1,
parameter USE_M0_ARREGION = 1,
parameter USE_M0_ARLEN = 1,
parameter USE_M0_ARSIZE = 1,
parameter USE_M0_ARBURST = 1,
parameter USE_M0_ARLOCK = 1,
parameter USE_M0_ARCACHE = 1,
parameter USE_M0_ARQOS = 1,
parameter USE_S0_ARREGION = 1,
parameter USE_S0_ARLOCK = 1,
parameter USE_S0_ARCACHE = 1,
parameter USE_S0_ARQOS = 1,
parameter USE_S0_ARPROT = 1,
parameter USE_M0_RID = 1,
parameter USE_M0_RRESP = 1,
parameter USE_M0_RLAST = 1,
parameter USE_S0_RRESP = 1,
parameter M0_ID_WIDTH = 3,
parameter S0_ID_WIDTH = 6,
parameter DATA_WIDTH = 512,
parameter WRITE_ADDR_USER_WIDTH = 32,
parameter READ_ADDR_USER_WIDTH = 32,
parameter WRITE_DATA_USER_WIDTH = 32,
parameter WRITE_RESP_USER_WIDTH = 32,
parameter READ_DATA_USER_WIDTH = 32,
parameter ADDR_WIDTH = 32,
parameter USE_S0_AWUSER = 0,
parameter USE_S0_ARUSER = 0,
parameter USE_S0_WUSER = 0,
parameter USE_S0_RUSER = 0,
parameter USE_S0_BUSER = 0,
parameter USE_M0_AWUSER = 0,
parameter USE_M0_ARUSER = 0,
parameter USE_M0_WUSER = 0,
parameter USE_M0_RUSER = 0,
parameter USE_M0_BUSER = 0,
parameter AXI_VERSION = "AXI4"
) (
input wire aclk, // clk.clk
input wire aresetn, // clk_reset.reset_n
output wire [2:0] m0_awid, // m0.awid
output wire [31:0] m0_awaddr, // .awaddr
output wire [7:0] m0_awlen, // .awlen
output wire [2:0] m0_awsize, // .awsize
output wire [1:0] m0_awburst, // .awburst
output wire [0:0] m0_awlock, // .awlock
output wire [3:0] m0_awcache, // .awcache
output wire [2:0] m0_awprot, // .awprot
output wire [3:0] m0_awqos, // .awqos
output wire [3:0] m0_awregion, // .awregion
output wire m0_awvalid, // .awvalid
input wire m0_awready, // .awready
output wire [511:0] m0_wdata, // .wdata
output wire [63:0] m0_wstrb, // .wstrb
output wire m0_wlast, // .wlast
output wire m0_wvalid, // .wvalid
input wire m0_wready, // .wready
input wire [2:0] m0_bid, // .bid
input wire [1:0] m0_bresp, // .bresp
input wire m0_bvalid, // .bvalid
output wire m0_bready, // .bready
output wire [2:0] m0_arid, // .arid
output wire [31:0] m0_araddr, // .araddr
output wire [7:0] m0_arlen, // .arlen
output wire [2:0] m0_arsize, // .arsize
output wire [1:0] m0_arburst, // .arburst
output wire [0:0] m0_arlock, // .arlock
output wire [3:0] m0_arcache, // .arcache
output wire [2:0] m0_arprot, // .arprot
output wire [3:0] m0_arqos, // .arqos
output wire [3:0] m0_arregion, // .arregion
output wire m0_arvalid, // .arvalid
input wire m0_arready, // .arready
input wire [2:0] m0_rid, // .rid
input wire [511:0] m0_rdata, // .rdata
input wire [1:0] m0_rresp, // .rresp
input wire m0_rlast, // .rlast
input wire m0_rvalid, // .rvalid
output wire m0_rready, // .rready
input wire [5:0] s0_awid, // s0.awid
input wire [31:0] s0_awaddr, // .awaddr
input wire [7:0] s0_awlen, // .awlen
input wire [2:0] s0_awsize, // .awsize
input wire [1:0] s0_awburst, // .awburst
input wire [0:0] s0_awlock, // .awlock
input wire [3:0] s0_awcache, // .awcache
input wire [2:0] s0_awprot, // .awprot
input wire [3:0] s0_awqos, // .awqos
input wire [3:0] s0_awregion, // .awregion
input wire s0_awvalid, // .awvalid
output wire s0_awready, // .awready
input wire [511:0] s0_wdata, // .wdata
input wire [63:0] s0_wstrb, // .wstrb
input wire s0_wlast, // .wlast
input wire s0_wvalid, // .wvalid
output wire s0_wready, // .wready
output wire [5:0] s0_bid, // .bid
output wire [1:0] s0_bresp, // .bresp
output wire s0_bvalid, // .bvalid
input wire s0_bready, // .bready
input wire [5:0] s0_arid, // .arid
input wire [31:0] s0_araddr, // .araddr
input wire [7:0] s0_arlen, // .arlen
input wire [2:0] s0_arsize, // .arsize
input wire [1:0] s0_arburst, // .arburst
input wire [0:0] s0_arlock, // .arlock
input wire [3:0] s0_arcache, // .arcache
input wire [2:0] s0_arprot, // .arprot
input wire [3:0] s0_arqos, // .arqos
input wire [3:0] s0_arregion, // .arregion
input wire s0_arvalid, // .arvalid
output wire s0_arready, // .arready
output wire [5:0] s0_rid, // .rid
output wire [511:0] s0_rdata, // .rdata
output wire [1:0] s0_rresp, // .rresp
output wire s0_rlast, // .rlast
output wire s0_rvalid, // .rvalid
input wire s0_rready // .rready
);
altera_axi_bridge #(
.USE_PIPELINE (USE_PIPELINE),
.USE_M0_AWID (USE_M0_AWID),
.USE_M0_AWREGION (USE_M0_AWREGION),
.USE_M0_AWLEN (USE_M0_AWLEN),
.USE_M0_AWSIZE (USE_M0_AWSIZE),
.USE_M0_AWBURST (USE_M0_AWBURST),
.USE_M0_AWLOCK (USE_M0_AWLOCK),
.USE_M0_AWCACHE (USE_M0_AWCACHE),
.USE_M0_AWQOS (USE_M0_AWQOS),
.USE_S0_AWREGION (USE_S0_AWREGION),
.USE_S0_AWLOCK (USE_S0_AWLOCK),
.USE_S0_AWCACHE (USE_S0_AWCACHE),
.USE_S0_AWQOS (USE_S0_AWQOS),
.USE_S0_AWPROT (USE_S0_AWPROT),
.USE_M0_WSTRB (USE_M0_WSTRB),
.USE_S0_WLAST (USE_S0_WLAST),
.USE_M0_BID (USE_M0_BID),
.USE_M0_BRESP (USE_M0_BRESP),
.USE_S0_BRESP (USE_S0_BRESP),
.USE_M0_ARID (USE_M0_ARID),
.USE_M0_ARREGION (USE_M0_ARREGION),
.USE_M0_ARLEN (USE_M0_ARLEN),
.USE_M0_ARSIZE (USE_M0_ARSIZE),
.USE_M0_ARBURST (USE_M0_ARBURST),
.USE_M0_ARLOCK (USE_M0_ARLOCK),
.USE_M0_ARCACHE (USE_M0_ARCACHE),
.USE_M0_ARQOS (USE_M0_ARQOS),
.USE_S0_ARREGION (USE_S0_ARREGION),
.USE_S0_ARLOCK (USE_S0_ARLOCK),
.USE_S0_ARCACHE (USE_S0_ARCACHE),
.USE_S0_ARQOS (USE_S0_ARQOS),
.USE_S0_ARPROT (USE_S0_ARPROT),
.USE_M0_RID (USE_M0_RID),
.USE_M0_RRESP (USE_M0_RRESP),
.USE_M0_RLAST (USE_M0_RLAST),
.USE_S0_RRESP (USE_S0_RRESP),
.M0_ID_WIDTH (M0_ID_WIDTH),
.S0_ID_WIDTH (S0_ID_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.WRITE_ADDR_USER_WIDTH (WRITE_ADDR_USER_WIDTH),
.READ_ADDR_USER_WIDTH (READ_ADDR_USER_WIDTH),
.WRITE_DATA_USER_WIDTH (WRITE_DATA_USER_WIDTH),
.WRITE_RESP_USER_WIDTH (WRITE_RESP_USER_WIDTH),
.READ_DATA_USER_WIDTH (READ_DATA_USER_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.USE_S0_AWUSER (USE_S0_AWUSER),
.USE_S0_ARUSER (USE_S0_ARUSER),
.USE_S0_WUSER (USE_S0_WUSER),
.USE_S0_RUSER (USE_S0_RUSER),
.USE_S0_BUSER (USE_S0_BUSER),
.USE_M0_AWUSER (USE_M0_AWUSER),
.USE_M0_ARUSER (USE_M0_ARUSER),
.USE_M0_WUSER (USE_M0_WUSER),
.USE_M0_RUSER (USE_M0_RUSER),
.USE_M0_BUSER (USE_M0_BUSER),
.AXI_VERSION (AXI_VERSION),
.BURST_LENGTH_WIDTH (8),
.LOCK_WIDTH (1)
) axi_bridge_0 (
.aclk (aclk), // input, width = 1, clk.clk
.aresetn (aresetn), // input, width = 1, clk_reset.reset_n
.s0_awid (s0_awid), // input, width = 6, s0.awid
.s0_awaddr (s0_awaddr), // input, width = 32, .awaddr
.s0_awlen (s0_awlen), // input, width = 8, .awlen
.s0_awsize (s0_awsize), // input, width = 3, .awsize
.s0_awburst (s0_awburst), // input, width = 2, .awburst
.s0_awlock (s0_awlock), // input, width = 1, .awlock
.s0_awcache (s0_awcache), // input, width = 4, .awcache
.s0_awprot (s0_awprot), // input, width = 3, .awprot
.s0_awqos (s0_awqos), // input, width = 4, .awqos
.s0_awregion (s0_awregion), // input, width = 4, .awregion
.s0_awvalid (s0_awvalid), // input, width = 1, .awvalid
.s0_awready (s0_awready), // output, width = 1, .awready
.s0_wdata (s0_wdata), // input, width = 512, .wdata
.s0_wstrb (s0_wstrb), // input, width = 64, .wstrb
.s0_wlast (s0_wlast), // input, width = 1, .wlast
.s0_wvalid (s0_wvalid), // input, width = 1, .wvalid
.s0_wready (s0_wready), // output, width = 1, .wready
.s0_bid (s0_bid), // output, width = 6, .bid
.s0_bresp (s0_bresp), // output, width = 2, .bresp
.s0_bvalid (s0_bvalid), // output, width = 1, .bvalid
.s0_bready (s0_bready), // input, width = 1, .bready
.s0_arid (s0_arid), // input, width = 6, .arid
.s0_araddr (s0_araddr), // input, width = 32, .araddr
.s0_arlen (s0_arlen), // input, width = 8, .arlen
.s0_arsize (s0_arsize), // input, width = 3, .arsize
.s0_arburst (s0_arburst), // input, width = 2, .arburst
.s0_arlock (s0_arlock), // input, width = 1, .arlock
.s0_arcache (s0_arcache), // input, width = 4, .arcache
.s0_arprot (s0_arprot), // input, width = 3, .arprot
.s0_arqos (s0_arqos), // input, width = 4, .arqos
.s0_arregion (s0_arregion), // input, width = 4, .arregion
.s0_arvalid (s0_arvalid), // input, width = 1, .arvalid
.s0_arready (s0_arready), // output, width = 1, .arready
.s0_rid (s0_rid), // output, width = 6, .rid
.s0_rdata (s0_rdata), // output, width = 512, .rdata
.s0_rresp (s0_rresp), // output, width = 2, .rresp
.s0_rlast (s0_rlast), // output, width = 1, .rlast
.s0_rvalid (s0_rvalid), // output, width = 1, .rvalid
.s0_rready (s0_rready), // input, width = 1, .rready
.m0_awid (m0_awid), // output, width = 3, m0.awid
.m0_awaddr (m0_awaddr), // output, width = 32, .awaddr
.m0_awlen (m0_awlen), // output, width = 8, .awlen
.m0_awsize (m0_awsize), // output, width = 3, .awsize
.m0_awburst (m0_awburst), // output, width = 2, .awburst
.m0_awlock (m0_awlock), // output, width = 1, .awlock
.m0_awcache (m0_awcache), // output, width = 4, .awcache
.m0_awprot (m0_awprot), // output, width = 3, .awprot
.m0_awqos (m0_awqos), // output, width = 4, .awqos
.m0_awregion (m0_awregion), // output, width = 4, .awregion
.m0_awvalid (m0_awvalid), // output, width = 1, .awvalid
.m0_awready (m0_awready), // input, width = 1, .awready
.m0_wdata (m0_wdata), // output, width = 512, .wdata
.m0_wstrb (m0_wstrb), // output, width = 64, .wstrb
.m0_wlast (m0_wlast), // output, width = 1, .wlast
.m0_wvalid (m0_wvalid), // output, width = 1, .wvalid
.m0_wready (m0_wready), // input, width = 1, .wready
.m0_bid (m0_bid), // input, width = 3, .bid
.m0_bresp (m0_bresp), // input, width = 2, .bresp
.m0_bvalid (m0_bvalid), // input, width = 1, .bvalid
.m0_bready (m0_bready), // output, width = 1, .bready
.m0_arid (m0_arid), // output, width = 3, .arid
.m0_araddr (m0_araddr), // output, width = 32, .araddr
.m0_arlen (m0_arlen), // output, width = 8, .arlen
.m0_arsize (m0_arsize), // output, width = 3, .arsize
.m0_arburst (m0_arburst), // output, width = 2, .arburst
.m0_arlock (m0_arlock), // output, width = 1, .arlock
.m0_arcache (m0_arcache), // output, width = 4, .arcache
.m0_arprot (m0_arprot), // output, width = 3, .arprot
.m0_arqos (m0_arqos), // output, width = 4, .arqos
.m0_arregion (m0_arregion), // output, width = 4, .arregion
.m0_arvalid (m0_arvalid), // output, width = 1, .arvalid
.m0_arready (m0_arready), // input, width = 1, .arready
.m0_rid (m0_rid), // input, width = 3, .rid
.m0_rdata (m0_rdata), // input, width = 512, .rdata
.m0_rresp (m0_rresp), // input, width = 2, .rresp
.m0_rlast (m0_rlast), // input, width = 1, .rlast
.m0_rvalid (m0_rvalid), // input, width = 1, .rvalid
.m0_rready (m0_rready), // output, width = 1, .rready
.s0_awuser (32'b00000000000000000000000000000000), // (terminated),
.s0_wuser (32'b00000000000000000000000000000000), // (terminated),
.s0_buser (), // (terminated),
.s0_aruser (32'b00000000000000000000000000000000), // (terminated),
.s0_ruser (), // (terminated),
.m0_awuser (), // (terminated),
.m0_wuser (), // (terminated),
.m0_buser (32'b00000000000000000000000000000000), // (terminated),
.m0_aruser (), // (terminated),
.m0_ruser (32'b00000000000000000000000000000000), // (terminated),
.m0_wid (), // (terminated),
.s0_wid (6'b000000) // (terminated),
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_M_V
`define SKY130_FD_SC_LP__AND2_M_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_m (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_m (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_M_V
|
//`#start header` -- edit after this line, do not edit this line
// ========================================
// Description:
// This component is designed to drive one or more LEDs interfaced
// with the Worldsemi WS2811 RGB LED Driver
//
// 05/27/2013 v1.0 Mark Hastings Initial working version
// 05/28/2013 v1.1 Mark Hastings Added complete state
// 10/01/2014 v1.3 Mark Hastings Seperated the two interrupts
//
// ========================================
`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 11/12/2011 at 15:55
// Component: B_WS2811_v1_3
module B_WS2811_v1_3 (
firq,
cirq,
sout,
cntl,
clk,
reset
);
output cirq;
output firq;
output sout;
output cntl;
input clk;
input reset;
//`#start body` -- edit after this line, do not edit this line
reg dataOut; // Serial Data Out
reg [1:0] dpAddr; // Data Path Address Control
reg [1:0] state; // Main state machine varaible
reg [2:0] bitCount; // Bit counter
reg pwmCntl; // Enable PWM
reg xferCmpt; // Transfer Complete
wire shiftOut; // Data out from data path
wire fifoEmpty; // FIFO empty signal
wire fifoNotFull; // FIFO not full signal
wire enable; // Enable module
wire cntl; // Spare control output
wire zeroBit;
wire oneBit;
wire zeroCmp; // Compare for zero output
wire oneCmp; // Compare for one output
wire pwmTC; // Pwm terminal count
wire npwmTC;
wire restart; // Transfer Enable
wire fifo_irq_en;
wire xfrCmpt_irq_en;
wire next_row;
assign npwmTC = pwmTC;
assign zeroBit = !zeroCmp; //
assign oneBit = !oneCmp; //
assign sout = dataOut;
// Datapath Shift state
parameter DP_IDLE = 2'b00;
parameter DP_LOAD = 2'b01;
parameter DP_SHIFT = 2'b10;
// Datapath PWM state
parameter PWM_RUN = 1'b0;
parameter PWM_RESET = 1'b1;
// Main State machine states
parameter STATE_IDLE = 2'b00; // Idle state while waiting for data
parameter STATE_START = 2'b01; // Start sending data
parameter STATE_DATA = 2'b10; // Send 3 bytes
parameter STATE_DONE = 2'b11; // FIFO empty
wire [7:0] control; // Control Register
wire [7:0] status; // Status reg bus
/* Instantiate the control register */
cy_psoc3_control #(.cy_force_order(1))
ctrl(
/* output [07:00] */ .control(control)
);
cy_psoc3_status #(.cy_force_order(`TRUE), .cy_md_select(8'b00000000)) StatusReg (
/* input [07:00] */ .status(status), // Status Bits
/* input */ .reset(reset), // Reset from interconnect
/* input */ .clock(clk) // Clock used for registering data
);
// Control register assignments
assign enable = control[0]; // Enable operation
assign restart = control[1]; // Restart transfer after string complete
assign cntl = control[2]; // Control signal output
assign fifo_irq_en = control[3]; // Enable Fifo interrupt
assign xfrCmpt_irq_en = control[4]; // Enable xfrcmpt interrupt
assign next_row = control[5]; // Next row of LEDs
// Status bit assignment
assign status[0] = fifoEmpty; // Status of fifoEmpty
assign status[1] = fifoNotFull; // Not full fifo status
assign status[6] = xferCmpt; // Set when xfer complete
assign status[7] = enable; // Reading enable status
assign status[5:2] = 4'b0000;
assign firq = (fifoEmpty & fifo_irq_en) & enable;
assign cirq = (xferCmpt & xfrCmpt_irq_en) & enable;
always @(posedge clk or posedge reset )
begin
if (reset)
begin
state <= STATE_IDLE;
bitCount = 3'b000;
dpAddr <= DP_IDLE;
dataOut <= 1'b0;
pwmCntl <= PWM_RESET;
xferCmpt <= 1'b0;
end
else
begin
case (state)
STATE_IDLE: // Wait for data to be ready
begin
bitCount = 3'b000;
dpAddr <= DP_IDLE;
dataOut <= 1'b0;
xferCmpt <= 1'b0;
pwmCntl <= PWM_RESET;
if(enable & !fifoEmpty)
begin
state <= STATE_START;
pwmCntl <= PWM_RUN;
end
else
begin
state <= STATE_IDLE;
pwmCntl <= PWM_RESET;
end
end
STATE_START: // Send start bit
begin
bitCount = 3'b000;
state <= STATE_DATA;
dpAddr <= DP_LOAD;
dataOut <= 1'b1; // Data always starts high
pwmCntl <= PWM_RESET;
xferCmpt <= 1'b0;
end
STATE_DATA: // Shift out the bits
begin
xferCmpt <= 1'b0;
dataOut <= shiftOut ? oneBit : zeroBit;
pwmCntl <= PWM_RUN;
if(pwmTC) // At TC we have end of bit
begin
bitCount = bitCount + 3'b001;
if(bitCount == 3'b000) // Check of end of byte
begin
if(enable & !fifoEmpty) // More data?
begin
state <= STATE_START;
end
else
begin
state <= STATE_DONE; // No more data
end
dpAddr <= DP_IDLE;
end
else // Not end of byte, shift another bit
begin
state <= STATE_DATA;
dpAddr <= DP_SHIFT;
end
end
else // No terminal count, keep driving 1 or 0
begin
dpAddr <= DP_IDLE;
state <= STATE_DATA;
end
end
STATE_DONE: // Data complete
begin
xferCmpt <= 1'b1;
dataOut <= 1'b0;
if(next_row)
begin
state <= STATE_IDLE;
end
else
begin
state <= STATE_DONE;
end
end
endcase
end
end
//`#end` -- edit above this line, do not edit this line
cy_psoc3_dp8 #(.cy_dpconfig_a(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: Idle State*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: Data Load*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: Bit Shift*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
8'hFF, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*CFG13-12: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
}
)) dshifter(
/* input */ .reset(reset),
/* input */ .clk(clk),
// /* input [02:00] */ .cs_addr({1'b0,dpAddr[1:0]}),
/* input [02:00] */ .cs_addr({1'b0,dpAddr[1:0]}),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(shiftOut),
/* output */ .f0_bus_stat(fifoNotFull),
/* output */ .f0_blk_stat(fifoEmpty),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat()
);
cy_psoc3_dp8 #(.a0_init_a(24), .a1_init_a(24), .d0_init_a(20),
.d1_init_a(12),
.cy_dpconfig_a(
{
`CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: Decrement*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: Load*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: Load Disable*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: Load Disable*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
8'hFF, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A0_D1, `SC_CMPA_A0_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*CFG13-12: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
}
)) pwm8(
/* input */ .reset(reset),
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr({1'b0,pwmCntl,pwmTC}),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(zeroCmp),
/* output */ .z0(pwmTC),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(oneCmp),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat()
);
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this line
|
//
// Copyright 2014-2015 Ettus Research LLC
//
module noc_block_channelizer_256 #(
parameter NOC_ID = 64'h11FB_0000_0000_0000,
parameter STR_SINK_FIFOSIZE = 11)
(
input bus_clk, input bus_rst,
input ce_clk, input ce_rst,
input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
output [63:0] debug,
output [31:0] t_loop_data_out
);
////////////////////////////////////////////////////////////
//
// RFNoC Shell
//
////////////////////////////////////////////////////////////
wire [31:0] set_data;
wire [7:0] set_addr;
wire set_stb;
wire [63:0] cmdout_tdata, ackin_tdata;
wire cmdout_tlast, cmdout_tvalid, cmdout_tready, ackin_tlast, ackin_tvalid, ackin_tready;
wire [63:0] str_sink_tdata, str_src_tdata;
wire str_sink_tlast, str_sink_tvalid, str_sink_tready, str_src_tlast, str_src_tvalid, str_src_tready;
wire clear_tx_seqnum;
noc_shell #(
.NOC_ID(NOC_ID),
.STR_SINK_FIFOSIZE(STR_SINK_FIFOSIZE))
inst_noc_shell (
.bus_clk(bus_clk), .bus_rst(bus_rst),
.i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready),
.o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready),
// Computer Engine Clock Domain
.clk(ce_clk), .reset(ce_rst),
// Control Sink
.set_data(set_data), .set_addr(set_addr), .set_stb(set_stb), .rb_data(64'd0),
// Control Source
.cmdout_tdata(cmdout_tdata), .cmdout_tlast(cmdout_tlast), .cmdout_tvalid(cmdout_tvalid), .cmdout_tready(cmdout_tready),
.ackin_tdata(ackin_tdata), .ackin_tlast(ackin_tlast), .ackin_tvalid(ackin_tvalid), .ackin_tready(ackin_tready),
// Stream Sink
.str_sink_tdata(str_sink_tdata), .str_sink_tlast(str_sink_tlast), .str_sink_tvalid(str_sink_tvalid), .str_sink_tready(str_sink_tready),
// Stream Source
.str_src_tdata(str_src_tdata), .str_src_tlast(str_src_tlast), .str_src_tvalid(str_src_tvalid), .str_src_tready(str_src_tready),
.clear_tx_seqnum(clear_tx_seqnum),
.debug(debug));
////////////////////////////////////////////////////////////
//
// AXI Wrapper
// Convert RFNoC Shell interface into AXI stream interface
//
////////////////////////////////////////////////////////////
wire [31:0] m_axis_data_tdata;
wire m_axis_data_tlast;
wire m_axis_data_tvalid;
wire m_axis_data_tready;
wire [31:0] s_axis_data_tdata;
wire s_axis_data_tlast;
wire s_axis_data_tvalid;
wire s_axis_data_tready;
localparam AXI_WRAPPER_BASE = 128;
localparam SR_NEXT_DST = AXI_WRAPPER_BASE;
// Set next destination in chain
wire [15:0] next_dst;
setting_reg #(
.my_addr(SR_NEXT_DST), .width(16))
sr_next_dst(
.clk(ce_clk), .rst(ce_rst),
.strobe(set_stb), .addr(set_addr), .in(set_data), .out(next_dst), .changed());
axi_wrapper
inst_axi_wrapper (
.clk(ce_clk), .reset(ce_rst),
.clear_tx_seqnum(clear_tx_seqnum),
.next_dst(next_dst),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.i_tdata(str_sink_tdata), .i_tlast(str_sink_tlast), .i_tvalid(str_sink_tvalid), .i_tready(str_sink_tready),
.o_tdata(str_src_tdata), .o_tlast(str_src_tlast), .o_tvalid(str_src_tvalid), .o_tready(str_src_tready),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tlast(m_axis_data_tlast),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_data_tready(m_axis_data_tready),
.s_axis_data_tdata(s_axis_data_tdata),
.s_axis_data_tlast(s_axis_data_tlast),
.s_axis_data_tvalid(s_axis_data_tvalid),
.s_axis_data_tready(s_axis_data_tready),
.m_axis_config_tdata(),
.m_axis_config_tlast(),
.m_axis_config_tvalid(),
.m_axis_config_tready());
////////////////////////////////////////////////////////////
//
// User code
//
////////////////////////////////////////////////////////////
// Control Source Unused
assign cmdout_tdata = 64'd0;
assign cmdout_tlast = 1'b0;
assign cmdout_tvalid = 1'b0;
assign ackin_tready = 1'b1;
channelizer_256 sysgen_dut (
.clk(ce_clk),
.reset_in(ce_rst),
//
.set_addr_in(set_addr),
.set_data_in(set_data),
.set_stb_in(set_stb),
//
.ready_in(m_axis_data_tready),
.last_in(m_axis_data_tlast),
.valid_in(m_axis_data_tvalid),
.data_in(m_axis_data_tdata),
//
.ready_out(s_axis_data_tready),
.valid_out(s_axis_data_tvalid),
.last_out(s_axis_data_tlast),
.data_out(s_axis_data_tdata)
);
endmodule
|
//==================================================================================================
// Filename : gpio.v
// Created On : 2015-01-02 19:44:15
// Last Modified : 2015-05-24 20:58:09
// Revision :
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : 8-bit GPIO module x 4
//
// Register's name:
// - PD: Port Data
// - DD: Data Direction
// - IE: Interrupt Enable (pin)
// - EP: Edge polarity: 0 -> Falling. 1-> Rising
// - IC: Clear interrupt flag
//
// Using a 5-bits address:
// - PTAD @ 0x00 (offset = 0)
// - PTBD @ 0x01
// - PTCD @ 0x02
// - PTDD @ 0x03
//
// - PTADD @ 0x04 (offset = 4)
// - PTBDD @ 0x05
// - PTCDD @ 0x06
// - PTDDD @ 0x07
//
// - PTAIE @ 0x08 (offset = 8)
// - PTBIE @ 0x09
// - PTCIE @ 0x0A
// - PTDIE @ 0x0B
//
// - PTAEP @ 0x0C (offset = 12)
// - PTBEP @ 0x0D
// - PTCEP @ 0x0E
// - PTDEP @ 0x0F
//
// - PTAIC @ 0x10 (offset = 16)
// - PTBIC @ 0x11
// - PTCIC @ 0x12
// - PTDIC @ 0x13
//==================================================================================================
`define GPIO_PD_OFFSET 5'd0
`define GPIO_DD_OFFSET 5'd4
`define GPIO_IE_OFFSET 5'd8
`define GPIO_EP_OFFSET 5'd12
`define GPIO_IC_OFFSET 5'd16
`define GPIO_UA_OFFSET 5'd20 // unimplemented address
`define ADDR_CHECK 5'b11100
module gpio(
input clk,
input rst,
inout [31:0] gpio_inout, // input/output port
input [4:0] gpio_address, // Address
input [31:0] gpio_data_i, // Data from bus
input [3:0] gpio_wr, // Byte select
input gpio_enable, // Enable operation
output reg [31:0] gpio_data_o, // Data to bus
output reg gpio_ready, // Ready operation
output reg [3:0] gpio_interrupt // Active interrupt. One for each port.
);
//--------------------------------------------------------------------------
// wire
//--------------------------------------------------------------------------
wire [31:0] gpio_data_wire_i;
wire enable_write;
wire enable_read;
wire [31:0] interrupt_signal; // Input "edges"
wire int_port_a; // the interrupt signals from port A
wire int_port_b; // the interrupt signals from port B
wire int_port_c; // the interrupt signals from port C
wire int_port_d; // the interrupt signals from port D
//--------------------------------------------------------------------------
// registers
//--------------------------------------------------------------------------
reg [31:0] gpio_data_reg_i;
reg [31:0] gpio_data_reg_o;
reg [31:0] gpio_dd;
reg [31:0] gpio_ie;
reg [31:0] gpio_ep;
//--------------------------------------------------------------------------
// Assignment
//--------------------------------------------------------------------------
assign enable_write = gpio_enable & gpio_wr != 4'b0000; // Enable if Valid operation, and write at least one byte
assign enable_read = (gpio_enable | gpio_ready) & gpio_wr == 4'b0000;
assign int_port_a = |interrupt_signal[7:0]; // OR the signals
assign int_port_b = |interrupt_signal[15:8]; // OR the signals
assign int_port_c = |interrupt_signal[23:16]; // OR the signals
assign int_port_d = |interrupt_signal[31:24]; // OR the signals
//--------------------------------------------------------------------------
// ACK generation
// Assert the ready port each cycle, depending on the enable signal.
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
gpio_ready <= 1'b0;
end
else begin
gpio_ready <= gpio_enable & (gpio_address < `GPIO_UA_OFFSET); // only if valid region
end
end
//--------------------------------------------------------------------------
// Get interrupt "edge"
// The interrupt flag will raise only if, at least one pin is interrupt
// enabled, and is configured as input.
//--------------------------------------------------------------------------
genvar i;
generate
for(i = 0; i < 32; i = i + 1) begin: gpio_interrupt_signal
assign interrupt_signal[i] = ( (gpio_ep[i]) ? gpio_data_reg_i[i] : ~gpio_data_reg_i[i] ) & gpio_ie[i] & ~gpio_dd[i];
end
endgenerate
//--------------------------------------------------------------------------
// Tri-state buffer
//--------------------------------------------------------------------------
generate
for(i = 0; i < 32; i = i + 1) begin: gpio_tristate
assign gpio_inout[i] = (gpio_dd[i]) ? gpio_data_reg_o[i] : 1'bZ; // If output: put data. Else, High-Z
assign gpio_data_wire_i[i] = (gpio_dd[i]) ? gpio_data_reg_o[i] : gpio_inout[i]; // If output: read output register. Else, read pin
end
endgenerate
//--------------------------------------------------------------------------
// Set data direction
// After reset: all ports to input state (avoid "accidents")
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
gpio_dd <= 32'b0;
end
else if(enable_write & (gpio_address & `ADDR_CHECK) == `GPIO_DD_OFFSET) begin
gpio_dd[7:0] <= (gpio_wr[0]) ? gpio_data_i[7:0] : gpio_dd[7:0];
gpio_dd[15:8] <= (gpio_wr[1]) ? gpio_data_i[15:8] : gpio_dd[15:8];
gpio_dd[23:16] <= (gpio_wr[2]) ? gpio_data_i[23:16] : gpio_dd[23:16];
gpio_dd[31:24] <= (gpio_wr[3]) ? gpio_data_i[31:24] : gpio_dd[31:24];
end
else begin
gpio_dd <= gpio_dd;
end
end
//--------------------------------------------------------------------------
// Set data output
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
gpio_data_reg_o <= 32'b0;
end
else if(enable_write & (gpio_address & `ADDR_CHECK) == `GPIO_PD_OFFSET) begin
gpio_data_reg_o[7:0] <= (gpio_wr[0]) ? gpio_data_i[7:0] : gpio_data_reg_o[7:0];
gpio_data_reg_o[15:8] <= (gpio_wr[1]) ? gpio_data_i[15:8] : gpio_data_reg_o[15:8];
gpio_data_reg_o[23:16] <= (gpio_wr[2]) ? gpio_data_i[23:16] : gpio_data_reg_o[23:16];
gpio_data_reg_o[31:24] <= (gpio_wr[3]) ? gpio_data_i[31:24] : gpio_data_reg_o[31:24];
end
else begin
gpio_data_reg_o <= gpio_data_reg_o;
end
end
//--------------------------------------------------------------------------
// Set interrupt enable
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
gpio_ie <= 32'b0;
end
else if(enable_write & (gpio_address & `ADDR_CHECK) == `GPIO_IE_OFFSET) begin
gpio_ie[7:0] <= (gpio_wr[0]) ? gpio_data_i[7:0] : gpio_ie[7:0];
gpio_ie[15:8] <= (gpio_wr[1]) ? gpio_data_i[15:8] : gpio_ie[15:8];
gpio_ie[23:16] <= (gpio_wr[2]) ? gpio_data_i[23:16] : gpio_ie[23:16];
gpio_ie[31:24] <= (gpio_wr[3]) ? gpio_data_i[31:24] : gpio_ie[31:24];
end
else begin
gpio_ie <= gpio_ie;
end
end
//--------------------------------------------------------------------------
// Set edge mode
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
gpio_ep <= 32'b0;
end
else if(enable_write & (gpio_address & `ADDR_CHECK) == `GPIO_IE_OFFSET) begin
gpio_ep[7:0] <= (gpio_wr[0]) ? gpio_data_i[7:0] : gpio_ep[7:0];
gpio_ep[15:8] <= (gpio_wr[1]) ? gpio_data_i[15:8] : gpio_ep[15:8];
gpio_ep[23:16] <= (gpio_wr[2]) ? gpio_data_i[23:16] : gpio_ep[23:16];
gpio_ep[31:24] <= (gpio_wr[3]) ? gpio_data_i[31:24] : gpio_ep[31:24];
end
else begin
gpio_ep <= gpio_ep;
end
end
//--------------------------------------------------------------------------
// Set interrupt signal
//--------------------------------------------------------------------------
always @(posedge clk) begin
if(rst) begin
gpio_interrupt <= 4'b0;
end
else if (enable_write & (gpio_address & `ADDR_CHECK) == `GPIO_IC_OFFSET) begin
gpio_interrupt[0] <= (gpio_wr[0]) ? 1'b0 : gpio_interrupt[0];
gpio_interrupt[1] <= (gpio_wr[1]) ? 1'b0 : gpio_interrupt[1];
gpio_interrupt[2] <= (gpio_wr[2]) ? 1'b0 : gpio_interrupt[2];
gpio_interrupt[3] <= (gpio_wr[3]) ? 1'b0 : gpio_interrupt[3];
end
else begin
gpio_interrupt[0] <= (int_port_a) ? 1'b1 : gpio_interrupt[0];
gpio_interrupt[1] <= (int_port_b) ? 1'b1 : gpio_interrupt[1];
gpio_interrupt[2] <= (int_port_c) ? 1'b1 : gpio_interrupt[2];
gpio_interrupt[3] <= (int_port_d) ? 1'b1 : gpio_interrupt[3];
end
end
//--------------------------------------------------------------------------
// Set data input
// Just sample/register the input data
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
gpio_data_reg_i <= 32'b0;
end
else begin
gpio_data_reg_i <= gpio_data_wire_i;
end
end
//--------------------------------------------------------------------------
// Read
//--------------------------------------------------------------------------
always @(*) begin
if (enable_read) begin
case (gpio_address & `ADDR_CHECK)
`GPIO_PD_OFFSET : gpio_data_o <= gpio_data_reg_i;
`GPIO_DD_OFFSET : gpio_data_o <= gpio_dd;
`GPIO_IE_OFFSET : gpio_data_o <= gpio_ie;
`GPIO_EP_OFFSET : gpio_data_o <= gpio_ep;
`GPIO_IC_OFFSET : gpio_data_o <= 32'h0000_0000;
default : gpio_data_o <= 32'hDEAD_F00D;
endcase
end
else begin
gpio_data_o <= 32'hDEAD_B00B;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSBP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DFSBP_BLACKBOX_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSBP_BLACKBOX_V
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: obc_upper.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module obc_upper (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [7:0] address_a;
input [5:0] address_b;
input clock;
input [1:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [1:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [1:0] sub_wire0;
wire [7:0] sub_wire1;
wire [1:0] q_a = sub_wire0[1:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 64,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 6,
altsyncram_component.width_a = 2,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "2"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "2"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "2"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]"
// Retrieval info: USED_PORT: address_b 0 0 6 0 INPUT NODEFVAL "address_b[5..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 2 0 INPUT NODEFVAL "data_a[1..0]"
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
// Retrieval info: USED_PORT: q_a 0 0 2 0 OUTPUT NODEFVAL "q_a[1..0]"
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 6 0 address_b 0 0 6 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 2 0 data_a 0 0 2 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 2 0 @q_a 0 0 2 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_upper.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_upper.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_upper.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_upper.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_upper_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_upper_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//
// usb 3.0 ltssm and lfps
//
// Copyright (c) 2013 Marshall H.
// All rights reserved.
// This code is released under the terms of the simplified BSD license.
// See LICENSE.TXT for details.
//
module usb3_ltssm (
input wire slow_clk,
input wire local_clk,
input wire reset_n,
input wire vbus_present,
input wire port_rx_valid,
input wire port_rx_elecidle,
input wire [1:0] port_power_state,
output reg port_rx_term,
output reg port_tx_detrx_lpbk,
output reg port_tx_elecidle,
output wire [4:0] ltssm_state,
input wire partner_looking,
input wire partner_detected,
output reg partner_detect,
input wire port_power_ack,
input wire port_power_err,
output reg [1:0] port_power_down,
output reg port_power_go,
output reg training,
output reg train_rxeq,
input wire train_rxeq_pass,
output reg train_active,
input wire train_ts1,
input wire train_ts2,
output reg train_config,
output reg train_idle,
input wire train_idle_pass,
input wire hot_reset,
input wire go_disabled,
input wire go_recovery,
input wire [2:0] go_u,
output reg lfps_send_ack,
output reg lfps_recv_active,
output reg lfps_recv_poll_u1,
output reg lfps_recv_ping,
output reg lfps_recv_reset,
output reg lfps_recv_u2lb,
output reg lfps_recv_u3,
output reg warm_reset,
output wire [4:0] dbg_state
);
`include "usb3_const.v"
reg vbus_present_1, vbus_present_2;
reg port_rx_elecidle_1, port_rx_elecidle_2;
reg port_rx_valid_1, port_rx_valid_2;
reg [4:0] state;
assign dbg_state = state;
reg [4:0] lfps_send_state;
reg [4:0] lfps_recv_state;
reg [24:0] dc; // delay count
reg [4:0] tc; // train count
reg [7:0] tsc; // train send count
//reg [24:0] ic; // interval count
reg [24:0] sc; // send FSM count
reg [24:0] sic; // send internal count
reg [24:0] rc; // receive FSM count
reg [24:0] ric; // receive interval count
reg lfps_send_poll_local; // OR'd with external LFPS request
reg lfps_send_ping_local; // inputs, so either source may invoke
reg lfps_send_u1_local; // an LFPS transmission
reg lfps_send_u2lb_local;
reg lfps_send_u3_local;
reg lfps_send_reset_local;
reg lfps_recv_poll_u1_prev; // used to detect these specific two LFPS
reg lfps_recv_ping_prev; // patterns that dictate repeat lengths
reg [3:0] rx_detect_attempts;
reg [5:0] polling_lfps_sent;
reg [3:0] polling_lfps_received;
reg [3:0] polling_lfps_sent_after_recv;
reg has_trained;
reg go_recovery_latch;
assign ltssm_state = state;
always @(posedge slow_clk) begin
// synchronizers
{vbus_present_2, vbus_present_1} <= {vbus_present_1, vbus_present};
{port_rx_elecidle_2, port_rx_elecidle_1} <= {port_rx_elecidle_1, port_rx_elecidle};
{port_rx_valid_2, port_rx_valid_1} <= {port_rx_valid_1, port_rx_valid};
// default levels for outputs
port_rx_term <= 1;
port_tx_detrx_lpbk <= 0;
port_tx_elecidle <= 1;
partner_detect <= 0;
port_power_go <= 0;
training <= 0;
train_rxeq <= 0;
train_active <= 0;
train_config <= 0;
train_idle <= 0;
lfps_send_ack <= 0;
lfps_send_poll_local <= 0;
lfps_send_ping_local <= 0;
lfps_send_u1_local <= 0;
lfps_send_u2lb_local <= 0;
lfps_send_u3_local <= 0;
lfps_send_reset_local <= 0;
lfps_recv_active <= 0;
lfps_recv_poll_u1 <= 0;
lfps_recv_ping <= 0;
lfps_recv_reset <= 0;
lfps_recv_u2lb <= 0;
lfps_recv_u3 <= 0;
warm_reset <= 0;
go_recovery_latch <= go_recovery;
// counters
`INC(dc);
`INC(sc);
`INC(sic);
`INC(rc);
`INC(ric);
///////////////////////////////////////
// LTSSM FSM
///////////////////////////////////////
case(state)
LT_SS_DISABLED: begin
port_power_down <= POWERDOWN_2;
port_power_go <= 1;
//port_rx_term <= 0;
//if(lfps_recv_reset) state <= LT_RX_DETECT_RESET;
end
LT_SS_INACTIVE: begin
// reset timeout counter and drop to P2 if not already
dc <= 0;
port_power_down <= POWERDOWN_2;
port_power_go <= 1;
if(port_power_ack) state <= LT_SS_INACTIVE_QUIET;
end
LT_SS_INACTIVE_QUIET: begin
if(dc == T_SS_INACTIVE_QUIET) begin
state <= LT_SS_INACTIVE_DETECT_0;
end
end
LT_SS_INACTIVE_DETECT_0: begin
partner_detect <= 1;
if(partner_looking) state <= LT_SS_INACTIVE_DETECT_1;
end
LT_SS_INACTIVE_DETECT_1: begin
dc <= 0;
if(~partner_looking) begin
if(partner_detected) begin
// we're still connected to the host, continue waiting for unplug
state <= LT_SS_INACTIVE_QUIET;
end else begin
// disconnect, start looking for new host
state <= LT_RX_DETECT_RESET;
end
end
end
LT_RX_DETECT_RESET: begin
// IF WARM RESET:
// finish transmitting LFPS.Reset until the duration
// is reached. (TODO)
rx_detect_attempts <= 0;
state <= LT_RX_DETECT_ACTIVE_0;
end
LT_RX_DETECT_ACTIVE_0: begin
partner_detect <= 1;
if(partner_looking) state <= LT_RX_DETECT_ACTIVE_1;
end
LT_RX_DETECT_ACTIVE_1: begin
if(~partner_looking) begin
dc <= 0;
if(partner_detected) begin
// far-end termination detected
polling_lfps_sent <= 0;
polling_lfps_received <= 0;
polling_lfps_sent_after_recv <= 0;
state <= LT_POLLING_LFPS;
end else begin
// not found
`INC(rx_detect_attempts);
if(rx_detect_attempts == 7) begin
state <= LT_SS_DISABLED;
end else begin
state <= LT_RX_DETECT_QUIET;
end
end
end
end
LT_RX_DETECT_QUIET: begin
// wait a bit, then run the farend detection again
if(dc == T_RX_DETECT_QUIET) begin
state <= LT_RX_DETECT_ACTIVE_0;
end
end
LT_POLLING_LFPS: begin
lfps_send_poll_local <= 1;
// receiving Polling.LFPS from link partner
if(lfps_recv_poll_u1) begin
if(polling_lfps_received < 15)
`INC(polling_lfps_received);
end
// confirmed LFPS fsm sent
if(lfps_send_ack) begin
if(polling_lfps_sent_after_recv < 15 && polling_lfps_received > 0)
`INC(polling_lfps_sent_after_recv);
if(polling_lfps_sent < 20)
`INC(polling_lfps_sent);
end
// exit conditions
if( polling_lfps_sent_after_recv >= 4 &&
polling_lfps_sent >= 16 &&
polling_lfps_received >= 2) begin
// done
lfps_send_poll_local <= 0;
state <= LT_POLLING_RXEQ_0;
end
if(dc == T_POLLING_LFPS) begin
// timed out
if(has_trained) state <= LT_SS_DISABLED;
dc <= 0;
end
end
LT_POLLING_RXEQ_0: begin
// wait for any straggling LFPS sends to clear
dc <= 0;
if(lfps_send_state == LFPS_IDLE) state <= LT_POLLING_RXEQ_1;
end
LT_POLLING_RXEQ_1: begin
port_power_down <= POWERDOWN_0;
port_power_go <= 1;
// maintain values, unless overridden below
training <= 1;
train_rxeq <= train_rxeq;
// wait until P0 powerdown is entered so that
// the transceiver proper is ready
if(port_power_ack) begin
// signal to PIPE module, TSEQ 65536 send
train_rxeq <= 1;
end
if(train_rxeq_pass) begin
// reset timeout count and proceed
dc <= 0;
tc <= 0;
state <= LT_POLLING_ACTIVE;
end
end
LT_POLLING_ACTIVE: begin
// send TS1 until 8 consecutive TS are received
training <= 1;
train_active <= 1;
if(train_ts1 | train_ts2) `INC(tc);
if(tc == 8) begin
// received 8 consecutive(TODO?) TS1/TS2
// reset timeout count and proceed
dc <= 0;
tc <= 0;
tsc <= 0;
state <= LT_POLLING_CONFIG;
end
// timeout
if(dc == T_POLLING_ACTIVE) state <= LT_SS_DISABLED;
end
LT_POLLING_CONFIG: begin
training <= 1;
train_config <= 1;
// increment TS2 receive count up to 8
if(train_ts2) begin
if(tc < 8) `INC(tc);
end
// increment TS2 send count, sequence is 2 cycles long
if(tc > 0) if(tsc < 16*2) `INC(tsc);
// exit criteria
// received 8 and sent 16
if(tc == 8 && tsc == 16*2) begin
// reset timeout count and proceed
dc <= 0;
tc <= 0;
tsc <= 0;
state <= LT_POLLING_IDLE;
end
// timeout
if(dc == T_POLLING_CONFIG) state <= LT_SS_DISABLED;
end
LT_POLLING_IDLE: begin
training <= 1;
train_idle <= 1;
if(train_idle_pass) begin
// exit conditions:
// 16 IDLE symbol sent after receiving
// first of at least 8 symbols.
dc <= 0;
if(hot_reset)
state <= LT_HOTRESET;
else
state <= LT_U0;
end
// timeout
if(dc == T_POLLING_IDLE) state <= LT_SS_DISABLED;
end
LT_U0: begin
// N.B. relevant LTSSM timeouts were moved to the Link Layer
// module since it is more practical to have them there, and not here
if(train_ts1) begin
// TS1 detected, go to Recovery
state <= LT_RECOVERY;
end else
if(go_recovery_latch) begin
// link layer had a problem, Recovery
state <= LT_RECOVERY;
end else
if(go_u == 3'b101) begin
// link layer requests U1
port_power_down <= POWERDOWN_1;
port_power_go <= 1;
if(port_power_ack) begin
dc <= 0;
state <= LT_U1;
end
end else
if(go_u == 3'b110) begin
// link layer requests U2
port_power_down <= POWERDOWN_2;
port_power_go <= 1;
if(port_power_ack) state <= LT_U2;
end
if(go_u == 3'b111) begin
// link layer requests U3
port_power_down <= POWERDOWN_2; // our clock depends on PHY so don't suicide
port_power_go <= 1;
if(port_power_ack) state <= LT_U3;
end
end
LT_U1: begin
// U1 power saving state
// PIPE module should turn off its bus and only use LFPS to resume
if(lfps_recv_poll_u1) begin
lfps_send_u1_local <= 1;
end else
//if(lfps_recv_u2lb ) begin
// lfps_send_u2lb_local <= 1;
//end else
if(lfps_send_ack) begin
state <= LT_RECOVERY;
end else
if(go_u == 3'b110) begin
// link layer requests U2
port_power_down <= POWERDOWN_2;
port_power_go <= 1;
if(port_power_ack) state <= LT_U2;
end else
if(dc == LFPS_BURST_PING_NOM) begin
// send Ping.LFPS every 200ms
dc <= 0;
lfps_send_ping_local <= 1;
end
end
LT_U2: begin
// U2 power saving state
if(lfps_recv_u2lb) begin
lfps_send_u2lb_local <= 1;
end
if(lfps_send_ack) begin
state <= LT_RECOVERY;
end
end
LT_U3: begin
// U3 power saving state
if(lfps_recv_u3) begin
lfps_send_u3_local <= 1;
end
if(lfps_send_ack) begin
state <= LT_RECOVERY;
end
end
LT_RECOVERY: begin
dc <= -10;
state <= LT_RECOVERY_WAIT;
end
LT_RECOVERY_WAIT: begin
if(dc == 0) begin
dc <= 0;
tc <= 0;
tsc <= 0;
port_power_down <= POWERDOWN_0;
port_power_go <= 1;
if(port_power_ack) state <= LT_RECOVERY_ACTIVE;
end
end
LT_RECOVERY_ACTIVE: begin
// send TS1 until 8 consecutive TS are received
training <= 1;
train_active <= 1;
if(train_ts1 | train_ts2) `INC(tc);
if(tc == 8) begin
// received 8 consecutive(TODO?) TS1/TS2
// reset timeout count and proceed
dc <= 0;
tc <= 0;
tsc <= 0;
state <= LT_RECOVERY_CONFIG;
end
if(dc == T_RECOV_ACTIVE) state <= LT_SS_INACTIVE;
end
LT_RECOVERY_CONFIG: begin
training <= 1;
train_config <= 1;
// increment TS2 receive count up to 8
if(train_ts2) begin
if(tc < 8) `INC(tc);
end
// increment TS2 send count, sequence is 2 cycles long
// (remember we are in 62.5mhz domain, not 125mhz link)
if(tc > 0) if(tsc < 16*2) `INC(tsc);
// exit criteria
// received 8 and sent 16
if(tc == 8 && tsc == 16*2) begin
// reset timeout count and proceed
dc <= 0;
tc <= 0;
tsc <= 0;
state <= LT_RECOVERY_IDLE;
end
if(dc == T_RECOV_CONFIG) state <= LT_SS_INACTIVE;
end
LT_RECOVERY_IDLE: begin
training <= 1;
train_idle <= 1;
if(train_idle_pass) begin
// exit conditions:
// 16 IDLE symbol sent after receiving
// first of at least 8 symbols.
dc <= 0;
if(hot_reset)
state <= LT_HOTRESET;
else
state <= LT_U0;
end
if(dc == T_RECOV_IDLE) state <= LT_SS_INACTIVE;
end
LT_COMPLIANCE: begin
end
LT_LOOPBACK: begin
end
LT_HOTRESET: begin
// reset Link Error Count is done by Link Layer
if(dc == 3) state <= LT_HOTRESET_ACTIVE;
end
LT_HOTRESET_ACTIVE: begin
state <= LT_HOTRESET_EXIT;
end
LT_HOTRESET_EXIT: begin
state <= LT_U0;
end
LT_RESET: begin
port_rx_term <= 0;
port_power_down <= POWERDOWN_2;
has_trained <= 0;
state <= LT_RX_DETECT_RESET;
end
default: state <= LT_RESET;
endcase
///////////////////////////////////////
// LFPS SEND FSM
///////////////////////////////////////
case(lfps_send_state)
LFPS_RESET: begin
lfps_send_state <= LFPS_IDLE;
end
LFPS_IDLE: begin
if(!training) begin // port_rx_elecidle_2 &&
// clear to go
if(lfps_send_poll_local) begin
// Polling.LFPS
sc <= LFPS_POLLING_NOM;
sic <= LFPS_BURST_POLL_NOM;
lfps_send_state <= LFPS_SEND_1;
end else if(lfps_send_ping_local) begin
// Ping.LFPS
sc <= LFPS_PING_NOM;
sic <= LFPS_BURST_PING_NOM;
lfps_send_state <= LFPS_SEND_1;
end else if(lfps_send_u1_local) begin
// U1 Exit
sc <= LFPS_U1EXIT_NOM;
sic <= LFPS_U1EXIT_NOM;
lfps_send_state <= LFPS_SEND_1;
end else if(lfps_send_u2lb_local) begin
// U2 Exit
sc <= LFPS_U2LBEXIT_NOM;
sic <= LFPS_U2LBEXIT_NOM;
lfps_send_state <= LFPS_SEND_1;
end else if(lfps_send_u3_local) begin
// U3 Exit
sc <= LFPS_U3WAKEUP_NOM;
sic <= LFPS_U3WAKEUP_NOM;
lfps_send_state <= LFPS_SEND_1;
end
end
if(lfps_send_reset_local) begin
// WarmReset
lfps_send_state <= LFPS_SEND_1;
end
end
LFPS_SEND_1: begin
// decide how to send LFPS based on power state
if(port_power_state == POWERDOWN_0) begin
port_tx_elecidle <= 1;
port_tx_detrx_lpbk <= 1;
end else begin
port_tx_elecidle <= 0;
end
// decrement pulse width and repeat interval
`DEC(sc);
`DEC(sic);
if(sc == 1) lfps_send_state <= LFPS_SEND_2;
if(lfps_send_reset_local) begin
// special case here -- WarmReset must be ack'd
// and in response send LFPS until it's deasserted by host
lfps_send_state <= lfps_send_state;
// catch the rising edge
if(port_rx_elecidle_2) begin
lfps_send_state <= LFPS_IDLE;
end
end
end
LFPS_SEND_2: begin
// decrement repeat interval
`DEC(sic);
if(sic == 0) begin
lfps_send_ack <= 1;
lfps_send_state <= LFPS_IDLE;
end
end
LFPS_SEND_3: begin
// keep
end
default: lfps_send_state <= LFPS_RESET;
endcase
///////////////////////////////////////
// LFPS RECEIVE FSM
///////////////////////////////////////
case(lfps_recv_state)
LFPS_RESET: begin
lfps_recv_state <= LFPS_IDLE;
lfps_recv_poll_u1_prev <= 0;
lfps_recv_ping_prev <= 0;
end
LFPS_IDLE: begin
// lfps burst begin
if(~port_rx_elecidle_2 & ~port_rx_valid_2) begin
rc <= 0;
lfps_recv_state <= LFPS_RECV_1;
end
end
LFPS_RECV_1: begin
// lfps burst end
// detect WarmReset by seeing if LFPS continues past tResetDelay
if(rc > LFPS_RESET_DELAY) begin
// want to send LFPS to signal we acknowledge the WarmReset
// N.B. per spec this is not acceptable during SS.Disabled
if(~port_rx_elecidle_2) lfps_send_reset_local <= 1;
end
if(rc == LFPS_U1EXIT_MIN) begin
// link partner is sending U1Exit handshake, reciprocate
lfps_recv_active <= 1;
lfps_recv_poll_u1 <= 1;
end
if(rc == LFPS_U2LBEXIT_MIN) begin
// link partner is sending U2/LBExit handshake, reciprocate
lfps_recv_active <= 1;
lfps_recv_u2lb <= 1;
end
if(rc == LFPS_U3WAKEUP_MIN) begin
// link partner is sending U3 wakeup, reciprocate
lfps_recv_active <= 1;
lfps_recv_u3 <= 1;
end
// wait for rising edge
if(port_rx_elecidle_2) begin
lfps_recv_state <= LFPS_IDLE;
lfps_recv_active <= 1;
// reset these by default
lfps_recv_poll_u1_prev <= 0;
lfps_recv_ping_prev <= 0;
ric <= 0;
if(rc >= LFPS_POLLING_MIN && rc < LFPS_POLLING_MAX) begin
// Polling.LFPS (or U1.Exit)
if(lfps_recv_poll_u1_prev) begin
// we've received this once already
// now check burst length parameters
if(ric >= LFPS_BURST_POLL_MIN && ric < LFPS_BURST_POLL_MAX)
lfps_recv_poll_u1 <= 1;
end else
lfps_recv_active <= 0;
lfps_recv_poll_u1_prev <= 1;
ric <= 0;
end else if(rc >= LFPS_PING_MIN && rc < LFPS_PING_MAX) begin
// Ping.LFPS
if(lfps_recv_ping_prev) begin
// we've received this once already
// now check burst length parameters
if(ric >= LFPS_BURST_PING_MIN && ric < LFPS_BURST_PING_MAX)
lfps_recv_ping <= 1;
end else
lfps_recv_active <= 0;
lfps_recv_ping_prev <= 1;
ric <= 0;
end else if(rc >= LFPS_RESET_MIN && rc < LFPS_RESET_MAX) begin
// WarmReset
lfps_recv_reset <= 1;
//end else if(rc >= LFPS_U1EXIT_MIN && rc < LFPS_U1EXIT_MAX) begin
// U1.Exit
// lfps_recv_poll_u1 <= 1;
//end else if(rc >= LFPS_U2LBEXIT_MIN && rc < LFPS_U2LBEXIT_MAX) begin
// U2/Loopback.Exit
// lfps_recv_u2lb <= 1;
//end else if(rc >= LFPS_U3WAKEUP_MIN && rc < LFPS_U3WAKEUP_MAX) begin
// U3.Wakeup
// lfps_recv_u3 <= 1;
end else begin
// invalid burst
//lfps_recv_state <= LFPS_IDLE;
lfps_recv_active <= 0;
end
end
end
LFPS_RECV_2: begin
// just wait for end of host LFPS to squelch generation of erroneous transfers
if(port_rx_elecidle_2) begin
ric <= 0;
lfps_recv_state <= LFPS_IDLE;
end
end
LFPS_RECV_3: begin
end
default: lfps_recv_state <= LFPS_RESET;
endcase
if(go_disabled) begin
// SS.Disabled
state <= LT_SS_DISABLED;
end
//if(hot_reset && state != LT_SS_DISABLED) begin
// Hot Reset (TS2 Reset bit)
// dc <= 0;
// state <= LT_HOTRESET;
//end
if(lfps_recv_reset && state != LT_SS_DISABLED) begin
// Warm Reset (LFPS)
warm_reset <= 1;
state <= LT_RX_DETECT_RESET;
end
if(~reset_n | ~vbus_present_2) begin
// reset
state <= LT_RESET;
lfps_send_state <= LFPS_RESET;
lfps_recv_state <= LFPS_RESET;
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9671_channel (
// adc interface
adc_clk,
adc_rst,
adc_valid,
adc_data,
adc_or,
// channel interface
adc_dfmt_valid,
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter CHID = 0;
// adc interface
input adc_clk;
input adc_rst;
input adc_valid;
input [15:0] adc_data;
input adc_or;
// channel interface
output adc_dfmt_valid;
output [15:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
wire [ 3:0] adc_pnseq_sel_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
// instantiations
axi_ad9671_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_valid (adc_valid),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
ad_datafmt #(.DATA_WIDTH(16)) i_ad_datafmt (
.clk (adc_clk),
.valid (adc_valid),
.data (adc_data),
.valid_out (adc_dfmt_valid),
.data_out (adc_dfmt_data),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`ifndef _sixbitfactorial_incl
`define _sixbitfactorial_incl
`include "sixbitmul.v"
`include "multiplexer.v"
module sixbitfactorial(ain, out, overflow);
input[5:0] ain;
output[5:0] out;
output overflow;
wire[15:0] ovf;
wire[15:0] ovf_sum;
wire[5:0] fact1;
wire[5:0] fact2;
wire[5:0] fact3;
wire[5:0] fact4;
wire[5:0] fact5;
wire[5:0] fact6;
wire[5:0] fact7;
wire[5:0] fact8;
wire[5:0] fact9;
wire[5:0] fact10;
wire[5:0] fact11;
wire[5:0] fact12;
wire[5:0] fact13;
wire[5:0] fact14;
wire[5:0] fact15;
wire[5:0] tmpout;
assign ovf[0] = 0;
assign ovf_sum[0] = 0;
sixbitmul mul1 (1, 1, fact1, ovf[1]);
sixbitmul mul2 (fact1, 2, fact2, ovf[2]);
sixbitmul mul3 (fact2, 3, fact3, ovf[3]);
sixbitmul mul4 (fact3, 4, fact4, ovf[4]);
sixbitmul mul5 (fact4, 5, fact5, ovf[5]);
sixbitmul mul6 (fact5, 6, fact6, ovf[6]);
sixbitmul mul7 (fact6, 7, fact7, ovf[7]);
sixbitmul mul8 (fact7, 8, fact8, ovf[8]);
sixbitmul mul9 (fact8, 9, fact9, ovf[9]);
sixbitmul mul10 (fact9, 10, fact10, ovf[10]);
sixbitmul mul11 (fact10, 11, fact11, ovf[11]);
sixbitmul mul12 (fact11, 12, fact12, ovf[12]);
sixbitmul mul13 (fact12, 12, fact13, ovf[13]);
sixbitmul mul14 (fact13, 12, fact14, ovf[14]);
sixbitmul mul15 (fact14, 12, fact15, ovf[15]);
or (ovf_sum[1], ovf_sum[0], ovf[1]);
or (ovf_sum[2], ovf_sum[1], ovf[2]);
or (ovf_sum[3], ovf_sum[2], ovf[3]);
or (ovf_sum[4], ovf_sum[3], ovf[4]);
or (ovf_sum[5], ovf_sum[4], ovf[5]);
or (ovf_sum[6], ovf_sum[5], ovf[6]);
or (ovf_sum[7], ovf_sum[6], ovf[7]);
or (ovf_sum[8], ovf_sum[7], ovf[8]);
or (ovf_sum[9], ovf_sum[8], ovf[9]);
or (ovf_sum[10], ovf_sum[9], ovf[10]);
or (ovf_sum[11], ovf_sum[10], ovf[11]);
or (ovf_sum[12], ovf_sum[11], ovf[12]);
or (ovf_sum[13], ovf_sum[12], ovf[13]);
or (ovf_sum[14], ovf_sum[13], ovf[14]);
or (ovf_sum[15], ovf_sum[14], ovf[15]);
multiplexer mux1 (1, fact1, fact2, fact3, fact4, fact5, fact6, fact7, fact8, fact9, fact10,
fact11, fact12, fact13, fact14, fact15, ain[3:0], tmpout);
assign out = (ain[4] || ain[5]) ? 0 : tmpout;
assign overflow = (ain[4] || ain[5]) ? 1 : ovf_sum[ain[3:0]];
endmodule
`endif
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Mar 28 02:26:33 2017
// Host : DESKTOP-B1QME94 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dds_compiler_0_sim_netlist.v
// Design : dds_compiler_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "dds_compiler_0,dds_compiler_v6_0_13,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "dds_compiler_v6_0_13,Vivado 2016.4" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(aclk,
s_axis_phase_tvalid,
s_axis_phase_tdata,
m_axis_data_tvalid,
m_axis_data_tdata);
(* x_interface_info = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *) input aclk;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TVALID" *) input s_axis_phase_tvalid;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TDATA" *) input [23:0]s_axis_phase_tdata;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID" *) output m_axis_data_tvalid;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA" *) output [15:0]m_axis_data_tdata;
wire aclk;
wire [15:0]m_axis_data_tdata;
wire m_axis_data_tvalid;
wire [23:0]s_axis_phase_tdata;
wire s_axis_phase_tvalid;
wire NLW_U0_debug_axi_resync_in_UNCONNECTED;
wire NLW_U0_debug_core_nd_UNCONNECTED;
wire NLW_U0_debug_phase_nd_UNCONNECTED;
wire NLW_U0_event_phase_in_invalid_UNCONNECTED;
wire NLW_U0_event_pinc_invalid_UNCONNECTED;
wire NLW_U0_event_poff_invalid_UNCONNECTED;
wire NLW_U0_event_s_config_tlast_missing_UNCONNECTED;
wire NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED;
wire NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED;
wire NLW_U0_event_s_phase_tlast_missing_UNCONNECTED;
wire NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED;
wire NLW_U0_m_axis_data_tlast_UNCONNECTED;
wire NLW_U0_m_axis_phase_tlast_UNCONNECTED;
wire NLW_U0_m_axis_phase_tvalid_UNCONNECTED;
wire NLW_U0_s_axis_config_tready_UNCONNECTED;
wire NLW_U0_s_axis_phase_tready_UNCONNECTED;
wire [0:0]NLW_U0_debug_axi_chan_in_UNCONNECTED;
wire [21:0]NLW_U0_debug_axi_pinc_in_UNCONNECTED;
wire [21:0]NLW_U0_debug_axi_poff_in_UNCONNECTED;
wire [21:0]NLW_U0_debug_phase_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_data_tuser_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_phase_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_phase_tuser_UNCONNECTED;
(* C_ACCUMULATOR_WIDTH = "22" *)
(* C_AMPLITUDE = "1" *)
(* C_CHANNELS = "1" *)
(* C_CHAN_WIDTH = "1" *)
(* C_DEBUG_INTERFACE = "0" *)
(* C_HAS_ACLKEN = "0" *)
(* C_HAS_ARESETN = "0" *)
(* C_HAS_M_DATA = "1" *)
(* C_HAS_M_PHASE = "0" *)
(* C_HAS_PHASEGEN = "1" *)
(* C_HAS_PHASE_OUT = "0" *)
(* C_HAS_SINCOS = "1" *)
(* C_HAS_S_CONFIG = "0" *)
(* C_HAS_S_PHASE = "1" *)
(* C_HAS_TLAST = "0" *)
(* C_HAS_TREADY = "0" *)
(* C_LATENCY = "7" *)
(* C_MEM_TYPE = "1" *)
(* C_MODE_OF_OPERATION = "0" *)
(* C_MODULUS = "10000" *)
(* C_M_DATA_HAS_TUSER = "0" *)
(* C_M_DATA_TDATA_WIDTH = "16" *)
(* C_M_DATA_TUSER_WIDTH = "1" *)
(* C_M_PHASE_HAS_TUSER = "0" *)
(* C_M_PHASE_TDATA_WIDTH = "1" *)
(* C_M_PHASE_TUSER_WIDTH = "1" *)
(* C_NEGATIVE_COSINE = "0" *)
(* C_NEGATIVE_SINE = "0" *)
(* C_NOISE_SHAPING = "0" *)
(* C_OPTIMISE_GOAL = "0" *)
(* C_OUTPUTS_REQUIRED = "0" *)
(* C_OUTPUT_FORM = "0" *)
(* C_OUTPUT_WIDTH = "12" *)
(* C_PHASE_ANGLE_WIDTH = "12" *)
(* C_PHASE_INCREMENT = "3" *)
(* C_PHASE_INCREMENT_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_PHASE_OFFSET = "0" *)
(* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_POR_MODE = "0" *)
(* C_RESYNC = "0" *)
(* C_S_CONFIG_SYNC_MODE = "0" *)
(* C_S_CONFIG_TDATA_WIDTH = "1" *)
(* C_S_PHASE_HAS_TUSER = "0" *)
(* C_S_PHASE_TDATA_WIDTH = "24" *)
(* C_S_PHASE_TUSER_WIDTH = "1" *)
(* C_USE_DSP48 = "0" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13 U0
(.aclk(aclk),
.aclken(1'b1),
.aresetn(1'b1),
.debug_axi_chan_in(NLW_U0_debug_axi_chan_in_UNCONNECTED[0]),
.debug_axi_pinc_in(NLW_U0_debug_axi_pinc_in_UNCONNECTED[21:0]),
.debug_axi_poff_in(NLW_U0_debug_axi_poff_in_UNCONNECTED[21:0]),
.debug_axi_resync_in(NLW_U0_debug_axi_resync_in_UNCONNECTED),
.debug_core_nd(NLW_U0_debug_core_nd_UNCONNECTED),
.debug_phase(NLW_U0_debug_phase_UNCONNECTED[21:0]),
.debug_phase_nd(NLW_U0_debug_phase_nd_UNCONNECTED),
.event_phase_in_invalid(NLW_U0_event_phase_in_invalid_UNCONNECTED),
.event_pinc_invalid(NLW_U0_event_pinc_invalid_UNCONNECTED),
.event_poff_invalid(NLW_U0_event_poff_invalid_UNCONNECTED),
.event_s_config_tlast_missing(NLW_U0_event_s_config_tlast_missing_UNCONNECTED),
.event_s_config_tlast_unexpected(NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED),
.event_s_phase_chanid_incorrect(NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED),
.event_s_phase_tlast_missing(NLW_U0_event_s_phase_tlast_missing_UNCONNECTED),
.event_s_phase_tlast_unexpected(NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tlast(NLW_U0_m_axis_data_tlast_UNCONNECTED),
.m_axis_data_tready(1'b0),
.m_axis_data_tuser(NLW_U0_m_axis_data_tuser_UNCONNECTED[0]),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_phase_tdata(NLW_U0_m_axis_phase_tdata_UNCONNECTED[0]),
.m_axis_phase_tlast(NLW_U0_m_axis_phase_tlast_UNCONNECTED),
.m_axis_phase_tready(1'b0),
.m_axis_phase_tuser(NLW_U0_m_axis_phase_tuser_UNCONNECTED[0]),
.m_axis_phase_tvalid(NLW_U0_m_axis_phase_tvalid_UNCONNECTED),
.s_axis_config_tdata(1'b0),
.s_axis_config_tlast(1'b0),
.s_axis_config_tready(NLW_U0_s_axis_config_tready_UNCONNECTED),
.s_axis_config_tvalid(1'b0),
.s_axis_phase_tdata(s_axis_phase_tdata),
.s_axis_phase_tlast(1'b0),
.s_axis_phase_tready(NLW_U0_s_axis_phase_tready_UNCONNECTED),
.s_axis_phase_tuser(1'b0),
.s_axis_phase_tvalid(s_axis_phase_tvalid));
endmodule
(* C_ACCUMULATOR_WIDTH = "22" *) (* C_AMPLITUDE = "1" *) (* C_CHANNELS = "1" *)
(* C_CHAN_WIDTH = "1" *) (* C_DEBUG_INTERFACE = "0" *) (* C_HAS_ACLKEN = "0" *)
(* C_HAS_ARESETN = "0" *) (* C_HAS_M_DATA = "1" *) (* C_HAS_M_PHASE = "0" *)
(* C_HAS_PHASEGEN = "1" *) (* C_HAS_PHASE_OUT = "0" *) (* C_HAS_SINCOS = "1" *)
(* C_HAS_S_CONFIG = "0" *) (* C_HAS_S_PHASE = "1" *) (* C_HAS_TLAST = "0" *)
(* C_HAS_TREADY = "0" *) (* C_LATENCY = "7" *) (* C_MEM_TYPE = "1" *)
(* C_MODE_OF_OPERATION = "0" *) (* C_MODULUS = "10000" *) (* C_M_DATA_HAS_TUSER = "0" *)
(* C_M_DATA_TDATA_WIDTH = "16" *) (* C_M_DATA_TUSER_WIDTH = "1" *) (* C_M_PHASE_HAS_TUSER = "0" *)
(* C_M_PHASE_TDATA_WIDTH = "1" *) (* C_M_PHASE_TUSER_WIDTH = "1" *) (* C_NEGATIVE_COSINE = "0" *)
(* C_NEGATIVE_SINE = "0" *) (* C_NOISE_SHAPING = "0" *) (* C_OPTIMISE_GOAL = "0" *)
(* C_OUTPUTS_REQUIRED = "0" *) (* C_OUTPUT_FORM = "0" *) (* C_OUTPUT_WIDTH = "12" *)
(* C_PHASE_ANGLE_WIDTH = "12" *) (* C_PHASE_INCREMENT = "3" *) (* C_PHASE_INCREMENT_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_PHASE_OFFSET = "0" *) (* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) (* C_POR_MODE = "0" *)
(* C_RESYNC = "0" *) (* C_S_CONFIG_SYNC_MODE = "0" *) (* C_S_CONFIG_TDATA_WIDTH = "1" *)
(* C_S_PHASE_HAS_TUSER = "0" *) (* C_S_PHASE_TDATA_WIDTH = "24" *) (* C_S_PHASE_TUSER_WIDTH = "1" *)
(* C_USE_DSP48 = "0" *) (* C_XDEVICEFAMILY = "artix7" *) (* downgradeipidentifiedwarnings = "yes" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13
(aclk,
aclken,
aresetn,
s_axis_phase_tvalid,
s_axis_phase_tready,
s_axis_phase_tdata,
s_axis_phase_tlast,
s_axis_phase_tuser,
s_axis_config_tvalid,
s_axis_config_tready,
s_axis_config_tdata,
s_axis_config_tlast,
m_axis_data_tvalid,
m_axis_data_tready,
m_axis_data_tdata,
m_axis_data_tlast,
m_axis_data_tuser,
m_axis_phase_tvalid,
m_axis_phase_tready,
m_axis_phase_tdata,
m_axis_phase_tlast,
m_axis_phase_tuser,
event_pinc_invalid,
event_poff_invalid,
event_phase_in_invalid,
event_s_phase_tlast_missing,
event_s_phase_tlast_unexpected,
event_s_phase_chanid_incorrect,
event_s_config_tlast_missing,
event_s_config_tlast_unexpected,
debug_axi_pinc_in,
debug_axi_poff_in,
debug_axi_resync_in,
debug_axi_chan_in,
debug_core_nd,
debug_phase,
debug_phase_nd);
input aclk;
input aclken;
input aresetn;
input s_axis_phase_tvalid;
output s_axis_phase_tready;
input [23:0]s_axis_phase_tdata;
input s_axis_phase_tlast;
input [0:0]s_axis_phase_tuser;
input s_axis_config_tvalid;
output s_axis_config_tready;
input [0:0]s_axis_config_tdata;
input s_axis_config_tlast;
output m_axis_data_tvalid;
input m_axis_data_tready;
output [15:0]m_axis_data_tdata;
output m_axis_data_tlast;
output [0:0]m_axis_data_tuser;
output m_axis_phase_tvalid;
input m_axis_phase_tready;
output [0:0]m_axis_phase_tdata;
output m_axis_phase_tlast;
output [0:0]m_axis_phase_tuser;
output event_pinc_invalid;
output event_poff_invalid;
output event_phase_in_invalid;
output event_s_phase_tlast_missing;
output event_s_phase_tlast_unexpected;
output event_s_phase_chanid_incorrect;
output event_s_config_tlast_missing;
output event_s_config_tlast_unexpected;
output [21:0]debug_axi_pinc_in;
output [21:0]debug_axi_poff_in;
output debug_axi_resync_in;
output [0:0]debug_axi_chan_in;
output debug_core_nd;
output [21:0]debug_phase;
output debug_phase_nd;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire event_s_phase_tlast_missing;
wire [11:0]\^m_axis_data_tdata ;
wire m_axis_data_tvalid;
wire [23:0]s_axis_phase_tdata;
wire s_axis_phase_tvalid;
wire NLW_i_synth_debug_axi_resync_in_UNCONNECTED;
wire NLW_i_synth_debug_core_nd_UNCONNECTED;
wire NLW_i_synth_debug_phase_nd_UNCONNECTED;
wire NLW_i_synth_event_phase_in_invalid_UNCONNECTED;
wire NLW_i_synth_event_pinc_invalid_UNCONNECTED;
wire NLW_i_synth_event_poff_invalid_UNCONNECTED;
wire NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED;
wire NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED;
wire NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED;
wire NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED;
wire NLW_i_synth_m_axis_data_tlast_UNCONNECTED;
wire NLW_i_synth_m_axis_phase_tlast_UNCONNECTED;
wire NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED;
wire NLW_i_synth_s_axis_config_tready_UNCONNECTED;
wire NLW_i_synth_s_axis_phase_tready_UNCONNECTED;
wire [0:0]NLW_i_synth_debug_axi_chan_in_UNCONNECTED;
wire [21:0]NLW_i_synth_debug_axi_pinc_in_UNCONNECTED;
wire [21:0]NLW_i_synth_debug_axi_poff_in_UNCONNECTED;
wire [21:0]NLW_i_synth_debug_phase_UNCONNECTED;
wire [14:11]NLW_i_synth_m_axis_data_tdata_UNCONNECTED;
wire [0:0]NLW_i_synth_m_axis_data_tuser_UNCONNECTED;
wire [0:0]NLW_i_synth_m_axis_phase_tdata_UNCONNECTED;
wire [0:0]NLW_i_synth_m_axis_phase_tuser_UNCONNECTED;
assign debug_axi_chan_in[0] = \<const0> ;
assign debug_axi_pinc_in[21] = \<const0> ;
assign debug_axi_pinc_in[20] = \<const0> ;
assign debug_axi_pinc_in[19] = \<const0> ;
assign debug_axi_pinc_in[18] = \<const0> ;
assign debug_axi_pinc_in[17] = \<const0> ;
assign debug_axi_pinc_in[16] = \<const0> ;
assign debug_axi_pinc_in[15] = \<const0> ;
assign debug_axi_pinc_in[14] = \<const0> ;
assign debug_axi_pinc_in[13] = \<const0> ;
assign debug_axi_pinc_in[12] = \<const0> ;
assign debug_axi_pinc_in[11] = \<const0> ;
assign debug_axi_pinc_in[10] = \<const0> ;
assign debug_axi_pinc_in[9] = \<const0> ;
assign debug_axi_pinc_in[8] = \<const0> ;
assign debug_axi_pinc_in[7] = \<const0> ;
assign debug_axi_pinc_in[6] = \<const0> ;
assign debug_axi_pinc_in[5] = \<const0> ;
assign debug_axi_pinc_in[4] = \<const0> ;
assign debug_axi_pinc_in[3] = \<const0> ;
assign debug_axi_pinc_in[2] = \<const0> ;
assign debug_axi_pinc_in[1] = \<const0> ;
assign debug_axi_pinc_in[0] = \<const0> ;
assign debug_axi_poff_in[21] = \<const0> ;
assign debug_axi_poff_in[20] = \<const0> ;
assign debug_axi_poff_in[19] = \<const0> ;
assign debug_axi_poff_in[18] = \<const0> ;
assign debug_axi_poff_in[17] = \<const0> ;
assign debug_axi_poff_in[16] = \<const0> ;
assign debug_axi_poff_in[15] = \<const0> ;
assign debug_axi_poff_in[14] = \<const0> ;
assign debug_axi_poff_in[13] = \<const0> ;
assign debug_axi_poff_in[12] = \<const0> ;
assign debug_axi_poff_in[11] = \<const0> ;
assign debug_axi_poff_in[10] = \<const0> ;
assign debug_axi_poff_in[9] = \<const0> ;
assign debug_axi_poff_in[8] = \<const0> ;
assign debug_axi_poff_in[7] = \<const0> ;
assign debug_axi_poff_in[6] = \<const0> ;
assign debug_axi_poff_in[5] = \<const0> ;
assign debug_axi_poff_in[4] = \<const0> ;
assign debug_axi_poff_in[3] = \<const0> ;
assign debug_axi_poff_in[2] = \<const0> ;
assign debug_axi_poff_in[1] = \<const0> ;
assign debug_axi_poff_in[0] = \<const0> ;
assign debug_axi_resync_in = \<const0> ;
assign debug_core_nd = \<const0> ;
assign debug_phase[21] = \<const0> ;
assign debug_phase[20] = \<const0> ;
assign debug_phase[19] = \<const0> ;
assign debug_phase[18] = \<const0> ;
assign debug_phase[17] = \<const0> ;
assign debug_phase[16] = \<const0> ;
assign debug_phase[15] = \<const0> ;
assign debug_phase[14] = \<const0> ;
assign debug_phase[13] = \<const0> ;
assign debug_phase[12] = \<const0> ;
assign debug_phase[11] = \<const0> ;
assign debug_phase[10] = \<const0> ;
assign debug_phase[9] = \<const0> ;
assign debug_phase[8] = \<const0> ;
assign debug_phase[7] = \<const0> ;
assign debug_phase[6] = \<const0> ;
assign debug_phase[5] = \<const0> ;
assign debug_phase[4] = \<const0> ;
assign debug_phase[3] = \<const0> ;
assign debug_phase[2] = \<const0> ;
assign debug_phase[1] = \<const0> ;
assign debug_phase[0] = \<const0> ;
assign debug_phase_nd = \<const0> ;
assign event_phase_in_invalid = \<const0> ;
assign event_pinc_invalid = \<const0> ;
assign event_poff_invalid = \<const0> ;
assign event_s_config_tlast_missing = \<const0> ;
assign event_s_config_tlast_unexpected = \<const0> ;
assign event_s_phase_chanid_incorrect = \<const0> ;
assign event_s_phase_tlast_unexpected = \<const0> ;
assign m_axis_data_tdata[15] = \^m_axis_data_tdata [11];
assign m_axis_data_tdata[14] = \^m_axis_data_tdata [11];
assign m_axis_data_tdata[13] = \^m_axis_data_tdata [11];
assign m_axis_data_tdata[12] = \^m_axis_data_tdata [11];
assign m_axis_data_tdata[11:0] = \^m_axis_data_tdata [11:0];
assign m_axis_data_tlast = \<const0> ;
assign m_axis_data_tuser[0] = \<const0> ;
assign m_axis_phase_tdata[0] = \<const0> ;
assign m_axis_phase_tlast = \<const0> ;
assign m_axis_phase_tuser[0] = \<const0> ;
assign m_axis_phase_tvalid = \<const0> ;
assign s_axis_config_tready = \<const1> ;
assign s_axis_phase_tready = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
(* C_ACCUMULATOR_WIDTH = "22" *)
(* C_AMPLITUDE = "1" *)
(* C_CHANNELS = "1" *)
(* C_CHAN_WIDTH = "1" *)
(* C_DEBUG_INTERFACE = "0" *)
(* C_HAS_ACLKEN = "0" *)
(* C_HAS_ARESETN = "0" *)
(* C_HAS_M_DATA = "1" *)
(* C_HAS_M_PHASE = "0" *)
(* C_HAS_PHASEGEN = "1" *)
(* C_HAS_PHASE_OUT = "0" *)
(* C_HAS_SINCOS = "1" *)
(* C_HAS_S_CONFIG = "0" *)
(* C_HAS_S_PHASE = "1" *)
(* C_HAS_TLAST = "0" *)
(* C_HAS_TREADY = "0" *)
(* C_LATENCY = "7" *)
(* C_MEM_TYPE = "1" *)
(* C_MODE_OF_OPERATION = "0" *)
(* C_MODULUS = "10000" *)
(* C_M_DATA_HAS_TUSER = "0" *)
(* C_M_DATA_TDATA_WIDTH = "16" *)
(* C_M_DATA_TUSER_WIDTH = "1" *)
(* C_M_PHASE_HAS_TUSER = "0" *)
(* C_M_PHASE_TDATA_WIDTH = "1" *)
(* C_M_PHASE_TUSER_WIDTH = "1" *)
(* C_NEGATIVE_COSINE = "0" *)
(* C_NEGATIVE_SINE = "0" *)
(* C_NOISE_SHAPING = "0" *)
(* C_OPTIMISE_GOAL = "0" *)
(* C_OUTPUTS_REQUIRED = "0" *)
(* C_OUTPUT_FORM = "0" *)
(* C_OUTPUT_WIDTH = "12" *)
(* C_PHASE_ANGLE_WIDTH = "12" *)
(* C_PHASE_INCREMENT = "3" *)
(* C_PHASE_INCREMENT_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_PHASE_OFFSET = "0" *)
(* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_POR_MODE = "0" *)
(* C_RESYNC = "0" *)
(* C_S_CONFIG_SYNC_MODE = "0" *)
(* C_S_CONFIG_TDATA_WIDTH = "1" *)
(* C_S_PHASE_HAS_TUSER = "0" *)
(* C_S_PHASE_TDATA_WIDTH = "24" *)
(* C_S_PHASE_TUSER_WIDTH = "1" *)
(* C_USE_DSP48 = "0" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dds_compiler_v6_0_13_viv i_synth
(.aclk(aclk),
.aclken(1'b0),
.aresetn(1'b0),
.debug_axi_chan_in(NLW_i_synth_debug_axi_chan_in_UNCONNECTED[0]),
.debug_axi_pinc_in(NLW_i_synth_debug_axi_pinc_in_UNCONNECTED[21:0]),
.debug_axi_poff_in(NLW_i_synth_debug_axi_poff_in_UNCONNECTED[21:0]),
.debug_axi_resync_in(NLW_i_synth_debug_axi_resync_in_UNCONNECTED),
.debug_core_nd(NLW_i_synth_debug_core_nd_UNCONNECTED),
.debug_phase(NLW_i_synth_debug_phase_UNCONNECTED[21:0]),
.debug_phase_nd(NLW_i_synth_debug_phase_nd_UNCONNECTED),
.event_phase_in_invalid(NLW_i_synth_event_phase_in_invalid_UNCONNECTED),
.event_pinc_invalid(NLW_i_synth_event_pinc_invalid_UNCONNECTED),
.event_poff_invalid(NLW_i_synth_event_poff_invalid_UNCONNECTED),
.event_s_config_tlast_missing(NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED),
.event_s_config_tlast_unexpected(NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED),
.event_s_phase_chanid_incorrect(NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED),
.event_s_phase_tlast_missing(event_s_phase_tlast_missing),
.event_s_phase_tlast_unexpected(NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED),
.m_axis_data_tdata({\^m_axis_data_tdata [11],NLW_i_synth_m_axis_data_tdata_UNCONNECTED[14:11],\^m_axis_data_tdata [10:0]}),
.m_axis_data_tlast(NLW_i_synth_m_axis_data_tlast_UNCONNECTED),
.m_axis_data_tready(1'b0),
.m_axis_data_tuser(NLW_i_synth_m_axis_data_tuser_UNCONNECTED[0]),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_phase_tdata(NLW_i_synth_m_axis_phase_tdata_UNCONNECTED[0]),
.m_axis_phase_tlast(NLW_i_synth_m_axis_phase_tlast_UNCONNECTED),
.m_axis_phase_tready(1'b0),
.m_axis_phase_tuser(NLW_i_synth_m_axis_phase_tuser_UNCONNECTED[0]),
.m_axis_phase_tvalid(NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED),
.s_axis_config_tdata(1'b0),
.s_axis_config_tlast(1'b0),
.s_axis_config_tready(NLW_i_synth_s_axis_config_tready_UNCONNECTED),
.s_axis_config_tvalid(1'b0),
.s_axis_phase_tdata({1'b0,1'b0,s_axis_phase_tdata[21:0]}),
.s_axis_phase_tlast(1'b0),
.s_axis_phase_tready(NLW_i_synth_s_axis_phase_tready_UNCONNECTED),
.s_axis_phase_tuser(1'b0),
.s_axis_phase_tvalid(s_axis_phase_tvalid));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64)
`pragma protect key_block
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1Ii0/OYJsQ==
`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
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`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
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`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
D+mEShAo+idVddojD4Ocf30d3PeQsjyupmNQjqsNdbpJFSb9AWyTI4HLKIImT0S50Zgb6LGKxa9h
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v0t8M5z/+3rsLJl0oKiKofyP/dx+okR3PXDIyw==
`pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
tcnuNu53+hchNr+pZ1NtakfiTYoR6SYivYJdM66R8/4XDELZLm46FZjh8e2MDPfDIe0TPxgXssIK
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`pragma protect key_keyowner="Xilinx", key_keyname="xilinx_2016_05", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`pragma protect encoding = (enctype="base64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Synplicity", key_keyname="SYNP05_001", key_method="rsa"
`pragma protect encoding = (enctype="base64", line_length=76, bytes=256)
`pragma protect key_block
ry90svkNr/JYbvd/80V2yEkyRl3WtPqNFBcWR+JVlFB+E3lvnDMNnnKeCKDY3C31isquaWCFOT2i
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`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 83296)
`pragma protect data_block
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//======================================================================
//
// uart.v
// ------
// A simple universal asynchronous receiver/transmitter (UART)
// interface. The interface contains 16 byte wide transmit and
// receivea buffers and can handle start and stop bits. But in
// general is rather simple. The primary purpose is as host
// interface for the coretest design. The core also has a
// loopback mode to allow testing of a serial link.
//
// Note that the UART has a separate API interface to allow
// a control core to change settings such as speed. But the core
// has default values to allow it to start operating directly
// after reset. No config should be needed.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014 Secworks Sweden AB
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module uart(
input wire clk,
input wire reset_n,
// External interface
input wire rxd,
output wire txd,
// Internal interface
output wire rx_syn,
output wire [7 : 0] rx_data,
input wire rx_ack,
input wire tx_syn,
input wire [7 : 0] tx_data,
output wire tx_ack,
// Debug
output wire [7 : 0] debug,
// API interface
input wire cs,
input wire we,
input wire [3 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire error
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// API addresses.
parameter ADDR_CORE_NAME0 = 4'h0;
parameter ADDR_CORE_NAME1 = 4'h1;
parameter ADDR_CORE_TYPE = 4'h2;
parameter ADDR_CORE_VERSION = 4'h3;
parameter ADDR_CTRL = 4'h8; // Enable/disable. Loopback on/off.
parameter ADDR_STATUS = 4'h9; // Buffer status.
parameter ADDR_CONFIG = 4'ha; // Num start, data, stop, parity bits.
parameter ADDR_CLK_DIV = 4'hb; // Clock divisor to set bitrate.
// These are WTC registers. The value written is ignored.
parameter ADDR_STAT_PARITY = 4'hc; // Stats: Num parity errors detected.
parameter ADDR_STAT_RX_FULL = 4'hd; // Stats: Num Rx buffer full events.
parameter ADDR_STAT_TX_FULL = 4'he; // Stats: Num Tx buffer full events.
// Core ID constants.
parameter CORE_NAME0 = 32'h75617274; // "uart"
parameter CORE_NAME1 = 32'h20202020; // " "
parameter CORE_TYPE = 32'h20202031; // " 1"
parameter CORE_VERSION = 32'h302e3031; // "0.01"
// The default clock rate is based on target clock frequency
// divided by the bit rate times in order to hit the
// center of the bits. I.e.
// Clock: 50 MHz
// Bitrate: 1200 bps
// Divisor = 5010E6 / (19200 * 4) = 651.041666
// Divisor = 50E6 / (1200 * 4) = 10416.6667
parameter DEFAULT_CLK_DIV = 10417;
parameter DEFAULT_START_BITS = 2'h1;
parameter DEFAULT_STOP_BITS = 2'h1;
parameter DEFAULT_DATA_BITS = 4'h8;
parameter DEFAULT_PARITY = 1'h0;
parameter DEFAULT_ENABLE = 1'h1;
parameter DEFAULT_ILOOPBACK = 1'h0;
parameter DEFAULT_ELOOPBACK = 1'h0;
parameter ITX_IDLE = 0;
parameter ITX_ACK = 1;
parameter ETX_IDLE = 0;
parameter ETX_START = 1;
parameter ETX_DATA = 2;
parameter ETX_PARITY = 3;
parameter ETX_STOP = 4;
parameter ETX_DONE = 5;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [15 : 0] clk_div_reg;
reg [15 : 0] clk_div_new;
reg clk_div_we;
reg enable_bit_reg;
reg enable_bit_new;
reg enable_bit_we;
reg iloopback_bit_reg;
reg iloopback_bit_new;
reg iloopback_bit_we;
reg eloopback_bit_reg;
reg eloopback_bit_new;
reg eloopback_bit_we;
reg [1 : 0] start_bits_reg;
reg [1 : 0] start_bits_new;
reg start_bits_we;
reg [1 : 0] stop_bits_reg;
reg [1 : 0] stop_bits_new;
reg stop_bits_we;
reg [3 : 0] data_bits_reg;
reg [3 : 0] data_bits_new;
reg data_bits_we;
reg parity_bit_reg;
reg parity_bit_new;
reg parity_bit_we;
// Rx data buffer with associated
// read and write pointers as well
// as counter for number of elements
// in the buffer.
reg [7 : 0] rx_buffer [0 : 15];
reg rx_buffer_we;
reg [3 : 0] rx_rd_ptr_reg;
reg [3 : 0] rx_rd_ptr_new;
reg rx_rd_ptr_we;
reg rx_rd_ptr_inc;
reg [3 : 0] rx_wr_ptr_reg;
reg [3 : 0] rx_wr_ptr_new;
reg rx_wr_ptr_we;
reg rx_wr_ptr_inc;
reg [3 : 0] rx_ctr_reg;
reg [3 : 0] rx_ctr_new;
reg rx_ctr_we;
reg rx_ctr_inc;
reg rx_ctr_dec;
// Tx data buffer with associated
// read and write pointers as well
// as counter for number of elements
// in the buffer.
reg [7 : 0] tx_buffer [0 : 15];
reg tx_buffer_we;
reg [3 : 0] tx_rd_ptr_reg;
reg [3 : 0] tx_rd_ptr_new;
reg tx_rd_ptr_we;
reg tx_rd_ptr_inc;
reg [3 : 0] tx_wr_ptr_reg;
reg [3 : 0] tx_wr_ptr_new;
reg tx_wr_ptr_we;
reg tx_wr_ptr_inc;
reg [3 : 0] tx_ctr_reg;
reg [3 : 0] tx_ctr_new;
reg tx_ctr_we;
reg tx_ctr_inc;
reg tx_ctr_dec;
reg rxd_reg;
reg [7 : 0] rxd_byte_reg;
reg [7 : 0] rxd_byte_new;
reg rxd_byte_we;
reg txd_reg;
reg txd_new;
reg txd_we;
reg [7 : 0] txd_byte_reg;
reg [7 : 0] txd_byte_new;
reg txd_byte_we;
reg [2 : 0] rxd_bit_ctr_reg;
reg [2 : 0] rxd_bit_ctr_new;
reg rxd_bit_ctr_we;
reg rxd_bit_ctr_rst;
reg rxd_bit_ctr_inc;
reg [15 : 0] rxd_bitrate_ctr_reg;
reg [15 : 0] rxd_bitrate_ctr_new;
reg rxd_bitrate_ctr_we;
reg rxd_bitrate_ctr_rst;
reg rxd_bitrate_ctr_inc;
reg [2 : 0] txd_bit_ctr_reg;
reg [2 : 0] txd_bit_ctr_new;
reg txd_bit_ctr_we;
reg txd_bit_ctr_rst;
reg txd_bit_ctr_inc;
reg [15 : 0] txd_bitrate_ctr_reg;
reg [15 : 0] txd_bitrate_ctr_new;
reg txd_bitrate_ctr_we;
reg txd_bitrate_ctr_rst;
reg txd_bitrate_ctr_inc;
reg [31 : 0] rx_parity_error_ctr_reg;
reg [31 : 0] rx_parity_error_ctr_new;
reg rx_parity_error_ctr_we;
reg rx_parity_error_ctr_inc;
reg rx_parity_error_ctr_rst;
reg [31 : 0] rx_buffer_full_ctr_reg;
reg [31 : 0] rx_buffer_full_ctr_new;
reg rx_buffer_full_ctr_we;
reg rx_buffer_full_ctr_inc;
reg rx_buffer_full_ctr_rst;
reg [31 : 0] tx_buffer_full_ctr_reg;
reg [31 : 0] tx_buffer_full_ctr_new;
reg tx_buffer_full_ctr_we;
reg tx_buffer_full_ctr_inc;
reg tx_buffer_full_ctr_rst;
reg itx_ctrl_reg;
reg itx_ctrl_new;
reg itx_ctrl_we;
reg [2 : 0] etx_ctrl_reg;
reg [2 : 0] etx_ctrl_new;
reg etx_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_read_data;
reg tmp_error;
reg muxed_txd;
reg muxed_rxd_reg;
reg tmp_rx_syn;
reg [7 : 0] tmp_rx_data;
reg tmp_tx_ack;
reg internal_rx_syn;
reg [7 : 0] internal_rx_data;
reg internal_rx_ack;
reg internal_tx_syn;
reg [7 : 0] internal_tx_data;
reg internal_tx_ack;
reg rx_empty;
reg rx_full;
reg tx_empty;
reg tx_full;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign txd = muxed_txd;
assign rx_syn = tmp_rx_syn;
assign rx_data = tmp_rx_data;
assign tx_ack = tmp_tx_ack;
assign read_data = tmp_read_data;
assign error = tmp_error;
assign debug = {rxd_reg, rxd_reg, rxd_reg, rxd_reg,
rxd_reg, rxd_reg, rxd_reg, rxd_reg};
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with
// asynchronous active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
clk_div_reg <= DEFAULT_CLK_DIV;
start_bits_reg <= DEFAULT_START_BITS;
stop_bits_reg <= DEFAULT_STOP_BITS;
data_bits_reg <= DEFAULT_DATA_BITS;
parity_bit_reg <= DEFAULT_PARITY;
enable_bit_reg <= DEFAULT_ENABLE;
iloopback_bit_reg <= DEFAULT_ILOOPBACK;
eloopback_bit_reg <= DEFAULT_ELOOPBACK;
rxd_reg <= 0;
rxd_byte_reg <= 8'h00;
txd_reg <= 0;
txd_byte_reg <= 8'h00;
rx_rd_ptr_reg <= 4'h0;
rx_wr_ptr_reg <= 4'h0;
rx_ctr_reg <= 4'h0;
tx_rd_ptr_reg <= 4'h0;
tx_wr_ptr_reg <= 4'h0;
tx_ctr_reg <= 4'h0;
rxd_bit_ctr_reg <= 3'b000;
rxd_bitrate_ctr_reg <= 16'h0000;
txd_bit_ctr_reg <= 3'b000;
txd_bitrate_ctr_reg <= 16'h0000;
rx_parity_error_ctr_reg <= 32'h00000000;
rx_buffer_full_ctr_reg <= 32'h00000000;
tx_buffer_full_ctr_reg <= 32'h00000000;
itx_ctrl_reg <= ITX_IDLE;
etx_ctrl_reg <= ETX_IDLE;
end
else
begin
// We sample the rx input port every cycle.
rxd_reg <= rxd;
if (rxd_byte_we)
begin
rxd_byte_reg <= {rxd_byte_reg[6 : 1], rxd_reg};
end
if (txd_we)
begin
txd_reg <= txd_new;
end
if (txd_byte_we)
begin
txd_byte_reg <= tx_buffer[tx_rd_ptr_reg];
end
if (clk_div_we)
begin
clk_div_reg <= clk_div_new;
end
if (start_bits_we)
begin
start_bits_reg <= start_bits_new;
end
if (stop_bits_we)
begin
stop_bits_reg <= stop_bits_new;
end
if (data_bits_we)
begin
data_bits_reg <= data_bits_new;
end
if (parity_bit_we)
begin
parity_bit_reg <= parity_bit_new;
end
if (enable_bit_we)
begin
enable_bit_reg <= enable_bit_new;
end
if (iloopback_bit_we)
begin
iloopback_bit_reg <= iloopback_bit_new;
end
if (eloopback_bit_we)
begin
eloopback_bit_reg <= eloopback_bit_new;
end
if (rx_buffer_we)
begin
rx_buffer[rx_wr_ptr_reg] <= rxd_byte_reg;
end
if (tx_buffer_we)
begin
tx_buffer[tx_wr_ptr_reg] <= tx_data;
end
if (rx_rd_ptr_we)
begin
rx_rd_ptr_reg <= rx_rd_ptr_new;
end
if (rx_wr_ptr_we)
begin
rx_wr_ptr_reg <= rx_wr_ptr_new;
end
if (rx_ctr_we)
begin
rx_ctr_reg <= rx_ctr_new;
end
if (tx_rd_ptr_we)
begin
tx_rd_ptr_reg <= tx_rd_ptr_new;
end
if (tx_wr_ptr_we)
begin
tx_wr_ptr_reg <= tx_wr_ptr_new;
end
if (tx_ctr_we)
begin
tx_ctr_reg <= tx_ctr_new;
end
if (rx_parity_error_ctr_we)
begin
rx_parity_error_ctr_reg <= rx_parity_error_ctr_new;
end
if (rx_buffer_full_ctr_we)
begin
rx_buffer_full_ctr_reg <= rx_buffer_full_ctr_new;
end
if (tx_buffer_full_ctr_we)
begin
tx_buffer_full_ctr_reg <= tx_buffer_full_ctr_new;
end
if (rxd_bit_ctr_we)
begin
rxd_bit_ctr_reg <= rxd_bit_ctr_new;
end
if (rxd_bitrate_ctr_we)
begin
rxd_bitrate_ctr_reg <= rxd_bitrate_ctr_new;
end
if (txd_bit_ctr_we)
begin
txd_bit_ctr_reg <= txd_bit_ctr_new;
end
if (txd_bitrate_ctr_we)
begin
txd_bitrate_ctr_reg <= txd_bitrate_ctr_new;
end
if (itx_ctrl_we)
begin
itx_ctrl_reg <= itx_ctrl_new;
end
if (etx_ctrl_we)
begin
etx_ctrl_reg <= etx_ctrl_new;
end
end
end // reg_update
//----------------------------------------------------------------
// api
//
// The core API that allows an internal host to control the
// core functionality.
//----------------------------------------------------------------
always @*
begin: api
// Default assignments.
tmp_read_data = 32'h00000000;
tmp_error = 0;
clk_div_new = 16'h0000;
clk_div_we = 0;
enable_bit_new = 0;
enable_bit_we = 0;
iloopback_bit_new = 0;
iloopback_bit_we = 0;
eloopback_bit_new = 0;
eloopback_bit_we = 0;
start_bits_new = 2'b00;
start_bits_we = 0;
stop_bits_new = 2'b00 ;
stop_bits_we = 0;
data_bits_new = 4'h0;
data_bits_we = 0;
parity_bit_new = 0;
parity_bit_we = 0;
rx_parity_error_ctr_rst = 0;
rx_buffer_full_ctr_rst = 0;
tx_buffer_full_ctr_rst = 0;
if (cs)
begin
if (we)
begin
// Write operations.
case (address)
ADDR_CTRL:
begin
enable_bit_new = write_data[0];
enable_bit_we = 1;
iloopback_bit_new = write_data[1];
iloopback_bit_we = 1;
eloopback_bit_new = write_data[2];
eloopback_bit_we = 1;
end
ADDR_CONFIG:
begin
start_bits_new = write_data[1 : 0];
start_bits_we = 1;
stop_bits_new = write_data[3 : 2];
stop_bits_we = 1;
data_bits_new = write_data[7 : 4];
data_bits_we = 1;
parity_bit_new = write_data[8];
parity_bit_we = 1;
end
ADDR_CLK_DIV:
begin
clk_div_new = write_data[15 : 0];
clk_div_we = 1;
end
ADDR_STAT_PARITY:
begin
// Note that we ignore the data being written.
rx_parity_error_ctr_rst = 1;
end
ADDR_STAT_RX_FULL:
begin
// Note that we ignore the data being written.
rx_buffer_full_ctr_rst = 1;
end
ADDR_STAT_TX_FULL:
begin
// Note that we ignore the data being written.
tx_buffer_full_ctr_rst = 1;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end
else
begin
// Read operations.
case (address)
ADDR_CORE_NAME0:
begin
tmp_read_data = CORE_NAME0;
end
ADDR_CORE_NAME1:
begin
tmp_read_data = CORE_NAME1;
end
ADDR_CORE_TYPE:
begin
tmp_read_data = CORE_TYPE;
end
ADDR_CORE_VERSION:
begin
tmp_read_data = CORE_VERSION;
end
ADDR_CTRL:
begin
tmp_read_data = {28'h0000000, 2'b01, eloopback_bit_reg,
iloopback_bit_reg, enable_bit_reg};
end
ADDR_STATUS:
begin
tmp_read_data = {24'h000000, tx_ctr_reg, rx_ctr_reg};
end
ADDR_CONFIG:
begin
tmp_read_data = {20'h00000, 3'b000,
parity_bit_reg, data_bits_reg,
stop_bits_reg, start_bits_reg};
end
ADDR_CLK_DIV:
begin
tmp_read_data = {16'h0000, clk_div_reg};
end
ADDR_STAT_PARITY:
begin
tmp_read_data = rx_parity_error_ctr_reg;
end
ADDR_STAT_RX_FULL:
begin
tmp_read_data = rx_buffer_full_ctr_reg;
end
ADDR_STAT_TX_FULL:
begin
tmp_read_data = tx_buffer_full_ctr_reg;
end
default:
begin
tmp_error = 1;
end
endcase // case (address)
end
end
end
//----------------------------------------------------------------
// eloopback_mux
//
// The mux controlled by the eloopback_bit_reg. If set the
// interfaces towards the external system is tied together
// making the UART echoing received data back to
// the external host.
//----------------------------------------------------------------
always @*
begin: eloopback_mux
if (eloopback_bit_reg)
begin
muxed_rxd_reg = 8'hff;
muxed_txd = rxd_reg;
end
else
begin
muxed_rxd_reg = rxd_reg;
muxed_txd = txd_reg;
end
end // eloopback_mux
//----------------------------------------------------------------
// iloopback_mux
//
// The mux controlled by the iloopback_bit_reg. If set the
// interfaces towards the internal system is tied together
// making the UART echoing received back to the external host
// via the buffers and serial/parallel conversions
//----------------------------------------------------------------
// always @*
// begin: iloopback_mux
// if (iloopback_bit_reg)
// begin
// internal_tx_syn = internal_rx_syn;
// internal_tx_data = internal_rx_data;
// internal_rx_ack = internal_tx_ack;
//
// tmp_rx_syn = 0;
// tmp_rx_data = 8'h00;
// tmp_tx_ack = 0;
// end
// else
// begin
// tmp_rx_syn = internal_rx_syn;
// tmp_rx_data = internal_rx_data;
// internal_rx_ack = rx_ack;
//
// internal_xx_syn = tx_syn;
// internal_tx_data = tx_data;
// tmp_tx_ack = internal_tx_ack;
// end
// end // iloopback_mux
//
//----------------------------------------------------------------
// rx_rd_ptr
//
// Read pointer for the receive buffer.
//----------------------------------------------------------------
always @*
begin: rx_rd_ptr
rx_rd_ptr_new = 4'h00;
rx_rd_ptr_we = 0;
if (rx_rd_ptr_inc)
begin
rx_rd_ptr_new = rx_rd_ptr_reg + 1'b1;
rx_rd_ptr_we = 1;
end
end // rx_rd_ptr
//----------------------------------------------------------------
// rx_wr_ptr
//
// Write pointer for the receive buffer.
//----------------------------------------------------------------
always @*
begin: rx_wr_ptr
rx_wr_ptr_new = 4'h00;
rx_wr_ptr_we = 0;
if (rx_wr_ptr_inc)
begin
rx_wr_ptr_new = rx_wr_ptr_reg + 1'b1;
rx_wr_ptr_we = 1;
end
end // rx_wr_ptr
//----------------------------------------------------------------
// rx_ctr
//
// Counter for the receive buffer.
//----------------------------------------------------------------
always @*
begin: rx_ctr
rx_ctr_new = 4'h00;
rx_ctr_we = 0;
rx_empty = 0;
if (rx_ctr_reg == 4'h0)
begin
rx_empty = 1;
end
if ((rx_ctr_inc) && (!rx_ctr_dec))
begin
rx_ctr_new = rx_ctr_reg + 1'b1;
rx_ctr_we = 1;
end
else if ((!rx_ctr_inc) && (rx_ctr_dec))
begin
rx_ctr_new = rx_ctr_reg - 1'b1;
rx_ctr_we = 1;
end
end // rx_ctr
//----------------------------------------------------------------
// tx_rd_ptr
//
// Read pointer for the transmit buffer.
//----------------------------------------------------------------
always @*
begin: tx_rd_ptr
tx_rd_ptr_new = 4'h00;
tx_rd_ptr_we = 0;
if (tx_rd_ptr_inc)
begin
tx_rd_ptr_new = tx_rd_ptr_reg + 1'b1;
tx_rd_ptr_we = 1;
end
end // tx_rd_ptr
//----------------------------------------------------------------
// tx_wr_ptr
//
// Write pointer for the transmit buffer.
//----------------------------------------------------------------
always @*
begin: tx_wr_ptr
tx_wr_ptr_new = 4'h00;
tx_wr_ptr_we = 0;
if (tx_wr_ptr_inc)
begin
tx_wr_ptr_new = tx_wr_ptr_reg + 1'b1;
tx_wr_ptr_we = 1;
end
end // tx_wr_ptr
//----------------------------------------------------------------
// tx_ctr
//
// Counter for the transmit buffer.
//----------------------------------------------------------------
always @*
begin: tx_ctr
tx_ctr_new = 4'h0;
tx_ctr_we = 0;
tx_full = 0;
if (tx_ctr_reg == 4'hf)
begin
tx_full = 1;
end
if ((tx_ctr_inc) && (!tx_ctr_dec))
begin
tx_ctr_new = tx_ctr_reg + 1'b1;
tx_ctr_we = 1;
end
else if ((!tx_ctr_inc) && (tx_ctr_dec))
begin
tx_ctr_new = tx_ctr_reg - 1'b1;
tx_ctr_we = 1;
end
end // tx_ctr
//----------------------------------------------------------------
// external_rx_engine
//
// Logic that implements the receive engine towards the externa
// interface. Detects incoming data, collects it, if required
// checks parity and store correct data into the rx buffer.
//----------------------------------------------------------------
always @*
begin: external_rx_engine
end // external_rx_engine
//----------------------------------------------------------------
// external_tx_engine
//
// Logic that implements the transmit engine towards the external
// interface. When there is data in the tx buffer, the engine
// transmits the data including start, stop and possible
// parity bits.
//----------------------------------------------------------------
always @*
begin: external_tx_engine
tx_rd_ptr_inc = 0;
tx_ctr_dec = 0;
txd_byte_we = 0;
txd_we = 0;
txd_bit_ctr_rst = 0;
txd_bit_ctr_inc = 0;
txd_bitrate_ctr_rst = 0;
txd_bitrate_ctr_inc = 0;
etx_ctrl_new = ETX_IDLE;
etx_ctrl_we = 0;
case (etx_ctrl_reg)
ETX_IDLE:
begin
if (!tx_empty)
begin
txd_byte_we = 1;
txd_bit_ctr_rst = 1;
txd_bitrate_ctr_rst = 1;
tx_rd_ptr_inc = 1;
tx_ctr_dec = 1;
etx_ctrl_new = ETX_START;
etx_ctrl_we = 1;
end
end
endcase // case (etx_ctrl_reg)
end // external_tx_engine
//----------------------------------------------------------------
// internal_rx_engine
//
// Logic that implements the receive engine towards the internal
// interface. When there is data in the rx buffer it asserts
// the syn flag to signal that there is data available on
// rx_data. When the ack signal is asserted the syn flag is
// dropped and the data is considered to have been consumed and
// can be discarded.
//----------------------------------------------------------------
always @*
begin: internal_rx_engine
end // internal_rx_engine
//----------------------------------------------------------------
// internal_tx_engine
//
// Logic that implements the transmit engine towards the internal
// interface. When the tx_syn flag is asserted the engine checks
// if there are any room in the tx buffer. If it is, the data
// available at tx_data is stored in the buffer. The tx_ack
// is then asserted. The engine then waits for the syn flag
// to be dropped.
//----------------------------------------------------------------
always @*
begin: internal_tx_engine
// Default assignments
tx_buffer_we = 0;
tx_wr_ptr_inc = 0;
tx_ctr_inc = 0;
tmp_tx_ack = 0;
itx_ctrl_new = ITX_IDLE;
itx_ctrl_we = 0;
case (itx_ctrl_reg)
ITX_IDLE:
begin
if (tx_syn)
begin
if (!tx_full)
begin
tx_buffer_we = 1;
tx_wr_ptr_inc = 1;
tx_ctr_inc = 1;
itx_ctrl_new = ITX_ACK;
itx_ctrl_we = 1;
end
end
end
ITX_ACK:
begin
tmp_tx_ack = 1;
if (!tx_syn)
begin
itx_ctrl_new = ITX_IDLE;
itx_ctrl_we = 1;
end
end
endcase // case (itx_ctrl_reg)
end // internal_tx_engine
endmodule // uart
//======================================================================
// EOF uart.v
//======================================================================
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21OI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A21OI_FUNCTIONAL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a21oi (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21OI_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__TAPVGND_PP_BLACKBOX_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapvgnd (
VPWR,
VGND
);
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND_PP_BLACKBOX_V
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:48:31 MST 2014
//Date : Wed Sep 30 15:12:45 2015
//Host : rcswrka27 running 64-bit Ubuntu 10.04.4 LTS
//Command : generate_target Test_AXI_Master_simple_v1_0_hw_1.bd
//Design : Test_AXI_Master_simple_v1_0_hw_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module Test_AXI_Master_simple_v1_0_hw_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
mosi_o,
ppm_signal_in,
sck_o,
ss_o);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output mosi_o;
input ppm_signal_in;
output sck_o;
output [0:0]ss_o;
wire GND_1;
wire [31:0]S00_AXI_1_ARADDR;
wire [1:0]S00_AXI_1_ARBURST;
wire [3:0]S00_AXI_1_ARCACHE;
wire [0:0]S00_AXI_1_ARID;
wire [7:0]S00_AXI_1_ARLEN;
wire S00_AXI_1_ARLOCK;
wire [2:0]S00_AXI_1_ARPROT;
wire [3:0]S00_AXI_1_ARQOS;
wire S00_AXI_1_ARREADY;
wire [2:0]S00_AXI_1_ARSIZE;
wire S00_AXI_1_ARVALID;
wire [31:0]S00_AXI_1_AWADDR;
wire [1:0]S00_AXI_1_AWBURST;
wire [3:0]S00_AXI_1_AWCACHE;
wire [0:0]S00_AXI_1_AWID;
wire [7:0]S00_AXI_1_AWLEN;
wire S00_AXI_1_AWLOCK;
wire [2:0]S00_AXI_1_AWPROT;
wire [3:0]S00_AXI_1_AWQOS;
wire S00_AXI_1_AWREADY;
wire [2:0]S00_AXI_1_AWSIZE;
wire S00_AXI_1_AWVALID;
wire [0:0]S00_AXI_1_BID;
wire S00_AXI_1_BREADY;
wire [1:0]S00_AXI_1_BRESP;
wire S00_AXI_1_BVALID;
wire [31:0]S00_AXI_1_RDATA;
wire [0:0]S00_AXI_1_RID;
wire S00_AXI_1_RLAST;
wire S00_AXI_1_RREADY;
wire [1:0]S00_AXI_1_RRESP;
wire S00_AXI_1_RVALID;
wire [31:0]S00_AXI_1_WDATA;
wire S00_AXI_1_WLAST;
wire S00_AXI_1_WREADY;
wire [3:0]S00_AXI_1_WSTRB;
wire S00_AXI_1_WVALID;
wire [31:0]S01_AXI_1_ARADDR;
wire [2:0]S01_AXI_1_ARPROT;
wire [0:0]S01_AXI_1_ARREADY;
wire S01_AXI_1_ARVALID;
wire [31:0]S01_AXI_1_AWADDR;
wire [2:0]S01_AXI_1_AWPROT;
wire [0:0]S01_AXI_1_AWREADY;
wire S01_AXI_1_AWVALID;
wire S01_AXI_1_BREADY;
wire [1:0]S01_AXI_1_BRESP;
wire [0:0]S01_AXI_1_BVALID;
wire [31:0]S01_AXI_1_RDATA;
wire S01_AXI_1_RREADY;
wire [1:0]S01_AXI_1_RRESP;
wire [0:0]S01_AXI_1_RVALID;
wire [31:0]S01_AXI_1_WDATA;
wire [0:0]S01_AXI_1_WREADY;
wire [3:0]S01_AXI_1_WSTRB;
wire S01_AXI_1_WVALID;
wire Syma_Ctrl_l_ss_init;
wire Syma_Ctrl_ppm_irq_complete;
wire Syma_Ctrl_ppm_irq_single;
wire VCC_1;
wire [3:0]axi_interconnect_general_M00_AXI_ARADDR;
wire [2:0]axi_interconnect_general_M00_AXI_ARPROT;
wire axi_interconnect_general_M00_AXI_ARREADY;
wire [0:0]axi_interconnect_general_M00_AXI_ARVALID;
wire [3:0]axi_interconnect_general_M00_AXI_AWADDR;
wire [2:0]axi_interconnect_general_M00_AXI_AWPROT;
wire axi_interconnect_general_M00_AXI_AWREADY;
wire [0:0]axi_interconnect_general_M00_AXI_AWVALID;
wire [0:0]axi_interconnect_general_M00_AXI_BREADY;
wire [1:0]axi_interconnect_general_M00_AXI_BRESP;
wire axi_interconnect_general_M00_AXI_BVALID;
wire [31:0]axi_interconnect_general_M00_AXI_RDATA;
wire [0:0]axi_interconnect_general_M00_AXI_RREADY;
wire [1:0]axi_interconnect_general_M00_AXI_RRESP;
wire axi_interconnect_general_M00_AXI_RVALID;
wire [31:0]axi_interconnect_general_M00_AXI_WDATA;
wire axi_interconnect_general_M00_AXI_WREADY;
wire [3:0]axi_interconnect_general_M00_AXI_WSTRB;
wire [0:0]axi_interconnect_general_M00_AXI_WVALID;
wire [4:0]axi_interconnect_general_M01_AXI_ARADDR;
wire [2:0]axi_interconnect_general_M01_AXI_ARPROT;
wire axi_interconnect_general_M01_AXI_ARREADY;
wire [0:0]axi_interconnect_general_M01_AXI_ARVALID;
wire [4:0]axi_interconnect_general_M01_AXI_AWADDR;
wire [2:0]axi_interconnect_general_M01_AXI_AWPROT;
wire axi_interconnect_general_M01_AXI_AWREADY;
wire [0:0]axi_interconnect_general_M01_AXI_AWVALID;
wire [0:0]axi_interconnect_general_M01_AXI_BREADY;
wire [1:0]axi_interconnect_general_M01_AXI_BRESP;
wire axi_interconnect_general_M01_AXI_BVALID;
wire [31:0]axi_interconnect_general_M01_AXI_RDATA;
wire [0:0]axi_interconnect_general_M01_AXI_RREADY;
wire [1:0]axi_interconnect_general_M01_AXI_RRESP;
wire axi_interconnect_general_M01_AXI_RVALID;
wire [31:0]axi_interconnect_general_M01_AXI_WDATA;
wire axi_interconnect_general_M01_AXI_WREADY;
wire [3:0]axi_interconnect_general_M01_AXI_WSTRB;
wire [0:0]axi_interconnect_general_M01_AXI_WVALID;
wire [4:0]axi_interconnect_general_M02_AXI_ARADDR;
wire axi_interconnect_general_M02_AXI_ARREADY;
wire [0:0]axi_interconnect_general_M02_AXI_ARVALID;
wire [4:0]axi_interconnect_general_M02_AXI_AWADDR;
wire axi_interconnect_general_M02_AXI_AWREADY;
wire [0:0]axi_interconnect_general_M02_AXI_AWVALID;
wire [0:0]axi_interconnect_general_M02_AXI_BREADY;
wire [1:0]axi_interconnect_general_M02_AXI_BRESP;
wire axi_interconnect_general_M02_AXI_BVALID;
wire [31:0]axi_interconnect_general_M02_AXI_RDATA;
wire [0:0]axi_interconnect_general_M02_AXI_RREADY;
wire [1:0]axi_interconnect_general_M02_AXI_RRESP;
wire axi_interconnect_general_M02_AXI_RVALID;
wire [31:0]axi_interconnect_general_M02_AXI_WDATA;
wire axi_interconnect_general_M02_AXI_WREADY;
wire [3:0]axi_interconnect_general_M02_AXI_WSTRB;
wire [0:0]axi_interconnect_general_M02_AXI_WVALID;
wire [6:0]axi_interconnect_spi_M00_AXI_ARADDR;
wire axi_interconnect_spi_M00_AXI_ARREADY;
wire [0:0]axi_interconnect_spi_M00_AXI_ARVALID;
wire [6:0]axi_interconnect_spi_M00_AXI_AWADDR;
wire axi_interconnect_spi_M00_AXI_AWREADY;
wire [0:0]axi_interconnect_spi_M00_AXI_AWVALID;
wire [0:0]axi_interconnect_spi_M00_AXI_BREADY;
wire [1:0]axi_interconnect_spi_M00_AXI_BRESP;
wire axi_interconnect_spi_M00_AXI_BVALID;
wire [31:0]axi_interconnect_spi_M00_AXI_RDATA;
wire [0:0]axi_interconnect_spi_M00_AXI_RREADY;
wire [1:0]axi_interconnect_spi_M00_AXI_RRESP;
wire axi_interconnect_spi_M00_AXI_RVALID;
wire [31:0]axi_interconnect_spi_M00_AXI_WDATA;
wire axi_interconnect_spi_M00_AXI_WREADY;
wire [3:0]axi_interconnect_spi_M00_AXI_WSTRB;
wire [0:0]axi_interconnect_spi_M00_AXI_WVALID;
wire axi_quad_spi_0_io0_o;
wire axi_quad_spi_0_sck_o;
wire [0:0]axi_quad_spi_0_ss_o;
wire axi_timer_0_interrupt;
wire clk_wiz_clk_out1;
wire clk_wiz_clk_out2;
wire [2:0]concat_irq_dout;
wire ppm_signal_in_1;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FCLK_CLK0;
wire processing_system7_0_FCLK_RESET0_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
wire processing_system7_0_M_AXI_GP0_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
wire processing_system7_0_M_AXI_GP0_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
wire processing_system7_0_M_AXI_GP0_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
wire processing_system7_0_M_AXI_GP0_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
wire processing_system7_0_M_AXI_GP0_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
wire processing_system7_0_M_AXI_GP0_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
wire processing_system7_0_M_AXI_GP0_RLAST;
wire processing_system7_0_M_AXI_GP0_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
wire processing_system7_0_M_AXI_GP0_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
wire processing_system7_0_M_AXI_GP0_WLAST;
wire processing_system7_0_M_AXI_GP0_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
wire processing_system7_0_M_AXI_GP0_WVALID;
wire [0:0]sys_reset_0_peripheral_aresetn;
wire [0:0]util_vector_logic_0_Res;
assign mosi_o = axi_quad_spi_0_io0_o;
assign ppm_signal_in_1 = ppm_signal_in;
assign sck_o = axi_quad_spi_0_sck_o;
assign ss_o[0] = util_vector_logic_0_Res;
GND GND
(.G(GND_1));
Test_AXI_Master_simple_v1_0_hw_1_Syma_Ctrl_0 Syma_Ctrl
(.l_ss_init(Syma_Ctrl_l_ss_init),
.m01_axi_aclk(processing_system7_0_FCLK_CLK0),
.m01_axi_araddr(S01_AXI_1_ARADDR),
.m01_axi_aresetn(sys_reset_0_peripheral_aresetn),
.m01_axi_arprot(S01_AXI_1_ARPROT),
.m01_axi_arready(S01_AXI_1_ARREADY),
.m01_axi_arvalid(S01_AXI_1_ARVALID),
.m01_axi_awaddr(S01_AXI_1_AWADDR),
.m01_axi_awprot(S01_AXI_1_AWPROT),
.m01_axi_awready(S01_AXI_1_AWREADY),
.m01_axi_awvalid(S01_AXI_1_AWVALID),
.m01_axi_bready(S01_AXI_1_BREADY),
.m01_axi_bresp(S01_AXI_1_BRESP),
.m01_axi_bvalid(S01_AXI_1_BVALID),
.m01_axi_rdata(S01_AXI_1_RDATA),
.m01_axi_rready(S01_AXI_1_RREADY),
.m01_axi_rresp(S01_AXI_1_RRESP),
.m01_axi_rvalid(S01_AXI_1_RVALID),
.m01_axi_wdata(S01_AXI_1_WDATA),
.m01_axi_wready(S01_AXI_1_WREADY),
.m01_axi_wstrb(S01_AXI_1_WSTRB),
.m01_axi_wvalid(S01_AXI_1_WVALID),
.ppm_irq_complete(Syma_Ctrl_ppm_irq_complete),
.ppm_irq_single(Syma_Ctrl_ppm_irq_single),
.ppm_signal_in(ppm_signal_in_1),
.s00_axi_aclk(processing_system7_0_FCLK_CLK0),
.s00_axi_araddr(axi_interconnect_general_M00_AXI_ARADDR),
.s00_axi_aresetn(sys_reset_0_peripheral_aresetn),
.s00_axi_arprot(axi_interconnect_general_M00_AXI_ARPROT),
.s00_axi_arready(axi_interconnect_general_M00_AXI_ARREADY),
.s00_axi_arvalid(axi_interconnect_general_M00_AXI_ARVALID),
.s00_axi_awaddr(axi_interconnect_general_M00_AXI_AWADDR),
.s00_axi_awprot(axi_interconnect_general_M00_AXI_AWPROT),
.s00_axi_awready(axi_interconnect_general_M00_AXI_AWREADY),
.s00_axi_awvalid(axi_interconnect_general_M00_AXI_AWVALID),
.s00_axi_bready(axi_interconnect_general_M00_AXI_BREADY),
.s00_axi_bresp(axi_interconnect_general_M00_AXI_BRESP),
.s00_axi_bvalid(axi_interconnect_general_M00_AXI_BVALID),
.s00_axi_rdata(axi_interconnect_general_M00_AXI_RDATA),
.s00_axi_rready(axi_interconnect_general_M00_AXI_RREADY),
.s00_axi_rresp(axi_interconnect_general_M00_AXI_RRESP),
.s00_axi_rvalid(axi_interconnect_general_M00_AXI_RVALID),
.s00_axi_wdata(axi_interconnect_general_M00_AXI_WDATA),
.s00_axi_wready(axi_interconnect_general_M00_AXI_WREADY),
.s00_axi_wstrb(axi_interconnect_general_M00_AXI_WSTRB),
.s00_axi_wvalid(axi_interconnect_general_M00_AXI_WVALID),
.s01_axi_aclk(processing_system7_0_FCLK_CLK0),
.s01_axi_araddr(axi_interconnect_general_M01_AXI_ARADDR),
.s01_axi_aresetn(sys_reset_0_peripheral_aresetn),
.s01_axi_arprot(axi_interconnect_general_M01_AXI_ARPROT),
.s01_axi_arready(axi_interconnect_general_M01_AXI_ARREADY),
.s01_axi_arvalid(axi_interconnect_general_M01_AXI_ARVALID),
.s01_axi_awaddr(axi_interconnect_general_M01_AXI_AWADDR),
.s01_axi_awprot(axi_interconnect_general_M01_AXI_AWPROT),
.s01_axi_awready(axi_interconnect_general_M01_AXI_AWREADY),
.s01_axi_awvalid(axi_interconnect_general_M01_AXI_AWVALID),
.s01_axi_bready(axi_interconnect_general_M01_AXI_BREADY),
.s01_axi_bresp(axi_interconnect_general_M01_AXI_BRESP),
.s01_axi_bvalid(axi_interconnect_general_M01_AXI_BVALID),
.s01_axi_rdata(axi_interconnect_general_M01_AXI_RDATA),
.s01_axi_rready(axi_interconnect_general_M01_AXI_RREADY),
.s01_axi_rresp(axi_interconnect_general_M01_AXI_RRESP),
.s01_axi_rvalid(axi_interconnect_general_M01_AXI_RVALID),
.s01_axi_wdata(axi_interconnect_general_M01_AXI_WDATA),
.s01_axi_wready(axi_interconnect_general_M01_AXI_WREADY),
.s01_axi_wstrb(axi_interconnect_general_M01_AXI_WSTRB),
.s01_axi_wvalid(axi_interconnect_general_M01_AXI_WVALID),
.sample_clk(clk_wiz_clk_out2));
VCC VCC
(.P(VCC_1));
Test_AXI_Master_simple_v1_0_hw_1_axi_interconnect_general_0 axi_interconnect_general
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(sys_reset_0_peripheral_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(sys_reset_0_peripheral_aresetn),
.M00_AXI_araddr(axi_interconnect_general_M00_AXI_ARADDR),
.M00_AXI_arprot(axi_interconnect_general_M00_AXI_ARPROT),
.M00_AXI_arready(axi_interconnect_general_M00_AXI_ARREADY),
.M00_AXI_arvalid(axi_interconnect_general_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_interconnect_general_M00_AXI_AWADDR),
.M00_AXI_awprot(axi_interconnect_general_M00_AXI_AWPROT),
.M00_AXI_awready(axi_interconnect_general_M00_AXI_AWREADY),
.M00_AXI_awvalid(axi_interconnect_general_M00_AXI_AWVALID),
.M00_AXI_bready(axi_interconnect_general_M00_AXI_BREADY),
.M00_AXI_bresp(axi_interconnect_general_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_interconnect_general_M00_AXI_BVALID),
.M00_AXI_rdata(axi_interconnect_general_M00_AXI_RDATA),
.M00_AXI_rready(axi_interconnect_general_M00_AXI_RREADY),
.M00_AXI_rresp(axi_interconnect_general_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_interconnect_general_M00_AXI_RVALID),
.M00_AXI_wdata(axi_interconnect_general_M00_AXI_WDATA),
.M00_AXI_wready(axi_interconnect_general_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_interconnect_general_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_interconnect_general_M00_AXI_WVALID),
.M01_ACLK(processing_system7_0_FCLK_CLK0),
.M01_ARESETN(sys_reset_0_peripheral_aresetn),
.M01_AXI_araddr(axi_interconnect_general_M01_AXI_ARADDR),
.M01_AXI_arprot(axi_interconnect_general_M01_AXI_ARPROT),
.M01_AXI_arready(axi_interconnect_general_M01_AXI_ARREADY),
.M01_AXI_arvalid(axi_interconnect_general_M01_AXI_ARVALID),
.M01_AXI_awaddr(axi_interconnect_general_M01_AXI_AWADDR),
.M01_AXI_awprot(axi_interconnect_general_M01_AXI_AWPROT),
.M01_AXI_awready(axi_interconnect_general_M01_AXI_AWREADY),
.M01_AXI_awvalid(axi_interconnect_general_M01_AXI_AWVALID),
.M01_AXI_bready(axi_interconnect_general_M01_AXI_BREADY),
.M01_AXI_bresp(axi_interconnect_general_M01_AXI_BRESP),
.M01_AXI_bvalid(axi_interconnect_general_M01_AXI_BVALID),
.M01_AXI_rdata(axi_interconnect_general_M01_AXI_RDATA),
.M01_AXI_rready(axi_interconnect_general_M01_AXI_RREADY),
.M01_AXI_rresp(axi_interconnect_general_M01_AXI_RRESP),
.M01_AXI_rvalid(axi_interconnect_general_M01_AXI_RVALID),
.M01_AXI_wdata(axi_interconnect_general_M01_AXI_WDATA),
.M01_AXI_wready(axi_interconnect_general_M01_AXI_WREADY),
.M01_AXI_wstrb(axi_interconnect_general_M01_AXI_WSTRB),
.M01_AXI_wvalid(axi_interconnect_general_M01_AXI_WVALID),
.M02_ACLK(processing_system7_0_FCLK_CLK0),
.M02_ARESETN(sys_reset_0_peripheral_aresetn),
.M02_AXI_araddr(axi_interconnect_general_M02_AXI_ARADDR),
.M02_AXI_arready(axi_interconnect_general_M02_AXI_ARREADY),
.M02_AXI_arvalid(axi_interconnect_general_M02_AXI_ARVALID),
.M02_AXI_awaddr(axi_interconnect_general_M02_AXI_AWADDR),
.M02_AXI_awready(axi_interconnect_general_M02_AXI_AWREADY),
.M02_AXI_awvalid(axi_interconnect_general_M02_AXI_AWVALID),
.M02_AXI_bready(axi_interconnect_general_M02_AXI_BREADY),
.M02_AXI_bresp(axi_interconnect_general_M02_AXI_BRESP),
.M02_AXI_bvalid(axi_interconnect_general_M02_AXI_BVALID),
.M02_AXI_rdata(axi_interconnect_general_M02_AXI_RDATA),
.M02_AXI_rready(axi_interconnect_general_M02_AXI_RREADY),
.M02_AXI_rresp(axi_interconnect_general_M02_AXI_RRESP),
.M02_AXI_rvalid(axi_interconnect_general_M02_AXI_RVALID),
.M02_AXI_wdata(axi_interconnect_general_M02_AXI_WDATA),
.M02_AXI_wready(axi_interconnect_general_M02_AXI_WREADY),
.M02_AXI_wstrb(axi_interconnect_general_M02_AXI_WSTRB),
.M02_AXI_wvalid(axi_interconnect_general_M02_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(sys_reset_0_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
Test_AXI_Master_simple_v1_0_hw_1_axi_interconnect_spi_0 axi_interconnect_spi
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(sys_reset_0_peripheral_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(sys_reset_0_peripheral_aresetn),
.M00_AXI_araddr(axi_interconnect_spi_M00_AXI_ARADDR),
.M00_AXI_arready(axi_interconnect_spi_M00_AXI_ARREADY),
.M00_AXI_arvalid(axi_interconnect_spi_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_interconnect_spi_M00_AXI_AWADDR),
.M00_AXI_awready(axi_interconnect_spi_M00_AXI_AWREADY),
.M00_AXI_awvalid(axi_interconnect_spi_M00_AXI_AWVALID),
.M00_AXI_bready(axi_interconnect_spi_M00_AXI_BREADY),
.M00_AXI_bresp(axi_interconnect_spi_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_interconnect_spi_M00_AXI_BVALID),
.M00_AXI_rdata(axi_interconnect_spi_M00_AXI_RDATA),
.M00_AXI_rready(axi_interconnect_spi_M00_AXI_RREADY),
.M00_AXI_rresp(axi_interconnect_spi_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_interconnect_spi_M00_AXI_RVALID),
.M00_AXI_wdata(axi_interconnect_spi_M00_AXI_WDATA),
.M00_AXI_wready(axi_interconnect_spi_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_interconnect_spi_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_interconnect_spi_M00_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(sys_reset_0_peripheral_aresetn),
.S00_AXI_araddr(S00_AXI_1_ARADDR),
.S00_AXI_arburst(S00_AXI_1_ARBURST),
.S00_AXI_arcache(S00_AXI_1_ARCACHE),
.S00_AXI_arid(S00_AXI_1_ARID),
.S00_AXI_arlen(S00_AXI_1_ARLEN),
.S00_AXI_arlock(S00_AXI_1_ARLOCK),
.S00_AXI_arprot(S00_AXI_1_ARPROT),
.S00_AXI_arqos(S00_AXI_1_ARQOS),
.S00_AXI_arready(S00_AXI_1_ARREADY),
.S00_AXI_arsize(S00_AXI_1_ARSIZE),
.S00_AXI_arvalid(S00_AXI_1_ARVALID),
.S00_AXI_awaddr(S00_AXI_1_AWADDR),
.S00_AXI_awburst(S00_AXI_1_AWBURST),
.S00_AXI_awcache(S00_AXI_1_AWCACHE),
.S00_AXI_awid(S00_AXI_1_AWID),
.S00_AXI_awlen(S00_AXI_1_AWLEN),
.S00_AXI_awlock(S00_AXI_1_AWLOCK),
.S00_AXI_awprot(S00_AXI_1_AWPROT),
.S00_AXI_awqos(S00_AXI_1_AWQOS),
.S00_AXI_awready(S00_AXI_1_AWREADY),
.S00_AXI_awsize(S00_AXI_1_AWSIZE),
.S00_AXI_awvalid(S00_AXI_1_AWVALID),
.S00_AXI_bid(S00_AXI_1_BID),
.S00_AXI_bready(S00_AXI_1_BREADY),
.S00_AXI_bresp(S00_AXI_1_BRESP),
.S00_AXI_bvalid(S00_AXI_1_BVALID),
.S00_AXI_rdata(S00_AXI_1_RDATA),
.S00_AXI_rid(S00_AXI_1_RID),
.S00_AXI_rlast(S00_AXI_1_RLAST),
.S00_AXI_rready(S00_AXI_1_RREADY),
.S00_AXI_rresp(S00_AXI_1_RRESP),
.S00_AXI_rvalid(S00_AXI_1_RVALID),
.S00_AXI_wdata(S00_AXI_1_WDATA),
.S00_AXI_wlast(S00_AXI_1_WLAST),
.S00_AXI_wready(S00_AXI_1_WREADY),
.S00_AXI_wstrb(S00_AXI_1_WSTRB),
.S00_AXI_wvalid(S00_AXI_1_WVALID),
.S01_ACLK(processing_system7_0_FCLK_CLK0),
.S01_ARESETN(sys_reset_0_peripheral_aresetn),
.S01_AXI_araddr(S01_AXI_1_ARADDR),
.S01_AXI_arprot(S01_AXI_1_ARPROT),
.S01_AXI_arready(S01_AXI_1_ARREADY),
.S01_AXI_arvalid(S01_AXI_1_ARVALID),
.S01_AXI_awaddr(S01_AXI_1_AWADDR),
.S01_AXI_awprot(S01_AXI_1_AWPROT),
.S01_AXI_awready(S01_AXI_1_AWREADY),
.S01_AXI_awvalid(S01_AXI_1_AWVALID),
.S01_AXI_bready(S01_AXI_1_BREADY),
.S01_AXI_bresp(S01_AXI_1_BRESP),
.S01_AXI_bvalid(S01_AXI_1_BVALID),
.S01_AXI_rdata(S01_AXI_1_RDATA),
.S01_AXI_rready(S01_AXI_1_RREADY),
.S01_AXI_rresp(S01_AXI_1_RRESP),
.S01_AXI_rvalid(S01_AXI_1_RVALID),
.S01_AXI_wdata(S01_AXI_1_WDATA),
.S01_AXI_wready(S01_AXI_1_WREADY),
.S01_AXI_wstrb(S01_AXI_1_WSTRB),
.S01_AXI_wvalid(S01_AXI_1_WVALID));
Test_AXI_Master_simple_v1_0_hw_1_axi_quad_spi_0_0 axi_quad_spi_0
(.ext_spi_clk(clk_wiz_clk_out1),
.io0_i(GND_1),
.io0_o(axi_quad_spi_0_io0_o),
.io1_i(GND_1),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(axi_interconnect_spi_M00_AXI_ARADDR),
.s_axi_aresetn(sys_reset_0_peripheral_aresetn),
.s_axi_arready(axi_interconnect_spi_M00_AXI_ARREADY),
.s_axi_arvalid(axi_interconnect_spi_M00_AXI_ARVALID),
.s_axi_awaddr(axi_interconnect_spi_M00_AXI_AWADDR),
.s_axi_awready(axi_interconnect_spi_M00_AXI_AWREADY),
.s_axi_awvalid(axi_interconnect_spi_M00_AXI_AWVALID),
.s_axi_bready(axi_interconnect_spi_M00_AXI_BREADY),
.s_axi_bresp(axi_interconnect_spi_M00_AXI_BRESP),
.s_axi_bvalid(axi_interconnect_spi_M00_AXI_BVALID),
.s_axi_rdata(axi_interconnect_spi_M00_AXI_RDATA),
.s_axi_rready(axi_interconnect_spi_M00_AXI_RREADY),
.s_axi_rresp(axi_interconnect_spi_M00_AXI_RRESP),
.s_axi_rvalid(axi_interconnect_spi_M00_AXI_RVALID),
.s_axi_wdata(axi_interconnect_spi_M00_AXI_WDATA),
.s_axi_wready(axi_interconnect_spi_M00_AXI_WREADY),
.s_axi_wstrb(axi_interconnect_spi_M00_AXI_WSTRB),
.s_axi_wvalid(axi_interconnect_spi_M00_AXI_WVALID),
.sck_i(GND_1),
.sck_o(axi_quad_spi_0_sck_o),
.ss_i(GND_1),
.ss_o(axi_quad_spi_0_ss_o));
Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0 axi_timer_0
(.capturetrig0(GND_1),
.capturetrig1(GND_1),
.freeze(GND_1),
.interrupt(axi_timer_0_interrupt),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(axi_interconnect_general_M02_AXI_ARADDR),
.s_axi_aresetn(sys_reset_0_peripheral_aresetn),
.s_axi_arready(axi_interconnect_general_M02_AXI_ARREADY),
.s_axi_arvalid(axi_interconnect_general_M02_AXI_ARVALID),
.s_axi_awaddr(axi_interconnect_general_M02_AXI_AWADDR),
.s_axi_awready(axi_interconnect_general_M02_AXI_AWREADY),
.s_axi_awvalid(axi_interconnect_general_M02_AXI_AWVALID),
.s_axi_bready(axi_interconnect_general_M02_AXI_BREADY),
.s_axi_bresp(axi_interconnect_general_M02_AXI_BRESP),
.s_axi_bvalid(axi_interconnect_general_M02_AXI_BVALID),
.s_axi_rdata(axi_interconnect_general_M02_AXI_RDATA),
.s_axi_rready(axi_interconnect_general_M02_AXI_RREADY),
.s_axi_rresp(axi_interconnect_general_M02_AXI_RRESP),
.s_axi_rvalid(axi_interconnect_general_M02_AXI_RVALID),
.s_axi_wdata(axi_interconnect_general_M02_AXI_WDATA),
.s_axi_wready(axi_interconnect_general_M02_AXI_WREADY),
.s_axi_wstrb(axi_interconnect_general_M02_AXI_WSTRB),
.s_axi_wvalid(axi_interconnect_general_M02_AXI_WVALID));
Test_AXI_Master_simple_v1_0_hw_1_clk_wiz_0 clk_wiz
(.clk_in1(processing_system7_0_FCLK_CLK0),
.clk_out1(clk_wiz_clk_out1),
.clk_out2(clk_wiz_clk_out2));
Test_AXI_Master_simple_v1_0_hw_1_concat_irq_0 concat_irq
(.In0(Syma_Ctrl_ppm_irq_single),
.In1(Syma_Ctrl_ppm_irq_complete),
.In2(axi_timer_0_interrupt),
.dout(concat_irq_dout));
Test_AXI_Master_simple_v1_0_hw_1_jtag_axi_0_0 jtag_axi_0
(.aclk(processing_system7_0_FCLK_CLK0),
.aresetn(sys_reset_0_peripheral_aresetn),
.m_axi_araddr(S00_AXI_1_ARADDR),
.m_axi_arburst(S00_AXI_1_ARBURST),
.m_axi_arcache(S00_AXI_1_ARCACHE),
.m_axi_arid(S00_AXI_1_ARID),
.m_axi_arlen(S00_AXI_1_ARLEN),
.m_axi_arlock(S00_AXI_1_ARLOCK),
.m_axi_arprot(S00_AXI_1_ARPROT),
.m_axi_arqos(S00_AXI_1_ARQOS),
.m_axi_arready(S00_AXI_1_ARREADY),
.m_axi_arsize(S00_AXI_1_ARSIZE),
.m_axi_arvalid(S00_AXI_1_ARVALID),
.m_axi_awaddr(S00_AXI_1_AWADDR),
.m_axi_awburst(S00_AXI_1_AWBURST),
.m_axi_awcache(S00_AXI_1_AWCACHE),
.m_axi_awid(S00_AXI_1_AWID),
.m_axi_awlen(S00_AXI_1_AWLEN),
.m_axi_awlock(S00_AXI_1_AWLOCK),
.m_axi_awprot(S00_AXI_1_AWPROT),
.m_axi_awqos(S00_AXI_1_AWQOS),
.m_axi_awready(S00_AXI_1_AWREADY),
.m_axi_awsize(S00_AXI_1_AWSIZE),
.m_axi_awvalid(S00_AXI_1_AWVALID),
.m_axi_bid(S00_AXI_1_BID),
.m_axi_bready(S00_AXI_1_BREADY),
.m_axi_bresp(S00_AXI_1_BRESP),
.m_axi_bvalid(S00_AXI_1_BVALID),
.m_axi_rdata(S00_AXI_1_RDATA),
.m_axi_rid(S00_AXI_1_RID),
.m_axi_rlast(S00_AXI_1_RLAST),
.m_axi_rready(S00_AXI_1_RREADY),
.m_axi_rresp(S00_AXI_1_RRESP),
.m_axi_rvalid(S00_AXI_1_RVALID),
.m_axi_wdata(S00_AXI_1_WDATA),
.m_axi_wlast(S00_AXI_1_WLAST),
.m_axi_wready(S00_AXI_1_WREADY),
.m_axi_wstrb(S00_AXI_1_WSTRB),
.m_axi_wvalid(S00_AXI_1_WVALID));
Test_AXI_Master_simple_v1_0_hw_1_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
.IRQ_F2P(concat_irq_dout),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb));
Test_AXI_Master_simple_v1_0_hw_1_sys_reset_0_0 sys_reset_0
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.mb_debug_sys_rst(GND_1),
.peripheral_aresetn(sys_reset_0_peripheral_aresetn),
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
Test_AXI_Master_simple_v1_0_hw_1_util_vector_logic_0_0 util_vector_logic_0
(.Op1(Syma_Ctrl_l_ss_init),
.Op2(axi_quad_spi_0_ss_o),
.Res(util_vector_logic_0_Res));
endmodule
module Test_AXI_Master_simple_v1_0_hw_1_axi_interconnect_general_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arprot,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awprot,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arprot,
M01_AXI_arready,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awprot,
M01_AXI_awready,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wready,
M01_AXI_wstrb,
M01_AXI_wvalid,
M02_ACLK,
M02_ARESETN,
M02_AXI_araddr,
M02_AXI_arready,
M02_AXI_arvalid,
M02_AXI_awaddr,
M02_AXI_awready,
M02_AXI_awvalid,
M02_AXI_bready,
M02_AXI_bresp,
M02_AXI_bvalid,
M02_AXI_rdata,
M02_AXI_rready,
M02_AXI_rresp,
M02_AXI_rvalid,
M02_AXI_wdata,
M02_AXI_wready,
M02_AXI_wstrb,
M02_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [3:0]M00_AXI_araddr;
output [2:0]M00_AXI_arprot;
input [0:0]M00_AXI_arready;
output [0:0]M00_AXI_arvalid;
output [3:0]M00_AXI_awaddr;
output [2:0]M00_AXI_awprot;
input [0:0]M00_AXI_awready;
output [0:0]M00_AXI_awvalid;
output [0:0]M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input [0:0]M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output [0:0]M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input [0:0]M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input [0:0]M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output [0:0]M00_AXI_wvalid;
input M01_ACLK;
input [0:0]M01_ARESETN;
output [4:0]M01_AXI_araddr;
output [2:0]M01_AXI_arprot;
input [0:0]M01_AXI_arready;
output [0:0]M01_AXI_arvalid;
output [4:0]M01_AXI_awaddr;
output [2:0]M01_AXI_awprot;
input [0:0]M01_AXI_awready;
output [0:0]M01_AXI_awvalid;
output [0:0]M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input [0:0]M01_AXI_bvalid;
input [31:0]M01_AXI_rdata;
output [0:0]M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input [0:0]M01_AXI_rvalid;
output [31:0]M01_AXI_wdata;
input [0:0]M01_AXI_wready;
output [3:0]M01_AXI_wstrb;
output [0:0]M01_AXI_wvalid;
input M02_ACLK;
input [0:0]M02_ARESETN;
output [4:0]M02_AXI_araddr;
input [0:0]M02_AXI_arready;
output [0:0]M02_AXI_arvalid;
output [4:0]M02_AXI_awaddr;
input [0:0]M02_AXI_awready;
output [0:0]M02_AXI_awvalid;
output [0:0]M02_AXI_bready;
input [1:0]M02_AXI_bresp;
input [0:0]M02_AXI_bvalid;
input [31:0]M02_AXI_rdata;
output [0:0]M02_AXI_rready;
input [1:0]M02_AXI_rresp;
input [0:0]M02_AXI_rvalid;
output [31:0]M02_AXI_wdata;
input [0:0]M02_AXI_wready;
output [3:0]M02_AXI_wstrb;
output [0:0]M02_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire axi_interconnect_general_ACLK_net;
wire [0:0]axi_interconnect_general_ARESETN_net;
wire [31:0]axi_interconnect_general_to_s00_couplers_ARADDR;
wire [1:0]axi_interconnect_general_to_s00_couplers_ARBURST;
wire [3:0]axi_interconnect_general_to_s00_couplers_ARCACHE;
wire [11:0]axi_interconnect_general_to_s00_couplers_ARID;
wire [3:0]axi_interconnect_general_to_s00_couplers_ARLEN;
wire [1:0]axi_interconnect_general_to_s00_couplers_ARLOCK;
wire [2:0]axi_interconnect_general_to_s00_couplers_ARPROT;
wire [3:0]axi_interconnect_general_to_s00_couplers_ARQOS;
wire axi_interconnect_general_to_s00_couplers_ARREADY;
wire [2:0]axi_interconnect_general_to_s00_couplers_ARSIZE;
wire axi_interconnect_general_to_s00_couplers_ARVALID;
wire [31:0]axi_interconnect_general_to_s00_couplers_AWADDR;
wire [1:0]axi_interconnect_general_to_s00_couplers_AWBURST;
wire [3:0]axi_interconnect_general_to_s00_couplers_AWCACHE;
wire [11:0]axi_interconnect_general_to_s00_couplers_AWID;
wire [3:0]axi_interconnect_general_to_s00_couplers_AWLEN;
wire [1:0]axi_interconnect_general_to_s00_couplers_AWLOCK;
wire [2:0]axi_interconnect_general_to_s00_couplers_AWPROT;
wire [3:0]axi_interconnect_general_to_s00_couplers_AWQOS;
wire axi_interconnect_general_to_s00_couplers_AWREADY;
wire [2:0]axi_interconnect_general_to_s00_couplers_AWSIZE;
wire axi_interconnect_general_to_s00_couplers_AWVALID;
wire [11:0]axi_interconnect_general_to_s00_couplers_BID;
wire axi_interconnect_general_to_s00_couplers_BREADY;
wire [1:0]axi_interconnect_general_to_s00_couplers_BRESP;
wire axi_interconnect_general_to_s00_couplers_BVALID;
wire [31:0]axi_interconnect_general_to_s00_couplers_RDATA;
wire [11:0]axi_interconnect_general_to_s00_couplers_RID;
wire axi_interconnect_general_to_s00_couplers_RLAST;
wire axi_interconnect_general_to_s00_couplers_RREADY;
wire [1:0]axi_interconnect_general_to_s00_couplers_RRESP;
wire axi_interconnect_general_to_s00_couplers_RVALID;
wire [31:0]axi_interconnect_general_to_s00_couplers_WDATA;
wire [11:0]axi_interconnect_general_to_s00_couplers_WID;
wire axi_interconnect_general_to_s00_couplers_WLAST;
wire axi_interconnect_general_to_s00_couplers_WREADY;
wire [3:0]axi_interconnect_general_to_s00_couplers_WSTRB;
wire axi_interconnect_general_to_s00_couplers_WVALID;
wire [3:0]m00_couplers_to_axi_interconnect_general_ARADDR;
wire [2:0]m00_couplers_to_axi_interconnect_general_ARPROT;
wire [0:0]m00_couplers_to_axi_interconnect_general_ARREADY;
wire [0:0]m00_couplers_to_axi_interconnect_general_ARVALID;
wire [3:0]m00_couplers_to_axi_interconnect_general_AWADDR;
wire [2:0]m00_couplers_to_axi_interconnect_general_AWPROT;
wire [0:0]m00_couplers_to_axi_interconnect_general_AWREADY;
wire [0:0]m00_couplers_to_axi_interconnect_general_AWVALID;
wire [0:0]m00_couplers_to_axi_interconnect_general_BREADY;
wire [1:0]m00_couplers_to_axi_interconnect_general_BRESP;
wire [0:0]m00_couplers_to_axi_interconnect_general_BVALID;
wire [31:0]m00_couplers_to_axi_interconnect_general_RDATA;
wire [0:0]m00_couplers_to_axi_interconnect_general_RREADY;
wire [1:0]m00_couplers_to_axi_interconnect_general_RRESP;
wire [0:0]m00_couplers_to_axi_interconnect_general_RVALID;
wire [31:0]m00_couplers_to_axi_interconnect_general_WDATA;
wire [0:0]m00_couplers_to_axi_interconnect_general_WREADY;
wire [3:0]m00_couplers_to_axi_interconnect_general_WSTRB;
wire [0:0]m00_couplers_to_axi_interconnect_general_WVALID;
wire [4:0]m01_couplers_to_axi_interconnect_general_ARADDR;
wire [2:0]m01_couplers_to_axi_interconnect_general_ARPROT;
wire [0:0]m01_couplers_to_axi_interconnect_general_ARREADY;
wire [0:0]m01_couplers_to_axi_interconnect_general_ARVALID;
wire [4:0]m01_couplers_to_axi_interconnect_general_AWADDR;
wire [2:0]m01_couplers_to_axi_interconnect_general_AWPROT;
wire [0:0]m01_couplers_to_axi_interconnect_general_AWREADY;
wire [0:0]m01_couplers_to_axi_interconnect_general_AWVALID;
wire [0:0]m01_couplers_to_axi_interconnect_general_BREADY;
wire [1:0]m01_couplers_to_axi_interconnect_general_BRESP;
wire [0:0]m01_couplers_to_axi_interconnect_general_BVALID;
wire [31:0]m01_couplers_to_axi_interconnect_general_RDATA;
wire [0:0]m01_couplers_to_axi_interconnect_general_RREADY;
wire [1:0]m01_couplers_to_axi_interconnect_general_RRESP;
wire [0:0]m01_couplers_to_axi_interconnect_general_RVALID;
wire [31:0]m01_couplers_to_axi_interconnect_general_WDATA;
wire [0:0]m01_couplers_to_axi_interconnect_general_WREADY;
wire [3:0]m01_couplers_to_axi_interconnect_general_WSTRB;
wire [0:0]m01_couplers_to_axi_interconnect_general_WVALID;
wire [4:0]m02_couplers_to_axi_interconnect_general_ARADDR;
wire [0:0]m02_couplers_to_axi_interconnect_general_ARREADY;
wire [0:0]m02_couplers_to_axi_interconnect_general_ARVALID;
wire [4:0]m02_couplers_to_axi_interconnect_general_AWADDR;
wire [0:0]m02_couplers_to_axi_interconnect_general_AWREADY;
wire [0:0]m02_couplers_to_axi_interconnect_general_AWVALID;
wire [0:0]m02_couplers_to_axi_interconnect_general_BREADY;
wire [1:0]m02_couplers_to_axi_interconnect_general_BRESP;
wire [0:0]m02_couplers_to_axi_interconnect_general_BVALID;
wire [31:0]m02_couplers_to_axi_interconnect_general_RDATA;
wire [0:0]m02_couplers_to_axi_interconnect_general_RREADY;
wire [1:0]m02_couplers_to_axi_interconnect_general_RRESP;
wire [0:0]m02_couplers_to_axi_interconnect_general_RVALID;
wire [31:0]m02_couplers_to_axi_interconnect_general_WDATA;
wire [0:0]m02_couplers_to_axi_interconnect_general_WREADY;
wire [3:0]m02_couplers_to_axi_interconnect_general_WSTRB;
wire [0:0]m02_couplers_to_axi_interconnect_general_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [31:0]s00_couplers_to_xbar_RDATA;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [31:0]s00_couplers_to_xbar_WDATA;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [3:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [2:0]xbar_to_m00_couplers_ARPROT;
wire [0:0]xbar_to_m00_couplers_ARREADY;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [2:0]xbar_to_m00_couplers_AWPROT;
wire [0:0]xbar_to_m00_couplers_AWREADY;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire [0:0]xbar_to_m00_couplers_BVALID;
wire [31:0]xbar_to_m00_couplers_RDATA;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire [0:0]xbar_to_m00_couplers_RVALID;
wire [31:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WREADY;
wire [3:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [63:32]xbar_to_m01_couplers_ARADDR;
wire [5:3]xbar_to_m01_couplers_ARPROT;
wire [0:0]xbar_to_m01_couplers_ARREADY;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [63:32]xbar_to_m01_couplers_AWADDR;
wire [5:3]xbar_to_m01_couplers_AWPROT;
wire [0:0]xbar_to_m01_couplers_AWREADY;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire [0:0]xbar_to_m01_couplers_BVALID;
wire [31:0]xbar_to_m01_couplers_RDATA;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire [0:0]xbar_to_m01_couplers_RVALID;
wire [63:32]xbar_to_m01_couplers_WDATA;
wire [0:0]xbar_to_m01_couplers_WREADY;
wire [7:4]xbar_to_m01_couplers_WSTRB;
wire [1:1]xbar_to_m01_couplers_WVALID;
wire [95:64]xbar_to_m02_couplers_ARADDR;
wire [0:0]xbar_to_m02_couplers_ARREADY;
wire [2:2]xbar_to_m02_couplers_ARVALID;
wire [95:64]xbar_to_m02_couplers_AWADDR;
wire [0:0]xbar_to_m02_couplers_AWREADY;
wire [2:2]xbar_to_m02_couplers_AWVALID;
wire [2:2]xbar_to_m02_couplers_BREADY;
wire [1:0]xbar_to_m02_couplers_BRESP;
wire [0:0]xbar_to_m02_couplers_BVALID;
wire [31:0]xbar_to_m02_couplers_RDATA;
wire [2:2]xbar_to_m02_couplers_RREADY;
wire [1:0]xbar_to_m02_couplers_RRESP;
wire [0:0]xbar_to_m02_couplers_RVALID;
wire [95:64]xbar_to_m02_couplers_WDATA;
wire [0:0]xbar_to_m02_couplers_WREADY;
wire [11:8]xbar_to_m02_couplers_WSTRB;
wire [2:2]xbar_to_m02_couplers_WVALID;
assign M00_AXI_araddr[3:0] = m00_couplers_to_axi_interconnect_general_ARADDR;
assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_interconnect_general_ARPROT;
assign M00_AXI_arvalid[0] = m00_couplers_to_axi_interconnect_general_ARVALID;
assign M00_AXI_awaddr[3:0] = m00_couplers_to_axi_interconnect_general_AWADDR;
assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_interconnect_general_AWPROT;
assign M00_AXI_awvalid[0] = m00_couplers_to_axi_interconnect_general_AWVALID;
assign M00_AXI_bready[0] = m00_couplers_to_axi_interconnect_general_BREADY;
assign M00_AXI_rready[0] = m00_couplers_to_axi_interconnect_general_RREADY;
assign M00_AXI_wdata[31:0] = m00_couplers_to_axi_interconnect_general_WDATA;
assign M00_AXI_wstrb[3:0] = m00_couplers_to_axi_interconnect_general_WSTRB;
assign M00_AXI_wvalid[0] = m00_couplers_to_axi_interconnect_general_WVALID;
assign M01_AXI_araddr[4:0] = m01_couplers_to_axi_interconnect_general_ARADDR;
assign M01_AXI_arprot[2:0] = m01_couplers_to_axi_interconnect_general_ARPROT;
assign M01_AXI_arvalid[0] = m01_couplers_to_axi_interconnect_general_ARVALID;
assign M01_AXI_awaddr[4:0] = m01_couplers_to_axi_interconnect_general_AWADDR;
assign M01_AXI_awprot[2:0] = m01_couplers_to_axi_interconnect_general_AWPROT;
assign M01_AXI_awvalid[0] = m01_couplers_to_axi_interconnect_general_AWVALID;
assign M01_AXI_bready[0] = m01_couplers_to_axi_interconnect_general_BREADY;
assign M01_AXI_rready[0] = m01_couplers_to_axi_interconnect_general_RREADY;
assign M01_AXI_wdata[31:0] = m01_couplers_to_axi_interconnect_general_WDATA;
assign M01_AXI_wstrb[3:0] = m01_couplers_to_axi_interconnect_general_WSTRB;
assign M01_AXI_wvalid[0] = m01_couplers_to_axi_interconnect_general_WVALID;
assign M02_AXI_araddr[4:0] = m02_couplers_to_axi_interconnect_general_ARADDR;
assign M02_AXI_arvalid[0] = m02_couplers_to_axi_interconnect_general_ARVALID;
assign M02_AXI_awaddr[4:0] = m02_couplers_to_axi_interconnect_general_AWADDR;
assign M02_AXI_awvalid[0] = m02_couplers_to_axi_interconnect_general_AWVALID;
assign M02_AXI_bready[0] = m02_couplers_to_axi_interconnect_general_BREADY;
assign M02_AXI_rready[0] = m02_couplers_to_axi_interconnect_general_RREADY;
assign M02_AXI_wdata[31:0] = m02_couplers_to_axi_interconnect_general_WDATA;
assign M02_AXI_wstrb[3:0] = m02_couplers_to_axi_interconnect_general_WSTRB;
assign M02_AXI_wvalid[0] = m02_couplers_to_axi_interconnect_general_WVALID;
assign S00_AXI_arready = axi_interconnect_general_to_s00_couplers_ARREADY;
assign S00_AXI_awready = axi_interconnect_general_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = axi_interconnect_general_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = axi_interconnect_general_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_interconnect_general_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = axi_interconnect_general_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = axi_interconnect_general_to_s00_couplers_RID;
assign S00_AXI_rlast = axi_interconnect_general_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_interconnect_general_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_interconnect_general_to_s00_couplers_RVALID;
assign S00_AXI_wready = axi_interconnect_general_to_s00_couplers_WREADY;
assign axi_interconnect_general_ACLK_net = ACLK;
assign axi_interconnect_general_ARESETN_net = ARESETN[0];
assign axi_interconnect_general_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_interconnect_general_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_interconnect_general_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_interconnect_general_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign axi_interconnect_general_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign axi_interconnect_general_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign axi_interconnect_general_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_interconnect_general_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign axi_interconnect_general_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_interconnect_general_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_interconnect_general_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_interconnect_general_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_interconnect_general_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_interconnect_general_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign axi_interconnect_general_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign axi_interconnect_general_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign axi_interconnect_general_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_interconnect_general_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign axi_interconnect_general_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_interconnect_general_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_interconnect_general_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_interconnect_general_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_interconnect_general_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_interconnect_general_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign axi_interconnect_general_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_interconnect_general_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_interconnect_general_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign m00_couplers_to_axi_interconnect_general_ARREADY = M00_AXI_arready[0];
assign m00_couplers_to_axi_interconnect_general_AWREADY = M00_AXI_awready[0];
assign m00_couplers_to_axi_interconnect_general_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_axi_interconnect_general_BVALID = M00_AXI_bvalid[0];
assign m00_couplers_to_axi_interconnect_general_RDATA = M00_AXI_rdata[31:0];
assign m00_couplers_to_axi_interconnect_general_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_axi_interconnect_general_RVALID = M00_AXI_rvalid[0];
assign m00_couplers_to_axi_interconnect_general_WREADY = M00_AXI_wready[0];
assign m01_couplers_to_axi_interconnect_general_ARREADY = M01_AXI_arready[0];
assign m01_couplers_to_axi_interconnect_general_AWREADY = M01_AXI_awready[0];
assign m01_couplers_to_axi_interconnect_general_BRESP = M01_AXI_bresp[1:0];
assign m01_couplers_to_axi_interconnect_general_BVALID = M01_AXI_bvalid[0];
assign m01_couplers_to_axi_interconnect_general_RDATA = M01_AXI_rdata[31:0];
assign m01_couplers_to_axi_interconnect_general_RRESP = M01_AXI_rresp[1:0];
assign m01_couplers_to_axi_interconnect_general_RVALID = M01_AXI_rvalid[0];
assign m01_couplers_to_axi_interconnect_general_WREADY = M01_AXI_wready[0];
assign m02_couplers_to_axi_interconnect_general_ARREADY = M02_AXI_arready[0];
assign m02_couplers_to_axi_interconnect_general_AWREADY = M02_AXI_awready[0];
assign m02_couplers_to_axi_interconnect_general_BRESP = M02_AXI_bresp[1:0];
assign m02_couplers_to_axi_interconnect_general_BVALID = M02_AXI_bvalid[0];
assign m02_couplers_to_axi_interconnect_general_RDATA = M02_AXI_rdata[31:0];
assign m02_couplers_to_axi_interconnect_general_RRESP = M02_AXI_rresp[1:0];
assign m02_couplers_to_axi_interconnect_general_RVALID = M02_AXI_rvalid[0];
assign m02_couplers_to_axi_interconnect_general_WREADY = M02_AXI_wready[0];
m00_couplers_imp_140AAGB m00_couplers
(.M_ACLK(axi_interconnect_general_ACLK_net),
.M_ARESETN(axi_interconnect_general_ARESETN_net),
.M_AXI_araddr(m00_couplers_to_axi_interconnect_general_ARADDR),
.M_AXI_arprot(m00_couplers_to_axi_interconnect_general_ARPROT),
.M_AXI_arready(m00_couplers_to_axi_interconnect_general_ARREADY),
.M_AXI_arvalid(m00_couplers_to_axi_interconnect_general_ARVALID),
.M_AXI_awaddr(m00_couplers_to_axi_interconnect_general_AWADDR),
.M_AXI_awprot(m00_couplers_to_axi_interconnect_general_AWPROT),
.M_AXI_awready(m00_couplers_to_axi_interconnect_general_AWREADY),
.M_AXI_awvalid(m00_couplers_to_axi_interconnect_general_AWVALID),
.M_AXI_bready(m00_couplers_to_axi_interconnect_general_BREADY),
.M_AXI_bresp(m00_couplers_to_axi_interconnect_general_BRESP),
.M_AXI_bvalid(m00_couplers_to_axi_interconnect_general_BVALID),
.M_AXI_rdata(m00_couplers_to_axi_interconnect_general_RDATA),
.M_AXI_rready(m00_couplers_to_axi_interconnect_general_RREADY),
.M_AXI_rresp(m00_couplers_to_axi_interconnect_general_RRESP),
.M_AXI_rvalid(m00_couplers_to_axi_interconnect_general_RVALID),
.M_AXI_wdata(m00_couplers_to_axi_interconnect_general_WDATA),
.M_AXI_wready(m00_couplers_to_axi_interconnect_general_WREADY),
.M_AXI_wstrb(m00_couplers_to_axi_interconnect_general_WSTRB),
.M_AXI_wvalid(m00_couplers_to_axi_interconnect_general_WVALID),
.S_ACLK(axi_interconnect_general_ACLK_net),
.S_ARESETN(axi_interconnect_general_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR[3:0]),
.S_AXI_arprot(xbar_to_m00_couplers_ARPROT),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR[3:0]),
.S_AXI_awprot(xbar_to_m00_couplers_AWPROT),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
m01_couplers_imp_DLTEH1 m01_couplers
(.M_ACLK(axi_interconnect_general_ACLK_net),
.M_ARESETN(axi_interconnect_general_ARESETN_net),
.M_AXI_araddr(m01_couplers_to_axi_interconnect_general_ARADDR),
.M_AXI_arprot(m01_couplers_to_axi_interconnect_general_ARPROT),
.M_AXI_arready(m01_couplers_to_axi_interconnect_general_ARREADY),
.M_AXI_arvalid(m01_couplers_to_axi_interconnect_general_ARVALID),
.M_AXI_awaddr(m01_couplers_to_axi_interconnect_general_AWADDR),
.M_AXI_awprot(m01_couplers_to_axi_interconnect_general_AWPROT),
.M_AXI_awready(m01_couplers_to_axi_interconnect_general_AWREADY),
.M_AXI_awvalid(m01_couplers_to_axi_interconnect_general_AWVALID),
.M_AXI_bready(m01_couplers_to_axi_interconnect_general_BREADY),
.M_AXI_bresp(m01_couplers_to_axi_interconnect_general_BRESP),
.M_AXI_bvalid(m01_couplers_to_axi_interconnect_general_BVALID),
.M_AXI_rdata(m01_couplers_to_axi_interconnect_general_RDATA),
.M_AXI_rready(m01_couplers_to_axi_interconnect_general_RREADY),
.M_AXI_rresp(m01_couplers_to_axi_interconnect_general_RRESP),
.M_AXI_rvalid(m01_couplers_to_axi_interconnect_general_RVALID),
.M_AXI_wdata(m01_couplers_to_axi_interconnect_general_WDATA),
.M_AXI_wready(m01_couplers_to_axi_interconnect_general_WREADY),
.M_AXI_wstrb(m01_couplers_to_axi_interconnect_general_WSTRB),
.M_AXI_wvalid(m01_couplers_to_axi_interconnect_general_WVALID),
.S_ACLK(axi_interconnect_general_ACLK_net),
.S_ARESETN(axi_interconnect_general_ARESETN_net),
.S_AXI_araddr(xbar_to_m01_couplers_ARADDR[36:32]),
.S_AXI_arprot(xbar_to_m01_couplers_ARPROT),
.S_AXI_arready(xbar_to_m01_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m01_couplers_AWADDR[36:32]),
.S_AXI_awprot(xbar_to_m01_couplers_AWPROT),
.S_AXI_awready(xbar_to_m01_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
.S_AXI_bready(xbar_to_m01_couplers_BREADY),
.S_AXI_bresp(xbar_to_m01_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
.S_AXI_rdata(xbar_to_m01_couplers_RDATA),
.S_AXI_rready(xbar_to_m01_couplers_RREADY),
.S_AXI_rresp(xbar_to_m01_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
.S_AXI_wdata(xbar_to_m01_couplers_WDATA),
.S_AXI_wready(xbar_to_m01_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
m02_couplers_imp_2JVYT2 m02_couplers
(.M_ACLK(axi_interconnect_general_ACLK_net),
.M_ARESETN(axi_interconnect_general_ARESETN_net),
.M_AXI_araddr(m02_couplers_to_axi_interconnect_general_ARADDR),
.M_AXI_arready(m02_couplers_to_axi_interconnect_general_ARREADY),
.M_AXI_arvalid(m02_couplers_to_axi_interconnect_general_ARVALID),
.M_AXI_awaddr(m02_couplers_to_axi_interconnect_general_AWADDR),
.M_AXI_awready(m02_couplers_to_axi_interconnect_general_AWREADY),
.M_AXI_awvalid(m02_couplers_to_axi_interconnect_general_AWVALID),
.M_AXI_bready(m02_couplers_to_axi_interconnect_general_BREADY),
.M_AXI_bresp(m02_couplers_to_axi_interconnect_general_BRESP),
.M_AXI_bvalid(m02_couplers_to_axi_interconnect_general_BVALID),
.M_AXI_rdata(m02_couplers_to_axi_interconnect_general_RDATA),
.M_AXI_rready(m02_couplers_to_axi_interconnect_general_RREADY),
.M_AXI_rresp(m02_couplers_to_axi_interconnect_general_RRESP),
.M_AXI_rvalid(m02_couplers_to_axi_interconnect_general_RVALID),
.M_AXI_wdata(m02_couplers_to_axi_interconnect_general_WDATA),
.M_AXI_wready(m02_couplers_to_axi_interconnect_general_WREADY),
.M_AXI_wstrb(m02_couplers_to_axi_interconnect_general_WSTRB),
.M_AXI_wvalid(m02_couplers_to_axi_interconnect_general_WVALID),
.S_ACLK(axi_interconnect_general_ACLK_net),
.S_ARESETN(axi_interconnect_general_ARESETN_net),
.S_AXI_araddr(xbar_to_m02_couplers_ARADDR[68:64]),
.S_AXI_arready(xbar_to_m02_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m02_couplers_AWADDR[68:64]),
.S_AXI_awready(xbar_to_m02_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),
.S_AXI_bready(xbar_to_m02_couplers_BREADY),
.S_AXI_bresp(xbar_to_m02_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m02_couplers_BVALID),
.S_AXI_rdata(xbar_to_m02_couplers_RDATA),
.S_AXI_rready(xbar_to_m02_couplers_RREADY),
.S_AXI_rresp(xbar_to_m02_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m02_couplers_RVALID),
.S_AXI_wdata(xbar_to_m02_couplers_WDATA),
.S_AXI_wready(xbar_to_m02_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m02_couplers_WVALID));
s00_couplers_imp_BMA8ID s00_couplers
(.M_ACLK(axi_interconnect_general_ACLK_net),
.M_ARESETN(axi_interconnect_general_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(axi_interconnect_general_ACLK_net),
.S_ARESETN(axi_interconnect_general_ARESETN_net),
.S_AXI_araddr(axi_interconnect_general_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_interconnect_general_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_interconnect_general_to_s00_couplers_ARCACHE),
.S_AXI_arid(axi_interconnect_general_to_s00_couplers_ARID),
.S_AXI_arlen(axi_interconnect_general_to_s00_couplers_ARLEN),
.S_AXI_arlock(axi_interconnect_general_to_s00_couplers_ARLOCK),
.S_AXI_arprot(axi_interconnect_general_to_s00_couplers_ARPROT),
.S_AXI_arqos(axi_interconnect_general_to_s00_couplers_ARQOS),
.S_AXI_arready(axi_interconnect_general_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_interconnect_general_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_interconnect_general_to_s00_couplers_ARVALID),
.S_AXI_awaddr(axi_interconnect_general_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_interconnect_general_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_interconnect_general_to_s00_couplers_AWCACHE),
.S_AXI_awid(axi_interconnect_general_to_s00_couplers_AWID),
.S_AXI_awlen(axi_interconnect_general_to_s00_couplers_AWLEN),
.S_AXI_awlock(axi_interconnect_general_to_s00_couplers_AWLOCK),
.S_AXI_awprot(axi_interconnect_general_to_s00_couplers_AWPROT),
.S_AXI_awqos(axi_interconnect_general_to_s00_couplers_AWQOS),
.S_AXI_awready(axi_interconnect_general_to_s00_couplers_AWREADY),
.S_AXI_awsize(axi_interconnect_general_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_interconnect_general_to_s00_couplers_AWVALID),
.S_AXI_bid(axi_interconnect_general_to_s00_couplers_BID),
.S_AXI_bready(axi_interconnect_general_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_interconnect_general_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_interconnect_general_to_s00_couplers_BVALID),
.S_AXI_rdata(axi_interconnect_general_to_s00_couplers_RDATA),
.S_AXI_rid(axi_interconnect_general_to_s00_couplers_RID),
.S_AXI_rlast(axi_interconnect_general_to_s00_couplers_RLAST),
.S_AXI_rready(axi_interconnect_general_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_interconnect_general_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_interconnect_general_to_s00_couplers_RVALID),
.S_AXI_wdata(axi_interconnect_general_to_s00_couplers_WDATA),
.S_AXI_wid(axi_interconnect_general_to_s00_couplers_WID),
.S_AXI_wlast(axi_interconnect_general_to_s00_couplers_WLAST),
.S_AXI_wready(axi_interconnect_general_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_interconnect_general_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_interconnect_general_to_s00_couplers_WVALID));
Test_AXI_Master_simple_v1_0_hw_1_xbar_1 xbar
(.aclk(axi_interconnect_general_ACLK_net),
.aresetn(axi_interconnect_general_ARESETN_net),
.m_axi_araddr({xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
.m_axi_arprot({xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}),
.m_axi_arready({xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
.m_axi_arvalid({xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
.m_axi_awaddr({xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
.m_axi_awprot({xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}),
.m_axi_awready({xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
.m_axi_awvalid({xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
.m_axi_bready({xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
.m_axi_bresp({xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
.m_axi_bvalid({xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
.m_axi_rdata({xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
.m_axi_rready({xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
.m_axi_rresp({xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
.m_axi_rvalid({xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
.m_axi_wdata({xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
.m_axi_wready({xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
.m_axi_wstrb({xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),
.m_axi_wvalid({xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
.s_axi_araddr(s00_couplers_to_xbar_ARADDR),
.s_axi_arprot(s00_couplers_to_xbar_ARPROT),
.s_axi_arready(s00_couplers_to_xbar_ARREADY),
.s_axi_arvalid(s00_couplers_to_xbar_ARVALID),
.s_axi_awaddr(s00_couplers_to_xbar_AWADDR),
.s_axi_awprot(s00_couplers_to_xbar_AWPROT),
.s_axi_awready(s00_couplers_to_xbar_AWREADY),
.s_axi_awvalid(s00_couplers_to_xbar_AWVALID),
.s_axi_bready(s00_couplers_to_xbar_BREADY),
.s_axi_bresp(s00_couplers_to_xbar_BRESP),
.s_axi_bvalid(s00_couplers_to_xbar_BVALID),
.s_axi_rdata(s00_couplers_to_xbar_RDATA),
.s_axi_rready(s00_couplers_to_xbar_RREADY),
.s_axi_rresp(s00_couplers_to_xbar_RRESP),
.s_axi_rvalid(s00_couplers_to_xbar_RVALID),
.s_axi_wdata(s00_couplers_to_xbar_WDATA),
.s_axi_wready(s00_couplers_to_xbar_WREADY),
.s_axi_wstrb(s00_couplers_to_xbar_WSTRB),
.s_axi_wvalid(s00_couplers_to_xbar_WVALID));
endmodule
module Test_AXI_Master_simple_v1_0_hw_1_axi_interconnect_spi_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid,
S01_ACLK,
S01_ARESETN,
S01_AXI_araddr,
S01_AXI_arprot,
S01_AXI_arready,
S01_AXI_arvalid,
S01_AXI_awaddr,
S01_AXI_awprot,
S01_AXI_awready,
S01_AXI_awvalid,
S01_AXI_bready,
S01_AXI_bresp,
S01_AXI_bvalid,
S01_AXI_rdata,
S01_AXI_rready,
S01_AXI_rresp,
S01_AXI_rvalid,
S01_AXI_wdata,
S01_AXI_wready,
S01_AXI_wstrb,
S01_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [6:0]M00_AXI_araddr;
input [0:0]M00_AXI_arready;
output [0:0]M00_AXI_arvalid;
output [6:0]M00_AXI_awaddr;
input [0:0]M00_AXI_awready;
output [0:0]M00_AXI_awvalid;
output [0:0]M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input [0:0]M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output [0:0]M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input [0:0]M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input [0:0]M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output [0:0]M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [0:0]S00_AXI_arid;
input [7:0]S00_AXI_arlen;
input [0:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [0:0]S00_AXI_awid;
input [7:0]S00_AXI_awlen;
input [0:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [0:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [0:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
input S01_ACLK;
input [0:0]S01_ARESETN;
input [31:0]S01_AXI_araddr;
input [2:0]S01_AXI_arprot;
output [0:0]S01_AXI_arready;
input [0:0]S01_AXI_arvalid;
input [31:0]S01_AXI_awaddr;
input [2:0]S01_AXI_awprot;
output [0:0]S01_AXI_awready;
input [0:0]S01_AXI_awvalid;
input [0:0]S01_AXI_bready;
output [1:0]S01_AXI_bresp;
output [0:0]S01_AXI_bvalid;
output [31:0]S01_AXI_rdata;
input [0:0]S01_AXI_rready;
output [1:0]S01_AXI_rresp;
output [0:0]S01_AXI_rvalid;
input [31:0]S01_AXI_wdata;
output [0:0]S01_AXI_wready;
input [3:0]S01_AXI_wstrb;
input [0:0]S01_AXI_wvalid;
wire axi_interconnect_spi_ACLK_net;
wire [0:0]axi_interconnect_spi_ARESETN_net;
wire [31:0]axi_interconnect_spi_to_s00_couplers_ARADDR;
wire [1:0]axi_interconnect_spi_to_s00_couplers_ARBURST;
wire [3:0]axi_interconnect_spi_to_s00_couplers_ARCACHE;
wire [0:0]axi_interconnect_spi_to_s00_couplers_ARID;
wire [7:0]axi_interconnect_spi_to_s00_couplers_ARLEN;
wire [0:0]axi_interconnect_spi_to_s00_couplers_ARLOCK;
wire [2:0]axi_interconnect_spi_to_s00_couplers_ARPROT;
wire [3:0]axi_interconnect_spi_to_s00_couplers_ARQOS;
wire axi_interconnect_spi_to_s00_couplers_ARREADY;
wire [2:0]axi_interconnect_spi_to_s00_couplers_ARSIZE;
wire axi_interconnect_spi_to_s00_couplers_ARVALID;
wire [31:0]axi_interconnect_spi_to_s00_couplers_AWADDR;
wire [1:0]axi_interconnect_spi_to_s00_couplers_AWBURST;
wire [3:0]axi_interconnect_spi_to_s00_couplers_AWCACHE;
wire [0:0]axi_interconnect_spi_to_s00_couplers_AWID;
wire [7:0]axi_interconnect_spi_to_s00_couplers_AWLEN;
wire [0:0]axi_interconnect_spi_to_s00_couplers_AWLOCK;
wire [2:0]axi_interconnect_spi_to_s00_couplers_AWPROT;
wire [3:0]axi_interconnect_spi_to_s00_couplers_AWQOS;
wire axi_interconnect_spi_to_s00_couplers_AWREADY;
wire [2:0]axi_interconnect_spi_to_s00_couplers_AWSIZE;
wire axi_interconnect_spi_to_s00_couplers_AWVALID;
wire [0:0]axi_interconnect_spi_to_s00_couplers_BID;
wire axi_interconnect_spi_to_s00_couplers_BREADY;
wire [1:0]axi_interconnect_spi_to_s00_couplers_BRESP;
wire axi_interconnect_spi_to_s00_couplers_BVALID;
wire [31:0]axi_interconnect_spi_to_s00_couplers_RDATA;
wire [0:0]axi_interconnect_spi_to_s00_couplers_RID;
wire axi_interconnect_spi_to_s00_couplers_RLAST;
wire axi_interconnect_spi_to_s00_couplers_RREADY;
wire [1:0]axi_interconnect_spi_to_s00_couplers_RRESP;
wire axi_interconnect_spi_to_s00_couplers_RVALID;
wire [31:0]axi_interconnect_spi_to_s00_couplers_WDATA;
wire axi_interconnect_spi_to_s00_couplers_WLAST;
wire axi_interconnect_spi_to_s00_couplers_WREADY;
wire [3:0]axi_interconnect_spi_to_s00_couplers_WSTRB;
wire axi_interconnect_spi_to_s00_couplers_WVALID;
wire [31:0]axi_interconnect_spi_to_s01_couplers_ARADDR;
wire [2:0]axi_interconnect_spi_to_s01_couplers_ARPROT;
wire [0:0]axi_interconnect_spi_to_s01_couplers_ARREADY;
wire [0:0]axi_interconnect_spi_to_s01_couplers_ARVALID;
wire [31:0]axi_interconnect_spi_to_s01_couplers_AWADDR;
wire [2:0]axi_interconnect_spi_to_s01_couplers_AWPROT;
wire [0:0]axi_interconnect_spi_to_s01_couplers_AWREADY;
wire [0:0]axi_interconnect_spi_to_s01_couplers_AWVALID;
wire [0:0]axi_interconnect_spi_to_s01_couplers_BREADY;
wire [1:0]axi_interconnect_spi_to_s01_couplers_BRESP;
wire [0:0]axi_interconnect_spi_to_s01_couplers_BVALID;
wire [31:0]axi_interconnect_spi_to_s01_couplers_RDATA;
wire [0:0]axi_interconnect_spi_to_s01_couplers_RREADY;
wire [1:0]axi_interconnect_spi_to_s01_couplers_RRESP;
wire [0:0]axi_interconnect_spi_to_s01_couplers_RVALID;
wire [31:0]axi_interconnect_spi_to_s01_couplers_WDATA;
wire [0:0]axi_interconnect_spi_to_s01_couplers_WREADY;
wire [3:0]axi_interconnect_spi_to_s01_couplers_WSTRB;
wire [0:0]axi_interconnect_spi_to_s01_couplers_WVALID;
wire [6:0]m00_couplers_to_axi_interconnect_spi_ARADDR;
wire [0:0]m00_couplers_to_axi_interconnect_spi_ARREADY;
wire [0:0]m00_couplers_to_axi_interconnect_spi_ARVALID;
wire [6:0]m00_couplers_to_axi_interconnect_spi_AWADDR;
wire [0:0]m00_couplers_to_axi_interconnect_spi_AWREADY;
wire [0:0]m00_couplers_to_axi_interconnect_spi_AWVALID;
wire [0:0]m00_couplers_to_axi_interconnect_spi_BREADY;
wire [1:0]m00_couplers_to_axi_interconnect_spi_BRESP;
wire [0:0]m00_couplers_to_axi_interconnect_spi_BVALID;
wire [31:0]m00_couplers_to_axi_interconnect_spi_RDATA;
wire [0:0]m00_couplers_to_axi_interconnect_spi_RREADY;
wire [1:0]m00_couplers_to_axi_interconnect_spi_RRESP;
wire [0:0]m00_couplers_to_axi_interconnect_spi_RVALID;
wire [31:0]m00_couplers_to_axi_interconnect_spi_WDATA;
wire [0:0]m00_couplers_to_axi_interconnect_spi_WREADY;
wire [3:0]m00_couplers_to_axi_interconnect_spi_WSTRB;
wire [0:0]m00_couplers_to_axi_interconnect_spi_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [31:0]s00_couplers_to_xbar_RDATA;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [31:0]s00_couplers_to_xbar_WDATA;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [3:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [31:0]s01_couplers_to_xbar_ARADDR;
wire [2:0]s01_couplers_to_xbar_ARPROT;
wire [1:1]s01_couplers_to_xbar_ARREADY;
wire [0:0]s01_couplers_to_xbar_ARVALID;
wire [31:0]s01_couplers_to_xbar_AWADDR;
wire [2:0]s01_couplers_to_xbar_AWPROT;
wire [1:1]s01_couplers_to_xbar_AWREADY;
wire [0:0]s01_couplers_to_xbar_AWVALID;
wire [0:0]s01_couplers_to_xbar_BREADY;
wire [3:2]s01_couplers_to_xbar_BRESP;
wire [1:1]s01_couplers_to_xbar_BVALID;
wire [63:32]s01_couplers_to_xbar_RDATA;
wire [0:0]s01_couplers_to_xbar_RREADY;
wire [3:2]s01_couplers_to_xbar_RRESP;
wire [1:1]s01_couplers_to_xbar_RVALID;
wire [31:0]s01_couplers_to_xbar_WDATA;
wire [1:1]s01_couplers_to_xbar_WREADY;
wire [3:0]s01_couplers_to_xbar_WSTRB;
wire [0:0]s01_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [0:0]xbar_to_m00_couplers_ARREADY;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [0:0]xbar_to_m00_couplers_AWREADY;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire [0:0]xbar_to_m00_couplers_BVALID;
wire [31:0]xbar_to_m00_couplers_RDATA;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire [0:0]xbar_to_m00_couplers_RVALID;
wire [31:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WREADY;
wire [3:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
assign M00_AXI_araddr[6:0] = m00_couplers_to_axi_interconnect_spi_ARADDR;
assign M00_AXI_arvalid[0] = m00_couplers_to_axi_interconnect_spi_ARVALID;
assign M00_AXI_awaddr[6:0] = m00_couplers_to_axi_interconnect_spi_AWADDR;
assign M00_AXI_awvalid[0] = m00_couplers_to_axi_interconnect_spi_AWVALID;
assign M00_AXI_bready[0] = m00_couplers_to_axi_interconnect_spi_BREADY;
assign M00_AXI_rready[0] = m00_couplers_to_axi_interconnect_spi_RREADY;
assign M00_AXI_wdata[31:0] = m00_couplers_to_axi_interconnect_spi_WDATA;
assign M00_AXI_wstrb[3:0] = m00_couplers_to_axi_interconnect_spi_WSTRB;
assign M00_AXI_wvalid[0] = m00_couplers_to_axi_interconnect_spi_WVALID;
assign S00_AXI_arready = axi_interconnect_spi_to_s00_couplers_ARREADY;
assign S00_AXI_awready = axi_interconnect_spi_to_s00_couplers_AWREADY;
assign S00_AXI_bid[0] = axi_interconnect_spi_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = axi_interconnect_spi_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_interconnect_spi_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = axi_interconnect_spi_to_s00_couplers_RDATA;
assign S00_AXI_rid[0] = axi_interconnect_spi_to_s00_couplers_RID;
assign S00_AXI_rlast = axi_interconnect_spi_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_interconnect_spi_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_interconnect_spi_to_s00_couplers_RVALID;
assign S00_AXI_wready = axi_interconnect_spi_to_s00_couplers_WREADY;
assign S01_AXI_arready[0] = axi_interconnect_spi_to_s01_couplers_ARREADY;
assign S01_AXI_awready[0] = axi_interconnect_spi_to_s01_couplers_AWREADY;
assign S01_AXI_bresp[1:0] = axi_interconnect_spi_to_s01_couplers_BRESP;
assign S01_AXI_bvalid[0] = axi_interconnect_spi_to_s01_couplers_BVALID;
assign S01_AXI_rdata[31:0] = axi_interconnect_spi_to_s01_couplers_RDATA;
assign S01_AXI_rresp[1:0] = axi_interconnect_spi_to_s01_couplers_RRESP;
assign S01_AXI_rvalid[0] = axi_interconnect_spi_to_s01_couplers_RVALID;
assign S01_AXI_wready[0] = axi_interconnect_spi_to_s01_couplers_WREADY;
assign axi_interconnect_spi_ACLK_net = ACLK;
assign axi_interconnect_spi_ARESETN_net = ARESETN[0];
assign axi_interconnect_spi_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_interconnect_spi_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_interconnect_spi_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_interconnect_spi_to_s00_couplers_ARID = S00_AXI_arid[0];
assign axi_interconnect_spi_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0];
assign axi_interconnect_spi_to_s00_couplers_ARLOCK = S00_AXI_arlock[0];
assign axi_interconnect_spi_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_interconnect_spi_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign axi_interconnect_spi_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_interconnect_spi_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_interconnect_spi_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_interconnect_spi_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_interconnect_spi_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_interconnect_spi_to_s00_couplers_AWID = S00_AXI_awid[0];
assign axi_interconnect_spi_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0];
assign axi_interconnect_spi_to_s00_couplers_AWLOCK = S00_AXI_awlock[0];
assign axi_interconnect_spi_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_interconnect_spi_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign axi_interconnect_spi_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_interconnect_spi_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_interconnect_spi_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_interconnect_spi_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_interconnect_spi_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_interconnect_spi_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_interconnect_spi_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_interconnect_spi_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign axi_interconnect_spi_to_s01_couplers_ARADDR = S01_AXI_araddr[31:0];
assign axi_interconnect_spi_to_s01_couplers_ARPROT = S01_AXI_arprot[2:0];
assign axi_interconnect_spi_to_s01_couplers_ARVALID = S01_AXI_arvalid[0];
assign axi_interconnect_spi_to_s01_couplers_AWADDR = S01_AXI_awaddr[31:0];
assign axi_interconnect_spi_to_s01_couplers_AWPROT = S01_AXI_awprot[2:0];
assign axi_interconnect_spi_to_s01_couplers_AWVALID = S01_AXI_awvalid[0];
assign axi_interconnect_spi_to_s01_couplers_BREADY = S01_AXI_bready[0];
assign axi_interconnect_spi_to_s01_couplers_RREADY = S01_AXI_rready[0];
assign axi_interconnect_spi_to_s01_couplers_WDATA = S01_AXI_wdata[31:0];
assign axi_interconnect_spi_to_s01_couplers_WSTRB = S01_AXI_wstrb[3:0];
assign axi_interconnect_spi_to_s01_couplers_WVALID = S01_AXI_wvalid[0];
assign m00_couplers_to_axi_interconnect_spi_ARREADY = M00_AXI_arready[0];
assign m00_couplers_to_axi_interconnect_spi_AWREADY = M00_AXI_awready[0];
assign m00_couplers_to_axi_interconnect_spi_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_axi_interconnect_spi_BVALID = M00_AXI_bvalid[0];
assign m00_couplers_to_axi_interconnect_spi_RDATA = M00_AXI_rdata[31:0];
assign m00_couplers_to_axi_interconnect_spi_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_axi_interconnect_spi_RVALID = M00_AXI_rvalid[0];
assign m00_couplers_to_axi_interconnect_spi_WREADY = M00_AXI_wready[0];
m00_couplers_imp_FBRXNR m00_couplers
(.M_ACLK(axi_interconnect_spi_ACLK_net),
.M_ARESETN(axi_interconnect_spi_ARESETN_net),
.M_AXI_araddr(m00_couplers_to_axi_interconnect_spi_ARADDR),
.M_AXI_arready(m00_couplers_to_axi_interconnect_spi_ARREADY),
.M_AXI_arvalid(m00_couplers_to_axi_interconnect_spi_ARVALID),
.M_AXI_awaddr(m00_couplers_to_axi_interconnect_spi_AWADDR),
.M_AXI_awready(m00_couplers_to_axi_interconnect_spi_AWREADY),
.M_AXI_awvalid(m00_couplers_to_axi_interconnect_spi_AWVALID),
.M_AXI_bready(m00_couplers_to_axi_interconnect_spi_BREADY),
.M_AXI_bresp(m00_couplers_to_axi_interconnect_spi_BRESP),
.M_AXI_bvalid(m00_couplers_to_axi_interconnect_spi_BVALID),
.M_AXI_rdata(m00_couplers_to_axi_interconnect_spi_RDATA),
.M_AXI_rready(m00_couplers_to_axi_interconnect_spi_RREADY),
.M_AXI_rresp(m00_couplers_to_axi_interconnect_spi_RRESP),
.M_AXI_rvalid(m00_couplers_to_axi_interconnect_spi_RVALID),
.M_AXI_wdata(m00_couplers_to_axi_interconnect_spi_WDATA),
.M_AXI_wready(m00_couplers_to_axi_interconnect_spi_WREADY),
.M_AXI_wstrb(m00_couplers_to_axi_interconnect_spi_WSTRB),
.M_AXI_wvalid(m00_couplers_to_axi_interconnect_spi_WVALID),
.S_ACLK(axi_interconnect_spi_ACLK_net),
.S_ARESETN(axi_interconnect_spi_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR[6:0]),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR[6:0]),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
s00_couplers_imp_13NO89L s00_couplers
(.M_ACLK(axi_interconnect_spi_ACLK_net),
.M_ARESETN(axi_interconnect_spi_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(axi_interconnect_spi_ACLK_net),
.S_ARESETN(axi_interconnect_spi_ARESETN_net),
.S_AXI_araddr(axi_interconnect_spi_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_interconnect_spi_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_interconnect_spi_to_s00_couplers_ARCACHE),
.S_AXI_arid(axi_interconnect_spi_to_s00_couplers_ARID),
.S_AXI_arlen(axi_interconnect_spi_to_s00_couplers_ARLEN),
.S_AXI_arlock(axi_interconnect_spi_to_s00_couplers_ARLOCK),
.S_AXI_arprot(axi_interconnect_spi_to_s00_couplers_ARPROT),
.S_AXI_arqos(axi_interconnect_spi_to_s00_couplers_ARQOS),
.S_AXI_arready(axi_interconnect_spi_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_interconnect_spi_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_interconnect_spi_to_s00_couplers_ARVALID),
.S_AXI_awaddr(axi_interconnect_spi_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_interconnect_spi_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_interconnect_spi_to_s00_couplers_AWCACHE),
.S_AXI_awid(axi_interconnect_spi_to_s00_couplers_AWID),
.S_AXI_awlen(axi_interconnect_spi_to_s00_couplers_AWLEN),
.S_AXI_awlock(axi_interconnect_spi_to_s00_couplers_AWLOCK),
.S_AXI_awprot(axi_interconnect_spi_to_s00_couplers_AWPROT),
.S_AXI_awqos(axi_interconnect_spi_to_s00_couplers_AWQOS),
.S_AXI_awready(axi_interconnect_spi_to_s00_couplers_AWREADY),
.S_AXI_awsize(axi_interconnect_spi_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_interconnect_spi_to_s00_couplers_AWVALID),
.S_AXI_bid(axi_interconnect_spi_to_s00_couplers_BID),
.S_AXI_bready(axi_interconnect_spi_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_interconnect_spi_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_interconnect_spi_to_s00_couplers_BVALID),
.S_AXI_rdata(axi_interconnect_spi_to_s00_couplers_RDATA),
.S_AXI_rid(axi_interconnect_spi_to_s00_couplers_RID),
.S_AXI_rlast(axi_interconnect_spi_to_s00_couplers_RLAST),
.S_AXI_rready(axi_interconnect_spi_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_interconnect_spi_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_interconnect_spi_to_s00_couplers_RVALID),
.S_AXI_wdata(axi_interconnect_spi_to_s00_couplers_WDATA),
.S_AXI_wlast(axi_interconnect_spi_to_s00_couplers_WLAST),
.S_AXI_wready(axi_interconnect_spi_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_interconnect_spi_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_interconnect_spi_to_s00_couplers_WVALID));
s01_couplers_imp_D9R03B s01_couplers
(.M_ACLK(axi_interconnect_spi_ACLK_net),
.M_ARESETN(axi_interconnect_spi_ARESETN_net),
.M_AXI_araddr(s01_couplers_to_xbar_ARADDR),
.M_AXI_arprot(s01_couplers_to_xbar_ARPROT),
.M_AXI_arready(s01_couplers_to_xbar_ARREADY),
.M_AXI_arvalid(s01_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s01_couplers_to_xbar_AWADDR),
.M_AXI_awprot(s01_couplers_to_xbar_AWPROT),
.M_AXI_awready(s01_couplers_to_xbar_AWREADY),
.M_AXI_awvalid(s01_couplers_to_xbar_AWVALID),
.M_AXI_bready(s01_couplers_to_xbar_BREADY),
.M_AXI_bresp(s01_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s01_couplers_to_xbar_BVALID),
.M_AXI_rdata(s01_couplers_to_xbar_RDATA),
.M_AXI_rready(s01_couplers_to_xbar_RREADY),
.M_AXI_rresp(s01_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s01_couplers_to_xbar_RVALID),
.M_AXI_wdata(s01_couplers_to_xbar_WDATA),
.M_AXI_wready(s01_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s01_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s01_couplers_to_xbar_WVALID),
.S_ACLK(axi_interconnect_spi_ACLK_net),
.S_ARESETN(axi_interconnect_spi_ARESETN_net),
.S_AXI_araddr(axi_interconnect_spi_to_s01_couplers_ARADDR),
.S_AXI_arprot(axi_interconnect_spi_to_s01_couplers_ARPROT),
.S_AXI_arready(axi_interconnect_spi_to_s01_couplers_ARREADY),
.S_AXI_arvalid(axi_interconnect_spi_to_s01_couplers_ARVALID),
.S_AXI_awaddr(axi_interconnect_spi_to_s01_couplers_AWADDR),
.S_AXI_awprot(axi_interconnect_spi_to_s01_couplers_AWPROT),
.S_AXI_awready(axi_interconnect_spi_to_s01_couplers_AWREADY),
.S_AXI_awvalid(axi_interconnect_spi_to_s01_couplers_AWVALID),
.S_AXI_bready(axi_interconnect_spi_to_s01_couplers_BREADY),
.S_AXI_bresp(axi_interconnect_spi_to_s01_couplers_BRESP),
.S_AXI_bvalid(axi_interconnect_spi_to_s01_couplers_BVALID),
.S_AXI_rdata(axi_interconnect_spi_to_s01_couplers_RDATA),
.S_AXI_rready(axi_interconnect_spi_to_s01_couplers_RREADY),
.S_AXI_rresp(axi_interconnect_spi_to_s01_couplers_RRESP),
.S_AXI_rvalid(axi_interconnect_spi_to_s01_couplers_RVALID),
.S_AXI_wdata(axi_interconnect_spi_to_s01_couplers_WDATA),
.S_AXI_wready(axi_interconnect_spi_to_s01_couplers_WREADY),
.S_AXI_wstrb(axi_interconnect_spi_to_s01_couplers_WSTRB),
.S_AXI_wvalid(axi_interconnect_spi_to_s01_couplers_WVALID));
Test_AXI_Master_simple_v1_0_hw_1_xbar_0 xbar
(.aclk(axi_interconnect_spi_ACLK_net),
.aresetn(axi_interconnect_spi_ARESETN_net),
.m_axi_araddr(xbar_to_m00_couplers_ARADDR),
.m_axi_arready(xbar_to_m00_couplers_ARREADY),
.m_axi_arvalid(xbar_to_m00_couplers_ARVALID),
.m_axi_awaddr(xbar_to_m00_couplers_AWADDR),
.m_axi_awready(xbar_to_m00_couplers_AWREADY),
.m_axi_awvalid(xbar_to_m00_couplers_AWVALID),
.m_axi_bready(xbar_to_m00_couplers_BREADY),
.m_axi_bresp(xbar_to_m00_couplers_BRESP),
.m_axi_bvalid(xbar_to_m00_couplers_BVALID),
.m_axi_rdata(xbar_to_m00_couplers_RDATA),
.m_axi_rready(xbar_to_m00_couplers_RREADY),
.m_axi_rresp(xbar_to_m00_couplers_RRESP),
.m_axi_rvalid(xbar_to_m00_couplers_RVALID),
.m_axi_wdata(xbar_to_m00_couplers_WDATA),
.m_axi_wready(xbar_to_m00_couplers_WREADY),
.m_axi_wstrb(xbar_to_m00_couplers_WSTRB),
.m_axi_wvalid(xbar_to_m00_couplers_WVALID),
.s_axi_araddr({s01_couplers_to_xbar_ARADDR,s00_couplers_to_xbar_ARADDR}),
.s_axi_arprot({s01_couplers_to_xbar_ARPROT,s00_couplers_to_xbar_ARPROT}),
.s_axi_arready({s01_couplers_to_xbar_ARREADY,s00_couplers_to_xbar_ARREADY}),
.s_axi_arvalid({s01_couplers_to_xbar_ARVALID,s00_couplers_to_xbar_ARVALID}),
.s_axi_awaddr({s01_couplers_to_xbar_AWADDR,s00_couplers_to_xbar_AWADDR}),
.s_axi_awprot({s01_couplers_to_xbar_AWPROT,s00_couplers_to_xbar_AWPROT}),
.s_axi_awready({s01_couplers_to_xbar_AWREADY,s00_couplers_to_xbar_AWREADY}),
.s_axi_awvalid({s01_couplers_to_xbar_AWVALID,s00_couplers_to_xbar_AWVALID}),
.s_axi_bready({s01_couplers_to_xbar_BREADY,s00_couplers_to_xbar_BREADY}),
.s_axi_bresp({s01_couplers_to_xbar_BRESP,s00_couplers_to_xbar_BRESP}),
.s_axi_bvalid({s01_couplers_to_xbar_BVALID,s00_couplers_to_xbar_BVALID}),
.s_axi_rdata({s01_couplers_to_xbar_RDATA,s00_couplers_to_xbar_RDATA}),
.s_axi_rready({s01_couplers_to_xbar_RREADY,s00_couplers_to_xbar_RREADY}),
.s_axi_rresp({s01_couplers_to_xbar_RRESP,s00_couplers_to_xbar_RRESP}),
.s_axi_rvalid({s01_couplers_to_xbar_RVALID,s00_couplers_to_xbar_RVALID}),
.s_axi_wdata({s01_couplers_to_xbar_WDATA,s00_couplers_to_xbar_WDATA}),
.s_axi_wready({s01_couplers_to_xbar_WREADY,s00_couplers_to_xbar_WREADY}),
.s_axi_wstrb({s01_couplers_to_xbar_WSTRB,s00_couplers_to_xbar_WSTRB}),
.s_axi_wvalid({s01_couplers_to_xbar_WVALID,s00_couplers_to_xbar_WVALID}));
endmodule
module m00_couplers_imp_140AAGB
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arprot,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awprot,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [3:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [3:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [3:0]M_AXI_wstrb;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [3:0]S_AXI_araddr;
input [2:0]S_AXI_arprot;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [3:0]S_AXI_awaddr;
input [2:0]S_AXI_awprot;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [3:0]S_AXI_wstrb;
input [0:0]S_AXI_wvalid;
wire [3:0]m00_couplers_to_m00_couplers_ARADDR;
wire [2:0]m00_couplers_to_m00_couplers_ARPROT;
wire [0:0]m00_couplers_to_m00_couplers_ARREADY;
wire [0:0]m00_couplers_to_m00_couplers_ARVALID;
wire [3:0]m00_couplers_to_m00_couplers_AWADDR;
wire [2:0]m00_couplers_to_m00_couplers_AWPROT;
wire [0:0]m00_couplers_to_m00_couplers_AWREADY;
wire [0:0]m00_couplers_to_m00_couplers_AWVALID;
wire [0:0]m00_couplers_to_m00_couplers_BREADY;
wire [1:0]m00_couplers_to_m00_couplers_BRESP;
wire [0:0]m00_couplers_to_m00_couplers_BVALID;
wire [31:0]m00_couplers_to_m00_couplers_RDATA;
wire [0:0]m00_couplers_to_m00_couplers_RREADY;
wire [1:0]m00_couplers_to_m00_couplers_RRESP;
wire [0:0]m00_couplers_to_m00_couplers_RVALID;
wire [31:0]m00_couplers_to_m00_couplers_WDATA;
wire [0:0]m00_couplers_to_m00_couplers_WREADY;
wire [3:0]m00_couplers_to_m00_couplers_WSTRB;
wire [0:0]m00_couplers_to_m00_couplers_WVALID;
assign M_AXI_araddr[3:0] = m00_couplers_to_m00_couplers_ARADDR;
assign M_AXI_arprot[2:0] = m00_couplers_to_m00_couplers_ARPROT;
assign M_AXI_arvalid[0] = m00_couplers_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[3:0] = m00_couplers_to_m00_couplers_AWADDR;
assign M_AXI_awprot[2:0] = m00_couplers_to_m00_couplers_AWPROT;
assign M_AXI_awvalid[0] = m00_couplers_to_m00_couplers_AWVALID;
assign M_AXI_bready[0] = m00_couplers_to_m00_couplers_BREADY;
assign M_AXI_rready[0] = m00_couplers_to_m00_couplers_RREADY;
assign M_AXI_wdata[31:0] = m00_couplers_to_m00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m00_couplers_to_m00_couplers_WSTRB;
assign M_AXI_wvalid[0] = m00_couplers_to_m00_couplers_WVALID;
assign S_AXI_arready[0] = m00_couplers_to_m00_couplers_ARREADY;
assign S_AXI_awready[0] = m00_couplers_to_m00_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m00_couplers_to_m00_couplers_BRESP;
assign S_AXI_bvalid[0] = m00_couplers_to_m00_couplers_BVALID;
assign S_AXI_rdata[31:0] = m00_couplers_to_m00_couplers_RDATA;
assign S_AXI_rresp[1:0] = m00_couplers_to_m00_couplers_RRESP;
assign S_AXI_rvalid[0] = m00_couplers_to_m00_couplers_RVALID;
assign S_AXI_wready[0] = m00_couplers_to_m00_couplers_WREADY;
assign m00_couplers_to_m00_couplers_ARADDR = S_AXI_araddr[3:0];
assign m00_couplers_to_m00_couplers_ARPROT = S_AXI_arprot[2:0];
assign m00_couplers_to_m00_couplers_ARREADY = M_AXI_arready[0];
assign m00_couplers_to_m00_couplers_ARVALID = S_AXI_arvalid[0];
assign m00_couplers_to_m00_couplers_AWADDR = S_AXI_awaddr[3:0];
assign m00_couplers_to_m00_couplers_AWPROT = S_AXI_awprot[2:0];
assign m00_couplers_to_m00_couplers_AWREADY = M_AXI_awready[0];
assign m00_couplers_to_m00_couplers_AWVALID = S_AXI_awvalid[0];
assign m00_couplers_to_m00_couplers_BREADY = S_AXI_bready[0];
assign m00_couplers_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign m00_couplers_to_m00_couplers_BVALID = M_AXI_bvalid[0];
assign m00_couplers_to_m00_couplers_RDATA = M_AXI_rdata[31:0];
assign m00_couplers_to_m00_couplers_RREADY = S_AXI_rready[0];
assign m00_couplers_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign m00_couplers_to_m00_couplers_RVALID = M_AXI_rvalid[0];
assign m00_couplers_to_m00_couplers_WDATA = S_AXI_wdata[31:0];
assign m00_couplers_to_m00_couplers_WREADY = M_AXI_wready[0];
assign m00_couplers_to_m00_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m00_couplers_to_m00_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module m00_couplers_imp_FBRXNR
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [6:0]M_AXI_araddr;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [6:0]M_AXI_awaddr;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [3:0]M_AXI_wstrb;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [6:0]S_AXI_araddr;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [6:0]S_AXI_awaddr;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [3:0]S_AXI_wstrb;
input [0:0]S_AXI_wvalid;
wire [6:0]m00_couplers_to_m00_couplers_ARADDR;
wire [0:0]m00_couplers_to_m00_couplers_ARREADY;
wire [0:0]m00_couplers_to_m00_couplers_ARVALID;
wire [6:0]m00_couplers_to_m00_couplers_AWADDR;
wire [0:0]m00_couplers_to_m00_couplers_AWREADY;
wire [0:0]m00_couplers_to_m00_couplers_AWVALID;
wire [0:0]m00_couplers_to_m00_couplers_BREADY;
wire [1:0]m00_couplers_to_m00_couplers_BRESP;
wire [0:0]m00_couplers_to_m00_couplers_BVALID;
wire [31:0]m00_couplers_to_m00_couplers_RDATA;
wire [0:0]m00_couplers_to_m00_couplers_RREADY;
wire [1:0]m00_couplers_to_m00_couplers_RRESP;
wire [0:0]m00_couplers_to_m00_couplers_RVALID;
wire [31:0]m00_couplers_to_m00_couplers_WDATA;
wire [0:0]m00_couplers_to_m00_couplers_WREADY;
wire [3:0]m00_couplers_to_m00_couplers_WSTRB;
wire [0:0]m00_couplers_to_m00_couplers_WVALID;
assign M_AXI_araddr[6:0] = m00_couplers_to_m00_couplers_ARADDR;
assign M_AXI_arvalid[0] = m00_couplers_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[6:0] = m00_couplers_to_m00_couplers_AWADDR;
assign M_AXI_awvalid[0] = m00_couplers_to_m00_couplers_AWVALID;
assign M_AXI_bready[0] = m00_couplers_to_m00_couplers_BREADY;
assign M_AXI_rready[0] = m00_couplers_to_m00_couplers_RREADY;
assign M_AXI_wdata[31:0] = m00_couplers_to_m00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m00_couplers_to_m00_couplers_WSTRB;
assign M_AXI_wvalid[0] = m00_couplers_to_m00_couplers_WVALID;
assign S_AXI_arready[0] = m00_couplers_to_m00_couplers_ARREADY;
assign S_AXI_awready[0] = m00_couplers_to_m00_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m00_couplers_to_m00_couplers_BRESP;
assign S_AXI_bvalid[0] = m00_couplers_to_m00_couplers_BVALID;
assign S_AXI_rdata[31:0] = m00_couplers_to_m00_couplers_RDATA;
assign S_AXI_rresp[1:0] = m00_couplers_to_m00_couplers_RRESP;
assign S_AXI_rvalid[0] = m00_couplers_to_m00_couplers_RVALID;
assign S_AXI_wready[0] = m00_couplers_to_m00_couplers_WREADY;
assign m00_couplers_to_m00_couplers_ARADDR = S_AXI_araddr[6:0];
assign m00_couplers_to_m00_couplers_ARREADY = M_AXI_arready[0];
assign m00_couplers_to_m00_couplers_ARVALID = S_AXI_arvalid[0];
assign m00_couplers_to_m00_couplers_AWADDR = S_AXI_awaddr[6:0];
assign m00_couplers_to_m00_couplers_AWREADY = M_AXI_awready[0];
assign m00_couplers_to_m00_couplers_AWVALID = S_AXI_awvalid[0];
assign m00_couplers_to_m00_couplers_BREADY = S_AXI_bready[0];
assign m00_couplers_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign m00_couplers_to_m00_couplers_BVALID = M_AXI_bvalid[0];
assign m00_couplers_to_m00_couplers_RDATA = M_AXI_rdata[31:0];
assign m00_couplers_to_m00_couplers_RREADY = S_AXI_rready[0];
assign m00_couplers_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign m00_couplers_to_m00_couplers_RVALID = M_AXI_rvalid[0];
assign m00_couplers_to_m00_couplers_WDATA = S_AXI_wdata[31:0];
assign m00_couplers_to_m00_couplers_WREADY = M_AXI_wready[0];
assign m00_couplers_to_m00_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m00_couplers_to_m00_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module m01_couplers_imp_DLTEH1
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arprot,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awprot,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [4:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [4:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [3:0]M_AXI_wstrb;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [4:0]S_AXI_araddr;
input [2:0]S_AXI_arprot;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [4:0]S_AXI_awaddr;
input [2:0]S_AXI_awprot;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [3:0]S_AXI_wstrb;
input [0:0]S_AXI_wvalid;
wire [4:0]m01_couplers_to_m01_couplers_ARADDR;
wire [2:0]m01_couplers_to_m01_couplers_ARPROT;
wire [0:0]m01_couplers_to_m01_couplers_ARREADY;
wire [0:0]m01_couplers_to_m01_couplers_ARVALID;
wire [4:0]m01_couplers_to_m01_couplers_AWADDR;
wire [2:0]m01_couplers_to_m01_couplers_AWPROT;
wire [0:0]m01_couplers_to_m01_couplers_AWREADY;
wire [0:0]m01_couplers_to_m01_couplers_AWVALID;
wire [0:0]m01_couplers_to_m01_couplers_BREADY;
wire [1:0]m01_couplers_to_m01_couplers_BRESP;
wire [0:0]m01_couplers_to_m01_couplers_BVALID;
wire [31:0]m01_couplers_to_m01_couplers_RDATA;
wire [0:0]m01_couplers_to_m01_couplers_RREADY;
wire [1:0]m01_couplers_to_m01_couplers_RRESP;
wire [0:0]m01_couplers_to_m01_couplers_RVALID;
wire [31:0]m01_couplers_to_m01_couplers_WDATA;
wire [0:0]m01_couplers_to_m01_couplers_WREADY;
wire [3:0]m01_couplers_to_m01_couplers_WSTRB;
wire [0:0]m01_couplers_to_m01_couplers_WVALID;
assign M_AXI_araddr[4:0] = m01_couplers_to_m01_couplers_ARADDR;
assign M_AXI_arprot[2:0] = m01_couplers_to_m01_couplers_ARPROT;
assign M_AXI_arvalid[0] = m01_couplers_to_m01_couplers_ARVALID;
assign M_AXI_awaddr[4:0] = m01_couplers_to_m01_couplers_AWADDR;
assign M_AXI_awprot[2:0] = m01_couplers_to_m01_couplers_AWPROT;
assign M_AXI_awvalid[0] = m01_couplers_to_m01_couplers_AWVALID;
assign M_AXI_bready[0] = m01_couplers_to_m01_couplers_BREADY;
assign M_AXI_rready[0] = m01_couplers_to_m01_couplers_RREADY;
assign M_AXI_wdata[31:0] = m01_couplers_to_m01_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m01_couplers_to_m01_couplers_WSTRB;
assign M_AXI_wvalid[0] = m01_couplers_to_m01_couplers_WVALID;
assign S_AXI_arready[0] = m01_couplers_to_m01_couplers_ARREADY;
assign S_AXI_awready[0] = m01_couplers_to_m01_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m01_couplers_to_m01_couplers_BRESP;
assign S_AXI_bvalid[0] = m01_couplers_to_m01_couplers_BVALID;
assign S_AXI_rdata[31:0] = m01_couplers_to_m01_couplers_RDATA;
assign S_AXI_rresp[1:0] = m01_couplers_to_m01_couplers_RRESP;
assign S_AXI_rvalid[0] = m01_couplers_to_m01_couplers_RVALID;
assign S_AXI_wready[0] = m01_couplers_to_m01_couplers_WREADY;
assign m01_couplers_to_m01_couplers_ARADDR = S_AXI_araddr[4:0];
assign m01_couplers_to_m01_couplers_ARPROT = S_AXI_arprot[2:0];
assign m01_couplers_to_m01_couplers_ARREADY = M_AXI_arready[0];
assign m01_couplers_to_m01_couplers_ARVALID = S_AXI_arvalid[0];
assign m01_couplers_to_m01_couplers_AWADDR = S_AXI_awaddr[4:0];
assign m01_couplers_to_m01_couplers_AWPROT = S_AXI_awprot[2:0];
assign m01_couplers_to_m01_couplers_AWREADY = M_AXI_awready[0];
assign m01_couplers_to_m01_couplers_AWVALID = S_AXI_awvalid[0];
assign m01_couplers_to_m01_couplers_BREADY = S_AXI_bready[0];
assign m01_couplers_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
assign m01_couplers_to_m01_couplers_BVALID = M_AXI_bvalid[0];
assign m01_couplers_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
assign m01_couplers_to_m01_couplers_RREADY = S_AXI_rready[0];
assign m01_couplers_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
assign m01_couplers_to_m01_couplers_RVALID = M_AXI_rvalid[0];
assign m01_couplers_to_m01_couplers_WDATA = S_AXI_wdata[31:0];
assign m01_couplers_to_m01_couplers_WREADY = M_AXI_wready[0];
assign m01_couplers_to_m01_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module m02_couplers_imp_2JVYT2
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [4:0]M_AXI_araddr;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [4:0]M_AXI_awaddr;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [3:0]M_AXI_wstrb;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [4:0]S_AXI_araddr;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [4:0]S_AXI_awaddr;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [3:0]S_AXI_wstrb;
input [0:0]S_AXI_wvalid;
wire [4:0]m02_couplers_to_m02_couplers_ARADDR;
wire [0:0]m02_couplers_to_m02_couplers_ARREADY;
wire [0:0]m02_couplers_to_m02_couplers_ARVALID;
wire [4:0]m02_couplers_to_m02_couplers_AWADDR;
wire [0:0]m02_couplers_to_m02_couplers_AWREADY;
wire [0:0]m02_couplers_to_m02_couplers_AWVALID;
wire [0:0]m02_couplers_to_m02_couplers_BREADY;
wire [1:0]m02_couplers_to_m02_couplers_BRESP;
wire [0:0]m02_couplers_to_m02_couplers_BVALID;
wire [31:0]m02_couplers_to_m02_couplers_RDATA;
wire [0:0]m02_couplers_to_m02_couplers_RREADY;
wire [1:0]m02_couplers_to_m02_couplers_RRESP;
wire [0:0]m02_couplers_to_m02_couplers_RVALID;
wire [31:0]m02_couplers_to_m02_couplers_WDATA;
wire [0:0]m02_couplers_to_m02_couplers_WREADY;
wire [3:0]m02_couplers_to_m02_couplers_WSTRB;
wire [0:0]m02_couplers_to_m02_couplers_WVALID;
assign M_AXI_araddr[4:0] = m02_couplers_to_m02_couplers_ARADDR;
assign M_AXI_arvalid[0] = m02_couplers_to_m02_couplers_ARVALID;
assign M_AXI_awaddr[4:0] = m02_couplers_to_m02_couplers_AWADDR;
assign M_AXI_awvalid[0] = m02_couplers_to_m02_couplers_AWVALID;
assign M_AXI_bready[0] = m02_couplers_to_m02_couplers_BREADY;
assign M_AXI_rready[0] = m02_couplers_to_m02_couplers_RREADY;
assign M_AXI_wdata[31:0] = m02_couplers_to_m02_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m02_couplers_to_m02_couplers_WSTRB;
assign M_AXI_wvalid[0] = m02_couplers_to_m02_couplers_WVALID;
assign S_AXI_arready[0] = m02_couplers_to_m02_couplers_ARREADY;
assign S_AXI_awready[0] = m02_couplers_to_m02_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m02_couplers_to_m02_couplers_BRESP;
assign S_AXI_bvalid[0] = m02_couplers_to_m02_couplers_BVALID;
assign S_AXI_rdata[31:0] = m02_couplers_to_m02_couplers_RDATA;
assign S_AXI_rresp[1:0] = m02_couplers_to_m02_couplers_RRESP;
assign S_AXI_rvalid[0] = m02_couplers_to_m02_couplers_RVALID;
assign S_AXI_wready[0] = m02_couplers_to_m02_couplers_WREADY;
assign m02_couplers_to_m02_couplers_ARADDR = S_AXI_araddr[4:0];
assign m02_couplers_to_m02_couplers_ARREADY = M_AXI_arready[0];
assign m02_couplers_to_m02_couplers_ARVALID = S_AXI_arvalid[0];
assign m02_couplers_to_m02_couplers_AWADDR = S_AXI_awaddr[4:0];
assign m02_couplers_to_m02_couplers_AWREADY = M_AXI_awready[0];
assign m02_couplers_to_m02_couplers_AWVALID = S_AXI_awvalid[0];
assign m02_couplers_to_m02_couplers_BREADY = S_AXI_bready[0];
assign m02_couplers_to_m02_couplers_BRESP = M_AXI_bresp[1:0];
assign m02_couplers_to_m02_couplers_BVALID = M_AXI_bvalid[0];
assign m02_couplers_to_m02_couplers_RDATA = M_AXI_rdata[31:0];
assign m02_couplers_to_m02_couplers_RREADY = S_AXI_rready[0];
assign m02_couplers_to_m02_couplers_RRESP = M_AXI_rresp[1:0];
assign m02_couplers_to_m02_couplers_RVALID = M_AXI_rvalid[0];
assign m02_couplers_to_m02_couplers_WDATA = S_AXI_wdata[31:0];
assign m02_couplers_to_m02_couplers_WREADY = M_AXI_wready[0];
assign m02_couplers_to_m02_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m02_couplers_to_m02_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module s00_couplers_imp_13NO89L
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [0:0]S_AXI_arid;
input [7:0]S_AXI_arlen;
input [0:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [0:0]S_AXI_awid;
input [7:0]S_AXI_awlen;
input [0:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [0:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [0:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire GND_1;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [0:0]s00_couplers_to_auto_pc_ARID;
wire [7:0]s00_couplers_to_auto_pc_ARLEN;
wire [0:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [0:0]s00_couplers_to_auto_pc_AWID;
wire [7:0]s00_couplers_to_auto_pc_AWLEN;
wire [0:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [0:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [0:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[7:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[7:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
GND GND
(.G(GND_1));
Test_AXI_Master_simple_v1_0_hw_1_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arregion({GND_1,GND_1,GND_1,GND_1}),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awregion({GND_1,GND_1,GND_1,GND_1}),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
module s00_couplers_imp_BMA8ID
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
Test_AXI_Master_simple_v1_0_hw_1_auto_pc_1 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
module s01_couplers_imp_D9R03B
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arprot,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awprot,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [3:0]M_AXI_wstrb;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [2:0]S_AXI_arprot;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [2:0]S_AXI_awprot;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [3:0]S_AXI_wstrb;
input [0:0]S_AXI_wvalid;
wire [31:0]s01_couplers_to_s01_couplers_ARADDR;
wire [2:0]s01_couplers_to_s01_couplers_ARPROT;
wire [0:0]s01_couplers_to_s01_couplers_ARREADY;
wire [0:0]s01_couplers_to_s01_couplers_ARVALID;
wire [31:0]s01_couplers_to_s01_couplers_AWADDR;
wire [2:0]s01_couplers_to_s01_couplers_AWPROT;
wire [0:0]s01_couplers_to_s01_couplers_AWREADY;
wire [0:0]s01_couplers_to_s01_couplers_AWVALID;
wire [0:0]s01_couplers_to_s01_couplers_BREADY;
wire [1:0]s01_couplers_to_s01_couplers_BRESP;
wire [0:0]s01_couplers_to_s01_couplers_BVALID;
wire [31:0]s01_couplers_to_s01_couplers_RDATA;
wire [0:0]s01_couplers_to_s01_couplers_RREADY;
wire [1:0]s01_couplers_to_s01_couplers_RRESP;
wire [0:0]s01_couplers_to_s01_couplers_RVALID;
wire [31:0]s01_couplers_to_s01_couplers_WDATA;
wire [0:0]s01_couplers_to_s01_couplers_WREADY;
wire [3:0]s01_couplers_to_s01_couplers_WSTRB;
wire [0:0]s01_couplers_to_s01_couplers_WVALID;
assign M_AXI_araddr[31:0] = s01_couplers_to_s01_couplers_ARADDR;
assign M_AXI_arprot[2:0] = s01_couplers_to_s01_couplers_ARPROT;
assign M_AXI_arvalid[0] = s01_couplers_to_s01_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = s01_couplers_to_s01_couplers_AWADDR;
assign M_AXI_awprot[2:0] = s01_couplers_to_s01_couplers_AWPROT;
assign M_AXI_awvalid[0] = s01_couplers_to_s01_couplers_AWVALID;
assign M_AXI_bready[0] = s01_couplers_to_s01_couplers_BREADY;
assign M_AXI_rready[0] = s01_couplers_to_s01_couplers_RREADY;
assign M_AXI_wdata[31:0] = s01_couplers_to_s01_couplers_WDATA;
assign M_AXI_wstrb[3:0] = s01_couplers_to_s01_couplers_WSTRB;
assign M_AXI_wvalid[0] = s01_couplers_to_s01_couplers_WVALID;
assign S_AXI_arready[0] = s01_couplers_to_s01_couplers_ARREADY;
assign S_AXI_awready[0] = s01_couplers_to_s01_couplers_AWREADY;
assign S_AXI_bresp[1:0] = s01_couplers_to_s01_couplers_BRESP;
assign S_AXI_bvalid[0] = s01_couplers_to_s01_couplers_BVALID;
assign S_AXI_rdata[31:0] = s01_couplers_to_s01_couplers_RDATA;
assign S_AXI_rresp[1:0] = s01_couplers_to_s01_couplers_RRESP;
assign S_AXI_rvalid[0] = s01_couplers_to_s01_couplers_RVALID;
assign S_AXI_wready[0] = s01_couplers_to_s01_couplers_WREADY;
assign s01_couplers_to_s01_couplers_ARADDR = S_AXI_araddr[31:0];
assign s01_couplers_to_s01_couplers_ARPROT = S_AXI_arprot[2:0];
assign s01_couplers_to_s01_couplers_ARREADY = M_AXI_arready[0];
assign s01_couplers_to_s01_couplers_ARVALID = S_AXI_arvalid[0];
assign s01_couplers_to_s01_couplers_AWADDR = S_AXI_awaddr[31:0];
assign s01_couplers_to_s01_couplers_AWPROT = S_AXI_awprot[2:0];
assign s01_couplers_to_s01_couplers_AWREADY = M_AXI_awready[0];
assign s01_couplers_to_s01_couplers_AWVALID = S_AXI_awvalid[0];
assign s01_couplers_to_s01_couplers_BREADY = S_AXI_bready[0];
assign s01_couplers_to_s01_couplers_BRESP = M_AXI_bresp[1:0];
assign s01_couplers_to_s01_couplers_BVALID = M_AXI_bvalid[0];
assign s01_couplers_to_s01_couplers_RDATA = M_AXI_rdata[31:0];
assign s01_couplers_to_s01_couplers_RREADY = S_AXI_rready[0];
assign s01_couplers_to_s01_couplers_RRESP = M_AXI_rresp[1:0];
assign s01_couplers_to_s01_couplers_RVALID = M_AXI_rvalid[0];
assign s01_couplers_to_s01_couplers_WDATA = S_AXI_wdata[31:0];
assign s01_couplers_to_s01_couplers_WREADY = M_AXI_wready[0];
assign s01_couplers_to_s01_couplers_WSTRB = S_AXI_wstrb[3:0];
assign s01_couplers_to_s01_couplers_WVALID = S_AXI_wvalid[0];
endmodule
|
//
// Copyright (C) 2015 Markus Hiienkari <[email protected]>
//
// This file is part of Open Source Scan Converter project.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module seg7_ctrl(
input [3:0] char_id,
output [6:0] segs
);
always @(*)
case (char_id)
4'h0: segs = ~7'b0111111;
4'h1: segs = ~7'b0000110;
4'h2: segs = ~7'b1011011;
4'h3: segs = ~7'b1001111;
4'h4: segs = ~7'b1100110;
4'h5: segs = ~7'b1101101;
4'h6: segs = ~7'b1111101;
4'h7: segs = ~7'b0000111;
4'h8: segs = ~7'b1111111;
4'h9: segs = ~7'b1101111;
4'hA: segs = ~7'b1001001; // ≡ (Scanline sign)
4'hB: segs = ~7'b1010100; // n
4'hC: segs = ~7'b0111001; // C
4'hD: segs = ~7'b1100110; // y
4'hE: segs = ~7'b0111000; // L
default: segs = ~7'b0000000;
endcase
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_wbctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_wbctl( /*AUTOARG*/
// Outputs
so, wbtag_write_wl_c4, wbtag_write_en_c4, wb_read_wl, wb_read_en,
sctag_scbuf_wbwr_wl_c6, sctag_scbuf_wbwr_wen_c6,
sctag_scbuf_wbrd_wl_r0, sctag_scbuf_wbrd_en_r0,
sctag_scbuf_ev_dword_r0, sctag_scbuf_evict_en_r0,
sctag_dram_wr_req, wbctl_hit_unqual_c2, wbctl_mbctl_dep_rdy_en,
wbctl_mbctl_dep_mbid, wbctl_arbctl_full_px1, rdmat_read_wl,
rdmat_read_en, wbctl_wr_addr_sel, wb_or_rdma_wr_req_en,
sctag_scbuf_rdma_rdwl_r0, sctag_scbuf_rdma_rden_r0,
reset_rdmat_vld, set_rdmat_acked, sctag_jbi_wib_dequeue,
// Inputs
si, se, rclk, arst_l, grst_l, dbginit_l, rst_tri_en,
dirty_evict_c3, arbdp_inst_fb_c2, mbctl_wbctl_mbid_c4,
mbctl_hit_c4, mbctl_fbctl_dram_pick, l2_bypass_mode_on,
wb_cam_match_c2, c1_addr_eq_wb_c4, arbctl_wbctl_hit_off_c1,
arbctl_wbctl_inst_vld_c2, dram_sctag_wr_ack, rdmat_pick_vec,
or_rdmat_valid
);
input si, se;
output so;
input rclk;
input arst_l;
input grst_l;
input dbginit_l;
input rst_tri_en;
input dirty_evict_c3;
// This indicates that the Tag of the instruction evicted
// (i.e. lru_tag_c3) needs to written into the WB tag array.
input arbdp_inst_fb_c2;
input [3:0] mbctl_wbctl_mbid_c4;
input mbctl_hit_c4;
input mbctl_fbctl_dram_pick;
// from csr
input l2_bypass_mode_on;
// from wbtag
input [7:0] wb_cam_match_c2;
output [7:0] wbtag_write_wl_c4; // tag wr wl. Tag is written in C4 PH1
output wbtag_write_en_c4; // tag wren Tag is written in C4 PH1
output [7:0] wb_read_wl;
output wb_read_en; // look at read pipeline
// from arbaddr
input c1_addr_eq_wb_c4;
// from arbctl.
input arbctl_wbctl_hit_off_c1; // hit qualifier.
input arbctl_wbctl_inst_vld_c2;
input dram_sctag_wr_ack;
output [2:0] sctag_scbuf_wbwr_wl_c6; // must come out of a flop
output [3:0] sctag_scbuf_wbwr_wen_c6; // must come out of a flop. 3:0 are the same
output [2:0] sctag_scbuf_wbrd_wl_r0;
output sctag_scbuf_wbrd_en_r0;
output [2:0] sctag_scbuf_ev_dword_r0;
output sctag_scbuf_evict_en_r0;
output sctag_dram_wr_req;
// to arbaddr
// to mbctl.
output wbctl_hit_unqual_c2; // hit not qualified with instruction valid.
output wbctl_mbctl_dep_rdy_en;
output [3:0] wbctl_mbctl_dep_mbid;
// to arbctl.
output wbctl_arbctl_full_px1;
// Can accomodate two more instructions
// This signal should come out of a flop
output [3:0] rdmat_read_wl;
output rdmat_read_en;
input [3:0] rdmat_pick_vec ; // from rdmatctl.
input or_rdmat_valid ;
output wbctl_wr_addr_sel;
output wb_or_rdma_wr_req_en; // to evict_tag_dp
output [1:0] sctag_scbuf_rdma_rdwl_r0;
output sctag_scbuf_rdma_rden_r0;
// rdmatctl
output [3:0] reset_rdmat_vld;
output [3:0] set_rdmat_acked;
// to jbi
output sctag_jbi_wib_dequeue;
////////////////////////////////////////////////////////////////////////////////
wire dram_sctag_wr_ack_d1;
wire [7:0] wb_valid_in;
wire [7:0] wb_valid;
wire or_wb_valid;
wire [2:0] enc_write_wl_c5;
wire [2:0] enc_write_wl_c6;
wire [7:0] wb_cam_hit_vec_c2;
wire [7:0] wb_cam_hit_vec_c3;
wire [7:0] wb_cam_hit_vec_c4;
wire wbctl_hit_unqual_c2;
wire wbctl_hit_qual_c2;
wire wbctl_hit_qual_c3;
wire wbctl_hit_qual_c4;
wire [7:0] set_wb_valid;
wire [7:0] reset_wb_valid;
wire [7:0] set_wb_acked;
wire [7:0] wb_acked_in;
wire [7:0] wb_acked;
wire mbid_wr_en;
wire [7:0] sel_insert_mbid_c4;
wire [3:0] mbid0;
wire [3:0] mbid1;
wire [3:0] mbid2;
wire [3:0] mbid3;
wire [3:0] mbid4;
wire [3:0] mbid5;
wire [3:0] mbid6;
wire [3:0] mbid7;
wire [7:0] wb_mbid_vld_in;
wire [7:0] wb_mbid_vld;
wire or_wb_mbid_vld_in;
wire or_wb_mbid_vld;
wire [7:0] sel_mbid;
wire sel_default_mux1;
wire sel_default_mux2;
wire sel_default_mbentry;
wire [3:0] sel_mbid3t0;
wire [3:0] sel_mbid7t4;
wire [3:0] sel_mbid7t0;
wire can_req_dram;
wire enter_state0;
wire leave_state0;
wire enter_state1;
wire leave_state1;
wire enter_state2;
wire leave_state2;
wire [2:0] next_state;
wire [2:0] state;
wire dram_req_pending_in;
wire dram_req_pending;
wire inc_cycle_count;
wire [3:0] cycle_count_plus1;
wire [3:0] next_cycle_count;
wire [3:0] cycle_count_in;
wire [3:0] cycle_count;
wire sctag_scbuf_evict_en_r0_d1;
wire init_pick_state;
wire sel_lshift_quad;
wire sel_same_quad;
wire [2:0] lshift_quad_state;
wire [2:0] quad_state_in;
wire [2:0] quad_state;
wire sel_lshift_quad0;
wire sel_same_quad0;
wire [3:0] lshift_quad0_state;
wire [3:0] quad0_state_in;
wire [3:0] quad0_state;
wire sel_lshift_quad1;
wire sel_same_quad1;
wire [3:0] lshift_quad1_state;
wire [3:0] quad1_state_in;
wire [3:0] quad1_state;
wire sel_lshift_quad2;
wire sel_same_quad2;
wire [3:0] lshift_quad2_state;
wire [3:0] quad2_state_in;
wire [3:0] quad2_state;
wire [3:0] pick_quad0_sel;
wire [3:0] pick_quad1_sel;
wire [3:0] pick_quad2_sel;
wire [2:0] pick_quad_sel;
wire [3:0] pick_quad0_in;
wire [3:0] pick_quad1_in;
wire [3:0] pick_quad2_in;
wire [2:0] pick_quad_in;
wire [7:0] pick_wb_read_wl;
wire [3:0] pick_rdmat_read_wl ;
wire [7:0] latched_wb_read_wl;
wire [3:0] latched_rdmad_read_wl;
wire latched_rdma_read_en, latched_wb_read_en ;
wire [3:0] wb_count;
wire [3:0] next_wb_count;
wire [3:0] wb_count_plus1;
wire [3:0] wb_count_minus1;
wire inc_wb_count;
wire dec_wb_count;
wire same_wb_count;
wire wb_count_5;
wire wb_count_5_plus;
wire wbctl_arbctl_full_px1_in;
wire sctag_jbi_wib_dequeue_prev;
wire [7:0] wbtag_write_wl_c5;
wire bypass_en_c1, bypass_en_c2;
wire bypass_hit_en_c2;
wire [7:0] wb_cam_hit_vec_tmp_c2;
wire wbtag_write_en_c3;
wire dbb_rst_l;
wire [7:0] sel_mbid_rst;
///////////////////////////////////////////////////////////////////
// Reset flop
///////////////////////////////////////////////////////////////////
dffrl_async #(1) reset_flop (.q(dbb_rst_l),
.clk(rclk),
.rst_l(arst_l),
.din(grst_l),
.se(se), .si(), .so());
////////////////////////////////////////////////////////////////////////////////
dff_s #(1) ff_arbctl_wbctl_inst_vld_c3
(.q (arbctl_wbctl_inst_vld_c3),
.din (arbctl_wbctl_inst_vld_c2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_arbdp_inst_fb_c3
(.q (arbdp_inst_fb_c3),
.din (arbdp_inst_fb_c2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_arbctl_wbctl_hit_off_c2
(.q (arbctl_wbctl_hit_off_c2),
.din (arbctl_wbctl_hit_off_c1),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_dram_sctag_wr_ack_d1
(.q (dram_sctag_wr_ack_d1),
.din (dram_sctag_wr_ack),
.clk (rclk),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
// eviction pipeline.
//------------------------------------------------------------------------------
// C2 C3 C4 C5 C6 C7
//------------------------------------------------------------------------------
// lru dirty xmit rd data rd_data write
// calc. evict lru way array array. WB array
// in PH2
// xmit
// lru way
//
// wen and wl write wtag xmit
// generation array in wl for write
// for wbtag. PH1 and wen.
//------------------------------------------------------------------------------
////////////////////////////////////////////////////////////////////////////////
assign wbtag_write_wl_c4[0] = ~wb_valid[0] ;
assign wbtag_write_wl_c4[1] = ~wb_valid[1] & wb_valid[0] ;
assign wbtag_write_wl_c4[2] = ~wb_valid[2] & (&(wb_valid[1:0])) ;
assign wbtag_write_wl_c4[3] = ~wb_valid[3] & (&(wb_valid[2:0])) ;
assign wbtag_write_wl_c4[4] = ~wb_valid[4] & (&(wb_valid[3:0])) ;
assign wbtag_write_wl_c4[5] = ~wb_valid[5] & (&(wb_valid[4:0])) ;
assign wbtag_write_wl_c4[6] = ~wb_valid[6] & (&(wb_valid[5:0])) ;
assign wbtag_write_wl_c4[7] = ~wb_valid[7] & (&(wb_valid[6:0])) ;
dff_s #(8) ff_wbtag_write_wl_c5
(.q (wbtag_write_wl_c5[7:0]),
.din (wbtag_write_wl_c4[7:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign enc_write_wl_c5[0] = (wbtag_write_wl_c5[1] | wbtag_write_wl_c5[3] |
wbtag_write_wl_c5[5] | wbtag_write_wl_c5[7]) ;
assign enc_write_wl_c5[1] = (wbtag_write_wl_c5[2] | wbtag_write_wl_c5[3] |
wbtag_write_wl_c5[6] | wbtag_write_wl_c5[7]) ;
assign enc_write_wl_c5[2] = (wbtag_write_wl_c5[4] | wbtag_write_wl_c5[5] |
wbtag_write_wl_c5[6] | wbtag_write_wl_c5[7]) ;
dff_s #(3) ff_enc_write_wl_c6
(.q (enc_write_wl_c6[2:0]),
.din (enc_write_wl_c5[2:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
/////////////////////////////////////////////////////////////////////////////////
// A fill causes the WBB to be written in L2 $ off mode.
// Here is the pipeline for a Fill in OFF mode.
//
// C5 C6 C7 C8 C8
//
// read FB mux xmit data write
// with in scdata in scbuf WB
// $ data.
//
// write xmit setup
// wbtag wl and wen wb write
// in PH1 from sctag en and wl
//
/////////////////////////////////////////////////////////////////////////////////
dff_s #(1) ff_l2_bypass_mode_on_d1
(.q (l2_bypass_mode_on_d1),
.din (l2_bypass_mode_on),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign wbtag_write_en_c3 = dirty_evict_c3 |
(l2_bypass_mode_on_d1 & arbdp_inst_fb_c3 &
arbctl_wbctl_inst_vld_c3) ;
dff_s #(1) ff_wbtag_write_en_c4
(.q (wbtag_write_en_c4),
.din (wbtag_write_en_c3),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_wbtag_write_we_c5
(.q (wbtag_write_we_c5),
.din (wbtag_write_en_c4),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_wbtag_write_we_c6
(.q (wbtag_write_we_c6),
.din (wbtag_write_we_c5),
.clk (rclk),
.se(se), .si (), .so ()
) ;
/////////////////////////////////////////////////////////////////////////////////
// An eviction causes the WBB to be written in L2 $ ON mode.
//
// C5 C6 C7 C8 C9
//
// read $ read $ cyc2 xmit data xmit write
// inside scdata to scbuf data into wbb
//
//
//
// write xmit wl setup
// wbtag to wbdata wb write
// in PH1 en and wl
//
//
// IN OFF mode, the wl and wen are transmitted to scbuf in the C6 cycle of
// a Fill operation.
// A fill is indicated by arbdp_inst_fb_c3 & arbctl_wbctl_inst_vld_c3
/////////////////////////////////////////////////////////////////////////////////
assign sctag_scbuf_wbwr_wl_c6[2:0] = enc_write_wl_c6[2:0] ;
assign sctag_scbuf_wbwr_wen_c6[3:0] = {4{wbtag_write_we_c6}} ;
////////////////////////////////////////////////////////////////////////////////
// VALID bit
// Set on insertion.
// Reset on an eviction to DRAM.
////////////////////////////////////////////////////////////////////////////////
assign reset_rdmat_vld = {4{leave_state2}} & latched_rdmad_read_wl ;
assign set_rdmat_acked = {4{leave_state1}} & latched_rdmad_read_wl ;
assign set_wb_valid = {8{wbtag_write_we_c5}} & wbtag_write_wl_c5 ;
assign reset_wb_valid = {8{leave_state2}} & latched_wb_read_wl ;
assign wb_valid_in = (wb_valid | set_wb_valid) & ~(reset_wb_valid) ;
dffrl_s #(8) ff_wb_valid
(.q (wb_valid[7:0]),
.din (wb_valid_in[7:0]),
.clk (rclk), .rst_l(dbb_rst_l),
.se(se), .si (), .so ()
) ;
assign or_wb_valid = |(wb_valid[7:0]) ;
////////////////////////////////////////////////////////////////////////////////
// ACKED bit
// Set when an entry is acked by the DRAM controller.
// Reset when the valid bit is reset i.e. on an eviction to DRAM.
////////////////////////////////////////////////////////////////////////////////
assign set_wb_acked = ({8{leave_state1}} & latched_wb_read_wl) ;
assign wb_acked_in = (wb_acked | set_wb_acked) & ~reset_wb_valid ;
dffrl_s #(8) ff_wb_acked
(.q (wb_acked[7:0]),
.din (wb_acked_in[7:0]),
.clk (rclk), .rst_l(dbb_rst_l),
.se(se), .si (), .so ()
) ;
///////////////////////////////////////////////
// Updated on 11/10/2002
// bypassing of wb_write_data
// required for generation
// of wb hit.
// evicted tag is written into the WBB in C5.
// The operation in C2 in that cycle will have
// to see the effect of the wb write. Hence the
// C4 address being written into the tag is compared
// with the address of the instruction in C1.
//////////////////////////////////////////////
assign bypass_en_c1 = c1_addr_eq_wb_c4 & wbtag_write_en_c4;
dff_s #(1) ff_bypass_en_c2
(.q (bypass_en_c2),
.din (bypass_en_c1),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign bypass_hit_en_c2 = ( bypass_en_c2 & ~arbctl_wbctl_hit_off_c2 ) ;
assign wb_cam_hit_vec_tmp_c2 = ( (wb_cam_match_c2[7:0] & wb_valid[7:0]) &
~(wb_acked[7:0] | {8{arbctl_wbctl_hit_off_c2}}) ) ;
assign wbctl_hit_unqual_c2 = (|(wb_cam_hit_vec_tmp_c2[7:0])) |
bypass_hit_en_c2 ;
assign wb_cam_hit_vec_c2 = ( wb_cam_hit_vec_tmp_c2 ) |
( {8{bypass_hit_en_c2}} & wbtag_write_wl_c5 ) ;
dff_s #(8) ff_wb_cam_hit_vec_c3
(.q (wb_cam_hit_vec_c3[7:0]),
.din (wb_cam_hit_vec_c2[7:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(8) ff_wb_cam_hit_vec_c4
(.q (wb_cam_hit_vec_c4[7:0]),
.din (wb_cam_hit_vec_c3[7:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign wbctl_hit_qual_c2 = wbctl_hit_unqual_c2 & arbctl_wbctl_inst_vld_c2 ;
dff_s #(1) ff_wbctl_hit_qual_c3
(.q (wbctl_hit_qual_c3),
.din (wbctl_hit_qual_c2),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_wbctl_hit_qual_c4
(.q (wbctl_hit_qual_c4),
.din (wbctl_hit_qual_c3),
.clk (rclk),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
// MBID and MBID_vld.
// Written in the C4 cycle of a non-dependent instruction that hits
// the Writeback buffer.
//
// When an ack is received from DRAM for the entry with mbid_vld,
// the corresponding mbid is used to wake up the miss buffer entry
// that depends on the write.The ack may be received when the instruction
// is in flight i.e in C2, C3 otr C4 and yet to set mbid vld. But that is
// okay since the "acked" bit can only be set for one entry in the WBB at
// a time.
// MBID_vld is reset when an entry has mbid_vld =1 and acked=1
//
////////////////////////////////////////////////////////////////////////////////
assign mbid_wr_en = wbctl_hit_qual_c4 & ~mbctl_hit_c4;
assign sel_insert_mbid_c4 = {8{mbid_wr_en}} & wb_cam_hit_vec_c4[7:0] ;
dffe_s #(4) ff_mbid0
(.q (mbid0[3:0]),
.din (mbctl_wbctl_mbid_c4[3:0]),
.en (sel_insert_mbid_c4[0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dffe_s #(4) ff_mbid1
(.q (mbid1[3:0]),
.din (mbctl_wbctl_mbid_c4[3:0]),
.en (sel_insert_mbid_c4[1]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dffe_s #(4) ff_mbid2
(.q (mbid2[3:0]),
.din (mbctl_wbctl_mbid_c4[3:0]),
.en (sel_insert_mbid_c4[2]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dffe_s #(4) ff_mbid3
(.q (mbid3[3:0]),
.din (mbctl_wbctl_mbid_c4[3:0]),
.en (sel_insert_mbid_c4[3]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dffe_s #(4) ff_mbid4
(.q (mbid4[3:0]),
.din (mbctl_wbctl_mbid_c4[3:0]),
.en (sel_insert_mbid_c4[4]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dffe_s #(4) ff_mbid5
(.q (mbid5[3:0]),
.din (mbctl_wbctl_mbid_c4[3:0]),
.en (sel_insert_mbid_c4[5]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dffe_s #(4) ff_mbid6
(.q (mbid6[3:0]),
.din (mbctl_wbctl_mbid_c4[3:0]),
.en (sel_insert_mbid_c4[6]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dffe_s #(4) ff_mbid7
(.q (mbid7[3:0]),
.din (mbctl_wbctl_mbid_c4[3:0]),
.en (sel_insert_mbid_c4[7]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign wb_mbid_vld_in[7:0] = (wb_mbid_vld[7:0] | sel_insert_mbid_c4[7:0]) &
~(sel_mbid[7:0]) ;
dffrl_s #(8) ff_wb_mbid_vld
(.q (wb_mbid_vld[7:0]),
.din (wb_mbid_vld_in[7:0]),
.clk (rclk), .rst_l(dbb_rst_l),
.se(se), .si (), .so ()
) ;
assign or_wb_mbid_vld_in = |(wb_mbid_vld_in[7:0]) ;
dffrl_s #(1) ff_or_wb_mbid_vld
(.q (or_wb_mbid_vld),
.din (or_wb_mbid_vld_in),
.clk (rclk), .rst_l(dbb_rst_l),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
assign sel_mbid[7:0] = wb_acked[7:0] & wb_mbid_vld[7:0] ;
assign sel_default_mux1 = ~(sel_mbid[0] | sel_mbid[1] | sel_mbid[2]) ;
assign sel_default_mux2 = ~(sel_mbid[4] | sel_mbid[5] | sel_mbid[6]) ;
assign sel_default_mbentry = |(sel_mbid[3:0]) ;
assign sel_mbid_rst[0] = sel_mbid[0] & ~rst_tri_en ;
assign sel_mbid_rst[1] = sel_mbid[1] & ~rst_tri_en ;
assign sel_mbid_rst[2] = sel_mbid[2] & ~rst_tri_en ;
assign sel_mbid_rst[3] = sel_default_mux1 | rst_tri_en ;
assign sel_mbid_rst[4] = sel_mbid[4] & ~rst_tri_en ;
assign sel_mbid_rst[5] = sel_mbid[5] & ~rst_tri_en ;
assign sel_mbid_rst[6] = sel_mbid[6] & ~rst_tri_en ;
assign sel_mbid_rst[7] = sel_default_mux2 | rst_tri_en ;
mux4ds #(4) mux_sel_mbid3t0
(.dout (sel_mbid3t0[3:0]),
.in0 (mbid0[3:0]), .sel0 (sel_mbid_rst[0]),
.in1 (mbid1[3:0]), .sel1 (sel_mbid_rst[1]),
.in2 (mbid2[3:0]), .sel2 (sel_mbid_rst[2]),
.in3 (mbid3[3:0]), .sel3 (sel_mbid_rst[3])
) ;
mux4ds #(4) mux_sel_mbid7t4
(.dout (sel_mbid7t4[3:0]),
.in0 (mbid4[3:0]), .sel0 (sel_mbid_rst[4]),
.in1 (mbid5[3:0]), .sel1 (sel_mbid_rst[5]),
.in2 (mbid6[3:0]), .sel2 (sel_mbid_rst[6]),
.in3 (mbid7[3:0]), .sel3 (sel_mbid_rst[7])
) ;
mux2ds #(4) mux_sel_mbid7t0
(.dout (sel_mbid7t0[3:0]),
.in0 (sel_mbid3t0[3:0]), .sel0 (sel_default_mbentry),
.in1 (sel_mbid7t4[3:0]), .sel1 (~sel_default_mbentry)
) ;
assign wbctl_mbctl_dep_rdy_en = |(sel_mbid[7:0]) ;
assign wbctl_mbctl_dep_mbid = sel_mbid7t0[3:0] ;
////////////////////////////////////////////////////////////////////////////////
// A Write request is generated only if a READ request is not being
// sent to DRAM in the same cycle. Here is the pipeline for making
// a write request to DRAM.
//------------------------------------------------------------------------------
// #1 #2 #3
//------------------------------------------------------------------------------
// if (atleast 1 rd wbtag xmit req,addr
// dram_req to
// AND DRAM
// not dram_pick
// in mbctl.
// AND
// not wrreq wbctl_wr_addr_sel
// pending to DRAM) xmitted to
// arbaddr.
// generate RD
// pointer
//
// set wrreq
// pending
//
// xmit read en
// and rd wl to wbtag.
//------------------------------------------------------------------------------
//#n-1 #n(r0) #n+1(r1) #n+2(r2) #n+2(r3)
//------------------------------------------------------------------------------
// ack from dram rd_en rd wbdata mux data
// rd_wl in PH1 in evict
// to scbuf.wbdata
//------------------------------------------------------------------------------
// r4 r5 r6 ...... r12
//------------------------------------------------------------------------------
// perform ecc xmit data1 dat2 data8
// to dram to dram to dram
//
// reset
// wrreq
// pending
//
// reset vld
//
// dec wb counter
////////////////////////////////////////////////////////////////////////////////
assign can_req_dram = ( or_wb_valid | or_rdmat_valid )
& ~dram_req_pending & ~mbctl_fbctl_dram_pick ;
assign enter_state0 = ~dbb_rst_l | leave_state2 ;
assign leave_state0 = state[0] & can_req_dram ;
assign next_state[0] = (state[0] | enter_state0) & ~leave_state0 ;
assign enter_state1 = leave_state0 ;
assign leave_state1 = state[1] & dram_sctag_wr_ack_d1 ;
assign next_state[1] = (state[1] | enter_state1) & ~leave_state1 & dbb_rst_l ;
assign enter_state2 = leave_state1 ;
assign leave_state2 = state[2] & (cycle_count[3:0] == 4'd12) ;
assign next_state[2] = (state[2] | enter_state2) & ~leave_state2 & dbb_rst_l ;
dff_s #(3) ff_state
(.q (state[2:0]),
.din (next_state[2:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign dram_req_pending_in = (dram_req_pending | leave_state0) & ~leave_state2 ;
dffrl_s #(1) ff_dram_req_pending
(.q (dram_req_pending),
.din (dram_req_pending_in),
.clk (rclk), .rst_l(dbb_rst_l),
.se(se), .si (), .so ()
) ;
assign inc_cycle_count = (enter_state2 | state[2]) ;
assign cycle_count_plus1 = cycle_count + 4'b1 ;
assign next_cycle_count = cycle_count_plus1 & ~{4{leave_state2}} ;
mux2ds #(4) mux_cycle_count_in
(.dout (cycle_count_in[3:0]),
.in0 (cycle_count[3:0]), .sel0 (~inc_cycle_count),
.in1 (next_cycle_count[3:0]), .sel1 (inc_cycle_count)
) ;
dffrl_s #(4) ff_cycle_count
(.q (cycle_count[3:0]),
.din (cycle_count_in[3:0]),
.clk (rclk), .rst_l(dbb_rst_l),
.se(se), .si (), .so ()
) ;
assign wb_read_en = leave_state0 & ~pick_quad_sel[2] ;
assign wb_read_wl = pick_wb_read_wl ;
assign rdmat_read_en = leave_state0 & pick_quad_sel[2] ;
assign rdmat_read_wl = pick_rdmat_read_wl;
dffe_s #(8) ff_latched_wb_read_wl
(.q (latched_wb_read_wl[7:0]),
.din (pick_wb_read_wl[7:0]),
.en (leave_state0),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dffe_s #(1) ff_latched_wb_read_en
(.q (latched_wb_read_en),
.din (wb_read_en),
.en (leave_state0),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dffe_s #(4) ff_latched_rdmad_read_wl
(.q (latched_rdmad_read_wl[3:0]),
.din (pick_rdmat_read_wl[3:0]),
.en (leave_state0),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dffe_s #(1) ff_latched_rdma_read_en
(.q (latched_rdma_read_en),
.din (rdmat_read_en),
.en (leave_state0),
.clk (rclk),
.se(se), .si (), .so ()
) ;
// the following signal indicates that the WBB buffer address
// needs to be selected over the rdmat address.
dff_s #(1) ff_wbctl_wr_addr_sel
(.q (wbctl_wr_addr_sel),
.din (wb_read_en),
.clk (rclk),
.se(se), .si (), .so ()
) ;
// the following signal goes to evict_tag_dp to enable the
// address flop that transmits the address to
// DRAM
dff_s #(1) ff_wb_or_rdma_wr_req_en
(.q (wb_or_rdma_wr_req_en),
.din (leave_state0),
.clk (rclk),
.se(se), .si (), .so ()
) ;
// the following signal indicates that a write
// request needs to be issued either from the
// wbb or the rdmat
dff_s #(1) ff_sctag_dram_wr_req
(.q (sctag_dram_wr_req),
.din (wb_or_rdma_wr_req_en),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign sctag_scbuf_wbrd_wl_r0[0] = (latched_wb_read_wl[1] | latched_wb_read_wl[3] |
latched_wb_read_wl[5] | latched_wb_read_wl[7]) ;
assign sctag_scbuf_wbrd_wl_r0[1] = (latched_wb_read_wl[2] | latched_wb_read_wl[3] |
latched_wb_read_wl[6] | latched_wb_read_wl[7]) ;
assign sctag_scbuf_wbrd_wl_r0[2] = (latched_wb_read_wl[4] | latched_wb_read_wl[5] |
latched_wb_read_wl[6] | latched_wb_read_wl[7]) ;
assign sctag_scbuf_wbrd_en_r0 = (sctag_scbuf_evict_en_r0 & ~sctag_scbuf_evict_en_r0_d1) &
latched_wb_read_en ;
assign sctag_scbuf_rdma_rdwl_r0[0] = (latched_rdmad_read_wl[1] | latched_rdmad_read_wl[3] );
assign sctag_scbuf_rdma_rdwl_r0[1] = (latched_rdmad_read_wl[2] | latched_rdmad_read_wl[3] );
assign sctag_scbuf_rdma_rden_r0 = (sctag_scbuf_evict_en_r0 & ~sctag_scbuf_evict_en_r0_d1) &
latched_rdma_read_en ;
assign sctag_scbuf_ev_dword_r0 = cycle_count[2:0] ;
assign sctag_scbuf_evict_en_r0 = leave_state1 | (state[2] & (cycle_count < 4'd8)) ;
dff_s #(1) ff_sctag_scbuf_evict_en_r0_d1
(.q (sctag_scbuf_evict_en_r0_d1),
.din (sctag_scbuf_evict_en_r0),
.clk (rclk),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
// Dequeue of rdmad buffer needs to be sent to jbus.
////////////////////////////////////////////////////////////////////////////////
assign sctag_jbi_wib_dequeue_prev = leave_state2 &
latched_rdma_read_en ;
dff_s #(1) ff_sctag_jbi_wib_dequeue
(.q (sctag_jbi_wib_dequeue),
.din (sctag_jbi_wib_dequeue_prev),
.clk (rclk),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
mux2ds #(4) mux_pick_quad0_in
(.dout (pick_quad0_in[3:0]),
.in0 (wb_valid[3:0]), .sel0 (~or_wb_mbid_vld),
.in1 (wb_mbid_vld[3:0]), .sel1 (or_wb_mbid_vld)
) ;
mux2ds #(4) mux_pick_quad1_in
(.dout (pick_quad1_in[3:0]),
.in0 (wb_valid[7:4]), .sel0 (~or_wb_mbid_vld),
.in1 (wb_mbid_vld[7:4]), .sel1 (or_wb_mbid_vld)
) ;
assign pick_quad2_in[3:0] = rdmat_pick_vec[3:0] ;
assign pick_quad_in[0] = |(pick_quad0_in[3:0]) ;
assign pick_quad_in[1] = |(pick_quad1_in[3:0]) ;
assign pick_quad_in[2] = |(pick_quad2_in[3:0]) ;
assign init_pick_state = ~dbb_rst_l | ~dbginit_l ;
assign sel_lshift_quad = leave_state1 & ~init_pick_state ;
assign sel_same_quad = ~sel_lshift_quad & ~init_pick_state ;
assign lshift_quad_state = {quad_state[1:0], quad_state[2]} ;
mux3ds #(3) mux_quad_state_in
(.dout (quad_state_in[2:0]),
.in0 (3'b01), .sel0 (init_pick_state),
.in1 (quad_state[2:0]), .sel1 (sel_same_quad),
.in2 (lshift_quad_state[2:0]), .sel2 (sel_lshift_quad)
) ;
dff_s #(3) ff_quad_state
(.q (quad_state[2:0]),
.din (quad_state_in[2:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign sel_lshift_quad0 = leave_state1 & |(latched_wb_read_wl[3:0]) & ~init_pick_state ;
assign sel_same_quad0 = ~sel_lshift_quad0 & ~init_pick_state ;
assign lshift_quad0_state = {quad0_state[2:0], quad0_state[3]} ;
mux3ds #(4) mux_quad0_state_in
(.dout (quad0_state_in[3:0]),
.in0 (4'b0001), .sel0 (init_pick_state),
.in1 (quad0_state[3:0]), .sel1 (sel_same_quad0),
.in2 (lshift_quad0_state[3:0]), .sel2 (sel_lshift_quad0)
) ;
dff_s #(4) ff_quad0_state
(.q (quad0_state[3:0]),
.din (quad0_state_in[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign sel_lshift_quad1 = leave_state1 & |(latched_wb_read_wl[7:4]) & ~init_pick_state ;
assign sel_same_quad1 = ~sel_lshift_quad1 & ~init_pick_state ;
assign lshift_quad1_state = {quad1_state[2:0], quad1_state[3]} ;
mux3ds #(4) mux_quad1_state_in
(.dout (quad1_state_in[3:0]),
.in0 (4'b0001), .sel0 (init_pick_state),
.in1 (quad1_state[3:0]), .sel1 (sel_same_quad1),
.in2 (lshift_quad1_state[3:0]), .sel2 (sel_lshift_quad1)
) ;
dff_s #(4) ff_quad1_state
(.q (quad1_state[3:0]),
.din (quad1_state_in[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign sel_lshift_quad2 = leave_state1 & |(latched_wb_read_wl[7:4]) & ~init_pick_state ;
assign sel_same_quad2 = ~sel_lshift_quad2 & ~init_pick_state ;
assign lshift_quad2_state = {quad2_state[2:0], quad2_state[3]} ;
mux3ds #(4) mux_quad2_state_in
(.dout (quad2_state_in[3:0]),
.in0 (4'b0001), .sel0 (init_pick_state),
.in1 (quad2_state[3:0]), .sel1 (sel_same_quad2),
.in2 (lshift_quad2_state[3:0]), .sel2 (sel_lshift_quad2)
) ;
dff_s #(4) ff_quad2_state
(.q (quad2_state[3:0]),
.din (quad2_state_in[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
// QUAD0 bits.
assign pick_quad0_sel[0] = pick_quad0_in[0] &
(quad0_state[0] |
(quad0_state[1] & ~(pick_quad0_in[1] |
pick_quad0_in[2] |
pick_quad0_in[3])) |
(quad0_state[2] & ~(pick_quad0_in[2] |
pick_quad0_in[3])) |
(quad0_state[3] & ~(pick_quad0_in[3])) ) ;
assign pick_quad0_sel[1] = pick_quad0_in[1] &
(quad0_state[1] |
(quad0_state[2] & ~(pick_quad0_in[2] |
pick_quad0_in[3] |
pick_quad0_in[0])) |
(quad0_state[3] & ~(pick_quad0_in[3] |
pick_quad0_in[0])) |
(quad0_state[0] & ~(pick_quad0_in[0])) ) ;
assign pick_quad0_sel[2] = pick_quad0_in[2] &
(quad0_state[2] |
(quad0_state[3] & ~(pick_quad0_in[3] |
pick_quad0_in[0] |
pick_quad0_in[1])) |
(quad0_state[0] & ~(pick_quad0_in[0] |
pick_quad0_in[1])) |
(quad0_state[1] & ~(pick_quad0_in[1])) ) ;
assign pick_quad0_sel[3] = pick_quad0_in[3] &
(quad0_state[3] |
(quad0_state[0] & ~(pick_quad0_in[0] |
pick_quad0_in[1] |
pick_quad0_in[2])) |
(quad0_state[1] & ~(pick_quad0_in[1] |
pick_quad0_in[2])) |
(quad0_state[2] & ~(pick_quad0_in[2])) ) ;
// QUAD1 bits.
assign pick_quad1_sel[0] = pick_quad1_in[0] &
(quad1_state[0] |
(quad1_state[1] & ~(pick_quad1_in[1] |
pick_quad1_in[2] |
pick_quad1_in[3])) |
(quad1_state[2] & ~(pick_quad1_in[2] |
pick_quad1_in[3])) |
(quad1_state[3] & ~(pick_quad1_in[3])) ) ;
assign pick_quad1_sel[1] = pick_quad1_in[1] &
(quad1_state[1] |
(quad1_state[2] & ~(pick_quad1_in[2] |
pick_quad1_in[3] |
pick_quad1_in[0])) |
(quad1_state[3] & ~(pick_quad1_in[3] |
pick_quad1_in[0])) |
(quad1_state[0] & ~(pick_quad1_in[0])) ) ;
assign pick_quad1_sel[2] = pick_quad1_in[2] &
(quad1_state[2] |
(quad1_state[3] & ~(pick_quad1_in[3] |
pick_quad1_in[0] |
pick_quad1_in[1])) |
(quad1_state[0] & ~(pick_quad1_in[0] |
pick_quad1_in[1])) |
(quad1_state[1] & ~(pick_quad1_in[1])) ) ;
assign pick_quad1_sel[3] = pick_quad1_in[3] &
(quad1_state[3] |
(quad1_state[0] & ~(pick_quad1_in[0] |
pick_quad1_in[1] |
pick_quad1_in[2])) |
(quad1_state[1] & ~(pick_quad1_in[1] |
pick_quad1_in[2])) |
(quad1_state[2] & ~(pick_quad1_in[2])) ) ;
// QUAD1 bits.
assign pick_quad2_sel[0] = pick_quad2_in[0] &
(quad2_state[0] |
(quad2_state[1] & ~(pick_quad2_in[1] |
pick_quad2_in[2] |
pick_quad2_in[3])) |
(quad2_state[2] & ~(pick_quad2_in[2] |
pick_quad2_in[3])) |
(quad2_state[3] & ~(pick_quad2_in[3])) ) ;
assign pick_quad2_sel[1] = pick_quad2_in[1] &
(quad2_state[1] |
(quad2_state[2] & ~(pick_quad2_in[2] |
pick_quad2_in[3] |
pick_quad2_in[0])) |
(quad2_state[3] & ~(pick_quad2_in[3] |
pick_quad2_in[0])) |
(quad2_state[0] & ~(pick_quad2_in[0])) ) ;
assign pick_quad2_sel[2] = pick_quad2_in[2] &
(quad2_state[2] |
(quad2_state[3] & ~(pick_quad2_in[3] |
pick_quad2_in[0] |
pick_quad2_in[1])) |
(quad2_state[0] & ~(pick_quad2_in[0] |
pick_quad2_in[1])) |
(quad2_state[1] & ~(pick_quad2_in[1])) ) ;
assign pick_quad2_sel[3] = pick_quad2_in[3] &
(quad2_state[3] |
(quad2_state[0] & ~(pick_quad2_in[0] |
pick_quad2_in[1] |
pick_quad2_in[2])) |
(quad2_state[1] & ~(pick_quad2_in[1] |
pick_quad2_in[2])) |
(quad2_state[2] & ~(pick_quad2_in[2])) ) ;
// QUAD bits.
assign pick_quad_sel[0] = pick_quad_in[0] & ( quad_state[0] |
( quad_state[1] & ~( pick_quad_in[1] | pick_quad_in[2] ) ) |
( quad_state[2] & ~pick_quad_in[2] ) ) ;
assign pick_quad_sel[1] = pick_quad_in[1] & ( quad_state[1] |
( quad_state[2] & ~( pick_quad_in[2] | pick_quad_in[0] ) ) |
( quad_state[0] & ~pick_quad_in[0] ) ) ;
assign pick_quad_sel[2] = pick_quad_in[2] & ( quad_state[2] |
( quad_state[0] & ~( pick_quad_in[0] | pick_quad_in[1] ) ) |
( quad_state[1] & ~pick_quad_in[1] ) ) ;
assign pick_wb_read_wl[3:0] = (pick_quad0_sel[3:0] & {4{pick_quad_sel[0]}}) ;
assign pick_wb_read_wl[7:4] = (pick_quad1_sel[3:0] & {4{pick_quad_sel[1]}}) ;
assign pick_rdmat_read_wl[3:0]= (pick_quad2_sel[3:0] & {4{pick_quad_sel[2]}}) ;
////////////////////////////////////////////////////////////////////////////////
assign inc_wb_count = wbtag_write_en_c4 & ~(leave_state2 &
latched_wb_read_en ) ;
assign dec_wb_count = ~wbtag_write_en_c4 &
( leave_state2 & latched_wb_read_en ) ;
assign same_wb_count = ~(inc_wb_count | dec_wb_count) ;
assign wb_count_plus1 = wb_count + 4'b1 ;
assign wb_count_minus1 = wb_count - 4'b1 ;
mux3ds #(4) mux_next_wb_count
(.dout (next_wb_count[3:0]),
.in0 (wb_count[3:0]), .sel0 (same_wb_count),
.in1 (wb_count_plus1[3:0]), .sel1 (inc_wb_count),
.in2 (wb_count_minus1[3:0]), .sel2 (dec_wb_count)
) ;
dffrl_s #(4) ff_wb_count
(.q (wb_count[3:0]),
.din (next_wb_count[3:0]),
.clk (rclk), .rst_l(dbb_rst_l),
.se(se), .si (), .so ()
) ;
// synopsys translate_off
always @(wb_count ) begin
if( wb_count > 4'd8 ) begin
// 0in <fire -message "FATAL ERROR: wb_counter overflow."
`ifdef DEFINE_0IN
`else
`ifdef MODELSIM
$display("WB_COUNT", "wb_counter overflow.");
`else
$error("WB_COUNT", "wb_counter overflow.");
`endif
`endif
end
end
// synopsys translate_on
////////////////////////////////////////////////////////////////////////////
// wb_count is a c5 flop.
// The following condition is actually evaluated in C4 and flopped to C5
//
// When an eviction is in C4, the earliest following eviction can be
// in C1 and the one following that could be in PX2 ( happens if the
// C1 instruction has stalled ).
// Hence the px1 instruction will not be picked if the counter is 6 or greater.
////////////////////////////////////////////////////////////////////////////
assign wb_count_5 = (wb_count[3:0] == 4'd5) ;
assign wb_count_5_plus = (wb_count[3:0] > 4'd5) ;
assign wbctl_arbctl_full_px1_in = wb_count_5_plus | (wb_count_5 & inc_wb_count) ;
dffrl_s #(1) ff_wbctl_arbctl_full_px1
(.q (wbctl_arbctl_full_px1),
.din (wbctl_arbctl_full_px1_in),
.clk (rclk), .rst_l(dbb_rst_l),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:29:47 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_processing_system7_0_2_sim_netlist.v
// Design : zynq_design_1_processing_system7_0_2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg484" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "zynq_design_1_processing_system7_0_2.hwdef" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
(* CHECK_LICENSE_TYPE = "zynq_design_1_processing_system7_0_2,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg484" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "zynq_design_1_processing_system7_0_2.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__CLKINV_PP_BLACKBOX_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_PP_BLACKBOX_V
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- --
// -- This is the core state machine for the memory subsystem. Talks to both --
// -- processor and the TLB controller. Cache uploads and downloads are done --
// -- using an incrementing burst on the Wishbone bus for maximum efficiency --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
`include "zap_defines.vh"
module zap_cache_fsm #(
parameter CACHE_SIZE = 1024, // Bytes.
parameter CACHE_LINE = 8
)
// ----------------------------------------------
// Port List
// ----------------------------------------------
(
/* Clock and reset */
input wire i_clk,
input wire i_reset,
/* From/to processor */
input wire [31:0] i_address,
input wire i_rd,
input wire i_wr,
input wire [31:0] i_din,
input wire [3:0] i_ben, /* Valid only for writes. */
output reg [31:0] o_dat,
output reg o_ack,
output reg o_err,
output reg [7:0] o_fsr,
output reg [31:0] o_far,
output reg o_err2,
/* From/To CP15 unit */
input wire i_cache_en,
input wire i_cache_inv,
input wire i_cache_clean,
output reg o_cache_inv_done,
output reg o_cache_clean_done,
/* From/to cache. */
input wire [CACHE_LINE*8-1:0]i_cache_line,
input wire i_cache_tag_dirty,
input wire [`CACHE_TAG_WDT-1:0] i_cache_tag, // Tag
input wire i_cache_tag_valid,
output reg [`CACHE_TAG_WDT-1:0] o_cache_tag,
output reg o_cache_tag_dirty,
output reg o_cache_tag_wr_en,
output reg [CACHE_LINE*8-1:0]o_cache_line,
output reg [CACHE_LINE-1:0] o_cache_line_ben, /* Write + Byte enable */
output reg o_cache_clean_req,
input wire i_cache_clean_done,
output reg o_cache_inv_req,
input wire i_cache_inv_done,
output reg [31:0] o_address,
/* From/to TLB unit */
input wire [31:0] i_phy_addr,
input wire [7:0] i_fsr,
input wire [31:0] i_far,
input wire i_fault,
input wire i_cacheable,
input wire i_busy,
/* Memory access ports, both NXT and FF. Usually you'll be connecting NXT ports */
output reg o_wb_cyc_ff, o_wb_cyc_nxt,
output reg o_wb_stb_ff, o_wb_stb_nxt,
output reg [31:0] o_wb_adr_ff, o_wb_adr_nxt,
output reg [31:0] o_wb_dat_ff, o_wb_dat_nxt,
output reg [3:0] o_wb_sel_ff, o_wb_sel_nxt,
output reg o_wb_wen_ff, o_wb_wen_nxt,
output reg [2:0] o_wb_cti_ff, o_wb_cti_nxt,/* Cycle Type Indicator - 010, 111 */
input wire i_wb_ack,
input wire [31:0] i_wb_dat
);
// ----------------------------------------------------------------------------
// Includes and Localparams
// ----------------------------------------------------------------------------
`include "zap_localparams.vh"
`include "zap_defines.vh"
`include "zap_functions.vh"
/* States */
localparam IDLE = 0; /* Resting state. */
localparam UNCACHEABLE = 1; /* Uncacheable access. */
localparam CLEAN_SINGLE = 2; /* Ultimately cleans up cache line. Parent state */
localparam FETCH_SINGLE = 3; /* Ultimately validates cache line. Parent state */
localparam INVALIDATE = 4; /* Cache invalidate parent state */
localparam CLEAN = 5; /* Cache clean parent state */
localparam NUMBER_OF_STATES = 6;
// ----------------------------------------------------------------------------
// Signal aliases
// ----------------------------------------------------------------------------
wire cache_cmp = (i_cache_tag[`CACHE_TAG__TAG] == i_address[`VA__CACHE_TAG]);
wire cache_dirty = i_cache_tag_dirty;
// ----------------------------------------------------------------------------
// Variables
// ----------------------------------------------------------------------------
reg [$clog2(NUMBER_OF_STATES)-1:0] state_ff, state_nxt;
reg [31:0] buf_ff [(CACHE_LINE/4)-1:0];
reg [31:0] buf_nxt[(CACHE_LINE/4)-1:0];
reg cache_clean_req_nxt,
cache_clean_req_ff;
reg cache_inv_req_nxt,
cache_inv_req_ff;
reg [$clog2(CACHE_LINE/4):0] adr_ctr_ff, adr_ctr_nxt; // Needs to take on 0,1,2,3, ... CACHE_LINE/4
reg rhit, whit; // For debug only.
integer i;
/* From/to processor */
reg [31:0] address;
reg rd;
reg wr;
reg [31:0] din;
reg [3:0] ben; /* Valid only for writes. */
reg [CACHE_LINE*8-1:0] cache_line;
reg cache_tag_dirty;
reg [`CACHE_TAG_WDT-1:0] cache_tag; // Tag
reg cache_tag_valid;
reg [31:0] phy_addr;
// ----------------------------------------------------------------------------
// Logic
// ----------------------------------------------------------------------------
/* Tie flops to the output */
always @* o_cache_clean_req = cache_clean_req_ff; // Tie req flop to output.
always @* o_cache_inv_req = cache_inv_req_ff; // Tie inv flop to output.
/* Buffers */
always @ ( posedge i_clk ) if ( state_ff == IDLE ) address <= i_address ;
always @ ( posedge i_clk ) if ( state_ff == IDLE ) rd <= i_rd;
always @ ( posedge i_clk ) if ( state_ff == IDLE ) wr <= i_wr;
always @ ( posedge i_clk ) if ( state_ff == IDLE ) din <= i_din;
always @ ( posedge i_clk ) if ( state_ff == IDLE ) ben <= i_ben ;
always @ ( posedge i_clk ) if ( state_ff == IDLE ) cache_line <= i_cache_line;
always @ ( posedge i_clk ) if ( state_ff == IDLE ) cache_tag_dirty <= i_cache_tag_dirty;
always @ ( posedge i_clk ) if ( state_ff == IDLE ) cache_tag <= i_cache_tag;
always @ ( posedge i_clk ) if ( state_ff == IDLE ) cache_tag_valid <= i_cache_tag_valid;
always @ ( posedge i_clk ) if ( state_ff == IDLE ) phy_addr <= i_phy_addr;
/* Sequential Block */
always @ (posedge i_clk)
begin
if ( i_reset )
begin
o_wb_cyc_ff <= 0;
o_wb_stb_ff <= 0;
o_wb_wen_ff <= 0;
o_wb_sel_ff <= 0;
o_wb_dat_ff <= 0;
o_wb_cti_ff <= CTI_CLASSIC;
o_wb_adr_ff <= 0;
cache_clean_req_ff <= 0;
cache_inv_req_ff <= 0;
adr_ctr_ff <= 0;
state_ff <= IDLE;
end
else
begin
o_wb_cyc_ff <= o_wb_cyc_nxt;
o_wb_stb_ff <= o_wb_stb_nxt;
o_wb_wen_ff <= o_wb_wen_nxt;
o_wb_sel_ff <= o_wb_sel_nxt;
o_wb_dat_ff <= o_wb_dat_nxt;
o_wb_cti_ff <= o_wb_cti_nxt;
o_wb_adr_ff <= o_wb_adr_nxt;
cache_clean_req_ff <= cache_clean_req_nxt;
cache_inv_req_ff <= cache_inv_req_nxt;
adr_ctr_ff <= adr_ctr_nxt;
state_ff <= state_nxt;
end
end
always @ ( posedge i_clk )
begin
for(i=0;i<CACHE_LINE/4;i=i+1)
buf_ff[i] <= buf_nxt[i];
end
/* Combo block */
always @*
begin:blk1
reg [$clog2(CACHE_LINE)-1:0] a;
/* Default values */
a = 0;
state_nxt = state_ff;
adr_ctr_nxt = adr_ctr_ff;
o_wb_cyc_nxt = o_wb_cyc_ff;
o_wb_stb_nxt = o_wb_stb_ff;
o_wb_adr_nxt = o_wb_adr_ff;
o_wb_dat_nxt = o_wb_dat_ff;
o_wb_cti_nxt = o_wb_cti_ff;
o_wb_wen_nxt = o_wb_wen_ff;
o_wb_sel_nxt = o_wb_sel_ff;
cache_clean_req_nxt = cache_clean_req_ff;
cache_inv_req_nxt = cache_clean_req_ff;
o_fsr = 0;
o_far = 0;
o_cache_tag = 0;
o_cache_inv_done = 0;
o_cache_clean_done = 0;
o_cache_tag_dirty = 0;
o_cache_tag_wr_en = 0;
o_cache_line = 0;
o_cache_line_ben = 0;
o_dat = 0;
o_ack = 0;
o_err = 0;
o_err2 = 0;
o_address = address;
for(i=0;i<CACHE_LINE/4;i=i+1)
buf_nxt[i] = buf_ff[i];
rhit = 0;
whit = 0;
case(state_ff)
IDLE:
begin
kill_access;
if ( i_cache_inv )
begin
o_ack = 1'd0;
state_nxt = INVALIDATE;
end
else if ( i_cache_clean )
begin
o_ack = 1'd0;
state_nxt = CLEAN;
end
else if ( !i_rd && !i_wr )
begin
o_ack = 1'd1;
end
else if ( i_fault )
begin
/* MMU access fault. */
o_err = 1'd1;
o_ack = 1'd1;
o_fsr = i_fsr;
o_far = i_far;
end
else if ( i_busy )
begin
/* Wait it out */
o_err2 = 1'd1;
o_ack = 1'd1;
end
else if ( i_rd || i_wr )
begin
if ( i_cacheable && i_cache_en )
begin
case ({cache_cmp,i_cache_tag_valid})
2'b11: /* Cache Hit */
begin
if ( i_rd ) /* Read request. */
begin
/*
* Accelerate performance
* Read throughput at 80MHz
* clock is 80M operations per
* second (Hit).
*/
o_dat = adapt_cache_data(i_address, i_cache_line);
rhit = 1'd1;
o_ack = 1'd1;
end
else if ( i_wr ) /* Write request */
begin
o_ack = 1'd1;
whit = 1'd1;
/*
* Each write to cache takes
* 3 cycles. Write throuput at
* 80MHz is 26.6M operations per
* second (Hit).
*/
o_cache_line =
{(CACHE_LINE/4){i_din}};
o_cache_line_ben = ben_comp ( i_address, i_ben );
/* Write to tag and also write out physical address. */
o_cache_tag_wr_en = 1'd1;
o_cache_tag[`CACHE_TAG__TAG] = i_address[`VA__CACHE_TAG];
o_cache_tag_dirty = 1'd1;
o_cache_tag[`CACHE_TAG__PA] = i_phy_addr >> $clog2(CACHE_LINE);
o_address = i_address;
end
end
2'b01: /* Unrelated tag, possibly dirty. */
begin
/* CPU should retry */
o_ack = 1'd1;
o_err2 = 1'd1;
if ( cache_dirty )
begin
/* Set up counter */
adr_ctr_nxt = 0;
/* Clean a single cache line */
state_nxt = CLEAN_SINGLE;
end
else if ( i_rd | i_wr )
begin
/* Set up counter */
adr_ctr_nxt = 0;
/* Fetch a single cache line */
state_nxt = FETCH_SINGLE;
end
end
default: /* Need to generate a new tag. */
begin
/* CPU should wait. */
o_ack = 1'd1;
o_err2 = 1'd1;
/* Set up counter */
adr_ctr_nxt = 0;
/* Fetch a single cache line */
state_nxt = FETCH_SINGLE;
end
endcase
end
else /* Decidedly non cacheable. */
begin
state_nxt = UNCACHEABLE;
o_ack = 1'd0; /* Wait...*/
o_wb_stb_nxt = 1'd1;
o_wb_cyc_nxt = 1'd1;
o_wb_adr_nxt = i_phy_addr;
o_wb_dat_nxt = i_din;
o_wb_wen_nxt = i_wr;
o_wb_sel_nxt = i_ben;
o_wb_cti_nxt = CTI_CLASSIC;
end
end
end
UNCACHEABLE: /* Uncacheable reads and writes definitely go through this. */
begin
if ( i_wb_ack )
begin
o_dat = i_wb_dat;
o_ack = 1'd1;
state_nxt = IDLE;
kill_access;
end
end
CLEAN_SINGLE: /* Clean single cache line */
begin
o_ack = 1'd1;
o_err2 = i_rd || i_wr ? 1'd1 : 1'd0;
/* Generate address */
adr_ctr_nxt = adr_ctr_ff + (o_wb_stb_ff && i_wb_ack);
if ( adr_ctr_nxt <= ((CACHE_LINE/4) - 1) )
begin
/* Sync up with memory. Use PA in cache tag itself. */
wb_prpr_write( clean_single_d (cache_line, adr_ctr_nxt),
{cache_tag[`CACHE_TAG__PA], {CACHE_LINE{1'd0}}} + (adr_ctr_nxt * (32/8)),
adr_ctr_nxt != ((CACHE_LINE/4) - 1) ? CTI_BURST : CTI_EOB, 4'b1111);
end
else
begin
/* Move to wait state */
kill_access;
state_nxt = IDLE;
/* Update tag. Remove dirty bit. */
o_cache_tag_wr_en = 1'd1; // Implicitly sets valid (redundant).
o_cache_tag[`CACHE_TAG__TAG] = cache_tag[`VA__CACHE_TAG]; // Preserve.
o_cache_tag_dirty = 1'd0;
o_cache_tag[`CACHE_TAG__PA] = cache_tag[`CACHE_TAG__PA]; // Preserve.
end
end
FETCH_SINGLE: /* Fetch a single cache line */
begin
o_ack = 1'd1;
o_err2 = i_rd || i_wr ? 1'd1 : 1'd0;
/* Generate address */
adr_ctr_nxt = adr_ctr_ff + (o_wb_stb_ff && i_wb_ack);
/* Write to buffer */
buf_nxt[adr_ctr_ff] = i_wb_ack ? i_wb_dat : buf_ff[adr_ctr_ff];
/* Manipulate buffer as needed */
if ( wr )
begin
a = address >> 2;
buf_nxt[a][7:0] = ben[0] ? din[7:0] : buf_nxt[a][7:0];
buf_nxt[a][15:8] = ben[1] ? din[15:8] : buf_nxt[a][15:8];
buf_nxt[a][23:16] = ben[2] ? din[23:16] : buf_nxt[a][23:16];
buf_nxt[a][31:24] = ben[3] ? din[31:24] : buf_nxt[a][31:24];
end
if ( adr_ctr_nxt <= (CACHE_LINE/4) - 1 )
begin
/* Fetch line from memory */
wb_prpr_read(
{phy_addr[31:$clog2(CACHE_LINE)], {$clog2(CACHE_LINE){1'd0}}} + (adr_ctr_nxt * (32/8)),
(adr_ctr_nxt != CACHE_LINE/4 - 1) ? CTI_BURST : CTI_EOB);
end
else
begin:blk12
integer i;
/* Update cache with previous buffers. Here _nxt refers to _ff except for the last one. */
o_cache_line = 0;
for(i=0;i<CACHE_LINE/4;i=i+1)
o_cache_line = o_cache_line | (buf_nxt[i][31:0] << (32 * i));
o_cache_line_ben = {CACHE_LINE{1'd1}};
/* Update tag. Remove dirty and set valid */
o_cache_tag_wr_en = 1'd1; // Implicitly sets valid.
o_cache_tag[`CACHE_TAG__TAG] = address[`VA__CACHE_TAG];
o_cache_tag[`CACHE_TAG__PA] = phy_addr >> $clog2(CACHE_LINE);
o_cache_tag_dirty = !wr ? 1'd0 : 1'd1; // BUG FIX.
/* Move to idle state */
kill_access;
state_nxt = IDLE;
end
end
INVALIDATE: /* Invalidate the cache - Almost Single Cycle */
begin
cache_inv_req_nxt = 1'd1;
cache_clean_req_nxt = 1'd0;
if ( i_cache_inv_done )
begin
cache_inv_req_nxt = 1'd0;
state_nxt = IDLE;
o_cache_inv_done = 1'd1;
end
end
CLEAN: /* Force cache to clean itself */
begin
cache_clean_req_nxt = 1'd1;
cache_inv_req_nxt = 1'd0;
if ( i_cache_clean_done )
begin
cache_clean_req_nxt = 1'd0;
state_nxt = IDLE;
o_cache_clean_done = 1'd1;
end
end
endcase
end
// ----------------------------------------------------------------------------
// Tasks and functions.
// ----------------------------------------------------------------------------
function [31:0] adapt_cache_data (
input [$clog2(CACHE_LINE)-1:0] shift,
input [CACHE_LINE*8-1:0] data
);
reg [31:0] shamt;
begin
shamt = (shift >> 2) * 32;
adapt_cache_data = data >> shamt;
end
endfunction
function [CACHE_LINE-1:0] ben_comp (
input [$clog2(CACHE_LINE)-1:0] shift,
input [3:0] bv
);
reg [31:0] shamt;
begin
shamt = (shift >> 2) * 4;
ben_comp = bv << shamt;
end
endfunction
function [31:0] clean_single_d (
input [CACHE_LINE*8-1:0] cl,
input [31:0] sh
);
reg [31:0] shamt;
begin
shamt = sh * 32;
clean_single_d = cl >> shamt; // Select specific 32-bit.
end
endfunction
/* Function to generate Wishbone read signals. */
task wb_prpr_read;
input [31:0] i_address;
input [2:0] i_cti;
begin
o_wb_cyc_nxt = 1'd1;
o_wb_stb_nxt = 1'd1;
o_wb_wen_nxt = 1'd0;
o_wb_sel_nxt = 4'b1111;
o_wb_adr_nxt = i_address;
o_wb_cti_nxt = i_cti;
o_wb_dat_nxt = 0;
end
endtask
/* Function to generate Wishbone write signals */
task wb_prpr_write;
input [31:0] i_data;
input [31:0] i_address;
input [2:0] i_cti;
input [3:0] i_ben;
begin
o_wb_cyc_nxt = 1'd1;
o_wb_stb_nxt = 1'd1;
o_wb_wen_nxt = 1'd1;
o_wb_sel_nxt = i_ben;
o_wb_adr_nxt = i_address;
o_wb_cti_nxt = i_cti;
o_wb_dat_nxt = i_data;
end
endtask
/* Disables Wishbone */
task kill_access;
begin
o_wb_cyc_nxt = 0;
o_wb_stb_nxt = 0;
o_wb_wen_nxt = 0;
o_wb_adr_nxt = 0;
o_wb_dat_nxt = 0;
o_wb_sel_nxt = 0;
o_wb_cti_nxt = CTI_CLASSIC;
end
endtask
endmodule // zap_cache_fsm
`default_nettype wire
// ----------------------------------------------------------------------------
// END OF FILE
// ----------------------------------------------------------------------------
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
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// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
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// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
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// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////
//
// aurora_64b66b_25p4G
//
//
//
// Description: This is the top level interface module
//
//
///////////////////////////////////////////////////////////////////////////////
// aurora core file
`timescale 1 ps / 1 ps
(* core_generation_info = "aurora_64b66b_25p4G,aurora_64b66b_v11_2_2,{c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTYQ0,c_gt_clock_2=None,c_gt_loc_1=1,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=25.4,c_gt_type=GTYE4,c_qpll=true,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=100.0,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=false,c_user_k=false,flow_mode=None,interface_mode=Framing,dataflow_config=Duplex}" *)
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_core #
(
parameter SIM_GTXRESET_SPEEDUP= 0, // Set to 1 to speed up sim reset
parameter CC_FREQ_FACTOR = 5'd24, // Its highly RECOMMENDED that this value be NOT changed.
// Changing it to a value greater than 24 may result in soft errors.
// User may reduce to a value lower than 24 if channel needs to be
// established in noisy environment
// Min value is 4.
// The current GAP in between two consecutive DO_CC posedge events is 4992 user_clk cycles.
parameter EXAMPLE_SIMULATION = 0
//pragma translate_off
| 1
//pragma translate_on
)
(
// AXI TX Interface
s_axi_tx_tdata,
s_axi_tx_tvalid,
s_axi_tx_tready,
s_axi_tx_tkeep,
s_axi_tx_tlast,
// AXI RX Interface
m_axi_rx_tdata,
m_axi_rx_tvalid,
m_axi_rx_tkeep,
m_axi_rx_tlast,
// GTX Serial I/O
rxp,
rxn,
txp,
txn,
// GTX Reference Clock Interface
gt_refclk1,
// Error Detection Interface
hard_err,
soft_err,
// Status
channel_up,
lane_up,
// System Interface
mmcm_not_locked,
user_clk,
sync_clk,
sysreset_to_core,
gt_rxcdrovrden_in,
power_down,
loopback,
pma_init,
//---{
// I am in AURORA TOP file in 8 series port instance
gt_qpllclk_quad1_in,
gt_qpllrefclk_quad1_in,
gt_qplllock_quad1_in,
gt_qpllrefclklost_quad1,
gt_to_common_qpllreset_out,
//---}
// AXI4-Lite Interface
// Write Address Channel
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
// Write Data Channel
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
// Read Address Channel
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
// Read Data Channel
s_axi_rdata,
s_axi_rvalid,
s_axi_rresp,
s_axi_rready,
init_clk,
link_reset_out,
gt_powergood,
gt_pll_lock,
sys_reset_out,
bufg_gt_clr_out,// connect to clk locked port of clock module
tx_out_clk
);
//Do not modify the below two parameters (Both TX and RX sides should have same value)
localparam SCRAMBLER_SEED = 58'h2AA_AAAA_AAAA_AAAA;
localparam GTY_CRC_NO_ZERO_PAD = 0; //Disable zero padding to the CRC engine
localparam wait_for_fifo_wr_rst_busy_value = 6'd32;
localparam INTER_CB_GAP = 5'd9;
localparam BACKWARD_COMP_MODE1 = 1'b0; //disable check for interCB gap
localparam BACKWARD_COMP_MODE2 = 1'b0; //reduce RXCDR lock time, Block Sync SH max count, disable CDR FSM in wrapper
localparam BACKWARD_COMP_MODE3 = 1'b0; //clear hot-plug counter with any valid btf detected
`define DLY #1
//***********************************Port Declarations*******************************
// TX AXI Interface
input [0:63] s_axi_tx_tdata;
input [0:7] s_axi_tx_tkeep;
input s_axi_tx_tlast;
input s_axi_tx_tvalid;
output s_axi_tx_tready;
// RX AXI Interface
output [0:63] m_axi_rx_tdata;
output [0:7] m_axi_rx_tkeep;
output m_axi_rx_tlast;
output m_axi_rx_tvalid;
// GTX Serial I/O
input rxp;
input rxn;
output txp;
output txn;
// GTX Reference Clock Interface
input gt_refclk1;
// Error Detection Interface
output hard_err;
output soft_err;
// Status
output channel_up;
output lane_up;
// System Interface
input mmcm_not_locked;
input user_clk;
input sync_clk;
input sysreset_to_core;
input gt_rxcdrovrden_in;
input power_down;
input [2:0] loopback;
input pma_init;
output sys_reset_out;
//---{
// for 1st Quad
input gt_qpllclk_quad1_in;
input gt_qpllrefclk_quad1_in;
input gt_qplllock_quad1_in;
input gt_qpllrefclklost_quad1;
// for 2nd Quad
// for 3rd Quad
// for 4th Quad
// for 5th Quad
output gt_to_common_qpllreset_out;
//---}
//-------------------- AXI4-Lite Interface -------------------------------
//-------------------- Write Address Channel --------------------------
input [31:0] s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
//-------------------- Write Data Channel -----------------------------
input [31:0] s_axi_wdata;
input [3:0] s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output s_axi_bvalid;
output [1:0] s_axi_bresp;
input s_axi_bready;
//-------------------- Read Address Channel ---------------------------
input [31:0] s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
//-------------------- Read Data Channel -----------------------------
output [31:0] s_axi_rdata;
output s_axi_rvalid;
output [1:0] s_axi_rresp;
input s_axi_rready;
output gt_pll_lock;
output tx_out_clk;
output bufg_gt_clr_out;// connect to clk locked port of clock module
//input gtwiz_userclk_tx_active_out;// connect to cloking module
output [0:0] gt_powergood;
input init_clk;
output link_reset_out;
//*********************************Wire Declarations**********************************
wire drp_clk;
wire rst_drp;
wire [0:63] tx_d_i2;
wire tx_src_rdy_n_i2;
wire tx_dst_rdy_n_i2;
wire [0:2] tx_rem_i2;
wire [0:2] tx_rem_i3;
wire tx_sof_n_i2;
wire tx_eof_n_i2;
wire [0:63] rx_d_i2;
wire rx_src_rdy_n_i2;
wire [0:2] rx_rem_i2;
wire [0:2] rx_rem_i3;
wire rx_sof_n_i2;
wire rx_eof_n_i2;
wire [0:63] tx_d_i;
wire tx_src_rdy_n_i;
wire tx_dst_rdy_n_i;
wire [0:2] tx_rem_i;
wire tx_sof_n_i;
wire tx_eof_n_i;
wire [0:63] rx_d_i;
wire rx_src_rdy_n_i;
wire [0:2] rx_rem_i;
wire rx_sof_n_i;
wire rx_eof_n_i;
wire ch_bond_done_i;
wire en_chan_sync_i;
wire chan_bond_reset_i;
wire [0:63] tx_data_i;
wire [0:63] rx_data_i;
wire [0:63] tx_pe_data_i;
wire tx_pe_data_v_i;
wire [0:63] rx_pe_data_i;
wire rx_pe_data_v_i;
wire channel_up_rx_if;
wire channel_up_tx_if;
wire system_reset_c;
wire tx_buf_err_i;
wire rx_lossofsync_i;
wire check_polarity_i;
wire rx_neg_i;
wire rx_polarity_i;
wire tx_header_1_i;
wire tx_header_0_i;
wire gt_pll_lock_i;
wire gt_pll_lock_ii;
wire tx_reset_i;
wire hard_err_i;
wire soft_err_i;
wire lane_up_i;
wire raw_tx_out_clk_i;
wire reset_lanes_i;
wire rx_buf_err_i;
wire rx_header_1_i;
wire rx_header_0_i;
wire rx_header_err_i;
wire rx_reset_i;
wire gen_na_idles_i;
wire gen_sep_i;
wire gen_sep7_i;
wire gen_ch_bond_i;
wire got_na_idles_i;
wire got_idles_i;
wire got_cc_i;
wire rxdatavalid_to_ll_i;
wire remote_ready_i;
wire got_cb_i;
wire gen_cc_i;
wire [0:2] sep_nb_i;
wire rx_sep_i;
wire rx_sep7_i;
wire [0:2] rx_sep_nb_i;
//Datavalid signal is routed to Local Link
wire rxdatavalid_i;
wire rxdatavalid_to_lanes_i;
wire txdatavalid_i;
wire txdatavalid_to_ll_i;
wire txdatavalid_symgen_i;
wire drp_clk_i;
wire [9:0] drpaddr_in_i;
wire [15:0] drpdi_in_i;
wire [15:0] drpdo_out_i;
wire drprdy_out_i;
wire drpen_in_i;
wire drpwe_in_i;
wire do_cc_i;
wire link_reset_i;
wire reset;
wire mmcm_not_locked_i;
reg soft_err;
wire sysreset_to_core_sync;
wire pma_init_sync;
//*********************************Main Body of Code**********************************
assign reset = sys_reset_out;
// BYTE SWAP LOGIC
// Connect top level logic
assign channel_up = channel_up_rx_if;
always @(posedge user_clk)
if(reset)
soft_err <= `DLY 1'b0;
else
soft_err <= `DLY (|soft_err_i) & channel_up_tx_if;
// Connect the TXOUTCLK of lane 0 to TX_OUT_CLK
assign tx_out_clk = raw_tx_out_clk_i;
assign gt_pll_lock = gt_pll_lock_i;
assign rxdatavalid_to_lanes_i = |rxdatavalid_i;
aurora_64b66b_25p4G_rst_sync #
(
.c_mtbf_stages (5)
)reset_pb_sync
(
.prmry_in (sysreset_to_core),
.scndry_aclk (user_clk),
.scndry_out (sysreset_to_core_sync)
);
aurora_64b66b_25p4G_rst_sync #
(
.c_mtbf_stages (5)
)gt_reset_sync
(
.prmry_in (pma_init),
.scndry_aclk (init_clk),
.scndry_out (pma_init_sync)
);
wire fsm_resetdone;
// RESET_LOGIC instance
aurora_64b66b_25p4G_RESET_LOGIC core_reset_logic_i
(
.RESET (sysreset_to_core_sync),
.USER_CLK (user_clk),
.INIT_CLK (init_clk),
.FSM_RESETDONE (fsm_resetdone),
.POWER_DOWN (power_down),
.LINK_RESET_IN (link_reset_i),
.SYSTEM_RESET (sys_reset_out)
);
assign link_reset_out = link_reset_i;
//_________________________Instantiate Lane 0______________________________
assign lane_up = lane_up_i;
aurora_64b66b_25p4G_AURORA_LANE aurora_lane_0_i
(
// TX LL
.TX_PE_DATA(tx_pe_data_i[0:63]),
.TX_PE_DATA_V(tx_pe_data_v_i),
.GEN_SEP7(gen_sep7_i),
.GEN_SEP(gen_sep_i),
.SEP_NB(sep_nb_i[0:2]),
.CHANNEL_UP(channel_up_tx_if),
.GEN_CC(gen_cc_i),
// RX LL
.RX_PE_DATA(rx_pe_data_i[0:63]),
.RX_PE_DATA_V(rx_pe_data_v_i),
.RX_SEP7(rx_sep7_i),
.RX_SEP(rx_sep_i),
.RX_SEP_NB(rx_sep_nb_i[0:2]),
// GTX Interface
.RX_DATA(rx_data_i[0:63]),
.RX_HEADER_1(rx_header_1_i),
.RX_HEADER_0(rx_header_0_i),
.RX_HEADER_ERR(rx_header_err_i),
.TX_BUF_ERR(|tx_buf_err_i),
.RX_BUF_ERR(|rx_buf_err_i),
.CHECK_POLARITY(check_polarity_i),
.RX_NEG(rx_neg_i),
.RX_POLARITY(rx_polarity_i),
.RX_RESET(rx_reset_i),
.TX_HEADER_1(tx_header_1_i),
.TX_HEADER_0(tx_header_0_i),
.TX_DATA(tx_data_i[0:63]),
.TX_RESET(tx_reset_i),
.RX_LOSSOFSYNC(rx_lossofsync_i),
// Global Logic Interface
.GEN_NA_IDLE(gen_na_idles_i),
.GEN_CH_BOND(gen_ch_bond_i),
.LANE_UP(lane_up_i),
.HARD_ERR(hard_err_i),
.SOFT_ERR(soft_err_i),
.GOT_NA_IDLE(got_na_idles_i),
.RXDATAVALID_TO_LL(rxdatavalid_to_ll_i),
.GOT_CC(got_cc_i),
.REMOTE_READY(remote_ready_i),
.GOT_CB(got_cb_i),
.GOT_IDLE(got_idles_i),
// System Interface
.USER_CLK(user_clk),
.RESET_LANES(reset_lanes_i),
.RESET(reset),
.TXDATAVALID_SYMGEN_IN(txdatavalid_symgen_i),
.RXDATAVALID_IN(rxdatavalid_to_lanes_i)
);
//_________________________Instantiate GTX Wrapper ______________________________
aurora_64b66b_25p4G_WRAPPER #
(
.INTER_CB_GAP (INTER_CB_GAP),
.SCRAMBLER_SEED(SCRAMBLER_SEED),
.wait_for_fifo_wr_rst_busy_value (wait_for_fifo_wr_rst_busy_value),
.BACKWARD_COMP_MODE1 (BACKWARD_COMP_MODE1),
.BACKWARD_COMP_MODE2 (BACKWARD_COMP_MODE2),
.BACKWARD_COMP_MODE3 (BACKWARD_COMP_MODE3),
.EXAMPLE_SIMULATION (EXAMPLE_SIMULATION)
)
aurora_64b66b_25p4G_wrapper_i
(
//----------- GT POWERGOOD STATUS Port -----------
.gt_powergood (gt_powergood),
// Aurora Lane Interface
.CHECK_POLARITY_IN (check_polarity_i),
.RX_NEG_OUT (rx_neg_i),
.RXPOLARITY_IN (rx_polarity_i),
.RXRESET_IN (rx_reset_i),
.TXDATA_IN (tx_data_i[0:63]),
.TXRESET_IN (tx_reset_i),
.RXDATA_OUT (rx_data_i[0:63]),
.RXBUFERR_OUT (rx_buf_err_i),
.TXBUFERR_OUT (tx_buf_err_i),
// Global Logic Interface
.CHBONDDONE_OUT (ch_bond_done_i),
.ENCHANSYNC_IN (en_chan_sync_i),
// Serial IO
.RX1N_IN (rxn),
.RX1P_IN (rxp),
.TX1N_OUT (txn),
.TX1P_OUT (txp),
//-----------
// Clocks and Clock Status
.TXUSRCLK_IN (sync_clk),
.TXUSRCLK2_IN (user_clk),
.RXLOSSOFSYNC_OUT (rx_lossofsync_i),
.TXOUTCLK1_OUT (raw_tx_out_clk_i),
//-----------
.PLLLKDET_OUT (gt_pll_lock_i),
//-----------
// System Interface
.GTXRESET_IN (pma_init_sync),
//-----------
.CHAN_BOND_RESET (chan_bond_reset_i),
.LOOPBACK_IN (loopback),
.POWERDOWN_IN (power_down),
.REFCLK1_IN (gt_refclk1),
//---{
/// Assumption: GT common is in the Ultrascale GT if CPLL is chosen
.gt_qpllclk_quad1_in (gt_qpllclk_quad1_in ),
.gt_qpllrefclk_quad1_in (gt_qpllrefclk_quad1_in ),
.gt_qplllock_quad1_in (gt_qplllock_quad1_in ),
.gt_qpllrefclklost_quad1 (gt_qpllrefclklost_quad1 ),
.gt_to_common_qpllreset_out (gt_to_common_qpllreset_out ),
//---}
.TXHEADER_IN({tx_header_1_i,tx_header_0_i}),
.RXHEADER_OUT({rx_header_1_i,rx_header_0_i}),
.RXHEADER_OUT_ERR({rx_header_err_i}),
.RESET(reset),
.GT_RXCDROVRDEN_IN(gt_rxcdrovrden_in),
.FSM_RESETDONE(fsm_resetdone),
.RXDATAVALID_OUT(rxdatavalid_i),
.TXDATAVALID_OUT(txdatavalid_i),
//---------------------- GT DRP Ports ----------------------
.DRP_CLK_IN (init_clk),
.gt0_drpaddr(drpaddr_in_i),
.gt0_drpdi(drpdi_in_i),
.gt0_drpdo(drpdo_out_i),
.gt0_drprdy(drprdy_out_i),
.gt0_drpen(drpen_in_i),
.gt0_drpwe(drpwe_in_i),
.INIT_CLK (init_clk),
.LINK_RESET_OUT (link_reset_i),
.USER_CLK (user_clk),
.bufg_gt_clr_out (bufg_gt_clr_out),// connect to clk locked port of clock module
.gtwiz_userclk_tx_active_out (mmcm_not_locked_i),// connect to clocking module//
.TXDATAVALID_SYMGEN_OUT (txdatavalid_symgen_i),
//-----------
.RXUSRCLK2_IN (user_clk)
);
assign mmcm_not_locked_i = !mmcm_not_locked;
//_____________________________ AXI DRP SHIM _______________________________
aurora_64b66b_25p4G_AXI_TO_DRP #
(
.DATA_WIDTH(32)
)
axi_to_drp_i
(
// AXI4-Lite input signals
.S_AXI_AWADDR(s_axi_awaddr),
.S_AXI_AWVALID(s_axi_awvalid),
.S_AXI_AWREADY(s_axi_awready),
.S_AXI_WDATA(s_axi_wdata),
.S_AXI_WSTRB(s_axi_wstrb),
.S_AXI_WVALID(s_axi_wvalid),
.S_AXI_WREADY(s_axi_wready),
.S_AXI_BVALID(s_axi_bvalid),
.S_AXI_BRESP(s_axi_bresp),
.S_AXI_BREADY(s_axi_bready),
.S_AXI_ARADDR(s_axi_araddr),
.S_AXI_ARVALID(s_axi_arvalid),
.S_AXI_ARREADY(s_axi_arready),
.S_AXI_RDATA(s_axi_rdata),
.S_AXI_RVALID(s_axi_rvalid),
.S_AXI_RRESP(s_axi_rresp),
.S_AXI_RREADY(s_axi_rready),
// DRP Interface
.DRPADDR_IN(drpaddr_in_i),
.DRPDI_IN(drpdi_in_i),
.DRPDO_OUT(drpdo_out_i),
.DRPRDY_OUT(drprdy_out_i),
.DRPEN_IN(drpen_in_i),
.DRPWE_IN(drpwe_in_i),
// System Interface
.DRP_CLK_IN (init_clk),
.RESET(rst_drp)
);
//__________Instantiate Global Logic to combine Lanes into a Channel______
aurora_64b66b_25p4G_GLOBAL_LOGIC #
(
.INTER_CB_GAP(INTER_CB_GAP)
) global_logic_i
(
//GTX Interface
.CH_BOND_DONE(ch_bond_done_i),
.EN_CHAN_SYNC(en_chan_sync_i),
.CHAN_BOND_RESET(chan_bond_reset_i),
// Aurora Lane Interface
.LANE_UP(lane_up_i),
.HARD_ERR(hard_err_i),
.GEN_NA_IDLES(gen_na_idles_i),
.GEN_CH_BOND(gen_ch_bond_i),
.RESET_LANES(reset_lanes_i),
.GOT_NA_IDLES(got_na_idles_i),
.GOT_CCS(got_cc_i),
.REMOTE_READY(remote_ready_i),
.GOT_CBS(got_cb_i),
.GOT_IDLES(got_idles_i),
// System Interface
.USER_CLK(user_clk),
.RESET(reset),
.CHANNEL_UP_RX_IF(channel_up_rx_if),
.CHANNEL_UP_TX_IF(channel_up_tx_if),
.CHANNEL_HARD_ERR(hard_err),
.TXDATAVALID_IN(txdatavalid_i)
);
//_____________________________ TX AXI SHIM _______________________________
// Converts input AXI4-Stream signals to LocalLink
// TX LOCALLINK
aurora_64b66b_25p4G_TX_LL tx_ll_i
(
// S_AXI_TX Interface
.s_axi_tx_tdata (s_axi_tx_tdata),
.s_axi_tx_tkeep (s_axi_tx_tkeep),
.s_axi_tx_tlast (s_axi_tx_tlast),
.s_axi_tx_tvalid (s_axi_tx_tvalid),
.s_axi_tx_tready (s_axi_tx_tready),
// Clock Compenstaion Interface
.DO_CC(do_cc_i),
// Global Logic Interface
.CHANNEL_UP(channel_up_tx_if),
// Aurora Lane Interface
.GEN_SEP(gen_sep_i),
.GEN_SEP7(gen_sep7_i),
.SEP_NB(sep_nb_i),
.TX_PE_DATA_V(tx_pe_data_v_i),
.TX_PE_DATA(tx_pe_data_i),
.GEN_CC(gen_cc_i),
// System Interface
.USER_CLK(user_clk),
.TXDATAVALID_IN(txdatavalid_i),
.RESET(reset_lanes_i)
);
//_____________________________ RX AXI SHIM _______________________________
// RX LOCALLINK
aurora_64b66b_25p4G_RX_LL rx_ll_i
(
//AXI4-Stream Interface
.m_axi_rx_tdata (m_axi_rx_tdata),
.m_axi_rx_tkeep (m_axi_rx_tkeep),
.m_axi_rx_tvalid (m_axi_rx_tvalid),
.m_axi_rx_tlast (m_axi_rx_tlast),
// Aurora Lane Interface
.RX_PE_DATA(rx_pe_data_i),
.RX_PE_DATA_V(rx_pe_data_v_i),
.RX_SEP(rx_sep_i),
.RX_SEP7(rx_sep7_i),
.RX_SEP_NB(rx_sep_nb_i),
.RXDATAVALID_TO_LL(rxdatavalid_to_ll_i),
.RX_CC(got_cc_i),
.RX_IDLE(got_idles_i),
// Global Logic Interface
.CHANNEL_UP(channel_up_rx_if),
// System Interface
.USER_CLK(user_clk),
.RESET(reset_lanes_i)
);
assign rst_drp = pma_init_sync;
// Standard CC Module
aurora_64b66b_25p4G_STANDARD_CC_MODULE #
(
.CC_FREQ_FACTOR (CC_FREQ_FACTOR)
)
standard_cc_module_i
(
.DO_CC (do_cc_i),
.USER_CLK (user_clk),
.CHANNEL_UP (channel_up_rx_if)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:43:58 11/19/2015
// Design Name:
// Module Name: IF_ID
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module IF_ID(
input clock,
input reset,
input debugEnable,
input debugReset,
input notEnable,
input clear,
input[31:0] instruction,
input[7:0] pcNext,
output reg[31:0] instructionOut,
output reg[7:0] pcNextOut
);
always @(negedge clock,posedge reset)begin
if(reset)begin
instructionOut<=0;
pcNextOut<=0;
end
else if(debugReset)begin
instructionOut<=0;
pcNextOut<=0;
end
else if(~notEnable && debugEnable)begin
if(clear)begin
instructionOut<=0;
end
else begin
instructionOut<=instruction;
end
pcNextOut<=pcNext;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_ncio_makq_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "jbi.h"
module jbi_ncio_makq_ctl(/*AUTOARG*/
// Outputs
makq_csn_wr, makq_waddr, makq_raddr, ncio_mondo_req, ncio_mondo_ack,
ncio_mondo_agnt_id, ncio_mondo_cpu_id, ncio_makq_level,
// Inputs
clk, rst_l, makq_push, makq_nack, iob_jbi_mondo_ack_ff,
iob_jbi_mondo_nack_ff, makq_rdata, mout_mondo_pop
);
input clk;
input rst_l;
// Mondo Request Queue Interface
input makq_push;
input makq_nack;
input iob_jbi_mondo_ack_ff;
input iob_jbi_mondo_nack_ff;
// Mondo ID Queue Interface
input [`JBI_MAKQ_WIDTH-1:0] makq_rdata;
output makq_csn_wr;
output [`JBI_MAKQ_ADDR_WIDTH-1:0] makq_waddr;
output [`JBI_MAKQ_ADDR_WIDTH-1:0] makq_raddr;
// Memory Out (mout) Interface
input mout_mondo_pop;
output ncio_mondo_req;
output ncio_mondo_ack; // 1=ack; 0=nack
output [`JBI_AD_INT_AGTID_WIDTH-1:0] ncio_mondo_agnt_id;
output [`JBI_AD_INT_CPUID_WIDTH-1:0] ncio_mondo_cpu_id;
output [`JBI_MAKQ_ADDR_WIDTH:0] ncio_makq_level;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire makq_csn_wr;
wire [`JBI_MAKQ_ADDR_WIDTH-1:0] makq_waddr;
wire [`JBI_MAKQ_ADDR_WIDTH-1:0] makq_raddr;
wire ncio_mondo_req;
wire ncio_mondo_ack; // 1=ack; 0=nack
wire [`JBI_AD_INT_AGTID_WIDTH-1:0] ncio_mondo_agnt_id;
wire [`JBI_AD_INT_CPUID_WIDTH-1:0] ncio_mondo_cpu_id;
wire [`JBI_MAKQ_ADDR_WIDTH:0] ncio_makq_level;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
wire [`JBI_MAKQ_ADDR_WIDTH:0] id_wptr;
wire [`JBI_MAKQ_ADDR_WIDTH:0] ack_wptr;
wire [`JBI_MAKQ_DEPTH-1:0] ack;
wire [`JBI_MAKQ_ADDR_WIDTH:0] rptr;
reg [`JBI_MAKQ_ADDR_WIDTH:0] next_id_wptr;
reg [`JBI_MAKQ_ADDR_WIDTH:0] next_ack_wptr;
reg [`JBI_MAKQ_DEPTH-1:0] next_ack;
reg [`JBI_MAKQ_ADDR_WIDTH:0] next_rptr;
reg [`JBI_MAKQ_ADDR_WIDTH:0] next_ncio_makq_level;
wire ack_push;
wire makq_empty;
//
// Code start here
//
//*******************************************************************************
// Push
//*******************************************************************************
//-------------------
// Push ID
//-------------------
always @ ( /*AUTOSENSE*/id_wptr or makq_push) begin
if (makq_push)
next_id_wptr = id_wptr + 1'b1;
else
next_id_wptr = id_wptr;
end
assign makq_csn_wr = ~makq_push;
assign makq_waddr = id_wptr[`JBI_MAKQ_ADDR_WIDTH-1:0];
//-------------------
// Push Ack/Nack
//-------------------
assign ack_push = iob_jbi_mondo_ack_ff
| iob_jbi_mondo_nack_ff
| (makq_push & makq_nack); // mondo with par error not forwarded to cmp but nacked on jbus
always @ ( /*AUTOSENSE*/ack or ack_push or ack_wptr
or iob_jbi_mondo_ack_ff or makq_nack or makq_push) begin
next_ack = ack;
if (ack_push)
next_ack[ack_wptr[`JBI_MAKQ_ADDR_WIDTH-1:0]] = iob_jbi_mondo_ack_ff & ~(makq_push & makq_nack);
end
always @ ( /*AUTOSENSE*/ack_push or ack_wptr) begin
if (ack_push)
next_ack_wptr = ack_wptr + 1'b1;
else
next_ack_wptr = ack_wptr;
end
//*******************************************************************************
// Pop
//*******************************************************************************
always @ ( /*AUTOSENSE*/mout_mondo_pop or rptr) begin
if (mout_mondo_pop)
next_rptr = rptr + 1'b1;
else
next_rptr = rptr;
end
assign makq_empty = rptr == ack_wptr;
assign makq_raddr = rptr[`JBI_MAKQ_ADDR_WIDTH-1:0];
//assign makq_csn_rd = next_rptr == id_wptr;
assign ncio_mondo_req = ~makq_empty;
assign ncio_mondo_ack = ack[rptr[`JBI_MAKQ_ADDR_WIDTH-1:0]];
assign ncio_mondo_agnt_id = makq_rdata[`JBI_MAKQ_AGTID_HI:`JBI_MAKQ_AGTID_LO];
assign ncio_mondo_cpu_id = makq_rdata[`JBI_MAKQ_CPUID_HI:`JBI_MAKQ_CPUID_LO];
always @ ( /*AUTOSENSE*/ack_push or mout_mondo_pop or ncio_makq_level) begin
case ({ack_push, mout_mondo_pop})
2'b00,
2'b11: next_ncio_makq_level = ncio_makq_level;
2'b01: next_ncio_makq_level = ncio_makq_level - 1'b1;
2'b10: next_ncio_makq_level = ncio_makq_level + 1'b1;
default: next_ncio_makq_level = {`JBI_MAKQ_ADDR_WIDTH+1{1'bx}};
endcase
end
//*******************************************************************************
// DFFRL Instantiations
//*******************************************************************************
dffrl_ns #(`JBI_MAKQ_ADDR_WIDTH+1) u_dffrl_id_wptr
(.din(next_id_wptr),
.clk(clk),
.rst_l(rst_l),
.q(id_wptr)
);
dffrl_ns #(`JBI_MAKQ_ADDR_WIDTH+1) u_dffrl_ack_wptr
(.din(next_ack_wptr),
.clk(clk),
.rst_l(rst_l),
.q(ack_wptr)
);
dffrl_ns #(`JBI_MAKQ_ADDR_WIDTH+1) u_dffrl_rptr
(.din(next_rptr),
.clk(clk),
.rst_l(rst_l),
.q(rptr)
);
dffrl_ns #(`JBI_MAKQ_DEPTH) u_dffrl_ack
(.din(next_ack),
.clk(clk),
.rst_l(rst_l),
.q(ack)
);
dffrl_ns #(`JBI_MAKQ_ADDR_WIDTH+1) u_dffrl_ncio_makq_level
(.din(next_ncio_makq_level),
.clk(clk),
.rst_l(rst_l),
.q(ncio_makq_level)
);
//*******************************************************************************
// Rule Checks
//*******************************************************************************
//synopsys translate_off
wire rc_makq_empty = rptr == ack_wptr;
wire rc_makq_full = ack_wptr[`JBI_MAKQ_ADDR_WIDTH] != rptr[`JBI_MAKQ_ADDR_WIDTH]
& ack_wptr[`JBI_MAKQ_ADDR_WIDTH-1:0] == rptr[`JBI_MAKQ_ADDR_WIDTH-1:0];
always @ ( /*AUTOSENSE*/makq_push or rc_makq_full) begin
@clk;
if (rc_makq_full && makq_push)
$dispmon ("jbi_ncio_makq_ctl", 49,"%d %m: ERROR - MAKQ overflow!", $time);
end
always @ ( /*AUTOSENSE*/mout_mondo_pop or rc_makq_empty) begin
@clk;
if (rc_makq_empty && mout_mondo_pop)
$dispmon ("jbi_ncio_makq_ctl", 49,"%d %m: ERROR - MAKQ underflow!", $time);
end
//synopsys translate_on
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
// vim: ts=4 sw=4 noexpandtab
/*
* pyprofibus FPGA PHY
*
* Copyright (c) 2019 Michael Buesch <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
`include "profibus_phy_mod.v"
`include "led_blink_mod.v"
`ifdef DEBUG
`define DEBUGOUT output
`else
`define DEBUGOUT input
`endif
module common_main_module #(
parameter CLK_HZ = 0,
) (
input clk,
input n_reset,
/* SPI bus */
input spi_mosi,
inout spi_miso,
input spi_sck,
input spi_ss,
/* Profibus and status */
input pb_rx,
output pb_rx_error,
output pb_rx_irq_edge,
output pb_rx_irq_level,
output pb_tx,
output pb_tx_active,
output pb_tx_error,
/* Status and debugging */
output led,
`ifdef DEBUG
output debug,
`endif
);
wire miso;
wire sck;
wire ss;
wire rx_error;
wire rx_irq_edge;
wire rx_irq_level;
wire tx;
wire tx_error;
wire rx_active;
wire tx_active;
`ifdef DEBUG
wire debug_w;
`endif
profibus_phy pb(
.clk(clk),
.n_reset(n_reset),
.rx_irq_edge(rx_irq_edge),
.rx_irq_level(rx_irq_level),
.mosi(spi_mosi),
.miso(miso),
.sck(spi_sck),
.ss(spi_ss),
.rx(pb_rx),
.rx_active(rx_active),
.rx_error(rx_error),
.tx(tx),
.tx_active(tx_active),
.tx_error(tx_error),
`ifdef DEBUG
.debug(debug_w),
`endif
);
bufif0(spi_miso, miso, spi_ss);
bufif0(pb_rx_error, rx_error, 0);
bufif0(pb_rx_irq_edge, rx_irq_edge, 0);
bufif0(pb_rx_irq_level, rx_irq_level, 0);
bufif0(pb_tx, tx, 0);
bufif0(pb_tx_active, tx_active, 0);
bufif0(pb_tx_error, tx_error, 0);
`ifdef DEBUG
bufif0(debug, debug_w, 0);
`endif
wire led_w;
wire led_enable;
assign led_enable = tx_active | rx_active;
led_blink #(
.BLINK_ON_CLKS(CLK_HZ / 10),
.BLINK_OFF_CLKS(CLK_HZ / 35),
) led_blink (
.clk(clk),
.n_reset(n_reset),
.enable(led_enable),
.led(led_w),
);
bufif0(led, led_w, 0);
endmodule
`ifdef TARGET_TINYFPGA_BX
`include "pll_mod.v"
/* TinyFPGA BX:
* +---------------+
* |P|GND Vin|P|
* not reset |O|1 GND|P|
* debug |D|2 3.3V|P|
* |N|3 T 24|N|
* |N|4 i 23|N|
* |N|5 n 22|N|
* |N|6 y 21|N|
* |N|7 F 20|O| PB RX IRQ level
* |N|8 P 19|O| PB RX IRQ edge
* |N|9 G 18|O| PB TX error
* SPI MISO |O|10 A 17|O| PB RX error
* SPI MOSI |I|11 16|O| PB TX active
* SPI SCK |I|12 B 15|O| PB UART TX
* SPI SS |I|13 X 14|I| PB UART RX
* +---------------+
* P = power
* I = input
* O = output
* D = debug output. Only if DEBUG is enabled. Otherwise N.
* N = not connected
*/
module top_module(
input CLK,
input SPI_SS,
input SPI_SCK,
input SPI_IO0,
input SPI_IO1,
input SPI_IO2,
input SPI_IO3,
input USBP,
input USBN,
output USBPU,
output LED,
input PIN_1,
`DEBUGOUT PIN_2,
input PIN_3,
input PIN_4,
input PIN_5,
input PIN_6,
input PIN_7,
input PIN_8,
input PIN_9,
inout PIN_10,
input PIN_11,
input PIN_12,
input PIN_13,
input PIN_14,
output PIN_15,
output PIN_16,
output PIN_17,
output PIN_18,
output PIN_19,
output PIN_20,
input PIN_21,
input PIN_22,
input PIN_23,
input PIN_24,
input PIN_25,
input PIN_26,
input PIN_27,
input PIN_28,
input PIN_29,
input PIN_30,
input PIN_31,
);
wire pll_clk_out;
wire pll_locked;
pll_module pll(
.clock_in(CLK),
.clock_out(pll_clk_out),
.locked(pll_locked),
);
wire n_reset;
assign n_reset = PIN_1 & pll_locked;
common_main_module #(
.CLK_HZ(`PLL_HZ),
) common (
.clk(pll_clk_out),
.n_reset(n_reset),
.spi_mosi(PIN_11),
.spi_miso(PIN_10),
.spi_sck(PIN_12),
.spi_ss(PIN_13),
.pb_rx(PIN_14),
.pb_rx_error(PIN_17),
.pb_rx_irq_edge(PIN_19),
.pb_rx_irq_level(PIN_20),
.pb_tx(PIN_15),
.pb_tx_active(PIN_16),
.pb_tx_error(PIN_18),
.led(LED),
`ifdef DEBUG
.debug(PIN_2),
`endif
);
assign USBPU = 0; /* Disable USB */
endmodule
`else /* TARGET */
`ERROR____TARGET_is_not_known
`endif /* TARGET */
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module unused_reg
#(
parameter REG_ADDR_WIDTH = 5
)
(
// Register interface signals
input reg_req,
output reg_ack,
input reg_rd_wr_L,
input [REG_ADDR_WIDTH - 1:0] reg_addr,
output [`CPCI_NF2_DATA_WIDTH - 1:0] reg_rd_data,
input [`CPCI_NF2_DATA_WIDTH - 1:0] reg_wr_data,
//
input clk,
input reset
);
reg reg_req_d1;
assign reg_rd_data = 'h dead_beef;
// Only generate an ack on a new request
assign reg_ack = reg_req && !reg_req_d1;
always @(posedge clk)
begin
reg_req_d1 <= reg_req;
end
endmodule // unused_reg
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 61: 0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [ 61: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 61: 0] entry_0;
reg [ 61: 0] entry_1;
wire full;
reg rd_address;
reg [ 61: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_sdram (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset_n,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 31: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 12: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 31: 0] zs_dq;
output [ 3: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 24: 0] az_addr;
input [ 3: 0] az_be_n;
input az_cs;
input [ 31: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset_n;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 24: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 31: 0] active_data;
reg [ 3: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 9: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 24: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 31: 0] f_data;
wire [ 3: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 61: 0] fifo_read_data;
reg [ 12: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 2: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 12: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 2: 0] m_count;
reg [ 31: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 3: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 2: 0] rd_valid;
reg [ 13: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 31: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 12: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 31: 0] zs_dq;
wire [ 3: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{32{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
usb_system_sdram_input_efifo_module the_usb_system_sdram_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset_n (reset_n),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 4'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[24],f_addr[10]};
// Refresh/init counter.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_counter <= 10000;
else if (refresh_counter == 0)
refresh_counter <= 390;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {13{1'b1}};
i_count <= {3{1'b0}};
end
else
begin
i_addr <= {13{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 0;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 3;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{3{1'b0}},1'b0,2'b00,3'h3,4'h0};
i_count <= 4;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[24],active_addr[10]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[23 : 11]} == {f_addr[23 : 11]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {3{1'b0}},f_addr[9 : 0] } : { {3{1'b0}},active_addr[9 : 0] };
// **** Main FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 13'b0000000000000;
m_data <= 32'b00000000000000000000000000000000;
m_dqm <= 4'b0000;
m_count <= 3'b000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 0;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[23 : 11];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 1;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 0;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {13{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 3;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b000100000;
m_next <= 9'b000000001;
m_count <= 1;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_valid <= {3{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {2{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[2];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
initial
begin
$write("\n");
$write("This reference design requires a vendor simulation model.\n");
$write("To simulate accesses to SDRAM, you must:\n");
$write(" - Download the vendor model\n");
$write(" - Install the model in the system_sim directory\n");
$write(" - `include the vendor model in the the top-level system file,\n");
$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");
$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");
$write(" (because this simulation is zero-delay based)\n");
$write("\n");
end
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
`timescale 1ns/1ps
module tb_Oper_Start_In (); /* this is automatically generated */
parameter PERIOD = 10;
reg clk;
reg rst;
// clock
initial begin
clk = 0;
forever #5 clk = ~clk;
end
// reset
initial begin
rst = 0;
#6
rst = 1;
repeat (6) @(posedge clk);
rst = 0;
end
// (*NOTE*) replace reset, clock
parameter W = 32;
reg rst;
reg load_a_i;
reg load_b_i;
reg add_subt_i;
reg [W-1:0] Data_X_i;
reg [W-1:0] Data_Y_i;
wire [W-2:0] DMP_o;
wire [W-2:0] DmP_o;
wire zero_flag_o;
wire real_op_o;
wire sign_final_result_o;
`ifdef OPER1
Oper_Start_In #(
.W(W)
) inst_Oper_Start_In (
.clk (clk),
.rst (rst),
.load_a_i (load_a_i),
.load_b_i (load_b_i),
.add_subt_i (add_subt_i),
.Data_X_i (Data_X_i),
.Data_Y_i (Data_Y_i),
.DMP_o (DMP_o),
.DmP_o (DmP_o),
.zero_flag_o (zero_flag_o),
.real_op_o (real_op_o),
.sign_final_result_o (sign_final_result_o)
);
`endif
Oper_Start_In_2_W32 inst_Oper_Start_In (
.clk (clk),
.rst (rst),
.load_b_i (load_b_i),
.intAS (add_subt_i),
.intDX (Data_X_i),
.intDY (Data_Y_i),
.DMP_o (DMP_o),
.DmP_o (DmP_o),
.zero_flag_o (zero_flag_o),
.real_op_o (real_op_o),
.sign_final_result_o (sign_final_result_o)
);
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer Cont_CLK;
integer Recept;
always begin
#(3*PERIOD/2)
@(posedge clk) begin
load_a_i = 1;
load_b_i = 0;
end
@(posedge clk) begin
Data_X_i = Array_IN[contador];
Data_Y_i = Array_IN_2[contador];
contador = contador + 1;
load_a_i = 1;
load_b_i = 1;
end
@(posedge clk) begin
load_a_i = 0;
load_b_i = 0;
end
#(3*PERIOD/2);
end
initial begin
$readmemh("Hexadecimal_A.txt", Array_IN);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
end
initial begin
load_a_i = 1;
load_b_i = 1;
add_subt_i = 0;
contador = 0;
repeat(5240)@(posedge clk);
$finish;
end
endmodule
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- --
// -- This is the top module of the ZAP processor. It contains instances of --
// -- processor core and the memory management units. I and D WB busses --
// -- are provided. --
// -- --
// ----------------------------------------------------------------------------
`default_nettype none
module zap_top #(
// -----------------------------------
// BP entries, FIFO depths
// -----------------------------------
parameter BP_ENTRIES = 1024, // Predictor depth.
parameter FIFO_DEPTH = 4, // FIFO depth.
parameter STORE_BUFFER_DEPTH = 16, // Depth of the store buffer.
// ----------------------------------
// Data MMU/Cache configuration.
// ----------------------------------
parameter [31:0] DATA_SECTION_TLB_ENTRIES = 32'd4, // Section TLB entries.
parameter [31:0] DATA_LPAGE_TLB_ENTRIES = 32'd8, // Large page TLB entries.
parameter [31:0] DATA_SPAGE_TLB_ENTRIES = 32'd16, // Small page TLB entries.
parameter [31:0] DATA_FPAGE_TLB_ENTRIES = 32'd32, // Tiny page TLB entries.
parameter [31:0] DATA_CACHE_SIZE = 32'd4096, // Cache size in bytes.
parameter [31:0] DATA_CACHE_LINE = 32'd64, // Cache line size in bytes.
// ----------------------------------
// Code MMU/Cache configuration.
// ----------------------------------
parameter [31:0] CODE_SECTION_TLB_ENTRIES = 32'd4, // Section TLB entries.
parameter [31:0] CODE_LPAGE_TLB_ENTRIES = 32'd8, // Large page TLB entries.
parameter [31:0] CODE_SPAGE_TLB_ENTRIES = 32'd16, // Small page TLB entries.
parameter [31:0] CODE_FPAGE_TLB_ENTRIES = 32'd32, // Fine page TLB entries.
parameter [31:0] CODE_CACHE_SIZE = 32'd4096, // Cache size in bytes.
parameter [31:0] CODE_CACHE_LINE = 32'd64 // Ccahe line size in bytes.
)(
// --------------------------------------
// Clock and reset
// --------------------------------------
input wire i_clk,
input wire i_reset,
// ---------------------------------------
// Interrupts.
// Both of them are active high and level
// trigerred.
// ---------------------------------------
input wire i_irq,
input wire i_fiq,
// ---------------------
// Wishbone interface.
// ---------------------
output wire o_wb_cyc,
output wire o_wb_stb,
output wire [31:0] o_wb_adr,
output wire o_wb_we,
output wire [31:0] o_wb_dat,
output wire [3:0] o_wb_sel,
output wire [2:0] o_wb_cti,
output wire [1:0] o_wb_bte,
input wire i_wb_ack,
input wire [31:0] i_wb_dat
);
assign o_wb_bte = 2'b00; // Linear Burst.
localparam COMPRESSED_EN = 1'd1;
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
wire wb_cyc, wb_stb, wb_we;
wire [3:0] wb_sel;
wire [31:0] wb_dat, wb_idat;
wire [31:0] wb_adr;
wire [2:0] wb_cti;
wire wb_ack;
reg reset;
// Synchronous reset signal flopped.
always @ (posedge i_clk)
reset <= i_reset;
wire cpu_mmu_en;
wire [31:0] cpu_cpsr;
wire cpu_mem_translate;
wire [31:0] cpu_daddr, cpu_daddr_nxt;
wire [31:0] cpu_iaddr, cpu_iaddr_nxt;
wire [7:0] dc_fsr;
wire [31:0] dc_far;
wire cpu_dc_en, cpu_ic_en;
wire [1:0] cpu_sr;
wire [7:0] cpu_pid;
wire [31:0] cpu_baddr, cpu_dac_reg;
wire cpu_dc_inv, cpu_ic_inv;
wire cpu_dc_clean, cpu_ic_clean;
wire dc_inv_done, ic_inv_done, dc_clean_done, ic_clean_done;
wire cpu_dtlb_inv, cpu_itlb_inv;
wire data_ack, data_err, instr_ack, instr_err;
wire [31:0] ic_data, dc_data, cpu_dc_dat;
wire cpu_instr_stb;
wire cpu_dc_we, cpu_dc_stb;
wire [3:0] cpu_dc_sel;
wire c_wb_stb;
wire c_wb_cyc;
wire c_wb_wen;
wire [3:0] c_wb_sel;
wire [31:0] c_wb_dat;
wire [31:0] c_wb_adr;
wire [2:0] c_wb_cti;
wire c_wb_ack;
wire d_wb_stb;
wire d_wb_cyc;
wire d_wb_wen;
wire [3:0] d_wb_sel;
wire [31:0] d_wb_dat;
wire [31:0] d_wb_adr;
wire [2:0] d_wb_cti;
wire d_wb_ack;
wire icache_err2, dcache_err2;
zap_core #(
.BP_ENTRIES(BP_ENTRIES),
.FIFO_DEPTH(FIFO_DEPTH)
) u_zap_core
(
// Clock and reset.
.i_clk (i_clk),
.i_reset (reset),
// Code related.
.o_instr_wb_adr (cpu_iaddr),
.o_instr_wb_cyc (),
.o_instr_wb_stb (cpu_instr_stb),
.o_instr_wb_we (),
.o_instr_wb_sel (),
// Code related.
.i_instr_wb_dat (ic_data),
.i_instr_wb_ack (instr_ack),
.i_instr_wb_err (instr_err),
// Data related.
.o_data_wb_we (cpu_dc_we),
.o_data_wb_adr (cpu_daddr),
.o_data_wb_sel (cpu_dc_sel),
.o_data_wb_dat (cpu_dc_dat),
.o_data_wb_cyc (),
.o_data_wb_stb (cpu_dc_stb),
// Data related.
.i_data_wb_ack (data_ack),
.i_data_wb_err (data_err),
.i_data_wb_dat (dc_data),
// Interrupts.
.i_fiq (i_fiq),
.i_irq (i_irq),
// MMU/cache is present.
.o_mem_translate (cpu_mem_translate),
.i_fsr ({24'd0,dc_fsr}),
.i_far (dc_far),
.o_dac (cpu_dac_reg),
.o_baddr (cpu_baddr),
.o_mmu_en (cpu_mmu_en),
.o_sr (cpu_sr),
.o_pid (cpu_pid),
.o_dcache_inv (cpu_dc_inv),
.o_icache_inv (cpu_ic_inv),
.o_dcache_clean (cpu_dc_clean),
.o_icache_clean (cpu_ic_clean),
.o_dtlb_inv (cpu_dtlb_inv),
.o_itlb_inv (cpu_itlb_inv),
.i_dcache_inv_done (dc_inv_done),
.i_icache_inv_done (ic_inv_done),
.i_dcache_clean_done (dc_clean_done),
.i_icache_clean_done (ic_clean_done),
.o_dcache_en (cpu_dc_en),
.o_icache_en (cpu_ic_en),
.i_icache_err2 (icache_err2),
.i_dcache_err2 (dcache_err2),
// Data IF nxt.
.o_data_wb_adr_nxt (cpu_daddr_nxt), // Data addr nxt. Used to drive address of data tag RAM.
.o_data_wb_we_nxt (),
.o_data_wb_cyc_nxt (),
.o_data_wb_stb_nxt (),
.o_data_wb_dat_nxt (),
.o_data_wb_sel_nxt (),
// Code access prpr.
.o_instr_wb_adr_nxt (cpu_iaddr_nxt), // PC addr nxt. Drives read address of code tag RAM.
// CPSR
.o_cpsr (cpu_cpsr)
);
zap_cache #(
.CACHE_SIZE(DATA_CACHE_SIZE),
.SPAGE_TLB_ENTRIES(DATA_SPAGE_TLB_ENTRIES),
.LPAGE_TLB_ENTRIES(DATA_LPAGE_TLB_ENTRIES),
.SECTION_TLB_ENTRIES(DATA_SECTION_TLB_ENTRIES),
.FPAGE_TLB_ENTRIES(DATA_FPAGE_TLB_ENTRIES),
.CACHE_LINE(CODE_CACHE_LINE)
)
u_data_cache (
.i_clk (i_clk),
.i_reset (reset),
.i_address (cpu_daddr + (cpu_pid << 25)),
.i_address_nxt (cpu_daddr_nxt + (cpu_pid << 25)),
.i_rd (!cpu_dc_we && cpu_dc_stb),
.i_wr ( cpu_dc_we && cpu_dc_stb),
.i_ben (cpu_dc_sel),
.i_dat (cpu_dc_dat),
.o_dat (dc_data),
.o_ack (data_ack),
.o_err (data_err),
.o_fsr (dc_fsr),
.o_far (dc_far),
.i_mmu_en (cpu_mmu_en),
.i_cache_en (cpu_dc_en),
.i_cache_inv_req (cpu_dc_inv),
.i_cache_clean_req (cpu_dc_clean),
.o_cache_inv_done (dc_inv_done),
.o_cache_clean_done (dc_clean_done),
.i_cpsr (cpu_mem_translate ? USR : cpu_cpsr),
.i_sr (cpu_sr),
.i_baddr (cpu_baddr),
.i_dac_reg (cpu_dac_reg),
.i_tlb_inv (cpu_dtlb_inv),
.o_err2 (dcache_err2),
.o_wb_stb (),
.o_wb_cyc (),
.o_wb_wen (),
.o_wb_sel (),
.o_wb_dat (),
.o_wb_adr (),
.o_wb_cti (),
.i_wb_dat (wb_dat),
.i_wb_ack (d_wb_ack),
.o_wb_stb_nxt (d_wb_stb),
.o_wb_cyc_nxt (d_wb_cyc),
.o_wb_wen_nxt (d_wb_wen),
.o_wb_sel_nxt (d_wb_sel),
.o_wb_dat_nxt (d_wb_dat),
.o_wb_adr_nxt (d_wb_adr),
.o_wb_cti_nxt (d_wb_cti)
);
zap_cache #(
.CACHE_SIZE(CODE_CACHE_SIZE),
.SPAGE_TLB_ENTRIES(CODE_SPAGE_TLB_ENTRIES),
.LPAGE_TLB_ENTRIES(CODE_LPAGE_TLB_ENTRIES),
.SECTION_TLB_ENTRIES(CODE_SECTION_TLB_ENTRIES),
.FPAGE_TLB_ENTRIES(CODE_FPAGE_TLB_ENTRIES),
.CACHE_LINE(DATA_CACHE_LINE)
)
u_code_cache (
.i_clk (i_clk),
.i_reset (reset),
.i_address ((cpu_iaddr & 32'hFFFF_FFFC) + (cpu_pid << 25)), // Cut off lower 2 bits.
.i_address_nxt ((cpu_iaddr_nxt & 32'hFFFF_FFFC) + (cpu_pid << 25)), // Cut off lower 2 bits.
.i_rd (cpu_instr_stb),
.i_wr (1'd0),
.i_ben (4'b1111),
.i_dat (32'd0),
.o_dat (ic_data),
.o_ack (instr_ack),
.o_err (instr_err),
.o_fsr (),
.o_far (),
.i_mmu_en (cpu_mmu_en),
.i_cache_en (cpu_ic_en),
.i_cache_inv_req (cpu_ic_inv),
.i_cache_clean_req (cpu_ic_clean),
.o_cache_inv_done (ic_inv_done),
.o_cache_clean_done(ic_clean_done),
.i_cpsr (cpu_mem_translate ? USR : cpu_cpsr),
.i_sr (cpu_sr),
.i_baddr (cpu_baddr),
.i_dac_reg (cpu_dac_reg),
.i_tlb_inv (cpu_itlb_inv),
.o_err2 (icache_err2),
.o_wb_stb (),
.o_wb_cyc (),
.o_wb_wen (),
.o_wb_sel (),
.o_wb_dat (),
.o_wb_adr (),
.o_wb_cti (),
.i_wb_dat (wb_dat),
.i_wb_ack (c_wb_ack),
.o_wb_stb_nxt (c_wb_stb),
.o_wb_cyc_nxt (c_wb_cyc),
.o_wb_wen_nxt (c_wb_wen),
.o_wb_sel_nxt (c_wb_sel),
.o_wb_dat_nxt (c_wb_dat),
.o_wb_adr_nxt (c_wb_adr),
.o_wb_cti_nxt (c_wb_cti)
);
zap_wb_merger u_zap_wb_merger (
.i_clk(i_clk),
.i_reset(i_reset),
.i_c_wb_stb(c_wb_stb),
.i_c_wb_cyc(c_wb_cyc),
.i_c_wb_wen(c_wb_wen),
.i_c_wb_sel(c_wb_sel),
.i_c_wb_dat(c_wb_dat),
.i_c_wb_adr(c_wb_adr),
.i_c_wb_cti(c_wb_cti),
.o_c_wb_ack(c_wb_ack),
.i_d_wb_stb(d_wb_stb),
.i_d_wb_cyc(d_wb_cyc),
.i_d_wb_wen(d_wb_wen),
.i_d_wb_sel(d_wb_sel),
.i_d_wb_dat(d_wb_dat),
.i_d_wb_adr(d_wb_adr),
.i_d_wb_cti(d_wb_cti),
.o_d_wb_ack(d_wb_ack),
.o_wb_cyc(wb_cyc),
.o_wb_stb(wb_stb),
.o_wb_wen(wb_we),
.o_wb_sel(wb_sel),
.o_wb_dat(wb_idat),
.o_wb_adr(wb_adr),
.o_wb_cti(wb_cti),
.i_wb_ack(wb_ack)
);
zap_wb_adapter #(.DEPTH(STORE_BUFFER_DEPTH)) u_zap_wb_adapter (
.i_clk(i_clk),
.i_reset(i_reset),
.I_WB_CYC(wb_cyc),
.I_WB_STB(wb_stb),
.I_WB_WE(wb_we),
.I_WB_DAT(wb_idat),
.I_WB_SEL(wb_sel),
.I_WB_CTI(wb_cti),
.O_WB_ACK(wb_ack),
.O_WB_DAT(wb_dat),
.I_WB_ADR(wb_adr),
.o_wb_cyc(o_wb_cyc),
.o_wb_stb(o_wb_stb),
.o_wb_we(o_wb_we),
.o_wb_sel(o_wb_sel),
.o_wb_dat(o_wb_dat),
.o_wb_adr(o_wb_adr),
.o_wb_cti(o_wb_cti),
.i_wb_dat(i_wb_dat),
.i_wb_ack(i_wb_ack),
// CYC and STB nxt.
.o_wb_stb_nxt (),
.o_wb_cyc_nxt (),
.o_wb_adr_nxt (),
.o_wb_sel_nxt (),
.o_wb_dat_nxt (),
.o_wb_we_nxt ()
);
endmodule // zap_top.v
`default_nettype wire
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/17.0std/ip/merlin/altera_avalon_mm_bridge/altera_avalon_mm_bridge.v#1 $
// $Revision: #1 $
// $Date: 2017/01/22 $
// $Author: swbranch $
// --------------------------------------
// Avalon-MM pipeline bridge
//
// Optionally registers Avalon-MM command and response signals
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_avalon_mm_bridge
#(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter RESPONSE_WIDTH = 2,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1,
// --------------------------------------
// Derived parameters
// --------------------------------------
parameter BYTEEN_WIDTH = DATA_WIDTH / SYMBOL_WIDTH
)
(
input clk,
input reset,
output s0_waitrequest,
output [DATA_WIDTH-1:0] s0_readdata,
output s0_readdatavalid,
output [RESPONSE_WIDTH-1:0] s0_response,
input [BURSTCOUNT_WIDTH-1:0] s0_burstcount,
input [DATA_WIDTH-1:0] s0_writedata,
input [HDL_ADDR_WIDTH-1:0] s0_address,
input s0_write,
input s0_read,
input [BYTEEN_WIDTH-1:0] s0_byteenable,
input s0_debugaccess,
input m0_waitrequest,
input [DATA_WIDTH-1:0] m0_readdata,
input m0_readdatavalid,
input [RESPONSE_WIDTH-1:0] m0_response,
output [BURSTCOUNT_WIDTH-1:0] m0_burstcount,
output [DATA_WIDTH-1:0] m0_writedata,
output [HDL_ADDR_WIDTH-1:0] m0_address,
output m0_write,
output m0_read,
output [BYTEEN_WIDTH-1:0] m0_byteenable,
output m0_debugaccess
);
// --------------------------------------
// Registers & signals
// --------------------------------------
reg [BURSTCOUNT_WIDTH-1:0] cmd_burstcount;
reg [DATA_WIDTH-1:0] cmd_writedata;
reg [HDL_ADDR_WIDTH-1:0] cmd_address;
reg cmd_write;
reg cmd_read;
reg [BYTEEN_WIDTH-1:0] cmd_byteenable;
wire cmd_waitrequest;
reg cmd_debugaccess;
reg [BURSTCOUNT_WIDTH-1:0] wr_burstcount;
reg [DATA_WIDTH-1:0] wr_writedata;
reg [HDL_ADDR_WIDTH-1:0] wr_address;
reg wr_write;
reg wr_read;
reg [BYTEEN_WIDTH-1:0] wr_byteenable;
reg wr_debugaccess;
reg [BURSTCOUNT_WIDTH-1:0] wr_reg_burstcount;
reg [DATA_WIDTH-1:0] wr_reg_writedata;
reg [HDL_ADDR_WIDTH-1:0] wr_reg_address;
reg wr_reg_write;
reg wr_reg_read;
reg [BYTEEN_WIDTH-1:0] wr_reg_byteenable;
reg wr_reg_waitrequest;
reg wr_reg_debugaccess;
reg use_reg;
wire wait_rise;
reg [DATA_WIDTH-1:0] rsp_readdata;
reg rsp_readdatavalid;
reg [RESPONSE_WIDTH-1:0] rsp_response;
// --------------------------------------
// Command pipeline
//
// Registers all command signals, including waitrequest
// --------------------------------------
generate if (PIPELINE_COMMAND == 1) begin
// --------------------------------------
// Waitrequest Pipeline Stage
//
// Output waitrequest is delayed by one cycle, which means
// that a master will see waitrequest assertions one cycle
// too late.
//
// Solution: buffer the command when waitrequest transitions
// from low->high. As an optimization, we can safely assume
// waitrequest is low by default because downstream logic
// in the bridge ensures this.
//
// Note: this implementation buffers idle cycles should
// waitrequest transition on such cycles. This is a potential
// cause for throughput loss, but ye olde pipeline bridge did
// the same for years and no one complained. Not buffering idle
// cycles costs logic on the waitrequest path.
// --------------------------------------
assign s0_waitrequest = wr_reg_waitrequest;
assign wait_rise = ~wr_reg_waitrequest & cmd_waitrequest;
always @(posedge clk, posedge reset) begin
if (reset) begin
wr_reg_waitrequest <= 1'b1;
// --------------------------------------
// Bit of trickiness here, deserving of a long comment.
//
// On the first cycle after reset, the pass-through
// must not be used or downstream logic may sample
// the same command twice because of the delay in
// transmitting a falling waitrequest.
//
// Using the registered command works on the condition
// that downstream logic deasserts waitrequest
// immediately after reset, which is true of the
// next stage in this bridge.
// --------------------------------------
use_reg <= 1'b1;
wr_reg_burstcount <= 1'b1;
wr_reg_writedata <= 0;
wr_reg_byteenable <= {BYTEEN_WIDTH{1'b1}};
wr_reg_address <= 0;
wr_reg_write <= 1'b0;
wr_reg_read <= 1'b0;
wr_reg_debugaccess <= 1'b0;
end else begin
wr_reg_waitrequest <= cmd_waitrequest;
if (wait_rise) begin
wr_reg_writedata <= s0_writedata;
wr_reg_byteenable <= s0_byteenable;
wr_reg_address <= s0_address;
wr_reg_write <= s0_write;
wr_reg_read <= s0_read;
wr_reg_burstcount <= s0_burstcount;
wr_reg_debugaccess <= s0_debugaccess;
end
// stop using the buffer when waitrequest is low
if (~cmd_waitrequest)
use_reg <= 1'b0;
else if (wait_rise) begin
use_reg <= 1'b1;
end
end
end
always @* begin
wr_burstcount = s0_burstcount;
wr_writedata = s0_writedata;
wr_address = s0_address;
wr_write = s0_write;
wr_read = s0_read;
wr_byteenable = s0_byteenable;
wr_debugaccess = s0_debugaccess;
if (use_reg) begin
wr_burstcount = wr_reg_burstcount;
wr_writedata = wr_reg_writedata;
wr_address = wr_reg_address;
wr_write = wr_reg_write;
wr_read = wr_reg_read;
wr_byteenable = wr_reg_byteenable;
wr_debugaccess = wr_reg_debugaccess;
end
end
// --------------------------------------
// Master-Slave Signal Pipeline Stage
//
// One notable detail is that cmd_waitrequest is deasserted
// when this stage is idle. This allows us to make logic
// optimizations in the waitrequest pipeline stage.
//
// Also note that cmd_waitrequest is deasserted during reset,
// which is not spec-compliant, but is ok for an internal
// signal.
// --------------------------------------
wire no_command;
assign no_command = ~(cmd_read || cmd_write);
assign cmd_waitrequest = m0_waitrequest & ~no_command;
always @(posedge clk, posedge reset) begin
if (reset) begin
cmd_burstcount <= 1'b1;
cmd_writedata <= 0;
cmd_byteenable <= {BYTEEN_WIDTH{1'b1}};
cmd_address <= 0;
cmd_write <= 1'b0;
cmd_read <= 1'b0;
cmd_debugaccess <= 1'b0;
end
else begin
if (~cmd_waitrequest) begin
cmd_writedata <= wr_writedata;
cmd_byteenable <= wr_byteenable;
cmd_address <= wr_address;
cmd_write <= wr_write;
cmd_read <= wr_read;
cmd_burstcount <= wr_burstcount;
cmd_debugaccess <= wr_debugaccess;
end
end
end
end // conditional command pipeline
else begin
assign s0_waitrequest = m0_waitrequest;
always @* begin
cmd_burstcount = s0_burstcount;
cmd_writedata = s0_writedata;
cmd_address = s0_address;
cmd_write = s0_write;
cmd_read = s0_read;
cmd_byteenable = s0_byteenable;
cmd_debugaccess = s0_debugaccess;
end
end
endgenerate
assign m0_burstcount = cmd_burstcount;
assign m0_writedata = cmd_writedata;
assign m0_address = cmd_address;
assign m0_write = cmd_write;
assign m0_read = cmd_read;
assign m0_byteenable = cmd_byteenable;
assign m0_debugaccess = cmd_debugaccess;
// --------------------------------------
// Response pipeline
//
// Registers all response signals
// --------------------------------------
generate if (PIPELINE_RESPONSE == 1) begin
always @(posedge clk, posedge reset) begin
if (reset) begin
rsp_readdatavalid <= 1'b0;
rsp_readdata <= 0;
rsp_response <= 0;
end
else begin
rsp_readdatavalid <= m0_readdatavalid;
rsp_readdata <= m0_readdata;
rsp_response <= m0_response;
end
end
end // conditional response pipeline
else begin
always @* begin
rsp_readdatavalid = m0_readdatavalid;
rsp_readdata = m0_readdata;
rsp_response = m0_response;
end
end
endgenerate
assign s0_readdatavalid = rsp_readdatavalid;
assign s0_readdata = rsp_readdata;
assign s0_response = rsp_response;
endmodule
|
`include "constants.vh"
`include "rv32_opcodes.vh"
module singlecycproc
(
output wire [`ADDR_LEN-1:0] iraddr1,
output wire [`ADDR_LEN-1:0] iraddr2,
output wire [`ADDR_LEN-1:0] draddr1,
output wire [`ADDR_LEN-1:0] draddr2,
input wire [`DATA_LEN-1:0] irdata1,
input wire [`DATA_LEN-1:0] irdata2,
input wire [`DATA_LEN-1:0] drdata1,
input wire [`DATA_LEN-1:0] drdata2,
output wire [1:0] drsize1,
output wire [1:0] drsize2,
output wire [`ADDR_LEN-1:0] dwaddr1,
output wire [`ADDR_LEN-1:0] dwaddr2,
output wire [`DATA_LEN-1:0] dwdata1,
output wire [`DATA_LEN-1:0] dwdata2,
output wire dwe1,
output wire dwe2,
output wire [1:0] dwsize1,
output wire [1:0] dwsize2,
input clk,
input reset
);
wire [6:0] opcode;
wire [`IMM_TYPE_WIDTH-1:0] imm_type;
wire [`REG_SEL-1:0] rs1;
wire [`REG_SEL-1:0] rs2;
wire [`REG_SEL-1:0] rd;
wire [`SRC_A_SEL_WIDTH-1:0] src_a_sel;
wire [`SRC_B_SEL_WIDTH-1:0] src_b_sel;
wire wr_reg;
wire ill_inst;
wire uses_rs1;
wire uses_rs2;
wire [`ALU_OP_WIDTH-1:0] alu_op;
wire [`RS_ENT_SEL-1:0] rs_ent;
wire [2:0] dmem_size;
wire [`MEM_TYPE_WIDTH-1:0] dmem_type;
wire [`MD_OP_WIDTH-1:0] md_req_op;
wire md_req_in_1_signed;
wire md_req_in_2_signed;
wire [`MD_OUT_SEL_WIDTH-1:0] md_req_out_sel;
wire [`DATA_LEN-1:0] imm;
wire [`DATA_LEN-1:0] rs1_data;
wire [`DATA_LEN-1:0] rs2_data;
reg [`DATA_LEN-1:0] wb_data;
wire [`DATA_LEN-1:0] alu_src_a;
wire [`DATA_LEN-1:0] alu_src_b;
wire [`DATA_LEN-1:0] alu_res;
wire [`DATA_LEN-1:0] mul_res;
wire [`DATA_LEN-1:0] load_dat;
wire [`DATA_LEN-1:0] imm_br;
wire [`DATA_LEN-1:0] imm_jal;
wire [`DATA_LEN-1:0] imm_jalr;
reg [`DATA_LEN-1:0] imm_j;
reg [`ADDR_LEN-1:0] pc;
reg [`ADDR_LEN-1:0] npc;
always @ (posedge clk) begin
if (reset) begin
pc <= 32'h0;
end
else begin
pc <= npc;
end
end
assign iraddr1 = pc;
assign opcode = irdata1[6:0];
/*
//512KB SRAM
memory_nolatch
simmem(
.clk(clk),
.iraddr1(iraddr1),
.iraddr2(iraddr2),
.draddr1(draddr1),
.draddr2(draddr2),
.irdata1(irdata1),
.irdata2(irdata2),
.drdata1(drdata1),
.drdata2(drdata2),
.drsize1(drsize1),
.drsize2(drsize2),
.dwaddr1(dwaddr1),
.dwaddr2(dwaddr2),
.dwdata1(dwdata1),
.dwdata2(dwdata2),
.dwe1(dwe1),
.dwe2(dwe2),
.dwsize1(dwsize1),
.dwsize2(dwsize2)
);
*/
decoder dcd(
.inst(irdata1),
.imm_type(imm_type),
.rs1(rs1),
.rs2(rs2),
.rd(rd),
.src_a_sel(src_a_sel),
.src_b_sel(src_b_sel),
.wr_reg(wr_reg),
.uses_rs1(uses_rs1),
.uses_rs2(uses_rs2),
.illegal_instruction(ill_inst),
.alu_op(alu_op),
.rs_ent(rs_ent),
.dmem_size(dmem_size),
.dmem_type(dmem_type),
.md_req_op(md_req_op),
.md_req_in_1_signed(md_req_in_1_signed),
.md_req_in_2_signed(md_req_in_2_signed),
.md_req_out_sel(md_req_out_sel)
);
imm_gen ig(
.inst(irdata1),
.imm_type(imm_type),
.imm(imm)
);
ram_sync_nolatch_2r1w #(`REG_SEL, `DATA_LEN, `REG_NUM)
regfile(
.clk(clk),
.raddr1(rs1),
.raddr2(rs2),
.rdata1(rs1_data),
.rdata2(rs2_data),
.waddr(rd),
.wdata(wb_data),
.we(wr_reg && (rd != 0))
);
src_a_mux sam(
.src_a_sel(src_a_sel),
.pc(pc),
.rs1(rs1_data),
.alu_src_a(alu_src_a)
);
src_b_mux sbm(
.src_b_sel(src_b_sel),
.imm(imm),
.rs2(rs2_data),
.alu_src_b(alu_src_b)
);
//ALICE so cute!
alu alu_normal(
.op(alu_op),
.in1(alu_src_a),
.in2(alu_src_b),
.out(alu_res)
);
//MULTIPLIER
multiplier mpr(
.src1(rs1_data),
.src2(rs2_data),
.src1_signed(md_req_in_1_signed),
.src2_signed(md_req_in_2_signed),
.sel_lohi(md_req_out_sel[0]),
.result(mul_res)
);
//LOAD UNIT
assign draddr1 = alu_res;
assign load_dat = drdata1;
assign drsize1 = dmem_size[1:0];
//STORE UNIT
assign dwaddr1 = alu_res;
assign dwsize1 = dmem_size[1:0];
assign dwdata1 = rs2_data;
assign dwe1 = (rs_ent == `RS_ENT_ST) ? 1 : 0;
//BRANCH UNIT
assign imm_br = { {20{irdata1[31]}}, irdata1[7], irdata1[30:25], irdata1[11:8], 1'b0 };
assign imm_jal = { {12{irdata1[31]}}, irdata1[19:12], irdata1[20],
irdata1[30:25], irdata1[24:21], 1'b0 };
assign imm_jalr = { {21{irdata1[31]}}, irdata1[30:21], 1'b0 };
always @(*) begin
case(rs_ent)
`RS_ENT_LD: begin
wb_data = load_dat;
end
`RS_ENT_MUL: begin
wb_data = mul_res;
end
default: begin
wb_data = alu_res;
end
endcase
end // always @ begin
always @(*) begin
case (opcode)
`RV32_BRANCH: begin
npc = alu_res ? (pc + imm_br) : (pc + 4);
end
`RV32_JAL: begin
npc = pc + imm_jal;
end
`RV32_JALR: begin
npc = rs1_data + imm_jalr;
end
default: begin
npc = pc + 4;
end
endcase
end // always @ begin
endmodule // testbench
|
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
// A Message stream is a wire of width WIDTH.
// If the first bit is a '1' it is a header.
// The following LOG_MAX_PACKET_LENGTH bits give the
// number of WIDTH bit blocks in the packet.
module message_stream_combiner
#(
parameter N_STREAMS = 4,
parameter LOG_N_STREAMS = 2,
parameter WIDTH = 32,
parameter INPUT_BUFFER_LENGTH = 64,
parameter LOG_INPUT_BUFFER_LENGTH = 6,
parameter MAX_PACKET_LENGTH = 1024,
parameter LOG_MAX_PACKET_LENGTH = 10
)
(
input clk,
input rst_n,
input wire [WIDTH*N_STREAMS-1:0] in_data,
input wire [N_STREAMS-1:0] in_nd,
output reg [WIDTH-1:0] out_data,
output reg out_nd,
output wire error
);
wire [N_STREAMS-1:0] stream_write_errors;
wire [N_STREAMS-1:0] stream_read_errors;
wire [N_STREAMS-1:0] stream_errors;
reg [N_STREAMS-1: 0] read_deletes;
wire [N_STREAMS-1: 0] read_fulls;
wire [WIDTH-1: 0] read_datas[N_STREAMS-1:0];
reg [LOG_N_STREAMS-1: 0] stream;
assign stream_errors = stream_write_errors | stream_read_errors;
assign error = | stream_errors;
genvar i;
// Set up the input buffers.
// FIXME: Change this to use buffer_BB so it is faster.
generate
for (i=0; i<N_STREAMS; i=i+1) begin: LOOP_0
buffer_AA #(WIDTH, INPUT_BUFFER_LENGTH, LOG_INPUT_BUFFER_LENGTH)
the_buffer
(.clk(clk),
.rst_n(rst_n),
.write_strobe(in_nd[i]),
.write_data(in_data[WIDTH*(i+1)-1 -:WIDTH]),
.read_delete(read_deletes[i]),
.read_full(read_fulls[i]),
.read_data(read_datas[i]),
.write_error(stream_write_errors[i]),
.read_error(stream_read_errors[i])
);
end
endgenerate
reg [LOG_MAX_PACKET_LENGTH-1:0] packet_pos;
reg [LOG_MAX_PACKET_LENGTH-1:0] packet_length;
wire is_header;
wire [WIDTH-1:0] temp_is_header;
// If I use is_header = read_datas[stream][WIDTH-1] it seems to pick up
// the least significant bit (irrespective of the value in the second
// bracket) when I synthesise (but not simulate in Icarus). So I'm using
// this alternate method.
assign temp_is_header = read_datas[stream] >> (WIDTH-1);
assign is_header = temp_is_header;
// Deal with reading from input buffers.
always @ (posedge clk)
begin
if (!rst_n)
begin
stream <= {LOG_N_STREAMS{1'b0}};
read_deletes <= {N_STREAMS{1'b0}};
packet_pos <= {LOG_MAX_PACKET_LENGTH{1'b0}};
packet_length <= {LOG_MAX_PACKET_LENGTH{1'b0}};
end
else
begin
// If just deleted then we need to wait a cycle before the
// buffer displays the new value for reading.
if ((!read_deletes[stream]) && (read_fulls[stream]))
begin
read_deletes <= {{N_STREAMS-1{1'b0}},{1'b1}} << stream;
out_nd <= 1'b1;
out_data <= read_datas[stream];
if (packet_pos == 0)
begin
// Check if header (look at header bit)
if (is_header)
begin
packet_length <= read_datas[stream][WIDTH-2 -:LOG_MAX_PACKET_LENGTH];
if (read_datas[stream][WIDTH-2 -:LOG_MAX_PACKET_LENGTH] != 0)
packet_pos <= packet_pos + 1;
end
end // if (packet_pos == 0)
else
begin
if (packet_pos == packet_length)
packet_pos <= 0;
else
packet_pos <= packet_pos + 1;
end
end
else
begin
out_nd <= 1'b0;
if (packet_pos == 0)
// Move onto next stream.
begin
if (stream == N_STREAMS-1)
stream <= 0;
else
stream <= stream + 1;
end
read_deletes <= {N_STREAMS{1'b0}};
end
end
end
endmodule
|
module antiDroopIIR (
input clk,
input trig,
input signed [12:0] din,
input signed [6:0] tapWeight,
input accClr_en,
input oflowClr,
output reg oflowDetect = 1'd0,
output reg signed [15:0] dout = 16'sd0);
parameter IIR_scale = 15; // define the scaling factor for the IIR multiplier, eg for 0.002 (din = 63, IIR_scale = 15).
//`define ADDPIPEREG
reg signed [12:0] din_del = 13'sd0;
`ifdef ADDPIPEREG reg signed [12:0] din_del_b = 13'sd0;
`endif
reg signed [47:0] tap = 48'sd0;
reg signed [19:0] multreg = 20'sd0;
(* equivalent_register_removal = "no" *) reg trig_a = 1'b0, trig_b = 1'b0;
wire trig_edge = trig_a & ~trig_b;
//reg trig_edge = 1'b0;
reg signed [6:0] tapWeight_a = 7'sd0, tapWeight_b = 7'sd0;
always @(posedge clk) begin
//trig_edge <= trig_a & ~trig_b;
tapWeight_a <= tapWeight;
tapWeight_b <= tapWeight_a;
trig_a <= trig;
trig_b <= trig_a;
din_del <= din;
`ifdef ADDPIPEREG
din_del_b <= din_del;
multreg <= din_del*tapWeight_b;
dout <= {din_del_b, 3'b000} + tap[IIR_scale+12:IIR_scale-3];
`else
multreg <= din*tapWeight_b;
dout <= {din_del, 3'b000} + tap[IIR_scale+12:IIR_scale-3];
`endif
if (trig_edge && accClr_en) tap <= 48'd0;
else tap <= multreg + tap;
//tap <= din*tapWeight + tap;
if (oflowDetect && oflowClr) oflowDetect <= 1'b0;
//else if ((~& tap[47:IIR_scale+12]) || (& ~tap[47:IIR_scale+12])) oflowDetect <= 1'b1;
//else if ((~& tap[47:IIR_scale+12]) || (& tap[47:IIR_scale+12])) oflowDetect <= 1'b1;
else if (^ tap[IIR_scale+13:IIR_scale+12]) oflowDetect <= 1'b1;
else oflowDetect <= oflowDetect;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:39:44 04/06/2010
// Design Name:
// Module Name: path
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MDPath(input clk,
input reset,
input MIO_ready, //=1
input IorD,
input IRWrite,
input[1:0] RegDst,
input RegWrite,
input[1:0]MemtoReg,
input ALUSrcA,
input[1:0]ALUSrcB,
input[1:0]PCSource,
input PCWrite,
input PCWriteCond,
input Branch,
input[2:0]ALU_operation,
output[31:0]PC_Current,
input[31:0]data2CPU,
output[31:0]Inst,
output[31:0]data_out,
output[31:0]M_addr,
output zero,
output overflow
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INV_SYMBOL_V
`define SKY130_FD_SC_HDLL__INV_SYMBOL_V
/**
* inv: Inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INV_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2_1_V
`define SKY130_FD_SC_MS__AND2_1_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2_1_V
|
/*
* Copyright (C) 2009 Onno Kortmann <[email protected]>
* 2015 Klaus Rudolph <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
*/
module ATmega32(clk, PA, PB, PC, PD);
parameter progfile="UNSPECIFIED";
input clk;
inout [7:0] PA;
inout [7:0] PB;
inout [7:0] PC;
inout [7:0] PD;
defparam core.progfile=progfile;
defparam core.name="atmega32";
AVRCORE core(clk);
avr_pin #("A0") pa0(PA[0]);
avr_pin #("A1") pa1(PA[1]);
avr_pin #("A2") pa2(PA[2]);
avr_pin #("A3") pa3(PA[3]);
avr_pin #("A4") pa4(PA[4]);
avr_pin #("A5") pa5(PA[5]);
avr_pin #("A6") pa6(PA[6]);
avr_pin #("A7") pa7(PA[7]);
avr_pin #("B0") pb0(PB[0]);
avr_pin #("B1") pb1(PB[1]);
avr_pin #("B2") pb2(PB[2]);
avr_pin #("B3") pb3(PB[3]);
avr_pin #("B4") pb4(PB[4]);
avr_pin #("B5") pb5(PB[5]);
avr_pin #("B6") pb6(PB[6]);
avr_pin #("B7") pb7(PB[7]);
avr_pin #("C0") pc0(PC[0]);
avr_pin #("C1") pc1(PC[1]);
avr_pin #("C2") pc2(PC[2]);
avr_pin #("C3") pc3(PC[3]);
avr_pin #("C4") pc4(PC[4]);
avr_pin #("C5") pc5(PC[5]);
avr_pin #("C6") pc6(PC[6]);
avr_pin #("D0") pd0(PD[0]);
avr_pin #("D1") pd1(PD[1]);
avr_pin #("D2") pd2(PD[2]);
avr_pin #("D3") pd3(PD[3]);
avr_pin #("D4") pd4(PD[4]);
avr_pin #("D5") pd5(PD[5]);
avr_pin #("D6") pd6(PD[6]);
avr_pin #("D7") pd7(PD[7]);
endmodule
|
/* An 8 clock of latency shift-register FIFO. (8bit queue)
*
* This really is an 8 bit circular array with a write pointer that moves but
* it will always read from position zero. Reading empty values will
* return zero.
*
* Created by David Tran
* Version 0.1.0.0
* Last Modified:04-24-2014
*/
module shift_fifo (
readMode, // Specifies if we want to read from the FIFO
writeMode, // Specifies if we want to write form the FIFO
inputBit, // The input bit to write to the shift-register
outputBit, // The output bit to read from the shift-register
clk, // Clock input
rst // Reset input
);
input readMode, writeMode, clk, rst;
input inputBit;
output outputBit;
reg outputBit;
reg [7:0] curData; // This contains the full queue.
reg [2:0] topPtr; // This is the current write pointer (top) of the queue.
always @(posedge clk or posedge rst)
if (rst) begin
topPtr <= 3'h0;
curData <= 8'h00;
end else begin
if (readMode) begin
{curData, outputBit} <= {1'b0, curData}; // Read out "zeroth" bit
topPtr <= topPtr - 1; // Change pointer location
end else if (writeMode) begin
curData[topPtr] <= inputBit; // Write in new bit
topPtr <= topPtr + 1; // Change pointer location
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name:
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module sgb_cpu(
input RST,
input CPU_RST,
input CLK,
input CLK_CPU_EDGE,
// SYS out
input SYS_RDY,
output SYS_REQ,
output SYS_WR,
output [15:0] SYS_ADDR,
input [7:0] SYS_RDDATA,
output [7:0] SYS_WRDATA,
output BOOTROM_ACTIVE,
output FREE_SLOT,
// PPU out
output PPU_DOT_EDGE,
output PPU_PIXEL_VALID,
output [1:0] PPU_PIXEL,
output PPU_VSYNC_EDGE,
output PPU_HSYNC_EDGE,
// APU out
output [19:0] APU_DAT,
// P1
output [1:0] P1O,
input [3:0] P1I,
// Halt
input HLT_REQ,
output HLT_RSP,
input IDL_ICD,
// Features
input [15:0] FEAT,
// State
output REG_REQ,
output [7:0] REG_ADDR,
output [7:0] REG_REQ_DATA,
input [7:0] MBC_REG_DATA,
// DBG
input MCU_RRQ,
input MCU_WRQ,
input [18:0] MCU_ADDR,
input [7:0] MCU_DATA_IN,
output MCU_RSP,
output [7:0] MCU_DATA_OUT,
output [11:0] DBG_ADDR,
input [7:0] DBG_ICD2_DATA_IN,
input [7:0] DBG_MBC_DATA_IN,
input [7:0] DBG_CHEAT_DATA_IN,
input [7:0] DBG_MAIN_DATA_IN,
input [8*8-1:0] DBG_CONFIG,
output DBG_BRK
);
integer i;
//-------------------------------------------------------------------
// DESCRIPTION
//-------------------------------------------------------------------
// This is the SGB2-CPU chip which consists of the following logic:
//
// CPU - Central Processing Unit
// IFD - Instruction Fetch and Decode
// EXE - Register Read, EXEcute/Memory, and Writeback
// ICT - Interrupt ConTroller
// PPU - Pixel Processing Unit
// APU - Audio Processing Unit
// MCT - Memory ConTroller for internal (VRAM, OAM, HRAM, REG) and external state (WRAM and CART)
// DMA - DMA engine for copying data to the OAM
// SER - SERial state machine
//
// DBG - DeBuG state available for breakpoint/watchpoint
//-------------------------------------------------------------------
// MISC
//-------------------------------------------------------------------
`define APU
`define OPR_I 4'd0
`define OPR_PC 4'd1
`define OPR_S8 4'd2
`define OPR_U16 4'd3
`define OPR_BC 4'd4
`define OPR_DE 4'd5
`define OPR_SP 4'd6
`define OPR_AF 4'd7
`define OPR_B 4'd8
`define OPR_C 4'd9
`define OPR_D 4'd10
`define OPR_E 4'd11
`define OPR_H 4'd12
`define OPR_L 4'd13
`define OPR_HL 4'd14
`define OPR_A 4'd15
`define GRP_SPC 4'd0
`define GRP_MOV 4'd1
`define GRP_INC 4'd2
`define GRP_DEC 4'd3
`define GRP_ALU 4'd4
`define GRP_BIT 4'd5
`define GRP_JMP 4'd6
`define GRP____ 4'd7
`define GRP_MST 4'd8
`define GRP_MLD 4'd9
`define GRP_MIC 4'd10
`define GRP_MDC 4'd11
`define GRP_MLU 4'd12
`define GRP_MBT 4'd13
`define GRP_CLL 4'd14
`define GRP_RET 4'd15
`define DEC_SZE 15:14
`define DEC_LAT 13:12
`define DEC_DST 11:8
`define DEC_SRC 7:4
`define DEC_GRP 3:0
// Forwarded signals
//
// IFD outputs
//
wire IFD_EXE_valid;
wire [23:0] IFD_EXE_op;
wire [15:0] IFD_EXE_decode;
wire [15:0] IFD_EXE_pc_start;
wire [15:0] IFD_EXE_pc_end;
wire [15:0] IFD_EXE_pc_next;
wire IFD_EXE_cb;
wire IFD_EXE_new;
wire IFD_EXE_int;
wire IFD_MCT_req_val;
wire [15:0] IFD_MCT_req_addr_d1;
wire [7:0] IFD_REG_ic;
//
// EXE outputs
//
wire EXE_MCT_req_val;
wire [15:0] EXE_MCT_req_addr_d1;
wire EXE_MCT_req_wr;
wire [7:0] EXE_MCT_req_data_d1;
wire EXE_IFD_redirect;
wire [15:0] EXE_IFD_target;
wire EXE_IFD_ready;
wire EXE_IFD_ime;
wire EXE_DMA_halt;
wire EXE_REG_ime;
//
// REG outputs
//
wire [7:0] REG_data;
wire REG_MCT_rsp_val;
wire REG_DBG_rsp_val;
wire REG_DMA_start;
wire REG_req_val;
wire REG_req_dbg;
wire [7:0] REG_address;
wire [7:0] REG_req_data;
//
// MCT outputs
//
wire [7:0] MCT_data;
wire MCT_IFD_rsp_val;
wire MCT_EXE_rsp_val;
wire MCT_VRAM_wren;
wire [12:0] MCT_VRAM_address;
wire [7:0] MCT_VRAM_data;
wire MCT_OAM_wren;
wire [7:0] MCT_OAM_address;
wire [7:0] MCT_OAM_data;
wire MCT_HRAM_wren;
wire [6:0] MCT_HRAM_address;
wire [7:0] MCT_HRAM_data;
wire MCT_REG_req_val;
wire MCT_REG_wren;
wire [7:0] MCT_REG_address;
wire [7:0] MCT_REG_data;
//
// MCT input data
//
wire [7:0] VRAM_data;
wire [7:0] OAM_data;
wire [7:0] HRAM_data;
//
// PPU outputs
//
wire PPU_VRAM_active;
wire [12:0] PPU_VRAM_address;
wire PPU_OAM_active;
wire [7:0] PPU_OAM_address;
wire PPU_REG_vblank;
wire PPU_REG_lcd_stat;
wire PPU_vblank;
//
// DMA outputs
//
wire DMA_SYS_active;
wire DMA_VRAM_active;
wire DMA_active;
wire DMA_req_val;
wire [15:0] DMA_address;
wire DMA_OAM_req_val;
wire [7:0] DMA_OAM_address;
wire [7:0] DMA_OAM_req_data;
//
// APU outputs
//
wire [3:0] APU_REG_enable;
wire SER_REG_done;
wire DBG_EXE_step;
wire DBG_REG_req_val;
wire DBG_REG_wren;
wire [7:0] DBG_REG_address;
wire [7:0] DBG_REG_data;
wire DBG_advance;
wire HLT_REQ_sync;
wire HLT_IFD_rsp;
wire HLT_EXE_rsp;
wire HLT_DMA_rsp;
wire HLT_SER_rsp;
assign HLT_RSP = HLT_REQ_sync & HLT_IFD_rsp & HLT_EXE_rsp & HLT_DMA_rsp & HLT_SER_rsp;
//-------------------------------------------------------------------
// Clocks
//-------------------------------------------------------------------
// Generate a BUS clock edge from the incoming CPU clock edge. The
// BUS clock is always /4.
reg [1:0] clk_bus_ctr_r; always @(posedge CLK) clk_bus_ctr_r <= RST ? 0 : clk_bus_ctr_r + (CLK_CPU_EDGE ? 1 : 0);
wire CLK_BUS_EDGE = CLK_CPU_EDGE & &clk_bus_ctr_r;
// Synchronize reset to bus edge. Want a full bus clock prior to first edge assertion and the system bus to be ready
reg cpu_ireset_r; always @(posedge CLK) cpu_ireset_r <= RST | CPU_RST | (cpu_ireset_r & (~CLK_BUS_EDGE | ~SYS_RDY));
// Assume GB only needs PSRAM on the first of the 4 CPU clocks. Each CPU clock is a minimum of 16 CLK2
// and PSRAM should only need ~8 of those clocks to perform the access. It's possible that the GB timing
// will spill into the first free slot, but that will just remove that slot for MCU use.
// The delay needs to match the mct request pipe to the system:
// -1 - CLK_BUS_EDGE
// 0 - MCT request dma_req_r SYS/REQ
// 1 - MCT decode ReqPendr
// 2 - MCT mct_req_r/SYS_REQ
// 3 - ReqPendr
reg [5:0] cpu_free_slot_r;
always @(posedge CLK) begin
// MCU needs more bandwidth so now we only block the last empty CPU clock cycle shifted by a value greater than the MCT delay
cpu_free_slot_r <= {cpu_free_slot_r[4:0],(~&clk_bus_ctr_r)};
end
assign FREE_SLOT = cpu_free_slot_r[5];
reg [1:0] ppu_vblank_sync_r;
reg hlt_req_sync_r;
always @(posedge CLK) begin
if (CLK_BUS_EDGE) ppu_vblank_sync_r <= {ppu_vblank_sync_r[0],PPU_vblank};
hlt_req_sync_r <= cpu_ireset_r ? 0 : (CLK_BUS_EDGE && ppu_vblank_sync_r == 2'b01) ? HLT_REQ : hlt_req_sync_r;
end
assign HLT_REQ_sync = hlt_req_sync_r;
//-------------------------------------------------------------------
// REG/MMIO
//-------------------------------------------------------------------
`define P1_I 3:0
`define P1_O 5:4
`define TAC_FREQ_DIV 1:0
`define TAC_ENABLE 2:2
`define LCDC_BG_EN 0:0
`define LCDC_SP_EN 1:1
`define LCDC_SP_SIZE 2:2
`define LCDC_BG_MAP_SEL 3:3
`define LCDC_BG_TILE_SEL 4:4
`define LCDC_WD_EN 5:5
`define LCDC_WD_MAP_SEL 6:6
`define LCDC_DS_EN 7:7
`define STAT_MODE 1:0
`define STAT_ACTIVE 1:1
`define STAT_LYC_MATCH 2:2
`define STAT_INT_H_EN 3:3 // mode 0
`define STAT_INT_V_EN 4:4 // mode 1
`define STAT_INT_O_EN 5:5 // mode 2
`define STAT_INT_M_EN 6:6
`define PAL0 1:0
`define PAL1 3:2
`define PAL2 5:4
`define PAL3 7:6
`define BOOT_ROM_DI 0:0
`define IE_VBLANK 0:0
`define IE_LCD_STAT 1:1
`define IE_TIMER 2:2
`define IE_SERIAL 3:3
`define IE_JOYPAD 4:4
// square1
`define NR10_SWEEP_SHIFT 2:0
`define NR10_SWEEP_NEG 3:3
`define NR10_SWEEP_TIME 6:4
`define NR11_LENGTH 5:0
`define NR11_DUTY 7:6
`define NR12_ENV_PERIOD 2:0
`define NR12_ENV_DIR 3:3
`define NR12_ENV_VOLUME 7:4
`define NR13_FREQ_LSB 7:0
`define NR14_FREQ_MSB 2:0
`define NR14_FREQ_STOP 6:6
`define NR14_FREQ_ENABLE 7:7
// square2
`define NR21_LENGTH 5:0
`define NR21_DUTY 7:6
`define NR22_ENV_PERIOD 2:0
`define NR22_ENV_DIR 3:3
`define NR22_ENV_VOLUME 7:4
`define NR23_FREQ_LSB 7:0
`define NR24_FREQ_MSB 2:0
`define NR24_FREQ_STOP 6:6
`define NR24_FREQ_ENABLE 7:7
// wave
`define NR30_WAVE_ENABLE 7:7
`define NR31_LENGTH 7:0
`define NR32_LEVEL 6:5
`define NR33_FREQ_LSB 7:0
`define NR34_FREQ_MSB 2:0
`define NR34_FREQ_STOP 6:6
`define NR34_FREQ_ENABLE 7:7
// noise
`define NR41_LENGTH 5:0
`define NR42_ENV_PERIOD 2:0
`define NR42_ENV_DIR 3:3
`define NR42_ENV_VOLUME 7:4
`define NR43_LFSR_DIV 2:0
`define NR43_LFSR_WIDTH 3:3
`define NR43_LFSR_SHIFT 7:4
`define NR44_FREQ_STOP 6:6
`define NR44_FREQ_ENABLE 7:7
// control
`define NR50_MASTER_LEFT_VOLUME 2:0
`define NR50_MASTER_LEFT_ENABLE 3:3
`define NR50_MASTER_RIGHT_VOLUME 6:4
`define NR50_MASTER_RIGHT_ENABLE 7:7
`define NR51_SELECT_LEFT_CH0 0:0
`define NR51_SELECT_LEFT_CH1 1:1
`define NR51_SELECT_LEFT_CH2 2:2
`define NR51_SELECT_LEFT_CH3 3:3
`define NR51_SELECT_RIGHT_CH0 4:4
`define NR51_SELECT_RIGHT_CH1 5:5
`define NR51_SELECT_RIGHT_CH2 6:6
`define NR51_SELECT_RIGHT_CH3 7:7
`define NR52_CONTROL_CH0_ACTIVE 0:0
`define NR52_CONTROL_CH1_ACTIVE 1:1
`define NR52_CONTROL_CH2_ACTIVE 2:2
`define NR52_CONTROL_CH3_ACTIVE 3:3
`define NR52_CONTROL_ENABLE 7:7
reg [15:0] PC_r;
reg [7:0] A_r;
reg [7:0] F_r;
reg [7:0] B_r;
reg [7:0] C_r;
reg [7:0] D_r;
reg [7:0] E_r;
reg [7:0] H_r;
reg [7:0] L_r;
reg [15:0] SP_r;
`define AF_r {A_r,F_r}
`define BC_r {B_r,C_r}
`define DE_r {D_r,E_r}
`define HL_r {H_r,L_r}
`define FLAG_Z 7
`define FLAG_N 6
`define FLAG_H 5
`define FLAG_C 4
reg [7:0] REG_P1_r; // FF00
reg [7:0] REG_SB_r; // FF01
reg [7:0] REG_SC_r; // FF02
reg [15:0] REG_DIV_r; // FF04 top 8b
reg [7:0] REG_TIMA_r; // FF05
reg [7:0] REG_TMA_r; // FF06
reg [7:0] REG_TAC_r; // FF07
reg [7:0] REG_IF_r; // FF0F
// APU
reg [7:0] REG_NR10_r; // FF10
reg [7:0] REG_NR11_r; // FF11
reg [7:0] REG_NR12_r; // FF12
reg [7:0] REG_NR13_r; // FF13
reg [7:0] REG_NR14_r; // FF14
reg [7:0] REG_NR21_r; // FF16
reg [7:0] REG_NR22_r; // FF17
reg [7:0] REG_NR23_r; // FF18
reg [7:0] REG_NR24_r; // FF19
reg [7:0] REG_NR30_r; // FF1A
reg [7:0] REG_NR31_r; // FF1B
reg [7:0] REG_NR32_r; // FF1C
reg [7:0] REG_NR33_r; // FF1D
reg [7:0] REG_NR34_r; // FF1E
reg [7:0] REG_NR41_r; // FF20
reg [7:0] REG_NR42_r; // FF21
reg [7:0] REG_NR43_r; // FF22
reg [7:0] REG_NR44_r; // FF23
reg [7:0] REG_NR50_r; // FF24
reg [7:0] REG_NR51_r; // FF25
reg [7:0] REG_NR52_r; // FF26
reg [7:0] REG_WAV_r[15:0]; // FF30-FF3F
// PPU
reg [7:0] REG_LCDC_r; // FF40
reg [7:0] REG_STAT_r; // FF41
reg [7:0] REG_SCY_r; // FF42
reg [7:0] REG_SCX_r; // FF43
reg [7:0] REG_LY_r; // FF44
reg [7:0] REG_LYC_r; // FF45
reg [7:0] REG_DMA_r; // FF46
reg [7:0] REG_BGP_r; // FF47
reg [7:0] REG_OBP0_r; // FF48
reg [7:0] REG_OBP1_r; // FF49
reg [7:0] REG_WY_r; // FF4A
reg [7:0] REG_WX_r; // FF4B
// MISC
reg [0:0] REG_BOOT_r; // FF50
reg [7:0] REG_IE_r; // FFFF
parameter
ST_REG_IDLE = 3'b001,
ST_REG_REQ = 3'b010,
ST_REG_END = 3'b100;
reg reg_req_r;
reg [2:0] reg_state_r;
reg [7:0] reg_addr_r;
reg reg_src_r;
reg reg_wr_r;
reg [7:0] reg_wr_data_r;
reg [7:0] reg_mdr_r;
reg tmr_apu_step_r;
reg tmr_ovf_1024_r;
reg tmr_ovf_16_r;
reg tmr_ovf_64_r;
reg tmr_ovf_256_r;
reg tmr_ovf_tima_r;
reg tmr_cpu_edge_d1_r;
reg reg_dma_start_r;
reg reg_int_write_r;
reg [7:0] reg_int_write_data_r;
assign BOOTROM_ACTIVE = ~REG_BOOT_r[`BOOT_ROM_DI];
assign P1O = REG_P1_r[5:4];
assign REG_MCT_rsp_val = |(reg_state_r & ST_REG_END) & ~reg_src_r;
assign REG_DBG_rsp_val = |(reg_state_r & ST_REG_END) & reg_src_r;
assign REG_data = reg_mdr_r;
assign REG_DMA_start = reg_dma_start_r;
assign REG_req_val = |(reg_state_r & ST_REG_REQ) & reg_wr_r;
`ifdef SGB_SAVE_STATES
assign REG_req_dbg = |(reg_state_r & ST_REG_REQ) & reg_wr_r & reg_src_r;
`else
assign REG_req_dbg = 0;
`endif
assign REG_address = reg_addr_r;
assign REG_req_data = reg_wr_data_r;
assign REG_REQ = REG_req_dbg;
assign REG_ADDR = REG_address;
assign REG_REQ_DATA = REG_req_data;
always @(posedge CLK) begin
if (cpu_ireset_r) begin
reg_state_r <= ST_REG_IDLE;
reg_req_r <= 0;
tmr_cpu_edge_d1_r <= 0;
tmr_ovf_tima_r <= 0;
reg_dma_start_r <= 0;
reg_int_write_r <= 0;
REG_P1_r[5:4] <= 2'b11; // FF00
//REG_SB_r; // FF01
//REG_SC_r; // FF02
REG_DIV_r <= 16'h0000; // FF04
REG_TIMA_r <= 8'h00; // FF05
REG_TMA_r <= 8'h00; // FF06
REG_TAC_r <= 8'h00; // FF07
REG_IF_r <= 8'h00; // FF0F
// Audio registers written by APU
REG_LCDC_r <= 8'h00; // FF40
REG_STAT_r[7:3] <= 0;
REG_SCY_r <= 8'h00; // FF42
REG_SCX_r <= 8'h00; // FF43
//REG_LY_r // FF44
REG_LYC_r <= 8'h00; // FF45
//REG_DMA_r // FF46
REG_BGP_r <= 8'hFC; // FF47
REG_OBP0_r <= 8'hFF; // FF48
REG_OBP1_r <= 8'hFF; // FF49
REG_WY_r <= 8'h00; // FF4A
REG_WX_r <= 8'h00; // FF4B
REG_BOOT_r <= 8'h00; // FF50
REG_IE_r <= 8'h00; // FFFF
end
else begin
// timers
if (CLK_CPU_EDGE & DBG_advance) begin
{tmr_ovf_16_r, REG_DIV_r[3:0] } <= REG_DIV_r[3:0] + 1;
{tmr_ovf_64_r, REG_DIV_r[5:4] } <= REG_DIV_r[5:4] + tmr_ovf_16_r;
{tmr_ovf_256_r, REG_DIV_r[7:6] } <= REG_DIV_r[7:6] + tmr_ovf_64_r;
{tmr_ovf_1024_r,REG_DIV_r[9:8] } <= REG_DIV_r[9:8] + tmr_ovf_256_r;
{tmr_apu_step_r,REG_DIV_r[12:10]} <= REG_DIV_r[12:10] + tmr_ovf_1024_r;
{ REG_DIV_r[15:13]} <= REG_DIV_r[15:13] + tmr_apu_step_r;
end
tmr_cpu_edge_d1_r <= CLK_CPU_EDGE;
// there are at least 16 base clocks in a CPU clock so update the timer state using a base clock delay
if (REG_TAC_r[`TAC_ENABLE]) begin
if (tmr_cpu_edge_d1_r) begin
if (REG_TAC_r[`TAC_FREQ_DIV] == 0 ? tmr_ovf_1024_r : REG_TAC_r[`TAC_FREQ_DIV] == 1 ? tmr_ovf_16_r : REG_TAC_r[`TAC_FREQ_DIV] == 2 ? tmr_ovf_64_r : tmr_ovf_256_r) begin
{tmr_ovf_tima_r,REG_TIMA_r} <= REG_TIMA_r + 1;
end
end
else if (CLK_CPU_EDGE) begin
tmr_ovf_tima_r <= 0;
// load TMA into TIMA one CPU clock after the overflow
if (tmr_ovf_tima_r) REG_TIMA_r <= REG_TMA_r;
end
end
else begin
tmr_ovf_tima_r <= 0;
end
// interrupt flags
if (CLK_CPU_EDGE) begin
// once we have halted instruction fetch then time has stopped and we need to avoid recording new interrupts
if (~HLT_IFD_rsp) begin
REG_IF_r[`IE_VBLANK] <= (REG_IF_r[`IE_VBLANK] | PPU_REG_vblank | (reg_int_write_r & reg_int_write_data_r[`IE_VBLANK]) ) & ~(IFD_REG_ic[`IE_VBLANK] | (reg_int_write_r & ~reg_int_write_data_r[`IE_VBLANK]) );
REG_IF_r[`IE_LCD_STAT] <= (REG_IF_r[`IE_LCD_STAT] | PPU_REG_lcd_stat | (reg_int_write_r & reg_int_write_data_r[`IE_LCD_STAT])) & ~(IFD_REG_ic[`IE_LCD_STAT] | (reg_int_write_r & ~reg_int_write_data_r[`IE_LCD_STAT]));
REG_IF_r[`IE_TIMER] <= (REG_IF_r[`IE_TIMER] | tmr_ovf_tima_r | (reg_int_write_r & reg_int_write_data_r[`IE_TIMER]) ) & ~(IFD_REG_ic[`IE_TIMER] | (reg_int_write_r & ~reg_int_write_data_r[`IE_TIMER]) );
REG_IF_r[`IE_SERIAL] <= (REG_IF_r[`IE_SERIAL] | SER_REG_done | (reg_int_write_r & reg_int_write_data_r[`IE_SERIAL]) ) & ~(IFD_REG_ic[`IE_SERIAL] | (reg_int_write_r & ~reg_int_write_data_r[`IE_SERIAL]) );
REG_IF_r[`IE_JOYPAD] <= (REG_IF_r[`IE_JOYPAD] | |(REG_P1_r[3:0] & ~P1I[3:0]) | (reg_int_write_r & reg_int_write_data_r[`IE_JOYPAD]) ) & ~(IFD_REG_ic[`IE_JOYPAD] | (reg_int_write_r & ~reg_int_write_data_r[`IE_JOYPAD]) );
end
end
if (CLK_CPU_EDGE) REG_P1_r[3:0] <= P1I[3:0];
if (CLK_BUS_EDGE) reg_dma_start_r <= 0;
if (CLK_CPU_EDGE) reg_int_write_r <= 0;
case (reg_state_r)
ST_REG_IDLE: begin
if (MCT_REG_req_val) begin
reg_src_r <= 0;
reg_addr_r <= MCT_REG_address;
reg_wr_r <= MCT_REG_wren;
reg_wr_data_r <= MCT_REG_data;
reg_state_r <= ST_REG_REQ;
end
else if (DBG_REG_req_val) begin
reg_src_r <= 1;
reg_addr_r <= DBG_REG_address;
reg_wr_r <= DBG_REG_wren;
reg_wr_data_r <= DBG_REG_data;
reg_state_r <= ST_REG_REQ;
end
end
ST_REG_REQ: begin
case (reg_addr_r)
8'h00: begin reg_mdr_r[7:0] <= {2'b11, REG_P1_r[5:0]}; if (reg_wr_r) REG_P1_r[5:4] <= reg_wr_data_r[5:4]; end
8'h01: reg_mdr_r[7:0] <= REG_SB_r;
8'h02: reg_mdr_r[7:0] <= {REG_SC_r[7],6'h3F,REG_SC_r[0]};
8'h04: begin reg_mdr_r[7:0] <= REG_DIV_r[15:8]; if (reg_wr_r) REG_DIV_r[15:0] <= 0; end
8'h05: begin reg_mdr_r[7:0] <= REG_TIMA_r; if (reg_wr_r) REG_TIMA_r[7:0] <= reg_wr_data_r[7:0]; end
8'h06: begin reg_mdr_r[7:0] <= REG_TMA_r; if (reg_wr_r) REG_TMA_r[7:0] <= reg_wr_data_r[7:0]; end
8'h07: begin reg_mdr_r[7:0] <= {5'h1F,REG_TAC_r[2:0]}; if (reg_wr_r) REG_TAC_r[2:0] <= reg_wr_data_r[2:0]; end
8'h0F: begin reg_mdr_r[7:0] <= REG_IF_r; if (reg_wr_r) begin reg_int_write_data_r <= reg_wr_data_r[7:0]; reg_int_write_r <= 1; end end
// APU registers read here for MMIO accesses and written in APU
8'h10: reg_mdr_r[7:0] <= {1'h1,REG_NR10_r[6:0]};
8'h11: reg_mdr_r[7:0] <= {REG_NR11_r[7:6],6'h3F};
8'h12: reg_mdr_r[7:0] <= REG_NR12_r[7:0];
8'h13: reg_mdr_r[7:0] <= 8'hFF;
8'h14: reg_mdr_r[7:0] <= {1'h1,REG_NR14_r[6],6'h3F};
8'h16: reg_mdr_r[7:0] <= {REG_NR21_r[7:6],6'h3F};
8'h17: reg_mdr_r[7:0] <= REG_NR22_r[7:0];
8'h18: reg_mdr_r[7:0] <= 8'hFF;
8'h19: reg_mdr_r[7:0] <= {1'h1,REG_NR24_r[6],6'h3F};
8'h1A: reg_mdr_r[7:0] <= {REG_NR30_r[7:7],7'h7F};
8'h1B: reg_mdr_r[7:0] <= 8'hFF;
8'h1C: reg_mdr_r[7:0] <= {1'h1,REG_NR32_r[6:5],5'h1F};
8'h1D: reg_mdr_r[7:0] <= 8'hFF;
8'h1E: reg_mdr_r[7:0] <= {1'h1,REG_NR34_r[6],6'h3F};
8'h20: reg_mdr_r[7:0] <= 8'hFF;
8'h21: reg_mdr_r[7:0] <= REG_NR42_r;
8'h22: reg_mdr_r[7:0] <= REG_NR43_r;
8'h23: reg_mdr_r[7:0] <= {1'h1,REG_NR44_r[6],6'hFF};
8'h24: reg_mdr_r[7:0] <= REG_NR50_r;
8'h25: reg_mdr_r[7:0] <= REG_NR51_r;
8'h26: reg_mdr_r[7:0] <= {REG_NR52_r[7:7],3'h7,({4{REG_NR52_r[7]}} & {APU_REG_enable})};
8'h30: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h31: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h32: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h33: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h34: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h35: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h36: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h37: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h38: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h39: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h3A: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h3B: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h3C: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h3D: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h3E: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h3F: reg_mdr_r[7:0] <= (APU_REG_enable[2] & ~reg_src_r) ? 8'hFF : REG_WAV_r[reg_addr_r[3:0]][7:0];
8'h40: begin reg_mdr_r[7:0] <= REG_LCDC_r; if (reg_wr_r) REG_LCDC_r[7:0] <= reg_wr_data_r[7:0]; end
8'h41: begin reg_mdr_r[7:0] <= {1'b1,REG_STAT_r[6:0]}; if (reg_wr_r) REG_STAT_r[7:3] <= reg_wr_data_r[7:3]; end
8'h42: begin reg_mdr_r[7:0] <= REG_SCY_r; if (reg_wr_r) REG_SCY_r[7:0] <= reg_wr_data_r[7:0]; end
8'h43: begin reg_mdr_r[7:0] <= REG_SCX_r; if (reg_wr_r) REG_SCX_r[7:0] <= reg_wr_data_r[7:0]; end
8'h44: reg_mdr_r[7:0] <= REG_LY_r;
8'h45: begin reg_mdr_r[7:0] <= REG_LYC_r; if (reg_wr_r) REG_LYC_r[7:0] <= reg_wr_data_r[7:0]; end
8'h46: begin reg_mdr_r[7:0] <= REG_DMA_r; if (reg_wr_r) begin REG_DMA_r[7:0] <= reg_wr_data_r[7:0]; reg_dma_start_r <= ~HLT_RSP; end end // don't trigger DMA on HLT
8'h47: begin reg_mdr_r[7:0] <= REG_BGP_r; if (reg_wr_r) REG_BGP_r[7:0] <= reg_wr_data_r[7:0]; end
8'h48: begin reg_mdr_r[7:0] <= REG_OBP0_r; if (reg_wr_r) REG_OBP0_r[7:0] <= reg_wr_data_r[7:0]; end
8'h49: begin reg_mdr_r[7:0] <= REG_OBP1_r; if (reg_wr_r) REG_OBP1_r[7:0] <= reg_wr_data_r[7:0]; end
8'h4A: begin reg_mdr_r[7:0] <= REG_WY_r; if (reg_wr_r) REG_WY_r[7:0] <= reg_wr_data_r[7:0]; end
8'h4B: begin reg_mdr_r[7:0] <= REG_WX_r; if (reg_wr_r) REG_WX_r[7:0] <= reg_wr_data_r[7:0]; end
8'h50: begin reg_mdr_r[7:0] <= {7'h7F,REG_BOOT_r[`BOOT_ROM_DI]}; if (reg_wr_r) REG_BOOT_r[`BOOT_ROM_DI] <= 1'b1; end
`ifdef SGB_SAVE_STATES
// special case debug source reads to read out arch state that isn't normally memory mapped
// ARCH state
8'h60: if (reg_src_r) reg_mdr_r <= A_r;
8'h61: if (reg_src_r) reg_mdr_r <= F_r[7:0];
8'h62: if (reg_src_r) reg_mdr_r <= B_r;
8'h63: if (reg_src_r) reg_mdr_r <= C_r;
8'h64: if (reg_src_r) reg_mdr_r <= D_r;
8'h65: if (reg_src_r) reg_mdr_r <= E_r;
8'h66: if (reg_src_r) reg_mdr_r <= H_r;
8'h67: if (reg_src_r) reg_mdr_r <= L_r;
8'h68: if (reg_src_r) reg_mdr_r <= SP_r[7:0];
8'h69: if (reg_src_r) reg_mdr_r <= SP_r[15:8];
8'h6A: if (reg_src_r) reg_mdr_r <= PC_r[7:0];
8'h6B: if (reg_src_r) reg_mdr_r <= PC_r[15:8];
8'h6C: if (reg_src_r) reg_mdr_r <= EXE_REG_ime;
// MBC
8'h70: if (reg_src_r) reg_mdr_r <= MBC_REG_DATA;
8'h71: if (reg_src_r) reg_mdr_r <= MBC_REG_DATA;
8'h72: if (reg_src_r) reg_mdr_r <= MBC_REG_DATA;
8'h73: if (reg_src_r) reg_mdr_r <= MBC_REG_DATA;
8'h74: if (reg_src_r) reg_mdr_r <= MBC_REG_DATA;
8'h75: if (reg_src_r) reg_mdr_r <= MBC_REG_DATA;
8'h76: if (reg_src_r) reg_mdr_r <= MBC_REG_DATA;
8'h77: if (reg_src_r) reg_mdr_r <= MBC_REG_DATA;
`endif
8'hFF: begin reg_mdr_r[7:0] <= {3'h0,REG_IE_r[4:0]}; if (reg_wr_r) REG_IE_r[4:0] <= reg_wr_data_r[4:0]; end
default: reg_mdr_r <= 8'hFF;
endcase
reg_state_r <= ST_REG_END;
end
ST_REG_END: begin
reg_state_r <= ST_REG_IDLE;
end
endcase
end
end
//-------------------------------------------------------------------
// IFD
//-------------------------------------------------------------------
// IFD performs Instruction Fetch and Decode operations in one or more
// bus cycles. The number of bytes fetched is based on the decoded
// operation in a prior cycle.
// Local
reg [7:0] ifd_op_r;
reg [1:0] ifd_size_r;
reg [7:0] ifd_data_r;
reg [15:0] ifd_decode_r;
reg ifd_req_r;
reg ifd_complete_r;
reg ifd_cb_r;
reg ifd_int_r;
reg [2:0] ifd_int_tgt_r;
reg [7:0] ifd_int_ic_r;
// Outputs
reg ifd_exe_valid_r;
reg [23:0] ifd_exe_op_r;
reg [15:0] ifd_exe_decode_r;
reg [15:0] ifd_exe_pc_start_r;
reg [15:0] ifd_exe_pc_end_r;
reg [15:0] ifd_exe_pc_next_r;
reg ifd_exe_cb_r;
reg ifd_exe_new_r;
reg ifd_exe_int_r;
reg [7:0] ifd_reg_ic_r;
// decoder
wire [7:0] dec_addr = ifd_op_r;
wire [15:0] dec_data;
// PC with bypass
wire [15:0] ifd_pc = EXE_IFD_redirect ? EXE_IFD_target : PC_r;
`ifdef MK2
dec_table dec (
.clka(CLK), // input clka
.addra(dec_addr), // input [7 : 0] addra
.douta(dec_data) // output [15 : 0] douta
);
`endif
`ifdef MK3
dec_table dec (
.clock(CLK), // input clock
.address(dec_addr), // input [7 : 0] address
.q(dec_data) // output [15 : 0] q
);
`endif
assign IFD_MCT_req_val = ifd_req_r;
assign IFD_MCT_req_addr_d1 = ifd_pc;
assign IFD_EXE_valid = ifd_exe_valid_r;
assign IFD_EXE_decode = ifd_exe_decode_r;
assign IFD_EXE_op = ifd_exe_op_r;
assign IFD_EXE_pc_start = ifd_exe_pc_start_r;
assign IFD_EXE_pc_end = ifd_exe_pc_end_r;
assign IFD_EXE_pc_next = ifd_exe_pc_next_r;
assign IFD_EXE_cb = ifd_exe_cb_r;
assign IFD_EXE_new = ifd_exe_new_r;
assign IFD_EXE_int = ifd_exe_int_r;
assign IFD_REG_ic = ifd_reg_ic_r;
// idle when:
// - at instruction boundary
// - not taking an interrupt
// - no in-progress ICD transfers
assign HLT_IFD_rsp = HLT_REQ_sync & ~|ifd_size_r & ~ifd_int_r & IDL_ICD;
always @(posedge CLK) begin
if (cpu_ireset_r) begin
PC_r <= 0;
ifd_exe_valid_r <= 0;
ifd_size_r <= 0;
ifd_req_r <= 1; // generate the initial request out of reset
ifd_exe_new_r <= 0;
ifd_int_ic_r <= 0;
end
else begin
ifd_exe_new_r <= 0;
if (CLK_CPU_EDGE) ifd_reg_ic_r <= 0;
if (CLK_BUS_EDGE & EXE_IFD_ready) begin
if (~HLT_IFD_rsp) begin
PC_r <= ifd_pc + 1;
// Flop pipeline registers
ifd_exe_valid_r <= ifd_complete_r;
ifd_exe_new_r <= ifd_complete_r;
ifd_exe_int_r <= ifd_complete_r & ifd_int_r;
// Adjust current instrucion size
ifd_size_r <= ifd_complete_r ? 0 : ifd_size_r + 1;
if (ifd_complete_r & ifd_int_r) ifd_reg_ic_r <= ifd_int_ic_r;
end
else begin
// force bypassed PC to be accounted for in state
PC_r <= ifd_pc;
ifd_exe_valid_r <= 0;
ifd_exe_new_r <= 0;
ifd_exe_int_r <= 0;
end
end
ifd_req_r <= CLK_BUS_EDGE;
end
if (CLK_BUS_EDGE & EXE_IFD_ready) begin
case (ifd_size_r)
0: ifd_exe_op_r[7:0] <= ifd_int_r ? {2'h3,ifd_int_tgt_r,3'h7} : ifd_data_r;
1: ifd_exe_op_r[15:8] <= ifd_data_r;
2: ifd_exe_op_r[23:16] <= ifd_data_r;
endcase
ifd_exe_decode_r <= ifd_decode_r;
if (ifd_size_r == 0) ifd_exe_pc_start_r <= ifd_pc;
ifd_exe_pc_end_r <= ifd_pc;
ifd_exe_pc_next_r <= ifd_pc + (ifd_int_r ? 0 : 1);
ifd_exe_cb_r <= ifd_cb_r;
end
if (MCT_IFD_rsp_val) begin
ifd_data_r <= MCT_data;
if (ifd_size_r == 0) ifd_op_r <= MCT_data;
end
// Interrupts
// this doesn't have to be the first base cycle since the instruction is contructed from constants and register state
ifd_int_r <= EXE_IFD_ime & |(REG_IE_r & REG_IF_r) & ~|ifd_size_r;
ifd_int_tgt_r <= ( (REG_IE_r[`IE_VBLANK] & REG_IF_r[`IE_VBLANK] ) ? 3'h0
: (REG_IE_r[`IE_LCD_STAT] & REG_IF_r[`IE_LCD_STAT]) ? 3'h1
: (REG_IE_r[`IE_TIMER] & REG_IF_r[`IE_TIMER]) ? 3'h2
: (REG_IE_r[`IE_SERIAL] & REG_IF_r[`IE_SERIAL]) ? 3'h3
: (REG_IE_r[`IE_JOYPAD] & REG_IF_r[`IE_JOYPAD]) ? 3'h4
: 3'h7
);
if (REG_IE_r[`IE_VBLANK] & REG_IF_r[`IE_VBLANK] ) ifd_int_ic_r <= 8'b00000001;
else if (REG_IE_r[`IE_LCD_STAT] & REG_IF_r[`IE_LCD_STAT]) ifd_int_ic_r <= 8'b00000010;
else if (REG_IE_r[`IE_TIMER] & REG_IF_r[`IE_TIMER] ) ifd_int_ic_r <= 8'b00000100;
else if (REG_IE_r[`IE_SERIAL] & REG_IF_r[`IE_SERIAL] ) ifd_int_ic_r <= 8'b00001000;
else if (REG_IE_r[`IE_JOYPAD] & REG_IF_r[`IE_JOYPAD] ) ifd_int_ic_r <= 8'b00010000;
else ifd_int_ic_r <= 8'b00000000;
ifd_complete_r <= (ifd_decode_r[`DEC_SZE] == ifd_size_r);
ifd_cb_r <= ifd_op_r == 8'hCB;
// SZE2, LAT2, DST4, SRC4, GRP4
ifd_decode_r <= ( ifd_int_r ? {2'h0,2'h0,`OPR_SP,`OPR_PC,`GRP_CLL}
: ifd_cb_r ? {2'h1,{(ifd_data_r[2:0] == 3'h6 ? 1'b1 : 1'b0),1'b0},{1'b1,ifd_data_r[2:0]},{1'b1,ifd_data_r[2:0]},({{(ifd_data_r[2:0] == 3'h6 ? 1'b1 : 1'b0),3'h0} | `GRP_BIT})}
: dec_data
);
// debug/state writes
if (REG_req_dbg) begin
case (REG_address)
8'h6A: PC_r[7:0] <= REG_req_data;
8'h6B: PC_r[15:8] <= REG_req_data;
endcase
end
end
//-------------------------------------------------------------------
// EXE
//-------------------------------------------------------------------
// EXE implements the execution component of the CPU.
//
// Overall instruction latency is defined as the following:
//
// OP [operand fetch-1 + execution/memory time + writeback]
//
// For example:
// LD R,R [0 + 0 + 1 = 1]
// LD R,n [1 + 0 + 1 = 2]
// LD (HL),n [1 + 1 + 1 = 3]
// RET CC [0 + 1 + 1 = 2] // not taken
// RET CC [0 + 4 + 1 = 5] // taken
//
// IFD handles operand fetch. EXE is responsible for performing any
// data bus operations and writing back to register state. Since
// the next opcode bus fetch is pipelined wrt Writeback,
// WB cannot peform any bus operations.
//
// This multi-cycle operation is composed of 4 distinct stages which can
// cover 1-5 cycles of latency in addition to the 1-2 cycles of operand fetch
// in IFD.
//
// Sequencing:
// 0* 3 2 1 0 // stage numbers
// WB // LD R,R LD R,n
// LD WB
// ST WB
// LD LD WB
// ST ST WB
// LD ST WB
// CC // JR CC not taken
// CC LD LD WB
// CC ST ST WB
// CC -- LD LD WB // RET CC taken
//
// 0/0* - WB/CC is always stage 0*/0. They are effectively the same stage.
// 0* indicates that certain condition code instructions will evaluate and
// possibly extend the execution time 1-4 additional clocks.
// 2/1 - Up to 2 memory data bus operation will be performed in the format of
// LD, ST, LD-LD, ST-ST, or LD-ST. These always occur in stage 2 and 1.
// 3 - This serves as an optional delay stage. No arch state is modified.
// Local
reg exe_advance_r;
reg exe_ready_r;
reg exe_complete_r;
reg [2:0] exe_ctr_r;
reg [2:0] exe_lat_add_r;
reg [15:0] exe_src_r;
reg [15:0] exe_dst_r;
reg [7:0] exe_cc_r;
reg [7:0] exe_src_alu_r;
reg [15:0] exe_res_r;
reg [7:0] exe_res_cc_r;
reg [7:0] exe_res_los_r;
reg [7:0] exe_res_cp_r;
// address arithmetic
reg exe_res_hl_mod_r;
reg [15:0] exe_res_hl_r;
reg exe_res_sp_mod_r;
reg [15:0] exe_res_sp_r;
// alu
reg exe_res_c15_r;
reg exe_res_c11_r;
reg exe_res_c7_r;
reg exe_res_c3_r;
reg exe_res_int_enable_r;
reg exe_res_int_disable_r;
reg exe_res_halt_r;
reg exe_res_stop_r;
reg exe_mem_req_r;
reg [15:0] exe_mem_data_r;
reg [15:0] exe_mem_addr_mod_r;
reg exe_ime_r;
wire exe_loadopstore = (IFD_EXE_decode[`DEC_GRP] == `GRP_MBT || IFD_EXE_decode[`DEC_GRP] == `GRP_MIC || IFD_EXE_decode[`DEC_GRP] == `GRP_MDC);
// use condition codes directly since the flopped version causes problems with evaluating redirect
wire exe_redirect_taken = ~(IFD_EXE_op[3] ^ (IFD_EXE_op[4] ? F_r[`FLAG_C] : F_r[`FLAG_Z]));
wire exe_stall = (exe_res_halt_r & ~|(REG_IE_r[4:0] & REG_IF_r[4:0])) | (exe_res_stop_r & ®_P1_r[3:0]);
// latency/stage computation
// latency adder state is set after cycle 0 to avoid treating the delay as a non-CC/WB cycle. Also, it is forced clear
// on the first base clock of a new op to make sure we do not make an access.
wire [2:0] exe_lat = IFD_EXE_decode[`DEC_LAT] + (IFD_EXE_new ? 0 : exe_lat_add_r);
wire [2:0] exe_stage = exe_lat - exe_ctr_r; // must be correct on first cycle for memory op
// Outputs
reg exe_ifd_redirect_r;
reg [15:0] exe_ifd_redirect_target_r;
reg [15:0] exe_pc_prev_r;
reg [15:0] exe_pc_prev_redirect_r;
reg [15:0] exe_target_prev_redirect_r;
assign EXE_IFD_redirect = IFD_EXE_valid & exe_ifd_redirect_r;
assign EXE_IFD_target = exe_ifd_redirect_target_r;
assign EXE_IFD_ready = exe_ready_r;
assign EXE_IFD_ime = (exe_ime_r | (exe_res_int_enable_r & ~IFD_EXE_op[5])) & ~IFD_EXE_int & ~exe_res_int_disable_r; // RETI and disables need bypass. EI is delayed a clock.
assign EXE_MCT_req_val = IFD_EXE_valid & exe_mem_req_r & ^exe_stage[1:0];
assign EXE_MCT_req_addr_d1 = ( EXE_MCT_req_wr ? {((IFD_EXE_decode[`DEC_DST] == `OPR_S8 || IFD_EXE_decode[`DEC_DST] == `OPR_C) ? 8'hFF : exe_dst_r[15:8]),exe_dst_r[7:0]}
: {((IFD_EXE_decode[`DEC_SRC] == `OPR_S8 || IFD_EXE_decode[`DEC_SRC] == `OPR_C) ? 8'hFF : exe_src_r[15:8]),exe_src_r[7:0]})
+ exe_mem_addr_mod_r;
assign EXE_MCT_req_wr = ( IFD_EXE_decode[`DEC_GRP] == `GRP_MST
|| IFD_EXE_decode[`DEC_GRP] == `GRP_CLL
// load-op-store operations need ST on second stage
|| (exe_stage[0] & exe_loadopstore)
);
// always write MSB followed by LSB. LOS ops need the result of math
assign EXE_MCT_req_data_d1 = exe_loadopstore ? exe_res_los_r[7:0] : (exe_stage[1] ? exe_src_r[15:8] : exe_src_r[7:0]);
assign EXE_DMA_halt = exe_res_halt_r;
assign EXE_REG_ime = exe_ime_r;
assign HLT_EXE_rsp = HLT_REQ_sync & ~IFD_EXE_valid;
reg dbg_advance_r;
assign DBG_advance = dbg_advance_r;
always @(posedge CLK) begin
if (cpu_ireset_r) begin
exe_ctr_r <= 0;
exe_ime_r <= 0;
dbg_advance_r <= 1;
end
else begin
if (CLK_BUS_EDGE & exe_advance_r) begin
exe_ctr_r <= exe_complete_r ? 0 : exe_ctr_r + 1;
if (exe_complete_r) begin
case (IFD_EXE_decode[`DEC_DST])
//`OPR_I : exe_src_r <= 0;
// this is for RET. could also make its target SP
`OPR_PC : begin if (exe_res_sp_mod_r) SP_r <= exe_res_sp_r; end
//`OPR_S8 : exe_dst_r[15:0] <= {8{IFD_EXE_op[15]},IFD_EXE_op[15:8]};
//`OPR_U16: exe_dst_r[15:0] <= IFD_EXE_op[23:8];
`OPR_BC : begin `BC_r <= exe_res_r; SP_r <= exe_res_sp_r; F_r[7:4] <= exe_res_cc_r[7:4]; end
`OPR_DE : begin `DE_r <= exe_res_r; SP_r <= exe_res_sp_r; F_r[7:4] <= exe_res_cc_r[7:4]; end
`OPR_SP : begin SP_r <= exe_res_sp_mod_r ? exe_res_sp_r : exe_res_r; F_r[7:4] <= exe_res_cc_r[7:4]; end
`OPR_AF : begin A_r <= exe_res_r[15:8]; SP_r <= exe_res_sp_r; F_r[7:4] <= exe_res_r[7:4]; end
`OPR_B : begin B_r <= exe_res_r[7:0]; F_r[7:4] <= exe_res_cc_r[7:4]; end
`OPR_C : begin C_r <= exe_res_r[7:0]; F_r[7:4] <= exe_res_cc_r[7:4]; end
`OPR_D : begin D_r <= exe_res_r[7:0]; F_r[7:4] <= exe_res_cc_r[7:4]; end
`OPR_E : begin E_r <= exe_res_r[7:0]; F_r[7:4] <= exe_res_cc_r[7:4]; end
`OPR_H : begin H_r <= exe_res_r[7:0]; F_r[7:4] <= exe_res_cc_r[7:4]; end
`OPR_L : begin L_r <= exe_res_r[7:0]; F_r[7:4] <= exe_res_cc_r[7:4]; end
`OPR_HL : begin `HL_r <= exe_res_hl_mod_r ? exe_res_hl_r : exe_res_r; SP_r <= exe_res_sp_r; F_r[7:4] <= exe_res_cc_r[7:4]; end
`OPR_A : begin A_r <= exe_res_r[7:0]; if (exe_res_hl_mod_r) `HL_r <= exe_res_hl_r; F_r[7:4] <= exe_res_cc_r[7:4]; end
endcase
// delay 1 inst because fetch will see this in the following cycle
exe_ime_r <= (exe_ime_r | exe_res_int_enable_r) & ~exe_res_int_disable_r & ~IFD_EXE_int;
exe_pc_prev_r <= IFD_EXE_pc_start;
if (exe_ifd_redirect_r) exe_pc_prev_redirect_r <= IFD_EXE_pc_start;
if (exe_ifd_redirect_r) exe_target_prev_redirect_r <= exe_ifd_redirect_target_r;
end
end
if (CLK_BUS_EDGE) dbg_advance_r <= ~IFD_EXE_valid | ~exe_complete_r | DBG_EXE_step;
end
// alu/bit/los input
exe_src_alu_r[7:0] <= IFD_EXE_decode[3] ? exe_mem_data_r[7:0] : exe_src_r[7:0];
// default to no redirect and no extended latency
exe_ifd_redirect_r <= 0;
exe_lat_add_r <= 0;
// default no mod to SP
exe_res_sp_mod_r <= 0;
exe_res_sp_r <= SP_r;
exe_res_int_enable_r <= 0;
exe_res_int_disable_r <= 0;
exe_res_r <= exe_dst_r;
exe_res_cc_r <= exe_cc_r;
exe_res_halt_r <= 0;
exe_res_stop_r <= 0;
// result computation
case (IFD_EXE_decode[`DEC_GRP])
`GRP_SPC: begin
// NOP (0x00), STOP (0x10), HALT (0x76), EI (0xFB), DI (0xF3)
exe_res_halt_r <= ~IFD_EXE_op[7] & IFD_EXE_op[4] & IFD_EXE_op[2];
exe_res_stop_r <= ~IFD_EXE_op[7] & IFD_EXE_op[4] & ~IFD_EXE_op[2];
exe_res_int_enable_r <= IFD_EXE_op[7] & IFD_EXE_op[3];
exe_res_int_disable_r <= IFD_EXE_op[7] & ~IFD_EXE_op[3];
end
`GRP_MOV: begin
exe_res_r <= exe_src_r;
exe_res_cc_r <= exe_cc_r;
// LD HL,SP requires an extra clock
if (&IFD_EXE_op[7:6]) exe_lat_add_r <= 1;
end
`GRP_MIC,`GRP_INC,`GRP_DEC,`GRP_MDC: begin
{exe_res_c3_r,exe_res_los_r[3:0]} <= exe_src_alu_r[3:0] + {{3{IFD_EXE_decode[0]}},1'b1};
{exe_res_c7_r,exe_res_los_r[7:4]} <= exe_src_alu_r[7:4] + {4{IFD_EXE_decode[0]}} + exe_res_c3_r;
exe_res_r[7:0] <= IFD_EXE_decode[3] ? exe_dst_r[7:0] : exe_res_los_r[7:0];
if (~IFD_EXE_op[2]) exe_res_r[15:8] <= exe_src_r[15:8] + {8{IFD_EXE_decode[0]}} + exe_res_c7_r;
exe_res_cc_r <= ~IFD_EXE_op[2] ? exe_cc_r : {~|exe_res_los_r,IFD_EXE_decode[0],IFD_EXE_decode[0]^exe_res_c3_r,exe_cc_r[`FLAG_C],exe_cc_r[3:0]};
// 16b operations require an extra clock
exe_lat_add_r <= IFD_EXE_op[1] ? 1 : 0;
end
`GRP_ALU,`GRP_MLU: begin
if (~IFD_EXE_op[7] | (IFD_EXE_op[6] & ~IFD_EXE_op[2])) begin
if (IFD_EXE_op[3:0] == 4'h9) begin
// ADD HL,BC
// ADD HL,DE
// ADD HL,HL
// ADD HL,SP
{exe_res_c11_r,exe_res_r[11:0]} <= exe_dst_r[11:0] + exe_src_r[11:0];
{exe_res_c15_r,exe_res_r[15:12]} <= exe_dst_r[15:12] + exe_src_r[15:12] + exe_res_c11_r;
exe_res_cc_r <= {exe_cc_r[`FLAG_Z],1'b0,exe_res_c11_r,exe_res_c15_r,exe_cc_r[3:0]};
exe_lat_add_r <= 1;
end
else if (IFD_EXE_op[3:0] == 4'h7) begin
if (~IFD_EXE_op[4]) begin
// DAA
if (exe_cc_r[`FLAG_N]) begin
exe_res_r[7:0] <= exe_src_r[7:0] - {(exe_cc_r[`FLAG_C] ? 4'h6 : 4'h0), (exe_cc_r[`FLAG_H] ? 4'h6 : 4'h0)};
exe_res_c7_r <= 0;
end
else begin
{exe_res_c3_r,exe_res_r[3:0]} <= exe_src_r[3:0] + ((exe_cc_r[`FLAG_H] | (exe_src_r[3] & | exe_src_r[2:1])) ? 4'h6 : 4'h0);
{exe_res_c7_r,exe_res_r[7:4]} <= exe_src_r[7:4] + ((exe_cc_r[`FLAG_C] | (exe_src_r[7:0] > 8'h99)) ? 4'h6 : 4'h0) + exe_res_c3_r;
end
exe_res_cc_r <= {~|exe_res_r[7:0],exe_cc_r[`FLAG_N],1'b0,(exe_res_c7_r | exe_cc_r[`FLAG_C]),exe_cc_r[3:0]};
end
else begin
// SCF
exe_res_r <= exe_dst_r;
exe_res_cc_r <= {exe_cc_r[`FLAG_Z],1'b0,1'b0,1'b1,exe_cc_r[3:0]};
end
end
else if (IFD_EXE_op[3:0] == 4'hF) begin
if (~IFD_EXE_op[4]) begin
// CPL
exe_res_r <= ~exe_src_r;
exe_res_cc_r <= {exe_cc_r[`FLAG_Z],1'b1,1'b1,exe_cc_r[4:0]};
end
else begin
// CCF
exe_res_r <= exe_dst_r;
exe_res_cc_r <= {exe_cc_r[`FLAG_Z],1'b0,1'b0,~exe_cc_r[`FLAG_C],exe_cc_r[3:0]};
end
end
else if (IFD_EXE_op[3:0] == 4'h8) begin
if (~IFD_EXE_op[4]) begin
// ADD SP,e
{exe_res_c3_r,exe_res_r[3:0]} <= exe_dst_r[3:0] + exe_src_r[3:0];
{exe_res_c7_r,exe_res_r[7:4]} <= exe_dst_r[7:4] + exe_src_r[7:4] + exe_res_c3_r;
exe_res_r[15:8] <= exe_dst_r[15:8] + exe_src_r[15:8] + exe_res_c7_r;
exe_res_cc_r <= {1'b0,1'b0,exe_res_c3_r,exe_res_c7_r,exe_cc_r[3:0]};
// hack to avoid memory access. stage is always 0 on first cycle
exe_lat_add_r <= |exe_ctr_r ? 2 : 1;
end
else begin
// LD HL,SP+e
{exe_res_c3_r,exe_res_r[3:0]} <= SP_r[3:0] + exe_src_r[3:0];
{exe_res_c7_r,exe_res_r[7:4]} <= SP_r[7:4] + exe_src_r[7:4] + exe_res_c3_r;
exe_res_r[15:8] <= SP_r[15:8] + exe_src_r[15:8] + exe_res_c7_r;
exe_res_cc_r <= {1'b0,1'b0,exe_res_c3_r,exe_res_c7_r,exe_cc_r[3:0]};
exe_lat_add_r <= 1;
end
end
end
else begin
// ALU
case (IFD_EXE_op[5:3])
3'h0,3'h1,3'h2,3'h3: begin // ADD,ADC,SUB,SBC
{exe_res_c3_r,exe_res_r[3:0]} <= exe_dst_r[3:0] + ({4{IFD_EXE_op[4]}} ^ exe_src_alu_r[3:0]) + ((IFD_EXE_op[3] & exe_cc_r[4]) ^ (IFD_EXE_op[4]));
{exe_res_c7_r,exe_res_r[7:4]} <= exe_dst_r[7:4] + ({4{IFD_EXE_op[4]}} ^ exe_src_alu_r[7:4]) + exe_res_c3_r;
exe_res_cc_r <= {~|exe_res_r[7:0],IFD_EXE_op[4],IFD_EXE_op[4]^exe_res_c3_r,IFD_EXE_op[4]^exe_res_c7_r,exe_cc_r[3:0]};
end
3'h4: begin // AND
exe_res_r[7:0] <= exe_dst_r[7:0] & exe_src_alu_r[7:0];
exe_res_cc_r <= {~|exe_res_r[7:0],1'b0,1'b1,1'b0,exe_cc_r[3:0]};
end
3'h5: begin // XOR
exe_res_r[7:0] <= exe_dst_r[7:0] ^ exe_src_alu_r[7:0];
exe_res_cc_r <= {~|exe_res_r[7:0],1'b0,1'b0,1'b0,exe_cc_r[3:0]};
end
3'h6: begin // OR
exe_res_r[7:0] <= exe_dst_r[7:0] | exe_src_alu_r[7:0];
exe_res_cc_r <= {~|exe_res_r[7:0],1'b0,1'b0,1'b0,exe_cc_r[3:0]};
end
3'h7: begin // CP
{exe_res_c3_r,exe_res_cp_r[3:0]} <= exe_dst_r[3:0] + ({4{1'b1}} ^ exe_src_alu_r[3:0]) + 1'b1;
{exe_res_c7_r,exe_res_cp_r[7:4]} <= exe_dst_r[7:4] + ({4{1'b1}} ^ exe_src_alu_r[7:4]) + exe_res_c3_r;
exe_res_cc_r <= {~|exe_res_cp_r[7:0],1'b1,~exe_res_c3_r,~exe_res_c7_r,exe_cc_r[3:0]};
end
endcase
end
end
`GRP_BIT,`GRP_MBT: begin
if (~IFD_EXE_cb) begin
exe_res_r[7:0] <= IFD_EXE_op[3] ? {(IFD_EXE_op[4] ? exe_cc_r[`FLAG_C] : exe_src_r[0]),exe_src_r[7:1]} : {exe_src_r[6:0],(IFD_EXE_op[4] ? exe_cc_r[`FLAG_C] : exe_src_r[7])};
exe_res_cc_r[7:0] <= {1'b0,1'b0,1'b0,(IFD_EXE_op[3] ? exe_src_r[0] : exe_src_r[7]),exe_cc_r[3:0]};
end
else begin
// CB bit operations
case (IFD_EXE_op[15:12])
4'h0,4'h1,4'h2: begin
// RLC,RRC
// RL,RR
// SLA,SRA
exe_res_los_r[7:0] <= IFD_EXE_op[11] ? {(IFD_EXE_op[12] ? exe_cc_r[`FLAG_C] : (IFD_EXE_op[13] ? exe_src_alu_r[7] : exe_src_alu_r[0])),exe_src_alu_r[7:1]} : {exe_src_alu_r[6:0],(IFD_EXE_op[12] ? exe_cc_r[`FLAG_C] : (~IFD_EXE_op[13] & exe_src_alu_r[7]))};
if (~IFD_EXE_decode[3]) exe_res_r[7:0] <= exe_res_los_r[7:0];
exe_res_cc_r <= {~|exe_res_los_r[7:0],1'b0,1'b0,(IFD_EXE_op[11] ? exe_src_alu_r[0] : exe_src_alu_r[7]),exe_cc_r[3:0]};
end
4'h3:begin
// SWAP,SRL
exe_res_los_r[7:0] <= IFD_EXE_op[11] ? {1'b0,exe_src_alu_r[7:1]} : {exe_src_alu_r[3:0],exe_src_alu_r[7:4]};
if (~IFD_EXE_decode[3]) exe_res_r[7:0] <= exe_res_los_r[7:0];
exe_res_cc_r <= {~|exe_res_los_r[7:0],1'b0,1'b0,(IFD_EXE_op[11] & exe_src_alu_r[0]),exe_cc_r[3:0]};
end
4'h4,4'h5,4'h6,4'h7:begin
// BIT
exe_res_los_r[7:0] <= exe_src_alu_r[7:0];
exe_res_cc_r <= {~exe_res_los_r[IFD_EXE_op[13:11]],1'b0,1'b1,exe_cc_r[`FLAG_C],exe_cc_r[3:0]};
// hack to avoid memory access. skips stage 1 (ST)
// NOTE: the previous version of this was holding lat_add from the prior op (2 cycle op, lat_add=1) during the first stage which caused us to not perform the LD
// 1) lat_add to be 0 while the stage is 0
// 2) lat_add to be 7 going into subsequent stages (keyed on BUS_EDGE)
if (IFD_EXE_decode[3]) exe_lat_add_r <= (~exe_stage[1] | CLK_BUS_EDGE) ? 3'h7 : 0;
end
4'h8,4'h9,4'hA,4'hB:begin
// RES
exe_res_los_r[7:0] <= exe_src_alu_r[7:0] & ~(8'h1 << IFD_EXE_op[13:11]);
if (~IFD_EXE_decode[3]) exe_res_r[15:0] <= {8'h00,exe_res_los_r[7:0]};
exe_res_cc_r <= exe_cc_r;
end
4'hC,4'hD,4'hE,4'hF:begin
// SET
exe_res_los_r[7:0] <= exe_src_alu_r[7:0] | (8'h1 << IFD_EXE_op[13:11]);
if (~IFD_EXE_decode[3]) exe_res_r[15:0] <= {8'h00,exe_res_los_r[7:0]};
exe_res_cc_r <= exe_cc_r;
end
endcase
end
end
`GRP_JMP: begin
// branch control flow
// redirect and the associated PC must be available 1 base clock after the start of the bus cycle for IFD to send
// the correct address to MCT! This is important for JMP HL.
// It's ok to cause a redirect even if this isn't the final stage as long as we don't advance EXE.
exe_ifd_redirect_r <= (IFD_EXE_op[0] | (~IFD_EXE_op[7] & ~IFD_EXE_op[5])) | exe_redirect_taken;
exe_ifd_redirect_target_r <= IFD_EXE_op[7] ? (IFD_EXE_op[5] ? `HL_r : exe_src_r) : (IFD_EXE_pc_next + exe_src_r);
// JMP HL needs to be special cased since HL looks like it can be bypassed.
exe_lat_add_r <= (exe_ifd_redirect_r & ~(IFD_EXE_op[7] & IFD_EXE_op[5])) ? 1 : 0;
end
`GRP_RET: begin
// RET
exe_ifd_redirect_r <= IFD_EXE_op[0] | exe_redirect_taken;
exe_ifd_redirect_target_r <= exe_mem_data_r;
exe_lat_add_r <= exe_ifd_redirect_r ? (IFD_EXE_op[0] ? 3 : 4) : 1;
exe_res_sp_mod_r <= exe_ifd_redirect_r;
exe_res_sp_r <= SP_r + 2;
// RETI enables interrupts
exe_res_int_enable_r <= IFD_EXE_op[4] & IFD_EXE_op[0];
end
`GRP_MST: begin
if (IFD_EXE_decode[`DEC_DST] == `OPR_SP) begin
exe_res_sp_mod_r <= 1;
exe_res_sp_r <= SP_r - 2;
end
end
`GRP_MLD: begin
exe_res_r <= exe_mem_data_r;
exe_res_cc_r <= exe_cc_r;
if (IFD_EXE_decode[`DEC_SRC] == `OPR_SP) exe_res_sp_r <= SP_r + 2;
end
`GRP_CLL: begin
// CALL + RST
exe_ifd_redirect_r <= IFD_EXE_op[0] | exe_redirect_taken;
exe_ifd_redirect_target_r <= IFD_EXE_op[1] ? {1'h0,IFD_EXE_int, IFD_EXE_op[5:3], 3'h0} : IFD_EXE_op[23:8];
exe_lat_add_r <= exe_ifd_redirect_r ? (IFD_EXE_int ? 4 : 3) : 0;
exe_res_sp_mod_r <= exe_ifd_redirect_r;
exe_res_sp_r <= SP_r - 2;
end
`GRP____: begin
end
endcase
exe_res_hl_mod_r <= IFD_EXE_op[7:0] == 8'h22 || IFD_EXE_op[7:0] == 8'h2A || IFD_EXE_op[7:0] == 8'h32 || IFD_EXE_op[7:0] == 8'h3A;
exe_res_hl_r <= IFD_EXE_op[4] ? `HL_r - 1 : `HL_r + 1;
// memory operations
exe_mem_req_r <= ~cpu_ireset_r & CLK_BUS_EDGE;
// force MSB -> LSB order for all memory operations to simplify 8/16b sequencing.
// LD (+1) +0
// ST (+1) +0
// PUSH/CALL/RST -1 -2
// POP/RET +1 +0
// LD-OP-ST +0 +0
exe_mem_addr_mod_r <= ((exe_stage[1] & ~exe_loadopstore) ? 1 : 0) + ((IFD_EXE_decode[`DEC_DST] == `OPR_SP) ? -2 : 0);
if (MCT_EXE_rsp_val & ~EXE_MCT_req_wr) if (exe_stage[1] & ~exe_loadopstore) exe_mem_data_r[15:8] <= MCT_data; else exe_mem_data_r[7:0] <= MCT_data;
// op completion and pipe advance
exe_complete_r <= IFD_EXE_valid & ~|exe_stage;
exe_advance_r <= IFD_EXE_valid & (~exe_complete_r | DBG_EXE_step & ~exe_stall);
exe_ready_r <= ~IFD_EXE_valid | (exe_complete_r & ~exe_stall & DBG_EXE_step);
// operand read
case (IFD_EXE_decode[`DEC_SRC])
//`OPR_I : exe_src_r <= 0;
`OPR_PC : exe_src_r[15:0] <= IFD_EXE_pc_next;
`OPR_S8 : exe_src_r[15:0] <= {{8{IFD_EXE_op[15]}},IFD_EXE_op[15:8]};
`OPR_U16: exe_src_r[15:0] <= IFD_EXE_op[23:8];
`OPR_BC : exe_src_r[15:0] <= `BC_r;
`OPR_DE : exe_src_r[15:0] <= `DE_r;
`OPR_SP : exe_src_r[15:0] <= SP_r;
`OPR_AF : exe_src_r[15:0] <= `AF_r;
`OPR_B : exe_src_r[15:0] <= {8'h0,B_r};
`OPR_C : exe_src_r[15:0] <= {8'h0,C_r};
`OPR_D : exe_src_r[15:0] <= {8'h0,D_r};
`OPR_E : exe_src_r[15:0] <= {8'h0,E_r};
`OPR_H : exe_src_r[15:0] <= {8'h0,H_r};
`OPR_L : exe_src_r[15:0] <= {8'h0,L_r};
`OPR_HL : exe_src_r[15:0] <= `HL_r;
`OPR_A : exe_src_r[15:0] <= {8'h0,A_r};
endcase
// operand read
case (IFD_EXE_decode[`DEC_DST])
//`OPR_I : exe_src_r <= 0;
`OPR_PC : exe_dst_r[15:0] <= IFD_EXE_pc_next;
`OPR_S8 : exe_dst_r[15:0] <= {{8{IFD_EXE_op[15]}},IFD_EXE_op[15:8]};
`OPR_U16: exe_dst_r[15:0] <= IFD_EXE_op[23:8];
`OPR_BC : exe_dst_r[15:0] <= `BC_r;
`OPR_DE : exe_dst_r[15:0] <= `DE_r;
`OPR_SP : exe_dst_r[15:0] <= SP_r;
`OPR_AF : exe_dst_r[15:0] <= `AF_r;
`OPR_B : exe_dst_r[15:0] <= {8'h0,B_r};
`OPR_C : exe_dst_r[15:0] <= {8'h0,C_r};
`OPR_D : exe_dst_r[15:0] <= {8'h0,D_r};
`OPR_E : exe_dst_r[15:0] <= {8'h0,E_r};
`OPR_H : exe_dst_r[15:0] <= {8'h0,H_r};
`OPR_L : exe_dst_r[15:0] <= {8'h0,L_r};
`OPR_HL : exe_dst_r[15:0] <= `HL_r;
`OPR_A : exe_dst_r[15:0] <= {8'h0,A_r};
endcase
// condition code read
exe_cc_r <= F_r;
// debug writes
if (REG_req_dbg) begin
case (REG_address)
8'h60: if (reg_src_r) A_r <= REG_req_data;
8'h61: if (reg_src_r) F_r[7:4] <= REG_req_data[7:4];
8'h62: if (reg_src_r) B_r <= REG_req_data;
8'h63: if (reg_src_r) C_r <= REG_req_data;
8'h64: if (reg_src_r) D_r <= REG_req_data;
8'h65: if (reg_src_r) E_r <= REG_req_data;
8'h66: if (reg_src_r) H_r <= REG_req_data;
8'h67: if (reg_src_r) L_r <= REG_req_data;
8'h68: if (reg_src_r) SP_r[7:0] <= REG_req_data;
8'h69: if (reg_src_r) SP_r[15:8] <= REG_req_data;
//8'h6A:
//8'h6B:
8'h6C: if (reg_src_r) exe_ime_r <= REG_req_data[0];
endcase
end
end
//-------------------------------------------------------------------
// DMA
//-------------------------------------------------------------------
parameter
ST_DMA_IDLE = 4'b0001,
ST_DMA_READ = 4'b0010,
ST_DMA_READ_WAIT = 4'b0100,
ST_DMA_WRITE = 4'b1000;
reg [3:0] dma_state_r;
reg [7:0] dma_addr_r;
reg dma_req_r;
reg dma_src_r;
reg [7:0] dma_data_r;
assign DMA_SYS_active = ~|(dma_state_r & ST_DMA_IDLE) & ~dma_src_r;
assign DMA_VRAM_active = ~|(dma_state_r & ST_DMA_IDLE) & dma_src_r;
assign DMA_active = DMA_SYS_active | DMA_VRAM_active;
assign DMA_req_val = |(dma_state_r & ST_DMA_READ_WAIT) & dma_req_r;
assign DMA_address = {REG_DMA_r,dma_addr_r};
assign DMA_OAM_req_val = |(dma_state_r & ST_DMA_WRITE);
assign DMA_OAM_address = dma_addr_r;
assign DMA_OAM_req_data = dma_data_r;
assign HLT_DMA_rsp = HLT_REQ_sync & ~DMA_active;
always @(posedge CLK) begin
if (cpu_ireset_r) begin
dma_state_r <= ST_DMA_IDLE;
dma_req_r <= 0;
end
else begin
dma_src_r <= (REG_DMA_r[7:5] == 3'b100) ? 1 : 0;
case (dma_state_r)
ST_DMA_IDLE: begin
dma_addr_r <= 0;
// sync start of DMA request to BUS edge
if (REG_DMA_start & CLK_BUS_EDGE) dma_state_r <= ST_DMA_READ;
end
ST_DMA_READ: begin
if (CLK_BUS_EDGE & ~EXE_DMA_halt) begin
// sync to one read/write pair per cycle
dma_req_r <= 1;
dma_state_r <= ST_DMA_READ_WAIT;
end
end
ST_DMA_READ_WAIT: begin
dma_req_r <= 0;
dma_data_r <= dma_src_r ? VRAM_data : SYS_RDDATA;
// address available 1 cycle early and we have the VRAM bus so not necessary to wait an extra clock
if (~dma_req_r & (dma_src_r | SYS_RDY)) dma_state_r <= ST_DMA_WRITE;
end
ST_DMA_WRITE: begin
dma_addr_r <= dma_addr_r + 1;
dma_state_r <= (dma_addr_r[7] & dma_addr_r[4] & &dma_addr_r[3:0]) ? ST_DMA_IDLE : ST_DMA_READ;
end
endcase
end
end
//-------------------------------------------------------------------
// PPU
//-------------------------------------------------------------------
wire vram_wren = DMA_VRAM_active ? 0 : PPU_VRAM_active ? 0 : MCT_VRAM_wren;
wire [12:0] vram_address = DMA_VRAM_active ? DMA_address[12:0] : PPU_VRAM_active ? PPU_VRAM_address : MCT_VRAM_address;
wire [7:0] vram_rddata;
wire [7:0] vram_wrdata = MCT_VRAM_data;
wire dbg_vram_wren;
wire [12:0] dbg_vram_address;
wire [7:0] dbg_vram_rddata;
wire [7:0] dbg_vram_wrdata;
`ifdef MK2
vram vram (
.clka(CLK), // input clka
.wea(vram_wren), // input [0 : 0] wea
.addra(vram_address), // input [12 : 0] addra
.dina(vram_wrdata), // input [7 : 0] dina
.douta(vram_rddata), // output [7 : 0] douta
.clkb(CLK), // input clkb
.web(dbg_vram_wren), // input [0 : 0] web
.addrb(dbg_vram_address), // input [12 : 0] addrb
.dinb(dbg_vram_wrdata), // input [7 : 0] dinb
.doutb(dbg_vram_rddata) // output [7 : 0] doutb
);
`endif
`ifdef MK3
vram vram (
.clock(CLK), // input clka
.wren_a(vram_wren), // input [0 : 0] wea
.address_a(vram_address), // input [12 : 0] addra
.data_a(vram_wrdata), // input [7 : 0] dina
.q_a(vram_rddata), // output [7 : 0] douta
.wren_b(dbg_vram_wren), // input [0 : 0] web
.address_b(dbg_vram_address), // input [12 : 0] addrb
.data_b(dbg_vram_wrdata), // input [7 : 0] dinb
.q_b(dbg_vram_rddata) // output [7 : 0] doutb
);
`endif
wire oam_wren = DMA_active ? DMA_OAM_req_val : PPU_OAM_active ? 0 : MCT_OAM_wren;
wire [7:0] oam_address = DMA_active ? DMA_OAM_address : PPU_OAM_active ? PPU_OAM_address : MCT_OAM_address;
wire [7:0] oam_rddata;
wire [7:0] oam_wrdata = DMA_active ? DMA_OAM_req_data : MCT_OAM_data;
wire dbg_oam_wren;
wire [7:0] dbg_oam_address;
wire [7:0] dbg_oam_rddata;
wire [7:0] dbg_oam_wrdata;
`ifdef MK2
oam oam (
.clka(CLK), // input clka
.wea(oam_wren), // input [0 : 0] wea
.addra(oam_address), // input [7 : 0] addra
.dina(oam_wrdata), // input [7 : 0] dina
.douta(oam_rddata), // output [7 : 0] douta
.clkb(CLK), // input clkb
.web(dbg_oam_wren), // input [0 : 0] web
.addrb(dbg_oam_address), // input [7 : 0] addrb
.dinb(dbg_oam_wrdata), // input [7 : 0] dinb
.doutb(dbg_oam_rddata) // output [7 : 0] doutb
);
`endif
`ifdef MK3
oam oam (
.clock(CLK), // input clka
.wren_a(oam_wren), // input [0 : 0] wea
.address_a(oam_address), // input [7 : 0] addra
.data_a(oam_wrdata), // input [7 : 0] dina
.q_a(oam_rddata), // output [7 : 0] douta
.wren_b(dbg_oam_wren), // input [0 : 0] web
.address_b(dbg_oam_address), // input [7 : 0] addrb
.data_b(dbg_oam_wrdata), // input [7 : 0] dinb
.q_b(dbg_oam_rddata) // output [7 : 0] doutb
);
`endif
`define MODE_H 0 // HBLANK
`define MODE_V 1 // VBLANK
`define MODE_O 2 // OAM READ
`define MODE_D 3 // DISPLAY WRITE
`define OBJ_FIFO_PIXEL 1:0
`define OBJ_FIFO_PRI 2:2
`define OBJ_FIFO_PAL 3:3
parameter
ST_PPU_OFF = 13'b0000000000001,
ST_PPU_FRM_NEW = 13'b0000000000010,
ST_PPU_OAM_NEW = 13'b0000000000100,
ST_PPU_OAM_POS = 13'b0000000001000,
ST_PPU_PIX_NEW = 13'b0000000010000,
ST_PPU_PIX_MAP = 13'b0000000100000,
ST_PPU_PIX_DT0 = 13'b0000001000000,
ST_PPU_PIX_DT1 = 13'b0000010000000,
ST_PPU_PIX_OB0 = 13'b0000100000000,
ST_PPU_PIX_OB1 = 13'b0001000000000,
ST_PPU_PIX_OB2 = 13'b0010000000000,
ST_PPU_HBL = 13'b0100000000000,
ST_PPU_VBL = 13'b1000000000000;
reg [12:0] ppu_state_r;
reg [8:0] ppu_dot_ctr_r;
reg [5:0] ppu_tile_ctr_r; // 32 tiles with 8 pixels in a 256 pixel source tile data. extra bit covers negative values
reg [7:0] ppu_pix_ctr_r;
reg [7:0] ppu_scanline_r;
wire ppu_vram_active = |(ppu_state_r & (ST_PPU_PIX_NEW | ST_PPU_PIX_MAP | ST_PPU_PIX_DT0 | ST_PPU_PIX_DT1 | ST_PPU_PIX_OB0 | ST_PPU_PIX_OB1 | ST_PPU_PIX_OB2));
wire ppu_oam_active = ~|(ppu_state_r & (ST_PPU_OFF | ST_PPU_HBL | ST_PPU_VBL));
assign PPU_vblank = |(ppu_state_r & ST_PPU_VBL);
reg ppu_first_frame_r;
reg [7:0] ppu_oam_address_r;
reg [7:0] ppu_oam_rddata_r;
reg [7:0] ppu_oam_data_r;
reg [12:0] ppu_vram_address_r;
reg [7:0] ppu_vram_data_r;
// OAM lookup table
`ifdef SGB_SPR_INCREASE
`define NUM_OAM_LUT 16
reg [5:0] ppu_oam_lut_cnt_r;
wire ppu_feat_spr_increase = FEAT[`SGB_FEAT_SPR_INCREASE];
wire ppu_oam_lut_full = ppu_feat_spr_increase ? ppu_oam_lut_cnt_r[4] : (ppu_oam_lut_cnt_r[3] & ppu_oam_lut_cnt_r[1]);
`else
`define NUM_OAM_LUT 10
reg [3:0] ppu_oam_lut_cnt_r;
wire ppu_oam_lut_full = ppu_oam_lut_cnt_r[3] & ppu_oam_lut_cnt_r[1];
`endif
reg [3:0] ppu_oam_lut_ypos_r[`NUM_OAM_LUT-1:0];
reg [7:0] ppu_oam_lut_xpos_r[`NUM_OAM_LUT-1:0];
reg [5:0] ppu_oam_lut_index_r[`NUM_OAM_LUT-1:0];
wire ppu_oam_end = ppu_oam_address_r[7] & &ppu_oam_address_r[4:2]; // 159 + 1 = 160 bytes (40 entries of 4 bytes each)
// window
reg [7:0] ppu_pix_win_line_r;
reg [4:0] ppu_pix_win_tile_r;
wire [8:0] ppu_pix_wx_m7 = {1'b0,REG_WX_r} - 7;
wire ppu_pix_win_active = REG_LCDC_r[`LCDC_WD_EN] && ppu_scanline_r >= REG_WY_r && $signed(ppu_tile_ctr_r[5:0]) >= $signed(ppu_pix_wx_m7[8:3]);
reg ppu_pix_win_active_r;
wire [7:0] ppu_pix_row = ppu_scanline_r + REG_SCY_r;
wire [4:0] ppu_pix_col = ppu_tile_ctr_r[4:0] + REG_SCX_r[7:3] + (|REG_SCX_r[2:0] ? 1 : 0);
wire [7:0] ppu_pix_win_row = ppu_pix_win_line_r;
wire [4:0] ppu_pix_win_col = ppu_pix_win_tile_r[4:0];
wire [1:0] ppu_tile_ctr_next = ppu_tile_ctr_r[1:0] + 1;
wire ppu_tile_dummy = ppu_tile_ctr_r[4] & ppu_tile_ctr_r[3];
wire ppu_pix_end = ppu_pix_ctr_r[7] & ppu_pix_ctr_r[5];
wire ppu_dot_edge = CLK_CPU_EDGE;
wire ppu_dot_end = &ppu_dot_ctr_r[8:6] & &ppu_dot_ctr_r[2:0]; // 455+1 = 456 dots
wire ppu_vis_end = ppu_scanline_r[7] & &ppu_scanline_r[3:0]; // 143+1 = 144 lines
wire ppu_disp_end = ppu_scanline_r[7] & ppu_scanline_r[4] & ppu_scanline_r[3] & ppu_scanline_r[0]; // 153+1 = 154 lines
wire ppu_tile_end = ~ppu_tile_dummy & ppu_tile_ctr_r[4] & &ppu_tile_ctr_r[1:0]; // 159+1 = 160 pixels, 19+1 = 20 tiles
wire ppu_fifo_data = ~ppu_tile_dummy && ppu_pix_ctr_r[5:3] != ppu_tile_ctr_r[2:0] && ~ppu_pix_end;
wire [2:0] ppu_bgw_fifo_index_start = (ppu_pix_win_active_r ? REG_WX_r[2:0] : ~REG_SCX_r[2:0]) + 1;
reg [1:0] ppu_bgw_fifo_r[31:0]; // 4 [tiles] * 8 [pixels/tile] * 2 [bpp]
reg [7:0] ppu_pix_bgw_data_r;
reg [3:0] ppu_obj_fifo_r[31:0]; // 4 [tiles] * 8 [pixels/tile] * 1+1+2[bpp,pri,pal]
reg [7:0] ppu_obj_fifo_transparent_r;
reg [7:0] ppu_pix_obj_data_r;
wire ppu_hsync = ppu_dot_edge & ppu_dot_end;
wire ppu_vsync = ppu_dot_edge & ppu_dot_end & ppu_disp_end;
reg ppu_pix_phase_r;
reg ppu_vblank_pulse_r;
reg ppu_vblank_seen_r;
reg ppu_stat_active_r;
reg [7:0] ppu_stat_match_r;
reg ppu_dot_start_r;
reg ppu_stat_write_r;
// OAM LUT lookup operation
reg ppu_oam_lut_found;
reg [3:0] ppu_oam_lut_match;
always @(ppu_oam_lut_xpos_r[0],ppu_oam_lut_xpos_r[1],ppu_oam_lut_xpos_r[2],ppu_oam_lut_xpos_r[3],ppu_oam_lut_xpos_r[4],
ppu_oam_lut_xpos_r[5],ppu_oam_lut_xpos_r[6],ppu_oam_lut_xpos_r[7],ppu_oam_lut_xpos_r[8],ppu_oam_lut_xpos_r[9],
ppu_tile_ctr_r) begin
ppu_oam_lut_match = 4'hF;
ppu_oam_lut_found = 0;
for (i = 0; i < `NUM_OAM_LUT; i = i + 1) begin
if (ppu_oam_lut_xpos_r[i][7:3] == ppu_tile_ctr_r[4:0] && ~ppu_oam_lut_found) begin
ppu_oam_lut_match = i[3:0];
ppu_oam_lut_found = 1;
end
end
end
reg ppu_pix_oam_lut_found_r;
reg [3:0] ppu_pix_oam_lut_match_r;
reg [7:0] ppu_pix_oam_tile_num_r;
reg [7:0] ppu_pix_oam_flag_r;
reg [7:0] ppu_oam_obj_xpos_r;
wire [3:0] ppu_pix_obj_row = (ppu_scanline_r[3:0] - ppu_oam_lut_ypos_r[ppu_pix_oam_lut_match_r][3:0]) ^ {4{ppu_pix_oam_flag_r[6]}};
reg ppu_bgw_fifo_wr_req_r;
reg [4:0] ppu_bgw_fifo_wr_req_index_r;
reg [1:0] ppu_bgw_fifo_wr_req_data_r[7:0];
reg ppu_bgw_fifo_wr_active_r;
reg [4:0] ppu_bgw_fifo_wr_index_r;
reg [2:0] ppu_bgw_fifo_wr_cnt_r;
reg [1:0] ppu_bgw_fifo_wr_data_r;
reg ppu_obj_fifo_wr_req_r;
reg [4:0] ppu_obj_fifo_wr_req_index_r;
reg [3:0] ppu_obj_fifo_wr_req_data_r[7:0];
reg ppu_obj_fifo_wr_active_r;
reg [4:0] ppu_obj_fifo_wr_index_r;
reg [2:0] ppu_obj_fifo_wr_cnt_r;
reg [3:0] ppu_obj_fifo_wr_data_r;
reg ppu_obj_fifo_wr_req_clear_r;
assign VRAM_data = vram_rddata;
assign OAM_data = oam_rddata;
assign PPU_VRAM_active = ppu_vram_active;
assign PPU_VRAM_address = ppu_vram_address_r;
assign PPU_OAM_active = ppu_oam_active;
assign PPU_OAM_address = ppu_oam_address_r;
assign PPU_REG_vblank = ppu_vblank_pulse_r;
assign PPU_REG_lcd_stat = ~ppu_stat_active_r & |ppu_stat_match_r;
assign PPU_MCT_vram_active = ppu_vram_active;
assign PPU_MCT_oam_active = ppu_oam_active;
wire [1:0] ppu_bgw_index = ppu_bgw_fifo_r[ppu_pix_ctr_r[4:0]][1:0];
wire [1:0] ppu_obj_index = ppu_obj_fifo_r[ppu_pix_ctr_r[4:0]][1:0];
reg ppu_obj_pal;
reg ppu_obj_pri;
// Xilinx compiler can silently fail if we don't expand out the obj fifo reads in a case statement.
always @(ppu_pix_ctr_r,
ppu_obj_fifo_r[0 ][3:2],ppu_obj_fifo_r[1 ][3:2],ppu_obj_fifo_r[2 ][3:2],ppu_obj_fifo_r[3 ][3:2],ppu_obj_fifo_r[4 ][3:2],ppu_obj_fifo_r[5 ][3:2],ppu_obj_fifo_r[6 ][3:2],ppu_obj_fifo_r[7 ][3:2],
ppu_obj_fifo_r[8 ][3:2],ppu_obj_fifo_r[9 ][3:2],ppu_obj_fifo_r[10][3:2],ppu_obj_fifo_r[11][3:2],ppu_obj_fifo_r[12][3:2],ppu_obj_fifo_r[13][3:2],ppu_obj_fifo_r[14][3:2],ppu_obj_fifo_r[15][3:2],
ppu_obj_fifo_r[16][3:2],ppu_obj_fifo_r[17][3:2],ppu_obj_fifo_r[18][3:2],ppu_obj_fifo_r[19][3:2],ppu_obj_fifo_r[20][3:2],ppu_obj_fifo_r[21][3:2],ppu_obj_fifo_r[22][3:2],ppu_obj_fifo_r[23][3:2],
ppu_obj_fifo_r[24][3:2],ppu_obj_fifo_r[25][3:2],ppu_obj_fifo_r[26][3:2],ppu_obj_fifo_r[27][3:2],ppu_obj_fifo_r[28][3:2],ppu_obj_fifo_r[29][3:2],ppu_obj_fifo_r[30][3:2],ppu_obj_fifo_r[31][3:2]
) begin
case (ppu_pix_ctr_r[4:0])
0: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[0 ][3:2];
1: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[1 ][3:2];
2: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[2 ][3:2];
3: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[3 ][3:2];
4: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[4 ][3:2];
5: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[5 ][3:2];
6: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[6 ][3:2];
7: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[7 ][3:2];
8: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[8 ][3:2];
9: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[9 ][3:2];
10: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[10][3:2];
11: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[11][3:2];
12: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[12][3:2];
13: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[13][3:2];
14: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[14][3:2];
15: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[15][3:2];
16: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[16][3:2];
17: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[17][3:2];
18: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[18][3:2];
19: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[19][3:2];
20: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[20][3:2];
21: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[21][3:2];
22: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[22][3:2];
23: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[23][3:2];
24: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[24][3:2];
25: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[25][3:2];
26: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[26][3:2];
27: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[27][3:2];
28: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[28][3:2];
29: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[29][3:2];
30: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[30][3:2];
31: {ppu_obj_pri,ppu_obj_pal} = ppu_obj_fifo_r[31][3:2];
endcase
end
// merge background and object indices and derive pixel values
assign PPU_PIXEL = HLT_REQ_sync ? 2'b00
: (~|ppu_obj_index | (|ppu_bgw_index & ppu_obj_pri)) ? ( (ppu_bgw_index == 0) ? REG_BGP_r[1:0]
: (ppu_bgw_index == 1) ? REG_BGP_r[3:2]
: (ppu_bgw_index == 2) ? REG_BGP_r[5:4]
: REG_BGP_r[7:6]
)
: ( (ppu_obj_index == 0) ? (ppu_obj_pal ? REG_OBP1_r[1:0] : REG_OBP0_r[1:0])
: (ppu_obj_index == 1) ? (ppu_obj_pal ? REG_OBP1_r[3:2] : REG_OBP0_r[3:2])
: (ppu_obj_index == 2) ? (ppu_obj_pal ? REG_OBP1_r[5:4] : REG_OBP0_r[5:4])
: (ppu_obj_pal ? REG_OBP1_r[7:6] : REG_OBP0_r[7:6])
);
assign PPU_DOT_EDGE = ppu_dot_edge;
assign PPU_HSYNC_EDGE = ppu_hsync;
assign PPU_VSYNC_EDGE = ppu_vsync;
assign PPU_PIXEL_VALID = ppu_fifo_data;
reg dbg_state_valid_r;
reg [7:0] dbg_reg_ly_r;
reg [8:0] dbg_dot_ctr_r;
reg [8:0] dbg_dot_ctr_next_r;
reg dbg_oam_active_r;
reg dbg_vram_active_r;
reg dbg_dma_active_r;
reg [7:0] dbg_ppu_stat_match_r;
reg [8:0] dbg_ppu_stat_dot_ctr_r;
always @(posedge CLK) begin
if (cpu_ireset_r) begin
REG_STAT_r[`STAT_MODE] <= `MODE_H;
REG_STAT_r[`STAT_LYC_MATCH] <= 0;
REG_LY_r <= 0;
ppu_scanline_r <= 0;
ppu_tile_ctr_r <= 0;
ppu_pix_ctr_r <= 0;
ppu_dot_ctr_r <= 0;
ppu_state_r <= ST_PPU_OFF;
ppu_vblank_pulse_r <= 0;
ppu_stat_active_r <= 0;
ppu_stat_match_r <= 0;
ppu_bgw_fifo_wr_req_r <= 0;
ppu_bgw_fifo_wr_active_r <= 0;
ppu_obj_fifo_wr_req_r <= 0;
ppu_obj_fifo_wr_active_r <= 0;
ppu_stat_write_r <= 0;
dbg_dot_ctr_next_r <= 0;
dbg_dot_ctr_r <= 0;
end
else begin
// The active scanline pixel output is composed of 3 distinct phases:
// - OAM test and buffer (~80 dot clocks)
// - pixel output (166-180 dot clocks)
// - h-blank (remaining dot clocks in 456 scanline)
//
// A VRAM access takes 2 dot clocks and an OAM access takes 1 dot clock.
//
// The phases of the display rendering are:
// 0 - hblank/display disable
// 1 - vblank
// 2 - OAM testing
// 3 - display
//
// Sequencing:
// - [OFF->VBL] The display is enabled by the sofware during the vblank region. This is the initial condition.
//
// - [VBL->OAM] OAM testing is performed to find up to 10 matching valid sprites in the scanline
// - Tests are performed on ypos and need to account for 8x8 vs 8x16 size.
// - There are 40 sprites to test and OAM is assumed to take 1 dot clock to read. This is separated into a
// ypos read clock followed by a test/xpos read clock.
// - A lookup table is kept with xpos and a pointer to the associated OAM entry.
// - [OAM->PIX] PIX reads the BG or window MAP, 2 bytes of 8 pixels, and then tests OAM matches on the current row.
// - [PIX->HBL] HBL is when we are in hblank
// - [HBL->OAM] From HBL we can transition back to OAM if the new line is visible
// - [HBL->VBL] From HBL we can transition to VBL (vblank) if the visible lines are complete
// debug
if (CLK_BUS_EDGE) begin
if (exe_advance_r) begin
dbg_state_valid_r <= 0;
end
else if (~dbg_state_valid_r) begin
dbg_state_valid_r <= 1;
dbg_reg_ly_r <= REG_LY_r;
{dbg_dot_ctr_r,dbg_dot_ctr_next_r} <= {dbg_dot_ctr_next_r,ppu_dot_ctr_r};
dbg_oam_active_r <= PPU_OAM_active;
dbg_vram_active_r <= PPU_VRAM_active;
dbg_dma_active_r <= DMA_active;
end
end
if (REG_req_val && REG_address == 8'h41) ppu_stat_write_r <= 1;
else if (ppu_dot_edge) ppu_stat_write_r <= 0;
// flop match
ppu_pix_oam_lut_match_r <= ppu_oam_lut_match;
ppu_pix_oam_lut_found_r <= ppu_oam_lut_found & ~(ppu_first_frame_r|~REG_LCDC_r[`LCDC_SP_EN] | DMA_active);
ppu_oam_rddata_r <= oam_rddata;
// Xilinx compiler (MK2) can silently fail if we don't expand out the pixel fifo writes in a case statement. Same goes for the packet buffer in ICD and others.
// This results in a lot of code verbosity, but it works.
ppu_bgw_fifo_wr_req_r <= 0;
if (ppu_bgw_fifo_wr_req_r) begin
ppu_bgw_fifo_wr_active_r <= 1;
ppu_bgw_fifo_wr_index_r <= ppu_bgw_fifo_wr_req_index_r;
ppu_bgw_fifo_wr_cnt_r <= 1;
ppu_bgw_fifo_wr_data_r <= ppu_bgw_fifo_wr_req_data_r[0];
end
else if (ppu_bgw_fifo_wr_active_r) begin
case (ppu_bgw_fifo_wr_index_r[4:0])
0: ppu_bgw_fifo_r[0 ] <= ppu_bgw_fifo_wr_data_r;
1: ppu_bgw_fifo_r[1 ] <= ppu_bgw_fifo_wr_data_r;
2: ppu_bgw_fifo_r[2 ] <= ppu_bgw_fifo_wr_data_r;
3: ppu_bgw_fifo_r[3 ] <= ppu_bgw_fifo_wr_data_r;
4: ppu_bgw_fifo_r[4 ] <= ppu_bgw_fifo_wr_data_r;
5: ppu_bgw_fifo_r[5 ] <= ppu_bgw_fifo_wr_data_r;
6: ppu_bgw_fifo_r[6 ] <= ppu_bgw_fifo_wr_data_r;
7: ppu_bgw_fifo_r[7 ] <= ppu_bgw_fifo_wr_data_r;
8: ppu_bgw_fifo_r[8 ] <= ppu_bgw_fifo_wr_data_r;
9: ppu_bgw_fifo_r[9 ] <= ppu_bgw_fifo_wr_data_r;
10: ppu_bgw_fifo_r[10] <= ppu_bgw_fifo_wr_data_r;
11: ppu_bgw_fifo_r[11] <= ppu_bgw_fifo_wr_data_r;
12: ppu_bgw_fifo_r[12] <= ppu_bgw_fifo_wr_data_r;
13: ppu_bgw_fifo_r[13] <= ppu_bgw_fifo_wr_data_r;
14: ppu_bgw_fifo_r[14] <= ppu_bgw_fifo_wr_data_r;
15: ppu_bgw_fifo_r[15] <= ppu_bgw_fifo_wr_data_r;
16: ppu_bgw_fifo_r[16] <= ppu_bgw_fifo_wr_data_r;
17: ppu_bgw_fifo_r[17] <= ppu_bgw_fifo_wr_data_r;
18: ppu_bgw_fifo_r[18] <= ppu_bgw_fifo_wr_data_r;
19: ppu_bgw_fifo_r[19] <= ppu_bgw_fifo_wr_data_r;
20: ppu_bgw_fifo_r[20] <= ppu_bgw_fifo_wr_data_r;
21: ppu_bgw_fifo_r[21] <= ppu_bgw_fifo_wr_data_r;
22: ppu_bgw_fifo_r[22] <= ppu_bgw_fifo_wr_data_r;
23: ppu_bgw_fifo_r[23] <= ppu_bgw_fifo_wr_data_r;
24: ppu_bgw_fifo_r[24] <= ppu_bgw_fifo_wr_data_r;
25: ppu_bgw_fifo_r[25] <= ppu_bgw_fifo_wr_data_r;
26: ppu_bgw_fifo_r[26] <= ppu_bgw_fifo_wr_data_r;
27: ppu_bgw_fifo_r[27] <= ppu_bgw_fifo_wr_data_r;
28: ppu_bgw_fifo_r[28] <= ppu_bgw_fifo_wr_data_r;
29: ppu_bgw_fifo_r[29] <= ppu_bgw_fifo_wr_data_r;
30: ppu_bgw_fifo_r[30] <= ppu_bgw_fifo_wr_data_r;
31: ppu_bgw_fifo_r[31] <= ppu_bgw_fifo_wr_data_r;
endcase
ppu_bgw_fifo_wr_index_r <= ppu_bgw_fifo_wr_index_r + 1;
case (ppu_bgw_fifo_wr_cnt_r[2:0])
0: ppu_bgw_fifo_wr_data_r <= ppu_bgw_fifo_wr_req_data_r[0];
1: ppu_bgw_fifo_wr_data_r <= ppu_bgw_fifo_wr_req_data_r[1];
2: ppu_bgw_fifo_wr_data_r <= ppu_bgw_fifo_wr_req_data_r[2];
3: ppu_bgw_fifo_wr_data_r <= ppu_bgw_fifo_wr_req_data_r[3];
4: ppu_bgw_fifo_wr_data_r <= ppu_bgw_fifo_wr_req_data_r[4];
5: ppu_bgw_fifo_wr_data_r <= ppu_bgw_fifo_wr_req_data_r[5];
6: ppu_bgw_fifo_wr_data_r <= ppu_bgw_fifo_wr_req_data_r[6];
7: ppu_bgw_fifo_wr_data_r <= ppu_bgw_fifo_wr_req_data_r[7];
endcase
ppu_bgw_fifo_wr_cnt_r <= ppu_bgw_fifo_wr_cnt_r + 1;
ppu_bgw_fifo_wr_active_r <= |ppu_bgw_fifo_wr_cnt_r;
end
ppu_obj_fifo_wr_req_r <= 0;
if (ppu_obj_fifo_wr_req_r) begin
ppu_obj_fifo_wr_active_r <= 1;
ppu_obj_fifo_wr_index_r <= ppu_obj_fifo_wr_req_index_r;
ppu_obj_fifo_wr_cnt_r <= 1;
ppu_obj_fifo_wr_data_r <= ppu_obj_fifo_wr_req_data_r[0];
end
else if (ppu_obj_fifo_wr_active_r) begin
case (ppu_obj_fifo_wr_index_r[4:0])
0: if (ppu_obj_fifo_r[0 ][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[0 ][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
1: if (ppu_obj_fifo_r[1 ][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[1 ][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
2: if (ppu_obj_fifo_r[2 ][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[2 ][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
3: if (ppu_obj_fifo_r[3 ][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[3 ][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
4: if (ppu_obj_fifo_r[4 ][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[4 ][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
5: if (ppu_obj_fifo_r[5 ][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[5 ][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
6: if (ppu_obj_fifo_r[6 ][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[6 ][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
7: if (ppu_obj_fifo_r[7 ][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[7 ][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
8: if (ppu_obj_fifo_r[8 ][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[8 ][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
9: if (ppu_obj_fifo_r[9 ][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[9 ][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
10: if (ppu_obj_fifo_r[10][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[10][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
11: if (ppu_obj_fifo_r[11][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[11][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
12: if (ppu_obj_fifo_r[12][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[12][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
13: if (ppu_obj_fifo_r[13][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[13][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
14: if (ppu_obj_fifo_r[14][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[14][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
15: if (ppu_obj_fifo_r[15][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[15][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
16: if (ppu_obj_fifo_r[16][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[16][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
17: if (ppu_obj_fifo_r[17][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[17][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
18: if (ppu_obj_fifo_r[18][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[18][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
19: if (ppu_obj_fifo_r[19][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[19][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
20: if (ppu_obj_fifo_r[20][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[20][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
21: if (ppu_obj_fifo_r[21][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[21][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
22: if (ppu_obj_fifo_r[22][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[22][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
23: if (ppu_obj_fifo_r[23][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[23][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
24: if (ppu_obj_fifo_r[24][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[24][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
25: if (ppu_obj_fifo_r[25][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[25][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
26: if (ppu_obj_fifo_r[26][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[26][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
27: if (ppu_obj_fifo_r[27][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[27][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
28: if (ppu_obj_fifo_r[28][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[28][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
29: if (ppu_obj_fifo_r[29][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[29][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
30: if (ppu_obj_fifo_r[30][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[30][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
31: if (ppu_obj_fifo_r[31][1:0] == 0 || ppu_obj_fifo_wr_req_clear_r) ppu_obj_fifo_r[31][3:0] <= ppu_obj_fifo_wr_data_r[3:0];
endcase
ppu_obj_fifo_wr_index_r <= ppu_obj_fifo_wr_index_r + 1;
case (ppu_obj_fifo_wr_cnt_r[2:0])
0: ppu_obj_fifo_wr_data_r <= ppu_obj_fifo_wr_req_data_r[0];
1: ppu_obj_fifo_wr_data_r <= ppu_obj_fifo_wr_req_data_r[1];
2: ppu_obj_fifo_wr_data_r <= ppu_obj_fifo_wr_req_data_r[2];
3: ppu_obj_fifo_wr_data_r <= ppu_obj_fifo_wr_req_data_r[3];
4: ppu_obj_fifo_wr_data_r <= ppu_obj_fifo_wr_req_data_r[4];
5: ppu_obj_fifo_wr_data_r <= ppu_obj_fifo_wr_req_data_r[5];
6: ppu_obj_fifo_wr_data_r <= ppu_obj_fifo_wr_req_data_r[6];
7: ppu_obj_fifo_wr_data_r <= ppu_obj_fifo_wr_req_data_r[7];
endcase
ppu_obj_fifo_wr_cnt_r <= ppu_obj_fifo_wr_cnt_r + 1;
ppu_obj_fifo_wr_active_r <= |ppu_obj_fifo_wr_cnt_r;
end
// scanline/state rendering datapath
if (ppu_dot_edge & DBG_advance) begin
ppu_pix_phase_r <= 0;
// read pointer advance
if (ppu_fifo_data) ppu_pix_ctr_r <= ppu_pix_ctr_r + 1;
ppu_vblank_pulse_r <= 0;
ppu_stat_active_r <= |ppu_stat_match_r;
if (~ppu_stat_active_r & |ppu_stat_match_r) begin
dbg_ppu_stat_match_r <= ppu_stat_match_r;
dbg_ppu_stat_dot_ctr_r <= ppu_dot_ctr_r;
end
ppu_oam_data_r <= ppu_oam_rddata_r;
case (ppu_state_r)
ST_PPU_OFF : begin
// clear display state
REG_STAT_r[`STAT_MODE] <= `MODE_H;
REG_LY_r <= 0;
ppu_scanline_r <= 0;
ppu_tile_ctr_r <= 0;
ppu_pix_ctr_r <= 0;
ppu_first_frame_r <= 1;
ppu_vblank_seen_r <= 0;
ppu_stat_match_r <= 0;
if (REG_LCDC_r[`LCDC_DS_EN]) ppu_state_r <= ST_PPU_FRM_NEW;
end
ST_PPU_FRM_NEW : begin
// next frame
ppu_pix_win_line_r <= 8'hFF;
// TODO: should we flop WY here for current frame?
REG_STAT_r[`STAT_MODE] <= `MODE_H;
ppu_state_r <= ST_PPU_OAM_NEW;
end
ST_PPU_OAM_NEW : begin
// start of new line
// setup initial address
ppu_oam_address_r <= 0;
// use -16 (instead of -8) in order to put the xpos before the dummy tile for empty entries
for (i = 0; i < `NUM_OAM_LUT; i = i + 1) ppu_oam_lut_xpos_r[i] <= 0-16;
// initialize all entries to be invalid
ppu_oam_lut_cnt_r <= 0;
REG_STAT_r[`STAT_MODE] <= `MODE_O;
// WARNING: this needs to only be one dot cycle to avoid multiple interrupts. Or we need to guard the interrupt with the same condition.
ppu_state_r <= ST_PPU_OAM_POS;
end
ST_PPU_OAM_POS : begin
// read in xpos if ypos is on this line
if (~ppu_oam_lut_full & ppu_pix_phase_r & ~DMA_active) begin
if (ppu_oam_data_r <= (ppu_scanline_r + 16) && (ppu_scanline_r + 16) < (ppu_oam_data_r + (REG_LCDC_r[`LCDC_SP_SIZE] ? 16 : 8))) begin
ppu_oam_lut_ypos_r[ppu_oam_lut_cnt_r] <= ppu_oam_data_r[3:0];
ppu_oam_lut_xpos_r[ppu_oam_lut_cnt_r] <= ppu_oam_rddata_r - (|ppu_oam_rddata_r ? 8 : 16);
ppu_oam_lut_index_r[ppu_oam_lut_cnt_r] <= ppu_oam_address_r[7:2];
ppu_oam_lut_cnt_r <= ppu_oam_lut_cnt_r + 1;
end
end
// calculate new address
ppu_oam_address_r <= ppu_oam_address_r + (ppu_pix_phase_r ? 3 : 1);
if (ppu_oam_end & ppu_pix_phase_r) begin
ppu_state_r <= ST_PPU_PIX_NEW;
end
ppu_pix_phase_r <= ~ppu_pix_phase_r;
end
ST_PPU_PIX_NEW : begin
// new visible scanline
// reset counter/pointer state
// Start at tile -1 to handle scrolling and window offsets
ppu_tile_ctr_r <= 6'h3F; // partial fifo write pointer
ppu_pix_ctr_r <= 0; // fifo read pointer
ppu_pix_win_active_r <= 0;
REG_STAT_r[`STAT_MODE] <= `MODE_D;
ppu_state_r <= ST_PPU_PIX_MAP;
end
ST_PPU_PIX_MAP : begin
// generate map address
ppu_vram_address_r <= ppu_pix_win_active_r ? {1'b1,1'b1,REG_LCDC_r[`LCDC_WD_MAP_SEL],ppu_pix_win_row[7:3],ppu_pix_win_col[4:0]} : {1'b1,1'b1,REG_LCDC_r[`LCDC_BG_MAP_SEL],ppu_pix_row[7:3],ppu_pix_col[4:0]};
ppu_vram_data_r <= vram_rddata;
if (ppu_pix_phase_r) ppu_state_r <= ST_PPU_PIX_DT0;
ppu_pix_phase_r <= ~ppu_pix_phase_r;
end
ST_PPU_PIX_DT0 : begin
// all BG tiles are consecutive 16B and naturally aligned
ppu_vram_address_r <= {(~REG_LCDC_r[`LCDC_BG_TILE_SEL] & ~ppu_vram_data_r[7]),ppu_vram_data_r[7:0],(ppu_pix_win_active_r ? ppu_pix_win_row[2:0] : ppu_pix_row[2:0]),1'b0};
ppu_pix_bgw_data_r <= vram_rddata;
if (ppu_pix_phase_r) ppu_state_r <= ST_PPU_PIX_DT1;
ppu_pix_phase_r <= ~ppu_pix_phase_r;
end
ST_PPU_PIX_DT1 : begin
ppu_oam_address_r <= {ppu_oam_lut_index_r[ppu_pix_oam_lut_match_r],2'b10};
ppu_vram_address_r <= {ppu_vram_address_r[12:1],1'b1};
if (ppu_pix_phase_r) begin
ppu_bgw_fifo_wr_req_r <= 1;
// write bgw fifo with current pixel data
ppu_bgw_fifo_wr_req_index_r <= {ppu_tile_ctr_r[1:0],ppu_bgw_fifo_index_start[2:0]};
for (i = 0; i < 8; i = i + 1) ppu_bgw_fifo_wr_req_data_r[i][0] <= (ppu_first_frame_r|~REG_LCDC_r[`LCDC_BG_EN]) ? 1'b0 : ppu_pix_bgw_data_r[7-i];
for (i = 0; i < 8; i = i + 1) ppu_bgw_fifo_wr_req_data_r[i][1] <= (ppu_first_frame_r|~REG_LCDC_r[`LCDC_BG_EN]) ? 1'b0 : vram_rddata[7-i];
// clear object fifo for next set of sprite tiles
ppu_obj_fifo_wr_req_r <= 1;
ppu_obj_fifo_wr_req_clear_r <= 1;
ppu_obj_fifo_wr_req_index_r <= {ppu_tile_ctr_next[1:0],3'h0};
for (i = 0; i < 8; i = i + 1) ppu_obj_fifo_wr_req_data_r[i][3:0] <= 0;
end
if (ppu_pix_phase_r) begin
// determine if there is a transition to window. If so, render the new active mode on top of the old by repeating the BGW tile fetch
ppu_pix_win_active_r <= ppu_pix_win_active;
if (ppu_pix_win_active_r ^ ppu_pix_win_active) ppu_pix_win_line_r <= ppu_pix_win_line_r + 1;
if (ppu_pix_win_active_r ^ ppu_pix_win_active) ppu_pix_win_tile_r <= 0;
ppu_state_r <= (ppu_pix_win_active_r ^ ppu_pix_win_active) ? ST_PPU_PIX_MAP : ST_PPU_PIX_OB0;
end
ppu_pix_phase_r <= ~ppu_pix_phase_r;
end
ST_PPU_PIX_OB0 : begin
ppu_oam_obj_xpos_r <= ppu_oam_lut_xpos_r[ppu_pix_oam_lut_match_r];
ppu_oam_address_r <= {ppu_oam_address_r[7:1],1'b1};
if (~ppu_pix_phase_r) ppu_pix_oam_tile_num_r <= ppu_oam_rddata_r; else ppu_pix_oam_flag_r <= ppu_oam_rddata_r;
if (ppu_pix_phase_r) begin
if (~ppu_pix_oam_lut_found_r) ppu_tile_ctr_r <= ppu_tile_ctr_r + 1;
if (~ppu_pix_oam_lut_found_r) ppu_pix_win_tile_r <= ppu_pix_win_tile_r + 1;
ppu_state_r <= ppu_pix_oam_lut_found_r ? ST_PPU_PIX_OB1 : (ppu_tile_end ? ST_PPU_HBL : ST_PPU_PIX_MAP);
end
ppu_pix_phase_r <= ~ppu_pix_phase_r;
end
ST_PPU_PIX_OB1 : begin
ppu_vram_address_r <= {1'b0,ppu_pix_oam_tile_num_r[7:1],(REG_LCDC_r[`LCDC_SP_SIZE] ? ppu_pix_obj_row[3] : ppu_pix_oam_tile_num_r[0]),ppu_pix_obj_row[2:0],1'b0};
// read second half of tile
ppu_pix_obj_data_r <= vram_rddata;
if (ppu_pix_phase_r) begin
ppu_state_r <= ST_PPU_PIX_OB2;
end
ppu_pix_phase_r <= ~ppu_pix_phase_r;
end
ST_PPU_PIX_OB2 : begin
ppu_vram_address_r <= {ppu_vram_address_r[12:1],1'b1};
// clear match for second phase
if (~ppu_pix_phase_r) ppu_oam_lut_xpos_r[ppu_pix_oam_lut_match_r] <= 0-16;
if (ppu_pix_phase_r) begin
// get address of next match
ppu_oam_address_r <= {ppu_oam_lut_index_r[ppu_pix_oam_lut_match_r],2'b10};
ppu_obj_fifo_wr_req_r <= 1;
ppu_obj_fifo_wr_req_clear_r <= 0;
ppu_obj_fifo_wr_req_index_r <= ppu_oam_obj_xpos_r[4:0];
for (i = 0; i < 8; i = i + 1) ppu_obj_fifo_wr_req_data_r[i][0] <= ppu_pix_oam_flag_r[5] ? ppu_pix_obj_data_r[i] : ppu_pix_obj_data_r[7-i];
for (i = 0; i < 8; i = i + 1) ppu_obj_fifo_wr_req_data_r[i][1] <= ppu_pix_oam_flag_r[5] ? vram_rddata[i] : vram_rddata[7-i];
for (i = 0; i < 8; i = i + 1) ppu_obj_fifo_wr_req_data_r[i][2] <= ppu_pix_oam_flag_r[4];
for (i = 0; i < 8; i = i + 1) ppu_obj_fifo_wr_req_data_r[i][3] <= ppu_pix_oam_flag_r[7];
ppu_state_r <= ST_PPU_PIX_OB0;
end
ppu_pix_phase_r <= ~ppu_pix_phase_r;
end
ST_PPU_HBL : begin
if (~ppu_fifo_data) begin
ppu_tile_ctr_r <= 0;
ppu_pix_ctr_r <= 0;
// TODO: late timer interrupt causes us to miss MODE_D during stat interrupt in PBF. Check if dot clock count is larger than some amount
// Need to look at potential problems:
// PBD wanted it pushed another bus clock (260->264).
// 1) timer interrupt starting at the very last cycle is not supposed to happen
// 2) draw mode needs to be extended by a few clocks
// 3) interrupts are supposed to be faster. e.g. is taking interrupt actually 4 bus clocks like RST (should solve the problem)
if (ppu_dot_ctr_r >= 264) REG_STAT_r[`STAT_MODE] <= `MODE_H; // H-Blank mode starts when the fifos have been consumed
end
ppu_vblank_seen_r <= 0;
if (ppu_dot_end) begin
ppu_state_r <= ppu_vis_end ? ST_PPU_VBL : ST_PPU_OAM_NEW;
end
end
ST_PPU_VBL : begin
REG_STAT_r[`STAT_MODE] <= `MODE_V;
if (~ppu_vblank_seen_r & ppu_dot_ctr_r[0]) begin
// assert on dot clock 2
ppu_vblank_pulse_r <= 1;
ppu_vblank_seen_r <= 1;
end
ppu_first_frame_r <= 0;
if (ppu_dot_end) begin
if (ppu_disp_end) ppu_state_r <= ST_PPU_FRM_NEW;
end
end
endcase
if (~|(ppu_state_r & ST_PPU_OFF)) begin
// It's possible for a write to happen on the last dot cycle which will cause us to miss a 1->0->1 transition.
//
// dot clk
// 0 - LY_r
// 1 - match
// 2 - ppu_stat_active_r[0]
// 3 - IF/earliest interrupt point
// 3+? - Wait for current instruction to finish. 4 * (0-6)
// 3+?+20 - +20 = 5 * 4 dot clocks to take interrupt
// P-M breaks if the transition to 0 on line 153 happens too early.
// BMF expects REG_LY_r to transition from 153->0 early in the line.
if (ppu_dot_end) ppu_scanline_r <= ppu_disp_end ? 0 : ppu_scanline_r + 1;
if (ppu_dot_end) REG_LY_r <= ppu_disp_end ? 0 : REG_LY_r + 1; else if (&ppu_dot_ctr_r[3:2] & ppu_disp_end) REG_LY_r <= 0;
// TODO: is the match clear necessary? Seems like the use case for it originally was actually a STAT write spurious interrupt.
// Definitely can't clear on the last line or it causes problems with double interrupts for LYC==0.
REG_STAT_r[`STAT_LYC_MATCH] <= (REG_LY_r == REG_LYC_r && ~(ppu_dot_end & ~ppu_disp_end)) ? 1 : 0;
// PBF limits IRQs by transitioning between enabled modes on the same cycle (M->O)
// RR expects stat write to trigger spurious interrupt during V-Blank to make menu->game not lock. 144 V-Blank Int -> 147-148 Spurious STAT (V-Blank) Int -> 153 STAT (LY==LYC==0) Int -> 0 STAT (H-Blank) Int
ppu_stat_match_r[`STAT_INT_H_EN] <= (REG_STAT_r[`STAT_INT_H_EN] | ppu_stat_write_r) & |(ppu_state_r & ST_PPU_HBL);
ppu_stat_match_r[`STAT_INT_V_EN] <= (REG_STAT_r[`STAT_INT_V_EN] | ppu_stat_write_r) & |(ppu_state_r & ST_PPU_VBL);
ppu_stat_match_r[`STAT_INT_O_EN] <= (REG_STAT_r[`STAT_INT_O_EN] | ppu_stat_write_r) & ((|ppu_scanline_r ? |(ppu_state_r & ST_PPU_OAM_NEW) : |(ppu_state_r & ST_PPU_FRM_NEW)) | (|(ppu_state_r & ST_PPU_VBL) & ~ppu_vblank_seen_r & ppu_dot_ctr_r[0])); // pulse
ppu_stat_match_r[`STAT_INT_M_EN] <= (REG_STAT_r[`STAT_INT_M_EN] | ppu_stat_write_r) & REG_STAT_r[`STAT_LYC_MATCH];
end
// 1->0 display disable happens imediately. it's only possible to go from 0->1 during vblank
if (~REG_LCDC_r[`LCDC_DS_EN]) ppu_state_r <= ST_PPU_OFF;
ppu_dot_ctr_r <= (ppu_dot_end | |(ppu_state_r & ST_PPU_OFF)) ? 0 : ppu_dot_ctr_r + 1;
end
end
end
//-------------------------------------------------------------------
// APU
//-------------------------------------------------------------------
`ifdef APU
reg [2:0] apu_frame_step_r;
// square1
reg apu_square1_enable_r;
reg [12:0] apu_square1_timer_r;
reg [5:0] apu_square1_length_r;
reg apu_square1_env_enable_r;
reg [2:0] apu_square1_env_timer_r;
reg [3:0] apu_square1_volume_r;
reg [2:0] apu_square1_pos_r;
reg [7:0] apu_square1_duty_r;
reg apu_square1_sweep_enable_r;
reg [3:0] apu_square1_sweep_timer_r;
reg [10:0] apu_square1_sweep_freq_r;
wire [15:0] apu_square1_sweep_freq_next = REG_NR10_r[`NR10_SWEEP_NEG] ? ({5'h00,apu_square1_sweep_freq_r} - ({5'h00,apu_square1_sweep_freq_r} >> REG_NR10_r[`NR10_SWEEP_SHIFT])) : ({5'h00,apu_square1_sweep_freq_r} + ({5'h00,apu_square1_sweep_freq_r} >> REG_NR10_r[`NR10_SWEEP_SHIFT]));
wire [12:0] apu_square1_period = {REG_NR14_r[`NR14_FREQ_MSB],REG_NR13_r[`NR13_FREQ_LSB],2'b00};
wire signed [4:0] apu_square1_output = (apu_square1_enable_r & apu_square1_duty_r[apu_square1_pos_r]) ? {apu_square1_volume_r,1'b0} : 5'h00;
// square2
reg apu_square2_enable_r;
reg [12:0] apu_square2_timer_r;
reg [5:0] apu_square2_length_r;
reg apu_square2_env_enable_r;
reg [2:0] apu_square2_env_timer_r;
reg [3:0] apu_square2_volume_r;
reg [2:0] apu_square2_pos_r;
reg [7:0] apu_square2_duty_r;
wire [12:0] apu_square2_period = {REG_NR24_r[`NR24_FREQ_MSB],REG_NR23_r[`NR23_FREQ_LSB],2'b00};
wire [4:0] apu_square2_output = (apu_square2_enable_r & apu_square2_duty_r[apu_square2_pos_r]) ? {apu_square2_volume_r,1'b0} : 5'h00;
// wave
reg apu_wave_enable_r;
reg [11:0] apu_wave_timer_r;
reg [7:0] apu_wave_length_r;
reg [4:0] apu_wave_pos_r;
reg apu_wave_sample_update_r;
reg [3:0] apu_wave_sample_r;
reg [3:0] apu_wave_data_r;
//reg [4:0] apu_wave_data_shifted_r;
reg [3:0] apu_wave_data_shifted_r;
wire [11:0] apu_wave_period = {REG_NR34_r[`NR34_FREQ_MSB],REG_NR33_r[`NR33_FREQ_LSB],1'b0};
wire [4:0] apu_wave_output = (apu_wave_enable_r & |REG_NR32_r[`NR32_LEVEL]) ? {apu_wave_data_shifted_r,1'b0} : 5'h00;
// noise
reg apu_noise_enable_r;
reg [21:0] apu_noise_timer_r;
reg [5:0] apu_noise_length_r;
reg [2:0] apu_noise_env_timer_r;
reg [3:0] apu_noise_volume_r;
reg [14:0] apu_noise_lfsr_r;
wire [21:0] apu_noise_period = {15'h0000,REG_NR43_r[`NR43_LFSR_DIV],~|REG_NR43_r[`NR43_LFSR_DIV],3'h0} << REG_NR43_r[`NR43_LFSR_SHIFT];
wire [4:0] apu_noise_output = (apu_noise_enable_r & apu_noise_lfsr_r[0]) ? {apu_noise_volume_r,1'b0} : 5'h00;
wire [6:0] apu_data[1:0];
reg [6:0] apu_data_r[1:0];
reg [9:0] apu_data_volume_r[1:0];
assign apu_data[0][6:0] = ( ((apu_square1_output[4:0] & {5{REG_NR51_r[`NR51_SELECT_LEFT_CH0] & REG_NR52_r[`NR52_CONTROL_ENABLE]}}))
+ ((apu_square2_output[4:0] & {5{REG_NR51_r[`NR51_SELECT_LEFT_CH1] & REG_NR52_r[`NR52_CONTROL_ENABLE]}}))
+ ((apu_wave_output[4:0] & {5{REG_NR51_r[`NR51_SELECT_LEFT_CH2] & REG_NR52_r[`NR52_CONTROL_ENABLE]}}))
+ ((apu_noise_output[4:0] & {5{REG_NR51_r[`NR51_SELECT_LEFT_CH3] & REG_NR52_r[`NR52_CONTROL_ENABLE]}}))
);
assign apu_data[1][6:0] = ( ((apu_square1_output[4:0] & {5{REG_NR51_r[`NR51_SELECT_RIGHT_CH0] & REG_NR52_r[`NR52_CONTROL_ENABLE]}}))
+ ((apu_square2_output[4:0] & {5{REG_NR51_r[`NR51_SELECT_RIGHT_CH1] & REG_NR52_r[`NR52_CONTROL_ENABLE]}}))
+ ((apu_wave_output[4:0] & {5{REG_NR51_r[`NR51_SELECT_RIGHT_CH2] & REG_NR52_r[`NR52_CONTROL_ENABLE]}}))
+ ((apu_noise_output[4:0] & {5{REG_NR51_r[`NR51_SELECT_RIGHT_CH3] & REG_NR52_r[`NR52_CONTROL_ENABLE]}}))
);
assign APU_REG_enable = {apu_noise_enable_r, apu_wave_enable_r, apu_square2_enable_r, apu_square1_enable_r};
reg apu_cpu_edge_d1_r;
reg apu_reg_update_r;
reg [7:0] apu_reg_update_address_r;
reg apu_reg_update_nr12_dir_r;
reg apu_reg_update_nr22_dir_r;
reg apu_reg_update_nr14_enable_r;
reg apu_reg_update_nr24_enable_r;
// convert to signed
assign APU_DAT = {~apu_data_volume_r[1][9],apu_data_volume_r[1][8:0],~apu_data_volume_r[0][9],apu_data_volume_r[0][8:0]};
always @(posedge CLK) begin
// Flop audio state since it is a critical path on MK2
for (i = 0; i < 2; i = i + 1) apu_data_r[i] <= apu_data[i];
apu_data_volume_r[0][9:0] <= apu_data_r[0][6:0] * ({7'h00,REG_NR50_r[`NR50_MASTER_LEFT_VOLUME]} + 1);
apu_data_volume_r[1][9:0] <= apu_data_r[1][6:0] * ({7'h00,REG_NR50_r[`NR50_MASTER_RIGHT_VOLUME]} + 1);
apu_wave_data_shifted_r[3:0] <= apu_wave_sample_r[3:0] >> (REG_NR32_r[`NR32_LEVEL] - 1);
case (REG_NR11_r[`NR11_DUTY])
0: apu_square1_duty_r <= 8'b00000001;
1: apu_square1_duty_r <= 8'b10000001;
2: apu_square1_duty_r <= 8'b10000111;
3: apu_square1_duty_r <= 8'b01111110;
endcase
case (REG_NR21_r[`NR21_DUTY])
0: apu_square2_duty_r <= 8'b00000001;
1: apu_square2_duty_r <= 8'b10000001;
2: apu_square2_duty_r <= 8'b10000111;
3: apu_square2_duty_r <= 8'b01111110;
endcase
apu_wave_sample_update_r <= 0;
if (apu_wave_sample_update_r) apu_wave_sample_r <= apu_wave_pos_r[0] ? REG_WAV_r[apu_wave_pos_r[4:1]][3:0] : REG_WAV_r[apu_wave_pos_r[4:1]][7:4];
if (cpu_ireset_r | ~REG_NR52_r[`NR52_CONTROL_ENABLE]) begin
REG_NR10_r <= 8'h00; // FF10
if (cpu_ireset_r) REG_NR11_r[`NR11_LENGTH] <= 0; // FF11
REG_NR11_r[`NR11_DUTY] <= 0;
REG_NR12_r <= 8'h00; // FF12
REG_NR13_r <= 8'h00; // FF13
REG_NR14_r <= 5'h00; // FF14
if (cpu_ireset_r) REG_NR21_r[`NR21_LENGTH] <= 0; // FF16
REG_NR21_r[`NR21_DUTY] <= 0;
REG_NR22_r <= 8'h00; // FF17
REG_NR23_r <= 8'h00; // FF18
REG_NR24_r <= 8'h00; // FF19
REG_NR30_r <= 8'h00; // FF1A
REG_NR31_r <= 8'h00; // FF1B
REG_NR32_r <= 8'h00; // FF1C
REG_NR33_r <= 8'h00; // FF1D
REG_NR34_r <= 8'h00; // FF1E
if (cpu_ireset_r) REG_NR41_r[`NR41_LENGTH] <= 0; // FF16
REG_NR42_r <= 8'h00; // FF21
REG_NR43_r <= 8'h00; // FF22
REG_NR44_r <= 8'h00; // FF23
REG_NR50_r <= 8'h00; // FF24
REG_NR51_r <= 8'h00; // FF25
REG_NR52_r <= 8'h00; // FF26
// RT1 uses uninitialized WAV RAM data. One possible set of SGB2 values used.
if (cpu_ireset_r) begin
REG_WAV_r[0] <= 8'h08;//8'hAC;
REG_WAV_r[1] <= 8'hF7;//8'hDD;
REG_WAV_r[2] <= 8'h04;//8'hDA;
REG_WAV_r[3] <= 8'hDF;//8'h48;
REG_WAV_r[4] <= 8'h08;//8'h36;
REG_WAV_r[5] <= 8'h66;//8'h02;
REG_WAV_r[6] <= 8'h00;//8'hCF;
REG_WAV_r[7] <= 8'h7F;//8'h16;
REG_WAV_r[8] <= 8'h00;//8'h2C;
REG_WAV_r[9] <= 8'h57;//8'h04;
REG_WAV_r[10] <= 8'h02;//8'hE5;
REG_WAV_r[11] <= 8'hFF;//8'h2C;
REG_WAV_r[12] <= 8'h08;//8'hAC;
REG_WAV_r[13] <= 8'hFF;//8'hDD;
REG_WAV_r[14] <= 8'h00;//8'hDA;
REG_WAV_r[15] <= 8'h9F;//8'h48;
end
apu_frame_step_r <= 0;
apu_square1_enable_r <= 0;
apu_square1_timer_r <= 0;
apu_square1_env_enable_r <= 0;
apu_square1_env_timer_r <= 0;
apu_square1_volume_r <= 0;
apu_square1_pos_r <= 0;
apu_square1_sweep_enable_r <= 0;
apu_square1_sweep_timer_r <= 0;
apu_square1_sweep_freq_r <= 0;
apu_square2_enable_r <= 0;
apu_square2_timer_r <= 0;
apu_square2_env_enable_r <= 0;
apu_square2_env_timer_r <= 0;
apu_square2_volume_r <= 0;
apu_square2_pos_r <= 0;
apu_wave_enable_r <= 0;
apu_wave_timer_r <= 0;
apu_wave_pos_r <= 0;
apu_noise_enable_r <= 0;
apu_noise_timer_r <= 0;
apu_noise_env_timer_r <= 0;
apu_noise_volume_r <= 0;
apu_noise_lfsr_r <= 0;
apu_cpu_edge_d1_r <= 0;
apu_reg_update_r <= 0;
// handle APU enable
if (REG_req_val) begin
case(REG_address)
8'h11: REG_NR11_r[`NR11_LENGTH] <= REG_req_data[`NR11_LENGTH];
8'h16: REG_NR21_r[`NR21_LENGTH] <= REG_req_data[`NR21_LENGTH];
8'h20: REG_NR41_r[`NR41_LENGTH] <= REG_req_data[`NR41_LENGTH];
8'h26: {REG_NR52_r[7:7],REG_NR52_r[3:0]} <= {REG_req_data[7:7],REG_req_data[3:0]};
endcase
end
end
else begin
apu_cpu_edge_d1_r <= CLK_CPU_EDGE;
if (apu_reg_update_r & apu_cpu_edge_d1_r) begin
case (apu_reg_update_address_r)
// square1
8'h11: apu_square1_length_r <= REG_NR11_r[`NR11_LENGTH]; // NR11
8'h12: begin // NR12
// volume side effect (inversion). see register writes for additional side effects.
if (apu_reg_update_nr12_dir_r ^ REG_NR12_r[`NR12_ENV_DIR]) apu_square1_volume_r <= ~apu_square1_volume_r + 1;
if (apu_reg_update_nr14_enable_r) apu_square1_pos_r <= apu_square1_pos_r + 1;
if (apu_square1_enable_r) apu_square1_enable_r <= |REG_NR12_r[7:3];
end
8'h13: begin // NR13
if (apu_reg_update_nr14_enable_r) apu_square1_pos_r <= apu_square1_pos_r + 1;
end
8'h14: begin // NR14
if (apu_reg_update_nr14_enable_r) apu_square1_pos_r <= apu_square1_pos_r + 1;
if (REG_NR14_r[`NR14_FREQ_ENABLE]) begin
apu_square1_enable_r <= (|REG_NR12_r[`NR12_ENV_VOLUME] | REG_NR12_r[`NR12_ENV_DIR]) & ~HLT_RSP;
apu_square1_timer_r <= apu_square1_period;
apu_square1_length_r <= &apu_square1_length_r ? 0 : apu_square1_length_r;
apu_square1_env_enable_r <= 1;
apu_square1_env_timer_r <= REG_NR12_r[`NR12_ENV_PERIOD];
apu_square1_volume_r <= REG_NR12_r[`NR12_ENV_VOLUME];
apu_square1_sweep_enable_r <= |REG_NR10_r[`NR10_SWEEP_TIME] | |REG_NR10_r[`NR10_SWEEP_SHIFT];
apu_square1_sweep_timer_r <= {~|REG_NR10_r[`NR10_SWEEP_TIME],REG_NR10_r[`NR10_SWEEP_TIME]};
apu_square1_sweep_freq_r <= {REG_NR14_r[`NR14_FREQ_MSB],REG_NR13_r[`NR13_FREQ_LSB]};
end
end
// square2
8'h16: apu_square2_length_r <= REG_NR21_r[`NR21_LENGTH]; // NR21
8'h17: begin // NR22
// volume side effect (inversion). see register writes for additional side effects.
if (apu_reg_update_nr22_dir_r ^ REG_NR22_r[`NR22_ENV_DIR]) apu_square2_volume_r <= ~apu_square2_volume_r + 1;
if (apu_reg_update_nr24_enable_r) apu_square2_pos_r <= apu_square2_pos_r + 1;
if (apu_square2_enable_r) apu_square2_enable_r <= |REG_NR22_r[7:3];
end
8'h18: begin // NR23
if (apu_reg_update_nr24_enable_r) apu_square2_pos_r <= apu_square2_pos_r + 1;
end
8'h19: begin // NR24
if (apu_reg_update_nr24_enable_r) apu_square2_pos_r <= apu_square2_pos_r + 1;
if (REG_NR24_r[`NR24_FREQ_ENABLE]) begin
apu_square2_enable_r <= (|REG_NR22_r[`NR22_ENV_VOLUME] | REG_NR22_r[`NR22_ENV_DIR]) & ~HLT_RSP;
apu_square2_timer_r <= apu_square2_period;
apu_square2_length_r <= &apu_square2_length_r ? 0 : apu_square2_length_r;
apu_square2_env_enable_r <= 1;
apu_square2_env_timer_r <= REG_NR22_r[`NR22_ENV_PERIOD];
apu_square2_volume_r <= REG_NR22_r[`NR22_ENV_VOLUME];
end
end
// wave
8'h1A: if (apu_wave_enable_r) apu_wave_enable_r <= REG_NR30_r[`NR30_WAVE_ENABLE]; // NR30
8'h1B: apu_wave_length_r <= REG_NR31_r[`NR31_LENGTH]; // NR31
8'h1E: begin // NR34
if (REG_NR34_r[`NR34_FREQ_ENABLE]) begin
apu_wave_enable_r <= REG_NR30_r[`NR30_WAVE_ENABLE] & ~HLT_RSP;
apu_wave_timer_r <= apu_wave_period;
apu_wave_length_r <= &apu_wave_length_r ? 0 : apu_wave_length_r;
apu_wave_pos_r <= 0;
end
end
// noise
8'h20: apu_noise_length_r <= REG_NR41_r[`NR41_LENGTH]; // NR41
8'h21: if (apu_noise_enable_r) apu_noise_enable_r <= (REG_NR42_r[`NR42_ENV_DIR] | |REG_NR42_r[`NR42_ENV_VOLUME]);// NR42
8'h23: begin // NR44
if (REG_NR44_r[`NR44_FREQ_ENABLE]) begin
apu_noise_enable_r <= (REG_NR42_r[`NR42_ENV_DIR] | |REG_NR42_r[`NR42_ENV_VOLUME]) & ~HLT_RSP;
apu_noise_timer_r <= apu_noise_period;
apu_noise_lfsr_r <= 15'h7FFF;
apu_noise_length_r <= &apu_noise_length_r ? 0 : apu_noise_length_r;
apu_noise_env_timer_r <= REG_NR42_r[`NR42_ENV_PERIOD];
apu_noise_volume_r <= REG_NR42_r[`NR42_ENV_VOLUME];
end
end
endcase
end
else if (CLK_CPU_EDGE) begin
if (tmr_apu_step_r) apu_frame_step_r <= apu_frame_step_r + 1;
////////////
// square1
////////////
if (tmr_apu_step_r) begin
// period
if (~apu_frame_step_r[0]) begin
if (REG_NR14_r[`NR14_FREQ_STOP]) begin
if (&apu_square1_length_r) apu_square1_enable_r <= 0; else apu_square1_length_r <= apu_square1_length_r + 1;
end
end
// envelope
if (&apu_frame_step_r) begin
if (apu_square1_env_enable_r & |REG_NR12_r[`NR12_ENV_PERIOD]) begin
apu_square1_env_timer_r <= apu_square1_env_timer_r - 1;
if (apu_square1_env_timer_r == 1) begin
if ( REG_NR12_r[`NR12_ENV_DIR] & ~&apu_square1_volume_r) apu_square1_volume_r <= apu_square1_volume_r + 1;
else if (~REG_NR12_r[`NR12_ENV_DIR] & |apu_square1_volume_r) apu_square1_volume_r <= apu_square1_volume_r - 1;
else apu_square1_env_enable_r <= 0;
apu_square1_env_timer_r <= REG_NR12_r[`NR12_ENV_PERIOD];
end
end
end
// sweep
if (apu_frame_step_r[1:0] == 2'b10) begin
if (apu_square1_sweep_enable_r) begin
if (|REG_NR10_r[`NR10_SWEEP_TIME]) begin
if (|apu_square1_sweep_timer_r) begin
apu_square1_sweep_timer_r <= apu_square1_sweep_timer_r - 1;
if (apu_square1_sweep_timer_r == 1) begin
if (~|REG_NR10_r[`NR10_SWEEP_SHIFT]) apu_square1_enable_r <= 0;
if (~|REG_NR10_r[`NR10_SWEEP_SHIFT]) apu_square1_sweep_enable_r <= 0;
apu_square1_sweep_timer_r <= {~|REG_NR10_r[`NR10_SWEEP_TIME],REG_NR10_r[`NR10_SWEEP_TIME]};
// need to update both reg and shadow here because period uses reg. period needs to use reg because the program may update that manually.
// the shadow is used to compute the next frequency for shutting down the output for sweep
// TODO: determine if looking one frequency shift in the future is enough.
if (|REG_NR10_r[`NR10_SWEEP_SHIFT]) {REG_NR14_r[`NR14_FREQ_MSB],REG_NR13_r[`NR13_FREQ_LSB]} <= apu_square1_sweep_freq_next[10:0];
if (|REG_NR10_r[`NR10_SWEEP_SHIFT]) apu_square1_sweep_freq_r[10:0] <= apu_square1_sweep_freq_next[10:0];
end
end
end
end
end
end
// duty cycle
apu_square1_timer_r <= apu_square1_timer_r + 1;
if (&apu_square1_timer_r) begin
apu_square1_pos_r <= apu_square1_pos_r + 1;
apu_square1_timer_r <= apu_square1_period;
end
// check sweep overflow
if (apu_square1_sweep_enable_r & |REG_NR10_r[`NR10_SWEEP_SHIFT] & |apu_square1_sweep_freq_next[15:11]) begin
apu_square1_enable_r <= 0;
apu_square1_sweep_enable_r <= 0;
end
////////////
// square2
////////////
if (tmr_apu_step_r) begin
// period
if (~apu_frame_step_r[0]) begin
if (REG_NR24_r[`NR24_FREQ_STOP]) begin
if (&apu_square2_length_r) apu_square2_enable_r <= 0; else apu_square2_length_r <= apu_square2_length_r + 1;
end
end
// envelope
if (&apu_frame_step_r) begin
if (apu_square2_env_enable_r & |REG_NR22_r[`NR22_ENV_PERIOD]) begin
apu_square2_env_timer_r <= apu_square2_env_timer_r - 1;
if (apu_square2_env_timer_r == 1) begin
if ( REG_NR22_r[`NR22_ENV_DIR] & ~&apu_square2_volume_r) apu_square2_volume_r <= apu_square2_volume_r + 1;
else if (~REG_NR22_r[`NR22_ENV_DIR] & |apu_square2_volume_r) apu_square2_volume_r <= apu_square2_volume_r - 1;
else apu_square2_env_enable_r <= 0;
apu_square2_env_timer_r <= REG_NR22_r[`NR22_ENV_PERIOD];
end
end
end
end
// duty cycle
apu_square2_timer_r <= apu_square2_timer_r + 1;
if (&apu_square2_timer_r) begin
apu_square2_pos_r <= apu_square2_pos_r + 1;
apu_square2_timer_r <= apu_square2_period;
end
////////////
// wave
////////////
if (tmr_apu_step_r) begin
// period
if (~apu_frame_step_r[0]) begin
if (REG_NR34_r[`NR34_FREQ_STOP]) begin
if (&apu_wave_length_r) apu_wave_enable_r <= 0; else apu_wave_length_r <= apu_wave_length_r + 1;
end
end
end
apu_wave_timer_r <= apu_wave_timer_r + 1;
if (&apu_wave_timer_r) begin
apu_wave_pos_r <= apu_wave_pos_r + 1;
apu_wave_timer_r <= apu_wave_period;
apu_wave_sample_update_r <= 1;
end
////////////
// noise
////////////
if (tmr_apu_step_r) begin
// period
if (~apu_frame_step_r[0]) begin
if (REG_NR44_r[`NR44_FREQ_STOP]) begin
if (&apu_noise_length_r) apu_noise_enable_r <= 0; else apu_noise_length_r <= apu_noise_length_r + 1;
end
end
// envelope
if (&apu_frame_step_r) begin
if (|apu_noise_env_timer_r) begin
apu_noise_env_timer_r <= apu_noise_env_timer_r - 1;
if (apu_noise_env_timer_r == 1) begin
if ( REG_NR42_r[`NR42_ENV_DIR] & ~&apu_noise_volume_r) apu_noise_volume_r <= apu_noise_volume_r + 1;
else if (~REG_NR42_r[`NR42_ENV_DIR] & |apu_noise_volume_r) apu_noise_volume_r <= apu_noise_volume_r - 1;
apu_noise_env_timer_r <= REG_NR42_r[`NR42_ENV_PERIOD];
end
end
end
end
// lfsr
if (REG_NR43_r[`NR43_LFSR_SHIFT] < 4'hE) begin
apu_noise_timer_r <= apu_noise_timer_r - 1;
if (~|apu_noise_timer_r) begin
apu_noise_timer_r <= apu_noise_period;
apu_noise_lfsr_r <= {^apu_noise_lfsr_r[1:0],apu_noise_lfsr_r[14:8],(REG_NR43_r[`NR43_LFSR_WIDTH] ? ^apu_noise_lfsr_r[1:0] : apu_noise_lfsr_r[7]),apu_noise_lfsr_r[6:1]};
end
end
end
//--------------
// APU REGISTERS
//--------------
// sync to one after CPU clock edge
if (apu_cpu_edge_d1_r) apu_reg_update_r <= 0;
if (REG_req_val) begin
apu_reg_update_r <= 1;
apu_reg_update_address_r <= REG_address;
apu_reg_update_nr12_dir_r <= REG_NR12_r[`NR12_ENV_DIR];
apu_reg_update_nr22_dir_r <= REG_NR22_r[`NR22_ENV_DIR];
apu_reg_update_nr14_enable_r <= REG_NR14_r[`NR14_FREQ_ENABLE];
apu_reg_update_nr24_enable_r <= REG_NR24_r[`NR24_FREQ_ENABLE];
case (REG_address)
8'h10: REG_NR10_r[7:0] <= REG_req_data[7:0];
8'h11: REG_NR11_r[7:0] <= REG_req_data[7:0];
8'h12: begin
REG_NR12_r[7:0] <= REG_req_data[7:0];
// volume side effects
// P-M uses the first one to wrap the volume from F->0
// CVL and probably many others use the second as predecrement of volume
if (REG_req_data[`NR12_ENV_DIR] & ~|REG_NR12_r[`NR12_ENV_PERIOD]) apu_square1_volume_r <= apu_square1_volume_r + 1;
else if (~REG_req_data[`NR12_ENV_DIR] & |REG_req_data[`NR12_ENV_PERIOD] & ~|REG_NR12_r[`NR12_ENV_PERIOD] & |apu_square1_volume_r) apu_square1_volume_r <= apu_square1_volume_r - 1;
end
8'h13: REG_NR13_r[7:0] <= REG_req_data[7:0];
8'h14: REG_NR14_r[7:0] <= REG_req_data[7:0];
8'h16: REG_NR21_r[7:0] <= REG_req_data[7:0];
8'h17: begin
REG_NR22_r[7:0] <= REG_req_data[7:0];
// volume side effects
// P-M uses the first one to wrap the volume from F->0
// CVL and probably many others use the second as predecrement of volume
if (REG_req_data[`NR22_ENV_DIR] & ~|REG_NR22_r[`NR22_ENV_PERIOD]) apu_square2_volume_r <= apu_square2_volume_r + 1;
else if (~REG_req_data[`NR22_ENV_DIR] & |REG_req_data[`NR22_ENV_PERIOD] & ~|REG_NR22_r[`NR22_ENV_PERIOD] & |apu_square2_volume_r) apu_square2_volume_r <= apu_square2_volume_r - 1;
end
8'h18: REG_NR23_r[7:0] <= REG_req_data[7:0];
8'h19: REG_NR24_r[7:0] <= REG_req_data[7:0];
8'h1A: REG_NR30_r[7:0] <= REG_req_data[7:0];
8'h1B: REG_NR31_r[7:0] <= REG_req_data[7:0];
8'h1C: REG_NR32_r[7:0] <= REG_req_data[7:0];
8'h1D: REG_NR33_r[7:0] <= REG_req_data[7:0];
8'h1E: REG_NR34_r[7:0] <= REG_req_data[7:0];
8'h20: REG_NR41_r[7:0] <= REG_req_data[7:0];
8'h21: REG_NR42_r[7:0] <= REG_req_data[7:0];
8'h22: REG_NR43_r[7:0] <= REG_req_data[7:0];
8'h23: REG_NR44_r[7:0] <= REG_req_data[7:0];
8'h24: REG_NR50_r[7:0] <= REG_req_data[7:0];
8'h25: REG_NR51_r[7:0] <= REG_req_data[7:0];
8'h26: {REG_NR52_r[7:7],REG_NR52_r[3:0]} <= {REG_req_data[7:7],REG_req_data[3:0]};
8'h30, 8'h31, 8'h32, 8'h33, 8'h34, 8'h35, 8'h36, 8'h37,
8'h38, 8'h39, 8'h3A, 8'h3B, 8'h3C, 8'h3D, 8'h3E, 8'h3F: if (~apu_wave_enable_r | REG_req_dbg) REG_WAV_r[REG_address[3:0]] <= REG_req_data;
endcase
end
end
end
`endif
//-------------------------------------------------------------------
// MCT
//-------------------------------------------------------------------
// MCT is the memory controller that allows the CPU pipeline stages
// to access all memory-mapped architectural state including:
//
// ROM (both cart and boot)
// SaveRAM
// WRAM
// VRAM
// OAM
// HRAM
// REG (IO registers)
//
// The first 3 are stored in the SD2SNES's 16MB PSRAM. The others
// are mapped to BRAM or registers because they need: higher bandwidth,
// concurrency (with other state), or partial byte support.
//
// In general, the GB's bandwidth requirements are very modest, but using
// BRAM simplifies having to balance the various sources.
//
// hram
//
wire hram_wren = MCT_HRAM_wren;
wire [6:0] hram_address = MCT_HRAM_address;
wire [7:0] hram_rddata;
wire [7:0] hram_wrdata = MCT_HRAM_data;
wire dbg_hram_wren;
wire [6:0] dbg_hram_address;
wire [7:0] dbg_hram_rddata;
wire [7:0] dbg_hram_wrdata;
`ifdef MK2
hram hram (
.clka(CLK), // input clka
.wea(hram_wren), // input [0 : 0] wea
.addra(hram_address), // input [6 : 0] addra
.dina(hram_wrdata), // input [7 : 0] dina
.douta(hram_rddata), // output [7 : 0] douta
.clkb(CLK), // input clkb
.web(dbg_hram_wren), // input [0 : 0] web
.addrb(dbg_hram_address), // input [6 : 0] addrb
.dinb(dbg_hram_wrdata), // input [7 : 0] dinb
.doutb(dbg_hram_rddata) // output [7 : 0] doutb
);
`endif
`ifdef MK3
hram hram (
.clock(CLK), // input clka
.wren_a(hram_wren), // input [0 : 0] wea
.address_a(hram_address), // input [6 : 0] addra
.data_a(hram_wrdata), // input [7 : 0] dina
.q_a(hram_rddata), // output [7 : 0] douta
.wren_b(dbg_hram_wren), // input [0 : 0] web
.address_b(dbg_hram_address), // input [6 : 0] addrb
.data_b(dbg_hram_wrdata), // input [7 : 0] dinb
.q_b(dbg_hram_rddata) // output [7 : 0] doutb
);
`endif
// Sources: IFD, EXE
// Targets: EXT (ROM, SaveRAM, WRAM), VRAM, OAM, IO/HRAM
`define MCT_TGT_VRAM(a) (a[15:13] == 3'b100) // 8000-9FFF
`define MCT_TGT_HIGH(a) (&a[15:9]) // FE00-FE9F,FF00-FF7F,FF80-FFFE,FFFF
parameter
ST_MCT_IDLE = 8'b00000001,
ST_MCT_DEC = 8'b00000010,
ST_MCT_VRAM = 8'b00000100,
ST_MCT_OAM = 8'b00001000,
ST_MCT_REG = 8'b00010000,
ST_MCT_HRAM = 8'b00100000,
ST_MCT_EXT = 8'b01000000,
ST_MCT_END = 8'b10000000;
reg [1:0] mct_req_r;
reg [7:0] mct_state_r;
reg [15:0] mct_addr_r;
reg mct_src_r;
reg mct_wr_r;
reg [7:0] mct_mdr_r;
wire [15:0] mct_addr_d1 = mct_src_r ? EXE_MCT_req_addr_d1 : IFD_MCT_req_addr_d1;
assign HRAM_data = hram_rddata;
assign MCT_VRAM_wren = mct_wr_r & |(mct_state_r & ST_MCT_VRAM) & mct_req_r[0];
assign MCT_VRAM_address = mct_addr_r[12:0];
assign MCT_VRAM_data = mct_mdr_r;
assign MCT_OAM_wren = mct_wr_r & |(mct_state_r & ST_MCT_OAM) & mct_req_r[0];
assign MCT_OAM_address = mct_addr_r[7:0];
assign MCT_OAM_data = mct_mdr_r;
assign MCT_HRAM_wren = mct_wr_r & |(mct_state_r & ST_MCT_HRAM) & mct_req_r[0];
assign MCT_HRAM_address = mct_addr_r[6:0];
assign MCT_HRAM_data = mct_mdr_r;
assign MCT_REG_wren = mct_wr_r & |(mct_state_r & ST_MCT_REG) & mct_req_r[0];
assign MCT_REG_address = mct_addr_r[7:0];
assign MCT_REG_data = mct_mdr_r;
assign SYS_REQ = DMA_SYS_active ? DMA_req_val : (|(mct_state_r & ST_MCT_EXT) & mct_req_r[0]);
assign SYS_WR = DMA_SYS_active ? 0 : mct_wr_r & mct_req_r[0];
assign SYS_ADDR = DMA_SYS_active ? DMA_address : mct_addr_r;
assign SYS_WRDATA = mct_mdr_r;
assign MCT_IFD_rsp_val = |(mct_state_r & ST_MCT_END) & ~mct_src_r;
assign MCT_EXE_rsp_val = |(mct_state_r & ST_MCT_END) & mct_src_r;
assign MCT_data = mct_mdr_r;
assign MCT_REG_req_val = |(mct_state_r & ST_MCT_REG);
reg [15:0] mct_oam_error_r;
reg [15:0] mct_vram_error_r;
always @(posedge CLK) begin
if (cpu_ireset_r) begin
mct_state_r <= ST_MCT_IDLE;
mct_req_r <= 0;
mct_oam_error_r <= 0;
mct_vram_error_r <= 0;
end
else begin
case (mct_state_r)
ST_MCT_IDLE: begin
if (EXE_MCT_req_val) begin
mct_src_r <= 1;
mct_wr_r <= EXE_MCT_req_wr;
mct_state_r <= ST_MCT_DEC;
end
else if (IFD_MCT_req_val) begin
mct_src_r <= 0;
mct_wr_r <= 0;
mct_state_r <= ST_MCT_DEC;
end
end
ST_MCT_DEC: begin
// data and address arrives one cycle late to simplify EXE register read -> AGEN
mct_addr_r <= mct_addr_d1;
if (mct_wr_r) mct_mdr_r <= EXE_MCT_req_data_d1;
if (`MCT_TGT_VRAM(mct_addr_d1)) begin
mct_state_r <= ST_MCT_VRAM;
end
else if (`MCT_TGT_HIGH(mct_addr_d1)) begin
mct_state_r <= mct_addr_d1[8] ? ((~mct_addr_d1[7] | &mct_addr_d1[6:0]) ? ST_MCT_REG : ST_MCT_HRAM) : ST_MCT_OAM;
end
else begin
mct_state_r <= ST_MCT_EXT;
end
end
ST_MCT_VRAM: begin
// SH writes 0 and checks for nonzero to see if the write failed. Returning FF here allows correct detection of the fail
if (~mct_wr_r) mct_mdr_r <= PPU_MCT_vram_active ? 8'hFF : VRAM_data;
// avoid false errors by only looking at EXE src
if (~|mct_req_r & PPU_MCT_vram_active & mct_src_r) mct_vram_error_r <= mct_vram_error_r + 1;
if (~|mct_req_r) mct_state_r <= ST_MCT_END;
end
ST_MCT_OAM: begin
if (~mct_wr_r) mct_mdr_r <= PPU_MCT_oam_active ? 8'hFF : OAM_data;
// avoid false errors by only looking at EXE src
if (~|mct_req_r & PPU_MCT_oam_active & mct_src_r) mct_oam_error_r <= mct_oam_error_r + 1;
if (~|mct_req_r) mct_state_r <= ST_MCT_END;
end
ST_MCT_REG: begin
if (~mct_wr_r) mct_mdr_r <= REG_data;
if (~|mct_req_r & REG_MCT_rsp_val) mct_state_r <= ST_MCT_END;
end
ST_MCT_HRAM: begin
if (~mct_wr_r) mct_mdr_r <= HRAM_data;
if (~|mct_req_r) mct_state_r <= ST_MCT_END;
end
ST_MCT_EXT: begin
// the main logic has a one entry buffer to always sink these requests
if (~mct_wr_r) mct_mdr_r <= SYS_RDDATA;
if (~|mct_req_r & SYS_RDY) mct_state_r <= ST_MCT_END;
end
ST_MCT_END: begin
mct_state_r <= ST_MCT_IDLE;
end
endcase
mct_req_r <= {mct_req_r[0],|(mct_state_r & ST_MCT_DEC)};
end
end
//-------------------------------------------------------------------
// SERIAL
//-------------------------------------------------------------------
// Basic functionality to allow multiplayer games to pass. missing external clock/data.
`ifdef SGB_SERIAL
reg ser_active_d1_r;
reg ser_clk_d1_r;
reg [9:0] ser_ctr_r;
reg [2:0] ser_pos_r;
reg ser_done_r;
assign SER_REG_done = ser_done_r;
assign HLT_SER_rsp = HLT_REQ_sync & (~REG_SC_r[7] | ~REG_SC_r[0]);
always @(posedge CLK) begin
if (cpu_ireset_r) begin
REG_SB_r <= 0;
REG_SC_r <= 8'h7F;
ser_active_d1_r <= 0;
ser_done_r <= 0;
end
else begin
if (CLK_CPU_EDGE) begin
ser_active_d1_r <= REG_SC_r[7];
ser_done_r <= 0;
if (REG_SC_r[7]) begin
if (~ser_active_d1_r) begin
ser_ctr_r <= 0;
ser_clk_d1_r <= 0;
ser_pos_r <= 0;
end
else begin
ser_ctr_r <= REG_SC_r[0] ? ser_ctr_r + 1 : ser_ctr_r;
ser_clk_d1_r <= ser_ctr_r[9];
if (ser_clk_d1_r ^ ser_ctr_r[9]) begin
REG_SB_r[~ser_pos_r] <= 1'b1;
ser_pos_r <= ser_pos_r + 1;
if (&ser_pos_r) begin
REG_SC_r[7] <= 0;
ser_done_r <= 1;
end
end
end
end
end
if (REG_req_val) begin
case (REG_address)
8'h01: REG_SB_r[7:0] <= REG_req_data[7:0];
8'h02: begin
REG_SC_r[7:0] <= REG_req_data[7:0];
// support MCU/DBG triggering interrupt on 1->0 transition. it's possible, but highly unlikely save states could trigger this and we
// may not want that. that would happen only on the few games that use this and require saving and then loading a state in
// external clock mode when the state machine is active. BMQ doesn't want to assert interrupt on CPU write of SC.
if (reg_src_r & ~HLT_RSP) ser_done_r <= REG_SC_r[7] & ~REG_req_data[7];
end
endcase
end
end
end
`endif
//-------------------------------------------------------------------
// DBG
//-------------------------------------------------------------------
// DBG contains all the state we want to read out from the SGB via
// the MCU. It mirrors the MCT pipe because the general operation is
// the same. If fitting this logic becomes problematic it can either
// be removed entirely or integrated into the MCU pipe (with some
// concurrency limitations).
parameter
ST_DBG_IDLE = 8'b00000001,
ST_DBG_DEC = 8'b00000010,
ST_DBG_VRAM = 8'b00000100,
ST_DBG_OAM = 8'b00001000,
ST_DBG_REG = 8'b00010000,
ST_DBG_HRAM = 8'b00100000,
ST_DBG_MISC = 8'b01000000, // MISC state we want to export at 810000-87FFFF
ST_DBG_END = 8'b10000000;
reg [1:0] dbg_req_r;
reg [7:0] dbg_state_r;
reg [15:0] dbg_addr_r;
reg dbg_wr_r;
reg [7:0] dbg_mdr_r;
reg [7:0] dbg_misc_data_r = 0;
// return bogus data under reset to avoid having to keep parts of the CPU awake
assign MCU_RSP = |(dbg_state_r & ST_DBG_END) | cpu_ireset_r;
assign MCU_DATA_OUT = dbg_mdr_r;
assign dbg_vram_wren = dbg_wr_r & |(dbg_state_r & ST_DBG_VRAM);
assign dbg_vram_address = dbg_addr_r[12:0];
assign dbg_vram_wrdata = dbg_mdr_r;
assign dbg_oam_wren = dbg_wr_r & |(dbg_state_r & ST_DBG_OAM);
assign dbg_oam_address = dbg_addr_r[7:0];
assign dbg_oam_wrdata = dbg_mdr_r;
assign dbg_hram_wren = dbg_wr_r & |(dbg_state_r & ST_DBG_HRAM);
assign dbg_hram_address = dbg_addr_r[6:0];
assign dbg_hram_wrdata = dbg_mdr_r;
assign DBG_REG_req_val = |(dbg_state_r & ST_DBG_REG);
assign DBG_REG_wren = dbg_wr_r & |(dbg_state_r & ST_DBG_REG);
assign DBG_REG_address = dbg_addr_r[7:0];
assign DBG_REG_data = dbg_mdr_r;
assign DBG_ADDR = dbg_addr_r[11:0];
`ifdef SGB_DEBUG
wire [7:0] config_r[7:0];
`endif
always @(posedge CLK) begin
if (cpu_ireset_r) begin
dbg_state_r <= ST_DBG_IDLE;
dbg_req_r <= 0;
dbg_wr_r <= 0;
end
else begin
case (dbg_state_r)
ST_DBG_IDLE: begin
if (MCU_RRQ | MCU_WRQ) begin
dbg_addr_r <= MCU_ADDR;
dbg_wr_r <= MCU_WRQ;
if (MCU_WRQ) dbg_mdr_r <= MCU_DATA_IN;
dbg_state_r <= ST_DBG_DEC;
end
end
ST_DBG_DEC: begin
if (`MCT_TGT_VRAM(dbg_addr_r)) begin
dbg_state_r <= ST_DBG_VRAM;
end
else if (`MCT_TGT_HIGH(dbg_addr_r)) begin
dbg_state_r <= dbg_addr_r[8] ? ((~dbg_addr_r[7] | &dbg_addr_r[6:0]) ? ST_DBG_REG : ST_DBG_HRAM) : ST_DBG_OAM;
end
else begin
dbg_state_r <= ST_DBG_MISC;
end
end
ST_DBG_VRAM: begin
if (~dbg_wr_r) dbg_mdr_r <= dbg_vram_rddata;
dbg_state_r <= ST_DBG_END;
end
ST_DBG_OAM: begin
if (~dbg_wr_r) dbg_mdr_r <= dbg_oam_rddata;
dbg_state_r <= ST_DBG_END;
end
ST_DBG_REG: begin
if (~dbg_wr_r) dbg_mdr_r <= REG_data;
if (~dbg_req_r[0] & REG_DBG_rsp_val) dbg_state_r <= ST_DBG_END;
end
ST_DBG_HRAM: begin
if (~dbg_wr_r) dbg_mdr_r <= dbg_hram_rddata;
dbg_state_r <= ST_DBG_END;
end
ST_DBG_MISC: begin
if (~dbg_wr_r) dbg_mdr_r <= dbg_misc_data_r;
// DEC - addr
// MISC0 - dbg_req_r[0], dbg_row_rddata
// MISC1 - dbg_req_r[1], data_in
// MISC2 - dbg_misc_data_r
if (~|dbg_req_r) dbg_state_r <= ST_DBG_END;
end
ST_DBG_END: begin
dbg_state_r <= ST_DBG_IDLE;
end
endcase
dbg_req_r <= {dbg_req_r[0],|(dbg_state_r & ST_DBG_DEC)};
end
`ifdef SGB_DEBUG
case (dbg_addr_r[11:8])
// ARCH
4'h0: case(dbg_addr_r[7:0])
8'h00: dbg_misc_data_r <= ifd_pc[7:0];
8'h01: dbg_misc_data_r <= ifd_pc[15:8];
8'h02: dbg_misc_data_r <= F_r;
8'h03: dbg_misc_data_r <= A_r;
8'h04: dbg_misc_data_r <= C_r;
8'h05: dbg_misc_data_r <= B_r;
8'h06: dbg_misc_data_r <= E_r;
8'h07: dbg_misc_data_r <= D_r;
8'h08: dbg_misc_data_r <= L_r;
8'h09: dbg_misc_data_r <= H_r;
8'h0A: dbg_misc_data_r <= SP_r[7:0];
8'h0B: dbg_misc_data_r <= SP_r[15:8];
default: dbg_misc_data_r <= 0;
endcase
// ARCH/MMIO
4'h1: casez(dbg_addr_r[7:0])
8'h00: dbg_misc_data_r <= REG_P1_r;
8'h01: dbg_misc_data_r <= REG_SB_r;
8'h02: dbg_misc_data_r <= REG_SC_r;
8'h04: dbg_misc_data_r <= REG_DIV_r;
8'h05: dbg_misc_data_r <= REG_TIMA_r;
8'h06: dbg_misc_data_r <= REG_TMA_r;
8'h07: dbg_misc_data_r <= REG_TAC_r;
8'h0F: dbg_misc_data_r <= REG_IF_r;
8'h10: dbg_misc_data_r <= REG_NR10_r;
8'h11: dbg_misc_data_r <= REG_NR11_r;
8'h12: dbg_misc_data_r <= REG_NR12_r;
8'h13: dbg_misc_data_r <= REG_NR13_r;
8'h14: dbg_misc_data_r <= REG_NR14_r;
8'h16: dbg_misc_data_r <= REG_NR21_r;
8'h17: dbg_misc_data_r <= REG_NR22_r;
8'h18: dbg_misc_data_r <= REG_NR23_r;
8'h19: dbg_misc_data_r <= REG_NR24_r;
8'h1A: dbg_misc_data_r <= REG_NR30_r;
8'h1B: dbg_misc_data_r <= REG_NR31_r;
8'h1C: dbg_misc_data_r <= REG_NR32_r;
8'h1D: dbg_misc_data_r <= REG_NR33_r;
8'h1E: dbg_misc_data_r <= REG_NR34_r;
8'h20: dbg_misc_data_r <= REG_NR41_r;
8'h21: dbg_misc_data_r <= REG_NR42_r;
8'h22: dbg_misc_data_r <= REG_NR43_r;
8'h23: dbg_misc_data_r <= REG_NR44_r;
8'h24: dbg_misc_data_r <= REG_NR50_r;
8'h25: dbg_misc_data_r <= REG_NR51_r;
8'h26: dbg_misc_data_r <= REG_NR52_r;
8'h3?: dbg_misc_data_r <= REG_WAV_r[dbg_addr_r[3:0]];
8'h40: dbg_misc_data_r <= REG_LCDC_r;
8'h41: dbg_misc_data_r <= REG_STAT_r;
8'h42: dbg_misc_data_r <= REG_SCY_r;
8'h43: dbg_misc_data_r <= REG_SCX_r;
8'h44: dbg_misc_data_r <= REG_LY_r;
8'h45: dbg_misc_data_r <= REG_LYC_r;
8'h46: dbg_misc_data_r <= REG_DMA_r;
8'h47: dbg_misc_data_r <= REG_BGP_r;
8'h48: dbg_misc_data_r <= REG_OBP0_r;
8'h49: dbg_misc_data_r <= REG_OBP1_r;
8'h4A: dbg_misc_data_r <= REG_WY_r;
8'h4B: dbg_misc_data_r <= REG_WX_r;
8'h50: dbg_misc_data_r <= REG_BOOT_r;
8'hFF: dbg_misc_data_r <= REG_IE_r;
default: dbg_misc_data_r <= 0;
endcase
// IFD
4'h2: case(dbg_addr_r[7:0])
8'h00: dbg_misc_data_r <= ifd_op_r;
8'h01: dbg_misc_data_r <= ifd_size_r;
8'h02: dbg_misc_data_r <= ifd_data_r;
8'h03: dbg_misc_data_r <= ifd_decode_r[7:0];
8'h04: dbg_misc_data_r <= ifd_decode_r[15:8];
8'h05: dbg_misc_data_r <= MCT_IFD_rsp_val;
8'h06: dbg_misc_data_r <= ifd_size_r;
8'h07: dbg_misc_data_r <= ifd_decode_r[`DEC_SZE];
8'h08: dbg_misc_data_r <= ifd_pc[7:0];
8'h09: dbg_misc_data_r <= ifd_pc[15:8];
8'h0A: dbg_misc_data_r <= PC_r[7:0];
8'h0B: dbg_misc_data_r <= PC_r[15:8];
8'h0C: dbg_misc_data_r <= ifd_complete_r;
default: dbg_misc_data_r <= 0;
endcase
// EXE
4'h3: case(dbg_addr_r[7:0])
8'h00: dbg_misc_data_r <= IFD_EXE_valid;
8'h01: dbg_misc_data_r <= IFD_EXE_op[7:0];
8'h02: dbg_misc_data_r <= IFD_EXE_op[15:8];
8'h03: dbg_misc_data_r <= IFD_EXE_op[23:16];
8'h04: dbg_misc_data_r <= exe_ime_r;
8'h10: dbg_misc_data_r <= IFD_EXE_decode[`DEC_GRP];
8'h11: dbg_misc_data_r <= IFD_EXE_decode[`DEC_LAT];
8'h12: dbg_misc_data_r <= IFD_EXE_decode[`DEC_DST];
8'h13: dbg_misc_data_r <= IFD_EXE_decode[`DEC_SRC];
8'h14: dbg_misc_data_r <= IFD_EXE_decode[`DEC_SZE];
8'h15: dbg_misc_data_r <= IFD_EXE_cb;
8'h20: dbg_misc_data_r <= exe_ctr_r;
8'h21: dbg_misc_data_r <= 0;
8'h22: dbg_misc_data_r <= exe_stage;
8'h23: dbg_misc_data_r <= exe_advance_r;
8'h24: dbg_misc_data_r <= exe_ready_r;
8'h25: dbg_misc_data_r <= exe_complete_r;
8'h26: dbg_misc_data_r <= exe_lat_add_r;
8'h27: dbg_misc_data_r <= exe_lat;
8'h30: dbg_misc_data_r <= IFD_EXE_pc_start[7:0];
8'h31: dbg_misc_data_r <= IFD_EXE_pc_start[15:8];
8'h32: dbg_misc_data_r <= IFD_EXE_pc_end[7:0];
8'h33: dbg_misc_data_r <= IFD_EXE_pc_end[15:8];
8'h34: dbg_misc_data_r <= IFD_EXE_pc_next[7:0];
8'h35: dbg_misc_data_r <= IFD_EXE_pc_next[15:8];
8'h40: dbg_misc_data_r <= exe_res_r[7:0];
8'h41: dbg_misc_data_r <= exe_res_r[15:8];
8'h42: dbg_misc_data_r <= exe_src_r[7:0];
8'h43: dbg_misc_data_r <= exe_src_r[15:8];
8'h44: dbg_misc_data_r <= exe_dst_r[7:0];
8'h45: dbg_misc_data_r <= exe_dst_r[15:8];
8'h46: dbg_misc_data_r <= exe_res_cc_r[7:0];
8'h47: dbg_misc_data_r <= exe_cc_r[7:0];
8'h48: dbg_misc_data_r <= EXE_MCT_req_addr_d1[7:0];
8'h49: dbg_misc_data_r <= EXE_MCT_req_addr_d1[15:8];
8'h4A: dbg_misc_data_r <= exe_mem_data_r[7:0];
8'h4B: dbg_misc_data_r <= exe_mem_data_r[15:8];
8'h4C: dbg_misc_data_r <= exe_res_los_r;
8'h4D: dbg_misc_data_r <= exe_src_alu_r;
8'h50: dbg_misc_data_r <= EXE_IFD_redirect;
8'h51: dbg_misc_data_r <= EXE_IFD_target[7:0];
8'h52: dbg_misc_data_r <= EXE_IFD_target[15:8];
8'h53: dbg_misc_data_r <= exe_pc_prev_r[7:0];
8'h54: dbg_misc_data_r <= exe_pc_prev_r[15:8];
8'h55: dbg_misc_data_r <= exe_pc_prev_redirect_r[7:0];
8'h56: dbg_misc_data_r <= exe_pc_prev_redirect_r[15:8];
8'h57: dbg_misc_data_r <= exe_target_prev_redirect_r[7:0];
8'h58: dbg_misc_data_r <= exe_target_prev_redirect_r[15:8];
//8'h60: dbg_misc_data_r <= tmp_div_r[3:0];
//8'h61: dbg_misc_data_r <= tmp_latency_r;
//8'h62: dbg_misc_data_r <= tmp_latency2_r;
//8'h63: dbg_misc_data_r <= tmp_latency3_r;
8'h70: dbg_misc_data_r <= IFD_EXE_int;
default: dbg_misc_data_r <= 0;
endcase
`ifndef MK2
// MCT,REG
4'h4: casez(dbg_addr_r[7:0])
8'h00: dbg_misc_data_r <= mct_state_r;
8'h01: dbg_misc_data_r <= mct_req_r;
8'h02: dbg_misc_data_r <= mct_addr_r[7:0];
8'h03: dbg_misc_data_r <= mct_addr_r[15:8];
8'h04: dbg_misc_data_r <= mct_src_r;
8'h05: dbg_misc_data_r <= mct_wr_r;
8'h06: dbg_misc_data_r <= mct_mdr_r;
8'h10: dbg_misc_data_r <= reg_state_r;
8'h11: dbg_misc_data_r <= reg_req_r;
8'h12: dbg_misc_data_r <= reg_addr_r[6:0];
//8'h13: dbg_misc_data_r <= 0;
8'h14: dbg_misc_data_r <= reg_src_r;
8'h15: dbg_misc_data_r <= reg_wr_r;
8'h16: dbg_misc_data_r <= reg_mdr_r;
8'h20: dbg_misc_data_r <= mct_vram_error_r[7:0];
8'h21: dbg_misc_data_r <= mct_vram_error_r[15:8];
8'h22: dbg_misc_data_r <= mct_oam_error_r[7:0];
8'h23: dbg_misc_data_r <= mct_oam_error_r[15:8];
8'hC0: dbg_misc_data_r <= HLT_REQ_sync;
8'hC1: dbg_misc_data_r <= HLT_RSP;
8'hC2: dbg_misc_data_r <= HLT_IFD_rsp;
8'hC3: dbg_misc_data_r <= HLT_EXE_rsp;
8'hC4: dbg_misc_data_r <= HLT_DMA_rsp;
8'hC5: dbg_misc_data_r <= HLT_SER_rsp;
8'hC6: dbg_misc_data_r <= ~|ifd_size_r;
8'hC7: dbg_misc_data_r <= ~ifd_int_r;
8'hC8: dbg_misc_data_r <= EXE_IFD_ime;
8'hC9: dbg_misc_data_r <= IDL_ICD;
8'hD?: dbg_misc_data_r <= DBG_MAIN_DATA_IN;
8'hE?: dbg_misc_data_r <= DBG_CHEAT_DATA_IN;
8'hF?: dbg_misc_data_r <= DBG_MBC_DATA_IN;
default: dbg_misc_data_r <= 0;
endcase
// PPU
4'h5: casez(dbg_addr_r[7:0])
8'h00: dbg_misc_data_r <= PPU_HSYNC_EDGE;
8'h01: dbg_misc_data_r <= PPU_VSYNC_EDGE;
8'h02: dbg_misc_data_r <= PPU_PIXEL_VALID;
8'h03: dbg_misc_data_r <= PPU_PIXEL;
8'h04: dbg_misc_data_r <= PPU_DOT_EDGE;
8'h10: dbg_misc_data_r <= ppu_state_r[7:0];
8'h11: dbg_misc_data_r <= ppu_state_r[12:8];
8'h12: dbg_misc_data_r <= ppu_dot_ctr_r[7:0];
8'h13: dbg_misc_data_r <= ppu_dot_ctr_r[8];
8'h20: dbg_misc_data_r <= ppu_tile_ctr_r[1:0];
//8'h21: dbg_misc_data_r <= 0;
8'h22: dbg_misc_data_r <= ppu_tile_ctr_r;
8'h23: dbg_misc_data_r <= ppu_pix_ctr_r;
//8'h24: dbg_misc_data_r <= 0;
8'h25: dbg_misc_data_r <= ppu_first_frame_r;
8'h30: dbg_misc_data_r <= dbg_reg_ly_r[7:0];
8'h31: dbg_misc_data_r <= dbg_dot_ctr_r[7:0];
8'h32: dbg_misc_data_r <= dbg_dot_ctr_r[8:8];
8'h33: dbg_misc_data_r <= dbg_oam_active_r;
8'h34: dbg_misc_data_r <= dbg_vram_active_r;
8'h35: dbg_misc_data_r <= dbg_dma_active_r;
8'h40: dbg_misc_data_r <= ppu_stat_active_r;
8'h41: dbg_misc_data_r <= ppu_stat_match_r;
8'h42: dbg_misc_data_r <= dbg_ppu_stat_match_r;
8'h43: dbg_misc_data_r <= dbg_ppu_stat_dot_ctr_r[7:0];
8'h44: dbg_misc_data_r <= dbg_ppu_stat_dot_ctr_r[8:8];
//8'h45: dbg_misc_data_r <= dbg_timer_ly_r;
//8'h46: dbg_misc_data_r <= dbg_timer_dot_ctr_r[7:0];
//8'h47: dbg_misc_data_r <= dbg_timer_dot_ctr_r[8:8];
8'hA0: dbg_misc_data_r <= apu_square1_enable_r;
8'hA1: dbg_misc_data_r <= apu_square1_timer_r[7:0];
8'hA2: dbg_misc_data_r <= apu_square1_timer_r[12:8];
8'hA3: dbg_misc_data_r <= apu_square1_length_r;
8'hA4: dbg_misc_data_r <= apu_square1_env_timer_r;
8'hA5: dbg_misc_data_r <= apu_square1_volume_r;
8'hA6: dbg_misc_data_r <= apu_square1_pos_r;
8'hA7: dbg_misc_data_r <= apu_square1_sweep_enable_r;
8'hA8: dbg_misc_data_r <= apu_square1_sweep_freq_r[7:0];
8'hA9: dbg_misc_data_r <= apu_square1_sweep_freq_r[10:8];
8'hAA: dbg_misc_data_r <= apu_square1_period[7:0];
8'hAB: dbg_misc_data_r <= apu_square1_period[12:8];
//8'hAC: dbg_misc_data_r <= apu_square1_duty;
8'hAF: dbg_misc_data_r <= apu_square1_output[4:0];
8'hB0: dbg_misc_data_r <= apu_square2_enable_r;
8'hB1: dbg_misc_data_r <= apu_square2_timer_r[7:0];
8'hB2: dbg_misc_data_r <= apu_square2_timer_r[12:8];
8'hB3: dbg_misc_data_r <= apu_square2_length_r;
8'hB4: dbg_misc_data_r <= apu_square2_env_timer_r;
8'hB5: dbg_misc_data_r <= apu_square2_volume_r;
8'hB6: dbg_misc_data_r <= apu_square2_pos_r;
//8'hB7: dbg_misc_data_r <= apu_square2_sweep_enable_r;
//8'hB8: dbg_misc_data_r <= apu_square2_sweep_freq_r[7:0];
//8'hB9: dbg_misc_data_r <= apu_square2_sweep_freq_r[15:8];
8'hBA: dbg_misc_data_r <= apu_square2_period[7:0];
8'hBB: dbg_misc_data_r <= apu_square2_period[12:8];
//8'hBC: dbg_misc_data_r <= apu_square2_duty;
8'hBF: dbg_misc_data_r <= apu_square2_output[4:0];
8'hC0: dbg_misc_data_r <= apu_wave_enable_r;
8'hC1: dbg_misc_data_r <= apu_wave_length_r[7:0];
//8'hC2: dbg_misc_data_r <= 0;
8'hC3: dbg_misc_data_r <= apu_wave_pos_r;
8'hC4: dbg_misc_data_r <= apu_wave_timer_r[7:0];
8'hC5: dbg_misc_data_r <= apu_wave_timer_r[11:8];
//8'hC6: dbg_misc_data_r <= apu_wave_timer_r[23:16];
//8'hC7: dbg_misc_data_r <= apu_wave_timer_r[31:24];
8'hC8: dbg_misc_data_r <= apu_wave_period[7:0];
8'hC9: dbg_misc_data_r <= apu_wave_period[11:8];
8'hCF: dbg_misc_data_r <= apu_wave_output[4:0];
8'hD0: dbg_misc_data_r <= apu_noise_enable_r;
8'hD1: dbg_misc_data_r <= apu_noise_length_r;
8'hD2: dbg_misc_data_r <= apu_noise_env_timer_r;
8'hD3: dbg_misc_data_r <= apu_noise_volume_r;
8'hD4: dbg_misc_data_r <= apu_noise_timer_r[7:0];
8'hD5: dbg_misc_data_r <= apu_noise_timer_r[15:8];
8'hD6: dbg_misc_data_r <= apu_noise_timer_r[21:16];
//8'hD7: dbg_misc_data_r <= apu_noise_timer_r[31:24];
8'hD8: dbg_misc_data_r <= apu_noise_period[7:0];
8'hD9: dbg_misc_data_r <= apu_noise_period[15:8];
8'hDA: dbg_misc_data_r <= apu_noise_period[21:16];
//8'hDB: dbg_misc_data_r <= apu_noise_period[31:24];
8'hDC: dbg_misc_data_r <= apu_noise_lfsr_r[7:0];
8'hDD: dbg_misc_data_r <= apu_noise_lfsr_r[14:8];
8'hDF: dbg_misc_data_r <= apu_noise_output[4:0];
8'hE0: dbg_misc_data_r <= APU_DAT[7:0];
8'hE1: dbg_misc_data_r <= APU_DAT[9:8];
8'hE2: dbg_misc_data_r <= APU_DAT[17:10];
8'hE3: dbg_misc_data_r <= APU_DAT[19:18];
default: dbg_misc_data_r <= 0;
endcase
`endif
// ICD2
4'h6: dbg_misc_data_r <= DBG_ICD2_DATA_IN;
// CONFIG
4'h7: case(dbg_addr_r[7:0])
8'h00: dbg_misc_data_r <= config_r[0];
8'h01: dbg_misc_data_r <= config_r[1];
8'h02: dbg_misc_data_r <= config_r[2];
8'h03: dbg_misc_data_r <= config_r[3];
8'h04: dbg_misc_data_r <= config_r[4];
8'h05: dbg_misc_data_r <= config_r[5];
8'h06: dbg_misc_data_r <= config_r[6];
8'h07: dbg_misc_data_r <= config_r[7];
default: dbg_misc_data_r <= 0;
endcase
default: dbg_misc_data_r <= 0;
endcase
`endif
end
reg step_r;
assign DBG_EXE_step = step_r;
`ifdef SGB_DEBUG
assign {config_r[7],config_r[6],config_r[5],config_r[4],config_r[3],config_r[2],config_r[1],config_r[0]} = DBG_CONFIG;
assign dbg_brk_enabled = config_r[0][0];
assign dbg_brk_matchpartialinst = config_r[0][1];
//
wire [7:0] dbg_brk_stepcnt = config_r[1];
wire [7:0] dbg_brk_data_watch = config_r[4];
wire [15:0] dbg_brk_addr_watch = {config_r[6],config_r[5]};
// breakpoints
reg dbg_brk_inst_rd_byte = 0;
reg dbg_brk_data_rd_byte = 0;
reg dbg_brk_data_wr_byte = 0;
reg dbg_brk_inst_rd_addr = 0;
reg dbg_brk_data_rd_addr = 0;
reg dbg_brk_data_wr_addr = 0;
reg dbg_brk_data = 0;
reg dbg_brk_stop = 0;
reg dbg_brk_error = 0;
reg [15:0] dbg_brk_addr_r;
reg [7:0] dbg_brk_data_r;
reg [7:0] stepcnt_r = 0;
always @(posedge CLK) begin
step_r <= ~dbg_brk_enabled | (stepcnt_r != dbg_brk_stepcnt);
if (CLK_BUS_EDGE & exe_advance_r) stepcnt_r <= dbg_brk_stepcnt;
end
assign DBG_BRK = |(config_r[2] & {dbg_brk_error,dbg_brk_stop,dbg_brk_data_wr_addr,dbg_brk_data_rd_addr,dbg_brk_inst_rd_addr,dbg_brk_data_wr_byte,dbg_brk_data_rd_byte,dbg_brk_inst_rd_byte});// | RST;
reg dbg_mem_req_val_d1_r;
reg dbg_mem_req_wr_d1_r;
reg [15:0] dbg_mct_vram_error_r;
reg [15:0] dbg_mct_oam_error_r;
always @(posedge CLK) begin
if (RST) begin
dbg_brk_inst_rd_byte <= 0;
dbg_brk_data_rd_byte <= 0;
dbg_brk_data_wr_byte <= 0;
dbg_brk_inst_rd_addr <= 0;
dbg_brk_data_rd_addr <= 0;
dbg_brk_data_wr_addr <= 0;
dbg_brk_stop <= 0;
dbg_brk_error <= 0;
dbg_brk_addr_r <= 0;
end
else begin
dbg_brk_inst_rd_addr <= IFD_EXE_valid && (IFD_EXE_pc_start == dbg_brk_addr_r);
dbg_brk_data_rd_addr <= (exe_advance_r && exe_complete_r) ? 0 : (IFD_EXE_valid && dbg_mem_req_val_d1_r && ~dbg_mem_req_wr_d1_r && EXE_MCT_req_addr_d1 == dbg_brk_addr_r); //&& (!config_r[2][0] || mmc_data_r[7:0] == dbg_brk_data_r);
dbg_brk_data_wr_addr <= (exe_advance_r && exe_complete_r) ? 0 : (IFD_EXE_valid && dbg_mem_req_val_d1_r && dbg_mem_req_wr_d1_r && EXE_MCT_req_addr_d1 == dbg_brk_addr_r && (!config_r[2][0] || EXE_MCT_req_data_d1 == dbg_brk_data_r));
dbg_brk_stop <= IFD_EXE_valid & IFD_EXE_int;
dbg_brk_error <= ( 0
|| (mct_vram_error_r != dbg_mct_vram_error_r)
|| (mct_oam_error_r != dbg_mct_oam_error_r)
);
dbg_brk_addr_r <= dbg_brk_addr_watch;
dbg_brk_data_r <= dbg_brk_data_watch;
dbg_mem_req_val_d1_r <= EXE_MCT_req_val;
dbg_mem_req_wr_d1_r <= EXE_MCT_req_wr;
dbg_mct_vram_error_r <= mct_vram_error_r;
dbg_mct_oam_error_r <= mct_oam_error_r;
end
end
`else
always @(posedge CLK) step_r <= 1;
assign DBG_BRK = 0;
`endif
endmodule
|
//# 18 inputs
//# 19 outputs
//# 5 D-type flipflops
//# 33 inverters
//# 256 gates (76 ANDs + 54 NANDs + 60 ORs + 66 NORs)
module s820(GND,VDD,CK,G0,G1,G10,G11,G12,G13,G14,G15,G16,G18,G2,G288,G290,G292,
G296,G298,
G3,G300,G302,G310,G312,G315,G322,G325,G327,G4,G43,G45,G47,G49,G5,G53,G55,G6,
G7,G8,G9);
input GND,VDD,CK,G0,G1,G2,G3,G4,G5,G6,G7,G8,G9,G10,G11,G12,G13,G14,G15,G16,G18;
output G290,G327,G47,G55,G288,G296,G310,G312,G325,G300,G43,G53,G298,G315,G322,
G49,G45,G292,G302;
wire G38,G90,G39,G93,G40,G96,G41,G99,G42,G102,G245,G323,G181,G256,G130,G203,
G202,G112,G198,G171,G172,G168,G201,G267,G317,G281,G313,G328,G88,G91,G94,
G97,G100,G280,G318,II127,G228,II130,G229,II133,G231,II198,G247,G143,G161,
G162,G163,G188,G189,G190,G195,G215,G120,G250,G118,G166,G199,G170,G169,G129,
G265,G142,G279,G103,G164,G167,G191,G200,G214,G234,G283,G141,G140,G127,G160,
G187,G193,G194,G213,G235,G249,G268,G276,G282,G117,G277,G278,G121,G128,G232,
G233,G251,G252,G271,G270,G210,G209,G226,G225,G175,G176,G197,G196,G263,G262,
G150,G147,G148,G149,G158,G157,G185,G184,G174,G173,G211,G212,G223,G222,G272,
G274,G264,G266,G294,G293,G152,G154,G218,G216,G217,G151,G153,G273,G275,G258,
G257,G219,G220,G259,G260,G89,G92,G95,G98,G101,G126,G124,G125,G107,G145,
G243,G111,G144,G239,G287,G115,G183,G237,G246,G113,G132,G133,G182,G238,G241,
G136,G116,G286,G108,G109,G240,G242,G244,G110,G134,G135,G114,G236,G248,G321,
G319,G180,G178,G78,G73,G74,G285,G284,G63,G59,G106,G105,G308,G304,G320,G316,
G52,G50,G139,G137,G255,G253,G207,G204,G205,G309,G305,G62,G57,G58,G307,G303,
G85,G81,G67,G177,G70,G65,G66,G155,G79,G75,G64,G60,G72,G68,G71,G86,G82,G80,
G76,G87,G83,G123,G295,G291,G329,G48,G56,G289,G297,G311,G314,G326,G301,G119,
G44,G54,G156,G299,G179,G224,G227,G131,G269,G46,G122,G69,G306,G138,G84,G254,
G51,G61,G146,G206,G77,G165,G192,G104,G324,G159,G186,G221,G261;
dff DFF_0(CK,G38,G90);
dff DFF_1(CK,G39,G93);
dff DFF_2(CK,G40,G96);
dff DFF_3(CK,G41,G99);
dff DFF_4(CK,G42,G102);
not NOT_0(G245,G0);
not NOT_1(G323,G1);
not NOT_2(G181,G2);
not NOT_3(G256,G4);
not NOT_4(G130,G5);
not NOT_5(G203,G6);
not NOT_6(G202,G7);
not NOT_7(G112,G8);
not NOT_8(G198,G9);
not NOT_9(G171,G10);
not NOT_10(G172,G11);
not NOT_11(G168,G12);
not NOT_12(G201,G13);
not NOT_13(G267,G15);
not NOT_14(G317,G40);
not NOT_15(G281,G16);
not NOT_16(G313,G41);
not NOT_17(G328,G42);
not NOT_18(G88,G18);
not NOT_19(G91,G18);
not NOT_20(G94,G18);
not NOT_21(G97,G18);
not NOT_22(G100,G18);
not NOT_23(G280,G38);
not NOT_24(G318,G39);
not NOT_25(II127,G38);
not NOT_26(G228,II127);
not NOT_27(II130,G15);
not NOT_28(G229,II130);
not NOT_29(II133,G313);
not NOT_30(G231,II133);
not NOT_31(II198,G38);
not NOT_32(G247,II198);
and AND2_0(G143,G40,G4);
and AND2_1(G161,G3,G42);
and AND2_2(G162,G1,G42);
and AND2_3(G163,G41,G42);
and AND2_4(G188,G3,G42);
and AND2_5(G189,G1,G42);
and AND2_6(G190,G41,G42);
and AND2_7(G195,G41,G42);
and AND2_8(G215,G41,G42);
and AND3_0(G120,G39,G40,G42);
and AND3_1(G250,G39,G40,G42);
and AND3_2(G118,G245,G38,G39);
and AND3_3(G166,G245,G38,G42);
and AND3_4(G199,G245,G38,G42);
and AND2_9(G170,G171,G172);
and AND2_10(G169,G172,G168);
and AND2_11(G129,G39,G317);
and AND2_12(G265,G317,G267);
and AND2_13(G142,G40,G281);
and AND2_14(G279,G281,G42);
and AND2_15(G103,G313,G38);
and AND2_16(G164,G42,G313);
and AND3_5(G167,G256,G38,G313);
and AND2_17(G191,G42,G313);
and AND3_6(G200,G256,G38,G313);
and AND2_18(G214,G267,G16);
and AND4_0(G234,G15,G40,G313,G42);
and AND2_19(G283,G317,G313);
and AND4_1(G141,G317,G16,G323,G140);
and AND4_2(G127,G38,G39,G313,G328);
and AND3_7(G160,G5,G313,G328);
and AND3_8(G187,G5,G313,G328);
and AND2_20(G193,G11,G328);
and AND2_21(G194,G10,G328);
and AND3_9(G213,G16,G313,G328);
and AND2_22(G235,G317,G328);
and AND3_10(G249,G40,G41,G328);
and AND2_23(G268,G328,G267);
and AND3_11(G276,G0,G38,G328);
and AND2_24(G282,G317,G328);
and AND3_12(G117,G1,G39,G313);
and AND3_13(G277,G323,G281,G280);
and AND2_25(G278,G280,G42);
and AND3_14(G121,G318,G317,G328);
and AND3_15(G128,G280,G318,G40);
and AND2_26(G232,G38,G318);
and AND2_27(G233,G15,G318);
and AND2_28(G251,G318,G313);
and AND2_29(G252,G318,G317);
and AND4_3(G271,G318,G15,G14,G270);
and AND4_4(G210,G39,G38,G245,G209);
and AND2_30(G226,G318,G225);
and AND2_31(G175,G317,G176);
and AND4_5(G197,G8,G7,G6,G196);
and AND3_16(G263,G39,G38,G262);
and AND4_6(G150,G256,G147,G148,G149);
and AND2_32(G158,G280,G157);
and AND2_33(G185,G280,G184);
and AND4_7(G174,G41,G40,G15,G173);
and AND4_8(G211,G317,G39,G256,G212);
and AND2_34(G223,G16,G222);
and AND3_17(G272,G318,G4,G274);
and AND2_35(G264,G318,G266);
and AND2_36(G294,G16,G293);
and AND4_9(G152,G313,G317,G318,G154);
and AND4_10(G218,G2,G323,G216,G217);
and AND4_11(G151,G38,G16,G256,G153);
and AND3_18(G273,G40,G39,G275);
and AND3_19(G258,G318,G280,G257);
and AND2_37(G219,G318,G220);
and AND2_38(G259,G41,G260);
and AND2_39(G90,G89,G88);
and AND2_40(G93,G92,G91);
and AND2_41(G96,G95,G94);
and AND2_42(G99,G98,G97);
and AND2_43(G102,G101,G100);
or OR2_0(G126,G10,G11);
or OR2_1(G124,G11,G12);
or OR2_2(G125,G10,G12);
or OR3_0(G107,G41,G40,G1);
or OR2_3(G145,G16,G41);
or OR2_4(G243,G5,G41);
or OR2_5(G111,G15,G42);
or OR2_6(G144,G16,G42);
or OR3_1(G239,G40,G41,G42);
or OR2_7(G287,G42,G5);
or OR2_8(G115,G39,G42);
or OR3_2(G183,G38,G39,G41);
or OR3_3(G237,G16,G39,G40);
or OR2_9(G246,G4,G39);
or OR4_0(G113,G203,G202,G112,G198);
or OR4_1(G132,G171,G11,G12,G42);
or OR4_2(G133,G10,G172,G12,G42);
or OR4_3(G182,G14,G267,G38,G39);
or OR4_4(G238,G14,G267,G40,G42);
or OR2_10(G241,G256,G317);
or OR2_11(G136,G4,G281);
or OR2_12(G116,G39,G313);
or OR2_13(G286,G42,G313);
or OR2_14(G108,G328,G15);
or OR3_4(G109,G201,G267,G328);
or OR3_5(G240,G256,G313,G328);
or OR2_15(G242,G41,G328);
or OR2_16(G244,G281,G328);
or OR2_17(G110,G280,G42);
or OR2_18(G134,G280,G42);
or OR2_19(G135,G280,G40);
or OR3_6(G114,G267,G318,G328);
or OR3_7(G236,G318,G317,G328);
or OR2_20(G248,G245,G318);
or OR4_5(G321,G317,G318,G38,G319);
or OR2_21(G180,G41,G178);
or OR4_6(G78,G39,G4,G73,G74);
or OR4_7(G285,G3,G2,G1,G284);
or OR4_8(G63,G40,G318,G4,G59);
or OR4_9(G106,G8,G7,G203,G105);
or OR4_10(G308,G40,G318,G16,G304);
or OR4_11(G320,G40,G39,G38,G316);
or OR4_12(G52,G328,G313,G39,G50);
or OR2_22(G139,G317,G137);
or OR2_23(G255,G317,G253);
or OR4_13(G207,G202,G203,G204,G205);
or OR3_8(G309,G39,G38,G305);
or OR4_14(G62,G267,G4,G57,G58);
or OR4_15(G307,G328,G313,G39,G303);
or OR4_16(G85,G328,G313,G317,G81);
or OR3_9(G67,G174,G175,G177);
or OR4_17(G70,G318,G4,G65,G66);
or OR4_18(G89,G150,G151,G152,G155);
or OR4_19(G79,G40,G281,G4,G75);
or OR3_10(G64,G317,G318,G60);
or OR3_11(G72,G317,G318,G68);
or OR4_20(G71,G39,G281,G4,G67);
or OR2_24(G86,G38,G82);
or OR2_25(G80,G38,G76);
or OR2_26(G87,G281,G83);
nand NAND2_0(G204,G9,G8);
nand NAND3_0(G73,G42,G41,G40);
nand NAND2_1(G319,G42,G41);
nand NAND4_0(G123,G124,G125,G126,G256);
nand NAND3_1(G65,G42,G41,G317);
nand NAND4_1(G295,G41,G317,G39,G256);
nand NAND2_2(G284,G42,G313);
nand NAND4_2(G291,G313,G317,G39,G15);
nand NAND4_3(G329,G313,G317,G39,G15);
nand NAND2_3(G59,G144,G145);
nand NAND4_4(G105,G328,G40,G15,G9);
nand NAND2_4(G225,G41,G256);
nand NAND2_5(G316,G328,G313);
nand NAND4_5(G48,G40,G39,G280,G130);
nand NAND4_6(G56,G40,G39,G280,G5);
nand NAND4_7(G176,G42,G41,G280,G15);
nand NAND4_8(G289,G313,G40,G39,G280);
nand NAND4_9(G297,G41,G40,G39,G280);
nand NAND4_10(G311,G313,G40,G39,G280);
nand NAND4_11(G314,G40,G39,G280,G16);
nand NAND4_12(G326,G313,G40,G39,G280);
nand NAND4_13(G301,G281,G3,G323,G119);
nand NAND4_14(G44,G317,G318,G280,G15);
nand NAND4_15(G54,G41,G317,G318,G280);
nand NAND4_16(G57,G41,G40,G318,G16);
nand NAND3_2(G156,G318,G280,G281);
nand NAND4_17(G299,G318,G280,G15,G14);
nand NAND2_6(G262,G113,G317);
nand NAND2_7(G179,G182,G183);
nand NAND2_8(G205,G228,G229);
nand NAND4_18(G224,G238,G239,G240,G241);
nand NAND4_19(G227,G242,G243,G244,G40);
nand NAND4_20(G266,G109,G110,G111,G40);
nand NAND4_21(G293,G8,G7,G6,G131);
nand NAND3_3(G58,G132,G133,G134);
nand NAND2_9(G303,G135,G136);
nand NAND4_22(G269,G114,G115,G116,G317);
nand NAND2_10(G217,G236,G237);
nand NAND3_4(G81,G246,G247,G248);
nand NAND4_23(G46,G318,G280,G16,G122);
nand NAND4_24(G69,G180,G328,G317,G179);
nand NAND3_5(G275,G285,G286,G287);
nand NAND3_6(G257,G106,G107,G108);
nand NAND2_11(G315,G320,G321);
nand NAND2_12(G306,G139,G138);
nand NAND2_13(G84,G255,G254);
nand NAND2_14(G49,G52,G51);
nand NAND4_25(G61,G328,G313,G317,G146);
nand NAND2_15(G75,G207,G206);
nand NAND4_26(G302,G307,G308,G309,G306);
nand NAND4_27(G92,G62,G63,G64,G61);
nand NAND4_28(G95,G70,G71,G72,G69);
nand NAND4_29(G98,G78,G79,G80,G77);
nand NAND4_30(G101,G85,G86,G87,G84);
nor NOR2_0(G216,G41,G3);
nor NOR2_1(G140,G42,G41);
nor NOR2_2(G119,G39,G38);
nor NOR4_0(G178,G16,G3,G181,G1);
nor NOR3_0(G74,G281,G267,G201);
nor NOR3_1(G147,G38,G281,G267);
nor NOR4_1(G148,G42,G313,G317,G39);
nor NOR3_2(G270,G42,G313,G40);
nor NOR3_3(G209,G328,G313,G317);
nor NOR2_3(G304,G328,G313);
nor NOR2_4(G50,G40,G280);
nor NOR3_4(G131,G280,G267,G198);
nor NOR3_5(G137,G42,G41,G280);
nor NOR2_5(G177,G195,G280);
nor NOR3_6(G196,G280,G267,G198);
nor NOR3_7(G253,G42,G41,G280);
nor NOR2_6(G138,G318,G256);
nor NOR2_7(G254,G318,G256);
nor NOR2_8(G122,G267,G123);
nor NOR2_9(G149,G169,G170);
nor NOR2_10(G165,G166,G167);
nor NOR2_11(G192,G199,G200);
nor NOR2_12(G290,G42,G291);
nor NOR2_13(G327,G328,G329);
nor NOR3_8(G305,G141,G142,G143);
nor NOR4_2(G157,G160,G161,G162,G163);
nor NOR4_3(G184,G187,G188,G189,G190);
nor NOR2_14(G173,G193,G194);
nor NOR3_9(G212,G213,G214,G215);
nor NOR2_15(G222,G234,G235);
nor NOR2_16(G274,G282,G283);
nor NOR3_10(G47,G42,G41,G48);
nor NOR3_11(G55,G42,G41,G56);
nor NOR2_17(G104,G117,G118);
nor NOR4_4(G154,G276,G277,G278,G279);
nor NOR2_18(G288,G42,G289);
nor NOR2_19(G296,G42,G297);
nor NOR2_20(G310,G328,G311);
nor NOR3_12(G312,G328,G313,G314);
nor NOR2_21(G325,G328,G326);
nor NOR4_5(G300,G42,G41,G40,G301);
nor NOR3_13(G43,G42,G313,G44);
nor NOR2_22(G53,G42,G54);
nor NOR2_23(G324,G120,G121);
nor NOR3_14(G51,G127,G128,G129);
nor NOR4_6(G146,G3,G181,G1,G156);
nor NOR3_15(G206,G231,G232,G233);
nor NOR4_7(G153,G249,G250,G251,G252);
nor NOR4_8(G298,G42,G313,G40,G299);
nor NOR2_24(G159,G164,G165);
nor NOR2_25(G186,G191,G192);
nor NOR2_26(G221,G226,G227);
nor NOR4_9(G155,G103,G328,G317,G104);
nor NOR2_27(G66,G197,G281);
nor NOR2_28(G261,G268,G269);
nor NOR4_10(G322,G41,G38,G323,G324);
nor NOR4_11(G45,G42,G313,G317,G46);
nor NOR2_29(G60,G158,G159);
nor NOR2_30(G68,G185,G186);
nor NOR2_31(G77,G210,G211);
nor NOR2_32(G220,G223,G224);
nor NOR3_16(G260,G263,G264,G265);
nor NOR3_17(G292,G294,G328,G295);
nor NOR3_18(G82,G271,G272,G273);
nor NOR3_19(G76,G218,G219,G221);
nor NOR3_20(G83,G258,G259,G261);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O32AI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O32AI_BLACKBOX_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O32AI_BLACKBOX_V
|
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20
module test_padder;
// Inputs
reg clk;
reg reset;
reg [31:0] in;
reg in_ready;
reg is_last;
reg [1:0] byte_num;
reg f_ack;
// Outputs
wire buffer_full;
wire [575:0] out;
wire out_ready;
// Var
integer i;
// Instantiate the Unit Under Test (UUT)
padder uut (
.clk(clk),
.reset(reset),
.in(in),
.in_ready(in_ready),
.is_last(is_last),
.byte_num(byte_num),
.buffer_full(buffer_full),
.out(out),
.out_ready(out_ready),
.f_ack(f_ack)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
in = 0;
in_ready = 0;
is_last = 0;
byte_num = 0;
f_ack = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
// pad an empty string, should not eat next input
reset = 1; #(`P); reset = 0;
#(7*`P); // wait some cycles
if (buffer_full !== 0) error;
in_ready = 1;
is_last = 1;
#(`P);
in_ready = 1; // next input
is_last = 1;
#(`P);
in_ready = 0;
is_last = 0;
while (out_ready !== 1)
#(`P);
check({8'h1, 560'h0, 8'h80});
f_ack = 1; #(`P); f_ack = 0;
for(i=0; i<5; i=i+1)
begin
#(`P);
if (buffer_full !== 0) error; // should be 0
end
// pad an (576-8) bit string
reset = 1; #(`P); reset = 0;
#(4*`P); // wait some cycles
in_ready = 1; is_last = 0;
byte_num = 3; /* should have no effect */
for (i=0; i<8; i=i+1)
begin
in = 32'h12345678; #(`P);
in = 32'h90ABCDEF; #(`P);
end
in = 32'h12345678; #(`P);
in = 32'h90ABCDEF; is_last = 1; #(`P);
in_ready = 0;
is_last = 0;
check({ {8{64'h1234567890ABCDEF}}, 64'h1234567890ABCD81 });
// pad an (576-64) bit string
reset = 1; #(`P); reset = 0;
// don't wait any cycle
in_ready = 1; is_last = 0;
byte_num = 1; /* should have no effect */
for (i=0; i<8; i=i+1)
begin
in = 32'h12345678; #(`P);
in = 32'h90ABCDEF; #(`P);
end
is_last = 1;
byte_num = 0;
#(`P);
in_ready = 0;
is_last = 0;
#(`P);
check({ {8{64'h1234567890ABCDEF}}, 64'h0100000000000080 });
// pad an (576*2-16) bit string
reset = 1; #(`P); reset = 0;
in_ready = 1;
byte_num = 7; /* should have no effect */
is_last = 0;
for (i=0; i<9; i=i+1)
begin
in = 32'h12345678; #(`P);
in = 32'h90ABCDEF; #(`P);
end
if (out_ready !== 1) error;
check({9{64'h1234567890ABCDEF}});
#(`P/2);
if (buffer_full !== 1) error; // should not eat
#(`P/2);
in = 64'h999; // should not eat this
#(`P/2);
if (buffer_full !== 1) error; // should not eat
#(`P/2);
f_ack = 1; #(`P); f_ack = 0;
if (out_ready !== 0) error;
// feed next (576-16) bit
for (i=0; i<8; i=i+1)
begin
in = 32'h12345678; #(`P);
in = 32'h90ABCDEF; #(`P);
end
in = 32'h12345678; #(`P);
byte_num = 2;
is_last = 1;
in = 32'h90ABCDEF; #(`P);
if (out_ready !== 1) error;
check({ {8{64'h1234567890ABCDEF}}, 64'h1234567890AB0180 });
is_last = 0;
// eat these bits
f_ack = 1; #(`P); f_ack = 0;
// should not provide any more bits, if user provides nothing
in_ready = 0;
is_last = 0;
for (i=0; i<10; i=i+1)
begin
if (out_ready === 1) error;
#(`P);
end
in_ready = 0;
$display("Good!");
$finish;
end
always #(`P/2) clk = ~ clk;
task error;
begin
$display("E");
$finish;
end
endtask
task check;
input [575:0] wish;
begin
if (out !== wish)
begin
$display("out:%h wish:%h", out, wish);
error;
end
end
endtask
endmodule
`undef P
|
`default_nettype none
// ============================================================================
module serializer #
(
parameter WIDTH = 4, // Serialization rate
parameter MODE = "SDR" // "SDR" or "DDR"
)
(
// Clock & reset
input wire CLK,
input wire RST,
// Data input
input wire[WIDTH-1:0] I,
output wire RD,
output wire CE,
// Serialized output
output wire O_CLK,
output wire O_DAT
);
// ============================================================================
generate if (MODE == "DDR" && (WIDTH & 1)) begin
error for_DDR_mode_the_WIDTH_must_be_even ();
end endgenerate
// ============================================================================
// Output clock generation
reg o_clk;
wire ce;
always @(posedge CLK)
if (RST) o_clk <= 1'd1;
else o_clk <= !o_clk;
assign ce = !o_clk;
// ============================================================================
reg [7:0] count;
reg [WIDTH-1:0] sreg;
wire sreg_ld;
always @(posedge CLK)
if (RST) count <= 2;
else if (ce) begin
if (count == 0) count <= ((MODE == "DDR") ? (WIDTH/2) : WIDTH) - 1;
else count <= count - 1;
end
assign sreg_ld = (count == 0);
always @(posedge CLK)
if (ce) begin
if (sreg_ld) sreg <= I;
else sreg <= sreg << ((MODE == "DDR") ? 2 : 1);
end
wire [1:0] o_dat = sreg[WIDTH-1:WIDTH-2];
// ============================================================================
// SDR/DDR output FFs
reg o_reg;
always @(posedge CLK)
if (!o_clk && MODE == "SDR") o_reg <= o_dat[1]; // +
else if (!o_clk && MODE == "DDR") o_reg <= o_dat[0]; // +
else if ( o_clk && MODE == "DDR") o_reg <= o_dat[1]; // -
else o_reg <= o_reg;
// ============================================================================
assign O_DAT = o_reg;
assign O_CLK = o_clk;
assign RD = (count == 1);
assign CE = ce;
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/16.1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2016/08/07 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
(** * Imp: Simple Imperative Programs *)
(** In this chapter, we begin a new direction that will continue for
the rest of the course. Up to now most of our attention has been
focused on various aspects of Coq itself, while from now on we'll
mostly be using Coq to formalize other things. (We'll continue to
pause from time to time to introduce a few additional aspects of
Coq.)
Our first case study is a _simple imperative programming language_
called Imp, embodying a tiny core fragment of conventional
mainstream languages such as C and Java. Here is a familiar
mathematical function written in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
*)
(** This chapter looks at how to define the _syntax_ and _semantics_
of Imp; the chapters that follow develop a theory of _program
equivalence_ and introduce _Hoare Logic_, a widely used logic for
reasoning about imperative programs. *)
Require Import Coq.Bool.Bool.
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import Coq.omega.Omega.
Require Import Coq.Lists.List.
Import ListNotations.
Require Import Maps.
Require Import SfLib. (* for [admit] *)
(* ####################################################### *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ####################################################### *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(** In this chapter, we'll elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1+2*3"] to the AST [APlus (ANum
1) (AMult (ANum 2) (ANum 3))]. The optional chapter [ImpParser]
develops a simple implementation of a lexical analyzer and parser
that can perform this translation. You do _not_ need to
understand that file to understand this one, but if you haven't
taken a course where these techniques are covered (e.g., a
compilers course) you may want to skim it. *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
a ::= nat
| a + a
| a - a
| a * a
b ::= true
| false
| a = a
| a <= a
| not b
| b and b
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written [+] and is an
infix symbol) while leaving other aspects of lexical analysis
and parsing (like the relative precedence of [+], [-], and
[*]) unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition (when implementing a compiler, for
example).
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- On the other hand, the BNF version is lighter and
easier to read. Its informality makes it flexible, which is
a huge advantage in situations like discussions at the
blackboard, where conveying general ideas is more important
than getting every detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say which
form of BNF they're using because there is no need to: a
rough-and-ready informal understanding is all that's
needed. *)
(** It's good to be comfortable with both sorts of notations:
informal ones for communicating between humans and formal ones for
carrying out implementations and proofs. *)
(* ####################################################### *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (a : aexp) : nat :=
match a with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval a1) (aeval a2)
| BLe a1 a2 => leb (aeval a1) (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ####################################################### *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0+e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (a:aexp) : aexp :=
match a with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a. induction a.
- (* ANum *) reflexivity.
- (* APlus *) destruct a1.
+ (* a1 = ANum n *) destruct n.
* (* n = 0 *) simpl. apply IHa2.
* (* n <> 0 *) simpl. rewrite IHa2. reflexivity.
+ (* a1 = APlus a1_1 a1_2 *)
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
+ (* a1 = AMinus a1_1 a1_2 *)
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
+ (* a1 = AMult a1_1 a1_2 *)
simpl. simpl in IHa1. rewrite IHa1.
rewrite IHa2. reflexivity.
- (* AMinus *)
simpl. rewrite IHa1. rewrite IHa2. reflexivity.
- (* AMult *)
simpl. rewrite IHa1. rewrite IHa2. reflexivity. Qed.
(* ####################################################### *)
(** * Coq Automation *)
(** The repetition in this last proof is starting to be a little
annoying. If either the language of arithmetic expressions or the
optimization being proved sound were significantly more complex,
it would begin to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ####################################################### *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ####################################################### *)
(** *** The [try] Tactical *)
(** If [T] is a tactic, then [try T] is a tactic that is just like [T]
except that, if [T] fails, [try T] _successfully_ does nothing at
all (instead of failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof. try reflexivity. (* this just does [reflexivity] *) Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros P HP.
try reflexivity. (* just [reflexivity] would have failed *)
apply HP. (* we can still finish the proof in some other way *)
Qed.
(** Using [try] in a completely manual proof is a bit silly, but
we'll see below that [try] is very useful for doing automated
proofs in conjunction with the [;] tactical. *)
(* ####################################################### *)
(** *** The [;] Tactical (Simple Form) *)
(** In its most commonly used form, the [;] tactical takes two tactics
as argument: [T;T'] first performs the tactic [T] and then
performs the tactic [T'] on _each subgoal_ generated by [T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, leb 0 n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals, which are discharged identically... *)
- (* n=0 *) simpl. reflexivity.
- (* n=Sn' *) simpl. reflexivity.
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, leb 0 n = true.
Proof.
intros.
destruct n; (* [destruct] the current goal *)
simpl; (* then [simpl] each resulting subgoal *)
reflexivity. (* and do [reflexivity] on each resulting subgoal *)
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
(* The remaining cases -- ANum and APlus -- are different *)
- (* ANum *) reflexivity.
- (* APlus *)
destruct a1;
(* Again, most cases follow directly by the IH *)
try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
(* The interesting case, on which the [try...] does nothing,
is when [e1 = ANum n]. In this case, we have to destruct
[n] (to see whether the optimization applies) and rewrite
with the induction hypothesis. *)
+ (* a1 = ANum n *) destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** Coq experts often use this "[...; try... ]" idiom after a tactic
like [induction] to take care of many similar cases all at once.
Naturally, this practice has an analog in informal proofs.
Here is an informal proof of this theorem that matches the
structure of the formal one:
_Theorem_: For all arithmetic expressions [a],
aeval (optimize_0plus a) = aeval a.
_Proof_: By induction on [a]. The [AMinus] and [AMult] cases
follow directly from the IH. The remaining cases are as follows:
- Suppose [a = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [a = APlus a1 a2] for some [a1] and [a2]. We
must show
aeval (optimize_0plus (APlus a1 a2))
= aeval (APlus a1 a2).
Consider the possible forms of [a1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [a1]; in these cases, the result follows directly from the
IH.
The interesting case is when [a1 = ANum n] for some [n].
If [n = ANum 0], then
optimize_0plus (APlus a1 a2) = optimize_0plus a2
and the IH for [a2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** This proof can still be improved: the first case (for [a = ANum
n]) is very trivial -- even more trivial than the cases that we
said simply followed from the IH -- yet we have chosen to write it
out in full. It would be better and clearer to drop it and just
say, at the top, "Most cases are either immediate or direct from
the IH. The only interesting case is the one for [APlus]..." We
can make the same improvement in our formal proof too. Here's how
it looks: *)
Theorem optimize_0plus_sound'': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when a = APlus a1 a2. *)
- (* APlus *)
destruct a1; try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
+ (* a1 = ANum n *) destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(* ####################################################### *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical also has a more general form than the simple
[T;T'] we've seen above, which is sometimes also useful. If [T],
[T1], ..., [Tn] are tactics, then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e. [T;T'] is just a shorthand for:
T; [T' | T' | ... | T']
*)
(* ####################################################### *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying
this tactic until the tactic fails. Here is an example showing
that [100] is even using repeat. *)
Theorem In10 : In 10 [1;2;3;4;5;6;7;8;9;10].
Proof.
repeat (right; try (left; reflexivity)).
Qed.
(* Print In10. *)
(** The [repeat T] tactic never fails; if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (it repeats zero times). *)
Theorem In10' : In 10 [1;2;3;4;5;6;7;8;9;10].
Proof.
repeat (left; reflexivity).
repeat (right; try (left; reflexivity)).
Qed.
(** The [repeat T] tactic does not have any bound on the number of
times it applies [T]. If [T] is a tactic that always succeeds then
repeat [T] will loop forever (e.g. [repeat simpl] loops forever
since [simpl] always succeeds). While Coq's term language is
guaranteed to terminate, Coq's tactic language is not! *)
(* ####################################################### *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic scripts.
- The [Tactic Notation] idiom illustrated below gives a handy
way to define "shorthand tactics" that bundle several tactics
into a single command.
- For more sophisticated programming, Coq offers a small
built-in programming language called [Ltac] with primitives
that can examine and modify the proof state. The details are
a bit too complicated to get into here (and it is generally
agreed that [Ltac] is not the most beautiful part of Coq's
design!), but they can be found in the reference manual, and
there are many examples of [Ltac] definitions in the Coq
standard library that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but
this is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips with,
and it offers plenty of power for many purposes. Here's an example.
*)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(** This defines a new tactical called [simpl_and_try] which
takes one tactic [c] as an argument, and is defined to be
equivalent to the tactic [simpl; try c]. For example, writing
"[simpl_and_try reflexivity.]" in a proof would be the same as
writing "[simpl; try reflexivity.]" *)
(** The next subsection gives a more sophisticated use of this
feature... *)
(* ####################################################### *)
(** *** Bulletproofing Case Analyses *)
(** Being able to deal with most of the cases of an [induction]
or [destruct] all at the same time is very convenient, but it can
also be a little confusing. One problem that often comes up is
that _maintaining_ proofs written in this style can be difficult.
For example, suppose that, later, we extended the definition of
[aexp] with another constructor that also required a special
argument. The above proof might break because Coq generated the
subgoals for this constructor before the one for [APlus], so that,
at the point when we start working on the [APlus] case, Coq is
actually expecting the argument for a completely different
constructor. What we'd like is to get a sensible error message
saying "I was expecting the [AFoo] case at this point, but the
proof script is talking about [APlus]." Here's a nice trick (due
to Aaron Bohannon) that smoothly achieves this. *)
(*
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
*)
(** ([Case_aux] implements the common functionality of [Case],
[SCase], [SSCase], etc. For example, [Case "foo"] is defined as
[Case_aux Case "foo".) *)
(** For example, if [a] is a variable of type [aexp], then doing
aexp_cases (induction a) Case
will perform an induction on [a] (the same as if we had just typed
[induction a]) and _also_ add a [Case] tag to each subgoal
generated by the [induction], labeling which constructor it comes
from. For example, here is yet another proof of
[optimize_0plus_sound], using [aexp_cases]: *)
Theorem optimize_0plus_sound''': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
try reflexivity.
(* At this point, there is already an ["APlus"] case name
in the context. The [Case "APlus"] here in the proof
text has the effect of a sanity check: if the "Case"
string in the context is anything _other_ than ["APlus"]
(for example, because we added a clause to the definition
of [aexp] and forgot to change the proof) we'll get a
helpful error at this point telling us that this is now
the wrong case. *)
- (* APlus *)
destruct a1;
try (simpl; simpl in IHa1;
rewrite IHa1; rewrite IHa2; reflexivity).
+ (* ANum *) destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** **** Exercise: 3 stars (optimize_0plus_b) *)
(** Since the [optimize_0plus] tranformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function which performs that transformation on [bexp]s, and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Fixpoint optimize_0plus_b (b : bexp) : bexp :=
(* FILL IN HERE *) admit.
Theorem optimize_0plus_b_sound : forall b,
beval (optimize_0plus_b b) = beval b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, optional (optimizer) *)
(** _Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many imaginable
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct.
* FILL IN HERE *
*)
(** [] *)
(* ####################################################### *)
(** ** The [omega] Tactic *)
(** The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented in 1992 by William Pugh.
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and inequality ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or tell you that
it is actually false. *)
Require Import Coq.omega.Omega.
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. omega.
Qed.
(** Leibniz wrote, "It is unworthy of excellent men to lose
hours like slaves in the labor of calculation which could be
relegated to anyone else if machines were used." We recommend
using the omega tactic whenever possible. *)
(* ####################################################### *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: Find an assumption [x = e] or [e = x] in the
context, replace [x] with [e] throughout the context and
current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x].
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, behave just like
[apply H].
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c]. *)
(** We'll see many examples of these in the proofs below. *)
(* ####################################################### *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoint]s. Another way to think about evaluation -- one that we
will see is often more flexible -- is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic
expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n: nat),
aevalR (ANum n) n
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus: forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
(** As is often the case with relations, we'll find it
convenient to define infix notation for [aevalR]. We'll write [e
\\ n] to mean that arithmetic expression [e] evaluates to value
[n]. (This notation is one place where the limitation to ASCII
symbols becomes a little bothersome. The standard notation for
the evaluation relation is a double down-arrow. We'll typeset it
like this in the HTML version of the notes and use a double slash
as the closest approximation in [.v] files.) *)
Notation "e '\\' n"
:= (aevalR e n) (at level 50, left associativity)
: type_scope.
End aevalR_first_try.
(** In fact, Coq provides a way to use this notation in the definition
of [aevalR] itself. This avoids situations where we're working on
a proof involving statements in the form [e \\ n] but we have to
refer back to a definition written using the form [aevalR e n].
We do this by first "reserving" the notation, then giving the
definition together with a declaration of what the notation
means. *)
Reserved Notation "e '\\' n" (at level 50, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) \\ n
| E_APlus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 \\ n1) -> (e2 \\ n2) -> (APlus e1 e2) \\ (n1 + n2)
| E_AMinus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 \\ n1) -> (e2 \\ n2) -> (AMinus e1 e2) \\ (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 \\ n1) -> (e2 \\ n2) -> (AMult e1 e2) \\ (n1 * n2)
where "e '\\' n" := (aevalR e n) : type_scope.
(* ####################################################### *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient to write the rules for
[aevalR] and similar relations in the more readable graphical form
of _inference rules_, where the premises above the line justify
the conclusion below the line (we have already seen them in the
Prop chapter). *)
(** For example, the constructor [E_APlus]...
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 \\ n1
e2 \\ n2
-------------------- (E_APlus)
APlus e1 e2 \\ n1+n2
*)
(** Formally, there is nothing very deep about inference rules:
they are just implications. You can read the rule name on the
right as the name of the constructor and read each of the
linebreaks between the premises above the line and the line itself
as [->]. All the variables mentioned in the rule ([e1], [n1],
etc.) are implicitly bound by universal quantifiers at the
beginning. (Such variables are often called _metavariables_ to
distinguish them from the variables of the language we are
defining. At the moment, our arithmetic expressions don't include
variables, but we'll soon be adding them.) The whole collection
of rules is understood as being wrapped in an [Inductive]
declaration (informally, this is either elided or else indicated
by saying something like "Let [aevalR] be the smallest relation
closed under the following rules..."). *)
(** For example, [\\] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n \\ n
e1 \\ n1
e2 \\ n2
-------------------- (E_APlus)
APlus e1 e2 \\ n1+n2
e1 \\ n1
e2 \\ n2
--------------------- (E_AMinus)
AMinus e1 e2 \\ n1-n2
e1 \\ n1
e2 \\ n2
-------------------- (E_AMult)
AMult e1 e2 \\ n1*n2
*)
(* ####################################################### *)
(** ** Equivalence of the Definitions *)
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree on all possible arithmetic
expressions... *)
Theorem aeval_iff_aevalR : forall a n,
(a \\ n) <-> aeval a = n.
Proof.
split.
- (* -> *)
intros H.
induction H; simpl.
+ (* E_ANum *)
reflexivity.
+ (* E_APlus *)
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
+ (* E_AMinus *)
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
+ (* E_AMult *)
rewrite IHaevalR1. rewrite IHaevalR2. reflexivity.
- (* <- *)
generalize dependent n.
induction a;
simpl; intros; subst.
+ (* ANum *)
apply E_ANum.
+ (* APlus *)
apply E_APlus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
+ (* AMinus *)
apply E_AMinus.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
+ (* AMult *)
apply E_AMult.
apply IHa1. reflexivity.
apply IHa2. reflexivity.
Qed.
(** Note: if you're reading the HTML file, you'll see an empty square box instead
of a proof for this theorem.
You can click on this box to "unfold" the text to see the proof.
Click on the unfolded to text to "fold" it back up to a box. We'll be using
this style frequently from now on to help keep the HTML easier to read.
The full proofs always appear in the .v files. *)
(** We can make the proof quite a bit shorter by making more
use of tacticals... *)
Theorem aeval_iff_aevalR' : forall a n,
(a \\ n) <-> aeval a = n.
Proof.
(* WORKED IN CLASS *)
split.
- (* -> *)
intros H; induction H; subst; reflexivity.
- (* <- *)
generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars (bevalR) *)
(** Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval].*)
(*
Inductive bevalR:
* FILL IN HERE *
*)
(** [] *)
End AExp.
(* ####################################################### *)
(** ** Computational vs. Relational Definitions *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste. In general, Coq has
somewhat better support for working with relations. On the other
hand, in some sense function definitions carry more information,
because functions are necessarily deterministic and defined on all
arguments; for a relation we have to show these properties
explicitly if we need them. Functions also take advantage of Coq's
computations mechanism.
However, there are circumstances where relational definitions of
evaluation are preferable to functional ones. *)
Module aevalR_division.
(** For example, suppose that we wanted to extend the arithmetic
operations by considering also a division operation:*)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp
| ADiv : aexp -> aexp -> aexp. (* <--- new *)
(** Extending the definition of [aeval] to handle this new operation
would not be straightforward (what should we return as the result
of [ADiv (ANum 5) (ANum 0)]?). But extending [aevalR] is
straightforward. *)
Reserved Notation "e '\\' n" (at level 50, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) \\ n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 \\ n1) -> (a2 \\ n2) -> (APlus a1 a2) \\ (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 \\ n1) -> (a2 \\ n2) -> (AMinus a1 a2) \\ (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 \\ n1) -> (a2 \\ n2) -> (AMult a1 a2) \\ (n1 * n2)
| E_ADiv : forall (a1 a2: aexp) (n1 n2 n3: nat),
(a1 \\ n1) -> (a2 \\ n2) -> (n2 > 0) ->
(mult n2 n3 = n1) -> (ADiv a1 a2) \\ n3
where "a '\\' n" := (aevalR a n) : type_scope.
End aevalR_division.
Module aevalR_extended.
(** *** Adding nondeterminism *)
(** Suppose, instead, that we want to extend the arithmetic operations
by a nondeterministic number generator [any]:*)
Reserved Notation "e '\\' n" (at level 50, left associativity).
Inductive aexp : Type :=
| AAny : aexp (* <--- NEW *)
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
(** Again, extending [aeval] would be tricky (because evaluation is
_not_ a deterministic function from expressions to numbers), but
extending [aevalR] is no problem: *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_Any : forall (n:nat),
AAny \\ n (* <--- new *)
| E_ANum : forall (n:nat),
(ANum n) \\ n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 \\ n1) -> (a2 \\ n2) -> (APlus a1 a2) \\ (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 \\ n1) -> (a2 \\ n2) -> (AMinus a1 a2) \\ (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 \\ n1) -> (a2 \\ n2) -> (AMult a1 a2) \\ (n1 * n2)
where "a '\\' n" := (aevalR a n) : type_scope.
End aevalR_extended.
(* ####################################################### *)
(** * Expressions With Variables *)
(** Let's turn our attention back to defining Imp. The next thing we
need to do is to enrich our arithmetic and boolean expressions
with variables. To keep things simple, we'll assume that all
variables are global and that they only hold numbers. *)
(* ####################################################### *)
(** ** States *)
(** Since we'll want to look variables up to find out their current
values, we'll reuse the type [id] from the [Maps] chapter for the
type of variables in Imp.
A _machine state_ (or just _state_) represents the current values
of _all_ the variables at some point in the execution of a
program. *)
(** For simplicity, we assume that the state is defined for
_all_ variables, even though any given program is only going to
mention a finite number of them. The state captures all of the
information stored in memory. For Imp programs, because each
variable stores only a natural number, we can represent the state
as a mapping from identifiers to [nat]. For more complex
programming languages, the state might have more structure.
*)
Definition state := total_map nat.
Definition empty_state : state :=
t_empty 0.
(* ################################################### *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| AId : id -> aexp (* <----- NEW *)
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition X : id := Id 0.
Definition Y : id := Id 1.
Definition Z : id := Id 2.
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in this part of
the course, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is the same as before (using the new
[aexp]s): *)
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(* ################################################### *)
(** ** Evaluation *)
(** The arith and boolean evaluators can be extended to handle
variables in the obvious way: *)
Fixpoint aeval (st : state) (a : aexp) : nat :=
match a with
| ANum n => n
| AId x => st x (* <----- NEW *)
| APlus a1 a2 => (aeval st a1) + (aeval st a2)
| AMinus a1 a2 => (aeval st a1) - (aeval st a2)
| AMult a1 a2 => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => leb (aeval st a1) (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => andb (beval st b1) (beval st b2)
end.
Example aexp1 :
aeval (t_update empty_state X 5)
(APlus (ANum 3) (AMult (AId X) (ANum 2)))
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (t_update empty_state X 5)
(BAnd BTrue (BNot (BLe (AId X) (ANum 4))))
= true.
Proof. reflexivity. Qed.
(* ####################################################### *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (often called _statements_). *)
(* ################################################### *)
(** ** Syntax *)
(** Informally, commands [c] are described by the following BNF
grammar:
c ::= SKIP
| x ::= a
| c ;; c
| IFB b THEN c ELSE c FI
| WHILE b DO c END
*)
(**
For example, here's the factorial function in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
When this command terminates, the variable [Y] will contain the
factorial of the initial value of [X].
*)
(** Here is the formal definition of the syntax of commands: *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
(** As usual, we can use a few [Notation] declarations to make things
more readable. We need to be a bit careful to avoid conflicts
with Coq's built-in notations, so we'll keep this light -- in
particular, we won't introduce any notations for [aexps] and
[bexps] to avoid confusion with the numerical and boolean
operators we've already defined. We use the keyword [IFB] for
conditionals instead of [IF], for similar reasons. *)
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
Z ::= AId X;;
Y ::= ANum 1;;
WHILE BNot (BEq (AId Z) (ANum 0)) DO
Y ::= AMult (AId Y) (AId Z);;
Z ::= AMinus (AId Z) (ANum 1)
END.
(* ####################################################### *)
(** ** Examples *)
(** Assignment: *)
Definition plus2 : com :=
X ::= (APlus (AId X) (ANum 2)).
Definition XtimesYinZ : com :=
Z ::= (AMult (AId X) (AId Y)).
Definition subtract_slowly_body : com :=
Z ::= AMinus (AId Z) (ANum 1) ;;
X ::= AMinus (AId X) (ANum 1).
(** *** Loops *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
subtract_slowly_body
END.
Definition subtract_3_from_5_slowly : com :=
X ::= ANum 3 ;;
Z ::= ANum 5 ;;
subtract_slowly.
(** *** An infinite loop: *)
Definition loop : com :=
WHILE BTrue DO
SKIP
END.
(* ################################################################ *)
(** * Evaluation *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [WHILE] loops don't necessarily terminate makes defining
an evaluation function tricky... *)
(* #################################### *)
(** ** Evaluation as a Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [WHILE] case. *)
Fixpoint ceval_fun_no_while (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| x ::= a1 =>
t_update st x (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| WHILE b DO c END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the [WHILE] case as follows:
<<
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| WHILE b DO c END =>
if (beval st b)
then ceval_fun st (c; WHILE b DO c END)
else st
end.
>>
Coq doesn't accept such a definition ("Error: Cannot guess
decreasing argument of fix") because the function we want to
define is not guaranteed to terminate. Indeed, it doesn't always
terminate: for example, the full version of the [ceval_fun]
function applied to the [loop] program above would never
terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is
an (invalid!) Coq program showing what would go wrong if Coq
allowed non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become provable
(e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_fun] cannot be written in Coq -- at least not without
additional tricks (see chapter [ImpCEvalFun] if curious). *)
(* #################################### *)
(** ** Evaluation as a Relation *)
(** Here's a better way: we define [ceval] as a _relation_ rather than
a _function_ -- i.e., we define it in [Prop] instead of [Type], as
we did for [aevalR] above. *)
(** This is an important change. Besides freeing us from the awkward
workarounds that would be needed to define evaluation as a
function, it gives us a lot more flexibility in the definition.
For example, if we added concurrency features to the language,
we'd want the definition of evaluation to be non-deterministic --
i.e., not only would it not be total, it would not even be a
partial function! *)
(** We'll use the notation [c / st \\ st'] for our [ceval] relation:
[c / st \\ st'] means that executing program [c] in a starting
state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']".
*)
(** *** Operational Semantics
---------------- (E_Skip)
SKIP / st \\ st
aeval st a1 = n
-------------------------------- (E_Ass)
x := a1 / st \\ (t_update st x n)
c1 / st \\ st'
c2 / st' \\ st''
------------------- (E_Seq)
c1;;c2 / st \\ st''
beval st b1 = true
c1 / st \\ st'
------------------------------------- (E_IfTrue)
IF b1 THEN c1 ELSE c2 FI / st \\ st'
beval st b1 = false
c2 / st \\ st'
------------------------------------- (E_IfFalse)
IF b1 THEN c1 ELSE c2 FI / st \\ st'
beval st b = false
------------------------------ (E_WhileEnd)
WHILE b DO c END / st \\ st
beval st b = true
c / st \\ st'
WHILE b DO c END / st' \\ st''
--------------------------------- (E_WhileLoop)
WHILE b DO c END / st \\ st''
*)
(** Here is the formal definition. (Make sure you understand
how it corresponds to the inference rules.) *)
Reserved Notation "c1 '/' st '\\' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
SKIP / st \\ st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st \\ (t_update st x n)
| E_Seq : forall c1 c2 st st' st'',
c1 / st \\ st' ->
c2 / st' \\ st'' ->
(c1 ;; c2) / st \\ st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
c1 / st \\ st' ->
(IFB b THEN c1 ELSE c2 FI) / st \\ st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
c2 / st \\ st' ->
(IFB b THEN c1 ELSE c2 FI) / st \\ st'
| E_WhileEnd : forall b st c,
beval st b = false ->
(WHILE b DO c END) / st \\ st
| E_WhileLoop : forall st st' st'' b c,
beval st b = true ->
c / st \\ st' ->
(WHILE b DO c END) / st' \\ st'' ->
(WHILE b DO c END) / st \\ st''
where "c1 '/' st '\\' st'" := (ceval c1 st st').
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
\\ (t_update (t_update empty_state X 2) Z 4).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (t_update empty_state X 2).
- (* assignment command *)
apply E_Ass. reflexivity.
- (* if command *)
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity. Qed.
(** **** Exercise: 2 stars (ceval_example2) *)
Example ceval_example2:
(X ::= ANum 0;; Y ::= ANum 1;; Z ::= ANum 2) / empty_state \\
(t_update (t_update (t_update empty_state X 0) Y 1) Z 2).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y].
Prove that this program executes as intended for X = 2
(this latter part is trickier than you might expect). *)
Definition pup_to_n : com :=
(* FILL IN HERE *) admit.
Theorem pup_to_2_ceval :
pup_to_n / (t_update empty_state X 2) \\
t_update (t_update (t_update (t_update (t_update (t_update empty_state
X 2) Y 0) Y 2) X 1) Y 3) X 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it allows us to escape from the
artificial requirement (imposed by Coq's restrictions on
[Fixpoint] definitions) that evaluation should be a total
function. But it also raises a question: Is the second definition
of evaluation actually a partial function? That is, is it
possible that, beginning from the same state [st], we could
evaluate some command [c] in different ways to reach two different
output states [st'] and [st'']?
In fact, this cannot happen: [ceval] is a partial function.
Here's the proof: *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st \\ st1 ->
c / st \\ st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
induction E1;
intros st2 E2; inversion E2; subst.
- (* E_Skip *) reflexivity.
- (* E_Ass *) reflexivity.
- (* E_Seq *)
assert (st' = st'0) as EQ1.
{ (* Proof of assertion *) apply IHE1_1; assumption. }
subst st'0.
apply IHE1_2. assumption.
- (* E_IfTrue, b1 evaluates to true *)
apply IHE1. assumption.
- (* E_IfTrue, b1 evaluates to false (contradiction) *)
rewrite H in H5. inversion H5.
- (* E_IfFalse, b1 evaluates to true (contradiction) *)
rewrite H in H5. inversion H5.
- (* E_IfFalse, b1 evaluates to false *)
apply IHE1. assumption.
- (* E_WhileEnd, b1 evaluates to false *)
reflexivity.
- (* E_WhileEnd, b1 evaluates to true (contradiction) *)
rewrite H in H2. inversion H2.
- (* E_WhileLoop, b1 evaluates to false (contradiction) *)
rewrite H in H4. inversion H4.
- (* E_WhileLoop, b1 evaluates to true *)
assert (st' = st'0) as EQ1.
{ (* Proof of assertion *) apply IHE1_1; assumption. }
subst st'0.
apply IHE1_2. assumption. Qed.
(* ####################################################### *)
(** * Reasoning About Imp Programs *)
(** We'll get much deeper into systematic techniques for reasoning
about Imp programs in the following chapters, but we can do quite
a bit just working with the bare definitions. *)
(* This section explores some examples. *)
Theorem plus2_spec : forall st n st',
st X = n ->
plus2 / st \\ st' ->
st' X = n + 2.
Proof.
intros st n st' HX Heval.
(* Inverting Heval essentially forces Coq to expand one
step of the ceval computation - in this case revealing
that st' must be st extended with the new value of X,
since plus2 is an assignment *)
inversion Heval. subst. clear Heval. simpl.
apply t_update_eq. Qed.
(** **** Exercise: 3 stars, recommended (XtimesYinZ_spec) *)
(** State and prove a specification of [XtimesYinZ]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, recommended (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(loop / st \\ st').
Proof.
intros st st' contra. unfold loop in contra.
remember (WHILE BTrue DO SKIP END) as loopdef eqn:Heqloopdef.
(* Proceed by induction on the assumed derivation showing that
[loopdef] terminates. Most of the cases are immediately
contradictory (and so can be solved in one step with
[inversion]). *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (no_whilesR) *)
(** Consider the definition of the [no_whiles] boolean predicate below: *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| SKIP => true
| _ ::= _ => true
| c1 ;; c2 => andb (no_whiles c1) (no_whiles c2)
| IFB _ THEN ct ELSE cf FI => andb (no_whiles ct) (no_whiles cf)
| WHILE _ DO _ END => false
end.
(** This predicate yields [true] just on programs that
have no while loops. Using [Inductive], write a property
[no_whilesR] such that [no_whilesR c] is provable exactly when [c]
is a program with no while loops. Then prove its equivalence
with [no_whiles]. *)
Inductive no_whilesR: com -> Prop :=
(* FILL IN HERE *)
.
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (no_whiles_terminating) *)
(** Imp programs that don't involve while loops always terminate.
State and prove a theorem [no_whiles_terminating] that says this. *)
(** (Use either [no_whiles] or [no_whilesR], as you prefer.) *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (stack_compiler) *)
(** HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a stack. For instance, the expression
<<
(2*3)+(3*(4-2))
>>
would be entered as
<<
2 3 * 3 4 2 - * +
>>
and evaluated like this:
<<
[] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
>>
The task of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad x]: Load the identifier [x] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract.
- [SMult]: Similar, but multiply. *)
Inductive sinstr : Type :=
| SPush : nat -> sinstr
| SLoad : id -> sinstr
| SPlus : sinstr
| SMinus : sinstr
| SMult : sinstr.
(** Write a function to evaluate programs in the stack language. It
takes as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and returns the stack after
executing the program. Test your function on the examples below.
Note that the specification leaves unspecified what to do when
encountering an [SPlus], [SMinus], or [SMult] instruction if the
stack contains less than two elements. In a sense, it is
immaterial what we do, since our compiler will never emit such a
malformed program. *)
Fixpoint s_execute (st : state) (stack : list nat)
(prog : list sinstr)
: list nat :=
(* FILL IN HERE *) admit.
Example s_execute1 :
s_execute empty_state []
[SPush 5; SPush 3; SPush 1; SMinus]
= [2; 5].
(* FILL IN HERE *) Admitted.
Example s_execute2 :
s_execute (t_update empty_state X 3) [3;4]
[SPush 4; SLoad X; SMult; SPlus]
= [15; 4].
(* FILL IN HERE *) Admitted.
(** Next, write a function which compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr :=
(* FILL IN HERE *) admit.
(** After you've defined [s_compile], prove the following to test
that it works. *)
Example s_compile1 :
s_compile (AMinus (AId X) (AMult (ANum 2) (AId Y)))
= [SLoad X; SPush 2; SLoad Y; SMult; SMinus].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (stack_compiler_correct) *)
(** The task of this exercise is to prove the correctness of the
compiler implemented in the previous exercise. Remember that
the specification left unspecified what to do when encountering an
[SPlus], [SMinus], or [SMult] instruction if the stack contains
less than two elements. (In order to make your correctness proof
easier you may find it useful to go back and change your
implementation!)
Prove the following theorem, stating that the [compile] function
behaves correctly. You will need to start by stating a more
general lemma to get a usable induction hypothesis; the main
theorem will then be a simple corollary of this lemma. *)
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st [] (s_compile e) = [ aeval st e ].
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 5 stars, advanced (break_imp) *)
Module BreakImp.
(** Imperative languages such as C or Java often have a [break] or
similar statement for interrupting the execution of loops. In this
exercise we will consider how to add [break] to Imp.
First, we need to enrich the language of commands with an
additional case. *)
Inductive com : Type :=
| CSkip : com
| CBreak : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Notation "'SKIP'" :=
CSkip.
Notation "'BREAK'" :=
CBreak.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** Next, we need to define the behavior of [BREAK]. Informally,
whenever [BREAK] is executed in a sequence of commands, it stops
the execution of that sequence and signals that the innermost
enclosing loop (if any) should terminate. If there aren't any
enclosing loops, then the whole program simply terminates. The
final state should be the same as the one in which the [BREAK]
statement was executed.
One important point is what to do when there are multiple loops
enclosing a given [BREAK]. In those cases, [BREAK] should only
terminate the _innermost_ loop where it occurs. Thus, after
executing the following piece of code...
X ::= 0;;
Y ::= 1;;
WHILE 0 <> Y DO
WHILE TRUE DO
BREAK
END;;
X ::= 1;;
Y ::= Y - 1
END
... the value of [X] should be [1], and not [0].
One way of expressing this behavior is to add another parameter to
the evaluation relation that specifies whether evaluation of a
command executes a [BREAK] statement: *)
Inductive status : Type :=
| SContinue : status
| SBreak : status.
Reserved Notation "c1 '/' st '\\' s '/' st'"
(at level 40, st, s at level 39).
(** Intuitively, [c / st \\ s / st'] means that, if [c] is started in
state [st], then it terminates in state [st'] and either signals
that any surrounding loop (or the whole program) should exit
immediately ([s = SBreak]) or that execution should continue
normally ([s = SContinue]).
The definition of the "[c / st \\ s / st']" relation is very
similar to the one we gave above for the regular evaluation
relation ([c / st \\ st']) -- we just need to handle the
termination signals appropriately:
- If the command is [SKIP], then the state doesn't change, and
execution of any enclosing loop can continue normally.
- If the command is [BREAK], the state stays unchanged, but we
signal a [SBreak].
- If the command is an assignment, then we update the binding for
that variable in the state accordingly and signal that execution
can continue normally.
- If the command is of the form [IF b THEN c1 ELSE c2 FI], then
the state is updated as in the original semantics of Imp, except
that we also propagate the signal from the execution of
whichever branch was taken.
- If the command is a sequence [c1 ; c2], we first execute
[c1]. If this yields a [SBreak], we skip the execution of [c2]
and propagate the [SBreak] signal to the surrounding context;
the resulting state should be the same as the one obtained by
executing [c1] alone. Otherwise, we execute [c2] on the state
obtained after executing [c1], and propagate the signal that was
generated there.
- Finally, for a loop of the form [WHILE b DO c END], the
semantics is almost the same as before. The only difference is
that, when [b] evaluates to true, we execute [c] and check the
signal that it raises. If that signal is [SContinue], then the
execution proceeds as in the original semantics. Otherwise, we
stop the execution of the loop, and the resulting state is the
same as the one resulting from the execution of the current
iteration. In either case, since [BREAK] only terminates the
innermost loop, [WHILE] signals [SContinue]. *)
(** Based on the above description, complete the definition of the
[ceval] relation. *)
Inductive ceval : com -> state -> status -> state -> Prop :=
| E_Skip : forall st,
CSkip / st \\ SContinue / st
(* FILL IN HERE *)
where "c1 '/' st '\\' s '/' st'" := (ceval c1 st s st').
(** Now the following properties of your definition of [ceval]: *)
Theorem break_ignore : forall c st st' s,
(BREAK;; c) / st \\ s / st' ->
st = st'.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_continue : forall b c st st' s,
(WHILE b DO c END) / st \\ s / st' ->
s = SContinue.
Proof.
(* FILL IN HERE *) Admitted.
Theorem while_stops_on_break : forall b c st st',
beval st b = true ->
c / st \\ SBreak / st' ->
(WHILE b DO c END) / st \\ SContinue / st'.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 3 stars, advanced, optional (while_break_true) *)
Theorem while_break_true : forall b c st st',
(WHILE b DO c END) / st \\ SContinue / st' ->
beval st' b = true ->
exists st'', c / st'' \\ SBreak / st'.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 4 stars, advanced, optional (ceval_deterministic) *)
Theorem ceval_deterministic: forall (c:com) st st1 st2 s1 s2,
c / st \\ s1 / st1 ->
c / st \\ s2 / st2 ->
st1 = st2 /\ s1 = s2.
Proof.
(* FILL IN HERE *) Admitted.
End BreakImp.
(** [] *)
(** **** Exercise: 3 stars, optional (short_circuit) *)
(** Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, optional (add_for_loop) *)
(** Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this file
are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(* FILL IN HERE *)
(** [] *)
(* <$Date: 2016-02-05 09:55:10 -0500 (Fri, 05 Feb 2016) $ *)
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define IVERILOG_SIM
`define TEST_PROG "prog_sub.list"
`include "top.v"
module top_test_sub;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = (1 << WIDTH) - 1;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] expected_output = OUTPUT_CNT-1;
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t(
.clk(clk),
.uart_tx_line(uart_tx));
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (expected_output == 0) begin
$display("Subtract test passed!\n");
$finish;
end
if (serial_data != expected_output) begin
$display("Subtract test failed!\n");
$display("Serial output:%d doesn't match expected_output:%d\n",
serial_data, expected_output);
$finish;
end
expected_output <= expected_output - 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111OI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A2111OI_FUNCTIONAL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a2111oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
// Local signals
wire C1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111OI_FUNCTIONAL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_gtp_pipe_rate.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : gtp_pipe_rate.v
// Description : PIPE Rate Module for 7 Series Transceiver
// Version : 19.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Rate Module --------------------------------------------------
module PCIEBus_gtp_pipe_rate #
(
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim mode
parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max
)
(
//---------- Input -------------------------------------
input RATE_CLK,
input RATE_RST_N,
input [ 1:0] RATE_RATE_IN,
input RATE_DRP_DONE,
input RATE_RXPMARESETDONE,
input RATE_TXRATEDONE,
input RATE_RXRATEDONE,
input RATE_TXSYNC_DONE,
input RATE_PHYSTATUS,
//---------- Output ------------------------------------
output RATE_PCLK_SEL,
output RATE_DRP_START,
output RATE_DRP_X16,
output [ 2:0] RATE_RATE_OUT,
output RATE_TXSYNC_START,
output RATE_DONE,
output RATE_IDLE,
output [ 4:0] RATE_FSM
);
//---------- Input FF or Buffer ------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2;
//---------- Internal Signals --------------------------
wire [ 2:0] rate;
reg [ 3:0] txdata_wait_cnt = 4'd0;
reg txratedone = 1'd0;
reg rxratedone = 1'd0;
reg phystatus = 1'd0;
reg ratedone = 1'd0;
//---------- Output FF or Buffer -----------------------
reg pclk_sel = 1'd0;
reg [ 2:0] rate_out = 3'd0;
reg [ 3:0] fsm = 0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 0;
localparam FSM_TXDATA_WAIT = 1;
localparam FSM_PCLK_SEL = 2;
localparam FSM_DRP_X16_START = 3;
localparam FSM_DRP_X16_DONE = 4;
localparam FSM_RATE_SEL = 5;
localparam FSM_RXPMARESETDONE = 6;
localparam FSM_DRP_X20_START = 7;
localparam FSM_DRP_X20_DONE = 8;
localparam FSM_RATE_DONE = 9;
localparam FSM_TXSYNC_START = 10;
localparam FSM_TXSYNC_DONE = 11;
localparam FSM_DONE = 12; // Must sync value to pipe_user.v
//---------- Input FF ----------------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
//---------- 1st Stage FF --------------------------
rate_in_reg1 <= 2'd0;
drp_done_reg1 <= 1'd0;
rxpmaresetdone_reg1 <= 1'd0;
txratedone_reg1 <= 1'd0;
rxratedone_reg1 <= 1'd0;
phystatus_reg1 <= 1'd0;
txsync_done_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
rate_in_reg2 <= 2'd0;
drp_done_reg2 <= 1'd0;
rxpmaresetdone_reg2 <= 1'd0;
txratedone_reg2 <= 1'd0;
rxratedone_reg2 <= 1'd0;
phystatus_reg2 <= 1'd0;
txsync_done_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
rate_in_reg1 <= RATE_RATE_IN;
drp_done_reg1 <= RATE_DRP_DONE;
rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE;
txratedone_reg1 <= RATE_TXRATEDONE;
rxratedone_reg1 <= RATE_RXRATEDONE;
phystatus_reg1 <= RATE_PHYSTATUS;
txsync_done_reg1 <= RATE_TXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
rate_in_reg2 <= rate_in_reg1;
drp_done_reg2 <= drp_done_reg1;
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
txratedone_reg2 <= txratedone_reg1;
rxratedone_reg2 <= rxratedone_reg1;
phystatus_reg2 <= phystatus_reg1;
txsync_done_reg2 <= txsync_done_reg1;
end
end
//---------- Select Rate -------------------------------------------------------
// Gen1 : div 2 using [TX/RX]OUT_DIV = 2
// Gen2 : div 1 using [TX/RX]RATE = 3'd1
//------------------------------------------------------------------------------
assign rate = (rate_in_reg2 == 2'd1) ? 3'd1 : 3'd0;
//---------- TXDATA Wait Counter -----------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
txdata_wait_cnt <= 4'd0;
else
//---------- Increment Wait Counter ----------------
if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt + 4'd1;
//---------- Hold Wait Counter ---------------------
else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt;
//---------- Reset Wait Counter --------------------
else
txdata_wait_cnt <= 4'd0;
end
//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS -----------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
else
begin
if ((fsm == FSM_RATE_DONE) || (fsm == FSM_RXPMARESETDONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE))
begin
//---------- Latch TXRATEDONE ------------------
if (txratedone_reg2)
txratedone <= 1'd1;
else
txratedone <= txratedone;
//---------- Latch RXRATEDONE ------------------
if (rxratedone_reg2)
rxratedone <= 1'd1;
else
rxratedone <= rxratedone;
//---------- Latch PHYSTATUS -------------------
if (phystatus_reg2)
phystatus <= 1'd1;
else
phystatus <= phystatus;
//---------- Latch Rate Done -------------------
if (rxratedone && txratedone && phystatus)
ratedone <= 1'd1;
else
ratedone <= ratedone;
end
else
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
end
end
//---------- PIPE Rate FSM -----------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
fsm <= FSM_IDLE;
pclk_sel <= 1'd0;
rate_out <= 3'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Detect Rate Change ----------------
if (rate_in_reg2 != rate_in_reg1)
begin
fsm <= FSM_TXDATA_WAIT;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
else
begin
fsm <= FSM_IDLE;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
end
//---------- Wait for TXDATA to TX[P/N] Latency ----
FSM_TXDATA_WAIT :
begin
fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Select PCLK Frequency -----------------
// Gen1 : PCLK = 125 MHz
// Gen2 : PCLK = 250 MHz
//--------------------------------------------------
FSM_PCLK_SEL :
begin
fsm <= (PCIE_SIM_SPEEDUP == "TRUE") ? FSM_RATE_SEL : FSM_DRP_X16_START;
pclk_sel <= (rate_in_reg2 == 2'd1);
rate_out <= rate_out;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Select Rate ---------------------------
FSM_RATE_SEL :
begin
fsm <= (PCIE_SIM_SPEEDUP == "TRUE") ? FSM_RATE_DONE : FSM_RXPMARESETDONE;
pclk_sel <= pclk_sel;
rate_out <= rate; // Update [TX/RX]RATE
end
//---------- Wait for RXPMARESETDONE De-assertion --
FSM_RXPMARESETDONE :
begin
fsm <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Start DRP x20 -------------------------
FSM_DRP_X20_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Wait for DRP x20 Done -----------------
FSM_DRP_X20_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Wait for Rate Change Done -------------
FSM_RATE_DONE :
begin
if (ratedone)
fsm <= FSM_TXSYNC_START;
else
fsm <= FSM_RATE_DONE;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START:
begin
fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE:
begin
fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE);
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Rate Change Done ----------------------
FSM_DONE :
begin
fsm <= FSM_IDLE;
pclk_sel <= pclk_sel;
rate_out <= rate_out;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
pclk_sel <= 1'd0;
rate_out <= 3'd0;
end
endcase
end
end
//---------- PIPE Rate Output --------------------------------------------------
assign RATE_PCLK_SEL = pclk_sel;
assign RATE_DRP_START = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
assign RATE_DRP_X16 = (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
assign RATE_RATE_OUT = rate_out;
assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RATE_DONE = (fsm == FSM_DONE);
assign RATE_IDLE = (fsm == FSM_IDLE);
assign RATE_FSM = {1'd0, fsm};
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: board.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`timescale 1 ns/10 ps
`uselib lib=unisims_ver
module board
(
sys_clk_pin,
sys_rst_pin
);
input sys_clk_pin;
input sys_rst_pin;
// Internal Signals
wire fpga_0_RS232_Uart_1_RX_pin;
wire fpga_0_RS232_Uart_1_TX_pin;
wire [1:0] fpga_0_DDR2_SDRAM_DDR2_ODT_pin;
wire [12:0] fpga_0_DDR2_SDRAM_DDR2_Addr_pin;
wire [1:0] fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin;
wire fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin;
wire [1:0] fpga_0_DDR2_SDRAM_DDR2_CE_pin;
wire [1:0] fpga_0_DDR2_SDRAM_DDR2_CS_n_pin;
wire fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin;
wire fpga_0_DDR2_SDRAM_DDR2_WE_n_pin;
wire [1:0] fpga_0_DDR2_SDRAM_DDR2_Clk_pin;
wire [1:0] fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin;
wire [7:0] fpga_0_DDR2_SDRAM_DDR2_DM_pin;
wire [7:0] fpga_0_DDR2_SDRAM_DDR2_DQS;
wire [7:0] fpga_0_DDR2_SDRAM_DDR2_DQS_n;
wire [63:0] fpga_0_DDR2_SDRAM_DDR2_DQ;
`ifdef ETHERNET_LITE
wire fpga_0_Ethernet_MAC_PHY_rst_n_pin;
wire fpga_0_Ethernet_MAC_PHY_crs_pin;
wire fpga_0_Ethernet_MAC_PHY_col_pin;
wire [3:0] fpga_0_Ethernet_MAC_PHY_tx_data_pin;
wire fpga_0_Ethernet_MAC_PHY_tx_en_pin;
wire fpga_0_Ethernet_MAC_PHY_tx_clk_pin;
wire fpga_0_Ethernet_MAC_PHY_rx_er_pin;
wire fpga_0_Ethernet_MAC_PHY_rx_clk_pin;
wire fpga_0_Ethernet_MAC_PHY_dv_pin;
wire [3:0] fpga_0_Ethernet_MAC_PHY_rx_data_pin;
`else
wire fpga_0_Hard_Ethernet_MAC_PHY_MII_INT;
wire fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin;
wire fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin;
wire fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin;
wire fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin;
wire fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin;
wire fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin;
wire fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin;
wire fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin;
wire fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin;
wire fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin;
wire fpga_0_Hard_Ethernet_MAC_MDC_0_pin;
wire fpga_0_Hard_Ethernet_MAC_MDIO_0_pin;
`endif
wire [9:0] noconnect10;
wire noconnect;
system
system_0
(
.fpga_0_RS232_Uart_1_RX_pin(fpga_0_RS232_Uart_1_RX_pin),
.fpga_0_RS232_Uart_1_TX_pin(fpga_0_RS232_Uart_1_TX_pin),
.fpga_0_DDR2_SDRAM_DDR2_ODT_pin(fpga_0_DDR2_SDRAM_DDR2_ODT_pin),
.fpga_0_DDR2_SDRAM_DDR2_Addr_pin(fpga_0_DDR2_SDRAM_DDR2_Addr_pin),
.fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin(fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin),
.fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin(fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin),
.fpga_0_DDR2_SDRAM_DDR2_CE_pin(fpga_0_DDR2_SDRAM_DDR2_CE_pin),
.fpga_0_DDR2_SDRAM_DDR2_CS_n_pin(fpga_0_DDR2_SDRAM_DDR2_CS_n_pin),
.fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin(fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin),
.fpga_0_DDR2_SDRAM_DDR2_WE_n_pin(fpga_0_DDR2_SDRAM_DDR2_WE_n_pin),
.fpga_0_DDR2_SDRAM_DDR2_Clk_pin(fpga_0_DDR2_SDRAM_DDR2_Clk_pin),
.fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin(fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin),
.fpga_0_DDR2_SDRAM_DDR2_DM_pin(fpga_0_DDR2_SDRAM_DDR2_DM_pin),
.fpga_0_DDR2_SDRAM_DDR2_DQS(fpga_0_DDR2_SDRAM_DDR2_DQS),
.fpga_0_DDR2_SDRAM_DDR2_DQS_n(fpga_0_DDR2_SDRAM_DDR2_DQS_n),
.fpga_0_DDR2_SDRAM_DDR2_DQ(fpga_0_DDR2_SDRAM_DDR2_DQ),
`ifdef ETHERNET_LITE
.fpga_0_Hard_Ethernet_MAC_PHY_MII_INT(fpga_0_Hard_Ethernet_MAC_PHY_MII_INT),
.fpga_0_Ethernet_MAC_PHY_rst_n_pin(fpga_0_Ethernet_MAC_PHY_rst_n_pin),
.fpga_0_Ethernet_MAC_PHY_crs_pin(fpga_0_Ethernet_MAC_PHY_crs_pin),
.fpga_0_Ethernet_MAC_PHY_col_pin(fpga_0_Ethernet_MAC_PHY_col_pin),
.fpga_0_Ethernet_MAC_PHY_tx_data_pin(fpga_0_Ethernet_MAC_PHY_tx_data_pin),
.fpga_0_Ethernet_MAC_PHY_tx_en_pin(fpga_0_Ethernet_MAC_PHY_tx_en_pin),
.fpga_0_Ethernet_MAC_PHY_tx_clk_pin(fpga_0_Ethernet_MAC_PHY_tx_clk_pin),
.fpga_0_Ethernet_MAC_PHY_rx_er_pin(fpga_0_Ethernet_MAC_PHY_rx_er_pin),
.fpga_0_Ethernet_MAC_PHY_rx_clk_pin(fpga_0_Ethernet_MAC_PHY_rx_clk_pin),
.fpga_0_Ethernet_MAC_PHY_dv_pin(fpga_0_Ethernet_MAC_PHY_dv_pin),
.fpga_0_Ethernet_MAC_PHY_rx_data_pin(fpga_0_Ethernet_MAC_PHY_rx_data_pin),
`else
.fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin(fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin),
.fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin(fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin),
.fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin(fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin),
.fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin(fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin),
.fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin(fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin),
.fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin(fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin),
.fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin(fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin),
.fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin(fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin),
.fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin(fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin),
.fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin(fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin),
.fpga_0_Hard_Ethernet_MAC_MDC_0_pin(fpga_0_Hard_Ethernet_MAC_MDC_0_pin),
.fpga_0_Hard_Ethernet_MAC_MDIO_0_pin(fpga_0_Hard_Ethernet_MAC_MDIO_0_pin),
`endif
.sys_clk_pin(sys_clk_pin),
.sys_rst_pin(sys_rst_pin)
);
// Micron DDR model version 5.5 now supports SODIMM modules
// Be sure to compile file ddr2_module.v with +define+SODIMM
ddr2_module ddr2_module
(
.ck (fpga_0_DDR2_SDRAM_DDR2_Clk_pin),
.ck_n (fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin),
.cke (fpga_0_DDR2_SDRAM_DDR2_CE_pin),
.s_n (fpga_0_DDR2_SDRAM_DDR2_CS_n_pin),
.ras_n (fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin),
.cas_n (fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin),
.we_n (fpga_0_DDR2_SDRAM_DDR2_WE_n_pin),
.ba ({1'b0,fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin}),
.addr (fpga_0_DDR2_SDRAM_DDR2_Addr_pin),
.odt (fpga_0_DDR2_SDRAM_DDR2_ODT_pin),
.dqs ({noconnect,fpga_0_DDR2_SDRAM_DDR2_DM_pin,noconnect,fpga_0_DDR2_SDRAM_DDR2_DQS}),
.dqs_n ({noconnect10,fpga_0_DDR2_SDRAM_DDR2_DQS_n}),
.dq (fpga_0_DDR2_SDRAM_DDR2_DQ),
.scl (1'b1),
.sa (),
.sda ()
);
/*
ddr
#("bin0.dat")
ddr_0 (
.Dq ( DDR_DQ[0:15] ),
.Dqs ( DDR_DQS[0:1] ),
.Addr ( DDR_Addr ),
.Ba ( DDR_BankAddr ),
.Clk ( DDR_Clk ),
.Clk_n ( DDR_Clkn ),
.Cke ( DDR_CKE ),
.Cs_n ( DDR_CSn ),
.Ras_n ( DDR_RASn ),
.Cas_n ( DDR_CASn ),
.We_n ( DDR_WEn ),
.Dm ( DDR_DM[0:1] )
);
ddr
#("bin1.dat")
ddr_1 (
.Dq ( DDR_DQ[16:31] ),
.Dqs ( DDR_DQS[2:3] ),
.Addr ( DDR_Addr ),
.Ba ( DDR_BankAddr ),
.Clk ( DDR_Clk ),
.Clk_n ( DDR_Clkn ),
.Cke ( DDR_CKE ),
.Cs_n ( DDR_CSn ),
.Ras_n ( DDR_RASn ),
.Cas_n ( DDR_CASn ),
.We_n ( DDR_WEn ),
.Dm ( DDR_DM[2:3] )
);
//init_mems init_mems_0 ();
*/
pcx_monitor pcx_mon_0 (
.rclk(system_0.gclk),
.spc_pcx_req_pq(system_0.ccx2mb_0_spc_pcx_req_pq),
.spc_pcx_data_pa(system_0.ccx2mb_0_spc_pcx_data_pa)
);
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:hls:pixelq_op:1.0
// IP Revision: 1504242149
(* X_CORE_INFO = "pixelq_op_top,Vivado 2014.4.1" *)
(* CHECK_LICENSE_TYPE = "tutorial_pixelq_op_0_0,pixelq_op_top,{}" *)
(* CORE_GENERATION_INFO = "tutorial_pixelq_op_0_0,pixelq_op_top,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=hls,x_ipName=pixelq_op,x_ipVersion=1.0,x_ipCoreRevision=1504242149,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_CONTROL_BUS_ADDR_WIDTH=5,C_S_AXI_CONTROL_BUS_DATA_WIDTH=32}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module tutorial_pixelq_op_0_0 (
s_axi_CONTROL_BUS_AWADDR,
s_axi_CONTROL_BUS_AWVALID,
s_axi_CONTROL_BUS_AWREADY,
s_axi_CONTROL_BUS_WDATA,
s_axi_CONTROL_BUS_WSTRB,
s_axi_CONTROL_BUS_WVALID,
s_axi_CONTROL_BUS_WREADY,
s_axi_CONTROL_BUS_BRESP,
s_axi_CONTROL_BUS_BVALID,
s_axi_CONTROL_BUS_BREADY,
s_axi_CONTROL_BUS_ARADDR,
s_axi_CONTROL_BUS_ARVALID,
s_axi_CONTROL_BUS_ARREADY,
s_axi_CONTROL_BUS_RDATA,
s_axi_CONTROL_BUS_RRESP,
s_axi_CONTROL_BUS_RVALID,
s_axi_CONTROL_BUS_RREADY,
interrupt,
INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY,
INPUT_STREAM_TDATA,
INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB,
INPUT_STREAM_TUSER,
INPUT_STREAM_TLAST,
INPUT_STREAM_TID,
INPUT_STREAM_TDEST,
OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY,
OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID,
OUTPUT_STREAM_TDEST,
aclk,
aresetn
);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS AWADDR" *)
input wire [4 : 0] s_axi_CONTROL_BUS_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS AWVALID" *)
input wire s_axi_CONTROL_BUS_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS AWREADY" *)
output wire s_axi_CONTROL_BUS_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS WDATA" *)
input wire [31 : 0] s_axi_CONTROL_BUS_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS WSTRB" *)
input wire [3 : 0] s_axi_CONTROL_BUS_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS WVALID" *)
input wire s_axi_CONTROL_BUS_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS WREADY" *)
output wire s_axi_CONTROL_BUS_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS BRESP" *)
output wire [1 : 0] s_axi_CONTROL_BUS_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS BVALID" *)
output wire s_axi_CONTROL_BUS_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS BREADY" *)
input wire s_axi_CONTROL_BUS_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS ARADDR" *)
input wire [4 : 0] s_axi_CONTROL_BUS_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS ARVALID" *)
input wire s_axi_CONTROL_BUS_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS ARREADY" *)
output wire s_axi_CONTROL_BUS_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS RDATA" *)
output wire [31 : 0] s_axi_CONTROL_BUS_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS RRESP" *)
output wire [1 : 0] s_axi_CONTROL_BUS_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS RVALID" *)
output wire s_axi_CONTROL_BUS_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_CONTROL_BUS RREADY" *)
input wire s_axi_CONTROL_BUS_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *)
output wire interrupt;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TVALID" *)
input wire INPUT_STREAM_TVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TREADY" *)
output wire INPUT_STREAM_TREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TDATA" *)
input wire [23 : 0] INPUT_STREAM_TDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TKEEP" *)
input wire [2 : 0] INPUT_STREAM_TKEEP;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TSTRB" *)
input wire [2 : 0] INPUT_STREAM_TSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TUSER" *)
input wire [0 : 0] INPUT_STREAM_TUSER;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TLAST" *)
input wire [0 : 0] INPUT_STREAM_TLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TID" *)
input wire [0 : 0] INPUT_STREAM_TID;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TDEST" *)
input wire [0 : 0] INPUT_STREAM_TDEST;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TVALID" *)
output wire OUTPUT_STREAM_TVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TREADY" *)
input wire OUTPUT_STREAM_TREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TDATA" *)
output wire [23 : 0] OUTPUT_STREAM_TDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TKEEP" *)
output wire [2 : 0] OUTPUT_STREAM_TKEEP;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TSTRB" *)
output wire [2 : 0] OUTPUT_STREAM_TSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TUSER" *)
output wire [0 : 0] OUTPUT_STREAM_TUSER;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TLAST" *)
output wire [0 : 0] OUTPUT_STREAM_TLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TID" *)
output wire [0 : 0] OUTPUT_STREAM_TID;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TDEST" *)
output wire [0 : 0] OUTPUT_STREAM_TDEST;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
input wire aresetn;
pixelq_op_top #(
.C_S_AXI_CONTROL_BUS_ADDR_WIDTH(5),
.C_S_AXI_CONTROL_BUS_DATA_WIDTH(32)
) inst (
.s_axi_CONTROL_BUS_AWADDR(s_axi_CONTROL_BUS_AWADDR),
.s_axi_CONTROL_BUS_AWVALID(s_axi_CONTROL_BUS_AWVALID),
.s_axi_CONTROL_BUS_AWREADY(s_axi_CONTROL_BUS_AWREADY),
.s_axi_CONTROL_BUS_WDATA(s_axi_CONTROL_BUS_WDATA),
.s_axi_CONTROL_BUS_WSTRB(s_axi_CONTROL_BUS_WSTRB),
.s_axi_CONTROL_BUS_WVALID(s_axi_CONTROL_BUS_WVALID),
.s_axi_CONTROL_BUS_WREADY(s_axi_CONTROL_BUS_WREADY),
.s_axi_CONTROL_BUS_BRESP(s_axi_CONTROL_BUS_BRESP),
.s_axi_CONTROL_BUS_BVALID(s_axi_CONTROL_BUS_BVALID),
.s_axi_CONTROL_BUS_BREADY(s_axi_CONTROL_BUS_BREADY),
.s_axi_CONTROL_BUS_ARADDR(s_axi_CONTROL_BUS_ARADDR),
.s_axi_CONTROL_BUS_ARVALID(s_axi_CONTROL_BUS_ARVALID),
.s_axi_CONTROL_BUS_ARREADY(s_axi_CONTROL_BUS_ARREADY),
.s_axi_CONTROL_BUS_RDATA(s_axi_CONTROL_BUS_RDATA),
.s_axi_CONTROL_BUS_RRESP(s_axi_CONTROL_BUS_RRESP),
.s_axi_CONTROL_BUS_RVALID(s_axi_CONTROL_BUS_RVALID),
.s_axi_CONTROL_BUS_RREADY(s_axi_CONTROL_BUS_RREADY),
.interrupt(interrupt),
.INPUT_STREAM_TVALID(INPUT_STREAM_TVALID),
.INPUT_STREAM_TREADY(INPUT_STREAM_TREADY),
.INPUT_STREAM_TDATA(INPUT_STREAM_TDATA),
.INPUT_STREAM_TKEEP(INPUT_STREAM_TKEEP),
.INPUT_STREAM_TSTRB(INPUT_STREAM_TSTRB),
.INPUT_STREAM_TUSER(INPUT_STREAM_TUSER),
.INPUT_STREAM_TLAST(INPUT_STREAM_TLAST),
.INPUT_STREAM_TID(INPUT_STREAM_TID),
.INPUT_STREAM_TDEST(INPUT_STREAM_TDEST),
.OUTPUT_STREAM_TVALID(OUTPUT_STREAM_TVALID),
.OUTPUT_STREAM_TREADY(OUTPUT_STREAM_TREADY),
.OUTPUT_STREAM_TDATA(OUTPUT_STREAM_TDATA),
.OUTPUT_STREAM_TKEEP(OUTPUT_STREAM_TKEEP),
.OUTPUT_STREAM_TSTRB(OUTPUT_STREAM_TSTRB),
.OUTPUT_STREAM_TUSER(OUTPUT_STREAM_TUSER),
.OUTPUT_STREAM_TLAST(OUTPUT_STREAM_TLAST),
.OUTPUT_STREAM_TID(OUTPUT_STREAM_TID),
.OUTPUT_STREAM_TDEST(OUTPUT_STREAM_TDEST),
.aclk(aclk),
.aresetn(aresetn)
);
endmodule
|
module probador(input logic pop,
input logic push,
output logic writeRead,
output logic newService,
output logic multiblock,
output logic timeoutenable,
output logic reset,
output logic[3:0] blockSize,
output logic fifo_full,
output logic [15:0] timeout ,
output logic SDclock,
output logic clock,
output logic [31:0] fromFifo_toPS,
output logic fromSD_SP);
initial begin
//reset
#0 writeRead=0;
#0 newService=0;
#0 multiblock =1;
#0 reset=1;
#0timeoutenable=0;
#0 blockSize=4'b0001;
#0 fifo_full =1;
#0 timeout=0;
#0 fromFifo_toPS=32'b11000000000000000000000000000011;
#0 fromSD_SP=0;
#30 reset=0;
//escritura a la SD
#40 writeRead=1;
#0 newService=1;
#50 newService=0;
#700 fromSD_SP=1;
#20 fromSD_SP=0;
#20 fromSD_SP=1;
#20 fromSD_SP=0;
#20 fromSD_SP=0;
#20 fromSD_SP=1;
#20 fromSD_SP=0;
#180fromFifo_toPS=32'b11000000000000001110000000000000;
#80 fromSD_SP=1;
#20 fromSD_SP=1;
#20 fromSD_SP=1;
#20 fromSD_SP=1;
#20 fromSD_SP=1;
#20 fromSD_SP=1;
#20 fromSD_SP=1;
#3000 $finish;
end
initial begin
clock = 0;
forever begin
#5 clock = ~clock;
end
end
initial begin
SDclock = 0;
forever begin
#15 SDclock = ~SDclock;
end
end
initial begin
//$display("\t\ttime,\tclk,\tmodo,\tenable,\tQ");
//$monitor("%d,\t%b,\t%b,\t%b,\t%b",$time, clk,modo,enb,Q);
$dumpfile ("tests/vcd/DAT.vcd");
$dumpvars;
end
endmodule
|
/*
* video.v Fake video driver
*
* This is a temporary display engine that simply renders the content of the
* screen buffer, ignoring the CRTC. This will be replaced by a proper render
* when memory is available.
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
module video(
input clk_i,
output hsync,
output vsync,
output de,
output clk_o,
output [7:0] r,
output [7:0] g,
output [7:0] b,
output [15:0] A_o,
input [7:0] D_i,
input [15:0] video_offset_i
);
parameter offset_x = 80;
parameter offset_y = 100;
// Wire definitions ===========================================================================
// Registers ==================================================================================
reg [10:0] hor = 0;
reg [9:0] ver = 0;
reg [10:0] pixel_x;
reg [9:0] pixel_y;
reg [15:0] video_offset;
reg [15:0] video_offset_delay;
reg [15:0] A = 0;
reg [7:0] rs = 0;
reg [7:0] gs = 0;
reg [7:0] bs = 0;
// Assignments ================================================================================
assign A_o = A;
// Module connections =========================================================================
// Simulation branches and control ============================================================
// Other logic ================================================================================
// Synchronizer chain for offset
always @(negedge clk_i) video_offset_delay <= video_offset_i;
// Move the counters
always @(negedge clk_i)
begin
if( hor < 11'd1056 )
hor <= hor + 1'b1;
else begin
hor <= 11'd0;
//ver <= (ver < 628) ? ver + 1'b1 : 1'b0;
if( ver < 628 )
begin
ver <= ver + 1'b1;
bs <= bs - 1'b1;
end else begin
ver <= 0;
bs <= 0;
video_offset = video_offset_delay;
end
end
end
// Valid during screen on
assign de = (hor >= 216) && (hor < 1016) && (ver >= 27) && (ver < 627);
// Syncs
assign hsync = (hor < 128); // Pos sync
assign vsync = (ver < 4); // Pos sync
// Clock
assign clk_o = clk_i;
// Generate picture here =========================
always @(posedge clk_i)
begin
// Display (DE) starts at pixel 216, so give us the timespan of 8 pixels
// To gather the data for the display, then pipeline the output
pixel_x <= hor - 11'd208; // Not 216
pixel_y <= ver - 10'd27 - offset_y;
end
// Convert X/Y to Address
wire [8:0] row = pixel_y[9:1]; // Duplicate rows
// Weird CPC offsets, every row is 2048 bytes offset
wire [10:0] Ay = (row[7:3] * 80);
wire [10:0] Axy = Ay + pixel_x[9:3]; // Div pixels by 8
wire [10:0] Atotal = Axy + video_offset[10:0];
// Set the address on negative clock because memory is strobed on positive clock
always @(negedge clk_i) A <= {video_offset[15:14], row[2:0], Atotal};
// Calculate the pixel (assume mode 1, so pixels 1+2,3+4,5+6,7+8 are duplicated)
// Don't care which color, so OR the bits, if not pen 0 then display
reg [0:7] pixels;
always @(negedge clk_i)
if ( pixel_x[2:0] == 3'd0 )
pixels <=
{
D_i[7] | D_i[3], D_i[7] | D_i[3],
D_i[6] | D_i[2], D_i[6] | D_i[2],
D_i[5] | D_i[1], D_i[5] | D_i[1],
D_i[4] | D_i[0], D_i[4] | D_i[0]
};
else
pixels <= {pixels[1:7],1'b0}; // Shift
// Use 648 as the last pixel location because pipeline needs 8 bits to read the memory
// So the end of the display is 8 pixels after the last pixel set has been obtained
wire en = de && (pixel_x < 10'd648) && (pixel_y < 10'd400);
assign r = (en) ? ((pixels[0]) ? 8'hf8 : 8'h0) : 8'd0;
assign g = (en) ? ((pixels[0]) ? 8'hf8 : 8'h0) : 8'd0;
assign b = (en) ? ((pixels[0]) ? 8'h00 : 8'h7d) : 8'd0;
/*
assign r = (en) ? ((pixels[0]) ? 8'h00 : 8'hff) : 8'd0;
assign g = (en) ? ((pixels[0]) ? 8'h00 : 8'hff) : 8'd0;
assign b = (en) ? ((pixels[0]) ? 8'h00 : 8'hff) : 8'd0;
*/
endmodule
|
/**
* @module controller
* @author sabertazimi
* @email [email protected]
* @brief control signals generator
* @input op op code
* @input funct functy code
* @output aluop,
* @output alusrc 1 => imm16, 0 => rt
* @output alusham 1 => sham, 0=> rt
* @output regdst 1 => rd, 0 => rt
* @output regwe 1 => enable, 0 => disable
* @output extop 1 => signed, 0 => unsigned
* @output ramtoreg 1 => ram to regfile, 0 => alu to regfile
* @output ramwe 1 => enable, 0 => disable
* @output beq 1 => current instruction is beq
* @output bne 1 => current instruction is bne
* @output bgtz 1 => current instruction is bgtz
* @output j 1 => current instruction is j
* @output jal 1 => current instruction is jal
* @output jr 1 => current instruction is jr
* @output syscall 1 => current instruction is syscall
* @output writetolo 1 => lo register write enable, 0 => lo register write disable
* @output lotoreg 1 => lo register to regfile, 0 => ram/alu to regfile
* @output rambyte 1 => load byte from ram, 0 => load word from ram
*/
module controller
(
input [5:0] op,
input [5:0] funct,
output [3:0] aluop,
output alusrc,
output alusham,
output regdst,
output regwe,
output extop,
output ramtoreg,
output ramwe,
output beq,
output bne,
output bgtz,
output j,
output jal,
output jr,
output syscall,
output writetolo,
output lotoreg,
output rambyte
);
wire add, addi, addiu, addu;
wire s_and, andi, sll, sra, srl;
wire sub, s_or, ori, s_nor;
wire lw, sw;
wire slt, slti, sltu;
wire divu, mflo;
wire lb;
instruction_typer instruction_typer (
.op(op),
.funct(funct),
.add(add),
.addi(addi),
.addiu(addiu),
.addu(addu),
.s_and(s_and),
.andi(andi),
.sll(sll),
.sra(sra),
.srl(srl),
.sub(sub),
.s_or(s_or),
.ori(ori),
.s_nor(s_nor),
.lw(lw),
.sw(sw),
.beq(beq),
.bne(bne),
.slt(slt),
.slti(slti),
.sltu(sltu),
.j(j),
.jal(jal),
.jr(jr),
.syscall(syscall),
.divu(divu),
.mflo(mflo),
.lb(lb),
.bgtz(bgtz)
);
assign aluop[0] = add || addi || addiu || addu || s_and || andi
|| sra || lw || sw || slt || slti || jal || lb || bgtz;
assign aluop[1] = s_and || andi || srl || sub || s_nor || slt || slti || bgtz;
assign aluop[2] = add || addi || addiu || addu || s_and || andi
|| sub || lw || sw || sltu || jal || divu || lb;
assign aluop[3] = s_or || ori || s_nor || slt || slti || sltu || bgtz;
assign alusrc = addi || addiu || andi || ori || lw || sw || slti || lb;
assign alusham = sll || sra || srl;
assign regdst = add || addu || s_and || sll || sra || srl
|| sub || s_or || s_nor || slt || sltu || mflo;
assign regwe = add || addi || addiu || addu || s_and || andi
|| sll || sra || srl || sub || s_or || ori || s_nor || lw
|| slt || slti || sltu || jal || mflo || lb;
assign extop = addi || addiu || lw || sw || slti || lb;
assign ramtoreg = lw || lb;
assign ramwe = sw;
assign writetolo = divu;
assign lotoreg = mflo;
assign rambyte = lb;
endmodule // controller
|
module abc9_test001(input a, output o);
assign o = a;
endmodule
module abc9_test002(input [1:0] a, output o);
assign o = a[1];
endmodule
module abc9_test003(input [1:0] a, output [1:0] o);
assign o = a;
endmodule
module abc9_test004(input [1:0] a, output o);
assign o = ^a;
endmodule
module abc9_test005(input [1:0] a, output o, output p);
assign o = ^a;
assign p = ~o;
endmodule
module abc9_test006(input [1:0] a, output [2:0] o);
assign o[0] = ^a;
assign o[1] = ~o[0];
assign o[2] = o[1];
endmodule
module abc9_test007(input a, output o);
wire b, c;
assign c = ~a;
assign b = c;
abc9_test007_sub s(b, o);
endmodule
module abc9_test007_sub(input a, output b);
assign b = a;
endmodule
module abc9_test008(input a, output o);
wire b, c;
assign b = ~a;
assign c = b;
abc9_test008_sub s(b, o);
endmodule
module abc9_test008_sub(input a, output b);
assign b = ~a;
endmodule
module abc9_test009(inout io, input oe);
reg latch;
always @(io or oe)
if (!oe)
latch <= io;
assign io = oe ? ~latch : 1'bz;
endmodule
module abc9_test010(inout [7:0] io, input oe);
reg [7:0] latch;
always @(io or oe)
if (!oe)
latch <= io;
assign io = oe ? ~latch : 8'bz;
endmodule
module abc9_test011(inout io, input oe);
reg latch;
always @(io or oe)
if (!oe)
latch <= io;
//assign io = oe ? ~latch : 8'bz;
endmodule
module abc9_test012(inout io, input oe);
reg latch;
//always @(io or oe)
// if (!oe)
// latch <= io;
assign io = oe ? ~latch : 8'bz;
endmodule
module abc9_test013(inout [3:0] io, input oe);
reg [3:0] latch;
always @(io or oe)
if (!oe)
latch[3:0] <= io[3:0];
else
latch[7:4] <= io;
assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
endmodule
module abc9_test014(inout [7:0] io, input oe);
abc9_test012_sub sub(io, oe);
endmodule
module abc9_test012_sub(inout [7:0] io, input oe);
reg [7:0] latch;
always @(io or oe)
if (!oe)
latch[3:0] <= io;
else
latch[7:4] <= io;
assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
endmodule
module abc9_test015(input a, output b, input c);
assign b = ~a;
(* keep *) wire d;
assign d = ~c;
endmodule
module abc9_test016(input a, output b);
assign b = ~a;
(* keep *) reg c;
always @* c <= ~a;
endmodule
module abc9_test017(input a, output b);
assign b = ~a;
(* keep *) reg c;
always @* c = b;
endmodule
module abc9_test018(input a, output b, output c);
assign b = ~a;
(* keep *) wire [1:0] d;
assign c = &d;
endmodule
module abc9_test019(input a, output b);
assign b = ~a;
(* keep *) reg [1:0] c;
reg d;
always @* d <= &c;
endmodule
module abc9_test020(input a, output b);
assign b = ~a;
(* keep *) reg [1:0] c;
(* keep *) reg d;
always @* d <= &c;
endmodule
// Citation: https://github.com/alexforencich/verilog-ethernet
module abc9_test021(clk, rst, s_eth_hdr_valid, s_eth_hdr_ready, s_eth_dest_mac, s_eth_src_mac, s_eth_type, s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid, s_eth_payload_axis_tready, s_eth_payload_axis_tlast, s_eth_payload_axis_tid, s_eth_payload_axis_tdest, s_eth_payload_axis_tuser, m_eth_hdr_valid, m_eth_hdr_ready, m_eth_dest_mac, m_eth_src_mac, m_eth_type, m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid, m_eth_payload_axis_tready, m_eth_payload_axis_tlast, m_eth_payload_axis_tid, m_eth_payload_axis_tdest, m_eth_payload_axis_tuser);
input clk;
output [47:0] m_eth_dest_mac;
input m_eth_hdr_ready;
output m_eth_hdr_valid;
output [7:0] m_eth_payload_axis_tdata;
output [7:0] m_eth_payload_axis_tdest;
output [7:0] m_eth_payload_axis_tid;
output m_eth_payload_axis_tkeep;
output m_eth_payload_axis_tlast;
input m_eth_payload_axis_tready;
output m_eth_payload_axis_tuser;
output m_eth_payload_axis_tvalid;
output [47:0] m_eth_src_mac;
output [15:0] m_eth_type;
input rst;
input [191:0] s_eth_dest_mac;
output [3:0] s_eth_hdr_ready;
input [3:0] s_eth_hdr_valid;
input [31:0] s_eth_payload_axis_tdata;
input [31:0] s_eth_payload_axis_tdest;
input [31:0] s_eth_payload_axis_tid;
input [3:0] s_eth_payload_axis_tkeep;
input [3:0] s_eth_payload_axis_tlast;
output [3:0] s_eth_payload_axis_tready;
input [3:0] s_eth_payload_axis_tuser;
input [3:0] s_eth_payload_axis_tvalid;
input [191:0] s_eth_src_mac;
input [63:0] s_eth_type;
(* keep *)
wire [0:0] grant, request;
wire a;
not u0 (
a,
grant[0]
);
and u1 (
request[0],
s_eth_hdr_valid[0],
a
);
(* keep *)
MUXF8 u2 (
.I0(1'bx),
.I1(1'bx),
.O(o),
.S(1'bx)
);
arbiter arb_inst (
.acknowledge(acknowledge),
.clk(clk),
.grant(grant),
.grant_encoded(grant_encoded),
.grant_valid(grant_valid),
.request(request),
.rst(rst)
);
endmodule
module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encoded);
input [3:0] acknowledge;
input clk;
output [3:0] grant;
output [1:0] grant_encoded;
output grant_valid;
input [3:0] request;
input rst;
endmodule
(* abc9_box_id=1, blackbox *)
module MUXF8(input I0, I1, S, output O);
specify
(I0 => O) = 0;
(I1 => O) = 0;
(S => O) = 0;
endspecify
endmodule
// Citation: https://github.com/alexforencich/verilog-ethernet
module abc9_test022
(
input wire clk,
input wire i,
output wire [7:0] m_eth_payload_axis_tkeep
);
reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0;
assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
always @(posedge clk)
m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f;
endmodule
// Citation: https://github.com/riscv/riscv-bitmanip
module abc9_test023 #(
parameter integer N = 2,
parameter integer M = 2
) (
input [7:0] din,
output [M-1:0] dout
);
wire [2*M-1:0] mask = {M{1'b1}};
assign dout = (mask << din[N-1:0]) >> M;
endmodule
module abc9_test024(input [3:0] i, output [3:0] o);
abc9_test024_sub a(i[1:0], o[1:0]);
endmodule
module abc9_test024_sub(input [1:0] i, output [1:0] o);
assign o = i;
endmodule
module abc9_test025(input [3:0] i, output [3:0] o);
abc9_test024_sub a(i[2:1], o[2:1]);
endmodule
module abc9_test026(output [3:0] o, p);
assign o = { 1'b1, 1'bx };
assign p = { 1'b1, 1'bx, 1'b0 };
endmodule
module abc9_test030(input [3:0] d, input en, output reg [3:0] q);
always @*
if (en)
q <= d;
endmodule
module abc9_test031(input clk1, clk2, d, output reg q1, q2);
always @(posedge clk1) q1 <= d;
always @(negedge clk2) q2 <= q1;
endmodule
module abc9_test032(input clk, d, r, output reg q);
always @(posedge clk or posedge r)
if (r) q <= 1'b0;
else q <= d;
endmodule
module abc9_test033(input clk, d, r, output reg q);
always @(negedge clk or posedge r)
if (r) q <= 1'b1;
else q <= d;
endmodule
module abc9_test034(input clk, d, output reg q1, q2);
always @(posedge clk) q1 <= d;
always @(posedge clk) q2 <= q1;
endmodule
module abc9_test035(input clk, d, output reg [1:0] q);
always @(posedge clk) q[0] <= d;
always @(negedge clk) q[1] <= q[0];
endmodule
module abc9_test036(input A, B, S, output [1:0] O);
(* keep *)
MUXF8 m (
.I0(I0),
.I1(I1),
.O(O[0]),
.S(S)
);
MUXF8 m2 (
.I0(I0),
.I1(I1),
.O(O[1]),
.S(S)
);
endmodule
|
module xyz (/*AUTOARG*/
// Outputs
signal_f, signal_c,
// Inputs
signal_b
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [2:0] signal_b; // To u_abc of abc.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output signal_c; // From u_abc of abc.v
output signal_f; // From u_def of def.v
// End of automatics
/*AUTOWIRE*/
/* abc AUTO_TEMPLATE
(
// Outputs
.signal_c (signal_c),
// Inputs
.signal_a ({1'b0, signal_f}),
.signal_b (signal_b[2:0]));
*/
abc u_abc
(/*AUTOINST*/
// Outputs
.signal_c (signal_c), // Templated
// Inputs
.signal_a ({1'b0, signal_f}), // Templated
.signal_b (signal_b[2:0])); // Templated
/* def AUTO_TEMPLATE
(// Outputs
.signal_f (signal_f),
// Inputs
.signal_d ({1'b1, signal_c}),
.signal_e ({2'b11, signal_e}),
.signal_e2 (({2'b11, signal_e2})),
.signal_e3 ((signal_e3)) );
*/
def u_def
(/*AUTOINST*/
// Outputs
.signal_f (signal_f), // Templated
// Inputs
.signal_d ({1'b1, signal_c}), // Templated
.signal_e ({2'b11, signal_e}), // Templated
.signal_e2 (({2'b11, signal_e2})), // Templated
.signal_e3 ((signal_e3))); // Templated
endmodule // xyz
module abc (/*AUTOARG*/
// Outputs
signal_c,
// Inputs
signal_a, signal_b
);
input [1:0] signal_a;
input [2:0] signal_b;
output signal_c;
endmodule // abc
module def (/*AUTOARG*/
// Outputs
signal_f,
// Inputs
signal_d, signal_e, signal_e2, signal_e3
);
input [1:0] signal_d;
input [2:0] signal_e;
input [3:0] signal_e2;
input [3:0] signal_e3;
output signal_f;
endmodule // def
// Local Variables:
// verilog-auto-ignore-concat: t
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4B_BEHAVIORAL_V
`define SKY130_FD_SC_LS__AND4B_BEHAVIORAL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__and4b (
X ,
A_N,
B ,
C ,
D
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B, C, D);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4B_BEHAVIORAL_V
|
/*
* DSI Shield
* Copyright (C) 2013-2014 twl <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* video_mixer.v - asynchronous video overlay. Overlays framebuffer
image over HDMI input, outputs data for the DSI core. Work in progress. */
`timescale 1ns/1ps
module video_mixer
(
input clk_sys_i,
input clk_dvi_i,
input rst_n_i,
output fb_almost_full_o,
input fb_wr_i,
input [47:0] fb_pixel_i,
input fb_vsync_i,
output fb_next_frame_o,
input dvi_de_i,
input dvi_hsync_i,
input dvi_vsync_i,
input [47:0] dvi_pixel_i,
input dvi_link_up_i,
input dvi_valid_i,
input dsif_almost_full_i,
output dsif_wr_o,
output [47:0] dsif_pix_o,
output reg dsif_vsync_o,
input dsif_next_frame_i,
output [7:0] mixer_ctl_o,
input [7:0] mixer_ctl_i
);
`define DVI_WAIT_VBLANK 0
`define DVI_WAIT_LINK 1
`define DVI_WAIT_ACTIVE 2
`define DVI_ACTIVE 3
reg [2:0] dvi_state;
reg dvi_visible_start;
reg dvi_vsync_d, dvi_frame_p;
reg dvi_fifo_mask;
wire rst_n_dvi = 1;
always@(posedge clk_dvi_i)
begin
if (!rst_n_dvi || !dvi_link_up_i) begin
dvi_state <= `DVI_WAIT_LINK;
dvi_visible_start <= 0;
dvi_vsync_d <= 0;
dvi_frame_p <= 0;
dvi_fifo_mask <= 0;
end else begin
dvi_vsync_d <= dvi_vsync_i;
case (dvi_state)
`DVI_WAIT_LINK:
begin
dvi_frame_p <= 0;
dvi_state<=`DVI_WAIT_VBLANK;
end
`DVI_WAIT_VBLANK:
begin
// vsync going low
if(!dvi_de_i && !dvi_vsync_i && dvi_vsync_d)
begin
dvi_fifo_mask <=1;
dvi_frame_p <= 1;
dvi_state <= `DVI_WAIT_ACTIVE;
end else
dvi_frame_p <= 0;
end // case: `DVI_WAIT_VBLANK
`DVI_WAIT_ACTIVE:
if(dvi_de_i)
dvi_state <= `DVI_ACTIVE;
`DVI_ACTIVE:
begin
if( dvi_vsync_i && !dvi_de_i )
dvi_state <= `DVI_WAIT_VBLANK;
end
endcase // case (dvi_state)
end
end
wire dvi_rd, dvi_empty;
wire [47:0] dvi_pixel, fb_pixel;
wire overlay_enable, fbuf_purge;
generic_async_fifo
#(
.g_size(512),
.g_data_width(48),
.g_almost_empty_threshold(10),
.g_almost_full_threshold(510)
)
U_DVI_ElasticBuffer
(
.rst_n_i(dvi_link_up_i & rst_n_i & overlay_enable & ~dvi_vsync_i),
.clk_wr_i(clk_dvi_i),
.clk_rd_i(clk_sys_i),
.wr_full_o(wr_full),
.d_i(dvi_pixel_i),
.we_i(dvi_valid_i & dvi_fifo_mask),
.rd_i(dvi_rd),
.rd_empty_o(dvi_empty),
.q_o(dvi_pixel)
);
generic_sync_fifo
#(
.g_size(128),
.g_data_width(48),
.g_almost_empty_threshold(1),
.g_almost_full_threshold(100),
.g_with_almost_full(1)
)
U_FB_ElasticBuffer
(
.rst_n_i(rst_n_i & ~fbuf_purge),
.clk_i(clk_sys_i),
.almost_full_o(fb_almost_full_ebuf),
.d_i(fb_pixel_i),
.we_i(fb_wr_i),
.rd_i(dvi_rd & ~dsif_almost_full_i),
.empty_o(),
.q_o(fb_pixel)
);
`define ST_IDLE 0
`define ST_WAIT_DVI 1
`define ST_PUSH 2
`define ST_WAIT_ACTIVE 3
`define ST_PREFILL 4
reg [2:0] vid_state;
reg [2:0] dvi_frame_p_sync;
wire dvi_frame_p_sys;
always@(posedge clk_sys_i)
dvi_frame_p_sync <= { dvi_frame_p_sync[1:0], dvi_frame_p };
assign dvi_frame_p_sys = dvi_frame_p_sync[1] & ~dvi_frame_p_sync[2];
reg [10:0] count;
reg dsif_wr_reg;
always@(posedge clk_sys_i) begin
if(!rst_n_i || !overlay_enable) begin
vid_state <= `ST_IDLE;
dsif_vsync_o <= 1;
end else begin
case (vid_state)
`ST_IDLE: if(dsif_next_frame_i) begin
vid_state <= `ST_WAIT_DVI;
dsif_vsync_o <= 0;
end
`ST_WAIT_DVI:
if(dvi_frame_p_sys) begin
vid_state <= `ST_WAIT_ACTIVE;
dsif_vsync_o <= 1;
count <= 0;
end
`ST_WAIT_ACTIVE:
if(!dsif_next_frame_i)
begin
dsif_vsync_o <= 0;
vid_state <= `ST_PUSH;
end
`ST_PUSH:
begin
dsif_vsync_o <= 0;
if(dsif_next_frame_i)
vid_state <= `ST_WAIT_DVI;
end
endcase // case (vid_state)
end // else: !if(!rst_n_i || !r_enable)
end // always@ (posedge clk_sys_i)
reg gb_even;
reg [23:0] dsif_pix_hi;
reg dsif_wr = 0;
reg [4:0] rst_dly;
always@(posedge clk_sys_i)
if(!rst_n_i)
rst_dly <= 10;
else if (rst_dly)
rst_dly <= rst_dly -1;
assign dvi_rd = (!dvi_empty) && (vid_state != `ST_IDLE) && (vid_state != `ST_WAIT_DVI);
reg dvi_rd_d0;
always@(posedge clk_sys_i)
if(!rst_n_i)
dvi_rd_d0 <= 0;
else
dvi_rd_d0 <= dvi_rd;
reg [47:0] dsif_pix_reg;
// color key
always@(posedge clk_sys_i)
begin
// no color key for the moment
// if(fb_pixel[47:24] == 'h0000f8)
dsif_pix_reg [47:24] <= dvi_pixel[47:24];
// else
// dsif_pix_reg [47:24] <= fb_pixel[47:24];
// if(fb_pixel[23:0] == 'h0000f8)
dsif_pix_reg [23:0] <= dvi_pixel[23:0];
// else
// dsif_pix_reg [23:0] <= fb_pixel[23:0];
dsif_wr_reg <= dvi_rd_d0;
end
assign dsif_pix_o = overlay_enable ? dsif_pix_reg : fb_pixel_i;
assign dsif_wr_o = overlay_enable ? dsif_wr_reg : fb_wr_i;
assign fb_next_frame_o = overlay_enable ? (vid_state == `ST_WAIT_DVI) : dsif_next_frame_i;
assign fb_almost_full_o = overlay_enable ? fb_almost_full_ebuf : dsif_almost_full_i;
assign overlay_enable = mixer_ctl_i[0];
assign fbuf_purge = mixer_ctl_i[1];
assign mixer_ctl_o[0] = dvi_link_up_i;
assign mixer_ctl_o[1] = dvi_vsync_i;
endmodule // video_mixer
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N (
Q ,
D ,
GATE ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__AND4B_FUNCTIONAL_PP_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B, C, D );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4B_FUNCTIONAL_PP_V
|
// file: Clock65MHz.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____65.000______0.000______50.0______507.692____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "Clock65MHz,clk_wiz_v3_6,{component_name=Clock65MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module Clock65MHz
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (20),
.CLKFX_MULTIPLY (13),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk0));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
// soc_system_hps_0.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1 162 at 2014.12.19.15:54:14
`timescale 1 ps / 1 ps
module soc_system_hps_0 #(
parameter F2S_Width = 2,
parameter S2F_Width = 2
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire f2h_cold_rst_req_n, // f2h_cold_reset_req.reset_n
input wire f2h_dbg_rst_req_n, // f2h_debug_reset_req.reset_n
input wire f2h_warm_rst_req_n, // f2h_warm_reset_req.reset_n
input wire [27:0] f2h_stm_hwevents, // f2h_stm_hw_events.stm_hwevents
input wire f2h_axi_clk, // f2h_axi_clock.clk
input wire [7:0] f2h_AWID, // f2h_axi_slave.awid
input wire [31:0] f2h_AWADDR, // .awaddr
input wire [3:0] f2h_AWLEN, // .awlen
input wire [2:0] f2h_AWSIZE, // .awsize
input wire [1:0] f2h_AWBURST, // .awburst
input wire [1:0] f2h_AWLOCK, // .awlock
input wire [3:0] f2h_AWCACHE, // .awcache
input wire [2:0] f2h_AWPROT, // .awprot
input wire f2h_AWVALID, // .awvalid
output wire f2h_AWREADY, // .awready
input wire [4:0] f2h_AWUSER, // .awuser
input wire [7:0] f2h_WID, // .wid
input wire [63:0] f2h_WDATA, // .wdata
input wire [7:0] f2h_WSTRB, // .wstrb
input wire f2h_WLAST, // .wlast
input wire f2h_WVALID, // .wvalid
output wire f2h_WREADY, // .wready
output wire [7:0] f2h_BID, // .bid
output wire [1:0] f2h_BRESP, // .bresp
output wire f2h_BVALID, // .bvalid
input wire f2h_BREADY, // .bready
input wire [7:0] f2h_ARID, // .arid
input wire [31:0] f2h_ARADDR, // .araddr
input wire [3:0] f2h_ARLEN, // .arlen
input wire [2:0] f2h_ARSIZE, // .arsize
input wire [1:0] f2h_ARBURST, // .arburst
input wire [1:0] f2h_ARLOCK, // .arlock
input wire [3:0] f2h_ARCACHE, // .arcache
input wire [2:0] f2h_ARPROT, // .arprot
input wire f2h_ARVALID, // .arvalid
output wire f2h_ARREADY, // .arready
input wire [4:0] f2h_ARUSER, // .aruser
output wire [7:0] f2h_RID, // .rid
output wire [63:0] f2h_RDATA, // .rdata
output wire [1:0] f2h_RRESP, // .rresp
output wire f2h_RLAST, // .rlast
output wire f2h_RVALID, // .rvalid
input wire f2h_RREADY, // .rready
input wire h2f_lw_axi_clk, // h2f_lw_axi_clock.clk
output wire [11:0] h2f_lw_AWID, // h2f_lw_axi_master.awid
output wire [20:0] h2f_lw_AWADDR, // .awaddr
output wire [3:0] h2f_lw_AWLEN, // .awlen
output wire [2:0] h2f_lw_AWSIZE, // .awsize
output wire [1:0] h2f_lw_AWBURST, // .awburst
output wire [1:0] h2f_lw_AWLOCK, // .awlock
output wire [3:0] h2f_lw_AWCACHE, // .awcache
output wire [2:0] h2f_lw_AWPROT, // .awprot
output wire h2f_lw_AWVALID, // .awvalid
input wire h2f_lw_AWREADY, // .awready
output wire [11:0] h2f_lw_WID, // .wid
output wire [31:0] h2f_lw_WDATA, // .wdata
output wire [3:0] h2f_lw_WSTRB, // .wstrb
output wire h2f_lw_WLAST, // .wlast
output wire h2f_lw_WVALID, // .wvalid
input wire h2f_lw_WREADY, // .wready
input wire [11:0] h2f_lw_BID, // .bid
input wire [1:0] h2f_lw_BRESP, // .bresp
input wire h2f_lw_BVALID, // .bvalid
output wire h2f_lw_BREADY, // .bready
output wire [11:0] h2f_lw_ARID, // .arid
output wire [20:0] h2f_lw_ARADDR, // .araddr
output wire [3:0] h2f_lw_ARLEN, // .arlen
output wire [2:0] h2f_lw_ARSIZE, // .arsize
output wire [1:0] h2f_lw_ARBURST, // .arburst
output wire [1:0] h2f_lw_ARLOCK, // .arlock
output wire [3:0] h2f_lw_ARCACHE, // .arcache
output wire [2:0] h2f_lw_ARPROT, // .arprot
output wire h2f_lw_ARVALID, // .arvalid
input wire h2f_lw_ARREADY, // .arready
input wire [11:0] h2f_lw_RID, // .rid
input wire [31:0] h2f_lw_RDATA, // .rdata
input wire [1:0] h2f_lw_RRESP, // .rresp
input wire h2f_lw_RLAST, // .rlast
input wire h2f_lw_RVALID, // .rvalid
output wire h2f_lw_RREADY, // .rready
input wire h2f_axi_clk, // h2f_axi_clock.clk
output wire [11:0] h2f_AWID, // h2f_axi_master.awid
output wire [29:0] h2f_AWADDR, // .awaddr
output wire [3:0] h2f_AWLEN, // .awlen
output wire [2:0] h2f_AWSIZE, // .awsize
output wire [1:0] h2f_AWBURST, // .awburst
output wire [1:0] h2f_AWLOCK, // .awlock
output wire [3:0] h2f_AWCACHE, // .awcache
output wire [2:0] h2f_AWPROT, // .awprot
output wire h2f_AWVALID, // .awvalid
input wire h2f_AWREADY, // .awready
output wire [11:0] h2f_WID, // .wid
output wire [63:0] h2f_WDATA, // .wdata
output wire [7:0] h2f_WSTRB, // .wstrb
output wire h2f_WLAST, // .wlast
output wire h2f_WVALID, // .wvalid
input wire h2f_WREADY, // .wready
input wire [11:0] h2f_BID, // .bid
input wire [1:0] h2f_BRESP, // .bresp
input wire h2f_BVALID, // .bvalid
output wire h2f_BREADY, // .bready
output wire [11:0] h2f_ARID, // .arid
output wire [29:0] h2f_ARADDR, // .araddr
output wire [3:0] h2f_ARLEN, // .arlen
output wire [2:0] h2f_ARSIZE, // .arsize
output wire [1:0] h2f_ARBURST, // .arburst
output wire [1:0] h2f_ARLOCK, // .arlock
output wire [3:0] h2f_ARCACHE, // .arcache
output wire [2:0] h2f_ARPROT, // .arprot
output wire h2f_ARVALID, // .arvalid
input wire h2f_ARREADY, // .arready
input wire [11:0] h2f_RID, // .rid
input wire [63:0] h2f_RDATA, // .rdata
input wire [1:0] h2f_RRESP, // .rresp
input wire h2f_RLAST, // .rlast
input wire h2f_RVALID, // .rvalid
output wire h2f_RREADY, // .rready
input wire [31:0] f2h_irq_p0, // f2h_irq0.irq
input wire [31:0] f2h_irq_p1, // f2h_irq1.irq
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO61 // .hps_io_gpio_inst_GPIO61
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
soc_system_hps_0_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.f2h_cold_rst_req_n (f2h_cold_rst_req_n), // f2h_cold_reset_req.reset_n
.f2h_dbg_rst_req_n (f2h_dbg_rst_req_n), // f2h_debug_reset_req.reset_n
.f2h_warm_rst_req_n (f2h_warm_rst_req_n), // f2h_warm_reset_req.reset_n
.f2h_stm_hwevents (f2h_stm_hwevents), // f2h_stm_hw_events.stm_hwevents
.f2h_axi_clk (f2h_axi_clk), // f2h_axi_clock.clk
.f2h_AWID (f2h_AWID), // f2h_axi_slave.awid
.f2h_AWADDR (f2h_AWADDR), // .awaddr
.f2h_AWLEN (f2h_AWLEN), // .awlen
.f2h_AWSIZE (f2h_AWSIZE), // .awsize
.f2h_AWBURST (f2h_AWBURST), // .awburst
.f2h_AWLOCK (f2h_AWLOCK), // .awlock
.f2h_AWCACHE (f2h_AWCACHE), // .awcache
.f2h_AWPROT (f2h_AWPROT), // .awprot
.f2h_AWVALID (f2h_AWVALID), // .awvalid
.f2h_AWREADY (f2h_AWREADY), // .awready
.f2h_AWUSER (f2h_AWUSER), // .awuser
.f2h_WID (f2h_WID), // .wid
.f2h_WDATA (f2h_WDATA), // .wdata
.f2h_WSTRB (f2h_WSTRB), // .wstrb
.f2h_WLAST (f2h_WLAST), // .wlast
.f2h_WVALID (f2h_WVALID), // .wvalid
.f2h_WREADY (f2h_WREADY), // .wready
.f2h_BID (f2h_BID), // .bid
.f2h_BRESP (f2h_BRESP), // .bresp
.f2h_BVALID (f2h_BVALID), // .bvalid
.f2h_BREADY (f2h_BREADY), // .bready
.f2h_ARID (f2h_ARID), // .arid
.f2h_ARADDR (f2h_ARADDR), // .araddr
.f2h_ARLEN (f2h_ARLEN), // .arlen
.f2h_ARSIZE (f2h_ARSIZE), // .arsize
.f2h_ARBURST (f2h_ARBURST), // .arburst
.f2h_ARLOCK (f2h_ARLOCK), // .arlock
.f2h_ARCACHE (f2h_ARCACHE), // .arcache
.f2h_ARPROT (f2h_ARPROT), // .arprot
.f2h_ARVALID (f2h_ARVALID), // .arvalid
.f2h_ARREADY (f2h_ARREADY), // .arready
.f2h_ARUSER (f2h_ARUSER), // .aruser
.f2h_RID (f2h_RID), // .rid
.f2h_RDATA (f2h_RDATA), // .rdata
.f2h_RRESP (f2h_RRESP), // .rresp
.f2h_RLAST (f2h_RLAST), // .rlast
.f2h_RVALID (f2h_RVALID), // .rvalid
.f2h_RREADY (f2h_RREADY), // .rready
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY), // .rready
.h2f_axi_clk (h2f_axi_clk), // h2f_axi_clock.clk
.h2f_AWID (h2f_AWID), // h2f_axi_master.awid
.h2f_AWADDR (h2f_AWADDR), // .awaddr
.h2f_AWLEN (h2f_AWLEN), // .awlen
.h2f_AWSIZE (h2f_AWSIZE), // .awsize
.h2f_AWBURST (h2f_AWBURST), // .awburst
.h2f_AWLOCK (h2f_AWLOCK), // .awlock
.h2f_AWCACHE (h2f_AWCACHE), // .awcache
.h2f_AWPROT (h2f_AWPROT), // .awprot
.h2f_AWVALID (h2f_AWVALID), // .awvalid
.h2f_AWREADY (h2f_AWREADY), // .awready
.h2f_WID (h2f_WID), // .wid
.h2f_WDATA (h2f_WDATA), // .wdata
.h2f_WSTRB (h2f_WSTRB), // .wstrb
.h2f_WLAST (h2f_WLAST), // .wlast
.h2f_WVALID (h2f_WVALID), // .wvalid
.h2f_WREADY (h2f_WREADY), // .wready
.h2f_BID (h2f_BID), // .bid
.h2f_BRESP (h2f_BRESP), // .bresp
.h2f_BVALID (h2f_BVALID), // .bvalid
.h2f_BREADY (h2f_BREADY), // .bready
.h2f_ARID (h2f_ARID), // .arid
.h2f_ARADDR (h2f_ARADDR), // .araddr
.h2f_ARLEN (h2f_ARLEN), // .arlen
.h2f_ARSIZE (h2f_ARSIZE), // .arsize
.h2f_ARBURST (h2f_ARBURST), // .arburst
.h2f_ARLOCK (h2f_ARLOCK), // .arlock
.h2f_ARCACHE (h2f_ARCACHE), // .arcache
.h2f_ARPROT (h2f_ARPROT), // .arprot
.h2f_ARVALID (h2f_ARVALID), // .arvalid
.h2f_ARREADY (h2f_ARREADY), // .arready
.h2f_RID (h2f_RID), // .rid
.h2f_RDATA (h2f_RDATA), // .rdata
.h2f_RRESP (h2f_RRESP), // .rresp
.h2f_RLAST (h2f_RLAST), // .rlast
.h2f_RVALID (h2f_RVALID), // .rvalid
.h2f_RREADY (h2f_RREADY), // .rready
.f2h_irq_p0 (f2h_irq_p0), // f2h_irq0.irq
.f2h_irq_p1 (f2h_irq_p1) // f2h_irq1.irq
);
soc_system_hps_0_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO48 (hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61) // .hps_io_gpio_inst_GPIO61
);
endmodule
|
module memory_tb;
// Constants
parameter data_width = 32;
parameter address_width = 32;
parameter depth = 1048576;
parameter bytes_in_word = 4-1; // -1 for 0 based indexed
parameter bits_in_bytes = 8-1; // -1 for 0 based indexed
parameter BYTE = 8;
parameter start_addr = 32'h80020000;
// Input Ports
reg clock;
reg [address_width-1:0] address;
reg [data_width-1:0] data_in;
reg [1:0] access_size;
reg rw;
reg enable;
// Output Ports
wire busy;
wire [data_width-1:0] data_out;
// fileIO stuff
integer fd;
integer scan_fd;
integer status_read, status_write;
integer sscanf_ret;
integer words_read;
integer words_written;
reg [31:0] line;
reg [31:0] data_read;
// Instantiate the memory
memory M0 (
.clock (clock),
.address (address),
.data_in (data_in),
.access_size (access_size),
.rw (rw),
.enable (enable),
.busy (busy),
.data_out (data_out)
);
initial begin
fd = $fopen("SumArray.x", "r");
if (!fd)
$display("Could not open");
clock = 0;
address = start_addr;
scan_fd = $fscanf(fd, "%x", data_in);
//data_in = 0;
access_size = 2'b0_0;
enable = 1;
rw = 0; // Start writing first.
words_read = 0;
words_written = 1;
end
always @(posedge clock) begin
if (rw == 0) begin
enable = 1;
//rw = 0;
scan_fd = $fscanf(fd, "%x", line);
if (!$feof(fd)) begin
data_in = line;
$display("line = %x", data_in);
address = address + 4;
words_written = words_written + 1;
end
else begin
rw = 1;
address = 32'h80020000;
end
end
else if ($feof(fd) && (words_read < words_written)) begin
// done writing, now read...
rw = 1;
enable = 1;
data_read = data_out;
$display("data_read = %x", data_read);
address = address + 4;
words_read = words_read + 1;
end
else if (words_read >= words_written) begin
// TODO: Add logic to end simulation.
end
end
always
#5 clock = ! clock;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41OI_SYMBOL_V
`define SKY130_FD_SC_MS__A41OI_SYMBOL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a41oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41OI_SYMBOL_V
|
module var18_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7
+ R * 9'd7;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23
+ R * 9'd26;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30
+ R * 9'd12;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVPWRVGND_TB_V
`define SKY130_FD_SC_HDLL__TAPVPWRVGND_TB_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__tapvpwrvgnd.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_hdll__tapvpwrvgnd dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVPWRVGND_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO0P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__LSBUFISO0P_BEHAVIORAL_PP_V
/**
* lsbufiso0p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbufiso0p (
X ,
SLEEP ,
A ,
DESTPWR,
VPWR ,
VGND ,
DESTVPB,
VPB ,
VNB
);
// Module ports
output X ;
input SLEEP ;
input A ;
input DESTPWR;
input VPWR ;
input VGND ;
input DESTVPB;
input VPB ;
input VNB ;
// Local signals
wire sleepb ;
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_sleepb;
wire and0_out_X ;
// Name Output Other arguments
not not0 (sleepb , SLEEP );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_sleepb, sleepb, DESTPWR, VGND );
and and0 (and0_out_X , pwrgood_pp1_out_sleepb, pwrgood_pp0_out_A);
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp2 (X , and0_out_X, DESTPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO0P_BEHAVIORAL_PP_V
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
// Oversampling UART receiver.
module UART_RX(
input rst, clk, baud_edge, rx,
output [7:0] data,
output data_ready, framing_error
);
parameter OVERSAMPLE = 8;
localparam FIND_EDGE = 3'd1, START = 3'd2, DATA = 3'd3, END = 3'd4;
reg prev_rx;
reg [7:0] data_reg;
reg [2:0] data_counter;
reg [2:0] state = 0;
reg [$clog2(OVERSAMPLE+OVERSAMPLE/2)-1:0] over_sample_counter = 0;
reg data_ready_reg = 0;
reg framing_error_reg = 0;
assign data = data_reg;
assign data_ready = data_ready_reg;
assign framing_error = framing_error_reg;
always @(posedge clk) begin
if(rst) begin
data_reg <= 0;
prev_rx <= 0;
data_ready_reg <= 0;
state <= FIND_EDGE;
data_counter <= 0;
over_sample_counter <= 0;
end else if(baud_edge) begin
case(state)
FIND_EDGE: begin
prev_rx <= rx;
if(prev_rx & !rx) begin
state <= START;
prev_rx <= 0;
over_sample_counter <= 0;
end
end
START: begin
// Align sample edge in the middle of the pulses.
if(over_sample_counter == OVERSAMPLE/2-1) begin
over_sample_counter <= 0;
data_counter <= 0;
state <= DATA;
end else begin
over_sample_counter <= over_sample_counter + 1;
end
end
DATA: begin
if(over_sample_counter == OVERSAMPLE-1) begin
over_sample_counter <= 0;
data_reg[data_counter] <= rx;
if(data_counter == 7) begin
state <= END;
data_counter <= 0;
end else begin
data_counter <= data_counter + 1;
end
end else begin
over_sample_counter <= over_sample_counter + 1;
end
end
END: begin
if(over_sample_counter == OVERSAMPLE-1) begin
if(rx) begin
data_ready_reg <= 1;
end else begin
framing_error_reg <= 1;
end
state <= FIND_EDGE;
end else begin
over_sample_counter <= over_sample_counter + 1;
end
end
default: begin
data_ready_reg <= 0;
state <= FIND_EDGE;
end
endcase
end else begin
data_ready_reg <= 0;
framing_error_reg <= 0;
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu Jun 01 02:22:05 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/test_cdma/test_cdma.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_stub.v
// Design : system_xlconstant_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_xlconstant_0_0(dout)
/* synthesis syn_black_box black_box_pad_pin="dout[0:0]" */;
output [0:0]dout;
endmodule
|
module rf(clk,p0_addr,p1_addr,p0,p1,re0,re1,dst_addr,dst,we,hlt);
//////////////////////////////////////////////////////////////////
// Triple ported register file. Two read ports (p0 & p1), and //
// one write port (dst). Data is written on clock high, and //
// read on clock low //////////////////////////////////////////
//////////////////////
input clk;
input [3:0] p0_addr, p1_addr; // two read port addresses
input re0,re1; // read enables (power not functionality)
input [3:0] dst_addr; // write address
input [15:0] dst; // dst bus
input we; // write enable
input hlt; // not a functional input. Used to dump register contents when
// test is halted.
output reg [15:0] p0,p1; //output read ports
integer indx;
reg [15:0]mem[0:15];
reg [3:0] dst_addr_lat; // have to capture dst_addr from previous cycle
reg [15:0] dst_lat; // have to capture write data from previous cycle
reg we_lat; // have to capture we from previous cycle
//////////////////////////////////////////////////////////
// Register file will come up uninitialized except for //
// register zero which is hardwired to be zero. //
///////////////////////////////////////////////////////
initial begin
mem[0] = 16'h0000; // reg0 is always 0,
end
//////////////////////////////////////////////////
// dst_addr, dst, & we all need to be latched //
// on clock low of previous cycle to maintain //
// in clock high write of next cycle. //
//////////////////////////////////////////////
always @(clk,dst_addr,dst,we)
if (~clk)
begin
dst_addr_lat <= dst_addr;
dst_lat <= dst;
we_lat <= we;
end
//////////////////////////////////
// RF is written on clock high //
////////////////////////////////
always @(clk,we_lat,dst_addr_lat,dst_lat)
if (clk && we_lat && |dst_addr_lat)
mem[dst_addr_lat] <= dst_lat;
//////////////////////////////
// RF is read on clock low //
////////////////////////////
always @(clk,re0,p0_addr)
if (~clk && re0)
p0 <= mem[p0_addr];
//////////////////////////////
// RF is read on clock low //
////////////////////////////
always @(clk,re1,p1_addr)
if (~clk && re1)
p1 <= mem[p1_addr];
////////////////////////////////////////
// Dump register contents at program //
// halt for debug purposes //
/////////////////////////////////////
always @(posedge hlt)
for(indx=1; indx<16; indx = indx+1)
$display("R%1h = %h",indx,mem[indx]);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dimm.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`timescale 1ps/1ps
// `define DIMM_DEB
//----------------------------------------------------------------------
// Functional DIMM model, Only Read/Write supported
//----------------------------------------------------------------------
module dimm(// inputs
clk, cs, ras, cas, we, ba, addr, cs_sel,
// inouts
dataq, ecc, dqs, dm_rdqs
);
parameter addr_width=17,
`ifdef DRAM_BANK_BITS2
bank_width=2,
`else
bank_width=3,
`endif
dqs_width=9;
// inputs
input [2:0] clk;
input [1:0] cs;
input ras, cas, we;
input [(bank_width-1):0] ba;
input [(addr_width-1):0] addr;
input [7:0] cs_sel;
// inouts
inout [63:0] dataq;
inout [7:0] ecc;
inout [(dqs_width-1):0] dqs, dm_rdqs;
// Local variables
integer datah, ecch; // Handles for memory model
parameter colm_width = 11;
parameter total_width = bank_width + addr_width + colm_width;
parameter bank_count = (1 << bank_width);
parameter depth = 31;
parameter dly = 400;
// wires
wire [3:0] ReadLat, ReadLat1, WriteLat;
// Registers
reg [(colm_width-1):0] ColAddr;
reg [63:0] dataq_out;
reg [63:0] dataq_d;
reg [7:0] ecc_out;
reg [7:0] ecc_d;
reg [depth:0] read_queue;
reg [depth:0] write_queue;
reg [3:0] AlignLat, BurstLen, CasLat;
reg [(total_width-1):0] rd_addr_queue [depth:0];
reg [(total_width-1):0] wr_addr_queue [depth:0];
reg [(addr_width-1):0] RowAddr [(bank_count-1):0];
reg [5:0] dv_cnt;
reg dataq_oe;
reg dqs_oe;
reg dqs_out;
// Delayed versions of the inputs
reg [1:0] cs_d;
reg ras_d, cas_d, we_d;
reg [(bank_width-1):0] ba_d;
reg [(addr_width-1):0] addr_d;
integer n;
//----------------------------------------------------------------------
// Drive outputs
//----------------------------------------------------------------------
assign dataq = (dataq_oe == 1'b1) ? dataq_out : {64{1'bz}};
assign ecc = (dataq_oe == 1'b1) ? ecc_out : {8{1'bz}};
assign dqs = (dqs_oe == 1'b1) ? {dqs_width{dqs_out}} : {dqs_width{1'bz}};
assign dm_rdqs = (dqs_oe == 1'b1) ? {dqs_width{dqs_out}} : {dqs_width{1'bz}};
//----------------------------------------------------------------------
// Model setup
//----------------------------------------------------------------------
initial
begin
if (!$value$plusargs("SYSTEM_DV_MATCH=%d", dv_cnt)) begin
dv_cnt = 2 ;
end
dv_cnt = dv_cnt-1;
end
`ifdef SYSTEM_DV_MATCH
assign ReadLat = AlignLat+CasLat+dv_cnt; // set DV_CNT = 2
assign ReadLat1= AlignLat+CasLat;
assign WriteLat = ReadLat1-1;
`else
assign ReadLat = AlignLat+CasLat;
assign WriteLat = ReadLat-1;
`endif
//----------------------------------------------------------------------
// Registered / Delayed versions of inputs
//----------------------------------------------------------------------
always @ (posedge clk[0])
begin
ba_d <= #dly ba;
addr_d <= #dly addr;
cs_d <= #dly cs;
ras_d <= #dly ras;
cas_d <= #dly cas;
we_d <= #dly we;
end
always @ (posedge dqs[0] or negedge dqs[0])
begin
dataq_d <= #dly dataq;
ecc_d <= #dly ecc;
end
//----------------------------------------------------------------------
// Positive edge clock
//----------------------------------------------------------------------
always @ (posedge clk[0])
begin
if ({cs_d[0], ras_d, cas_d, we_d} == 4'b0101) // Read
begin
`ifdef DIMM_DEB
$display("%d: %m dimm read addr %x",$time,addr_d);
`endif
ColAddr = {addr_d[colm_width:11],addr_d[9:0]};
for (n=0; n<BurstLen; n=n+1) begin
read_queue[2*ReadLat+n] <= #dly 1'b1;
rd_addr_queue[2*ReadLat+n] <= #dly {RowAddr[ba_d], ColAddr[10:2], ba_d,
ColAddr[1:0] + n[1:0]};
end
end
else if ({cs_d[0], ras_d, cas_d, we_d} == 4'b0100) // Write
begin
`ifdef DIMM_DEB
$display("%d: %m dimm write addr %x",$time,addr_d);
`endif
ColAddr = {addr_d[colm_width:11],addr_d[9:0]};
for (n=0; n<BurstLen; n=n+1) begin
write_queue[2*WriteLat+n+1] <= #dly 1'b1;
wr_addr_queue[2*WriteLat+n+1] <= #dly
{RowAddr[ba_d], ColAddr[10:2], ba_d, ColAddr[1:0] + n[1:0]};
end
end
else if ({cs_d[0], ras_d, cas_d, we_d} == 4'b0011) // RAS
begin
`ifdef DIMM_DEB
$display("%d: %m dimm act addr %x ba %x",$time,addr_d,ba_d);
`endif
RowAddr[ba_d] = addr_d;
end
else if ({cs_d[0], ras_d, cas_d, we_d} == 4'b0000) // Setup
begin
`ifdef DIMM_DEB
$display("%d: %m dimm Setup addr %x ba %x",$time,addr_d,ba_d);
`endif
if (ba_d == 0)
begin
BurstLen = (1 << addr_d[2:0]);
CasLat = addr_d[6:4];
`ifdef DIMM_DEB
$display("%d: %m dimm BurstLen %x CasLat %x",$time,BurstLen,CasLat);
`endif
end
else if (ba_d == 1)
begin
AlignLat = addr_d[5:3];
`ifdef DIMM_DEB
$display("%d: %m dimm AlignLat set %x",$time,AlignLat);
`endif
end
end
end // always
//----------------------------------------------------------------------
// Positive and Negative Edge for DDR
//----------------------------------------------------------------------
always @ (posedge clk[0] or negedge clk[0])
begin
for (n=0; n<depth; n=n+1)
begin
read_queue[n] = read_queue[n+1];
rd_addr_queue[n] = rd_addr_queue[n+1];
wr_addr_queue[n] = wr_addr_queue[n+1];
write_queue[n] = write_queue[n+1];
end
if (read_queue[2] == 1'b1) dqs_oe = 1'b1;
else if (read_queue[0] == 1'b0)
begin
dqs_out = 1'b0;
dqs_oe = 1'b0;
end
if (read_queue[0] == 1'b1)
begin
{ecc_out,dataq_out} = Read_mem(rd_addr_queue[0]);
dataq_oe = 1'b1;
dqs_out = ~dqs_out;
dqs_oe = 1'b1;
end else begin
dataq_oe = 1'b0;
end
if (write_queue[0] == 1'b1)
begin
Write_mem(wr_addr_queue[0],{ecc_d,dataq_d});
end
end
//----------------------------------------------------------------------
// Read function
//----------------------------------------------------------------------
function [71:0] Read_mem;
input [(total_width-1):0] faddr;
reg [71:0] data;
begin
$read_mem(datah, data[3:0], faddr, cs_sel);
$read_mem(datah+1, data[7:4], faddr, cs_sel);
$read_mem(datah+2, data[11:8], faddr, cs_sel);
$read_mem(datah+3, data[15:12], faddr, cs_sel);
$read_mem(datah+4, data[19:16], faddr, cs_sel);
$read_mem(datah+5, data[23:20], faddr, cs_sel);
$read_mem(datah+6, data[27:24], faddr, cs_sel);
$read_mem(datah+7, data[31:28], faddr, cs_sel);
$read_mem(datah+8, data[35:32], faddr, cs_sel);
$read_mem(datah+9, data[39:36], faddr, cs_sel);
$read_mem(datah+10, data[43:40], faddr, cs_sel);
$read_mem(datah+11, data[47:44], faddr, cs_sel);
$read_mem(datah+12, data[51:48], faddr, cs_sel);
$read_mem(datah+13, data[55:52], faddr, cs_sel);
$read_mem(datah+14, data[59:56], faddr, cs_sel);
$read_mem(datah+15, data[63:60], faddr, cs_sel);
$read_mem(ecch, data[67:64], faddr, cs_sel);
$read_mem(ecch+1, data[71:68], faddr, cs_sel);
Read_mem = data;
`ifdef DIMM_DEB
$display("%d: %m dimm Read_mem addr %x Data %x \n",$time,faddr,data);
`endif
end
endfunction
//----------------------------------------------------------------------
// Write task
//----------------------------------------------------------------------
task Write_mem;
input [(total_width-1):0] faddr;
input [71:0] data;
begin
$write_mem(datah, data[3:0], faddr, cs_sel);
$write_mem(datah+1, data[7:4], faddr, cs_sel);
$write_mem(datah+2, data[11:8], faddr, cs_sel);
$write_mem(datah+3, data[15:12], faddr, cs_sel);
$write_mem(datah+4, data[19:16], faddr, cs_sel);
$write_mem(datah+5, data[23:20], faddr, cs_sel);
$write_mem(datah+6, data[27:24], faddr, cs_sel);
$write_mem(datah+7, data[31:28], faddr, cs_sel);
$write_mem(datah+8, data[35:32], faddr, cs_sel);
$write_mem(datah+9, data[39:36], faddr, cs_sel);
$write_mem(datah+10, data[43:40], faddr, cs_sel);
$write_mem(datah+11, data[47:44], faddr, cs_sel);
$write_mem(datah+12, data[51:48], faddr, cs_sel);
$write_mem(datah+13, data[55:52], faddr, cs_sel);
$write_mem(datah+14, data[59:56], faddr, cs_sel);
$write_mem(datah+15, data[63:60], faddr, cs_sel);
$write_mem(ecch, data[67:64], faddr, cs_sel);
$write_mem(ecch+1, data[71:68], faddr, cs_sel);
`ifdef DIMM_DEB
$display("%d: %m dimm Write_mem addr %x Data %x \n",$time,faddr,data);
`endif
end
endtask
//----------------------------------------------------------------------
// Initialization
//----------------------------------------------------------------------
initial begin
dataq_oe = 0;
dqs_oe = 0;
dqs_out = 1'b0;
dataq_out = 64'b0;
ecc_out = 8'b0;
for (n=0; n<depth; n=n+1)
begin
read_queue[n] = 1'b0;
rd_addr_queue[n] = {total_width{1'b0}};
wr_addr_queue[n] = {total_width{1'b0}};
write_queue[n] = 1'b0;
end
end
//----------------------------------------------------------------------
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXBP_BLACKBOX_V
`define SKY130_FD_SC_HD__SDFXBP_BLACKBOX_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXBP_BLACKBOX_V
|
// This module compares two bitstreams and automatically determines their
// offset. This is done by iteratively changing bit delay for I_DAT_REF
// every time the number of errors exceeds ERROR_COUNT. The output O_ERROR
// signal is high for at least ERROR_HOLD cycles.
`default_nettype none
// ============================================================================
module comparator #
(
parameter ERROR_COUNT = 8,
parameter ERROR_HOLD = 2500000
)
(
input wire CLK,
input wire RST,
input wire I_DAT_REF,
input wire I_DAT_IOB,
output wire O_ERROR
);
// ============================================================================
// Data latch
reg [2:0] i_dat_ref_sr;
reg [2:0] i_dat_iob_sr;
always @(posedge CLK)
i_dat_ref_sr <= (i_dat_ref_sr << 1) | I_DAT_REF;
always @(posedge CLK)
i_dat_iob_sr <= (i_dat_iob_sr << 1) | I_DAT_IOB;
wire i_dat_ref = i_dat_ref_sr[2];
wire i_dat_iob = i_dat_iob_sr[2];
// ============================================================================
// Shift register for reference data, shift strobe generator.
reg [31:0] sreg;
reg [ 4:0] sreg_sel;
wire sreg_dat;
reg sreg_sh;
always @(posedge CLK)
sreg <= (sreg << 1) | i_dat_ref;
always @(posedge CLK)
if (RST)
sreg_sel <= 0;
else if(sreg_sh)
sreg_sel <= sreg_sel + 1;
assign sreg_dat = sreg[sreg_sel];
// ============================================================================
// Comparator and error counter
wire cmp_err;
reg [31:0] err_cnt;
assign cmp_err = sreg_dat ^ i_dat_iob;
always @(posedge CLK)
if (RST)
err_cnt <= 0;
else if(sreg_sh)
err_cnt <= 0;
else if(cmp_err)
err_cnt <= err_cnt + 1;
always @(posedge CLK)
if (RST)
sreg_sh <= 0;
else if(~sreg_sh && (err_cnt == ERROR_COUNT))
sreg_sh <= 1;
else
sreg_sh <= 0;
// ============================================================================
// Output generator
reg [24:0] o_cnt;
always @(posedge CLK)
if (RST)
o_cnt <= -1;
else if (cmp_err)
o_cnt <= ERROR_HOLD - 2;
else if (~o_cnt[24])
o_cnt <= o_cnt - 1;
assign O_ERROR = !o_cnt[24];
endmodule
|
module cache(clk,rst_n,addr,wr_data,wdirty,we,re,rd_data,tag_out,hit,dirty);
input clk,rst_n;
input [13:0] addr; // address to be read or written, 2-LSB's are dropped
input [63:0] wr_data; // 64-bit cache line to write
input wdirty; // dirty bit to be written
input we; // write enable for cache line
input re; // read enable (for power purposes only)
output hit;
output dirty;
output [63:0] rd_data; // 64-bit/4word cache line read out
output [10:0] tag_out; // 8-bit tag. This is needed during evictions
reg [76:0] mem[0:7]; // {valid,dirty,tag[10:0],wdata[63:0]}
reg [3:0] x;
reg [76:0] line;
reg we_del;
wire we_filt;
//////////////////////////
// Glitch filter on we //
////////////////////////
always @(we)
we_del <= we;
assign we_filt = we & we_del;
///////////////////////////////////////////////////////
// Model cache write, including reset of valid bits //
/////////////////////////////////////////////////////
always @(clk or we_filt or negedge rst_n)
if (!rst_n)
for (x=0; x<8; x = x + 1)
mem[x] = {2'b00,{75{1'bx}}}; // only valid & dirty bit are cleared, all others are x
else if (~clk && we_filt)
mem[addr[2:0]] = {1'b1,wdirty,addr[13:3],wr_data};
////////////////////////////////////////////////////////////
// Model cache read including 4:1 muxing of 16-bit words //
//////////////////////////////////////////////////////////
always @(clk or re or addr)
if (clk && re) // read is on clock high
line = mem[addr[2:0]];
/////////////////////////////////////////////////////////////
// If tag bits match and line is valid then we have a hit //
///////////////////////////////////////////////////////////
assign hit = ((line[74:64]==addr[13:3]) && (re | we)) ? line[76] : 1'b0;
assign dirty = line[76]&line[75]; // if line is valid and dirty bit set
assign rd_data = line[63:0];
assign tag_out = line[74:64]; // need the tag for evictions
endmodule
|
//move some stuff to minitests/ncy0
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [255:0] din, output [255:0] dout);
parameter N=3;
//ok
clb_NOUTMUX_CY #(.LOC("SLICE_X18Y100"), .N(N))
clb_NOUTMUX_CY (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
//ok
generate
if (N != 3) begin
clb_NOUTMUX_F78 #(.LOC("SLICE_X18Y101"), .N(N))
clb_NOUTMUX_F78 (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
end
endgenerate
//ok
clb_NOUTMUX_O5 #(.LOC("SLICE_X18Y102"), .N(N))
clb_NOUTMUX_O5 (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
//clb_NOUTMUX_O6 #(.LOC("SLICE_X18Y103"), .N(N))
// clb_NOUTMUX_O6 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8]));
//FIXME
clb_NOUTMUX_XOR #(.LOC("SLICE_X18Y104"), .N(N))
clb_NOUTMUX_XOR (.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8 ]));
//ok
clb_NOUTMUX_B5Q #(.LOC("SLICE_X18Y105"), .N(N))
clb_NOUTMUX_B5Q (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8 ]));
endmodule
module myLUT8 (input clk, input [7:0] din,
output lut8o, output lut7bo, output lut7ao,
//caro: XOR additional result (main output)
//carco: CLA result (carry module additional output)
output caro, output carco,
output bo5, output bo6,
//Note: b5ff_q requires the mux and will conflict with other wires
//Otherwise this FF drops out
output wire ff_q);
//output wire [3:0] n5ff_q);
parameter N=-1;
parameter LOC="SLICE_FIXME";
wire [3:0] caro_all;
assign caro = caro_all[N];
wire [3:0] carco_all;
assign carco = carco_all[N];
wire [3:0] lutno6;
assign bo6 = lutno6[N];
wire [3:0] lutno5;
assign bo5 = lutno5[N];
//Outputs does not have to be used, will stay without it
(* LOC=LOC, BEL="F8MUX", KEEP, DONT_TOUCH *)
MUXF8 mux8 (.O(lut8o), .I0(lut7bo), .I1(lut7ao), .S(din[6]));
(* LOC=LOC, BEL="F7BMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7b (.O(lut7bo), .I0(lutno6[3]), .I1(lutno6[2]), .S(din[6]));
(* LOC=LOC, BEL="F7AMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7a (.O(lut7ao), .I0(lutno6[1]), .I1(lutno6[0]), .S(din[6]));
(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_DEAD_0000_0001)
) lutd (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutno5[3]),
.O6(lutno6[3]));
(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_BEEF_0000_0001)
) lutc (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutno5[2]),
.O6(lutno6[2]));
(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_CAFE_0000_0001)
) lutb (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutno5[1]),
.O6(lutno6[1]));
(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_1CE0_0000_0001)
) luta (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutno5[0]),
.O6(lutno6[0]));
//Outputs do not have to be used, will stay without them
(* LOC=LOC, KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(caro_all), .CO(carco_all), .DI(lutno5), .S(lutno6), .CYINIT(1'b0), .CI());
generate
if (N == 3) begin
(* LOC=LOC, BEL="D5FF", KEEP, DONT_TOUCH *)
FDPE d5ff (
.C(clk),
.Q(ff_q),
.CE(1'b1),
.PRE(1'b0),
.D(lutno5[3]));
end
if (N == 2) begin
(* LOC=LOC, BEL="C5FF", KEEP, DONT_TOUCH *)
FDPE c5ff (
.C(clk),
.Q(ff_q),
.CE(1'b1),
.PRE(1'b0),
.D(lutno5[2]));
end
if (N == 1) begin
(* LOC=LOC, BEL="B5FF", KEEP, DONT_TOUCH *)
FDPE b5ff (
.C(clk),
.Q(ff_q),
.CE(1'b1),
.PRE(1'b0),
.D(lutno5[1]));
end
if (N == 0) begin
(* LOC=LOC, BEL="A5FF", KEEP, DONT_TOUCH *)
FDPE a5ff (
.C(clk),
.Q(ff_q),
.CE(1'b1),
.PRE(1'b0),
.D(lutno5[0]));
end
endgenerate
endmodule
//******************************************************************************
//BOUTMUX tests
module clb_NOUTMUX_CY (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
parameter N=1;
myLUT8 #(.LOC(LOC), .N(N))
myLUT8(.clk(clk), .din(din), .lut8o(),
.caro(), .carco(dout[0]),
.bo5(), .bo6(),
.ff_q());
endmodule
//clb_NOUTMUX_F78: already have above as clb_LUT8
module clb_NOUTMUX_F78 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
parameter N=1;
wire lut8o, lut7bo, lut7ao;
/*
D: N/A (no such mux position)
C: F7B:O
B: F8:O
A: F7A:O
*/
generate
if (N == 3) begin
//No muxes, so this is undefined
invalid_configuration invalid_configuration3();
end else if (N == 2) begin
assign dout[0] = lut7bo;
end else if (N == 1) begin
assign dout[0] = lut8o;
end else if (N == 0) begin
assign dout[0] = lut7ao;
end
endgenerate
myLUT8 #(.LOC(LOC), .N(N))
myLUT8(.clk(clk), .din(din),
.lut8o(lut8o), .lut7bo(lut7bo), .lut7ao(lut7ao),
.caro(), .carco(),
.bo5(), .bo6(),
.ff_q());
endmodule
module clb_NOUTMUX_O5 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
parameter N=1;
myLUT8 #(.LOC(LOC), .N(N))
myLUT8(.clk(clk), .din(din), .lut8o(),
.caro(), .carco(),
.bo5(dout[0]), .bo6(),
.ff_q());
endmodule
/*
//FIXME: need to force it to use both X and O6
module clb_NOUTMUX_O6 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
parameter N=1;
myLUT8 #(.LOC(LOC), .N(N))
myLUT8(.clk(clk), .din(din), .lut8o(), .co(), .carco(), .bo5(), .bo6());
endmodule
*/
module clb_NOUTMUX_XOR (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
parameter N=1;
myLUT8 #(.LOC(LOC), .N(N))
myLUT8(.clk(clk), .din(din), .lut8o(),
.caro(dout[0]), .carco(),
.bo5(), .bo6(),
.ff_q());
endmodule
module clb_NOUTMUX_B5Q (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
parameter N=1;
myLUT8 #(.LOC(LOC), .N(N))
myLUT8(.clk(clk), .din(din),
.lut8o(),
.caro(), .carco(),
.bo5(), .bo6(),
.ff_q(dout[0]));
endmodule
|
(** * Smallstep: Small-step Operational Semantics *)
(* $Date: 2012-07-25 16:43:16 -0400 (Wed, 25 Jul 2012) $ *)
Require Export Ch07_Imp.
(** The evaluators we have seen so far (e.g., the ones for [aexp]s,
[bexp]s, and commands) have been formulated in a "big-step"
style -- they specify how a given expression can be evaluated to
its final value (or a command plus a store to a final store) "all
in one big step."
This style is simple and natural for many purposes (indeed, Gilles
Kahn, who popularized its use, called it _natural semantics_), but
there are some things it does not do well. In particular, it
does not give us a natural way of talking about _concurrent_
programming languages, where the "semantics" of a program -- i.e.,
the essence of how it behaves -- is not just which input states
get mapped to which output states, but also includes the
intermediate states that it passes through along the way, since
these states can also be observed by concurrently executing code.
Another shortcoming of the big-step style is more technical, but
critical for some applications. Consider the variant of Imp with
lists that we introduced in ImpList.v. We chose to define the
meaning of programs like [0 + nil] by specifying that a list
should be interpreted as [0] when it occurs in a context expecting
a number, but this was a bit of a hack. It would be better simply
to say that the behavior of such a program is _undefined_ -- it
doesn't evaluate to any result. We could easily do this: we'd
just have to use the formulations of [aeval] and [beval] as
inductive propositions (rather than Fixpoints), so that we can
make them partial functions instead of total ones.
However, this way of defining Imp has a serious deficiency. In
this language, a command might _fail_ to map a given starting
state to any ending state for two quite different reasons: either
because the execution gets into an infinite loop or because, at
some point, the program tries to do an operation that makes no
sense, such as taking the successor of a boolean variable, and
none of the evaluation rules can be applied.
These two outcomes -- nontermination vs. getting stuck in an
erroneous configuration -- are quite different. In particular, we
want to allow the first (permitting the possibility of infinite
loops is the price we pay for the convenience of programming with
general looping constructs like [while]) but prevent the
second (which is just wrong), for example by adding some form of
_typechecking_ to the language. Indeed, this will be a major
topic for the rest of the course. As a first step, we need a
different way of presenting the semantics that allows us to
distinguish nontermination from erroneous "stuck states."
So, for lots of reasons, we'd like to have a finer-grained way of
defining and reasoning about program behaviors. This is the topic
of the present chapter. We replace the "big-step" [eval] relation
with a "small-step" relation that specifies, for a given program,
how the "atomic steps" of computation are performed. *)
(* ########################################################### *)
(** * Relations *)
(** A _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Our main examples of such relations in this chapter will be
the single-step and multi-step reduction relations on terms, [==>]
and [==>*], but there are many other examples -- some that come to
mind are the "equals," "less than," "less than or equal to," and
"is the square of" relations on numbers, and the "prefix of"
relation on lists and strings.
The optional [Rel] chapter tells a more detailed story about how
relations are treated in Coq. *)
(* ########################################################### *)
(** * A Toy Language *)
(** To save space in the discussion, let's go back to an
incredibly simple language containing just constants and
addition. (We use single letters -- [C] and [P] -- for the
constructor names, for brevity.) At the end of the chapter, we'll
see how to apply the same techniques to the full Imp language. *)
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P" ].
Module SimpleArith0.
(** Here is a standard evaluator for this language, written in the
same (big-step) style as we've been using up to this point. *)
Fixpoint eval (t : tm) : nat :=
match t with
| C n => n
| P a1 a2 => eval a1 + eval a2
end.
End SimpleArith0.
(** Now, here is the same evaluator, written in exactly the same
style, but formulated as an inductively defined relation. Again,
we use the notation [t || n] for "[t] evaluates to [n]." *)
(**
-------- (E_Const)
C n || n
t1 || n1
t2 || n2
---------------------- (E_Plus)
P t1 t2 || C (n1 + n2)
*)
Reserved Notation " t '||' n " (at level 50, left associativity).
Inductive my_eval: tm -> nat -> Prop:=
| e_const:forall n, my_eval (C n) n
| e_plus:forall t1 t2 n1 n2,
my_eval t1 n1 ->
my_eval t2 n2 ->
my_eval (P t1 t2) (n1+n2)
.
Inductive eval : tm -> nat -> Prop :=
| E_Const : forall n,
C n || n
| E_Plus : forall t1 t2 n1 n2,
t1 || n1 ->
t2 || n2 ->
P t1 t2 || (n1 + n2)
where " t '||' n " := (eval t n).
Tactic Notation "eval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Const" | Case_aux c "E_Plus" ].
Module SimpleArith1.
(** Now, here is a small-step version. *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
t2 ==> t2'
--------------------------- (ST_Plus2)
P (C n1) t2 ==> P (C n1) t2'
*)
Inductive my_step: tm -> tm -> Prop:=
|st_plusconstconst:forall n1 n2,
my_step (P (C n1)(C n2)) (C (n1+n2))
|st_plus1:forall t1 t1' t2,
my_step t1 t1' ->
my_step (P t1 t2) (P t1' t2)
|st_plus2:forall n1 t2 t2',
my_step t2 t2' ->
my_step (P (C n1) t2) (P (C n1) t2')
.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall n1 t2 t2',
t2 ==> t2' ->
P (C n1) t2 ==> P (C n1) t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(**
Note that, there are following differences between "small step" and "big step",
1. In [my_step], a constant cannot be further reduced to a natural number while
it is the case in [my_eval]
2. In [my_eval], [my_eval (P t1 t2) (n1+n2)],from [P t1 t2] to [n1+n2] involves
multiple steps of evaluation of both t1 and t2 according to the two constructors
while in [my_step], a step is clearly defined as replacing [P (C n1)(C n2)]
with [C (n1+n2)] whenever possible from left to right of the related expression
until it is reduced to a constant.
*)
(** Things to notice:
- We are defining just a single reduction step, in which
one [P] node is replaced by its value.
- Each step finds the _leftmost_ [P] node that is ready to
go (both of its operands are constants) and rewrites it in
place. The first rule tells how to rewrite this [P] node
itself; the other two rules tell how to find it.
- A term that is just a constant cannot take a step. *)
(** A couple of examples of reasoning with the [step]
relation... *)
(** If [t1] can take a step to [t1'], then [P t1 t2] steps
to [plus t1' t2]: *)
Example test_step_1 :
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>
P
(C (0 + 3))
(P (C 2) (C 4)).
Proof.
apply ST_Plus1. apply ST_PlusConstConst. Qed.
(** **** Exercise: 2 stars (test_step_2) *)
(* EXPECTED *)
(** Right-hand sides of sums can take a step only when the
left-hand side is finished: if [t2] can take a step to [t2'],
then [P (C n) t2] steps to [P (C n)
t2']: *)
Example test_step_2 :
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>
P
(C 0)
(P
(C 2)
(C (0 + 3))).
Proof.
apply ST_Plus2. apply ST_Plus2. apply ST_PlusConstConst.
Qed.
(** [] *)
(** One simple property of the [==>] relation is that, like the
evaluation relation for our language of Imp programs, it is
_deterministic_.
_Theorem_: For each [t], there is at most one [t'] such that [t]
steps to [t'] ([t ==> t'] is provable). Formally, this is the
same as saying that [==>] is deterministic.
_Proof sketch_: We show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal, by induction on a derivation of
[step x y1]. There are several cases to consider, depending on
the last rule used in this derivation and in the given derivation
of [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) _and_ one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] has both the form [P t1 t2] and
the form [C n]. [] *)
Definition deterministic {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
Theorem my_step_deterministic:
deterministic my_step.
Proof.
unfold deterministic. intros. generalize dependent y2.
induction H.
Case ("1"). intros. inversion H0. subst. reflexivity.
subst. inversion H3. subst. inversion H3.
Case ("2"). intros. inversion H0. subst. inversion H.
subst. apply IHmy_step in H4. subst. reflexivity.
subst. inversion H.
Case ("3"). intros. inversion H0. subst. inversion H. subst.
inversion H4. subst. apply IHmy_step in H4. subst.
reflexivity.
Qed.
Theorem my_step_deterministic':
deterministic step.
Proof.
unfold deterministic. intros. generalize dependent y2.
induction H.
Case ("1"). intros. inversion H0;subst;try inversion H3;try reflexivity.
Case ("2"). intros. inversion H0.
SCase ("2_1"). subst. inversion H.
SCase ("2_2"). subst. apply IHstep in H4. subst. reflexivity.
SCase ("2_3"). subst. inversion H.
Case ("3"). intros. inversion H0.
SCase ("3_1"). subst. inversion H.
SCase ("3_2"). subst. inversion H4.
SCase ("3_3"). subst. apply IHstep in H4. subst. reflexivity.
Qed.
Theorem step_deterministic:
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2.
Case "ST_PlusConstConst". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". reflexivity.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2". inversion H2.
Case "ST_Plus1". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H0 in Hy1. inversion Hy1.
SCase "ST_Plus1".
rewrite <- (IHHy1 t1'0).
reflexivity. assumption.
SCase "ST_Plus2". rewrite <- H in Hy1. inversion Hy1.
Case "ST_Plus2". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H1 in Hy1. inversion Hy1.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2".
rewrite <- (IHHy1 t2'0).
reflexivity. assumption. Qed.
End SimpleArith1.
(* ########################################################### *)
(** ** Values *)
(** Let's take a moment to slightly generalize the way we state the
definition of single-step reduction. *)
(** It is useful to think of the [==>] relation as defining an
_abstract machine_:
- At any moment, the _state_ of the machine is a term.
- A _step_ of the machine is an atomic unit of computation --
here, a single "add" operation(note: from one term to another).
- The _halting states_ of the machine are ones where there is no
more computation to be done.
We can then execute a term [t] as follows:
- Take [t] as the starting state of the machine.
- Repeatedly use the [==>] relation to find a sequence of
machine states, starting with [t], where each state steps to
the next.
- When no more reduction is possible, "read out" the final state
of the machine as the result of execution. *)
(** Intuitively, it is clear that the final states of the
machine are always terms of the form [C n] for some [n].
We call such terms _values_. *)
Inductive value : tm -> Prop :=
v_const : forall n, value (C n).
(** Having introduced the idea of values, we can use it in the
definition of the [==>] relation to write [ST_Plus2] rule in a
slightly more elegant way: *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
value v1
t2 ==> t2'
-------------------- (ST_Plus2)
P v1 t2 ==> P v1 t2'
*)
(** Again, the variable names here carry important information:
by convention, [v1] ranges only over values, while [t1] and [t2]
range over arbitrary terms. (Given this convention, the explicit
[value] hypothesis is arguably redundant. We'll keep it for now,
to maintain a close correspondence between the informal and Coq
versions of the rules, but later on we'll drop it in informal
rules, for the sake of brevity.) *)
Inductive my_step: tm -> tm -> Prop:=
| st_plusconstconst:forall n1 n2,
my_step (P (C n1)(C n2)) (C (n1+n2))
| st_plus1:forall t1 t1' t2,
my_step t1 t1' ->
my_step (P t1 t2)(P t1' t2)
| st_plus2:forall v1 t2 t2',
value v1 ->
my_step t2 t2' ->
my_step (P v1 t2)(P v1 t2')
.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2)
==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 -> (* <----- n.b. *)
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** **** Exercise: 3 stars, recommended (redo_determinism) *)
(** As a sanity check on this change, let's re-verify determinism
Proof sketch: We must show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal. Consider the final rules used in
the derivations of [step x y1] and [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) AND one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] both has the form [P t1 t2] and
is a value (hence has the form [C n]).
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis. [] *)
(** Most of this proof is the same as the one above. But to get
maximum benefit from the exercise you should try to write it from
scratch and just use the earlier one if you get stuck. *)
(** **** Exercise: 2 stars, optional (step_deterministic) *)
(* EXPECTED *)
Theorem my_step_deterministic:
deterministic my_step.
Proof.
unfold deterministic. intros. generalize dependent y2.
induction H.
Case ("1"). intros. inversion H0. subst. reflexivity.
subst. inversion H3. subst. inversion H4.
Case ("2"). intros. inversion H0. subst. inversion H.
subst. apply IHmy_step in H4. subst. reflexivity.
subst. inversion H3. subst. inversion H.
Case ("3"). intros. inversion H1. subst. inversion H0.
subst. inversion H. subst. inversion H5.
subst. apply IHmy_step in H6. subst.
reflexivity.
Qed.
Theorem my_step_deterministic':
deterministic step.
Proof.
unfold deterministic. intros. generalize dependent y2.
induction H.
Case ("st_plusconstconst"). intros. inversion H0.
SCase ("st_plusconstconst"). subst. reflexivity.
SCase ("st_plus1"). subst. inversion H3.
SCase ("st_plus2"). subst. inversion H4.
Case ("st_plus1"). intros. inversion H0.
SCase ("st_plusconstconst"). subst. inversion H.
SCase ("plus1"). subst. apply IHstep in H4. subst.
reflexivity.
SCase ("plus2"). subst. inversion H3. subst. inversion H.
Case ("st_plus2"). intros. inversion H1.
SCase ("st_plusconstconst"). subst. inversion H0.
SCase ("st_plus1"). subst. inversion H. subst. inversion H5.
SCase ("st_plus2"). subst. apply IHstep in H6. subst. reflexivity.
Qed.
Theorem step_deterministic :
deterministic step.
Proof.
unfold deterministic. intros. generalize dependent y2. induction H.
Case ("ST_PlusConstConst"). intros. inversion H0. subst. reflexivity.
subst. inversion H3. inversion H3. inversion H4.
Case ("ST_Plus1"). intros. inversion H0. subst. inversion H. subst.
apply IHstep in H4. subst. reflexivity. subst.
inversion H. subst. inversion H3. subst. inversion H3.
subst. inversion H3.
Case ("ST_Plus2"). intros. inversion H1. subst. inversion H0. subst.
inversion H5. subst. inversion H. subst. inversion H.
subst. inversion H. subst. apply IHstep in H6. subst.
reflexivity.
Qed.
(** [] *)
(* ########################################################### *)
(** ** Strong Progress and Normal Forms *)
(** The definition of single-step reduction for our toy language is
fairly simple, but for a larger language it would be pretty easy
to forget one of the rules and create a situation where some term
cannot take a step even though it has not been completely reduced
to a value. The following theorem shows that we did not, in fact,
make such a mistake here. *)
(** _Theorem_ (_Strong Progress_): For all [t:tm], either [t] is a
value, or there exists a term [t'] such that [t ==> t'].
_Proof_: By induction on [t].
- Suppose [t = C n]. Then [t] is a [value].
- Suppose [t = P t1 t2], where (by the IH) [t1] is either a
value or can step to some [t1'], and where [t2] is either a
value or can step to some [t2']. We must show [P t1 t2] is
either a value or steps to some [t'].
- If [t1] and [t2] are both values, then [t] can take a step, by
[ST_PlusConstConst].
- If [t1] is a value and [t2] can take a step, then so can [t],
by [ST_Plus2].
- If [t1] can take a step, then so can [t], by [ST_Plus1]. [] *)
Theorem my_strong_progress:forall t,
value t \/ (exists t', my_step t t').
Proof.
intros t. induction t.
Case ("C"). left. apply v_const.
Case ("P"). inversion IHt1.
SCase ("P_1"). inversion IHt2. inversion H. inversion H0. subst.
right. exists (C (n+n0)). apply st_plusconstconst.
inversion H. subst. inversion H0. subst. right.
exists (P (C n) x). apply st_plus2. apply H. apply H1.
SCase ("P_2"). inversion H. subst. right. exists (P x t2). apply st_plus1.
apply H0.
Qed.
Theorem my_strong_progress': forall t,
value t \/ (exists t', t ==> t').
Proof.
intros. induction t.
Case ("C n"). left. apply v_const.
Case ("P"). right. inversion IHt1. inversion IHt2.
SCase ("1"). inversion H. inversion H0. exists (C (n+n0)).
apply ST_PlusConstConst.
SCase ("2"). inversion H. inversion H0. exists (P (C n) x).
apply ST_Plus2. rewrite<-H1 in H. apply H. apply H2.
SCase ("3"). inversion H. exists (P x t2). apply ST_Plus1.
apply H0.
Qed.
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
tm_cases (induction t) Case.
Case "C". left. apply v_const.
Case "P". right. inversion IHt1.
SCase "l". inversion IHt2.
SSCase "l". inversion H. inversion H0.
exists (C (n + n0)).
apply ST_PlusConstConst.
SSCase "r". inversion H0 as [t' H1].
exists (P t1 t').
apply ST_Plus2. apply H. apply H1.
SCase "r". inversion H as [t' H0].
exists (P t' t2).
apply ST_Plus1. apply H0. Qed.
(** This important property is called _strong progress_, because
every term either is a value or can "make progress" by stepping to
some other term. (The qualifier "strong" distinguishes it from a
more refined version that we'll see in later chapters, called
simply "progress.") *)
(** The idea of "making progress" can be extended to tell us something
interesting about [value]s: in this language [value]s are exactly
the terms that _cannot_ make progress in this sense. To state
this fact, let's begin by giving a name to terms that cannot make
progress: We'll call them _normal forms_. *)
(**
Note the quantifier "in this language" above,
It is possible that in some other language, there are terms that are
both value and make some progress. For [strong progress] does not rule out
the possibility that both [value t] and [exists t', t==>t'] are true.
*)
Definition normal_form {X:Type} (R:relation X) (t:X) : Prop :=
~ exists t', R t t'.
(** This definition actually specifies what it is to be a normal form
for an _arbitrary_ relation [R] over an arbitrary set [X], not
just for the particular single-step reduction relation over terms
that we are interested in at the moment. We'll re-use the same
terminology for talking about other relations later in the
course. *)
(** We can use this terminology to generalize the observation we made
in the strong progress theorem: in this language, normal forms and
values are actually the same thing. *)
Lemma my_nf_same_as_value:forall t,
value t<->normal_form my_step t.
Proof.
split.
Case ("->"). intros. inversion H. subst. unfold normal_form.
intros contra. inversion contra. subst. inversion H0.
Case ("<-"). unfold normal_form. intros.
assert (A: value t \/ exists t':tm, my_step t t').
apply my_strong_progress. inversion A. apply H0.
apply H in H0. inversion H0.
Qed.
(**
Note that there are two points worth noticing,
1. [my_nf_same_as_value] is more restrictive than [my_strong_progress]:
the "<-" direction of [my_nf_same_as_value] is equivalent to [my_strong_progress]
while "->" direction of it rules out the possiblity that once a term is reduced
to a value, it can be further reduced.
2. How to prove the following Lemma,
[forall t1 t2, exists t':tm, my_step (P t1 t2) t'].
*)
Lemma my_nf_same_as_value':forall t,
value t<->normal_form step t.
Proof.
intros. split.
Case ("->"). intros. inversion H. intros contra. inversion contra.
inversion H1.
Case ("<-"). unfold normal_form. intros.
assert (A:value t \/ (exists t', t ==> t')). apply my_strong_progress'.
inversion A. apply H0. apply H in H0. inversion H0.
Qed.
Lemma value_is_nf : forall t,
value t -> normal_form step t.
Proof.
unfold normal_form. intros t H. inversion H.
intros contra. inversion contra. inversion H1.
Qed.
Lemma nf_is_value : forall t,
normal_form step t -> value t.
Proof. (* a corollary of [strong_progress]... *)
unfold normal_form. intros t H.
assert (G : value t \/ exists t', t ==> t').
SCase "Proof of assertion". apply strong_progress.
inversion G.
SCase "l". apply H0.
SCase "r". apply ex_falso_quodlibet. apply H. assumption. Qed.
Corollary nf_same_as_value : forall t,
normal_form step t <-> value t.
Proof.
split. apply nf_is_value. apply value_is_nf. Qed.
(** Why is this interesting? For two reasons:
- Because [value] is a syntactic concept -- it is a defined by
looking at the form of a term -- while [normal_form] is a
semantic one -- it is defined by looking at how the term steps.
It is not obvious that these concepts should coincide!
- Indeed, there are lots of languages in which the concepts of
normal form and value do _not_ coincide. *)
(**
Note that for having this conincidence, two features are required,
1. As long as the term is not a value it can be further reduced, hence
ruling out cases where the transition system gets stuck.
2. Once a term is reduced to a value, it can no longer be further reduced.
*)
(** Let's examine how this can happen... *)
(* ##################################################### *)
(** We might, for example, mistakenly define [value] so that it
includes some terms that are not finished reducing. *)
(*Violation of feature two*)
Module Temp1.
(* Open an inner module so we can redefine value and step. *)
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_funny : forall t1 n2, (* <---- *)
value (P t1 (C n2)).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 3 stars, optional (value_not_same_as_normal_form) *)
(* EXPECTED *)
Lemma value_not_same_as_normal_form:
exists t, value t /\ ~normal_form my_step t.
Proof.
exists (P (C 1)(C 1)). split.
apply v_funny. intros contra. apply contra.
exists (C 2). apply st_plusconstconst.
Qed.
Lemma value_not_same_as_normal_form' :
exists t, value t /\ ~ normal_form step t.
Proof.
exists (P (P (C 1)(C 1))(C 1)). split.
apply v_funny. intros contra. apply contra.
exists (P (C 2)(C 1)). apply ST_Plus1. apply ST_PlusConstConst.
Qed.
(** [] *)
End Temp1.
(* ########################################################### *)
(** Alternatively, we might mistakenly define [step] so that it
permits something designated as a value to reduce further. *)
(*Violation of feature 2*)
Module Temp2.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_Funny : forall n, (* <---- *)
C n ==> P (C n) (C 0)
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 2 stars, optional (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form:
exists t, value t /\ ~normal_form step t.
Proof.
exists (C 0). split.
apply v_const. intros contra. apply contra.
exists (P (C 0)(C 0)). apply ST_Funny.
Qed.
Lemma value_not_same_as_normal_form' :
exists t, value t /\ ~ normal_form step t.
Proof.
exists (C 1). split.
apply v_const. intros contra. apply contra.
exists (P (C 1)(C 0)). apply ST_Funny.
Qed.
(** [] *)
End Temp2.
(* ########################################################### *)
(** Finally, we might define [value] and [step] so that there is some
term that is not a value but that cannot take a step in the [step]
relation. Such terms are said to be _stuck_. In this case this is
caused by a mistake in the semantics, but we will also see
situations where, evne in a correct language definition, it makes
sense to allow some terms to be stuck. *)
(*Violation of feature 1*)
Module Temp3.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
where " t '==>' t' " := (step t t').
(** (Note that [ST_Plus2] is missing.) *)
(** **** Exercise: 3 stars (value_not_same_as_normal_form') *)
Lemma value_not_same_as_normal_form :
exists t, ~ value t /\ normal_form step t.
Proof.
exists (P (C 0) (P (C 0)(C 0))). split.
intros contra. inversion contra. intros contra.
inversion contra. inversion H. subst. inversion H3.
Qed.
(** [] *)
End Temp3.
(* ########################################################### *)
(** *** Additional Exercises *)
Module Temp4.
(** Here is another very simple language whose terms, instead of being
just plus and numbers, are just the booleans true and false and a
conditional expression... *)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_true : value ttrue
| v_false : value tfalse.
Inductive my_step: tm->tm->Prop:=
| st_iftrue:forall t1 t2,
my_step (tif ttrue t1 t2) t1
| st_iffalse:forall t1 t2,
my_step (tif tfalse t1 t2) t2
| st_if:forall t1 t1' t2 t3,
my_step t1 t1' ->
my_step (tif t1 t2 t3)(tif t1' t2 t3)
.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
(** **** Exercise: 1 star (smallstep_bools) *)
(** Which of the following propositions are provable? (This is just a
thought exercise, but for an extra challenge feel free to prove
your answers in Coq.) *)
Definition bool_step_prop1 :=
tfalse ==> tfalse.
Example my_bool_step_prop1:
~(my_step tfalse tfalse).
Proof.
intros contra. inversion contra. Qed.
Example my_bool_step_prop1':
~(tfalse ==> tfalse).
Proof. intros contra. inversion contra. Qed.
Definition bool_step_prop2 :=
tif
ttrue
(tif ttrue ttrue ttrue)
(tif tfalse tfalse tfalse)
==>
ttrue.
Example my_bool_step_prop3:
~(my_step (tif
ttrue
(tif ttrue ttrue ttrue)
(tif tfalse tfalse tfalse))
ttrue).
Proof.
intros contra. inversion contra. Qed.
Example my_bool_step_prop3':
~(tif
ttrue
(tif ttrue ttrue ttrue)
(tif tfalse tfalse tfalse)
==>ttrue).
Proof. intros contra. inversion contra. Qed.
(**
although it is possible in multi-steps, it is
impossible in one step.
*)
Definition bool_step_prop3 :=
tif
(tif ttrue ttrue ttrue)
(tif ttrue ttrue ttrue)
tfalse
==>
tif
ttrue
(tif ttrue ttrue ttrue)
tfalse.
Example my_bool_step_prop4:
my_step (tif
(tif ttrue ttrue ttrue)
(tif ttrue ttrue ttrue)
tfalse)
(tif
ttrue
(tif ttrue ttrue ttrue)
tfalse).
Proof.
apply st_if. apply st_iftrue. Qed.
Example my_bool_step_prop4':
tif
(tif ttrue ttrue ttrue)
(tif ttrue ttrue ttrue)
tfalse
==>
tif
ttrue
(tif ttrue ttrue ttrue)
tfalse.
Proof. apply ST_If. apply ST_IfTrue. Qed.
(** [] *)
(** **** Exercise: 3 stars, recommended (progress_bool) *)
(* EXPECTED *)
(** Just as we proved a progress theorem for plus expressions, we can
do so for boolean expressions, as well. *)
Theorem my_strong_progress:forall t,
value t \/ (exists t', my_step t t').
Proof.
intros. induction t.
Case ("ttrue"). left. apply v_true.
Case ("tfalse"). left. apply v_false.
Case ("tif"). inversion IHt1.
SCase ("left"). destruct t1.
SSCase ("ttrue"). right. exists t2. apply st_iftrue.
SSCase ("tfalse"). right. exists t3. apply st_iffalse.
SSCase ("tif"). inversion H.
SCase ("right"). inversion H. subst. right. exists (tif x t2 t3).
apply st_if. apply H0.
Qed.
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
intros. induction t.
Case ("ttrue"). left. apply v_true.
Case ("tfalse"). left. apply v_false.
Case ("tif"). inversion IHt1.
SCase ("left"). destruct t1.
SSCase ("ttrue"). right. exists t2. apply ST_IfTrue.
SSCase ("tfalse"). right. exists t3. apply ST_IfFalse.
SSCase ("tif"). inversion H.
SCase ("right"). inversion H. subst. right. exists (tif x t2 t3).
apply ST_If. apply H0.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (step_deterministic) *)
Theorem my_step_deterministic:
deterministic my_step.
Proof.
unfold deterministic. intros. generalize dependent y2.
induction H.
Case ("1"). intros. inversion H0. subst. reflexivity. subst.
inversion H4.
Case ("2"). intros. inversion H0. subst. reflexivity. subst.
inversion H4.
Case ("3"). intros. inversion H0. subst. inversion H. subst.
inversion H. subst. apply IHmy_step in H5. subst.
reflexivity.
Qed.
Theorem step_deterministic :
deterministic step.
Proof.
unfold deterministic. intros. generalize dependent y1.
induction H0.
Case ("1"). intros. inversion H. subst. reflexivity. subst.
inversion H4.
Case ("2"). intros. inversion H. subst. reflexivity. subst.
inversion H4.
Case ("3"). intros. inversion H. subst. inversion H0. subst.
inversion H0. subst. apply IHstep in H5. subst.
reflexivity.
Qed.
(** [] *)
Module Temp5.
(** **** Exercise: 2 stars (smallstep_bool_shortcut) *)
(* EXPECTED *)
(** Suppose we want to add a "short circuit" to the step relation for
boolean expressions, so that it can recognize when the [then] and
[else] branches of a conditional are the same value (either
[ttrue] or [tfalse]) and reduce the whole conditional to this
value in a single step, even if the guard has not yet been reduced
to a value. For example, we would like this proposition to be
provable:
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
*)
(** Write an extra clause for the step relation that achieves this
effect and prove [bool_step_prop4]. *)
Inductive my_step: tm ->tm->Prop:=
| st_iftrue:forall t1 t2,
my_step (tif ttrue t1 t2) t1
| st_iffalse:forall t1 t2,
my_step (tif tfalse t1 t2) t2
| st_if:forall t1 t1' t2 t3,
my_step t1 t1' ->
my_step (tif t1 t2 t3)(tif t1' t2 t3)
| st_ifs:forall t1 t2,
my_step (tif t1 t2 t2) t2
.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
| ST_IfS: forall t1 t2,
tif t1 t2 t2 ==>t2
where " t '==>' t' " := (step t t').
(** [] *)
Definition my_bool_step_prop4:=
my_step (tif
(tif ttrue ttrue ttrue)
tfalse
tfalse)
tfalse.
Example my_bool_step_prop4_holds:
my_bool_step_prop4.
Proof.
unfold my_bool_step_prop4. apply st_ifs.
Qed.
Definition bool_step_prop4 :=
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
Example bool_step_prop4_holds :
bool_step_prop4.
Proof.
unfold bool_step_prop4. apply ST_IfS.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (properties_of_altered_step) *)
(** It can be shown that the determinism and strong progress theorems
for the step relation in the lecture notes also hold for the
definition of step given above. After we add the clause
[ST_ShortCircuit]...
- Is the [step] relation still deterministic? Write yes or no and
briefly (1 sentence) explain your answer.
A: No at all deterministic after adding [ST_ShortCircuit].
For there are cases where more than one rule can be used to generate
totally different results,
tif (tif ttrue ttrue ttrue) tfalse tfalse ==>tfalse by [ST_IfS]
or,
tif (tif ttrue ttrue ttrue) tfalse tfalse ==>tif ttrue tfalse tfalse
by [ST_If].
Optional: prove your answer correct in Coq.
*)
Theorem nondeterministic:
exists t,exists t1, exists t2, (my_step t t1 -> my_step t t2 -> t1 <> t2).
Proof.
exists (tif (tif ttrue ttrue ttrue) tfalse tfalse).
exists (tfalse).
exists (tif ttrue tfalse tfalse).
intros. intros contra. inversion contra.
Qed.
(* FILL IN HERE *)
(**
- Does a strong progress theorem hold? Write yes or no and
briefly (1 sentence) explain your answer.
A: It holds. Adding one more way to reduce a term will not cause
it to get stuck before it gets reduced to a value if it does
get there before adding it.
Optional: prove your answer correct in Coq.
*)
Theorem my_strong_progress:forall t,
value t\/(exists t', my_step t t').
Proof.
intros t. induction t.
Case ("1"). left. apply v_true.
Case ("2"). left. apply v_false.
Case ("3"). inversion IHt1.
SCase ("left"). destruct t1.
SSCase ("ttrue"). right. exists t2. apply st_iftrue.
SSCase ("tfalse"). right. exists t3. apply st_iffalse.
SSCase ("tif"). inversion H.
SCase ("right"). right. inversion H. exists (tif x t2 t3).
apply st_if. apply H0.
Qed.
(**
Note that the above proof is exactly the same as that in case without the additional
step rule. In fact there are three rules which are crucial to proving "strong progress"
holds,
[st_iftrue],[st_iffalse], and [st_if].
Any new [step] by adding additional rules will not affect this property. Qed.
*)
(* FILL IN HERE *)
(**
- In general, is there any way we could cause strong progress to
fail if we took away one or more constructors from the original
step relation? Write yes or no and briefly (1 sentence) explain
your answer.
A: Yes. If a constructor is required to reduce an already reduced term to
a value and there is no other way around it, then taking it away will
result in a situation where some terms get stuck before they are reduced
to values.
(* FILL IN HERE *)
*)
(** [] *)
End Temp5.
End Temp4.
(* ########################################################### *)
(** * Multi-Step Reduction *)
(** Until now, we've been working with the _single-step reduction_
relation [==>], which formalizes the individual steps of an
_abstract machine_ for executing programs.
We can also use this machine to reduce programs to completion --
to find out what final result they yield. This can be formalized
as follows:
- First, we define a _multi-step reduction relation_ [==>*], which
relates terms [t] and [t'] if [t] can reach [t'] by any number
of single reduction steps (including zero steps!).
- Then we define a "result" of a term [t] as a normal form that
[t] can reach by multi-step reduction. *)
(* ########################################################### *)
(** ** Definitions *)
(** Since we'll want to reuse the idea of multi-step reduction many
times in this and future chapters, let's take a little extra
trouble here and define it generically. Given a relation [R], we
define a relation [multi R] as follows: *)
Inductive multi {X:Type} (R: relation X) : relation X :=
| multi_refl : forall (x : X), multi R x x
| multi_step : forall (x y z : X),
R x y ->
multi R y z ->
multi R x z.
(** The effect of this definition is that [multi R] relates two
elements [x] and [y] of [X] if either [x = y] or else there is
some (possibly empty) sequence [z1], [z2], ..., [zn] such that:
R x z1
R z1 z2
...
R zn y
*)
Tactic Notation "multi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "multi_refl" | Case_aux c "multi_step" ].
Theorem my_multi_R: forall (X:Type)(R:relation X)(x y: X),
R x y -> (multi R) x y.
Proof.
intros. apply multi_step with y. apply H. apply multi_refl.
Qed.
Theorem multi_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> (multi R) x y.
Proof.
intros X R x y H.
apply multi_step with y. apply H. apply multi_refl. Qed.
(** The crucial properties of the [multi R] relation are
- [multi R] is reflexive
- [multi R] is transitive
- [multi R] relates everything related by [R] *)
Theorem my_multi_trans:
forall (X:Type)(R: relation X)(x y z : X),
multi R x y ->
multi R y z ->
multi R x z.
Proof.
intros. induction H. apply H0. apply IHmulti in H0.
apply multi_step with y. apply H. apply H0.
Qed.
Theorem multi_trans :
forall (X:Type) (R: relation X) (x y z : X),
multi R x y ->
multi R y z ->
multi R x z.
Proof.
intros X R x y z G H.
multi_cases (induction G) Case.
Case "multi_refl". assumption.
Case "multi_step".
apply multi_step with y. assumption.
apply IHG. assumption. Qed.
(** We now write [==>*] for the [multi step] relation -- i.e., the
relation that relates two terms [t] and [t'] if we can get from
[t] to [t'] using the [step] relation zero or more times. *)
Definition my_multistep:= multi my_step.
Definition multistep := multi step.
Notation " t '==>*' t' " := (multistep t t') (at level 40).
(* ########################################################### *)
(** ** Examples *)
Lemma my_test_multistep_1:
my_multistep
(P
(P (C 0) (C 3))
(P (C 2) (C 4)))
(C ((0 + 3) + (2 + 4))).
Proof.
apply multi_step with (P (C (0+3))(P (C 2)(C 4))).
apply st_plus1. apply st_plusconstconst.
apply multi_step with (P (C (0+3))(C (2+4))). apply st_plus2.
apply v_const. apply st_plusconstconst.
apply my_multi_R. apply st_plusconstconst.
Qed.
Lemma my_test_multistep_1':
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
apply multi_step with (P (C (0+3))(P (C 2)(C 4))).
apply ST_Plus1. apply ST_PlusConstConst.
apply multi_step with (P (C (0+3))(C (2+4))). apply ST_Plus2.
apply v_const. apply ST_PlusConstConst.
apply multi_R. apply ST_PlusConstConst.
Qed.
Lemma test_multistep_1:
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
apply multi_step with
(P
(C (0 + 3))
(P (C 2) (C 4))).
apply ST_Plus1. apply ST_PlusConstConst.
apply multi_step with
(P
(C (0 + 3))
(C (2 + 4))).
apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
apply multi_R.
apply ST_PlusConstConst. Qed.
(** Here's an alternate proof that uses [eapply] to avoid explicitly
constructing all the intermediate terms. *)
Lemma my_test_multistep_2:
my_multistep
(P
(P (C 0) (C 3))
(P (C 2) (C 4)))
(C ((0 + 3) + (2 + 4))).
Proof.
eapply multi_step. apply st_plus1. apply st_plusconstconst.
eapply multi_step. apply st_plus2. apply v_const.
apply st_plusconstconst.
eapply multi_step. apply st_plusconstconst.
apply multi_refl.
Qed.
Lemma my_test_multistep_2':
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
eapply multi_step. apply ST_Plus1. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. apply v_const.
apply ST_PlusConstConst. eapply multi_step.
apply ST_PlusConstConst. apply multi_refl.
Qed.
Lemma test_multistep_2:
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
eapply multi_step. apply ST_Plus1. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
eapply multi_step. apply ST_PlusConstConst.
apply multi_refl. Qed.
(** **** Exercise: 1 star, optional (test_multistep_2) *)
Lemma my_test_multistep_3:
my_multistep (C 3)(C 3).
Proof. apply multi_refl. Qed.
Lemma test_multistep_3':
C 3 ==>* C 3.
Proof.
apply multi_refl. Qed.
(** [] *)
(** **** Exercise: 1 star, optional (test_multistep_3) *)
Lemma my_test_multistep_4:
my_multistep (P (C 0)(C 3)) (P (C 0)(C 3)).
Proof. apply multi_refl. Qed.
Lemma test_multistep_4:
P (C 0) (C 3)
==>*
P (C 0) (C 3).
Proof.
apply multi_refl. Qed.
(** [] *)
(** **** Exercise: 2 stars (test_multistep_4) *)
Lemma my_test_multistep_5:
my_multistep
( P
(C 0)
(P
(C 2)
(P (C 0) (C 3))))
(P
(C 0)
(C (2 + (0 + 3)))).
Proof.
eapply multi_step. apply st_plus2. apply v_const.
apply st_plus2. apply v_const. apply st_plusconstconst.
eapply multi_step. apply st_plus2. apply v_const.
apply st_plusconstconst. apply multi_refl.
Qed.
Lemma test_multistep_5:
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>*
P
(C 0)
(C (2 + (0 + 3))).
Proof.
eapply multi_step. apply ST_Plus2. apply v_const. apply ST_Plus2.
apply v_const. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. apply v_const. apply ST_PlusConstConst.
apply multi_refl.
Qed.
(** [] *)
(* ########################################################### *)
(** ** Normal Forms Again *)
(** If [t] reduces to [t'] in zero or more steps and [t'] is a
normal form, we say that "[t'] is a normal form of [t]." *)
(*##########################################################*)
Definition my_step_normal_form:=normal_form my_step.
Definition my_normal_form_of (t t':tm):=
(my_multistep t t'/\my_step_normal_form t').
(*##########################################################*)
Definition step_normal_form := normal_form step.
Definition normal_form_of (t t' : tm) :=
(t ==>* t' /\ step_normal_form t').
(*###########################################################*)
(** We have already seen that, for our language, single-step reduction is
deterministic -- i.e., a given term can take a single step in
at most one way. It follows from this that, if [t] can reach
a normal form, then this normal form is unique. In other words, we
can actually pronounce [normal_form t t'] as "[t'] is _the_
normal form of [t]." *)
(** **** Exercise: 3 stars, optional (normal_forms_unique) *)
(**
Note that firstly, we prove a set of Lemmas to simplify the proof of
[my_multistep_deterministic],
*)
(*auxiliary lemmas*)
(*##############################################################*)
Lemma normal_form_of_term_1:forall x1 x2 x,
my_multistep x1 (C x)->
my_multistep (P x1 x2) (P (C x) x2).
Proof.
intros. induction H. apply multi_refl. apply multi_step with (P y x2).
apply st_plus1. apply H. apply IHmulti.
Qed.
Lemma normal_form_of_term_1':forall x1 x2 x3 x,
my_multistep x1 (C x)->
my_multistep (P x1 x2)(C x3)->
my_multistep (P (C x) x2)(C x3).
Proof.
intros. apply normal_form_of_term_1 with (x2:=x2) in H.
intros. generalize dependent x3.
induction H. intros. apply H0. intros.
inversion H1. subst. inversion H. subst.
assert (A: my_step x0 y ->my_step x0 y0->y=y0). apply my_step_deterministic.
apply A in H. apply IHmulti. subst. apply H3. apply H2.
Qed.
(**
Note that a review of the above Lemma should be added here,
Why it works...
*)
Lemma normal_form_of_term_2:forall x2 x x0,
my_multistep x2 (C x0)->
my_multistep (P (C x) x2)(P (C x)(C x0)).
Proof.
intros. induction H. apply multi_refl. apply multi_step with (P (C x) y).
apply st_plus2. apply v_const. apply H. apply IHmulti.
Qed.
Lemma normal_form_of_term_2':forall x2 x3 x x0,
my_multistep x2 (C x0)->
my_multistep (P (C x) x2)(C x3)->
my_multistep (P (C x) (C x0))(C x3).
Proof.
intros. apply normal_form_of_term_2 with (x:=x) in H.
generalize dependent x3.
induction H. intros. apply H0. intros.
inversion H1. subst. inversion H. subst.
assert (A: my_step x1 y ->my_step x1 y0->y=y0). apply my_step_deterministic.
apply A in H. apply IHmulti. subst. apply H3. apply H2.
Qed.
Lemma normal_form_of_term:forall x,
exists n, my_multistep x (C n).
Proof.
induction x. exists n. apply multi_refl. inversion IHx1.
inversion IHx2. clear IHx1. clear IHx2. exists (x+x0).
apply multi_trans with (y:=P (C x) x2). apply normal_form_of_term_1 with (x2:=x2)in H.
apply H. apply multi_trans with (y:= P (C x) (C x0)).
apply normal_form_of_term_2 with (x:=x) in H0. apply H0. apply multi_R.
apply st_plusconstconst.
Qed.
(*########################################################*)
(*end of auxiliary lemmas*)
Theorem my_multistep_deterministic:forall x x0 x1,
my_multistep x (C x0) ->
my_multistep x (C x1) ->
x0 = x1.
Proof.
intros x. destruct x.
intros. inversion H. subst. inversion H0. subst. reflexivity.
subst. inversion H1. subst. inversion H1.
intros.
assert (A: exists n, my_multistep x1 (C n)). apply normal_form_of_term.
inversion A. clear A.
assert (A: exists n, my_multistep x2 (C n)). apply normal_form_of_term.
inversion A. clear A.
assert (H3: my_multistep x1 (C x)). apply H1.
assert (H4: my_multistep x2 (C x4)). apply H2.
apply normal_form_of_term_1' with (x2:=x2)(x3:=x3) in H1.
apply normal_form_of_term_2' with (x:=x)(x3:=x3)in H2. inversion H2.
subst. inversion H5. subst. inversion H6. subst.
apply normal_form_of_term_1' with (x2:=x2)(x3:=x0) in H3.
apply normal_form_of_term_2' with (x:=x)(x3:=x0)in H4. inversion H4.
subst. inversion H7. subst. inversion H8. subst. reflexivity.
inversion H9. inversion H12. inversion H13. apply H3.
apply H. inversion H7. inversion H10. inversion H11. apply H1.
apply H0.
Qed.
(**
Now we are ready to prove [my_normal_forms_unique],
*)
Theorem my_normal_forms_unique:
deterministic my_normal_form_of.
Proof.
unfold deterministic. unfold my_normal_form_of. intros.
inversion H. unfold my_step_normal_form in H2. unfold normal_form in H2.
clear H.
assert (A: ~(exists t':tm, my_step y1 t') ->(exists n, y1 = (C n))).
intros. assert (A_1: value y1\/(exists y1', my_step y1 y1')).
apply my_strong_progress. inversion A_1. inversion H3. exists n.
reflexivity. apply H in H3. inversion H3. apply A in H2. inversion H2.
subst. clear H2. clear A.
inversion H0. clear H0. unfold my_step_normal_form in H2. unfold normal_form in H2.
assert (A: ~(exists t':tm, my_step y2 t') ->(exists n, y2 = (C n))).
intros. assert (A_1: value y2\/(exists y1', my_step y2 y1')).
apply my_strong_progress. inversion A_1. inversion H3. exists n.
reflexivity. apply H2 in H3. inversion H3. apply A in H2. inversion H2.
subst. clear H2. clear A.
apply my_multistep_deterministic with (x:=x)(x0:=x0)(x1:=x1)in H1.
subst. reflexivity. apply H.
Qed.
(**
Note that the case where the concerning relation is [step] is omitted.
*)
Theorem normal_forms_unique:
deterministic normal_form_of.
Proof.
unfold deterministic. unfold normal_form_of. intros x y1 y2 P1 P2.
inversion P1 as [P11 P12]; clear P1. inversion P2 as [P21 P22]; clear P2.
generalize dependent y2.
(* We recommend using this initial setup as-is! *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** Indeed, something stronger is true for this language (though not
for all languages): the reduction of _any_ term [t] will
eventually reach a normal form -- i.e., [normal_form_of] is a
_total_ function. Formally, we say the [step] relation is
_normalizing_. *)
Definition normalizing {X:Type} (R:relation X) :=
forall t, exists t',
(multi R) t t' /\ normal_form R t'.
(**
Note that given the proof of [my_normal_forms_unique], it is easy to prove,
[normalizing my_step],
*)
Theorem my_step_normalizing:
normalizing my_step.
Proof.
unfold normalizing. intros.
assert (A: exists n, my_multistep t (C n)). apply normal_form_of_term.
inversion A. clear A. exists (C x). split.
apply H. unfold normal_form. intros contra. inversion contra.
inversion H0.
Qed.
(**
With the help of the following Lemmas, the case where the concerning relation
is [step] is also simple,
*)
(*#############################################*)
Lemma normal_form_of_term_1_1:forall x1 x2 x,
x1 ==>*(C x)->
(P x1 x2)==>* (P (C x) x2).
Proof.
intros. induction H. apply multi_refl. apply multi_step with (P y x2).
apply ST_Plus1. apply H. apply IHmulti.
Qed.
Lemma normal_form_of_term_2_2:forall x2 x x0,
x2==>* (C x0)->
(P (C x) x2)==>*(P (C x)(C x0)).
Proof.
intros. induction H. apply multi_refl. apply multi_step with (P (C x) y).
apply ST_Plus2. apply v_const. apply H. apply IHmulti.
Qed.
Lemma normal_form_of_term':forall x,
exists n, x ==>*(C n).
Proof.
induction x. exists n. apply multi_refl. inversion IHx1.
inversion IHx2. clear IHx1. clear IHx2. exists (x+x0).
apply multi_trans with (y:=P (C x) x2). apply normal_form_of_term_1_1 with (x2:=x2)in H.
apply H. apply multi_trans with (y:= P (C x) (C x0)).
apply normal_form_of_term_2_2 with (x:=x) in H0. apply H0. apply multi_R.
apply ST_PlusConstConst.
Qed.
(*#################################################*)
Theorem step_normalizing_mine:
normalizing step.
Proof.
unfold normalizing. intros.
assert (A: exists n, t==>* (C n)). apply normal_form_of_term'.
inversion A. clear A. exists (C x). split.
apply H. unfold normal_form. intros contra. inversion contra.
inversion H0.
Qed.
(**
Note that this way of proving it is simpler than
what follows suggested by the author.
*)
(** To prove that [step] is normalizing, we need a couple of lemmas.
First, we observe that, if [t] reduces to [t'] in many steps, then
the same sequence of reduction steps within [t] is also possible
when [t] appears as the left-hand child of a [P] node, and
similarly when [t] appears as the right-hand child of a [P]
node whose left-hand child is a value. *)
Lemma my_multistep_congr_1: forall t1 t1' t2,
t1 ==>* t1' ->
P t1 t2 ==>* P t1' t2.
Proof.
intros. induction H. apply multi_refl.
apply multi_step with (P y t2). apply ST_Plus1.
apply H. apply IHmulti. Qed.
Lemma multistep_congr_1 : forall t1 t1' t2,
t1 ==>* t1' ->
P t1 t2 ==>* P t1' t2.
Proof.
intros t1 t1' t2 H. multi_cases (induction H) Case.
Case "multi_refl". apply multi_refl.
Case "multi_step". apply multi_step with (P y t2).
apply ST_Plus1. apply H.
apply IHmulti. Qed.
(** **** Exercise: 2 stars (multistep_congr_2) *)
(* EXPECTED *)
Lemma my_multistep_congr_2:forall t1 t2 t2',
value t1 ->
t2 ==>* t2' ->
P t1 t2 ==>* P t1 t2'.
Proof.
intros. induction H0. apply multi_refl.
apply multi_step with (P t1 y). apply ST_Plus2.
apply H. apply H0. apply IHmulti.
Qed.
Lemma multistep_congr_2 : forall t1 t2 t2',
value t1 ->
t2 ==>* t2' ->
P t1 t2 ==>* P t1 t2'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** _Theorem_: The [step] function is normalizing -- i.e., for every
[t] there exists some [t'] such that [t] steps to [t'] and [t'] is
a normal form.
_Proof sketch_: By induction on terms. There are two cases to
consider:
- [t = C n] for some [n]. Here [t] doesn't take a step,
and we have [t' = t]. We can derive the left-hand side by
reflexivity and the right-hand side by observing (a) that values
are normal forms (by [nf_same_as_value]) and (b) that [t] is a
value (by [v_const]).
- [t = P t1 t2] for some [t1] and [t2]. By the IH, [t1] and
[t2] have normal forms [t1'] and [t2']. Recall that normal
forms are values (by [nf_same_as_value]); we know that [t1' =
C n1] and [t2' = C n2], for some [n1] and [n2].
We can combine the [==>*] derivations for [t1] and [t2] to prove
that [P t1 t2] reduces in many steps to [C (n1 + n2)].
It is clear that our choice of [t' = C (n1 + n2)] is a
value, which is in turn a normal form. [] *)
Theorem step_normalizing :
normalizing step.
Proof.
unfold normalizing.
tm_cases (induction t) Case.
Case "C".
exists (C n).
split.
SCase "l". apply multi_refl.
SCase "r".
(* We can use [rewrite] with "iff" statements, not
just equalities: *)
rewrite nf_same_as_value. apply v_const.
Case "P".
inversion IHt1 as [t1' H1]; clear IHt1. inversion IHt2 as [t2' H2]; clear IHt2.
inversion H1 as [H11 H12]; clear H1. inversion H2 as [H21 H22]; clear H2.
rewrite nf_same_as_value in H12. rewrite nf_same_as_value in H22.
inversion H12 as [n1]. inversion H22 as [n2].
rewrite <- H in H11.
rewrite <- H0 in H21.
exists (C (n1 + n2)).
split.
SCase "l".
apply multi_trans with (P (C n1) t2).
apply multistep_congr_1. apply H11.
apply multi_trans with
(P (C n1) (C n2)).
apply multistep_congr_2. apply v_const. apply H21.
apply multi_R. apply ST_PlusConstConst.
SCase "r".
rewrite nf_same_as_value. apply v_const. Qed.
(* ########################################################### *)
(** ** Equivalence of Big-Step and Small-Step Reduction *)
(** Having defined the operational semantics of our tiny
programming language in two different styles, it makes sense to
ask whether these definitions actually define the same thing!
They do, though it takes a little work to show it. The details
are left to you. *)
(** **** Exercise: 3 stars (eval__multistep) *)
(* EXPECTED *)
Theorem my_eval_multistep:forall t n,
my_eval t n ->
my_multistep t (C n).
Proof.
intros. assert (A: exists n, my_multistep t (C n)). apply normal_form_of_term.
induction H.
apply multi_refl.
assert (B: exists n, my_multistep t1 (C n)). apply normal_form_of_term.
apply IHmy_eval1 in B.
assert (C: exists n, my_multistep t2 (C n)). apply normal_form_of_term.
apply IHmy_eval2 in C.
clear IHmy_eval1. clear IHmy_eval2. inversion A. clear A.
apply normal_form_of_term_1' with (x2:=t2)(x3:=x) in B.
apply normal_form_of_term_2' with (x:=n1)(x3:=x) in C.
inversion C. subst. inversion H2. subst. inversion H3. subst.
apply H1. subst. inversion H4. subst. inversion H7.
subst. inversion H8. apply B. apply H1.
Qed.
(**
Note that the above proof is based upon our earlier proof of
[my_multistep_deterministic].
*)
Theorem eval__multistep : forall t n,
t || n -> t ==>* C n.
(** The key idea behind the proof comes from the following picture:
P t1 t2 ==> (by ST_Plus1)
P t1' t2 ==> (by ST_Plus1)
P t1'' t2 ==> (by ST_Plus1)
...
P (C n1) t2 ==> (by ST_Plus2)
P (C n1) t2' ==> (by ST_Plus2)
P (C n1) t2'' ==> (by ST_Plus2)
...
P (C n1) (C n2) ==> (by ST_PlusConstConst)
C (n1 + n2)
That is, the multistep reduction of a term of the form [P t1 t2]
proceeds in three phases:
- First, we use [ST_Plus1] some number of times to reduce [t1]
to a normal form, which must (by [nf_same_as_value]) be a
term of the form [C n1] for some [n1].
- Next, we use [ST_Plus2] some number of times to reduce [t2]
to a normal form, which must again be a term of the form [C
n2] for some [n2].
- Finally, we use [ST_PlusConstConst] one time to reduce [P (C
n1) (C n2)] to [C (n1 + n2)].
To formalize this intuition, you'll need to use the congruence
lemmas from above (you might want to review them now, so that
you'll be able to recognize when they are useful), plus some basic
properties of [==>*]: that it is reflexive, transitive, and
includes [==>]. *)
Proof.
intros. induction H. apply multi_refl.
apply my_multistep_congr_1 with (t2:=t2) in IHeval1.
apply multi_trans with (P (C n1) t2). apply IHeval1.
apply my_multistep_congr_2 with (t1:=C n1) in IHeval2.
apply multi_trans with (P (C n1)(C n2)). apply IHeval2.
apply multi_R. apply ST_PlusConstConst. apply v_const.
Qed.
(** [] *)
(** **** Exercise: 3 stars (eval__multistep_inf) *)
(** Write a detailed informal version of the proof of [eval__multistep].
(* FILL IN HERE *)
[]
*)
(** For the other direction of the correspondence, we need one lemma,
which establishes a relation between single-step reduction and
big-step evaluation. *)
(** **** Exercise: 3 stars (step__eval) *)
(* EXPECTED *)
Lemma step__eval : forall t t' n,
t ==> t' ->
t' || n ->
t || n.
Proof.
intros t t' n Hs. generalize dependent n.
induction Hs. intros. inversion H. apply E_Plus. apply E_Const.
apply E_Const.
intros. inversion H. subst. apply IHHs in H2. apply E_Plus.
apply H2. apply H4.
intros. inversion H0. subst. apply IHHs in H5. apply E_Plus.
apply H3. apply H5.
Qed.
(** [] *)
(** The main theorem is now straightforward to prove, once it is
stated correctly. The proof proceeds by induction on the
multipstep reduction sequence that is buried in the hypothesis
[normal_form_of t v]. *)
(** Make sure you understand the statement before you start to
work on the proof. *)
(** **** Exercise: 3 stars (multistep__eval) *)
(* EXPECTED *)
Theorem multistep__eval : forall t v,
normal_form_of t v -> exists n, v = C n /\ t || n.
Proof.
intros. unfold normal_form_of in H. inversion H.
induction H0. assert (A:value x \/ exists t',x==>t'). apply my_strong_progress'.
inversion A. inversion H0.
exists n. split. reflexivity. apply E_Const. apply H1 in H0. inversion H0.
inversion H. apply IHmulti in H4.
assert (A:value z \/ exists t',z==>t'). apply my_strong_progress'.
inversion A. inversion H5. exists n. split. reflexivity.
inversion H4. subst. inversion H7. inversion H6.
apply step__eval with (y). apply H0. apply H8.
apply H1 in H5. inversion H5. split. apply H2.
apply H4.
Qed.
(**
Or, use my version of the relation [step], [my_step], we have to
prove the following,
*)
Lemma my_multistep_eval_1:forall t n,
my_multistep t (C n)->
my_eval t n.
Proof.
intros t. induction t.
Case ("1"). intros. inversion H. subst. apply e_const. subst.
inversion H0.
Case ("2"). intros. assert (A: exists n, my_multistep t1 (C n)). apply normal_form_of_term.
inversion A. clear A.
assert (B: exists n, my_multistep t2 (C n)). apply normal_form_of_term.
inversion B. clear B.
assert (A: my_multistep t1 (C x)). apply H0.
assert (B: my_multistep t2 (C x0)). apply H1.
apply normal_form_of_term_1' with (x2:=t2)(x3:=n) in H0.
apply normal_form_of_term_2' with (x3:=n)(x:=x) in H1.
inversion H1. subst. inversion H2. subst. inversion H3. subst.
apply IHt1 in A. apply IHt2 in B. apply e_plus. apply A. apply B.
inversion H4. inversion H7. inversion H8. apply H0.
apply H.
Qed.
Theorem my_multistep__eval:forall t v,
my_normal_form_of t v ->
exists n, v = C n /\ my_eval t n.
Proof.
unfold my_normal_form_of. unfold my_step_normal_form. unfold normal_form.
intros. inversion H. clear H.
assert (A: value v \/ (exists t', my_step v t')). apply my_strong_progress.
inversion A. inversion H. subst. exists n. split. reflexivity.
apply my_multistep_eval_1. apply H0.
apply H1 in H. inversion H.
Qed.
(**
Note the above proof is based upon the Lemmas
used to prove [my_normal_forms_unique].
*)
(** [] *)
(* ########################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 4 stars (combined_properties) *)
(** We've considered the arithmetic and conditional expressions
separately. This exercise explores how the two interact. *)
Module Combined.
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P"
| Case_aux c "ttrue" | Case_aux c "tfalse" | Case_aux c "tif" ].
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_true : value ttrue
| v_false : value tfalse.
(**
Again define [my_step] as follows,
*)
Inductive my_step: tm -> tm -> Prop :=
| st_plusconstconst: forall n1 n2,
my_step (P (C n1)(C n2)) (C (n1 + n2))
| st_plus1: forall t1 t1' t2,
my_step t1 t1' ->
my_step (P t1 t2)(P t1' t2)
| st_plus2: forall v1 t2 t2',
value v1 ->
my_step t2 t2' ->
my_step (P v1 t2)(P v1 t2')
| st_iftrue: forall t1 t2,
my_step (tif ttrue t1 t2)(t1)
| st_iffalse: forall t1 t2,
my_step (tif tfalse t1 t2)(t2)
| st_if: forall t1 t1' t2 t3,
my_step t1 t1' ->
my_step (tif t1 t2 t3)(tif t1' t2 t3)
.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2"
| Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
(** Earlier, we separately proved for both plus- and if-expressions...
- that the step relation was deterministic, and
- a strong progress lemma, stating that every term is either a
value or can take a step.
Prove or disprove these two properties for the combined language. *)
(* FILL IN HERE *)
(**
Firstly, we prove that [my_step] is deterministic.
This should be the case here for the new language is a combination of two
which are deterministic.
*)
Theorem my_step_deterministic:
deterministic my_step.
Proof.
unfold deterministic. intros. generalize dependent y2.
induction H.
Case ("1"). intros. inversion H0. subst. reflexivity. subst.
inversion H3. subst. inversion H4.
Case ("2"). intros. inversion H0. subst. inversion H. subst.
apply IHmy_step in H4. subst. reflexivity. subst.
inversion H3. subst. inversion H. subst. inversion H0.
subst. inversion H2. subst. inversion H. subst. inversion H.
Case ("3"). intros. inversion H. subst. inversion H1. subst.
inversion H0. subst. inversion H5. subst.
apply IHmy_step in H6. subst. reflexivity. subst.
inversion H1. subst. inversion H5. subst. apply IHmy_step in H6.
subst. reflexivity. subst. inversion H1. subst. inversion H5.
subst. apply IHmy_step in H6. subst. reflexivity.
Case ("4"). intros. inversion H0. subst. reflexivity. subst. inversion H4.
Case ("5"). intros. inversion H0. subst. reflexivity. subst. inversion H4.
Case ("6"). intros. inversion H0. subst. inversion H. subst. inversion H.
subst. apply IHmy_step in H5. subst. reflexivity.
Qed.
(**
Secondly, it can be shown that the language [my_step] no longer has
strong progress property for it is possible in the language to have
cases where a term is neither a value nor can be reduced further.
By pointing out one counter example is enough to prove the point.
For example,
[P (ttrue) (C 7)] is not a value and cannot be further reduced.
Qed.
*)
Lemma my_strong_progress_fail_1:
~ exists t', my_step (P ttrue (C 7)) t'.
Proof.
intros contra. inversion contra. inversion H.
subst. inversion H3. subst. inversion H4.
Qed.
Theorem my_strong_progress_fail:
exists t, ~( value t\/(exists t', my_step t t')).
Proof.
exists (P (ttrue)(C 7)). intros contra.
inversion contra. inversion H.
apply my_strong_progress_fail_1 in H. inversion H.
Qed.
(** [] *)
End Combined.
(* ########################################################### *)
(** * Small-Step Imp *)
(** For a more serious example, here is the small-step version of the
Imp operational semantics. *)
(** The small-step evaluation relations for arithmetic and boolean
expressions are straightforward extensions of the tiny language
we've been working up to now. To make them easier to read, we
introduce the symbolic notations [==>a] and [==>b], respectively,
for the arithmetic and boolean step relations. *)
Inductive aval : aexp -> Prop :=
av_num : forall n, aval (ANum n).
(** We are not actually going to bother to define boolean
values -- they aren't needed in the definition of [==>b]
below (why?), though they might be if our language were a bit
larger (why?). *)
Reserved Notation " t '/' st '==>a' t' " (at level 40, st at level 39).
Inductive astep : state -> aexp -> aexp -> Prop :=
| AS_Id : forall st i,
AId i / st ==>a ANum (st i)
| AS_Plus : forall st n1 n2,
APlus (ANum n1) (ANum n2) / st ==>a ANum (n1 + n2)
| AS_Plus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(APlus a1 a2) / st ==>a (APlus a1' a2)
| AS_Plus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(APlus v1 a2) / st ==>a (APlus v1 a2')
| AS_Minus : forall st n1 n2,
(AMinus (ANum n1) (ANum n2)) / st ==>a (ANum (minus n1 n2))
| AS_Minus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMinus a1 a2) / st ==>a (AMinus a1' a2)
| AS_Minus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMinus v1 a2) / st ==>a (AMinus v1 a2')
| AS_Mult : forall st n1 n2,
(AMult (ANum n1) (ANum n2)) / st ==>a (ANum (mult n1 n2))
| AS_Mult1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMult (a1) (a2)) / st ==>a (AMult (a1') (a2))
| AS_Mult2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMult v1 a2) / st ==>a (AMult v1 a2')
where " t '/' st '==>a' t' " := (astep st t t').
Reserved Notation " t '/' st '==>b' t' " (at level 40, st at level 39).
Inductive bstep : state -> bexp -> bexp -> Prop :=
| BS_Eq : forall st n1 n2,
(BEq (ANum n1) (ANum n2)) / st ==>b
(if (beq_nat n1 n2) then BTrue else BFalse)
| BS_Eq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BEq a1 a2) / st ==>b (BEq a1' a2)
| BS_Eq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BEq v1 a2) / st ==>b (BEq v1 a2')
| BS_LtEq : forall st n1 n2,
(BLe (ANum n1) (ANum n2)) / st ==>b
(if (ble_nat n1 n2) then BTrue else BFalse)
| BS_LtEq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BLe a1 a2) / st ==>b (BLe a1' a2)
| BS_LtEq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BLe v1 a2) / st ==>b (BLe v1 (a2'))
| BS_NotTrue : forall st,
(BNot BTrue) / st ==>b BFalse
| BS_NotFalse : forall st,
(BNot BFalse) / st ==>b BTrue
| BS_NotStep : forall st b1 b1',
b1 / st ==>b b1' ->
(BNot b1) / st ==>b (BNot b1')
| BS_AndTrueTrue : forall st,
(BAnd BTrue BTrue) / st ==>b BTrue
| BS_AndTrueFalse : forall st,
(BAnd BTrue BFalse) / st ==>b BFalse
| BS_AndFalse : forall st b2,
(BAnd BFalse b2) / st ==>b BFalse
| BS_AndTrueStep : forall st b2 b2',
b2 / st ==>b b2' ->
(BAnd BTrue b2) / st ==>b (BAnd BTrue b2')
| BS_AndStep : forall st b1 b1' b2,
b1 / st ==>b b1' ->
(BAnd b1 b2) / st ==>b (BAnd b1' b2)
where " t '/' st '==>b' t' " := (bstep st t t').
(** The semantics of commands is the interesting part. We need two
small tricks to make it work:
- We use [SKIP] as a "command value" -- i.e., a command that
has reached a normal form.
- An assignment command reduces to [SKIP] (and an updated
state).
- The sequencing command waits until its left-hand
subcommand has reduced to [SKIP], then throws it away so
that reduction can continue with the right-hand
subcommand.
- We reduce a [WHILE] command by transforming it into a
conditional followed by the same [WHILE]. *)
(** (There are other ways of achieving the effect of the latter
trick, but they all share the feature that the original [WHILE]
command needs to be saved somewhere while a single copy of the loop
body is being evaluated.) *)
Reserved Notation " t '/' st '==>' t' '/' st' "
(at level 40, st at level 39, t' at level 39).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ; c2) / st ==> (c1' ; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
IFB BTrue THEN c1 ELSE c2 FI / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
IFB BFalse THEN c1 ELSE c2 FI / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b / st ==>b b' ->
IFB b THEN c1 ELSE c2 FI / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st
==> (IFB b THEN (c1; (WHILE b DO c1 END)) ELSE SKIP FI) / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
(* ########################################################### *)
(** * Concurrent Imp (Optional) *)
(** Finally, to show the power of this definitional style, let's
enrich Imp with a new form of command that runs two subcommands in
parallel and terminates when both have terminated. To reflect the
unpredictability of scheduling, the actions of the subcommands may
be interleaved in any order, but they share the same memory and
can communicate by reading and writing the same variables. *)
(**
Note that a concurrent Imp can be obtained by introducing nondeterminism
into the language [Imp]. In [cstep], there if exactly one rule for each
different kind of term and there is only one way to reduce one term to
another. If however, we have two different rules which can be applied to
reduce the same term to different intermediate terms with exactly the same
end product, we have successfully introduced concurrency into [Imp].
Consider the following three additional rules,
[| CS_Par1: forall st c1 c1' st' c2,
c1 /st ==>c1'/st' ->
(PAR c1 WITH c2 END)/st ==>(PAR c1' WITH c2 END)/st'
| CS_Par2: forall st c2 c2' st' c1,
c2 /st==>c2'/st' ->
(PAR c1 WITH c2 END)/st==>(PAR c1 WITH c2' END)/st'
| CS_ParFinish: forall st,
(PAR SKIP WITH SKIP END)/st==>SKIP /st]
*)
Module CImp.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
(* New: *)
| CPar : com -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "PAR" ].
Notation "'SKIP'" :=
CSkip.
Notation "l '::=' a" :=
(CAss l a) (at level 60).
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'PAR' c1 'WITH' c2 'END'" :=
(CPar c1 c2) (at level 80, right associativity).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
(* Old part *)
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ; c2) / st ==> (c1' ; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
(IFB BTrue THEN c1 ELSE c2 FI) / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
(IFB BFalse THEN c1 ELSE c2 FI) / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b /st ==>b b' ->
(IFB b THEN c1 ELSE c2 FI) / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st ==>
(IFB b THEN (c1; (WHILE b DO c1 END)) ELSE SKIP FI) / st
(* New part: *)
| CS_Par1 : forall st c1 c1' c2 st',
c1 / st ==> c1' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1' WITH c2 END) / st'
| CS_Par2 : forall st c1 c2 c2' st',
c2 / st ==> c2' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1 WITH c2' END) / st'
| CS_ParDone : forall st,
(PAR SKIP WITH SKIP END) / st ==> SKIP / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
Definition cmultistep := multi cstep.
Notation " t '/' st '==>*' t' '/' st' " :=
(multi cstep (t,st) (t',st'))
(at level 40, st at level 39, t' at level 39).
(** Among the many interesting properties of this language is the fact
that the following program can terminate with the variable [X] set
to any value... *)
Definition par_loop : com :=
PAR
Y ::= ANum 1
WITH
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END
END.
(** In particular, it can terminate with [X] set to [0]: *)
(**
Note that in respect to the above programme, there is indeed at least one
sequence of execution such that starting from empty state, the value of [X]
is set to be zero after the execution.
Consider the following,
firstly, [Y::=ANum 1] is executed within one small step:
[Y::=ANum 1 /empty_state ==>SKIP/update empty_state Y 1],
then, [WHILE] loop within the parallel branch is converted to
[IF] within one small step,
after that,[IF] is transformed into [SKIP/update empty_state Y 1] within
one small step,
at last, [PAR SKIP WITH SKIP END/update empty_state Y 1] is transformed into
[SKIP/update empty_state Y 1] and the program terminates at 4 small steps.
It is clear that in the final state [X= 0].
*)
Example par_loop_example_0:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 0.
Proof.
eapply ex_intro. split.
unfold par_loop.
eapply multi_step. apply CS_Par1.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** It can also terminate with [X] set to [2]: *)
Example par_loop_example_2:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 2.
Proof.
eapply ex_intro. split.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** More generally... *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n__Sn : forall n st,
st X = n /\ st Y = 0 ->
par_loop / st ==>* par_loop / (update st X (S n)).
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n : forall n st,
st X = 0 /\ st Y = 0 ->
exists st',
par_loop / st ==>* par_loop / st' /\ st' X = n /\ st' Y = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** ... the above loop can exit with [X] having any value
whatsoever. *)
Theorem par_loop_any_X:
forall n, exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = n.
Proof.
intros n.
destruct (par_body_n n empty_state).
split; unfold update; reflexivity.
rename x into st.
inversion H as [H' [HX HY]]; clear H.
exists (update st Y 1). split.
eapply multi_trans with (par_loop,st). apply H'.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id. rewrite update_eq.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
apply multi_refl.
rewrite update_neq. assumption. reflexivity.
Qed.
End CImp.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCON_FUNCTIONAL_V
`define SKY130_FD_SC_LS__FAHCON_FUNCTIONAL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
// Local signals
wire xor0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
buf buf1 (COUT_N , or0_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCON_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD1_BEHAVIORAL_PP_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv5sd1 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD1_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__NAND2B_BEHAVIORAL_PP_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand2b (
VPWR,
VGND,
Y ,
A_N ,
B
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B ;
// Local signals
wire Y not0_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y , not0_out, A_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2B_BEHAVIORAL_PP_V
|
`include "logfunc.h"
module pfmonitor_wp (
input clk
,input reset
,input logic coretopfm_dec_valid
,output logic coretopfm_dec_retry
,input SC_pcsign_type coretopfm_dec_pcsign
,input SC_robid_type coretopfm_dec_rid
,input SC_decwidth_type coretopfm_dec_decmask
,input logic coretopfm_retire_valid
,output logic coretopfm_retire_retry
,input PF_entry_type coretopfm_retire_pfentry
,input SC_robid_type coretopfm_retire_d0_rid
,input PF_delta_type coretopfm_retire_d0_val
,input SC_robid_type coretopfm_retire_d1_rid
,input PF_delta_type coretopfm_retire_d1_val
`ifdef SCMEM_PFRETIRE_4
,input SC_robid_type coretopfm_retire_d2_rid
,input PF_delta_type coretopfm_retire_d2_val
,input SC_robid_type coretopfm_retire_d3_rid
,input PF_delta_type coretopfm_retire_d3_val
`endif
,output logic pfmtocore_pred_valid
,input logic pfmtocore_pred_retry
,output PF_entry_type pfmtocore_pred_pfentry
,output SC_robid_type pfmtocore_pred_d0_rid
,output PF_delta_type pfmtocore_pred_d0_val
,output PF_weigth_type pfmtocore_pred_d0_w
,output SC_robid_type pfmtocore_pred_d1_rid
,output PF_delta_type pfmtocore_pred_d1_val
,output PF_weigth_type pfmtocore_pred_d1_w
,output SC_robid_type pfmtocore_pred_d2_rid
,output PF_delta_type pfmtocore_pred_d2_val
,output PF_weigth_type pfmtocore_pred_d2_w
,output SC_robid_type pfmtocore_pred_d3_rid
,output PF_delta_type pfmtocore_pred_d3_val
,output PF_weigth_type pfmtocore_pred_d3_w
);
pfmonitor pfm (
.clk (clk)
,.reset (reset)
,.coretopfm_dec_valid (coretopfm_dec_valid)
,.coretopfm_dec_retry (coretopfm_dec_retry)
,.coretopfm_dec ({coretopfm_dec_pcsign
,coretopfm_dec_rid
,coretopfm_dec_decmask})
,.coretopfm_retire_valid (coretopfm_retire_valid)
,.coretopfm_retire_retry (coretopfm_retire_retry)
,.coretopfm_retire ({coretopfm_retire_pfentry
,coretopfm_retire_d0_rid
,coretopfm_retire_d0_val
,coretopfm_retire_d1_rid
,coretopfm_retire_d1_val
,coretopfm_retire_d2_rid
,coretopfm_retire_d2_val
,coretopfm_retire_d3_rid
,coretopfm_retire_d3_val})
,.pfmtocore_pred_valid (pfmtocore_pred_valid)
,.pfmtocore_pred_retry (pfmtocore_pred_retry)
,.pfmtocore_pred ({pfmtocore_pred_pfentry
,pfmtocore_pred_d0_rid
,pfmtocore_pred_d0_val
,pfmtocore_pred_d0_w
,pfmtocore_pred_d1_rid
,pfmtocore_pred_d1_val
,pfmtocore_pred_d1_w
,pfmtocore_pred_d2_rid
,pfmtocore_pred_d2_val
,pfmtocore_pred_d2_w
,pfmtocore_pred_d3_rid
,pfmtocore_pred_d3_val
,pfmtocore_pred_d3_w})
);
endmodule
|
module BRAMInterconnect(rddata_bo,s1_addr_bo,s1_wrdata_bo,s1_en_o,s1_we_bo,s2_addr_bo,s2_wrdata_bo,s2_en_o,s2_we_bo,s3_addr_bo,s3_wrdata_bo,s3_en_o,s3_we_bo,addr_bi,clk_i,wrdata_bi,en_i,rst_i,we_bi,s1_rddata_bi,s2_rddata_bi,s3_rddata_bi);
output [31:0] rddata_bo;
output [12:0] s1_addr_bo;
output [31:0] s1_wrdata_bo;
output s1_en_o;
output [3:0] s1_we_bo;
output [12:0] s2_addr_bo;
output [31:0] s2_wrdata_bo;
output s2_en_o;
output [3:0] s2_we_bo;
output [12:0] s3_addr_bo;
output [31:0] s3_wrdata_bo;
output s3_en_o;
output [3:0] s3_we_bo;
input [12:0] addr_bi;
input clk_i;
input [31:0] wrdata_bi;
input en_i;
input rst_i;
input [3:0] we_bi;
input [31:0] s1_rddata_bi;
input [31:0] s2_rddata_bi;
input [31:0] s3_rddata_bi;
reg [31:0] rddata_bo;
reg [12:0] s1_addr_bo;
reg [31:0] s1_wrdata_bo;
reg s1_en_o;
reg [3:0] s1_we_bo;
reg [12:0] s2_addr_bo;
reg [31:0] s2_wrdata_bo;
reg s2_en_o;
reg [3:0] s2_we_bo;
reg [12:0] s3_addr_bo;
reg [31:0] s3_wrdata_bo;
reg s3_en_o;
reg [3:0] s3_we_bo;
reg next_en_o_reg;
reg en_o_reg;
//write:
always @(we_bi or en_i or wrdata_bi or addr_bi )
begin
if (en_i )
begin
case(addr_bi )
'h0, 'h4, 'h8 :
begin
s1_addr_bo =(addr_bi );
s1_wrdata_bo =(wrdata_bi );
s1_en_o =(en_i );
s1_we_bo =(we_bi );
end
'h0C, 'h10, 'h14 :
begin
s2_addr_bo =(addr_bi -'h0C );
s2_wrdata_bo =(wrdata_bi );
s2_en_o =(en_i );
s2_we_bo =(we_bi );
end
'h18, 'h1C :
begin
s3_addr_bo =(addr_bi -'h18);
s3_wrdata_bo =(wrdata_bi );
s3_en_o =(en_i );
s3_we_bo =(we_bi );
end
endcase
end
else
begin
s1_addr_bo =(0);
s1_wrdata_bo =(0);
s1_en_o =(0);
s1_we_bo =(0);
s2_addr_bo =(0);
s2_wrdata_bo =(0);
s2_en_o =(0);
s2_we_bo =(0);
s3_addr_bo =(0);
s3_wrdata_bo =(0);
s3_en_o =(0);
s3_we_bo =(0);
end
end
//read:
always @(s3_rddata_bi or s2_rddata_bi or s1_rddata_bi or en_o_reg )
begin
if (en_o_reg )
begin
case(addr_bi )
'h0, 'h4, 'h8 :
begin
rddata_bo =(s1_rddata_bi );
end
'h0C, 'h10, 'h14 :
begin
rddata_bo =(s2_rddata_bi );
end
'h18, 'h1C :
begin
rddata_bo =(s3_rddata_bi );
end
endcase
end
else
begin
rddata_bo =(0);
end
end
//neg_clk:
always @(negedge clk_i )
begin
next_en_o_reg <=(en_i &&!we_bi );
end
//registers:
always @(posedge clk_i or posedge rst_i )
begin
if (!rst_i &&clk_i )
begin
en_o_reg <=(next_en_o_reg );
end
else
begin
en_o_reg <=(0);
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "ge_1000baseX_an.v" ////
//// ////
//// This file is part of the : ////
//// ////
//// "1000BASE-X IEEE 802.3-2008 Clause 36 - PCS project" ////
//// ////
//// http://opencores.org/project,1000base-x ////
//// ////
//// Author(s): ////
//// - D.W.Pegler Cambridge Broadband Networks Ltd ////
//// ////
//// { [email protected], [email protected] } ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 AUTHORS. All rights reserved. ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// This module is based on the coding method described in ////
//// IEEE Std 802.3-2008 Clause 37" Auto-Negotiation function, ////
//// type 1000BASE-X"; see : ////
//// ////
//// http://standards.ieee.org/about/get/802/802.3.html ////
//// and ////
//// doc/802.3-2008_section3.pdf, Clause 37. ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "ge_1000baseX_constants.v"
`include "timescale.v"
module ge_1000baseX_an #(
parameter BASEX_AN_MODE = 0
) (
// --- clocks and reset ---
input ck,
input reset,
// --- Startup interface. ---
input startup_enable,
// --- Auto-negotiation ctrl parameter ---
output reg [2:0] xmit,
output reg [15:0] tx_config,
input [15:0] rx_config,
input rx_config_set,
input ability_match,
input acknowledge_match,
input consistency_match,
input idle_match,
// --- RX_UNITDATA.indicate messages from RX state machine ---
input [2:0] rudi,
// --- Synchronisation Status ---
input sync_status,
// --- GMII Register 0 - AN Basic Control register ---
input mr_main_reset,
input mr_loopback,
input mr_restart_an,
input mr_an_enable,
// --- GMII Register 1 - AN Basic Status register ---
output reg mr_an_complete,
// --- GMII register 4 - AN Advertisement
input [15:0] mr_adv_ability,
// --- GMII register 5 - AN Link Partner Ability
output reg [15:0] mr_lp_adv_ability,
// --- GMII register 6 - AN Expansion
output reg mr_np_abl,
output reg mr_page_rx,
// --- GMII register 7 - AN Next Page
input [15:0] mr_np_tx,
// --- GMII register 8 - AN Link Partner Next Page
output reg [15:0] mr_lp_np_rx,
// --- DEBUG
output [3:0] debug_pcs_an_present,
output [17:0] debug_linktimer,
output reg debug_an_restart_state
);
//////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////
reg mr_np_loaded;
//////////////////////////////////////////////////////////////////////////////
//
//////////////////////////////////////////////////////////////////////////////
`ifdef MODEL_TECH
enum logic [3:0] {
`else
localparam
`endif
S_PCS_AN_STARTUP_RUN = 0,
S_PCS_AN_ENABLE = 1,
S_PCS_AN_RESTART = 2,
S_PCS_AN_DISABLE_LINK_OK = 3,
S_PCS_AN_ABILITY_DETECT = 4,
S_PCS_AN_ACKNOWLEDGE_DETECT = 5,
S_PCS_AN_COMPLETE_ACKNOWLEDGE = 6,
S_PCS_AN_IDLE_DETECT = 7,
S_PCS_AN_LINK_OK = 8,
S_PCS_AN_NEXT_PAGE_WAIT = 9
`ifdef MODEL_TECH
} pcs_an_present, pcs_an_next;
`else
; reg [3:0] pcs_an_present, pcs_an_next;
`endif
assign debug_pcs_an_present = pcs_an_present;
//////////////////////////////////////////////////////////////////////////////
// rx configuration
//////////////////////////////////////////////////////////////////////////////
wire rx_config_clr = ~rx_config_set;
//////////////////////////////////////////////////////////////////////////////
// Link timer
//////////////////////////////////////////////////////////////////////////////
`ifdef MODEL_TECH // if Modelsim
`define LINK_TIMER_DONE 2000
`else
`ifdef _VCP // if Aldec Riviera
`define LINK_TIMER_DONE 2000
`else
`define LINK_TIMER_DONE 200000
`endif
`endif
reg [17:0] link_timer_cnt;
reg link_timer_m_start, link_timer_m_inc;
wire link_timer_done;
always @(posedge ck, posedge reset)
if (reset)
begin
link_timer_cnt <= 0;
end
else
begin
if (link_timer_m_start) link_timer_cnt <= 0;
else if (link_timer_m_inc) link_timer_cnt <= link_timer_cnt + 1;
end
assign link_timer_done = (link_timer_cnt >= `LINK_TIMER_DONE);
assign debug_linktimer = link_timer_cnt;
//////////////////////////////////////////////////////////////////////////////
// xmit - set to tell TX state machine state of AN
//////////////////////////////////////////////////////////////////////////////
reg xmit_CONFIGURATION_m_set, xmit_DATA_m_set, xmit_IDLE_m_set;
always @(posedge ck, posedge reset)
if (reset)
xmit <= `XMIT_IDLE;
else
begin
if (~mr_an_enable & rudi != `RUDI_INVALID) xmit <= `XMIT_DATA;
else if (xmit_CONFIGURATION_m_set) xmit <= `XMIT_CONFIGURATION;
else if (xmit_DATA_m_set) xmit <= `XMIT_DATA;
else if (xmit_IDLE_m_set) xmit <= `XMIT_IDLE;
end
//////////////////////////////////////////////////////////////////////////////
// mr_lp_adv_ability - variable to store Link partner capabilities
//////////////////////////////////////////////////////////////////////////////
reg mr_lp_adv_ability_set, mr_lp_adv_ability_clr;
always @(posedge ck, posedge reset)
if (reset)
mr_lp_adv_ability <= 16'h0;
else
begin
if (mr_lp_adv_ability_set) mr_lp_adv_ability <= rx_config;
else if (mr_lp_adv_ability_clr) mr_lp_adv_ability <= 16'h00;
end
//////////////////////////////////////////////////////////////////////////////
// mr_np_loaded - variable to indicate if the next page has been loaded
//////////////////////////////////////////////////////////////////////////////
reg mr_np_loaded_m_set, mr_np_loaded_m_clr;
always @(posedge ck, posedge reset)
if (reset)
mr_np_loaded <= 0;
else
begin
if (mr_np_loaded_m_set) mr_np_loaded <= 1;
else if (mr_np_loaded_m_clr) mr_np_loaded <= 0;
end
//////////////////////////////////////////////////////////////////////////////
// mr_page_rx_m_clr
//////////////////////////////////////////////////////////////////////////////
reg mr_page_rx_m_set, mr_page_rx_m_clr;
always @(posedge ck, posedge reset)
if (reset)
mr_page_rx <= 0;
else
begin
if (mr_page_rx_m_set) mr_page_rx <= 1;
else if (mr_page_rx_m_clr) mr_page_rx <= 0;
end
//////////////////////////////////////////////////////////////////////////////
// mr_an_complete
//////////////////////////////////////////////////////////////////////////////
reg mr_an_complete_m_set, mr_an_complete_m_clr;
always @(posedge ck, posedge reset)
if (reset)
mr_an_complete <= 0;
else
begin
if (mr_an_complete_m_set) mr_an_complete <= 1;
else if (mr_an_complete_m_clr) mr_an_complete <= 0;
end
//////////////////////////////////////////////////////////////////////////////
// toggle_tx
//////////////////////////////////////////////////////////////////////////////
reg toggle_tx, toggle_tx_adv_m_set, toggle_tx_toggle_m_set;
always @(posedge ck, posedge reset)
if (reset)
toggle_tx <= 0;
else
begin
if (toggle_tx_adv_m_set) toggle_tx <= mr_adv_ability[12];
else if (toggle_tx_toggle_m_set) toggle_tx <= ~toggle_tx;
end
//////////////////////////////////////////////////////////////////////////////
// toggle_rx
//////////////////////////////////////////////////////////////////////////////
reg toggle_rx, toggle_rx_m_set;
always @(posedge ck, posedge reset)
if (reset)
toggle_rx <= 0;
else
begin
if (toggle_rx_m_set) toggle_rx <= rx_config[11];
end
//////////////////////////////////////////////////////////////////////////////
// tx_config register ctrl
//////////////////////////////////////////////////////////////////////////////
reg tx_config_m_clr, tx_config_ABILITY_m_set, tx_config_ACK_m_set, tx_config_NP_m_set;
always @(posedge ck, posedge reset)
if (reset)
tx_config <= 0;
else
begin
if (tx_config_m_clr) tx_config <= 0;
else if (tx_config_ACK_m_set) tx_config[14] <= 1;
else if (tx_config_ABILITY_m_set) tx_config <= { mr_adv_ability[15],1'b0, mr_adv_ability[13:0] };
else if (tx_config_NP_m_set) tx_config <= { mr_np_tx[15], 1'b0, mr_np_tx[13:12], toggle_tx,mr_np_tx[10:0] };
end
//////////////////////////////////////////////////////////////////////////////
// np_rx
//////////////////////////////////////////////////////////////////////////////
reg np_rx, np_rx_m_set;
always @(posedge ck, posedge reset)
if (reset)
np_rx <= 0;
else
begin
if (np_rx_m_set) np_rx <= rx_config[15];
end
//////////////////////////////////////////////////////////////////////////////
// mr_lp_np_rx
//////////////////////////////////////////////////////////////////////////////
reg mr_lp_np_rx_m_set;
always @(posedge ck, posedge reset)
if (reset)
mr_lp_np_rx <= 0;
else
begin
if (mr_lp_np_rx_m_set) mr_lp_np_rx <= rx_config[15];
end
//////////////////////////////////////////////////////////////////////////////
// np_page_rx
//////////////////////////////////////////////////////////////////////////////
reg np_page_rx, np_page_rx_m_set;
always @(posedge ck, posedge reset)
if (reset)
np_page_rx <= 0;
else
begin
if (np_page_rx_m_set) np_page_rx <= 1;
end
//////////////////////////////////////////////////////////////////////////////
// resolve_priority
//////////////////////////////////////////////////////////////////////////////
reg resolve_priority, resolve_priority_m_set;
always @(posedge ck, posedge reset)
if (reset)
resolve_priority <= 0;
else
begin
if (resolve_priority_m_set) resolve_priority <= 1;
end
//////////////////////////////////////////////////////////////////////////////
// autonegotiation state machine registered part
//////////////////////////////////////////////////////////////////////////////
always @(posedge ck, posedge reset)
pcs_an_present <= (reset) ? S_PCS_AN_STARTUP_RUN : pcs_an_next;
//////////////////////////////////////////////////////////////////////////////
// autonegotiation state machine - IEEE 802.3-2008 Clause 36
//////////////////////////////////////////////////////////////////////////////
always @*
begin
pcs_an_next = pcs_an_present;
xmit_CONFIGURATION_m_set = 0; xmit_DATA_m_set = 0; xmit_IDLE_m_set = 0;
mr_np_loaded_m_set = 0; mr_np_loaded_m_clr = 0;
mr_page_rx_m_set = 0; mr_page_rx_m_clr = 0;
mr_an_complete_m_set = 0; mr_an_complete_m_clr = 0;
mr_lp_adv_ability_set = 0; mr_lp_adv_ability_clr = 0;
tx_config_m_clr = 0; tx_config_ABILITY_m_set = 0;tx_config_ACK_m_set = 0;tx_config_NP_m_set = 0;
link_timer_m_start = 0; link_timer_m_inc = 0;
toggle_tx_adv_m_set = 0; toggle_tx_toggle_m_set = 0;
toggle_rx_m_set = 0; mr_lp_np_rx_m_set = 0; np_rx_m_set = 0; np_page_rx_m_set = 0;
resolve_priority_m_set = 0;
debug_an_restart_state = 0;
case (pcs_an_present)
S_PCS_AN_STARTUP_RUN:
begin
pcs_an_next = startup_enable ? S_PCS_AN_ENABLE: S_PCS_AN_STARTUP_RUN;
end
S_PCS_AN_ENABLE:
begin
mr_page_rx_m_clr = 1; mr_lp_adv_ability_clr = 1; mr_an_complete_m_clr = 1;
if (mr_an_enable)
begin
xmit_CONFIGURATION_m_set = 1; tx_config_m_clr = 1;
end
else xmit_IDLE_m_set = 1;
pcs_an_next = (mr_an_enable) ? S_PCS_AN_RESTART : S_PCS_AN_DISABLE_LINK_OK;
link_timer_m_start = mr_an_enable;
end
S_PCS_AN_RESTART:
begin
mr_np_loaded_m_clr = 1; tx_config_m_clr = 1; xmit_CONFIGURATION_m_set = 1;
pcs_an_next = (link_timer_done) ? S_PCS_AN_ABILITY_DETECT : S_PCS_AN_RESTART;
debug_an_restart_state = 1;
link_timer_m_inc = ~link_timer_done;
end
S_PCS_AN_DISABLE_LINK_OK:
begin
xmit_DATA_m_set = 1;
pcs_an_next = S_PCS_AN_DISABLE_LINK_OK;
end
S_PCS_AN_ABILITY_DETECT:
begin
toggle_tx_adv_m_set = 1; tx_config_ABILITY_m_set = 1;
pcs_an_next = (ability_match & rx_config_set) ? S_PCS_AN_ACKNOWLEDGE_DETECT : S_PCS_AN_ABILITY_DETECT;
mr_lp_adv_ability_set = (ability_match & rx_config_set);
end
S_PCS_AN_ACKNOWLEDGE_DETECT:
begin
tx_config_ACK_m_set = 1;
pcs_an_next = (acknowledge_match & consistency_match) ? S_PCS_AN_COMPLETE_ACKNOWLEDGE :
(acknowledge_match & ~consistency_match) ? S_PCS_AN_ENABLE :
(ability_match & rx_config_clr) ? S_PCS_AN_ENABLE : S_PCS_AN_ACKNOWLEDGE_DETECT;
link_timer_m_start = (acknowledge_match & consistency_match);
end
S_PCS_AN_COMPLETE_ACKNOWLEDGE:
begin
toggle_tx_toggle_m_set = 1; toggle_rx_m_set = 1; np_rx_m_set = 1; mr_page_rx_m_set = 1;
if (ability_match & rx_config_clr) pcs_an_next = S_PCS_AN_ENABLE;
else if (link_timer_done & (~ability_match | rx_config_set))
begin
link_timer_m_start = 1; pcs_an_next = S_PCS_AN_IDLE_DETECT;
end
else link_timer_m_inc = ~link_timer_done;
end
S_PCS_AN_IDLE_DETECT:
begin
xmit_IDLE_m_set = 1; resolve_priority_m_set = 1;
pcs_an_next = (ability_match & rx_config_clr) ? S_PCS_AN_ENABLE :
(idle_match & link_timer_done) ? S_PCS_AN_LINK_OK : S_PCS_AN_IDLE_DETECT;
link_timer_m_inc = ~link_timer_done;
end
S_PCS_AN_LINK_OK:
begin
xmit_DATA_m_set = 1; mr_an_complete_m_set = 1; resolve_priority_m_set = 1;
pcs_an_next = (ability_match | mr_restart_an) ? S_PCS_AN_ENABLE : S_PCS_AN_LINK_OK;
end
endcase
if (~sync_status) pcs_an_next = S_PCS_AN_ENABLE;
else if (mr_main_reset) pcs_an_next = S_PCS_AN_ENABLE;
else if (mr_restart_an) pcs_an_next = S_PCS_AN_ENABLE;
else if (rudi == `RUDI_INVALID) pcs_an_next = S_PCS_AN_ENABLE;
end
endmodule
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