Search is not available for this dataset
content
stringlengths 0
376M
|
|---|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity mux21_32 is
port (a: in std_logic_vector(0 to 31);
b: in std_logic_vector(0 to 31);
sel: in std_logic;
g: out std_logic_vector(0 to 31));
end mux21_32;
architecture m of mux21_32 is
begin
process(sel, a, b)
begin
if (sel = '0') then
g <= a;
else
g <= b;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package my_lib is
function f_log2 (
x : integer)
return natural;
end package;
package body my_lib is
function f_log2 (x : integer) return natural is
variable i : natural;
begin
i := 0;
while (2**i <= x) and i < 31 loop
i := i + 1;
end loop;
return i;
end function;
end package body;
|
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity sqrt_test is
end sqrt_test;
architecture behavior of sqrt_test is
-- Component declaration for the unit under test
-- inputs
signal clk,reset, din_valid,dout_ready: std_logic;
signal din: std_logic_vector(15 downto 0);
signal dout : std_logic_vector(7 downto 0);
constant clk_period: time := 20 ns;
begin
uut: entity work.sqrt port map(
clk => clk,
reset => reset,
din => din,
din_valid => din_valid,
dout_ready => dout_ready,
dout => dout
);
clk_process: process
begin
clk <= '0';
wait for clk_period/2; -- wait for 10ns
clk <= '1';
wait for clk_period/2;
end process;
-- stimulus process
stim_proc: process
begin
din_valid <= '0';
din <= (others=>'0');
reset <= '1';
wait for 30 ns;
reset <= '0';
-- value goes here
din <= X"0051";
din_valid <= '1';
wait for 20 ns;
din_valid <= '0';
wait for 500 ns;
assert false
report "Simulation complete"
severity failure;
end process;
end architecture;
|
<filename>hdl/libram.vhdl<gh_stars>10-100
-- Common RAM library package
-- For MIPS specific RAM package: see pkg_ram.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package ram is
-- Unconstrained 16 bit RAM initialization type
type ram16_init_t is array(natural range <>) of
unsigned(15 downto 0);
-- Unconstrained 32 bit RAM initialization type
type ram32_init_t is array(natural range <>) of
unsigned(31 downto 0);
component DPRAM16_init is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 16;
INIT_DATA : ram16_init_t;
SYN_RAMTYPE : string := "block_ram"
);
port (
clk : in std_logic;
-- Port A
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0)
);
end component DPRAM16_init;
component DPRAM16_init_ce is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 16;
INIT_DATA : ram16_init_t;
SYN_RAMTYPE : string := "block_ram"
);
port (
clk : in std_logic;
-- Port A
a_ce : in std_logic;
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_ce : in std_logic;
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0)
);
end component DPRAM16_init_ce;
component DPRAM16_init_hex_ce is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 16;
INIT_DATA : string := "mem.hex";
SYN_RAMTYPE : string := "block_ram"
);
port (
-- Port A
a_clk : in std_logic;
a_ce : in std_logic;
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_clk : in std_logic;
b_ce : in std_logic;
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0)
);
end component DPRAM16_init_hex_ce;
component DPRAM_init_hex is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 32;
INIT_DATA : string := "mem32.hex";
SYN_RAMTYPE : string := "block_ram"
);
port (
clk : in std_logic;
-- Port A
a_ce : in std_logic;
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_ce : in std_logic;
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0)
);
end component DPRAM_init_hex;
component DPRAM32_init is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 32;
INIT_DATA : ram32_init_t;
SYN_RAMTYPE : string := "block_ram"
);
port (
clk : in std_logic;
-- Port A
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0)
);
end component DPRAM32_init;
component DPRAM is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 16;
EN_BYPASS : boolean := false;
SYN_RAMTYPE : string := "block_ram"
);
port (
clk : in std_logic;
-- Port A
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0)
);
end component DPRAM;
component DPRAM_clk2
generic(
ADDR_W : natural := 6;
DATA_W : natural := 16;
EN_BYPASS : boolean := true;
SYN_RAMTYPE : string := "block_ram"
);
port(
a_clk : in std_logic;
-- Port A
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_clk : in std_logic;
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0)
);
end component;
component bram_2psync is
generic (
ADDR_W : natural := 6;
DATA_W : natural := 16;
SYN_RAMTYPE : string := "block_ram"
);
port (
-- Port A
a_we : in std_logic;
a_addr : in unsigned(ADDR_W-1 downto 0);
a_write : in unsigned(DATA_W-1 downto 0);
a_read : out unsigned(DATA_W-1 downto 0);
-- Port B
b_we : in std_logic;
b_addr : in unsigned(ADDR_W-1 downto 0);
b_write : in unsigned(DATA_W-1 downto 0);
b_read : out unsigned(DATA_W-1 downto 0);
clk : in std_logic
);
end component bram_2psync;
end package;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Adder is
port
(
nibble1, nibble2 : in unsigned(3 downto 0);
sum : out unsigned(3 downto 0);
carry_out : out std_logic
);
end entity Adder;
architecture Behavioral of Adder is
signal temp : unsigned(4 downto 0);
begin
temp <= ("0" & nibble1) + nibble2;
-- OR use the following syntax:
-- temp <= ('0' & nibble1) + ('0' & nibble2);
sum <= temp(3 downto 0);
carry_out <= temp(4);
end architecture Behavioral;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:50:20 01/29/2021
-- Design Name:
-- Module Name: /mnt/hgfs/patrick/Dropbox/University-College-London/UCL-CS/Year-3/Research-Project/cpu-fpga-nwofle/hw/dns-anomaly/test.vhd
-- Project Name: dns-anomaly
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: main
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test IS
END test;
ARCHITECTURE behavior OF test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT main
PORT (
clk : IN STD_LOGIC;
E_RX_CLK : IN STD_LOGIC;
E_RX_DV : IN STD_LOGIC;
E_RXD : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
E_RX_ER : IN STD_LOGIC;
E_TX_CLK : IN STD_LOGIC;
E_TX_EN : OUT STD_LOGIC;
E_TXD : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
E_TX_ER : OUT STD_LOGIC;
LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
--Inputs
SIGNAL clk : STD_LOGIC := '0';
SIGNAL E_RX_CLK : STD_LOGIC := '0';
SIGNAL E_RX_DV : STD_LOGIC := '0';
SIGNAL E_RXD : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL E_RX_ER : STD_LOGIC := '0';
SIGNAL E_TX_CLK : STD_LOGIC := '0';
--Outputs
SIGNAL E_TX_EN : STD_LOGIC;
SIGNAL E_TXD : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL E_TX_ER : STD_LOGIC;
SIGNAL LED : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- Clock period definitions
CONSTANT clk_period : TIME := 10 ns;
CONSTANT E_RX_CLK_period : TIME := 20 ns;
CONSTANT E_TX_CLK_period : TIME := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : main PORT MAP(
clk => clk,
E_RX_CLK => E_RX_CLK,
E_RX_DV => E_RX_DV,
E_RXD => E_RXD,
E_RX_ER => E_RX_ER,
E_TX_CLK => E_TX_CLK,
E_TX_EN => E_TX_EN,
E_TXD => E_TXD,
E_TX_ER => E_TX_ER,
LED => LED
);
-- Clock process definitions
clk_process : PROCESS
BEGIN
clk <= '0';
WAIT FOR clk_period/2;
clk <= '1';
WAIT FOR clk_period/2;
END PROCESS;
E_RX_CLK_process : PROCESS
BEGIN
E_RX_CLK <= '0';
WAIT FOR E_RX_CLK_period/2;
E_RX_CLK <= '1';
WAIT FOR E_RX_CLK_period/2;
END PROCESS;
E_TX_CLK_process : PROCESS
BEGIN
E_TX_CLK <= '0';
WAIT FOR E_TX_CLK_period/2;
E_TX_CLK <= '1';
WAIT FOR E_TX_CLK_period/2;
END PROCESS;
-- Stimulus process
stim_proc : PROCESS
BEGIN
-- hold reset state for 100 ns.
WAIT FOR 100 ns;
WAIT FOR clk_period * 10;
-- insert stimulus here
WAIT;
END PROCESS;
END;
|
<reponame>Domipheus/ArtyS7
----------------------------------------------------------------------------------
-- Company: Domipheus Labs
-- Engineer: Colin "domipheus" Riley
--
-- Create Date: 26.04.2018 23:29:09
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name: Arty S7 HDMI out to PMod A example.
-- Target Devices: Arty S7 XC7S50
-- Tool Versions:
-- Description:
--
-- Dependencies: VGA/TMDS/DVID code from Mike Field <<EMAIL>>
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity top is
Port (
CLK100MHZ : in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC_VECTOR (3 downto 0);
hdmi_out_p : out STD_LOGIC_VECTOR(3 downto 0);
hdmi_out_n : out STD_LOGIC_VECTOR(3 downto 0)
);
end top;
architecture Behavioral of top is
COMPONENT clocking
generic (
in_mul : natural := 10;
pix_div : natural := 30;
pix5x_div : natural := 10
);
PORT (
I_unbuff_clk : in STD_LOGIC;
O_buff_clkpixel : out STD_LOGIC;
O_buff_clk5xpixel : out STD_LOGIC;
O_buff_clk5xpixelinv : out STD_LOGIC
);
END COMPONENT;
COMPONENT vga_gen
generic (
hRez : natural := 1280;
hStartSync : natural := 1280+72;
hEndSync : natural := 1280+72+80;
hMaxCount : natural := 1280+72+80+216;
hsyncActive : std_logic := '0';
vRez : natural := 720;
vStartSync : natural := 720+3;
vEndSync : natural := 720+3+5;
vMaxCount : natural := 720+3+5+22;
vsyncActive : std_logic := '1';
prefetch_idx:natural := 8
);
PORT(
pixel_clock : in std_logic;
pixel_h : out STD_LOGIC_VECTOR(11 downto 0);
pixel_v : out STD_LOGIC_VECTOR(11 downto 0);
pixel_h_pref : out STD_LOGIC_VECTOR(11 downto 0) := (others => '0');
pixel_v_pref : out STD_LOGIC_VECTOR(11 downto 0) := (others => '0');
blank_pref : OUT std_logic;
blank : OUT std_logic;
hsync : OUT std_logic;
vsync : OUT std_logic
);
END COMPONENT;
COMPONENT dvid
PORT(
clk : IN std_logic;
clk_n : IN std_logic;
clk_pixel: IN std_logic;
red_p : IN std_logic_vector(7 downto 0);
green_p : IN std_logic_vector(7 downto 0);
blue_p : IN std_logic_vector(7 downto 0);
blank : IN std_logic;
hsync : IN std_logic;
vsync : IN std_logic;
red_s : OUT std_logic;
green_s : OUT std_logic;
blue_s : OUT std_logic;
clock_s : OUT std_logic
);
END COMPONENT;
-- Counter for LEDs
signal count: unsigned(31 downto 0) := X"00000000";
-- Clock engine
signal cEng_pixel_720 : std_logic;
signal cEng_5xpixel_720 : std_logic;
signal cEng_5xpixel_inv_720 : std_logic;
-- Vga timing
signal pixel_h : STD_LOGIC_VECTOR(11 downto 0);
signal pixel_v : STD_LOGIC_VECTOR(11 downto 0);
signal blank : std_logic;
signal hsync : std_logic;
signal vsync : std_logic;
-- Pixel colour data
signal red_ram_p : std_logic_vector(7 downto 0) := (others => '0');
signal green_ram_p : std_logic_vector(7 downto 0) := (others => '0');
signal blue_ram_p : std_logic_vector(7 downto 0) := (others => '0');
-- TMDS
signal red_s : std_logic;
signal green_s : std_logic;
signal blue_s : std_logic;
signal clock_s : std_logic;
begin
-- increment the counter each 100MHz cycle
process(CLK100MHZ)
begin
if rising_edge(CLK100MHZ) then
count <= count + 1;
end if;
end process;
-- assign LEDs to bits far enough up the counter as to see
-- them count.
led(0) <= count(24);
led(1) <= count(25);
led(2) <= count(26);
led(3) <= count(27);
-- Gen 75Mhz pixel clock generation
-- Technically, 720p should be 74.25MHz. 75 generally works on monitors. YMMV.
clock_eng_1280_720A: clocking
generic map (
in_mul => 9,
pix_div => 12,
pix5x_div => 2
)
port map (
I_unbuff_clk => CLK100MHZ,
O_buff_clkpixel => cEng_pixel_720,
O_buff_clk5xpixel => open,
O_buff_clk5xpixelinv => open
);
-- Gen 375Mhz 5xpixel and 5xpixel inverted clock generation
clock_eng_1280_720B: clocking
generic map (
in_mul => 10,
pix_div => 1,
pix5x_div => 2
)
port map (
I_unbuff_clk => cEng_pixel_720,
O_buff_clkpixel => open,
O_buff_clk5xpixel => cEng_5xpixel_720,
O_buff_clk5xpixelinv => cEng_5xpixel_inv_720
);
-- This generates controls and offsets required for a fixed resolution
-- We don't need the _pref 'prefetch' signals here - they can be used in
-- conjunction with e.g. my character generator to prefetch glyph rows.
-- Default to 1280x720x60Hz. You can modify the below values, and clock,
-- to output different resolutions.
Inst_vga_gen: vga_gen
generic map (
hRez => 1280,
hStartSync => 1280+72,
hEndSync => 1280+72+80,
hMaxCount => 1280+72+80+216,
hsyncActive => '0',
vRez => 720,
vStartSync => 720+3,
vEndSync => 720+3+5,
vMaxCount => 720+3+5+22,
vsyncActive => '1'
)
PORT MAP(
pixel_clock => cEng_pixel_720,
pixel_h => pixel_h,
pixel_v => pixel_v,
pixel_h_pref => open,
pixel_v_pref => open,
blank_pref => open,
blank => blank,
hsync => hsync,
vsync => vsync
);
-- Colour pattern generation based on horiz/vert location
red_ram_p <= std_logic_vector(signed( count(28 downto 21)) + signed( pixel_h(7 downto 0)));
green_ram_p <= std_logic_vector(signed( count(28 downto 21)) + signed( pixel_v(7 downto 0)));
blue_ram_p <= std_logic_vector(count(28 downto 21));
-- TMDS signal generation
-- This takes pixel colour values and synd data, generating the
-- 10-bit coding.
dvid_1: dvid PORT MAP(
clk => cEng_5xpixel_720,
clk_n => cEng_5xpixel_inv_720,
clk_pixel => cEng_pixel_720,
red_p => red_ram_p,
green_p => green_ram_p,
blue_p => blue_ram_p,
blank => blank,
hsync => hsync,
vsync => vsync,
-- outputs to TMDS drivers
red_s => red_s,
green_s => green_s,
blue_s => blue_s,
clock_s => clock_s
);
-- Differential output buffers
OBUFDS_blue : OBUFDS port map ( O => hdmi_out_p(0), OB => hdmi_out_n(0), I => blue_s );
OBUFDS_green : OBUFDS port map ( O => hdmi_out_p(1), OB => hdmi_out_n(1), I => green_s );
OBUFDS_red : OBUFDS port map ( O => hdmi_out_p(2), OB => hdmi_out_n(2), I => red_s );
OBUFDS_clock : OBUFDS port map ( O => hdmi_out_p(3), OB => hdmi_out_n(3), I => clock_s );
end Behavioral;
|
<gh_stars>0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Reverse_tb IS
END Reverse_tb;
ARCHITECTURE behavior OF Reverse_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Reverse
PORT(
a : IN std_logic_vector(7 downto 0);
y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal y : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Reverse PORT MAP (
a => a,
y => y
);
-- Stimulus process
stim_proc: process
begin
a <= "10000000";
wait for 200ns;
a <= "00000001";
wait for 200ns;
a <= "10101010";
wait for 200ns;
a <= "00001111";
wait for 200ns;
a <= "10000001";
wait for 200ns;
a <= "00011000";
wait for 200ns;
end process;
END;
|
-------------------------------------------------------------------------------
-- Title : Floating-Point Non-Computational Operations Unit
-- Project :
-------------------------------------------------------------------------------
-- File : fp_noncomp.vhd
-- Author : <NAME> <<EMAIL>>
-- Company : Integrated Systems Laboratory, ETH Zurich
-- Created : 2018-02-14
-- Last update: 2018-04-18
-- Platform : ModelSim (simulation), Synopsys (synthesis)
-- Standard : VHDL'08
-------------------------------------------------------------------------------
-- Description: Parametric floating-point comparison unit.
-- Supported operations from fpnew_pkg.fpOp_t:
-- - SGNJ
-- - MINMAX
-- - CMP
-- - CLASS
-------------------------------------------------------------------------------
-- Copyright 2018 ETH Zurich and University of Bologna.
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the "License"); you may not use this file except in
-- compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-- or agreed to in writing, software, hardware and materials distributed under
-- this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-- CONDITIONS OF ANY KIND, either express or implied. See the License for the
-- specific language governing permissions and limitations under the License.
-------------------------------------------------------------------------------
library IEEE, work;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.fpnew_pkg.all;
use work.fpnew_comps_pkg.all;
entity fp_noncomp is
generic (
EXP_BITS : natural := 5;
MAN_BITS : natural := 10;
LATENCY : natural := 0;
TAG_WIDTH : natural := 0);
port (
Clk_CI : in std_logic;
Reset_RBI : in std_logic;
---------------------------------------------------------------------------
A_DI, B_DI : in std_logic_vector(EXP_BITS+MAN_BITS downto 0);
ABox_SI, BBox_SI : in std_logic;
RoundMode_SI : in rvRoundingMode_t;
Op_SI : in fpOp_t;
OpMod_SI : in std_logic;
VectorialOp_SI : in std_logic;
Tag_DI : in std_logic_vector(TAG_WIDTH-1 downto 0);
---------------------------------------------------------------------------
InValid_SI : in std_logic;
InReady_SO : out std_logic;
Flush_SI : in std_logic;
---------------------------------------------------------------------------
Z_DO : out std_logic_vector(EXP_BITS+MAN_BITS downto 0);
Status_DO : out rvStatus_t;
Tag_DO : out std_logic_vector(TAG_WIDTH-1 downto 0);
UnpackClass_SO : out std_logic;
Zext_SO : out std_logic;
---------------------------------------------------------------------------
OutValid_SO : out std_logic;
OutReady_SI : in std_logic);
end entity fp_noncomp;
architecture rtl of fp_noncomp is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant MAXEXP : unsigned(EXP_BITS-1 downto 0) := MAXEXP(EXP_BITS);
-- The quiet bit index is the topmost bit of the mantissa of a NaN value
constant QUIETBIT : natural := MAN_BITS-1;
-- Bit-Patterns of special values, only read from these!
signal INFEXP : std_logic_vector(EXP_BITS-1 downto 0);
signal INFMANT : std_logic_vector(MAN_BITS-1 downto 0);
-----------------------------------------------------------------------------
-- Type Definitions
-----------------------------------------------------------------------------
--! @brief Non-computational operation groups
--! @details Enumerators for indexing arrays that hold values depending on
--! the operation group currently executed.
type nonCompOpGroup_t is (SGNJ, MINMAX, CMP, CLASS);
--! @brief Array of output words indexed by operation
--! @details An output word for each operation in this unit. Addressable by
--! enumerators from nonCompOpGroup_t corresponding to the operation classes.
type resultArray_t is array (nonCompOpGroup_t) of std_logic_vector(Z_DO'range);
--! @brief Array of status flags indexed by operation
--! @details An fflags word for each operation in this unit. Addressable by
--! enumerators from nonCompOpGroup_t corresponding to the operation classes.
type statusArray_t is array (nonCompOpGroup_t) of rvStatus_t;
--! @brief Array of std_logic indexed by operation
--! @details A bit for each operation in this unit. Addressable by
--! enumerators from nonCompOpGroup_t corresponding to the operation classes.
type logicArray_t is array (nonCompOpGroup_t) of std_logic;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
-- Provide aliased signal names for parts of input FP numbers
alias SignA_DI : std_logic is A_DI(A_DI'high);
alias SignB_DI : std_logic is B_DI(B_DI'high);
alias AbsA_DI : std_logic_vector(EXP_BITS+MAN_BITS-1 downto 0)
is A_DI(EXP_BITS+MAN_BITS-1 downto 0);
alias AbsB_DI : std_logic_vector(EXP_BITS+MAN_BITS-1 downto 0)
is B_DI(EXP_BITS+MAN_BITS-1 downto 0);
alias ExpA_DI : std_logic_vector(EXP_BITS-1 downto 0)
is A_DI(EXP_BITS+MAN_BITS-1 downto MAN_BITS);
alias ExpB_DI : std_logic_vector(EXP_BITS-1 downto 0)
is B_DI(EXP_BITS+MAN_BITS-1 downto MAN_BITS);
alias MantA_DI : std_logic_vector(MAN_BITS-1 downto 0)
is A_DI(MAN_BITS-1 downto 0);
alias MantB_DI : std_logic_vector(MAN_BITS-1 downto 0)
is B_DI(MAN_BITS-1 downto 0);
-- FP classification signals
signal IsNormalA_S, IsNormalB_S : boolean;
signal IsInfA_S, IsInfB_S : boolean;
signal IsNaNA_S, IsNaNB_S : boolean;
signal IsZeroA_S, IsZeroB_S : boolean;
signal SignalingNaN_S, SignalingNaNA_S : boolean;
signal InputInf_S, InputNaN_S : boolean;
-- Classification
signal ClassResult_D : rvClassBit_t;
signal VecClassBlock_D : vecClassBlock_t;
signal ScalarClassRes_D, VecClassRes_D : std_logic_vector(Z_DO'range);
-- Comparator Outputs
signal OperandsEqual_S, OperandASmaller_S : boolean;
-- Operation Select
signal OpGroup_S : nonCompOpGroup_t;
-- Results of operations
signal ResArray_D : resultArray_t;
signal ZextArray_S : logicArray_t;
-- RISC-V FP FLAGS
signal StatArray_D : statusArray_t;
-- Final result (pre-pipelining)
signal Result_D : std_logic_vector(Z_DO'range);
signal Status_D : rvStatus_t;
-- Control information about the output
signal UnpackClass_S : std_logic;
signal Zext_S : std_logic;
signal TagInt_D, TagIntPiped_D : std_logic_vector(TAG_WIDTH+1 downto 0);
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Special Value Constant Signals
-----------------------------------------------------------------------------
-- Infinity and NaN constants
INFEXP <= (others => '1');
INFMANT <= (others => '0');
-----------------------------------------------------------------------------
-- Input Classification
-----------------------------------------------------------------------------
-- Normal if non-zero exponents
IsNormalA_S <= unsigned(ExpA_DI) /= 0;
IsNormalB_S <= unsigned(ExpB_DI) /= 0;
-- Infinities have all-ones exponents and zero mantissa
-- Improperly boxed operands are treated as canonical NaNs
IsInfA_S <= ExpA_DI = INFEXP and MantA_DI = INFMANT;
IsInfB_S <= ExpB_DI = INFEXP and MantB_DI = INFMANT;
-- Nans have all-ones exponents and non-zero mantissa
IsNaNA_S <= (unsigned(ExpA_DI) = MAXEXP and unsigned(MantA_DI) /= 0) or ABox_SI = '0';
IsNaNB_S <= (unsigned(ExpB_DI) = MAXEXP and unsigned(MantB_DI) /= 0) or BBox_SI = '0';
-- Zeroes are encoded by all-zero eponent and mantissa
IsZeroA_S <= unsigned(std_logic_vector'(ExpA_DI & MantA_DI)) = 0;
IsZeroB_S <= unsigned(std_logic_vector'(ExpB_DI & MantB_DI)) = 0;
-- An input is Inf
InputInf_S <= IsInfA_S or IsInfB_S;
-- An input is NaN
InputNaN_S <= IsNaNA_S or IsNaNB_S;
-- Detect a signaling NaN at the inputs
-- Improperly boxed operands are treated as canonical NaNs
SignalingNaNA_S <= (IsNaNA_S and ABox_SI = '1' and MantA_DI(QUIETBIT) = '0');
SignalingNaN_S <= SignalingNaNA_S or (IsNaNB_S and BBox_SI = '1' and MantB_DI(QUIETBIT) = '0');
-- Assign current operation group for later output selection
with Op_SI select
OpGroup_S <=
CLASS when CLASS,
CMP when CMP,
MINMAX when MINMAX,
SGNJ when SGNJ,
SGNJ when others;
-----------------------------------------------------------------------------
-- Classification
-----------------------------------------------------------------------------
--! @brief Classification of input A
--! @details Generate the RISC-V classification block as well as the
--! vectorial classification block from input operand A
p_class : process (all) is
begin -- process p_class
-- Sign into Vectorial Class Block
VecClassBlock_D.Sign <= SignA_DI;
-- NaN cases
if IsNaNA_S then
if SignalingNaNA_S then
ClassResult_D <= SNAN;
VecClassBlock_D.Class <= SNAN;
else
ClassResult_D <= QNAN;
VecClassBlock_D.Class <= QNAN;
end if;
-- negative cases
elsif SignA_DI = '1' then
if IsInfA_S then
ClassResult_D <= NEGINF;
VecClassBlock_D.Class <= INF;
elsif IsZeroA_S then
ClassResult_D <= NEGZERO;
VecClassBlock_D.Class <= ZERO;
elsif IsNormalA_S then
ClassResult_D <= NEGNORM;
VecClassBlock_D.Class <= NORM;
else
ClassResult_D <= NEGSUBNORM;
VecClassBlock_D.Class <= SUBNORM;
end if;
-- positive cases
else
if IsInfA_S then
ClassResult_D <= POSINF;
VecClassBlock_D.Class <= INF;
elsif IsZeroA_S then
ClassResult_D <= POSZERO;
VecClassBlock_D.Class <= ZERO;
elsif IsNormalA_S then
ClassResult_D <= POSNORM;
VecClassBlock_D.Class <= NORM;
else
ClassResult_D <= POSSUBNORM;
VecClassBlock_D.Class <= SUBNORM;
end if;
end if;
ScalarClassRes_D <= (others => '0');
ScalarClassRes_D(3 downto 0) <= to_slv(ClassResult_D); -- packed slv
VecClassRes_D <= (others => '0');
VecClassRes_D(7 downto 0) <= to_slv(VecClassBlock_D);
end process p_class;
-- Scalar class result is sent out packed into the enumerated representation,
-- Vectorial class result is unpacked right here
ResArray_D(CLASS) <= VecClassRes_D when VectorialOp_SI = '1' else
ScalarClassRes_D;
-- Classification never raises exceptions
StatArray_D(CLASS) <= (others => '0');
-- Output is integer reg, zero extend
ZextArray_S(CLASS) <= '1';
-----------------------------------------------------------------------------
-- Sign Injection - operation is encoded in RoundMode_SI:
-- RNE = SGNJ, RTZ = SGNJN, RDN = SGNJX, RUP = Passthrough (no NaN-box check)
-- OpMod_SI enables sign-extension of result (for storing to integer regfile)
-----------------------------------------------------------------------------
p_signInjections : process (all) is
variable SgnjResult_D : std_logic_vector(A_DI'range);
variable SignA_D, SignB_D : std_logic;
begin
-- Assign A or the canonical NaN to the Reuslt first
if RoundMode_SI = RUP then
SgnjResult_D := A_DI;
elsif ABox_SI = '0' then
SgnjResult_D := NAN(EXP_BITS, MAN_BITS);
else
SgnjResult_D := A_DI;
end if;
-- In case of improper boxing on input operands, they get can. NaN sign (0)
SignA_D := SignA_DI and ABox_SI;
SignB_D := SignB_DI and BBox_SI;
-- Do the actual sign injection
if RoundMode_SI = RNE then
SgnjResult_D(SgnjResult_D'high) := SignB_D;
elsif RoundMode_SI = RTZ then
SgnjResult_D(SgnjResult_D'high) := not SignB_D;
elsif RoundMode_SI = RDN then
SgnjResult_D(SgnjResult_D'high) := SignA_D xor SignB_D;
end if;
ResArray_D(SGNJ) <= SgnjResult_D;
end process p_signInjections;
-- Sign Injection never raises exceptions
StatArray_D(SGNJ) <= (others => '0');
-- Sign extend if selected by OpMod_SI
ZextArray_S(SGNJ) <= OpMod_SI and (not ResArray_D(SGNJ)(Z_DO'high));
-----------------------------------------------------------------------------
-- Comparators
-----------------------------------------------------------------------------
-- All other ops need the comparator outputs for their result
OperandsEqual_S <= (signed(A_DI) = signed(B_DI)) or (IsZeroA_S and IsZeroB_S);
OperandASmaller_S <= (signed(A_DI) < signed(B_DI)) xor (SignA_DI and SignB_DI) = '1';
-----------------------------------------------------------------------------
-- Minimum/Maximum - operation is encoded in RoundMode_SI:
-- RNE = MIN, RTZ = MAX
-----------------------------------------------------------------------------
--! @brief Handle MIN/MAX operations and their special cases
p_minMax : process (all) is
begin -- process p_minMax
-- Default assignment: clear exception flags
StatArray_D(MINMAX) <= (others => '0');
-- Min/Max use quiet comparisons - only SNAN are invalid
StatArray_D(MINMAX)(NV) <= to_sl(SignalingNaN_S);
-- Both NaN inputs cause a NaN output
if (IsNaNA_S and IsNaNB_S) then
ResArray_D(MINMAX) <= NAN(EXP_BITS, MAN_BITS); -- return canonical qnan
-- If one operand is QNaN, the non-NaN operand is returned
elsif IsNaNA_S then
ResArray_D(MINMAX) <= B_DI;
elsif IsNaNB_S then
ResArray_D(MINMAX) <= A_DI;
-- A is the desired output when smaller and min or larger and max
elsif ((OperandASmaller_S and RoundMode_SI = RNE)
or (not OperandASmaller_S and RoundMode_SI = RTZ)) then
ResArray_D(MINMAX) <= A_DI;
-- B is the desired output when smaller and min or larger and max
elsif ((not OperandASmaller_S and RoundMode_SI = RNE)
or (OperandASmaller_S and RoundMode_SI = RTZ)) then
ResArray_D(MINMAX) <= B_DI;
-- otherwise no valid op and optimize away
else
ResArray_D(MINMAX) <= (others => '0');
end if;
end process p_minMax;
-- Result is floating-point number, always NaN-box
ZextArray_S(MINMAX) <= '0';
-----------------------------------------------------------------------------
-- Comparisons - operation is encoded in RoundMode_SI:
-- RNE = LE, RTZ = LT, RDN = EQ
-- OpMod_SI inverts boolean outputs
-----------------------------------------------------------------------------
--! @brief Handle Comparisons and their special cases
p_cmp : process (all) is
begin -- process p_comp
-- Default assignment: FALSE and clear exception flags
ResArray_D(CMP) <= (others => '0');
StatArray_D(CMP) <= (others => '0');
-- Signaling NaNs are always illegal
if SignalingNaN_S then
-- result is 0 (false), already set
StatArray_D(CMP)(NV) <= '1'; -- raise invalid exception
-- LE and LT perform signalling comparisons: any NaN input is invalid
elsif (RoundMode_SI = RNE or RoundMode_SI = RTZ) and InputNaN_S then
-- result is 0 (false), already set
StatArray_D(CMP)(NV) <= '1'; -- raise invalid exception
-- Less or Equal
elsif RoundMode_SI = RNE then
ResArray_D(CMP)(0) <= to_sl(OperandASmaller_S or OperandsEqual_S) xor OpMod_SI;
-- Less Than -> make sure -0 does not compare less than +0
elsif RoundMode_SI = RTZ then
ResArray_D(CMP)(0) <= to_sl(OperandASmaller_S and not OperandsEqual_S) xor OpMod_SI;
-- Equals
elsif RoundMode_SI = RDN and not InputNaN_S then
ResArray_D(CMP)(0) <= to_sl(OperandsEqual_S) xor OpMod_SI;
-- Equals with NaNs compares to false -> not equals on ANY NaN is actually TRUE!
elsif InputNaN_S then
ResArray_D(CMP)(0) <= OpMod_SI;
-- otherwise no valid op and optimize away
else
ResArray_D(CMP) <= (others => '0');
end if;
end process p_cmp;
-- Result is boolean in integer register, always zero-extend
ZextArray_S(CMP) <= '1';
-----------------------------------------------------------------------------
-- Pipeline registers at the outputs of the unit
-----------------------------------------------------------------------------
-- We're outputting the enumerated classification for later unpacking since
-- the scalar classification block is 10 bits wide which breaks FP8 here
UnpackClass_S <= '1' when OpGroup_S = CLASS and VectorialOp_SI = '0' else
'0';
-- Output should be zero-extended downstream if it doesn't contain FP values
Zext_S <= ZextArray_S(OpGroup_S);
-- Select output according to operation group and feed into pipeline
Result_D <= ResArray_D(OpGroup_S);
Status_D <= StatArray_D(OpGroup_S);
-- Pipe through the classification block indicator as well
TagInt_D <= UnpackClass_S & Zext_S & Tag_DI;
i_fp_pipe : fp_pipe
generic map (
WIDTH => EXP_BITS+MAN_BITS+1,
LATENCY => LATENCY,
TAG_WIDTH => TAG_WIDTH+2)
port map (
Clk_CI => Clk_CI,
Reset_RBI => Reset_RBI,
Result_DI => Result_D,
Status_DI => Status_D,
Tag_DI => TagInt_D,
InValid_SI => InValid_SI,
InReady_SO => InReady_SO,
Flush_SI => Flush_SI,
ResultPiped_DO => Z_DO,
StatusPiped_DO => Status_DO,
TagPiped_DO => TagIntPiped_D,
OutValid_SO => OutValid_SO,
OutReady_SI => OutReady_SI);
UnpackClass_SO <= TagIntPiped_D(TagIntPiped_D'high);
Zext_SO <= TagIntPiped_D(TagIntPiped_D'high-1);
Tag_DO <= TagIntPiped_D(Tag_DO'range);
end architecture rtl;
|
-- Copyright 2018-2019 Delft University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- This file was generated by Fletchgen. Modify this file at your own risk.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.Array_pkg.all;
entity Kernel_rematch004 is
generic (
INDEX_WIDTH : integer := 32;
TAG_WIDTH : integer := 1;
REMATCH004_IN_BUS_ADDR_WIDTH : integer := 64;
REMATCH004_IN_BUS_DATA_WIDTH : integer := 512;
REMATCH004_IN_BUS_LEN_WIDTH : integer := 8;
REMATCH004_IN_BUS_BURST_STEP_LEN : integer := 1;
REMATCH004_IN_BUS_BURST_MAX_LEN : integer := 16
);
port (
bcd_clk : in std_logic;
bcd_reset : in std_logic;
kcd_clk : in std_logic;
kcd_reset : in std_logic;
rematch004_in_valid : out std_logic;
rematch004_in_ready : in std_logic;
rematch004_in_dvalid : out std_logic;
rematch004_in_last : out std_logic;
rematch004_in_length : out std_logic_vector(31 downto 0);
rematch004_in_count : out std_logic_vector(0 downto 0);
rematch004_in_chars_valid : out std_logic;
rematch004_in_chars_ready : in std_logic;
rematch004_in_chars_dvalid : out std_logic;
rematch004_in_chars_last : out std_logic;
rematch004_in_chars : out std_logic_vector(31 downto 0);
rematch004_in_chars_count : out std_logic_vector(2 downto 0);
rematch004_in_bus_rreq_valid : out std_logic;
rematch004_in_bus_rreq_ready : in std_logic;
rematch004_in_bus_rreq_addr : out std_logic_vector(REMATCH004_IN_BUS_ADDR_WIDTH-1 downto 0);
rematch004_in_bus_rreq_len : out std_logic_vector(REMATCH004_IN_BUS_LEN_WIDTH-1 downto 0);
rematch004_in_bus_rdat_valid : in std_logic;
rematch004_in_bus_rdat_ready : out std_logic;
rematch004_in_bus_rdat_data : in std_logic_vector(REMATCH004_IN_BUS_DATA_WIDTH-1 downto 0);
rematch004_in_bus_rdat_last : in std_logic;
rematch004_in_cmd_valid : in std_logic;
rematch004_in_cmd_ready : out std_logic;
rematch004_in_cmd_firstIdx : in std_logic_vector(INDEX_WIDTH-1 downto 0);
rematch004_in_cmd_lastIdx : in std_logic_vector(INDEX_WIDTH-1 downto 0);
rematch004_in_cmd_ctrl : in std_logic_vector(REMATCH004_IN_BUS_ADDR_WIDTH*2-1 downto 0);
rematch004_in_cmd_tag : in std_logic_vector(TAG_WIDTH-1 downto 0);
rematch004_in_unl_valid : out std_logic;
rematch004_in_unl_ready : in std_logic;
rematch004_in_unl_tag : out std_logic_vector(TAG_WIDTH-1 downto 0)
);
end entity;
architecture Implementation of Kernel_rematch004 is
signal in_inst_cmd_valid : std_logic;
signal in_inst_cmd_ready : std_logic;
signal in_inst_cmd_firstIdx : std_logic_vector(INDEX_WIDTH-1 downto 0);
signal in_inst_cmd_lastIdx : std_logic_vector(INDEX_WIDTH-1 downto 0);
signal in_inst_cmd_ctrl : std_logic_vector(REMATCH004_IN_BUS_ADDR_WIDTH*2-1 downto 0);
signal in_inst_cmd_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal in_inst_unl_valid : std_logic;
signal in_inst_unl_ready : std_logic;
signal in_inst_unl_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal in_inst_bus_rreq_valid : std_logic;
signal in_inst_bus_rreq_ready : std_logic;
signal in_inst_bus_rreq_addr : std_logic_vector(REMATCH004_IN_BUS_ADDR_WIDTH-1 downto 0);
signal in_inst_bus_rreq_len : std_logic_vector(REMATCH004_IN_BUS_LEN_WIDTH-1 downto 0);
signal in_inst_bus_rdat_valid : std_logic;
signal in_inst_bus_rdat_ready : std_logic;
signal in_inst_bus_rdat_data : std_logic_vector(REMATCH004_IN_BUS_DATA_WIDTH-1 downto 0);
signal in_inst_bus_rdat_last : std_logic;
signal in_inst_out_valid : std_logic_vector(1 downto 0);
signal in_inst_out_ready : std_logic_vector(1 downto 0);
signal in_inst_out_data : std_logic_vector(67 downto 0);
signal in_inst_out_dvalid : std_logic_vector(1 downto 0);
signal in_inst_out_last : std_logic_vector(1 downto 0);
begin
in_inst : ArrayReader
generic map (
BUS_ADDR_WIDTH => REMATCH004_IN_BUS_ADDR_WIDTH,
BUS_DATA_WIDTH => REMATCH004_IN_BUS_DATA_WIDTH,
BUS_LEN_WIDTH => REMATCH004_IN_BUS_LEN_WIDTH,
BUS_BURST_STEP_LEN => REMATCH004_IN_BUS_BURST_STEP_LEN,
BUS_BURST_MAX_LEN => REMATCH004_IN_BUS_BURST_MAX_LEN,
INDEX_WIDTH => INDEX_WIDTH,
CFG => "listprim(8;epc=4)",
CMD_TAG_ENABLE => true,
CMD_TAG_WIDTH => TAG_WIDTH
)
port map (
bcd_clk => bcd_clk,
bcd_reset => bcd_reset,
kcd_clk => kcd_clk,
kcd_reset => kcd_reset,
cmd_valid => in_inst_cmd_valid,
cmd_ready => in_inst_cmd_ready,
cmd_firstIdx => in_inst_cmd_firstIdx,
cmd_lastIdx => in_inst_cmd_lastIdx,
cmd_ctrl => in_inst_cmd_ctrl,
cmd_tag => in_inst_cmd_tag,
unl_valid => in_inst_unl_valid,
unl_ready => in_inst_unl_ready,
unl_tag => in_inst_unl_tag,
bus_rreq_valid => in_inst_bus_rreq_valid,
bus_rreq_ready => in_inst_bus_rreq_ready,
bus_rreq_addr => in_inst_bus_rreq_addr,
bus_rreq_len => in_inst_bus_rreq_len,
bus_rdat_valid => in_inst_bus_rdat_valid,
bus_rdat_ready => in_inst_bus_rdat_ready,
bus_rdat_data => in_inst_bus_rdat_data,
bus_rdat_last => in_inst_bus_rdat_last,
out_valid => in_inst_out_valid,
out_ready => in_inst_out_ready,
out_data => in_inst_out_data,
out_dvalid => in_inst_out_dvalid,
out_last => in_inst_out_last
);
rematch004_in_valid <= in_inst_out_valid(0);
rematch004_in_chars_valid <= in_inst_out_valid(1);
in_inst_out_ready(0) <= rematch004_in_ready;
in_inst_out_ready(1) <= rematch004_in_chars_ready;
rematch004_in_dvalid <= in_inst_out_dvalid(0);
rematch004_in_chars_dvalid <= in_inst_out_dvalid(1);
rematch004_in_last <= in_inst_out_last(0);
rematch004_in_chars_last <= in_inst_out_last(1);
rematch004_in_length <= in_inst_out_data(31 downto 0);
rematch004_in_count <= in_inst_out_data(32 downto 32);
rematch004_in_chars <= in_inst_out_data(64 downto 33);
rematch004_in_chars_count <= in_inst_out_data(67 downto 65);
rematch004_in_bus_rreq_valid <= in_inst_bus_rreq_valid;
in_inst_bus_rreq_ready <= rematch004_in_bus_rreq_ready;
rematch004_in_bus_rreq_addr <= in_inst_bus_rreq_addr;
rematch004_in_bus_rreq_len <= in_inst_bus_rreq_len;
in_inst_bus_rdat_valid <= rematch004_in_bus_rdat_valid;
rematch004_in_bus_rdat_ready <= in_inst_bus_rdat_ready;
in_inst_bus_rdat_data <= rematch004_in_bus_rdat_data;
in_inst_bus_rdat_last <= rematch004_in_bus_rdat_last;
rematch004_in_unl_valid <= in_inst_unl_valid;
in_inst_unl_ready <= rematch004_in_unl_ready;
rematch004_in_unl_tag <= in_inst_unl_tag;
in_inst_cmd_valid <= rematch004_in_cmd_valid;
rematch004_in_cmd_ready <= in_inst_cmd_ready;
in_inst_cmd_firstIdx <= rematch004_in_cmd_firstIdx;
in_inst_cmd_lastIdx <= rematch004_in_cmd_lastIdx;
in_inst_cmd_ctrl <= rematch004_in_cmd_ctrl;
in_inst_cmd_tag <= rematch004_in_cmd_tag;
end architecture;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:58:05 10/27/2018
-- Design Name:
-- Module Name: C:/arxitektonikh1/Qblock_test.vhd
-- Project Name: arxitektonikh1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Q_block
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Qblock_test IS
END Qblock_test;
ARCHITECTURE behavior OF Qblock_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Q_block
PORT(
Clk : IN std_logic;
Ri : IN std_logic_vector(4 downto 0);
Rj : IN std_logic_vector(4 downto 0);
Rk : IN std_logic_vector(4 downto 0);
tag : IN std_logic_vector(4 downto 0);
Instr_valid : IN std_logic;
CDB_Q : IN std_logic_vector(4 downto 0);
CDB_valid : IN std_logic;
Qj : OUT std_logic_vector(4 downto 0);
Qk : OUT std_logic_vector(4 downto 0);
Value_WrEn : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Ri : std_logic_vector(4 downto 0) := (others => '0');
signal Rj : std_logic_vector(4 downto 0) := (others => '0');
signal Rk : std_logic_vector(4 downto 0) := (others => '0');
signal tag : std_logic_vector(4 downto 0) := (others => '0');
signal Instr_valid : std_logic := '0';
signal CDB_Q : std_logic_vector(4 downto 0) := (others => '0');
signal CDB_valid : std_logic := '0';
--Outputs
signal Qj : std_logic_vector(4 downto 0);
signal Qk : std_logic_vector(4 downto 0);
signal Value_WrEn : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Q_block PORT MAP (
Clk => Clk,
Ri => Ri,
Rj => Rj,
Rk => Rk,
tag => tag,
Instr_valid => Instr_valid,
CDB_Q => CDB_Q,
CDB_valid => CDB_valid,
Qj => Qj,
Qk => Qk,
Value_WrEn => Value_WrEn
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 100ns;
Ri <= "00000";
Rj <= "00001";
Rk <= "00010";
tag <= "00011";
Instr_valid <= '1';
CDB_Q <= "11111";
CDB_valid <= '0';
wait for Clk_period;
Ri <= "00000";
Rj <= "00000";
Rk <= "00010";
tag <= "00011";
Instr_valid <= '0';
CDB_Q <= "00011";
CDB_valid <= '1';
wait for Clk_period;
Ri <= "00000";
Rj <= "00011";
Rk <= "01110";
tag <= "00111";
Instr_valid <= '1';
CDB_Q <= "00111";
CDB_valid <= '0';
wait for Clk_period;
Ri <= "00000";
Rj <= "00011";
Rk <= "01110";
tag <= "11111";
Instr_valid <= '1';
CDB_Q <= "00111";
CDB_valid <= '1';
-- insert stimulus here
wait;
end process;
END;
|
-- Copyright (c) 2013 Nokia Research Center
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : cdc rtl
-- Project : tta
-------------------------------------------------------------------------------
-- File : cdc-rtl.vhdl
-- Author : <NAME> <<EMAIL>>
-- Company : Nokia Research Center
-- Created : 2013-03-14
-- Last update: 2013-10-24
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: rtl code for cdc
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Nokia Research Center
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-03-14 1.0 zetterma Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- full handshake interface between fpga and debugger
-- simple, slow and works with arbitrary clocks
-------------------------------------------------------------------------------
architecture rtl of cdc is
-- fpga interface states
type fpgaif_state_t is (IDLE, READ_PENDING, WRITE_PENDING, RESETTING);
signal fpgaif_state : fpgaif_state_t;
-- debugger interface states
type dbgif_state_t is (IDLE, READ_PENDING, READ_PENDING_W1, READ_DONE,
WRITE_PENDING, WRITE_DONE);
signal dbgif_state : dbgif_state_t;
-- cdc signals for handshaning
signal req, req1, req2, ack, ack1, ack2 : std_logic;
-- other signals between clock domains (stable when sampled)
signal we,re : std_logic;
signal addr : std_logic_vector(addr_width_g-1 downto 0);
signal addr_dbg_r : std_logic_vector(addr_width_g-1 downto 0);
signal din, dout : std_logic_vector(data_width_g-1 downto 0);
begin
-----------------------------------------------------------------------------
-- clock domain crossing, fpga interface -> debugger
-----------------------------------------------------------------------------
cdc_req : process(clk_dbg, nreset)
begin
if (nreset = '0') then
req1 <= '0';
req2 <= '0';
elsif rising_edge(clk_dbg) then
req1 <= req;
req2 <= req1;
end if;
end process;
-----------------------------------------------------------------------------
-- clock domain crossing, debugger -> fpga interface
-----------------------------------------------------------------------------
cdc_ack : process(clk_fpga, nreset)
begin
if (nreset = '0') then
ack1 <= '0';
ack2 <= '0';
elsif rising_edge(clk_fpga) then
ack1 <= ack;
ack2 <= ack1;
end if;
end process;
-----------------------------------------------------------------------------
-- fpga interface
-----------------------------------------------------------------------------
debugger_fpgaif : process(clk_fpga, nreset)
begin
if (nreset = '0') then
fpgaif_state <= IDLE;
req <= '0';
we <= '0';
re <= '0';
addr <= (others => '0');
din <= (others => '0');
dout_fpga <= (others => '0');
dv_fpga <= '0';
busy <= '0';
elsif rising_edge(clk_fpga) then
dv_fpga <= '0';
dout_fpga <= (others => '0');
case fpgaif_state is
when IDLE =>
assert (ren_fpga='1' or wen_fpga='1')
report "Debugger:Simultaneous write and read request from fpga"
severity failure;
if (wen_fpga = '0') then
fpgaif_state <= WRITE_PENDING;
we <= '1';
addr <= addr_fpga;
din <= din_fpga;
req <= '1';
busy <= '1';
elsif (ren_fpga = '0') then
fpgaif_state <= READ_PENDING;
re <= '1';
addr <= addr_fpga;
req <= '1';
busy <= '1';
end if;
when WRITE_PENDING =>
assert (ren_fpga='1' and wen_fpga='1')
report "Debugger:Access request while busy"
severity failure;
if (ack2 = '1') then
fpgaif_state <= RESETTING;
req <= '0';
we <= '0';
addr <= (others => '0');
din <= (others => '0');
dv_fpga <= '1';
end if;
when READ_PENDING =>
assert (ren_fpga='1' and wen_fpga='1')
report "Debugger:Access request while busy"
severity failure;
if (ack2 = '1') then
fpgaif_state <= RESETTING;
req <= '0';
re <= '0';
-- output read data for single cycle
dout_fpga <= dout;
dv_fpga <= '1';
end if;
when RESETTING =>
assert (ren_fpga='1' and wen_fpga='1')
report "Debugger:Access request while busy"
severity failure;
if (ack2 = '0') then
fpgaif_state <= IDLE;
busy <= '0';
end if;
when others =>
assert (false)
report("Debugger: invalid fpgaif state")
severity failure;
fpgaif_state <= IDLE;
req <= '0';
we <= '0';
re <= '0';
addr <= (others => '0');
din <= (others => '0');
dout_fpga <= (others => '0');
dv_fpga <= '0';
busy <= '0';
end case;
end if;
end process;
addr_dbg <= addr_dbg_r;
-----------------------------------------------------------------------------
-- debugger interface
-----------------------------------------------------------------------------
debugger_dbgif : process(clk_dbg, nreset)
begin
if (nreset = '0') then
dbgif_state <= IDLE;
ack <= '0';
re_dbg <= '0';
we_dbg <= '0';
addr_dbg_r <= (others => '0');
din_dbg <= (others => '0');
dout <= (others => '0');
elsif rising_edge(clk_dbg) then
case dbgif_state is
when IDLE =>
if (req2 = '1') then
if (re = '1') then
dbgif_state <= READ_PENDING;
re_dbg <= '1';
addr_dbg_r <= addr;
elsif (we = '1') then
dbgif_state <= WRITE_PENDING;
we_dbg <= '1';
addr_dbg_r <= addr;
din_dbg <= din;
end if;
end if;
when READ_PENDING =>
-- one wait state when synchronous single-cycle read is used
dbgif_state <= READ_PENDING_W1;
re_dbg <= '0';
addr_dbg_r <= (others => '0');
when READ_PENDING_W1 =>
ack <= '1';
dbgif_state <= READ_DONE;
dout <= dout_dbg;
when READ_DONE =>
if (req2 = '0') then
dbgif_state <= IDLE;
ack <= '0';
dout <= (others => '0');
end if;
when WRITE_PENDING =>
-- single-cycle write, add wait states if needed
dbgif_state <= WRITE_DONE;
ack <= '1';
we_dbg <= '0';
addr_dbg_r <= (others => '0');
din_dbg <= (others => '0');
when WRITE_DONE =>
if (req2 = '0') then
dbgif_state <= IDLE;
ack <= '0';
end if;
when others =>
assert (false)
report "Debugger: invalid dbgif state"
severity failure;
dbgif_state <= IDLE;
ack <= '0';
re_dbg <= '0';
we_dbg <= '0';
addr_dbg_r <= (others => '0');
din_dbg <= (others => '0');
dout <= (others => '0');
end case;
end if;
end process;
end rtl;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_wr_llink.vhd
--
-- Description:
-- THis file implements the Write LocalLink to AXI Stream adapter for the
-- AXI Master burst core.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_wr_llink.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.1 $
-- Date: $1/27/2011$
--
-- History:
-- DET 1/27/2011 Initial Version
--
-- DET 2/14/2011 Initial for EDK 13.2
-- ~~~~~~
-- -- Per CR593485
-- - Modified the Error logic to clear the wrllink_llink_busy assertion
-- when the localLink discontinue completes.
-- - Added logic to complete a Write Discontinue per LocalLink spec after a
-- wrllink_wr_error assertion.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_master_burst_wr_llink is
generic (
C_NATIVE_DWIDTH : INTEGER range 32 to 128 := 32
-- Set this equal to desred data bus width needed by IPIC
-- LocalLink Data Channels.
);
port (
-------------------------------------------------------------------------
-- Write LocalLink Clock input
-------------------------------------------------------------------------
wrllink_aclk : in std_logic;
-------------------------------------------------------------------------
-- Write LocalLink Reset input
-------------------------------------------------------------------------
wrllink_areset : in std_logic;
-------------------------------------------------------------------------
-- RDWR Cntlr Internal Error Indication
-------------------------------------------------------------------------
wrllink_wr_error : In std_logic;
-------------------------------------------------------------------------
-- LocalLink Enable Control (1 Clock wide pulse)
-------------------------------------------------------------------------
wrllink_llink_enable : In std_logic;
-------------------------------------------------------------------------
-- IPIC LocalLink Busy Flag
-------------------------------------------------------------------------
wrllink_llink_busy : Out std_logic;
-------------------------------------------------------------------------
-- Write Address Posting Contols/Status
-------------------------------------------------------------------------
wrllink_allow_addr_req : Out std_logic; -- Active High enable (1-clk pulse wide)
wrllink_addr_req_posted : In std_logic; -- ignored
wrllink_xfer_cmplt : In std_logic; -- ignored
-------------------------------------------------------------------------
-- Write AXI Slave Master Channel
-------------------------------------------------------------------------
wrllink_strm_tdata : Out std_logic_vector(C_NATIVE_DWIDTH-1 downto 0); -- Write AXI Stream
wrllink_strm_tstrb : Out std_logic_vector((C_NATIVE_DWIDTH/8)-1 downto 0); -- Write AXI Stream
wrllink_strm_tlast : Out std_logic; -- Write AXI Stream
wrllink_strm_tvalid : Out std_logic; -- Write AXI Stream
wrllink_strm_tready : In std_logic; -- Write AXI Stream
-------------------------------------------------------------------------
-- IPIC Write LocalLink Channel
-------------------------------------------------------------------------
ip2bus_mstwr_d : In std_logic_vector(0 to C_NATIVE_DWIDTH-1); -- IPIC Write LocalLink
ip2bus_mstwr_rem : In std_logic_vector(0 to (C_NATIVE_DWIDTH/8)-1); -- ignored IPIC Write LocalLink
ip2bus_mstwr_sof_n : In std_logic; -- ignored -- IPIC Write LocalLink
ip2bus_mstwr_eof_n : In std_logic; -- IPIC Write LocalLink
ip2bus_mstwr_src_rdy_n : In std_logic; -- IPIC Write LocalLink
ip2bus_mstwr_src_dsc_n : In std_logic; -- ignored -- IPIC Write LocalLink
bus2ip_mstwr_dst_rdy_n : Out std_logic; -- IPIC Write LocalLink
bus2ip_mstwr_dst_dsc_n : Out std_logic -- IPIC Write LocalLink
);
end entity axi_master_burst_wr_llink;
architecture implementation of axi_master_burst_wr_llink is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constants
Constant STRB_WIDTH : integer := C_NATIVE_DWIDTH/8;
-- Signals
signal sig_inv_rem : std_logic_vector(0 to STRB_WIDTH-1) := (others => '0');
signal sig_llink_busy : std_logic := '0';
signal sig_last_debeat_xfered : std_logic := '0';
signal sig_allow_wr_requests : std_logic := '0';
signal sig_llink_dst_ready_n : std_logic := '0';
signal sig_set_discontinue : std_logic := '0';
signal sig_wr_error_reg : std_logic := '0';
signal sig_wr_dsc_in_prog : std_logic := '0';
signal sig_discontinue_dst_rdy : std_logic := '0';
signal sig_discontinue_cmplt : std_logic := '0';
signal sig_discontinue_accepted : std_logic := '0';
signal sig_assert_discontinue : std_logic := '0';
begin --(architecture implementation)
-------------------------------------------------------------------------
-- Write Stream Output Port Assignments
-------------------------------------------------------------------------
wrllink_strm_tdata <= ip2bus_mstwr_d ;
wrllink_strm_tstrb <= sig_inv_rem ;
wrllink_strm_tlast <= not(ip2bus_mstwr_eof_n) ;
wrllink_strm_tvalid <= not(ip2bus_mstwr_src_rdy_n) and
sig_llink_busy;
-------------------------------------------------------------------------
-- Write LocalLink Output Port Assignments
-------------------------------------------------------------------------
bus2ip_mstwr_dst_rdy_n <= sig_llink_dst_ready_n ;
--bus2ip_mstwr_dst_dsc_n <= not(wrllink_wr_error) ;
bus2ip_mstwr_dst_dsc_n <= not(sig_assert_discontinue) ;
sig_llink_dst_ready_n <= not((wrllink_strm_tready and sig_llink_busy) or
sig_discontinue_dst_rdy) ;
-- Since the PLB Master burst ignored the REM input, Just
-- assign the inverted REM to be all asserted. This will be
-- used for the AXI Stream output.
sig_inv_rem <= (others => '1');
-------------------------------------------------------------------------
-- LocalLink Busy Flag logic
-------------------------------------------------------------------------
wrllink_llink_busy <= sig_llink_busy ;
-- Detect the last data beat of the incoming LocalLink transfer
sig_last_debeat_xfered <= not(ip2bus_mstwr_eof_n or
ip2bus_mstwr_src_rdy_n or
sig_llink_dst_ready_n );
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LLINK_BUSY_FLOP
--
-- Process Description:
-- Implements the LocalLink Busy Flop
--
-------------------------------------------------------------
IMP_LLINK_BUSY_FLOP : process (wrllink_aclk)
begin
if (wrllink_aclk'event and wrllink_aclk = '1') then
if (wrllink_areset = '1') then
sig_llink_busy <= '0';
elsif (wrllink_llink_enable = '1') then
sig_llink_busy <= '1';
elsif (sig_last_debeat_xfered = '1') then
sig_llink_busy <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_LLINK_BUSY_FLOP;
-------------------------------------------------------------------------
-- AXI Write Address Posting Control logic
-------------------------------------------------------------------------
wrllink_allow_addr_req <= sig_allow_wr_requests;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ALLOW_WR_REQ_FLOP
--
-- Process Description:
-- Implements the AXI Write Address Request control flop.
-- AXI Write Requests will be withheld from the AXI Write Address
-- Channel until the LocalLink Source is ready to drive data.
--
-------------------------------------------------------------
IMP_ALLOW_WR_REQ_FLOP : process (wrllink_aclk)
begin
if (wrllink_aclk'event and wrllink_aclk = '1') then
if (wrllink_areset = '1' or
wrllink_llink_enable = '1') then
sig_allow_wr_requests <= '0';
elsif (ip2bus_mstwr_src_rdy_n = '0' and
sig_llink_busy = '1') then
sig_allow_wr_requests <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_ALLOW_WR_REQ_FLOP;
-------------------------------------------------------------------------
-- Write Error LLink discontinue logic
-------------------------------------------------------------------------
-- Detect rising edge of the Read Error assertion
sig_set_discontinue <= wrllink_wr_error and
not(sig_wr_error_reg) and
sig_llink_busy ;
-- Force the assertion of the Dest ready during the discontinue
-- sequence.
sig_discontinue_dst_rdy <= sig_wr_dsc_in_prog and
sig_llink_busy;
-- Detect the acceptance of discontinue by the source but not
-- necessarily the completion of the discontinue sequence.
sig_discontinue_accepted <= Not(ip2bus_mstwr_src_rdy_n) and
sig_assert_discontinue;
-- Detect Completion of the Write Discontinue sequence
-- when the EOF is transfered by the Source
sig_discontinue_cmplt <= sig_discontinue_dst_rdy and
Not(ip2bus_mstwr_src_rdy_n) and
not(ip2bus_mstwr_eof_n);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_ERROR_FLOP
--
-- Process Description:
-- Implements the register for the write error flag.
--
-------------------------------------------------------------
IMP_WR_ERROR_FLOP : process (wrllink_aclk)
begin
if (wrllink_aclk'event and wrllink_aclk = '1') then
if (wrllink_areset = '1') then
sig_wr_error_reg <= '0';
else
sig_wr_error_reg <= wrllink_wr_error;
end if;
end if;
end process IMP_WR_ERROR_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_DSC_FLOP
--
-- Process Description:
-- Implements the register for the write discontinue flag
-- indicating that a discontinue sequence is in progress.
--
-------------------------------------------------------------
IMP_WR_DSC_FLOP : process (wrllink_aclk)
begin
if (wrllink_aclk'event and wrllink_aclk = '1') then
if (wrllink_areset = '1' or
sig_discontinue_cmplt = '1') then
sig_wr_dsc_in_prog <= '0';
elsif (sig_set_discontinue = '1') then
sig_wr_dsc_in_prog <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_WR_DSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SEND_WR_DSC
--
-- Process Description:
-- Implements the register for the flag signaling the
-- assertion of the LLink Dest discontinue output.
--
-------------------------------------------------------------
IMP_SEND_WR_DSC : process (wrllink_aclk)
begin
if (wrllink_aclk'event and wrllink_aclk = '1') then
if (wrllink_areset = '1' or
sig_discontinue_accepted = '1') then
sig_assert_discontinue <= '0';
elsif (sig_set_discontinue = '1') then
sig_assert_discontinue <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_SEND_WR_DSC;
end implementation;
|
-------------------------------------------------------------------------------
-- Title :
-------------------------------------------------------------------------------
-- File : AtlasChess2FebEvrGtx.vhd
-- Author : <NAME> <<EMAIL>>
-- Company : SLAC National Accelerator Laboratory
-- Created : 2016-06-08
-- Last update: 2016-06-08
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- This file is part of 'ATLAS CHESS2 DEV'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'ATLAS CHESS2 DEV', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.StdRtlPkg.all;
library unisim;
use unisim.vcomponents.all;
entity AtlasChess2FebEvrGtx is
generic (
TPD_G : time := 1 ns;
EVR_VERSION_G : boolean := false); -- V1 = false, V2 = true
port (
-- Stable Clock Reference
stableClk : in sl;
-- EVR Ports
evrRefClkP : in sl;
evrRefClkN : in sl;
evrRxP : in sl;
evrRxN : in sl;
evrTxP : out sl;
evrTxN : out sl;
evrRefClk : out sl;
evrRecClk : out sl;
-- EVR Interface
evrClk : out sl;
evrRst : out sl;
rxLinkUp : out sl;
rxError : out sl;
rxData : out slv(15 downto 0);
rxDataK : out slv(1 downto 0));
end AtlasChess2FebEvrGtx;
architecture rtl of AtlasChess2FebEvrGtx is
constant CPLL_REFCLK_SEL_C : bit_vector := ite(EVR_VERSION_G, "010", "001");
constant CPLL_FBDIV_C : integer := ite(EVR_VERSION_G, 1, 2);
constant CPLL_FBDIV_45_C : integer := 5;
constant CPLL_REFCLK_DIV_C : integer := 1;
constant RXOUT_DIV_C : integer := ite(EVR_VERSION_G, 1, 2);
constant TXOUT_DIV_C : integer := ite(EVR_VERSION_G, 1, 2);
constant RX_CLK25_DIV_C : integer := ite(EVR_VERSION_G, 15, 10);
constant TX_CLK25_DIV_C : integer := ite(EVR_VERSION_G, 15, 10);
constant RXCDR_CFG_C : bit_vector := ite(EVR_VERSION_G, x"03000023ff20400020", x"03000023ff40200020");
signal gtRefClk : sl;
signal gtRefClkDiv2 : sl;
signal gtRxRefClkBufg : sl;
signal stableRst : sl;
signal gtRxResetDone : sl;
signal dataValid : sl;
signal evrRxRecClk : sl;
signal linkUp : sl;
signal cPllLock : sl;
signal decErr : slv(1 downto 0);
signal dispErr : slv(1 downto 0);
signal cnt : slv(23 downto 0);
signal gtRxData : slv(19 downto 0);
signal data : slv(15 downto 0);
signal dataK : slv(1 downto 0);
begin
rxError <= not(dataValid) and linkUp;
rxLinkUp <= linkUp;
evrClk <= evrRxRecClk;
evrRst <= not(gtRxResetDone);
evrRefClk <= gtRxRefClkBufg;
evrRecClk <= evrRxRecClk;
IBUFDS_GTE2_Inst : IBUFDS_GTE2
port map (
I => evrRefClkP,
IB => evrRefClkN,
CEB => '0',
ODIV2 => gtRefClkDiv2,
O => gtRefClk);
BUFG_Inst : BUFG
port map (
I => gtRefClkDiv2,
O => gtRxRefClkBufg);
PwrUpRst_Inst : entity work.PwrUpRst
generic map(
TPD_G => TPD_G)
port map (
clk => stableClk,
rstOut => stableRst);
Decoder8b10b_Inst : entity work.Decoder8b10b
generic map (
TPD_G => TPD_G,
RST_POLARITY_G => '0', -- Active low polarity
NUM_BYTES_G => 2)
port map (
clk => evrRxRecClk,
rst => gtRxResetDone,
dataIn => gtRxData,
dataOut => data,
dataKOut => dataK,
codeErr => decErr,
dispErr => dispErr);
rxData <= data when(linkUp = '1') else (others => '0');
rxDataK <= dataK when(linkUp = '1') else (others => '0');
dataValid <= not (uOr(decErr) or uOr(dispErr));
process(cPllLock, evrRxRecClk, gtRxResetDone)
begin
if (gtRxResetDone = '0') or (cPllLock = '0') then
cnt <= (others => '0') after TPD_G;
linkUp <= '0' after TPD_G;
elsif rising_edge(evrRxRecClk) then
if cnt = x"FFFFFF" then
linkUp <= '1' after TPD_G;
else
cnt <= cnt + 1 after TPD_G;
end if;
end if;
end process;
Gtx7Core_Inst : entity work.Gtx7Core
generic map (
TPD_G => TPD_G,
SIM_GTRESET_SPEEDUP_G => "FALSE",
SIM_VERSION_G => "4.0",
SIMULATION_G => false,
STABLE_CLOCK_PERIOD_G => 4.0E-9,
CPLL_REFCLK_SEL_G => CPLL_REFCLK_SEL_C,
CPLL_FBDIV_G => CPLL_FBDIV_C,
CPLL_FBDIV_45_G => CPLL_FBDIV_45_C,
CPLL_REFCLK_DIV_G => CPLL_REFCLK_DIV_C,
RXOUT_DIV_G => RXOUT_DIV_C,
TXOUT_DIV_G => TXOUT_DIV_C,
RX_CLK25_DIV_G => RX_CLK25_DIV_C,
TX_CLK25_DIV_G => TX_CLK25_DIV_C,
TX_PLL_G => "QPLL",
RX_PLL_G => "CPLL",
TX_EXT_DATA_WIDTH_G => 16,
TX_INT_DATA_WIDTH_G => 20,
TX_8B10B_EN_G => true,
RX_EXT_DATA_WIDTH_G => 20,
RX_INT_DATA_WIDTH_G => 20,
RX_8B10B_EN_G => false,
TX_BUF_EN_G => false,
TX_OUTCLK_SRC_G => "PLLREFCLK",
TX_DLY_BYPASS_G => '0',
TX_PHASE_ALIGN_G => "MANUAL",
RX_BUF_EN_G => false,
RX_OUTCLK_SRC_G => "OUTCLKPMA",
RX_USRCLK_SRC_G => "RXOUTCLK",
RX_DLY_BYPASS_G => '1',
RX_DDIEN_G => '0',
RX_ALIGN_MODE_G => "FIXED_LAT",
RX_DFE_KL_CFG2_G => X"301148AC",
RX_OS_CFG_G => "0000010000000",
RXCDR_CFG_G => RXCDR_CFG_C,
RXDFEXYDEN_G => '1',
RX_EQUALIZER_G => "DFE",
RXSLIDE_MODE_G => "PMA",
FIXED_COMMA_EN_G => "0011",
FIXED_ALIGN_COMMA_0_G => "----------0101111100", -- Normal Comma
FIXED_ALIGN_COMMA_1_G => "----------1010000011", -- Inverted Comma
FIXED_ALIGN_COMMA_2_G => "XXXXXXXXXXXXXXXXXXXX", -- Unused
FIXED_ALIGN_COMMA_3_G => "XXXXXXXXXXXXXXXXXXXX") -- Unused
port map (
stableClkIn => stableClk,
cPllRefClkIn => gtRefClk,
cPllLockOut => cPllLock,
qPllRefClkIn => '0',
qPllClkIn => '0',
qPllLockIn => '1',
qPllRefClkLostIn => '0',
qPllResetOut => open,
gtRxRefClkBufg => gtRxRefClkBufg,
-- Serial IO
gtTxP => evrTxP,
gtTxN => evrTxN,
gtRxP => evrRxP,
gtRxN => evrRxN,
-- Rx Clock related signals
rxOutClkOut => evrRxRecClk,
rxUsrClkIn => evrRxRecClk,
rxUsrClk2In => evrRxRecClk,
rxUserRdyOut => open,
rxMmcmResetOut => open,
rxMmcmLockedIn => '1',
-- Rx User Reset Signals
rxUserResetIn => stableRst,
rxResetDoneOut => gtRxResetDone,
-- Manual Comma Align signals
rxDataValidIn => dataValid,
rxSlideIn => '0',
-- Rx Data and decode signals
rxDataOut => gtRxData,
rxCharIsKOut => open,
rxDecErrOut => open,
rxDispErrOut => open,
rxPolarityIn => '0',
rxBufStatusOut => open,
-- Rx Channel Bonding
rxChBondLevelIn => (others => '0'),
rxChBondIn => (others => '0'),
rxChBondOut => open,
-- Tx Clock Related Signals
txOutClkOut => open,
txUsrClkIn => '0',
txUsrClk2In => '0',
txUserRdyOut => open,
txMmcmResetOut => open,
txMmcmLockedIn => '1',
-- Tx User Reset signals
txUserResetIn => '0',
txResetDoneOut => open,
-- Tx Data
txDataIn => (others => '0'),
txCharIsKIn => (others => '0'),
txBufStatusOut => open,
-- Misc.
loopbackIn => (others => '0'),
txPowerDown => (others => '1'),
rxPowerDown => (others => '0'));
end rtl;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity Core is
port (clock : in STD_LOGIC;
btn_reset : in STD_LOGIC;
btn_inc : in STD_LOGIC;
btn_dec : in STD_LOGIC;
switch_done : in STD_LOGIC;
switch_input : in STD_LOGIC;
switch_operation : in STD_LOGIC;
btn_display_mode : in STD_LOGIC;
current_display : out STD_LOGIC_VECTOR (3 downto 0);
display_output : out STD_LOGIC_VECTOR (7 downto 0));
end Core;
architecture Behavioral of Core is
signal btn_inc_debounce, btn_dec_debounce : STD_LOGIC;
signal output_display : STD_LOGIC_VECTOR (15 downto 0);
begin
core : entity work.Calculator
port map (clock,
btn_reset,
btn_inc_debounce,
btn_dec_debounce,
switch_input,
switch_operation,
switch_done,
output_display);
debouce_btn_inc :entity work.Debounce
port map (clock, btn_inc, btn_inc_debounce);
debouce_btn_dec :entity work.Debounce
port map (clock, btn_dec, btn_dec_debounce);
display_linker : entity work.DisplayDriver
port map (clock,
btn_reset,
btn_display_mode,
output_display,
current_display,
display_output);
end Behavioral;
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date : Sun Dec 8 17:09:36 2019
-- Host : DESKTOP-OBAJBNI running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/yakuza/Desktop/git/fpgaProjects/11-streamHDMI/HDL_sources/blockDesign/hdmi_to_vga/ip/hdmi_to_vga_v_axi4s_vid_out_0_0/hdmi_to_vga_v_axi4s_vid_out_0_0_sim_netlist.vhdl
-- Design : hdmi_to_vga_v_axi4s_vid_out_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_formatter is
port (
vid_active_video : out STD_LOGIC;
vid_vsync : out STD_LOGIC;
vid_hsync : out STD_LOGIC;
vid_vblank : out STD_LOGIC;
vid_hblank : out STD_LOGIC;
vid_field_id : out STD_LOGIC;
fivid_reset_full_frame : out STD_LOGIC;
vid_data : out STD_LOGIC_VECTOR ( 23 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
vid_io_out_ce : in STD_LOGIC;
vtg_active_video : in STD_LOGIC;
aclk : in STD_LOGIC;
vtg_vsync : in STD_LOGIC;
vtg_hsync : in STD_LOGIC;
vtg_vblank : in STD_LOGIC;
vtg_hblank : in STD_LOGIC;
vtg_field_id : in STD_LOGIC;
src_in : in STD_LOGIC;
aresetn : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_formatter : entity is "v_axi4s_vid_out_v4_0_10_formatter";
end hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_formatter;
architecture STRUCTURE of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_formatter is
signal \^fivid_reset_full_frame\ : STD_LOGIC;
signal fivid_reset_full_frame_i_1_n_0 : STD_LOGIC;
signal vblank_rising : STD_LOGIC;
signal vblank_rising_i_1_n_0 : STD_LOGIC;
signal vtg_vblank_1 : STD_LOGIC;
signal vtg_vblank_1_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of vblank_rising_i_1 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of vtg_vblank_1_i_1 : label is "soft_lutpair17";
begin
fivid_reset_full_frame <= \^fivid_reset_full_frame\;
fivid_reset_full_frame_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EA000000"
)
port map (
I0 => \^fivid_reset_full_frame\,
I1 => vblank_rising,
I2 => vid_io_out_ce,
I3 => src_in,
I4 => aresetn,
O => fivid_reset_full_frame_i_1_n_0
);
fivid_reset_full_frame_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => fivid_reset_full_frame_i_1_n_0,
Q => \^fivid_reset_full_frame\,
R => '0'
);
\in_data_mux_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(0),
Q => vid_data(0),
R => SR(0)
);
\in_data_mux_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(10),
Q => vid_data(10),
R => SR(0)
);
\in_data_mux_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(11),
Q => vid_data(11),
R => SR(0)
);
\in_data_mux_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(12),
Q => vid_data(12),
R => SR(0)
);
\in_data_mux_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(13),
Q => vid_data(13),
R => SR(0)
);
\in_data_mux_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(14),
Q => vid_data(14),
R => SR(0)
);
\in_data_mux_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(15),
Q => vid_data(15),
R => SR(0)
);
\in_data_mux_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(16),
Q => vid_data(16),
R => SR(0)
);
\in_data_mux_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(17),
Q => vid_data(17),
R => SR(0)
);
\in_data_mux_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(18),
Q => vid_data(18),
R => SR(0)
);
\in_data_mux_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(19),
Q => vid_data(19),
R => SR(0)
);
\in_data_mux_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(1),
Q => vid_data(1),
R => SR(0)
);
\in_data_mux_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(20),
Q => vid_data(20),
R => SR(0)
);
\in_data_mux_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(21),
Q => vid_data(21),
R => SR(0)
);
\in_data_mux_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(22),
Q => vid_data(22),
R => SR(0)
);
\in_data_mux_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(23),
Q => vid_data(23),
R => SR(0)
);
\in_data_mux_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(2),
Q => vid_data(2),
R => SR(0)
);
\in_data_mux_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(3),
Q => vid_data(3),
R => SR(0)
);
\in_data_mux_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(4),
Q => vid_data(4),
R => SR(0)
);
\in_data_mux_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(5),
Q => vid_data(5),
R => SR(0)
);
\in_data_mux_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(6),
Q => vid_data(6),
R => SR(0)
);
\in_data_mux_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(7),
Q => vid_data(7),
R => SR(0)
);
\in_data_mux_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(8),
Q => vid_data(8),
R => SR(0)
);
\in_data_mux_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => E(0),
D => D(9),
Q => vid_data(9),
R => SR(0)
);
in_de_mux_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => vtg_active_video,
Q => vid_active_video,
R => SR(0)
);
in_field_id_mux_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => vtg_field_id,
Q => vid_field_id,
R => SR(0)
);
in_hblank_mux_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => vtg_hblank,
Q => vid_hblank,
R => SR(0)
);
in_hsync_mux_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => vtg_hsync,
Q => vid_hsync,
R => SR(0)
);
in_vblank_mux_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => vtg_vblank,
Q => vid_vblank,
R => SR(0)
);
in_vsync_mux_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => vtg_vsync,
Q => vid_vsync,
R => SR(0)
);
vblank_rising_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => vtg_vblank,
I1 => vtg_vblank_1,
I2 => vid_io_out_ce,
I3 => vblank_rising,
O => vblank_rising_i_1_n_0
);
vblank_rising_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => vblank_rising_i_1_n_0,
Q => vblank_rising,
R => '0'
);
vtg_vblank_1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => vtg_vblank,
I1 => vid_io_out_ce,
I2 => vtg_vblank_1,
O => vtg_vblank_1_i_1_n_0
);
vtg_vblank_1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => vtg_vblank_1_i_1_n_0,
Q => vtg_vblank_1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_sync is
port (
fifo_eol_dly : out STD_LOGIC;
src_in : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
fifo_rd_en : out STD_LOGIC;
status : out STD_LOGIC_VECTOR ( 19 downto 0 );
vid_io_out_ce : in STD_LOGIC;
vtg_active_video : in STD_LOGIC;
aclk : in STD_LOGIC;
vtg_vsync : in STD_LOGIC;
dout : in STD_LOGIC_VECTOR ( 2 downto 0 );
fifo_eol_re : in STD_LOGIC;
fifo_pix_cnt : in STD_LOGIC;
\FSM_sequential_state_reg[0]_0\ : in STD_LOGIC;
vtg_field_id : in STD_LOGIC;
aresetn : in STD_LOGIC;
fivid_reset_full_frame : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_sync : entity is "v_axi4s_vid_out_v4_0_10_sync";
end hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_sync;
architecture STRUCTURE of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_sync is
signal \FSM_sequential_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[0]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[0]_i_4_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[0]_i_5_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[0]_i_6_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[0]_i_8_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[1]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[1]_i_4_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[1]_i_5_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[1]_i_6_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[1]_i_7_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[1]_i_8_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[1]_i_9_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[2]_i_4_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_10_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_11_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_12_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_15_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_16_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_17_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_18_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_19_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_20_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_21_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_22_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_23_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_24_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_4_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_6_n_0\ : STD_LOGIC;
signal \FSM_sequential_state[3]_i_9_n_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal fifo_eol_cnt : STD_LOGIC;
signal \fifo_eol_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \fifo_eol_cnt[0]_i_4_n_0\ : STD_LOGIC;
signal fifo_eol_cnt_dly : STD_LOGIC_VECTOR ( 12 downto 0 );
signal fifo_eol_cnt_reg : STD_LOGIC_VECTOR ( 12 downto 0 );
signal \fifo_eol_cnt_reg[0]_i_3_n_0\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[0]_i_3_n_1\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[0]_i_3_n_2\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[0]_i_3_n_3\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[0]_i_3_n_4\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[0]_i_3_n_5\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[0]_i_3_n_6\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[0]_i_3_n_7\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \fifo_eol_cnt_reg[8]_i_1_n_7\ : STD_LOGIC;
signal fifo_eol_error : STD_LOGIC;
signal fifo_eol_error1 : STD_LOGIC;
signal \fifo_eol_error1_carry__0_i_1_n_0\ : STD_LOGIC;
signal fifo_eol_error1_carry_i_1_n_0 : STD_LOGIC;
signal fifo_eol_error1_carry_i_2_n_0 : STD_LOGIC;
signal fifo_eol_error1_carry_i_3_n_0 : STD_LOGIC;
signal fifo_eol_error1_carry_i_4_n_0 : STD_LOGIC;
signal fifo_eol_error1_carry_n_0 : STD_LOGIC;
signal fifo_eol_error1_carry_n_1 : STD_LOGIC;
signal fifo_eol_error1_carry_n_2 : STD_LOGIC;
signal fifo_eol_error1_carry_n_3 : STD_LOGIC;
signal fifo_eol_error2 : STD_LOGIC;
signal fifo_eol_error_i_1_n_0 : STD_LOGIC;
signal fifo_eol_error_i_3_n_0 : STD_LOGIC;
signal fifo_eol_error_i_4_n_0 : STD_LOGIC;
signal fifo_eol_re_dly : STD_LOGIC;
signal \fifo_pix_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \fifo_pix_cnt[0]_i_5_n_0\ : STD_LOGIC;
signal fifo_pix_cnt_dly : STD_LOGIC_VECTOR ( 12 downto 0 );
signal \fifo_pix_cnt_dly1__11\ : STD_LOGIC;
signal \fifo_pix_cnt_dly[12]_i_1_n_0\ : STD_LOGIC;
signal \fifo_pix_cnt_dly[12]_i_3_n_0\ : STD_LOGIC;
signal \fifo_pix_cnt_dly[12]_i_5_n_0\ : STD_LOGIC;
signal \fifo_pix_cnt_dly[12]_i_6_n_0\ : STD_LOGIC;
signal \fifo_pix_cnt_dly[12]_i_7_n_0\ : STD_LOGIC;
signal \fifo_pix_cnt_dly[12]_i_8_n_0\ : STD_LOGIC;
signal fifo_pix_cnt_dly_0 : STD_LOGIC;
signal fifo_pix_cnt_reg : STD_LOGIC_VECTOR ( 12 downto 0 );
signal \fifo_pix_cnt_reg[0]_i_3_n_0\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[0]_i_3_n_1\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[0]_i_3_n_2\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[0]_i_3_n_3\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[0]_i_3_n_4\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[0]_i_3_n_5\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[0]_i_3_n_6\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[0]_i_3_n_7\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \fifo_pix_cnt_reg[8]_i_1_n_7\ : STD_LOGIC;
signal fifo_pix_error : STD_LOGIC;
signal fifo_pix_error0 : STD_LOGIC;
signal fifo_pix_error1 : STD_LOGIC;
signal \fifo_pix_error1_carry__0_i_1_n_0\ : STD_LOGIC;
signal fifo_pix_error1_carry_i_1_n_0 : STD_LOGIC;
signal fifo_pix_error1_carry_i_2_n_0 : STD_LOGIC;
signal fifo_pix_error1_carry_i_3_n_0 : STD_LOGIC;
signal fifo_pix_error1_carry_i_4_n_0 : STD_LOGIC;
signal fifo_pix_error1_carry_n_0 : STD_LOGIC;
signal fifo_pix_error1_carry_n_1 : STD_LOGIC;
signal fifo_pix_error1_carry_n_2 : STD_LOGIC;
signal fifo_pix_error1_carry_n_3 : STD_LOGIC;
signal fifo_pix_error_i_1_n_0 : STD_LOGIC;
signal fifo_sof_cnt : STD_LOGIC;
signal \fifo_sof_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \fifo_sof_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal fifo_sof_cnt_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
signal fifo_sof_dly : STD_LOGIC;
signal locked_i_1_n_0 : STD_LOGIC;
signal next_state110_out : STD_LOGIC;
signal next_state121_out : STD_LOGIC;
signal next_state124_out : STD_LOGIC;
signal \next_state1__0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_18_in : STD_LOGIC;
signal p_25_in : STD_LOGIC;
signal sof_ignore : STD_LOGIC;
signal sof_ignore_i_1_n_0 : STD_LOGIC;
signal \^src_in\ : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 3 downto 0 );
signal state_dly : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \state_dly[3]_i_1_n_0\ : STD_LOGIC;
signal state_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^status\ : STD_LOGIC_VECTOR ( 19 downto 0 );
signal status_reg1 : STD_LOGIC;
signal \status_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \status_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \status_reg[10]_i_1_n_0\ : STD_LOGIC;
signal \status_reg[10]_i_2_n_0\ : STD_LOGIC;
signal \status_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \status_reg[11]_i_3_n_0\ : STD_LOGIC;
signal \status_reg[11]_i_4_n_0\ : STD_LOGIC;
signal \status_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \status_reg[12]_i_2_n_0\ : STD_LOGIC;
signal \status_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \status_reg[1]_i_2_n_0\ : STD_LOGIC;
signal \status_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \status_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \status_reg[2]_i_2_n_0\ : STD_LOGIC;
signal \status_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \status_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \status_reg[5]_i_1_n_0\ : STD_LOGIC;
signal \status_reg[5]_i_2_n_0\ : STD_LOGIC;
signal \status_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \status_reg[6]_i_2_n_0\ : STD_LOGIC;
signal \status_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \status_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \status_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \status_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \status_reg[9]_i_2_n_0\ : STD_LOGIC;
signal vtg_de_dly : STD_LOGIC;
signal vtg_lag : STD_LOGIC;
signal \vtg_lag[0]_i_1_n_0\ : STD_LOGIC;
signal \vtg_lag[0]_i_4_n_0\ : STD_LOGIC;
signal vtg_lag_reg : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \vtg_lag_reg[0]_i_3_n_0\ : STD_LOGIC;
signal \vtg_lag_reg[0]_i_3_n_1\ : STD_LOGIC;
signal \vtg_lag_reg[0]_i_3_n_2\ : STD_LOGIC;
signal \vtg_lag_reg[0]_i_3_n_3\ : STD_LOGIC;
signal \vtg_lag_reg[0]_i_3_n_4\ : STD_LOGIC;
signal \vtg_lag_reg[0]_i_3_n_5\ : STD_LOGIC;
signal \vtg_lag_reg[0]_i_3_n_6\ : STD_LOGIC;
signal \vtg_lag_reg[0]_i_3_n_7\ : STD_LOGIC;
signal \vtg_lag_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \vtg_lag_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \vtg_lag_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \vtg_lag_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \vtg_lag_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \vtg_lag_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \vtg_lag_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \vtg_lag_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \vtg_lag_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \vtg_lag_reg[16]_i_1_n_1\ : STD_LOGIC;
signal \vtg_lag_reg[16]_i_1_n_2\ : STD_LOGIC;
signal \vtg_lag_reg[16]_i_1_n_3\ : STD_LOGIC;
signal \vtg_lag_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \vtg_lag_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \vtg_lag_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \vtg_lag_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \vtg_lag_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \vtg_lag_reg[20]_i_1_n_1\ : STD_LOGIC;
signal \vtg_lag_reg[20]_i_1_n_2\ : STD_LOGIC;
signal \vtg_lag_reg[20]_i_1_n_3\ : STD_LOGIC;
signal \vtg_lag_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \vtg_lag_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \vtg_lag_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \vtg_lag_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \vtg_lag_reg[24]_i_1_n_0\ : STD_LOGIC;
signal \vtg_lag_reg[24]_i_1_n_1\ : STD_LOGIC;
signal \vtg_lag_reg[24]_i_1_n_2\ : STD_LOGIC;
signal \vtg_lag_reg[24]_i_1_n_3\ : STD_LOGIC;
signal \vtg_lag_reg[24]_i_1_n_4\ : STD_LOGIC;
signal \vtg_lag_reg[24]_i_1_n_5\ : STD_LOGIC;
signal \vtg_lag_reg[24]_i_1_n_6\ : STD_LOGIC;
signal \vtg_lag_reg[24]_i_1_n_7\ : STD_LOGIC;
signal \vtg_lag_reg[28]_i_1_n_1\ : STD_LOGIC;
signal \vtg_lag_reg[28]_i_1_n_2\ : STD_LOGIC;
signal \vtg_lag_reg[28]_i_1_n_3\ : STD_LOGIC;
signal \vtg_lag_reg[28]_i_1_n_4\ : STD_LOGIC;
signal \vtg_lag_reg[28]_i_1_n_5\ : STD_LOGIC;
signal \vtg_lag_reg[28]_i_1_n_6\ : STD_LOGIC;
signal \vtg_lag_reg[28]_i_1_n_7\ : STD_LOGIC;
signal \vtg_lag_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \vtg_lag_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \vtg_lag_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \vtg_lag_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \vtg_lag_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \vtg_lag_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \vtg_lag_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \vtg_lag_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \vtg_lag_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \vtg_lag_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \vtg_lag_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \vtg_lag_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \vtg_lag_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \vtg_lag_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \vtg_lag_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \vtg_lag_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \vtg_lag_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 5 );
signal vtg_sof : STD_LOGIC;
signal vtg_sof_cnt : STD_LOGIC;
signal \vtg_sof_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \vtg_sof_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \vtg_sof_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal vtg_sof_cnt_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
signal vtg_sof_dly : STD_LOGIC;
signal vtg_vsync_bp_i_1_n_0 : STD_LOGIC;
signal vtg_vsync_bp_reg_n_0 : STD_LOGIC;
signal vtg_vsync_dly : STD_LOGIC;
signal \NLW_fifo_eol_cnt_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_fifo_eol_cnt_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_fifo_eol_error1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_fifo_eol_error1_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_fifo_eol_error1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_fifo_pix_cnt_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_fifo_pix_cnt_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_fifo_pix_error1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_fifo_pix_error1_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_fifo_pix_error1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_vtg_lag_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_state[0]_i_3\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \FSM_sequential_state[1]_i_4\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \FSM_sequential_state[1]_i_5\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \FSM_sequential_state[1]_i_6\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \FSM_sequential_state[1]_i_8\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \FSM_sequential_state[1]_i_9\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \FSM_sequential_state[2]_i_3\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \FSM_sequential_state[3]_i_10\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \FSM_sequential_state[3]_i_13\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \FSM_sequential_state[3]_i_14\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \FSM_sequential_state[3]_i_15\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \FSM_sequential_state[3]_i_17\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \FSM_sequential_state[3]_i_19\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \FSM_sequential_state[3]_i_3\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \FSM_sequential_state[3]_i_5\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \FSM_sequential_state[3]_i_7\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \FSM_sequential_state[3]_i_9\ : label is "soft_lutpair20";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[0]\ : label is "C_SYNC_FALN_EOL_LAGGING:0011,C_SYNC_FALN_EOL_LEADING:0000,C_SYNC_CALN_SOF_FIFO:0100,C_SYNC_LALN_SOF_LEADING:0111,C_SYNC_LALN_SOF_LAGGING:0110,C_SYNC_LALN_EOL_LAGGING:1000,C_SYNC_CALN_SOF_VTG:0101,C_SYNC_IDLE:0001,C_SYNC_LALN_EOL_LEADING:1100,C_SYNC_FALN_ACTIVE:0010,C_SYNC_FALN_LOCK:1011,C_SYNC_FALN_SOF_LAGGING:1010,C_SYNC_FALN_SOF_LEADING:1001";
attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[1]\ : label is "C_SYNC_FALN_EOL_LAGGING:0011,C_SYNC_FALN_EOL_LEADING:0000,C_SYNC_CALN_SOF_FIFO:0100,C_SYNC_LALN_SOF_LEADING:0111,C_SYNC_LALN_SOF_LAGGING:0110,C_SYNC_LALN_EOL_LAGGING:1000,C_SYNC_CALN_SOF_VTG:0101,C_SYNC_IDLE:0001,C_SYNC_LALN_EOL_LEADING:1100,C_SYNC_FALN_ACTIVE:0010,C_SYNC_FALN_LOCK:1011,C_SYNC_FALN_SOF_LAGGING:1010,C_SYNC_FALN_SOF_LEADING:1001";
attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[2]\ : label is "C_SYNC_FALN_EOL_LAGGING:0011,C_SYNC_FALN_EOL_LEADING:0000,C_SYNC_CALN_SOF_FIFO:0100,C_SYNC_LALN_SOF_LEADING:0111,C_SYNC_LALN_SOF_LAGGING:0110,C_SYNC_LALN_EOL_LAGGING:1000,C_SYNC_CALN_SOF_VTG:0101,C_SYNC_IDLE:0001,C_SYNC_LALN_EOL_LEADING:1100,C_SYNC_FALN_ACTIVE:0010,C_SYNC_FALN_LOCK:1011,C_SYNC_FALN_SOF_LAGGING:1010,C_SYNC_FALN_SOF_LEADING:1001";
attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[3]\ : label is "C_SYNC_FALN_EOL_LAGGING:0011,C_SYNC_FALN_EOL_LEADING:0000,C_SYNC_CALN_SOF_FIFO:0100,C_SYNC_LALN_SOF_LEADING:0111,C_SYNC_LALN_SOF_LAGGING:0110,C_SYNC_LALN_EOL_LAGGING:1000,C_SYNC_CALN_SOF_VTG:0101,C_SYNC_IDLE:0001,C_SYNC_LALN_EOL_LEADING:1100,C_SYNC_FALN_ACTIVE:0010,C_SYNC_FALN_LOCK:1011,C_SYNC_FALN_SOF_LAGGING:1010,C_SYNC_FALN_SOF_LEADING:1001";
attribute SOFT_HLUTNM of fifo_pix_error_i_1 : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \fifo_sof_cnt[1]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \fifo_sof_cnt[2]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \fifo_sof_cnt[3]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \fifo_sof_cnt[4]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \fifo_sof_cnt[6]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of locked_i_1 : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \state_dly[0]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \state_dly[1]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \state_dly[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \state_dly[3]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \status_reg[0]_i_2\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \status_reg[11]_i_3\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \status_reg[7]_i_2\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \status_reg[9]_i_2\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \vtg_sof_cnt[1]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \vtg_sof_cnt[2]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \vtg_sof_cnt[3]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \vtg_sof_cnt[4]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \vtg_sof_cnt[6]_i_2\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of vtg_sof_dly_i_1 : label is "soft_lutpair33";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
src_in <= \^src_in\;
status(19 downto 0) <= \^status\(19 downto 0);
\FSM_sequential_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAFFEAFFEAAAEA"
)
port map (
I0 => \FSM_sequential_state[0]_i_2_n_0\,
I1 => \FSM_sequential_state[0]_i_3_n_0\,
I2 => \FSM_sequential_state[0]_i_4_n_0\,
I3 => state(3),
I4 => \FSM_sequential_state[0]_i_5_n_0\,
I5 => \^q\(1),
O => \FSM_sequential_state[0]_i_1_n_0\
);
\FSM_sequential_state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA000000A800"
)
port map (
I0 => \FSM_sequential_state[0]_i_6_n_0\,
I1 => \FSM_sequential_state[3]_i_11_n_0\,
I2 => \FSM_sequential_state[1]_i_7_n_0\,
I3 => \FSM_sequential_state_reg[0]_0\,
I4 => state(0),
I5 => \^q\(1),
O => \FSM_sequential_state[0]_i_2_n_0\
);
\FSM_sequential_state[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00B00FB0"
)
port map (
I0 => dout(2),
I1 => dout(1),
I2 => state(0),
I3 => \^q\(0),
I4 => \next_state1__0\,
O => \FSM_sequential_state[0]_i_3_n_0\
);
\FSM_sequential_state[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555545455555554"
)
port map (
I0 => \^q\(1),
I1 => state(0),
I2 => \FSM_sequential_state[1]_i_5_n_0\,
I3 => next_state121_out,
I4 => \FSM_sequential_state[3]_i_9_n_0\,
I5 => next_state124_out,
O => \FSM_sequential_state[0]_i_4_n_0\
);
\FSM_sequential_state[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBB8BBBBBBBBBBBB"
)
port map (
I0 => \FSM_sequential_state[0]_i_8_n_0\,
I1 => \^q\(0),
I2 => \FSM_sequential_state[3]_i_11_n_0\,
I3 => \FSM_sequential_state[1]_i_7_n_0\,
I4 => state(0),
I5 => p_18_in,
O => \FSM_sequential_state[0]_i_5_n_0\
);
\FSM_sequential_state[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEFFFFFFFFFFF"
)
port map (
I0 => \^q\(0),
I1 => vtg_de_dly,
I2 => vtg_vsync_bp_reg_n_0,
I3 => vtg_active_video,
I4 => vtg_field_id,
I5 => state(0),
O => \FSM_sequential_state[0]_i_6_n_0\
);
\FSM_sequential_state[0]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6500650000006500"
)
port map (
I0 => fifo_eol_re_dly,
I1 => vtg_active_video,
I2 => vtg_de_dly,
I3 => state(0),
I4 => p_18_in,
I5 => vtg_sof_dly,
O => \FSM_sequential_state[0]_i_8_n_0\
);
\FSM_sequential_state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"04040C0C04040CFC"
)
port map (
I0 => \FSM_sequential_state[1]_i_2_n_0\,
I1 => \FSM_sequential_state[1]_i_3_n_0\,
I2 => \^q\(1),
I3 => \FSM_sequential_state[1]_i_4_n_0\,
I4 => \^q\(0),
I5 => state(3),
O => \FSM_sequential_state[1]_i_1_n_0\
);
\FSM_sequential_state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => p_18_in,
I1 => vtg_sof_dly,
I2 => sof_ignore,
I3 => state(3),
I4 => state(0),
I5 => \FSM_sequential_state[1]_i_5_n_0\,
O => \FSM_sequential_state[1]_i_2_n_0\
);
\FSM_sequential_state[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8888888B"
)
port map (
I0 => \FSM_sequential_state[1]_i_6_n_0\,
I1 => \^q\(0),
I2 => \FSM_sequential_state[3]_i_11_n_0\,
I3 => \FSM_sequential_state[1]_i_7_n_0\,
I4 => \FSM_sequential_state[1]_i_8_n_0\,
O => \FSM_sequential_state[1]_i_3_n_0\
);
\FSM_sequential_state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFDFFF"
)
port map (
I0 => state(0),
I1 => vtg_field_id,
I2 => vtg_active_video,
I3 => vtg_vsync_bp_reg_n_0,
I4 => vtg_de_dly,
O => \FSM_sequential_state[1]_i_4_n_0\
);
\FSM_sequential_state[1]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => p_25_in,
I1 => state(0),
I2 => state(3),
I3 => \^q\(0),
I4 => \^q\(1),
O => \FSM_sequential_state[1]_i_5_n_0\
);
\FSM_sequential_state[1]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"4BFFFFFB"
)
port map (
I0 => vtg_active_video,
I1 => vtg_de_dly,
I2 => fifo_eol_re_dly,
I3 => state(0),
I4 => state(3),
O => \FSM_sequential_state[1]_i_6_n_0\
);
\FSM_sequential_state[1]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \vtg_lag_reg__0\(7),
I1 => \vtg_lag_reg__0\(8),
I2 => \vtg_lag_reg__0\(5),
I3 => \vtg_lag_reg__0\(6),
I4 => \FSM_sequential_state[3]_i_20_n_0\,
I5 => \FSM_sequential_state[1]_i_9_n_0\,
O => \FSM_sequential_state[1]_i_7_n_0\
);
\FSM_sequential_state[1]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFF0BFFF"
)
port map (
I0 => dout(1),
I1 => fifo_sof_dly,
I2 => state(0),
I3 => state(3),
I4 => fifo_eol_re_dly,
O => \FSM_sequential_state[1]_i_8_n_0\
);
\FSM_sequential_state[1]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \vtg_lag_reg__0\(10),
I1 => \vtg_lag_reg__0\(9),
I2 => \vtg_lag_reg__0\(12),
I3 => \vtg_lag_reg__0\(11),
O => \FSM_sequential_state[1]_i_9_n_0\
);
\FSM_sequential_state[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAA0000"
)
port map (
I0 => \FSM_sequential_state[2]_i_2_n_0\,
I1 => state(0),
I2 => next_state110_out,
I3 => \^q\(1),
I4 => \FSM_sequential_state[2]_i_4_n_0\,
O => \FSM_sequential_state[2]_i_1_n_0\
);
\FSM_sequential_state[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"06066F06FFFFFFFF"
)
port map (
I0 => p_18_in,
I1 => vtg_sof_dly,
I2 => fifo_eol_re_dly,
I3 => vtg_de_dly,
I4 => vtg_active_video,
I5 => \^q\(0),
O => \FSM_sequential_state[2]_i_2_n_0\
);
\FSM_sequential_state[2]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => vtg_de_dly,
I1 => vtg_vsync_bp_reg_n_0,
I2 => vtg_active_video,
I3 => vtg_field_id,
O => next_state110_out
);
\FSM_sequential_state[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111189880000"
)
port map (
I0 => \^q\(0),
I1 => state(3),
I2 => dout(2),
I3 => dout(1),
I4 => state(0),
I5 => \^q\(1),
O => \FSM_sequential_state[2]_i_4_n_0\
);
\FSM_sequential_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA000200000002"
)
port map (
I0 => \FSM_sequential_state[3]_i_2_n_0\,
I1 => \FSM_sequential_state[3]_i_3_n_0\,
I2 => \FSM_sequential_state[3]_i_4_n_0\,
I3 => p_18_in,
I4 => \^q\(0),
I5 => \FSM_sequential_state[3]_i_6_n_0\,
O => \FSM_sequential_state[3]_i_1_n_0\
);
\FSM_sequential_state[3]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \vtg_lag_reg__0\(11),
I1 => \vtg_lag_reg__0\(12),
I2 => \vtg_lag_reg__0\(9),
I3 => \vtg_lag_reg__0\(10),
I4 => \FSM_sequential_state[3]_i_20_n_0\,
O => \FSM_sequential_state[3]_i_10_n_0\
);
\FSM_sequential_state[3]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \FSM_sequential_state[3]_i_21_n_0\,
I1 => \FSM_sequential_state[3]_i_22_n_0\,
I2 => \vtg_lag_reg__0\(30),
I3 => \vtg_lag_reg__0\(29),
I4 => \FSM_sequential_state[3]_i_23_n_0\,
I5 => \FSM_sequential_state[3]_i_24_n_0\,
O => \FSM_sequential_state[3]_i_11_n_0\
);
\FSM_sequential_state[3]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2D"
)
port map (
I0 => fifo_sof_dly,
I1 => dout(1),
I2 => vtg_sof_dly,
O => \FSM_sequential_state[3]_i_12_n_0\
);
\FSM_sequential_state[3]_i_13\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => vtg_active_video,
I1 => vtg_de_dly,
I2 => fifo_eol_re_dly,
O => \next_state1__0\
);
\FSM_sequential_state[3]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => fifo_eol_re_dly,
I1 => vtg_active_video,
I2 => vtg_de_dly,
O => p_25_in
);
\FSM_sequential_state[3]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => state(3),
I3 => state(0),
O => \FSM_sequential_state[3]_i_15_n_0\
);
\FSM_sequential_state[3]_i_16\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => fifo_sof_cnt_reg(2),
I1 => fifo_sof_cnt_reg(4),
I2 => fifo_sof_cnt_reg(3),
O => \FSM_sequential_state[3]_i_16_n_0\
);
\FSM_sequential_state[3]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFEEE"
)
port map (
I0 => fifo_sof_cnt_reg(6),
I1 => fifo_sof_cnt_reg(5),
I2 => fifo_sof_cnt_reg(1),
I3 => fifo_sof_cnt_reg(0),
I4 => fifo_sof_cnt_reg(7),
O => \FSM_sequential_state[3]_i_17_n_0\
);
\FSM_sequential_state[3]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => vtg_sof_cnt_reg(2),
I1 => vtg_sof_cnt_reg(4),
I2 => vtg_sof_cnt_reg(3),
O => \FSM_sequential_state[3]_i_18_n_0\
);
\FSM_sequential_state[3]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFEEE"
)
port map (
I0 => vtg_sof_cnt_reg(6),
I1 => vtg_sof_cnt_reg(5),
I2 => vtg_sof_cnt_reg(1),
I3 => vtg_sof_cnt_reg(0),
I4 => vtg_sof_cnt_reg(7),
O => \FSM_sequential_state[3]_i_19_n_0\
);
\FSM_sequential_state[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => \^q\(1),
I1 => next_state124_out,
I2 => next_state121_out,
I3 => \FSM_sequential_state[3]_i_9_n_0\,
I4 => state(0),
O => \FSM_sequential_state[3]_i_2_n_0\
);
\FSM_sequential_state[3]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \vtg_lag_reg__0\(14),
I1 => \vtg_lag_reg__0\(13),
I2 => \vtg_lag_reg__0\(16),
I3 => \vtg_lag_reg__0\(15),
O => \FSM_sequential_state[3]_i_20_n_0\
);
\FSM_sequential_state[3]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \vtg_lag_reg__0\(22),
I1 => \vtg_lag_reg__0\(21),
I2 => \vtg_lag_reg__0\(24),
I3 => \vtg_lag_reg__0\(23),
O => \FSM_sequential_state[3]_i_21_n_0\
);
\FSM_sequential_state[3]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \vtg_lag_reg__0\(18),
I1 => \vtg_lag_reg__0\(17),
I2 => \vtg_lag_reg__0\(20),
I3 => \vtg_lag_reg__0\(19),
O => \FSM_sequential_state[3]_i_22_n_0\
);
\FSM_sequential_state[3]_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAAAAAAAAAAAAAAA"
)
port map (
I0 => \vtg_lag_reg__0\(31),
I1 => vtg_lag_reg(3),
I2 => vtg_lag_reg(2),
I3 => vtg_lag_reg(0),
I4 => vtg_lag_reg(4),
I5 => vtg_lag_reg(1),
O => \FSM_sequential_state[3]_i_23_n_0\
);
\FSM_sequential_state[3]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \vtg_lag_reg__0\(26),
I1 => \vtg_lag_reg__0\(25),
I2 => \vtg_lag_reg__0\(28),
I3 => \vtg_lag_reg__0\(27),
O => \FSM_sequential_state[3]_i_24_n_0\
);
\FSM_sequential_state[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => state(0),
I1 => state(3),
O => \FSM_sequential_state[3]_i_3_n_0\
);
\FSM_sequential_state[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \FSM_sequential_state[3]_i_10_n_0\,
I1 => \vtg_lag_reg__0\(6),
I2 => \vtg_lag_reg__0\(5),
I3 => \vtg_lag_reg__0\(8),
I4 => \vtg_lag_reg__0\(7),
I5 => \FSM_sequential_state[3]_i_11_n_0\,
O => \FSM_sequential_state[3]_i_4_n_0\
);
\FSM_sequential_state[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => fifo_sof_dly,
I1 => dout(1),
O => p_18_in
);
\FSM_sequential_state[3]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCC8CCC803030003"
)
port map (
I0 => \FSM_sequential_state[3]_i_12_n_0\,
I1 => state(0),
I2 => \next_state1__0\,
I3 => p_25_in,
I4 => \FSM_sequential_state[3]_i_15_n_0\,
I5 => state(3),
O => \FSM_sequential_state[3]_i_6_n_0\
);
\FSM_sequential_state[3]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => vtg_sof_dly,
I1 => fifo_sof_dly,
I2 => dout(1),
I3 => sof_ignore,
I4 => \FSM_sequential_state[3]_i_15_n_0\,
O => next_state124_out
);
\FSM_sequential_state[3]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"E000E000E0000000"
)
port map (
I0 => \FSM_sequential_state[3]_i_16_n_0\,
I1 => \FSM_sequential_state[3]_i_17_n_0\,
I2 => vtg_sof_dly,
I3 => p_18_in,
I4 => \FSM_sequential_state[3]_i_18_n_0\,
I5 => \FSM_sequential_state[3]_i_19_n_0\,
O => next_state121_out
);
\FSM_sequential_state[3]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"00D0"
)
port map (
I0 => fifo_sof_dly,
I1 => dout(1),
I2 => vtg_sof_dly,
I3 => sof_ignore,
O => \FSM_sequential_state[3]_i_9_n_0\
);
\FSM_sequential_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => \FSM_sequential_state[0]_i_1_n_0\,
Q => state(0),
S => \status_reg[20]_i_1_n_0\
);
\FSM_sequential_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => \FSM_sequential_state[1]_i_1_n_0\,
Q => \^q\(0),
R => \status_reg[20]_i_1_n_0\
);
\FSM_sequential_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => \FSM_sequential_state[2]_i_1_n_0\,
Q => \^q\(1),
R => \status_reg[20]_i_1_n_0\
);
\FSM_sequential_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => \FSM_sequential_state[3]_i_1_n_0\,
Q => state(3),
R => \status_reg[20]_i_1_n_0\
);
\fifo_eol_cnt[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => \fifo_pix_cnt_dly[12]_i_1_n_0\,
I1 => fifo_sof_dly,
I2 => dout(1),
I3 => vid_io_out_ce,
O => \fifo_eol_cnt[0]_i_1_n_0\
);
\fifo_eol_cnt[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => vid_io_out_ce,
I1 => fifo_eol_re_dly,
O => fifo_eol_cnt
);
\fifo_eol_cnt[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => fifo_eol_cnt_reg(0),
O => \fifo_eol_cnt[0]_i_4_n_0\
);
\fifo_eol_cnt_dly[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => fifo_sof_dly,
I1 => dout(1),
I2 => vid_io_out_ce,
O => fifo_sof_cnt
);
\fifo_eol_cnt_dly_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => fifo_eol_cnt_reg(0),
Q => fifo_eol_cnt_dly(0),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_eol_cnt_dly_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => fifo_eol_cnt_reg(10),
Q => fifo_eol_cnt_dly(10),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_eol_cnt_dly_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => fifo_eol_cnt_reg(11),
Q => fifo_eol_cnt_dly(11),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_eol_cnt_dly_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => fifo_eol_cnt_reg(12),
Q => fifo_eol_cnt_dly(12),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_eol_cnt_dly_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => fifo_eol_cnt_reg(1),
Q => fifo_eol_cnt_dly(1),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_eol_cnt_dly_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => fifo_eol_cnt_reg(2),
Q => fifo_eol_cnt_dly(2),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_eol_cnt_dly_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => fifo_eol_cnt_reg(3),
Q => fifo_eol_cnt_dly(3),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_eol_cnt_dly_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => fifo_eol_cnt_reg(4),
Q => fifo_eol_cnt_dly(4),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_eol_cnt_dly_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => fifo_eol_cnt_reg(5),
Q => fifo_eol_cnt_dly(5),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_eol_cnt_dly_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => fifo_eol_cnt_reg(6),
Q => fifo_eol_cnt_dly(6),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_eol_cnt_dly_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => fifo_eol_cnt_reg(7),
Q => fifo_eol_cnt_dly(7),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_eol_cnt_dly_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => fifo_eol_cnt_reg(8),
Q => fifo_eol_cnt_dly(8),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_eol_cnt_dly_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => fifo_eol_cnt_reg(9),
Q => fifo_eol_cnt_dly(9),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_eol_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_eol_cnt,
D => \fifo_eol_cnt_reg[0]_i_3_n_7\,
Q => fifo_eol_cnt_reg(0),
R => \fifo_eol_cnt[0]_i_1_n_0\
);
\fifo_eol_cnt_reg[0]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \fifo_eol_cnt_reg[0]_i_3_n_0\,
CO(2) => \fifo_eol_cnt_reg[0]_i_3_n_1\,
CO(1) => \fifo_eol_cnt_reg[0]_i_3_n_2\,
CO(0) => \fifo_eol_cnt_reg[0]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \fifo_eol_cnt_reg[0]_i_3_n_4\,
O(2) => \fifo_eol_cnt_reg[0]_i_3_n_5\,
O(1) => \fifo_eol_cnt_reg[0]_i_3_n_6\,
O(0) => \fifo_eol_cnt_reg[0]_i_3_n_7\,
S(3 downto 1) => fifo_eol_cnt_reg(3 downto 1),
S(0) => \fifo_eol_cnt[0]_i_4_n_0\
);
\fifo_eol_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_eol_cnt,
D => \fifo_eol_cnt_reg[8]_i_1_n_5\,
Q => fifo_eol_cnt_reg(10),
R => \fifo_eol_cnt[0]_i_1_n_0\
);
\fifo_eol_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_eol_cnt,
D => \fifo_eol_cnt_reg[8]_i_1_n_4\,
Q => fifo_eol_cnt_reg(11),
R => \fifo_eol_cnt[0]_i_1_n_0\
);
\fifo_eol_cnt_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_eol_cnt,
D => \fifo_eol_cnt_reg[12]_i_1_n_7\,
Q => fifo_eol_cnt_reg(12),
R => \fifo_eol_cnt[0]_i_1_n_0\
);
\fifo_eol_cnt_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \fifo_eol_cnt_reg[8]_i_1_n_0\,
CO(3 downto 0) => \NLW_fifo_eol_cnt_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_fifo_eol_cnt_reg[12]_i_1_O_UNCONNECTED\(3 downto 1),
O(0) => \fifo_eol_cnt_reg[12]_i_1_n_7\,
S(3 downto 1) => B"000",
S(0) => fifo_eol_cnt_reg(12)
);
\fifo_eol_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_eol_cnt,
D => \fifo_eol_cnt_reg[0]_i_3_n_6\,
Q => fifo_eol_cnt_reg(1),
R => \fifo_eol_cnt[0]_i_1_n_0\
);
\fifo_eol_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_eol_cnt,
D => \fifo_eol_cnt_reg[0]_i_3_n_5\,
Q => fifo_eol_cnt_reg(2),
R => \fifo_eol_cnt[0]_i_1_n_0\
);
\fifo_eol_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_eol_cnt,
D => \fifo_eol_cnt_reg[0]_i_3_n_4\,
Q => fifo_eol_cnt_reg(3),
R => \fifo_eol_cnt[0]_i_1_n_0\
);
\fifo_eol_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_eol_cnt,
D => \fifo_eol_cnt_reg[4]_i_1_n_7\,
Q => fifo_eol_cnt_reg(4),
R => \fifo_eol_cnt[0]_i_1_n_0\
);
\fifo_eol_cnt_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \fifo_eol_cnt_reg[0]_i_3_n_0\,
CO(3) => \fifo_eol_cnt_reg[4]_i_1_n_0\,
CO(2) => \fifo_eol_cnt_reg[4]_i_1_n_1\,
CO(1) => \fifo_eol_cnt_reg[4]_i_1_n_2\,
CO(0) => \fifo_eol_cnt_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \fifo_eol_cnt_reg[4]_i_1_n_4\,
O(2) => \fifo_eol_cnt_reg[4]_i_1_n_5\,
O(1) => \fifo_eol_cnt_reg[4]_i_1_n_6\,
O(0) => \fifo_eol_cnt_reg[4]_i_1_n_7\,
S(3 downto 0) => fifo_eol_cnt_reg(7 downto 4)
);
\fifo_eol_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_eol_cnt,
D => \fifo_eol_cnt_reg[4]_i_1_n_6\,
Q => fifo_eol_cnt_reg(5),
R => \fifo_eol_cnt[0]_i_1_n_0\
);
\fifo_eol_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_eol_cnt,
D => \fifo_eol_cnt_reg[4]_i_1_n_5\,
Q => fifo_eol_cnt_reg(6),
R => \fifo_eol_cnt[0]_i_1_n_0\
);
\fifo_eol_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_eol_cnt,
D => \fifo_eol_cnt_reg[4]_i_1_n_4\,
Q => fifo_eol_cnt_reg(7),
R => \fifo_eol_cnt[0]_i_1_n_0\
);
\fifo_eol_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_eol_cnt,
D => \fifo_eol_cnt_reg[8]_i_1_n_7\,
Q => fifo_eol_cnt_reg(8),
R => \fifo_eol_cnt[0]_i_1_n_0\
);
\fifo_eol_cnt_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \fifo_eol_cnt_reg[4]_i_1_n_0\,
CO(3) => \fifo_eol_cnt_reg[8]_i_1_n_0\,
CO(2) => \fifo_eol_cnt_reg[8]_i_1_n_1\,
CO(1) => \fifo_eol_cnt_reg[8]_i_1_n_2\,
CO(0) => \fifo_eol_cnt_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \fifo_eol_cnt_reg[8]_i_1_n_4\,
O(2) => \fifo_eol_cnt_reg[8]_i_1_n_5\,
O(1) => \fifo_eol_cnt_reg[8]_i_1_n_6\,
O(0) => \fifo_eol_cnt_reg[8]_i_1_n_7\,
S(3 downto 0) => fifo_eol_cnt_reg(11 downto 8)
);
\fifo_eol_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_eol_cnt,
D => \fifo_eol_cnt_reg[8]_i_1_n_6\,
Q => fifo_eol_cnt_reg(9),
R => \fifo_eol_cnt[0]_i_1_n_0\
);
fifo_eol_dly_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => dout(0),
Q => fifo_eol_dly,
R => \status_reg[20]_i_1_n_0\
);
fifo_eol_error1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => fifo_eol_error1_carry_n_0,
CO(2) => fifo_eol_error1_carry_n_1,
CO(1) => fifo_eol_error1_carry_n_2,
CO(0) => fifo_eol_error1_carry_n_3,
CYINIT => '0',
DI(3 downto 0) => B"1111",
O(3 downto 0) => NLW_fifo_eol_error1_carry_O_UNCONNECTED(3 downto 0),
S(3) => fifo_eol_error1_carry_i_1_n_0,
S(2) => fifo_eol_error1_carry_i_2_n_0,
S(1) => fifo_eol_error1_carry_i_3_n_0,
S(0) => fifo_eol_error1_carry_i_4_n_0
);
\fifo_eol_error1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => fifo_eol_error1_carry_n_0,
CO(3 downto 1) => \NLW_fifo_eol_error1_carry__0_CO_UNCONNECTED\(3 downto 1),
CO(0) => fifo_eol_error1,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3 downto 0) => \NLW_fifo_eol_error1_carry__0_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \fifo_eol_error1_carry__0_i_1_n_0\
);
\fifo_eol_error1_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => fifo_eol_cnt_dly(12),
I1 => fifo_eol_cnt_reg(12),
O => \fifo_eol_error1_carry__0_i_1_n_0\
);
fifo_eol_error1_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => fifo_eol_cnt_reg(9),
I1 => fifo_eol_cnt_dly(9),
I2 => fifo_eol_cnt_dly(11),
I3 => fifo_eol_cnt_reg(11),
I4 => fifo_eol_cnt_dly(10),
I5 => fifo_eol_cnt_reg(10),
O => fifo_eol_error1_carry_i_1_n_0
);
fifo_eol_error1_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => fifo_eol_cnt_reg(6),
I1 => fifo_eol_cnt_dly(6),
I2 => fifo_eol_cnt_dly(8),
I3 => fifo_eol_cnt_reg(8),
I4 => fifo_eol_cnt_dly(7),
I5 => fifo_eol_cnt_reg(7),
O => fifo_eol_error1_carry_i_2_n_0
);
fifo_eol_error1_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => fifo_eol_cnt_reg(3),
I1 => fifo_eol_cnt_dly(3),
I2 => fifo_eol_cnt_dly(5),
I3 => fifo_eol_cnt_reg(5),
I4 => fifo_eol_cnt_dly(4),
I5 => fifo_eol_cnt_reg(4),
O => fifo_eol_error1_carry_i_3_n_0
);
fifo_eol_error1_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => fifo_eol_cnt_reg(0),
I1 => fifo_eol_cnt_dly(0),
I2 => fifo_eol_cnt_dly(2),
I3 => fifo_eol_cnt_reg(2),
I4 => fifo_eol_cnt_dly(1),
I5 => fifo_eol_cnt_reg(1),
O => fifo_eol_error1_carry_i_4_n_0
);
fifo_eol_error_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00800000"
)
port map (
I0 => fifo_eol_error1,
I1 => fifo_eol_error2,
I2 => vid_io_out_ce,
I3 => dout(1),
I4 => fifo_sof_dly,
I5 => fifo_eol_error,
O => fifo_eol_error_i_1_n_0
);
fifo_eol_error_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => fifo_eol_error_i_3_n_0,
I1 => fifo_eol_error_i_4_n_0,
I2 => fifo_eol_cnt_dly(7),
I3 => fifo_eol_cnt_dly(6),
I4 => fifo_eol_cnt_dly(9),
I5 => fifo_eol_cnt_dly(8),
O => fifo_eol_error2
);
fifo_eol_error_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => fifo_eol_cnt_dly(1),
I1 => fifo_eol_cnt_dly(4),
I2 => fifo_eol_cnt_dly(5),
I3 => fifo_eol_cnt_dly(2),
I4 => fifo_eol_cnt_dly(3),
O => fifo_eol_error_i_3_n_0
);
fifo_eol_error_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => fifo_eol_cnt_dly(11),
I1 => fifo_eol_cnt_dly(10),
I2 => fifo_eol_cnt_dly(0),
I3 => fifo_eol_cnt_dly(12),
O => fifo_eol_error_i_4_n_0
);
fifo_eol_error_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => fifo_eol_error_i_1_n_0,
Q => fifo_eol_error,
R => \status_reg[20]_i_1_n_0\
);
fifo_eol_re_dly_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => fifo_eol_re,
Q => fifo_eol_re_dly,
R => \status_reg[20]_i_1_n_0\
);
\fifo_pix_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \fifo_pix_cnt_dly[12]_i_1_n_0\,
I1 => fifo_eol_re_dly,
I2 => vid_io_out_ce,
O => \fifo_pix_cnt[0]_i_1_n_0\
);
\fifo_pix_cnt[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8AAA8AA00020000"
)
port map (
I0 => vid_io_out_ce,
I1 => \^q\(0),
I2 => state(3),
I3 => \^q\(1),
I4 => state(0),
I5 => vtg_active_video,
O => fifo_rd_en
);
\fifo_pix_cnt[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => fifo_pix_cnt_reg(0),
O => \fifo_pix_cnt[0]_i_5_n_0\
);
\fifo_pix_cnt_dly[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"10FF"
)
port map (
I0 => state(3),
I1 => \^q\(0),
I2 => state(0),
I3 => aresetn,
O => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_pix_cnt_dly[12]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A800"
)
port map (
I0 => vid_io_out_ce,
I1 => \fifo_pix_cnt_dly[12]_i_3_n_0\,
I2 => \fifo_pix_cnt_dly1__11\,
I3 => fifo_eol_re_dly,
O => fifo_pix_cnt_dly_0
);
\fifo_pix_cnt_dly[12]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \fifo_pix_cnt_dly[12]_i_5_n_0\,
I1 => \fifo_pix_cnt_dly[12]_i_6_n_0\,
I2 => fifo_eol_cnt_reg(7),
I3 => fifo_eol_cnt_reg(6),
I4 => fifo_eol_cnt_reg(9),
I5 => fifo_eol_cnt_reg(8),
O => \fifo_pix_cnt_dly[12]_i_3_n_0\
);
\fifo_pix_cnt_dly[12]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \fifo_pix_cnt_dly[12]_i_7_n_0\,
I1 => \fifo_pix_cnt_dly[12]_i_8_n_0\,
I2 => fifo_pix_cnt_dly(7),
I3 => fifo_pix_cnt_dly(6),
I4 => fifo_pix_cnt_dly(9),
I5 => fifo_pix_cnt_dly(8),
O => \fifo_pix_cnt_dly1__11\
);
\fifo_pix_cnt_dly[12]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => fifo_eol_cnt_reg(1),
I1 => fifo_eol_cnt_reg(4),
I2 => fifo_eol_cnt_reg(5),
I3 => fifo_eol_cnt_reg(2),
I4 => fifo_eol_cnt_reg(3),
O => \fifo_pix_cnt_dly[12]_i_5_n_0\
);
\fifo_pix_cnt_dly[12]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => fifo_eol_cnt_reg(11),
I1 => fifo_eol_cnt_reg(10),
I2 => fifo_eol_cnt_reg(0),
I3 => fifo_eol_cnt_reg(12),
O => \fifo_pix_cnt_dly[12]_i_6_n_0\
);
\fifo_pix_cnt_dly[12]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => fifo_pix_cnt_dly(1),
I1 => fifo_pix_cnt_dly(4),
I2 => fifo_pix_cnt_dly(5),
I3 => fifo_pix_cnt_dly(2),
I4 => fifo_pix_cnt_dly(3),
O => \fifo_pix_cnt_dly[12]_i_7_n_0\
);
\fifo_pix_cnt_dly[12]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => fifo_pix_cnt_dly(11),
I1 => fifo_pix_cnt_dly(10),
I2 => fifo_pix_cnt_dly(0),
I3 => fifo_pix_cnt_dly(12),
O => \fifo_pix_cnt_dly[12]_i_8_n_0\
);
\fifo_pix_cnt_dly_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt_dly_0,
D => fifo_pix_cnt_reg(0),
Q => fifo_pix_cnt_dly(0),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_pix_cnt_dly_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt_dly_0,
D => fifo_pix_cnt_reg(10),
Q => fifo_pix_cnt_dly(10),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_pix_cnt_dly_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt_dly_0,
D => fifo_pix_cnt_reg(11),
Q => fifo_pix_cnt_dly(11),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_pix_cnt_dly_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt_dly_0,
D => fifo_pix_cnt_reg(12),
Q => fifo_pix_cnt_dly(12),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_pix_cnt_dly_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt_dly_0,
D => fifo_pix_cnt_reg(1),
Q => fifo_pix_cnt_dly(1),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_pix_cnt_dly_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt_dly_0,
D => fifo_pix_cnt_reg(2),
Q => fifo_pix_cnt_dly(2),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_pix_cnt_dly_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt_dly_0,
D => fifo_pix_cnt_reg(3),
Q => fifo_pix_cnt_dly(3),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_pix_cnt_dly_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt_dly_0,
D => fifo_pix_cnt_reg(4),
Q => fifo_pix_cnt_dly(4),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_pix_cnt_dly_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt_dly_0,
D => fifo_pix_cnt_reg(5),
Q => fifo_pix_cnt_dly(5),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_pix_cnt_dly_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt_dly_0,
D => fifo_pix_cnt_reg(6),
Q => fifo_pix_cnt_dly(6),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_pix_cnt_dly_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt_dly_0,
D => fifo_pix_cnt_reg(7),
Q => fifo_pix_cnt_dly(7),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_pix_cnt_dly_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt_dly_0,
D => fifo_pix_cnt_reg(8),
Q => fifo_pix_cnt_dly(8),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_pix_cnt_dly_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt_dly_0,
D => fifo_pix_cnt_reg(9),
Q => fifo_pix_cnt_dly(9),
R => \fifo_pix_cnt_dly[12]_i_1_n_0\
);
\fifo_pix_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt,
D => \fifo_pix_cnt_reg[0]_i_3_n_7\,
Q => fifo_pix_cnt_reg(0),
R => \fifo_pix_cnt[0]_i_1_n_0\
);
\fifo_pix_cnt_reg[0]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \fifo_pix_cnt_reg[0]_i_3_n_0\,
CO(2) => \fifo_pix_cnt_reg[0]_i_3_n_1\,
CO(1) => \fifo_pix_cnt_reg[0]_i_3_n_2\,
CO(0) => \fifo_pix_cnt_reg[0]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \fifo_pix_cnt_reg[0]_i_3_n_4\,
O(2) => \fifo_pix_cnt_reg[0]_i_3_n_5\,
O(1) => \fifo_pix_cnt_reg[0]_i_3_n_6\,
O(0) => \fifo_pix_cnt_reg[0]_i_3_n_7\,
S(3 downto 1) => fifo_pix_cnt_reg(3 downto 1),
S(0) => \fifo_pix_cnt[0]_i_5_n_0\
);
\fifo_pix_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt,
D => \fifo_pix_cnt_reg[8]_i_1_n_5\,
Q => fifo_pix_cnt_reg(10),
R => \fifo_pix_cnt[0]_i_1_n_0\
);
\fifo_pix_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt,
D => \fifo_pix_cnt_reg[8]_i_1_n_4\,
Q => fifo_pix_cnt_reg(11),
R => \fifo_pix_cnt[0]_i_1_n_0\
);
\fifo_pix_cnt_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt,
D => \fifo_pix_cnt_reg[12]_i_1_n_7\,
Q => fifo_pix_cnt_reg(12),
R => \fifo_pix_cnt[0]_i_1_n_0\
);
\fifo_pix_cnt_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \fifo_pix_cnt_reg[8]_i_1_n_0\,
CO(3 downto 0) => \NLW_fifo_pix_cnt_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_fifo_pix_cnt_reg[12]_i_1_O_UNCONNECTED\(3 downto 1),
O(0) => \fifo_pix_cnt_reg[12]_i_1_n_7\,
S(3 downto 1) => B"000",
S(0) => fifo_pix_cnt_reg(12)
);
\fifo_pix_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt,
D => \fifo_pix_cnt_reg[0]_i_3_n_6\,
Q => fifo_pix_cnt_reg(1),
R => \fifo_pix_cnt[0]_i_1_n_0\
);
\fifo_pix_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt,
D => \fifo_pix_cnt_reg[0]_i_3_n_5\,
Q => fifo_pix_cnt_reg(2),
R => \fifo_pix_cnt[0]_i_1_n_0\
);
\fifo_pix_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt,
D => \fifo_pix_cnt_reg[0]_i_3_n_4\,
Q => fifo_pix_cnt_reg(3),
R => \fifo_pix_cnt[0]_i_1_n_0\
);
\fifo_pix_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt,
D => \fifo_pix_cnt_reg[4]_i_1_n_7\,
Q => fifo_pix_cnt_reg(4),
R => \fifo_pix_cnt[0]_i_1_n_0\
);
\fifo_pix_cnt_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \fifo_pix_cnt_reg[0]_i_3_n_0\,
CO(3) => \fifo_pix_cnt_reg[4]_i_1_n_0\,
CO(2) => \fifo_pix_cnt_reg[4]_i_1_n_1\,
CO(1) => \fifo_pix_cnt_reg[4]_i_1_n_2\,
CO(0) => \fifo_pix_cnt_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \fifo_pix_cnt_reg[4]_i_1_n_4\,
O(2) => \fifo_pix_cnt_reg[4]_i_1_n_5\,
O(1) => \fifo_pix_cnt_reg[4]_i_1_n_6\,
O(0) => \fifo_pix_cnt_reg[4]_i_1_n_7\,
S(3 downto 0) => fifo_pix_cnt_reg(7 downto 4)
);
\fifo_pix_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt,
D => \fifo_pix_cnt_reg[4]_i_1_n_6\,
Q => fifo_pix_cnt_reg(5),
R => \fifo_pix_cnt[0]_i_1_n_0\
);
\fifo_pix_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt,
D => \fifo_pix_cnt_reg[4]_i_1_n_5\,
Q => fifo_pix_cnt_reg(6),
R => \fifo_pix_cnt[0]_i_1_n_0\
);
\fifo_pix_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt,
D => \fifo_pix_cnt_reg[4]_i_1_n_4\,
Q => fifo_pix_cnt_reg(7),
R => \fifo_pix_cnt[0]_i_1_n_0\
);
\fifo_pix_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt,
D => \fifo_pix_cnt_reg[8]_i_1_n_7\,
Q => fifo_pix_cnt_reg(8),
R => \fifo_pix_cnt[0]_i_1_n_0\
);
\fifo_pix_cnt_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \fifo_pix_cnt_reg[4]_i_1_n_0\,
CO(3) => \fifo_pix_cnt_reg[8]_i_1_n_0\,
CO(2) => \fifo_pix_cnt_reg[8]_i_1_n_1\,
CO(1) => \fifo_pix_cnt_reg[8]_i_1_n_2\,
CO(0) => \fifo_pix_cnt_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \fifo_pix_cnt_reg[8]_i_1_n_4\,
O(2) => \fifo_pix_cnt_reg[8]_i_1_n_5\,
O(1) => \fifo_pix_cnt_reg[8]_i_1_n_6\,
O(0) => \fifo_pix_cnt_reg[8]_i_1_n_7\,
S(3 downto 0) => fifo_pix_cnt_reg(11 downto 8)
);
\fifo_pix_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_pix_cnt,
D => \fifo_pix_cnt_reg[8]_i_1_n_6\,
Q => fifo_pix_cnt_reg(9),
R => \fifo_pix_cnt[0]_i_1_n_0\
);
fifo_pix_error1_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => fifo_pix_error1_carry_n_0,
CO(2) => fifo_pix_error1_carry_n_1,
CO(1) => fifo_pix_error1_carry_n_2,
CO(0) => fifo_pix_error1_carry_n_3,
CYINIT => '0',
DI(3 downto 0) => B"1111",
O(3 downto 0) => NLW_fifo_pix_error1_carry_O_UNCONNECTED(3 downto 0),
S(3) => fifo_pix_error1_carry_i_1_n_0,
S(2) => fifo_pix_error1_carry_i_2_n_0,
S(1) => fifo_pix_error1_carry_i_3_n_0,
S(0) => fifo_pix_error1_carry_i_4_n_0
);
\fifo_pix_error1_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => fifo_pix_error1_carry_n_0,
CO(3 downto 1) => \NLW_fifo_pix_error1_carry__0_CO_UNCONNECTED\(3 downto 1),
CO(0) => fifo_pix_error1,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3 downto 0) => \NLW_fifo_pix_error1_carry__0_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \fifo_pix_error1_carry__0_i_1_n_0\
);
\fifo_pix_error1_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => fifo_pix_cnt_dly(12),
I1 => fifo_pix_cnt_reg(12),
O => \fifo_pix_error1_carry__0_i_1_n_0\
);
fifo_pix_error1_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => fifo_pix_cnt_reg(9),
I1 => fifo_pix_cnt_dly(9),
I2 => fifo_pix_cnt_dly(11),
I3 => fifo_pix_cnt_reg(11),
I4 => fifo_pix_cnt_dly(10),
I5 => fifo_pix_cnt_reg(10),
O => fifo_pix_error1_carry_i_1_n_0
);
fifo_pix_error1_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => fifo_pix_cnt_reg(6),
I1 => fifo_pix_cnt_dly(6),
I2 => fifo_pix_cnt_dly(8),
I3 => fifo_pix_cnt_reg(8),
I4 => fifo_pix_cnt_dly(7),
I5 => fifo_pix_cnt_reg(7),
O => fifo_pix_error1_carry_i_2_n_0
);
fifo_pix_error1_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => fifo_pix_cnt_reg(3),
I1 => fifo_pix_cnt_dly(3),
I2 => fifo_pix_cnt_dly(5),
I3 => fifo_pix_cnt_reg(5),
I4 => fifo_pix_cnt_dly(4),
I5 => fifo_pix_cnt_reg(4),
O => fifo_pix_error1_carry_i_3_n_0
);
fifo_pix_error1_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => fifo_pix_cnt_reg(0),
I1 => fifo_pix_cnt_dly(0),
I2 => fifo_pix_cnt_dly(2),
I3 => fifo_pix_cnt_reg(2),
I4 => fifo_pix_cnt_dly(1),
I5 => fifo_pix_cnt_reg(1),
O => fifo_pix_error1_carry_i_4_n_0
);
fifo_pix_error_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF7AA00"
)
port map (
I0 => vid_io_out_ce,
I1 => fifo_sof_dly,
I2 => dout(1),
I3 => fifo_pix_error0,
I4 => fifo_pix_error,
O => fifo_pix_error_i_1_n_0
);
fifo_pix_error_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => fifo_eol_re_dly,
I1 => \fifo_pix_cnt_dly1__11\,
I2 => fifo_pix_error1,
O => fifo_pix_error0
);
fifo_pix_error_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => fifo_pix_error_i_1_n_0,
Q => fifo_pix_error,
R => \status_reg[20]_i_1_n_0\
);
\fifo_sof_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => fifo_sof_cnt_reg(0),
O => \p_0_in__0\(0)
);
\fifo_sof_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => fifo_sof_cnt_reg(0),
I1 => fifo_sof_cnt_reg(1),
O => \p_0_in__0\(1)
);
\fifo_sof_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => fifo_sof_cnt_reg(0),
I1 => fifo_sof_cnt_reg(1),
I2 => fifo_sof_cnt_reg(2),
O => \p_0_in__0\(2)
);
\fifo_sof_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => fifo_sof_cnt_reg(1),
I1 => fifo_sof_cnt_reg(0),
I2 => fifo_sof_cnt_reg(2),
I3 => fifo_sof_cnt_reg(3),
O => \p_0_in__0\(3)
);
\fifo_sof_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => fifo_sof_cnt_reg(2),
I1 => fifo_sof_cnt_reg(0),
I2 => fifo_sof_cnt_reg(1),
I3 => fifo_sof_cnt_reg(3),
I4 => fifo_sof_cnt_reg(4),
O => \p_0_in__0\(4)
);
\fifo_sof_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => fifo_sof_cnt_reg(3),
I1 => fifo_sof_cnt_reg(1),
I2 => fifo_sof_cnt_reg(0),
I3 => fifo_sof_cnt_reg(2),
I4 => fifo_sof_cnt_reg(4),
I5 => fifo_sof_cnt_reg(5),
O => \p_0_in__0\(5)
);
\fifo_sof_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => fifo_sof_cnt_reg(4),
I1 => fifo_sof_cnt_reg(2),
I2 => \fifo_sof_cnt[6]_i_2_n_0\,
I3 => fifo_sof_cnt_reg(3),
I4 => fifo_sof_cnt_reg(5),
I5 => fifo_sof_cnt_reg(6),
O => \p_0_in__0\(6)
);
\fifo_sof_cnt[6]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => fifo_sof_cnt_reg(1),
I1 => fifo_sof_cnt_reg(0),
O => \fifo_sof_cnt[6]_i_2_n_0\
);
\fifo_sof_cnt[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \fifo_sof_cnt[7]_i_2_n_0\,
I1 => fifo_sof_cnt_reg(6),
I2 => fifo_sof_cnt_reg(7),
O => \p_0_in__0\(7)
);
\fifo_sof_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => fifo_sof_cnt_reg(5),
I1 => fifo_sof_cnt_reg(3),
I2 => fifo_sof_cnt_reg(1),
I3 => fifo_sof_cnt_reg(0),
I4 => fifo_sof_cnt_reg(2),
I5 => fifo_sof_cnt_reg(4),
O => \fifo_sof_cnt[7]_i_2_n_0\
);
\fifo_sof_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => \p_0_in__0\(0),
Q => fifo_sof_cnt_reg(0),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
\fifo_sof_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => \p_0_in__0\(1),
Q => fifo_sof_cnt_reg(1),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
\fifo_sof_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => \p_0_in__0\(2),
Q => fifo_sof_cnt_reg(2),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
\fifo_sof_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => \p_0_in__0\(3),
Q => fifo_sof_cnt_reg(3),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
\fifo_sof_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => \p_0_in__0\(4),
Q => fifo_sof_cnt_reg(4),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
\fifo_sof_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => \p_0_in__0\(5),
Q => fifo_sof_cnt_reg(5),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
\fifo_sof_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => \p_0_in__0\(6),
Q => fifo_sof_cnt_reg(6),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
\fifo_sof_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => fifo_sof_cnt,
D => \p_0_in__0\(7),
Q => fifo_sof_cnt_reg(7),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
fifo_sof_dly_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => dout(1),
Q => fifo_sof_dly,
R => \status_reg[20]_i_1_n_0\
);
\in_data_mux[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA0E00000000"
)
port map (
I0 => vtg_active_video,
I1 => state(0),
I2 => \^q\(1),
I3 => state(3),
I4 => \^q\(0),
I5 => vid_io_out_ce,
O => E(0)
);
in_de_mux_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^src_in\,
I1 => aresetn,
I2 => fivid_reset_full_frame,
O => SR(0)
);
locked_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => state(0),
I1 => state(3),
I2 => \^q\(1),
I3 => \^q\(0),
O => locked_i_1_n_0
);
locked_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => locked_i_1_n_0,
Q => \^src_in\,
R => '0'
);
sof_ignore_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFDF00"
)
port map (
I0 => vid_io_out_ce,
I1 => dout(2),
I2 => \fifo_pix_cnt_dly[12]_i_3_n_0\,
I3 => sof_ignore,
I4 => \vtg_lag[0]_i_1_n_0\,
O => sof_ignore_i_1_n_0
);
sof_ignore_reg: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => sof_ignore_i_1_n_0,
Q => sof_ignore,
R => '0'
);
\state_dly[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4C3"
)
port map (
I0 => \^q\(0),
I1 => state(3),
I2 => \^q\(1),
I3 => state(0),
O => state_reg(0)
);
\state_dly[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"401F"
)
port map (
I0 => state(3),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => state(0),
O => state_reg(1)
);
\state_dly[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1708"
)
port map (
I0 => state(3),
I1 => state(0),
I2 => \^q\(1),
I3 => \^q\(0),
O => state_reg(2)
);
\state_dly[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aresetn,
I1 => vid_io_out_ce,
O => \state_dly[3]_i_1_n_0\
);
\state_dly[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8C4"
)
port map (
I0 => state(0),
I1 => state(3),
I2 => \^q\(1),
I3 => \^q\(0),
O => state_reg(3)
);
\state_dly_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \state_dly[3]_i_1_n_0\,
D => state_reg(0),
Q => state_dly(0),
R => '0'
);
\state_dly_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \state_dly[3]_i_1_n_0\,
D => state_reg(1),
Q => state_dly(1),
R => '0'
);
\state_dly_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \state_dly[3]_i_1_n_0\,
D => state_reg(2),
Q => state_dly(2),
R => '0'
);
\state_dly_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \state_dly[3]_i_1_n_0\,
D => state_reg(3),
Q => state_dly(3),
R => '0'
);
\status_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00080000"
)
port map (
I0 => vid_io_out_ce,
I1 => status_reg1,
I2 => state(3),
I3 => \^q\(1),
I4 => \status_reg[0]_i_2_n_0\,
I5 => \^status\(0),
O => \status_reg[0]_i_1_n_0\
);
\status_reg[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => \^q\(0),
O => \status_reg[0]_i_2_n_0\
);
\status_reg[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002FFFF00020000"
)
port map (
I0 => state(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => state(0),
I4 => \status_reg[10]_i_2_n_0\,
I5 => \^status\(10),
O => \status_reg[10]_i_1_n_0\
);
\status_reg[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000080000"
)
port map (
I0 => vid_io_out_ce,
I1 => status_reg1,
I2 => \^q\(1),
I3 => state(0),
I4 => state(3),
I5 => \^q\(0),
O => \status_reg[10]_i_2_n_0\
);
\status_reg[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000080"
)
port map (
I0 => vid_io_out_ce,
I1 => status_reg1,
I2 => \^q\(1),
I3 => state(3),
I4 => \status_reg[11]_i_3_n_0\,
I5 => \^status\(11),
O => \status_reg[11]_i_1_n_0\
);
\status_reg[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F6FFFFF6"
)
port map (
I0 => state_dly(3),
I1 => state_reg(3),
I2 => \status_reg[11]_i_4_n_0\,
I3 => state_reg(0),
I4 => state_dly(0),
O => status_reg1
);
\status_reg[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^q\(0),
I1 => state(0),
O => \status_reg[11]_i_3_n_0\
);
\status_reg[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"EDEBEB77EEEDBEDD"
)
port map (
I0 => state_dly(1),
I1 => state_dly(2),
I2 => state(3),
I3 => state(0),
I4 => \^q\(1),
I5 => \^q\(0),
O => \status_reg[11]_i_4_n_0\
);
\status_reg[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020FFFF00200000"
)
port map (
I0 => \^q\(0),
I1 => state(0),
I2 => \^q\(1),
I3 => state(3),
I4 => \status_reg[12]_i_2_n_0\,
I5 => \^status\(12),
O => \status_reg[12]_i_1_n_0\
);
\status_reg[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000008000"
)
port map (
I0 => vid_io_out_ce,
I1 => status_reg1,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => state(3),
I5 => state(0),
O => \status_reg[12]_i_2_n_0\
);
\status_reg[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020FFFF00200000"
)
port map (
I0 => state(0),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => state(3),
I4 => \status_reg[1]_i_2_n_0\,
I5 => \^status\(1),
O => \status_reg[1]_i_1_n_0\
);
\status_reg[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => vid_io_out_ce,
I1 => status_reg1,
I2 => state(3),
I3 => \^q\(0),
I4 => state(0),
I5 => \^q\(1),
O => \status_reg[1]_i_2_n_0\
);
\status_reg[20]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => \status_reg[20]_i_1_n_0\
);
\status_reg[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010FFFF00100000"
)
port map (
I0 => \^q\(0),
I1 => state(0),
I2 => \^q\(1),
I3 => state(3),
I4 => \status_reg[2]_i_2_n_0\,
I5 => \^status\(2),
O => \status_reg[2]_i_1_n_0\
);
\status_reg[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000080000"
)
port map (
I0 => vid_io_out_ce,
I1 => status_reg1,
I2 => state(3),
I3 => state(0),
I4 => \^q\(1),
I5 => \^q\(0),
O => \status_reg[2]_i_2_n_0\
);
\status_reg[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00080000"
)
port map (
I0 => vid_io_out_ce,
I1 => status_reg1,
I2 => state(3),
I3 => \^q\(1),
I4 => \status_reg[9]_i_2_n_0\,
I5 => \^status\(3),
O => \status_reg[3]_i_1_n_0\
);
\status_reg[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000008"
)
port map (
I0 => vid_io_out_ce,
I1 => status_reg1,
I2 => state(3),
I3 => \^q\(1),
I4 => \status_reg[11]_i_3_n_0\,
I5 => \^status\(4),
O => \status_reg[4]_i_1_n_0\
);
\status_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020FFFF00200000"
)
port map (
I0 => state(3),
I1 => \^q\(1),
I2 => state(0),
I3 => \^q\(0),
I4 => \status_reg[5]_i_2_n_0\,
I5 => \^status\(5),
O => \status_reg[5]_i_1_n_0\
);
\status_reg[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => vid_io_out_ce,
I1 => status_reg1,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => state(0),
I5 => state(3),
O => \status_reg[5]_i_2_n_0\
);
\status_reg[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020FFFF00200000"
)
port map (
I0 => state(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => state(0),
I4 => \status_reg[6]_i_2_n_0\,
I5 => \^status\(6),
O => \status_reg[6]_i_1_n_0\
);
\status_reg[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => vid_io_out_ce,
I1 => status_reg1,
I2 => state(0),
I3 => \^q\(1),
I4 => \^q\(0),
I5 => state(3),
O => \status_reg[6]_i_2_n_0\
);
\status_reg[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00080000"
)
port map (
I0 => vid_io_out_ce,
I1 => status_reg1,
I2 => state(3),
I3 => \^q\(1),
I4 => \status_reg[7]_i_2_n_0\,
I5 => \^status\(7),
O => \status_reg[7]_i_1_n_0\
);
\status_reg[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(0),
I1 => state(0),
O => \status_reg[7]_i_2_n_0\
);
\status_reg[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000800"
)
port map (
I0 => vid_io_out_ce,
I1 => status_reg1,
I2 => \^q\(1),
I3 => state(3),
I4 => \status_reg[11]_i_3_n_0\,
I5 => \^status\(8),
O => \status_reg[8]_i_1_n_0\
);
\status_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF80000000"
)
port map (
I0 => vid_io_out_ce,
I1 => status_reg1,
I2 => \status_reg[9]_i_2_n_0\,
I3 => state(3),
I4 => \^q\(1),
I5 => \^status\(9),
O => \status_reg[9]_i_1_n_0\
);
\status_reg[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
I1 => state(0),
O => \status_reg[9]_i_2_n_0\
);
\status_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \status_reg[0]_i_1_n_0\,
Q => \^status\(0),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \status_reg[10]_i_1_n_0\,
Q => \^status\(10),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \status_reg[11]_i_1_n_0\,
Q => \^status\(11),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \status_reg[12]_i_1_n_0\,
Q => \^status\(12),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => fifo_pix_error,
Q => \^status\(13),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => fifo_eol_error,
Q => \^status\(14),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => vtg_lag_reg(0),
Q => \^status\(15),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => vtg_lag_reg(1),
Q => \^status\(16),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => vtg_lag_reg(2),
Q => \^status\(17),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => vtg_lag_reg(3),
Q => \^status\(18),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \status_reg[1]_i_1_n_0\,
Q => \^status\(1),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => vtg_lag_reg(4),
Q => \^status\(19),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \status_reg[2]_i_1_n_0\,
Q => \^status\(2),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \status_reg[3]_i_1_n_0\,
Q => \^status\(3),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \status_reg[4]_i_1_n_0\,
Q => \^status\(4),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \status_reg[5]_i_1_n_0\,
Q => \^status\(5),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \status_reg[6]_i_1_n_0\,
Q => \^status\(6),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \status_reg[7]_i_1_n_0\,
Q => \^status\(7),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \status_reg[8]_i_1_n_0\,
Q => \^status\(8),
R => \status_reg[20]_i_1_n_0\
);
\status_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \status_reg[9]_i_1_n_0\,
Q => \^status\(9),
R => \status_reg[20]_i_1_n_0\
);
vtg_de_dly_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => vtg_active_video,
Q => vtg_de_dly,
R => \status_reg[20]_i_1_n_0\
);
\vtg_lag[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0100FFFF"
)
port map (
I0 => state(3),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => state(0),
I4 => aresetn,
O => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200002"
)
port map (
I0 => vid_io_out_ce,
I1 => \^q\(0),
I2 => state(3),
I3 => \^q\(1),
I4 => state(0),
O => vtg_lag
);
\vtg_lag[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => vtg_lag_reg(0),
O => \vtg_lag[0]_i_4_n_0\
);
\vtg_lag_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[0]_i_3_n_7\,
Q => vtg_lag_reg(0),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[0]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \vtg_lag_reg[0]_i_3_n_0\,
CO(2) => \vtg_lag_reg[0]_i_3_n_1\,
CO(1) => \vtg_lag_reg[0]_i_3_n_2\,
CO(0) => \vtg_lag_reg[0]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \vtg_lag_reg[0]_i_3_n_4\,
O(2) => \vtg_lag_reg[0]_i_3_n_5\,
O(1) => \vtg_lag_reg[0]_i_3_n_6\,
O(0) => \vtg_lag_reg[0]_i_3_n_7\,
S(3 downto 1) => vtg_lag_reg(3 downto 1),
S(0) => \vtg_lag[0]_i_4_n_0\
);
\vtg_lag_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[8]_i_1_n_5\,
Q => \vtg_lag_reg__0\(10),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[8]_i_1_n_4\,
Q => \vtg_lag_reg__0\(11),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[12]_i_1_n_7\,
Q => \vtg_lag_reg__0\(12),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vtg_lag_reg[8]_i_1_n_0\,
CO(3) => \vtg_lag_reg[12]_i_1_n_0\,
CO(2) => \vtg_lag_reg[12]_i_1_n_1\,
CO(1) => \vtg_lag_reg[12]_i_1_n_2\,
CO(0) => \vtg_lag_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vtg_lag_reg[12]_i_1_n_4\,
O(2) => \vtg_lag_reg[12]_i_1_n_5\,
O(1) => \vtg_lag_reg[12]_i_1_n_6\,
O(0) => \vtg_lag_reg[12]_i_1_n_7\,
S(3 downto 0) => \vtg_lag_reg__0\(15 downto 12)
);
\vtg_lag_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[12]_i_1_n_6\,
Q => \vtg_lag_reg__0\(13),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[12]_i_1_n_5\,
Q => \vtg_lag_reg__0\(14),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[12]_i_1_n_4\,
Q => \vtg_lag_reg__0\(15),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[16]_i_1_n_7\,
Q => \vtg_lag_reg__0\(16),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vtg_lag_reg[12]_i_1_n_0\,
CO(3) => \vtg_lag_reg[16]_i_1_n_0\,
CO(2) => \vtg_lag_reg[16]_i_1_n_1\,
CO(1) => \vtg_lag_reg[16]_i_1_n_2\,
CO(0) => \vtg_lag_reg[16]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vtg_lag_reg[16]_i_1_n_4\,
O(2) => \vtg_lag_reg[16]_i_1_n_5\,
O(1) => \vtg_lag_reg[16]_i_1_n_6\,
O(0) => \vtg_lag_reg[16]_i_1_n_7\,
S(3 downto 0) => \vtg_lag_reg__0\(19 downto 16)
);
\vtg_lag_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[16]_i_1_n_6\,
Q => \vtg_lag_reg__0\(17),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[16]_i_1_n_5\,
Q => \vtg_lag_reg__0\(18),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[16]_i_1_n_4\,
Q => \vtg_lag_reg__0\(19),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[0]_i_3_n_6\,
Q => vtg_lag_reg(1),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[20]_i_1_n_7\,
Q => \vtg_lag_reg__0\(20),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vtg_lag_reg[16]_i_1_n_0\,
CO(3) => \vtg_lag_reg[20]_i_1_n_0\,
CO(2) => \vtg_lag_reg[20]_i_1_n_1\,
CO(1) => \vtg_lag_reg[20]_i_1_n_2\,
CO(0) => \vtg_lag_reg[20]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vtg_lag_reg[20]_i_1_n_4\,
O(2) => \vtg_lag_reg[20]_i_1_n_5\,
O(1) => \vtg_lag_reg[20]_i_1_n_6\,
O(0) => \vtg_lag_reg[20]_i_1_n_7\,
S(3 downto 0) => \vtg_lag_reg__0\(23 downto 20)
);
\vtg_lag_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[20]_i_1_n_6\,
Q => \vtg_lag_reg__0\(21),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[20]_i_1_n_5\,
Q => \vtg_lag_reg__0\(22),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[20]_i_1_n_4\,
Q => \vtg_lag_reg__0\(23),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[24]_i_1_n_7\,
Q => \vtg_lag_reg__0\(24),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[24]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vtg_lag_reg[20]_i_1_n_0\,
CO(3) => \vtg_lag_reg[24]_i_1_n_0\,
CO(2) => \vtg_lag_reg[24]_i_1_n_1\,
CO(1) => \vtg_lag_reg[24]_i_1_n_2\,
CO(0) => \vtg_lag_reg[24]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vtg_lag_reg[24]_i_1_n_4\,
O(2) => \vtg_lag_reg[24]_i_1_n_5\,
O(1) => \vtg_lag_reg[24]_i_1_n_6\,
O(0) => \vtg_lag_reg[24]_i_1_n_7\,
S(3 downto 0) => \vtg_lag_reg__0\(27 downto 24)
);
\vtg_lag_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[24]_i_1_n_6\,
Q => \vtg_lag_reg__0\(25),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[24]_i_1_n_5\,
Q => \vtg_lag_reg__0\(26),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[24]_i_1_n_4\,
Q => \vtg_lag_reg__0\(27),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[28]_i_1_n_7\,
Q => \vtg_lag_reg__0\(28),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[28]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vtg_lag_reg[24]_i_1_n_0\,
CO(3) => \NLW_vtg_lag_reg[28]_i_1_CO_UNCONNECTED\(3),
CO(2) => \vtg_lag_reg[28]_i_1_n_1\,
CO(1) => \vtg_lag_reg[28]_i_1_n_2\,
CO(0) => \vtg_lag_reg[28]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vtg_lag_reg[28]_i_1_n_4\,
O(2) => \vtg_lag_reg[28]_i_1_n_5\,
O(1) => \vtg_lag_reg[28]_i_1_n_6\,
O(0) => \vtg_lag_reg[28]_i_1_n_7\,
S(3 downto 0) => \vtg_lag_reg__0\(31 downto 28)
);
\vtg_lag_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[28]_i_1_n_6\,
Q => \vtg_lag_reg__0\(29),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[0]_i_3_n_5\,
Q => vtg_lag_reg(2),
S => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[28]_i_1_n_5\,
Q => \vtg_lag_reg__0\(30),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[28]_i_1_n_4\,
Q => \vtg_lag_reg__0\(31),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[0]_i_3_n_4\,
Q => vtg_lag_reg(3),
S => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[4]_i_1_n_7\,
Q => vtg_lag_reg(4),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vtg_lag_reg[0]_i_3_n_0\,
CO(3) => \vtg_lag_reg[4]_i_1_n_0\,
CO(2) => \vtg_lag_reg[4]_i_1_n_1\,
CO(1) => \vtg_lag_reg[4]_i_1_n_2\,
CO(0) => \vtg_lag_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vtg_lag_reg[4]_i_1_n_4\,
O(2) => \vtg_lag_reg[4]_i_1_n_5\,
O(1) => \vtg_lag_reg[4]_i_1_n_6\,
O(0) => \vtg_lag_reg[4]_i_1_n_7\,
S(3 downto 1) => \vtg_lag_reg__0\(7 downto 5),
S(0) => vtg_lag_reg(4)
);
\vtg_lag_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[4]_i_1_n_6\,
Q => \vtg_lag_reg__0\(5),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[4]_i_1_n_5\,
Q => \vtg_lag_reg__0\(6),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[4]_i_1_n_4\,
Q => \vtg_lag_reg__0\(7),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[8]_i_1_n_7\,
Q => \vtg_lag_reg__0\(8),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_lag_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vtg_lag_reg[4]_i_1_n_0\,
CO(3) => \vtg_lag_reg[8]_i_1_n_0\,
CO(2) => \vtg_lag_reg[8]_i_1_n_1\,
CO(1) => \vtg_lag_reg[8]_i_1_n_2\,
CO(0) => \vtg_lag_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vtg_lag_reg[8]_i_1_n_4\,
O(2) => \vtg_lag_reg[8]_i_1_n_5\,
O(1) => \vtg_lag_reg[8]_i_1_n_6\,
O(0) => \vtg_lag_reg[8]_i_1_n_7\,
S(3 downto 0) => \vtg_lag_reg__0\(11 downto 8)
);
\vtg_lag_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_lag,
D => \vtg_lag_reg[8]_i_1_n_6\,
Q => \vtg_lag_reg__0\(9),
R => \vtg_lag[0]_i_1_n_0\
);
\vtg_sof_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => vtg_sof_cnt_reg(0),
O => p_0_in(0)
);
\vtg_sof_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => vtg_sof_cnt_reg(0),
I1 => vtg_sof_cnt_reg(1),
O => p_0_in(1)
);
\vtg_sof_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => vtg_sof_cnt_reg(0),
I1 => vtg_sof_cnt_reg(1),
I2 => vtg_sof_cnt_reg(2),
O => p_0_in(2)
);
\vtg_sof_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => vtg_sof_cnt_reg(1),
I1 => vtg_sof_cnt_reg(0),
I2 => vtg_sof_cnt_reg(2),
I3 => vtg_sof_cnt_reg(3),
O => p_0_in(3)
);
\vtg_sof_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => vtg_sof_cnt_reg(2),
I1 => vtg_sof_cnt_reg(0),
I2 => vtg_sof_cnt_reg(1),
I3 => vtg_sof_cnt_reg(3),
I4 => vtg_sof_cnt_reg(4),
O => p_0_in(4)
);
\vtg_sof_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => vtg_sof_cnt_reg(3),
I1 => vtg_sof_cnt_reg(1),
I2 => vtg_sof_cnt_reg(0),
I3 => vtg_sof_cnt_reg(2),
I4 => vtg_sof_cnt_reg(4),
I5 => vtg_sof_cnt_reg(5),
O => p_0_in(5)
);
\vtg_sof_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => vtg_sof_cnt_reg(4),
I1 => vtg_sof_cnt_reg(2),
I2 => \vtg_sof_cnt[6]_i_2_n_0\,
I3 => vtg_sof_cnt_reg(3),
I4 => vtg_sof_cnt_reg(5),
I5 => vtg_sof_cnt_reg(6),
O => p_0_in(6)
);
\vtg_sof_cnt[6]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => vtg_sof_cnt_reg(1),
I1 => vtg_sof_cnt_reg(0),
O => \vtg_sof_cnt[6]_i_2_n_0\
);
\vtg_sof_cnt[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"063BFFFF"
)
port map (
I0 => state(0),
I1 => state(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => aresetn,
O => \vtg_sof_cnt[7]_i_1_n_0\
);
\vtg_sof_cnt[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => vid_io_out_ce,
I1 => vtg_sof_dly,
O => vtg_sof_cnt
);
\vtg_sof_cnt[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \vtg_sof_cnt[7]_i_4_n_0\,
I1 => vtg_sof_cnt_reg(6),
I2 => vtg_sof_cnt_reg(7),
O => p_0_in(7)
);
\vtg_sof_cnt[7]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => vtg_sof_cnt_reg(5),
I1 => vtg_sof_cnt_reg(3),
I2 => vtg_sof_cnt_reg(1),
I3 => vtg_sof_cnt_reg(0),
I4 => vtg_sof_cnt_reg(2),
I5 => vtg_sof_cnt_reg(4),
O => \vtg_sof_cnt[7]_i_4_n_0\
);
\vtg_sof_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_sof_cnt,
D => p_0_in(0),
Q => vtg_sof_cnt_reg(0),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
\vtg_sof_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_sof_cnt,
D => p_0_in(1),
Q => vtg_sof_cnt_reg(1),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
\vtg_sof_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_sof_cnt,
D => p_0_in(2),
Q => vtg_sof_cnt_reg(2),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
\vtg_sof_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_sof_cnt,
D => p_0_in(3),
Q => vtg_sof_cnt_reg(3),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
\vtg_sof_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_sof_cnt,
D => p_0_in(4),
Q => vtg_sof_cnt_reg(4),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
\vtg_sof_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_sof_cnt,
D => p_0_in(5),
Q => vtg_sof_cnt_reg(5),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
\vtg_sof_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_sof_cnt,
D => p_0_in(6),
Q => vtg_sof_cnt_reg(6),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
\vtg_sof_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vtg_sof_cnt,
D => p_0_in(7),
Q => vtg_sof_cnt_reg(7),
R => \vtg_sof_cnt[7]_i_1_n_0\
);
vtg_sof_dly_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => vtg_active_video,
I1 => vtg_vsync_bp_reg_n_0,
I2 => vtg_de_dly,
O => vtg_sof
);
vtg_sof_dly_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => vtg_sof,
Q => vtg_sof_dly,
R => \status_reg[20]_i_1_n_0\
);
vtg_vsync_bp_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AEAA0000"
)
port map (
I0 => vtg_vsync_bp_reg_n_0,
I1 => vid_io_out_ce,
I2 => vtg_vsync,
I3 => vtg_vsync_dly,
I4 => aresetn,
I5 => vtg_de_dly,
O => vtg_vsync_bp_i_1_n_0
);
vtg_vsync_bp_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => vtg_vsync_bp_i_1_n_0,
Q => vtg_vsync_bp_reg_n_0,
R => '0'
);
vtg_vsync_dly_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => vid_io_out_ce,
D => vtg_vsync,
Q => vtg_vsync_dly,
R => \status_reg[20]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single : entity is 4;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single : entity is "xpm_cdc_single";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single : entity is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single : entity is 0;
attribute VERSION : integer;
attribute VERSION of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single : entity is "SINGLE";
end hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single;
architecture STRUCTURE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single is
signal syncstages_ff : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[3]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[3]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[3]\ : label is "SINGLE";
begin
dest_out <= syncstages_ff(3);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => src_in,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(1),
Q => syncstages_ff(2),
R => '0'
);
\syncstages_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(2),
Q => syncstages_ff(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single__2\ is
port (
src_clk : in STD_LOGIC;
src_in : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_out : out STD_LOGIC
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single__2\ : entity is 4;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single__2\ : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single__2\ : entity is "xpm_cdc_single";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single__2\ : entity is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single__2\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single__2\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single__2\ : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single__2\ : entity is "SINGLE";
end \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single__2\;
architecture STRUCTURE of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single__2\ is
signal syncstages_ff : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SINGLE";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[3]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[3]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[3]\ : label is "SINGLE";
begin
dest_out <= syncstages_ff(3);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => src_in,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(1),
Q => syncstages_ff(2),
R => '0'
);
\syncstages_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(2),
Q => syncstages_ff(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn is
port (
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
count_value_i : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
ram_empty_i : in STD_LOGIC;
\count_value_i_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn : entity is "xpm_counter_updn";
end hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn;
architecture STRUCTURE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn is
signal \^count_value_i\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_2_n_0\ : STD_LOGIC;
begin
count_value_i(1 downto 0) <= \^count_value_i\(1 downto 0);
\count_value_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1222211110202121"
)
port map (
I0 => \^count_value_i\(0),
I1 => \count_value_i_reg[0]_1\(0),
I2 => \count_value_i_reg[0]_0\(1),
I3 => rd_en,
I4 => ram_empty_i,
I5 => \count_value_i_reg[0]_0\(0),
O => \count_value_i[0]_i_1_n_0\
);
\count_value_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"22222022"
)
port map (
I0 => \count_value_i[1]_i_2_n_0\,
I1 => \count_value_i_reg[0]_1\(0),
I2 => \count_value_i_reg[0]_0\(1),
I3 => ram_empty_i,
I4 => \count_value_i_reg[0]_0\(0),
O => \count_value_i[1]_i_1_n_0\
);
\count_value_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BFD5BFDD402A4022"
)
port map (
I0 => \^count_value_i\(0),
I1 => \count_value_i_reg[0]_0\(1),
I2 => rd_en,
I3 => ram_empty_i,
I4 => \count_value_i_reg[0]_0\(0),
I5 => \^count_value_i\(1),
O => \count_value_i[1]_i_2_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \count_value_i[0]_i_1_n_0\,
Q => \^count_value_i\(0),
R => '0'
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \count_value_i[1]_i_1_n_0\,
Q => \^count_value_i\(1),
R => '0'
);
\gwdc.wr_data_count_i[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^count_value_i\(0),
I1 => Q(0),
O => DI(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\count_value_i_reg[4]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
\count_value_i_reg[0]_0\ : out STD_LOGIC;
\count_value_i_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\count_value_i_reg[1]_1\ : out STD_LOGIC;
ram_rd_en_pf : out STD_LOGIC;
\count_value_i_reg[3]_0\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 1 downto 0 );
\count_value_i_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
p_16_in : in STD_LOGIC;
write_allow : in STD_LOGIC;
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]\ : in STD_LOGIC;
ram_wr_en_pf : in STD_LOGIC;
\count_value_i_reg[5]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
ram_empty_i : in STD_LOGIC;
count_value_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
\count_value_i_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized0\ : entity is "xpm_counter_updn";
end \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized0\;
architecture STRUCTURE of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized0\ is
signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_2__0_n_0\ : STD_LOGIC;
signal \^count_value_i_reg[0]_0\ : STD_LOGIC;
signal \^count_value_i_reg[1]_1\ : STD_LOGIC;
signal \^count_value_i_reg[4]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \count_value_i_reg_n_0_[5]\ : STD_LOGIC;
signal \^ram_rd_en_pf\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[0]_i_1__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \count_value_i[1]_i_1__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \count_value_i[4]_i_1__1\ : label is "soft_lutpair1";
begin
\count_value_i_reg[0]_0\ <= \^count_value_i_reg[0]_0\;
\count_value_i_reg[1]_1\ <= \^count_value_i_reg[1]_1\;
\count_value_i_reg[4]_0\(4 downto 0) <= \^count_value_i_reg[4]_0\(4 downto 0);
ram_rd_en_pf <= \^ram_rd_en_pf\;
\count_value_i[0]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"04FB"
)
port map (
I0 => rd_en,
I1 => \count_value_i_reg[5]_0\(1),
I2 => \count_value_i_reg[5]_0\(0),
I3 => \^count_value_i_reg[4]_0\(0),
O => \count_value_i[0]_i_1__1_n_0\
);
\count_value_i[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FFFB00"
)
port map (
I0 => \count_value_i_reg[5]_0\(0),
I1 => \count_value_i_reg[5]_0\(1),
I2 => rd_en,
I3 => \^count_value_i_reg[4]_0\(0),
I4 => \^count_value_i_reg[4]_0\(1),
O => \count_value_i[1]_i_1__1_n_0\
);
\count_value_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^count_value_i_reg[4]_0\(0),
I1 => \^count_value_i_reg[4]_0\(1),
I2 => \^count_value_i_reg[4]_0\(2),
O => \count_value_i[2]_i_1__1_n_0\
);
\count_value_i[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^count_value_i_reg[4]_0\(1),
I1 => \^count_value_i_reg[4]_0\(0),
I2 => \^count_value_i_reg[4]_0\(2),
I3 => \^count_value_i_reg[4]_0\(3),
O => \count_value_i[3]_i_1__1_n_0\
);
\count_value_i[4]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^count_value_i_reg[4]_0\(2),
I1 => \^count_value_i_reg[4]_0\(0),
I2 => \^count_value_i_reg[4]_0\(1),
I3 => \^count_value_i_reg[4]_0\(3),
I4 => \^count_value_i_reg[4]_0\(4),
O => \count_value_i[4]_i_1__1_n_0\
);
\count_value_i[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^count_value_i_reg[4]_0\(3),
I1 => \count_value_i[5]_i_2__0_n_0\,
I2 => \^count_value_i_reg[4]_0\(2),
I3 => \^count_value_i_reg[4]_0\(4),
I4 => \count_value_i_reg_n_0_[5]\,
O => \count_value_i[5]_i_1__0_n_0\
);
\count_value_i[5]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AA8A00000000"
)
port map (
I0 => \^count_value_i_reg[4]_0\(1),
I1 => \count_value_i_reg[5]_0\(0),
I2 => \count_value_i_reg[5]_0\(1),
I3 => rd_en,
I4 => ram_empty_i,
I5 => \^count_value_i_reg[4]_0\(0),
O => \count_value_i[5]_i_2__0_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^ram_rd_en_pf\,
D => \count_value_i[0]_i_1__1_n_0\,
Q => \^count_value_i_reg[4]_0\(0),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^ram_rd_en_pf\,
D => \count_value_i[1]_i_1__1_n_0\,
Q => \^count_value_i_reg[4]_0\(1),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^ram_rd_en_pf\,
D => \count_value_i[2]_i_1__1_n_0\,
Q => \^count_value_i_reg[4]_0\(2),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^ram_rd_en_pf\,
D => \count_value_i[3]_i_1__1_n_0\,
Q => \^count_value_i_reg[4]_0\(3),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^ram_rd_en_pf\,
D => \count_value_i[4]_i_1__1_n_0\,
Q => \^count_value_i_reg[4]_0\(4),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^ram_rd_en_pf\,
D => \count_value_i[5]_i_1__0_n_0\,
Q => \count_value_i_reg_n_0_[5]\,
R => \count_value_i_reg[0]_1\(0)
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4DB2B24D"
)
port map (
I0 => Q(2),
I1 => \^count_value_i_reg[4]_0\(2),
I2 => \^count_value_i_reg[0]_0\,
I3 => \^count_value_i_reg[4]_0\(3),
I4 => Q(3),
O => D(0)
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7510000FFFFF751"
)
port map (
I0 => \^count_value_i_reg[4]_0\(0),
I1 => p_16_in,
I2 => write_allow,
I3 => Q(0),
I4 => Q(1),
I5 => \^count_value_i_reg[4]_0\(1),
O => \^count_value_i_reg[0]_0\
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"69699669"
)
port map (
I0 => \^count_value_i_reg[1]_1\,
I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\(2),
I2 => \^count_value_i_reg[4]_0\(2),
I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\(1),
I4 => \^count_value_i_reg[4]_0\(1),
O => \count_value_i_reg[1]_0\(0)
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0BF4BF4040BF0BF4"
)
port map (
I0 => \^count_value_i_reg[4]_0\(1),
I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\(1),
I2 => \^count_value_i_reg[1]_1\,
I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]\,
I4 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\(2),
I5 => \^count_value_i_reg[4]_0\(2),
O => \count_value_i_reg[1]_0\(1)
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0090000090999090"
)
port map (
I0 => \^count_value_i_reg[4]_0\(1),
I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\(1),
I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\(0),
I3 => \^ram_rd_en_pf\,
I4 => ram_wr_en_pf,
I5 => \^count_value_i_reg[4]_0\(0),
O => \^count_value_i_reg[1]_1\
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[5]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^count_value_i_reg[4]_0\(3),
I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\(3),
I2 => \^count_value_i_reg[4]_0\(4),
I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\(4),
O => \count_value_i_reg[3]_0\
);
\gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \count_value_i_reg[5]_0\(0),
I1 => \count_value_i_reg[5]_0\(1),
I2 => rd_en,
I3 => ram_empty_i,
O => \^ram_rd_en_pf\
);
\gwdc.wr_data_count_i[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^count_value_i_reg[4]_0\(2),
I1 => Q(2),
I2 => \^count_value_i_reg[4]_0\(3),
I3 => Q(3),
O => \count_value_i_reg[2]_0\(2)
);
\gwdc.wr_data_count_i[3]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"D22D2DD2"
)
port map (
I0 => \^count_value_i_reg[4]_0\(0),
I1 => count_value_i(0),
I2 => count_value_i(1),
I3 => \^count_value_i_reg[4]_0\(1),
I4 => Q(1),
O => \count_value_i_reg[2]_0\(1)
);
\gwdc.wr_data_count_i[3]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^count_value_i_reg[4]_0\(0),
I1 => count_value_i(0),
I2 => Q(0),
O => \count_value_i_reg[2]_0\(0)
);
\gwdc.wr_data_count_i[5]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^count_value_i_reg[4]_0\(4),
I1 => Q(4),
I2 => \count_value_i_reg_n_0_[5]\,
I3 => Q(5),
O => S(1)
);
\gwdc.wr_data_count_i[5]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^count_value_i_reg[4]_0\(3),
I1 => Q(3),
I2 => \^count_value_i_reg[4]_0\(4),
I3 => Q(4),
O => S(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized0_0\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_i0 : out STD_LOGIC;
leaving_empty0 : out STD_LOGIC;
\count_value_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[0]\ : in STD_LOGIC;
ram_rd_en_pf : in STD_LOGIC;
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[0]_0\ : in STD_LOGIC;
ram_wr_en_pf : in STD_LOGIC;
read_only : in STD_LOGIC;
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]_0\ : in STD_LOGIC;
ram_empty_i : in STD_LOGIC;
\gen_pntr_flags_cc.ram_empty_i_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
\count_value_i_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rst_d1 : in STD_LOGIC;
\gen_pntr_flags_cc.ram_empty_i_reg_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
DI : in STD_LOGIC_VECTOR ( 0 to 0 );
\grdc.rd_data_count_i_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
S : in STD_LOGIC_VECTOR ( 1 downto 0 );
count_value_i : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized0_0\ : entity is "xpm_counter_updn";
end \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized0_0\;
architecture STRUCTURE of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized0_0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_2_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_6_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[2]_i_2_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[4]_i_3_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[3]_i_2_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[3]_i_3_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[3]_i_6_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[5]_i_2_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[5]_i_1_n_3\ : STD_LOGIC;
signal \^leaving_empty0\ : STD_LOGIC;
signal \NLW_gwdc.wr_data_count_i_reg[5]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gwdc.wr_data_count_i_reg[5]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \count_value_i[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_pntr_flags_cc.ram_empty_i_i_3\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[2]_i_2\ : label is "soft_lutpair4";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
leaving_empty0 <= \^leaving_empty0\;
\count_value_i[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \count_value_i[0]_i_1_n_0\
);
\count_value_i[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \count_value_i[1]_i_1_n_0\
);
\count_value_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \count_value_i[2]_i_1_n_0\
);
\count_value_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \count_value_i[3]_i_1_n_0\
);
\count_value_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \count_value_i[4]_i_1_n_0\
);
\count_value_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(3),
I1 => \count_value_i[5]_i_2_n_0\,
I2 => \^q\(2),
I3 => \^q\(4),
I4 => \^q\(5),
O => \count_value_i[5]_i_1_n_0\
);
\count_value_i[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => \^q\(1),
I1 => wr_en,
I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[0]_0\,
I3 => \count_value_i_reg[5]_0\(0),
I4 => rst_d1,
I5 => \^q\(0),
O => \count_value_i[5]_i_2_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => ram_wr_en_pf,
D => \count_value_i[0]_i_1_n_0\,
Q => \^q\(0),
R => \count_value_i_reg[5]_0\(0)
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => ram_wr_en_pf,
D => \count_value_i[1]_i_1_n_0\,
Q => \^q\(1),
R => \count_value_i_reg[5]_0\(0)
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => ram_wr_en_pf,
D => \count_value_i[2]_i_1_n_0\,
Q => \^q\(2),
R => \count_value_i_reg[5]_0\(0)
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => ram_wr_en_pf,
D => \count_value_i[3]_i_1_n_0\,
Q => \^q\(3),
R => \count_value_i_reg[5]_0\(0)
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => ram_wr_en_pf,
D => \count_value_i[4]_i_1_n_0\,
Q => \^q\(4),
R => \count_value_i_reg[5]_0\(0)
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => ram_wr_en_pf,
D => \count_value_i[5]_i_1_n_0\,
Q => \^q\(5),
R => \count_value_i_reg[5]_0\(0)
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"82000082"
)
port map (
I0 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_6_n_0\,
I1 => \^q\(3),
I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(3),
I3 => \^q\(2),
I4 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(2),
O => \^leaving_empty0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(4),
I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(4),
I2 => \^q\(1),
I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(1),
I4 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(0),
I5 => \^q\(0),
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_6_n_0\
);
\gen_pntr_flags_cc.ram_empty_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22FA22AA22AA22AA"
)
port map (
I0 => ram_empty_i,
I1 => \^leaving_empty0\,
I2 => \gen_pntr_flags_cc.ram_empty_i_reg\,
I3 => ram_wr_en_pf,
I4 => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\,
I5 => ram_rd_en_pf,
O => ram_empty_i0
);
\gen_pntr_flags_cc.ram_empty_i_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(1),
I1 => \gen_pntr_flags_cc.ram_empty_i_reg_0\(1),
I2 => \^q\(0),
I3 => \gen_pntr_flags_cc.ram_empty_i_reg_0\(0),
O => \gen_pntr_flags_cc.ram_empty_i_i_3_n_0\
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6966666669666966"
)
port map (
I0 => \^q\(0),
I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(0),
I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[0]\,
I3 => ram_rd_en_pf,
I4 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[0]_0\,
I5 => ram_wr_en_pf,
O => D(0)
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D42B2BD4"
)
port map (
I0 => \^q\(0),
I1 => read_only,
I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(0),
I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(1),
I4 => \^q\(1),
O => D(1)
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB2B2B2244D4D4DD"
)
port map (
I0 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(1),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => read_only,
I4 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(0),
I5 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[2]_i_2_n_0\,
O => D(2)
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(2),
O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[2]_i_2_n_0\
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4D44DD4DB2BB22B2"
)
port map (
I0 => \^q\(3),
I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(3),
I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]_0\,
I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(2),
I4 => \^q\(2),
I5 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[4]_i_3_n_0\,
O => D(3)
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(4),
O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[4]_i_3_n_0\
);
\gwdc.wr_data_count_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(3),
O => \gwdc.wr_data_count_i[3]_i_2_n_0\
);
\gwdc.wr_data_count_i[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(2),
O => \gwdc.wr_data_count_i[3]_i_3_n_0\
);
\gwdc.wr_data_count_i[3]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"4DB2B24D"
)
port map (
I0 => \^q\(1),
I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(1),
I2 => count_value_i(0),
I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(2),
I4 => \^q\(2),
O => \gwdc.wr_data_count_i[3]_i_6_n_0\
);
\gwdc.wr_data_count_i[5]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(4),
O => \gwdc.wr_data_count_i[5]_i_2_n_0\
);
\gwdc.wr_data_count_i_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gwdc.wr_data_count_i_reg[3]_i_1_n_0\,
CO(2) => \gwdc.wr_data_count_i_reg[3]_i_1_n_1\,
CO(1) => \gwdc.wr_data_count_i_reg[3]_i_1_n_2\,
CO(0) => \gwdc.wr_data_count_i_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3) => \gwdc.wr_data_count_i[3]_i_2_n_0\,
DI(2) => \gwdc.wr_data_count_i[3]_i_3_n_0\,
DI(1) => DI(0),
DI(0) => \^q\(0),
O(3 downto 0) => \count_value_i_reg[0]_0\(3 downto 0),
S(3) => \grdc.rd_data_count_i_reg[3]\(2),
S(2) => \gwdc.wr_data_count_i[3]_i_6_n_0\,
S(1 downto 0) => \grdc.rd_data_count_i_reg[3]\(1 downto 0)
);
\gwdc.wr_data_count_i_reg[5]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gwdc.wr_data_count_i_reg[3]_i_1_n_0\,
CO(3 downto 1) => \NLW_gwdc.wr_data_count_i_reg[5]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \gwdc.wr_data_count_i_reg[5]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \gwdc.wr_data_count_i[5]_i_2_n_0\,
O(3 downto 2) => \NLW_gwdc.wr_data_count_i_reg[5]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \count_value_i_reg[0]_0\(5 downto 4),
S(3 downto 2) => B"00",
S(1 downto 0) => S(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized1\ is
port (
\count_value_i_reg[3]_0\ : out STD_LOGIC;
\count_value_i_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
\count_value_i_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
\count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_rd_en_pf : in STD_LOGIC;
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized1\ : entity is "xpm_counter_updn";
end \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized1\;
architecture STRUCTURE of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized1\ is
signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \^count_value_i_reg[1]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \count_value_i_reg_n_0_[2]\ : STD_LOGIC;
signal \count_value_i_reg_n_0_[3]\ : STD_LOGIC;
signal \count_value_i_reg_n_0_[4]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \count_value_i[4]_i_1__2\ : label is "soft_lutpair2";
begin
\count_value_i_reg[1]_0\(1 downto 0) <= \^count_value_i_reg[1]_0\(1 downto 0);
\count_value_i[0]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"04FB"
)
port map (
I0 => rd_en,
I1 => \count_value_i_reg[1]_1\(1),
I2 => \count_value_i_reg[1]_1\(0),
I3 => \^count_value_i_reg[1]_0\(0),
O => \count_value_i[0]_i_1__2_n_0\
);
\count_value_i[1]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FFFB00"
)
port map (
I0 => \count_value_i_reg[1]_1\(0),
I1 => \count_value_i_reg[1]_1\(1),
I2 => rd_en,
I3 => \^count_value_i_reg[1]_0\(0),
I4 => \^count_value_i_reg[1]_0\(1),
O => \count_value_i[1]_i_1__2_n_0\
);
\count_value_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^count_value_i_reg[1]_0\(0),
I1 => \^count_value_i_reg[1]_0\(1),
I2 => \count_value_i_reg_n_0_[2]\,
O => \count_value_i[2]_i_1__2_n_0\
);
\count_value_i[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^count_value_i_reg[1]_0\(1),
I1 => \^count_value_i_reg[1]_0\(0),
I2 => \count_value_i_reg_n_0_[2]\,
I3 => \count_value_i_reg_n_0_[3]\,
O => \count_value_i[3]_i_1__2_n_0\
);
\count_value_i[4]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \count_value_i_reg_n_0_[2]\,
I1 => \^count_value_i_reg[1]_0\(0),
I2 => \^count_value_i_reg[1]_0\(1),
I3 => \count_value_i_reg_n_0_[3]\,
I4 => \count_value_i_reg_n_0_[4]\,
O => \count_value_i[4]_i_1__2_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => ram_rd_en_pf,
D => \count_value_i[0]_i_1__2_n_0\,
Q => \^count_value_i_reg[1]_0\(0),
S => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => ram_rd_en_pf,
D => \count_value_i[1]_i_1__2_n_0\,
Q => \^count_value_i_reg[1]_0\(1),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => ram_rd_en_pf,
D => \count_value_i[2]_i_1__2_n_0\,
Q => \count_value_i_reg_n_0_[2]\,
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => ram_rd_en_pf,
D => \count_value_i[3]_i_1__2_n_0\,
Q => \count_value_i_reg_n_0_[3]\,
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => ram_rd_en_pf,
D => \count_value_i[4]_i_1__2_n_0\,
Q => \count_value_i_reg_n_0_[4]\,
R => \count_value_i_reg[0]_0\(0)
);
\gen_pntr_flags_cc.ram_empty_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \count_value_i_reg_n_0_[3]\,
I1 => Q(1),
I2 => \count_value_i_reg_n_0_[4]\,
I3 => Q(2),
I4 => \count_value_i_reg_n_0_[2]\,
I5 => Q(0),
O => \count_value_i_reg[3]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized1_1\ is
port (
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\count_value_i_reg[3]_0\ : out STD_LOGIC;
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg\ : out STD_LOGIC;
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
ram_wr_en_pf : in STD_LOGIC;
ram_rd_en_pf : in STD_LOGIC;
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\ : in STD_LOGIC;
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]_0\ : in STD_LOGIC;
leaving_empty0 : in STD_LOGIC;
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1\ : in STD_LOGIC;
clr_full : in STD_LOGIC;
\count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized1_1\ : entity is "xpm_counter_updn";
end \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized1_1\;
architecture STRUCTURE of \hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized1_1\ is
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \^count_value_i_reg[3]_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_2_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_5_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[5]_i_4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[1]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \count_value_i[4]_i_1__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_2\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[1]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[5]_i_2\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[5]_i_4\ : label is "soft_lutpair11";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
\count_value_i_reg[3]_0\ <= \^count_value_i_reg[3]_0\;
\count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \count_value_i[0]_i_1__0_n_0\
);
\count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \count_value_i[1]_i_1__0_n_0\
);
\count_value_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \count_value_i[2]_i_1__0_n_0\
);
\count_value_i[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \count_value_i[3]_i_1__0_n_0\
);
\count_value_i[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \count_value_i[4]_i_1__0_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => ram_wr_en_pf,
D => \count_value_i[0]_i_1__0_n_0\,
Q => \^q\(0),
S => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => ram_wr_en_pf,
D => \count_value_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => ram_wr_en_pf,
D => \count_value_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => ram_wr_en_pf,
D => \count_value_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => ram_wr_en_pf,
D => \count_value_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => \count_value_i_reg[0]_0\(0)
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000033FF2020"
)
port map (
I0 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_2_n_0\,
I1 => ram_rd_en_pf,
I2 => ram_wr_en_pf,
I3 => leaving_empty0,
I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1\,
I5 => clr_full,
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"82000082"
)
port map (
I0 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_5_n_0\,
I1 => \^q\(4),
I2 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\(4),
I3 => \^q\(3),
I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\(3),
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_2_n_0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\(2),
I2 => \^q\(1),
I3 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\(1),
I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\(0),
I5 => \^q\(0),
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_5_n_0\
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9969"
)
port map (
I0 => \^q\(0),
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\(0),
I2 => ram_wr_en_pf,
I3 => ram_rd_en_pf,
O => D(0)
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF4520BA20BADF45"
)
port map (
I0 => \^q\(0),
I1 => ram_rd_en_pf,
I2 => ram_wr_en_pf,
I3 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\(0),
I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\(1),
I5 => \^q\(1),
O => D(1)
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"455D5DDFBAA2A220"
)
port map (
I0 => \^count_value_i_reg[3]_0\,
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\(2),
I2 => \^q\(2),
I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\,
I4 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[5]_i_4_n_0\,
I5 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]_0\,
O => D(2)
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[5]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\(3),
O => \^count_value_i_reg[3]_0\
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[5]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\(1),
O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q[5]_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_reg_bit is
port (
rst_d1 : out STD_LOGIC;
write_allow : out STD_LOGIC;
clr_full : out STD_LOGIC;
write_only : out STD_LOGIC;
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_rd_en_pf_q_reg\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg\ : in STD_LOGIC;
rst : in STD_LOGIC;
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0\ : in STD_LOGIC;
ram_rd_en_pf : in STD_LOGIC;
prog_full_i217_in : in STD_LOGIC;
ram_rd_en_pf_q : in STD_LOGIC;
ram_wr_en_pf_q : in STD_LOGIC;
prog_full : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_reg_bit : entity is "xpm_fifo_reg_bit";
end hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_reg_bit;
architecture STRUCTURE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_reg_bit is
signal \^clr_full\ : STD_LOGIC;
signal \^rst_d1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_4\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[4]_i_5\ : label is "soft_lutpair3";
begin
clr_full <= \^clr_full\;
rst_d1 <= \^rst_d1\;
d_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => Q(0),
Q => \^rst_d1\,
R => '0'
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => rst,
I1 => \^rst_d1\,
I2 => Q(0),
O => \^clr_full\
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[4]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => \^rst_d1\,
I1 => Q(0),
I2 => wr_en,
I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg\,
O => write_allow
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"04000404"
)
port map (
I0 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg\,
I1 => wr_en,
I2 => \^rst_d1\,
I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0\,
I4 => ram_rd_en_pf,
O => write_only
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"55150400"
)
port map (
I0 => \^clr_full\,
I1 => prog_full_i217_in,
I2 => ram_rd_en_pf_q,
I3 => ram_wr_en_pf_q,
I4 => prog_full,
O => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_rd_en_pf_q_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_rst is
port (
overflow_i0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
read_only : out STD_LOGIC;
ram_wr_en_pf : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\ : out STD_LOGIC;
underflow_i0 : out STD_LOGIC;
rst : in STD_LOGIC;
\gof.overflow_i_reg\ : in STD_LOGIC;
rst_d1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.read_only_q_reg\ : in STD_LOGIC;
ram_rd_en_pf : in STD_LOGIC;
\grdc.rd_data_count_i_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
prog_empty : in STD_LOGIC;
write_only_q : in STD_LOGIC;
read_only_q : in STD_LOGIC;
prog_empty_i1 : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_rst : entity is "xpm_fifo_rst";
end hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_rst;
architecture STRUCTURE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_rst is
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_rst_cc.fifo_wr_rst_cc\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_0_in : STD_LOGIC;
signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC;
signal rst_i : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gof.overflow_i_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \grdc.rd_data_count_i[5]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \guf.underflow_i_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of wr_rst_busy_INST_0 : label is "soft_lutpair12";
begin
Q(0) <= \^q\(0);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFAEEEEE"
)
port map (
I0 => \^q\(0),
I1 => prog_empty,
I2 => write_only_q,
I3 => read_only_q,
I4 => prog_empty_i1,
O => \gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.read_only_q_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444044"
)
port map (
I0 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.read_only_q_reg\,
I1 => ram_rd_en_pf,
I2 => \gof.overflow_i_reg\,
I3 => wr_en,
I4 => \^q\(0),
I5 => rst_d1,
O => read_only
);
\gen_rst_cc.fifo_wr_rst_cc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_0_in,
I1 => rst,
O => rst_i
);
\gen_rst_cc.fifo_wr_rst_cc_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
Q => \gen_rst_cc.fifo_wr_rst_cc\(0),
S => rst_i
);
\gen_rst_cc.fifo_wr_rst_cc_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \gen_rst_cc.fifo_wr_rst_cc\(0),
Q => \gen_rst_cc.fifo_wr_rst_cc\(1),
S => rst_i
);
\gen_rst_cc.fifo_wr_rst_cc_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \gen_rst_cc.fifo_wr_rst_cc\(1),
Q => \^q\(0),
S => rst_i
);
\gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => wr_en,
I1 => \gof.overflow_i_reg\,
I2 => \^q\(0),
I3 => rst_d1,
O => ram_wr_en_pf
);
\gof.overflow_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => \gof.overflow_i_reg\,
I1 => \^q\(0),
I2 => rst_d1,
I3 => wr_en,
O => overflow_i0
);
\grdc.rd_data_count_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F1"
)
port map (
I0 => \grdc.rd_data_count_i_reg[0]\(0),
I1 => \grdc.rd_data_count_i_reg[0]\(1),
I2 => \^q\(0),
O => SR(0)
);
\guf.underflow_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E0"
)
port map (
I0 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.read_only_q_reg\,
I1 => \^q\(0),
I2 => rd_en,
O => underflow_i0
);
\power_on_rst_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
Q => \power_on_rst_reg_n_0_[0]\,
R => '0'
);
\power_on_rst_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \power_on_rst_reg_n_0_[0]\,
Q => p_0_in,
R => '0'
);
wr_rst_busy_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^q\(0),
I1 => rst_d1,
O => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base is
port (
sleep : in STD_LOGIC;
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
dina : in STD_LOGIC_VECTOR ( 26 downto 0 );
injectsbiterra : in STD_LOGIC;
injectdbiterra : in STD_LOGIC;
douta : out STD_LOGIC_VECTOR ( 26 downto 0 );
sbiterra : out STD_LOGIC;
dbiterra : out STD_LOGIC;
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 26 downto 0 );
injectsbiterrb : in STD_LOGIC;
injectdbiterrb : in STD_LOGIC;
doutb : out STD_LOGIC_VECTOR ( 26 downto 0 );
sbiterrb : out STD_LOGIC;
dbiterrb : out STD_LOGIC
);
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 5;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 5;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 27;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 27;
attribute CASCADE_HEIGHT : integer;
attribute CASCADE_HEIGHT of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is "";
attribute MEMORY_OPTIMIZATION : string;
attribute MEMORY_OPTIMIZATION of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is "true";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 864;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 1;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is "xpm_memory_base";
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 32;
attribute P_MEMORY_OPT : string;
attribute P_MEMORY_OPT of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is "yes";
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is "auto";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 27;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 27;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 27;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 27;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 27;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 1;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 5;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 5;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 5;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 5;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 27;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 27;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 27;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 27;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 2;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 2;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is "0";
attribute RST_MODE_A : string;
attribute RST_MODE_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is "SYNC";
attribute RST_MODE_B : string;
attribute RST_MODE_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is "SYNC";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute USE_EMBEDDED_CONSTRAINT : integer;
attribute USE_EMBEDDED_CONSTRAINT of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute VERSION : integer;
attribute VERSION of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 27;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 27;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 2;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 2;
attribute XPM_MODULE : string;
attribute XPM_MODULE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is "TRUE";
attribute rsta_loop_iter : integer;
attribute rsta_loop_iter of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 28;
attribute rstb_loop_iter : integer;
attribute rstb_loop_iter of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base : entity is 28;
end hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base;
architecture STRUCTURE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base is
signal \<const0>\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg0\ : STD_LOGIC_VECTOR ( 26 downto 0 );
signal \gen_rd_b.doutb_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[10]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[11]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[12]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[13]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[14]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[15]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[16]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[17]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[18]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[19]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[20]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[21]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[22]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[23]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[24]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[25]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[26]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[2]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[3]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[4]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[5]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[6]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[7]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[8]\ : STD_LOGIC;
signal \gen_rd_b.doutb_reg_reg_n_0_[9]\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_12_17_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26_DOB_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26_DOC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_6_11_DOD_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute dram_emb_xdc : string;
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[0]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[10]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[11]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[12]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[13]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[14]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[15]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[16]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[17]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[18]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[19]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[1]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[20]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[21]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[22]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[23]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[24]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[25]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[26]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[2]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[3]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[4]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[5]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[6]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[7]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[8]\ : label is "no";
attribute dram_emb_xdc of \gen_rd_b.doutb_reg_reg[9]\ : label is "no";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5\ : label is "";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5\ : label is 864;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute ram_addr_begin : integer;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5\ : label is 0;
attribute ram_addr_end : integer;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5\ : label is 31;
attribute ram_offset : integer;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5\ : label is 0;
attribute ram_slice_begin : integer;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5\ : label is 0;
attribute ram_slice_end : integer;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5\ : label is 5;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_12_17\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_12_17\ : label is 864;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_12_17\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_12_17\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_12_17\ : label is 31;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_12_17\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_12_17\ : label is 12;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_12_17\ : label is 17;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23\ : label is 864;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23\ : label is 31;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23\ : label is 18;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23\ : label is 23;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26\ : label is 864;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26\ : label is 31;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26\ : label is 24;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26\ : label is 26;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_6_11\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31_6_11\ : label is 864;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31_6_11\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_6_11\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_6_11\ : label is 31;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31_6_11\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31_6_11\ : label is 6;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31_6_11\ : label is 11;
begin
dbiterra <= \<const0>\;
dbiterrb <= \<const0>\;
douta(26) <= \<const0>\;
douta(25) <= \<const0>\;
douta(24) <= \<const0>\;
douta(23) <= \<const0>\;
douta(22) <= \<const0>\;
douta(21) <= \<const0>\;
douta(20) <= \<const0>\;
douta(19) <= \<const0>\;
douta(18) <= \<const0>\;
douta(17) <= \<const0>\;
douta(16) <= \<const0>\;
douta(15) <= \<const0>\;
douta(14) <= \<const0>\;
douta(13) <= \<const0>\;
douta(12) <= \<const0>\;
douta(11) <= \<const0>\;
douta(10) <= \<const0>\;
douta(9) <= \<const0>\;
douta(8) <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
sbiterra <= \<const0>\;
sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_rd_b.doutb_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(0),
Q => \gen_rd_b.doutb_reg_reg_n_0_[0]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(10),
Q => \gen_rd_b.doutb_reg_reg_n_0_[10]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(11),
Q => \gen_rd_b.doutb_reg_reg_n_0_[11]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(12),
Q => \gen_rd_b.doutb_reg_reg_n_0_[12]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(13),
Q => \gen_rd_b.doutb_reg_reg_n_0_[13]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(14),
Q => \gen_rd_b.doutb_reg_reg_n_0_[14]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(15),
Q => \gen_rd_b.doutb_reg_reg_n_0_[15]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(16),
Q => \gen_rd_b.doutb_reg_reg_n_0_[16]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(17),
Q => \gen_rd_b.doutb_reg_reg_n_0_[17]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(18),
Q => \gen_rd_b.doutb_reg_reg_n_0_[18]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(19),
Q => \gen_rd_b.doutb_reg_reg_n_0_[19]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(1),
Q => \gen_rd_b.doutb_reg_reg_n_0_[1]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(20),
Q => \gen_rd_b.doutb_reg_reg_n_0_[20]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(21),
Q => \gen_rd_b.doutb_reg_reg_n_0_[21]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(22),
Q => \gen_rd_b.doutb_reg_reg_n_0_[22]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(23),
Q => \gen_rd_b.doutb_reg_reg_n_0_[23]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(24),
Q => \gen_rd_b.doutb_reg_reg_n_0_[24]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(25),
Q => \gen_rd_b.doutb_reg_reg_n_0_[25]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(26),
Q => \gen_rd_b.doutb_reg_reg_n_0_[26]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(2),
Q => \gen_rd_b.doutb_reg_reg_n_0_[2]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(3),
Q => \gen_rd_b.doutb_reg_reg_n_0_[3]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(4),
Q => \gen_rd_b.doutb_reg_reg_n_0_[4]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(5),
Q => \gen_rd_b.doutb_reg_reg_n_0_[5]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(6),
Q => \gen_rd_b.doutb_reg_reg_n_0_[6]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(7),
Q => \gen_rd_b.doutb_reg_reg_n_0_[7]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(8),
Q => \gen_rd_b.doutb_reg_reg_n_0_[8]\,
R => '0'
);
\gen_rd_b.doutb_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => enb,
D => \gen_rd_b.doutb_reg0\(9),
Q => \gen_rd_b.doutb_reg_reg_n_0_[9]\,
R => '0'
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[0]\,
Q => doutb(0),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[10]\,
Q => doutb(10),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[11]\,
Q => doutb(11),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[12]\,
Q => doutb(12),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[13]\,
Q => doutb(13),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[14]\,
Q => doutb(14),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[15]\,
Q => doutb(15),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[16]\,
Q => doutb(16),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[17]\,
Q => doutb(17),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[18]\,
Q => doutb(18),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[19]\,
Q => doutb(19),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[1]\,
Q => doutb(1),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[20]\,
Q => doutb(20),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[21]\,
Q => doutb(21),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[22]\,
Q => doutb(22),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[23]\,
Q => doutb(23),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[24]\,
Q => doutb(24),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[25]\,
Q => doutb(25),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[26]\,
Q => doutb(26),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[2]\,
Q => doutb(2),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[3]\,
Q => doutb(3),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[4]\,
Q => doutb(4),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[5]\,
Q => doutb(5),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[6]\,
Q => doutb(6),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[7]\,
Q => doutb(7),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[8]\,
Q => doutb(8),
R => rstb
);
\gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => regceb,
D => \gen_rd_b.doutb_reg_reg_n_0_[9]\,
Q => doutb(9),
R => rstb
);
\gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4 downto 0) => addrb(4 downto 0),
ADDRB(4 downto 0) => addrb(4 downto 0),
ADDRC(4 downto 0) => addrb(4 downto 0),
ADDRD(4 downto 0) => addra(4 downto 0),
DIA(1 downto 0) => dina(1 downto 0),
DIB(1 downto 0) => dina(3 downto 2),
DIC(1 downto 0) => dina(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => \gen_rd_b.doutb_reg0\(1 downto 0),
DOB(1 downto 0) => \gen_rd_b.doutb_reg0\(3 downto 2),
DOC(1 downto 0) => \gen_rd_b.doutb_reg0\(5 downto 4),
DOD(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5_DOD_UNCONNECTED\(1 downto 0),
WCLK => clka,
WE => wea(0)
);
\gen_wr_a.gen_word_narrow.mem_reg_0_31_12_17\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4 downto 0) => addrb(4 downto 0),
ADDRB(4 downto 0) => addrb(4 downto 0),
ADDRC(4 downto 0) => addrb(4 downto 0),
ADDRD(4 downto 0) => addra(4 downto 0),
DIA(1 downto 0) => dina(13 downto 12),
DIB(1 downto 0) => dina(15 downto 14),
DIC(1 downto 0) => dina(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => \gen_rd_b.doutb_reg0\(13 downto 12),
DOB(1 downto 0) => \gen_rd_b.doutb_reg0\(15 downto 14),
DOC(1 downto 0) => \gen_rd_b.doutb_reg0\(17 downto 16),
DOD(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_12_17_DOD_UNCONNECTED\(1 downto 0),
WCLK => clka,
WE => wea(0)
);
\gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4 downto 0) => addrb(4 downto 0),
ADDRB(4 downto 0) => addrb(4 downto 0),
ADDRC(4 downto 0) => addrb(4 downto 0),
ADDRD(4 downto 0) => addra(4 downto 0),
DIA(1 downto 0) => dina(19 downto 18),
DIB(1 downto 0) => dina(21 downto 20),
DIC(1 downto 0) => dina(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => \gen_rd_b.doutb_reg0\(19 downto 18),
DOB(1 downto 0) => \gen_rd_b.doutb_reg0\(21 downto 20),
DOC(1 downto 0) => \gen_rd_b.doutb_reg0\(23 downto 22),
DOD(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23_DOD_UNCONNECTED\(1 downto 0),
WCLK => clka,
WE => wea(0)
);
\gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4 downto 0) => addrb(4 downto 0),
ADDRB(4 downto 0) => addrb(4 downto 0),
ADDRC(4 downto 0) => addrb(4 downto 0),
ADDRD(4 downto 0) => addra(4 downto 0),
DIA(1 downto 0) => dina(25 downto 24),
DIB(1) => '0',
DIB(0) => dina(26),
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1 downto 0) => \gen_rd_b.doutb_reg0\(25 downto 24),
DOB(1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26_DOB_UNCONNECTED\(1),
DOB(0) => \gen_rd_b.doutb_reg0\(26),
DOC(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26_DOC_UNCONNECTED\(1 downto 0),
DOD(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_24_26_DOD_UNCONNECTED\(1 downto 0),
WCLK => clka,
WE => wea(0)
);
\gen_wr_a.gen_word_narrow.mem_reg_0_31_6_11\: unisim.vcomponents.RAM32M
generic map(
INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000"
)
port map (
ADDRA(4 downto 0) => addrb(4 downto 0),
ADDRB(4 downto 0) => addrb(4 downto 0),
ADDRC(4 downto 0) => addrb(4 downto 0),
ADDRD(4 downto 0) => addra(4 downto 0),
DIA(1 downto 0) => dina(7 downto 6),
DIB(1 downto 0) => dina(9 downto 8),
DIC(1 downto 0) => dina(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1 downto 0) => \gen_rd_b.doutb_reg0\(7 downto 6),
DOB(1 downto 0) => \gen_rd_b.doutb_reg0\(9 downto 8),
DOC(1 downto 0) => \gen_rd_b.doutb_reg0\(11 downto 10),
DOD(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_6_11_DOD_UNCONNECTED\(1 downto 0),
WCLK => clka,
WE => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_cdc_single is
port (
src_in : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_cdc_single : entity is "v_axi4s_vid_out_v4_0_10_cdc_single";
end hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_cdc_single;
architecture STRUCTURE of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_cdc_single is
signal xpm_cdc_single_inst_n_0 : STD_LOGIC;
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of xpm_cdc_single_inst : label is 4;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of xpm_cdc_single_inst : label is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of xpm_cdc_single_inst : label is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of xpm_cdc_single_inst : label is 0;
attribute VERSION : integer;
attribute VERSION of xpm_cdc_single_inst : label is 0;
attribute XPM_CDC : string;
attribute XPM_CDC of xpm_cdc_single_inst : label is "SINGLE";
attribute XPM_MODULE : string;
attribute XPM_MODULE of xpm_cdc_single_inst : label is "TRUE";
begin
xpm_cdc_single_inst: entity work.hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single
port map (
dest_clk => aclk,
dest_out => xpm_cdc_single_inst_n_0,
src_clk => '0',
src_in => src_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_cdc_single__xdcDup__1\ is
port (
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_cdc_single__xdcDup__1\ : entity is "v_axi4s_vid_out_v4_0_10_cdc_single";
end \hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_cdc_single__xdcDup__1\;
architecture STRUCTURE of \hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_cdc_single__xdcDup__1\ is
signal xpm_cdc_single_inst_n_0 : STD_LOGIC;
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of xpm_cdc_single_inst : label is 4;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of xpm_cdc_single_inst : label is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of xpm_cdc_single_inst : label is 0;
attribute SRC_INPUT_REG : integer;
attribute SRC_INPUT_REG of xpm_cdc_single_inst : label is 0;
attribute VERSION : integer;
attribute VERSION of xpm_cdc_single_inst : label is 0;
attribute XPM_CDC : string;
attribute XPM_CDC of xpm_cdc_single_inst : label is "SINGLE";
attribute XPM_MODULE : string;
attribute XPM_MODULE of xpm_cdc_single_inst : label is "TRUE";
begin
xpm_cdc_single_inst: entity work.\hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_cdc_single__2\
port map (
dest_clk => aclk,
dest_out => xpm_cdc_single_inst_n_0,
src_clk => '0',
src_in => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base is
port (
sleep : in STD_LOGIC;
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 26 downto 0 );
full : out STD_LOGIC;
full_n : out STD_LOGIC;
prog_full : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
overflow : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 26 downto 0 );
empty : out STD_LOGIC;
prog_empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
underflow : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
almost_empty : out STD_LOGIC;
data_valid : out STD_LOGIC;
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC
);
attribute CDC_DEST_SYNC_FF : integer;
attribute CDC_DEST_SYNC_FF of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 2;
attribute COMMON_CLOCK : integer;
attribute COMMON_CLOCK of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 1;
attribute DOUT_RESET_VALUE : string;
attribute DOUT_RESET_VALUE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "0";
attribute ECC_MODE : integer;
attribute ECC_MODE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 0;
attribute ENABLE_ECC : integer;
attribute ENABLE_ECC of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 0;
attribute EN_ADV_FEATURE : string;
attribute EN_ADV_FEATURE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "16'b0000011100000111";
attribute EN_AE : string;
attribute EN_AE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "1'b0";
attribute EN_AF : string;
attribute EN_AF of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "1'b0";
attribute EN_DVLD : string;
attribute EN_DVLD of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "1'b0";
attribute EN_OF : string;
attribute EN_OF of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "1'b1";
attribute EN_PE : string;
attribute EN_PE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "1'b1";
attribute EN_PF : string;
attribute EN_PF of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "1'b1";
attribute EN_RDC : string;
attribute EN_RDC of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "1'b1";
attribute EN_UF : string;
attribute EN_UF of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "1'b1";
attribute EN_WACK : string;
attribute EN_WACK of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "1'b0";
attribute EN_WDC : string;
attribute EN_WDC of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "1'b1";
attribute FG_EQ_ASYM_DOUT : string;
attribute FG_EQ_ASYM_DOUT of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "1'b0";
attribute FIFO_MEMORY_TYPE : integer;
attribute FIFO_MEMORY_TYPE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 0;
attribute FIFO_MEM_TYPE : integer;
attribute FIFO_MEM_TYPE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 0;
attribute FIFO_READ_DEPTH : integer;
attribute FIFO_READ_DEPTH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 32;
attribute FIFO_READ_LATENCY : integer;
attribute FIFO_READ_LATENCY of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 0;
attribute FIFO_SIZE : integer;
attribute FIFO_SIZE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 864;
attribute FIFO_WRITE_DEPTH : integer;
attribute FIFO_WRITE_DEPTH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 32;
attribute FULL_RESET_VALUE : integer;
attribute FULL_RESET_VALUE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 1;
attribute FULL_RST_VAL : string;
attribute FULL_RST_VAL of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "1'b1";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "xpm_fifo_base";
attribute PE_THRESH_ADJ : integer;
attribute PE_THRESH_ADJ of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 8;
attribute PE_THRESH_MAX : integer;
attribute PE_THRESH_MAX of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 27;
attribute PE_THRESH_MIN : integer;
attribute PE_THRESH_MIN of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 5;
attribute PF_THRESH_ADJ : integer;
attribute PF_THRESH_ADJ of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 8;
attribute PF_THRESH_MAX : integer;
attribute PF_THRESH_MAX of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 27;
attribute PF_THRESH_MIN : integer;
attribute PF_THRESH_MIN of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 5;
attribute PROG_EMPTY_THRESH : integer;
attribute PROG_EMPTY_THRESH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 10;
attribute PROG_FULL_THRESH : integer;
attribute PROG_FULL_THRESH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 10;
attribute RD_DATA_COUNT_WIDTH : integer;
attribute RD_DATA_COUNT_WIDTH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 6;
attribute RD_DC_WIDTH_EXT : integer;
attribute RD_DC_WIDTH_EXT of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 6;
attribute RD_LATENCY : integer;
attribute RD_LATENCY of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 2;
attribute RD_MODE : integer;
attribute RD_MODE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 1;
attribute RD_PNTR_WIDTH : integer;
attribute RD_PNTR_WIDTH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 5;
attribute READ_DATA_WIDTH : integer;
attribute READ_DATA_WIDTH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 27;
attribute READ_MODE : integer;
attribute READ_MODE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 1;
attribute RELATED_CLOCKS : integer;
attribute RELATED_CLOCKS of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 0;
attribute REMOVE_WR_RD_PROT_LOGIC : integer;
attribute REMOVE_WR_RD_PROT_LOGIC of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 0;
attribute USE_ADV_FEATURES : string;
attribute USE_ADV_FEATURES of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "0707";
attribute VERSION : integer;
attribute VERSION of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 0;
attribute WIDTH_RATIO : integer;
attribute WIDTH_RATIO of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 1;
attribute WRITE_DATA_WIDTH : integer;
attribute WRITE_DATA_WIDTH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 27;
attribute WR_DATA_COUNT_WIDTH : integer;
attribute WR_DATA_COUNT_WIDTH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 6;
attribute WR_DC_WIDTH_EXT : integer;
attribute WR_DC_WIDTH_EXT of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 6;
attribute WR_DEPTH_LOG : integer;
attribute WR_DEPTH_LOG of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 5;
attribute WR_PNTR_WIDTH : integer;
attribute WR_PNTR_WIDTH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 5;
attribute WR_RD_RATIO : integer;
attribute WR_RD_RATIO of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 0;
attribute WR_WIDTH_LOG : integer;
attribute WR_WIDTH_LOG of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 5;
attribute XPM_MODULE : string;
attribute XPM_MODULE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is "TRUE";
attribute both_stages_valid : integer;
attribute both_stages_valid of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 3;
attribute invalid : integer;
attribute invalid of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 0;
attribute stage1_valid : integer;
attribute stage1_valid of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 2;
attribute stage2_valid : integer;
attribute stage2_valid of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base : entity is 1;
end hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base;
architecture STRUCTURE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base is
signal \<const0>\ : STD_LOGIC;
signal clr_full : STD_LOGIC;
signal count_value_i : STD_LOGIC_VECTOR ( 1 downto 0 );
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal diff_pntr_pe : STD_LOGIC_VECTOR ( 4 downto 0 );
signal diff_pntr_pf_q : STD_LOGIC_VECTOR ( 5 downto 1 );
signal diff_pntr_pf_q0 : STD_LOGIC_VECTOR ( 5 downto 1 );
signal \^empty\ : STD_LOGIC;
signal \^full\ : STD_LOGIC;
signal \gen_fwft.empty_fwft_i_reg0\ : STD_LOGIC;
signal \gen_fwft.ram_regout_en\ : STD_LOGIC;
signal \gen_fwft.rdpp1_inst_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[0]\ : STD_LOGIC;
signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[1]\ : STD_LOGIC;
signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[2]\ : STD_LOGIC;
signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[3]\ : STD_LOGIC;
signal \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[4]\ : STD_LOGIC;
signal \grdc.diff_wr_rd_pntr_rdc\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \grdc.rd_data_count_i0\ : STD_LOGIC;
signal leaving_empty0 : STD_LOGIC;
signal \next_fwft_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal overflow_i0 : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal \^prog_empty\ : STD_LOGIC;
signal prog_empty_i1 : STD_LOGIC;
signal \^prog_full\ : STD_LOGIC;
signal prog_full_i217_in : STD_LOGIC;
signal ram_empty_i : STD_LOGIC;
signal ram_empty_i0 : STD_LOGIC;
signal ram_rd_en_pf : STD_LOGIC;
signal ram_rd_en_pf_q : STD_LOGIC;
signal ram_wr_en_pf : STD_LOGIC;
signal ram_wr_en_pf_q : STD_LOGIC;
signal rd_pntr_ext : STD_LOGIC_VECTOR ( 4 downto 0 );
signal rdp_inst_n_11 : STD_LOGIC;
signal rdp_inst_n_12 : STD_LOGIC;
signal rdp_inst_n_13 : STD_LOGIC;
signal rdp_inst_n_14 : STD_LOGIC;
signal rdp_inst_n_15 : STD_LOGIC;
signal rdp_inst_n_16 : STD_LOGIC;
signal rdp_inst_n_6 : STD_LOGIC;
signal rdp_inst_n_9 : STD_LOGIC;
signal rdpp1_inst_n_0 : STD_LOGIC;
signal rdpp1_inst_n_1 : STD_LOGIC;
signal rdpp1_inst_n_2 : STD_LOGIC;
signal read_only : STD_LOGIC;
signal read_only_q : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal rst_d1_inst_n_4 : STD_LOGIC;
signal underflow_i0 : STD_LOGIC;
signal wr_pntr_ext : STD_LOGIC_VECTOR ( 4 downto 0 );
signal write_allow : STD_LOGIC;
signal write_only : STD_LOGIC;
signal write_only_q : STD_LOGIC;
signal wrp_inst_n_4 : STD_LOGIC;
signal wrpp1_inst_n_3 : STD_LOGIC;
signal wrpp1_inst_n_4 : STD_LOGIC;
signal wrpp1_inst_n_5 : STD_LOGIC;
signal wrpp1_inst_n_6 : STD_LOGIC;
signal wrpp1_inst_n_7 : STD_LOGIC;
signal wrpp1_inst_n_8 : STD_LOGIC;
signal wrpp1_inst_n_9 : STD_LOGIC;
signal xpm_fifo_rst_inst_n_1 : STD_LOGIC;
signal xpm_fifo_rst_inst_n_6 : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 26 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair14";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
attribute SOFT_HLUTNM of \gen_fwft.empty_fwft_i_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[4]_i_4\ : label is "soft_lutpair14";
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 27;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 27;
attribute CASCADE_HEIGHT : integer;
attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is "";
attribute MEMORY_OPTIMIZATION : string;
attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 864;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 32;
attribute P_MEMORY_OPT : string;
attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "auto";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 27;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 27;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 27;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 27;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 27;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 5;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 27;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 27;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 27;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 27;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
attribute RST_MODE_A : string;
attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
attribute RST_MODE_B : string;
attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute USE_EMBEDDED_CONSTRAINT : integer;
attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 27;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 27;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE";
attribute rsta_loop_iter : integer;
attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 28;
attribute rstb_loop_iter : integer;
attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 28;
attribute SOFT_HLUTNM of \gen_sdpram.xpm_memory_base_inst_i_3\ : label is "soft_lutpair15";
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
data_valid <= \<const0>\;
dbiterr <= \<const0>\;
empty <= \^empty\;
full <= \^full\;
full_n <= \<const0>\;
prog_empty <= \^prog_empty\;
prog_full <= \^prog_full\;
rd_rst_busy <= \<const0>\;
sbiterr <= \<const0>\;
wr_ack <= \<const0>\;
\FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A91"
)
port map (
I0 => curr_fwft_state(0),
I1 => curr_fwft_state(1),
I2 => rd_en,
I3 => ram_empty_i,
O => \next_fwft_state__0\(0)
);
\FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7C"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
O => \next_fwft_state__0\(1)
);
\FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \next_fwft_state__0\(0),
Q => curr_fwft_state(0),
R => xpm_fifo_rst_inst_n_1
);
\FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \next_fwft_state__0\(1),
Q => curr_fwft_state(1),
R => xpm_fifo_rst_inst_n_1
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_fwft.empty_fwft_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F380"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(0),
I2 => curr_fwft_state(1),
I3 => \^empty\,
O => \gen_fwft.empty_fwft_i_reg0\
);
\gen_fwft.empty_fwft_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \gen_fwft.empty_fwft_i_reg0\,
Q => \^empty\,
S => xpm_fifo_rst_inst_n_1
);
\gen_fwft.rdpp1_inst\: entity work.hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn
port map (
DI(0) => \gen_fwft.rdpp1_inst_n_0\,
Q(0) => rd_pntr_ext(0),
count_value_i(1 downto 0) => count_value_i(1 downto 0),
\count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
\count_value_i_reg[0]_1\(0) => xpm_fifo_rst_inst_n_1,
ram_empty_i => ram_empty_i,
rd_en => rd_en,
wr_clk => wr_clk
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => wrpp1_inst_n_9,
Q => \^full\,
S => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.ram_empty_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_empty_i0,
Q => ram_empty_i,
S => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe[4]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00005545"
)
port map (
I0 => ram_empty_i,
I1 => rd_en,
I2 => curr_fwft_state(1),
I3 => curr_fwft_state(0),
I4 => \^empty\,
O => p_16_in
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pe(0),
Q => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[0]\,
R => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pe(1),
Q => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[1]\,
R => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pe(2),
Q => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[2]\,
R => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pe(3),
Q => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[3]\,
R => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pe(4),
Q => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[4]\,
R => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[0]\,
I1 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[1]\,
I2 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[2]\,
I3 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[4]\,
I4 => \gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg_n_0_[3]\,
O => prog_empty_i1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.prog_empty_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => xpm_fifo_rst_inst_n_6,
Q => \^prog_empty\,
R => '0'
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.read_only_q_reg\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => read_only,
Q => read_only_q,
R => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => write_only,
Q => write_only_q,
R => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pf_q0(1),
Q => diff_pntr_pf_q(1),
R => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pf_q0(2),
Q => diff_pntr_pf_q(2),
R => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pf_q0(3),
Q => diff_pntr_pf_q(3),
R => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pf_q0(4),
Q => diff_pntr_pf_q(4),
R => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pf_q0(5),
Q => diff_pntr_pf_q(5),
R => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => diff_pntr_pf_q(1),
I1 => diff_pntr_pf_q(2),
I2 => diff_pntr_pf_q(3),
I3 => diff_pntr_pf_q(5),
I4 => diff_pntr_pf_q(4),
O => prog_full_i217_in
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.prog_full_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1_inst_n_4,
Q => \^prog_full\,
S => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_rd_en_pf_q_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => ram_rd_en_pf,
Q => ram_rd_en_pf_q,
R => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_wr_en_pf_q_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => ram_wr_en_pf,
Q => ram_wr_en_pf_q,
R => xpm_fifo_rst_inst_n_1
);
\gen_sdpram.xpm_memory_base_inst\: entity work.hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_memory_base
port map (
addra(4 downto 0) => wr_pntr_ext(4 downto 0),
addrb(4 downto 0) => rd_pntr_ext(4 downto 0),
clka => wr_clk,
clkb => '0',
dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\,
dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\,
dina(26 downto 0) => din(26 downto 0),
dinb(26 downto 0) => B"000000000000000000000000000",
douta(26 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(26 downto 0),
doutb(26 downto 0) => dout(26 downto 0),
ena => '0',
enb => ram_rd_en_pf,
injectdbiterra => '0',
injectdbiterrb => '0',
injectsbiterra => '0',
injectsbiterrb => '0',
regcea => '0',
regceb => \gen_fwft.ram_regout_en\,
rsta => '0',
rstb => xpm_fifo_rst_inst_n_1,
sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\,
sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\,
sleep => sleep,
wea(0) => ram_wr_en_pf,
web(0) => '0'
);
\gen_sdpram.xpm_memory_base_inst_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"38"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
O => \gen_fwft.ram_regout_en\
);
\gof.overflow_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => overflow_i0,
Q => overflow,
R => '0'
);
\grdc.rd_data_count_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(0),
Q => rd_data_count(0),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(1),
Q => rd_data_count(1),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(2),
Q => rd_data_count(2),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(3),
Q => rd_data_count(3),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(4),
Q => rd_data_count(4),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(5),
Q => rd_data_count(5),
R => \grdc.rd_data_count_i0\
);
\guf.underflow_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => underflow_i0,
Q => underflow,
R => '0'
);
\gwdc.wr_data_count_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(0),
Q => wr_data_count(0),
R => xpm_fifo_rst_inst_n_1
);
\gwdc.wr_data_count_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(1),
Q => wr_data_count(1),
R => xpm_fifo_rst_inst_n_1
);
\gwdc.wr_data_count_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(2),
Q => wr_data_count(2),
R => xpm_fifo_rst_inst_n_1
);
\gwdc.wr_data_count_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(3),
Q => wr_data_count(3),
R => xpm_fifo_rst_inst_n_1
);
\gwdc.wr_data_count_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(4),
Q => wr_data_count(4),
R => xpm_fifo_rst_inst_n_1
);
\gwdc.wr_data_count_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(5),
Q => wr_data_count(5),
R => xpm_fifo_rst_inst_n_1
);
rdp_inst: entity work.\hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized0\
port map (
D(0) => diff_pntr_pe(3),
Q(5) => wrp_inst_n_4,
Q(4 downto 0) => wr_pntr_ext(4 downto 0),
S(1) => rdp_inst_n_12,
S(0) => rdp_inst_n_13,
count_value_i(1 downto 0) => count_value_i(1 downto 0),
\count_value_i_reg[0]_0\ => rdp_inst_n_6,
\count_value_i_reg[0]_1\(0) => xpm_fifo_rst_inst_n_1,
\count_value_i_reg[1]_0\(1 downto 0) => diff_pntr_pf_q0(4 downto 3),
\count_value_i_reg[1]_1\ => rdp_inst_n_9,
\count_value_i_reg[2]_0\(2) => rdp_inst_n_14,
\count_value_i_reg[2]_0\(1) => rdp_inst_n_15,
\count_value_i_reg[2]_0\(0) => rdp_inst_n_16,
\count_value_i_reg[3]_0\ => rdp_inst_n_11,
\count_value_i_reg[4]_0\(4 downto 0) => rd_pntr_ext(4 downto 0),
\count_value_i_reg[5]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[4]\ => wrpp1_inst_n_8,
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\(4) => wrpp1_inst_n_3,
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\(3) => wrpp1_inst_n_4,
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\(2) => wrpp1_inst_n_5,
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\(1) => wrpp1_inst_n_6,
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\(0) => wrpp1_inst_n_7,
p_16_in => p_16_in,
ram_empty_i => ram_empty_i,
ram_rd_en_pf => ram_rd_en_pf,
ram_wr_en_pf => ram_wr_en_pf,
rd_en => rd_en,
wr_clk => wr_clk,
write_allow => write_allow
);
rdpp1_inst: entity work.\hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized1\
port map (
Q(2 downto 0) => wr_pntr_ext(4 downto 2),
\count_value_i_reg[0]_0\(0) => xpm_fifo_rst_inst_n_1,
\count_value_i_reg[1]_0\(1) => rdpp1_inst_n_1,
\count_value_i_reg[1]_0\(0) => rdpp1_inst_n_2,
\count_value_i_reg[1]_1\(1 downto 0) => curr_fwft_state(1 downto 0),
\count_value_i_reg[3]_0\ => rdpp1_inst_n_0,
ram_rd_en_pf => ram_rd_en_pf,
rd_en => rd_en,
wr_clk => wr_clk
);
rst_d1_inst: entity work.hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_reg_bit
port map (
Q(0) => xpm_fifo_rst_inst_n_1,
clr_full => clr_full,
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg\ => \^full\,
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.write_only_q_reg_0\ => \^empty\,
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.ram_rd_en_pf_q_reg\ => rst_d1_inst_n_4,
prog_full => \^prog_full\,
prog_full_i217_in => prog_full_i217_in,
ram_rd_en_pf => ram_rd_en_pf,
ram_rd_en_pf_q => ram_rd_en_pf_q,
ram_wr_en_pf_q => ram_wr_en_pf_q,
rst => rst,
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_en => wr_en,
write_allow => write_allow,
write_only => write_only
);
wrp_inst: entity work.\hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized0_0\
port map (
D(3) => diff_pntr_pe(4),
D(2 downto 0) => diff_pntr_pe(2 downto 0),
DI(0) => \gen_fwft.rdpp1_inst_n_0\,
Q(5) => wrp_inst_n_4,
Q(4 downto 0) => wr_pntr_ext(4 downto 0),
S(1) => rdp_inst_n_12,
S(0) => rdp_inst_n_13,
count_value_i(0) => count_value_i(1),
\count_value_i_reg[0]_0\(5 downto 0) => \grdc.diff_wr_rd_pntr_rdc\(5 downto 0),
\count_value_i_reg[5]_0\(0) => xpm_fifo_rst_inst_n_1,
\gen_pntr_flags_cc.ram_empty_i_reg\ => rdpp1_inst_n_0,
\gen_pntr_flags_cc.ram_empty_i_reg_0\(1) => rdpp1_inst_n_1,
\gen_pntr_flags_cc.ram_empty_i_reg_0\(0) => rdpp1_inst_n_2,
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[0]\ => \^empty\,
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[0]_0\ => \^full\,
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]\(4 downto 0) => rd_pntr_ext(4 downto 0),
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.diff_pntr_pe_reg[4]_0\ => rdp_inst_n_6,
\grdc.rd_data_count_i_reg[3]\(2) => rdp_inst_n_14,
\grdc.rd_data_count_i_reg[3]\(1) => rdp_inst_n_15,
\grdc.rd_data_count_i_reg[3]\(0) => rdp_inst_n_16,
leaving_empty0 => leaving_empty0,
ram_empty_i => ram_empty_i,
ram_empty_i0 => ram_empty_i0,
ram_rd_en_pf => ram_rd_en_pf,
ram_wr_en_pf => ram_wr_en_pf,
read_only => read_only,
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_en => wr_en
);
wrpp1_inst: entity work.\hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_counter_updn__parameterized1_1\
port map (
D(2) => diff_pntr_pf_q0(5),
D(1 downto 0) => diff_pntr_pf_q0(2 downto 1),
Q(4) => wrpp1_inst_n_3,
Q(3) => wrpp1_inst_n_4,
Q(2) => wrpp1_inst_n_5,
Q(1) => wrpp1_inst_n_6,
Q(0) => wrpp1_inst_n_7,
clr_full => clr_full,
\count_value_i_reg[0]_0\(0) => xpm_fifo_rst_inst_n_1,
\count_value_i_reg[3]_0\ => wrpp1_inst_n_8,
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg\ => wrpp1_inst_n_9,
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\(4 downto 0) => rd_pntr_ext(4 downto 0),
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1\ => \^full\,
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]\ => rdp_inst_n_9,
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpf_cc_sym.diff_pntr_pf_q_reg[5]_0\ => rdp_inst_n_11,
leaving_empty0 => leaving_empty0,
ram_rd_en_pf => ram_rd_en_pf,
ram_wr_en_pf => ram_wr_en_pf,
wr_clk => wr_clk
);
xpm_fifo_rst_inst: entity work.hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_rst
port map (
Q(0) => xpm_fifo_rst_inst_n_1,
SR(0) => \grdc.rd_data_count_i0\,
\gen_pntr_flags_cc.wrp_eq_rdp_pf_cc.gpe_cc_sym.read_only_q_reg\ => \^empty\,
\gen_rst_cc.fifo_wr_rst_cc_reg[2]_0\ => xpm_fifo_rst_inst_n_6,
\gof.overflow_i_reg\ => \^full\,
\grdc.rd_data_count_i_reg[0]\(1 downto 0) => curr_fwft_state(1 downto 0),
overflow_i0 => overflow_i0,
prog_empty => \^prog_empty\,
prog_empty_i1 => prog_empty_i1,
ram_rd_en_pf => ram_rd_en_pf,
ram_wr_en_pf => ram_wr_en_pf,
rd_en => rd_en,
read_only => read_only,
read_only_q => read_only_q,
rst => rst,
rst_d1 => rst_d1,
underflow_i0 => underflow_i0,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy,
write_only_q => write_only_q
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync is
port (
sleep : in STD_LOGIC;
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 26 downto 0 );
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
overflow : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 26 downto 0 );
empty : out STD_LOGIC;
prog_empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
underflow : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
almost_empty : out STD_LOGIC;
data_valid : out STD_LOGIC;
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC
);
attribute DOUT_RESET_VALUE : string;
attribute DOUT_RESET_VALUE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is "0";
attribute ECC_MODE : string;
attribute ECC_MODE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is "no_ecc";
attribute EN_ADV_FEATURE_SYNC : string;
attribute EN_ADV_FEATURE_SYNC of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is "16'b0000011100000111";
attribute FIFO_MEMORY_TYPE : string;
attribute FIFO_MEMORY_TYPE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is "auto";
attribute FIFO_READ_LATENCY : integer;
attribute FIFO_READ_LATENCY of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 0;
attribute FIFO_WRITE_DEPTH : integer;
attribute FIFO_WRITE_DEPTH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 32;
attribute FULL_RESET_VALUE : integer;
attribute FULL_RESET_VALUE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is "xpm_fifo_sync";
attribute PROG_EMPTY_THRESH : integer;
attribute PROG_EMPTY_THRESH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 10;
attribute PROG_FULL_THRESH : integer;
attribute PROG_FULL_THRESH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 10;
attribute P_COMMON_CLOCK : integer;
attribute P_COMMON_CLOCK of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 1;
attribute P_ECC_MODE : integer;
attribute P_ECC_MODE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 0;
attribute P_FIFO_MEMORY_TYPE : integer;
attribute P_FIFO_MEMORY_TYPE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 0;
attribute P_READ_MODE : integer;
attribute P_READ_MODE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 1;
attribute P_WAKEUP_TIME : integer;
attribute P_WAKEUP_TIME of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 2;
attribute RD_DATA_COUNT_WIDTH : integer;
attribute RD_DATA_COUNT_WIDTH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 6;
attribute READ_DATA_WIDTH : integer;
attribute READ_DATA_WIDTH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 27;
attribute READ_MODE : string;
attribute READ_MODE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is "fwft";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 0;
attribute USE_ADV_FEATURES : string;
attribute USE_ADV_FEATURES of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is "0707";
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 0;
attribute WRITE_DATA_WIDTH : integer;
attribute WRITE_DATA_WIDTH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 27;
attribute WR_DATA_COUNT_WIDTH : integer;
attribute WR_DATA_COUNT_WIDTH of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is 6;
attribute XPM_MODULE : string;
attribute XPM_MODULE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync : entity is "TRUE";
end hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync;
architecture STRUCTURE of hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync is
signal \<const0>\ : STD_LOGIC;
signal \^rd_rst_busy\ : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_full_n_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED : STD_LOGIC;
attribute CDC_DEST_SYNC_FF : integer;
attribute CDC_DEST_SYNC_FF of xpm_fifo_base_inst : label is 2;
attribute COMMON_CLOCK : integer;
attribute COMMON_CLOCK of xpm_fifo_base_inst : label is 1;
attribute DOUT_RESET_VALUE of xpm_fifo_base_inst : label is "0";
attribute ECC_MODE_integer : integer;
attribute ECC_MODE_integer of xpm_fifo_base_inst : label is 0;
attribute ENABLE_ECC : integer;
attribute ENABLE_ECC of xpm_fifo_base_inst : label is 0;
attribute EN_ADV_FEATURE : string;
attribute EN_ADV_FEATURE of xpm_fifo_base_inst : label is "16'b0000011100000111";
attribute EN_AE : string;
attribute EN_AE of xpm_fifo_base_inst : label is "1'b0";
attribute EN_AF : string;
attribute EN_AF of xpm_fifo_base_inst : label is "1'b0";
attribute EN_DVLD : string;
attribute EN_DVLD of xpm_fifo_base_inst : label is "1'b0";
attribute EN_OF : string;
attribute EN_OF of xpm_fifo_base_inst : label is "1'b1";
attribute EN_PE : string;
attribute EN_PE of xpm_fifo_base_inst : label is "1'b1";
attribute EN_PF : string;
attribute EN_PF of xpm_fifo_base_inst : label is "1'b1";
attribute EN_RDC : string;
attribute EN_RDC of xpm_fifo_base_inst : label is "1'b1";
attribute EN_UF : string;
attribute EN_UF of xpm_fifo_base_inst : label is "1'b1";
attribute EN_WACK : string;
attribute EN_WACK of xpm_fifo_base_inst : label is "1'b0";
attribute EN_WDC : string;
attribute EN_WDC of xpm_fifo_base_inst : label is "1'b1";
attribute FG_EQ_ASYM_DOUT : string;
attribute FG_EQ_ASYM_DOUT of xpm_fifo_base_inst : label is "1'b0";
attribute FIFO_MEMORY_TYPE_integer : integer;
attribute FIFO_MEMORY_TYPE_integer of xpm_fifo_base_inst : label is 0;
attribute FIFO_MEM_TYPE : integer;
attribute FIFO_MEM_TYPE of xpm_fifo_base_inst : label is 0;
attribute FIFO_READ_DEPTH : integer;
attribute FIFO_READ_DEPTH of xpm_fifo_base_inst : label is 32;
attribute FIFO_READ_LATENCY of xpm_fifo_base_inst : label is 0;
attribute FIFO_SIZE : integer;
attribute FIFO_SIZE of xpm_fifo_base_inst : label is 864;
attribute FIFO_WRITE_DEPTH of xpm_fifo_base_inst : label is 32;
attribute FULL_RESET_VALUE of xpm_fifo_base_inst : label is 1;
attribute FULL_RST_VAL : string;
attribute FULL_RST_VAL of xpm_fifo_base_inst : label is "1'b1";
attribute PE_THRESH_ADJ : integer;
attribute PE_THRESH_ADJ of xpm_fifo_base_inst : label is 8;
attribute PE_THRESH_MAX : integer;
attribute PE_THRESH_MAX of xpm_fifo_base_inst : label is 27;
attribute PE_THRESH_MIN : integer;
attribute PE_THRESH_MIN of xpm_fifo_base_inst : label is 5;
attribute PF_THRESH_ADJ : integer;
attribute PF_THRESH_ADJ of xpm_fifo_base_inst : label is 8;
attribute PF_THRESH_MAX : integer;
attribute PF_THRESH_MAX of xpm_fifo_base_inst : label is 27;
attribute PF_THRESH_MIN : integer;
attribute PF_THRESH_MIN of xpm_fifo_base_inst : label is 5;
attribute PROG_EMPTY_THRESH of xpm_fifo_base_inst : label is 10;
attribute PROG_FULL_THRESH of xpm_fifo_base_inst : label is 10;
attribute RD_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 6;
attribute RD_DC_WIDTH_EXT : integer;
attribute RD_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 6;
attribute RD_LATENCY : integer;
attribute RD_LATENCY of xpm_fifo_base_inst : label is 2;
attribute RD_MODE : integer;
attribute RD_MODE of xpm_fifo_base_inst : label is 1;
attribute RD_PNTR_WIDTH : integer;
attribute RD_PNTR_WIDTH of xpm_fifo_base_inst : label is 5;
attribute READ_DATA_WIDTH of xpm_fifo_base_inst : label is 27;
attribute READ_MODE_integer : integer;
attribute READ_MODE_integer of xpm_fifo_base_inst : label is 1;
attribute RELATED_CLOCKS : integer;
attribute RELATED_CLOCKS of xpm_fifo_base_inst : label is 0;
attribute REMOVE_WR_RD_PROT_LOGIC : integer;
attribute REMOVE_WR_RD_PROT_LOGIC of xpm_fifo_base_inst : label is 0;
attribute SIM_ASSERT_CHK of xpm_fifo_base_inst : label is 0;
attribute USE_ADV_FEATURES of xpm_fifo_base_inst : label is "0707";
attribute VERSION : integer;
attribute VERSION of xpm_fifo_base_inst : label is 0;
attribute WAKEUP_TIME of xpm_fifo_base_inst : label is 0;
attribute WIDTH_RATIO : integer;
attribute WIDTH_RATIO of xpm_fifo_base_inst : label is 1;
attribute WRITE_DATA_WIDTH of xpm_fifo_base_inst : label is 27;
attribute WR_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 6;
attribute WR_DC_WIDTH_EXT : integer;
attribute WR_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 6;
attribute WR_DEPTH_LOG : integer;
attribute WR_DEPTH_LOG of xpm_fifo_base_inst : label is 5;
attribute WR_PNTR_WIDTH : integer;
attribute WR_PNTR_WIDTH of xpm_fifo_base_inst : label is 5;
attribute WR_RD_RATIO : integer;
attribute WR_RD_RATIO of xpm_fifo_base_inst : label is 0;
attribute WR_WIDTH_LOG : integer;
attribute WR_WIDTH_LOG of xpm_fifo_base_inst : label is 5;
attribute XPM_MODULE of xpm_fifo_base_inst : label is "TRUE";
attribute both_stages_valid : integer;
attribute both_stages_valid of xpm_fifo_base_inst : label is 3;
attribute invalid : integer;
attribute invalid of xpm_fifo_base_inst : label is 0;
attribute stage1_valid : integer;
attribute stage1_valid of xpm_fifo_base_inst : label is 2;
attribute stage2_valid : integer;
attribute stage2_valid of xpm_fifo_base_inst : label is 1;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
data_valid <= \<const0>\;
dbiterr <= \<const0>\;
rd_rst_busy <= \^rd_rst_busy\;
sbiterr <= \<const0>\;
wr_ack <= \<const0>\;
wr_rst_busy <= \^rd_rst_busy\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
xpm_fifo_base_inst: entity work.hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_base
port map (
almost_empty => NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED,
almost_full => NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED,
data_valid => NLW_xpm_fifo_base_inst_data_valid_UNCONNECTED,
dbiterr => NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED,
din(26 downto 0) => din(26 downto 0),
dout(26 downto 0) => dout(26 downto 0),
empty => empty,
full => full,
full_n => NLW_xpm_fifo_base_inst_full_n_UNCONNECTED,
injectdbiterr => '0',
injectsbiterr => '0',
overflow => overflow,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => '0',
rd_data_count(5 downto 0) => rd_data_count(5 downto 0),
rd_en => rd_en,
rd_rst_busy => NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED,
rst => rst,
sbiterr => NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED,
sleep => sleep,
underflow => underflow,
wr_ack => NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(5 downto 0) => wr_data_count(5 downto 0),
wr_en => wr_en,
wr_rst_busy => \^rd_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_fifo_sync is
port (
overflow : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 26 downto 0 );
fifo_read_level : out STD_LOGIC_VECTOR ( 5 downto 0 );
underflow : out STD_LOGIC;
fifo_pix_cnt : out STD_LOGIC;
s_axis_video_tready : out STD_LOGIC;
\FSM_sequential_state_reg[1]\ : out STD_LOGIC;
fifo_eol_re : out STD_LOGIC;
aclk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 26 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn : in STD_LOGIC;
vid_io_out_ce : in STD_LOGIC;
fifo_rd_en : in STD_LOGIC;
s_axis_video_tvalid : in STD_LOGIC;
aclken : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
fifo_eol_dly : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_fifo_sync : entity is "v_axi4s_vid_out_v4_0_10_fifo_sync";
end hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_fifo_sync;
architecture STRUCTURE of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_fifo_sync is
signal XPM_FIFO_SYNC_INST_n_2 : STD_LOGIC;
signal XPM_FIFO_SYNC_INST_n_3 : STD_LOGIC;
signal XPM_FIFO_SYNC_INST_n_4 : STD_LOGIC;
signal XPM_FIFO_SYNC_INST_n_48 : STD_LOGIC;
signal XPM_FIFO_SYNC_INST_n_5 : STD_LOGIC;
signal XPM_FIFO_SYNC_INST_n_6 : STD_LOGIC;
signal XPM_FIFO_SYNC_INST_n_7 : STD_LOGIC;
signal \^dout\ : STD_LOGIC_VECTOR ( 26 downto 0 );
signal fifo_empty : STD_LOGIC;
signal \^fifo_read_level\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal full_i : STD_LOGIC;
signal vid_reset : STD_LOGIC;
signal wr_en_i : STD_LOGIC;
signal wr_rst_busy_i : STD_LOGIC;
signal NLW_XPM_FIFO_SYNC_INST_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_XPM_FIFO_SYNC_INST_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_XPM_FIFO_SYNC_INST_data_valid_UNCONNECTED : STD_LOGIC;
signal NLW_XPM_FIFO_SYNC_INST_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_XPM_FIFO_SYNC_INST_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_XPM_FIFO_SYNC_INST_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_XPM_FIFO_SYNC_INST_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_XPM_FIFO_SYNC_INST_wr_ack_UNCONNECTED : STD_LOGIC;
attribute DOUT_RESET_VALUE : string;
attribute DOUT_RESET_VALUE of XPM_FIFO_SYNC_INST : label is "0";
attribute ECC_MODE : string;
attribute ECC_MODE of XPM_FIFO_SYNC_INST : label is "no_ecc";
attribute EN_ADV_FEATURE_SYNC : string;
attribute EN_ADV_FEATURE_SYNC of XPM_FIFO_SYNC_INST : label is "16'b0000011100000111";
attribute FIFO_MEMORY_TYPE : string;
attribute FIFO_MEMORY_TYPE of XPM_FIFO_SYNC_INST : label is "auto";
attribute FIFO_READ_LATENCY : integer;
attribute FIFO_READ_LATENCY of XPM_FIFO_SYNC_INST : label is 0;
attribute FIFO_WRITE_DEPTH : integer;
attribute FIFO_WRITE_DEPTH of XPM_FIFO_SYNC_INST : label is 32;
attribute FULL_RESET_VALUE : integer;
attribute FULL_RESET_VALUE of XPM_FIFO_SYNC_INST : label is 1;
attribute PROG_EMPTY_THRESH : integer;
attribute PROG_EMPTY_THRESH of XPM_FIFO_SYNC_INST : label is 10;
attribute PROG_FULL_THRESH : integer;
attribute PROG_FULL_THRESH of XPM_FIFO_SYNC_INST : label is 10;
attribute P_COMMON_CLOCK : integer;
attribute P_COMMON_CLOCK of XPM_FIFO_SYNC_INST : label is 1;
attribute P_ECC_MODE : integer;
attribute P_ECC_MODE of XPM_FIFO_SYNC_INST : label is 0;
attribute P_FIFO_MEMORY_TYPE : integer;
attribute P_FIFO_MEMORY_TYPE of XPM_FIFO_SYNC_INST : label is 0;
attribute P_READ_MODE : integer;
attribute P_READ_MODE of XPM_FIFO_SYNC_INST : label is 1;
attribute P_WAKEUP_TIME : integer;
attribute P_WAKEUP_TIME of XPM_FIFO_SYNC_INST : label is 2;
attribute RD_DATA_COUNT_WIDTH : integer;
attribute RD_DATA_COUNT_WIDTH of XPM_FIFO_SYNC_INST : label is 6;
attribute READ_DATA_WIDTH : integer;
attribute READ_DATA_WIDTH of XPM_FIFO_SYNC_INST : label is 27;
attribute READ_MODE : string;
attribute READ_MODE of XPM_FIFO_SYNC_INST : label is "fwft";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of XPM_FIFO_SYNC_INST : label is 0;
attribute USE_ADV_FEATURES : string;
attribute USE_ADV_FEATURES of XPM_FIFO_SYNC_INST : label is "0707";
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of XPM_FIFO_SYNC_INST : label is 0;
attribute WRITE_DATA_WIDTH : integer;
attribute WRITE_DATA_WIDTH of XPM_FIFO_SYNC_INST : label is 27;
attribute WR_DATA_COUNT_WIDTH : integer;
attribute WR_DATA_COUNT_WIDTH of XPM_FIFO_SYNC_INST : label is 6;
attribute XPM_MODULE : string;
attribute XPM_MODULE of XPM_FIFO_SYNC_INST : label is "TRUE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of XPM_FIFO_SYNC_INST_i_2 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of s_axis_video_tready_INST_0 : label is "soft_lutpair16";
begin
dout(26 downto 0) <= \^dout\(26 downto 0);
fifo_read_level(5 downto 0) <= \^fifo_read_level\(5 downto 0);
\FSM_sequential_state[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEEE55555555"
)
port map (
I0 => Q(0),
I1 => \^fifo_read_level\(5),
I2 => \^fifo_read_level\(3),
I3 => \^fifo_read_level\(2),
I4 => \^fifo_read_level\(4),
I5 => Q(1),
O => \FSM_sequential_state_reg[1]\
);
XPM_FIFO_SYNC_INST: entity work.hdmi_to_vga_v_axi4s_vid_out_0_0_xpm_fifo_sync
port map (
almost_empty => NLW_XPM_FIFO_SYNC_INST_almost_empty_UNCONNECTED,
almost_full => NLW_XPM_FIFO_SYNC_INST_almost_full_UNCONNECTED,
data_valid => NLW_XPM_FIFO_SYNC_INST_data_valid_UNCONNECTED,
dbiterr => NLW_XPM_FIFO_SYNC_INST_dbiterr_UNCONNECTED,
din(26 downto 0) => din(26 downto 0),
dout(26 downto 0) => \^dout\(26 downto 0),
empty => fifo_empty,
full => full_i,
injectdbiterr => '0',
injectsbiterr => '0',
overflow => overflow,
prog_empty => NLW_XPM_FIFO_SYNC_INST_prog_empty_UNCONNECTED,
prog_full => NLW_XPM_FIFO_SYNC_INST_prog_full_UNCONNECTED,
rd_data_count(5 downto 0) => \^fifo_read_level\(5 downto 0),
rd_en => E(0),
rd_rst_busy => XPM_FIFO_SYNC_INST_n_48,
rst => vid_reset,
sbiterr => NLW_XPM_FIFO_SYNC_INST_sbiterr_UNCONNECTED,
sleep => '0',
underflow => underflow,
wr_ack => NLW_XPM_FIFO_SYNC_INST_wr_ack_UNCONNECTED,
wr_clk => aclk,
wr_data_count(5) => XPM_FIFO_SYNC_INST_n_2,
wr_data_count(4) => XPM_FIFO_SYNC_INST_n_3,
wr_data_count(3) => XPM_FIFO_SYNC_INST_n_4,
wr_data_count(2) => XPM_FIFO_SYNC_INST_n_5,
wr_data_count(1) => XPM_FIFO_SYNC_INST_n_6,
wr_data_count(0) => XPM_FIFO_SYNC_INST_n_7,
wr_en => wr_en_i,
wr_rst_busy => wr_rst_busy_i
);
XPM_FIFO_SYNC_INST_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => vid_reset
);
XPM_FIFO_SYNC_INST_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => s_axis_video_tvalid,
I1 => wr_rst_busy_i,
I2 => aresetn,
I3 => full_i,
I4 => aclken,
O => wr_en_i
);
fifo_eol_re_dly_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^dout\(24),
I1 => fifo_eol_dly,
O => fifo_eol_re
);
\fifo_pix_cnt[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => vid_io_out_ce,
I1 => fifo_empty,
I2 => fifo_rd_en,
O => fifo_pix_cnt
);
s_axis_video_tready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => wr_rst_busy_i,
I1 => aresetn,
I2 => full_i,
O => s_axis_video_tready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_coupler is
port (
overflow : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 26 downto 0 );
fifo_read_level : out STD_LOGIC_VECTOR ( 5 downto 0 );
underflow : out STD_LOGIC;
fifo_pix_cnt : out STD_LOGIC;
s_axis_video_tready : out STD_LOGIC;
\FSM_sequential_state_reg[1]\ : out STD_LOGIC;
fifo_eol_re : out STD_LOGIC;
aclk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 26 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn : in STD_LOGIC;
vid_io_out_ce : in STD_LOGIC;
fifo_rd_en : in STD_LOGIC;
s_axis_video_tvalid : in STD_LOGIC;
aclken : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
fifo_eol_dly : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_coupler : entity is "v_axi4s_vid_out_v4_0_10_coupler";
end hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_coupler;
architecture STRUCTURE of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_coupler is
begin
\generate_sync_fifo.FIFO_INST\: entity work.hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_fifo_sync
port map (
E(0) => E(0),
\FSM_sequential_state_reg[1]\ => \FSM_sequential_state_reg[1]\,
Q(1 downto 0) => Q(1 downto 0),
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
din(26 downto 0) => din(26 downto 0),
dout(26 downto 0) => dout(26 downto 0),
fifo_eol_dly => fifo_eol_dly,
fifo_eol_re => fifo_eol_re,
fifo_pix_cnt => fifo_pix_cnt,
fifo_rd_en => fifo_rd_en,
fifo_read_level(5 downto 0) => fifo_read_level(5 downto 0),
overflow => overflow,
s_axis_video_tready => s_axis_video_tready,
s_axis_video_tvalid => s_axis_video_tvalid,
underflow => underflow,
vid_io_out_ce => vid_io_out_ce
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_video_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axis_video_tvalid : in STD_LOGIC;
s_axis_video_tready : out STD_LOGIC;
s_axis_video_tuser : in STD_LOGIC;
s_axis_video_tlast : in STD_LOGIC;
fid : in STD_LOGIC;
vid_io_out_clk : in STD_LOGIC;
vid_io_out_ce : in STD_LOGIC;
vid_io_out_reset : in STD_LOGIC;
vid_active_video : out STD_LOGIC;
vid_vsync : out STD_LOGIC;
vid_hsync : out STD_LOGIC;
vid_vblank : out STD_LOGIC;
vid_hblank : out STD_LOGIC;
vid_field_id : out STD_LOGIC;
vid_data : out STD_LOGIC_VECTOR ( 23 downto 0 );
vtg_vsync : in STD_LOGIC;
vtg_hsync : in STD_LOGIC;
vtg_vblank : in STD_LOGIC;
vtg_hblank : in STD_LOGIC;
vtg_active_video : in STD_LOGIC;
vtg_field_id : in STD_LOGIC;
vtg_ce : out STD_LOGIC;
locked : out STD_LOGIC;
overflow : out STD_LOGIC;
underflow : out STD_LOGIC;
fifo_read_level : out STD_LOGIC_VECTOR ( 5 downto 0 );
status : out STD_LOGIC_VECTOR ( 31 downto 0 );
repeat_en : in STD_LOGIC;
remap_420_en : in STD_LOGIC
);
attribute C_ADDR_WIDTH : integer;
attribute C_ADDR_WIDTH of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is 5;
attribute C_ADDR_WIDTH_PIXEL_REMAP_420 : integer;
attribute C_ADDR_WIDTH_PIXEL_REMAP_420 of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is 10;
attribute C_COMPONENTS_PER_PIXEL : integer;
attribute C_COMPONENTS_PER_PIXEL of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is 3;
attribute C_FAMILY : string;
attribute C_FAMILY of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is "zynq";
attribute C_HAS_ASYNC_CLK : integer;
attribute C_HAS_ASYNC_CLK of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is 0;
attribute C_HYSTERESIS_LEVEL : integer;
attribute C_HYSTERESIS_LEVEL of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is 12;
attribute C_INCLUDE_PIXEL_REMAP_420 : integer;
attribute C_INCLUDE_PIXEL_REMAP_420 of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is 0;
attribute C_INCLUDE_PIXEL_REPEAT : integer;
attribute C_INCLUDE_PIXEL_REPEAT of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is 0;
attribute C_NATIVE_COMPONENT_WIDTH : integer;
attribute C_NATIVE_COMPONENT_WIDTH of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is 8;
attribute C_NATIVE_DATA_WIDTH : integer;
attribute C_NATIVE_DATA_WIDTH of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is 24;
attribute C_PIXELS_PER_CLOCK : integer;
attribute C_PIXELS_PER_CLOCK of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is 1;
attribute C_SYNC_LOCK_THRESHOLD : integer;
attribute C_SYNC_LOCK_THRESHOLD of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is 4;
attribute C_S_AXIS_COMPONENT_WIDTH : integer;
attribute C_S_AXIS_COMPONENT_WIDTH of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is 8;
attribute C_S_AXIS_TDATA_WIDTH : integer;
attribute C_S_AXIS_TDATA_WIDTH of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is 24;
attribute C_VTG_MASTER_SLAVE : integer;
attribute C_VTG_MASTER_SLAVE of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is 1;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 : entity is "v_axi4s_vid_out_v4_0_10";
end hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10;
architecture STRUCTURE of hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10 is
signal \<const0>\ : STD_LOGIC;
signal COUPLER_INST_n_37 : STD_LOGIC;
signal fifo_data : STD_LOGIC_VECTOR ( 23 downto 0 );
signal fifo_eol : STD_LOGIC;
signal fifo_eol_dly : STD_LOGIC;
signal fifo_eol_re : STD_LOGIC;
signal fifo_fid : STD_LOGIC;
signal fifo_pix_cnt : STD_LOGIC;
signal fifo_rd_en : STD_LOGIC;
signal fifo_sof : STD_LOGIC;
signal fivid_reset_full_frame : STD_LOGIC;
signal in_data_mux : STD_LOGIC;
signal in_de_mux0 : STD_LOGIC;
signal \^locked\ : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \^status\ : STD_LOGIC_VECTOR ( 20 downto 0 );
signal \^vid_io_out_ce\ : STD_LOGIC;
begin
\^vid_io_out_ce\ <= vid_io_out_ce;
locked <= \^locked\;
status(31) <= \<const0>\;
status(30) <= \<const0>\;
status(29) <= \<const0>\;
status(28) <= \<const0>\;
status(27) <= \<const0>\;
status(26) <= \<const0>\;
status(25) <= \<const0>\;
status(24) <= \<const0>\;
status(23) <= \<const0>\;
status(22) <= \<const0>\;
status(21) <= \<const0>\;
status(20 downto 16) <= \^status\(20 downto 16);
status(15) <= \<const0>\;
status(14 downto 0) <= \^status\(14 downto 0);
vtg_ce <= \^vid_io_out_ce\;
CDC_SINGLE_LOCKED_INST: entity work.hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_cdc_single
port map (
aclk => aclk,
src_in => \^locked\
);
CDC_SINGLE_REMAP_UNDERFLOW_INST: entity work.\hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_cdc_single__xdcDup__1\
port map (
aclk => aclk
);
COUPLER_INST: entity work.hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_coupler
port map (
E(0) => in_data_mux,
\FSM_sequential_state_reg[1]\ => COUPLER_INST_n_37,
Q(1 downto 0) => state(2 downto 1),
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
din(26) => fid,
din(25) => s_axis_video_tuser,
din(24) => s_axis_video_tlast,
din(23 downto 0) => s_axis_video_tdata(23 downto 0),
dout(26) => fifo_fid,
dout(25) => fifo_sof,
dout(24) => fifo_eol,
dout(23 downto 0) => fifo_data(23 downto 0),
fifo_eol_dly => fifo_eol_dly,
fifo_eol_re => fifo_eol_re,
fifo_pix_cnt => fifo_pix_cnt,
fifo_rd_en => fifo_rd_en,
fifo_read_level(5 downto 0) => fifo_read_level(5 downto 0),
overflow => overflow,
s_axis_video_tready => s_axis_video_tready,
s_axis_video_tvalid => s_axis_video_tvalid,
underflow => underflow,
vid_io_out_ce => \^vid_io_out_ce\
);
FORMATTER_INST: entity work.hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_formatter
port map (
D(23 downto 0) => fifo_data(23 downto 0),
E(0) => in_data_mux,
SR(0) => in_de_mux0,
aclk => aclk,
aresetn => aresetn,
fivid_reset_full_frame => fivid_reset_full_frame,
src_in => \^locked\,
vid_active_video => vid_active_video,
vid_data(23 downto 0) => vid_data(23 downto 0),
vid_field_id => vid_field_id,
vid_hblank => vid_hblank,
vid_hsync => vid_hsync,
vid_io_out_ce => \^vid_io_out_ce\,
vid_vblank => vid_vblank,
vid_vsync => vid_vsync,
vtg_active_video => vtg_active_video,
vtg_field_id => vtg_field_id,
vtg_hblank => vtg_hblank,
vtg_hsync => vtg_hsync,
vtg_vblank => vtg_vblank,
vtg_vsync => vtg_vsync
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
SYNC_INST: entity work.hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10_sync
port map (
E(0) => in_data_mux,
\FSM_sequential_state_reg[0]_0\ => COUPLER_INST_n_37,
Q(1 downto 0) => state(2 downto 1),
SR(0) => in_de_mux0,
aclk => aclk,
aresetn => aresetn,
dout(2) => fifo_fid,
dout(1) => fifo_sof,
dout(0) => fifo_eol,
fifo_eol_dly => fifo_eol_dly,
fifo_eol_re => fifo_eol_re,
fifo_pix_cnt => fifo_pix_cnt,
fifo_rd_en => fifo_rd_en,
fivid_reset_full_frame => fivid_reset_full_frame,
src_in => \^locked\,
status(19 downto 15) => \^status\(20 downto 16),
status(14 downto 0) => \^status\(14 downto 0),
vid_io_out_ce => \^vid_io_out_ce\,
vtg_active_video => vtg_active_video,
vtg_field_id => vtg_field_id,
vtg_vsync => vtg_vsync
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_to_vga_v_axi4s_vid_out_0_0 is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_video_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axis_video_tvalid : in STD_LOGIC;
s_axis_video_tready : out STD_LOGIC;
s_axis_video_tuser : in STD_LOGIC;
s_axis_video_tlast : in STD_LOGIC;
fid : in STD_LOGIC;
vid_io_out_ce : in STD_LOGIC;
vid_active_video : out STD_LOGIC;
vid_vsync : out STD_LOGIC;
vid_hsync : out STD_LOGIC;
vid_vblank : out STD_LOGIC;
vid_hblank : out STD_LOGIC;
vid_field_id : out STD_LOGIC;
vid_data : out STD_LOGIC_VECTOR ( 23 downto 0 );
vtg_vsync : in STD_LOGIC;
vtg_hsync : in STD_LOGIC;
vtg_vblank : in STD_LOGIC;
vtg_hblank : in STD_LOGIC;
vtg_active_video : in STD_LOGIC;
vtg_field_id : in STD_LOGIC;
vtg_ce : out STD_LOGIC;
locked : out STD_LOGIC;
overflow : out STD_LOGIC;
underflow : out STD_LOGIC;
fifo_read_level : out STD_LOGIC_VECTOR ( 5 downto 0 );
status : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of hdmi_to_vga_v_axi4s_vid_out_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of hdmi_to_vga_v_axi4s_vid_out_0_0 : entity is "hdmi_to_vga_v_axi4s_vid_out_0_0,v_axi4s_vid_out_v4_0_10,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of hdmi_to_vga_v_axi4s_vid_out_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of hdmi_to_vga_v_axi4s_vid_out_0_0 : entity is "v_axi4s_vid_out_v4_0_10,Vivado 2019.1";
end hdmi_to_vga_v_axi4s_vid_out_0_0;
architecture STRUCTURE of hdmi_to_vga_v_axi4s_vid_out_0_0 is
attribute C_ADDR_WIDTH : integer;
attribute C_ADDR_WIDTH of inst : label is 5;
attribute C_ADDR_WIDTH_PIXEL_REMAP_420 : integer;
attribute C_ADDR_WIDTH_PIXEL_REMAP_420 of inst : label is 10;
attribute C_COMPONENTS_PER_PIXEL : integer;
attribute C_COMPONENTS_PER_PIXEL of inst : label is 3;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_HAS_ASYNC_CLK : integer;
attribute C_HAS_ASYNC_CLK of inst : label is 0;
attribute C_HYSTERESIS_LEVEL : integer;
attribute C_HYSTERESIS_LEVEL of inst : label is 12;
attribute C_INCLUDE_PIXEL_REMAP_420 : integer;
attribute C_INCLUDE_PIXEL_REMAP_420 of inst : label is 0;
attribute C_INCLUDE_PIXEL_REPEAT : integer;
attribute C_INCLUDE_PIXEL_REPEAT of inst : label is 0;
attribute C_NATIVE_COMPONENT_WIDTH : integer;
attribute C_NATIVE_COMPONENT_WIDTH of inst : label is 8;
attribute C_NATIVE_DATA_WIDTH : integer;
attribute C_NATIVE_DATA_WIDTH of inst : label is 24;
attribute C_PIXELS_PER_CLOCK : integer;
attribute C_PIXELS_PER_CLOCK of inst : label is 1;
attribute C_SYNC_LOCK_THRESHOLD : integer;
attribute C_SYNC_LOCK_THRESHOLD of inst : label is 4;
attribute C_S_AXIS_COMPONENT_WIDTH : integer;
attribute C_S_AXIS_COMPONENT_WIDTH of inst : label is 8;
attribute C_S_AXIS_TDATA_WIDTH : integer;
attribute C_S_AXIS_TDATA_WIDTH of inst : label is 24;
attribute C_VTG_MASTER_SLAVE : integer;
attribute C_VTG_MASTER_SLAVE of inst : label is 1;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 aclk_intf CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF video_in, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN hdmi_to_vga_axi_dynclk_0_0_PXL_CLK_O, INSERT_VIP 0";
attribute X_INTERFACE_INFO of aclken : signal is "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
attribute X_INTERFACE_PARAMETER of aclken : signal is "XIL_INTERFACENAME aclken_intf, POLARITY ACTIVE_HIGH";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 aresetn_intf RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME aresetn_intf, POLARITY ACTIVE_LOW, INSERT_VIP 0";
attribute X_INTERFACE_INFO of s_axis_video_tlast : signal is "xilinx.com:interface:axis:1.0 video_in TLAST";
attribute X_INTERFACE_PARAMETER of s_axis_video_tlast : signal is "XIL_INTERFACENAME video_in, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN hdmi_to_vga_axi_dynclk_0_0_PXL_CLK_O, LAYERED_METADATA undef, INSERT_VIP 0";
attribute X_INTERFACE_INFO of s_axis_video_tready : signal is "xilinx.com:interface:axis:1.0 video_in TREADY";
attribute X_INTERFACE_INFO of s_axis_video_tuser : signal is "xilinx.com:interface:axis:1.0 video_in TUSER";
attribute X_INTERFACE_INFO of s_axis_video_tvalid : signal is "xilinx.com:interface:axis:1.0 video_in TVALID";
attribute X_INTERFACE_INFO of vid_active_video : signal is "xilinx.com:interface:vid_io:1.0 vid_io_out ACTIVE_VIDEO";
attribute X_INTERFACE_INFO of vid_field_id : signal is "xilinx.com:interface:vid_io:1.0 vid_io_out FIELD";
attribute X_INTERFACE_INFO of vid_hblank : signal is "xilinx.com:interface:vid_io:1.0 vid_io_out HBLANK";
attribute X_INTERFACE_INFO of vid_hsync : signal is "xilinx.com:interface:vid_io:1.0 vid_io_out HSYNC";
attribute X_INTERFACE_INFO of vid_io_out_ce : signal is "xilinx.com:signal:clockenable:1.0 vid_io_out_ce_intf CE";
attribute X_INTERFACE_PARAMETER of vid_io_out_ce : signal is "XIL_INTERFACENAME vid_io_out_ce_intf, POLARITY ACTIVE_HIGH";
attribute X_INTERFACE_INFO of vid_vblank : signal is "xilinx.com:interface:vid_io:1.0 vid_io_out VBLANK";
attribute X_INTERFACE_INFO of vid_vsync : signal is "xilinx.com:interface:vid_io:1.0 vid_io_out VSYNC";
attribute X_INTERFACE_INFO of vtg_active_video : signal is "xilinx.com:interface:video_timing:2.0 vtiming_in ACTIVE_VIDEO";
attribute X_INTERFACE_INFO of vtg_field_id : signal is "xilinx.com:interface:video_timing:2.0 vtiming_in FIELD";
attribute X_INTERFACE_INFO of vtg_hblank : signal is "xilinx.com:interface:video_timing:2.0 vtiming_in HBLANK";
attribute X_INTERFACE_INFO of vtg_hsync : signal is "xilinx.com:interface:video_timing:2.0 vtiming_in HSYNC";
attribute X_INTERFACE_INFO of vtg_vblank : signal is "xilinx.com:interface:video_timing:2.0 vtiming_in VBLANK";
attribute X_INTERFACE_INFO of vtg_vsync : signal is "xilinx.com:interface:video_timing:2.0 vtiming_in VSYNC";
attribute X_INTERFACE_INFO of s_axis_video_tdata : signal is "xilinx.com:interface:axis:1.0 video_in TDATA";
attribute X_INTERFACE_INFO of vid_data : signal is "xilinx.com:interface:vid_io:1.0 vid_io_out DATA";
begin
inst: entity work.hdmi_to_vga_v_axi4s_vid_out_0_0_v_axi4s_vid_out_v4_0_10
port map (
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
fid => fid,
fifo_read_level(5 downto 0) => fifo_read_level(5 downto 0),
locked => locked,
overflow => overflow,
remap_420_en => '0',
repeat_en => '0',
s_axis_video_tdata(23 downto 0) => s_axis_video_tdata(23 downto 0),
s_axis_video_tlast => s_axis_video_tlast,
s_axis_video_tready => s_axis_video_tready,
s_axis_video_tuser => s_axis_video_tuser,
s_axis_video_tvalid => s_axis_video_tvalid,
status(31 downto 0) => status(31 downto 0),
underflow => underflow,
vid_active_video => vid_active_video,
vid_data(23 downto 0) => vid_data(23 downto 0),
vid_field_id => vid_field_id,
vid_hblank => vid_hblank,
vid_hsync => vid_hsync,
vid_io_out_ce => vid_io_out_ce,
vid_io_out_clk => '0',
vid_io_out_reset => '0',
vid_vblank => vid_vblank,
vid_vsync => vid_vsync,
vtg_active_video => vtg_active_video,
vtg_ce => vtg_ce,
vtg_field_id => vtg_field_id,
vtg_hblank => vtg_hblank,
vtg_hsync => vtg_hsync,
vtg_vblank => vtg_vblank,
vtg_vsync => vtg_vsync
);
end STRUCTURE;
|
-- This test suite verifies the check_stable checker.
--
-- This Source Code Form is subject to the terms of the Mozilla Public
-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
-- You can obtain one at http://mozilla.org/MPL/2.0/.
--
-- Copyright (c) 2014-2018, <NAME> <EMAIL>
-- vunit: run_all_in_same_sim
library ieee;
use ieee.std_logic_1164.all;
library vunit_lib;
use vunit_lib.run_types_pkg.all;
use vunit_lib.run_pkg.all;
use vunit_lib.runner_pkg.all;
use vunit_lib.log_levels_pkg.all;
use vunit_lib.logger_pkg.all;
use vunit_lib.checker_pkg.all;
use vunit_lib.check_pkg.all;
use work.test_support.all;
entity tb_check_stable is
generic (
runner_cfg : string);
end entity tb_check_stable;
architecture test_fixture of tb_check_stable is
signal clk : std_logic := '0';
signal check_stable_in_1, check_stable_in_2, check_stable_in_3,
check_stable_in_8, check_stable_in_10 : std_logic_vector(1 to 5) := "00000";
alias check_stable_start_event_1 : std_logic is check_stable_in_1(1);
alias check_stable_end_event_1 : std_logic is check_stable_in_1(2);
alias check_stable_expr_1 : std_logic_vector(2 downto 0) is check_stable_in_1(3 to 5);
alias check_stable_start_event_2 : std_logic is check_stable_in_2(1);
alias check_stable_end_event_2 : std_logic is check_stable_in_2(2);
alias check_stable_expr_2 : std_logic_vector(2 downto 0) is check_stable_in_2(3 to 5);
alias check_stable_start_event_3 : std_logic is check_stable_in_3(1);
alias check_stable_end_event_3 : std_logic is check_stable_in_3(2);
alias check_stable_expr_3 : std_logic_vector(2 downto 0) is check_stable_in_3(3 to 5);
alias check_stable_start_event_8 : std_logic is check_stable_in_8(1);
alias check_stable_end_event_8 : std_logic is check_stable_in_8(2);
alias check_stable_expr_8 : std_logic_vector(2 downto 0) is check_stable_in_8(3 to 5);
alias check_stable_start_event_10 : std_logic is check_stable_in_10(1);
alias check_stable_end_event_10 : std_logic is check_stable_in_10(2);
alias check_stable_expr_10 : std_logic_vector(2 downto 0) is check_stable_in_10(3 to 5);
signal check_stable_start_event_4 : std_logic := '0';
signal check_stable_end_event_4 : std_logic := '0';
signal check_stable_expr_4 : std_logic_vector(7 to 9) := "000";
signal check_stable_in_5, check_stable_in_6, check_stable_in_7, check_stable_in_9,
check_stable_in_11 : std_logic_vector(1 to 3) := "000";
alias check_stable_start_event_5 : std_logic is check_stable_in_5(1);
alias check_stable_end_event_5 : std_logic is check_stable_in_5(2);
alias check_stable_expr_5 : std_logic is check_stable_in_5(3);
alias check_stable_start_event_6 : std_logic is check_stable_in_6(1);
alias check_stable_end_event_6 : std_logic is check_stable_in_6(2);
alias check_stable_expr_6 : std_logic is check_stable_in_6(3);
alias check_stable_start_event_7 : std_logic is check_stable_in_7(1);
alias check_stable_end_event_7 : std_logic is check_stable_in_7(2);
alias check_stable_expr_7 : std_logic is check_stable_in_7(3);
alias check_stable_start_event_9 : std_logic is check_stable_in_9(1);
alias check_stable_end_event_9 : std_logic is check_stable_in_9(2);
alias check_stable_expr_9 : std_logic is check_stable_in_9(3);
alias check_stable_start_event_11 : std_logic is check_stable_in_11(1);
alias check_stable_end_event_11 : std_logic is check_stable_in_11(2);
alias check_stable_expr_11 : std_logic is check_stable_in_11(3);
signal check_stable_en_1, check_stable_en_2, check_stable_en_3, check_stable_en_4 : std_logic := '1';
signal check_stable_en_5, check_stable_en_6, check_stable_en_7, check_stable_en_8 : std_logic := '1';
signal check_stable_en_9, check_stable_en_10, check_stable_en_11 : std_logic := '1';
signal en, start_event, end_event, expr : std_logic := '1';
constant my_checker2 : checker_t := new_checker("my_checker2");
constant my_checker3 : checker_t := new_checker("my_checker3", default_log_level => info);
constant my_checker6 : checker_t := new_checker("my_checker6");
constant my_checker7 : checker_t := new_checker("my_checker7", default_log_level => info);
constant my_checker10 : checker_t := new_checker("my_checker10");
constant my_checker11 : checker_t := new_checker("my_checker11");
begin
clock : process is
begin
while get_phase(runner_state) < test_runner_exit loop
clk <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
wait;
end process clock;
check_stable_1 : check_stable(clk,
check_stable_en_1,
check_stable_start_event_1,
check_stable_end_event_1,
check_stable_expr_1);
check_stable_2 : check_stable(my_checker2,
clk,
check_stable_en_2,
check_stable_start_event_2,
check_stable_end_event_2,
check_stable_expr_2,
active_clock_edge => falling_edge);
check_stable_3 : check_stable(my_checker3,
clk,
check_stable_en_3,
check_stable_start_event_3,
check_stable_end_event_3,
check_stable_expr_3);
check_stable_4 : check_stable(clk,
check_stable_en_4,
check_stable_start_event_4,
check_stable_end_event_4,
check_stable_expr_4);
check_stable_5 : check_stable(clk,
check_stable_en_5,
check_stable_start_event_5,
check_stable_end_event_5,
check_stable_expr_5);
check_stable_6 : check_stable(my_checker6,
clk,
check_stable_en_6,
check_stable_start_event_6,
check_stable_end_event_6,
check_stable_expr_6,
active_clock_edge => falling_edge);
check_stable_7 : check_stable(my_checker7,
clk,
check_stable_en_7,
check_stable_start_event_7,
check_stable_end_event_7,
check_stable_expr_7);
check_stable_8 : check_stable(clk,
check_stable_en_8,
check_stable_start_event_8,
check_stable_end_event_8,
check_stable_expr_8,
"Checking stability",
allow_restart => true);
check_stable_9 : check_stable(clk,
check_stable_en_9,
check_stable_start_event_9,
check_stable_end_event_9,
check_stable_expr_9,
result("for my data"),
allow_restart => true);
check_stable_10 : check_stable(my_checker10,
clk,
check_stable_en_10,
check_stable_start_event_10,
check_stable_end_event_10,
check_stable_expr_10,
allow_restart => true);
check_stable_11 : check_stable(my_checker11,
clk,
check_stable_en_11,
check_stable_start_event_11,
check_stable_end_event_11,
check_stable_expr_11,
allow_restart => true);
check_stable_runner : process
variable stat : checker_stat_t;
constant default_level : log_level_t := error;
procedure test_concurrent_std_logic_vector_check (
signal clk : in std_logic;
signal check_input : out std_logic_vector(1 to 5);
checker : checker_t;
constant level : in log_level_t := error;
constant active_rising_clock_edge : in boolean := true) is
constant logger : logger_t := get_logger(checker);
begin
if running_test_case = "Test concurrent checker should pass stable window" then
get_checker_stat(checker, stat);
apply_sequence("00.101;10.101;00.101;01.101;00.101", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
verify_passed_checks(checker, stat, 1);
elsif running_test_case = "Test concurrent checker should pass window with varying drive strength" then
get_checker_stat(checker, stat);
apply_sequence("00.101;10.101;00.1LH;01.101;00.101", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
verify_passed_checks(checker, stat, 1);
elsif running_test_case = "Test concurrent checker should handle weak start and end events" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.101;HL.101;LL.111;LH.111", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got 111 (7) at 2nd active and enabled clock edge. Expected 101 (5).",
level);
apply_sequence("LH.111;00.111", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got 111 (7) at 3rd active and enabled clock edge. Expected 101 (5).",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 2);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should fail unstable window" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.101;10.101;00.111;00.111", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got 111 (7) at 2nd active and enabled clock edge. Expected 101 (5).",
level);
apply_sequence("01.111;00.111", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got 111 (7) at 3rd active and enabled clock edge. Expected 101 (5).",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 2);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should fail window with weak changes to opposite level" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.101;10.101;00.101;00.L01;01.1H1", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got L01 (1) at 3rd active and enabled clock edge. Expected 101 (5).",
level);
apply_sequence("01.1H1;00.111", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got 1H1 (7) at 4th active and enabled clock edge. Expected 101 (5).",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 2);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should fail on unknown start event" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.101;X0.101;00.101;01.101;00.101", clk, check_input, active_rising_clock_edge);
check_only_log(logger,
"Stability check failed - Start event is X.",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 1);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should fail on unknown end event in active window" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.101;0X.101;10.101;0X.101;00.101", clk, check_input, active_rising_clock_edge);
check_only_log(logger,
"Stability check failed - End event is X.",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 1);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should fail on stable unknown window" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.101;10.10X;00.10X;01.10X;00.101", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got 10X (NaN) at 1st active and enabled clock edge.",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 1);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should fail on unknown in window" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.101;10.101;00.10X;01.101;01.101;00.101", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got 10X (NaN) at 2nd active and enabled clock edge. Expected 101 (5).",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 1);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should handle back to back windows" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.101;10.101;01.111;10.010", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got 111 (7) at 2nd active and enabled clock edge. Expected 101 (5).",
level);
apply_sequence("10.010;01.101;00.101", clk, check_input, active_rising_clock_edge);
check_only_log(logger,
"Stability check failed - Got 101 (5) at 2nd active and enabled clock edge. Expected 010 (2).",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 2);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should ignore second of two overlapping windows" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.101;10.101;10.111;01.111", clk, check_input,
active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got 111 (7) at 2nd active and enabled clock edge. Expected 101 (5).",
level);
apply_sequence("01.111;00.111;00.101;01.101;00.101", clk, check_input,
active_rising_clock_edge);
check_only_log(logger,
"Stability check failed - Got 111 (7) at 3rd active and enabled clock edge. Expected 101 (5).",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 2);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should handle one cycle windows" then
get_checker_stat(checker, stat);
apply_sequence("00.101;11.101;10.111;01.111;00.111", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
verify_passed_checks(checker, stat, 2);
end if;
end procedure test_concurrent_std_logic_vector_check;
procedure test_concurrent_std_logic_check (
signal clk : in std_logic;
signal check_input : out std_logic_vector(1 to 3);
checker : checker_t;
constant level : in log_level_t := error;
constant active_rising_clock_edge : in boolean := true) is
constant logger : logger_t := get_logger(checker);
begin
if running_test_case = "Test concurrent checker should pass stable window" then
get_checker_stat(checker, stat);
apply_sequence("00.1;10.1;00.1;01.1;00.1", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
verify_passed_checks(checker, stat, 1);
elsif running_test_case = "Test concurrent checker should pass window with varying drive strength" then
get_checker_stat(checker, stat);
apply_sequence("00.1;10.1;00.H;01.1;00.1", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
verify_passed_checks(checker, stat, 1);
elsif running_test_case = "Test concurrent checker should handle weak start and end events" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.0;HL.0;LL.1;LH.1", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got 1 at 2nd active and enabled clock edge. Expected 0.",
level);
apply_sequence("LH.1;00.1", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got 1 at 3rd active and enabled clock edge. Expected 0.",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 2);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should fail unstable window" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.0;10.0;00.1;01.1", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got 1 at 2nd active and enabled clock edge. Expected 0.",
level);
apply_sequence("01.1;00.1", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got 1 at 3rd active and enabled clock edge. Expected 0.",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 2);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should fail window with weak changes to opposite level" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.1;10.1;00.1;00.1;00.L;01.1;00.1", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got L at 4th active and enabled clock edge. Expected 1.",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 1);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should fail on unknown start event" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.0;X0.0;00.0;01.0;00.0", clk, check_input, active_rising_clock_edge);
check_only_log(logger,
"Stability check failed - Start event is X.",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 1);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should fail on unknown end event in active window" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.1;0X.1;10.1;0X.1;00.1", clk, check_input, active_rising_clock_edge);
check_only_log(logger,
"Stability check failed - End event is X.",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 1);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should fail on stable unknown window" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.1;10.X;00.X;01.X;00.1", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got X at 1st active and enabled clock edge.",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 1);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should fail on unknown in window" then
mock(logger);
apply_sequence("00.1;10.1;00.X;01.1;01.1;00.1", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got X at 2nd active and enabled clock edge. Expected 1.",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 1);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should handle back to back windows" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.0;10.0;01.1;10.1", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got 1 at 2nd active and enabled clock edge. Expected 0.",
level);
apply_sequence("10.1;01.0;00.0", clk, check_input, active_rising_clock_edge);
check_only_log(logger,
"Stability check failed - Got 0 at 2nd active and enabled clock edge. Expected 1.",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 2);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should ignore second of two overlapping windows" then
get_checker_stat(checker, stat);
mock(logger);
apply_sequence("00.0;10.0;10.1;01.1", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
check_only_log(logger,
"Stability check failed - Got 1 at 2nd active and enabled clock edge. Expected 0.",
level);
apply_sequence("01.1;00.1;00.0;01.0;00.0", clk, check_input, active_rising_clock_edge);
check_only_log(logger,
"Stability check failed - Got 1 at 3rd active and enabled clock edge. Expected 0.",
level);
unmock(logger);
verify_passed_checks(checker, stat, 0);
verify_failed_checks(checker, stat, 2);
reset_checker_stat(checker);
elsif running_test_case = "Test concurrent checker should handle one cycle windows" then
get_checker_stat(checker, stat);
apply_sequence("00.0;11.0;10.1;01.1;00.1", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
verify_passed_checks(checker, stat, 2);
end if;
end procedure test_concurrent_std_logic_check;
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("Test concurrent checker should pass stable window") or
run("Test concurrent checker should pass window with varying drive strength") or
run("Test concurrent checker should handle weak start and end events") or
run("Test concurrent checker should fail unstable window") or
run("Test concurrent checker should fail window with weak changes to opposite level") or
run("Test concurrent checker should fail on unknown start event") or
run("Test concurrent checker should fail on unknown end event in active window") or
run("Test concurrent checker should fail on stable unknown window") or
run("Test concurrent checker should fail on unknown in window") or
run("Test concurrent checker should handle back to back windows") or
run("Test concurrent checker should ignore second of two overlapping windows") or
run("Test concurrent checker should handle one cycle windows") then
test_concurrent_std_logic_vector_check(clk, check_stable_in_1, default_checker);
test_concurrent_std_logic_vector_check(clk, check_stable_in_2, my_checker2, error, false);
test_concurrent_std_logic_vector_check(clk, check_stable_in_3, my_checker3, info);
test_concurrent_std_logic_check(clk, check_stable_in_5, default_checker);
test_concurrent_std_logic_check(clk, check_stable_in_6, my_checker6, error, false);
test_concurrent_std_logic_check(clk, check_stable_in_7, my_checker7, info);
elsif run("Test concurrent checker with std_logic_vector input should pass unstable window if not enabled") then
wait until rising_edge(clk);
wait for 1 ns;
get_checker_stat(stat);
apply_sequence("00.101;10.101;00.111", clk, check_stable_in_1);
check_stable_en_1 <= '0';
apply_sequence("00.111;01.101", clk, check_stable_in_1);
check_stable_en_1 <= '1';
apply_sequence("01.101;00.101", clk, check_stable_in_1);
apply_sequence("00.101;10.101;00.111", clk, check_stable_in_1);
check_stable_en_1 <= 'L';
apply_sequence("00.111;01.101", clk, check_stable_in_1);
check_stable_en_1 <= 'H';
apply_sequence("01.101;00.101", clk, check_stable_in_1);
apply_sequence("00.101;10.101;00.111", clk, check_stable_in_1);
check_stable_en_1 <= 'X';
apply_sequence("00.111;01.101", clk, check_stable_in_1);
check_stable_en_1 <= '1';
apply_sequence("01.101;00.101", clk, check_stable_in_1);
wait until rising_edge(clk);
wait for 1 ns;
verify_passed_checks(stat, 3);
verify_failed_checks(stat, 0);
elsif run("Test concurrent checker with std_logic input should pass unstable window if not enabled") then
wait until rising_edge(clk);
wait for 1 ns;
get_checker_stat(stat);
apply_sequence("00.0;10.0;00.1", clk, check_stable_in_5);
check_stable_en_5 <= '0';
apply_sequence("00.1;01.0", clk, check_stable_in_5);
check_stable_en_5 <= '1';
apply_sequence("01.0;00.0", clk, check_stable_in_5);
apply_sequence("00.0;10.0;00.1", clk, check_stable_in_5);
check_stable_en_5 <= 'L';
apply_sequence("00.1;01.0", clk, check_stable_in_5);
check_stable_en_5 <= 'H';
apply_sequence("01.0;00.0", clk, check_stable_in_5);
apply_sequence("00.0;10.0;00.1", clk, check_stable_in_5);
check_stable_en_5 <= 'X';
apply_sequence("00.1;01.0", clk, check_stable_in_5);
check_stable_en_5 <= '1';
apply_sequence("01.0;00.0", clk, check_stable_in_5);
wait until rising_edge(clk);
wait for 1 ns;
verify_passed_checks(stat, 3);
verify_failed_checks(stat, 0);
elsif run("Test should handle reversed and or offset expressions") then
wait until rising_edge(clk);
wait for 1 ns;
get_checker_stat(stat);
check_stable_start_event_4 <= '1';
check_stable_expr_4 <= "101";
wait until rising_edge(clk);
check_stable_start_event_4 <= '0';
wait until rising_edge(clk);
check_stable_end_event_4 <= '1';
wait until rising_edge(clk);
check_stable_end_event_4 <= '0';
wait for 1 ns;
verify_passed_checks(stat, 1);
elsif run("Test pass message and that internal checks don't count for std_logic_vector") then
get_checker_stat(stat);
mock(check_logger);
apply_sequence("00.101;10.101;00.111;01.101;00.101;00.101", clk, check_stable_in_8);
check_only_log(check_logger,
"Checking stability - Got 111 (7) at 2nd active and enabled clock edge. Expected 101 (5).",
default_level);
apply_sequence("00.101;10.101;00.101;01.101;00.101", clk, check_stable_in_8);
wait for 1 ns;
check_only_log(check_logger,
"Checking stability - Got 101 (5) for 3 active and enabled clock edges.",
pass);
apply_sequence("00.101;10.101;00.101;10.111;00.111", clk, check_stable_in_8);
wait for 1 ns;
check_only_log(check_logger,
"Checking stability - Got 101 (5) for 2 active and enabled clock edges.",
pass);
unmock(check_logger); verify_passed_checks(stat, 2);
verify_failed_checks(stat, 1);
reset_checker_stat;
elsif run("Test pass message and that internal checks don't count for std_logic") then
get_checker_stat(stat);
mock(check_logger);
apply_sequence("00.1;10.1;00.0;01.1;00.1;00.1", clk, check_stable_in_9);
check_only_log(check_logger,
"Stability check failed for my data - Got 0 at 2nd active and enabled clock edge. Expected 1.",
default_level);
apply_sequence("00.1;10.1;00.1;01.1;00.1", clk, check_stable_in_9);
wait for 1 ns;
check_only_log(check_logger,
"Stability check passed for my data - Got 1 for 3 active and enabled clock edges.",
pass);
apply_sequence("00.1;10.1;00.1;10.0;00.0", clk, check_stable_in_9);
wait for 1 ns;
check_only_log(check_logger,
"Stability check passed for my data - Got 1 for 2 active and enabled clock edges.",
pass);
unmock(check_logger);
verify_passed_checks(stat, 2);
verify_failed_checks(stat, 1);
elsif run("Test that a new start event restarts a std_logic_vector window when allowed") then
wait until rising_edge(clk);
wait for 1 ns;
get_checker_stat(my_checker10, stat);
apply_sequence("00.101;10.101;00.101;10.110;10.111", clk, check_stable_in_10);
apply_sequence("10.111;00.111;H0.101;00.101;01.101;00.110", clk, check_stable_in_10);
wait until rising_edge(clk);
wait for 1 ns;
verify_passed_checks(my_checker10, stat, 4);
verify_failed_checks(my_checker10, stat, 0);
elsif run("Test that a new start event restarts a std_logic window when allowed") then
wait until rising_edge(clk);
wait for 1 ns;
get_checker_stat(my_checker11, stat);
apply_sequence("00.1;10.1;00.1;10.0;10.1", clk, check_stable_in_11);
apply_sequence("10.1;00.1;H0.0;00.0;01.0;00.1", clk, check_stable_in_11);
wait until rising_edge(clk);
wait for 1 ns;
verify_passed_checks(my_checker11, stat, 4);
verify_failed_checks(my_checker11, stat, 0);
elsif run("Test that check_stable can be called sequentially") then
get_checker_stat(stat);
check_stable(clk, en, start_event, end_event, expr);
verify_passed_checks(stat, 1);
verify_failed_checks(stat, 0);
reset_checker_stat;
end if;
end loop;
test_runner_cleanup(runner);
wait;
end process;
test_runner_watchdog(runner, 4 us);
end test_fixture;
|
<filename>Labs/project/countdwn/top_tb00.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:51:22 04/29/2020
-- Design Name:
-- Module Name: D:/SKOLA/letny/DE1/projekt/final/countdwn/top_tb00.vhd
-- Project Name: countdwn
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY top_tb00 IS
END top_tb00;
ARCHITECTURE behavior OF top_tb00 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top
PORT(
pinA_i : IN std_logic;
pinB_i : IN std_logic;
butt_i : IN std_logic;
clk_i : IN std_logic;
s_reset_i : IN std_logic;
sclk_o : OUT std_logic;
dio_o : OUT std_logic;
LED_o : OUT std_logic
);
END COMPONENT;
--Inputs
signal pinA_i : std_logic := '0';
signal pinB_i : std_logic := '0';
signal butt_i : std_logic := '0';
signal clk_i : std_logic := '0';
signal s_reset_i : std_logic := '0';
signal firstTime : boolean := true;
--Outputs
signal sclk_o : std_logic;
signal dio_o : std_logic;
signal LED_o : std_logic;
--
-- Clock period definitions
constant clk_i_period : time := 0.1 ms;
constant pinA_i_period : time := 100 ms;
constant pinB_i_period : time := 100 ms;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top PORT MAP (
pinA_i => pinA_i,
pinB_i => pinB_i,
butt_i => butt_i,
clk_i => clk_i,
s_reset_i => s_reset_i,
sclk_o => sclk_o,
dio_o => dio_o,
LED_o => LED_o
);
-- Clock process definitions
clk_i_process :process
begin
clk_i <= '0';
wait for clk_i_period/2;
clk_i <= '1';
wait for clk_i_period/2;
end process;
pinA_process :process
begin
-- make signal 1/4 of period late
if firstTime then
firstTime <= false;
wait for pinA_i_period/4;
end if;
pinA_i <= '0';
wait for pinA_i_period/2;
pinA_i <= '1';
wait for pinA_i_period/2;
end process;
pinB_process :process
begin
--make signal 1/4 of period late
--if firstTime then
-- firstTime <= false;
-- wait for pinB_i_period/4;
-- end if;
pinB_i <= '0';
wait for pinB_i_period/2;
pinB_i <= '1';
wait for pinB_i_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
s_reset_i <= '1';
butt_i <= '0';
wait for 100ms;
wait for 10000 ms;
butt_i <= '1'; --check if the switch sends out a signal
wait for 200 ms;
butt_i <= '0';
wait for clk_i_period*10;
-- insert stimulus here
wait;
end process;
END;
|
<reponame>blair3sat/LimeSDR-PCIe_GW
-- ----------------------------------------------------------------------------
-- FILE: LFSR.vhd
-- DESCRIPTION: Linear-feedback shift register
-- DATE: June 15, 2016
-- AUTHOR(s): <NAME>
-- REVISIONS:
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity LFSR is
generic(
reg_with : integer := 32;
seed : integer := 32 --starting seed
);
port (
clk : in std_logic;
reset_n : in std_logic;
en : in std_logic;
data : out std_logic_vector(reg_with-1 downto 0)
);
end LFSR;
-- ----------------------------------------------------------------------------
-- Architecture
-- ----------------------------------------------------------------------------
architecture arch of LFSR is
--declare signals, components here
signal lfsr_data : std_logic_vector (reg_with-1 downto 0);
begin
process(reset_n, clk)
begin
if reset_n='0' then
lfsr_data <= std_logic_vector(to_unsigned(seed, reg_with));
elsif (clk'event and clk = '1') then
if en='1' then
for i in 0 to reg_with-1 loop
if i=0 then
lfsr_data(i)<=lfsr_data(reg_with-1);
elsif i>=2 and i<5 then
lfsr_data(i)<=lfsr_data(i-1) xor lfsr_data(reg_with-1);
else
lfsr_data(i)<=lfsr_data(i-1);
end if;
end loop;
else
lfsr_data<=lfsr_data;
end if;
end if;
end process;
data<=lfsr_data;
end arch;
|
entity test is
subtype t is foo(0 to 2)(bar);
end;
|
----------------------------------------------------------------------------------
-- MEGA65 Top Module for simulation: HRAM debugging
--
-- done by sy2002 in June and August 2020
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use work.env1_globals.all;
entity MEGA65_HRAM_SIM is
end MEGA65_HRAM_SIM;
architecture beh of MEGA65_HRAM_SIM is
-- CPU control signals
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_data_in : std_logic_vector(15 downto 0);
signal cpu_data_out : std_logic_vector(15 downto 0);
signal cpu_data_dir : std_logic;
signal cpu_data_valid : std_logic;
signal cpu_wait_for_data : std_logic;
signal cpu_halt : std_logic;
-- MMIO control signals
signal switch_reg_enable : std_logic;
signal switch_data_out : std_logic_vector(15 downto 0);
signal rom_enable : std_logic;
signal rom_busy : std_logic;
signal rom_data_out : std_logic_vector(15 downto 0);
signal ram_enable : std_logic;
signal ram_busy : std_logic;
signal ram_data_out : std_logic_vector(15 downto 0);
signal hram_en : std_logic;
signal hram_we : std_logic;
signal hram_reg : std_logic_vector(3 downto 0);
signal hram_cpu_ws : std_logic;
signal hram_data_out : std_logic_vector(15 downto 0);
-- Main clock: 50 MHz as long as we did not solve the timing issues of the register file
signal SLOW_CLOCK : std_logic;
-- Pixelclock and fast clock for HRAM
signal CLK1x : std_logic; -- 100 MHz clock created by mmcme2 for congruent phase
signal CLK2x : std_logic; -- 4x SLOW_CLOCK = 200 MHz
-- emulate the switches on the Nexys4 dev board to toggle VGA and PS/2
signal SWITCHES : std_logic_vector(15 downto 0);
-- HRAM simulation signals
signal hr_d : unsigned(7 downto 0); -- Data/Address
signal hr_rwds : std_logic; -- RW Data strobe
signal hr_reset : std_logic; -- Active low RESET line to HyperRAM
signal hr_clk_p : std_logic;
signal hr2_d : unsigned(7 downto 0); -- Data/Address
signal hr2_rwds : std_logic; -- RW Data strobe
signal hr2_reset : std_logic; -- Active low RESET line to HyperRAM
signal hr2_clk_p : std_logic;
signal hr_cs0 : std_logic;
signal hr_cs1 : std_logic;
signal gbl_reset : std_logic;
signal reset_counter : unsigned(15 downto 0) := x"0000";
begin
cpu_data_in <= switch_data_out or rom_data_out or ram_data_out or hram_data_out;
fakehyper0: entity work.s27kl0641
generic map (
id => "$8000000",
tdevice_vcs => 5 ns,
timingmodel => "S27KL0641DABHI000"
)
port map (
DQ7 => hr_d(7),
DQ6 => hr_d(6),
DQ5 => hr_d(5),
DQ4 => hr_d(4),
DQ3 => hr_d(3),
DQ2 => hr_d(2),
DQ1 => hr_d(1),
DQ0 => hr_d(0),
CSNeg => hr_cs0,
CK => hr_clk_p,
RESETneg => hr_reset,
RWDS => hr_rwds
);
fakehyper1: entity work.s27kl0641
generic map (
id => "$8800000",
tdevice_vcs => 5 ns,
timingmodel => "S27KL0641DABHI000"
)
port map (
DQ7 => hr2_d(7),
DQ6 => hr2_d(6),
DQ5 => hr2_d(5),
DQ4 => hr2_d(4),
DQ3 => hr2_d(3),
DQ2 => hr2_d(2),
DQ1 => hr2_d(1),
DQ0 => hr2_d(0),
CSNeg => hr_cs1,
CK => hr2_clk_p,
RESETneg => hr2_reset,
RWDS => hr2_rwds
);
-- QNICE CPU
cpu : entity work.QNICE_CPU
port map (
CLK => SLOW_CLOCK,
RESET => gbl_reset,
WAIT_FOR_DATA => cpu_wait_for_data,
ADDR => cpu_addr,
DATA_IN => cpu_data_in,
DATA_OUT => cpu_data_out,
DATA_DIR => cpu_data_dir,
DATA_VALID => cpu_data_valid,
HALT => cpu_halt
);
-- ROM: up to 64kB consisting of up to 32.000 16 bit words
rom : entity work.BROM
generic map (
FILE_NAME => ROM_FILE
)
port map (
clk => SLOW_CLOCK,
ce => rom_enable,
address => cpu_addr(14 downto 0),
data => rom_data_out,
busy => rom_busy
);
-- RAM: up to 64kB consisting of up to 32.000 16 bit words
ram : entity work.BRAM
port map (
clk => SLOW_CLOCK,
ce => ram_enable,
address => cpu_addr(14 downto 0),
we => cpu_data_dir,
data_i => cpu_data_out,
data_o => ram_data_out,
busy => ram_busy
);
-- HyperRAM
HRAM : entity work.hyperram_ctl
port map (
clk => SLOW_CLOCK,
clk2x => CLK1x,
clk4x => CLK2x,
reset => gbl_reset,
hram_en => hram_en,
hram_we => hram_we,
hram_reg => hram_reg,
hram_cpu_ws => hram_cpu_ws,
data_in => cpu_data_out,
data_out => hram_data_out,
hr_d => hr_d,
hr_rwds => hr_rwds,
hr_reset => hr_reset,
hr_clk_p => hr_clk_p,
hr2_d => hr2_d,
hr2_rwds => hr2_rwds,
hr2_reset => hr2_reset,
hr2_clk_p => hr2_clk_p,
hr_cs0 => hr_cs0,
hr_cs1 => hr_cs1
);
-- memory mapped i/o controller
mmio_controller : entity work.mmio_mux
port map (
HW_RESET => gbl_reset,
CLK => SLOW_CLOCK,
addr => cpu_addr,
data_dir => cpu_data_dir,
data_valid => cpu_data_valid,
cpu_wait_for_data => cpu_wait_for_data,
cpu_halt => cpu_halt,
rom_enable => rom_enable,
rom_busy => rom_busy,
ram_enable => ram_enable,
ram_busy => ram_busy,
switch_reg_enable => switch_reg_enable,
hram_en => hram_en,
hram_we => hram_we,
hram_reg => hram_reg,
hram_cpu_ws => hram_cpu_ws
);
generate_clocks: process
begin
SLOW_CLOCK <= '0';
CLK1x <= '0';
CLK2x <= '0';
wait for 2.5 ns;
CLK2x <= '1';
wait for 2.5 ns;
CLK2x <= '0';
CLK1x <= '1';
wait for 2.5 ns;
CLK2x <= '1';
wait for 2.5 ns;
CLK2x <= '0';
CLK1x <= '0';
SLOW_CLOCK <= '1';
wait for 2.5 ns;
CLK2x <= '1';
wait for 2.5 ns;
CLK2x <= '0';
CLK1x <= '1';
wait for 2.5 ns;
CLK2x <= '1';
wait for 2.5 ns;
end process;
startup_reset_handler : process(CLK1x)
begin
if rising_edge(CLK1x) then
if reset_counter < x"3B1" then
reset_counter <= reset_counter + 1;
end if;
end if;
end process;
-- HRAM needs *very* long to initialize ("busy=1" at the beginning)
gbl_reset <= '1' when reset_counter < x"3B1" else '0';
-- handle the toggle switches
switch_data_out <= x"0000";
end beh;
|
<reponame>Filip-ZL/MPC-PLD
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
<KEY>
`protect key_keyowner = "Synopsys", key_keyname = "<KEY>", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
eTlSagg5AgxRZKeRGsY0QojO1rwu+kzrmoyR4TnqpZkjRMoTfcqI1pa0pw1ZcGz0qJws6i/zKI2H
<KEY>
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect key_keyowner = "Real Intent", key_keyname = "RI-RSA-KEY-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 214096)
`protect data_block
<KEY>
<KEY>
HaOUERToM6uYA+lB6Dg2/GLY+Wjc0mFVRknOsNEMMbVx23rbu3VoH4Aie06jwdthPlIlWgDIFKKE
8pudwtVHdAoraUryMblQqQM2Xr4jY+Q7j4lXzv311QuGlZ+3LAo/4V3gl/c8dGNk04/Hqp3wylKe
Zx2+qvboLCdSHkLnVj81eKoiplJLvKuSTHxyb2vm+a/6obbiOwfaaOJRXLkjDUj+Ou9Upx9ptqsF
WS7ogrSOvL2mRiXGuofb3dT4gpC3GOv79cMSTwm6Y23D+RUyy3Y7myjqWCtibWO/vjkZkjDW7mu2
wxfPKAE/af+foSANKLX02kIGIKG2stEmU/Mit/nC5iSuosaOylYogX6vAKrwi/NPKwFPTivPesoo
VSPsTPpSpcUKv1gIadmzWJpQXyFao9QOW2bDvc46l/uQWVxENh4IMcxdoEcTn4a1tCn8NWKdTlJE
1bkJ16S4kSXCXxR5BdU+vu9gvu40Ent0MLibyv/arlGn+3+34I7pJ0LEJ9IXdNcNK8D5oBznCC56
06w2u2TjExqeHWOBbDB2GKyeKFFzBAYbF8Btcj+oBjYT7JlyW/eaIg6AxsnONphkbefQGEc6lXIz
zh2P+v2MSXQl+mz/EXevc5G8pq2aW0EtQFWlO4m1o3c6YyidwlidiSKbrIstjbwagejCak5Zc0bY
8fPkqplHP4oHjDV9bsPdxNZEp1g/vbB6I9vKbDn9pvA4GgB1cGHkwmmOXvFzrAh+FyzyGXhA9PhH
nR4Md/qz23+Se8Jwbjk7kZlNZopo0v8dkfSHPnWWlngxIsm058MpYSQnvcQDyZ+NkoZNKynwWlpT
NynQQw1s2gyxch+GQzJKaXvubifhhxt4qEV0CAfbTEWwb3rP9egv98+AOOj/8KhxLzkzwCp5m9Cn
GBOeb4NfUrjTV0GIxWwbJvE0Bn6hkzwoJEHoS7cWCdjqdr8xdQu6qDE4HRV85g5pL8Vzo0JkpMb6
aMt+vQoeYp/dIeHJmTWBcMbHRQFPtn9w++Px4PXyRoggULvPLaesHLoc2+/00ir5oWD6EroQQi2G
r8sKfRMQt4GW02vvhvFuaJGLfQknXqOKrUQDA24rL1aZmnL9VApFg9p06uQCLj31qN6lQU+7tLwK
Uu8F6trZSdCIyMnS4R+mj7D7PoqOoeyL9e/uf4hCLFmbE27i/fT2/x8lK0esAVeLq0YuHi3ueCs3
Ol6jy80MbeqPxiIaXJxRMn0xESHcsxVqX7qwKM14qm5IGVAlbEYPtXxPV6Ke3CaI3Bb40+4SlE6V
vH6ivRxzyYwjReRUDXnKUfp7EPE4BSkXuVVXpGlA0MftGSRRlRJOhXXbP/2Ez64gShRz4iCcWjdX
i++rSdxU42NRuKFbH/0Dsl3cyXYDvAY1A+xtwuC/X1JQyV+7Ct7esFWgdjwDtq8DqGUSIuFB3OwA
ZNaREEki1w9MUX26EPeSuQsZnJVRSRZmk9FI4g2/46h4cNj4z+cpi34x8WG8KTRnUpFjHLA/eN9x
zS6U4dq8ijjOKYAjOv4lGtx907f9sNzTVFAh9JlQygygydWhO4RfeLe9ZmiX96YnQgk8nI6MTzAH
IdW2IR5xBS/YPjtNtsvXdOxgMbjw03DyeJcHb/lgD15kD0LHlUyrfpGplV58eTk3IbztVDKmiM3A
9iVh6QHKcYjr+ZED/Au3JnWdeEAmSUIf7dHMdNVCA05YOHTmY3qZqkifgp5I7xs3dUm/5+3tvGqt
0ATY0QlAwN8pbs6maQ3lTWX9bPHDXbAXzQEtn2cL/dKj/nCeixB7kz4iDjgyZ7RSjzeLtF5h5FqK
ADO+wDUSBxvCiNgIPX7itodAbgTYR/fc8vEM2SUd8FwsPqT/Nvezfxhi07GoYNLZnrVLBn8q6rN4
JYkgMHDtMZEg8FV3oQR+kpQA6cXvk2JbcGphI3/TYb7a1RMBixnRUerZEPAS0wQLE7ECyD4g5Xet
yNEfc4tgNGlAPY/Fh5O06GY/yTt0mL4XwiKeUnTTB2njXEumMPQH9vGtXBmvg5+pCuOopPKg6oz7
UC1wxANtNcggcnOvxt3VhrRcBB27IaaW/4JXdlO7CkqAw2FO2LT7K0fyvVdknY4fH5BWr0c7GUq+
X2POzUrfLBJxg9PVP6PEFDQDkzeBSp2J/Z7VSlovfnpRYs/iztKI73KqBXXrH2LzSjulovuHQB2R
VaCJgXs1/FkT64FFTx5pxP/obSPnTccBeG4QObUD23WK0TE/JYvt6BjvqtoPbXDmfV9hMrdEnaBR
TWs5XYZXESIfL6me9Q7C+SH2G3Qyi9YrzsBrgcaQpANFcg2W9oOPZz0u4H8d/qNyEzBsl4PKjb/H
V7OWEYjQYgK2PyIbUAVQp7xNorE7YeXetBZBm9hPI6lXgonr8hvdbDQEKnHQAs4T2OHbpz2VakR7
vShNN/gd1EwGYT5uoHfOXv0qadXxIb2AZ4XpCEB+QISyTKgatE2U2VL7w7jvb2eBLFTcaJ2zT+vG
AlprUjDFBUWS3tM9WwO1mJlNPzxkTF2lUsI+d0/kU7hM/ZFJo4WTWKfkgb99vQxF4W7xIFJNM8T8
qJg83JeWk6ZMJn4Uj9IPgNlFa+lyK1k0gLAAmPn6bqMY2Rzf/8/pb7dqkEk9eQBKA6OGGNx0COFR
txWgQIt0568CtP/dYQLtcRENBsfzqNVWc733b8v0te03on6H9pzjn5vbmImmogicRtFfD/J1ewcY
jWxyG7UBvyQaVjMpRTcX655fRWHK2mvG/9AyhCkoIDIx9Xej5ItP6XV4FdmccIYaOdHv6iuVwzD3
vtZmgRhPG9snpzWNcUGXKfAOYZbrqz4r+qbuPUQcn/J3ZacXjrfTJyV/a4W00f08sUyap5fTNYqk
11Bt0fbF4puMt+U0nyqk5/k69S8JNuHYbYnKn3IoCJ/AWYguO9Frh1aDSjv4zEDJeZkt/rUVoJln
kBjUc0EMIP1VK4pIuJ9RUWeYbVYIxl5j3WXoteXEEzmdM+iN8ixmhpMh1b9UkBz9FZ07xPTr7uII
uBQVwWUUZsqKezJPb6Bn/UpH4YBeofF0sKsPAOgQHtkX6yDxknjCZtMZITiyMXHMYghScsiSqZao
YnwEPM4enK7sG2XX8rg+WS/S7qSSsvips1FOqx4FovfowaLmaJcENe6g4nEk1a/hyx5zF7YBVJEj
SIMnXfDGdWwyEVkIQvizoBGAHjHdwqsvxc6oeZ7jhe63uxIchAwy6+wUPfvBt84G0QcuJO8u0SF/
rHgPkqZG1w5GJCx5eriV8gOTKPDQhHheaZ+O6QV9bAzCUisP1EviYCxV0FHxBrYsxag5I5OoWOPL
4lMgGEI5hQyb6K7JTgC5JFgvK0kIsi4z0zA1JLXHAgPGzhlWJ24F2VK0+Q4D6Djpo+T0oUYCbBV5
ZkYGFkslUmRbuJSQT+kaybBWNVWb/euXWjbyW0ssAAQw8JxrDG8DGvpaMPfSG+aeRTJZwZlfiSUN
Sf1SpFR5X7RkZ2EB3ILr2/Y9SVPqgqkT4YH0kai+vQCyyZqxhoq8TJkDhuLIFXX9Kiyzv1WJFmY0
kS/KkPAUHLgiUDlXVM3Tb59CApNfgcDvsHjkrbqFWkjO2/LKIo+SbpdWBCd3wcf28ST2MfZdbbhX
osCmU1+5TeDKLLhMm3CcgM8Gn1p2PUFkhDZw+B71NMzCTTunFiCVg4FfKP8fQFiyuy+xOWjYQAwz
EsKPt1mj7RfU1YJwfifY1BBnafuumRHIaMTfs5s59NDdYq/1aTbDnEQdkGuzCiS4UfVG7/wzD7Bo
OXGXgCWqXVRQ2OyXaukOYB1ceYUiPmiCGxbAQVpCKlnKk00QRLji25mrRaA6tLZJzLRm8gsz9D6n
TOAgL2lH6bKUUz8JGzunNrexywYNNZa0s8OOlI3SJZMBRJmtH3V4jqEehNLYuZkDZ+W/1e2NrjO3
ldlF290iHuYgzLYQxVI1SeCByX1w5gHuLwtCDvZzODm5nHQvmdnc3tFB8dbNL7rfIwDp7uT73vC7
9ZMPuijl7FAI8+j541mksl/f3FckHyO1FSoL6YucERnbAsMLLXdFLECGW/o+OO7t2YnLGf1QohK7
D/6/xB2cG+11GbRRxtcPvxItWdgtPCgBKNH5zeF8Ho9cMfDjrB1zyqXy4DZx1+fB41JHM3RXRMh0
0FagurgeeJ61XcIUsYHRLIUKSToJkZU9RIXFs3DlbKx/jzEQK4pVGrf8dLt1Y7uklvAns8RDSDXI
6loyYeut/bUfOMBm7CVjO33Jo4H4aNowc6etIxzt00BQdVsyYvWp7BpdeaeCFK8c6Anpqh5TFHbb
b+2w0bzjlyK9h9ae/eRji3GCs9x2kmYVrrvD5A/Nw3XNDAl7d7szR2U7XPUYCCuEVY46yZGE9rHr
ccYUWnuQWdkRlzYC9LLANaxrXl1CULrIk4SxsEyN2cddjGq6TraxSrpUM890HVd4SlJsDjaUFG2L
5Fh6U7Xp70w4Q9HIK4ocT43WM2c1VA/5EWzatCoLOE5CcP+wyymM9W4xbU5O/9s+/RvWNVZxzEbu
esLEp1kgq9d9lwZg/AaYliOaAyMzLa1zeEK/Ugs3xngfv/beIvdbv5uhrQGgKm02mvNf8Ul+1mZy
F34eU9+F4HcdfrRb3whFyNh8J7elQCsF+3EkJ942Gv7U4m1kw4hsIMhfSSFxvraP6tL3CE/xM3hZ
WWx82/QWKrtG6Uco2RD/YoihgJJ0atI5JPiTwFiiBsSL1nDtiG4RiXsH2SEhsX3WwjmSGDNGfJO9
RWaysKSgjChOY5cX9j6i4mWTbuOglmFp+qHsHirB14nQDm2voDuqCwriZhkp56UiGwXeaKsdST5O
7SUzrxfntcPsSPQk6Dfl7YyUTmkFwaQSsXqOLT7ONzZiEdsPV+VRxnAvwXnDqLGDKwc3fZcS6JNN
rqHyb7NU5hs3/wcYCA4QfdPGgKn435IYTEgusGQv0KoyMFjMJUVYLYt3VP5FcwLi+j6W049Wu9v3
2/RPmY0LKa1XOR+gfh+dOWJfLpC6FHumAxcWxzRB2YQvVYOo6bstZbZ7INXXoSJwvF9dZ94eJ4oZ
j5D5yCGIYonZLEJElqztKix+1hL+7ROpa5DFNGDxtj9/ib2MeGVc9gniH3tpUp+DbJvIc8nH/dsz
DHif/NPeKVQ78aaHy60RynpkFBSqZonAXT3vQ2x3vqg/Y3JnY/Vz23YkhqHKBrwCJFkIxq86wuII
Z7GAq0fL/nEP2EtbxGy36yQG0oKyurVySiHlG9lJZGSfcTyzZRkZmQlQgs5zth0VK9erJ0DbKcYa
NeiUM9mXxvkpAkxrJyP96tbgGaAmCWixIIcAJuGx/ETPzyl9robjpHWrEuH8Nar84E2F0dAU5bK8
UUHcBbLgyRxUm8WkB4ydw5BD7W1jN2dxW052nVXg8FP3S8Vo3ue4bXvBbFac3FC17YmBceTXPA7s
qtgQ3FXODdbMBPHup9fYCQr89aRD0U52nI33/npbnMg1GUQKeLfePwcm4hYmi7XhAQcHOv6nGOzj
IlWnH5FrerPT2qY2q4imoFg2TvOkrNV+0eQqG2vAlVKRJNfj8KXx9uL/uw1LsgxOqE2q0O88CZAp
+eXjzzo6WabMEf/jxuQc6zHw9WWTJjVLSGYH5ZbuVPufs4y/BsdS+HWjGeW+O3Co1krxD6qGrEP2
fyQjy8IeQKfqrYAw/E5RAVoKESnhGh6QXKpJo/zHvQUHEwCWa9MtQwyMW3iHATNar/e3q5a48L7C
fqEhJtdAqOFBK6JanH/7gY3K1d2WXnGn18bxjE54yWX9vp+yfZLlESJgQjNsoHI1Yv/OQeUGy4aI
vEdTBNpnIp7FnLxeDd0s0/scGvrQvJMAf5ZcYHQ/8Jqc8T44gbgAi+96iETMQLicu8l1gRs0RTEQ
cno5aojqaNF09lwKjsgRFY39qh4ouweMCYvrniQ6vIJzBez7qJe82j4vd+gwb29E9pveBCLaEpBK
LQ/WLsEAYklEmUtdha9h8mWgUI0pDWVp2RNicahLhzGDjWlg+P4ncQ3U4iW8V3syyNWBsuiUJo9w
YcnkREOgngpJ9WIFTb0yYZW0ks/FKEIFxRu6rIlRVYxAyaryP2bjzupONJzcSJPU90sSCoYQB0Lw
Y8yC28jbbXeqxW/bWYAVpjZLYzIOrSzMFO+cGR4wy75n0tdFsp41/sqWjI0kOuIYFn16lo2eu+I9
KaSp622PAREnTOvfAAzjvoJIuCFtny1W7jnaCEFD4VZ00c28c6M/2OtW8quzge33PV2l0h63zmKN
XNPQ0wp/mMsVtE8FIyT/fpuvoTfewiydAlRjAa8NDvcb0eTKwc1Zc9rWmM8AQWc1CQZeykMFyPnB
+M2O/mpvHIHx+7tAtS7j4na9T31WDMUNtJ9VtVAzqqwaYzQFO1C0eUCduaue96qs3DCIU7PFvkL/
u3Q+JSzhZFHCLYVhAZCy9+RmQRHzgMe4Ta9cxMYMQKk8h4997svMeA9pW0NOu2QGwELajV+eJIv4
o5jEwOv/lT9m1w43oUJLRspoBslsCQr5f+ZALSPTUiu6ASEyn0SvHzMfnuLPW9aYjBVxaD6BchGf
6dbLW72Cgw+KpPb9BBNfkL0Z/9DJG0w7Q33FhijQBQpXKK5QUhQMul2wT5jv7nfq9YWIFcnZMXtZ
cOhqIutzUHS48iZ5iiCSNXNPaLmGi0fmWdeD40se18g7pu0UZoTKzPtFbgN9ico+I0z1KYWVmcva
EC9Kpg0oqXmdn24mdXd+O9rl765jhC4pGQR8L2I9i/WmB2VvutV/gex/gYguaBKiW0sHy44QSKDk
MZCaxj54ZVxyxYLANxX0KM+eDrVmAgDb+jgTAdT/r1cx5sDqrJOl5N8LhMN3/0Z4dS3YMSlwzZ4m
9UFvq55Htzav23LnxVplwPREcCSlO9y01SScQQz0eEzcn4msV8tt3CDVgVlFHEOCmrjrkQLvOSJ3
bChFFNeKc4QbRTdDH8IlW2TtkahHQaK87Hjszj/W0qtBvsTqkpgyE1t/o4kQ1q03GdBc768GymW/
6usUDdCr51hWLl0lMWjiKJjbAWZYgHn+gCMO8D35QSXoB+1yylpklJH110GyWs9UkX/TMMtpXSTw
+agCqaqC/cHf7ZwIjE2bQvK1CiDR+f5tm2Y0UCmzmCQ3ozh1ecBOMiF/EAk9p0rbIc6or01rs1H5
0XE2pZEkBGl6Y/r/qmkXv3bDUBQwfPy/H2QZ/BCLZpEOuIefcQx8QRuSaWzNk1+WthKZz7jXyuNh
/O/0Onb0wuSxR6UYTp6ruDecPETOjq89X4/DGB6qr6mMS3ls71k6mZm6F/AVdvZxMyugo4aXVtQt
cT+00dNToeewgLTFFBvtJPyDa85mzBuOk87UI6gzpERi+eitcEPwW720wAIR/mHsxl/Zq7RsBMdS
UGtuwttTOgHpmXnECPG3/3oklwGwQNxbnifvJxbPPlzxA/v5B2hLfN4MxXQxUtunK6HtJj3Je4lG
6lGmSeNr9U64KROOmLz94tTpRHql32ZXJu3JSw/w606ggYFk9UB7fcosjA1u2MNVL++gjFpCsEpP
sy6tk0pjFrIvAU0ZqZkpnbhzhmaOP5cLce7R8EZLsPnEl7Xf9eTWF43wkIcsShhBax98z1JzsegQ
PMteSQ4ekCXrKjvZCM3fu26wph8pepoYDT/p9K77BjbbBn12YeID6zHWjKQ5Naq8fNrdckWLU5E3
K9dXAgDAfq+Py3WVBNjz9SCCsdCUD7Ui/Eb1iJVl8X5NFxMabK77P40rs53NoqCSQUvsC6U9TtGJ
p2D58eKdHfKh5nY6IedxlokOJYDbA8wyJkNrhjfyX5qccETgoAH3lD62hb+NXpfQx0dOfhY/FIiF
M/wtFNCGu4YdkRCzncuYoIacP2gIfOU3V0gk1Z7m0n6XJyctqnzqosagdFX0/YsZqTwqWurRLxpb
0+W1O0a+XEm4kuWEQSsSYZv4L+DygCrjIg53GU2GRqut6tLHaBHtp55rutUa4wAh449SaP2WaNq/
GxBQk+VbRXw3Zqm85aVkTCXZVR7W4TQOv9upilIfuUYT6448SyYOk4qWIa+qxyBgyLbZHhpRES9/
r/cjI4PjDBI3sTcWyC4MFxw+LGl07kx5gLxwopUXcOwWFmZEWzB9MI2rO7jKS9fl8cNXbpZKYcGL
PW3cwUJleB130tKOv51lcsjLDdRlYACB+kZ819BYOZUBfGrENZx4R4jCBhFtmOwVTkoDoEsoA+fj
xgp4FbOaIAA1mCU6mz/5Qh9mbM9vCrRlueWAHx409WHfJtEnAxMd6OiijSmT0yZq3+Xrs6SENKWu
SAC7wcaTFN7QUFPepWN8dMwAdgWucNQnaOVdHMlmj3Yp1jhgEIhjuSacVOL6IApE2EOkmtEXLTeY
doCITXaSri1LI8t3seWaBBC59JuXOAgc/NBZ4TfcG5rVOrBC4c4A4K7IcOpAmM8a4erwDVQ7qwLz
0unrVvQ2eU38BM/B612itTZDsCzZ34hgY0XJTWLkyCDagMljPJ7kMw1Iez0NCXbAsbaCbSLvj0B5
wWlrFMSJ5LsKfa8LbKDQLdLY4Oa9DuDmORu8Y+0WKs8HFKbTxoSszvqv4bjAa5XWNDp8NG8GxDCd
u6Ivx0DMAa5jdId8yQOOnFUP9FTfe3nvGbK4fmQ7Jp3zvRm6NhRNGA6r03LM5VEzIShv/S5nSBBx
yYWaFfA/pLhvvM6ykEDaxRR46Cj5lkaXX9MNan+1e2Y0xBW8r0TPI1DGEY1TK0hVVWTfa62qsU9Y
dlvfSprQbuCcECJl9bRqaWUaxBV6k0UUN2IQUhOtgZdwbFWpJMR5cjQzUpSq0rKHINGgPMsyi9kR
Bl4nnPi1C0FQ9mH9BL+H5CI6UQwGFgal9z23HjZGv3Kgqw/OoD8mZg6yn2rR35S9nyjUn3nZJzf0
QkwtJiXeyN/CF4/SfCKuYSivptSLM4GC/YBLhp4iKbi+l1PBC8HrUMu2LxKqcLDW8vIxxWaZYO3U
fWivqg0MOUPrRc/LSUiIKHfSH0m91gAIlXLMfpKegNXtdhUtlVnC2g1BQXLv4GGc/e/qOsWFO0Ai
Zd6rZrfpSsm3Y6gavCM0qNmaTu/J58iV48yzi79yEt6PRSskQVZvLDeQU8rZgP6nKJ1XUg1ahZoy
3oGLzIMTMk4+j+xzI5na4SK+S4s3UEcjoxTyafLV8ex6zJV+NxEanloF7s6I4dsEiVt/X8tvVgcn
Lgax1Vxae1gJ3agLDlRCVKBt1srfxQNpKRIu36R5uV/x9o0Pr45u5ctb31rjCTVeGvztCZXOrlgL
bhEje2xhXICSqHEJRmB5ThXD+qs0q4vLMI8UF7UKG4DUH9e22r5NVzVV3wYHuTvfe6p1RpQlx9CK
8w40RqjuQPU6cuHyWcF0yHG7rrePG4i5vvOUBfCqzQ8pYw3l/BXthp4fDy8TxC9GTTYz2eOXj9an
dyqhT1BEVGR92lXIKfmBLMiei95+Hn29AhLmqLkglbSFcs0te8LG+YUg9LldUhI+w2q8Mc1mPKO5
goOUXsNdfSKcpBAZP79IxgaHnBRS4NlSZ8qCK5nr1VbRdRkh5Tb38TCOYOwHSJx7krBeh+pY0N9u
A/Me0GlBQNVtrROh8BlxP0llNTxdZ8kK3tPROGmK/nX6HVliW1x9GX4tNpAy5xJMdMuJ9Le+RsmX
UObIAQbhwzHQgr8u5GH3Eq6wnetGI5LpSnIk8qQ37QZROOx9N3/ClWPNLXAuqyllVuvtoc65BDrQ
lIX2gaFHYoYGoYPc1nOK7kfdtIPyExn57M8S8Wh8ocqB1dL8qmAuqW9zSPcjiZwCZEyOlV1QOFrb
f5/U8tybqtoA3RXzULtQ94z8zyLfRQqaXZCmkuys10sd86pM6CshmO1HY6OL6+Jo9q5cSwJtGo+1
uLTd9gPpB/AMO6/ykac+Te+1hCbYzGKbU93mw8m+fqeHIXQjJn7eVBb0grXx/CU3l5rxivOUKwtc
hzw9ougqFkL5UC4cho7VHBq2+B6LbfusGY9RG1eL2TWNJdss0/QoNFfERg4IHhqQ1s4h1fxqAH3x
BNxbKhmhF0jw1XlqWZmVG/apz/wskEaW8HTfVG77qwfF1r0C/FOoRGwcaSExzKXPR8hQ1kctRR8B
/m6rQyn06eT7z2K45TV1W4P2uUNcK7tv8dBM7n/SFazJlcRVVNUBr9WnRi/6zj5OyjqJbh4epUx5
N1a70r54yenJhCCQpQv4s331nr7ktRNI8pdap1zbGqZhQsJ247Zhqo9MGqEuOkFPzQAWgpyzWdV6
+R9z4VeJVO078txTtaS4XAJyMPi8PdExuIED8NI8ZGaVY5sX0fH7IO5YogRBjzq40GWmjz5aHxNI
wfjxKa7kRNIDIeqnaLpH8o0EIq8xKg/8uOe4dE8S4QFjPCNkidDCQBVxxxOUI13iFmkVnLtVy4DI
3YRAybnP0xS7WVusDl4jN78JO1wDnQlwjJnNewakEc9QZif/P2tbuTgU0FOQC7CRg/nqdIz9A2ep
JyT7wCYd4mNQ4HrSBAxqHbH6mC1J/X+KnMIY6sNSWLOLe/WaMpi/S1Hbon9zFP3A0N6goAJsCFo0
CfODq4HBAHyzVnMZd/q9n6VsDA/OzyAh5gwadxZZQn6NxZ8rhv0xwoC/Ptt3i37NDUHNPmUMRWZh
JFpkTVIdYICBN9vO3sTlA8+r4yfWZmQtDo6jJqYoE43C8S+5fQJNqmDrAxxzVhOBpH8kNZ84k9L7
6b7zvKMA/FzTmXHCsUWbROnI0xnKusoVW7hlAcusE02xZUoOzdmqzDPolHi4zwCA5/GUoi8CWJQq
pmu6RY+VI7Dxh18d7OrVlizcBwuZ8m1BtBWI50N04lrNi2ec+J0tR0fe3YDnA4hQ67tMIBvPUZjB
dTocHYoWZDLdfhn6/nUQkSKsUO7gQQfuOvqjTIRopyiPqH5Ckz5L1kawLg6L8QGOunNjQDpmzKfQ
eGE8/519OSNHGNswfi4njZjZ2d3To7mbRBMi0SQ3OJP3Bso6Ht2AzrAwXBLsKK6AGsSnwouDrI5G
EOjdU/sMZW8bY9kABckpvH+RVSli7YTF/IoaJET1SVEe6i/Gcy53WUHr7uZPfLIk5TfCL/+0FGly
J6ku3meH5DAoJf2AF6KdWZ9WfUb/HxERxzjirwtqwL5dxfp/Nmo67GynQdqmXVNkZ0a2tzDeyd3+
/CbcDBsF8u1RWeA0qL2TUnqgopuIVJ/DuAjDh7DUpXflzust6zMJrwxsxNUcEhHw821rjEAueW6H
Nqnw1VIMNel/fcfIXiFNtjMfqntFWBIBNSiK8wXyaWMWoM6oE5Vlh7MNv3w2Gt/2qswT0s2oS5of
IRVxhh1gCBb6g4zhFlJDoq2nsEmmnlvL4jzpWlAYNa/lI5C0nvzTE5aaMMjzVwm7B0nOuwbuhL7z
6neWLbdYJXUmtFX42N/0wX2uS3bcOBXiypnN9+jrX8q+8ex25I7KFHEQnStQxpEjMCANana7YuL8
WIIstcU5HCBqg/E2Dwe1WIFRaEkOYM9Y6Gsv8hpVmjYpBxiJb5ekkxPANlmWuB9GNOPl6e9Lhfcv
n8ccu4lS1sK1n+fiC+kiPr1E9MGOeGBHd6A3TPY0rJYKDWQK8nsIQoBYHY7GGlvzSSfydUolDD3S
htE9soHvhB0QXJLKiwA47cWtLTPk6zl9gOHIcdNZfMh+7M9pVVegAZKOVuvl/Zu0z0tJ9cjHwJHU
dMz+pn2vy/YT5PVEIFCTVovB8ScZr6KhxfEBe7KqMZvjC2s5qoVHuDbCzbmc50GJpfVGyVP9UNiQ
ahaIh7itDCBRyESz+q+QmgNs/P5IrxCuG8O2xOmtrkB7qiYtPQWFePpx3vkM3SH25YwMWjiIB3R1
ALAY7xJIOBRa0t+G3pmGiyGCSoduZGSYuBMwMCEvwbZ8DPJhAIuRZsqmtl/AOalqxkNJI5BqeUkZ
cJuQoat/onHbnvI/c9Q+iegGhvxfyXMtY8NB97itVIXXZwhl6ZmA1KbomMTd2uVlmWzblH+5xaSH
GeF3v3gE8U7zQ3N0aXY6AhoOj8H4a7D8QpWFSZyHEwb514VzbHEm34+MwqaEI3g/PNktQdGzIe3G
/WSu7bXQhREmXW9xVHFwPPCMMDijVFj4FrAJY6+N89Twl76qnePkw/UHQKQ/YW6XH/wIiZhGAfuo
cspLnqczoYG697uGw3DhqTt/6nHj987F9mHEMhZfXmgnFR23YHLhqPw23g7CeH0lv9FsfO/sBysm
lRPwEOLyzCz36fUqs3JZP1m7Q6VTFTmy2VE7UU9gqUdlkApfl99HF4AMCzPdXIIVnY0iaLe+bySu
v2LFzKl0CAITc6b6srNo+KmUy9wh/wlOKwMc8r5txMh9jebzLshNybfI3AzpyRHAlwHPD4XhexYz
e5aredzuD8s+HWleaUhyEArLnbCHd+swXhkAn1GpcvgcQp47cfYXa30Fwjkav/y3XQsc6yuCejoa
1xPlQ7sHv22kmvnyC+W2aWFFY/1b7tRpaaOc1G+uRBjMTrNhBLIQvTZcA8ri8ILmtmEji3qVRFfe
deNUv5nRn47S6yC3S3VBio7kIZ/Gj7GDHCB61dfG+g1fSnRaXbiCX99hQEtmczH5SV2XznaWCdIx
0Go5NumzUokNAEXX83BwZ2+JfKosS2cFaK/PSN9EDl4wgnZFkAd7IqLaWZh8+EaUQhI9UyyDWByy
r7Hg/vKbJJ6Sv5ElVxmFhGTsLa/jIeI4nEXlUz4PjCAVm1Jf3lRvNU10MECGIPPFOuWkw7K8/D4X
5nsh3B1P1+/WAdPu+cO0/unmjxQNM1T01fsBkiOoozfb7r3JlqnJ64cOKaiKP+LHBu+x6uzKwCHT
EQ0NieVdeBHjZZpgVfpyzoEsXTrAg19gJQc6vd42eNd04pBEHPFfPMchKIEJTFV0O6Fpy9Zn4OzH
153Vb8g2WB664PENmgf/EpNfmCtQhLnyMucC5EU06e8j5P6cxB6JRGmsNlfzU6rtRL27x6zTGb1p
3wmDaDB2pZCc2cOzjV2TQoBkINiHvlcuLrM8E9T2XPH73v5Q0vgsg7wXGigtPQoRya5/DzpukeAB
h19FiN1y17dORy3wk+p3t2I2b9r997MIN8AOLUWpBJDE+/zQR/kzYjMzAfgPRJ8LNXHxIl0Jc7Gm
uPRPSmWIlR2vSBo693vMWq5S9k8MIrHvCoB/g4NLpbpwxNKsr7pRhlKal1//726Eenwp9rLShKzG
f3+zjr6Ewy5lBkAElQT1RGVinl6Tqx2ITQ3/qjVClvYRmjOuoVfCwID57oO1ujuIgitRZJdf6DiA
658JuRgDwbQGqWbDmlpu5LPxpl1KQWF6WMfZ81Jht/gQMTSQGKxS2OybTj25DJogGwumF9dGCCBS
cb7rd7IQfBCsQN4wjrkbd/za6FZJA4caPpumzokgnHuUTejKnyF3ZTnvyVUFtBA+PpZWEFTXkoll
+s/BK5Z9VptfMz2NBkCiJxCTrvoI4M464KsnFzJZETwqTX8clSOvey+TEQhNrXk7Sc1+v2wpHx+q
PWR48tU4tPg9CgiAL4ZenMrCjtHCqrrhRY3+QCbs/SfvBhEq3hJBaSGkUeX356QCz7rzxbDyiFc2
v/akdNdXpgwLbjZDYdz+ZSmDBJDQlhu9xltfiiBjTW2e2GSnXIsY70EHm6Y0lFOhJFWhduvTJZg2
5/b9hRTkFvzid45dUhYqeRxtUfWsTf+q4nB4izQI7ZuQzmiJILP8taiJiSyeg30r0jbc38vAhnWP
I0lhPznxl0FmBARnx9xMYFmV+Ed+LnT5A4169O8PWP1YU1/QJOLjcKg/Kuu3Yd0G+p4vWKNe87Mg
Uc6tvTaTE3JFJ5DnLFjGl+l9VAM0ly2KQKw7Fl/JZotNo5EvG6Et8xavGoGuhf072bhYxFuZijEh
lo3deZ5zFL7LjxxZEAt32EZptRxOLuzLf89EWPovh3eP1mWZ5dwdcK5rRoFXuJQqlNrZF1titCHe
LRmQFy6NDeTd1tCiXO9ICZLRsI18iFhOj9873X4l9n4cAA8sLdZ7hHfHTrbUxhNbAH5uRV/jCeyr
N+QmtqaL6Dh7tmDdrcPBD9RPG+DP4zvGavt6jQDdWm8s8dTmnbWwqfvDUBO4WoeA7nL+k/kCaRD9
4OTaUkvhyKRj9EpbuEbiRoJYfppx/P+nSfktiLe/eBjcuGyNhN0SSyXrrGZ9i0O7O22WkCkxNtP7
YbgH0eZkQVMoUMizExkUAOkRWg+G2GReg8qzZdE57Fj0BAFjjybJWxc9MD20N2fxEzjhZpyvD5v4
Y7WXruUvGg/Zbo42wBrS5xMRkbBEHKPMC18zd7Gl6Y0U0MIrWwxYMT3tGKcQ+FvwS7Ldau7YU1Bh
okyadAklqahUi71DIq8WN4AbHitLVxY4MNOTpAFa6cfEjRAY87/F6DAPKjBSsOCK4ltPGxpr21ep
0+FYLML+qxZDFPLVv2VdkoHM7pZSZHluJ4tg5NpRsuQYCUT7evjBVwMfGAGlaAze+lSYK3tbiceP
BGF0Xzspp5QNrnQXNVBZZpvkImlzbNteQe/bM3bkt14lsfLP4bExnkCPTfRgh+NQuDTZzPwM6lRY
kswFwRR5dIoClmNSihIOM9/xE51iFmWc0emUdUz+ZiqhrhJT57GIHHoxIIwB1H17nV4nwjjZJUEa
kk2LhL9+H0EkoI2/ZI+fU3+PUPDekl7wYk34rtRfewIb8w9vsatADnP6rxlkY74elMDouHzsBowK
9bX6qHXPne/Cp5EZNhHsktyPMrgaFhHaF+wIlUgfvzg21UX08cebSkZhBFRenuUl/lb+y2xfHOI7
2QL4msg42ndUymwreXTJlL/AbkNrL1JZ77j7jUqKltXtM6QoYFK6Tx91itTYa12aFhRKV0IPAU7A
blrtt7MmNTTuuqaGlXZtlAKa0EpPCF9c9fqXZAP5AlEk22VM8gWhZT2ScLQkvvFG/htumEfFLIcG
KHztFQGwxS1FSIPoUKJlRLPgPvqNEJvZKoWOH9q2soeyYATW70UUXh73Cs/8LEJ2BPzGcQO23AD3
20RbyGT5LDv6zehJeNFkuZta/y30mSGhyA2pcGNj7MG6a0vGgasKvKPnOyT4KITzR9RpiGAKsWqj
GIBseZtwgXNHn7fPKC0Dbw2GO/MRfz7aNSXs7kS/a861Mn4ANdiovvvC0LdW5b9KW0CtF2rmoZD1
/XTRvU5cQbh4vI90EUF5jxWADrAVgzuBUcsVsk7pAXaxK5KgTQQy/jNdX8YN+2bsJ7nnsZAETmWU
CD1fxxOfI34CaWG5gxN7eAH0bzBNkwlqR2VkBppdvfojo/1xqlILOLLrOrX6fScIKFkOfnCM4EXf
nyrHbKERO1930HAgMz8Exp4VC7ows/X9fiiRuw4tanBbugELhcrZUT5Bqqc+awJrWXjlLpTUduc7
SzNEr/hj7bTNN+IrDY8z9VdnEe4TdKVm7Eu5I2vs+gti4khD7Q2XFYLNNwx7qKC83ZDgwu0g8Ibd
OzT8pkUcqlU8O3RgOHjlYfumm/RS65qpYr4UNs9klILUuRCrLMz0RynSbpmExPoHjyqK4Hwhyw4x
izUudavgcccFw39pedAdq4vyeUPd//GEZrFYAvsyhn/idITtvHy/QxG/0a/e49ZXynn+ayCIpnCr
4N45bW3ydLXHERJomuZht2CYi0FUgBKMfraKQCK2mmUYesSWGhyh8zkkmGdtzqjni+mTRncSrwy8
BA40AQMruam/lRltbIltLiTEo3M8zoEzhOXx4tj90vfBqbVrHjc9p2qntmhxOAlOWmOpL5AaVHkx
T/orRt8Ax8w1DkYZuQnT9GQvs5a3QVzZYagsaxMloyBmt+UTok3mQ+AO5hBlhPyu3S2JTSmmvSdn
ygzXxDhLWkbJvpSfeiKtkDYJSjuy03k7Q40evMKiXwhLmVmEA9aKvzwysmqj7DUBcNu5//zhJyXl
tBpZvxU1oa+JOIo17mUvxlwTOVzREepT1rQ5/suMakX2ETzATZOpHoJdKK9dhZPOjsKX6sou+Xtk
tWH+r+3Cuu9HM0laYkoyiJqvdA4qS+7d1K9PPTyQNKvShYekGHrHfuAiLYRYnqs+PxfNr0B1R2J+
48zX2ESiD4dU9m4L5ygjCmGErgj+MbN+OL2LsVh8Q0b3oVuGrIRHKE7m3y46luv0Ic7PmY1TOsdZ
ZbHpti6se8l2u4rWSIRKU8Dvht8TTrMxaVAMsoBb7sENnIMd0xqhu2mP+yeeGvvxoyghwC+Dfre3
5EBnYk/4shjnh0zd+SuO+oH1qi5sZHUdQ8yZ/0ZJyXVKVJhhbBB3p1+a02SoAjtvwyP71jeQwC7p
U5ZhV9N59IEOZVInXGsBnBKW+e6iicVRjfrvmMP/f2ZHxmGZMa7mkAhPdA4DfHmvUwfi3K+HjU/Z
E/X20m24uj9HJEQzGuefhOfuJe5dmv2du04Z897eUXBQpqfrmLAeMk5VFh3UYxUt6Sd7V7b/kJE/
w+RsMMZ5GiEwTy6PYzC0u9pI5g1rFFt78SU1G+z90FRBahp0zsBNOUu7fHCNkI3HHJDHkC99CFJi
VHheZ3kDbwxnnrIKTq4WwS21qgFRQbzy6t/+b4UPGdZa7kzOnc8iGmJKr/aOYkNAjeK8MX3RANTP
UrHziVdWmQJjQwMhTcBM6peMjJcu7CoBDnwdUeGSMfPKNum6J0Q0rHgffoIap/aXZ5rLrrxkVIHr
/ggAk/eGuoCBrF7vinaeUfCmAqQH2cJX+8fBtZGm2osrgQyw9BCg7/z4WUWc8fQ+xl2CxUVj+tJA
eIoFooezxEwTt91Bb0PtNXhoB4qCENt/GySgcR9BvJIst1EUVdTepfHuhCEO+QFryjdSkl4DiVTH
CitCU4OhgH0bRJiJS4uIQdlH6mOEEh50qHXshbByrG4mIMN+apYIj0j3vHNwD03YFNgOPG2296Kq
7e2WAd3Ldzj+zsHe+vL3IUHYEDufmpWD5jtIPGhpB19hzXds7WiLDpzrR8rOh4IUvIlckoo0xj8U
t+p89CzGzcsbJHH18XEErenH9SoSCzKzjFLtHn6lLVkoNUzqXYloqvHKwawGTaBiDuv36I/PG1fD
Zk1hAXq8XITG33h/Tkhy+Bt8JGeb/p2GkDnKxahvDT0GdYUvQnRQ5vu0dq0mgRSXgrxjAcgw1Lxt
Uo4C0DUSKlwwYSWLKvClUAtozuboB99gMkXv/kZjMOtczE0MQ8747wiY+7GgmCkVjd2wvVfBFD83
7nxH7FC57RUftsNLx6uYV6tOBT0YvjBhjxw/8Qohk2ud0ceRK+Jh659xRCiXqgDi+K7EDCR3vONf
fSkqCkb6wukqOZdBxpqXqiftCruz5NRZWvHJ6gmyXkMZSJgYPV6bK7NrPgCK3dW7icsvYA2NEx6R
nn3UoSxBpQK7do4k+7roaFeshLMU8fcLVG42uhkXfy8ai3q2Lg7ldsN7bfQbNnd+UrZlN2nB1Pni
cOOPk0gR21YOf9N5TCXkGNWkEx7hXM00O3UHv1CrEo6rYCbFCbqhBJTBLblTJ6iN+XpJl4E8dQq+
ae02OA2lfDZ16bqPKG+qcEw6ZNMOApEz5jv+hFPfY4+4ExwVVWjrJN0Sl9ByqWL3yt9c0XIjGNeX
3ggujPqjBmYaHVhuTpPBdg7hWS5mR4RerhCXsWc3aaA3SwFZMAEkl5yphbuGVyzKOCYAt7oU3/XE
7Jm6z/cQiikzs0NLy89YgJoD4pDvJ7NiytOOOp1WurTOVjOJhnPldQLXIMGsaGBrexu3kRRl/O7i
5p2UK4bqyobbVf0B4S7RruGQthA8DOmZaY93VQoIjtEoZ1AasIhrJGjbvDMZaHFn5czwUWVOUZu2
Vp1tPClHiXczj/kaUkb9J4jHYu5tqZ5ZbpjHNu9/QPZ7Gg52KMRwRDPVYpLrLbyxWTxAKmq5XEQv
hVrBu8pCgmB1G94aHuKHirqOJ6QsYHNc7svGNZegwlzAdzYv2uI3e0zUi6+rf+O2d2BBAAZuTwS7
D2zu6A6CgszMMYkwmrV+wwltyRqaS8wU+Z8KR2X+GddOMmjP3+DJN3XP8Y8RmRHVDrC3IUpMJo0D
7iPb11x/XwLUYoHSMw1xo63KrYNsOSTn3UwKc6Ea3r6pjEcShfWD6MY1T5r6xhsusVtN9SMjyKBp
aBuBTbzU3rczhNd6v0xhPsMkpH3e7R/3/tX01Hm+0TP+93fxh+Q+emJl0K8VdjkTNPVVtQ3LDwqM
tQwF/6aCYudMnfdMZNddSg1Eg8Yvt2Ffs5tiFfg3XH7lej4yE11tXE5Lj6TdRb/oMS4mfObP3EBl
SR30ccxMKo5iiuWk8BzLio0UCrNbKGW1uhUinGCE9dSYQB0eofucDqS/+cP66eAXNi4ZhbM/gxNA
u+aTtV0+JqpbEv5Se73QQKG4JOPVkZzWnR2mbZZQmAEGGBYE0RmFNpcrT2y0T7V6ves3vvZcb8Wc
yH3aAqJuGNnht2xahddg9sNvZFijand2VVG6bq0qeVgfDQVWFFI4obROhUell1Ql2kiLAhstqXTo
VWJkMf/ZcQJyJ1pXFFf8R4kN7yNbs8TVnfjhhVVnsf8B9fKcRZiGENE4Eej6JfYgGnUbEtpCTkZg
rLnrNXMUhEhXiA3Jg3f9vvzNstEkHk7SLTiBRMHznd+jZjsmnjU0rQErJPHgZypvEYm74JD3RR4r
SjOuJedD7yL2jDa48XXzeFUKW4LYJUjteBnEJp2IEiiuON4f1AQ5Rgb6FrYe58JzbnwfU02bQhqe
hOE3ardVRP+vy4ghTnEXDnq+hRXf8lx+01S4uljyg5zMKe1sJFvuLaGAtZmpqZVsLzLbiRphL9di
yTuDxxXlZEVgxsXmNeIeX+Prln5sYdwDYUPfLbkXXxXlw9vIMn03ijh4y+M5Yje0aWOX0DwOn8KP
oCS4ZEfomxeUmPbIZVu1Vpj+1F3cLxuQoQL4BqS1TBg0EFAjJoMWp3r+wDfU3POBHZbyQRvvhm8K
mNRm2S3rnd4TjhUNDTIzJx15+GQvKPQlYsD+wnvbCBR3v5aUHVxM68h9prv7K1/uEGxfeakoxSfv
Cgt9IeTrgTSisL6X6uypOZYwkbb53uKuZlMnqPmHRNzmeod/D5jQXLKARdxSU1/PLasg3dpDdXvu
CGiYIRlaE/VyooVXLIjjm0QKfhoBdZuGlTYzSUIXVyHYZcE3ko4hYXRQaZAtmOsGreM7zoLZwVAw
OWcIbqJTvEc+wwf5OMTuBdFg0kWC/5CsWMy4TGc/H0zd3rpg9wrtJrcmHsnqvOydGqbVq5Dy0vfn
wDIGIYgdaVgpICqTXpV8OsGaDYXIwgYAdtsdmI6DTIZp8d5uv52QGXMDSbR3K+9vnKMb/6+bVc5D
vW5W0v8seyCzOgwEsG8OcEyYYi2P4dSU11aVvm0pv5IqduseQ+EgYCAhoRePnp/hI9xZ+29R302M
RrO49epv9WqOAl9cYvh1hqmq0j+/dbS7SRHwvVBvoGzu25U7km10EzKQybFJM5jQAv7e+j4wURUq
Ptt7dg0/Md5OsZ0084HFfP618HeRsIt+iemxgc8ofVzci0sxYTauyaTToXxea171HmxrkVts7Q2H
4vh4bQ+VZaZEp2YYdzQuHXRAcxvwuRBZB2s54qZ/GJ8EzeORT3vFDIO4AjJHG0O7kCuQ08kmwzfx
IX0DhSW+ti7E7CMyrGyEO9jyR5DS0Fw1QItH8a6/5ibewFcnYkjVQj74I13kktba2gKZISpi8UfS
neAlvOqQfXLDngDG0mX/FRbJiW+AfCiUZo9CzSWxK/xceShqflEA1eIWywstT6QyfhE0dBdNfOBP
gZfUZpVsW3b32uyqdsHwGrrtpbYiTehO5+aCNJxaARIjZ9doqiDo1gNo5F4OTKicA96a4QstW8k9
35Z54XWHQ0UywY5ojnetzI1JD0WQ8dQBKTSzHP8Fhn1gLtKH77oDOmHYEbXUfcDrraixLe8JiQU1
rJIgZ/CUNV9UntEiwhQz5EYcTWNqsg6YdHG1GteXyjFNMjPqeOVyRKrjGv0ssxt2OONYjl77ARdW
n8e4WPqcHgc/bSqk3KhfAoYWJUQ6ikvtssOngIUZiycjlTsZx8nbEtzB29yn2hp99/fEHxW4G4UF
kgmH6HBf5DKmWmoGd1jAqFTDFV2RBbcocgvTPxFTF0PzVWeu4kAf95XvX8kp5dzElzE6fgTcIFY9
3uoCrwbFhJq6iLjF4w40loOf4882bWuDVnnvnnHtZ+3JU+hQzIe1Iu9clmVr7NL+0GIkkOLjD/qt
JBuMonsGtKi2p1KAkD+8xvQde+OonpQgg4Kz9Jsfd/+uIG+eLJg7Y/ztU66Sbn51iw3dgbpSWvHd
dPRTw+zn40zzT62AL4Y03v+3KehXv4fy/wdBJIomivKW7M6ZtkncWPLDvkggZNegpPcvTnrRCHnz
nseJMaSOrL+VQ+nUNdOKlcOgCHg+cuygV4i8kj257QDN9fhzVqysrVg8p6gZ/VUoqR7R6NoTQmnD
EDxsDa5JsbUPvTtcQ3UAIAlewLEJRIM+S0xnLYDv30lU8niPfHZ2vSxlWkvAz3Q02bCvKzOLLKw8
W6OuBLdAmmVB7ZB3wbPkEYHzC6MIYEEkek4JMvWitvSvL2JRRBlDvZvpf3eqgAVwmNfuAnvnCxFo
N75piDiVxqnhEsT3x9maJFq3bAtmdSJUGDBcyjOIxiMNo2j1SYUWBB0xtQLr81TuO2SH3JjyBSSs
/J7IWSB+Tnqv6LY0WeMLZECSfVkfk+7Lv9ZXDLT/9dm2ycDB/XmW8YRrdbC4s92/rliJXhzuVQcJ
5kHdfqYgezHW5+nbO7k2JaoZUcuY2FMLFEUOuTgyz9KI4gJ5+tCP/gTBbhsmrJlMf9/OAPWs2dAH
/IwD+XJitdUNZnuAQSGS5IEexNOHsA/1fu5BH/GHbV7m2wvjZ6XJpgXbMnjqnWPdFnF9H3OS0hQ2
xRssGuUIdcqD3G/23FaHKBAvNbSj2ICcx3b6hPbq5+yW6Sr6saxAfuR4AeZLjW/nTdB7VN3lDNhK
zJLJ/RM3WlIBB8Ph+KOjIAoL5xYxQzfho3HIHLX9el7Klr47z+U2tZhepLesogX3/BBZtlR0ugVP
d8WgvSPep0IiMWTeoaCkdpuls9G4BNj+1V1tUxAICN1RLHcodR48OKqxjydmEsmK+uGjOwGjY3mK
R4J0ZhDyRboFCEuxX1udPRE1eWBnt7Vu5kOcSvEhPDP+qagh5QGWzHc/3R8dTxIUBPTZuFwQ9VH0
KHcD35E/MdUKmidV6vlxTzKCBkMoGRRKAwSsbdsGK/YRb5gvtmBR5lhSjSzq8vk8OF1p6YSAXHzy
ByG0fA2+RkIoBRaw+y0n58deZ5l4oNxaaHwFQFALJoWw0XoYRI5j5U2lpPJi7dCxm0FXvPOzFBU/
7Yd/7D2To2pNcnzMqnVkpd3r0r88N8FsPwjblDR6hKZZ8Ww4XM4ZBAsF5SjwKo99Y1HpiMB3ojer
e3jAgN96Y4SOVvZfOspieodc6g7t1uUFRDIIiYnIocr7TxUrduTqvOHnCGvCTYwOyFcGx/4ykzkZ
KCttYARdAcOimyyGHJ9E5mR2sdgB/TVqBRB2sR/++HyQaynFZVRuzCRvr0HQHh457JSapdxjOJsQ
wAvsEBVMmwtHTgsmaMma4QNW8zO2qeO79TBdIktU81r82XDO8MNB2uGO3ikFJsM6kxGaak6fvUal
kunIkJpqtOV2K+2D9DIU5OgNbgVXqPJKsNrmUBbEcnSwgW63QlH1yOBe48JVkdg9QK1VDD7SaUx7
PvHVpLXYeYEtQAM8HVwZ9Upd/mN25HOfLH/SFiU4RALqi+Di7SQxme2UBrDjN9lALi5ZpF3rhGHh
szuZaJbgudiqHpkFfP/jqYO1HwxsO9AMKzBkNM3MaBuR+/OC+pM52WOW3P643j5St7JEI00m/uy2
T3hJSYMoXFkXZAdE+BVzXe9nv9xL4cLoLNN+7vCkrD+g10edwFOegJ/ErlVl0G6QetR+tLCGPgSP
ZZQtSfBF1AR5jfBRiNUQuYVWkh30f/hLsq83MIM2K13S/139TMEBx3sOdS+iiPnIgFq8/oh2cfu4
FkV3dBL15aAlb52WKYFYHSDY74vkrleI7N1ImRRZ28l1OHZTddcYgVF3kqkNLFjcpDKFqXN6D5Bk
UbKcGN/eL4sVY2us7W+KH3vGWjf02DPMKYTix1cMLsMFQhVTc+nixwv9Pbp0r38oY/BeOw716uqe
Rb8WTTTpCD6QFwUDLj+0L0OI0eDOKoXmkcxo8hcQTrP68yzzmpYOCPPzMCPIEPRiWtMUTYSpUH0/
AmB7uvSCeS9AbnEkFqpzBdVMvdfebunZ91vKHeHaSpUp+fLUSAVjFalJ7qGJxlS1lWBgTQIWWuaj
PfV97fbguTKeGGlBOLU40U3hu+vJ1tsvdSBb4o86SxQBTFxIM1kiaioZJu6D37pwK3Roip7Er5Yl
m99PoM0vYjLAYiasXWy0r6Zj+f3G6ZYbKoTTFAmtBW7S6vKI3MZaExwVemR4/K6qiWUTsmNF8ILh
TAwz24Y57tTrXsdvYVd9hkabHQtYJ3ACmyHkaDctzmZufkAC87ysMt8hwZKKe8xxqFMBDaZPPEbU
h+449jsIDqeJGnaAA0N4TR5h7fEkNGqHfItWcuQjypi3ZZjcmMk2HkqL2ev3QD+UoJGmZ1cwaAPa
jj+DOPeKMApdeXS3IHDpnS9841u3HbKZmkSC2ZUpPL2pNkLyaOrtlfHp/Bw6YPQK0OmQvy1Tz0aq
QQXWT/7ByJOI/9UFMIalUHZbeMYwZUWM5Tc0KjKEZpchheDUWFYcV5rjWUdhD6e7BVlA3z9Fx77s
bQjt73htlV+rUg0QpP98k13Ojar+Ri0+1ovG4qFHWQmd72ac/zE60PNRR7Qiok/GBvSNcmAbah4i
U7tAzRnL19Z3QQTF17GlGc8TsFN/2Q4LONmVFL02oX+j1c2uaMRX4uEaK1SDrlNTzPB9F20yhDZ0
pEQckoAxpy/1v7qPmzx6GZK1JbXU2kQYYGk0wTI+RRjkRpCyRsH7JkNdPiRCtoLWdSwkU46RENsS
BoGWfh7sC04DAbxN0lequTpo1RjYw+DcistDLv3x+AAR9jbuSp/ymYO+5nW/0ihwIvtLPO8u0q2Y
Smn9dqSBn1s95KgVMYwNiSymmphSd/kseZDGiGi2ZtlsJlaAhlC0hIBv6byRvisanawZD9j81BNi
++PhipprNqSOdTyiCD+7ON5Mgc7FOd31ziCAKMM8Hg090VGpxIi1Z1ITIgH9M3HdmYTl8DSXfoMX
QpbZRXeOsZ5SQb+niFIX0juS6d/qiTruFIsTsDUjq3UzjaSTP5ESA9KOTNC/KsZY3kllmf+DM1SI
vN1/x1FODjthIA4sN2Qi8E1YZDlnikYNrNgZQ7Yis/UYHrXWGgcHHWT8HIWm3ql4UwEFGB6pd+BX
8v8oj0QS7lzgOjbl+3APZ+WVUOfKKS12/+hZz4AnT952RuLnuFaQ/VMrjsScRgfa9g+BkxGiQSHQ
x5Ih+kGtXHeMrGn++7Cura1uiMeG8/bT2onta8Fuxn5RvrE+FGgjJwdU29YW7SkWAwBZ5eZETLWP
a3icJB/VLm8h5WgDQ7TGsr+kSVfuo24Ihgr2GIVTTZaDABDc5WIG0olSpRHMk9ekuYWYLPiPoIB5
ap1+ATtpj5jf9sQRKpn4PYEzSPQ+VNZthYLMA3O8tZjLwjStzGpzyioJrS7kIzg90Cb8o/cKUNWl
BxR3/RoW1TMhwlMxEgvs2lShtHHA3KdS3n8Ufm9k7uF4rhW5tbKLZusOb1vcazC9UIV11VmUBnr8
57WxusyPhT2SGGimRPIo4gUEWtNEqz0Nta0/nmdKahqy6gERuDEvRalk3cvSZSmSzgWM/BrOErX0
LkFB5OYcK7S892i2p9F2J1/aak2WIbmSMpN3jiw67n1gP5VL2AbUE1WuH1u2map2X0zkBk/WPspe
LOYwHzuYoKGwfXXIwovQ6sC4dmplQV5+x4WKKn3nJY7dblEAdRmURWZl2/MbBMYmi4sPEK3SAsZm
8MkqndzgOiDHDmFCMlDco+yGPi7pKAWzVUCoRuf7jId8B8BS/5YIKbkgNHXEzNAewfsLm77sWjsF
A42jCzJAjjzIti8/pTanRelJNLRV4hzoLtMjV0NEaO0qmPsAk3XZ84A5pHnr/5iPCf+vZYOqEZPA
FfGjwmHL5TVTp7FRpYCwd9rUwjpDs/qp+sXU1RvffeIAxF+D6TRnslM1KsQG2Z2uy57JvyXSw8JY
DYDiLIbCLXitGTO+XHEz85lhi8Y0OpbTJI0Y647saGUF6FkS4eTIPdmC3JL8VEquqfLCiyBaUwUZ
3RnMsjHUW3mYhZuIJIYuqudtmQCtppXRaFSPalGrjuo7Hy9zPCxg5k88u0IGgHmjHLcp/fiJTUup
+/Ot+8HF0KDNGiEyecFCx0/XKd0scltuau2IYyNeP5HRK10anAmSsIZkZ7sX/RxDDK+DGvADUbJI
7WQUSn6WNRTFpLhMBIVr4tBqcWWGTo3AIZ2fV3zww8jwFT/BwKRRuPLySbToSgKxHzU/lC3sWksl
61KMLrIQzpTAAZ7MMy6LTsFD+8gWhMe69/qPh2w1ywATDxbeDhGwvOEhAvaJ1DBJ87VT0NfvoYeX
1/vLT5DzVavh/0aCvQY+5RwHLMAOgX34h/Cu3knGtPfyD69ZczmjzpfmFXKHyCbDfwkaqcHv7hWb
SA2gH4qgAU5wSoa4oEk5J6WUnZdI9DAgBoG2ybJ3sYMsn1BJpIPn4I/7FaJEM2mZwS+sqB2iytHr
3pwoBKGTmcwdf9Vcjgkxa4/ldOQWzAmcr5IM9Dhx+qyakMuTH4SNRsslwjE7n7BDjOD0AbbDs9KH
oGOuHNvJEi/8xvS9QE6gVGDPghGCyMjyxdwACIupdxU51W6yQ1ADxW498XsUC38Ek2lQGmHvP+BY
CG/sk67AxoOyn9qV5PgSAGvZAmp8lZFXnbURDlgnJZEkdAr59fSSfe6OMd0VGTurS4mDYgwCovIz
NIyfG8+UgwbkbnavEzrVZAc3zi/N9uKgSUMnEJ34EnKkjfdXIj4fSa3cU8UdXk2CqSNzF7l9BmsD
LesaiX94wuVVMc9x+Ynhg9wOJvf4s0hLUcPOoZnZKaIaYlsC2I+YguyTr2w/+QjFLANw701stB2G
av7GKUiz8l9jgcqBWnYkOKcie1RmrvsM3zzESNJPcdJRXcYHvviS45CrG7RSctONquzuf8kfboIA
uL4kHC2KfqzI7fTCBLd/tZiGhDLlb/dlsS+mKcbEVqei2v8j4xRzTg7zwbQ8OE7zhK+kdTDPlodI
Jo8NUD8ooBSwKCRMBVUZkh2TKvyYilCzobOyOBB2/80A10m+8vUeTHzLsg0kBoGsjGroITpaYsQk
arKkJbt8M7yz8aZaKBCj5x9SKIbALqapEnym56huFMPfmejPGJO9NhiH52iwALAzQ9roZXwzJRD8
MHqhvZ7jE6mMsaPQD2zGzKWfhQ7DFTR86UWB7lmwaBWnNjch+Nn5mkE7k3ILokvcKkEKGXvkQWct
Il/VFKhLmMFYEazWP46jtiFchIy2hdiD/9EYKHzY2AueXln0a0V97+ozQesq0PBgSZC7dTL7ryeF
J5ETbaadE6eYEYBUSZ2SG3LVvQHenzcjuPkViu2zYgJ8l0nCK5sR823dIytUKgTgR/tD2ikaeCb4
YE3TSmAXcKoTsKy6mLOOzXEVCF1APr1ti8bSE32gZPIop7fSA5AhSg4Uww3tEo8cyY0Kdb6c167k
ByyrbCajkMM9Ab6WK2MGGALxltFzRRvWqNd+nhjyAwqcK4rxq5TsySjm9rWiashiWuCgGhrc/DKp
KaHKaNHEkCc/aCrvk/Gtgtx4PkVIq5HGvXWViNa5L+CFyK7ZMh284ApWUuHRZgFi0a7NApJ+36Tj
KkIyo85ZMfpx7G8slkEMs89u/nn7UVfVVOtqws9su8TL7L7f6dLsQsPSYh5xYjFVZQ3wLRjoIJbP
dtQGjoySt6mKrPoIH1OYdS7vyYadr0Ofk57N+pbER/6bOJcviwfwgm1Esen8qXEBER0D2IUjBfti
DnHXZvaLmf+ajJbiaTL8UrRjaIJCUxhAWDoJ+38v++vN+l0rmqguKrUhv7tlCotUig1Ntaa6dQWj
TLYmT/GarGSPTUZ1adTEkOaF47l35DE+m1O5d6zIv3Jd4uGHW/45sDmXVce7+vuaLtoraW7Z5GIj
kdXQK/MSR/1d66AoMVa39DrdF15rfhg48nU2UIRky0m7HK+4dWo2e0NfMXDMZZxz1rzP9dsr5xau
sLANT9sf3bgLFhxw3WEwPYtGYBR+Fq+3nT6uZx556hwrEspaChlyFDJhAKGn4Tx6lL8wr55rFxpV
AULiHrTil3IHPjXl0xRXLFR09QUK4WMwxjA1s2fxGJnXo3VqcDf/tzH+ac2eUq6dfoD1odM2imLe
qeO7WpHpKPB7Zf2ECDtbK7DPt2v72B12ZYE5a5YL6g+6bcTVcmxhJi2N9HOTsD9qGwN0mcTj8aM3
u68rsCI30ap9qpvtQIoPksERWCrLV+O9HYzN0KZzN1IuSuidb6mGVUBYrqvdWvUAcjjs71iio84S
nLYlQBhzWdfW9GGKN8xMHtADmm9E7t1BEJU8I2gW478vUWKchjWqUfwsilLDmuSf0lnIkTEMdbCA
l9KEpnmtQd9mXy3JdALJsdSc1ABgzdu4WsfN5GoZd5FuQsYYJgUOJCF4FGfcv3+iKqYkpozg7wBR
5Qn09XG0c6JNGPI+T8e8rmt+hZ3tIBQf4i2WppGvmU7qb0zEVT/+coqXB4myOiOXpB860YS5vj9C
w0wpl/cRDM5ECdxG1z/wCKM6j0k09R2jmuKvSGPVv370B6EMkiQHfMHHZxq8h0DVvzBcbgmmzreu
fOPWKMFJ/u8Wc6+ZVpf2lWABLkxgL3jYwxCXPHfP+sQdpeeZgdV9lJ6D+ocFGhMRX6PcJ3qYJd4M
GJ821GABOk2hUL2LcJzypSmsbq0+v7cS+JxupxHP87Hg3vkcIHhtXE6Xy+Dw9pjVsesAIsYjJHLE
sKsTRkg3344huXJR77LI91MzkSAir2aaCDuej0zfU73K1HxRS/onUk+VsgJ9ZP87yBKcDj+AWUgF
gJndvHrETGo+fXLNcsD/7ijOvkwo0ACJOPat4tDf10biT5+iGZsAFTRK1RC6dOWO0Ef2h/V8I3ue
UB9k0ET3FrOUZh0hkH/NGovu9nMeN9sAj1PwSp0uadHcd/6b7UthYrXZ1uKcKu4hUqy2i3BG2qB5
zYCF/ZNPFzIX69XNZcFMQxOMTfhFS6y8QgxBeVrdONZKNTovHx8KBS+Aq0wBpk/ZG4m6+0qJuUpT
YPYLs7iBOewzvgm1eZBo8UNRiQOUcr3vvQ5b/8HQn7QlfIulHRcw0/ezE0YCrgKh1TTi1h17fy/Y
RWC0HE6Vre/D+8447JijXgcG81tSk3m2fAOcggMoh6gD598Btn39SZAJYA2csQ5eXpde7hWHJaG7
/kyXGYU3ywfBmymAiDGnXPWFBjuRLbZ87rapFrbU/iYPXeTQVl71X6keFB7HhKYdu135F5yKJtzX
+b3Q9RoMR+6IRAoAxugGbOzHBr4upgD8IbqIchQUhQ3eG0zJh1EtJlsXqMyzRPamiaDsOZL8+q6F
ZeoKkehgFAyovoMscLDYqFWoscDXXqiYfUt7hVLBhYhNDolvDqsucgZcUYbhvcWDeDQ0YkxkWxJA
5p+3g5Lb6tDn1PRJDWxfT8yfsKq+Zww9Q4NUscp9tREtaMKgMWG6okvitvZe5U6tQtWh9v//PTrO
tO4GE4AE8uqsqTor4AavqSSZibFlub5uxLTKk0YEVWqIdNwmqAvAeOKJtD18ClouqYqVZuZ7O0fN
PS9d2pe0NK95mvdw5oNlDp9d+k+TusmCVCBHCUNKtJSt0XNrrcbKzW0WmAI3GDgervZPUDeih+zc
Wj31N5yCXb/ottGkucIUaAAgs4anN4paFJqxgoGY8skvBz1UWJ/aAyFoGg7MYizooWs9Mptvk9Bo
JCfcV9IuB30gqPGQiR8KkSwSwq/RePEFLLRp64Iv3liZIpy+QEosPksHSlNRgWGXqGKUYuVyPv9I
6arD5B/GoUJYogc7YJtZNltARN/AMpFZ4Df25rtBL2+Xey7Ueqgwv4QgaQKe8byUn8gXVl+I91JV
G3l5nQszQQBqJC966YTsryLh7nYoi7n9lMuxcZFhbAr17EEJ7ApxZ7mvC7dhRJk8DELi9P+cIhPY
vZUyY3cCzoeJ78/AuoS7E8DYUyYnFU4m8gF38vnz66+ZJvQXZMmpsOqA3hgO5UwmKS2QAuW7NLrc
6dz1E47L1bYshKAWy7MEZjc3n9Tblz6dUKCN4PVBHROu0rZXTZjQJch9CBweQHBMldWABrZKLtnE
9A6IE+vGZ1QxrhIenGg5Dilx0oPsUpGQmNCm4aH1rYYAzHM8NdoRYHr+q6944RJAkSksA49lbKT4
mZ747GvkJaTVEu4/+0Q9bXlqO1GVC5enW+8FPAiMT3GtrV+eJHWIpd19o9tTpedpPj+OR7riBdn0
8hbRMU7nyInUWpl5OyAiyNItw739aHFuklz6RHYYMuz4vH+TlxSIMAOCVDCfysw8bxhkuTuvLdCc
7nVpObwZd/hCs2C/ta4s1oo0q2fQ9580tKBs2LSb88gYUD4u0MQBcq3PfOt3z8/4rPra2KauIykZ
p9eVhFm6VWYyMgZf/G7YH5u8btQdRiSeFaRoZAwMGCx7hQBxOm7MeypO0IHy5nuALqQplHGgkCdP
foht0UALNPAAVMuuNDWmdA0JiMGIrfTHtQo7t3NbJ0c0L0YnljRzbcvSJZDy3l38uUuuxowZRt24
S0M/4h0ikRacbh3ulgEcmuu6zrsYtGV5OsAnZP3BfEo2SgZl9ffKnNnjgCsCS05337xVqCSN6JLr
Wf8mdWWZZhnWdHfsNZ20uaQAquMjlO75bttf8OsDOgLRFunMD9UA1QdLEBkckgkOo1fK/Db071Yd
ih5ucMVHVX8dqnJRu9DEXnQydXJitqLK0X9mBD6OmTiDiO1IQYwVXFhCT6aNRGa5LAJxEoquLHi2
M34Lp0l2wffwVPLR4Yc15JYndBDRVaqo4j950RfhEwbvrdcN2zdZrAmuNLOEY/owjUWX0Ts48bfr
W62sgv8izbhnk6GHkXF8r3edBhl+9kq+Squy87Mt6TMqa1MMf+JuB6ivS88MmWIETdzBI1BYEtsy
eGDVaNSzAeQS08z2bxx6L7U2yX0KJx2GFtIs1ZWlbLAHgSeIMNg/OMQbVbx3V86hkPdEDCcvgh7t
KvDhIkb1UxLt+gNlWQjG854wq2Ql+A4RU3KyX3no689m3UqwDm84as0DBe6Ha4Dpe4nOpceQHrHG
JAATQblejryd0lWycBFOO/ofXBEvPW5BZXD12nvXN/a+urJjhfj4Qb+kdOshzWZBP/Ia7dO599gw
Xf7Lvh+WwHcfscvxPMmNUke2utOTuUwo7qUmCMtN6pAbs+4y6vKjNoPareZsngSHvypOw5niGIzk
0Pf+wZxWb4TicK3xFSZ4KDRuDpKqcUvGvyeM79yTIhciZJ8T1uU7N3IwykedxAtWJPX+2+37V8H/
kdEtrSihsAsVSisyfHdJZgz96/ZHAXXHeSWon6Qt8BMWKyQBOAYcYlhApwFFO0DSJTgTTnaXHdYV
5ywZ4n0B12jH0HYqOEQcJZNuJ2UcmMo+zQDw1YHexBOlIXpnJFkT6bTS/lVuc9jPbbbimSYj92Ie
672S/eSBA4V1QWOaSC/E49WPCOFstHgF1u/Lu/GNdxcDxo+mPIT2q96mgKWdBDt4wOcAldnmvKtP
f2FOBYuGEoaLTOqT4is13wztaqNWPL6xahmcayMbDftTEjE1bhQAlhVUEx7EsU4X85OLx0m6NGKQ
/GfFcWG9rzFB/lV8RhTGE87fNc+fXDNO9UHipbVqEEv2QiKIHdvoZ8fEE9s65LyfUHHGcKwS0B8Z
VItDX67L1cId3SEURVSHBf9LqbF1fL/FDXbFK7vZ3RlfVjXSbCNevQSlB7sfNZYAC3DdNZ494koR
vV7R4bmuAETu8ypGiAoONVCX5/zCRpxs6Pp4QGJtRJiIBtMM4cog16+BjYXC+gve2eDPurmFZjdr
9KK/ROCxDdqU+idQhvxMCUKUq4DxFB1v/FmtJZoqBhbGWJRiRRtlKyHpLRMUhzCNroBjX8YL6cQ9
nNEHceiPxcTh79UENm922INL2Q7AR9+b6NQrqi/VEXX9Y4zaAO2rGDyGMXT7tZIBro3O27y8xINb
4XPUESfqAwa6b7bmQrfFQ1OaL697O/1O+x2YRdIp3Rt4eFQ+gwaPwRaC1TTxtlWiRkE1TEq/1Jry
OKhN0TAxphX1XavFuXrYWRIV7jewKLKvqkW8O7oy5Q9kY3ym/MYfe4MyLxYQSxG/JmD+8XfEfw9P
t6CZht1yDDHTiQDmcqyErIuypXHJnP+cktsVXMFAbzj5VZvguQWRfHOXs1xF5Huw86hsTAwbsRR0
Gahmtc433eee2C3LbJwyzyKp9XeIfg37Nq8Phkp4k7dWCk51Izuy1wM8NNeuyjDhtyUegZYYVu5x
1gayqXwVj+XdmRXR6c8xQuGUjaGX/eR7thhxXH5IWrMjGQtJDSxkmYSzPnF9JbTDMpOWBqMxBFO9
xsM01Uy7ctvDkWiBaQE3DXg1ZlI8USA+5+0KScFfIaCVumMLMCmOAwvZVCGSU1MJO5uRE3tAH3c2
HDFQ4a8/AMJCDzvVLsgTnqmJSYwH+zl1Jw6u7/ikWc6uPJhwDDN3w1kYARI+C55zhFX/oPvenqDR
UaMQd+9L76XcGhBpREQqZnWTXPluF6RwmsDIhIlkxP/3T1F32QfzOEhbPiP4b0sdaOwN2cdtNn0+
/WGC64j7wOK1W9PB9YWJ2hwoxN/xdzaU9DD/qJNLwupZZQ+KrsA7OcNcnCQxkqd4vhUw0RX/gBCU
pQETIrVHVpAlprHSBwxJV0C067i1LqaGU3FxTN7sCdg7xYCEJOQcnjMvJhSWcggW6lR0m/SnfE4f
w5OmR0kCTUYf5sMjrB3sK/7InHF9+nXyvgwlminE87cgsxC2GaaFAENwRoWdrD2QL0sH8ghBoIw2
zbphOsCMNOeq6Dl1aDGljkBamrYQNq87IYr2Z18wITuYlKH0kSw46FT5KJSUONJ8f4g66iBwpZui
HvbdRm+MNPnApkiNmw7nnjtVKII/ZuWM4mc32/pSO34uv45b8HEBmYt6zroKEWuB6bc2H7VGgT9D
uI0TYtN9iFxA5vit5SXyGOyCyfRoavoG9/mDEbzvF2Z+8P7roCl2ekimpe+yDoeTn3hOKQOmIyhw
7KT9yO6ZlTQNabFSl5kURf4xuiYDJdZgBeXhEgb7ULe3iglah9KaxYVLbCKtCSx68vriwmnShWXj
Ki66TNS+SPutLLjAqbRqJUHYnwC9UmscwO/yM4WvtHNDcPB7Xeu76/UJ+CHVD+HA7z0XIA7E7aWg
FrMNur1LZLjGLCqti1VRh7JHQwhT2vajcfcAbaqeUg0fPH/zjcPhhsKOtuLq3Y9ifHAEZL3C8YII
YBoKeUMC/6lQRacr85L/CXqUEs8AbKn2JMSklR6U6jtZUp2ggxEHT3adPn9Asw+V2TRYkGWYHvWW
1UpAyLgtsPRwNCUmNexFrMHmN1Bg2A4i/mldc6Xk6ocMiigEKWZa575PY4LsCWm5Puu4S75e4Dd1
r6/lGp2aQE8c6PlTQ4oRdBrphKMfPH3Vqwbzbv5dG+gkk7y78vhYLJvi00e3W1E7aNCUeFJ4HWWM
RntyN6/3CQ7mJOvZTbqFxUO/UZ7pM2Gk5/8FdabZ+m1C3mzpcB4bkCWlAhv6Ypo48n8mRO9APq9p
hjIcF1CFYg8M9lTvIz+qUSIrTulBeOMdJycwqQH69KzpehnzQvqqzmcXjcIjpbCtZeA/oWRH4dGQ
DL7LZjKbd2vX73qHkKnxC/khQRLjAp2ejLMfx2uEMLCEk55dcu0ikf/Lka9+0seKNSMDyBf49jDj
ecMkU3lzkKjQCardd1PBCtPFPMTuNovFWXTU2q5D7BquLFZHwllVgGvu07n7bfUwhNMEEHynIn+b
oUxWjlN/XVF/zV7UKAmn+0PJMUZG0UHGHSBtI2jxq8tFjooggNNhWVlt8nHz7uB2BseKb5ACQwYg
NEwccou+KOJz6QvQsgd2xAE5MUQHfDkGt43f1LRkUd3eIaxforalsk+vspqAmogpFRdCs73c/0to
Xh2ZY0/pjQniFpplQHjXqWlnQjRwdkDupZlQRWy9ZLTJAEUK92Ia/JttbsJYum4PFNyvjSjrWtKb
kI/0AQP7J8eUnOJVpDvxqxRFIvNuvenHgJJj/AfpD5XucsjXQ+9d+IY7WGgfwsB6iBOCydTUXo8t
SZfANOW1a/+0sWzKQoQdbNHzQlVT1W0CtdtJ5BluAFghfi4fnKCLX5fWvTJC7CIe2lwYkHd+sR3Z
G9H+SloQRgrSA6TiUG+tUToxm+rI4CTUIjIQdgC/xHly81yIwga7pv7S5WvWboLNGbFKdYshknv/
Sy/yRXLAiDgUYgnzaOvW7PU3bA3El+7T/ZlfHhk+IYDBS0W+55+64har8Z2cFUxbgpvN/HDwY3bP
/gCgvMtdqUHjLr9GGyAE4uFrGsxUkPc/5EVk/7rZMsehx3RhaUD2j1F6IumjmrRmJcONQV8QEGLF
3X/1wvJZLhxRav0guRq8ep6ZrUveKygkE2Q6mWlwu/WkVpSfykOmNricYXLpsI9cDJPPsjqNAaEH
CqyfMfFSSi5vir7DG6a2egDhswLT4TGasDcA22b6oa9YHp1LYCKeYltGbfP48DoRXzz58XOvPh7O
OIoYWJTlfjwwvSa4Vpa7EQdrDC/55ZJiJz7gA9tOD2/+Setu0DUfPEOaNy9lLtKPS0MS2ES2Cxpf
58NzioJ0jKqQX9RQiv2PUWnOPE+xE+tWQnZfRCndgQ3uEorUmo4HsY8iBd/Yj/OKnbame7aewP8Q
NvAje2NkCdpOrdBiCJDR0d226bc34f0lHufNou3k9iHymvL7jXArzblE7TRcWyA/dt8Qv6vG2WkA
FhInf2vQDrdq0QdAtXrJBq7bxH+TBslBWpYpz7vaV5ebjmf/ETzaMiNhk5vahy0Px4ltGytCqN+l
lrZdBshNSiWI21quBJvRhv/ruZcSj2OyIuf7tnAuHb77BsqUYjGVbu1KMzyeaUXg7iNVXOS3ycgg
2uUhITkpNkttQNpAKKNN11blLVfKcZESUiUdJNFdap2sCu36NZUUcbwr6aU/WO7GjNVH7V/j0OYN
E/VvdyI5A3mDYauA9FrffrxcR8qlvzsnMGTKPvSoyGvgccwQS7Q8U3jPun2J3iS09XXQWpL32Zn2
0NaQOu3S1L2hgD6j8Qf8zyOzqGkfiGtFidxliViHVB0S0s3uZS5xYuT+xp/mzSxjzO89ZFD59Pfx
E2tEsXsrgvW9vwHKKIZuVNwPXDwM+Jv4j8+jZnliJts7KVMi73dRsOYMD4A2NmojD0HZtj4/3LkR
4B7scoq+4HqVBHR1BvpPgKEav3O34gg2qSOQe6fGTiEvNzFZpgI6FxHQ+Vd46C8tjmlOjBLxGWww
6984jjG3BaTHyTXmeV/9hJ2VDZOyzF+3UV0CxwiD8ql1CXpH2BbIuRW/j23B7IhghZrZ2wold9Ow
HGu9k4NNOCQyO5okX/hGdfyvNFYyKndyfY9fVbNl+g8sl/7uhf5g3MrMuiK9o4aERxBVBJm1IwrU
Sz8ats4blcn1GATcmukmjEM7mhykscjVlpOtt0YAHcolofClilVyiRwkYQP5uQIfKliBwOCuWa1a
/veNFuoft6qLz60Q49vcwGR2U5Ah8FgXKZOu0lrZmTsjidTiVP1mXW9uY3QAHX2QRXUo/WF3LeKb
lIvr8nxgHHDftaPorZdVUP/u7+c4LHf35c/YRWMKDaOXgrLY7N+ORZcl3oHqWMYDK/JmO5CnMDh3
FIpN9VbyxxES3rnQ6lCkz7NRHsnngkkhDHA7Ws8h2o0QKh9OD+Dp72+RC7iEKALhOEWTHlzHwcmE
gKU9+kFG7LE6a6SGmLLWRrsGBoAZe5ol9i65G2DfHReMkPqKlQSgAaVvyDSy1Foob1fCY5X/KuXz
eSZfwDSmR/xcWkCRZ8dKJY4SFJbAlffda6994rDRq17voQFQreKvFEpPMLFKvnhNU7wT8PL1Xyhf
rQazoI8jegU0/omzna4YBYTDPsraX2cljfbw+sbTrkyWpy8ndiYMu3vcWxilFdPXakrUEHsgEgO4
wRubXaGdkMkslGl4m3yntT540X5Wqt6X5g4LrYTEm1uXH2u2cgLtAHFz9ha9Nf0U3E8Cti9ZcO6k
ElzhfBEtfnBBDkJskPixfxJBcbXVgwrrwOTZsPXONcTlmAEBVlvh6GeUsaWsSLv7LohsuwKc+Fai
JeabUcbkvJomXnD72ZmQphEymHyKm2u9kCzyMgnpTy840MqQO0CJPGylRQX58FCwERLXkC52qDR5
gk2TVEt/lDYRbLCvZGPFC+qG+mER2FWH99CUF/sVUImx2HWGFXJIBIWbHIipUxR5IuylAvd8UT7E
F/jkEcvUTus/9sKfUCk4Um/XFUUcQOzTuF5qOdhkNSpFDTn7ciKY8mIW/ew4if0HLVAZv9aBDBD3
uVq4TAPqVScVvUScnXR6JL2RjjVKTjXFGUKOV7wzvd3gZ0GmOhDaIq7xkH0U9FrAXF529F3kScEe
MgqRJ4vhs235QDK/tp2VB9/w376pq1jDY4o7zK6NYzbSIkLcDyMERZo8B5Mytmokh9liy9dySxr9
wxrYMVesmHNDsmjc6Ctzb1ya7JEuG/3qfo2lWaqB5cQITLWPvmTvu5tlDy6CTMmJbSkqM+7Qokt4
gF4vgDTugtClowf6EbMOVyPTZ3bkXhQ+WhSLjczbNZICE8o10UTApiBkrFlHbflvJL0zWrmZRcM1
Vd7KZMaY6JI5NWc7DuUX+x9db4t9pvlFUZ+jBFl1BCNYUDtv5RszaJkIK69ZVNKg0XV/e/tOEiyH
vpHNnMpyJI+QDbqDb+0l9z6SVPcNmkpiskUMHXT1VsOERJmkCltJHTdcch0W0unVOwRuEB3AjOMN
6s8f1D7wNZ4k+bNuw8DXKTn6U7jdgU8VIxQX6ytjeD4nHtra7LNSNQrdksx/D51vj8m37CsiqhJX
KZAO/Mj9jB4pmcXBY/yqqrbeymA7ZS1863PVKc/xnjT9BWtW68wpRN9iyG0EDF1Jnd+L/FKLOaSp
gBJ67UVB+EOxEsTCIUHuiKizRNXiw1pSNIitUA9yxT0DldgGJouNoq47TKpRc6YG4CxRBmQ3W4HV
ZpveCLRc8nPjzc88WiVEzmKSykyF8YL9YHXx8pcKv5v3Ce5VqgU4dbd+/pkapG0o4ZRP8YZ4Xi+h
Xkjl8GzxWFRE0tfcFuMzUmAJ9HJXVpGqqnMy4ZtIO0r+vcB0N6+z4FKPtUCpCcG3P5C/w8g8XIH6
K7tmKjaSpdWIc+bSP7BlPsYsX0aVQQam2DO+gYitEnDEGfd/96TgjMx+M9MGTy+VQoBieJoPC/hR
QHBRZEj2eETsMH1vgXG5pz3TY81eufkeXHalOuzCf6bb2ABLFHNv3UNWQDDkKPZ5SPofcK7WaFOA
i80yc82k7i/CK9lue4ibtddiLF7P5LzaDSfx8rirUNh+soIv9q4fJ4WYJJIAkAwXmENpvD5j+L9o
yBCpduGVhF/KFtx5zLBAxcV6mtCkEqOZGlCWTae98cJY9Q5ONRHUHW/83Td5/Thn4UgrdxOC4X26
h34kyY82PkktBSAFw7LyQr9MZ5okDAwY0e3LqT3qXW8bV1lf8/lJxCraCtL7xD+Bzgau3zS2iu5n
CoWA1ja+c8cIIt5KjjO2QFbVUXzhtbg9uQ5rfCUzy1Y3GXmkIziko6zDGXP8wAt9Z/RUD2EQMuRt
qKvG82G0SdHraiBCCqKg7jI7X9sOGNVI2tXTXVBiimuLx2s0TsdTUsPcvz/YaYktob8lh75yLhUg
TlIMYINrWYw8Ee8BMMl2tW2TTkA9RigpMpC2ln14Xc5GyQ75p9mu0wG+A2Jkv1q5Q/6bhCrbbfb3
X/F2kda5+zUKF9CF8W1Ovdd1voLuJTIUZyJCspDC+GD1zr9H8qGFF2kSP0rKsvq8DPH1ZqGXVt+G
iYjJjlr/UBGG6Xe2LY9PAqPb71jo7BUAmovGPbZlSFt59T5DfoffvwmZbd9EM2Q1J7Bo23xdwhVV
HiFArBBK3gMTa/QTSCyMRnx4pCteogWwavFBxm9mz+2/6LDEbnfCifpQcBB20IMpOl3TXXI/kDUq
jJU8sc29/lgSOs+JpC+Q3d0im/fiqPcORhBu067kkg+5vVSVd3WV9Xdgp1Tl4oQwJKvVyEImU4Jd
nRRuH2XMkyYao1CGx/D4h9pavm3ZxsuzFniUZL3w4nrJNvIxgMgMXPfDERn7BKKgGyX2oh2jdaY+
wq0KDkWNUF5VzFp5t1q/kYuJXOpJcI283wfjBiH6/AMmWFkyguqI3YMUfgJGEm/EnkeiyM1afVmW
K53FYYzOGICHoWeZHyIO9qLDsG0A0izHG2knrgsDBwBEmS+VF+lJSn2YCvMGMCJHy60J0h14rC6B
5bUhOByVB6TEmG0gCSFSG72i2C8DB57ABtAWLuV1iky+VB4hkPG3HX3WYYy0GIXdqbTn6BvcpUEQ
jCWyIlvO5TXkYIebO3iMMva8NvPeR6Tk57F5zcNFMa9w/YLbRXve2VVkHeTyVKPshPMU4/88mq9J
QKD410nbSnOsy+4dxjev7SYZPpShRd3vClTLyv1nFfpuDI8CqirotNcuYWwu09hcHgAhacNou6TX
zFfxm2ttnn1p7qINAWUOIbkUIy9vzXCvS4cvDTyTnTJM9jjDYjemYwOv+1Rnx8j38yyBuV8ALqNe
2Ef/YLZxIxJckCUEyUPPI3Gt2mXhHE7E0cQW2l8aCx9L6RQiBFArf5YltoNCEeTtpCEsVYyXNyEp
3lNN5cVjdP0tgjeh5SvSFO4btJetqWvWer42dKmnh9dkLTi/Y+Vh7gENYw3oJ0lGN1ijTYq/o1Ak
VO38jhWWR9Qwar+zICLYMRa+JNvdf10WJLBWh8WtmPMEhepAimuLJ+na/o/OZVT2axrWE5eBiAnW
JEAPPrDMTxKZ621G4hMbXCMikixuLBffOgjaTvufBtbt1GKzY4a+vCWhCBrh9AMap37MuL4It+sb
L2IpPVH93VugUQ5eP+/UDQ2/2xwSpKqefbnuO08mAPmXiHfKf/ekYktJwbWG8M5AAMMR6ID4sYSn
phuryf3wIt8gkmQzLlHbDlG8a40/NuLNjbeW5pTeoX3xVkHHTRddbFJUscAm9/R3ghfZRmlxXpdM
IHHj9zeoS0gk5ECIeJmbBLYDIaPnqQuqOQryycv5JyZj9SBg5S5q8aJc9Vjx/jCRomXTobUUUPLr
2CSI8KNiu/4g1fbtBK+Ulphhm0mv159UkNg5oFoE3Z4WAygXHzd/S8tBvyJZo59M2JHLDXzHmQRd
8x+RiWrCsuho3cVRAEPYjb8lVva9FIF6H1Q3TjIdvrAf38RcT6jvUGWpXGZPHsq9QAdoNCiP5Inl
uUu1EDMKOhrZbKk7V+qiYGIwZ9bAzcbhbUIK0Y6JClZL786WbtpW7Oh90wm9XGRnGwMSom6IKXmR
IZYHBqGbQcPNc0fZP04beQBKFI23dPUK/AUVbuVaAH/IimqKiP3NZw3NKqMWAUoWZd2Pgn6jBAGL
6MBcaYrMQihfTLxTEZ+AE0nJZcDbrPPzAu7IHNPaTiQ/SrJk8tG/9WN4iT3YQNAPFzC6+xtWWB6C
t8vxJX4CiqWkPia8iJoKHR/F4rm/yqQE8ZtF9D9UWrQKH3ViSZ3fU5vXrpuPDa94SfgLadW3KdlO
rvIuXUvslyfbeduRDOpmwRu1/D/XQb+gWimBcgCuEV4PeVzOi76M4bUQlPBOoT31a5wPlARhhz0B
9x6E0bTvgGcyxb30+2ozwulwNsg630sMGx6bws2Wcep5AUKGAzMPWraNZwvUtiiKi10v0YmaASse
zuwQT/WCiSUK7kr++E5fT6i/c9kwI/fNCElxHIIhbotq/u8QDFApuKVw+NgPYeIHGnN2dINou4LS
t8uXBR1vNDFSYajctTQLluaJSNb87sEIJ87hjCGw8DGi4jMHyjwNxT/LuXZKNQ9aBVuj4BN7QGEJ
CgzbYoZ2Fc3aBmSgX6jz7GlZfwWdSQB5F6yDo3gvs+8vF3TqiMxZTFw/BPz8bKEsV3G5/Dc1hCIy
Qga/gssEkgDgoZ7pnIxrQ0HPMukC0lYRHFie131J/vMKulIEVF0GrvY39oant3OQfUJ6wpKbZ7am
SUNAPH6oJUEqQQWEnXxKpwCGusYAMPUzk1qBq6hOM4ZUPcNIkma65uchvxIWqdPo0ySlbw2NLLnq
ynFZxU4cmi4pzvHoePy88u8JlVJ+49MzUkxAsXUf3LXxIubtX/B7qU0eq9akxACzOJ5yeksTVEZ2
zFHEMlzXXeweUnEWeHIa1hj49a6isU/I+Kz7k3sZKws7hL4LzjBgi83ugLa56eNHd2PLiTgRAqZI
3Jceq8UbGdRUKFIEU/UXa3VPXy9q+3ZUABgvFj28KZk4DnFQBDoBM1lNdQK9/J3RVCj3/SdF84WL
vYodFAXprjm4qdPvGcdyxkad7BiScD/zLdc/8pxf4NV5zvDtxpXRqtIDDUMcgtFVFiiOvGX1Wa2y
f16Y69hUt3KJd+eICm7TfQdSYEfJG6642/BY4AU0jtWHGYEk7aZZ4kkAYggsbHpU+jErDhyPVeug
wm9Aw+tzDvFaghruxpniodJLov6UqshdbHXmy4EH90uE/3TS2ux5ZrqBstCedSWSDSyPJqVeYsmW
fuyXdGW+F8fxl/ecxny9mhjzOw2xB+0mH0aIJYbuBPkZr5ugV5UI/dkLNWpyTik1nIS50pdg1xx3
4/BNRhh/y3oFYBoReXVUal1K+Olttvk3nNJjwE2504tzJOIl968gmudlZS9RMphcGLxu1XxcwH6D
ktEMLrGo5O3ATpM6z6XxPwX/YCgEWkwbFyJXpyhj5SDkG0BlDmzvDsQ6v+jcDk7DjegbUnpLhzp/
z5eamPXSDaC63En/jaV+TUz79BIGOXjcXj4KJOjt4DqsTF5w0TUNTpNc90tLBY7rn9oyXsxOT8di
1Kbs3Wx/ji+3kv4kyG50Dczmkwk0Xxtlch0TiKHRctUpW1scCWGtCQ5IhbBr2irLJTDUv6Fow8qa
/HLK0CtAumFInwT/ScEiGvWNf7JWnKuuRINmg1Enh7f0xsGr4T66A5LRfzUIBVTdbU+cfwnsUd+M
wOMNRyuc4l0n8mJGBRfcuqVvmDMmaXuYTzAi0P6+wHI7Hn9uSuO6ppWjgcpTro0JW6VqCo9cVQvZ
bhEpauoLcPBzt/OjukcZEH2+sDdDdiJTAkdI9G3QEUnLWaBn+Sz8nPezohrlaoGHsxEgWsIsKm7y
uWOliPA6upDOp77ApOcF1tYOWI4al3g8eNNB/j+2mqwVTSWDJKhZ2V6B8pDOEIh1rTECTOq85pJJ
hZOdSqP1hvpaIVXC2Zc4bA1V3Z6aRlMNaba1MDE48JsnsHwYj7D6ihqyQLR9W9rHeku40I4LNDv8
i2z3xtG3oOcO6Nd9jMkYEb0+fAJy3lHmTZmZHHUJsacuKddS1fZlX0m/0hKx6o3deUYIWCwDMd2l
+X41wMGpMlmCdDt6ErORbR6TVIwsibJSKf0DlLOqJlLVgpuXGBVU64ULjkmqbx1W0K4VAkwaVmYc
aQ7dfhq2MxLYyRwE5ulokMRA4y3FQZNqRRW7WO7NyhT9ENd4isbe1hAdDFpXu0IicA8viBXRmnYV
/X6F2MLgoZwFglmDQjjDAHk6JGYTOlBVBxSXXLv5QkuLDVvcs5LuUqxTfYMnYizjFhBashuVaZwe
b4aOAQo1kcgoohucMDURgtCZt/+da+CUR64D/xWjAqDz0aAn4EN5OCY6Gco4Gzv9/jRj+2gWrPbD
AWtejPpUT2kExAgolKc8uCulY+u0u1dfCU9x7apZtOkPAKcA5uxzyNu+BfhHTTEkJLEroD1rbdPr
neIMz+lLrPHBDVf9h9dc80WvEbrOIjw4Irp+R+X43IYQANeEETvUkBDxHSOFpRHskH18fN4XXdkn
013X/DLBMkgH8c87i3W0d3fmEKX4IVO2wGn7E8ZIEjx6eLwt3d/JUA2FHm0/rX/+jaf+NpwNTZvn
BuhaHT38tMeRMv7UiYhwqhwgwd1R8VrAaq7ZWv+dYOmdwRqy7toXrH6ZH7FgG03f3+EQ9MSDfltp
NPCs+Ua0z1FfG2yFagZiHI4DHYpwO1eVwgSdeyj8rUOiCatBQXX5hdTgO0g01aBjLbRt8YN9o0lj
f4UVCW8jbrVh52B6ZD9zptJHcg3iMzpzDZcJXO0dmrU1/84n7HfX2vGNl5dyQVsA9oKb9KHmRx5V
GL0YqwqxroL4Je99LGejkTIyMuaZdZhwcateLqFrLUXqiCyiY5KhUdFzfSBBp9MTSepVEzhB71xF
O7WCmWEXHw7Vl3rG7rwRwKsVT53F98ffRXojr8DfE3Dy5AWTLG1+yaFEujp0z0pL7GG6eol3Yfrh
czLZb2Dd02KK41QJo+R71o+dTcr3U8wpaiXE7sgfPnieIQxbojaGp/asrvAlYIaaPfFIPjxDoUyD
3g7OFuR9ZWAyzybNJaSMLIeVnsqi1/gC03mAIYLMKytw+EbYciFhKk3opsRrP3dweGD9cgapOZoz
B/qgiio3Kb+31kF+A/Dt2s4kMlkHxHyHEfJ2Nj3smfbgxKmzt8AQoRXFnSPij8Pxetu4LwKgBLkP
mg0iIjSEZaKzxuqFh5D1sPTf3LQQARmc+s6ZgvWd1uS3FH0TddlQJ/LE44lRsPc3cSZONr29PHQd
Zh3IfU7uDeDDfVoGy1XLnfkjVgE9vgAKyvNFMf53j8rLm9+tbjM5rUDdRZQyORZZWAvwBatfQRuo
WuTGnTxsl/bL+V5mlUG0No5HFTLX1fpL6/K569C2dHExVfNG69MTgxRmp3iB6JlnwLNZJ4qcSm/J
4EUgPixuV/jOQqUTooHPydq33FsqmRxTa8mfpWgXwwYgrEcvMwi4mFrDWpWhQPV8Nj0vBjWlTiZL
NzAvnnfO6vLqnCZTlH5Ta+EJzu9zvpiDGcMnT8RNgLY0VhWJ722fnL6QicA7dl9zBB+axAR5txWh
HTQ3YbGjrluUdtWEV0eI5FIrkL6Kuia/lgga6xvd5Pq6aKMH6aT/TcM0bFONpSWYdPY1V66iSnFR
tt5/N1p8Nr3PpKkwMfhl1498H92gCPcUmzL8BXjk7RCQgyfAZx7TLnNNAHeK3oDdQGBzIQ3+PGkV
62RCwncAefmy5+PN0qoSmLdGNtZS2o8atc8UswLFWcF5ZU5WtFITG4t611p10TumfU5ztZ5toB91
O4KZeKqlHiEQ/D0AxundQFn1js43vXm3y5QrYuH+xW1ywjsupjhgtFR2C+aderKS85LHymbow0tD
brozpTJQNlrvTusvmqV1rC22FbVo+SpPRBM5I+l1iYQmfKnps3+ezZze6FcyfG7vHTmHUhqGy2Zu
CUHJND9vPP5de0jpeZP5dpOQWiDKvh2cnpfkyRV4jm+I5Mrf4INbLGW5CfhYSZRyQ9GqJ6t89h8T
47drA8+Fwo3pxft1ZOzhMQP6XVL0TArYA1NH4WYXS+jeYE9RlkeOoGB9t8LJvfQsUY0AVYTO4YVf
D5zzy/W/ap+YuXuEpZk6O7bZLmhVluDm+F9duvg+ettpptp0YRIm6Vhqo8GandBp84DFa/v2s7fW
SnvB8qFYDhoT4EC1fUswo5rx29A1KVCtPHeUQKJ3DbqpBI/UJlm1d2MCN2yZb3532VGueGfWRS2z
hfxTU6PTvngH298HOQXNbH4Z4lAdMfk94IqUTQU7WvqlOiPRLKZyY8Q1e8Q+g7fM6OwyO5iEdRFd
OqlmDE8q4lt+oBtd2xnSwkHWwhZv1ThYPNpocIjPWVTp63k60cCO0FYcPdh6aIAbyk02zoAZfx0P
9qz/72pmFM/sauy4ywAFE5GM/zu3xrzx2fmQH/O8UuEXcZB+0qjj9BJf99qj/Cl2QuoxyP9Fdu6D
ayWZD2xCpN3Pz+KExEI1z1RAL2fVsFkbUgV1Joz3aOig4AY9Gu3jnI/a8q2uoXlh62L2Q8sv7Qf5
AN2LdF2ZAlDFPMHrMw0xCFiQsdtCOkCluwPsX2ZMeZQlx6K1z6fLy2V4aF0o3mXUrkDMONoeX7qc
+gBRkdoS7xrO0p5VoT/71APdA8Vc4jXDSNj/XlcytmM73Xb/pms56FOUe5XjhdlrWr6lV9BDmtvT
ap+bBDMojEbQa0vokWt9oJPz4viO3AM8IIiZf0JefI+zrqjdm1/NRbXbS4CdMUPrrGyeWiZ1wQAc
PtsBY5FBmV0ixFgPHQXQWfxsmu3P/wdM3gmm5d+xrNrZNwipnVIu+ZRgTrL9RzADR0t+7E6Cuc35
g+ufnfjVcCjlnAq61Ecds2rhbkCq3nsEonb8O3bfJBwj88Eoo/8fOosYqn89fUS1JhjdgCoV1ceH
9V5UocwZObTvubzNfCp/jpEmqSWcqHYDOvIHjE5JsAGWtBr1/01Xh/arb9cQMNrbPjQWAumyTJSp
TZUifKWipN8Tx5Fovxodo0PZkGO5Dj6Avw9C90iPQDJxA3hAzjc9qMNGJtU66auf46X9A0cEVmyV
D/ySh4KXBRoc7QhuGrGkBLDnRlHP4tPHN+aNZ6Gn/oL8FfnDbCkaGqnS2hhPkssshJoSUar2bOZ9
PIvtqx2s/SaG1oUQGBbd2KozSxCDjBxI6Zg2JH/05Taq5Qr877LPPrajb7wf0bZ4hhEPqK44Cwx6
NIkab17NkCPnMY5RL0t4vSv1j2Ae12S773nzA4Isa1UZA0BL+OrMMsYVINro5IdjgTunDWbXTxsK
49k5WASqe1YjyOyYoTz2meQZZJgdH03z9aQ0sgdOiL6Z7mY1wbrSTj3cF6CDfMndvsiBPmiaw73K
nlEsRDHABsAzu6VCsWXhjw6H72L6KxdEGfJzxiUpJtVJ9S/AAifLZAv6aTRsasJi9DL2zjHLZPQ3
sRltlavoIMxGl7/yFsF60kz4kIrLTFyb+EBnA6XR1AKjrKr8i4FHDCd3t6FbmAdobag+dPvXGn+p
RE7HTXcGMTxObcFnVOdgJ5auMnYRSLmexqOKJ4uKAo26Bpo/A64+8XKPJ/YA/l1Su1HXpxnUJGpu
/oXbdpKDUbjNNIEIJ1DqMVMHyQ/wrt/24AeR+e32szG0eb1/Cv58jIkay88T8wV+GRuLg0UWwqB8
9XiNEMwX5/JTl1CnscnuddlXnY28WjsQ3FMKVSKL+YkOVpdXc+BQvO02WamRpA/rvRrYJZAZN6mI
UqWvvojE4Lka0U5XTHsFeay4pxUtW/GeLmS8su0hHhUnHSgLawdtPDC8QKiQsWdnuPLW0jbn1YrY
ynEqyBHgR9xV+zVxQXLmnl5pv3k7svydSlB+KVGoNGMCA7PRTQJ0288gP99kBRNVkdXKpPXPL8m5
4I09h3ZOzZPaVZqGn1TTlSDNbgsdBUd9WNKmOWU6lD7pwMY8mqQwx7jia3xWxT+5RWky1C4LC/F3
QUn0we2KZcojRpZ4KrPhBZCYtuzmb9vs5kHkY2gT7xB5tV9xxhl3Egbt080ZzSJcKUfvOG8kcoL/
58jewTF/xfGLhYDovRhTmGhX/WHDL5q8VEoNGG5vbQ7/2C8KO5/ZY10cIVL3ppfo8DPKORDP0dai
NuIuHGnLFiS30H81/l/oSAlKzbKO+Y/ha4I2xBBRwv8fFCWRuW1YwWyeg0HNTKFuSaWTe9oqGhsF
hsAQ/LAdr5tCsB3qt6dAzCCgWoVrS01CGV0QMvZcwdU9f/BZkc7Qr+4EydNgdcu31LpajyTPLfjC
iDNrdnIxvD5wtFhZHc20JqQ21r+tPFYvjG/7o8kqlpMfYGz0SJCOV0a3wdoZzhtJwqVts7SPoehV
bap14npBcakCDo/COktX4YjAfx8ix1P+8uQwYZXRJ5viNoB3K03vmxZZcvcNbSWn20rKSB0oRHnS
Q+4/bTZqNjVpkx4+3EfHbuIzjfiSfvaWOmFxe0Yd0Z622lCmdcy2c6Q/YdQH4uUn0NUrpgHD5vud
+JdNZRMxbkh6m/fMWBZgsl5yDoooQAhcS47/NUSXdTkbqxlozvDuqa36rqIZELex/MG48074q6PC
BCVdtXphqRKq82l0bbtsFGNQvytJyN3jT0LgEJckw1/YfL+XfiqfROllwZdFtqwSVgTOXqLC21Ed
ow+FuJZn9jefcVaZLN+ZSzHrKC3HxNO6oxOfUlPRlZNE3BET0JrxiS1d3szXEB5SGwB2eKgnb1pL
AgmB4vyUfObamX4pUn0PAKeoGE5e1CRjLGHaoaY19tYFvupATASBPln8pTCYTYjpVmP1my7k/4Zz
UMI8XxgHRjaKlrjrFZ9n+KR7gIaJcWVCg8doDwA/aZ9lFE507mRxY7lqZmt2F0NVa+ihlio1L6Bh
jQkzYP/JX4KHzQSOtZMyYVSW2yv2v5NygMAxg7GP7W4O3VCE8/qpptmLWtEZRZVNaqO9EzoZzGW0
EMoLcCW0Ac2Zl3zPZgh0LEK3h/oMCkW6nZaXooLt0gn6sRwXDR04C+FXGjtQY1s+pWZxKbpv2l1p
lHvem3R+UxKBTK+aBAkMusKtsO32KzXBVs6Pu8uflRSXe2FmU4AKlFY0epHvXHs0WwZY5h7tWfwA
ELMYN048mT87HDZIuHNpE3J6lvw68MpoWTIB7oV7uAnre1ACYwDOO/eagnF2QLe01aFZX9FLXA0d
kD5UHu72ILhjghC58T1fKm0kSKgpdNTGWDfW7IdDH6s288wTEhMhij9tCGmN1XSaUPeDXjytc7pi
cI9JdGv45w19PlcAQZdmujYXHT855KXeLkJqjSbkDnjeEn69PeRQkXQ/UPFqaHzUUqSs/O5urZx8
0a6HgILrPIbTZcoY/zNjvcX0BajmomlPdL2EcUn5lxLelu6+x8xnGnJ0Nxg8Hgo9kMAZ9MVsgeAn
ObqIHPTFPzm376W48Ij0bPx38av8Ok3KUURHmQMaC+Md+I7sbWdYqtLVgBuGSPm+hmctevLw6hot
Ytt56CR7iLOiaRKkSISEOjr7E6w3o+Talv61Ztq64Ua6OABc61fHB17d3LdDbrqgIW9W2OocecjQ
Mc4RkjM3nWjDuKRxXSz0iEcqnhlO0AOs6Pw/F6bb7pxRu526CmlOFK17UXCuwpI/b66fWGL/O3P+
MsA062Nos7iueBWfQvVPak+aKI2P/j26izIrCFGXbylxV8NJ8mJVKQ0zQinUe/a7OupJsuE0gEkq
jHN1QXtzuWXRHrm1pkfwDpEFjGRyR1G0igDUnQzVh3hsK//sik+524L94f3WLI1mzYIlE5A3rk6g
uw8OfQjZDaPODzRtDCyEhSIEuF1JzGENKzVwuEfDEHrWMba2FHa/TLF4056A96nfUPfpXBb2NfE/
Yh+oUoAFtGYf1Vid8rqYCsPPeNVUb1qqNlZG/Kf3p7Ic1LiXbn1NK80VRtLRCfThDF1lUrnFC9cC
WcGk5hkhRIjIYJh84pfAfzO3vC0tIPLdEWN1m5IXVVx6Cf5/QS9JL0zxnBgPqe0C7DBWixrT77V6
a+IiGuJe0pOejl2C3LyHLNev3zYieMPwnmvMu+c/4Q3DjNaaYALAnAtrxLEe2UhS/jT4DEOXYq7z
seKhljoVG+rXB21CBFtgrPnfpRkdp9q6pYmeDFLKjoM2DNHuI1bA+LZmaOYL8pWGYkdVODKR4ee6
WGTqW9eOdIQA3cb6p90VtnQ2UiClBWWYCYgBvVWEb32btlPl11dZ7/X4sMnDA3YVSK52mxE6QQ8F
gOIKVXeTQfH+3chB2sfeRX3ypLnDuipBhd9R2x5h8d7Lq6TNilyT0ONzQYbMhiIa0UtUUtIfUP8C
lS/5OwFM+kgpnFpx+DlYZKlLVj8qxscRKdE8xJsuuJlFU90kcGxZkO/NVkkcGkHBwtqQP91d7gP3
RdIs3WC/gFMsuf1lCdw+1L0xI4CiiVyfN3d+OKTiDzYrVmLzNZDR8gH20caT9JOoXcSei6AC9qF6
VcuabuxwtFyBQQPrFRJdRdG14ucj2hUErRLiidASIhO8SRHQaFRkiXN4lV8Z9qSGEkpW46qq5UEM
9pTjmO3WgqLAczkinZR+nxmaNl49Zj2IPEkNXxjtBUihaMKnnsHh9AmtM6xrtHShyV7qrj2B2Muf
IFqBYjgVTGkZZ5GP0+00V48E22mLvgAWQkxQEyJwBWZCwfJ6freg7gQgimnXLPabp2Ii4vxwEcNV
87IadA1RDRxj4vYlD1DD7Z17Ioc9SZded4vBatVe00/IlYIcrbrzkNBoEI+69uq0HcZmcvZCDVUE
3MdJWFuA1BMdWju1viJOVnizMT8mKK96YfCZdZMwZG+e4MQKpnnaGo3ta3jhQRyQlJLrtG4XpjZS
9Qlw82+v6P66EHL1z8T99LTwrH8qtwhVAu/M16cj2WeNGcwq3ju6VLp9TRAJq0ZDgNHSOpQaDMRx
uNaO9caRtxs714TQqyEy9CjTN9BZ+iYOVbv5RKoYjBxwY5PpH/wnRrNIhNPj+VboL15BwODP9cW7
OGiLMI9z/gp82OjxfJXkp4B6rU7vZYRnXCdwHyjEphEvPGeh6EYdbxDx0HSZcqjvFZ7HVQ8I+p0N
NtqZDXlSkyxsOEeEM1P//Ex2n7BEVYnXk+NHoz7cde6cov3f9YvjA4eAG82pO0f1HXsP5s+9YjdM
patnxR4479DuL8TkvCQ5KRHe3NHkaX36culnrGyXYJTkpn164aHulS74BIzexMhPvdUu9jlKCFEl
yKQ/KqcvOKt4LABNMGH/DmBXpU8dLW+hDajXMJe7BxLgNPzbGhOlUIp/f/dc0YB0yM+6/l4GtJ7L
osgBYin7TkgljgLfl7hdJmjxks7XmUXLNrLh4BY+h1UYWRj/Ai0W4vz5nwJKOCLT1XXjc47ZO1P3
W4uctl4Y/wBBYSmaUT1i6xNDrNI0ZbEG8oyqSj1Dk3EjwDbn9/S6BxS++t7BV7mVlD6q6NYo8btL
0+OFseFziiGbfAUHzYLNgsfvlCK7TldPB+RMHPl6/dR+VmtL7hJKadlWYZkVCJpYGhYrMWochEGf
1sClTSIRAUlDSmt6EPi3VUjuYAyEmG3/ZNdEQKwVHzDFywMXHh/0+wkD9MD6HLVQntKr9rAWJBT3
a/+iiwYVwKBC6PrF479y+vRhowKdUHWXqGaRbXrEO0eN8VCvqq4ZqpTyKEKQjG7u5hhYDiKv68LW
UhjHZSw93Rk23c1i2fyh/qJhjRYFogDI0pCmg4nEKdkaCvai6wQh42sKn7gO2Wofz9gvQzTqomob
2CFaEle07+cD1H6pkPAoLyMY+D7EqTEifJsdUglK+xiePF2TkZzIGxgg+0p7FJIu6terHMkwm+n6
SiaOxVLR8g9FfN59AKbOf4zJljo0cJHA7qZvmGayJAsZk9+jkvhK8AW2Q/yBX6+mORBtaxYG4pMR
fV77JJXbETPxQQFzmkgjeIR5Vz7kHSvwsoY9uWfu25d6ipffQcyXOqZxtBXaPpoZ6LiIdAyAJJL2
g6n1OEIRNmj5ZnTzchxCdoA5/JdB8kJbWu+7v8Fh3z0bsnjPP/NjM5nEdgKH/CRmLqNf733nQ0oh
ruWTh7cwQqQni1spjBXRs1OiObZ1DtIVNUkUQD1SnDaX0sGAnWsAocRMmnobh4Pil4LuAm3mP4f/
bJfyHYbVdDarJi/ZmlS6DzyAM8QUFKnnVQpe6vBlohaBBPGU5dDW0ucskThe+HWkbxxnm5JNTObr
zcwCGYosRqrqiy/HjkpZkrZleZ0pNN1CDcm1c4q53fLwajMQxdwv8BSxZzmm3YtYvJRZvipEZ+19
lg8rNaSaZcoBjIps9+q2aXTGLRTEYulOHMK8nAQZChHTMF6wyl4HFWYq6vEhH82v8ltGAp7LvhbG
t2lb9SDVSuPLgHcWQnb7CExYzPMyT2hI6HjJ+nR+FfoDFgjB0mtQkD9T0srKNeDN1Wb2lSiJrPo0
08XrqFWArhg/qISANcAE5W7yUphY1Kxks4bccD5PGYE3IOzEOfoHMtweJiNZh1E3JYzFvjfbH82S
e1GWT+9lXEsFXYtvwYhDcBLYDf+z5XJg4i6h33ZtYlvnOcnsACw3d8ymfDQXpQ7m4dUkXRvrVtFN
KHe0RJA4bD9orjfDNtimE2QCbHz/IPQcsrS3kkyfMQ7d+XxU4seQG16lY3dPr41lAzl0SzsRR7q+
ObTy9ahSyQ7I8CUVTHdNXDD99iCOTxjHfI7unrNujOXG/g0twjYgSjeOjPRihk1SMuYLuUNK8//m
QQ60fJDgk2rBMoblJvQoD3xRTkFHgamFbf39u0a/0IK1IBRZ5AblS96fUrYrm2v8SgiSjd2ylsjF
X+Awb8MbuF+vsuTe6nOCaowr9UJfxcaex5csRKKZWMTJeRatws152/8pFq9dkIe9hu0rhRYLxpZC
xgyd5ka0fENYvfdvEO25kfSGTZPGy50r3HFgqGUlQtGEisEqdX4Fk29PA/QsP8/r0jLkl2cv6mKC
AjsQ75KUZvhGyb3mx2qqiK9wmicO5EqaD536B7vrz/WkTq7CBBJxQfDNqqYlqi1iJjqwIWUQNSdH
B3Jrr7Eh7vh9haZfzDId5YJIxVz79TI5ZSHKNP7qpyqQF7adEaNb6eMf94kIvfB0hY9LvAeKvveH
u9+rtTJAcDapZ0P/BWheWRux/ztISJB8s1lg3Sjvet4oTi+2Ve8jtKKiK/INDBAp862hHRDYr06D
CZC2AthcI2LTN2VejCsHmkBpP0dX2QiDigMupJNCbGgnAgilr+DgdZ6CqjOonGtCH2beKr+2yCN9
VH77/QLy6ndwlMzI2hYtM9VJia7X9SJegtVRdusbZSSNk2b/NzYTF5xZt/A9uRDvEUytLLwykt+Z
oKah58peGU4lYV5XPo9xlAv0BcAPl6LFvcbfz3aV7Nj0aL4xz4deJdJMemifNFGn8WIoqCyh0eE/
yKvWpjeSlEkLLZhzFJOmnv201I5JkRUlHYzsqJgvZEdDlCyzwnSyEPX7ZTnMt2GWlsu+6W3isCcO
+8onpjzH3rdzRnmqd7ar9E74PLO+FBUpJSSS593EiRsfOIOXvfOvcNIOgFdassxSVUgKUimb+z/P
eGrkBkUgGLAK9PFl82OuIpqyKF2inq7pEuOnejeglZk5nI7XT+9mdhm45AK3Kk4XnqtzmWE0RepS
8dGUmG55C6p9CHwV5GRilbX24jYEiVLOfB6t67ozS/kabyi2kYa2nFAQH1bNeoPHHq4C0anXeL+P
CIK1IyECpPXy5XjekTzuQJ8RB2O9E9N5h6d1ydtY8ciDPlWEAea1PJOSVBGfkmuEIWIWO/ZzXLoV
H58Y8gQmTc0FhJnL/rNxFLSlbb1l9dX+joNzKQDIYLu6Ecj/hEdIDIktapctLfIBs6jgRnD3PSq1
OmPseyv2ditz2+d0YHxCZgl1rPJf1KGcer8Wps7sgZcmLYk9Mu0Wbn8kZWjxri7hzLXNTjHJcYUM
f6oFrqCdMrYcnKWKVzHVB9nryN/TSfaMGmRlsm1hFU6N374wRG3alcj3dYJflfQQwn5RgLI89aPI
hUloPJY7Po9NwC6bf65HYwyo0nkdLM6p76JyR2KlU3iM5Yv3DIr8g3DFQ62BypE5f5+fV9Cnvf21
PKnn7Nltc9M7AOACQaIF+nJk9nOYq63NSGL2buoPtsD4SLMN8S2R1WmpRiE5qnOfySqQZCnd9IN4
8vjd5r/oOr127RHWkeK2amdtFiv+sAPE0ZGj9566Qz88I+YL93/k7QNWp6E3WhICHP8ZbbpDFfdN
DSMxXhEtqJAbkgD0uVYDfHtvR3j5vGvqmF5mXDiDniqzgTiBFZtYRro+bX5a7cMDYdyoXi3HcDS+
MS0y9kEdH2CFKZFN7oNwKOeGlCpIrhnwcQ4O15iMWfpCM+3xAuItzLBtosCL+KCPY2ZFWMOftM4q
XgMP14i9ahBrC0UHSSOyEJh/MUyLhNjRnJ6Ea3Whe5uKZLTtHXME30kDajC1ReEHHaLJLHH1TFga
171BaOqBb0ibV7IC648iMzwZju/kxq8k9C/PtA1WwO9VkZmfSfCzd6G39DbT5A5RZ9t8QTemwPlU
jMKvBD4tj6HexwIWasYtU6Xf+EbAClaqHgWxwrAOx7JBHdWNYQZtQ9n2xq7e5/l0n8F5cF5jjOrg
IplHlDlZfIwb+v1Yj2zMjvLAG869RBXtzvwhONgjtOMUoxrhQ59r/OvvYwyWG49soOWYOBw3OsEB
cmHUg9Y7zvnMWXWvNGqaHH9sXCPPyJnLso0/PJdsNO+ghfSpTGlyx1qexYrcri2s/KceXHcDjzgf
soI/Uc7ziFEFRwPFo9yHSj+HiQm1Ef1R1FyGb9mnUq6xeJuCgKrs2FfC0fWY69dQPnljavBJjemF
zuiJrVbp+OzCefj98xw4niXRJmWGS5CHcVGsa/qEaFQIeAV/E9+0HMIiDf95+6E5C/wEfcEaWkkr
aM0sNrsImeaawKVmKTDOp1Yt0AXJ+baWYXKuGLv9tkwEwz09K+8JWUby21J+fKrRDQeoQntIrEc/
GcjtQYAJsvPwtx4qdkGB2yl9fXbfgkwYCzl82OtsC3bgnDprsMAPOGF3S4yu5/O8+wDbu5D8QAKa
GBGS/NFrDTFhZ8H96tB307tK8597+rKbLg5o/pEb5aToVV7VCsskTnaaAxRBgyj0y1rLu2qtY3mr
LZ9a4O61N/LRZt3igVTj9nQ5hFrWcvdI8hP9TeB1RVfj+gYOmSdD6CNO4YtUfoI469CBK+SPEIj/
5FpBoXLtwb9uj3Q54V/fqmoDAYpT78pT/PHrmP7Ge83hjlc+4iVWUygar+1cYL8La6sbuB6MraKj
Ut4hxYbEw9ITWZ5unWWv8EjbkWgLIG4/hA7p+86s8dlN2FgTRCQci2cXZv9rdKkWTHujDyzo9FEX
adjJFPO1K3TA/WdwLFdFKKyEIW9aOn2kx5BVdWQpE02NBaxlqyvrPYy79McsknW3MC+Gqp4HcVN7
iD6amKSgGNUPP2YcVVtlSAZsp4TxN1ZI/8IbaaicmUFhTfuNuDG8DdSjprlfQdjkzfqwIn8B1RV8
FcTCYUjqGu93Pbfgq3vqHtxQ0sGsuVUY4ghpMP81KpsRweuCjpvsKxY3w3+fKjADkrwfObFzkeAB
+gfSuW9LrUKkNKcqiNuN57PgDtjM+rSVOEfEB673t2MfgmxMZWnhbcuYSaPsZcL/yEV44yUWRQU4
R/UmdDYlMFAQLPhzjxmKGNUvcV7+966asxygEkEWAukzfpBl+26s39MFy3PZqPbfjevWmH6RPiiW
gzyL1SXBM5olXjKJzIbdEicTHGu3+Zc3GJmpMEF1qPu5wTLIpI4Zl7u/nMXicE5wwxQ6iJ71RSoG
9JEAcjAFz+u9aadmJdqqBgr6/54wgw0MMWw/GmlN6VKZMAKpi4xC5xIGIpneNahpJES5WA9ALT3k
hCyzvQ0Oob6k57y+dQztvRAWJNlclmQLnGCkTwWl3XK0hyeUpZV33xsi5O7vRKAeSpDhZ9BUWkXH
cZrZQvltrl99+M/Lezr2+HdU6Li40Z19GN6wgCwfBWXYWCqtib/9/86iJAaav6sMk6n/yoym0mbf
05mFg23BOcRUtmHyIRBNktjEJwlK9QcPnRN/ZNbn1aGjX4QPqjGEWPPn6nUCTzOzGqZS884u4gsm
sgVSYESOrvUfohdBALkxhgbd3AS00lh3C317mw0YVSvNAcZ0buW3q+xz/w2dB/Y5FRBMC2qyrnUN
akp5htUzrszOhFtwYZSIy1QtRr2JzpF85kMTT16kNL4caidsITiltaKfPd/C26MTe1KKrAXosuYT
dLDPAGIZQK2MxKdDB25Uh2P7R75jY3VMykl0fMS073flCWt34kq0XawVhdrdBtz+NFKc+I9BEQ26
JNoGKNEIL6Q8Z18CSyBIM5YLmjbB6fuwPi1ZIN3oVDHFT5mbKRmL6nuYLKa2wtmqe/yWdsoWpe7y
6k2XPQDQCAGCtIQpsky07HOi8t5jIUTjQPApFz04TxgMMLSE0gBHkjd8Yz9BV259nCzbLMhqQpvk
3aCxT57FLhwX0pIYJ4Xqgausz3ic4cC//BuDZYlnK/yBc89NXp02wuBmLXdHdM7l/PZ2U8FrLhYm
EKdjZ59JZfDln2PE+jqMGXH30peYXYuy5aKbysZZf1aic0+KJm/iEULf0O0EYFoxqLfF59T7bzza
4usLJsUqPHFl1iMwnHAUrZ9JN9wMF7Ld15R8mA7R8omPFF22pY3Zxy60SvJj8knjVnaJPc6RvWrM
dV04eBxTfiNMXgqANbRch8KocB/CBRkt6/Q69zUiI91lHsKjkudMnpxsRNSW45DGCtmp2eCv90OB
mN5lq7Bbey1RdLRvORiBvGMcnsEB4osdcJxH7NSTLU0WwME8UIiiKv5TIU6rp3yjF3rdq0m0WL6K
L0WqCke5Tlpg3eSozlicfxrvPP3JjkHc0mBsr80k42f2f1Ro4cFAgYo3/DimbUNKCMLLGg4e45fV
mXUmX2S6TSpDbCl//5pj+iTQlfPMgQWFp7sQOr79zWF/x0W9sOb9sZNStNAJ7JUbYYNcgikxziYe
UKM/Z15AMzI63oN1YpvEt8qmAXJJo+1eXvvLtNYK91WxonFAK+AeeoXufj7UqL4qnRMAMRMNX3oG
VBjYCuzXEVySEoYwvHE/msdPNCRGwb1P4LdyVMRbe+QTvmFyAnuHO7dRIIA5ar2jeOumKDLpOHax
HF5p+D6sJfbb0zCYw8i/4YIsm1R1U6Lib2xGuOz1GXL+PLbpMx+hXlRGLgZ3kz792cCWf1aStCAL
j3ppzTOG+gxdHaB/SPfXUxAR4T7zCwwhv0eC1V6Rg/QgTYX6Tmks57B80yGU9gVRNEZnDfW2S0MY
UAGfBQT34bE4TUzOiePvwQCxN3DPJS9uZNFuds2DEmGfX1npfYYpxRd0wAME1yMqgMpuP/1qVdLW
m1u2tXfxtIFWMHOQg9iDjjytGF9hl+9S42M33Bgp/NBhq3IJeaKeOinZJL2u9Ku7up95yxSL2l/a
p7edIBuelz5Yk0Fgi/5lAw1CZPfb4EvoQAkXslyQ5NIR4XITDM88yWNYjnRSgAMpwqa3f8Mm8j+K
h4ELh4ZPyl0UMWt+DO1bvPBkrahh2gFnCK8hFODwBCjuFVXddZ1XLuocAPrZsI4vAvN0cuzDIji4
yrJzG+q8pDMqvJ7wezl/O5ipiATjv4DI8NFM76PNsucS5wDT4CYsGKtiQxFaEVuc5dJdTv6S8JfX
L1PWlVk6aed0JsFf7zlHwg/S0NWkUbETq7AnqcUDucERtQTBXswXoKo72l+VrWteK1HGBMp4nN8K
gQacv90ElYcKWNVw3FZMz6rYD/2rjmdgWW0XPOxz2nOKTPjc/0LtZVhKJOnoZV0/GrcDtnjsfCZY
EVd6yjiosPxlPue6r/Acw8RmTCbVFruBRLZtX0bKxRLeszdwnlBsTNXuWewoc2MnEwWOh7zfRIZ6
ISGKIWm5BV03cnEH6duTAEX5vA0x+NXGOtQdnDzHq5rN4nhE1jLtK85gg1HAOV2Keo4EGTwGuh0B
A8eLYvd6xkAW7381glqYFkSurYSy0xmYwf8s4+xKyGP0IZtSXHUpP4sg4NxCkD4SFGSHtW2Tvirc
nNX182pVmC62B5S/JRWrIXt2YlZMPN7n6B82M/TIzaZSixJQmJj0Y+ADHE1hEzWQVgHudwpD1KsI
WvPHJ7HZAziaqLaDQn9S3+j20LBvk5wlxhz/GPGdU3NNb8eeZp6XVf0vVm8cXO7LRLfRo8BglcQa
O/LyKcwotWg/LJ4bC74mVxoZjIB6Znpk9rzASHgDuRXKTzrhM3rMxc6yIuTWZt1uSbmgtZw295nf
MjIYnxowAemapFbXZCQ45353Uy2eYOUSuQD+fJju5NXIe1oFjTVL9GuLasOyt0xEnafETx6RHtws
ZXStFCJF6KCnlejlEw828TJ2B6FIw5UqvBEXaUwjCLefZFXGTPJGx5BeRb2DmJNoRC+XDZztFo1h
rQtmzCpRKMDaOphvPj4rIIAvhi8PGlli3wPvnfdAcZ9nguOmxbWdlKfpf1PUTvaoJdlszyPOHYWI
9K3sbzlajvTnh2qh9Gd9S0nbF5xoyDKwdlEo5pYQi6qPQupiqv0TvNQJ6KHZvjcF85xvysBo44vt
72rXpsj083bIni1cDnfpdtvrLZej7vRpIyhSlaYUTO6NDHgObIh6i9Yjb7XqHprw964S9ELWby0c
ptrbMkYZUTNeDZdGPeiNMp9A3NNHzhb2eah1t0OPb6Z0HrlfjOooEZGnWWW3sFELaXywsQiwezYq
/CFQUpfP0Ru/1pyLLpq80P+OS/vTY1TYwyK3lHU2iwBZmOKZ51EyDhRmG9KVJlscpoQqb3hl2mou
UwgenB1BuHRwAowweaQrTibqbH93K4vHJ4LkaeBWWzNmFfOH/RLeZgqlnJ+P90iQluRq783xHEYU
pGXNbWXJGYvLLp29b0+MAkndvIegQOESide8U8/ffObPuknj33btghNFfxAKGSiK8hE5fjVYui6R
8iQf5J2zPXM+KNyaoS+Q3EV/TD91eVLUKDFALPEe0LnJjmLpqlBJqr5ah8R7kmxPt/sX7plaepWK
J6YwyQoI19HFTYgL3AbHIsSx+MwgbdX0rbnqPvk3iqjlV942HlvNKR62r6CfwjgjTFm3PzWFVeRa
D//FMgC6NXP6i6J8Tz+fwwJ/nmbfxoNJ3pGWS7dZNO0St6sOUMQfVKYmFu3emGlh/HlQQr8M5GUK
J771d6QzTURTljIdeT/dHjvz734gTw8bXLoDyN0GnRF9fwH1I05xBkgUmswirhpZ926mn9ytp53P
xMLSGvEU4Wh0dnQ5Ph6qUQsXXsmJ0d17q7cbkM86UjBX1bqD7cD/GL8wf+f8h8BB7YXLV7aNO/N6
LHjiXLyjDXWH4RgWYHL5gwmDj+JaC+ImlNipZRf3Jv2WVGcR/dIWZwerip4s2jYEQ1ju0K05TS/z
bM+EUT6APTTBEYpgxgyiASFTjQhoiGEOYWvJBx1JWppn4FWbI8Sxf8N1vRD14aUo1gf8rK168jyK
Qz5kf+FsCX3hhlrXL0C1NJPe6hnnJvqIYdB80FcVcVvi3TCvWgx+kerLZp0Yd5wPR20r1nBrE5gT
WvVgbgXYQrHqEJ2baK8Fkl75OuNeJiFxt7NaP0OzOXZ6ml7LjOf6QC3W8aWnIauxqr8771saPRaT
GvRST8UZ7lvJiYqo1b3WKL4dqN1zSeuPDwmN0XI8vhP4KPKtetCAFvDN/DXnuB4h8ZYxWGkHi5Cb
G++3oYV8Qc3rFNL12anAxQh3wgLGMLNCPNZJyAgvC3Wtr3KdNOV99oQF2mMtlDSi80P9BgRgEZfM
Os8fU4yXZVYrTfOhk+r5pNf9ly8q/vaeplgNNfpnMO/6Z0c8il1OXCcpuELLT+Wb1xcvJraOFx6I
8CwL65iigsJO2ipfICmO4qyTAYiIX/dLZjFF62P4tNejv+Vj8b5TGf2bdbJwt/sBkyHk8jzpjlDb
OX2BRSrGhr90XsnItvBWshLl/SjRIJrMqvwLKvnsAlSOzkbA/ucbMUP+PmRUPFg0gIe5hUJ/Sij3
yBJ4syUl6jiExL7AviW4WZCo0r3m9ujAEiR8n8L9an+GlnRbV30a38DpR1SE5KHaIW5YMRsxB6Se
/cvfd1EtzSiEqy04TPoGjmpj8DkvZZqnQjH/JsntPo1ZEnyuP0vBeoMkp8BhNnPyojfEXc/q9ErT
F6BKIUCB8tq2xGTWu5KrG88mrNxnC4DEDt0XxVOzOlpOmIt1PV+sepvGPpkL3fEeGeMZ/IrSOP9m
q/hL8l7dxnUIo5JvWmv294yzeK9X6D4LG81O4C5kAe/rOz7rgPnNHH5AVUy5vfRo5pzNTyBrkpBg
QMkHJSSzBKJoBi4/VYcPfzeYrIhWMob+bhwW7u3gkAtoz79uyFfoRF32U4e7DmGPALudCQ7U/II0
A0QhZRFjyaefgUk2jjYH1jizEP+7GSD/6OaMufOrc3eXXWuor8N9VAjST0ttmJW+yT8dcjBY5yAq
Yi7PW57YkvU2FHOthuaW8+nPgGg9eiP1vNf1fnNgLaI8aEo8/HxkOar7fm/t6PNMzzC9wgUM8Oix
y0trfn79tk1zc0OtZleoQ81GTOgbg69F3Xree9zDB5H5xcDH0TLnrO1C5ZDxqZ6MvPY26UR0bU2+
FWmpL8jSVUj3l00c4QqVX5LeJ8P3ZiUm5s1TRVpUoj/a6FvY2IgM+kHV7TrITYDTV++KoZ7J8Zbz
SWnF8JgJ4dpsv+0lqdKSxtUFgNx2zYaaYIRFs675BiB3FFORIh3sVp9zoVpU8n0ZIYV6SfX0I4Z9
dK0y+0nV7Jzr25Ynzb7vD1HB4Ymont9QqdoBFSxZxaTAQFqmezt3KvxTIn+Bu2MdXrWPixGZfs7q
QlSkJFkaSe52dGCkVZzg39dWmceFBj6yMhKXoJ8YgY6aFrr0wj0Gh7v3z8TX/3smyuqaZO+eOkIz
uzk4OWHsj9Mi1b1vQ4ohu1rau5e5D5XL1fTRVINHbl9MZIOIHftw0OL6JStZHPUSeShwf7/WsVMR
6ltzav3nqjH5N9IGwAYhrpJJ7Mn2B09mOtwZ39WZCGPSG2iHJKunRAbZWDYHOc0/qzu12UdWpuXP
fESyz7fL7ZF64arw/GjOUYtVbgCPtR3+3W8GEffnOzXxMA5hPWmCpwUaSsWgZ9OOhdmJ3J/VaPZ/
F/+M26J73gWjNiKtwGSlehgz6w9/VxgWYY8nv3jyntKdzn0Xsp5oqnkAkqQK9qdHzSWBf0kxDSZQ
2FXZir1M+PWy1Rm67Hh1iipF5D2iieYMreqvIxLDXZuOu64RgT5f3NAagNdead3yesDGD8pVuS4B
1Li7LWH2PU1m1Cgr6c9vad9wiBHuDsb2dJAghpgH/Rvvov/Up0WkBmHaO69nZ8ICK3Eo3FpqpEup
I5e2PUddQW+JmSW8lDieEgD/XR8klNHtrMYvQJQg2ZKOAFqfvkPjbLmRf50KK0j+d/loPMQzbTMV
BfW485mCZ9kMqWKXByKD/G7XdCAoesd7iL/jpMvm9P8m88uoBEBSFgO8YQVnxrkE73HcUl8GY7zX
M/WW6hSQHIBWgSV6IOknuWE9AGCcojZLW+3gssjBz1+FkQisGRKYmAoyS37RD3OmdMQ/oGX0jHbn
kGk0t/2kNArfDAORnLMt46h/UCOtMSOVWJkkwhUUxJLoQJaJbni9aSVdxW6PJ0DWzw4Noz1qjxD2
4xrHl/rjdhz4XGekq/VgMxRIrMZVJ8CCMQCSlAnpeSy/+m7zjBmTPbcbReibZnBunCzJlnzPuUe0
Q4BKGo3dM78OXDb3/QmZoASZ/6KULUCpkf5pK4qAA0Li1qJyW6WOEMveHwuo0P9FHZg9uohr17i1
zgtWlNsvPQ8gc66M51W9J+Xq5tm5rVyP/vSU/QD/n8boEejIRuG7eEGuW4vvyw7GMcO0OgZ705nw
QXSs1JhyMcrsM7ZCESQyCQP9Xcp0V5NB4DiQSWriiqBHO0jF+Kw8eRiTtlf8Lbd884IyunjA6iwU
C7RValILXXgvMWS9P3LKCpqSs5wDZwjE64tXwOOfEGeJ9mPQxiM5pIMuwOLfWotuj435ly2ryqv0
qeZ8Dx0+/wj5Sr3wpEbg2FYycG9u1vMRrYAdn3hxvLVZxnQsaR4Ha72s4UFIPFzANf2Lq3VGy9sx
PS4UzEp8pyUWUabXiN9Q2CdXajjIc6mazEzW8WceOSMsGpqCeZSkvsLEyeOwcLqYTu60VfPhAxIB
dhiMc4GKV2rb5H4G596mWo57PhvyjYqzzQWBVs0+VHz5eze95pyVXXrzZL4QH9hMF6+VQOKkkKXe
UA2Ye6YN3QM+YT5YqdTdmhX6YE71ksAQQtLEKnlZoCty/SwUW1/GkVgaZJ9C3kDUcgrgOslYxWeR
CIHghHmEtbh5ZNVyo+qXsrQilomIbUGO+MhasxvyRGvthGJiXFsMc8pTfeLpybqGZlZVxaHlRtLB
9X59M21cXQkg15uQJO2ZNBM73QlmjHeggNjWoF85pej/V3FSAxbJvErbS7swyYcl/wecTPaHiNEP
nRWwl2+2Hv6Hiplhuue6LhytqP6OMJaM/LpV6jHpQymamOBhHlkyZnibJd5KmaoamnVo+k7LGT9y
cjHGIUrkKhLtIwzT9WvIpTSc0mYspoBgPHTD+EyqWSkx5Ez/OM6uHOPubjpDef49WlQ4HI0DVM+n
hAJ+RkMz2jjMjdgCWtBe00LrZfRtvfyMOKCW2QR8xwqJDpkYpTi/i+ptHhudpvFc603B3X2vTV37
3jQRh9gdg4sMmLF96xF3hli4utZaegFdbhTX/Fwr1eUnmiUaKEbDInrtO+9EZoQ1cmcsWRHNw5YN
j4qKNfzul2iTRfkt3LHFFnr6/QkYdyIuB2bHHxsyS+1rKw2vZbrCUozYEGFjpGs4oBBy1Z0aPAzl
XmKaC4LqgPBskhxzryk1cDal/SeSKLrxLGw1UhUIONeXkcf1WldzybwV5TubnmkNuttno+SnhsvO
njpIzG3LTUpk3FuajxLhkX6EExJhDiK8WladvsX0igkOvEuhKEOE3EZjkVfkxmSgNlMf52zQIFrv
jMXox5/RwFawhBJEyogD79Po/FSm2ke26H6sQiwgUAZ+sp+T99qVVbqo2N7rn9T5IREP99D10TEa
Lk6iKUy2XojuLZnI1BejjdOGdeoLpT//rB715zd5OYo8+SNUodCbzyxMwfwyk1EfOSlqE+e2yqPP
hwZI8AzeUuoXGZJQsrc9hkmxT2DQobx0Y/ISrZRqq4HbSpaVgno/GNqi7KYt8n86JT8daw4poAOD
TpJvhp0jGkgwX2yaVQ3JjNGJXaAgaVA9lOpInX24H3niUPmmRWUj7pmhqDj6awgZdo1tklIHGEUS
btYROnEb5+4AfX1K8JrRfdm6AUS1ncF+zatGKag91tt1OPDHhrmiGkfuNy/58M+WFtoZP9PlPIiL
VBgnaXvawkH3jD/haF1MKSxZhTeE0WOjPPoroheiT9Fs0d8LLS1afvQb/vwSnm+CgqjCyuivD0RH
oOZ8K5TgMPQCN0FvYSipGhBrPnO17q1kU4yxPZOy9G/8W2XJIvWbbWwQko4ShvkkjJ2lDNQsF7tH
PNQHsTmV4vGfYzd08sZYiFox8po7ZM1lwBrreE9/b8JqSiL3vEkJdxC1Kca7eijyxnaPj5R+bdk5
2UH9wWsxGRbmNFgNoSoktnK9gHBavjSXq+RUeKNjgwfATpo+MAG3q+0bK6El/xzNoQyOiZH0YLHc
IApukfecPOIj1jWnWcm+yeEwUUBrOdnyh5CZ9nDChO7BzJ5FZBF00pYOhI2SjmCWYQXYor6IVDWd
NM2QQDc6VaxV1AQ7bb2Qb7RXAVQ0F+yjz2pqHyh2X59ZQ/zHLWv6oVcVgfCOhBEgV4LaZu6S7Apb
/BPb5CVxiJ+oAyfexsg+/q/qLA8v9Q5eAXfqw2hxQaLqN/AaEBHH6N6IuhFVMkPoJvpG8bxtf2C1
gKJpYuX6oF35xZknpbYUXQRKCFEsXqP4APU9+gHnXTSNwOxB1nUEwwvTBXYG6eImV82u+3UhNmyx
XPw8wwjFWKEQcYqRGDopWymujVYk+VrXmECNJ3543RejK3URADbgYKqm3SAUlA0duXasTbShDNCy
W5s1BL8yCjTQcQDKmZqupcXKCbtcrGrI+nW5RtGkrZuhZ7irPu3tKCHkS//IbGtuF9N5ORadgjOp
XYeF7KUgn2VmmTwvKdlhFewe1lxQkhvosQGV2qs5YV29uytzJVMHrCT++qNWfBa77KnP+yJLxBRA
/cOwutvizERI3EGl4E029MMviL1DtOoGbt/KA9yZnWg5fky4HVcQNSqW+VpylqWiu7dAAiHPTbPj
NLlkQjVqv4IQwE0koNpRWTThBvKfLAyh2MSgQelBfjW+C2Ja5Tjut3ni2ifAZwXUQGnVYs/trLes
hrGfjzOAgoXHa/yOWFGktJrjnL2EDHTd5xumK2fdkkg9KB5c9NLW5oxCWPKcL/fF4LbtiPEHvXq1
/rIAjRNgnnHn4r64PaLwfkzfBLM3kYftCRChLnjTDcCclhVoi2dsFLFttxg+Cnl5tOCu6iZz40Kt
JOMQc+A2CilboYknZhnwDM91tTeUwJ5XBKyAF/g6UkwdLg7WuzoxE/dg1S8DmLtJvxgpzemA38qf
c/J+N1f0APK2ZPLrrlT6SiLiXA7ApzQoYSjqVsdaUcy+9+CPgdhoX1DyYKciZa4tfMmoLevkrmSO
cRLUz76LEp/Mt7NiF2yUAlfCYtyhTvxs6MuCfA0X0MWBMSBrx50j0nAt6jHDj6lp8+yfMzNoCsqP
/7mEZGXog03Zv5ERGM2AOM/XI2T0X/YBFFWMJYMO9zaggP/G6oGKA19IWMiAUMqmJQKz50nD66ww
/49PWItJ4niem89StfPukA4DtsFvYnbqMYkyudL7pP2DTWKrkM3CldSLOM8bQGf41MRHvUQAgDq7
+zd+jnXznZIkLuFtr/1WwGtcIPP3hl/C3xbBb5iLuIpoTx6b7HYCywtM+L7aIK+oSznU3HImX2iz
ZT3f1blOVv3BUi/FbgaleMiuKV6mG/bC59psshObRgjqg22V2PHOBR7d7jQskAjMcU+Ha+1TMjJ0
8Q2kGWgyKKjR4CwXMnhEBWHpJv1sRQ6B/rGjZNKkq4c5LMNf9+0tzTxUDSWLUKNg+1A4kWVhGMtb
EKTERQNsQwii/HUAjbi7/eDRvvch5e1NOTj1gFqQneGK//7V5OWFm6t8/nlOWrufFxydPJLwOCa7
OVYWwS6UlvAWQgfen9z1ye99+ScAMdggLwdTthEZQvkLtcr8vBMhjaad+MDGamn/P7bLGzVyPcVu
32FICumGUxJyNleJMw3K4HEqjjJFLH9KZe9zb8zqtyfYdKZJaBq1YhDTb2E+ppVlyEpQGRdojwJA
wtXLW61JJDxPaI9dbZXpzJVq13IXiTMBuKR0M5ZMHrM80edgeucC/G1Q6fNkE7uNRS4maEntyPq/
35PFo9mJe4nu4DwPtW7v3VgrWXx5ew3W53g4maIvWN9fv94qup2u4JHMT1FPBiVRp5MWGxAKjDN5
5Ha3tjX38QSSkIGptkdGvIyFx/wPJ+rDc/O0pooH4QLjtIDwlbrN8C6fuVcNoQVk7XnwIIpTj4CO
TanloVBM81yreg5qS59Re1CLMqLGeMZerQIMCctAA4NwMN/b/3nZioQ9QzVBgk8R4XsLLwN62Nrt
kZKrvXUchQOaWzJUJbzbu//m4Gp2beKVDed+vXGwi6UlryaBRBalUomDi1BXYB7Zbb310mkcxl1L
3eL3sRW+tqCl7hbHmCt8EyWO4Y0EQJ8BmYeXnTarORLBS76Wzxwx/QnsZaOAAxHepPp7IGdnm/Vm
oo2Wfdki336chvhBjk39bZ7Cc2eEBUdjWjC/RBA3mFhXVwwCg14Wb03BH2/PxNjZDnYZz5S78nOH
Zeo7w+lp0ymp0bjliLlqbSIibEshWdLn9v+hMdz1AA24NRoolcc1J9G0Xp2OiZ89VYEkeP7sy6vf
toDFUov0Ao3xc7vQCFEp3tRC4b89gQcBjC7Wv9LKKinPorbczfhpTzLauA2PNwW6mQRwOj0aQGw4
K+owFiKzzPjPBy8VjxKJfhm9n0FzF6Vbn3+qdJTI0/iSzRoXRooUBJz1dL+KQoE1ppK1C6LXyX2J
5r00jLFgQf8ZTjiaDjOm+9/93ltTI3NMP61Zb5g+Hxx5gOGYp/t/cpgaNfqfbZpyg186npEBcTGK
p1fJpLIy7CAfRRnYX83vkIWSFDwhUegVvMadXjzgn/vP4lDnnIJJwXbtV8KJ+cZdpu9frAgl5PQ1
mZQhvMcFNTADiikLEdP7LuKcbAXDx+280INePKH8hJNfd5sXuXHTmgr2mjk7uk4OPAxlZl/OwlV3
A6fBvrgCBFm1YIp6+jgclB5dMigvSyppHA1RjDtenEwhfOvdPGgJWTpULwbM8HZOLWorm177DuwK
tNBo5JfIimDlfgmyqWDT7iPTPBxNpz49CWoFqHJ0/p7ydO5uZusRNX017qjHQGciZ+pk8TX7BzDe
QKUfGrTzhFqvgiJU46DQ/T+GBYfY2GvX+1YIftcB5RHxvWdUfIRxZ0i5Hpx2+yMN0QBGTobP8K8P
1D77n9szuE4mu4mP3Qyv6KQJDsZ8wufpX8O5pKRoL2/PbLqiqLDA3ARBeULYgRdbaWeTJZvI6QAp
ocujjtqG7ENseC54IhuoQ6y6m2ZEVlnmkrUH0m8MJ2IZIFst4w8NFhBIVaemFFU2vAOZ1oKFyPUr
yaLxYwSKPWCnS5WhK1jxVsBjavAdSTPCsSk1g4v/KAXTh6Lz0QcdW8mhgiHv4depI4KWUVf/uYjL
zVE+aYjDl6K6sXyOqk/9tNv98zTQNX+1BN5H7sH51n/3/s3VYxoirfMmHJdB1CE2PGrLdtGg0hbt
n7SQSNjrsJk3ECUFWZHeCcUX9IWE773UNh/eN4vnzmcDgg6WWwNQiEeJor64T2rLnZV6MEiIBiX2
Wz2C+Gla2FdwaSYoRPd+XAo5flC7F/SB4YOELfk9WipGhf/yyhpVg9rKQjl5iSbB3+es9sEZKs2X
TjzJT2mAKomuDYNDDvIeOEqjZ73zWPHA7ygAbTjIiZI8x+HeRdNQVzYW8tqcxws6r0PUD98h1UAA
wQNYX/amj21NjVfwyRNR/THG5bLJ74MS182vhlOjxUe5E1M/PVcc3H7FWYW0EgHBg1UczxrBDmFl
5r4bV1i2ucK7XkGi2AT15NWh31I2bjp9uvsXqJFKLo9JpzBDVo2079OQGnAS67uAFp1kCzu1+OC9
PmrcBsuHmnQnLHOgAu5HnHqpmmKT62TVIJXUoGSkDJnx1r82ANlfDr/Cn4hi1SLHz1fDIrsMVM6h
0c8SK0887Ue4T/Q8nMOX2hJ4n6gn/erWIz3Wpbjcw8+1B6zOG9HfVbjHH6ZrAcJnCzkmzPoMCCBM
g3eC7tT5kt1SWLEdau0Vb+Tev9VJFuHSgIxyBokndrzhW8DgTrIy8Milq/Bbi9oIbX0zKAhgygHG
5P6mgjCzrCLITix5B3ZEKMXvGACUogiggJKaBqsJeXpWUvWx/0HRX/YpjXYCJQU7YX4AFt5fIY47
dy2r+rBK8sjEEr49X1VmyhyefGiL97qrG+vdwKgUiKJc4zjqJuy7zxYGdr6PFzMtEKLY1ex4Sqh/
FdhRtarSO5PQcqHw3qM2x/80t76Nkfrdh/z/N72xFJsz/3cadj8TGXp4GH9UYxCScPnojnj0jkvk
/bKcVg5NjV0yZcd5YReRqx18rndJ4hQNr1u3XJnVb3DkvNtUkgKUjGBQ5QfIpRQUAjYvL9Z8Jt+u
ocuvWChZLwlZtEKKxhfnIDrpUSQyUHa3OzS+pY8gCphUYekOP0D3p0TrYT7+HijBDHgkhJMhN9iT
gQjB7Oe7lm3eOIKwUsze0AxadT/9Ai1Ijj8tFzTCDKf+spISe9y+w5/N84gSjg07TnR4UKnywNjF
SCh/YD8FsHiWiTcF8fvb5zYFyJSYjSq8pqq4+w0DGcRGzj6e0QK6sm413EJPAzaMozRSh83JlF/V
iTaMHXc+dNPWTg/N0wDqjnc7PGIL6hitiqoF1kZAHEmVCTILUm0LfBhaby47SIaS5FodamxaLfdG
Oj9nItzFAbYXhHFUQO+o0aYpwcO+2JdBfUa4vUWvjrn9GvBcXNEb9rfMTIixpGXdgO38GIgLXviM
ttYnscaKuz4ZXGAw8x8zwIeDbYBET8WnsB3QcjfwiXlWH0IQPHJNgxkMvtzkCW9xPBgKqNnlAU10
0SWFy7tRv5aHyaGqOfiy7eVO4jWnTuTYREJdFhyKy/sl64zuh4qrk4YEhbxEpsVJ9fJIwXiATu4C
Jk8vQ58GUT2F5MnytUpsgyfMmEg4O6SqNLjhbD9YnD3omx7WK4vG0hTRrIdgUysDPYNmvlyBinEg
3lTYJ6YgKzM9j/y0nHxctkszGdZVXsUlWQgiD4bjZR4rr5e3i7yZKQzBkRub3TIA5jBU5SlrstST
qp43lKDYQR9099f/x2m+VFo9IhNiM7a5F8uflX3z34vhOU08aj4Zpj2xygE5JxqiPfoFFZXmHtbA
EdlFGWIndm1EjD0KP9vDkC6w2kto8xHYog5KKI5Ud21yR8h9dkPIm4uLnMZi/+l1U30UR/WytKKC
3lIte/7xQ8UULu5Tb2TNyk/hfsT+rK1ftJucUD1PffS6ePpY8pRnFct9yGhDebI9LPkVTCvkhs+U
VLpRcuecAKSCqt/UPv0Y0eFj3p8v+J7y7JPl94yHj3K64kJk8xSrxRZIchJrsxQx8TwIofQQQyUO
aAHxgeSXDg7uUKv/Q41eNg4mFQJ6ZPfNWwEViKgcIryqBgGqCk5ZCubV+YJ1V0A5h2BeFqR0UbkJ
Ir459ni3oBfjzU6pbbV8JVl7LhqIVu2Eagn1Pakz2Y/C62EbC7riKkFBwrcr1yFwWACa2S8XR5j7
PFbGmtToaE3v+FJ1sK+O/5abom7jb49oNAvTvqpZkV5Wb8qJYi7c8rdOzH4y7kCDNihjNVmHKx/O
TkkV+6WpEe1BsEQ19onHbDN3nYMicApKdlqvGUekGx7R6dQ0OBwvbm4szOqb0vjIILB+Qijrl1Ho
WvXiKwcQVAjXklm13u2LxXLZoXxU/G+2/1pKA+8f1XLxT2PLV427woLr1CP1TS0+9bmzR/TPCWgN
X3Cgbp7AICOAZm7GKawQyGfJqoxxKcMjYmYHMQzjt3lbmuh0x9Ckb5kMvKN53ASR22tJ73pDZtfQ
nKFsmK25jEQuPwAm9xxAGQQf22VOhOx4hHCGgulKoRGBwhSe3zv5xL8yj+3upbz8kHdjS4ISUW8X
IgkIvi8wO8nknDXLRzXlEB4wSAkqS0JQ8a/gvoR7H/FTy1cdVCX3t3WzdH7rY26CxlNFaL/u8qv/
9Jtx1xDhOqiNtshY2HcLDk4GVRUkgPYSnlx+krFMPDQH22ZhK6gWpoq+n6/c/QLcAexR7elQ2Pxp
dPTgWhGSAc9irTVHAdlvZEWvB91NrPrLVSNp3w4XIf9neM0fD8gs5mqHJmj5rGcXe/tTZ+PKFHib
a0crHT+v6yP1zeu80tzH+BXOxciC6hvNerxmfk8hHr1JqhjW8n8ER1+bAKZ4Ii+pE+7kr/uuK2x2
K55oX88j+At3nDKTGKb6d3fvDb3wqolvW3higplImVuy6FchYS3J4GnpyEv8A/EqSTVkHAVua4Vm
EmtrjPfBDwEWY3HDRk3Dx88q19cgFS3nSbLzCLj/pk7lbdYvZ9VDc70jfs+dVB3v/2ezUH/kSsoA
6W0PoKQt4ptzIrpfkITmawLj+/+S39kIKneFHV/bDoYoctJlRHm+n5hE/HdwIBJ75Y0zMSsRmb3Q
0pn3ZxyP5leBpE+6M8+tx6r6XwuhvYL1cdYmfA5SKe7dfUAbyPtE/TZPk5tKO7NsgBblg7yuklIb
lvBtAAqjPH3Ra/++0gWEfg/ecncefEMpfbY8hTAy+C1YGxX+c/76+ME8Mz1z/cGdXT8BhqhQ9/SD
FU3vFSd+tsQ9Jzimi1ryCJfBSgCOjjKUefDu4CQjIOWVFVKbtRRZRAiluvIuvxMxfBcN0n14PcuD
lXwd7Ue/4GIMNmpk1gTApWjIcwn/EdATx4HLD79RAUDOxgt24Tui84SdjT5/sqhZBE6IrZER27BC
csjgW/up4+BMZqreqWL1570EAZNpJmlKkYZZhRtS5lcypePA3mcuk7+gmn4BxxVrgQTTBTIH62iz
dKz4RLH5mFy4yW/dzZ+5y/772Bpy9Jub/oiKT0JQhho7GlVdb1EP6dpwg0Vd/igxdVQDz79BcSmo
z0nKutqkMdoUtwn88jrzhnMHywH64nzZ8hynS7CkTDH13bPheuAqMED8fFXaXDwmM0ytDEaB04yf
j94AGDouULvyTiG1HMAxU2Hc+yIIsQRHVRTLeGyackygORRLpDsllzPLHtNousn3gbXkRMM1TacO
QlDKqTbOw0svaY5a5APPfRbnWp19GGpHXcH4Bhww05dCexSLCqgYU/xEuyq9uYfV8dOZJ7FiCrpN
qlITXzn11sfN+5OQh3/mUEzlNx8HZlr4xaF3B/QZLWGOm/dxHa0oRalTzDNRh9sSyYI6hxrA/5Mw
+bH+eUJMaW/vHzvHpB3hLi3zDyLHM4+7QNJWyKhFEOPSGmkSsigQS0+9IRkUjQTe/mreLCtYLXvC
+TFfwNDlKWKRuwZYDXGy42TBwmB66dx27LN6xyTnISn8AJ0TZaSkhOX/8K+IRZxTOtttOpubiEW8
fj/NMhEu89sTAfEF2p7fUO8D6UNycHJKB4dQr0WzcyhfUfWiv4LkWu/BW7vaI8h1bDXPR/Ja9SQB
WFbKIZbYe6OFTL9rkQWE3bCMKVPNfH0SD+L7QWRsuu9IHhgAAjUTVF22vzKk78P8Clpi3ye6yBee
/2mhO/No/3xR9KIrk1wijGclIGG1hsiN7A80xGk/FpH3lbgv6fFPKB9endMjspYtx3eB2XNYXx/a
qLG60YGakozRNtQCMwhT+xey8LSFkW0b2PO2b6batTuLYl8JwvFAX5Jb/Y0Ln2uPqK/hcGC172DK
oSOIcFeGyCNGk3Q24rijnOduK4PRAAa5NiYJEsuZROXsRi2TjphGp0MnsAtKhF6GbJWcc/2KIDS+
XXizfMuPAeDxuim53geQpmRBcDVZ9VunMNpo+5gRbClptmZSb5WXk00dSE9loct/odVtq4kFcIpj
Wt+Gy0A+TWHAeBFY/4pjwGy3xU+SYhodgbmLyRqpkHy9Z9TobeXsx+5UTlpzq1PRLMF3Jzw8pf5Y
orX/Wr/jM8Yn7doo2Vu7v1S8S+k+L0XPTok41viWCWzIiKs2JJVkQj41qmzkSAb3bkyElkpeiN9M
9PYc1TszgIEzLfvuZh09LDcBHteEF6gbQ1QjbG3I9vmdCcRy0B4lYMV1a5E/7NlgjADe0k7k+QtC
hqMvaxW4flPXn/J4HuSZxyyccfbRM9mXdqPJ7vRN+Ka/h8QKAcCoFFxoUrPgMpo9yvQBfUVN1RWY
Nm8bw0j5UmCKUINOGrck9Ci2O6U1R0mzZj5LCmeJMzZj83oJSuLPd8s3b68SFF28LA3B1/Tflqes
vYFDjvvwR6yNQaaEXtnjsj9dAevu6+8PRDZWVMUenLbLNU3RhDwfsoYYKt3n4dNovLKqfpWTMWTn
wU2NnjaX+gVbOmnEYzZRn+UAurB5pRDk3PTRKNUsZV9ShE2UEahU0f/ElQfrPldfZevHJRlRcLHi
B8bBo/cjssKMuq+wpznOBSE2Kq2YvRPB+5VmN+gIdDi0UUC5wNLy2UysItEv1AyAyQVf/ysRMefv
7gLh9qUf+h1e8LgOkzCXbWaNMsIUVR9v6BrXi2fNSIZOEbqfzRzqS1F3JOskNBMexyjEpMahl2VY
fFBFa7NN9UIApm9o44U4QzEg+KgH0ZQeY3K3FBqky37gg/VHu2hh4z6xmgUdqSfs3qn3ssrvvgwv
bj2hi7tu0oDRrEnHDmr5idS3tEec3mq77XEq8Zh9iXBt6+QGwhb7/0R80FOvfJEYU1MQKA0e+BPp
1GojkA160EecVZsL9cl2kKDBhPLz+lhYvsdLwGacekFaRc3yYM8q4h+E2KuvzR3eR+Xyi9uSs6qc
1F1SvpXGZ6OmM+ahf/srDfXrbn/mYCFrZNERav0FujpGbNR4cWzONMkkVHTRBsLCDIXbRPiV6Oz2
bZks7iAE4T+intWWsNsaCP/2d73NC3iq6FkN9iY747xSCD2uWfTr+fqgAwxAKMLDzRMbWRXwO6qZ
qTE3xY16FtIeaJTm8VtE2TzqL0CRJfDu962h9nXANX44polqdQD3Cr2JBKOWmowjiVJgzc1fxO7F
dEbEOpb+r9iKoCeIS+FzUtEBEsysa/YhF1gWav4lmYWP1xZkirrwaV81tGHS8rLLn+q46qtvOcWk
fkOlYknSA7QGQ2qvZim344XPFeDAu5Uswk92PxHYdWVqQrvCC8kXFmR6YKVxd7g8PYiszFbtPmX5
O6tYznfh/ZFy9XA1rdOuu0BtWG2YS6GNm9JCPC1ahJGuXm85PzQcLSAp7IPPJCkmevR/7Vred3lh
zWgU3vnEUZZBqJtymxfWIFzHyAErwnq9gKmLsjDad5VNZmUK9RSp74DR/bJOjxqBc9SsB4bGCNqL
lQhYKcQfBV216ue/OoNAlgkWfWVRl288wdTJdOsYJDRNOG0ktCvL75CgSWfEtlLtRyN0v5IgiieU
ysTwK127Tqqay2iJC9pgqGazwrBaUHBmGG4lI53/qXY43/Ezi84jyTqtp4srXYVug8Wbaf+xnTT0
CsHP2XiSYaQ5ATEMUc8L2lnUBp8Kxa0cNuz+EWgNG8jdisKolua+kbOZAdvPjEmk2KDMb1dDCnMv
h6HjHpCcxtPvYHHbrdkumH/yUpVWgqJmOSxaj/dghLb1SvRioatTFToNQc7Kb6G4h/gdPGkd997s
tj844jC+ULF557NEQMRg3AB0Byl7mw0ErP16pW48u0s5TJvZnRiQYWiJKX9LdxLGR1yziNXHp2DG
B3ir76cLoXLNxDHoeOJWfWQuWbPuFIGGP/bpvgnLFOps4yK0ddlebYLoAzi9CX81g4WEACa4VA7v
7wrdA1c+0nA8RTpA1rBAlnmouqhPwCmpd0hkIY/yHyrMW996aeke1Q/LcvQNSN0ep4GLgX0p3qKX
9lOYzqc+0vzPg5zTDI7VJafcNcWLj5BFUk2WfIWcOf2O2j97F1j5wvWoDDNOC6Zk4RzGD+k48fL1
IMrdbdEA8qDRPMr9r8NNbrViB7IQL9IKmbCe4ALwHEdkKB3dVB64QrMXiILmjrfjP2G5l9f+g7aZ
NCBMEFM7eUk+Wa4CVBOeiRV2uWpnFe95qGc6u5fRGJU3kizfZ4AUN8lOdZroM8gkedDPZESQpLha
vixNzmFjUrcxeBo1kMVEYOyxRw7iPuOgkEDwSGR7bcF9lhwWjvMXAmytPWaXYbrxXxkPsz+WmC8f
JA5+wlXPohRmXOkzh7alTWW+X7tQcoP9rzIAyrcYmvgGVDCW3Ldo4oLUnd2BulCE0+dbpK/DibJk
7xQP0tSmeaKDgu92SS2xuwkbmRt5AEuEGP/stjrG3TD01BmR/sG9bIq/VFaJMc/kEyxOdP9+I1Us
vXWPMYsyJihP25msSqNmj/UQ9zNpd5vNQ+cY11iAEmzydYaAXRpcQObrInYLDvNrcVgAMO2nXewc
1Q/yEqCNMjjOQ77kuKu7kgTBVAshDLHFBmxMOqC6W2MeX+UTB0NsiRLlIAy8yTZNi/mVyvid/96w
oBsoDAb4Ydm3CxXMyPDcyZ34ac2UAJUazrHqewl91EIu4hRBZ1AEsnlrxa7Bsofn3L625T8Dj6K2
bKhq8p0cL5OaOvGaKXAmbpbLNtZlwoF4clF3PuVYa+gWA+ajxWDkJQnrNkuWQ+DlViVsKa6BTT6x
zXfAHhd77LQIhbXNSQi9M2LMsxNq8KwIa2IlNMIUichKVi8jQru914dU9feG+U1B0ABtmqpBrU7J
R3u9GIn0ix+Z6LrYcAGM9Ex0/UtqYj+VuMzb5mc1lSshGZkvu99E8laGOGEHo3qDxAAsRnzo3bDC
ECtz8u5A+4RCnPtHi9R6td9/Y5IFLBYMmKRhF/WRlv1AaFp0aBR6WET5msWFLSuEd6YUDiFtyamm
f+aA5DbbB6cpSQPgOZzLTzuOeGiHfEu5ztcjgce3rfw9ACoAVijh0RafCEYH9t9jRd8ZEGb3u3MJ
Ua7JSVDdYb2XNk6MigD9+XhdSyAycCZ5a9aFB9l9eiG3BAJ3vacC68nug5Qbbm+2NExi2xGQ+zWa
WuztbbGK+U4dr2VK1gWNMYvsIuy7uaM+RjM+Ko4YspgpwmIDqKSAJDF4XiUIHgu1+R7KmfMWiE3L
N09z/dDxJ4BrETXStFzAzN8KWrukloX6y2+nO5OAGQFjVczrozMl5o/RVo2DaliYr2VP9Ru7+Yre
v2YsGmuCi674uIBuS/7Nc2YaJiyesDSyITiiyFwCSLpO7aqLSPtEvnYJ8i8ttpJKhSqvE8oSgzty
xmWDQ4anD2x42VJFQEs24+OtUipUyLZ9KhoYd0nAugBMq2eXtMxJGhE1D2eQnlhzMpABihlHQLmp
JDCvyAjTx68wkIK9h7aEw5AMa0gXQEGEM8gvQMoF5z37pwehGY0avMv1w3EHd7ttvCyNTfqy+3T7
fye9aLxNC6tD6R0/9ruOMqRD4hKenuBfkQPNgJ6LZ5PHu/IeACck+4pfm6JVFdXczHyyi1Ls1gm9
N2+KINKqHu8oSlQrZTPRSXO/reXZPVVq/VQovFVWA7Lv3Yac2OZlTHitKCzToUt6hwkqL8uNgebT
aJCdhFkJgFLqhYYMuMCn1MjMAC04ceAZUFrNjSK0YWOnmy8fsB7cR0weJcWe+ta/FVDzAaAp4Y+p
BjC+i1PZWGU8EWp0pfGun/xzTOt1RqqlfpwkXNBSgtA7n9ZMtqXkvySF+GbWCcGeqDvC6NVI8yTc
qVj9yFqw9OXZgT86XOuIfR8DU8o7MUgHO+HtPozkXjU5PzYFJkOYb1qpqbJmVMsKSXt4KL1zg8KR
vBYWn41I6RCiqS81CDBmTbPk1uKVMKvWhBCZmTm0fD1oZfUU57eq2FyscBezo5+XdpYD6u2DAnhV
S1AkAzQeQxQQLxKMjHfZr0bSOeqtxskepC2oim5GBIeoy17VLfbyKvXh5pHrqI8x6Vn18uttBThW
rjLUOz9IgAVki4GHBbo/67hbOStsqxJJi+fN+E/DufGjGJFyUKh4qYTSIJjGDmTe4ljazPrtJnTP
QYvVEaDotX563vgdA55MXapz5PzWkS0lcDCjYTiDJyGZchHwt6vux/HueNwUexbE9y5FxjcnVELk
uVmSemyrZptMZ6zDVgtuKrpySoyHA5jtyv7Ox0iWcTRuS5+LzzSBZKmQyTeaT0AC3IlfJcHHtf+x
qTqRPnTJwh9L8DCmJKidjIMSOD0jFKlVZfjyuUZaiv62qRZpxv+C0JZOWKaHw/eUIObb9ysuZ058
TkFV7Kc7iCRyjhJL5gMWDNs0PaE6dOxY6iWRc0RTRz9bFip+Rh7OZQcN9QXEgDjg2N6M+KAi3t35
O0u4SCJWF1neGogQETOFb2tcMHAiA86qDyTX9G0Z1aLAu5h+6bRVh96ieLDzlCQjewdg3OLUOqGZ
wNd1CBkc+tVtOJIIw9GBqq+yJoCKt1bYxpsFeMvcapIvoqQnRc4hqhOMKkd/i6Rc4GRulmRrGnTH
4ujKBm4YDb0OnU0iwaEfagqkO3txVtpvCNbjXbDVUEywIOB6zjZ52ewIlzEdhCJqv6+rsQ9BxGWf
dJDXM2jvWrPPon2MqtF0Q83SGq8WDYD9+xqCFOuSgqPMLFADRgix+NJAiBj2L0w6uU/KEHc7sFZC
QmpQbfShpLt6xuqzvW1WNTlEFGcdkqdCeBj5ZbEuukMRU1brySOgvT+0wuUE1M2IyE0pyI80s52b
4N27ZrstilLECy4c1VrHmD7s98jPhukZtjBS6u8IQ7Ouqy5gMAZdaBYJthd7QFFQaA2RZIFdhvaB
oihtfhLJe3uNrAiobKpqg5jtHUa6EPQ8AmTTfWaMbtciIoQO8IEYhfKyKLpeC0Q88b5sIwKm3qxX
VNngdYjnOBPBHr74LyNWGyLuUcWyZ7O+z+Hyz7KXUgCjaDRy0SNZjIbsIkvFlbNeVWYQZR00KsjK
j0+UGqSvQw635DJgLRbXD+E3nEKNO268SCMZ/o4AoJidy7K/uvS7wg+bv94pXebT27UrZCKg5pME
o1ScznTUmR/uVYNfP0in1/I45aQ22pe49P3NxSgRTgFtsx40RZioSZi1qzLesEChmzQWwpzEeime
75afdDgAIKm1PB1/W3cPQA7VU2E8+Ki+1q0XAL/scYgoIucMclhHXUC2KJ2TEvK2v+6D/QvQXAvK
JU0g5EDwBaOtKfqM/kec9S1AxUwiVV0MWUBBFyjvRivEY9rsLOOndRQhiz7B0ZBGm4cd451OdoXG
vJnL0nfYecnrRTwk9RvKvHZxnd5czWEQuhEGzk1XSR4coxw8E4Fxp2Zp828j/oUWs58kXraFe2wn
+hdU6ijx7BrthYHX33pbZ4ksS/ylgAU4vbI1Pn4Zg3j0gxkPeBei838cJ02wQK1OXWCoGGnYiXxz
FWD9T/r+wqUKF2BX3Ze8Rujn5Db65dgyVCWLQGbRb62vQDJB/EaxQnW4/FAtdTAUbduNQO0dPfPa
A4OJLAxEaPNFPGRn1lp47F45OSFNjCs61QHICZ5R2Badz24kc2tsSrP/biA1eiMIsl8Bs872+I/P
UPjF2+RnS5023mwvPwv/fT9ru/SSKSnzCSlkD72sTgBgmXlh02TWCAw9VS5AA8DE5DH+LkKheVNw
Jg2jV/HBz3Nf+thTxpRT1mHA+AVsyJPoptCBV3FuEJ95H6OXav99I5wjUhKXUZYEf1uas7EoLwQ9
p74BtclXhcmamfOvgSFy39o7T2afgCtWx0sAABmZqbUlHtqet8eUoIPcZQkpKtkbm8JW1NDuxOFR
kpwQyqInK1Q+IV0d8idyQZbUIT1VHmk2cIUprRYGGbtQi85Hr9h3GGhQasSZsMwQa21vIdFAZrzu
jsuEwWUwJSWRubYwI4mAjOndbEf8DXXl2VUtaubR3Ntt+/c8k0v3GVFoM58p3YSNg77v5SQFfGTx
V5ou7vM27gAJiNmTPycsVEUKnTxSq7Diy3vNkXdT32J/oetC87VL/XOXTSXa34W3B2UQ8kpCJ1OY
PjPccsl4Mi3aYyu6lQEpRL9DmB6rpLDDj2Ye9m9i2HRPFIv3E9C3oI84EL2J3goEUpVpqkIZnipN
42gsbfQO9xkMdMf+KOvh76Gk7QUN05tjKUr8+2CYjluLVwkaEcULAz0DBpiilFgmQR9ckL2+JMMs
//476MvahJoCajcFW/n0GlJFw2dX/yg52B7WNGRXpdsFIgCNVK4AzIFoyEXg+pp+Jh2oXm7B8/0f
DKcdGKa7U4ANEGL6jMnvb9cnOjaZhBBVw7JgQKJ2xlCCsvB9c92fnSmEnYab/1c3TevTxkyh7wCy
YqdFhbMsuT/b2PTEi21KG/rU6kOJre17DtgEAVLzNTW16aKDqA/YXsgqz165AFZRlW35jXGShtLj
2DB6csEsz8uXWWxIe93v5aqBnNXWRMz0zvPm/NHwzHKBvMWMnhfJezLWjxE6/9sYOWd6C8LsX0Y2
rrr1QI/gkd3MBx9jUpfqiWfCD/zBDvp3Zv/mY7Hc6WgjD5QZV02mIz9+GVeQg+JNijwzCnHAUgQB
5pkkTE3ogxTQY+EAot2nbSjEjnnaWSGK9tmn+wuQUhxxY4ZVHd1hZ1ZxQrDOrzDBxB0lzvNnqt4h
OciPGvPOUOnaCSgm+ZEykSTNdCbgIxIb68rfQm4vRKrjj2o7ZKzb9wyQotEz8x/DLY0YQ6WnaZsm
k0tmm/2WUyipt+B00CbZQKVPTP9DwqBe5viVU6ZgTBQ82Rjg6QZWCOuNjc7MyME3HbC+ZAJmNXym
TRL/krMc8/1rSycotyb5TDjyJFt4QEwe0lhLwbZgeZ0Cyt6y8OX+IuuvM5LRSrcNLjD8yCiiaQJp
AiYgDrEWT87UQkhE9hdeKFEkr3YAz3ck3eFnf6Zd3ZFTitopYj2GeHrg03iv7e6vXxQQ0C8yvKmH
/TxOtAE2VUf0BMBQwTL2oX5kFEiieEOvF1xy3shCQUlLzOGGorIGJw9wjH/EF1E3aFgDSedjnsY5
b/tuZO687vgCQz6hhIOYtW4DYbXUjS8yFgKmpbL1gL+tgRW5NRPZCbC+g2xLxZ+0b0Yqj28tJl0e
uLZiCIs87Z1a2JwjhF9m8O3RQ1wCcsCJRVFfGAkoXuplAd4fjgiEWknNe6RA1FLYVSDEDdSF1/jV
visexHZl8JJEZrFJcecyRW7i/b1GwQmJOlsDe0bVmYZGmcc0iI94Dn/ZaCYo/ADNEDqUBU52Ow97
2k+z/UbjxQPqP05LKun3XOrUtiob0WnO6i78Q7DT2dPX9mULRLjXaM5m5+wLkUAZ9P8lbj5YGE4z
gxH91H9dj0RZW+ED+2/tIJmcEpkKQpLF7scYcNMAz0d7VZ/n2URAuFhFo5xdOsYOiN3T0thzfF/9
143JqlA9Rmd48lqu7mr31GpCF8wGn3Vo539AFCSy7rfMAd06uAdbPMNdPzdqNAGSpJ0xvwRgkowG
GZ3qonO3Qwxar5HRgAkxFTdPzzc7KuTg8IcWi9HHZjBgNENms9EmnDf9ZJWi6SFBRQjkz2lh80NT
LhrfiCByWNoBwah4qDLpRG2X3nP23hYji2adAGiPvCh+TIDpnOyb0ftkTSlV1EZAUO3Syd2saRy3
82s8NoO+5aN1pivMhcHSw64NSvHspM79jY8ToVogXk1Yf0NigRwP31p7SW1NSbq4eJ3fMzSjvKUK
oyibRJO6IKWMUTMc2PTp/yC+2HihkjVvUhlogxt+Vya8xmgC35ThSzcHBx7j1nP19YSgIHnugL9c
j1aO8rIisj2u27RV2xQKaFWDPE1go+MkKjlsg1hoC3VNVjxZ0XyetgwUu6/sr9OQ8B9IV6SlXi0r
DT7ikwImYIAUOp8iRuYczWAx1/O53NjONMcI/wKc5fQRq7MZDlTXrPtEqmY5RnWYRDNnQsXgT0uJ
k27DTcwzg37bqBv0MCW7EI9nw8xrqeJLIbC/m47deFp9G0EHka6FJw06ZkY7h0OOp3nw1/mgLUcj
UPj9wY8yn4X1BczX82Lr3y+uZu4pC02wTL65sQmuGcZ6Qdcq7uje/eKVSnGXomor+pOcdelbLjtg
zpsanA0Z+XBFphCbuIH4wGvr+m4rIJrywbmvSgd7irDItNU5ac3UIbaZcwNTk5mpoSVrc6aLAl01
FuE3/1CNRIEVAmsrZmthLqD4aCk/rreTyZ4fUk7LztCsZlodBW32PCwVukdSTVfcGdojToT0nQLF
D6XylJsdGLTXDtiCED71pAZJunnUBpfY29e1ZyFEkgOBHpuDGdr6XLkg9uZTzbvJlcE7qXzN+n+K
IiNKCcOkszD91SIGK69RNG8RTczkJ0e7xkxbGXY4JGXfruWj1AjBv+H/sGYaaDzDsndECKf97cFx
8ZWvRn/P1LUEEup/LlDt6r34BNOtLuo3kzfHFnGpL1uDyIlvSXkfvbJHdvLZr7DqbuXH/MEEkFDf
tPokBARmjeBCLV8IwoSo8KTVtcezAhT0/CDOAXPrPzgTomlPg4s0nBzsN05ZmCX7V3UrExKdvlG/
+x2huvo+o3RypyyllgpmL0yqUJQPLUeEUDCWZabsSo1FBtRBMpPO08CkTCDki/3s8hT6dU5emhfI
ZRm/L0d8qj18g6P0IGyRlIPcjhvlIwyVVXnOODt3YH1WgcMCyi44bYYldZIIjIqSlKSXeD0xEcHx
nYvKobAaC703ULifPMeYo4yOZCZWNEImhUFlwAfVcWi5suuW/Rrldi6y5gaWhmVJy3uYq4/jlevo
s4gjDZJwubDoneaT5K0+oipXD7Kas1vR4s1LhArys69pFAyRef8yzR1VqUSg7FvHGK2P6tWX+kWN
qC2ayeyhF4OFnuyjKtOIdmgLJNqWkjAA7k4jvq4FOB4nYCA8zqPoFc9nB9zzrg+tZ0G/2zz325Qf
4dmXh25ZvEmzzgVGaKkIxm5Ax5KswnTZGI+sXL4Pno+P0bGSFhqFWxfvlKBrluxvBaV8xeaju6Lv
WG4VlFd26h7u5qGRtSPFGNAghVonvqwhIW9XXStDm1k9aC68PExtvUmKCi4UUFVsq+aO3WoALIDX
KpNF9L57Tga0y1DmV9jTPFgUiDXdH+MRr/y0AjExAdCaFfvl0RF4oGsatp5/3bGFV8uepDoXcXR1
zjkuR3Ub6O9RSggFC1e/iy3yvN0hQ0k71Ha1lmQhTPcO3Vnu/lU7H0Kc2vbeDID/POkkMxui74gE
MpZZ27hbTkgToofZDqRipm98VFf5Zdo8IwEcSFKOwjmyPWSNVmT0lwWwnmXXojj765w8CUxxbaJB
Lesbq8l2pR7RwGCWYb1znvixT8J/sTg4ChrYGpjcO/mRAsgpW55PfnPP9FYA9UP/5HEtedOClXGi
XFN9jI8oMa3JXZg2pE9CFmtMRIWxEyDZebO8FnB2Bfg+4SiWF8LZbgguUMVbZsWxNzLGvYR9w+ny
7kiKOokcCmg3wA+YxgfII2lDDJENL+VmYwyhoqAQs9MGmca8U1fQksjvAuYKBB6XCdGNjOHdqmrx
IaeTuLBK9O8wbwf8aEkErfqu04oq+E1mYLccLm+kOu4oPz6FHDk2k/8dI+kosbrXKf+l8wx60mFt
HUbZG5XNoChooVuRQahRJbCkHBg1ktfyE2IfGHsB4cto6TIeSw8aaz3Yf+BI5hqIC8W3blCAyn+N
rZqURaosWwluerEkWjX3tbLxX8j1z9wIanfgC8sqXQqwb7FhC25ELGHBXkY9iBE3OQzdIgKEwfFy
z6zt3lIL7Wd+UWzBBkOnozCg/7ar+JcsF6M0OAbn8ueVv3GjddihQzE1wPcldsi2WMw2tWr+HaOB
REWTBomgAfK2dqfbMrrIkyg1d1jjv6Mmp3jxDhUvB1WS7HbfX8sUiFs0XSfbxUn/5Wzopec/e0Yd
VvqnvsukKhJsb02fSug3EmDSKz5oGaL/CcSEhwyLf97dy7BuzJz8Tyzv/JjTGXzlbMpKKFGgolG7
+bE9XzI/3VOyhpfG88vmK3oBpA0AfFPONLOXRSpPp4VVTNLZU2wZG1lxSdEWvRRi3SPEc2YdZWeA
cAgD+PLSD8VrhgCuuQUQ7ZQfI8rvRlxUMq4Rd+rBPnLAIsp9+OsB16U+MBYmLrj+E0XG0WfavKGE
cRwp659rjq441emlYC+fI1IolG0nhWjRveAVFKxwp0MOCjAkpT6B7qsdB+yvPlK2wNkf7PmB2mf8
wqyyZtfXlOUeciVULzYqJRInaf/+JOIMks8wnCTEactANC4pl01/A8SlgExAKdBRHkbJ860/us5y
KFSwIRNL9q3lHeVwJjQ/Tf/7mDiyW9cwHKrDL75q8njlgGYNh5iW3eBEOOiJbzF3/GbVNh7SC4af
r14G7quswHr6LRtmE2K8WMpcsDDfZfVEUvrGr44MsbRLznIQpdDdF3mM2SZR/gh7GJYdkCHcv9sg
BV+Ndx5nUcte8UPOyFBWgVK0IgN7FKXFw/j+jsQcrDvpSiwCyDkUUzV3ebzZAyS/wxcBrco5a98T
LgjQDW+pOimsZqNAqlZim0wSwJZpsNRRNAX5f7VF57vBekluFVkLgHFE3ql5p5KuJMc5BYRw7ypM
qah1fVlcGFjunMLXrwwMHogBuym5qnDFkSM23z+DwQyqM1H2+13nkNo1vqFp+fQTFco6Y6yGPF+d
LYolMYtN12Cm+catzbKKyrHhEhSPtJXK/CmHgPc7ZSnMAtQFfLoLT4k+1Rsru5WAQill2h0vPqBu
LphoPga5KSXs2dnZnkHgEgjD3ktLEkANEWqNloPnji9SgjsIT0OrBeLUR9d9U0N8HgsepMh9l5cN
LQC0x5y0UNJKSC83HHxhpe+YcwzHCvG2xQej7VFpJmEg53EMjytmNMYKmoeTvX9DXLsc+Pw9JuaG
vC/MzIprb6OdDBD23gdu0i+kwRXjeoceHmHngtXRWBf7g1NffBF7deSHo5OIM22d4q3z3tyYwsom
0oJ8f9pBGyirnQf53vtdASJul2k75GbDBM5VlJ3woy49frsCq/K8IRE+xF/F9sJheln6wLMLNzvf
MoGmfgiKJbgGaXbSsfhqh6jDoDC3ThZcWA+dUOv0xxzMJk9YNVnHKQjO++O507f+6NgEowl5Ys1h
vChyHvrmAj63DuURnIOxdKTkD1gApp5pdZOfuapJrcfyusZlj/DfStHKWsp+MZTencCoU2gzWmGb
1F+Une3eDX8HW4DKbFNMFfaTbDEawxg4oYsB9c0uS3TUJZBA7GDQagpSoJ5rYxcnrkb0HckI9zXM
JivNPGAWO3nvz6Jcfo5bQzYWc6gVgW64TxcaV/FODYlAYSP2mve4kqMI7Yxh7cGU8/MY70CnHygH
MwFAisKv+Ub4QLsOvjaZr/Prm0ewASX9KoDR/HJKzXwWD5+H7OYeH++KHVbNKe9FtQjztRfUu1lJ
FIJXPbLfw7/MAkTJRO+VVMl1SkIH/DaqL0uSpgwNje9dl2tMzqFp6kbgHv1PWt8PCNML+MRyNw0o
/fpzacx89A1z4JiA7G8/7mcsxpDWQnf+Ohp05YAF9vJICfH7Zva3Lje3Z1Vr/K+/gqfaXn/uzU6X
hJRYVwkTXaWbbRzB46Z7+aLnPmZZPLDETx6/FqbGxrnQUOrh1GejYaezC0gMcLLBzjO6nDGEpCfa
uP8ylhCbEsofix9xv376aLAWxGEaGms3OgBRDkQnlcccYMSo86VKo8mweutmrVnKM/60nyrFZm63
6BZeqSgrak9fdTXnzyZ5YUukIrCqp9tu+fBJ4EwG+wrkFP8leLZi0BO+JCY6OahHiD0QUJYDrZF5
whaOmjKREX7yGq0npoD0BVB8TENgnpFKE31nUk4TO7ZAtSLA9WysczRFKs59OYpFy5ZYyRKIi5Bs
vQxvTm8i26H46CeBBdLMe4hfDfk1UgB6zTY1cYrltaTvDVIKJDhCuy4bW/pXoNTnhpT9kYvpG1r+
diEcBsyjllb/YAMZaOpRiVpehXHpLCK17a+ptDbA2qr2QY3upDUd5u3iN1x+2nNkkM2gp/Nc+uJn
LTWBuCNIaFFPYOyuc/Xvyq8soFRjchgptYrk2JI1XEwUkUhDm33qrdPscWEIwbRvKZqJMjjbJle/
Vh2nJVvnjILlYVACaokIhNjls9AinDxcD8ptLI1aPIyTmXe/Nu/8beO2tmAzcNXysW8l0NUYrdiC
xTLYN8VlmpE/zJ4L+tDUD+iknACaTlj+U4kvs+K3hBEM+o2PxSNcQc0fWe0MgRPKfoEbBPXGPf2w
IV7VGVq40SN46TH9bppY/FCKQ/y031fHig0mq1rCvmiLWN6POwWZEw/FWRtfj59grQZDZVnpM+Bf
zVDcWDJ8x4CCiQB3Z5cEaMl2kjzn5c6+qrspCA0/FXG7kAZDfjaPl1Js/L0zQckXv7otjH+CUeZe
QeFG3xUMNZ13XqY0X8IQzlpjdj6xsfCflzC01YF+hWrfCHiilpzmqzVdJQybPbw/TQ0nyPpMVsgD
nFRG6qZSeFkOqVo+7LC8YhkSfzGEzKf3lxbMyjFrd++inI5lu/TeSVftsQDpol83mk0DMmDR+snX
9ot0wpHWGR7IrBAC4/qujR07k6ZHtYOVP4McAPt6c37vG0P5UHlx82NKY+0xsYqdnMXqF5m1HfQw
6kNYNawwI+ZSLh6uoP6Av1UF0QDbZrth+OXPTtMskoUCZ4pWhY26R/R4HUOXR5Th358k2wzvpTJn
1pNTrAKWVME9FeDML9WonSGH0H5HBpFHTAo8ETfqfyQoMfkwKh6Q6UUNF3TE7M524zTDPCx8J+6V
89EeV4GQJ7Av5GOyGuMAp22xhknT+iynTBsUKMy7XnF/uHQh7/b7tpkdI8dDokn61BgnLqr54AvR
V4B9h63B3qWD7l5+YpVAH2vy1b+BlR5WySEmV+rX9XksUY9a93MbIU7cwZ6u5MZ0nSnAlcKuuCww
Eo9cMjdyfT8AcYGjqdfKj9niwokFWlHQta05Q9ZTrH8zKbc4kOtIO7fRBXWHO6U3FVk0lX9Pdb7v
xtEon13qH9KLDUW/UqCPfhEZ78mlChL+rCKplXLC5Zbsr85qU27F/Sb2IK+wgrQxu37h7GC82Q4k
J6mH8l4lqKYLKV2J9nFbs4nVRg7zukB5lBs5+ALCt2usJCg+mD/qvNQJsO8IgjHHXcSmn+mGjGCT
Fp32+wRGgBoaq5lJCPgRQcwaxAVMqaq4x8Nv0e9bbHd4sK/jhgRwMSUTJEST3+jKRfUopPGO4su6
m6aArAo6SdrYYImgJHJOUZM3vEmabSGElZdjYzYi+eaKNxmmvXgfouVkcAU745C3uW7AQTHmCTzC
f+95gMTw4wwQUsrG/AiCeNq3JsLhoTgAncmeab4R+R5Uxp0Yk67hLadUmhi5p2qqfN6j7EMUMUvl
3MTC6cqeMc41YyybOvnhhkxDVpiRgjDA9R6Ye4NZuxT14mKrqrIUqvHmmNvCUjnVoBOkvfLhagE7
CF8gqSnPztodnSZUeJx62ZIIBYTa6aA4lf7ENhTuAwDsTV2fWWwXPC0+5cTm42jVmS2NRJKULhts
9dMmgmOMCYEDiOo2JkpWGh1nsN14rgCGI30rkGxytCK6OPwQZa7rWQi1SK1rAr0oa849lFZENiXn
Y7mO0M8WQXUVFVpcXXSFD4mwbzzMJRTnIkkWqYME5JOMO8sEoGdnTNCn/AzZ4Ma/IsOEMtQXOwnR
h62z1P+5K6tU4ReewsyaNE0g47DvNr0ALoM8of8eSXL6glvkXy76woBttA+aAy4Uy97kGetPsGlE
HZwpkeIjG0oox+qsCf92hN7Ko3GHyFGkQJcrSmYyCyKCVfiznxZ7YsB5jfHOzDLM067XJrdcXvdz
DuCmXkFhznJJnLVdmq1LG2qKQWkw7/Wl8+nA9RYO3AEAgsB88uV5JfA1DB9P9B11FANRsHuwYecP
qVRl05fntm1V5bv8oHZwYqJ50FLKU8EEu/fC6dYEKnPuoD/bhxEExeO75nMgDYwc6+Unl3ErYlbO
Z4HtnM0bqCawGlY7vBca90gAN++OcDXOIoW7IsrLIeEMCx9QHx1Oq4rSw/UlschextvtFasHYX6K
xDhkUlhp4a8I1WtZN0ZwQEiiKYgK8iE2jjkTpy72kxL8bNB1h8GJysuUdmFlnoibscULIo6/ssF1
gMVytVs8gIfg+czifxlxka2R0Q/HqYQIpWZdOf1yjX7pYXYiIZbxjiHwDkSSdvKrl5K+r0jtrtpm
n1Gfli1tQ9cN7UnX3XTmLJF/5de5L0WPGuxd94qYey+FWh7Y7VOWp0wb/AAOa3iMmighirH4pPKC
NkIQ/j43IrvnkUeP7YB7Z41syYfb44fSKhzmMVtEuV56R+E68B5JMl7M1y9bH/aVLdmwySp2/WHb
3WHE+3WgmhNrJ22PydSnMjvp5e+IoSaTDQoTZfjzn9dxu5B4LhLsfokSDxhc3t55GO88NUzHc4A3
uz8oJHuiMqXK2ILud+H0pV5pSdUyUS7QjNIzcXDghIWEvZwGleKnWazQZGLAdtzFvpPCe/a4gfR9
EaKewmbkNtWT3+13CpYJupXbmQMAe0gNVKfebEpoiW3YonXEA7NcJ0aM9heZ1Q3rV3ojnVqIdT2B
k+ss6eccMkIU0mN4GtLScCNbjZmrePMt1T58xXnh88/L/+b9STvbdxFrH0scRmWDsEqfdtx9+08a
9iugIy9MSYUnuhpnC3rIsoeJm1wsd6A/f1/DP2FjfOv1cSNc8/y8efVYUuJJBZbtDm52qxtiQ06S
UQVfuLCBJGWbIYOtRhiNu+YkpdtgOhbDp2LCMcxRx3Wp0AsXnQJldzDaZUcHZk9dldsUGxnuVibd
OPO5WaxJry9SKMawB7+vQRbier3fxXshBmxGsMu84KxaU3bsIt++bY6EGZTP/wX9hidQj8LBeVhx
vD8stYG/vJ465TyOP8ZYQMhGkqlyrQPr4WUuoU3uH/Sab7S+vxQGbHS/hY9SnEvXjxDmtCOLKj0g
CHXi/6csbe4fwTtpoVAaYrCs0+vkeYZelDDmGygfyc4gAiaO6VW2ol9XMFxXz4v7RnPcksqMsKPE
1wKd7lStB4uVJBO3c6C99/4Uy7eR9HVPXfYVvZC7S0qC666VEnX+GYdKN6kkn7yELFyKn/9CJupZ
vVaWGWzI1fq7YgYBqipqgW+QjT8JFDIfq+FRkxyD8fPwJLeoB5WVWpySo1FLpw0JqCvF2uoLStlj
TH+MYK3wZWcqIA7vHAoKDz/45pz9lX1f212iMaHOuDAgtlNjBy1PaqJITi31JUJapVySeH6T/6vc
eoK8MZxFgmfeXJTZgm4lpfe1Y+htNs6AdgwIrXZt+XOCmPY/zyifjMxQZ/lP68IAoe0thhGS48AU
roz1qymlz/0S50d6bX04nTdQO4X71LaZjwckJD513GAMdAa0tpR2+y8CAjfqmwx8/AO/Dh9F80Mz
cMDyu0U+/wMlyOiNnQgi/3CZRHX2VBPeHWjWnV1eL+f4eXeC0dypJmgobD77nrrpdaHCnmLEm8wB
sIm83CAVUt4wkfI/NXeztvnMxU2rvXsUJNaS7Z2jcgLII27F4qHln0g4BCk2JPZBbSMpFvt70o35
U0ZMB9lcXv6yBHVSsI8r6rJdi6oOJYfxll3B7oKupLnKWZc7v/+/c1NiRQdw9mwV4P6nlc1+I+CA
/Vz8NssH5dTLt23/wOwQElM98G+RC3nV64Hh3PhlT4yWFGRvPnqDztmFIjVucM1dKOI67Zj/C48Z
U6TRMAcC4wjqdBHDwTZZ3ADM20eJtMhbcyh1yZNj8zVEBR4hcpdPXysLQ3b8HvHZw909hDmZbcv+
LH4GrmJo83Hpf8sTFlzJwnqTn4thMAuTDkyB32VXCp0eSMxGXRNoER8SKqS+t5IF9fMnHtnRyRcz
jBxvF4PRet4RAmbHHJ3Bbg4nfTCG1zixFf07nbHPOcaUA0iqtSY/+lOH2YcpfudK8FrWpMhBvODs
qZOXPuWauM6xjlmYnMx0regS58ROU39KdVabRM/trWRDfTnqecsl/vFimIEn/UyOdMvmZ0FQpjWB
wDDuzxXltr3pY+8RrLWYYNnbEFow0mJo/HpUTlTDAgCaUm7mmYAgtL9j8eSje7dsctdrBrVYe8tN
6kptEOJ9xxb1OTedZjUw6YlKM0JHKhXNLrQ1L3a8m1OmDsr66Rug2ifv9g3QupJAQgWoz8yRslH8
l4HygQcDQVHHvIiTah1PVsQ6t4rpAwTVeZSawmpNYfyQZqLS4fpnRrmuH0uvb6YlkzmHDOWV2zXm
cywcSwSaKJZyuUEWNiNo3pcUI3A/+JNkud0RvYL+Yd718JvdlzeSYS44uSrcNfRu6R54VS4gfXlg
l5i9EcFVRXbV3SB3OApeFABzwryXP3a+8omkjmdfM/mV3tf4lLsFPR2lvbILrW1T2+zy+0LWEDKx
PRqYv3CkDkJVehMOHb7EJLyzgHGXqmBpxnBIdZR+URvMVle0IIiDdjPsnCbP2prLmRlUjVhrWi1J
xzT/ZXas64hzylfDpdEsSF6S+w8/Z9YVt0UkLKqHYs1fICMD3QjiCm+YORwh4QKhMoLAXDIpCWnU
Y3c1x4PMziq0WKZdvmJ3W2RG+9GGoTHpIS9Sc9MccLEcMu5VD2XTZj27iUtKXydfjtJP3En4fvTb
C35xgoXkxi2WC41N8COkGz3YxAHrcmYl2ygDYpknmKr3ZGYuoy8xgfncU6AQcI6AYVDq6ld8S3eN
Xxedkli2LaPs99t5NbFD7ikUe+TbFveW7o0bUZGywg+MFPWwClv5sfWyMjvoKcXd0ls6BTFeVTMn
s5lLyqxqick18TTOfDaF1sKXQ+Hsou/TDM0ZhjfqBSEUiaKUrPsCJuHqvayPmvp3Km/L2uOmVb22
X1Lem2zcRmIPw5cC3E+BcT9TDWxKmYfs6+SVm0z3P7HXVodVVEODVMYgro675PNakVhcBg3jJfRL
TwCzeMMIx8rif4yBNo2/TEL4LuCqfroKYYIpp57EO0A9p+ytnU+APiLAwkx0pdnSq2Z5c8zsVXF0
ScQIBaWNCag4yya/BeCIM2GfrzmgMka88azkqXb2IpoJUBymAKBV5093O9iqsPPRFaDtZLlP6hd0
EBLzrlxHeDFouyWflH3LP3mdhWeZut27Ouqp8YbrTgnQV5DQD6TP33W7lLmuV9TDKJiXMVACHUDM
4NeK3d2JoIb4yuq5hwVJf9xD50i3ZOxVYKlFqxRiXZC32CZJNlZ/GSLeefaj4iutoFo0p3rGUzJp
tS4F1e7VU8TZ+Jdg7ICM95QBFg123GMJzWbvdqnEH1SrVC4mV0Yn0kgB0XusPqxIcmS/erhGrz1C
PrOQIXYiIur7OcBqUnmeTVLDHU7KUPdeWWV9UutdHLpS4AbNZhvpkIWAyVMMCemqdM+CM1wls2Cp
asvbTNN87uPmTNfLV4BH9V92sGf6LKp9QSuHo0gnVP01CsUHzvv4Fj/Is5zsbdegGVnkETdbdiOx
CEDu9LMQ1Wgxlhu/FIJO4anptJgXooslyj75ZzN/cXx8jsqnSv2UldhxRs4MVq7a2C+pfAjFi0Nc
x7TDlljVFr2EDCXF8169pkqM7BCF9wZldm4/168oCfDM3zHCRj2jjL0m0G4E5fy/x71lsWIsxy2M
FPi7mymCPi/QpikUJeXCJokkVoNb3SXZ6j4X4PjxEum/PZnGCPkHYk0nbFHYU8TKHJ8eaVghjd7O
Figf+JOTPi4pi4GyCGGFuk+6DJ+sbJpRnNzjUqLo513bGZEqp9wSQdnoS5/BptVgrbQiSUMFra6R
cYCUA7wkrripU5leITFCXPqIFpKtxDpsfo//jPMnsE9xsQDJlLj7JCgxaz5qj7HCJC6mFrVzzLTI
jG0M2oSWdrxoT8shw6vB0dxgebiYA3DTzIj6yb9PawYfJ6rCSzhmf9d/lgPjheVn0QMKe9d1TWC6
kEA4zCNFq1fK8nmQtLJo6wD51+/m7Hu8va7TuxJpgB1QkvOjoT9bnTyLdkJNdMsTf0m3OSZHUQRr
SmkEiztTJYPqv7MzQxe5A5CuPuBn5X4oYlNQgklPIjVQp9V6sEMoCAIUT1EAWWVfSeiMZH29NW1z
RduFY/LfDWPQrNUYMrEDbTJdT85HSh0U1bw2k8n6qZEYZqVrUTRGh0ekkg36YBTjgL+xOun7OuoF
icE3NQDyabK2VmziO7sKRfdnOPe0o9hz9AsxeX6gRlg4PrP2qoqskbXT/0S0kjWz0QDnIoze5P/x
s/RmmhYQjwbJppywwTARIgCky+xvKutykQQy6IrkFSyzdHN2VS8xbaZCVGiL0TV2HJGo4cog4VPg
5tT9KKSZzMcCATE1ttd+/Y8u8/LVtXaYhKf6/lgbXL/depjmF0vH9SiZcPE4Z13aftuFRriR5tDm
Rx11emnep3WjlsgLXk97myQv/ucDmH1MiVnBK4VVZAlBEdbf91K8PrIMP4ZZaqMvxEPSsbYH9YKB
z3RvK75ZtkHfxJdNmsRvEQbDlzriA7XOcFdeXp9/U407twL6XIgBCz0bV9pbfI5QN1KY6qV6YZU8
aKKbZhRJheI4i51/dc1eVNh9ZN8l312b1B6mC8KM5I1SiW1N7D675ppUDYTX62y782XoPhKvK6gv
/+4oxkJ2NUMXnwpe8j64+pssv6pO34Ss5AO4EgiSJH/+5MkTfx6768/43sXBzoKtG/zjXXL3ELSa
17df71oGoTkF/H92vFFnhwCci/q9WDrLKHmahwK0/nerSN+5Ic/2PVZDg3myx45KEEFXdPFdvvlo
Vv/1io5ShypX3FxCOSb5Qur07QS5lIJ673mFm+Xs8pZEg/rd4/d5aaFxWOMGQTFYBjJKGoyNXg1+
qvBlIe8FIFdHirAq6h/1NWmewNuXCoSnFxWGwrsiLijA939cikDXCYugtSFeP1GllRGa5c1EsojS
RNenrEq6smxmYhtMRhLpBcIsiZCAUv6zS84gQ4ByUu2/NHFljDciL5EoXKzTxzMUI7qZ0qsoGpGr
kN+r+0VFsjXa1gCUmnYxGHnfyTMGuTMaP98DxZ/S5fCzEr4Sdx24KQHMujURKgp/6SjSoJfy9E2m
GucLulR2QmItpKvHdM8vd4y+LoaUBTKVgNfyWHCPyH23YTcmLidUXKj2+7B/ARxIXpmEeJAXA+nT
fqTBf4a0KSNh58K8+aD5m+mMPUdCQOyH06b2OEr1wOwYSqbrvPwAKwRobftKTNh9fylsJPcMNnfC
bpRPXM1jZCKEb/GhZFPyC5V5Axz5xxCD48HbyAV18WBThv+tdTpIPKm76LjSkM2ZYRzDLeg05cjs
ZIJ4RO3mDtifg597NnnEdByXaU0MVDS7h842QH6TLLE02+xPktat1HrxL5Q5H6uZLvzukUC04UtK
JliyT6G5u4jvEU7EsKYDQXyU4/TDvUxCcqpd1t7ghgLucqTHMlMRcCba9GAp7R079I51V1NrI41O
RTWNnkHZcz2st/s2mGpWVkYCgNWp/4yJUjhKxR50Vozaf9EwBzuo8psbiZJ1BtC8vF+U8HZ+rMgT
PhFZxr0IqqwnXUP5vqPRJNEMmQuA7kIq3ch+/syC4uiKNARlDXTsqHtuSJsVEMXXdtfSVr/Cof4C
FhQxSBLg2SRtABzSqZN9Y71LfbrJBPXUhqY+XxsrsGyS15CjLwd4wUnGrRH2JbzLIN2aXQ/xmiDy
AVgDlKsRiUxT0QNyFxIrtsKCNVF2/7JHNNZ3s0rFtpYJpR+gd2mFj6+6nM2LC5IapSqxqWCJ53d2
Cu2ly9CRmxd7d8uAN7eXYuCY/dY90VlOJj/k5T5HIoyXU7dPGtmsAAza1gbx280HHEj997qloGx2
M6B4dfnOyBQihKVYtj5Ip6JpcQUt2kC8hDbCZf3Ig/W36CAXneUy9usIc6d4tVG9jpn5tvXxt5uo
d0UzBiVgSUEzSMPSQibfPfs/kFm2oGftFJEfyIYZFXs+I4G6t6VIOaITM6dUFv3gPK1E1O3HkOTB
CYRaYvu/b2q8cEri+b9bQ20Ma059DPv4eVlYkKUMkO4kizAulyOMxQM7kC4vrzCEmCyCbNQf2eJc
QdiNZaQcmY4nihhYEO1mZfwB9NUsW045c2yMPYJHAwPatAjBaZhgbhNxPlKXhTaDDxBjqyJn+59F
vmEZuT35XoJI3LcKUbhMzl4R1mBa9Xth2xDf3tHL3ZbYuHhhQyCgJ4Sq2FcTK8O0pl3lQ0ssKlCW
KSdY9t+Suqb7T0T3stO8nPqmnVLwaUXWrq7H9C0/DTHSXCq+bHR9St9unrTcViIR2iJdku0wFFTF
De07ccWZyT6dV7oMMHp837W+YTq44w2c1i6D6gZSKDV5fyasLE91QPHVjnE3euzdwvVQQWyAVf6w
mVhPVfzZIE+TvA8OYW2JTpTPjoW3X++vvLR/eA+HWnRnfh9IvvW/dV8e42myj22IaKyKWUcCuHJ0
L1MagbwphwPddb0b6FnqheuSDub8GXuTY5b4t+Aq1NWj+5jxYFrqf3k5FDGJiOV4J3woHELTCQKT
S3k3GaN1nuNErVoNXrjvn1qcnP+zFRx8OC42UqEclKR9crFlZ5ZvWnkdnsFuJ46hDSsux/PR+vTi
RuohcajvuhUWeuv1PUgW9FZzSPu9llwe0QOsulPs3gn3cRubYdIuK19C6rPy29p3NkpVAeweIJIq
rnRJiBQSozAeOMaAEgQrvUvu+303bL2DZtsg5gb0Jaraxkw7ADtMdOtu9f3rPfGzu7onyEV0SARr
nJi3/CT2Ith0os/Na1d/4e28wjKi9RyqmEuxzHVbfnXrkcgVkfMOf9/d5sGTguiz1+xMVorMf0Aj
ZhE5aGnrkTB/ZHgsYUswKpjODAYt0OTdQonjGdoxoTG4P+WEhm8FYE/iNE9ZUkQjHskHKRtAxnmg
HA0j7vtphu/pcGQJ5XXMjCF7fmvn1sZClwzL/GIH5HXdm0L1JsyfiMpfvtb65kRvCIwjjiDPcOXW
6MyB4J7qgMq14zqO17tv1PirM6i8x1foI3L4+aO5Q/2mtq2Mwptba5MY2Wima5AYmixQ76rgK3cG
HH9KqL7P2d5+alEWdhrfzoUEw8XdsOjXPpJ3/AUj23TkBTPEZc856tjRPHB9S4kNoqQnZYcA6hq+
8IbYIIbvU+Yl3seAGNdTVW0fteOaUyXhsO8ovCvV1eyX98zdC+yejJprr9Fa6KferHDMibEpi3ST
33amX6QCicyqMbSKTmoKsyFKrebTvwq6cJsREy3m7wdbf5p/rqEE0Ls+HYBBXwTgKqXAMuecTqqd
r7vbJJRiYjlGSn6E3cMb1xQ5oq5XCHhSJCNr4cvcj1WNzbGzm4XugkIZ8uh92cP69vcrVKM8Zvwj
oni9lkeq0V5CS2JwyBtPPQpq1kBEYel80nDbRN7FfUfHwRhsk149HgoNzRINrTimh1vPoVE95pyF
JpBh663dVo3Wj78vGf59ZMXtNeCe30d7NyyKbhhhgp7mJgYJcRz6b7x/qv7XqOmnmWZ1wZwfdIib
OTPORPoIiVbshtYt+kIMUkMKZ2p+Ag185FeOMEdW1PtWM0XVxcKSwaoOlJPIW1VQV70roeO22ko5
nI6io3OxY95izTp+OGhG5ysIq7RyvJxbKj6T24R6BzkpB3xyLC/LxFf1nmn94Jum4msU+EZrga1u
9dnPbkxnOnn9dXr49wI/+aX5A6B+MV97EI06U8CuflI6AgFWjtvHPp+bg4M1vDFcJ/QdCpnN0P47
4ac5LMpqXpYgiypeYqup6rsXY7iHhiAhf3G3vGml4N1zyCbJb8weepNQ4Hgs+M4eVCOq8pUnAkwr
jr1NgBxIx+kocXXPO66tt7UEN3dt1FkRMrVj0ukWPvk1JcmJ4XT1kPU0GYhnZGGbhDUbeEoFLyxb
tfMgYxxyuzc5gaM1/YOKyLlRS2HuV3a2Ou7WSulQLb4PEOPmXztAEvn4dlu/SyI7gyL51/OWgE9u
711RFBx10co2LTUbPfgF+A1eSzNFJd45Bv1NWqKn+8AAyEav2Zx7+bGGnzCB1+5pilFAve6iu3d4
nwwHSJo5GNQg+c5bhSA1BBQYZwqWBbGZoxQHnqf2m58yjbDDRnQ1Jn96a2ynsCIPmfe2mXfMICK8
exP3ZQNWbpNWvuExn3/zRhSDZ5ewvkzuUDy8bk3B9EZy9Dgi/ahRDUp/cnel8I4VFjORfqwB6V/9
zSl+PM7izPKcdgxOww5ttH2L9nOZfRaWlVKFi3qsf/HQATfVjw4e9ok5VUKfElrRuQB+46NNeJCm
rd6I1WXTTbsMtI2CjHlU9akO5ZZPC6euRFkTjwGNUn7A5aGM27sINVVo5ATz+NDLLGPe39XFmnKt
iIBS53KbwUxS6Ut30jSKkJnZVXpWiOZiFjJ79BDPPU+H+x8EiBCsk9WlxGMSBqjFFoONOHL7tovq
sCqKccu5e2N1HJxzzF0HOzyttNpixNYmJsEYAyonjWtGUEYR/gAXMq3hCfr58Wfbr3BIbcYWQHTj
qmc5V4QsMvuI/atYhclrtWa96E7Ojkw5cGbPrqqlFOp1GOIMB7Qa9y0uYgatLrRTcqsZrrKRDb0l
gr6BCjHkKmeGvTdsBbJ/ldYdRuOlfg2P6fm3tOJg8pkvoQ+l4/uwEUUESjhPRxiHd3PucnqtboxR
K1ecUQVH4Rm66xCjdqlLWhOYXwRBbD1QBLdVeqhIIek4iaePH0XVBs8KTNjgSgoiywh7okKzoJwu
nZtt9it4SUA5WxwA1J5NTJjKBaGylKjhJZT7W+aQCCqiu+ASjbLfFmpLIWryVwhxV6GvL/vUeU3u
jqxfL3Fs03qxjTphZ5A2f4qOEkdHW6ICay1fukU2F0nPfsTv3MIqTKgzFQSOuvZFBKEllCqlfqYJ
UvUhD3Hu2zu8gQOqkwLSMr5iBLLXyEgitC4VxxQkhapFXQWcv9LdrDEuA9uW21fKsP8+XHnQsXcl
<KEY>
MCE<KEY>
+lsikKCuYZdf48bny7NxOAyebyDRG+Nra8kFsUkZbaDebOIW15UcNFq7xUAVyNuSfdz0kcCcYrvP
G5G0HimI9YOz35qYCVw1H1OBqDU3D2pfNC1uk6+GyxsvwRzij+B60ANSduK4G0I8p1aD1/V6sW3v
k7LNZ82GKTydnTPXhXNedt/7Wt7dZ2ZdoTKTVYOnTvR2Ea6TKdAKiPilMIjz3UU8hK+e9vxKxRdh
gKLkIAzN+lCr6Zh+FZ92QLAyZGZaUN7zDEg/QElstVmvOYRsBKbx+Zo2t5rWbzqJYUbjHsSql8SV
HPVPEKg8K7K4VrfASa7oyiMa7v9+t5zgKA9NdHegHl5I0bzbYucAFcWyVKedHOvFYu761KmcE354
VVt4ezB8zjmtJCuqq8kkZWAOBfJti8iTY0lskKxBqFwvLu18jjUAz5i3EgduUxU0QiACw8OIKIhb
329A9EMBk2FFW/Onx0YA7oYyYIw/chKQhsb8mOd1ud40h2qbgoJGS1vA4e/nX5ysIq8vYAGPTzkB
NPSGqj/bW2b4WKKJqwJbnK8sNO2U9XZ0Uk+QCCzrdVIULifxY4lgMUrJYJcz+SNrgs2d98cvT1dm
f+Jn6OvGyujfFD1Fcxyk3jwtNWUWBXT/1569k6waYkVzL5gFwQIQXLV80ok7QPb6LqKwFU/xA6fo
rg4lY0M8A6+0bzgfpDlZBFchyZfxmWHq+EAs1A3FpC2Kf72oSnpoTMl1leowEWzII0+gWoDbBKkZ
5wXMxRK3gzii/xx7bPm74owSlpgzducAQfjRF3/z69LLcpibyunQYqauUOdyb1dgVXlbeMg2s9mh
KNbeF0hHKPbycNPYpeMf2YoB2bYeppxFyH+KTgfncWpXQ8prwlp1+XSd6rCBa7u+DMkKvXflaiPR
rWT7pxRnQuw7vtrLD6NVxA70QIvQteq1tHh5Xdum+zhv+KYTBeHVqWnnZ+Nbu0QD85Cw7G8Rx5Hm
XL2bYoaqse4bAwOO3Eu+9tmHTGExnQ5A7JVNGyZztt6cZ14pN9AZEeKPb/n+l+wCcU2Y1fU3X+Js
Rs882Z68s82BybUQGoHZgi+zIxAFxIMr+LMEevCXvptQlQFHcqX40ZGl6azuAA9+o1j8STkMlqNv
vRjE3ZVlftbaMnmkBQNHYigHN1aDer/6+q1XCp+ZsXrrEgtOpvaeugUOMpxfRHs1RrT9lI8XE8dH
EAMdopmfLBmHA/dMITE+qgBdDZ3RxjnHETn9pKL3CGpcAWpzOj4MD53NtnoaZxyHkmLJBlyLnNB4
A3j7VMmUO7QVRV+ubRV9MLQ6zsnmAsQzqIn1IISsEmjsaI4zZjIJOflJe0MJ7OwWdmDDLLZjCFjg
n9HQplboZJAHxXcoFcgC3gETuXWBHVLTffV1zVbQpvgcFw9SSbAXvtkEaMr1DhYgde2c2k+94N8G
gVowrE4WhH206lHGcUY3M2uQVXaI//u+43LqqAdiiG3Z3zdoWTqUpleFE0eCahqWwHt7wsrr2k4J
PhAnaniwlY4cJ/JaxkKIxF/+Yn0H/hCQf2Gi/ENSSHxvmVa1lZh6MSwHaPN+XkQBjvY9b5Kb4QJJ
gGSdysdx5UkHvRwW+x/QuKdsxEtyXj/J5h8OwpMsLMJNazmeQP14vXejt84BMhmXJG4y/xosU3jQ
hlU7Siihq68BnUCkigmhqr1pfhB0fJl6aDsF3+LWAX+oKydm1vfQM+/KHqV3uFkdwnE0HpNy+i5X
f0GWcHZa5ddGbHMwvXstHvRcE0xTOGe477AxNUtGESKqOSg5R6DHFhnDv6GrbFpeA9+pk/hlIR4g
WQj2SLrq1mCevrHr+yyzIFEBcPzwQtxbtGjk2ArfpL3686WGkA8OcRRuv58VLskqAYIaN073yEpk
hETpRh7nRhT7T2KxRt/6f4jOX/S2u5V5np4luSIg43xEMwDhnxq/A0DxHtsJQ2aEzeUY5uqEUtoZ
X57PZ4vDJjEcpH0EdzjMtiJgj4ftN4NprTcLWl64dk2/+kEaPLTq3cpNgd6Sckn8sIJCG0vKU3pP
oMu8vhy0PhLu2OrEAlfFfgSXYcGDnab8mKgRnDPSqU1YJAgi824CkKt2JLHEII4nJCWCGnAJy6aN
/ypCG3t5tG9Nb8dL9ysbSCcJAMIStVjYhD97DpdcWxjaWd8+bv5dvlsWg37a4n9fSugRBg680NyS
TcYsN2hdSX2U5+nXy0XfscZm3g2gS9F364JPjA1cpA5QBxDJ1OEU/D2DkZ00MAfelzmXRwAQ32W7
pwdPTZTjuLUz7llrvpYeXVeOjXR+NQf8lo9jJiSRSFRn+LqwoWuQ5HRMoYYpGlPHAQYclFAPwD2p
Canjvc/o5I1TPNKq6J+ljxH8PFwK7/v5TKftRkuIwEicB8C8jr7lrrV7/wPS9a7U5aH6TbdbrQ1F
iwJ+5vNxuDBAuaRO85CZl8BOBYo89RV3eSRjk0ALFThsUQMEZGnboGZ8tVIInOPV23Uk/aXKgAc2
fqByHC8zcBxjkP4lDwbDKdzCIOlnbQu+Au7GRm15a6AHAt8qjUPYyQR5UuBK9Nimfbnk/w3Y808b
1snj3t+0H8Jm4W9DPslKX8AM3LpaYnWXTXMwjbU9UQ+dJLzGXcs17afFh2p2hERMItLxM25x+md8
5Al8IV2bt+61406V5M7E0c1kbK1iPvvYiB+FuJ3CVFz3lqDotFoT9nRTx9vP4tRq9016MUhP2p3h
55k2e+yA4xJN48wejOBU+gFtdn5hAexJHlWFYAWlS8qfEC7QCqaG2utoM4OeG8o4KKZlGS+P7cZn
N03wIzrjmDb/k90aIbWtFasnwM7eAP1Iv6TWAVT1OPi3qvAsFDKRaJkfOgeo2MGUF2uTCk1Llbh7
CKKLTBeLv0upNDLcV5v8+woAaYWRH0zZWXsX69+oLj7Gozcm5zMTI5vjpIZre4dt5Haq6N0uh9yd
rEG11Oh7FfLI0eVs9u8XrI8RrmfLUiyQ14whOwuKOX88XdcbYVZRbCcAqjwLBQuPhMaZpH2svq8y
14a7vSc+fvEl8JY8jCmqxRRWCG+G6q1WHRq4hd23FIC8jkx60CKH0eAYnd+iMk8cKzM7DV1lz0lo
YpgkuWmX/Kp6Rw1/XedqMlEaa9CeWZglDAe5/7UblCMJeP90UEXZe1vjMe3l/L+QSyNnqMsmhI2z
FPwYRu6/ixb+rjZYvHSsPQaP7YDWdrvpoYxoqZxV5vy3nuNerqcgbEM9XRuaPIouRo8YqJz5EgDa
0fRkUmanHfmfbvmdfHANvh52tsvp121+2c6pScsdepxzpWWWOqoHAQuwEvsO1t8buUZSTgOCJren
TiQPwEpVa5k3Bk/ou1MhF1CL0kGxHK1AIR5k22iMj2n7nHJPyg9GKWtar1vI6HovTCxg+VBM7znP
9BFAOGFs0SK36aUTi/F9hVyd849Em+MfjhB7hpFDGyO58PzYgNSVr5LmOChU57f+XisbeDjlLjK9
6ggnmMirLZsZ9km9bB1B73QzaqRN+bo6VYAUDbx4YvRJ6Zjov5NZ3bkZ3MxxZX+ogRhNUorQ7Zw8
+gJPea0z2k+zLgjoNOjSpcCxviu74tD1WuxY7wmfez52A9n2B0fKa6RKdyNSuMxHcQ941YGQNHKV
GHnHIGd6f2btxxqdgFG38uzrAIBmV5SAzDmro4Fg2YWgCRy/ujCqekveMccDa/nAZDb3kDFpQhWL
/pYCXLxG5e9ygV2LwCfve161RZaI6UsrQV8G9j1MRrDMumSJ35qlPXBULl9ySsz7XBxgcVNOUax9
4At+VG82yU5n69UELPbfqWqaErfAse1g/xdHEXFAOJD//z7J+G66bSW7iqjjCa2Mc/1SusLUETy6
LG6ITy/D147vtBr5mmbqGA+EGcVbiLnEzQnUVQKXnPzTxlYfM0W5g8d7iaIcAqoCocvUweCNZo3R
uftoLApUmQOXTdD9Ho5ssRukSJTGGpLufq3ZYz7xhBzS9BNv+KEanAzzbA3Gu7ABPX7pyZeH+/7e
rTxaE0heWYcIJ954z2P3ztUTVIAIFuY0V24d+GlGuuKPBpnQKQ98XSCDTifChEn83jerW3t8BcYz
RYrM94mpSBvJ2QrPSSZ4Vx3dP/hqzcFZq6D7Aa1jaAryHQcb0OBuvUAdM0p9qythKZ1/xxzcG2A3
9yDsTsj614l1qYEFIDittZUwNke/TWcu51DmOLyOrNL089RT/YhhbHxR+NdmVaUhxwfHMY1sxCP/
/t4U2xjbrj3f0bg2RFwJJW+KsBwNuq7ZwLW8llBB8BsFkmbIwCCuJchgDxCKJm494tYROkaNH9gC
lP8xrvVSqY9txeXDNa3YNYxHGHlR9n/aj/MgT9u9CPw2RK5+/enrXLVeLLdWy0wU6zOASqFQLekN
Ksa1g3iUFhe6L1eP2rVkzuNpe9N5A5x0qj/5AXULnuy7T/0blHrcZKPy1H1SyZP73wLAENy/Of8k
GqCafkq7Z4A0NDGVgxDXcSE3rr4VnNdvQdY8Z88jG9u+Ux6uUzQw+hku1BfPzSLp/Oy96o0W6PDs
LVlsFbpY2XVVklAjKkF34zdoXMYs1EWTko0mcO29Z56pQHGyyshM+fS+D0NcKezbGfQAMTdgtEDO
x5CCkKxS5Oqc+q94ssaiLjiquVT2Cwv1TYkx5VkUjywqABPkpP3jJr2Kd7dlEqMUGhndQZ0Fg7np
dPQAK6oOheINfSaGTOEeEw0TtKmjeJn4Xl+UJAPI0cAsqum4x4nPN3/mH9YL4TDnb8Q3Mcr7GjYf
o1Pw/IhBhS14Xb7q4yM11cROgNADJdprzQjNnPQjKuVZIiuc9t9bzPXDUpFsKaugfVv8AYdjuJS4
uoe0sR8FectgpdKRklvviCRRfSpV0lGSeDBapWmdS0/AwbgRIsng3Bxey67ZViPZw2ibO4TGtc39
7G7vuOI6A6DsLtskXozlecytMBO0BfehAuDlm+Y7a+l873ErApsk3CRRnBWdoRT5ap+P7QJr/LF7
uaOmyyvST8g+c/jTDbzmAYJWtba6pYa6wpEV3ZVbqDThfcnG08pY72EP2q+49MKpNCQ/js5UEPY7
J+YWMbUfiZb60jgSWs4YnO31Pyt6rhPn95xQakraw1L/UoYbnK1w00QwUKV1lQs0eIMABw8CnofH
0bjrtm4uLBj0NGsGkE/D2xVtSHUy5Y5xkaQZBWLMk4HXZhJY9Pc8m3oPhgslG6qcDQEIxAUEw60o
bmuhmTZrfdnOFMLRTNourQPSWprAWOtjvZ2hC8po3Zz2gCHga/jQvcUkUwUSF2PLZCgJMpME2d6I
jZyeB9i2otusdmf2GcDds10zyY/Ke7FzR1Cfe7qMrr25YE53nfv1qFB8NtjyXxcJ6QcnOkMs6yds
7DHUCXaBVjd7lktTmkbiNj4OsTRgegCyjH4mHQldFs6qMtwDwBTYy/yz4ogq760kNjk5mbJT4A5J
AkSMB+6Ml+4niZR0tB59HGYu3NuWIe8jOGlUEBBr93RSQA+Ck5tCAeW8ark8g3OJjCBl0rb4y2zR
z97bz6xCUvXSAMsUtfJFTlajvWDjmWS/XPU6Gk4igCVmGnkRtLZDbm4mB5ei8GVcGYQLzqvrEhSd
QlbNfScLVrKyXJ8vc002RnDdVVD91U5Zkoj6iIMDxOeenghLkwh9MJPeh+SV4EI1Touxz/GDj3r+
bwFIsLJU1Z09zkWxhcvN4InJgR6JXAVNfNULqP5y/eeTE8Nq020lJTmcosyW8GqwX4PD0TkrjEcN
ayu+lX4QKIPLA5G/TlgiRnu+nIMg+8vpLgJZ4idVTyWWLP5UA5ETKoAe8qOO1O0DEWE0rkUKuG26
b6ZSQEgSZ7OSgyPgHvsnU0flzH52wAa680ut/WOEnovXYTjVtmgWKeqviL0lfPLvaUS8eJiwJId/
+cL8j+bu8LxYB3lxJ2Wkv0vNGdlx5ymsoNEbEmbLzvHRW9HQE1b8WrQ4La5Zc1D6a6/Fhb94fote
iAC16Pz4Asbco++Hs+qojHbSEsS8KnxjK5pKJgZmPOkJhJsqP5MRofkapnPM1HUVy84oTlLBP6VH
RMhfVw5E1G00Pkw5bbk2KekLTYXgbTA5WMqTjYNWIePRzgeI/lm3IEpaSyeIS2v3HycCKhubewKl
xDW7mMoyL6cjOqfEvMZR16/2ARy6iG2NGNvScSE+fHQU/tOQxCO6DudP7UZW1x2QSKnIAmKCviDN
lhSrRffixSxN2SkYxEgCJR0BCTQWSDvI9pr9yEvSLoE4/JlFHhJF7jIyaBKG2fLyLqQPTZLBcAhY
KQTVA2HNAvFAHT1Rxq8fQem2JO8NeDQGvwLheEkUoG889eZS9NZUhGNFDA+rbLTe3ArC3C5P02hh
46DjQgYDJzAugNLDx3pdxb5nltdUZaPKOv6sAMQeo7mENbOmjlCERaITqHvpJ8GIeoQHLkChdYM9
LIvqkxpXOBMLYNAeObSlrISIQzA3AwKHXpv39bUf70JILrSNjBkrlXeEXLWGLb85adGN/zfsgMUj
IzQi/+fjkzXKplBkdTJH+Va6a86J2swn/rE0BvS5mwaY2+ZEYHGRtvN+ft85JnNeofxRn8e9/rXV
tN/FKlHRm5gqlTyOmj50RDJEkLjnX/fXuiCLQoiJAKPZ4f3tvl1AzfIagm5TMy8keALNEoez8Peq
H5LhP/NdOuC8a8DWuo7oXiVT8RdjqNotewxBDyv1RQ4Eyfuyi1pjPZU0/dSGB7XpGJ74r8P3kDgd
ncsjenztMEBwIYN7FX5fucVHJug2XkdPXCQ0cCmyeiXAeYGxMnbDIRs5EhFdzYrd/KISbJDFvdQU
Ay/W4f651/1/Woa3hWUERjJhhqePYEOV1BG/OJsSDIFTI8aLjduSD9Zx8oY3SCwEkuGrs2GSIsZW
1IHvEgdQCxJWz6VpMxqU4mwxGoIvYJKYxzhl2M9qZNQCrawMWk8woeOXT6zusMLqRE/+R5j0TCcY
3TcoSX6dXdKdXUU4rt2hvUeuYd4OTOT9Ram9bKfuv/xfrHnjJwV6hljaMZrUIlht8X6+3HAUD/kj
UmalUy+EFaZoWb2/m9KbPkZiwS6IEKBsm5FmhLj9tLuUEk9olXRZdrnr5SkjNbw7nRVEkiAHLI40
9CeATEBSFRKtfg+VfO6xjJzg8XszN7051wS3Gj7B4QfBhS6uFXk3QAz5+oRuN9NR7YR8NZvnc0gl
gkRqCR3u+bmJeqd1FZ1ePWPx/6tG2SB0PLPRt7hr194JWUz1SjfCuKrObnZ9v0NIdX3pjKBpx4kL
Zr0KJK6xUFy3QrNg9LqDQWWpguF7Xje3AbFE7o0fpRKGvqRkfwtIvKuRnxX8dIIpfym99b/BTcL9
CUZX3+Ou6nqnNULO/v8rNhMze/CplqAH6V/lxJ6LtlIzw6+kPUztH2/L8Ry686mnKZpvdffesOWd
dA0onKJQgARt2LcNGW2fsHJbnZrfAZ+7sP5hei4iYnQeqLy8L6ibaEXX5220GpRKcHk2lwuXQfGT
nKzyehLHgRDFNDlRTG7gJgT/gf6hWaQsu4POeBWA85P3mm0Jp8VfgL0z3CxtORtWIlh7LpilE8ba
Cjz9AkVYPrpA23+cQ9RgEikXpC+X5B9TbknzgJnPWpdMVps4JjF32u1M0YvPrj+jkM4VyAQtUgZT
ECLZJE1BLdifw/MpUhVArgwKCaP2LMCV9KLaBiEYrZD7vC3JSNsY+tTf7hrh8ZK6ZvU3TcofxmHG
z/3eanVEmm65Ir6bBWH+AXqDaAWddAHTBsgXxX945WkEiCLQuiDB2c+/Fn/4OLDa28Adr2YTPVaZ
382+Kfj8YvFLfuxYK4P6pa5+9csDjnJqgCC+LuGyP2vR+Ew7W6INQyoaKIcom/J440+dfWvGdML0
TXNuBKz2hD5FzqNuBf4x2QpdvgpIZSW3VrMHIbth9DLW/vr1ffMmF2y0KbevqeiSwVlDaKDFm0XM
5vG7x6v7UnTpKc4O49Nrni42+4C1EEorragzm6TO6YJKHHaI74XEGdSlePkcI+ftlYHITO+yVtz+
axzvRW1YDtmjmfDbgqSSYv0D5w5n476Mn1dYrio1LrZlY8fSqxBOS5XMwfrErulT9NvpT0a7/6HQ
2BlYUsorZx5F+8srOcgNoNYCkpi2bd3KZYt20S16tqImpnYNOocxE8/s5EahmX6HMyxiVSBmia+a
5j/tIKtKkM09o+dInKlUiUaCgecgOdmDrAiWF4BrfX5s5nvriSv87eyMSsFGSutJqFaZ+ZrBMXVu
80Rj8rOj9DP+xoHBhgwWHqOVw/1a3fgFkKgPdh7+qFvJhwq9PMP9d/ShgyMoOAWwQh/ds/dsRhyC
zzVXS76jwENVDCk7C2ekSoj5wu00SMKw8OqVLXJHf8XHSB7sdOXUJKQYaxqp+g31tjlcMrGDI+MX
fpGHqjp7Q7lfjkdufYLAMZwSJkjnt0HDdMF+fcbJH3hAdf44o8j9bFunj4dXaxoCQq/Y00xrrnAE
f/yVgHglZG0GPpl6f5xn6faDrIfg5rGBHZyNeLHE+It5UraWw0yjFRtbiKUPpUghr89GoU3iPsx2
CiE1IwABXbks6FY16eMxeH7WQ/O323DDLjBwkcYIxnHMkwns4023jtEc4Tdw1EeY0owUtngmyFcI
EHfKAJZXx9ZaGOFaYq9gRmVFvoAz3eQWED2xAKweQ2fwgRMh40Ll82YRAFv4q2FzHrb1twXoFtxu
1vKa6yj5idq1k1CBEjdpH0nhiy1SWK2X7JbtsInaFiP2QflzoUkSJHcsKKWUVQ/A3d/8RoAzHTnT
XQWjUBpz/0v67f3ESXShPqkXruB/pbJN7Mek/Obyoh1iAb5Gr33YP6NYjYVqOM5Uwin0YQKPUdES
vTytNP7lVbBcHX0/5ZpAnCi8yDXjrwK7s/1Oe812NssXp9L+zsA8Am8fcATUn3VdFsrtvqDQeX4O
XhXbD0h0fhL2o+5hInG0F6I5QMfFcvySBUS5L4V3MpXSkd4dFzz1TS38bVR5KuZhLV5MyQAC0Ktl
zkxz+r6QPgsrnZ5KZeGOezArNJIjxqAZZ79SOVhNgPOjwvIVX28cq0sUP81YAfgwBsR8OyM9Eskp
Ok601sYYatgoRBFTzJgUtHnPHha5aqhpmN9Tj8h/RCUJhBS5caMMN0YXW/AkfmtaBnwfNp8RM2lM
ySKAnfxnb1FGAFWq5Ts8Af/0M5IKgItyudy1EFJE7PekIbTJCmMm74q0Qkd1KlZ8xTi5Xz7crD57
79Gn74gdD8ZyyZZ9jbZu4FeAEtXbudhPy1TlNDx1cmWRP0dW8dax12tO0/8CVt2a9T47JAJ6JzpY
EeBiU+1CVhlQ/Px0aVgo85eQg0qemBpdoPeKlcmpz8FJ/fGtEZoPDKNnasqhboZ7m4vYCguJWmsY
JtNSqrE8eTs8Ilm0VXCD5iNcH4Q/LWFiAj5n45h1eVdHGsi2eY7lSMcVa4SUCahfvo4xqBqqpofG
ngkBmiYXhNfyoyzSl8UPmIuNw1k0RKenuysN6juDtJI9ygaRMJ7dQ2LAuWLQlmkMzH2gpyJkyfPg
FrzYo5YNsevVa5qgr9J0pcpRvJYNtio/FQ9Y1x5flaUsgQvniC0I2mesvUfOIHiIemZWYiMCuil8
inoKFjALxP7BBDZKURLkyizK1jvYf+vFH35+BBUBS9KlBeqyzY1OGhg2y7jDYI399ycfQp32Xgew
QoGezGojzU0GDiU/BUAqXTwc/V0dJ7qxdfA+mdGCLN49zjKAIuZxWlb7TtW1ynCaC+jvBfM+MykY
WZ9U5wMwxwPb0VlVLbBEZ0HYqkolRWpgWUyne305yuKZRZ0beBCn7TEoM80MBtBSHdoGf3ydLZq6
1RFRSqRcXUNprwcrATaywkKu7vE0tuy3u15yRY6yIWWhigYE7blnduUYJNYoKEyqWSowvtNDeBAA
3t7KioR93CpAGVrNWWQnHWsg5nE9WjpZqdNiVGXiJsb9OaNaXZOAVIGwJrwrrlcVLCjM5DARdv8s
awUryoTQ8oAEtOg9iZsz3OdPDf7dcBmW4i1hSw6DycYLEIy+zk1iJFIGubFrLs6pXsgTeqOO3NAb
tFodbu/0l+2FfPZwJSWy7QFVDB6UKsHJisQEyoWUUtAdtFaKefQKsRRK9AKya2mHRvwHS/RULPfN
YOFNtpyS8ez2isMohOH+FMbOvGLAWU9oOo44jhF6CPKU4SlyRC4UV2c5HA3FrNGN3tIvqXauQxWZ
UkhaOGDsiLqEZL6wvZGHAq8mM09sRfAjIGrx6U0aTcvSIYt8XwgDfmcEIOMOmvAFgCCY5v+nZo5H
UJ0/HyW031w8N4PXIGXek2E0OisY++eRg6exfzEZGcElWMAKUw/x2FrhwR9gx3Qi/pjrt/BOJfL9
P1LrUEqMlXF7zZxBRy7sscpibjcXyuP2YcF3wbIR8lAiTAvSmCD9LWXxbLcJCMgMlfm6y5Lyyvgu
MjvecJCtuRdnwmVIxLDg+5+WB5jsRkvavBZ5RSmxlS2Fast22eaaz/M0tBNSuNm5k/ufQBCss+0x
7D2vA69M/E/YHtj9ie/DBrRsXB2IBYGAsuW4OY+TMesg9RL1gx5IuNfQHxT2He2TXwtw06Rn0c57
Zl0ruAC+UTtSCrXGU0KdiA0TY+FXQna3qQZdnXlJ9c2O6roz/c+OY1nhH6E50LbVRmsjzt6o9XCM
6PWfaPGSuL8vQJ9v7CA30pPJXb9t5C7PW5cB6QP70YUbbnEYsoWdT7BdGdQ+Hcsik/yPyWq0jOLH
EWSEOdgqceMs1X4SFINcNvvzVPaGMEXDXRb7xI7Xfis/alIjDLbf/fEo/wEy3IbGUOiXYPy3+tce
sExDHFpUg8/veemU5kibi40zkYIyqlSG9EzwWEenenZaBuRaIbvE5ajlg6DpeekaueI7tBuGsHwx
xEQiyPcyaiqVEtmRCvpOHJHFdbrXGhGK+8H8aDDDFreBIhvCg98KeUuxD57e3Cs6GfUnKHzUfyte
CcfMsP9Uj3Xbbzh8SWCdSwLAIQeaje5Wud5tswv5P9nMFkArldp/R8Z3bpPnl3++UmRIJioZiWTT
AXDR+Xe1di0TftUKEN8zrt7CQRMYHxv4pHv3Y8WpLS46Qhr8SuAasdrB9vw0htmWKgRpp5hrc05J
AbE7fK9rFIbXz51K+/HtbXSaIsswQhnQMbrqj5srrcF2CykIbFx+u34asLZa/gCbje2HBm+Wiuvp
nBz3PK9xppWTLCfywy7M1H+3nUQYFNIyeD2dJYyOdvzVJ7mMaKxwKd8W9eHmqJjBH1FwRRgxg9Mh
eYWFPhG+0AicfEyqVjZXGDjInHjx9f8ZDB3bnmJIhFcHrA0kXBRhywYSfiAHbcgoIgcfeoUfrwDQ
vIFy796Pl4W35IQHLp52Vb6PkmK3EM0eQ6o7zPDQKyPHSdJXl0mPpO5a/P3cY2xXfJqvufVkD9vd
nRSQ98DcbG2XU7NurfukMfJM8fXlJva9/MI5h09THi0EWXewaajfB2J3xp3BTid45qHiiLxonY/u
Fe15/OO8g673K3oQw+ofaWtnkmBNCsynHsXW68gi9x9hrOIgT5jXiaPGC9Wshh41XVEzWAyqsxHX
w1leWYA7lfG5oJEFdqT3nMUfwICyorNOqh9Ad+jHNMvMFZVdYnE5sSbddVyRzGk9MiYlo4jkRvNG
U8/ZZR3IZoDShElqmUOUMIldfEUn5PXZ5M9WC/TL0wLI5OFcuRLV6LZjX9s3VaKHHHO7DvAIgyhj
JxEBJkb19mT8pV32g+928JVw4zNb2GY8uvl3jKIy/mkdq+tbGLuORc0cpdobnAo/39OFUOox1Qd0
IFjBoZZJJnTSKLKLwmB742peYhf2fTYGKZZtuSynNkwyURjZO3ZyZRxRBC6yBfS4Bm7AlhNjwyzW
a90GThH5lj2dYhmwheJOJUbC5mCx2F0AfrS8sQQMpZI+VKzKjCwP6bJKv99wc8VnfRbc+Ve1Iad9
DyDsEpME0U57DXkV9jNDmKSVUQXAyQJT4S9ULiW1ueu2f1r9xFWSesTQE9EaGaTmPqH76IhFkumY
3ttWPxSw8h09/sTRiwevhUVMJcnvXH3j2p3FWE34U/e29yHXPMFdran0pBBEUPg3e4+a6Sf0i2TT
OSoTwaYWwCJoOqIBYGMJTb6KMmtzH8gIW3T/kAEyoC3qiboyYo7EOmpHo9IiyThXnShgb/9KgLun
0zMLmKP/XSgX1VRPYAgnBCB7Q8Et7X9DeH95uSCyCUpqhV48xp2NOPYJdgZrtylgfVwLnlwx8khk
51lk2gYsW3mvM1v885jp09txAklHiX+ZYkmgt/fi7hsG3MLLMXKCYhYl5n/4MngK0enGQrIdSTYG
NYzZu+yIsFoami4skws7WPlm5MJiS3O6lQCE36fKqBhEafBfqn1KFSN5UcJgUJqBnnzsgPEWcJ+l
o7AO6Xgc8YexDW2Ot+fGSIcMNVnu04eFhnWWfrbRNgDn6BThc7+Y5kQhwsLM8LkofnH1GPClfrT8
zpyzq8zt9FpWSUwvHcnIohrCNOT7F8VE0EtzdxEUcKcl57JEw97ExabtbjRkds6nItA+Jrv0xdtr
Kfmk1PNcHMQ/fe2rfTFhg+WCIpIQRqmdV6CO3KRXC8/lPoP5tO+5ayDPHJ4YUpajiS0FJmXTdwbW
dOjgsJIRLbjM3GJmfdw+rxNAd7mTlHzstDCkcaYcjF14jSFnDVFmsaBW0Y4pCi9D7GFTBE5HVW7e
PKqu5o9bJRSSqzSzZD//7mxzORXOZ0T5duFp2LEmUyDIsfY2ugzohNygmFWiQgDEqFHwLeXRbDRB
tHTXQSfNyfTJaJCcJ3oQpfgn0SXezXwZxdGHldf5qyJjUU41Hwe/J3ZhWDJOlYEdIKnyRrRrsh77
Nk5xEboZXQYsA6ufuhKym7Wheek9fEGr3mZBRn7qspyMydgdjrRpnDiyao4LQWxVW8I9Q5c9Z+1z
lXdTjtI+QLXLGZRNEvCxI7LuQMx9SwqFvz4knxD85H+iVSEreP9ra/cL7gpXAivgYLIoS+RROOVp
pmFy1OtD8e0K19yCdf+DKwVNWnNMe0MsjZh3ho9zvTZbz7z5/Kgn+2w2KLghxEeU16PR6NzExCrN
Ueeew/ZtKxqy7Ov5Q6owNbFkTrRmdy/NMRONOnmwJZM5Rs6km2uDjygJPYdr9Jb7Hd1dzNCqDaQQ
oo+uxb1HfeU08e74+Mf/JRRDlOFdP0Px2HL8TrgWTqLvrEpPol0qfnVLbJ6ztkhDUT1q4HGqlus1
YkXuUZXjsyXGJaxihJgHVJBtjUuSsHJQJKhMVqFeUpHjuCcglCpxt4ilPTFe37LkIm2A64kZyHMo
pYUR/yAy4iZD/d/ESJyxM6hiat/YDfbHVndmq6u6bl4i5/06m5JEpdpE4S52iQlbZREE+XbVONUl
aRKjsv7PxmTd1s5PK3wtTV4mGOAve4/AtqgX+/sAPeyWZkMr33YPodxhtb9v01PySYYo+1lMLzg5
fnaOvlJsbPYrcJCdqE/5abuknOnN7DKkJ7WvNyjKaeo+YzU1d5fr1dTp8Io9+ToHpSAI5+fvMlLS
it52AAwSk/DGrrj5yQcnAJiSs3kUpV/6CeG4U1zABes3pt6mYwtkpzoj2Pmbq4na/Urvy8PJEAbz
bpz4VFgondvojaQR30eXeX3+e/Jpdd3HcwHhoQ8tI8pmDGGqjgNNa5ueCTbsj/D6btODG3G1RJ3c
gffHCd9fjKhJt006AX2gxqS3LV2JOr6VRlosRgnu800PUZJStrclV8B5AYy9I0YqLplXJxI7+ii7
ope6pcpSgqdgG1kyNIU92Ua7cY0DahppN83IZsYwi9Yxme4jkX93WT7hU6AdL4tpxjguW2exqm2C
4HZHN7ntpt5t6btBf0KOetV4nEy+nGtWJyTRhinlvPAqwfe+InYq1wBlpWB+wZ/IX1+gFZq/Iz31
oYFYXpkHs1tR61ZCWFg7TuZA0yljEaOqhnqDjj3fp58VFFmLMDPbbR8tC8+dNY2EaUmg3YyX2For
ndK7Sv9o0xDrmd1Ui73GZqKfynM5cfv9Qq8II4hfGTIYEgoEK3Wg7GCNz6py9nGPfN3nr+WTtEiB
J1xHzMY7oP2N4oY9vHxdCxIlvd9gs7OuwobrODvhjsUY6qy2T22jIDXNzxvAKVPN9EjWoQUFHRgA
3YmKii06RRytU3LE0xBEjt6U+ciGsFVxY0ltsdz25KRTaFaI1iTnIcHGoCcbVZ9SM4ybNG8jM2Fw
sQ1uLfmTlQ7Q/ZrIBFJbPm1h8gQwazvaBp+g7OolYc8lfmCVBdkPfsepPB0n7QwH1gG4oLPMiSN5
Fb9QS/VkNbZaVRPdzoQ9/5tgV+FWry1lxT2DCZSmUYoAUHhA7s062NIonkMwHey3m6V6O8YsK0aY
VzxlwFFKv/5rZT3BYVm9tdJO63bPTTNEMpexiTihJoUYSDojq5kvRXvVc4o3x7p7QpFpSqf81DJD
nTPBdXvWTJoKZqNDihHAGiPOd0xR8G/8IlQczjvOHCX7dmWndUa5iK4hju282jGHlqxVqCUuNzpb
TFSRWsdyVbMC3bOmJRfMMbWA+R06qZ+ubT40jqPP80S3gA1CjahyeW92kZweJseGyBzwlFlE03UA
lmrxUTs/oBhwWsEDrg4/UJul7Sxfrsv/QkvvzV78bLuWCoiguujmFbkVNRxVgWwCCwvj7kBfkvGs
hCFp/iWdarIz/ofSWHYDDA9ClPDiLrKy48WZp1ZhvkiW+h2ZmI4PG5JNxay3K0/peJA7KZx2Kfuu
zeXCzWLdCEPMC4S+pFTAITcW5szKDgPUucDzs06MkXG1/m6B9XY2tEOB2cft9C8HVuLLEu55SAIp
QvoT5vWxjGGHb+3r2lL4UQgt+iUU0B9f4qsB/gSKL1orVZstc6TtWmQ6ILENRE6eq00ammHGksi8
S1OahbuLMMJoIFvGMJzKvOpog2DO/qPz1ioURya5vuLo6t9QjUdsx5mMgBSaw6gsIX92mHXiM0Lu
b6a12xtKXDQXvohc+Y1IpGl92jypK05DHEJmv3qCq5sAXJUABJbqPv3msAJokjJ2vGHtNC0r3nBC
7J8RCe6/SK2XtenvfPhnPUBpqAgFNYq8ub9If+PnTsIkxAvU2Wp/dEQqJmBblYnHgHdkO7X/FqNe
MZuhSsV06nKBFAPLfAEAunq7QzuTUcKpc+W4DM4yxCoO+7enG/XMwaA6BT9udxw5W+qlo6hrCH7x
2PKOS4ynujTq8LqjKLeAhgWB00YwV6l08e8KS0nFd9DG3oJTVnPtoCQ6JGryla54E+mOsB6q3pHD
AQnIiuodx2zSkeO2+2C/LmKjEoqZp9WRV0krHb2XSUbqQuE0o2eX4OziAdKaM8YKgHY1gh4LaPVL
3JNvbj038JdNU2e/F853l/PJZTe4TwmFG9U8tOFRHHVOS0Mo0JM1CS+Ni+hUehAltKK/WjX4IWx3
pcHSu4rijqqM5Ko2GdLSz7rAe1cxF166OtcbOgAh7vRlkRZ/yimSQ8hSZR2x+DF7Bkz8V/W506d5
Xo7am6HmcfAsR55qZu3Cj3+pTrLl82D55l7u4LKtMqKpJyCE4yvYv67/WWopxOpSlgKOs7OfCRoF
VxeMjK0l/y5E6qSTz3PS/sSJQY3PcQ8+RrG0JgPFRgKsGWObvlTnkqhx4dNiSHoT+f++lToakFR/
g56OPCgxz9DSjT5RD03JMq/C7S6sDsP/cfvALEJ3bI9u8arhu2HHwn6gAUDB7iQyGEHpKEzAm0Ng
Akpq/la2qkN957IK9SHZF06B+3jvsUbTKStMVqMXIBNKJinADyUkAqKnxF5G1rksE7cRRh/+8gr3
Bm2scGlsCF2esgW04DeQPF0O5oIFh0ZsMa9qAwt9fEdr58JxEgM4EGvFyGl6ztrDYeFRG+sIXc8b
RxAz7CxFLW048kxj4nBp92wRMvfGAeMW9sE+nSzZQuRuFyeGE0kwPE0qytbwJPeElZ6QRJMHdTuW
w4QKag3bDR31zuB7E/3GydyD/4gXEquaQvEMkHs1uIdo5pm+F21rl5q5NGjIqRCv7mUiYB9LRf3W
yj5IMXkecVxBo2fXxwBQOqRHQ+YVxQQcNgYwYhHKh/MAHsTunPK45mb3GQk5DBf1lz2G5vhe+cgq
TMOTMhyfWM113UIyPFTkb5K2N2zdh8pj9lye8dCoIJTNeR2sqisYJUA5/2fAmhUKy/LU3ZCDMgFW
tYQqAHURA/oiuQj7Swwp8oHsOi2IcbNL+own9RltQk7Z7N7hN0GL+0Dv+fq1L1YKfZlsWWD31Cp5
JuVJbDu3KmqizH47HBJ7a7EgOfk4tBtn0IRHRQqdQek6W7edXJxzi8Spk4Mxa1SPZ5CMqU2m3fSM
ZRHbtq82815AnXcLxtuavZ84M9Hojyh4lfwJ2U0WkouhuuA2BTuHKy9X4NNrc5/ZKxydqYVSw7rZ
NUWh7/yGcYI5txp4ZlPK56Gz2KvGQzANpz2lW1nPrPIXjYDAq3TOP8+wg9AyYpuB8cLsikGDpqgY
kOGH+qmO4tJj49u2qnpAQ+UH+E85AeFosRWEMdR+sNXg4MujwnkwO2acaAsNJSgojf0ko9XIoo9M
8uLTMUs7Yl20wLN8psJHazTCEmj5AMQRb0UtsL5nVZFqUog/AoktSmrcQaGVJfWvR+mQaBcLo3+1
70t/eYdTTOGfWsIEzB8nHXXrhOxaP77HRqsydyrQA7IEGB7jJTzjT4ekv4o25N0zkleyGZZ8qomf
+1QHP0ryW5WXaZeFPVYDqcrJwzSeuDQitaUV3nmw3oOIRvA09TaE6351zd43arRWQ4ucj7h9jMGw
B8ZvfjP+X+omQgijtltoKJTnOFAeTYAbf7mI+cA1cy0AaQSxDZ6zTH2nd7rVtzI8v8zxX72jeMvo
8gTiGcdpypNxyzMhKcTuqmnJ7+sLDjwh/IdZ4Tb1h5T8xek3uOWr6h/nkYPqF6UAbhcy7qvChS5O
Mfr1W2aR/PFOjpmJj//2kpTrxPAi8wCUhWMW0cIor0lKPBKiPdOWp1SsSbTrXN33YWZ1Vp2tyT+d
Tr97rDVQBBjO2fU4tv/sluZTuhG1fIh/GPd0Uh1ve0HkqZGoSrD2D+WJIvMa17ED/7NdL003YQbB
nWe6smnhmysQSehE5x5VRsbpUiwi/57m8730AE5L4fzzdoyFl79qlpR7Y7NteRlqZNkAJZ08GtTi
QW2ldchKyfrSxSkrr7UXkRFWx4MsndN/OzjmiamXw9JqIGZh8cBHIJMTGHikSJQ61uw2sBMBXF/C
xdAJiy67iGjheuCRG2ItR8wgxfjLwpI+LI7LMf+HeyFyZsXOIuMV958CPC2j5HBWL8Gbn16JSwun
gsUbz0NU3i53k39JwGiiXdQS4SrOleoZExjGA5xT/R9lVhXljEJegcVWcIHi+O1NefVn/QxAamAH
XMEeGhcwiHBYL889SUXrRM7vU7XXXP0rJvFHm36FR2WHeU0pGfCjp2IRtwqnO6bebDT79grPiFtr
gh9AZaqm7lq4Laq7WVSfi89955reDQRy3edrZ7SPVTOWeo/37zONOk6tyRDyWGdmkkrfZ2ao+cyQ
QVI1NzNQYs8TymJI9iZ6adkP/4eik4HJxTrDpHf2XOGQnh5isVgtGi7+qV0QU263TXA+C746Xj/6
H7W3QclrSeedIWC/IsRnlM3Ykjk81p/EtLt7X/NB43fDHcutMCwZdHt26Eb4yVLBR+PNsbGUQOnl
0xyeS/VPvBeS19azbD4n6rujZM595ysEqltuF1DAANk7SyfSDMU0h29uy1dgoHjErq4P6Z/fmDWm
Jzia1oU3vjDncO6neXdVACIB0mxjcmzPsBrb8v3a/G5fKilh2noRcgXh0EBYyLlpt9YFleLI29Qp
CCBSVeSSZVcK3yB4H1r4f/pAQnoHhwVZCfCgy9CXvfOBgHGXVMkyuTzCVC/y/JPyRVYCxyh0wL2e
u0wz3x+7AhtS/ylGve2DYkyKPNdIYtrLxmCrwa31GA+kpVEMpsZxuAxcpZ3vtgoqRcXEC+zmX6Vf
cjV582gIRjKbj2IIDvxeW8VcLXCcCfy2I3LSq8xQKpsde1JmHIUeaVAVGv2uI/ZTI0ZlgyGAaDOO
wjEKCKJcVRL71Pt+RFwXmfK8PV6+MCe0lW3ZbO1YanRmFoiuywbhj5+QtasFhIC4Mi6Cd/7h6rjz
RSSfN0C2ZMtbLZOtnPp2aQuB32ZXiUXQ7LZQsZkksIQhB7tmU3g5Cb9HoNZKIMByhq2XEpqZA/TY
FdBm5PX5cC3BoPkHmXaMfg+oNHYgCr7xIr8qQj/m5ipRba50hjqxelGfb8u/JU67W086zFxjQ7VM
fmGKi5f3yDnXsEJl3WylU2lxSpEDnLa77ydh3eNeZL5cmj/y9zhizqgMkdmVbGNpwSI1VHBtZne+
9cbycOm5oRiLCTXhp+RdwqNUlncSVdyFh9pCHYVxq/ajeVaQkMDs5IvsBZwEmqEIfFveguDcKDnF
o8CyTQaNB+n3etrpfCjgm3Juk6NsonIsGveRQYiZ/ynC4/HQk+0MBO3zAa7MwVPNsAE4aP89YQJ7
laV9DqkYz4Fb0/mcp8xhfpc00DlIH7CgDV9uicIzWMufstZv0Xsi29qbfg1ga2ATXuPrHRAW+QvA
yKnHhowMR3as2LWGGJnk7c57c4JrcnNudg6qJ8rW9Tfn1LG8xLNcrvXl9NAFkWNOgHvQQjZcVyEB
627VDYPhC3Bw4TqxNcpEDE9pSTHNKDSrpfS10i1CWFh33wFitgA8OdvSs7EhPqfmeak+QO+P4YNk
yFy2CeZk/W2EWFq3xg/kpHmdq/jl5kg0qAbCFq1ZBbIyrKffvwVX7a8g792q9D3ct87XFQjt2UpM
rBngbieLyqK2BLkC6WzjfBhQ9ppgodYHkSUIEfiOq/ZCBob/+o3JGt8Y+1YYr8SgCOgTw7LESVKQ
WvTgpDNTG8OnNyTutZi7stAMOu7324LARz80l1QVAV8+dwzLmZB6q+5dFWvoGzbdNGfGkF97SnnR
YbTk5ql3IiaSSj8ieDv+CFB2dPnfrvWZmMHh4ZqXpIoSsj2OHWeM3lQ51u5t5F8zCF+v7MdXXq0G
jEyljUpHGdfOmMPWHTWy0wYSweyV39mCPuQB9vxQSF8wp1yIclhLy7i3sPILdezxP75OPfnWxgnp
VlaSklY7V8FA/M9Yh24ejb4+Z92p09Jd+GGY84dFu5HrRk1zV6HZy0uzD9Hw7TcZHsM+3X01WdQd
qZHyHobM/l7XKeikWu794gPdnJm7gKQj5rHBUACQ+Fb6sSKOxTZnR8++vceFccxAS/5mMUuGQYfA
aJnJ6D5U14EsIZPg4D7H/HgLE5hXwDDUKomdBB/q1p0avo3IGrDs+9hrCQ4X/F0jQmp2v0U1xCdc
dNT8IYPJAmv8Qz6ShVvcO5LSs9AbZQQzqLpTzcX/qhjZflDkD1yhYqX6bSbEk/bbj8H4PP0MmgKz
r4FPb9ehgo1sWzR5l7FNb30paUC99cy677lEuk9JA7yWL4UvbntM9Cpt8zoghTQRUPV52nNnfIJ8
kR04Wt42aJzw3H22CVLD3uwzYkvFU6pXreGcZAP5rablYbF6hW50RZxsfuOzKAzsejcI0d9eFz3I
uL22ET4RlyX/9RwQj3w8+LCci/tQAiCgiqh1mOl7zX5pYv2wCGJ7cfQ+zxSNhQv8G2xNZA2wwvMc
Bs3oWwTy5ZNOfneah15ATtJF/fQ4SKc5kaK2nbGAXSo6ffvoh+zwuNNaxu//F8RNLNGbFf9LOHk+
sxZaxwxwnwyjN41VJTXztPubN15ra9qARhNjn+FFTQbtRARSYVHOegMNfELyAwElqYPGdcgHZu8g
jA60/a2UnL7s4fj5IilLTBeS3/Oqswe8dEZeXfjy6XB0oe0I4jB788xj11QzHtg2zweQ3OS+5kpk
NhM2+DPxF9UBOweGuiksfHSeLYTTbuLRtafZzHGiw/tmT9DwlmJHVZNFdixzwFmykRmtQucQY0s4
FdoUM2q4T/dIBF0K3xgozV6cCTgh2r+CBm9yDTPMXEqmeXUwFdxNNhpgg2uKyTagNc/pHXxP7XB1
j53Y8wS/S/w3NLPZ5C7XPCw17z1vXV5rLC62t7d1y13HHtEWzMfTlLB1pnj/X1qZQaEnzxbBp5jV
7BLGYiBBdXmlNF8lGnpHjlNpSAI2K+odaJeZb41HjUXqi1/NvAtVx3d56xmy2E3d5Pw/IPEVvkyV
AP5MKhCL+PyMvVY5ysQcbOP+PCDxx1jlXJtCJMW9M+vIuoG6NhSPzBaLNWmbVB9hKhrIQZFz7cx9
jm4Q/iKcZC6JjBoRrCd0oKyR8FPe+iZr+12FQUbYNk2VoRRu3hsSKiCSAZcLrssmat6m03NMdhxS
nPFgK+ncNXIJPYHJ+MWw98LBx1Z+s0mzeI1CierYtZQn+HxI9UOW1C41zbePyIt60lGIE8Tk3szF
TsxHa4oIWtuKwvlUt85t3rxZpSbXOEsIeolPRq2B2gi/b8VNcrzC+hXfxAjgE7Dof2r1Ali75a0I
gn8Y+MRETuhdJjP0t70LJ5/f50/BR0MPAP9mqexloG5rLo/jLUBZQVJX5bAD3tGnuyMgny0Pd0ab
Cfh+i41nbDbv+o5UvK373F3bhrtP5VYm11cKxwgql/BAnP3N13Jd3Xxu1u0xBsDCoSwYDPzYu0rz
0QcWZFn4j1yNYwMjvNbRJTO0URw1RQNfOWvQOIyfohm9F159DxYp/n9aWYZi4LYZOAs+UBjm+TTm
TJEzQiDpMmv3uIyArpar1RRO0/6WZ6iFtqA3ErsFRdhM6sq8yMffhSE0jaXAy9GZtZPKDw4bJJ2g
av/hj1+IAIJVEseY+jA1oDv83xUSzkHgyqIB0epM0UD/iUa8Vx7C750tImbDB0cDH74WEAjKMePK
TFm8/cuKRdUqU9CNOhKSEgDm07JYkFud/6eM/GszpzUJIfpb6ReVTrKgzhffS278bo2nxmUD/YfH
MArxQGmWK3YeaBT/RXUtzP1XFbm4jnoDbJYW/4GQTPj3hd+t8Dk+EZmx3C0IYHsCc326mmboVePR
ymAW1ozsPFNMwEJi+5cnY4bWYLBvjKuwdPIwyg5t9Ov22RHVqrwZ6+OnrludyLvQ3PwT8h0VlSLk
Doimycq8fPI/zgRCrfadqaWD+0fsPu3rj/PEom/yHST1YewYcAxiV3p574zBbukCNiAtK54B0g8y
Snb+2GCmXtAr7kT19SJoyI9bqMBFzAKt+Ji8t4CYmEiMdtz+BiNG75osGTsjiPOZsRdJ/D2o+gJU
KRgR5IJzqtHhVJCVfEN5trj+2Y4qr38Xhbl+gpYtfgdcujFZFtk1HVXAvuijp2k1lz4qzmLXTpaG
/BgKqbIJAp5yBZ6cjdabD6WysmpBDA/+mK/W7laRguzGUY+x5fwXCQtut9QYLznpH3SJJw+SiSo8
02RYYWfpftSZTlusnv8TylETktCQjuYBg/TAMDEuO8Sqc9Lb+00uk4A9TWsesyxfEGbh5cJPJI2x
FFClU9FhQAXcEnVZqaXJqaht25tLT+1wFogTVUvjGkgOPQbpxx2fi1+SV34aydFP1SN2madGcP6K
Kg/CvRZZv26dqzGYTAogX/0JdQjzvYJt1r/gJeAT8RMKZlIJsWC8zBInK/gWvANx9EJA5ihzSvrm
REvWwr1K1ze1NoTXSRH6bPjR0aaF0kEwte7uJpy6zpKEBIZScRiMi1pY8Ieo+UL5DKmtAoVyzGAD
sWLcktosXvjBE3nxt1Atp5v7Y0+ZJXzw4hb0VHW5kNMZTvOufmssNhOi0A+cyLMInZ1TSVDWNpay
EKbm4N5XnCbgXJdXVCb16fWPrkFWRiwOu7lwQeJ1LqMxFzBH2wF4+6ybcANcTvEMZqnzy52tp1Vk
qKo/FTGNcYOFgYukxejG9ep73n9fxixlJAnATCvyn8CBwyn8IbsbC76urjq5bsiDs51dyDu1o85W
F9FdDGNQ//8cNh4h5eNmpAEMrU0RTlqEU6XCviRk6j5GpdGDCw5SXd+M8/TmxuhOSc/c8r+FgYZS
dzgy+bkPcPdWuKxoCAhXgA1r+PN6/w0/f12LUBfBwofUOJjNSu7FA9GE9FmUOVzdyX/l2Fv3HJJ1
ik2XrA/aAWOckfs1cBLLR7r3TyvuKcqNmMeGcKEOjuy3NdgNZlWnVf7heZghFycgQbdbLjOEkFxt
Szq5z4UC6xF2jF+4+KXKxqB5EmfiNw7sIDvpc3/rrYmHDoVxPO1XZ6UtooFDORwPhRL0SRsLKc1y
HMgKbtmuSP1wbNHvPeD5P3B768yKo9rXR5k8fAYAcA55K7oDPIsEmSJFCQYUjyBU7ykcF3Ut9MKK
YS4V550PTazhr6NEcccDArbK8YOHnUESAkJhXUbstjmVbtn1PsIu1sob3M70sw114CzXo5GhPB74
mzo6xB/J2qh4dZQW8jXGq4e4PsqmG7NP5+0eO1Fvw1LRH76A6OUQvJpvy61fGDLXtCF7mz6Em/oD
UYKRRaQhjbRf3xJAvSXjJpYYdrYEEh8loMbfFSSW2CbsE1mtBRm/LWXvpPAj++kz0zqzhdm2fP9Y
f/fMY/zBS8T1NZPM2nIT1nmTDhOJcwSpfY5d+Op6YNH+KvLKgYnXKhEjCFAUFEgk1v+HxnuclR9T
ZtAyFixFRTMpPH0GWZe4Ai7shIQg7IQyffJzwc7N0r3WOUY1UVlrO8zx1ITVCpUH0YvJD6sdruNv
7NTd5nqm6F2E93cavv5ul2mYXXSphJ+smVza7UQuMMuvztTHgUi+M4trS/Rv6q3KnM0Wdjufc0e1
3kHaZOuXAZy/9xypN71tA+VeYrB1ZISbYoD3/vBqzh4pIFSrE65jx+LGpXv+/f8TCp5+nC93nmjQ
jaNJg+DDLdsJ4kRzGG4QbSKQXlgcruduf/vhcAynO/3SCYZ8AkPgnGIkbd7wBdBL/Nejzs/AHj9o
tSRK4U6+lcjgaHpPRlPmzRR3c6TIbnjeohFxR3dXmgtCTxAQOcT0ydVNOT8j5pdUW7AqM8D20g5S
KDHyhlA1O+rZY0p0EJb6e0AariGzzP0mQw/A0dQExUzmo+KHi+GhFBGPMkbqcDuTcej1jjhNsMaT
ZmziO4Zw1ByIZKloe4+8s2oKoQ4bCd9GizrlSvkJAShJhPLDq60hjUoIYR3S4HKMTyh7/dt3T0kR
TkWqWtOEp4HvFG2QkyV6SQZwcTFc4qwEWhzIrCRpbNYcwCoduh5vGl9KXI19woqTxQyrul+q/jG+
iTnQMQlpWkWoFdgIAfF9t68yRuIXSSeB/vw53hXI2a3pm2OJ7sKZQLxYepwycwVepzsn/zJ23feO
NgwIra0z2Q91AgMQt0qAKouWvKZyRgWCDUei6UAwvIh3y+Xp200OOZn9ecANtSJxOTeNYMMokRkf
STGNdLrZLwVjsOU2u2/E/7BNK67kUMvSDa0+Hx2ePdNuvpntmYT3PNoCJ7mshQcyfYq7UwK98mbT
KT3pBi6lVujLA4P59A1IuMLvTfuxyuVLxlRXu0XoWD4u0z41t+QqudNtNCGjxXIGeD8RvnI53JVZ
bsj9DPgAwgaV5sRdukOzuAjl67pHrQcU4EaRGNQKs4ico6WPLe8+MbAgiLE0MUdBhN1uU2UW87f+
ILHjpSP/Fr/rMcDT5Xew2X1+u17O6pi1SS48yGNMncT8GBwCA4FlLJEVcwSEzoC6YH/MpFv4DSys
JdhE2+dKrZHDXxu2prTbWxdEZ7/piqwehoXYrluwoBh8zWTuaUBrMhZf3Mez8+WqWP7orhlYD26+
1LbrDHvvPhnz3EV+uFl/6YDYUoU+8fcYcy4vSf0VWuEzyCmWLCfe8n4lCyZ4zPdMGBcxreNgcDtR
55OogiaVxPrM2kHRmPRscub74BOZBtr2fx/iHgF/Qy3qbVmxzN+Wojs3IwUXzG8U7D+B3WTodOle
40ppTsPwNiXtj/8w7CeGkNdaBQ0BfBoZm/9qqlVLq2DrE9P7GEjTXqZ3TDkbIsJN6VuF1S33C1Lg
pEqwbxtqqiC0fMUn/bExTPa3FbPSge+KLSePLdVifMpFLoZbTz9Yx26pw91KxP2QGtgUoqEr8YYM
iMForm9QfGf0vYy3xJlXeiDypSpNJLBSqSr1qUzoHM2UczA/I1bmPaQGAM3v9NOGnj0K+KLxcC9D
5YDrgUcom4tjtLVFkOvrR8jOPp/ed34qbq9QIMHWW6uLG1qwuBBD94IMjIbR8iDWACUcPOiiZsOj
IpQDKQi5LyNiTEgSqLr9y2UWoWwaLRtLH9FN48JXGqFDVlgqZStRL2ne5wF8HxoSJHmtHXOfj3cd
tCRXOTnWNG8MROU4peCuOU5oNj9GbO6VH6Boghu5fySJxurzYgdxkbYJGUqNhdz66N6L1I82yOxB
8jmXj0kAMTLxoUkR1rtaJihrXUz2FUX4sDXHUpXzygAHVMf7DNmuIRh/wdqh1i+aU6w/tMIMXk4o
YxcZNCbupiyJ9EDMMEGkN0FGLxsxPXnq2qsS8ZsFunCZevKjMie5Kzgg68qox4VUR6+qK01m2XE+
o1ul8i6jLAitusZUGNGwSNpfXqLdVFswhwV89WgYNxrwENHMyw3voebYVaGSyEkeGJKUqoNvZcS+
B4KNqP9ZtfdrlXX8W2HIjSIiqkhgh/QkWPaIFnVZpFT/x6cHkg90FM2pRNnIhbuu/RrZmtv4jBrU
g0Vv6nOsGOjRLT2hPD1GgnVwHksG416lVpM8XBbNn0sz3fNMIDsJ1hGLy3VDwq21ZvZ19xWxLEDn
bPGjCW73HTu4oTyA2bMXf5ttq93E6hWKy1ygHnDcTRJqqVxWc28GNHlWP5jmH8svcVqgh3GjMdTy
Q61BG8N2mC9+FQUBmD0Ei0AfRTHw2BWkO0VnGH9V47WNlZnJUfArZ3r54WCR5cR/EoAEZ7mpOaXZ
pQAixegM0tBZumBd1loLwwJwpQryZ0jE10NRvuXyyKBOddHZXppH7Iy9D6Apnkv77ghfQncm58V6
PYJsQ2ZkETFuibFiSHSdu+0T1pnRGwZXqbh1d2+I7lQScnwZO+mKpIeprvB1Z6P0Vr+uD7a7DDk8
uy6Xtf2IZKZhCqotTuAWUCEtyr4EYJdeWNmqSPthbk56hQFLuR3nztWWKKdB5RlcueHuvicFn4l+
m/SGmKsXMRjKs6g/9mFbNAiw3jeQTl6FKZzzU5caJLK8g/IlStvx65YLJpUyoOTXKqr2X8zpuIPp
DQGReFQxuBGhk0idfomAp7+sF/gcXK1dzGgbVzEY7H9VSk1fVmd0sm3YeR2p/wstjiFo37OZZLwm
mwGKNcOUIteg3eardj1MKX0HTZ44xASIXj10cN9I78yiaj6l1XpTC9DmA3vVtWXWcTe5T22U7Lw5
m5fqBGHt/69A0RLOzquJP9XexPLvzhq9+3jxTc/YhvwLeC10J5uzjDWVDUe9geV2ZOIC8HS3I7rD
yuEA53L+5KOcQ+FLegD1Izu8mzsKVe4hlfUvU6ZX/k1r+s3u1h7MrcGWZS9SyJnMgkzYFXqk99WD
waJw08beQzpVel4R+GBZ9qwXhWWGh4T3Qa0C89xFveM59AO5eiMT3H9EgRuL6pYZFaY0iJRyNKHa
lNnMhS+WbXCL3ZhcNbjd8y4Qe9ENgHdb9Uqcdh7F6wDrlvutA+kkxwGrI3aB6cNB5tBDn2zQ7N0O
giejACR2HKfbjy5RrEYdImtAyyrRhx2omdtlEmZZPbcj88sm/TJweQAKE3o9Iz7pODcMcVs37GKi
ynrNE832eUIwqt381XdGlx7lKpqp2KE261ElgSO6sMUIOpQszdGVqgjZSxMS+rxiGAmRnQ8+UWwt
ZpzuYEYsjOrWgItFSnfTw9DMK0awcLS1Rijf9HhMvm2sPGZnuw8+Nc5zLkwW7v2/SYjtiGG3PSL4
twhaoV8gkPQYU7vzifd9LxbFmluRE91HsJhhHC75OAknT1zEg2ddwZMoFpdeV7boKdJqgKKebo6Y
GZEcz4OvuT+k8Kmf43204WRX9VPWkmEaglSAfrXhMp4iBJ97/v6P/st62vY8TexJb2WNn7cgd+Aa
DUHrAPUjkHLhugAkARmyu/Tkrd/YwbJXv5mJTecpZ2nhff1iNPu2xfVdStwKYiaA0nLnLDm9jWj5
sQy7XoKj6iTq+53rClSWZFkBvHDVlzdxHJbSZX5bEGi3Y7v4ub5rqV5zK+qWHOUZdp9Io/6tRe/l
r9txSK//S3GWmqSeEfreFYJ/bKANP3LA4d0XIbdGCKXL6n5PHqKqQe7Fn9IYOBVI7CEs8QjQiOsW
U/DfE1F1GPyp49G6prK//vzadCw6Ggz7UgHk8XV2/uTHEfmLIuZTh1FcJtSTJE3swMVT1UlXamb3
PETGMD7edX8+9IVLUG+Y6+oBI+1gx3Pl8PHmYwWqv8XoRfehl39gaf4LSszLBkGwyN1oASKvrfQA
GgoE4o0Qd2pYK5YzZGqd7uX/4AvDD8q91cEKBYDaVdxFk05dZmAQPwahcVv113tkGV59hrv2jZyp
bmIGrl/p4/D/8WcRhIqL7TimeBjTOD+/PIQf6PTN49JzXG83LdhR/tlo66KSjgX7jS3S8BUQ4EHf
MYqCcyjjSZKevPOeM0Fxn6jI/NBY7JusUQk9ixlnNANT9MifDQiWc+tVEfH7MH13g27P6l5NhLF9
2/ukm7D8gfgdEMGLrS7xtYOPFycbD+hXJ3/fwmIZPU0XiLLo7320jlLXBraaFfJYCr8UB2n9tcv/
VMMlb06lWHkiRgCCGP3M2IDdVbpUy0Px5VprPtw0kMQCfNlcqJyff/RVi98BiTlrYnWC97HRTfAz
FPtb/n52obmblJ4kq3x+r/8Ox/yPfKzwJGAeN9Zg0rKpNDeNYRckjZNaf/u917vIidPgKKJ8zOUR
mixCn3uK892aVV9/Xi2rfzlkZCM1TiwBHUb8nayAUnhMEmV6EMCekbcD9HnmfIzInbeeWJA9EhHg
KexyofInKUQKgHrO4ojQy10B7asH6RPu0wzHBMmzCgIjSqfGUuSF+HoT+Bek8C7zl8Inx4ppHtuA
4qFeRzm7xLsS3P7CC1aeUmtmBAcufYkle8OuBJ6ZGZr4Ji4xPvj/bT7Cz7YaHU33FraS7z0JMHLP
KR9MJsSEWwTl2Z6SR8ptBbxpRVrsE4Fwsgd2Dt8Qq5J0n7REnGbl3Y6DDKmCCUEOLRt4A9IT4klw
qJTIUryK0Y5wCKiYtex+AHLxqDndnFhCXluJnAljeNb5/b0oYmjFMHxQ79TMAv0MrHs261PDVVpv
hcE2gEVpTFgi0rys8glUEqKph/eNSdWN9TYGbTahtn21MremSDwATQ7n15394llB7b+vPqSclVvE
Ey5QZgQ3vBtLww1BarVJCsOOtS2Zw2VDPwcK2qS5O5g9+sNcvyX54tpzcH9xwEiOboMurIvwqDtA
BCChh0RlbFkkUD8B1C5TORKa2E6kq6+iJ3/vgvs2yptj+6EcyqNpgJl7iUuFfY4+NjLJJjvt0lWT
fOdt74fkdBQvA381R5tZSPMX3oX/52FzJSJIvCmCCes1LaqS39hfpxTAHrQMhROy7m5k6vzpLEUb
sRMGM09lgbCHqPhDxmXrXDxxU0J4c/RfAjbcnWU/JmWVBENWNnQDYMtj7Wk848Ef7iyzJVkVJ1ka
JsevJNBDTg4Llxs4k03U2EjlQ06Q1sUUOT5JxzaA2gxHmjuNu1dAyKln7AXi0Mb0f7yVRjfGtVlU
k+3wf0mE2CwnNN9+fWPJzX2aOLvdX3wFkRH+Yk6lOXToXDWmBPgDXrlesiveFF+ZO1IgvEWF7jeO
Z7uAgs4YNHraPQ6gnSD67BoiMeSWdJTqv0gNfOwel20UFMoznd6r1Q9bHFy/+BK3eEiDO6IgioQ7
ehqpvLzzpemzoq+Rxw3h/wLstkQeYIY/rP9hgMNXLfAhnjhnsc2PYqLIr5+e5gTsSc7u6FttZIKg
0IDOEoMSflZroxX8Ua2dB+Uy7Z97ko4UnXW5HJKN7a0iN44Bcqnwc1Ye8Z2+XeKMuO5M3UtoecM9
p6QMKq9Ph9Ogjglu4QiYsqMUAHYmlpybUPJLnv/TyukqW+BUxiWjHiTJEzDJRRxbh87sPIugvYvA
sy6zdXYPWdjElZJES4CZN9CoHDDHAloltueTCOMH5lQINUKVw2cs92WNr7agk7o9TfGC9z2FtdMb
9y6Qgt3wxZ0sOWURHaN/l4b2b6XRtV3Tz16DxK3cC6R0ErrdmCvzYcPh11dEJjXg79sNfxdIytbK
mCr9dy2nmKXrIY9IXUxRrievMxc70GcJgIivnfaEeMHH0RQszUlvzyanFmDv/3pycwck2QKFPS9T
yLmKa6cl0rpLwmOB4po8+BoWuePLZwDcXwVqKgoq7YeFh2gVuZD0PQzjKqkUI52qOR7KDa7AJdv+
TU8SW3yGJHffS+OlJ746LWwsPDv7QyM9h/dTI0F8WN1vvWQk9/zgv6HHouKjJHkwoJTWgNyuTrXi
iXiBFYb0BUOAjFuuXWVnK7EeVAnm60TEDbiDS27OySY3kKEuwNMUEHOl/9KYr9dnQ8k2NwEhHM+a
+sBcutUc9ayOeJZoMFDWJ+kpdO8uG15SEUULHi7ldycMR+gMUIu6uG0CfTAEvu00rTx6Av8BGmvt
EY0VQsnazC89Vd47S5yd6TJfGHMfCztP62tdVTCq7FyClYx6eNzkE0rx8/Bq2me5buY3QEjdohY2
Hz7wxbZFDweGRzrNikK/Dt6G3D6kIq+iL8DGyFETBA6abHyk9qJqOHf513wmctpMGEpXCoE7VVtZ
FMFcWIujyKaTs5R7xuzvS0zHSvLLH3M0OSuLtODeDgQuz65JZPVklGk/RxVV8ht1iZR77rMlwYVV
F5ApoJxXxyFm+jRumhEo8mezlyb2XD5+gvoo7ULiiqKNWzDKRGMPpnOTBjuRXoeXS1J1QkPBOQpW
U7ZW3MEr6WGDfnzneWmVHwscT9149UKFQucuXXz1c3kVbsiH4oJ3QrW3nEOxUppg8W7MUFqG3Ad0
WTm5WDQ5hZ63vFB2kA36tpY7wUR4DSOjS0zkp2h7k8YohY8VOj240R5VtczHYZp0d6PoUSTpaFaE
sXCg907Swk+1Qch54y22JiPllb9XOVD+TBSJ96Mp/i6iUcwfKeiy10RNppKkZeiCq7Pww+vMpuAu
B7gVvpDToWLSrbXZ+1hunSP2YCfTrUNZEOoBBzgRVQaJeMbR/92YFMZgRZ/EHvdVeKg6a0yXgRh2
e4I8xVYM+cVXNEXM8IHgTsjZzu6bdFf1Y3HmREBw26Pm5bQC3L26bvtMePCxuHtaZ95AWuwPCNko
xs8jNSecAzUquccXCdL524xlGkCBPTO+Mf39LdPwjSxmsJstxoc8JJndTAHsKK9i7luqZr59Yogs
v1LikVD36EoNjUSgd8lXUdOt6FEryY3V5RbiUQseoLFxisgIpc3EUNZxwqGh32TJjtu+qfU5o+oR
SGvRIjbTjr1a+iAwisDwppuOK8+6QcTLRDZAVN2Weml7lSCkxdoRkeFRwPYRO1Bo9DpxkAql5yQD
SHSoJ5j3UXj9sdKmY/gtXAmn5ddnpEs6gVybgX8q9KT1FOnFvd3to3fLriIX7UTf1gwz3fDMV3AF
pyPnS9Qs6CwtV9dnDEXjrEu1KvjXwjssB199BBFOohmnPGSgYWhiNfBHajENwUuawfXwyXi05o5y
oP238wFV5hJCdA87AZBZX+Xl+AWi4RoNhnbDzutgX5akY0j2xJG5y0DQB4d4IBKGFRoU8fUxDIzt
McZrHXwfeyc/JDZR1ELE5bQDv5YdwFczBLrVea36t04tbGIwScdKbSTVwgM6L/CNmQPZ7dF5eCl8
LmGVU8gkc+B9DbliCufoNqDeEOv/km+VUad+77LzDVOgygOg6US0rblp91Wny1Sa2GIEwCd58vZj
ANR86MUVCsC4ArqLoqMTQ5aOx6dcj+tGWU5PJs3KtvgRntasIwySR0SvEv2sWmUR1VjqoXVnVDjv
N1ff5L8oCezi5UKCTqGwLplDaVI//taVGOzDjyxckQkGtWIHJjyTxvSTe6pmdL8UWjstACzq0Sie
US0KEauuAShb391ws80PaN5A59H6nASCrPc1cMkddaO0JXiOu0Qyrvm1PSPfIiq57ksv/9FCA+LC
9TdOXBK9RtmPmgHISEpQ/myTaQfYvQKOrKqWK46X8u8lipAs173g93GWur23oXjxtJ+92ABRjaA1
yyf1ePtXZRVYhpnACg3jxZ7mDfM5O7U6sCC5hRMNSOsxYG/nE3kdcJdweWjSYYDVL93/c8JjFPgr
DHaahXD8tfwUxV6CKXJd+A1pqhcSMrR6dh+gt4pw3pMjjzLln4eNJPVEt+j/tD9QOwpuN1XsFhb9
E57QSQbrZ/d+cXeMDuaNEYBmvulTAPqD6bHl3wO99dktNMt4wZlPSwRaeL3EZDsBvZfE68QAYs9Z
XdMwIK7Q8xi6s2Q8fK6u8vshEY68gd1KOaMSk4qqyCD8cJuhQaK9Uw9C0BUjqHfmnCD1u6Tn8RwQ
Ku+ymx/qDMhy3x3s4CsHeVTqMUB42FGZNEfvaob2rD2XWxoxLt6ByH4RI3rsx7IoWYBPnIjBpyzT
FKyfRXDOPWEWPet7Hf2IBLwdpyNTft0tMP0UUBRzGFPYWyGZr3GpnsT+8tE/EN1QzbmOchoZdcp2
mcfjNHHE1ji4PZPS9PHwEfFBMbtca4WhwKnIWoIVymMu0/BOi/e8jaWC0ukGz+ocnBOSKgJjJpGn
B5VFcftnI8GIwkwbcm3jSf0+nw/shANlbix2005e4mSnIJmWIZ0myXhA6cMsZt9la4ZX3IzcBLWO
VZyoHSAWyFVf0k2kufyozg7lREZviLowuh40wvLtd71JzPpXZPyyt4lroo5Z4Pq+jstVtKDG+JNc
LzYjR8+VNKhJrwLs1jbH9Gs+igIANrSVD+qnfg2jAn5ZxDN9HKQW2YTh8ukYILosw6PwhyEki193
Y+cphjoRWadTolgOu/3i6X7jftAqnB/QIqlI4LTsQjGcJGlVW4LJBC6G2E1/fFEqUNXYqFhAmQaC
Io5EjTuPi1noyBiX5XJq61xxn4Xrm21P7ptlcoS05bJZtnPLTFPk3h038r0/NmlkZGZP7O3UU5iz
gD+rk0Ikh1aF9P6cA2RaRrJ5Npl9yrA5hxGSdUX5t4S0eOWJYu+66WGUJ8KhnYptJlN5TgTOR7wm
PSjSYCH1xrXYEAKfkc+0mKTzxc6swHZ1HasLWcWt5sbN0I7eead/bjCormRwdGzl0AcLvCAm1fa3
cpuxqi6WWQHqdQMx2PcgZN68+FgidbV182ZDyjdM1D53K1eE4VGIYKjWL8aMrHtZyX+JYUDNWT2Y
WeHed7S/WqbaoWzpWCesL1De2w/eidKKOPSOADV3IG8BF4zeNgkGOXyI/ebYroFi7+oXsk5DYbAj
jWhxmZ2zNWhpWzJytP6zp0CRxGIjORM8/mGqqHvCIxtNpO/Vwfp0xRqJZi0Zrm4KpUfPb1qxIJjV
uwK40k0ROSsAYTf3TrrO1CfcLMw6RBc6KTA44QYHEngIXb7ovobB3fxEFghLZnILYX9+xa9BOd/9
aBPfyQJ5PT9NCUfQDkAYUZzOSFanjNxc5LCLyWIW2TrfdyfJw3lQRoxMStYoqU89ITztIf9a1gwS
cC1kImJWrI9L6mPdEC1VDI7LAP4+EKNLekIfUdNm2dFN/1lN9AB6CkaUbCCUgY5TCdMrYscj7dGT
NPn1baYnrhK6KKkqFCMiCqHYl4kssnkez2mQJDprBp248oHHKdMF593rWfHRcCW++bksYUA+fVhK
d0SgMmFX9k67cUrKyZsLIXXJ18JYq+TjKL9sZre3/Efznd5gD/fEvCSHi/qoDK5drbeOml5NjEO2
pFiRduYnF9g2QXi2dtFmDPCtOlTXzSm9ZaYE0ZaLCVAqkc+lNJI3+zMHbJR05Tfxn3G7vN0Rk19O
w160aE39AhDBVaAKGzTraQe/AkPTo8oagZbWx/Djd4T56MYMyDY+0JErl+xIo8IqaNFydy4qLRzo
X9Im6VxtwYaT8YNDTyQU17Ut9Zmimao34DhWlMlV4tiB9uy6PPX7cliZEYhfKLaWfHBMa3zZpti0
cypvhxO+kx+tFeBMklqSi0xuXOtuIv/fvrJB8ps9MGv7JhWah2n3CIzfUJjnI6dKsbL7vbtilMDD
1es5d6swRq0ravQ1Qh4W5aY/tWvXwFYmq6spNsqOe9525nSj/eb3WHYJafM+tZW3DS691BWMEbtc
yJ343s/Zzi5FzWB6m9XfbMOg+UBdh8HcEhPtkd2sUuMbhl6PlkN0SzByJCjufXXb4Ft87vjZxtVm
bk6XX5XXZr0OI3zY1psyxtft+f7M6eDNrcrwsmo0Eicg1jcmv49qTfhWjP+hwaAu5q/yGSpT8jCm
l4zgPwIkBVnQAMOOH47VhoBmdylJ/EN/IqwY+XdyjoZQGy7i1M2B2mg51iQFUJjbXc5BNaInjPc3
vLSOjsokIug/bL0/zzI+prGpjUe7wnksCmPARf8EamVWXTyEyc5LubIjBdSpJuvKdGq1RI5YMkdq
ue/k0RnH5NkkDTIav5tzpn/tAiNtoTBbqfzK0AcblGKUE9w/pYfC250Vc3yy9xcqYn+oh8e5jWpy
flAO9WtloqOcveyAhymxDhwcY0zdloVAYEtHMdu/wQype7F0lobzUF4d6ueE9rOWbr6DCtik+ulm
jos6EV0mUQzOVaS2P30WZT1cjZh/9ZiVhPawvtONmkU0F4H9C7i1vUAvmKCmB8ybV3/tm1pj6b/I
YxpRO9qy6kHXx4ENtI8hq3dZo9q6cco8cPxceMCF+h1u6Sun4XRNSj9Jkm798U4yC0Z5I31h8XmH
2d7WRchPTFKB3ujaWFMqvRhRTu/ToexJMkrVJYKlkeG8SDhUnjmqJdjNY0O2AG4M3Bv52bwgOh5j
ynzee2xYJY4gBqMz+3Q3nAnSDqPVwnrs4dwn2CLIxYdWgQRY+gxX6btStMbirtdZ4klhJraZWECL
B0YOTrjZNIFzIM2FdMk5hUgnIC0G/znR02U/1dJrH0BhjNZQMn9DLxwh3cow5dRgSAem0RG09y9l
vL67qMJVkNurRl4q7Dvwp63KRzqQ4x4AovY8R94ri2i0mqE9VwxaT6WXdlkCgYCBZ6IiHd+44RkV
FqSo7BQSiPgeXvXxAplAdVwcbMXZOp6FuYwJkhp8eHuIIPDD7l/upfb9TTsIv4UhqRFzgy18dnO9
oj94HTb5i8rukXXJDn2arQv6tA+XDu8/aRTAGmBvKWUg7q35DreATNrSSJEA3xLjTCm5sERZZmpg
tARr3KJ4uROcXN4j/F6hNqogfDdZd84pP8Su9NNz/QegxwBLQ0D/rzw6hzUwLSVhVJHxfhPESE97
jRIiKS33IYuYnsBCFHn9Vw/bsDJF0swOppFIaZNksOObMnJijK764Y2iaHVb0hmz90Rw90meAqz1
dLpzjoRhY5HiHbos3L0Oq4hZtcbkhmIa+J9+T0KR+FgSz2G4Rh4KaokXTyy+WCSunkQeF/GxBLLy
v7YTej7nhtJQfJ8ucRAO/VrqFfpxWa6OVC2VCcftxxZD2US22efNuynsK2Xns2sEhAD/XoBhryL0
A6iXr7a4Qtkif6ztgHuEQNSEUaVrq0rxovxmJIUTNd34s+fHJ+7WJ/aJtz1Bs4Qg3J9a4UmTMvaH
5H88OlRe4Qk7PdGXLaxjntidFdypCiFUEgJymVI8KKPs1E1qyrRKNAqGxhj220UwHTu6T1W5MSaT
XJ0K+/hod85p92Aa284Utr+VoSyY7BIyIa0LZWb1RXmNTMdtIdYJlAK9sYs6NQcEmq3RzknUTEp5
naZWw3bfdpvT+bfbzRTImSRr5bcMAjeDcpH7zz8Qbk9/gdj56x/xYSgFOhPAUPrq2YXB6dk2CU2T
hkkKBXtTzkDSn6+92/1vNV0DHPdH50Zssf9U029WSjAv0+WGe6lD4mBuNqKdVJMJuxdhb0hGjb7s
v33EdXNCb+gdSL0SJ6y6Pyhmd5ifDbpZWnbOpOrOSqTrfuknLu2jfdBXgW5yOz54EWt+0oGfRCQ9
iJNw92Z4SXO39r30A4x0KA2D0cb9Kb6hGFYii7w/q5NrQ9NBHvobSceM5ooCkEaSHuHhUks1ypl8
q6UiY7OCuKxlH4MyXA6/OMn65EZEhDRwcD3K/ZmFN9UbsSU+TGqhgA0fvh8tBpUZXFcQb1HAb4uh
EkpHc99dfgYyOikXs9bGqTMQ2bPdWcwbIwfFdzAdYQNaAh6+OeJrBsel0BuOmG4xUfa1IfG9Z6be
GWQUvJLClSAtUZ9lemPYjVwLPnf2rDU0l4DtMdjRctR2MK2Zvosg1+9vQS6Xsj5ofdxJO1VRam48
mnVCbutlJz/qKf+x0OqaljBCpcwZ8QA6aaoe5b7VTaOsNnI1mr28EVFOrk3xuNc7nAlc8dxRpvZq
KdjurGkelghKjo27aLxxqxv8t29/NmbSgVX0jjZiHdkj/KJv+WAPJpIc4jVQ9JR5yYe0jIrThTWm
iHJSz1etU6m5M0iMCckb+PJQY+WtGBlCjYtDrIQGUMNlAY0ysMx8/l9Uz8lIPDkYOfTLzfadiO/a
NZ5uM8pJD++IU2vDLh8rJlFmN2y0HGwPn9gwrrhdaoifqyxiYkSjWrcCTLS80UAXTXnCf0CtacYg
AExEoFWUcfXFgt9jmC46HxeikrWO6/cEHxApX1eU1sZOg/4b3yWJOrPAdAZYcaujVaktfo20jWWj
xc9wXCcHZwH4v9goQowugzuI5YaiPKTkta+QWJnKyDoZ3ict2n04TSEIiEnAbXS+uKAmMcwdrfJC
dwnZpacF/jHUF/9cXtH0kZBahz1EvexW2puNbu3R1c7XFBnmYfpMvOerYzMhHwfNjZhBlOO3tiGA
U3T/kHeqoikpdUEMqcaJS43eJ6FSx4SGFk4TZeKAI6dXez/Wl2Tujv4lRJGshbmy8nUAaoRNZW77
mVivVkzodWTQxZCiXMqHIgrqa4mGaxVdohVJYvDQQgWxlx3F2scNc+yntm0WgMk+Hvpa2HAu0Oqj
mPUEiWomjp5yymUTs3ULrarfqP86pUFY/+r2NCPP+amEsJqkTq9yQoMOuPUzf6FTOKBLSqm0KGy/
Wx95/7AoSFSJyj3BLyOZSIIrOvsq0denQv4HZvT7jpmAX8vQGZz03qa6puLtU9gngrU/QyV5y/ZK
aBQm6nivBk0IQgyzR39ZDeefzceO8g8YjncEaNZPbSiIM70wLU9BR+oigxYOY0zBahjliOUQCaBP
ZntfDrzfwDg08RXDNyduSBicO3x/GTuF93ZXF2vf7VlFqR3gOfK1bikhIsEuNdBZvcJ+wZarWIJF
fobp5xsqVIuad7iATatSTt0zziDXa7MNwKTGo0HDoj+WV4eqSwXqLVGfYH1+c71aFykvtBnRSgvY
66uuU4DlcId9aZQFh05VwbKWIECWG90Y+pxiqkBpewcFu/dshRI2A9V7wxeq4tNmrcGMuqR7vfBB
OpJb1Ni/+l0S9Y77QicMz7P8+k3yC4hhGhznkPwKG1Isbsp3b1TSFwMg2fZt9FtKM0vdUG6y2AbX
Q3NNzRKAIoO5a7JqgJjcFTuSvFsZMTr3jPCXakfv0/wzCq4FizVaB9sCw+yZ/esfb95m0Bau4RWV
r0645uWK/r9+FL77Kxlo5wHNRPI3ZagMvYlv8qDAVtNGxD6RHLTOXBWmZhY/2KiAHvG8MdQma1DB
2PaWD6hRN13813GIav7AjDwIIwHPYrIzg0qHhAO8aPweZkeoQ49jq/7h1PHc0WI4uaUBjOOH8g8Y
OrlxpajEspNeiHQvr0ftqC2+lYSULxwPumbQq1ec8Nu1vPvbu1GZCUo5ngs6gRCjGOp3m5QWAynz
vEGmaYWaonzkKk/SZjUfnmG/AVEb3DKJQqH/X7Iqq3w1mhwolIZy1+CzJV+p10yPPDQ/4WY+JQnt
4XsyyBS60Oq+EpHQH1WJlv7wXSDczlTJJWsdMnS7igEoi9n98jlEaLQ0iU/xokSLq4rTlIl7gUVb
hD9zeL1THddjbMYeWyGYSLcFhcimHNbT6esyPmU4mHc/fF8h4PnOeukUw/9KVnW2tEhK02ZWN8cQ
tvo7M/qPpReDcvUaNiSLi8p8NIMgLlqMeeGS1uyXhkG1KNyWaUfBx7cm388lI7gYyKNzaFPb45lY
UsRzTkpUUYtKqk8n2U3sfYRBsdImWWvCar7c4Ync0XpnPR/Amfud0gXdjRLLqtI0Zuz4X7mbsjlY
3skJ6MuCgfPPvsueqNt34NugL/ozefoBK/EXsqEiGtqk97pLWvagbqSYCXq4bgOHZoVd8s/jqJpq
Hzq4sCrKrCGO/ltEU43juluGHGRHInOwPSAC4Zu+eOhpOOqfPUt6ndSaXSFT8f34wGZmAulhA6+o
vGQxzszB3mfdWmrzIP0RPYH4QFQRB4DFBDGyyGZGQvo/pFhnev+YkHIPCikcBzv/BIniBu46mF3h
tuZNdK7uXwuRVmnhZvS+QS0M2haTA8CV3cx/Y0l0EMPccVf8B2ItUTOfHbKIIhJdHz8dcZMR11Pn
GlDqV8Eyds/tjSPffF7kCNNZoRRhyk0loKK+kMVNTrA7r1W687T66LQTw20BWtJIyvf8k30YSuG/
hAV7nwbzcCU28HlCXpDBVSyyp/gGG6gNYgh5KmbB5eFZtBY3sNbsaUH9UXNSf1jH+8Hdofd0QSIc
j9/mED7bPQVjgxMzmLTrz3hYEtcBZ8eUlVh/0fgsEn1Z2J8eh5NYGznXf0eXlDGW3pIlutxjrdLz
burSVtwqhfQ8w+nJoea5HfWjYcAhXNjh4hgZqXmcgTeypV6PIZtHaw/EEcSo+vRw3oOqADUqEiQR
nkYGIdtqEZtqmbHTYWM51tbRHvqmkI5sqJI2QJrNm7QCcoP+oQUrq2bEcekyYdUQOIs6Iuaggcut
HWs2t5b3OVNPo6a56FIwiuUj9A6pqsvIx5LlFaRqGicNHqB5VOYcxErOz54WtuW1zBxwd7l1vgPO
310Nwmwuvsj5a2lYm66p8L9UB8F8aMenZkrrNTjWM45tGW+quGx+KTYkGBw+7PltFMQFOgZxKwMF
IKj/f/IQXhs3b7a9zgQvpaen731S4O/1otfkcybrqbxZmat8KgOYFqthLMQ6f4zUNfou2xDlMwNQ
qWCPzwHamLLGf2sifOXroquUMuhOcffCOBvaVJHTGjrNlhky0yGP6n9JFdLS/hbyovNvRySiEMo1
xhCph4q6taK11otFg4MYHXphrlYE84Gm32Qi7h7DiggaBKIWAD2ItGt7vIg8MjWE0zyIYleLMgzG
AzLSDyRQESYdd67lBBHvqI7jRy9lEcFWh5fNtrt8K8AQZz4zdr9kAOJD7kisoCIGMNMOR8PWT4Lx
mkQWmwHamXyee1mPid7w0BA+TF7TCMP4AJWcx58gffHfVBn66ztuzyvwHhJHRknOddiL8cbzk07p
wubuYWxK70BYajrJVMMWVP9wuzcVGA9z7EAlRTwJIe/CpadFNE5XpEkDissBfP5HC7ePyWazw1Xu
I7IjN+ZnlP+QVyeRgjWwjw78QU4xNezkWguEbPUW3zPjNWFd/6zVH+V3cc+syzqXq4Nqjc+B9LbF
9RtaEZXKzb2Zx3FUovNGKMIMeSn0r4J/S0D7oB4W0u5xTemA5QZbRU3mVYWrkdXaag97J+9foZ3z
gC8Fb7xz+zokVSU0/ZVFu3WEhPCH+x9Ck8FItvM4wo03ov0l1V0BeMmuc8Pl2uJy6R8uyfVPn2x+
aAuucIuGLhdkDdPslcehVTcKEJ4OXCcMAgpbT+Izi7dAXZCkduKKcUPoGwgUkBcLy34sx5Ix/wpY
M7fnmHOA7XRmb8Wpj7LD9fTIKtu2PJkd+r+1yEeSonsoIm1hNq9hhXx6GnpW7FHol0GUNWlaMqRx
fxmPXbbocGc9g6CzaGltbIm7LL8Ti3qTmLOca4/dHNdgzDy0GcSGC8zY61n6zfDMovXWwoT9Rk2L
hxPri7DAvnvqUfV8q6+QJfqmcO0VeEwROVSTG6ibf3qfHvLXk672BM35t+W8fBNihu/EjKHQCNhx
vvKF2ShEFme+go9E5bCw/WCPiI7zWVk9YJDEcrQNX1BXdQ4SOpY5E3rocBOMYAYNsqjizHcZ+Eer
mKh3ua3ru1arUgLi2XdnfwQ5r0X2DtLLiHk3fnTIMKzRzXh1KLvsAN9T5OMktAGq0RGoufVOJbLH
GbzL4gnRz6iktsdJ5eiqrQJHwQ9QexGapHhc521kk9XsS0KLEAQAh/Y+kJkf9e8qnPu1QsITti1P
w1AkUAt/AcZDqWZqlJEq0ryC7QGoYWLVAoxHnIlhRIj7KM+B9D68pID6OxBtZRSkYJ6kV2dD+/TO
FjB9UIqAhumQzy85gJJKj/lFE0M4BH7mo7HHcIgU3wguSHsVXAPkekiKFixtBVWqv+HjWQSCY1dE
BiYy2zyJo0qa6b1gEq+FIdp8mf6vAmHJ/q/R7sjOM2bn2Ju8TmkOwwt6reQn076k7dFKQIAodTiC
gE9Qr9uCgv570aToAaqnqcfxyJEsUbB7X+8qDGXhabsT/hLxhkt9IAiXUI8G7FHo4yjR9UBXq8Kd
ZJkCMhVJQvEO90FXKIE9OrXxS6o/8UYcbgZxjWdGsqKhZKexRQAkJpJKVBceqPNlys6H+EpaXOSX
bb6ZKcGr6NLO2vwWBEsmKjnbclM2PSUZbqg5aGCMGcoik9OIvRXTCaw4Dd3FCOdSM6uvMauwCJUH
BVZ72txRvX6Ob/ibNktUlvGnmlJCiZ+oIO9RHbZTyzKAHN1PNpwLeTQHLu7wbPQv36rb1u4n5Hi8
qeulGez8kRN66I3owjEqAEwvTVOshBiGx7A6V7z+gzeEycKPOMR67eYJ/mXtummmYFlwVf4CaZCd
wxypgf5madlvm72AjWvL0lwDOM4wqJArsJidckbDpBTDRdEJ7uufmbC4OFIbUaL+kMsODab5zwXW
T4gI/mugT3k46mwpfq01bOMC0pk+YhQ/aDi14ekGZwgnnezLYKy0Y2VAccdRNNnq9K5S1SmzGbHl
KyQjU6gHRALNCbjwjP5FhgRs9F1wq6sAJKDVvcBKS11WWfxuEA7xdpwzxaPk0TnHRNVvtomyuogL
gp3256RLqPr8GU9OsPIZXuAZZuOOFikzJzTln7fR0MzBvzxGlz/njZeUYfJAEPoEcWyGSJaTWEjl
VWNN9NhFzJRzkS4ieNXOSkyqKngimg13tdh2IGbSCOf8w7bg7XSO/jgjssV9Jw6U4jOSDyxdT8Hc
aGvxIITk4Q42r8lkGGqcOOXd0NEPxVytN3L0iFUqEXSOc6IUf4MbyGUHgNeuagGRG19ufxGJS5EE
QT5DQr5ebsZqpikhhkgZe4p67o9RufMB/NCiXg0wosKb4XOPTSn5i7bxVhw/aQ/Nru3h68gJFKYg
VqrwbtH8NGsyYQuMFeXxDuLO8aV2ePADsXGtPHQzBK8b27ZfG0T5aH9p9tSAJ7fdHrjQAcNJ7Ig+
f3PbDjm59g7yt0y6VVm4Zs0cH0Rb5EYdgNReeOiAq9hZa3MTw21ta5BzBR2kBBVNTEvXy5Grdnos
BEUm04o5D/1nkQhhB2mfwLszxcBlMnoIPEvOKvM9xyrY3fA5164x71VUxAz+hLtDwdmRmHa8nVZj
J4bnev6pJhCLrYZL7Rg1jSS3yl+q+drpf4J3jfgHcHf+HqH82VpR6PYHQADwz/J1Xn8XQPXAn1rv
CyRdA42K/H4Lm2mJwbcKg5v3r4SkVnTkbE6xzmY5gI7qMArLjlPjddGQFQBxZbOzKDn8wXobNmDS
C8cNmf0sdpIwLSQuk3pYUbu07g9EB7TRwL54LXwYm1aUflN4YzKrZQbplHsbmMwo1CS/mdPjI9jL
NuwxLiBponVFhdDTr1UCt1S91ZM1dLyROddfR+2xpcxpkd+/VJpZnvELvOXe+KCaAqJC1n+0Ju8m
WMRsP+tMwrZS8Jfs4vrIwr9Q6aP0qg1WiinNGgR6Kp/KvitkWidmLFHG+GexidSaWoXLHchkYHEr
S2//ZdP0UrhXMKTRNMqf9rVTXU0bpv3is2wQMao7DVu/V3/7Ac8qARJT5tehX+ZSel6J0gvt8RaW
t2sVgPXouB1/XpK3fCResiyEQQFGeCf+jjMV1f/NLoq2Y8i4tyRCKVshANxDiPmiekzfQ1U55vhx
3ByN1e3z1ZPCGeDirBrEwCED8fnzOohS30+YAy2HqHK1J+tIl+0+A7xf6uA+NXmnSQgO9d75gocV
ypmjqp6x27jaQmP5e0h3BG5/RRSXjr7k7vBx6VvjVL9vxCGmh6EX+pyJtUGdUngyyMNS1Ep6kzd9
9/wZlRcsXuSuAYm5CoFYz4ody4I/rKOZD+DTz5J5uPC8hEnSNhyyiU9tdm9ccamKocJUNVmgbn7D
AK8bupEjwzJOUOapLI6aJEZq/lzKwOi8HtL3J8xRaxBbR8kqWMim3taWxmSpe2GdE+9LsgNK7AxU
1P7uxehuj8Rh22Z+nQ6WK/DrBXToTZi9Ovt9E5pB7/a+ZbpDpggdTW9ZQodpW6uP6L1uyUc2hrrL
1gGlBDXx4M/KR8+ShIj/D7gq4QWMxlvAVBNpjwxMRex0kh4Bviculeys+aSBN8dNOVnJN6V2TEuV
dDxd6omtu+1m5Oo6f5HV0v526i4+0Z4snueFsj1MKavG6Ap5xzz7uZ3s74Wfp+naROD9TMvM2NhO
T/bBTl3J+9hWQtHrITMcO3uPZN6EetqSLlDRM0nNcFNgy72qpT1usvS9cR68Lb4m2Q6ZepieEw5k
siUhHK65eiEqwTcH4wbez+oWHEidVL7IQeFtBOZ6lK+n+v+/nZPlCBoJ4jVkswVXjwaYKWMA0hin
XplO0OCwahDYItJtVr7OZwG7tveF9/hyTmJKoDAKVXOLNQ8mPGfIsoAbtOk7b/gFJn9QNmmOCc2T
MW/POIJIYuyVcVX38xsAb+IdwjpeOr7oJw+YY+DWl1yT08i0XxFogRGnVPXxQuGd4a64ZIK3pQzK
uVXjHyvfrWAUnNpQjr/FTMdUoIV9I9/Q1Ud7xD60kGho9Zv1TJBSiaoL0iu4BghiR2sxYZeQL82j
M4mBWH7bBqaIEFNuR5B9ms86/rCCc83ZdsB4mXVnEcscxRLWNpWSsoukmAdeRbaK0WlK7jzn2mRh
etR0aKeVNkZTiUvLWIIXwPgwcu2VeGGftSNEJI7QLlHQJsJI9WQdFW9FFMtcOm3z/zPBPF8coD0E
VhZSrkHvqjnqT4j4lQJAqNFPnji5Nt4OfR3c3tTIx18+J9hhM8R7oILdNuWaetL7e4LNfLpmdpoA
gPYvGCXu5iD5iY4rUDO8IvzatsiARvsX7lOZHsynyjBLjns87xgn0RyS0M84JW1zpGlZAJXT3uip
Kh34LperkhpSYlqfpUPOzO4apbYjDb4uOx+ev52BznKK96GSX0kpkrJ2SpICXKaHH17HwcVnbTkl
WwoxnRmBY+joiEHUMZfijXb6fLLGkGuy1r/guBQvuySZDy9sL3pbl/zwyg1ngAbBJ1hNf5cUReO3
sPvxQYK+tAG2TmkZ1ob5XM2tM58y9oEMqLg8AnXl8T+ZAbqUF6m82/IU2SyD95dMjfZwcJjVAbem
84WEkIf7UhBsjTTRQd6UiP5bEajL280ejZDe6V2kJAszoCI661FX3V+ZBLamds5HPbvfrpebhhdw
uSwafM/a4S48Ok5seMzrti9gKojwlB5iLIIZ66VQJoi9Tz5jTX8HY05hCbXUFXMtyha+YJEZcwZT
R5tpFCpu5V0mWuLzMl2dVftVZ2r2joGJ97wqL5EMdcJwLdAnnikayGqYzh8exstI9MJR0lNTXSlE
Z5ycDhBzt9weZak2+g9JLgwIt+CY/ihpcCaGKVteoK5iMOOYm0vM7txuuMuqoCk7xTR5ym2QEoM1
ZKSteWRc81E9ih9GXdrIQH/lPzNeGiUZalIyKTjZpPpQgxwifKAR38IQGyEcUvp1/QLQPPeoHS+Q
QEQ3pngYTmqx/MJfALWKePhcOl/Jznlr9y/3AQeFd9m6dhXQtMAe1Bj2P2Ns9ZRA8BihSVHigSo1
6y5c79x/vaekHjtyjnvr6Yybfl6X+bgILICB2pRroEN2FKgQm3MdpZr7IygNXmef8kX3KcvVtFsj
iFAHQMcoLeoSgO6mVz7zNYOdmRMQKshfEENvbaV5HUh+mr2StL+Rhbri5BUZwpQFLRrZaCFMLSd+
UOR6y1KjlUBPp7jhgrJAq9Bx51o+8Lv5GFYn9KIR/EDuZl9x/RDBap76h01PuUMzWcAu1LRm9XUS
FplT0e4bDgOD7tiqnB5R9X5TLdFX/tJWFOxD3fh3Nb6w3uGb1ErIFxkKUYOJeaWALiaXWaV3+mus
1iJMTJnqydppMU9R5okr+Aan/TKbW6CpjlrI9s3+BrI9zu3B0IzLBFv4DbYBU/ATTBcoH8vDoBeX
Jbmi1cfByIDnome8LdZPQYxN9gpd5AwfkukAJhg8UExb4SrbjoSAwA7IGJNmBT2nbkPO5S0Vuc/x
DT1+AIkPiLkAsIsgZeILEpkgCzUh5Qo3OPF8jfTbUYw9zAzqxhp9B5WCQ9naDn200QCF08uC6XjJ
akHTnwUsW8D3AmvwO3J4hYsVVV/0keaauYCiDCbgMvqKzt4bcN3ldmli+i3mT9OtLR2d7Y3UgjAe
Gf9WGIUvF3+ZqBEpdtMQjrB2HF6P4MUmJkIu6l3uD7xmge7QX+JwI9/72lEFrXtzxBViHHzQ/ftC
yPly6rHQpIYKm0YXLmby1ahzbJcw7+SZjfmiyIXVuccZvGzvoQTVXm3W7EUQP5NX2jkJXW7RGgmK
T/xM4eSfepS+EbioWp5modONTnIW9KGpLP2vbRd/V8vMmpqbmbdFktW+UgDutux3815rypfVgfHb
zYtMSB7Md3pe/8qsmSyVYvOkFoUxxwLaSrDmfI+gdazIvMkOJWl5DS3/W/3r12OWCuotE0GkO4ww
8HjDjR5Jax9bmNlk71GH2zVMtP3lB2g6notQgMQ8tROYwvbf2nNpvckQ1ji/7W9yBJaM9W4VDzM6
LKnjZRXJQSKwqW1S0igE8nhiSw2wT10TfhI/3LuUoh2DszXmKInxRNLHjVWYu0ffuWUuwGBt3li6
GAPDiYapVfdU+5BkUck8VuWF2AzddBrtdWG1DjBa+930WJVrgeWBzQSp4FAw3PZqyYuujGGh31G8
JyPAfxZU97YudQzRJSbDqP7rEaFz/BtAxqHtbYI/mnsNnE85GKdrEZS7QR58GySTWyz5/nMYkPA2
WtNV0dcLYNf79FK8TmWCzyZ6BesK7ujhoaqrsC4AqhQzBX54x57KQkOXBMOX28DEdbl/TTRXZKzN
se0/A7ZrHJgogZA/KSl2k1HBmyx2YkYmiOvgTscq9qQwSxm1DNd8iH1N13DhK5v3b4Pc5Fjj5tXw
ZQrtGAOcO4YnbP68/MlxWgjqeQWWf1HL+xD3visX684s6MEoh1SOlJxhaFipjwZmvfhVXfyROdm5
x3s8qXCosmgtP3NtHsKb5atCePT3z+/oOyBLDg4WyX/7mnHZWLiZ7IJK1Fe5pfUXQw9ufklRqbXO
bx1adu59LhiEST02H5Pla1xuFAs9pRu6Xtv7IyJws3+j2S1XP3+X/t0EdvGZqahmcBpFjkXz7XQ8
2MoKenYPZib97SyOG0aFmQTKKPZWSMUUw1N/JSRhGWBEJ7C5TsiePoPONETKjGRfubw4fCAR4W5u
p40bEJMIx2J6yM+9+/mgLZWwFy0RZ4NzYGgnPz4R6DNKHJjim3ILQtH913q1HghUXs2LdI+kqgWD
fLu1KPJOuuv4JXaLHnMrKK4RspIGFQ1P6r6+3KZ9/eI/QLinY/cWfgxyf1Q4IUWsbxY4vmrrf312
WC/tksTyQcXP9FEjytG1IM5IkkUeD+CkeYED1USZy1d2arsYPOpa4DHZPIwAE3SldiWkTQf8B/hI
te8bgYAfpftushUyesMEtQNxqCItTdrAd1VPgEcDuxL2AbXrk7LdAah5mmSB7Hfta/Vh20qSMP53
iBTLp5+lX/5kIPf3rDTvQ7jGrEtIm5pIHo5OJO/Ic1gUAISPAioE6CvKrauxzbXoeOpBFjxtg2D6
NjnMCEVL/VgpMJVhZSK6GWqD3buoJD2Nd8XRvOqFOalDveAzJoVgXQVEdoYUVLprxuw8JVjFHRDi
rWKYwnXb2soIzjtyIl2rOvTM1dqQcanTEAFuDW4Rx/3iMAazGQ1zsmIlme27hp2jCI48NzmBu4WB
eZEF29e+CL+ul1k5/nDKdd3dcb0gI0m9uvXM8YiTV7/KkWKzW5DWy0VmzXDKZMUsSPvtrYk6Iei/
p1dN+TbgEnshx3oFzpAPZsFIkYo6Mg0h4bzPvbA8ZaXAm0OotHBOWgmZMatgmIDu6u1K0n+3CGqR
kxYIuWOQDnIw9kXE23zu8LHqS2MC6HO7fKyzx0XU1/CZunNepfV8puSz2sPUtVdnCah5TjmfH1l7
MRVSi84mQy6dODrh9nT+MirumH/iM3e+k/qxVeBS5HgTmt7QSUPjtEdRCH5QMUX8rqFX9q1cZjWj
ZLl5+sJZKn9/AVdeYtShgSjp7P8bsf7UvGElizPg3YoLPy1/FGbAUI00mzng1MUYNPXnG5F3+agb
mbjJILYNl9LExqDY8xyDQSdrQPGkYpXRE3FnIZxkOZCSyeTi5P1l3JUbPNw2ECsJ+2lrFDm6JszR
ZxCqcsgX9E7xmbzWam0aqwyILSKb2u7KfqWlaJ8xjmCMXaAQHhxOI7jhfPdo/AvK/IEdUeuNb41e
zzdktzkUSbJIc5e7h7RqJgFNwXaz+4qQT73s9p3QHHlxXXnxWSWjVtp91dbafUGY1cVEID+1rq0D
sqLeWkrk0wkO2wRLHY7hJfazvUZzTPD34PBEZF3nVlCdgCH8bZdsuE/cJKbXcdRY8IHY7cNiMbnA
NeKw1+DHy7YHcVX62AtQtmu8wYhECHjrzuzSLy5zcFDCPomafeWyAdeGs1yIxnSTLhCeJo337/Sx
auHs7J8jexw/stgyjI5cTpoV5BaQ5ftsCK4+7xGq/y6nkgqJ4aI7fS8eydIIhSee8xQlCSaPEELb
jYsM1DGjgJN0Gb4jfLSwlZuVSTfcb+TE3E4DeZh8nqut7d1vtn9v0S82DkzJKpXXXuEoQS/ynJIg
Hy79gg4nY0IWd6i+VR8Z07omf9+iw+2uyzR0f2O69hCU4isluVKKLo8imMIXyZWUGO8ap9tXXAa3
iMTmFZtk2MxVJq+IeZ6XEUzQXFtse08JXkY6qRewCwAt8+oo3lAoAS8j15Dm3rRi3SmMKqOogcGc
tZwh8qUH0Dvsuyd93AoxjcuEyNK0q56jhDXkL+GC5m9DL5g9wGD0c/a8KtzH3qiC/pI30agRr/wm
tjivjmC9fBvrw5QltJa8ZuDIAh1ojBYwGq01RpZuoWrrKRWboKjntkhNCkPgZaMGc9kUjtk/+Pfs
Vh2ht6SiFx8Mo2dXab6T59o0f9JyE1y7Ned8Ii4ICwDO4oIcYKbk5bwAG6P2x7mxMdkuWpBg0ZnL
Put1zYe++VP36vykm2FQ9eN6YnCyGRsHS+Cgz6IcODOuIRs3JtVbzK2TMEHZsOVDnNf50Q/4DD3r
7wWnPZ/PjS/kYgeLaJ+bK1JR5rRnVemG13ZqC5DYmXe9FHfow6Yz6XjIIpiJvjdzGFQ7nG8r7K5t
3ShGgtispUigJJOmsdgRjsTrMqQF/1RbKb8I18ZE66DkWbhLUJaLQZBMTd1bRWy3TS8jwhO52iEd
SRRR6O0wqwCYcITse42ec4gmz9mYdJ4iwOHTFzmTLdsJe4r/7+HWrGpQTgCEOFb3YrVXBffeW/PC
tvaE68ertP/tSBoE7WmhMjZHnLxVZZdo0WZ/wTFTUBWli2PPP6m+PwUHrieDn4KFy3TvZYTtvtID
YX62ckfwkThxpRTOWGiOOQnzLfeXUZjgFPW7cFh2UlmU5KSc8vC9cq+KOQH6UdAXA4qh0nIJEKBj
cCKJmQCN+T3NMMAoZxXD7GqUmrExoHmQjhyZUoweA0Qh17dTfU9gP8CpmfT+EaT84GMmr/yYUpVY
Sw+sv7MVWldAcG89a/X5xfi91lstwCk1ZKhsg6/HmGF2Vs+GFyhFxiimoKGQ0QvI4qAvXOcR2/P0
PHrQpUVcheFWn6L8xIkDwcIxk6UmT8k1rAko4gNfNXrmGg0vxWHqwNOiZQA+09qJtdLtunRH197d
JyCtqklcteL/HLxR9twS4MmaYvv63QbdbrlAnDd3tm5ngaOGe+De4f2ZPWtySzeCNXPcChb+Ms1H
NZXbp/PPgeeW555P/8LgYVBps2rfC94m9ZSVdJEqyfZfPqoUGlIQjUIvMGGgFYPYgjmg81xA/rqD
CgWv3XO6eaAGlU1s2Lfrz9w1+wqomwtA0oZj4xMjaNCVgzTptyfDYSz1wXeZGEaEqSAfHnLKragb
H6XyaCGH/ytt2VgcIr/3R1ZRkQ7SWoruY2v2W4iAX5vQHUU0yyEwQEzsFrrh5CcELmaMHxaW+/N5
A+gckxMfKIyBqriPQTYVrTDPWqf3fuPx1WV63SRtXiboDYVTkmR+URFeYqArM8d4r6K0qbURMEoO
D1WBtrrZWQK8ZhZO7MetU2KmZBiV/lf2K0KcWNafDAh4Ldr8eP7tc8wcC8rgtwxvDMus8fu2q6F2
p09LdzP0MlqkEsd4toFiELY7H0IzZ+V0HvIW2SCaI4PSb8FfWZksIjym16PSP7GEFAMwE7Lxpl8a
M7csWRsOzjE9Wi4ASv144i95WozlGwNWAQOZ2pFtHq2fxEVnkkzFnjMzttxmNruK+emh9SuxvPfX
cFSKbyFnCDIDs0MZoWd2ksnAk07J7bOg6iIZ6Gk7LgZNwL2qiu4n0aEYgFnxOPmvUmEN7b9vlHZ3
VaRFXml6S1A6Scb9wtKUKeR7zEI9eTW4+VBNbadOfd9gXZ7Ui7sA6f2fxZAyTUaD7numt2ViKtEO
QDu5iebMyEOdGTr67LA/bat2fAwzTijv1dqPzCJRgiP5/kQjVIxsBmqBABx5Qc37jVuMFL9U9h4d
IcUa5abPOfU+Fa5CIPF0EmH6jgXed0hk1uYAV+6ZA6qunx03fEI0OXq/omepAsWnvIMK7cNWxQYS
NFMBgbuGJ7PTcOzmECUw0qkOD6JvYyTpHwOH7v9qQ+URFLro0IWaI6qkBDFztnasOHjaQoS2gxxB
llZy2Na9JbKflzoch3JSiXtdvuCyZszPEPzubT4tH0ceHAJgYzU++M8pxaSZGKcBUb92s1wKZu8l
lc0uZH38FADpwul0KK7acWqgcv9lGdIOaZ6NxConNVSl0nJn2dXLl2eDDUkwzkNA+CDCEcC/sMCV
keXnUWqm0izYn6llLAqynqGVLCBLnTbwRcU1e0XUZnSpsjMrmuaPACqpxFK7izKbeqd6VNmfOoVb
l9jSOQDNJAtD3dt8EFYZbsqEk6dQT53kRMtv7v7r+DjJyaVYGNrB9BDBh/XYSBGoOie16la4t1Jg
8yxcSzIoScAUt5GELRELRKGC3ICPfuvmkOEn0E3YXQas2VSvQYLHol9bfNOSfis84+iBG0wHMeSO
o5RnE8BBJzosPaGallQAg3sjd06xnHQKoCZlUUCRRuhNUMLpFiXhMVHVG0ZZckkP6GlMLUDTYwBG
aq+Fmt37pr9WwF0U4AqleskSnHsfF+J0f1xirro3LUa82s4hDYIeVbOV+JAGVNWWeQBztFk2b6YP
IrOYvUeP/WPoyWzhAwww7Puj399URm0mxYVR+X+253y0Gg6SNTVIC6qc8xX5rVWsU4OI40oXSqKe
6pIIqSs7VKceNFHz0SW9sxuCBa2o/IhwI2DJ/1pbel/Cv+uKzI12LqIF2gjlRQ9baVMPbWzorFXJ
WJM/faf2puVuMdZtyFVCTqwvdAG+pHsCpMp7FYyiVt61WyOJUOd0OX/9Gy3lz/ONcZOIZhQ5lzgi
3OyQHFCRXmDQpYh5HUgh72q/0G72Gsutqb23W1YlBJxsMBQd3A18knk/dhkn788vQBpxEsg2GjZA
2VIFDNoyRi7PKkL1QaivFIWZ77dOP5LgSqitkWVb4YgP/AktW5c0bGcsWvV8iuHtRQkNEJluZKpP
BzuNQX5aRvJmHYhMUpw7GVlkwZanmu0FIggi/dssWKWqFPSvtCn9Am0QWppAmaaRGvQ/4ceaaz5X
AF1xTFILnHszoAmBz/2zygtcoqZ+aCYqyZmqtFwpl6tRz0UK5qmY4Cg7HdQ+j5dw2WtPQcy2NTZL
9uaOQAEkIysdTG5adr8Zote3pxGJxmH7IzM0p4qBCBh9ewFNDPXEn+GqonXTpvT6mfg3FZUb8d4h
y8HWDQOZs4aQZmTkKbro6rks5NY8hORzNT8XdE3T9XizvHcyV/W4RdEc+0j26XdOa43TfPMHPDuU
p9FIBRl2OMLkXutkEmOfZ+7W3AH52LsIQBhBqW5PyTOsUNUCDmC+nTrIYhtgJi4W+s47XtW+QJ0A
FIEWv5kqDilUEPh+HRIjL0Dx2sRZh+viq6eAOYFeHMeaBmAX5NthltEdm45karJ8Grm/JVeq3HH1
6g1YquNv2OcI7p7NL/RUqy/nLjp3H8z85f5k1ErhrDsrH5H+FYLZDVi+5b3luePvZWewg3iKtMqm
/eZ2/K0cndmz6uD6Bpy8kLs0fAWGAX9NVGxGO9l2ptjPqbOU/zrQXOcFRNZnFxW3ElijRGh5PBma
UNEUIhgIYb92D7eA7CJw1r3dEHO/T9TX3gn/12Zp9NewHKnDn5ouXa2KI3Ble47px1OYn7DsLIFm
TMTp/Kqq1oBTdlGqZCea1QOnDpiQu5w7BF+WlDY+VEJ87arcE2fOs9e+smETUpBdMNOgcz3PCToP
YY7ManynAdtKa9GeIxb/dehgtnXdxjoEk3L7OsmfggDT7GHSOlH+v0duhzEVNxwHmqqDIF6xTmqM
AF8MTQEXbEPBV5flrD23zCwFcC5GhJtvRw5YgeDqWPIKFRommy5WPK3FDLdT/EPZD+wkIcv3Dc17
q2kPrx/OC8votk9Ql6HU84wThYEVHdUTnwFADYhGSMc4111IoNDFcZoWr6vDx7vjf056BeuR4oFK
1p57hlZOyF/P2KgrIOqXnhW1MbDkAazu85/YUU29+w4Gv1GHBbZHr4wOHLZVLWVcSgcXaWjgKnKi
KHhLcZOMO6V5KTGSW8wdvgExS2dDTun9MF+vI7hNqHHqZh0EYmaphnK0J1rPsv7v9NYCKW1N4RZK
TTmZXxwuwyyXywzaxO71dMxaPAbmV+jWtdmIYVsXYTvFqPifHu1JFVSrO/yX2RkZABU4lF6eAkhY
i/V1PHiumJ8tt7Bhtz4nGjLxjIowQTr0oym4ilVjtO678Vxzh1/SEwIOslxKS9cZuJNEQfHKdvWa
vmUdz1/5f3KEGrG5LSXTMHRP0X2/dm4KwQelbj4cDbdPI5oYZlF2LTRo1ZgYZ4svHOOjp4CM86Mn
YaZXi09oaXTzY7gaEbVmNzVkZJ9wN8j55aTcf18NqAg2YOOo+avuFqOed4wU6ho7KwNqa0bgqF+p
Y6f9Qxs3iLSaM5sB8NOYH6bdWvBjo7++FrZyQArgEjiaTvmRVSwjXrgDPSqXy0833K761ocjDlaW
3SDwGn6uU1IcZpnSG4DhuTq5E2i3Z00nGJZR69OW+kFMRl25lnZaMslUgyFqQeXcCMZYCbJlPijI
SnmbqtmAEGReKXfD4+zuckjitolBbAE1uDHDtfPQa1ISsbDAHGyFNkXY0r+rKfDhaduIUBcKwHm4
MGO3EJB1ke0Pbc2s6Bgog0LY/soIm+kCV2ziphdnncKS+QOrTmm34/v2h/WuJERmjUM+2oanl9+X
Vt7tg6BRMHspZO9wfGrqU81hUSxg0N0xkNX2CJVMwjhBpqQrJcplELoATgFbxAvdJZ0+dx3F6NmF
QFTFuLdOi8ZWLDB1rxCOWhw0zPuSa/e3Q4V7Y7WvXbuydfvhXehTg6b8VGDISyH0loClbPISbKgH
PepbIv2vuOcU7dMivDanDHzcdUd5KwQey9mpsybHc+Mshsr695B/MAq91LhYw1PhWjdn8D+NPsWY
bHLF2OenSCnNxdk1z5mj2fWlmi2Oc++hcR+uLGY4w4bG5+EXp/u6oZf2VQ6Q4fkWiP3g1rXbadxN
CrQoBEqQAhznuVK9Nbje7RGMaO0ZVu43new5bAbyOLo+daMy/8s2PX2lvp50Yqn2HJyj8A86OBrK
Fgf5FEVWZfok9tcdrINEKlWwbQz+FaQJiHJMz9Rw34B6ZbUrFonhM3GdVp3AqDjgul/uwPIdK72C
k0xM3nGluEkepAo1SzeHSAOVPQ/9ZWbA+DmKjAJNFOXCwif91WuK29sRvk74PdOdlKU7tS1deOTv
3NkVeoFH8pPTIUloGX6Zg888TNgALHc8CpAuwVm9PKFsryW3vE9YxEpscBcnSc4yo/NNKhc8FbW5
QZIA03JJ0s/R8lz9EW03zlRUe806yftuBM6M0YtgA2Oa27M+z1GMIdHzMftqyf+0QfARqLpAiW5h
aMDM2FHSOUPxfsZyBWdet3gOVOTsTGHtQHyxx6LiS3UqOOTeYNqznO0xbxtpjnD/KQD9wFWqykJi
acg4DVFIWU9I6/cN14ZfxpXvidjvve10AIW1pb53b3jMG3+pkT0lY/Xn8XdG+H5Qq3VcPrpdJBx3
Kwf7iOvD+0AATKCFCSCSLYfuWBy+2D5cWXsRXQ/f0j3V8GcL0PbB+9oFPaYBjy1VKYuUbmxT1try
f7VNIXMPgbb6aZjFiL62nElQiRJIDUwNJEYza2DGrXTG9c5bnmHMUDj2QZ571ykZrNL3dVz2Fkmr
qiuRG6raLSVA/RKlc9OnAm6GuNyDNdtj0/Po/3TTY6Jy50Up9a3PDZHmct8wy+z56wfazw4+6QAN
d84MJ1zMks/gCpmTgP9kVd12yhQmORB0bXUlTH11VC/ACbYVf3ur25I3+Hm1Eyc1j6Kon6SzR2io
PfqsRfNU90gfjWcNxoaH6i/Oc0dqwAvDQ7iYAVtcczuVHtwIgBq7pAROa+lQusntFqut5H1zKOwn
Z4VlxsSXruc8xJXA0kReN26HnDGKaMhRWwDvUjdtI9t/5ZJYjbNr/xccC3lNp+tgEOC+IzvyB6ke
kD7OlXJtsFh+A5Zsj34a66M1C80bH4yo/kCFUXsNXryfxABmkqiaSGtqHbyBhPeg5/XHciWU7AUw
AW0bFZXMfWzenrIeHbpNfZFDFztzsoelJKzZovF3aAVi5sdgZxdRyv48HAzrx208PKMYUDQyqsFG
SC2pw0NfJ6DynOgUkbmemvE5DwyVHMKMu+KH0CUvcRt/PgKTi6EyYKw+C/tgnn1fQWN1UdgS4b7v
GuMlJhvtoBon4iXHQS89HWtrXR0NNsWClE7A0TucmKvL/oyuh7Nl8maAKp1cfJiWUe221DY0oeaT
d6U0jsiHuCZsF1nkhQfAtjF0la9bxyYnVU9/edWLTous7/3IAhNl9yKxRKnRwhx1TpvbTU13PqrU
GK/QEyPOigBn7t3DMCcSBe8k9Z3DIBhhu2FQqaRobEoBQ4orNJRfk+ig40mxR8c0dQPs+NeUWjRu
2inuVbVnOn7fFHscW85VuWSMSUZQRv0/UIH4OjdxsTRBUj5KuswB0wuJ5jBhOwGlXdXDC1pWCbLl
ydM4LtQAotc71PcD+3GuJkaafJDXiA5LO5V67PdhG5fZieK86iTvImUqQEY9JclA3FmKc4/sWZpo
J+j9upLCnDjYbu90D2CxzKuWzeDJvCrRhp+T/GXlTBqcP93rOwvG1VlvQdtCL3bLGXOtjdLH6gfN
xUWjWZuky/ZvY8L+PbqTID7XLV9bRcM0s2PbRbksk0uo3Swdfwwv46U6RzouUQ6nQTfiKzJ5MIdE
HPs/+dysgmQSiieFsPfvcHBcGE43HWmT0hBlVsEKGCCvV0Kkh4GxefTcOtprjPZ5saAhEUWsjp0e
ioHn0pc5VKimNMjLTHzoLfciKNFwy9wCTDat0vj6Ik22VRekkjB9pVJK2nrKzCbi6W8Cgao7RkCC
zVeqdu+c5Z2cCwH22ldPPSlTdUk7+q6lgVe0114uhqhgcSELdSEaPXAOvansb2EqQMBXnaGbItun
aXRE64WYSFVDR26m7SE5kDBIcrLyRUNOpCPyI5RkVXn7hGv9KAQ7E8C/ZKdhCAlfGD7QvBHpchGe
PebvTIi7ai2+5Bc8SVRvTW5k8FYdvi29m6LzvYZJCR9XNP8bahxlU5n2aKUa+4qM5/3sqZe3vSxI
niN7OxKL4svO8zBS3ypX5NA6GUJBSoKOplzB5OgV8BS9vBJVr8dKVlltzjX/PEIegemiFl3a0jmE
sJc3qLMDOc1X92iPzkXr0wjGoJzJA2JvvIfK0do8QYyLXC6KVvniVvsGny9JG1pcI2bwA23MyEQW
oYVJSioTc3/v4QPeYDxMYBWwrqth5Y+fszgDEiYQX8Vc7iI4O9t5GhI26wnHrO1SeYM7k63lY/LB
/qHgnGpBxNYo/qFh6b0jmW+AfHvbd2Xmh+n9WzxDIE7Rhl7uic/Rs8Xfh8LM6qFPjIG5OMBwXVWX
/nl2dYaqwePuMaQXhTAl2jyeK2GZkCYTVb4x6xJlAnIZNlUhqusP6iAbPnAHgOp9bhdeK6FPv0B/
1sTEa6k2YAAC1I5X/ILS45K9ytv1QUuCHhEx8rLCoFwwDIqtE52Kxdxup5RUBLrhDvpkF0/sNksv
wonciAC+U2fNn4GwJQAmikrlaBxEbm6E/1ZV7irw4r0iCazAQHLZquX9V9FtMH29uEu9EnY/rny1
neNHbG8bURZ8vPB5EHrxuXJ7K3CpCMA17PL2D2Lrp4bPo+TVPy6tpeqshY96m2y9FVAm4hR3ndyD
hpD4aP4x6AcU8lA1t25c+6E3Wkzv3jDzWVPAqHV2ilFNWsx3Z5RK3vV0RI/gFAijLo3E1ePIbfLm
y83hT/L503XvCCD1GUBhv73RC3NNFITr2/v/tkIGxIX0+grrk33FctNtKEldb32RAogMTiCwcZCW
2gGMJNyOLCGTZsKbZqAVzacVRFMdH6OztA7IM9XN8eJooVycUPu41zAhIA+vi7tmAjjMesUrdyY+
yvbUbzDEsxG7MvmlkLn0C3xrvOcl2sAHX3S4S3Dn00MtlhsgBaXOXYPphWnZ1XVntfaKqvQbDwNh
fQRwT4Zsikby8AAWVEC7z51CuFUPYEYnszWx3s64q5/mXFKyqnBPpYAhkuW4zAqDWHDF14m7x3ik
4W6vo2DrJRIr9ojHC/rFmFVnAnGGor860Xlmsm+IlIbZ2kuv4GXyfZ/z7hlqz6Ow751KZQOCLOif
4UnPTn3OTgZ/zyKwf7KxFe88dbccxK8V1kB5RQzIwNp/ENj6CQyzDN/idn6RJ+i76AdNuOzlRtC1
xx+uKjEMGBZlSGp8tr9e179pSC0iDnqH+BQjpyOYwF74/ty6tNn7Zp9fWScKbr49A9las+VM9jWR
dvJZChsAuRkUJoQVjt46cXZmfea2AKGwEiMXAJiKaeQ2FGY0xeszbrVHm5vBoaDOGFzRF0p8m9Jw
exxt83HH2qp/DsdF+9EyOyIzfDldtDskqFaNQjjT/xnoxk9+FU+kve+iM4koLGRrO2nvf23pOE4x
U1LvUiolnSCo3qh/qd8QR2w2TxARyML57Ih1NcUy1lcHHUiIlXgwkQ1wpXZrxihN4ninj5eDAfqm
xAGdkIpNKFAJonqgOKT2BFy5cYB7UhmMCyo7otBk5E9EX7ktC6AddOIXXzZffXjzSZ6d5btPZCjc
OiT6i1THXPewT6VVB+twQV05+rVm6c4uH2btpyN99hgWA0sAjibUF4vqTrCAYNKJWlb6fv3Ip13A
U7Za0rUYXJCFURwZ7YFi5CY1okg6sOdhjrLaWKCSqrtXvrwcAoDJ5abck8m3MvsSRU3ZQg9LoAT5
N8l4ZsBVGwBJD7fi/+qhYFB0seIjz+w78ToqaSjdRWSQnU1kqTsdOEPHyMQOMF16Acr7ijaJ0+fF
cNSh2mwJnnnQwTDQoGaaC42Y1KqCpN1wZApOlEGHYreHAd1BU11jkeE8tJ3rTYXtBYYwQPJfM9Az
/BSWAcW/gV59wh3zohHf5A/wZTlWupxaf1H3BbtC0TE6rjO/jrfmYEMlpMNS5n2dHMUQTpns+7wi
W6AFk2Nx29JsieMN1KSIQrLHf9ZsCQAZK2dXLj7H2N1VlAWb33fg6+q9QEi/HDmvAq0xHxI2sKU4
cZ9V3bmLFESe/nAw9XOotw0K8hd0PuomuX+mKFefl4V6PsarqfuZnc+4CKQDJ670tOBQ75dxpUt0
RC0f+iRpQWI1Sh1iOLeG0QDL9QXUV4s8EqigNkuKYqsAY0fBjebvpSFwSrhkDLAF9IyVgXNWZhUh
dxl7GMHTNoVu0+irCRtTnbcKR5w9U7xHICsJxDQW2IsRq9zR5PCFECuyk8CEvaNoyH0h6o3Cm7Rk
jEbB0ff78YQ9ULHg/WEtRuri10+s4lZCeKdwWEn0dmoOvLrGXoHGzAi9WzPO0rS/aEOpFJ10nDWQ
twBECg2PukJ6p24E9XzJSe2coyqQ6Jwbbn6F+93zAfH4Lw3+qB1HWi7s3/7HkifNIjiq8/LrDDmm
A35HRjRIec6C0B/fDIyX4hwmvM83NZ6O7BHkEe/4wpBTyfiS7kHTMmvZ19YuOaApXv28WubYQn5c
AwUux1h0uyZ7jmNyl2tDbudiiKettGsIGMv/a7NYuXKELYdRxlruG8FxDcJMKaHc2Ci05+b4Rvcp
CKWv/waIEAqg8y3BBcreTYajfdB9TupwGUNHSFD/zxqxqB4cgTYBpvbopTd1m2V99Lh8VcO+Vwm8
9WokRelUzMrpKJYkp0reDarWfpBQDM8k95pOYhyhl4uuqIkqdaDPi3pgrG7wO4hKHwS1ZU3dzK9v
5FlP9jt/nIyO5nXcZxhwWRbUFGLQPJ4l3zA1UKAwGuR8YMonrKZ6HuMdIIrUmtgZE5/RB3SA1G4M
dB2AhVhUiUni1fjR9JmQjoWOv40R2nuEacjhkONfMZDBpdTMt1DLCZ/TGAMLCOc0/0HPKBU52WS8
H/B81t4jQ2L0yE5V9inh520ADDaBxtbA7efDsp7etx2mbDHGVPN59+moflGruJ18UEo1a9xaHyIJ
k1J6cshQwlxQ9xIHlGdMbwwpHFDs50PzU3S+cXXgSxSDjHjTfqxM4k0tzMXRY0ZLoBfmttZwTow6
FsXdLeeunWm5aBXVBwI8pf6ZQCbhLAb1zGg7GEhDtK7VqyGi2Tc/l2OV9XOfKIVAm9IGiqYdFM9M
Bu7oSr5HxZX4i3PSkIGEg1PXqI9Doe6p9mww2xvT60/mH4X/aKRQI6648j+rWuKG8Qc7IosevvCC
KKlx4APjYOsOp0weXdAWjDArwKdJpVoFRViaIAgLGAlpC0WVfom6IN2CrYUyOZ170XbWKhTALE8l
NS/ScKsZc4FgYJyjCU0oXnFZ78v2cit+QNemHhwelKlY7oS58eu0U7ZObhk7DHjb74Yu70Ge55Wy
AL+KeZwQFuQZNqOA+859bwvfK9wyiZUk/KrfnZxADnY8Syssumh0OZYrFUjn17EvynIh1gz5AxrJ
KtlDxWKrI/glyVjgr5/GXmcp52XV7IY9aC1d5y8ILhxJU5e6rNbvGg891EGLgR6TcybAA6IbFbpL
TQoaE5qENBXWZuho1umKvCRL/2cjimRlGi1RbOuV4WlKxUg/zwjBFkTcmwnNtDapYquQ0zIJOALg
0oQMXWkAaae6hnHfUIV6dIcNalLpZZMUfI9wPtvIbX+0MZ9KmedZ1cA4pyiUfL85/Tz9L9ATTE8i
EtU7b8vXufQMCONe/Xb0RJou3ElemVPr+rq7iM0+CO3hEPQgFmiOfuu+6p/bVR9myZgO9gUqLUJC
Bpt0Lt9cw337IAGg9qE+JGcpkf0OjWr+iczsssaDa3b5cA9eRNudOuxOV7aeTwZ4U1HLSzuBXWbn
8Xf7tN0E4af42lADVBip2S0HqWfXq6Gfk82W0lrxyUj+9lTMAgnBBdTgGxh/Fd9EJPRd8JGMvPda
zUu02SITgvL9PNmqiVcZd4CwsB7L3ABju068Wk/vMCQgJi+RNitgCBlJiu2ufFhZwsjwEqgGKQYn
uqWzLQ0/odlBcrY/I7265jKmmqw5tr0sBIg1IYy1cBoPVsjE646WIUhqJKzn1ImXaLGuPKMUC1bq
ARkM5zqFqt17M7cWR/AujHd2YEvWuDpqmJlhDNEiTOrfrISv4JBxgfWyo2uDJYCl5lQp13ElcJip
5TRdMDeec41eGHFjRI+WrE000uAjyNu7q/ccwPCjbVi00Qy86a3tUAwSVs2DdybVg8Y/58ttsISI
q/p3iB7Nqs9e3ZMrr1wzTCj5P4g7YJl4QCDrO6bYeSQq2lUYRgRMMfTn40H8BBGX62GSYLHMbflm
S60XKX9aK82MnmPBLv9HgSijSnQAgLLt78j4H39v7wm7b8wW4SDwwCdtI16S81l51fmSyVawbVF1
sevr23OirBuwZCzm4DxCOXs3b/BoKVO1ewJo5RsVwc/p2ivQ+gKurh/2a7zg+Pt1FFhVP3ma8Xwi
2qut1yXq9X0Uc0DKY6nb/LSEmFePLYhQvVCsx+njmcZHC7AW643gRiQw3MTqGfK6afocIz1S9TEC
6cVO61tw/Y3WatE484WeQGeDaK8VlqRKMj2FJ/sIHegUOUSo0g1EqJwPMNy1TW3Clc40wTUYlcLZ
Zg7gcGXZ0j6zkxw0N1P9tqaq1Y9NZZ1fgc95IxrSixfe6Avzl7zLakHFEEOAQKBI1Pl3ZNOjnKrm
h+zZlveOGmtwa9eK0DG4x7n+jxvPW/8v0Xnfs91ho0l9nz1ygqHANEjukerqFnoY6Yg6uH8TTisx
1Fge0cVhs+8M6+Yue/ev+B2VS8vd3HIxD2g6iyTOQI+eW9RmnYW7KjLkmjO8w3aGy0MtF7mLAozp
ckPzF2cyEItE7qnbqOIo4e7YxqId0fSAUDjEPgzzVQi0SY4EFABjwz3XItSJUG/f46QmqcYQ6GjN
OT2naCZcB2wRA+Guq7lT9Bs8bAPutKD0mKRPMGcC7UhsOckZK5Ye6L2PgGHAtOefDX3DN85hT2e7
IjykS1s8xTknERHVD3wdRWqfZ2ejE3EE5miTK6eL0mZQ1ZFBm56u34fYqjshrStjOMPMqQT0fu/q
hw7ehdAZ4nNnaE8LpyKiTPkSk520X29QWmJsJVtMaMAY6c9s0mt7IjLrlHhzNNeANosYCrjD0P7a
dcLveIAXz8/6Nh1Do2cc59zRATf87Slm/avYB7GjB/847JfTs0DuBeG/pzGruK3noH3LjqeDgBt6
IKLsZpVQ8SDNV8tL1MdsbPovS/rqfdGv0GvWuWEjHONeDxy0mjliQXdgQdPI9YROjEy5Sepj8giQ
pLhKAumQVvfpGXe0NCMkJaTJhX1E+KCOAsI64sVNbRBO0v42MDJck0J93c6j/zSUuYGZ/qftTMnb
3LOH8ipZbGfJ7dHxI/bzHCHDF166kS/NnrAloworNFVevQpXnboWjgf2y3HKpdy3W8MQg3V1VdWM
yoVgyGlrLHPIfPFWJgaYfcKc1KIbYeyc9knuOU7CBfqtrAt0xmAhOwN7ndOMJhMLzoLujOLqftVK
PWt0MKnpd/G6PCqxeRIenxgWqdQRwpIYjThhgNrTftOIJKrV/ES1hGM/769IvcQgGuFv9X5b+NaI
KMStRZJBdOGqZ6eDBBrlMhoNmNnSM7RwnMUdTFQi7Qlz8nl/JJ24VwyyMteUrkXSSzfEuSEo/P/S
nGveGK3rqjDxtf3PDahTt5PfEGIQlx1VMNAE3mLLBojzpOdOgdx9uIUBPILh/fkxi24KOFNUNr/k
V2C+/krScYw9UX2m3s9BzEZ74CfHgFxIp6SrB6WmkFUHErix5/1i7sD5Ss/4d/tmqgOy4ezCGN4L
G1URJkqSGaTeIkZt0/RbVPCUjhgqgCYdTYdyuCdvSgvov6tZLihruI5ndD88K6gEH9VtDJBSnecw
bV1OkkWLaAHQOQjDMsVXyYP99UL4Tb92B1lFWO7Q60lkw0Dfjpfea9iiR/P1eBZ/32WzfNDiF6yW
u2vYTH+2ZZtc/8Db3F+qkymoUuR5oxZSuM1RLLtUIa8lxCGOsZQmQ7zCD6f22rdrhmnv1be3oUtF
o/zrnMwNfxU/LmhiuyPQXZ2t8s1lOt7c9fVHGUVX1Vq5m0L6EHinjXU7teWQnqchJKLm0DL2N+FZ
XoBefb3Ci94kvCl0drLUwS/VRLazzlZoxYlf84kGs5xDnEuWDRNgAbxSyQVnx7pDdd5Ynb4e7cbH
DUw968yUiUKKM1wU5yICmKt9jcILxtN8W0ILYLWhEmsqUbxRfl9qU990QDfQDws+jzQdYqHldJrQ
/xgDGnECBDZohOvXdWhg9cE0aXb09Ut91Vb8iHWx+cZmv5WUc3j8eR3jvw0LCDb9SVA7gvdV+e2c
edclyb3WFWWDO5BEmADTgnH6tFinN5OEcA+V/wR+1QgzsjXEf+oIK5TrtSqVgxs/Sz3jSZFLUZAH
kyUQMdstCh6sZskZJO+e5ie3vh/fQ/2O5eJSBVEBQKcUnNp25A4em1da5hKzgwA6Doqy/few4EYI
9qYmf7nEYngw38AUMiUvzeWnbIt5F+WBvyJSpcgqDb+KF6DQpwQ1Dr3M8UUweWJSCF6qMgAcT+zG
7G5J3XatfYBgj6ZhJbkK3Y5xKM0zYrYvfKXAxJprRt6OZ3PkIE/Hh9DczV0bBb88X3ap3kQDrrEK
IXN/Vv0xap++HAREN4gBeDDUyp8si8W7wWZ3XyvgFsKVgi+C2NtGC4vIbdEdOYvkMTAVUykhmajS
SZTX8KeVo9huV8y1gB2ClRRf1C0NV7GECvFGVyGJNNPR0ZFyo3eq+IfPTOutj3PKVPZRMidfwRHW
1AZZ5TLOEXmyaJr3mw9Wl3CyEiMGLOGKsEsEKEfhNOzix7wl26A1xOqowcooauE1mqMqFrh7fkbW
58akpYvPjbaN26vMdfu7VpBqATF/A23IUHUTNJR5AwohwhNjfSNhyqHXEAdbtKmMaZFbduiPDn/g
taKyridbSyJFSRRtmiXGQpV1/xN6IIo9H4dVa5gmAGOapdPvccv5Eg+3CmEiovRIJpHWjaG7iJRY
1ZmmIGEPfCrlKq7//Biif2FTo3C2AKCW5oREA4EUMSd5gle0lTvn/KCkvlY+pqCDHWMnZTMnYkVa
9mXHHxAAN+VIYlvMYD3BDFOWSQ82jnJFc2d3iJBQk81EsA8aMgawOv6+QQs7ZMeo0je91s3OMHCT
5F2aG7yeTuPC/ARHnWV2dh2lggtr68Psc2ry0GheYtRahM/Jbca9ZI56+ouNUopvkmwoIx6JZ0Xd
tV6vsTrGfueqJDb+OQNuyX0GGCTRAHTyCwDe3zsDv5Vbu8lUF8PlJMqZoOmEoVObmAj36P9OF/WB
afJBLdQZD1ShRR9mgUNNH4kaA+Mnvh6B/aabT6fki9qdLS6kPA0CZDnrdCIyw7ZA2gIud482cvA5
CVNCC6Qwyf3bl0id1uVaDReF0lVhSQUbNHX/qoCOGHHFkmQtO6J0xRSOlxGWATCu9UeaaP6jfvIJ
QhOhMiBMi/PsNxTIzj8rXAvM7uOCqiXgtd9PRQjVugoF8xIAIop++KCMN3MH1VDLj5Nuf/FGe6ka
sslI2PHjqOMrIrgR36UrxUT0rpd7xKpfweUvRX0qLoWeZ/K4n37hoCiPbWocawpLYrrtXUajtvwg
rHGwq9sLMovWMw8MHgVhvRRwK2ouFE/CfVvhzIuHpoaTDRSODWd34Onq1mf3msBgAB9plg1Ll51s
74qXXa0WAzZ+pQpL3r8CF8zknvSgRzrVn4PdDKnfCznxndK+loAz0gBVv01h4GK3YmqMq+B1i2v2
wcslSpSE3NHcDuOP4EnTrcFnHi1fJH/kkyRdWXk7QwZOldFONfGdAuQK//XlL8D3ncg2Bhh5WS/b
N6NHFXjXq+fdA2rXEUmpVhKOH3FULhj9d9T4hdTsXENxapsTv3xq6e5BOXDCMWqc02dT6rijQEfp
erEvGOyQbgwsBI2dmL8MO4PPELBy3ih4KJPFWq1GSEeSkJD6uYcNQJr6xt/S8H6vmqWirLFsbHA1
wYCsus3FdEZd6j9I9hMNVIIkMS0Bz+UZXjCCR6Y9ywRzgkqeCyaOiwWPEaEAzKyxif9FLxUtVQkF
KBB1SKzQwXEHF2FMFrIBbDNAVhfT2vZfL0iPMauCa7LrnBS2OBSH3n8qQpAKgCZ/C6h9duJJXO8L
rSFqOu5mM3JdfhTBhURGN6C73g8rVLgaerlG19boZiWehf1sCHsmuu7Gt04ViT5f3oGAnwah5JLG
MqfvDnLzWU2PsRkNX2ir9X99Qxv6nb9FAYvsenHr4+SOzu5GWdx75cf9QYonpAvawcsoCPhCdLUW
FIZvuo1tQKZu73ytZOfMdC4z2V58G/lxXrahJkLPzMK+Jq7vMqk05nrchwdhHk3ICLLgpQIdW9tZ
bQa2BP+3GZF8mHI5NlsMs4xYvtTrh3xdksxXY03K2T7QP7qpSoarpUhQz4AMur4DmSLNAfdvXjEQ
7QB0hbWdjTwvfot68VmsE+0esSzQTBY5D5mALuIRJGJMFjEVwJcKw26BwqlpeO71WsOmwqlDkthr
Pwmv0uz8V3P+alfm3VaUUmQb6hWTEPBswDapEqnkpzE3ecS7lWLu8wC2xPfjFqzfWmm7gKS496xw
1ilnJKNznTFEMMzUzWZA+OGT62LZihDKdT4HgJ18dQNJXyKWwLzd2uHjoHwUJW3nOX2B00RuxmLc
tH9BTUndCWQNFwGAWf43He2hRLpBrWS4nfCHHStbt2TyGoUIToVjIzemMi+/3j6ymIkMmNdtECeE
d8esC8Uy7I1RBa8uqQcTrYrh+FTvIP8xq6fhp3h48KW79oRedXydUjuPWjAHXn8EVNBEgzIdgtuf
/43YAKHP9aBG4ZrJOQS+THRPn0It7cbqNGT/jNE0xVo2Cn6MZ34socp3Sg6qPud1V164Xzq4GCRl
Mp1Rsdn3qEhfmuXO+Q/CSfbN1OGy2jOHiY+5gYiW6vgMiGWHk/bm5nVlyPxVvLmz1IAJXE8Pm2Ct
E8Rh5tRDlkAxUgLD1Jn4yPRpPCotvgHuavtDoTmk29VzbCN60xjJpYFLo0vLW00YIDrraYT3lsKe
KCrfL3vuNBRA8hxdf/Dc+DcJdAno4ZFOunJs98M6Uz5LmYLMy8Ko3VIax7cyISuiQBkfz5xkY89A
Js07/G8kMyA67xdo/utVsEsr/yCsvc2ke6HP8ZUnd2Pg11zOyDu3cT/yVIE7Ev2PlcUHsYXs9uFi
/0n/KFtpuoVpsGUNLbnoOd8tnsEW108Rm59nTekwJ87r8TW6ZQnDe3wjlRE2C6az2YVWIjj6InJr
8oFXjaH40TGja+CWsaur0fWB43r0evW0xtrC9EKh+ECuB0uYS42yHwdPVVZquE3ZT7kZf0GND1D/
5e6aBqAE+AHDwi/k6sKKpON3LPbQyGS3BQ3bDPBkdpJopLaGLM4MkFinw2O2gONfTywkr3eC260d
D1nXYnsQ85e8rH8q/QXiwIjuhCIZO+9oFRP/rh0y4DUC9hk4xFA1ea8YN6s07smCaIfZnKgQ0Njo
Dy3gylLqLURUOgp57+OlTITtPizi3cxwmerK8Xj5JJCwCQgxUKOTXJ/CJeP3bKM+c90xkRAW+LWZ
y4kzBk/HHf7q34rbC82dvtoJE9Jo/PvJZ10y2OCq9L/J3f1GkdDjEUEcdcKUkaPywKCqkg8mgxBn
f4hW8DkTx7mVUoZCQlD2ghytCgjMFGhJ4KZuzlNmPOfoo7pdWHHJsyzugeTm70PMEYbB3QBE/avw
i2+Td4YGr9oLlZo4sn94F5kfGFj8Nyfm9CUdcGBvmmiZ3eWXR/CQm05aF0IYX1eo0gzn0rag1ulg
LVbIFufWyybB4iuQT7FTNN+8hrbVQqPHPTN//U7i/14hFkfA+Bwphc6DXTyGRaffZJfsW2icsgQb
aNLL262hK1GZnDCoBFeZG41oVgujvxNTRmby8PZ77tkYFNDklJtC9FhX7NekbtTxAg8pYmEPBEq+
b8xub/4epL/F0Vv4BE5dtneWkA8XQDzj63JGdDxQ45Po3+A6QbqvkxVdC7vxfFrA+13aTApvcSNV
orL9pyhQ2EEFGAy+2qaDkxgBqodlwkA9ysVjodxMuPGRRWpnAZgOpdXCuVTWwrQj/KXySuV8JNm4
TG48j+cts2Yk7sR8yYl0uUCjaaqa8QJ+Xj1YsiFD3Y/OJ4smS1P/RViNYCMb0BiB0vswqCpZPnbg
E/eOoRieucvSbKAK7yVyTVWHOGeWtxWpKrztqu2fUi83X5eunyNFsxjAPXSbWx3WwoifYKmeEeJj
72rE8Jk7veXtidB9N8fUI5EfGeBulMqmRJ/FR2ZVEVdkRD7bIfY8y0EK8OMDYmu1hYTbw46U+KaF
6kbDgVNbziBhDm+NE17M2nHGXItSvBLIwyPcLszslFoV0RCc8MoO39ngKM+tIzxFKJoLGw+1UZx8
crx5yr8+4fYdN/W4XmB/pQVafaDIdpfMd/nc4Gw/IKpkDvVdkHbsNS9Bk3KBP/6krfhwNEC14pQO
Z8vRHDwEbeEjcggFL9n5f6P6gIGH8m5JmwIkOP/+ZMtI0/gOo6Gr/8wn2iU3MYqDfzUYqZ8TPgLZ
VhFmm4VumdgBiCxInX1Lq5caJRBvV8N3yI/af+279+sIviVAaKl5KyZOP9j6KM4E1rP0rttTy3Yt
LQ3gbQYizRxamj7UPoh/URbYYG7cyPh/X2mHXvWh1AtI1MueVlfT2ldubgKNrmou6rLdJ9GpXf3r
BHiAor6seepXivx2O040xJWDb9W79S5YhRHDg5iFULhw3OFD2fxIv5ulZIqXBQ1sp+kVy1u/ENvm
hRhQN4Ldbdee+0uFEiF2ZP6VKFusorIGKCiT+oioUiM+h1q4uhJOclylDzXrvSgjzsXURu7gMhGq
owYlddcImxJpLWIgSNQLO616WeUFbrcVUc5KFGjpe+qA8y4FKEAYDAMlYi9/EKU6xzQkATn+t6C1
662uTCCWqJ7B4fCpVzf+wgoSQRUb2cU02ConxMtU0mmR52Obk50r4xbqB//CQRHs8IFnK123149b
ykPCWWILD/jfzVDaJ2xPIOVkSjIP6SmcOSafVf4oYHKzKkPBZxAU91QNCiNeIOEnSzDQWxdDIdAE
u8EWdQuJ1Jdw6WBJIzPVgs0jCj0WdCBIyzdAy48S4ejJVLLLaes8Vc7PC39gldFq2C/rnYtVZoHF
Qn7ca54G8c/LYmnpNzN5vbPlmEPe6tH9REU4zkMQ1LIojOZ6fkl8OoHH2kJRCVsBZvaMaeAb2r3D
8erqA61he1Dgciq4pqkX6jvCFT5vCtQ2/9cSnw9QQj1TcOsJSdmeB8wHuuk1M/ZMlFse7imWjJtW
LEnnGtwz76LtqR9YLTI2UkiJG+8nziW2yJlgoH4tJK1Hi7okOYXHuWNHhsMamg+YIgjTED67jeSr
EmZgHD8F9XTa3lIF2NPIofKJOv3+w1hCyVkVGXR7IzI4Xrnosb3f60CVHZrr85rNoxCPW4wT5+0c
CRfJbdBb27MVPlG4Mo/c8lFt3WupIp7o1SQ8uBjNDA1bISNhECDhtuQcv6WdY/1phsUIZt89ThXC
7JAPpj7Fut8aehNmC1aLE5Oy/PwGnWGALjEIhclClI4Y886GPMX51nx8Kpo3PtLCxTgYyCVOEwzw
Uc9nmm/2rGwuAUvBOKv4X6mtTMZw1j3b1C6GlH6M257NLvPw02kCPSSEoS83pX7SqRfFdmf6IePz
qr/mfHKYed3iE6S7FrBVNsIOTpLx2J2/TkHJWGfT7peh7iDchJWBC+GDpqnZXH5NQtbvy9mCIL9Y
VJtiWfTpjDoSap1ll9BLhtl3TV9QSdh+Tc4OcYCxC9+rQm5wGdLpidPKm83i69qC/72iRKouuuUM
aVlUDSJag1pZILPCBBZ+v5p0iMS6szHZFHlQq0Yf+ZFacMxDgE7IsIrc4NMzRtjwKumtDaEuzAN5
eEaZnZV8MwVKPutg6hgTj7D95yHzI9QndckRlkcrfzkYVIYYFFt+YSUp3xYwFhbPjy4DwrZ3qwJS
MfLhG/wZZVKPD/latx4fVhGKP/DAfr3aVrQTLPEe/9sQnsl/kRqzFPChUzQj9v1GW/LsDi6L/kNS
ZBvlYXCYVUl0mVNUCrTyhi4EOKmfAgy5qCscn7EfS1S2S19IzOtmwu1Vlw/dJHFCEP58VfAiYdPE
r1SwMmyISR20VaP0Dsw9pbuZfVL1S0iYCaqfFnThZ+ols6uNJjIUbqk7lKdWJ0cJrBgduuv3crTB
oSTl07zEOfdJz2KVjf4cvKfjrwFA+/gjuOS+mWRlBRmNhXEIW3ptpsIrjhv0XHl4248d1xTs/xcZ
UhJZMHdD+j5GxV71axonlTllaWkDViYc1b/E6v2CgQsHQ6+xu7u2nA6+lZSsuy96U/iV89TfSozu
09ZjJBHJ1/KR9x5T/wVvyH4i8RUMYSe2FhdC4z9tzfF7elMVRwB77LrgemeRozAHHvY2cVq2c2Fh
sHSqNFM+ef/Fh5Dcirj9sDvbLTtFig1tDEn8OCWoE2GrCPcWhxyzGUE3IBDTzT+iy9q0VJ3npcCe
zpXxU/cQ7mioP3lW52JqkIGStKHyh5Wv8KGILUZkwE3bwy4I/RK4y29+vUHAiUFGIdncwuZP3Yhd
jD5erA1WCFutqXcvKxPUvRJU9nl2/vzPoiFwh1Wgm8myl5Ov4CUNHrDJJYpDZ5Is2PIQmIQr/CaY
r7Vpg9Rs7z22rvPKMN2kENc3GLSe1Ln1laWVHFp1ln0jvjsy9SIbf42Ld7NV+fOLvovmBCZde2cv
X22lCI7tqMkP1hjYPrVkFVvJ/lRYtBaL2NF4qNKvdkXGDeSvbk7VrTdMhfFDXR7qLFrkIxrS8OqN
8CJ3+2C2n8V5tXX2P7vpJMmoiKnOVKZA04Q3u9tP2DoGrDGT31INasBL7O/waHotqZw16twSZSPO
Ec5AhdoR8Cd0uSUemqEGsEFp6Eqkpt1xiQHctfgs2XtTWcIgMcLZwI2mSjk4pnKWShz2hpphsZ7b
zaQRqtsvGfeBnZF5evCG+WU2G89dZGB30BaicHQ6qKbkda8oPGf+enPDQ9z9r9VE1vcxBnHl0kwj
Wciy+nlrj1qq4lMu3mC42AaS666rmKF1Obz9Oa2poliw1ZhJc0QtCuwEC2MnKsehXYqKgIHNBszm
8GjLqtab75QieoIL7rw5aUd9jxYuVh0etAEwQvBtzNKlLW4eQHJ7C/1fwecMiLwJSg40OSoAw7c1
lOn56PUTtfavSnHPtyh0+5xBnFEuykLsyrgQQDHuW23dJU0G1LkopK8EbchJip8NuMQuKYTJ+IjE
A9pkZf69zcroNthkxqrPfb67RzQ8Sl2wKZdA0BShQCjzvNJdd/bl2y2BkUfUvc9vp/JIu3zzuWJ8
TnD4dB9pmv0g95mSaep9WZa2aSA3kPEJ5VCtWoz55q3lASMKI1aH4t8Jq+V9Dj63/qvB17RhwcHg
Bo/OZeg7hYYMdSxLs2HHfTCq1+PrAhIV8URyNsDwgXHaCaFKCt+Q0YcuU0BOXjMfCqgAq67nIXI7
EYOqNKVscvpxD3mc6kp/2A4jfIgI0VVcj1vfRwukkVG09C53pWsQ4jMY1OS1UsmYiuJfhXksBV4p
5z+ehVY+tnn451F6TtCIktA99JSM/iXc8hRBFknVgKTry42IhxWQpub3dKOzEbvg8FohCxOKIcbn
QJF48YCnnjK2sf+sAb3tHuCQe8V36mz6Uam6qQ7n7h58i3neCCgRJQB/ZppgHy/10E30wrBJMZRq
3O2cI/2QLUEdsn5rIq4oOwZPER14z2+MTTEwBTpg1qxDXD0ZE7VsK0L7RwWAXIMH4owdDvCGamsG
FHh5VeRSBEo4sRMZTBQteg7w3TWpo1Rmdvy82qgMPnVIv/lBflxvy686X34xzB8WM+h6rrb3Pl2X
7lM0dkqnblfAOa9FMn6aT9qF/AETHUsPkTvvJzCBITUraVDFdfk44ttGdA2O2OggQvQaQDQZngzV
rswkR82S091BlmUQu52+qG2mVsWXEF32kl1nI42FLNzsO2Tpq6BIW4Hr1Hl65dT4v5/ulvKCW3sR
engmA8yfao57GFR4PFTL6hPK/R5RbfncXLUQEBIgS+0wv9rax5uYacThzYha2zsk0DAMib+VQY0H
E/7jn/C6mkhSXiYhwcvPn0luLUf7U1QnWVzRAQMncH1FbHMBUiLAL4qoMosCel85deGUaTC7GRvq
7zbn+usKD81ApxiWLxZpI+RcSx4tbW9Wsvsaf0Roz5nMAVAhmaD+b6Ch4GuoobtIdd3ONQO2Rt3m
zVjXk+4lxZ+I3voHWLdB62lwHBg+7MBBMmlKDhPhRp47HR9hX9LPththOZPADgRyQu/MJUs+2565
1v0vRX7giJuAUpU3pa0VtHfjmouroLH4d07HysenGYz9g0PqIv7YQJsWu3a5RRm8iWXNgXE5asqH
IfXCuFWCX9W0REju+CL3SDd2p3IAxpF3XBtiMEjeyeY06EMXPCfhttiw68yvTcs0CnpLVFw4k7CZ
Udj1qxm60lpgAs91zJzhX2mL90LCx+08VqnR0xDVdPRKe6L/lEqIq+ENgJs4yxvFg5RKEd16CgSt
aH+4BIzjMaUzyh/lv/UuSNfUgzTbio8p8dgkHSpdXdkouFgFcGCzQP/iodrBdJ0ZdmmhXC7UPE98
tXoJj+o6acw9TeyO+oafQkTNBRwSp17H6fZxZvL2UhxH0MiR9Rz+HASHOx+/6x9e8oJQpV9eE5Ho
rmGajUGduqNYdwhy+zRHgzkhzZgvSzuZyeFy7oYjnxejFQ3s+NPw5Ji4eTvNeGYdDeKr81R7u5wy
/AyzDTCJq0XNW1oW9gBsCNOVU0hKBQM5p2m4kLVicvers3nAtpVsxT2xBDF3DgG9Cr9qkF2x2YVO
Pp1ZQ2L+Ov1IwoN3B7VySa8NtemeGqg9xMv5gCsBCydRtc+mAFRyNotqfjBQUlR+FjtgDS6pAYoH
YrGQDbp/dK4HCJneMZkG0Sa6ilvf8I/LqzzTzaMj/tKl2zFRFmqpQbYHn4+hPSzPWYTUclAORbg8
cnV9E96ByG35y2wQwGUrYPcpOCjf35Jyz9CwbNn42OQNug3jWjghazYbV8ITUmjFxV1R2fOS1zyc
mBijzzy/lwmBXg4z/D7+V7F4eFV0IwNw/XMEZcoHQ2gI9TbfoCL4Rn23Bglwujv7d7593fdTBFZa
6dZfXcoHqRnUlyUimHIQesGcHXAWLmOe2n0KmCH5V0SzEd7lLgV5T83K/1QeWDJ3lu68TCwqN/4/
RNUYz2EWJl+jRQJgHy1gqeRHyP7rIJ3J/HJjCeHgAJLFZ4FkJvbVSKW3c8tvZ9rn+BUUFaT6VsvZ
tC+PFqQ/RNVHlhQgXRvwJkoDKuhd8oK3yCBf21sjIbI2g108XTQYop36pK1ZpY9E1VwyS1YE7fnu
j2htbXhrH7tFapuMAiD8JrKWArT6N+7yjriI01KuZNEt46kmdqQZQ58nuUWfCIaUiIQPYXHkkaSb
Hm+nUpPdwbgQDLi9QELxD9XgvzDamvktsjPD/kI1eHkr3+OADBqYD9XgaQdHabeP5NiQNcOXHtiS
utr4O9iHvPTPjaNp0zMcSffJLgEGfzXVH3Taj/H4ZLwaZoB3wF8JSbpsJiYAD0p8vrKL09EvO8Gw
LuE2l5vhG8CBcHAniVCklLC7RG451ZDvE3c6ljfAkqzoKZBtIYo111Gy9VRv36ajpRxhCYe9GrkI
0JQ7A4HoVfBtcOnjGcIwBXDLV0zFCnxQNOqKCgiVhzMKMcFSh3jwfY2jDRhJc6ehYsWZC+g7ihzJ
60SAtNEFY5JCYOy4Zwl8ri1ajc+/PZ8COO0fk5k02apMwPqFz9e70lh/p0RgE6zk5b0xoQZKiDdD
+t9tgXi4eN/nAQAiUgF5n5HJ9xm/5YMBHrBNSieeszWjk7UMt5vlCodNn3mI46UM28f0hQiX9H3a
5npHzm9ZxBdmbh4fv83PB/M/ySGTpwjZK1luG2ioAQKSiK5VZT7G6qv1Hs3x0a3ZKIsWLzH4rTWv
sS/NslSDo3+Oj4YYS1mUn+bgNakLZ2FKDYB3fKMWQAf+4nKaJLwbp4lMOjZK8NwytILUoG55oNvY
cbJ5bv+DJBHmuZbgWkzoqUP4+YiMGY8L1zUi4nLRESLXJmiyR3GSR2SXidqsd9PK7fedxzuSiQce
fciyCAp6fhdg+ZYXtld9c2EWW4saZ6sAKCXCncUM6e1EVHkB1fUFqP1MXh8WDCflDg6BgQfjsYYE
o45IWX0s/paPl+sT4mCVWofD948/zSmpLtHk3MBGCIW39paL4am80RU+8oGqb2DWGeSt4G0nLVlM
rM5frpQTxQQNsW9MceyRyt664ytPocXJMhQgjwIJ415GstTeQTZtOv3zFYmIEfwvtDARq/Y4OaF2
oBGqVESVUyTJIU9lyYGC1EuT6adb8AtlJ5kJzIR3JHyabKg7IsFbJARi7LupP/QTp3ofIVTYEdhA
4PTnSC2FENVo5cnnsZ4r7Wu9MntCeVWfKPbMx+G+A3qt1Suy2FKuttVuA/C9MCuoQ7RuZypSRZbd
7+uccks7tTkauCd/UB1XRBAeT4KwnilbkaDwYDVlTd4guN9xMz56k4BQpbWa/mKjmUZeYYXIhVdL
5G/UI8ItSYYaVQA1JFIPzpvaLXo4Jkz+JXodEqcm6J9DBXi60gsspJFDi06md343Ia04EUI+Kqr6
cnlUW9BDtUFX88zn9ECSUbA7MIbU+hg/7g8x5MF6Y9nwQZKl8Yfrwt8PouX9f2HCh491WVOmPjrL
/ck0Tftps/a9K0wjWFV3RLO3QLupogD68l8BP3WQGcm7I4xWkDVMSZrt9OvZ+9Hv5lpsbUeR329o
Wm7LuhG/YUDcNdZCjzLK5nZUf9XFPr5OaBajC1q0dnjpdvDsSkXNz4MTNKOg96dIOPDTDKZaofmu
uHjpnxX9UE/RLPh+h5aCBTTqRi9zYrA2rdRpmBFhfwOfFoeH/grKnu9hIQsPiJ9/Ezo5tPAO7EHp
U27bRFFgMAl/5rQ5KvrZVhNACmzwG6klm8U4k6Pz8XugSx8D/Y4E6pGj4vyOdbYyppJJ91C7MN5Z
KKopqGMJZQpmJMf1bFMRVtXXqWANJsqtE04OkMhvNHCMWjK90z1ytAiDHmX1PfglTcwiTixj4ydn
ESuop1CQQGSO25isLgWk5rHy+2OZqVmpa8wnfTdg0zy1HpTkOUB5DopLxAamGdyfDRwp4IlGlKIs
/+9RYXDLwILXKKgTCen03tbwGtqj0do81CuZA2SaXZ42C4wQu5Ju8Pv4+gDeXUclPlDLlC4pgoGh
cf8YhpjZcse5QbD1ZZrLZl9I2tvTiR2Pks4eVdfwHNmFW/kpw2OzTawD7HUbbW1FcTSXaG0l2YXX
8k9ZLTSfrBrS6MCOqpVCvA3NgeQE5TtE5dXxSgXO8nnLXZpJB6SPjhkuzF7S6aLzTGtUFICCfeSN
+IcGsK2IsCo7/LKJfnqrrZXkuNtkOVHzjF7mYU/DGGRH1p5H0bfzPgfk16QY+ZvhBwgffFup2GKq
W36v1md07X+6Bj6QP+ajdb8rppGlVQJq7EhvRImY43dxqx5yaZOHmassVXBkWd37V1MUoLKQuI0Y
HH1vdIkIiFUkWdeAFrfF/mdS71vW7XrWWeye2R6VTP3WhGv+yr0lJX8sUW4kcKfl6O77lHxiiqSn
1DXT03Cg42N9fcg7gYZNdmJjPhsLy7PdO95WuwFTr/aFYYdPmjhH2NvOshO6q0GPFRqB8TAuR1pk
vGLc16ZI6nt1s6c6/8rO3+J18OVEFpNvBUq7kw+D8xabysY3naTjrv/B8HZVryQsOsIpf/XZk0WF
uHeOBe5nNv7qfIcsTekD8TMDE7mClgo8Z7aSDax+c3wvmk4Qs3fazT0bqtsz+oPVdI5I9YJ6LrnK
tBIZOSyWa688VGem771YYSN850QbPpDk+HDQmI+74ilgOExIcE1Aq2i6FwkVWjCndNENsB9YTSQL
IbeTcIXzXAdaIvZhDFsQPVU7/HFthqMu6+EvNROhzBVTJ2jijuVtTOGeDoAWfYSoHzFMoztFlKoo
wvxq+NC59fb6Oieg6pv847lA/DVn/q/FHGqn9OZbm6A4W3xm81y4CgpJjswKADrukWkZMAGf1etD
2i8oRDBEVNFMNT+r15o7vywdnETN7ZIzu//ffowgmzniXN9fYJ5RlL0XhyezV8Qu4/1RneiHrxAX
NhMqFX+W66rQTl8K7cL/Ac/GXSv62bqczcDeAwjWU9LWzfou4oEZMcEDsnC4daJ10tE0wpzOYGcq
Zr89wdEI9oVvmPUCdjDMgoMS9TB0m6tAb4iV0UNTtjFIIaWWBOjqVRvTkHEWWPx1q1Js0rOKbo4b
VSuoe8lC/R/h3fj2IXq/hryqe9Hgc5NPWeRfgiHm74LfXydsifMbTAqjbNrzudg8bYR5Q2oh1RzG
cBpTZylpcEXd+jzpH41ceOCWA+TefimQwy62Z+oM4hW9u5jNsQ6Aoa6/5UaAzIya6Dupoax8XLaL
IGxwm8SBOBaofbB4bNZYWp/KYlI8hbOPBWaYxaL5vE4BZvVtc0Kn4uCbfWRpv8bj20SJHtexE1nc
XCyMTD7HS5zu6T7bI95F7VO0SptDCyBVS7CHpkBTX9z+a7N1gMZjqjkHu88PaoLuUxt2YOf7mzzm
ZFBEGYq70mSyHeiqYmNNvC19BsWU88gs2J2II9hLwEZNOgVbW6zZUVpJWpHtb1IVl7/qo2ID4nMK
p/sgxSnOHk7rd6EYUS6gGFol/2kqR4lCl5/DSeQTwnFTd7x9a1E4GWmu1mgvjVbFPbUKzkzKkoUI
lpEaejCQjzhexhBBcXtUcmc+fMfaBXJWvnyVoHO27iOMHGseMu7XjdCm4Qi+Qy6H2tZmVp2miA/Z
nkVGT9+B7e1iq72YEFKef2r0JqFHQv2CG70KRnO6Io54ZwiTS1ZCcfesJqzb/Avb3rehJM6ENCrJ
bp4rB+aNyMzAb7KAUH9/4V/fKusO1+fYKtRWkx+RXo8SCxFHj/Bc1oaunnJZWz99Cz7p1Fes2ozi
s6QnrzYkYPr7GIXViIyzA3/5lQqPqtDh6lYNbHvtiGj6LRKQS733TwGFBbwjZ2gSWvgwRWjWHwPs
42O2g5ixiq62X49feEoRisTu6lgvYZ9NLGmA/XCQZA7ynD97aq6kWQytgyv4s9/GNrViFuTzxgZB
jqGHmlRbcXw39zB7Ex1pOq+PLFzQJyFA8uWB4064J2eDzdePeD86XfX4zI2Z+zr35dOTFS3RPHoU
p2QbRNe24cG4BkM/QmUdhlEr5wBBBqzDCWldhnRuHUCD/bEtA7XYP5zUg1+Pi9QKF/ZuPL3JlfqT
oP05B2Q4lbfm5X3L5z/Y9zwaQJy0TmfaJwHwNPnA8LFdOu7aF1OcQXm3a0GD+5RSQxLDpGHaI0xz
Oyz0TQopXXTZKWyxNSJsk0rW/zVZx3CvzvPk5sV/F62uT14nwHkq1qDC+768pwtIGfFfk0FEv9Al
oCeTNRChgqTDnwhzfX6U7F1gUlpOk5y9SqYLPe25Okw0+Elh0Hq8IKikRWYjHL8Ufq6+Y3A1L4dD
HY5/ZY7knAuOKyb1UWyw1J9eMJ55F9ceMyba2O/wrultU++vEazVMF0YAY9Yi8eJQE14WLrvu21y
PJ7l6qWh+5XuKbjMYBWtXont42dPmb+MVNqzodma7U3ocOHAbuBx9rEqcCLmYIt877gka/18Vu+B
BovYbNbd4uMR0ORsQbEklmsT2sbfuLrUX7QD8bf27UJ9XrKL58hXyaZrqRSd8SFBms9geSlhOBmd
pi7SZGFIbtrfjsCMsC0xOvR9FIt1AOsFWxIWxfVgmN2iZfvCbcUW7qLCXWf5JvFVqqPx0Z63t2LB
o+zbL0OdRlaeSowUY/rz4g6QAZ/ixPUOlJOA3LI+DvsHW7d02kJR2Ljs9fldnIDrFWZXMYem+Ek/
2oIkxwBxw8L7Eub1diTg3ptmKgTE3ZgFYk/HdAbnx6tIicKd9DQQq7J481J3v+79IZ1xir8NY08x
LWWMyfJ/LqQEz6qsGIhvqr2IG4gnX7YF66RK1zcfuj0R95Jyw6ZHyKkar/KafxdujK1i3aiUvPNH
BWlNYlm+2ZLmPJHbZuLOxdiFDTvSw+M0Va+BzG9qmAIcKhiDLjPwZJGRJO4D4DPAw6HvKvBPnN4w
GuSFfE10y2Qxpc3xNkpc6fNLRtTfYjTLHDSlLjSN31SgGgvXmK9I6Swj3OxVGXSOvyOSyX7uA0UQ
oCkh1/mC8T/mnjngDKy9utB4DxrkNnWugwai1MxAh6cxAsbr5+zg3fTVXvyHjv9vjLS+7MBQ2XN3
yWeqKN49UKB1sU6EvaJw97MCZl457OKBGujGBVdGx8xrwTvZTwXpCOdFu4anD5Jihl1MuuDBXOX6
WqoJAWNGv5ymdhZaS3CQvVARjRsJT0jQTitKFE8Cwqg7ESf+7/LAbykmV+r0yeO5NdPxDV2mLeSN
kVUsizZNqcafLfQPSzGmjs/5TDDli0KN5rjBqNxRO4o0BriT5gSWD+YY4UG1kqGYEAHJHg/pWaLg
B2+vGwzBxQ0NLKz+JverBT2zUTkDyM35vt4/Z8ZSyfZx9eQXaIDFUCCmr0zPq8uCsZGUeDdAgwb1
6kwqtozdejX+D1gHZ+B/oH48pXT1h9tLkbHO2wwcfiq/zddlKAGURajMgMmXawnQdPv94VjMe4b2
g5QyJ7mRmqyDlZ/dLP7f6Ag++89Ko1wd+aCFJaDDTd0HMf3s1R9J7Ol5sAK8hnRjNcuQliM8UPaA
MNIEhbuO+CF3wRH5FlmdXrFGuRSHoDfnCoptCcoUvj7RIs65cn03Nvu/BGM6y+J4v8p+qH0Vt+Sa
ptJP1QoQEHY17i4Nzzj9Lub3yT9UIWPiF5b/yqrd4Byzatw+1o9f9muud0xXPQo0Ouq9y6WtL7pv
szuaFE/+DDRvivNkUzECVnJDwgMZsW2E9N196EgRQ0I5FO5mGESbEPi5X0jqIYoR+3Ei7IKzdVFL
U3EhJajgQEoEqmdL9QJpK4yAJGj1wojyg0nSSrjrOQAQP1VoOUcTZaswuCKA6jQ/bIkgzzPwXRTD
Y9xOGsB+gzvQOxnVzfcvjY7PW09vhWDOkDSs80xY4RPftR/HO0ZHfVwxOnEaPq673XyZN42mn7vU
6zmXDESwlsOn+tRKKjopZR3+LFOdanV17x8gngCHiNpShAYnN6IMae/AMpJmhB9k8I/eo3THQpbH
ATu6pyvFSdshaDks016rCkrEpMwxmWXHA/SO3NeznpSG8LYB9aWuqDZrtRZjw1SvdXQxb5935m5B
uMehzAO18WnUjCVnAX/3+1JNX9tOedXtcNBz6v+4I1nayUcpBAm3BA4Wo3FEnmBb90gZth3czSkN
wc+Df4p+onfwQoxoHle/j14ZdOIcLRduHNgTeucVb/w7Dc7itB8Ba3w2RsFH6s1QqbVlP4pHmbTq
z9ArnAa4wHYeJ6a6PLC8D5MROMbOAzmK+6H06APD/ZZh+/u+lULhqg4uVLhOYMCK737y6HYIV1II
qVta3pakx45YNTqMd5wFch1IXLe2q0E0bIDUAc3qMhtAeJoDn63FQbsNR3aUSc5HRAGx0nOQLJ9n
YdPeN0R1rPW+tEpn21D/Y1hvhHXD1VEbOv0FW2s5nES1p7GjQLv2VI53PsjiPFAe2V3DG8oqdbxY
oZTX+eYfif5+FHVhcJCcUyd4kkWzIXEs628STdg+eznKMfQgae0pDacRA6VfAU0ONMiZgI808XJM
e8Tax8Ybzs4s9ZV1hpiUHk3V+IPueXIDNIl1DQPcsgZ7ql3q2zcmDYTrmyofjWT27EDMQ57ajZEu
9fVOoXLdy7c19seIsjoz1bn3RzngvTylOecHB0tGzw4QlntyT/kR3VBoHohE+vmMQSH6QgUeZp1J
j5n3TMID0AXb+MpV4xMLkuAp5kd0sWgXaK3B4tZlMrcYTVy1SdqVqXhz9uur7U79tK9fI1SIK+wp
NAY7nmSWyG6kFqUJHjkTP0dRhjcPotAhxlNy3TFhdJqC2VbX+K5NAiNI9gxjZIYO/t7l4Lg1DFkQ
extJy3pRXPQIMs3/IW897EzaohBNW1vZcUo/ogaWFFxVJZCa//o/zfzRa/OVU5ATKSoGlD3z8xKr
iedJ2LBHWeqcQWAG5yRiWoIPRzCTjZsjtmXSaNBBWlJJphKFJIZPzNRKeFb+Itpsq3lNES9F3NFa
uHfr4na6pKJ65dBTfeqbD/1nQp0ZkEB9wuoJFEX25Anfmax/JzbdEjPMEp/5KvJiUzzIiQuOi/cT
a5McQ/ZCBMa+aPgh6EMeo1XS+CkGeqan/emwx82JmBTCnZWx5eqKDUIUT3wlb5WzBVFJXV26ukvk
3KKfJIge7cJSmVFD472VnQJUvFVpF9tze7pEDVdY0otj8VpET5TLG3de/kyTz1TmxpBtXmXMChMu
O08xK3o5R/FWHHS9zrmgqYf+72l1BiaOxFnHFOLBRvrNsmfMJBgAMwZOnJFGgK0Cdr5U0po8Il1v
UL4uWu2G6l1ntp4Wq6g4Cpkb5DF5nwQtM2wDl6/tYx5ZBioLDCpI4MHiJD/HmLLcoCsdiVgLUlZh
hBXUkSfN5/iyvtD4szWppZ+zwI+u7eUaPrxdqtquL25MQmNTNCy81sxFN/Zgdj6CaqhtzEQYb0Yh
oxmzwRpYtiYlgVU06kBeroIGLwPQ12JinMKpnEFSSnlxiVVYnLceEj+DeP8AiB/YrqniOyOWq1UR
Jnb8xZm7+i6KOJA1WPYAbCtoumMqQAPeuaew6ZnOIYvH5/i+xosxX0ti2/upFoq6fqUb9QIU50Ol
F+T/y+AqLbT41+Ef8kDLPiGti9cwwXfyVxck5rzIn54Fwlrn5bCedm8W+EpF+dx5QKMMCsyufJsc
q4hMyM5EclnJk6qVlbc2cO7KPRvHAoKI3Pd0HnnaC2r27fJnpYOwt1hnSzjh2xHVc6RQwRrFXzT1
x6GSioCeaLKSk84F1dyoT/QciS36x1Ey2kXw0QpHcC5aUEwLBptQeL7FIQ8E+2WyOfjl31MdEV8z
03XkcbtvONCW2pacudutP8bWFVjGbF8I+uNf0LNk/1OnRV0ajvSZC9LbyrFGNYmIrs/AVM9OQ0Nd
hrgxfZfkg/Rw3Cat0fuPiIjUFHx1gC/f35QiLRNNSha3BLwqXgft5i/R63uFHFrJpVJSyaWzP5qS
5QK02v19Revt3O2o6xE9G38g/2Iudl3s6B3rHK6lVSn853QEXYS8oOIGoaYbIb9WfZMI6z/S9wbt
yuCE6GYYk7zu9FnYvXj6eN7EzNsq3EFdgwz8LaL7mvMwzm0p/Ra22d3xEkjQ0OXFdtg2mpZdNs2V
3L6hZpmzqDNIm6sQ7qmaIS651VssxOPP5PJx1WM+gdxCyGBTkYQHXfM+6JRaDXFf6OnFWy9V8eMt
q3/2Qu2IrNginbGHSFifYtRtsG3OLiwBG3bgC+iUxAEqKj/C7/0F74yPC+EWQpqvXySJaHEOBcql
1E1o5eTvXkeqgqzlrLFGGaCNdHnhmERX6Oxh3CV+Oan0a4fAcBjyX0B4hrPgtAGOoQTu5++0Yxqt
BOaarzeli0IVxkK1vlMcpE4x7SWTthPQNWz0+qiUSDfJsHDLcOjaJ0NKvKsW531ytTKCcn7cHVkh
Es5TYxwu0Vzijxcw9eBMs6qfMmUEcpi68LiG+EKoT2YS5xVQy1A5EvVY+y83Q29sp06QUHLSdHlC
HLlz7nrR9ufEZI9gXbCCd+8Sa6huZsRu4ibUmr8Yndl/bwYjYOMKxZziRHREDpfuwjFmutniBOFQ
NQS6HGhxkwEkZvqSota6f3OtgMlKONS9cs3A2YXwBc6jvRDeCASuUQHCeINt+Ut3d9Tcf08EwYRQ
534RZR7DII88uznRnc3LalArLwyXU2hRE7zVVvoZJrsCXYn9octLV+d6LjFTkXiAyqno8QM+Jrrx
mLc4w7/j3zPg1NutKo3NzMGaP3gUG9OZsjRm4qhLn3DsnC8jszHT/7mHqBAMqM9Ikxh3qsJtWHBo
+hzPQt6vwY0xW40kKkzAFvZ8QSOEt7MxWIJSwFNSAqW+KAZDvrChYdXvF1E5Bru81PiNmnVfaR7P
sJ/qnQWTaPHZAUsYxoNevD3CZm8eWznRzgTi2sCn0WuX1fRXtp+77XSWm89qzzxBvsCAV72PwLEB
+IF6zGqLTcezYsMWCIVBlNMAlymsDwZkzHpdaJcG2V1WGvfiXaWErhGTARNF47tNU3ew+CJjOhpm
+NWcAORKhJdw3MhiHRVy37UFIZ85U82W3L0zDSPnd+h2mqRgI2YyhPYWMJIw8ZejVjvfB2eh0rca
DbrRtAGZgnu3CyAjig5XPHop+rWpwB1kyuACBwitfzBFWPUg/BIU4YoY3/89FcANbpbaGPRVZ/iT
RrkEeenJKPfuQLZED38OWxI83RkBs8RukPGm0TsK3o+UJLRTZ+/N9WqHqjmUwNfAdjRrXgV7oKWe
oJNffbq3kM+jkq6vCHbi1QM3pMCxuXJ9fhvux7upuCa2GPqXXYeNMIG6qfcfEuxiaQJDLSC/ak4y
3PAD0quu7c+AVuMjcoQWNKxPJAWpC9MEa3btAihtaFyyb+nMzGa6lSwZAykUeJb801nN17sXAm5y
xcltTKfDrPVE+0TdQjOtHNFmGEAVfr60jfofY/ilpAdwiiOxtEv9rt58G5knqETXDDoctouDh+LS
Jep1zlBK9jB1xKcZsXK5fQxT9OpXv3fP1sTWf6fEwlskT5Tjs8DGUlQ3AyWdqUBGctDZE8P2XUfx
MoBfHJD/1EUziltK3cxE5gh4KIgKe5vizVWMavWNt16EZGHjEzYGb9uW6muoc1WEbiVJPxlNdbEn
bLmemgV5G4R31RqV2FZP1W9VU6vM6mUhkpNkGkCaSJBhFkHymyWrhPYFrP1k6moQkWBUOKR/MOa3
ed9EKPzbR1rhvWVJwEjyxsW9rSFO0AvbG7Wkb99E3dMzXTb+5hrU2G0nh9McQLR6kH/w1T0fDQop
GnA+SVw/CrxZOyBQ8LGzqcUav827pjrO8ZncvvJwYZh/sDXIRxqHw8PSxTx5P1SW8ue5l+4Cgl9U
kzjC7JI0DghVm2nEHMHZEU53L5JFOKy3Vliq0zInXTUmW9zIuLQHzXYsxxsnQTDHaq79aWDRrN02
Gd7aGxuev0cAQ9Mf3AKjcZgyIOAEINaO58pcp8RTZmkKf9twvLrYLHgb4BmGhdHxDPlqqvPpspQv
8XsMKtsCaPlffqvyzGdkDK+xIlDlwZP5JYq+FzKixvM6k3ar8frAMPzLG382LrbA5AMNy4lZKN0y
zSORD5X2g6fb3jDC0w5kd6hjd9ObzUS7H1gVgY0zGSjEgyOOtaPML5iae5XqTM2L6J+aiavCaCB0
4ZEiTEQ0L/9kUmUXHPdgS/vOwNA68iTRnXNj64fa04s5ODQVjlW3gELh9rnjd3afjp73yaFhwotd
jxtn+Te537/bPyX8Qcg4NwWQMHab67hcO/GvU04uAy7ClaIO++hTJLUSVRXxfATe05zLZ/2jjcW/
wIHLuCZHzLRPGAaQti9daRuz2ZYPo+OU+HGmF36fEJxtnpuIg3j1uVbKrbhtT7Zm8WqaUhs3Z+vy
8TWA9NlHNo1fH7hF+AsMis1OT7aCk3CLx20a+p8xb8WIJlwyVE5uj4O45+PuUeBqN7rtZSufp3Vc
s6PG6tW6xwlRmK/eeuRXpa8ilJymrT1Kziqeji3KPxPlmpgjKMNOawDse8HV4956vnZEdjYVBh9l
SxAsYgPeJiDhns7b/lN94JQ59ZFIA2UrcgQFsmPQ7xfHNWmj2zc1t0DS1BvBXLQ/gBMDJuGKrW2Z
wZwzXx6cQGv6JxrUHHSD2va2WKwCsnAkGxfjE//ZIlnCj0v/F4RpfLZVY/Am4HInAqVjcIlgYnEg
B+i1tQht+Kb+JlyuXaI1vH4SE2PJyDSLeOJRY5gX+tX7IVKMKIjhB2rAZ4/nLcYAVJQ/toXM9gRH
+r57ydkG38rcZkog5rh9AGjIcP/YiZLMyEBNwu1UKpOnQqGDBxaN/MnjMQ2syC1MND+hFC0nc/I1
2wvz8qYLjKlANQlmHeHTv+cfJRJvht78krl0qMB1sR7kVV2IJe+/txhz9I3DxepEQdtOSVTkaElO
duVHRNEJqSSXrSg9NKJswqIIIY6RjHa3jNYZDDFRNS0+SiyqPVkamYRk84CGcfZxMaZy6fGVNnps
AhrX0SN31N87Ejd31BKRb2mLHAD8k7OyLGdxhjRyCNZhjVulqZaBoUFuRG/SDxibns2MhnQ4fu6K
wuzhCHQFGLwNdbiBzkAtqLpd8CBRKROSCFKl2lcIHbjMeJNCOrd6gGc7FHFw4h1SYnQNZ7Kcw9NH
qZUzCRqTvkeSaRrOLDsgCQZ9nq2SaKdPG3Tq2MQTeMFdsTqR+Z35LMlYnFzfMy6pw6ojXUK0vEvb
X/iOc5KfwGHVTJcPsMaev+CU8MxFG5mrVuD1pSr9Ay1b00EI7/ouFckXHM08oWTky4Vkti73fJSL
SdvSa4au9Mao3zbk1sMMzAu49W3bROELbfW6/vILa85KjjSGdgwXnS8jC5l2lDGQprDKpbEsOmMu
AX8nP6qu62Zfg4wAvPPngIqVhpqnARXEucismqCEYfl9tJ5V5qDxRF9WvrMgw1XWaPIe2f0521Fa
y2Z9i/cAMzIeQkyqU1vdVbcBk2y1dNKj5ZMKLH4o/kxc8USYtX/Uyzr6PjT2ISU/Jwvp+NtoloJC
En8nVE/sG8ykJq49ul1/ukEfubKFmhRa8lotx8zzquPxqMDEvDajDkPx/x7l8EPDCaB2QoBHUEY4
Jhhx9tIM/2c2yWqwUy/agFEANoeuPVetcwxBBSWRvqNIBxHSVkSEQ+1juEFGaJgs0oiS33tdIGXw
cr7T1xdZ7Xot8n8cviK39sJz8lRIbSJ9Gw5X+Vrb1jyKXbWHnJUnpKSbx2eXLYFHReKwIcrtxNSE
vk6IhEvwDHH3ta+ye8rQO1DdE+anvGoSmkTkenIyl/sky65qHDXBPOGAIXmB0MISfhqZTCfy7yyb
hb0ZbBmwM7SX20FhHxV5/iDln9JyjYhPH6O18iOt9lv65x5heFeK9G8BBqfbMJRNriNT9UbM/8DN
d0roTlYQDI/nSTwMR/yDXbnGtCxO9p8pERycj/wD+P1oxfjflO2MtsXTu5qJVBT5UVZmzjxG2aw0
iCne0G6T1w+NNSzy3lo2yawhbX2soDA+uG8iF5OR94xBs3aYdjdjU45pzvqkivNzFwm5YewmT72C
nGn2iZ8jZ4Qqq/DFDqfgg1MN0wNP1ZvvZVvfGu7lsLai1dfv0Vq35F4vxPqelF8YvyswVaK3wujp
paeNbG1zkOao16sEist76Cu7X0nNTwCFufOVJ1bmI8T5by5kDdx8OpHUlOdm94fz91+0HTKZe/pf
V6lL5LsKpKp3J7i8VJ9vApzKneY2tO6bFtJiIR91uHj497V5h7rXg8YolGqOgrr1ncojLDe7saHS
aIeSwXMfeHiFyf3LglYMAuQ1P5ozXHy0ku/N0tc6aViROMiKyzzhDrU49+AEJp7UtS4kvN/qeEqB
RJObeajxEOx7+eWLcID18NrbZlswoDtlMbO1fLA4fAApaJ+AuOrbUoZFedcsWsAvnTZHwylF8r3f
tTCHtWvw/l2vXPTVFH+Dj6DNv9/TRa58gFMPTFZjCZrxl1D2IacXJ/lJbSAoQz/3zZfZQY/trnPg
Fz89k0XAgsiq44TJSLBPI9mNI/VQbRJFsyZJ/oGUUAaN+aryvpujlVjmVbEZVh4j+QYbQEKDWgek
7Dqj2B17j9D0QWiSI4q4yikce/LfNZ9Ty+bIaNtiAo0RwH308co4fATNlSYtKPWoyXYHmHBV9dkb
gZ+/Rx6CCagmrxN8aPvS4XjN5MPuKNCGX/ZCQRSQTYO+d9VVG3wtYMlO5ccx1IUUehlNjpK44wEH
kOMZ7+fzCjpiAFbtEp3tZafRiIIVIlHQPhZ1qAY6rURvKWhBYWmjwxPHyQSHQDM9qxZ+7x+QALMw
RnZmAPM3Y57EQiDbv/bqlK4z+abFYnxrEWWb0WXYbOFdtw7Kxnu90wDqXZ+nucD4BNTvyrAFKzD6
mhRZUx+q4jr2WUirooBws9WfqmiaWv8KkqKz+O4Xr8xQrQ3lJyBQ/qakqJUPMXytQxqKkzxmU0Qk
ES4rPfH9AQtW1OYOfjwGOAmFhy1x9QO0WhVHhZh7Jx4WihSNvr5oK7N/3Ol88RUfCGfg2aZDJyKn
9LUeUEH5F4TbRf/NFzExyyLGXNbbJd2wig6WM464n94Qr0W/cn9FjdRxHu4FyLxtdbJOwLDOGqTi
zQyCGR9wOm/DmUuhc0pPgH7P9qHBXycDFvSGB9UU4lt9El8J+19o9IASapa1IFgyDAScZ2Fhg/QE
4cRPwiMbsOZDjpeA7jjnPmS7QjTOidk5NlrS5g5US4+NCXj52ShyR4xtb5Rswu+vjyww32lUK1Cw
U73m6FVOMPQVojhkZkXs2SQMOeJKxG45nmU0fAp3RUICLM4dwNzOVuVKzeZo4A4LiqGcuu2Pf5dY
Q6vpFGhgDsYe+V8pU+SXnfIhFnbss0Q8LaOMTueQ0BkjIq3zvxWrtvL3CFcW6sEyv1YkUlEewwty
ptHIkX3pk2GZtxBtUBvY40kv0KH6H06xDfMTC/rlqWeCjl+BV5Etnaf8Gi6aMfV5KCfXP12pzvHF
bOtOGCftNAHnB2wfwq8OkBpJVWq0Kr57l3LQJo0BssRXlvQznF7GLvQEn0VU+SVGpfZ2cxjfT/Eh
MKaz4RkZMCktW+WgurN2zhJDn8IL6jbouQ6AX8c2nzyf+L0qqcj0mWqpuApaKkcVheLbN+CBxiXH
rAo7JB+CiWcWNeLxbJqoHtLPMo21ng1Tyse1i1bTujjU7YSF2g+uQpGwW7w6t4vJYsqqGSJ2fRNk
19OCGvd/AndxKjwwE6QE11TvH2n/nyL7fHx/X76dBvdz8ITJaegvALuoL9D1NrMv1SiYkFntJPnB
HkErNlxQppn22EE7F5XkDEypsGhwaaKEBv8EN9VrN3KniTpHPllFIpRTRo6Ja+PnRlfjC+udQyzn
DCASEuHrtaG7IpeuD75QQKCYM8nSEqt7na8ua6l6Bt5SE/EUBYami1LobjkUQHLbM2JNlLRj9160
SXdqZ8V3hj5fG4w6kfU04ixwarPSn43grKJm19L4ldurHjr/mRYVlv77TAL+VbxhQVwqruprElS8
df9YoPDvah3n3Kr+fmI1mmQqUlmySULwVlUt1eCCj//4VYkQP/f5hUv9/U8TH+QhALnTjuNk0C32
qnU35o1u1msJXS6JCOwRyEotVDFxMztQxLIAV5nX4whorTAi0Qs5pa5eqK3wF/ip1pcwkgq6zVPD
JMom6xZcRR/t7V+ZosTKZMFmQt9U8IRaqK46rcqvC3pGdcoXnvLO5gARk0iIpJ4NFl96/G+YmqOt
WBkFxVIurAcZbChwcq4X+nAHWjEB5pPZts8VSuJOeK26iFo9owNAH3iQry9AT5QViSot5C4UFxcZ
ObfHojUjGnKzVUwjhDUda0H+yVeRmBcy6mVSDGCesJ1XsoCpIj0/zHqvcdbx4qasKzbsC5XrEFPu
zs7f5n6IEx0g2VRbEE0GEDE8Ocjuopn4LBwwcXUqpmph76XKQduwBXjzyJ0tFkmYmg6l0BXSvMs/
r8QAPnXwaY3giAFEXO0gJvPbBNEKDtmrPKPCWol0xUCx87Q7juzQvfzAfDnbTycrVHo2VcdQreOX
BwWHJsUyWgra8y9JHh7d9yLkdgupGO0SSXMtWqJA6r8rRG+TY5WbW/7xHMvKjHt+BvgSn5DjcVbq
MYX0GU40tbEhmEjSw+Jsl0WLa0/lem8hSfZrtN9Ojpsv10mH9bDDs3Nu/Iu1jzfPgM55F5RwYmNy
aO4MeEJ83P16mlfQv0jQpl114IVG7yxlolrrJmam3vdfnG9DNZGO78T/4zmPKjnn3JYttYiTz/aq
iBC7BLrjMibBS8yDHctuN0wiuvCooFDpQ0d8+v8JbjLxHoqs1rGrV0FVgdPR8UNvi23DoBiYADgO
nVoNH11ioPF/6pzFl4suFAIzedHIFGNWgJC+iYO5NNTAlW0OXppcaxxZPNv25j48i2ZSrZZVJ1QC
Xw1dr8nTtADtHjMdbpdhhixvlrbVI8QuSRP6kt6U384xef9CBxCLm3ZdSo1BGdXs5cSSp0KP122Z
FnT+5MgCnY7M2lYy5h163FPtcMLLvoTfhptGvN+WaufZ6JKu449g6N4KNaG9PABadgBA0c3KOCNU
/pCeTQR1C8fwZD1qKDsEs/DnG+C6pK6S4P1BX+zDtdU39qbKhqNwPc8PC0F1dhKe3JrFzu10iqOe
WNyVRs6ZABP2kkh/I+tlU1NL9X/NIVwrtpBWAMyFc6uYTrM1hFdKsih8zXl8qDLjnlU7GazhtuPU
ZM2daECFH+Q8etbjbJTsp0ohnY1bAKEvdzcZ4a3CICPOyStrHPKRL9H3xmeXmafTdAyUspWKV2EK
pCOK8CW4Kv23XwP0HXnslgWOq2KPigSiSkEfQ1Ujqj3eomhZ+UvsmKTiMpiIFD8I5grnTuqSNcTo
+0vKa+8IixyDmTIZb0Ac/h9J5OH6k2K3eilnwiMfX14nmj0/H0jGBYQq1/hACz9dr4NBovTiqgKF
TQw9zRn3DSrdC3BWBFivZgUXsE6+qTKkdpVZNhI/xjbfkIPOx0FaZFREnqctC+IkweXqnaVYra4r
uBTuEl2IQSQqJFuM7hakdt7Ynmpv0vgQMhdBpAn0MI/K9XpyBS3Glej3RwBNi+zwCN6RHSxmH8/C
SeNeVVh8ZggqAvk4vu4ZHoB4qSJsrS81cCliVXywrE8iirUgupMA8djKZ9qEbDJu066X91k03WYr
4x7iOk4gi281Rf/kP98bSXaxji8S3nij1hdnPN3vZLdY0ShRFOgSrhF7cgwQjzzsUT/44uH5xM2t
/DUdOGncAb0Xet9L0ZOIma1apgTHly1KgiTloENw3kiRvi8JHYG3r3kgQibJLVfIQXgobxIUjny6
NSJCj9REzIU7KUChCM2O2tcJdy8hWuCbntc/V5lLFvtqkRaPM/yFAgcYgsxWA0wx8fh+YVtCdMc/
eeiNDr31FxaCw/zHMFQDMxcw+R3gr5TVJbyuDWJOdOgFc5skgYmWCazOlEO7pd//Ot2J/5HQPdm2
gkfM8T69wc0LAzIUSojS0d22881x8/eml9+GQE2uDooje5y+RvUEorNHswLRLHs44uOTRZ5W0eve
u0bjljI0XgtH7AVVujvECcpY3wWNnAKvZqaXUnclg3LhWMfB4+dO+xi9r1wMrAsULIQ4RB1f26iA
1pqXYVApDwAgGz/fXy7CrguWJkvtocz7RfMk5MQWs/p+E0i5fTrDvTep9oSsFoMbCzWFyx+hfQlG
DxgXoCrX3WmQwpLpcV/0RoKkk/kVA7ciSZ6F2p2MRnVQZq8QlMxK8pkdyq39JdAQ9NJfPIoS8jcE
B5rFRCRLdUd1c8rBh9Nrf9vKj5B0mZXmW6BkVsLqbDjolNab8NI7CwIZiXOeRBZO62mTU+5qQ2R5
akyvIWPw8uawq9JFtvNCeop2h96OzlU8FQ0TXspz1pL09esaKEPRr7L9E06JDH0mVjH5bues7sd0
YHGMKA/L/Z2p0h63YuFHL2X7X7rQeiyphuW/ezpKfMjYD3ZccFFRX4jRduvy7+e0LYNmrKcIohL6
woqolRz9FyewpktFxE5Vav6UOhX5QNfMU8bXWKkXzziY25pgkhTI1aZcSvdEkvOH97rnLil1Z9qs
ojNcnf+0Lzj3F1bFy213pypitIj06cHf3C0zPlDzeErLySrG79zzw5FqmoA587NESXEZGQXbgCec
8tck7kBaIn2DKNfiqJbKYBGtF5JUTv+O25vgo+rj1BSDx+Dr2rZIqNXrhkjpjHmb4is/jRaKsxnw
Nz56aySwI8ph2RH2prk76l+RxhhwJWaJrmklc9/ZTRrPR+9OwHrByZ055IgKIcCJsOQjTBYiElnX
86WTd0nNV53Z1wzc4zuUmwlDPLl8mZEWAk3aEGM3mIWxR53ESYLS+UwbFRgU91cu7PP+qE4A2XZX
ty7BOth6/6JiDQAnQEDvSsSb6tdTaEEEiq5rez0iKSz2HQLL6b34/JzWW5bcFlwOFDWfu/PX5O0Y
gUIqnjAkSPyeQQdcW58CXIPe9fXhff9XQXCXbFLZ09qxY1+VzSWeL5nLKDunjA+bVfXpxhfAOgGf
nHcfRPa1wIwUyJK9qfDgffz+v/C6YbCwbS/AK9luwZk6xX9gSG2AKA8NQRyhKaNP3mVcPu+1j2xv
uvldVTo465dZQ4SIdEbvvTf5lIYbtQNEL5x7NieobekzSkB/M0NvH6k2rWchowJANn01qhttBYds
H0ZXQutMNmIImACdtRib4IimbjLb+xeGAYQGgtVhdVXHefDAcC2gLtswWcuCXdgLmcw7S/a+LpkB
AYWM5D8BPlObT/rSiHN0ZONRR9adLS806YslHq9+wGuFXC/+qP3x1kM+aO7uVbXOHJcDX5ErVgvQ
6wdYD6m8zSRVyuWLuUvXmUlkgMIpWtnIGsxYtNtAsiBe5eukbjDzYgDBYLY+g5kA3Cvy9JM1pzp5
tS9Uv8FmEQ7MmSojL71BCdlOC0lfBLwEcLwaH1ovgkbU9rDACdLdDAqGTYAcdG6Hs4mJXS9pNmN7
Kb9JB7lcnYGaONAtCJP2PC9CrQ3B8o4P8icG1H5rE8T6m8VasonQkToFuCN33r5DfdSAOxYYU89g
RXYtrXz4tVaX9NwUpMO4gJqY4mAWg1PDjeJEH7b7jpKAg/rgTzLxZfLEI7OAf+CcGjbLsVkEF79e
1XybrLLMd2qtY5KxLlOsB5Z6vwdhCpOC0/QffgpaqguXaRZv/VfVuVN2v8t7TS+qsBKgfwE2mGrD
SOAvxSPZydREgutuU4PL4iusSvQcqpQv8YQHS/10pljGCKqUWfNshAW/BmRUor5saptQhsd7Wyro
/hd8jt26oCJWi2KDYdjkAsPS8UDj/1OiU9UGLFgm7JUJkqmJzw/KhOzT3fK9zTYRWoSoH1AmjJjj
GEAJI9ceRUSSX5Jz1yzNwBPmQ7yYY8z+YB2HHzTuNoER8k86hHdc0lGZDho3XFWqnjYD1/fgq1Ov
GKAZbYHWIejsQX0Fbq61x6K8c0BMQzhZ0vzN4uMLMa6Je+UyjCYyQeTpYo2AbzYRvJ5XniuFZc1Y
uyJHufvFZpnnPwk9XlDQEgVjTu3d7fY8j51iywPxYhVpcw35F2wRlENNUsh/bSBOigeP8fnHzCaN
Yd+Ho0h5GDo1GvocpBaAHTb1MKQrovVq040magl79xTWKtSuxpBCvJpsVQLb1G0aMAwQNNNANkee
FBUdB5nZSdURF0rpMWALxm52jgZpGmHpq/uTS89KgGZ9Z6xZ8LFDRrGtzDKI2XD/1psPyfibbIci
Ek+F7x496tHvvg1G3ZfqXbuBtVGqna2K5tr7en9XftZawL8CvDjsMjKcAjFkFX0w8iq5PPHPAlDB
ypE7xplnIwnR8cotqDa3l5k+wmLPQh11NumJ1FPBcGq0DXG+62Ppeu/IWxFUmLDCsU2iazimACpK
WYrXmuc8YU/E4cq4ksuVrobwndzPo2IzJECYldIzruZ0+twbxeE4hdBR7FCzDnLI8qDRn9Fpfrl1
/yH+0K9wPz8j28cnRtgSsGWW9MMoCdW4dNo92Lt0kT8vFLLd7d3/c49LqdyTZ2asw2Z/A0SiMacu
Q/ugyr2sEDpWAXu8eoV9dQXGHmiGfrUVZVrzjIrRf7JDTiSNktlME4y6cCZsphCFUt5pbxPhQl0W
4rHyBr+M8Uo36ZEHmhNFLONr6L01T6v+FTJ3gcbxVjGfjKbTIrg6w3KF+k9SWSVPGhW2BWqjcq8u
63qXaXS3UZhRpblcBltBaRugPDn/eR+SK/dzdAOC458TfFxVtx5qwCVv5U9Nd7TJ+10PXfBODTFD
pN2M/RDmtUPzU/NjaDBQRLneTR+LWyVxU3/rP2tJzo+jEEh6vMX86jy3SXIY3EBhDrYj4/QZzMzK
iuF6ptcAj5XjXSE17dBsp6GmY+41HBSn/KQoS9btFfbzOzRxjh7hq9/3x6Il13cwD7u/Ig+oNUmg
iIMtlSDnf3tIyJHwq8K0w6an28N5VeVU/PLGgHftsSemD2TA+HkH6YYJNKZqNMi3xWnaXws+cy7X
i1vu3wChlj0rVIJQiOyflTwbutza3X+QOgHb1HBd+ZXGu+Y/RFitOWbQ1VbDPh5fEHciyVtPVJc4
p0VqfCZC1oa+uRutZH4pR74YFP0pOnZ6ISHkuqwLR6wOR1ngKiGtlgXTVQ9bPntnLtGPzkkJyxrD
Ubn43mk42B9iEfqvdLGvzgLa92jtAJrgwjqIUG9p0FDaRIKPFFeq5BZ6lX22Kgtzkv2u9/g9jewO
61BMRaim62zqcgwwvZe3nooFeUvwl+9SVdc6oqOC+VyHBByUWPk4HfrtUKuegp9UYfuPE2HXUsEh
nMExZHIPpnK7Bp9D4SrILvWLV/2Q8WvhO6tUlUWAFJZ1fCJchOIZeqFMaeSYtmXzSR3rAiNUIh9M
m9bxZqYJhlB95oyIP8fRUup+3cv2MKp2biAT8km2EzKFsMeVGfQPEKt7wqYbuRgkEo/jKaC+Tl94
KY9rtsDOFoP+qnasaWK4TMM22+orvYR97fQOAEvI8gOihXFaC4Wzw8udzfyzYvXjLzcbYRtvOnnI
57ETiMj3OAWAyYAOKBGzcRnfyttg+pX+3NzfKJc1v+DvqPHAXV0J20nek9DjhBGWXLTChbqTYJ2J
rjYKP91RWeXMJ6oMrsBLZUycCoh17pMOaF07G0xzqjoIfuN8qGwJ6Bvy9mMlIQS8GI4M5n3H7cnL
11/s2L4XYxNhLqPa0x/Xtoz6c4ulzBuRzosoVhVVBo6XZwXAWmpIBrSsbEFybrpUeyTuWHHEB6Bm
MOSgPnXDtM0rKWl8lAIfOob2biQRplqm3/kXEoidVUeN07dcW31gemG+oi4DR9dw+Xx6mvwwcrQ8
U/Zc8h7k1ywwG13dbplL1L+sguy2mb4tTz5QWRythpeGLwcRSv+7nqXA1G6gK9rwbtL1H2APAvB2
Vzam+sMsMPTzGqg6JbXAISpGE3sKfBJCR/TQsQRB7TibGJ7+JjFvHpt7lJgD6OhEo7kFUyWN9P/F
QiogvdvuSgS0M2trLc0w666Ik4kI4GGtFq+6Zbuy6sVOzLkjipBmkYqIUTvL3DwdesYCV4Fy6Rdk
7btbmNM4NWm7a5nuKw5m2HSBol+MbDp84BSYHItVw76Mljo1T+4ribxE62EYqMM6/BuxvUKvX4TV
1RTD/yaN8CS372rifAYlDftOiTzn7tsSLlNel7BY/C0/4diHq44nrXjki2kBnlMkPt5tTWifu7Ki
LKF+jDaI3QAxSbpABf8WbgEq4k767ndjnNz8RzM0GuJXcXjFr/eDlkBWwhXMq1l1PnTrIWH+KCi/
RpYrJtspW7/by8pzxFNQpItB436MByxyNTJTA+v4dzRW/zdD86InFJqlC2zG8vcDFeGGFG+3kC1h
w/0ghj3/98pUMDIMFe2/I1ErI3ztRooFdRNhtYKPwosfr8AAmtUUoJuRImJm595Gr3Ru8gOfMAcR
bW/dpD4cWiPdvtTe2eoGFrA9LrmLvyGqqFpd5ueP6vjnaOTHf+qVYJge9A/wvlKNCZ1vrouKLG0+
YIP3Uq8v8a1EsHiXnmlXGpDo7Ka+n0h1ufhvSMyScsIJyvp5YY3R7c7qegnLljZSUTiaFF8X74nD
lR+GtUqYCqK4bZ3DM/Feaby69LrT2qtSzPQ9VT3QVn5iFRjpczE3ouj786gEFvB9dfj1pvjhy9PF
IdVYq+/Tis6rl50Ssq7He0Aco6B8jR+TeD4JdolVgiqGZ9Dasiusiir5OTi+yp2nzDoIp+wKG6wO
HRlzB58FiheVkkKdnVTYINIVIgc5VK8aGDTRDWDIRDbqm2qTfBefXLzS+0nhOLVxBj6gn6LtSG+a
IC7KksRtdn2hb3nEWvKv5/0MTLjwvwgJYAkQTe6fxJsy698SKyqZqND3vJrJZojZoDITNfrQbj/y
nXtJK9WDCvEfQRCXjA6NXoP0/zKYUBVPmHTzMXJZBdqDTCqpc1xnPApZJIiL0VVBZuk0tTZT8Wt0
iUQ5nvS2gl1pQjyu5HyhYbuu2O0Wd6sdGoPo3xq4v6r3xqcC9C0GcnIzjesQ5Pr1n1l1/i9x7wwa
MePfjDKp4+80DglVu9LVssQNVEoyn5MFKxJ8ks6oxNvc1QF31XjUfTC2/AWthfwTEteRBJ+5DK8a
SteJComOqvWG4Q8aGXzcQFGen1OZlSwgjF+MK/arPub8f4XBXEZnnp/kcC6awZKKCWf5qwlt4S0P
ZiNwWMCX+zzwg05REsJNkI4mi+OYcddh89NaQZOagRG7C1jQdGHdAz4bvB6oQoBy4O/cwoeC9Ge4
VhJgBWc1eEf8aEoQfRkExAbEE3KHPyFIuLcSr3/b38sT5hum+B+wi9OnspUPbRdx6lO2NKzdQZNX
ZIQmsyX47EMxGjL+2DdwRLsB7tudqxmiPMbl+MPtGKsSYlUwF1IoUYqvdr68jXFgZoUfnXGKjmN9
NrMxNXtnPq6crEGb2Ybq5LybB+iEmedTe9cEPwUxB9GFVjVuL3T0amsADX9nSiLLmycE+tAMVh/2
1L/TI10gx2oumvXfK9FqrIdFh/O+0wPexL3RiR4cf3DRiTAPuLGxCs0AsUd2WnK1KlqgevTAoXa1
nesKAKwELLhhHZTeYPCgEMZ9i8tkI2jmNBSqOxPkuSmaHfkN/+PEed/AkICfkFb93Hvt+8Xi2j8b
UOu0YkYj0MNSLSLq6fGNs87EeZ2QPY61z13Iwcq0VL8DJQwg6OiJBTYdnEzwj93vHpVEremIQ14Z
qqZ8diRoknzTlEjP12FSVhjYyp39UIyRJ5FpDkzHh8nw2EO6eG8LYakg6r/Pav89WowH2RmF4Qa9
YlXtx2EvSTCNbouLG6H80EHwjUOIjyuFvJx67qCQlGb2BfqcTnhso5bGk2X6bOf+UlFqW3d9Q5HU
94DODaABVQDTk3r4b7wKKqGQ6WdaByl7ixxG9muuFoNqnnKfaTWWDMl0QV/m2iGiE4bdl2HBvMro
HO11+N4CTgfOmuS9FpXBlHM+bg0fLEJ2rqVkpLiBMF1Kj32V5Lk6HC302GWR/NPfELSCHcMwxhZ0
uiRt2R4THdN9pfKPPvVFm2LKxQ97JZ3mvdzV21u9F2+chOefJgQpPCeweDWtBnuiOh15VbIa7fWL
IaKKUuA4WGbvBRtvGwgcgkejqGOGiZoTj2iBIGME7OLCL6yJZzmAEwSVtohwqf/pEarHu0AxB1ns
K32F7Th0Llp8U+y2arQWOOC81xUFPLIBz63MICHztfu11GEg+QGMNfyEpJMUJ8csxmY9z2FrNEzZ
Ph6wLJ+1yewkgd4R/UIodUu6POFMG9zKcG/fqu96e7/40KdKvfBWSc1PMN0r4NJrLHXmb8ljgzS8
HDJQYNAVqwJl/P1JeiIBlb+IxCkIpNhEw3zv8UjhvXoCC8/x7yUNy5goLWhXppQWPcaICq5KLjWI
xcYRSXQwaTHnDATPAoiKFE/EdlkWv1LTLYGfaYvefY+Jna4ZsCp2MS0kgSVSfr958Ar31oWsFSPa
sAgliZxN8fBPuQyzcEMqdxDqE1llIfXsmV8owf+mMvQ2EGHmniysZ09jSANGrYns+WLvqJRZJugP
Rt5awndx8Mp4AKWiZhpg/P9/FYqQzPjaFFOI4nt9yh/pTUvv8b4THSjRtexbQyMR8mLLbERwA2Fc
Wu/KZA7A+ZtvrgE75ewhlugTzOXGi1D0GQNuvf/WP1C26qiJjsnOnoey4rTGJ2mnOeg00l3hp94z
o+zbhmBYK9NAt9KSWwSF8Z5ICkCPi6omzwGVzmeRf5Cb5Lu53ApRSSm5O2ZBF64lbIJq1hTLEwih
NCsaO+qh14jQaWMXlXNv63IpsL8Sp0WvEOIvfW1l53ap0/uhNT4G65SoZEOtUjZM4JSgkxKvphE0
3XCuC0C9NReen66fuAAdtMEijt044WeZqanl9xw7IOysR7kap16a4HPPeff9CDQUu6xPljWTviel
YBiPDRanD8m03RSokPMqrqljDY6F41VHn/MF+sDwkTZ0YYUDhKQCYfJSz6FvwdnPd88QE0littX4
TOKn3knrFu4Fo3qB6Jtybrt4DhOl4mHOl8DipOKuRx6El4st1sOx4oK6KULy+X2BrZIuAFuyh6Mj
nwXB9FasOj1bf97gyWC5HJTwPol2cYi7pBjkF6hwsFHSwI4sDZnbjvZ+9Iq97e6P33Q9XTFIvYTZ
fvGNT2wrCMbGNdTaCjVPVnf21wBMI5Q201oI2O0ZPe1PY/0bGinTzUgFbfXGYtXjH3c8m48FtSvD
MLH19Igq6feHQHvRvx055l3VeHRKnvyhNd25g8A2ZvDHiGi1Cox+TvKpuGD0gOjdQnRH3W40Y2f/
Bo/QeW7C9pClHD150YSMBCGLgqkAIbbv/Em3iejluHpADUOQCP2a6mSTyWe7pzSBzgSEeIS04LEs
njqGlo734TuVZtTzODn5j9yhLOhlRgPHN95mHb6tjmxxnq37xTPlFtMmWxAzdA0TjRngTztzWaPy
PXHaCEna+lfz9kIYylkW44Vzd+r8Vl8hRiM6BYuFoZgOc0zkord5UAJlRUcCN+5nx1gsqs2RY6y5
ZBcco5Fk5o1YWP/ymLecr/Gy3o9FXl74fhCM1L1N50XlAb/VSE5e3SmlNHLguBkUewVpbx8gP7yf
bLs0H2Voj+f9ZPGAWPCApta5fcp5YeNKMVPIbidajDWVCwiCPEzO+g5BKTSfMSjfyQTYcn6nP7eG
bByEqYqq2PHVf6fvywXk/OKDxryqhKhGRiwSiHvOtEHmZSXfQWNysYi4wnQS65rAfbjtfLYkfq1X
8Ih/L8STTsU1xxawdY+yCU5DmgrRtfaqGz6+T7Qqt3uxy2Xzgfp8+LA2XgNCyyG0/mrLeQ0Ts9WE
pQGTVm8JJ2fjvKnTRZocSR5/g18wJLsfXNJHBEPyQaxR1M32/+nGgNfaeERE/Du9RwjA8sr06vbk
zSBCqhKCLNqWrhHrb08bAYuQlTxAPOX9NkOvdXXpkHsDUJNB62sp6XsZGfYisdJqKo8osBkHqJ+G
Kt8hHEg3FPMd3JuwB6mqy7c5gE2+J4/HTE/BR+a5J63v2SzTF5aiIXf7nfAPD8GNRFaDb4ixLkYP
E0e20TH6Jpmxp3hIOAjYXKRj4LMqL+sfPFYnn2OnceBlgPePgWIDMsXvVXKCSCUquFA6dQXjgNf1
QlHRNx0PnHClFjMQ6+wLfhGZLVXPw1jcSMagBhzx4alTVZVNMwZHrtrUPjMULZYlS3Zt1clKEkVU
ppuxpdYlL3+CJYMyJKk4eQnFphYZSl0H5ruqSrwg+Gs/bb4ZFI1VsFCaUKbSUevktHkCdHRXdeul
ghO2ZMAk+SLcvOE8pg9myHjlIANxCQ8NrFc0Et72Lst9cGTTRgr6A61Fq/+GdUDjC04aQuIhhuMY
51XlOKQPr2wxkPQ3yv07EssYtw3H6t7AhGKqQSn0TAq3FKdr47lPt7Wdu69MX8Hy6XFnvlXh2llG
VuWubKvAprN9Q66U+Cp/aXctkjvSXhaAFYYruOzkqEefnebhjQnR2js5xVGpcseRLw9iuN9ZwJNB
zMwrGOm6O+I/UG+JowZFo3ROi7zYodT11Xb8Ma4+nQ3PWIrGh50SwtCs45pWx4SXAjFD9DJdpB19
/UxNvImpEOP2aw3QArEHtHsMz8pxNthKVh8VUS9Z2rqCgPpnBghe/+gQeb4OD+mau0U00dcAsIud
4Iki7HRQMHhAsRdzRPcxctn7TBm1e+wERTbsiLia+K6JCuwYD8N+cYUZ2dywYoSA03gciMcYN8Y9
wDLAtjzofio7g6rJoWWbeIQJDIwrT0NTUfDTh2cRLPkFCMIIrK1Iiwrx2HJaWjdMw8QMzyGc7lUg
2ZAV08qpy3jU/kR3hl8Kh0vzU9hU0sA5946IHPamg+I94yaYREOKEh/2xBp9LT0mJ2m6hJR0+sTs
iAslSMDc96XQPXt26qe/4dg0T7HdwFMapfdquA94NQjsYdET5xFPCxNVWwLSSe0FRjl0hXS9GFHQ
Q4vY9gLMz6U4Uf1wEpc2nWuueaHrliXzBn7s4WqvJwvMHlofrZQzIuEiFwrQLs6HV5aOWxk327fd
tFEYgk2JKRf0tDOZYyiWlLWe05nAynS23rrivRrXNCvHvQr2tUcWZpec2kX/4ID7DxTPykKHW1BJ
P9UaTAb8pZECCr83Si6IJDvo/t/TLEHq644nhS+OqxhwNBLHasmMn9aWCPNmCnQr6wmcc1fP+wIP
CLcbnLJ5tTyZoWiFWwyQHmFZSerDMLrvDgK75POfKbJvHBtRbggqLq77LWUae2h/nKhgEmDINL/b
59kGA/WiponWWyCC4UEHtloOR5u4rBIai16feDcsNDvuIpLrn6fGcwAtlA6kUfkRySpvpCwlO5jR
QmGmR6tfTKiaTzyIGvrhdhhUSN6Fz3PqWH8rUVZVuHrl6op45IfQd4hq5kMqtkDbduE+CxcCbu4k
XSYpU12JALDvL5+PRv1IhFs2FfrpKz+y/7omuIkuWc+pTEb4CcDOIHCg6t0aGJUOrGrSY/kAquhm
wWyoT/ffCF76HHwa9lKV3K05KKf/Dsj6uMFRCmXI4V8A2DMoYFlbLGbyE6taN7kOHDGI6AHq8ZG+
aya29hZqsl72ENZhhLje7RGN08zIbZsYLwYDTKLwF/1PyN1nJgl7E4IfYhVkfNrN36mcx1EvUWK4
OrNYFAExWsaILmeDhY4ROEEjKpUaVkqxhba54oOQrHGoQIN+qh8+VkPfa2oG6JfvCOB3BO3miMeV
b7tNQaWjJ+P4xumqo2jqojUhHoQHmUVc1fvBHnRKkq2r2ERajBT6+KYT8TkBbhOyIuqvP5bd1rrc
bzT5XtrwlDx86otumH3EAX1gbiiyCXlwgm4sZJrmBT1AVejgGuv3GXi7z1hoLRuQsbDSn8ezgXr3
jevjDnH2eQ3sixPZnUoQMOAaZk6f+OiU+mcJu1Nobz3njMxMW4/PRH45b0F1J/IU5baluZo80f0z
H8z3bFJZPqRGaS5c1ZjmEkFFDiCqMEBqyTilHj/ZY/MScuprlF/SX5q/ZQ9VR3UbP8oZDkpwNxRQ
DcqXcA8QwXsQtF++J4SElcb4U8Gmq94b57oG2V1vNJGr0G06gX1MVa6pNHPmrdXp5fseRS/LzkCv
YvsvgS2fvNQSNkleFryWpH0ZeESR43c5gwChVn+drTwPz4nkQwdZ1O/pvBMe9hSHgCsNwiJTalvU
P7WE8OVHfYg5JnAMKol7il70Fpv5LrLqSislt/ZxjsdRNE4X3F+DHzH0NqByj8kBEFufjhvAuJiO
p66VTgwz25S0z1wR3vX9S3AFBK0pdp8F4Fgpnm038MBHTNQDILOvOzxZ3U9TUUJizqwrFiWx8rQc
At7gmaVjpE5416BnMHh48SrXdNx5fmSeV+7QO9oV05a3L1zqzSZh8wrfSW5dtfk6W/tMu8lGHwvc
H1g1B3ktxUSGNXfF+8lBF9b5DtPE6Gc1ZtTYpBY6sX0gbWB6XLIJ6QDAfmQ/J164syREBEWiegg6
eCI96e+q1lrVd7qe+xSba1sv0TrS94tRrdKUDXNUmoSdt0KgWVVoxf1sJZY5hU+FdcIqmFE87rNo
TcANnr7QulZZuhxMj1ELnf4Cvv8wEEYKFFUpgltCGpf6a+p+RoZYFeYzf+DcZ7r5IS7xemOhE1xA
uLQUb4353iO0PV/mWbBGzaDxzzRD3m6RmKpExLgoqDTFsw5sk97iTCQ7JOv1H+O4Tuc3szcJleAO
bU49CNGXNnpBjTGDQOKntc08vdZLK8QRl6MuGXhRQI+kLmW5T/mPA9aRwifU+G3rJTiTSXtVIHcw
MckypNBOAfb/LGJOHgUnSuxF754wQtIa7AcpJuP6G1KmF+1CVGqwkvOsJVf57k6HpGJlqny0rrRO
JOMEPVCBqY69RDHBo0N7Rr7maaUeZmgw0Id6l9VsIm7m/hQ3jsu54MAM+g2XZUbNgPBI3QsoeFL1
BISb2QwdiWtiNOR1Z5X9+gdZYwIAypnt065xAspCf6yG5CNmvqrYZPnSorKBoTm+JZZVvgiCQ/pn
ILPiR/FpNzT+OIORh6zEy1bL3ZWQ9UoR+bi9VmePRY6oHltiFOa0u7kHHe49fni2F28qrTMlk4/j
D+A+J/gqHXfX3n87/Kmz6pUiVXK0iqA5+OLESVqYBx6gvDs4XNMg7Kd8PHgyAAsUdYkC/PEXSpGM
yZmwnhbkPvHGdeV1oN8dm3nafVoT77O7ACJD+1qsKsmISq0tdCbjTO2UgVXXppQVdwm5WjQ0fz+0
t6cjxBfbvI+uTKO1LnhmoNdd/b/HCac4xwqHFACxX9lbqfm7tx4hlvsob1gJ98oOLah/9R+geBdr
ovHAr7Bg1WALBPJPZ0kTb7ORZkL6jVWylZc9H30ueL2AZrZ+na0JDc6U138glLWITi58NATHmOE9
26ZPCFd6xoRYQufvhFBGn2rH+VLY20tHkNn04Uaamuwws8PNxqMgkuLu9Fd1MnZ5RGltFiYAZ6eT
uM3ae9f32W6zc86BBI2alN4gVjHQuI/KQqj81/WwoMRrqSY4A7xc2GGw1Qj+PyR6twvDUQ+c2NW6
xT8CD1lxICTEgxP/l9p8dWf7elhV1UJlAz4rf07ZnRi1e0oaSGPiq4UGVDu7PaFse61nTJOO1lT1
C0SIYKxVY4Xu6YSV/7XAaWoA/FIjx5sQID/wSbzBCNlqH2POQKIHNWh8CLXdj2ZItTamSGvSGURI
/FTeUGK999x/Fot1+5Az3HUK65ws1fBDF+qhS3k0y4Ht8k2gdHW4PWKdKu/TijjvBo8hn/w9wDUe
9PNfGl3EmzPRYq2pz4j/XZ+dJvEAsHdKbZoVoefly55QpYMHLFOvnuwaNXLrkJtrgyOw6LAhpKTc
7CwA1U63qQCVI8FNhqCKJLx6T4+TxEEWrhk5vhxaW6uTm44vcTgjsBxpqp+FL4oY9PACOEdn8UAl
IWrVMijirLrNJb4e8b6ar4KBbPDpcJiu6DR8+FJ8k6j95SzWg+u3FtuIIlIDZIXhNPZ0/ZjmtPjX
EqZ6BwzRj+8MzbCi1eOBpSXV8fT1trFyffEtI424FB1PXD+EPw1NOfRTj5ZxmAm/oUVESe9wcpXW
UiNrU0t7G7rqYOjfELKZyGjKkDG9bLKHe+cGZ+VhC/SNvH8lba7oIHIuYEA1SoQ7WFMR0Ngkze5W
2+P9TuG53AbFke25IODCWT+DxKo5pb+PDCjfruSMMGeOkgvuXbEIQlke8NRDaqaUNkWk/ItCDp9f
IBuCfzNJvTBPb9feJx2V+oYhHf8xAh136U+0iJNpvpFJwTpLqRtRgQql6tuJAeHT1S5l1pshdg19
K/a8iY7LU61FJjo5nMKX1jRC1kCidiQX4oyrejsWiVHO7vDc7ww53CZNA1yIPnfTIl0lXvCb7JHW
de1mq7RW1NYqU7neSRYK+WfSeu2MlzaukuZdOrAmJe5JZtq7kKCxNMMtP/te87F8GzewgG/TeDBq
tI9HZJlzpZUeCme6yT/KYIvBwPgA/Sed728XQmR64hlMjMcuWZ3GbZuYP8kwJ47MaF1FldN9kAk9
176pX6Z9orqSnQ264ZZYU8VeQyOx+xifRSQsQtp3iIP2vY3tqfEXMV5aiBPsZhQNcdrtYVVX0E+F
6+H0u9PgyFThVZrk9hym6n9XIaxPS/AzXvwFEV/2f2GWr+2FqCOPuXL5Zdq821944fY/RoeN7pAO
2V88SLq5oxD22UiMnKvjwTcQwUK9TWgH9xs9H6GpUAHMKBHBVKn2pAoPS7hRnPZd+2SUPexWO39D
dDh9Yvjc3rCNGcPqAJGrsS8bK/F9I1DaGOl2HI4AAso/sGqBdB7EGGPcYdf94Ol2Db1GY1ty+nQx
mqAo23CavIgmJoRSRVbZKfEISHmv01ZNhYy90+PGsEO6GlfVGbnbH9CLWgvoHVHl76cgjYbVjnfT
WLOqtYxsa1j34QfVujZPLvFzFQ/06b+N/L3xzoSFkQSyyk8+Alqj7n82FjHHMxr9PhLvFkcJZVRj
Urfawry9Bd5YMsS5LCUzO080RVi3r/6+r3SFQeUsuwDzJKFzbAR+ZiV8OzQbIzj/6p9Fwtp/2VNF
vVw6/lZb7JZRycFtKPY+tXNvf47stc8XSML5T7aL4SUHs5jGDInQYE3070AjExX8vQ0QlSCkub29
1SVi5X8L04ZG0Y9mCULK5hbcub9zzh0XfbgMPYbqpI5I77s6ydGF9v+vZWLiuhGFNC3/qmR9sY0U
JNe7W/u1ViFCVc9Z64Jwlon7Osz2Mt4VmIKyWpsjJUes2i6vGIC4tPXnmkuJeX91U0OX56RnIsD2
/Q1gDsnjEa/8VJCluSMFbutpGyHrCQPSPsdgSogFxiJchFgXcRcdOyYGnElbC0Y5jxqOguRncpMl
COyuRlmTIzFevZlFeKzDImSpIlwcwvJUBM8Ruyt5X+1GJIijTJXB8o6ZoVvNPrxkO8/w0m6LQdGs
xNoDfqY1bgRPU6pEwH0UcXk6KohsXpwomSXSLA/WObd6mcDIhh8OGTxruA7SxabkZFxtkaJPDVoi
evrxSpBN6hP8uLj6jXghcxIbkAcWf9yL+ZpyXiZUMczzgU/lnVrVvuU81C+rm0aAqbGGrNPpTr/K
jIUh834yaR6Ndn3jK4Ll6XGv6Use0UamBNFrfYKBY8+lazrNuKTb0eA05ZqSsyjzdfXkJZheS8+1
AD3IUsldVATldoPt3oCcunRiS3uAGPXZ6UvGCxWUuE5dD+uU34c7aTavpJORirhABPG5wLUY/5/j
LtpxxU5kZp1HEAItd1Xx3pDoqnkVPSyIQFcSXdgyk7K8p0HVV5AoPHT+kJW8K24zHvvPI+Y2dFio
jYwjFYyEmG9V5ewZ1uQMUBeloi4wrmKa4GKdNUfZIsQPQpGmKYCXJbgHiHJZtpeyOsFZgHkebGM7
WR9h3oe2+iH074d7WnxgUdMt5EQjvR87biA81IIQkO3X/63SVVPJd07a1RLDDV0nL4wSpvN0trBS
u4qCel/W3mKgc1QvA9n51ZJxF39cZZpOsrofDvuS3O9+gn6nstVl5ptpjAZ1LwCaWH1AGhBRLQ1T
lgPCNPX014cVtWiWKLFYtloBa12JzMhA5K1mEiSf/eYHFRKzWDlqcccLxklw/grHTnj15l6rkWvV
coh/+YXB9jnHI9M2ssvujXxNbUtlHnGrMvAwJtuv5AaJpXC6f4W+e+AQPR0oWxBJf/HeZsMlmGva
XXgKxgkkIooPuQ3IkNHfC2di8HNNRV6xFpJdBeyU2CiQm6SVFECdWvuwGm3i3IhXAGu9V4yiZLHc
heRra6V35HelEN3oeep004VPA/OOGl1rdItf5lJ/oWGfb/WiVWNheL1Vq4OwSgXSONqMx50Y1+lf
V6cVKOsBniby0rCU8JcUufcU3RTuqd53OHq5zK7slXssZBkScAh91mxHYCokXUDwCtiUnQsW2wXm
DAn/m1sy30LYMOZcCV/AAZpgsQ3qzfOcPjWW2VHU861nfnkr+yxe71yHRIj/2Wgb1p0hchvTTSIB
UGcMAXU57DCDGehSAmZqSo+341N3FINCboKbyrJ72Ea+V+JQc/B+fRZlMMN1hPKyn0X/mXtnG7Ek
sao5CXYEr4brHq4RwStaMPYDdYFkHYs+bjr1c33Qgk5sYLmX6YgqI+8i/7y9rjj5UuErExUXzA3t
P60b9klfa2owGspNe1j8xeChB49uB5gsyPg9P2Yg+n9fmY6HlXjVlNkTlieXi4POV9v5KXtXLOoF
L0QMxNKISpG15R0lBc6LGbL4KKqE5xfuP0BpYLi2iWSXxnvNk+O+cL8kEUcSiQFBklX/1KnBp3BO
+TjncSr8Jtdt8ljLCxl410B8djWAvLizDy9y4Lg1kSArq4y7CEXyE4vkAXsLfTxhonT6Pfez3Rnc
5R1fd6K+v+yVhHYX+/orzfgrWxBe3iYf7cazrU+Sr0g2Y3rKn+US+nhN8hS1LJB6gNl2mQjukxhk
kVJmZEoxvQFSwXWgeV8hjP/mz/wgLry3SR6b1R+S7/SfVhEfIKHJwOfYHO18XpH8PXSyVsfoK9oz
0ujF4CZrhrs2N5oKQiMFb2OFlHCRCYEVThpwgf2SoJmHw2mbNTP0iq5uaZvnMQeN085zQ9dD2aOr
DrP/q6aFhS92O9OGyDzj+xYYkcAp77mviHw+gkxQcPkeal2QNbec5klqXhXstTYiOtjqx3BqJfJg
IUtfCfFm3SY95kgZR0Y38wh0sB3lU8zEV20SNcz56HvbEvBInizqQw3YzmW9Wgsg8hZYszB33r3H
5N1kMp/qZjNPNduMWW5MIPFv5/J/3lGl0y98nuLojXa0bg+rTulKaQRTse4uqsouxKfxeNYUBYi0
4gZRHId/0U3f5ZxOutIvZkDx13X13skweHNsXZZN29kKOhnKlbUqVqNTYYk67+DFH/1OHgYJV3RB
oStPlmF+7y5vC7Ox7h6dZD1N59YURUawbbUU6jS9CXD0ZcTRj0/cx8wk13MhPmukh5LwxxY7Shuq
gOp3HzdEE9k1pIzPho9FCZS0/LK4UvgHu0vwCF5ubtr1fAA90ZbYtg+ppM1Bdz2N7YWdqBfQN9MI
55EXJaBho+Cskc4pBj8K4JkLocMqGK8DkucTnG/SAQe3f5JU7DLpWi1jA6illrS9L0H+HTLQGIte
Ene9SF5mZiGQc3YkJK9mMnhmuitkpl5+/uSNY6lUP3AgqcDTY0YWv2Eskz5Bi4A05N158wF+hNkg
vyCSkufxl4p8AtmUec2SjmnvTJDawV9rRPsDYpHo9CVpQ5xRPHD1v7yTqkuR33N/wtabK3rxkLJc
PPxDYkIwPzI4TVFOsMDo5jq6igmjZkD7Fqw728WfIOVrKDoz8/POW6QtKTTRv4WgeG1VR1en3cOm
FVHon/PClg7QQCNWUmtmwkxn272c1cRZCAcIRVAuoJF0IbBN4Wh/nolmIv50XcBhkFYWJQUgDucs
re6M0YDCCIjmLtgTm9KUpp9r0TlcdEisa+6cgSdpro92bAzn2MGc9XLeEGiEpn1PdwCdCK9ciWYH
Tw9/iX1bZlFV9KmT8/y6f6lKcuH3Sr7wKkAra5J5DLLazSzA0g7QOWuJ8m5yXdSrZMYgsmTfjoa1
S/AU3lgyfYOvCY1+ZN/3KwzE6ML7sWaM1WjvgI+g2usM1MBT8lySl51+3RBqyVwdjRlt7UFiEKc7
rXulfLnipX3JiB0/MGfeVLtaPg7Ua1bpOU6iz3lrlhCynqNq4eoOPXEL4+JEYet4h3y2LL+owYLl
Mmr68PWwpLVoQgzPPoG53Y+Js4T3BbRukK2C7cqaVGTta0RQosEkp9sJ6eIWFtBKQ6x4Sobfv+Du
VHTCV0m640iKQGczaPzvAv/Za3uO2bZMHhO6uMR8vLCbxhwCqe9hW+m3IFrb9dBrOcrXFaZ8TxJz
IRCVJNN8U3FXSRdb+xW7SjmbIaqxA139tAgfbpK89LLgh3ZGuZG3w0mCTzMIgc68k4EgR6VTgKvY
DIKBIPQ0MysE3X71yhE351xnIbsGIT4oJTNDlIfL03TY/MypLkETezsGV+HEv51wYD3sHB+mOICO
PogGbJupH3nKroHH9nMvnQrrfPmXRL6A9BS6A4TOMLrk7AHyqiE2i4yLj9feJzlyG6UQSXYw/YaC
xFSVbd6Dw4xDE8vQArGfFv+nq1Wcl9v/DMl3jC2Wvhbm1QtV89ByXEcxSbP5/L3NXne9c5RFoV4S
gBreje0dvReuDtNa+ZEpQTWyCGrO+buBl1wKje38teDaX2+UMjd3/rjERvKu9pShQLmD9u/O0MoF
t30kKYeoXLvwCBTkxVBxTgr1yACRiR5yLFbH1Ms/b7CMLDUmFTYWA1CdWKXhsTWEifvvlLK7NFbe
ySjyYd8P1LKxW3u5jry16efAOujaKZv3CLSGv5gRp/RefrK/9fXHCQWRTDfHZI3pG2QO9Y5Qdjqq
E96VPa7jubzaFP2I9O4QTPa9Le/uQEnvweAh6nMj6549GRO31Q2N9gDrClsBojsk7It/GZcnvqNH
vsCrF3zjL7GFmCCCrRRC6t4ltAEOC5g/tMNKcYP2eMaQU/PLLrRwdK/qGjzos5agrRl7D9xLDaRz
69RwltEWPO09W8SjRavGvwIMGzLxqpzZ++WXXsW6nW8fVskkpzWCDpl062RhSsqIrLMZcWT2BNxm
3yNgvv1ateE/NBZeix2lPAzksZxS2EsEa16Hgq5mRhKfyu9SC714eb4aWqevVxEgO1Fm1kkzVS0i
L860PdMs3cQ+5F6QCergxqRjmPdoHJ70lyT8A7gm3iDc+hG8STQOMmi1tcMCAB2bef2skz4IwS7Z
RJRpoLxAHjqCIlEMZVRnaX9W2sN5HwmXMeSl7VdBYr3h+0Tn060BsH4Ga5pnKLmSH7WUzmXFDX1B
lgZpRUiYxM5Rkxln70/Cig2x511/xysV/77zi12G/ksdz9XtXTlpmbssdzT/KAKlz8H9o6IWo0uG
/jrKBR9Yv4Oaqr4rT6IbVr5pHYU/HOCH4m2/A5ifo90Rj2bZwOW8CiTE2XFxE2mf+P+00hQcYE9y
s448NyCJmin3d3uHKpSFJukxwnOWrKYB+TTK0k7O+RgCrkP7DsbYUdprFdXtHipRp2RwfJ25gCbP
bkiEtj8zhHBwA/fR8Dpjb5uhm9yqxPJQt2e8+6iEzRPzfW/uGMCzFUWMgGlFsoer/eicoP1XROk3
IlreVA95FXqnlKnMCw0aVHr40sswEjD117dguXU+iML+eSbQ9561p6EZJ/N1w/KtiI9MkbylKdc/
X/hU/i+I6Nbw56G1FsCJwoIE1DzDhyUd7kuVubBnXZ2ZJjKATu6S1qreUNUPm/cFFGlenwa1ANyS
edkmCl0V4D+ltIo4VWoU5TYnhmH+DDQGhBkD/siCfEioUXagquJVdqOuxA4zAWiaMhXnVbu6rYsx
Phx/H1K90RucLohQj69+rNoUAgJZlu55iUTzeff0OFSB8xEy8w7m79lbxqoOMsGCvJuyb/ur2km2
mhCAIN9nRkacTnqxPhLVaglLrEoEn5wtBx/+nEmnzXyUeOXxb+V5kYPnSEC6nBz9r/zlf7WgK2nz
NvZIKAomhmJ+cmy2OM6d3QXIDK+BcOykgBMNTSZh/Ug932B5hsNd9G4nIFypE5x1UZhB9R5hAWAk
GN7V++1XtGi/syIO7uzwmTM8QZuo0BEc3wK/qf9+3kKYHQ3BVEhqPV+MbARRWPkPeQM6zZG6rXFC
uc1UDxMdOSMBc56ixkjBSxwhKoVSm0r/hYU/DZoEUM1LFeKtpj83snw69r5Kz2WrmKbQ7gandunL
P6eSj2w5ctDgaXEkZJsyi++MdsVHRCgrdoHSkp3GZlxH2uNBrVqnqifRauQkJgzIuGf9/T60BKY3
DOI1fcB0X3fVlcuWqNE9b1iBgAZnXX90V1E09oRmBDu9J5183DBTy3vbmsB0Utfn5CtOD8D8hGMt
YDF/nqBrv/xqno0r0LqeBHLDrmzAuS5BxhcRM1DJDS2eXkY9Ra9QQi/MlRxU2cgPpfm3PL8iTjh2
Rzy88roiOmUVB99OvqUgSdexHnh1W/H62ozUMPD0vGguY/nRrF2S7OWDoEqDKW5EP7SkMSlP5dqK
/eN/NMZlaUody3X+8R+7oGciCzpvArL00q+MherGhrWScQO5avN05pjE++Bg4NKLMKH8uBA0xZcH
Zth6CEygheSjv1TPjWvhlhpxC7TbeLDatGugFjsm1nkBfC2md3Pla4vXpOvBqLk+UA+UtQk+pJBh
Ge5EM++wyumtIna3D9atfyQ82jqIQ1I3Ijn1cOREpqMO7QabhQZytFr28VMNJ/GPfwC/42vwlSqK
5G/Kxj8C+KZlLRwEFxpcWL1GzSaFmj3CDw3/b8jYJ/TnJvpN1f7hkVufM+YSApTBL26N7HRwIHUS
wVSdBif551nbj7PwZY62cDxvW+5sxNcgYYdw25cN7VOex68+WndkAO+qWfQbdgKIaLyzL7IT/rZK
af1lu+AKmPC653tGFcojD1ln8ey6mBpnLpdDLLre3e6npNNH66LDJjUrB3uyliPwPVEV9ptJOqE8
kwo0Cf+gNLU2+PFWuXkcEgOR02ry6dwAu3VQVJzvIAFNWtEdb1ophAEMrbwcfTAkToi6e0MpvTN7
sE+GLnr6gvyIF8zLtDFyQ9SXRipj5Q7+1ond5Mi5Fq16KnVkMCW4eY0tyIH7/hrxxtIFuSdF6SN0
z3HRj0J8xko7fovwlTkMCKaq8p+TNcDBhevoXgzLT9WfnCGk81p1SQHdLafnByCdQyZCB6W4bcl3
RfM3fX0vNHLSN9bPHDzvhFEl7xuG5PKe2VTyWFzuW9YWNzeK+cwXc/U7uNv9OYeaNthcKjwsJQYH
Uloys4SYSAqsrDnIqfEsDT8It1hLXWrNJ+gT2u8cPYHSwnslWpQOPGh/LPiv7XzARaKlzzs1bG5P
IuSwijcnTJqLiOpuDeyIFSfab6VYUsiyUxzlGR6ojAm6rLOiHeXjhwed3W/whTOXo7HuIAf4T5Ka
C8RNt5YQ1V4nV4KGv1rEGvlEnQGHcmlNyKZmfyw+T/SSGLGe/ZV1PNe0O4HlVa+rEJugs3QqQ4+/
2SQ59zDpOuxWZQiIyGaTsUvuIU4/pYeHiJpAOTEuhYPqBbhQHlA/ALUlzyHm8RyjVOTHoUyKwm8t
DcjUqQ8uTPVaUmrTihGMzpYwqzdGLImF8BCa9iw2ilnq0DyfD8ZytRDiNqKQJvnU7OVkIA0GjsDa
AHdpxKlDTdrnlMIc+UW6Fsn5zIg7wfKG53NxHmzZ0PrTF024RdleQzUlW4YoAms+29pHyh7Q3dv4
t7nPdjxmXVBcrZhDZSSRhWzT//AaMb9pep9BEClLpLKQx8Z9uZplbpNPTTubO0ElHf1nG8uzl4n2
+LTxP5eXBtUXHixZJwWpY9h3CLgCX+otrWD7yYG9R7VdOPKVtF3GyQtSoUTj5TDYAaJMQTbzXIll
ZI2ApIDajiTmLAZ6PXqiol8ToBy7hmvapGD49dKvJACuLBDkFygf13xl/rrfKCeu+dIbDKdILM07
pngzJAkfo08FwaQDWWERMprXU30ENgYaLmZw4egFyCnohpwgjNjWEFWc5s3CVQz5l98GmDoxZ0XT
7humFAO8pFfWHHkolVqMQPqnb9o3c82TKuyDcyjJODyr6HvJ7UrDZ3nKrtDxxTGAQF1xUhRbwx4g
Mao+UddzNvlb8DxLxafuTl/GJ97lSZBgaj8hmrDf5Fl2GNPJUnPH2ei5BgPnyLHrIJMgAPW3elgF
DEFWXQ323ZAGMaHjA08KRIZ5lb95+qVTcXCmblS3espXxZlo5dAcfbkbBiykV8Ywi2uL33JR0Kcj
MADvpVDCgrLIsL4NtsKAlw2v+2Ts/THuXMU646lJmJzKWk/HZLNi38KyLEJRsfOrg7fyiRsXTvWY
pJ7Amxdo18nM1GEnahKD5XOSSbhIpIbukqvvkmshZFZ5WEg0KXqAMq7llcMGgts3dnL9vGo7CQUC
IFaRBmcGCnd4npQ5Wfogt92Yz+X1L0TTd8l2QsiSIA0G/GSiH0nOQewEL15vd7gBALss6RTWsUDp
qKg1j7Ik53+baMecYxyecaAU77aSvMYDjeoioVJ5Zs6+LcDz5AGsbI2jDyI9wTSg13ulAvR7Pjpd
CICd9fyTfsQzggLlGMNreTJA+oC9KMrCBq9OMLMmOKYXJ/v8dAqj73W2gtqKyMkSNZgQjZWcjdCf
JjycSf5xg7WMdmN1OYnpKdNPNilTl6iqBFNlq1SVnIEkvarXhm95BbAiHPuC+PzyUhZaS7EnR8Zk
TsC0H//EePhZYJZ+0VnKRFfLX5rx7lyXyKHgzpwf3FzqmItQszicthNOD1CO+7urCO8HAJrvWPAb
gDm8Rt0I6jIWZQDnjXz7AtEmRfbsDea1cYf2sbmG2LJxezdnCJCW8oQgHJcLzX79ITEAoe2226ap
xNQTP0aCnNp5iNr+MKQ2LFvo/dwaq8UG4dLrDRB7X0mk1IMCLPu9/51qZQqngsEKRBqhI4OTfzk3
0E7dTToDZaem+m1WQRts4yRuGyYq2ak52SqNiAxHR1QQoXZrk8v/MMTSpdojtkMZgDektrJUaVmk
GwLmt7mcOxMyq/d1os6JlwgFYT4NTZ/Id0/NEbAOolMzvTnu9gU+TLu1S57iVKOCHfhAGKD5BFAt
AH7tXIgBjwO1yDrwxEtZn776bAZBbK/Tpb2DUvc1YfPcWHcAbAEw1E/uoWGfC6Oy11v1ED5dzseB
dj5k46ULumL0CBo1D4NW//aWe5mC3Lc5WQ6kbWaGb1MMG4oVuHT0/BGmG3OCd7hp7DOaUK/4Osos
QUqZ+3N4NNTdJXu/kq59CWGC8wlTCPDmMWJG+PjSzNvZJCXuO7tyz2T5FPKSlIXhYin5jAjJnT2y
FnDQwF6n2QkVVwEv/JRY3QBkba9CYn/S+F/lucsoxAcRf/sR1NMsnN2pcnvXDcX/G7MCHhkda0wW
mBKjqTq14RGtUh55vzZNAv/em4GWGgiduzuZiHGjmxissOTeMfl6tJdF/2WXrDUdx3XBusQ5GFrJ
ASdMxC8PhOlXaST+z2tKN8V6gj0C3miXXVPruktlPoxa+kKUHOTNoAC6Lvlcr9fvaH0wlSE26gY3
qCC7SMWxaUFWIZI0BSIUrvH095V8wpH5+CEGSZ1wcO+7ZY7iOWFApc3DoTxfzCVNgd26Lb3OYSr7
0/qv1vB9bOpke5lOfRklLj7gX2bsuKDaN4Ij5z+v/IDJz8v6swOraZaSmjB5hxPLLisH6SduwRh0
ztkMBlPRnDy181KTMY3/hXWzMM8Y+BCSCDZRlkiBdTbZmY7fHCL9ZcD42V7843mIh/TbpV5Y2CQ8
/kABeKEGGLixr8QBy6jolbh6jRY1fjsTWqBDs5KaISxsFGLEhr17K9hK7azeIFH32DMfCt6m30Z4
F+g3PuJ6UG7m4ZRSO9vkivs9BMOiZ5qp7v7LI1dr7xLsp2NwpZlqRHwx3F2nJq4/CwWGR6RW2tYm
5bpRiuVLiASS9OPA2bhfCafz19X4vPuLaENZzoWeyT/TxqLSXkMCrhS/Id8owCQXzol/CyPjyrjA
i2hh4M4A0GoYRR7LJBQBc81T5Z1dJw+MjO/Go3NObgbyoKF4yCEMOZOSIa7fuxN7MwZXlzkboG/q
RPgN2cAhloeZaTBlKPkJWvIRfYVCetlN0trj1NJ076A1RAni5bpwJO7g1mffDsOzF7GBMR9eV7LZ
1haPNob32kEIrlk84Dp+TDdOpdtZpHFhYZVXNgY8BM9NoJjZo51vv+ayUXBFRVXmIIGfhBBMBwQ3
d7n8GcvKCPZRNYRqdWwOO2AOjwnjeJce6NY39etWLV3id1CIh1tXznCEAXI6d3Lc3ZAy4E2HwdwV
5jvqFydFsCpK8PtO/woJLhV+Iw/kladwgza2nAymIhqUj1S5jmfoKcFJaEPD+QswY60uSWRMmcYH
lWEiw/QZaSkIwDzQe9bYFmL3itJ7YWBHTeJbyOsPV0BAk0H3J0h9gSc0j8UG7ZxQhoOCzYexxVdy
lNKyLB3updATvWhAjnAiRL91RTz9EdMQDJrRgFegZwtbM9iFUge3uXqwJVDWO9tMaBQ2Kc8vWehd
YI0vmLfZJTidGfCH5ofQUffoyjIU6/PT052f//Ua6ki2zA55PNtgEt6DEWknFTY91X/SeErRAr0y
I+T5Wy45HLiSs0DJAufvKBuGHnrdAwXoZajmhFekj6dRTaI7ViNHQO9tCE43rlH9skPrMuRsev5X
2nl0UYUDd4mceRSZ6tOVG6NZHAYgxIadsLDon7ph4vhji1LNvve9dDybGQX91KmxroHwDJJRb26b
WsDPYnZY0ErZroJxAYBlvrO1ySLUu5ROjmoUVI5S/1kxkdlwwaythq/NluoH9PObKxUYbDFsCu8E
dqzLIBNdS+LgQ5hzt4IxQ83wg3kBMcaKVQYHoWRy7MpZ6avuH0jmWzrsTBk+iWgBmir86nKW/cr1
lNpUJ9Uni1DbejBRS0Tv0xsC4BfJYMIUaeyvjeebzFSAG8z7xryd/dd4g1KdAkXqmF8t09lFlV7N
RASdB/WvZ1I995JYIOkg2lLjzx80rmsOcQFXF01SGFBK/hwCe2cxR2AHc4hTCWxDMsDoKpwvLmIz
fZDL4pxD59jC8j6o+19uUpWIztKO1nJV7ks1FKgntZLFGgNH2daNhDQKyD1L/5xhdhwj/hnJ6f4M
AD3TzOrsYt/aBV7yCFkhaxXXE+kssh318mDqDqyhZENBV15mtuKLCJADSE3PzJOu6Hn+NckWoO8X
ah42uLPR7TmMVBRCTI5BAJLl745ZAjCSQOxjZk9GWDX+fLlywsoZRgpEts7uWcF+PAxSydD56Urt
0k6WciG0sdVsf70KMH8N9c2D6XwYwiVfv6Kx8FKOG40xpWvzCCcZTyPDBFveMriU9FTEpKrZjsLn
v7qhrjnRHWidxp3hTtwW82UhIMbnbleJw/wZX7T+1xNgg9Hxuuf7nPkeTWwqFJhHlbleU26PYIow
OHXnQcIWC2oJnF/Jt0A5svVegIxAfPnAH73xMDFSMCo4Gu0F3Sjv+pmdbqmaim41Wn38e2ae1/m2
FbfPv00x7yD89rWBEoqeiL+yvb7BO9rgEMrhtxCIUEze8laGew4RRYVf9br8g8m84reNFeULVbWQ
etfuHdn+kM5FR5IJClqEDIcAgeHowU8NZAm0Ae90srkvgKnRBaGk7i8jcvVL8yEXlHhdUYuIS7iG
377pk3OBlpOcs/QN6Nkr96qyphpi+uV53qBIjY66nJSQlffeJs7A9huSQXdi7LcJbA7Wcytr77m8
4N0JNUryTVDR8tg3J7dFUIeJvQ4rPRJZJWoFSFW7+RryCyYt18bZYmWl6bNziBvLQGyja87H1KZ2
GEC8BVuVQOJtFM7xvb2Y5UO3Dgn0rvqw7KpP2TiOnToM2KND2J3ejwHdrjPwEQYb940t7rje/mGR
KhVBWHLuGItE35zDYi6pMOXVZOzR0ScO5JnA+kCpyh2RgMyB0+Th1d/THD81cf832WDOZg4SEoNR
7+DSM+OHoSqqtSjsrx5pSD+8ZBmTTZjhd+6+Ls73qTPkuCi8voW3cn8B+cNoZObOQxPd9NMyOgSW
DcD0wqfB/fWd5M3J91HGf1P06QlwWq2/Mg12KVABq0XHL0/J/ezVo45q2St7g6J2psdgFdJJj8xj
eat3cs4hEwVj9gzNYnXiueaSRlfduktsMH7lFPH9nSQug5l6cqCisSS0bHAJ4apWUCoj9CRi+Trz
oF+B1MzCC2IxFyDzWYQECTsNNZ5uyt6SmHsdcMXnaRge+BRkzNdunotb9phmdyLAkwofuvFIOUzM
URO8UDrz1qFaeVjOYJT5CsDFLRvgM1hYBAkPLvPKWsX2R3wnvtxYIR0XIOmG7xIBXUB4scfaxMLd
LuNN4cbN7KkTFqvLGc2lJR6sn3GX3IwL7g2JPW+W8UHzw3znzuoILyrP4PbzTT9vS1ej+EH1nFPL
dpmH9uVKY/a1ZblxeT4dEMCe4HsZ5h8HqMABqzkb8XychqA78PCpJ8sRnCKnCrrWEFaBH+Pg6X+L
FMusYBbAslaAMFgq1ZYKmO3IpZBxaUYXPMyfVtAaEg7Mk990Vsbowek8WEtFWo/Ia4BJKJFvgXxA
P46YUZgJrpo/f7xabRhVHKPjcXH0WMPuMPNs+MKvOWKZ1/s9GEeJZxtuRVBvsn82kOqonACMGxv1
RKezCyaxLZPp0T438nMjW7mOWG98VJLnMpdTY2zx0yTwvuo2qBWWxaRavZQDrMNLDYsrtHf5z/Bt
QlajnmKpuVesPuRzQqsdcjtpDsF84CoweiHL1wX6eaKWy7a2rwXX4O17uBGUqttino2awz4SF6Wv
sxHNUTlOqNPC/SOxuwLd7wSFCmwcsdp4Jd2lI/DFVJcopmmIxo05k50Vsd5QP+Cwf0i/tIN83cpK
mTsFCuJAj2VrFq/oS5/cckmGDENr+NDvCPmUx7CnywukJFaRqk5K7WyV906NNx8YeFWPTUwn3+s1
nNZFzc5550no09BFS0pjuK55A68sWQajgn4Fvk14y2P5yw6Y86ApgcKLDmE9LUO38+AlWLoixjTa
L3U50YyaQAwbFjXHciUuF60FYtnXaP1JxIub76PqHy/mfi6s0SDqw31Pq08ccEJzix32VUAieuYI
UjU/AD6ODUvzJh+dtgHwnWVXwwiUIiNvcAVZR7HcZYTw+7ck0f0+ykYRs8IyTleNrdNxH7/qFLL+
Wh8K7hpcFxUfPKIE6FR5u7cZmU894Ki/jSOWPDw2H0ydysnMPL7xiOfvJY2vu/5ucBDq+7LXTSw8
VQaj7buufAo1aOYcqotwsoHnYEW238dovqPNxUHrutp6pEdbh38F0y4/UcUFk3GH+anCKrNv2NEt
npNN990cb00N1nIxObpMulUN8zEAeKCmqDkpj1Df8c73OOi+ZvvNQ9zueoIpYIc0yRol6jqt9Ihm
Rs7W64f2+iwOvHza20vnN68CQSkQ7jQ1RipW+V31qI7SDqKskzm4Oy7jZKO7u5eMAC55BDP9luGv
Xd/SDOSjWzl6sciKToTHlGZT4tr2jP+KN0INlph9dpJFX57FTI+tjqzKKUc7UlBwqc6k023rDFrV
s6r0rq2+xsWb7LANvY2VxgtJfkb4aIOuzpaIY1NA+8YdeEzNRybHQjalgKa5U6HwPFy+PWym6C7N
eVBgCF8w1oBzXY3gBGUBrURygsIwzgNobRqiqXnIY0g8pzIsYSMtJTm9vpWvGw7XFhBI0lw+wWzS
vgRBviGkiwqvle54dlgjdUIA0FxYx1Cuxzpn1hbvUSgW2ihnLMjSdNl90L8FVEpE/NMwJKxwlTZV
gTGmFfJtVtbQqX7/5FhGfrdG3I0OvAGR9lerqk7CC8/R9mImvovu3b/mKe/vAW9Ws/9dDNPdUa1S
bW6SR/AFYqnkiIv2NQVoyzKpufZk4WS9jmMTkeR3UQ2lia3nh6snibEgb7GMFtkOZPLEw83/N+tj
kSG83fqbJNpyKZuX40r9DRiW2/yrkhRUk8GFS0+p/hnPYbjbVuESw2T4HhT0HRQRFoGXaghUvCmj
XO19IMenwD17nwLevaSEIwPTGxH3+E+DRixoPVyhS4J62cDBYdHeLYNGpDzxUxudDdM7p46cKIwa
GIiKdrfHEsYXtJTQvZ56/qP/MM9LrPuDMdDQ8X9sfv+dvHdget7Mt2BeVKuaxZRrAiLzO7bs5frH
WzX5A8q/iRz31ORcI11qJwgwo8K5qwAIetubjFKbQnKH4Kwt6tal3U0oyCc8EVoMP7TEFlPvRqYn
gwLn67GJEgf3bxq87gOkrh5vo8hTw4jCQQv2f2H0JAysz0fElb1uNUGeKVunjWpNDnIuPan5jf+w
h36VIGr8xqpvAgh5Qjq5HI17yza/s1pkzHOEnl0doxiYZAyBEBFhe4fihf2O4hEPAOdzd/rkT+7+
pM2mPU27P1fzeole4e98yHPWCM3Vqfo7BjL+YrX1Q3W0oTPW2j0rNjtLitEen02rXfzPxYG+4CsY
ayXnOb9PDiKSeeQzeIpUXK5yReLgv+DTS/0o2bl3o8NtqhePZ/s7We2/+ypDpDJvHhyI93k/hFdk
gPiG7AMTGy4vou0frUt+GWfzAS6oCuxz3g1XQ580fhq6A9n7OkcXgIFAz4/+RWTL0J2u0elPUGcp
Wpl0SVPI3XGy+m175dZ2m2x2JAAZ0gJTqbsHhLMGnlYK1xWeIJJNjW14DacP4yHL+yd6lt54r19b
w9SjrpaWyK4v5JZUuL3u2tvXndxHzGKb2sOGeSDNM4INInaZQhDjqrZIJ/E9xh/IHYp/pgnjTP9Z
HcSyM52sPH8WfzsrlJigWzbBespj5ptUtPpn4nsYFuKdF0TgIQzOMTiJnpJtiyPjnI33/Hosex2D
iIW1NenbJ6tB8kSIzzbWxUCnH59J9ReZLMdERpQMpASRVOzXI0Hrn31KsCtMgfHMq0mHa8VOIM86
XNgOD0WSCo8fklBi1vmGM32hgEbaSngk+F7tkiEuE5DUKlu6KeZCAo6bzxvKD0H4uChU2t8gKgjr
wCL0C+q3JQzpR8xdAYd8b6IFVtmXMk8UzaJMzX5xcdL/rvJ1VzSEZgeoPxdoW4jiQ6e79Q/ROj+O
wp9XJzqNgIOV6+GQXZ0/4dN3W90/hkhIou/5KAZTG3uzmJ4MtSVB1HWiJU8uNCQPF/f2e4dq+Of8
5PCJXQprhJahOtBYNv9maZi7wmZJ7/V4lcCCWAMieOcFjEp22RxIRoDUefomQwaclXksXwIvVP2w
WLONo6VxNTbw1Ae/Iv6WT5HgoeA1BEGuYz8YKvFpxqfAj2j7Yg6gyS3YedCCT6MY6rUG4JH0J26T
0Va930NiO3XvcOvfoQagjvr+bWCguvpHxnGdP7gaNftsx69Jpw+eeV4wLHkBSOSNap7HTocQPa+t
v9IoaJIZ/JecPMdJV/4V0Y4jWsT/hXKiCHecS7uRiE25S/kRmZ2fA3gLHrQjl7+x2ScTp5gAQkNy
ABWzesytN4xYfe3E/rS+fw33sx5GNxdqOqqBvW49Vs1P/+yeadUxJ/H3wqCsc2XLtal7UPf1DOUT
EzcspCmlApsqhm7qbzZi29BYG+WSPI0aItewCFSRJ7vBqlTYA66SPmBYWFGLxo87xDRI+24I/Xfb
k/oNfKJtu/epRaqCzgRBbjDWV2n8P68sjIfXI3KgUJdnuKczUacGzUV0A9CIwapSqyiLClZ+9MlF
krg4ShAFXjOOLd+GxBBNEx9fAgjlIc9JA7sVDZnzuinAnxKvjP4mFSksTumWe1AA5LAgXcHfctPj
Tt4QfdTDAzuF6ltxNHj3vR00NG8xwJ2LRq8hGxC8M35wBK6vG9bS2CuF04ovG5hIH4+dTPJNqtE6
jkeG8MCvRGCMb4I2SwHkbEQLLK1nrwWmnOdkt0knGiH+BQjXC62+hZRCrtjf+H9eD+2l0odj/tpD
65x25lTwP1tpwY9+4wLopB01Re1ycceiRe9fptKZiz1vBd6Jw74B/uMtM2KXma4UgBOimxhNUuSC
ZTuI1utlAUz0QtUnKdKcC3GBqClZjFISRi8zNJfiY99ckZ7El/OJawZaTl3HgXAmRjAcKgFYVoiu
XBwbv2luLSeX77MpHD763cBB4w3rbUQGnQzpcDCcO1ylAFCv+wll41bVfGRQGFqBWwWkYs8selZm
BUjqqrrVPSnA5tek/OGfaaPxUUFArdVstQt2sMirVnTkugg3s5Hv+0DPGLO5AjdvDDSdEBC7QbXn
DwxtdxjGs0CCKgBgufcL12LRrEi4vSmeLBJlh1/YOMo8WhNVbYDrUgCXknZ/8VxHWYM6ZUzRutEW
NoA0ZFOIL5qeMvCN+4zzJQoghKdr0eUuSko5dy6L5M63IxuB/QcnCpPySDFilnPFRKgkA/b9k0TU
6232HdEq52y36laTCIaTf0HXrr3tI2GRuRs//AeIx9pOnXrK3BYcaln6azT33YzwDcM1xFGtjH59
lS17Nz17QZV9yskXEorllTf3hEpLSHP7gsryBzRhPjPO21RgC7NhGKzjz7OBDNbJWugtB+SaZjLv
bc+CoUZoXS1Ql8a7FI6EaztBQMQeTlI1hf3+xdeRD1b4Q/IfqfZfyXUiEFzsvrfiA1uEuQmIrs2K
fxtWpD8jgN9bqXrvwkMiXFNwYcbzhrcvpsY9qIv+4vP+JiWp7zd3zk/MmlyYjNWBDHZoMMEkr2yW
GCP8N9VUujAZwlmbbZsR4Ny8B5qnhpisdLPACtG6djnDCG3JCTGZ23JIa4/meOYV1VqYMO/KdPMX
zMo3fESUF/+SqBT8JQITT4XFEmrwiYpqN++QzYTpop8L+RIjvHTCA2vW+mzL2IHbxSvhxpbF2pFA
qM/tUqeKj4RXUuCFJS8nNp/wEeDrCyEXQzb3iCAopbt5yOIlRhpAl+hxs5NUdrmGjpHXUvqMtXgR
7sHedo+qDopUT5xRYULHnmy+WV8h6xGMvwwf1iHaVsq5pCUyhotqab1+IQOf9GMaltJG96zeLg0v
sXIwZ70okZaRvdULKsraE/06ZTFHwj9uZ3nDVAWWTv3lI8sSdi4mlP0OulXJaOqHFyVxEGSe0clr
pVZY+lnIufUweMPCQ+q8opuCMgv8anu13QtXPhDLFopdJ88pX4PBxGxx0E8dO1bCOljLDHWC1bz5
ys4wpvGlfwfLofUkvAV7ykz0tuh64cWWkvN8ynntLjglpn/Ox5syR1kF2msFREP98y0XVcuoxV8O
0fD50EwZj4BzPzo8WKNcLNbkBcSNxv5AFxIJ6hQbE1z1wmMtLWKQy30jd2M6lvVmnZBWbl/W1I9p
+pgoaASt3IIZjjPwSQ6pI9TNHNQPH1RjyDONi+FYG+YRZtKvxkszdkYAtP8L9lckiZdW6X/GPBsR
BPNtI1/EKrkLm9arX5x9vmPTezSJ9BPHZsCRzamAxV+m0RfYl+rl9rBeNDpeDZjgp8O2dOElPVhv
26I8eZASVYK4JJEqncU4nL2WCfdkcslqK0n5Aae9s/5DP/bck0pGi6kxxCkgnVZXiUk+4tLMz5cM
rBmZ1VEm+Ge45pHwNAwFAsYHpMDtihQvgC0dcg5Cih7L/lkYqCWfg1I0fkGeZxqzldvj+GiZrrq4
ng2TWrBOOl8moaF7DN8UMhJqYebnF2LQ6BFnFCNizztC8RzoX+1gj74gtsrg1ljvtvRpsgZGfZu7
MEs6BEu4N8GR6u2NLU4Y1BITvENATHp/DaC9dMG8vo/v5cwm4AmtzwPhFFlV/5VyF4F8TcP2BlUU
dBHkNDoEa6dr+2k1XrSPeJUVlPVqxaZKWbPcSGb9itMxkmVhgndL1cVt3u61bvA4Hg2oBmrDCE2V
Q1d3Mhw9J7bTW8OJ14mxMc5eQfy83xhM1djvVFo8+/zBkecPqRRcZvL5BOFEg5oNnCdysvQzcYho
/V50HG/WBJrfK6obaYwp80u0EVrCuWBwYxE4k7iRBGY6oyuqBAFXsrHKrQp/kfoyW1dKUplOd5AB
rLDSyDfGzVu64B7ybqNPhnu60fkvGDq2qEfiiFhC/prRmCidoNBoCrk3XyW6OKwLi/XOh4qbJpve
mmaEQgP5pT9NHOAY5W1Uqb1ZxsF8Y4oP5Yt5U8d9Dk5mNolC1jNyFL9s1EZvupa6/zffPs+REgCz
VfxLqRHN7OYwskroKVez6+JynThGbZ24miiBIvWDhQ+f/cHS+nF11B35XgcN3GwkYexeDE5kEaIi
CR8IfSy0txsQqEdCqgVOV4yOciWu3i3ie8e2PKHJXE9BkDBXfA6suLGWEjrAJRfyubdkURwyiiT6
p8mYa3QF4yl9aYb4SQAuZ/EJDRJaUgvcWy5vro4glEaHHTE35MRbHnDh9HI/fpX/vhnj2Y5jm40R
avNo6Wpna3+VKo3fH4KMoaO83VVflLsaWPpMffxu/nYX1nBMA52mLF8BKtIz3q/qabRM0y+rCNl5
6v16RxIvQKy2Ntg8Pwn/o8MkJaR6b7aW778hUoVT7RNkUdcsvMhhOSkHdYyl75wTClZs98FXppZJ
B5N10auEEQeZVXeLG7Vf/8gfDIsZyPaoxtTA4bOVKrnQebopF7kUtVODpbrMk4QnyAWJPydcSeev
EGdmYaPnLZ7zoeR8ap8O9T3AQHZUfjn6TyFLo+BXENTzwC6/OxKbVvaFACS9inYPwjGBMPhkpeKw
wtvDoBjjSDwJzVFMtS/rNsp5MwTb3qhPtGe6DneF6koOBYWCS/5+iRRakooH2FIJ7QrwTdGRno0r
mCHlY4xO2CqidVQASgYBkNj8wpZi7rBae/eRdhAoFHZX5mDqR6j0/Lg0pHHz1ZKJf75hmyX2LLbE
DlTBnZxXPLAeEEKDcZz9oTZRTT2de9coooq2hnhrm+iwq+wY3GfQqAyCv11QTHUCI2rFXM/S5J/C
PiaQrG+0g0xFtEjqS7nCVHm0nz5g4MkQf7VAM3v4iIr0nZQyhISGk97ejyrPxotNhlY4jMGEEEhd
FANLnhML+P2xezZJMJlJh711x+wiYxu5opYJQLQlmNU2/BZOjxanPkc5+S+SbivpEeaA7NRheHac
ofQH2B0IEkLEipMzZ6v3AO5/ZiXdYSenY6AyOcQyPdkWtXtG2wnU5jAgPx8p1pDxtuojGjaEu8sc
y1Ch0Sfs4MGOotRqbc+5h2yseB5wlxg5JSEtZ/FwV0YSyOt59v5ZWwuPgixOJpjEJnhpVrmr2E+6
0NfkpPzveSwR95A/m7/BGWQxgUT5xVdhawn5XEi3AAm85DaKHvE/sksUBo/AAEIAL9g1ZFGbpdUh
aJP1VOYJHDe+lsx1QpgtM0upmhmbMSyL0TvOvzmeJ5hT6ngWmqeNqjaHbsmQZGmtemyyg8u/DLCb
Trx3qJa4pTcdSw9q6nLh/atawM8ja4Z7M6Dml5sGWxLe0YYfr0vTPUSN/8Io5NKXyHkxa4DqnGMc
WpbwE/iq+eEDeSOf5aVbJeUxoSDYkRZTKVQxEUDUMOi56qZpppLASBhYIyUONVzvB871T/AqcgUp
aKZ0HAGuMmv2PP+4ILMQmb3vB4+IwMO8Vg+reKcqk+C8xohhMaSZlBf9IuFuv3afkoPa7U7m9Axp
ZRuOfmcJAlfeanobsUOxKrtOlltxBK1VZR/ueiCQTWsjbBOeG+1/+HE+HDlL1iRXG8xjreswv3Hg
wnmZPm7j3N29Y50kp+jvBfK169G7YefEsc+Mtlyxx4lpMLoGg+wxTigC/8zDGEyOOUm79tu0GT3k
sJHJ8nF5WKz5/KzFu0C2lnN4Fe0u+6PkQo2s2vwi4+upFspVhYColX6pOlOX6XQeD3u9ONBVQlYn
rjLlDS3+Ri/2ZtVorsiSptzL3NZlgg2aBSoYZaVk8dxxpZUuUbjxhauBU8OS2sG/6wZ/AYm87ome
R1opuPMGLiUhuB2wdkA6psCwoD7boPCMm+6v4gNty4HClKwKxTYiYHHXmbMCyLqlweQwwBNfFvG/
wdKNwc/toVKLbyE932pgzX2/4SrxoFNnRnxRe7Xjh/2MRonBl9CXKRne2n86i0ER/GHEHnYpKnYf
nB8fBJzYLJOa13gdvD1qtVLKEX8CIOokTyPkPmczQCd9lKwNfkJJGY8BEKORO6wRVWE1SsYqK8vU
locpbnwOGtQMCWxe0k4kqZkuXyYSpaFcJPbTjtSYC088AP0XOkP5sNroPjYCqEoEGHjRwYr4utke
fPuaS/GridMqU3Yf5X0DRC6AaUV6lw7cnq47MCMICje7SR7aoidhqZMTqQ0iMwt/saEFIKA63Jpm
UFmb+/1mK6JHY32Ojyy+4A7flISKf41ypX8w6mXxVlPVAc8S60nQ0kLSY7GL8nv/NCUqXs9hnHdl
lhpEGVmPPQ0jQw29d4cJtiF3TWKXDjOPO7a/D5eHGeXeBc3QUMLKpimJJcAx0Ke/V2EdyfCf/AXK
8cUa/ugjM7RFEXwp4huSE4EfS0oFWAEJXyMmjRqt9DWCs6ZP6EIGh5kKy/MUomdNqFJD6uUjWfu8
DxFrC0/Ppn7sXdecnPMq9MN1H4gaRrAsyGO5i68H0Qd6c9cw2n0wlv8qNxELlBGawN335UJRg2gQ
/O5hJZiiIe8XXHukE0yU727Jz5T1DkI17g79H3FV7Ump45+m4ba5JdENddcHtD7HQVB8aIUHYwwQ
bK96M+iZkQw6aaWGBZ806ltX8EfzrnlxDYEoBPwhUDrsvvrcz+FfxKhnAdFCo2mIohzMyo0f0UvQ
Nd15J3cSJJq1Yp2H1pY7ZodpqQNnrHyMvQ0LFjKZlLIdvj5JE5rDbXKmh0NsnNysiMV1vqvKNOyp
TQuZue3r5JpDwSHiZIYHpWYL2WsdQ51y4yYVX3ZU5CPv7PWOl2ON65wI7fg8Z7Z2imm2HI7ASt7q
p3rCUongo1dvuC3kYrXikGNL8M/SX4Sjy+yg+cpLJz4624wcSNmgSetyx1XPCjJCwEH1wcY+dVY1
cCaO637gYd6OGaLMxHEUggDqnPW3mKKZ359mkTnk6h8SlqSo1gcS4gXtLudw6I5S7DKkrXHJ4b5l
6qnefiTog5AidD3g90D2JLvmT1pboGbhp9wLsJuX3cD1inSBlFuUnXtkmdMxMEV+buTZaVLNhbge
hPcJ1vitny1KlrnJsk/9IBUB2Vt03gj5gF3EJJaq80MeZxz/eu9f41cHdomC6ZBa5JfxOeGF0/oS
4sTmnQLW09ZfMIfnITpB3BH/wbxEFZjeN5n9/jHiyGzq03bYxqW3ihV/oUwone0eVqB1RjeDiLhT
kpKuVQZiyHWtQH8Ql3xVGBzUnJmNd22HRWDEMizJQdNvoKyUKlXiaTMb8HgGuYEap9b4q+SdQ+tj
+lA3jOVk5hRrc6VKk9DYvKdkaPTRmNjKVQfeJl8Y7z/YIe+NLwAn6rvHvVa9+IcMihU6YwtZraxO
KvqQtpLw4XKHIwX3b4Iwu5iMYmRX9Gk7KQEQb5DRHSfPLEOQgPxopzQkuoU1wZw6YP7rJYLXPJaY
eqMEV+pnw2Afc4erxXk9bIuHlR/zUuVJiulAadYZYfouErIuNU6XxNDDdi8Z/L0Qg9skiv1yl7us
yhuW0MiwLfl6d9cOHqv2s23UQsEyZL90jEV/t8OyowBSh2OuHZhIPENY+HP3ZL11CYJOFYXAXr/w
fcVBADHnOL/W8VY3kgIblKz6DLhGPBdA17vrAawyqtt9QxUG9ciQZsm/HPkY+5X3BaRoT+k3RFLK
cDSJJ69D0/L4deK0mKLR9itzj9ERXt452IEHx5t8t3tBVBLPvPmRiCC0SJZpdWC/JcqdAE/XZKA2
9dCvfUTC28FMVmKP2nshB1ixaa35pKvr6AQFySfiB6QSG4saV/Xl/Z5NSCFEIBiLG1480902M0M6
NOdDR4pdN+acJfurbmrNlBg9YQU/e83LAD9aR9SKdrOUwl+NSkhi4vYDQSuVp8sMyMNxT9VOaToU
fW+QT8cV41lXQfKGvLkFRUFxooQXfu4y3kUBEcJ+vXJfCmmNAZX3dPZ1u9rr9GjVZQSIn3n18zr5
BZyVV9vE5GnN0nybwi4Wi0U5bqb/Jq3BVs6khgfMXx+mIOS3i4MVLlvoNwcv7yW98khOlVM5urr/
OPyq+QR+ss85wEV1fAn6UTlPNRYWmQi2x9nj/lhx9oY3xliUNBDoSzlE+y+9kv0DRqx1v0oiA4Q8
iJncgvMljTt3EPl0fiA78D2I6VFpJ5FywjjYkguy/IUBTxx0dUMdqmyPi60+YDsobCjgU6ZdLFdm
LJdwOw2+3wIxzFW6+4pM4S1gtjU86mBcRpQdTav4NF1lRi126emJcF1iXUlW2xXKLCSjH63YplsH
KkZWGcUk5MDq9YkaiW3hPd/JCYbeeaxHoEhh00+26fT7ew6qeosMGVwIVWJf1KsAbqnlcxeFDxl/
OxkfPQ457nvj/eLxOocBUx/8107jFbe0jACV69QjahFb61wZp7dSeigCGIGOJqQQTe09AWrUwCfA
aQXGqNWBlbza07qZ4pxS0g/aZWqiwdtp0coJMWmiMFYAX3c31QTrSjO2ZG2YaDdfgpp4P4tXklGA
aA7UXfGwCjKzgcrMQrnhxXeYEl9PQzznw4H4jBdm5prLFbcvTZWjUZ3f3Vu4XH3PargAqKOJm8dj
XhW4VPQIpTGTxOEF6sAFCJTRL01G7FS1w4kyaXHQPpUY/U1go/++k5rtGtnEClXNCCjJXK7uy1F2
C90aAisj/b4wcS0XZp/Fu5/hWGTDG0cbasfmtlofy2rLbiBvPK74Akdy+Rb9EWdoQlStjJ37W+Yg
IugKkidtAjEfiyw4RdU241gca5KPj6x8j9zTODSDA9l9EFNcxU82yHHrJpzbMwR1xwRZWotHZJiR
2egNtZLkyCdHNUVRP9RbTBAs4Yoasn3HeGLBfO/JWPR6Ur2rP5cxnLZYpxh0VHqV4nGnOXRlO5/t
bqsPjucSPSSQ6JD2sf8mrcipxSS+Uisi02YJFUplpbP8YTSnDEPSNx8rY+COFo5rRskMHvClDIgO
ChManp1Zu+DTbK46EtopYwYOyPAdVCY6uflZjQ5m0er9FV8MTk67nnQwYO+RhM7qnz6y46n53bRD
aPRVuqGL51qQD5PS603pDnDiftgtkNFSyUHXdd2URybI9BF3Ef57aGgqifUPlYsNZk+YXCnD+T9F
kcNh50p943t83cDUThcT5mrYMf94E49cPWEAftYqI5bqg/VopXcJzlyu+9lji6SWMCodSvycgNte
6Ac4YkexXUnY9gsIv9pvxAW1M8gTAapkBIowt8vCrKN8rOYTrd+fECT1asrpgareYJeVa0UxKeKH
owp3yumzrVZvE11M8qwGf74tBvkQ4oSIPh3gXnSUdM+PRceUCvZspMi7Fud4XSdBQzpqoKOeIyXj
ThP0NaaHq2aSR30P7k9fbVlecHfE+3b78lL5QRv42n12VMk53vPrp6iRe4OZMsGa1FIo8YkKi9D+
qVQVa8DV8OzR59NdxRZRBtp9/wkDTJu7vMO019mc29Ju/UBZYk86yOcYlXz7eRwDe9L7YBihASeJ
T0MUWUQBNtH0lH+CdkIidqerDD8JW1HO3lpsoSJrqlIuD7VhCgrqdDFKk1OzSKs165zcnMvUk/w1
Pck5SYyVl0H8hTu7DzHWV2yUWnjjzpdePO9h4XS76mzqksOh3y/y9/rL/yrEAQOrgVw0WESpVsqt
dfg8MdW2GAj501gNUClcFRnU/u3UQhbkUDRSbG0N+cU0h+Nh0JV7XRzMQx70QfGQErd28aiJCRAL
whnQOZRGnxgHo5RzrkhImK5yM5Ib8uTiGKPWApORb/NbYkIda0ijTLkaMpj+EOWuG+svPyUlq7Wx
O68NRlsgbii7+jkmh9jgxNxRZgGPYSu6eXAzgAIJd4QFRb0gc0jM06387ZLfilrv/BpnM3vVK4eU
CuO1hWBY/Z2XYTM8cQpb/khtERvZ4P7ktDoFAjdE2n8ByWyc3IEMRnb6DhNIghj8J6AdIkoIqTjb
DNJs/h/7a4qtu4WenIZfhSuKen6qSmXmeIfhXVPPsBWRS89F7VLHtq8+WnL1PSXWyS2Esrbki7Iu
Lyn7odhHxy/WG3pOASm9VOdXLhW549c0oFBqPvoW9OjhO3Hk93m1H1Rf+/ZxmJz8HGCrKRNyim1O
OxwEzuQhzNeAdV6QUsP6I4gF75pljxmOnbspoAVvL70+Qv2eYcR7E90dPF7hyPwRqQWgJLywELXh
FJclNz3I2GC08WsUyDpre5roIvn+CpFtLQRV+tK7EZQLRywl9r8vS79Vwyo6OGslyFY67F8MnMFG
mSnl9Cpeh8W58y4PY8xWniqVi04Klix4+4DorCLLqxeNapsm4zPeAEobt84lGo9oQ5FZyWAgcmRU
ObCtjcD4mmcpz2gF0M8ReA+vMGnSKwFXC9MPXm+D+4J4qbPSfZAa3L5jN4PuMi4DATu8q9G0oC/A
BtYa7xnOJ0gh49Yr4UoHeWLeIBUqbQppV9vPpae7L/i96zF6KXLcIo0G8DmLiG7DTETeSJwoMAKI
A4Csn6EGAjbobvGGM8cZaWvVdsyO+3FOAmbFxXo6acmcaYSotLwLrZQlPZCN1VlTRFnASXoq9uQy
eh9MijmNsUYBgiaoyMcJmXBta4PJlMsPTvUT+7qrEJVGMVDWBpaQOfr5Pq5ftOqaMgRBjSXYootu
Uvf9cVrM/w+V8LrYDOOYUkto4+cvHmbEf7/NLWm88q1cOZH+cAP/d6h46lrG7aNEFs0M9DqIQr9O
TSkmwGFELjpa9ybpy2x5rBkgaU2ROjVhgTGnTOlvlYQVcjQGOSW79Auok5LD/V29wycPIT9KASGl
+/4qBEVjazYWHPJICoOVBoL/DHzNMfTutx2f6n1Bk2Yi5Nx9Jc/R8od+Klo7guMXdFZ79tS+G0Wc
9cuukY5XwZHJERUzG4ePWgxtEoHjcFcZ56pLODw0vZEF75KhNxfBjTHWFBBgIUNlF3foTsjkErmw
PTYM+dO1pQEm0PncceienJZgbYnZE1mXXXJxgLCiYtM82guPMtqV5YUOTlXXR1cJHRD9hQKzNGyC
OUA4KcpT/s3XOSlqNt8w+lHAaF/v9E5UBIt7Eq95PWTj9+79yqS2HromNrXlpf7SUEpt3jcvADXm
wmA1/FIhtzeVOx8FpthvGcqGozw8S4chytWrN3zMvKh49uV8+scQJN1UU1+iBF3k9vp5u7w42ths
pKIbXqKuVMoT2Mf8nC9D7/yIzCPTzFtTvGqI0TNPMEXyKLFt6LIYFV6PQRKl38GAVVwGFG54XFkN
oMxBuNRcwuZc+RdMZJumWiRTI7WjbizaezwjaknPi2hH1IKD2e+oq+t3DpG2fmy/IL8a4EdVUX9A
zJnigjuIGNTxhGrRSNc3FPteDB2aejaEcPHmZeDkflyecs9t0cfiL6w+3P3iKIv8JuptObbm284s
4pPWcpq549gyfS8si0g5x48SDIGRKuzTkelsHP6iD/q+wUuqVHDoLrOdieiHr5v1xX0h0TLFw+7l
86f4K+/0vU9Uow6n3BcYR7Iv6Cf83EwFEWVy6K8BTc3qv1s5rXFINaZQ+SyCm4QzWpOTDydefseV
PSyaN1nFaykg/n+37Jm4iRZgxej/wVCCnYrb9XOfOyL0y6m6YjNYDUCkgw4XWa3qJHeOoC49mKwN
NaU+7+8156YEds3LRKeY1L80vI5uBhPV6OBOLjYsnzD3COO0KHDEK82xhAeXEwt40Xq57Uea8ius
lxIypgOGS/MfAMCSUB0InUWYdAFHKyVIL/r6FOpXojalg3r3OcmGcHG7tUD7PgTIX5S7dfblf4Vi
uOm1hE/lkQT5HMBXq+GjTEnjeVQj86Y/oWmcbLiXZz3VakxXVzLLOTy8qnvB26zd0zj/GvT69+vp
hdN4u0J5kk42HyIYRmqaM0QTB0J6mFdPkFOhuSzrRtreA/zaERuw17THCMPgDkOAu1HlVm9B1brg
7UIOk+3I5j60rJprGgE8ac+W7FHvSH8QEzwDDYAPI8DvfAJmJIKozAy+ZTgsuqugk6ZanusIWiIH
kih8ZMzKKaHq7bGQ2yEERsnTaNgKEjcf5j5Pc/m/Qslgxo2AhO2v+sgBnNTsim7OrRyMeAz+fyiZ
VE5GKva5BqtEuwLW2SvwtsszEmGSvH4F1Dd7ecmDnbzAPyivo7kSAi5tQO5EaPdfRJuqasBZ7oVx
6W0mrkhf+sWkbg9EhbqPkTbdOA4i8I3fnHI22NdJHNLDPD3TtQz5s0RiwZud24LWT/2OiZsvdgTK
gLLYFXvR9mrMR0oaqHGGAVYcPVECzXBI0wpiasxi0G7Usj7SKrvP2rj8J5uO4qCTnG11cfNFyxeM
Amp/DfoAhpn5W44EQtZ4uRvwtvzSgy1iqDx6srw/ADwM2OsVVSOoZDrXZnlmSAET7Mc9VrleB3mJ
u3weKqVf/ddzo9VY0SFvlWvTvkweCUCIvxk+UvQ/5EVjagnLckIbsGO4h3crl/ZO8zWElbLfqjIM
Ni5tquVrheBde3L2ERL/JFBGeolFIjSQkNvizQLEDYZAtihNMvmdAtOR8Tbzgzy///4sOFXmtX+n
qwDBhV7l3L8yXpbVMR9PH+rul4YFsiG+K8WGXjG42gz9akd3zxhoQ0QIJNOJ5jFQ6f1zOUHhCtQc
/fmL+mDNFXBHb0sQCc9uHYAqIPHz3CS3sqKgR70JiuJvKNqCUlTXyXVo0WzvblfX0Y5Pd0GR630M
UIyTB6ma9nK5dbOz+JrC6zPkUZogVZ8QzQ7uGkweb8ODYrJz1FKXvD8HAdkap2VDUE9mvzWU3BWL
antgh4ZGBJGlOOdZVYTOUyF7ssToByCvNFd9TXeODT4undyo+be1oLmous8OOzugpDfUqxHgdFZA
yJYZefBgpH+XHUWyRcUu42Vn3NF7SGvcBxx8BEcLZ2w8Yg3K276vmzEABhbg97/LhzwRfq+z+v9G
8f7FpB5TckYhcU0YNCwclgNdSjI13jZ9w53yBH9R0nCECUQzkXwQitKeTYU/3IiilvLhM/9hU7UN
HGY9VvEkdilgwx+qKv01z7o3QJk+QB5z4lVbbmX4gPMmsuaQAHskCIie9qhHswK+Y9P7wF6Ka6Rr
PsWeHjZpR9QKHbUZrz0YQfFuEajQChPx8Wbi0Mg5rkuF/6yQEVWoX0/7xe2uXpsVQsTe0arG7UJa
/ASqTqVvFvZgA7F5YFylXzWBemR3Dqbr5ayGowI1u0zLX0wA71Vns6lyrP7+Ya0X8tfGZGjJD9Ld
Mnh+oDaen8Ws1ou/cmm5cixJBxmnZ3MxyvoA3CxxJ3rxL2jsom3a9upp3f6JBUxMarexpyaYIhZZ
F7zJBTjndA6iG26SGX3x/njjJFgYuQTBusu1pGDHdiw0fN3TIWjc4a4yDPYLsbfcVUVgy2omhPgO
Y9OD53X+c/4ROveYj7mOncSEYN7uAREw1fzzwG0J8SaOldO35cViApP7UoXXBsNk3NjFsiTdOKdr
z+DnacvUwXOjffbk/SnNDovMs3oDaGjxcv3nxOgBEU1WGE2wgZ3fF4kyfabg7NUpjYlje7i75haN
2TnIGcR/tnI8/R13cpr3kLEmIBraV2LDM7tv1PkYvondTr10j9V3uNYSnVEAWXeV5fhEY4rQ1w2u
Llpkq7T3Fn5CEMl3rXvk/6R9B6V9VkKkALFGoeva+yHtIPzwMbCk/q3jwljL3lXAZS50pg3bsaro
POFIzxE2pXiAiKUNAUQh7KWHd7ctnQSLsdq5b7DAuHJskwiQJWNv0weJPdie6ddpwt+DPjhJtm85
hfiblWPLq8CnDvmCbg/wG9nMmbve8HBZApteaYyXYiLwO7LT8PymvdW8Ip92wdDaH1OGRCv12QMk
Kg0QQf1FL1cTtSVz+fwSqaQtLjwgiBI69TA9jilbCbZWduV9VkunpdTgLSKvMpKN1VJH5gClIrKG
DRDwxPXwTKNt5w5RdoBcTPEkylmsEYpQtGynWseM83uETimS1BLZAD6vNwnqB0Akff34q5WeERlV
nzk7hTEcr3TqfHTH91iKAwXnayowWuEEQFdIA8AOfr+6G21sezcnvPcI2eB0Ke75tEn2yrg2D10h
SCxBeCAo3pvGKonbfST4CzfJPaXqAvl8XXjOwt9cgBYJeNTTor2KEmon5B0l1xoDl0qv84ApiPFH
y35sfU6+uixUJGHWNeldwRDSWCw51wYxen5B5z71CJx6DmXksQFUXgOtgzZBbU8DAmhJbX4VdqIM
gkF5KbVrZdlDg4iC2frMBYrsq9W7HYQnOOwmuKlpxyCepoRDqdIrvzgghgQib6n8MJvOWO1Dz9ql
6UEmLrfFiOafwqZcvKhOCJOHRtz2qbWY6W8odGUaRD1TI8699+RWxTsc8XEs9uvXEHRx5o6qFMUZ
2nDs+b72p47Y+pOqBOgjWzz+WOCXsI+mDVsdu0M1IUPVWEpDr7HV8r4XcEYxGJK0AaOa2fK8V/rq
mnl09CEjWG0JdZACWRzdxRG7dZLnrQrn5ADW36B3Gp4YVbohImbRgliEEdSlVQKKIuRbTUXXoa5j
6wh5QoV39DohwKIy5GDzldNA62JqfZAvueL5i7k3l6orKVgGVg/9bZjR0t8cbb+yePfKO1r2X2yu
HU0aXojgUE4RE/aGXVQ/rOpzFuapGK7GShEjRtuMYo+wrX+52WwSPgwDeR6MIJJfpiJf8S14oOEh
SSSTaKH7IkQ32Jq4r3BfD/6ChwVdKPOTuHv34JUPAVpFmKH1H82cME7BWBOSUrzknACqj9+xHvkV
b1Rd2XpCIfFtdsisuql1Irx4SSans5hEVCos2bLq4gUDBN04kXPGqQjfxW75oUSA7lt1j1iRF6td
fH6j9jeYAnx/lntaC2Bva51hT1OOz773duVebC1td2nWl17h43MWNY22oBbRs8n7Yf5cz6EN/X3z
SXM1GIROd749P7g7uV59dKQpbW82ReCzukW6y2dZZktuvADyI5W4mif6ptL7w67wL0nDL9GFHSL1
JrXGVEkLrZrDNyCP2uYHxZQyVeFQainC8L/SPI3trwJSn9TgeYXV9/cFohRsP+V9fyC4RG25FOi8
iQpaGXliir7iA3Htmf0NKUJOa5nBbVCu49WUizHk9cwNGW/rHZbDaRrWRk3Y9X7d3EErQGnaCzL2
WKepDVdHFd8m4jtvcx1BQMieVexaS5qPViJyr8MBXNdaIy3r2xLYzi99paue2zAJ+gE2qmApliaO
Y2H9FtfknKyPNh963i/q7/sVQAFYz/LqIGcHnpVLvN7SAaAAxuESGS9jM1ZQffyE2dvfZPq6RaD0
xkRqJDEUDTJ7ksNqTEgmn1ghK/91hMTTArfWn7gh54sNLgsxnAdKyYlWM5Awu/RgDqhOCayfBjHv
txcIa+ekBB6dsBR/cL2oWLhk9ArqwYKUdM9EXzsBemB1IbVD3mEbDRJ0bzmPgykWR26543QiIke5
YWIeLTuNCFND+v/Jg/Vdl++smXckgBP/zOdM5mO0WwW2JHeoozlVjQHVvGcOZ/Ckh5MDppnOiU6Q
y+LBQotcqUZmdFbFMNxMdl9TbV6MV6Exbuy+iOVcg7BJNc3O47J+T0wHHoI1sq+yQN+ZN2g6YOEZ
orzJHhFnyYzhjID3mNz0PLSvo0zhyLJ+LUT8+aHV2WgUP3soHXeKsD4f6d/By+Nu51UWE4Key8xE
b4T+KO2Ot2pQR4hvIcIvexyKrFhHoz5JiLtdDgqukj2j5jfMKYXghob+4TafX0Lej8uME0EMy+na
+hW5E4MsoSr7symF9g8oHPFgXsEHsCEGJPOU+U6PcNmZiOzufPhSjMOZk/1yy+NqWlf7jZaZO9BH
jc3QoBkwpUFiSbHRQc2TUr9q/UW5T2/hx/2tlQElroH3GDkh4kBtpHJ+q5mOuvWTRZ7CL1vpfO6n
N34iSJ5Gy4ylZj74mMonE1OlKLIRfNx4/gKtAUZvbE2PW8pBdZl8jGRHexAGNsjBBJhQhe+XtzS9
Qmh08VdYQZl0FcQwJRyLTPOE6Y6dhesbQX986GTSQynnCdECNSxldg1qNON/zrHte4x9DeQI0GVY
ww6FlcSbtb5N9yXmdxw36CVv/8J36FL8jBfqnIZcRJiT0WaU4IXFRU6/XO3xM8PsTmswV8sF2TGs
OrFn9NIafDAiu3OgvN8Nghq9oidxA9+Pt7T7cji52puxKtOG8nMy5ZZF06gTzajrVfj2200zvFrG
P4EQLFCEIfYahQnil4Q31uD9yNd5qXfUE5W7lSsmlw8hPPDXm8CzFPH+1N1r8HXDi6lAOqIWKSYk
6oBs1TzYqrRamDkCgbQzhOa9yNk1H1VG7dmyp8q7ld+9pR9XwpOqGUfuBKOVNeH6uqgN3lPRqpcT
3NmYo02PGjgqiFbl0PRo5P0mTvQJlA7maEDtwyHyGlObFKo750j/6Rrw8YBImT5okfugOUD2KddG
G35tzskyUIQK0WhGn71qSdiJw0k5MtXatrdxNFORNBHy0plUt9iPvtemzpGAm4DEmTppnPZFvRgM
OpgFSGVhylxHUUhAg5Jdghp+xPse6shb6FIihhwXOZ567HCeyLJbCCiCJ0UI+SWHkFR6mDl5abUI
8CyD2ReY9XJ2WJUCiKqSArMa3z7MkE85/jrNzWS22E9ow49e0IO9TRBcEoU1lIUW1DAlzRayWBpL
UK4GrRfxM/mQJYwavy1h3/Ckz7ctXgT4vqK+0cIA8I1Us6t8IbyUeebjvoAkDjAg4uSwb8VGiPfw
D4soaEcpma8VUS47Ixkbv2G9XLTe0f9jc9le0uHZCnxfwPviVy7n9c41uaeFiJL0FL1LG5LtDh/E
9kVNGV65+rf2YAyhi/VWqR35y/nIBNYJQppw9kn415pQ7P1IFnqTUPXXArjH9Qa9yG076XCjqdmT
1tlv6qGyYCWJ2z/LJ7TW023cL9HL54xvQo1X2Im2zpARZvkptRRzdg88teJAvRQDg9PpyHso5OnQ
kWfluUHllRX+HH9jXHHO+G4p7U/OKJsdC1XMmzAYcS4t6CEWQ8cXdD/CQFhSYrcIQ+eDNyoayke4
7txtUlkHu0iszTk7qr0tajPcj8PZ9dCMFFcqD5cKDSBVWTzKKj9uDzNfeJ8DyYlWBC+YSgKT0UHu
VyBmRYqUauuPS0apvJYP4cMDmp6MUTv2W4IFhhkYaofPzaJq0gqP7P5JdjGjBegdiNtmkk6KxJ/N
/dAoHMpK9YgL8IM4AvpxklYnHEhoDyTu9IlYI/+x47nzIGShbNjTs1s5opQWQsm6HHUbrRtzcaTh
aOnM3XTX7r0s99UnA7bryuWNSHOENg1iqvCF6huD0xBuprQhIGg9UZ84Kx27TqPKkf+3ZenbZcEl
mmx8IGW+IOwmNI8JfmM+r3jZaKE1i/sPk4VwZyuTdngsBelD4aBdcEH3vbYgpDRH9BNDW+EBAAhz
z8+nt8FMzt5zfdOgSWEqDh3kme0MpQI7xd6qb5qfVHbW6IikIkvppf5x8LmPZyT+OyQcQudkty/o
8HtTodik17EhwlRwISSJK8dW3X2PVtXcktvkTjf1BRcwrvt1XNuilbXBU/dLyWUcla57nQ0IHWqf
welZMP/8H5CwHL3gCnqd1NpGcTZE84bU2vxmd2RIwBklvIzfbeWyHzGAWtXJgPSlzlD/DcW98TzG
X3XepNXUSTnEDi2L1ULDdfA8jtItbNCbANGaShqLXVceKNxvK363ygJOekuZlS8z5U7g1ihSO3du
vCCltA2X24x3s9hxtUSLtQt7Vik/IFB6eOIrlWKBYloyVPHZ8ZoU2fqylKJDeGHccfEe1i+c6Oya
6QutA3AUhwfk6Ep6qBiRo0gC01pifQJ+vFtoKPRPfZ3FnyXO4fcdmW1X7TZ4Ay+jMbK8DPO444UB
7r6dxpjdhcMqBOihZEGxEj1gwvR+rTZtDJlbS8t/TK0zrOZAFTGOvS60iyj60NXwIY6rd9w8KulO
tNw+an3WjZgB6yfGsiHzQA60UB1/+uhS2dwM/tO+78OhA1Sb9whXGN9lw5Vp0JOL72Oo/qUA72En
c2Zrw45UTXD+5PwbZ72C9UPa0u8qaIrfyi5gA35iTzhwmXfCkEm+UN2uiKafvccYQcQk071nRCsI
r21TEZ7ZgMsY6v6XELtKbif6O+PMSxifDcPAXGn6bZZxRjwdVehPzCrTuuHE5/fQHkVyL04Xl/LA
w91SAwTf49UVa1Q7g9IiNPh9a9c6prWGszTR5rVSpkmYYVk8aje024GyZnvHx61oSF9apYQPaOLX
SNich/7Q45wfQr5WLVkw97HFbuckvfzgQXBRVJmv8l29o7Mm9Vtoxr6iS0+vz1W13bPRdQFRxg4x
1/zKW8tkQoULxluLepijNfjLH9Ws9sUBDBvOypdVhA+1QUwiQIza8SBqeo2ScUnyEn/awfFk89gg
S9J6XaGoGPTwYfGEzGRgrzBEisLHXRLYkENQ+H7P15CbZ3pqLEfvHwIkfHNG/kOsyz5fDGWkLE/U
xXQUyrW0gdQgFR9l2o+LH4fm2Qc3ZPh0Zg4o2XQlJwDAOCHCC+gUFPAdwHHQUk5wfOdsx3VjZ8qK
UItIE8pAGNplNT9yMRIcIkatnP9suTonYFLsD5dEWcsc2AmgA0cKCzQIGsN9Xe+q7EbGQHM30osq
+uPt91OXm6Rypo/QfrHhRF0DeJFAB+n42ld7fccx6e8Ob+57qGMo8y5hsPQbpboZ08I2MC45cySv
tJtT3tKG7PpLDVGnntGDVTvMTbzft13mCOnNgRON47V+hgGirmbpCRoidEDX+wcckQEc9JZ7H6DC
GwLh603AbWhw7t5L9dXh4DVAj3h9OpAGQ23SnRTNpxC4SgPyZgqbOSuMJrntNIz0tWGF6QDmcU95
PLlkKaIuaf/+3OPFn82jG/gDxlQVyWw3wyDkUxvSCBNaZQnwjU4C9nLswmK4qTtoLsZqUqrI6ihy
XrhL/wgThOlJTkW7/RqxpjiWxd1htwWoXtbXRD67ACULpyAzcgh6n4roeERC44N78Vj3LuN/WjVx
WulkxJvK4z10R1blElJpB6df4el0MqZ3PXDhGxEZlbDBNdpiz+YNftleREOwFQDhnZsxDX1B6Gsk
lA48pCdGvPUJxnTZovw5u3y1VOguYGVfl46v42quXYfawLRWYIhtZT9vFRcNh55gnJzMqeOSCX2Z
NB5krQllu4jcFWkEvDxMzfHwrMgRkK1Rq5wolKKhI6MdbYf9f5gvq08k1vTabuIpKky6LYqfALZp
ESHMRku6Gz1/XKyJiPr4D8ywhg0GZmvw3OH9BrGmr4hXzR4jObYkRuQtxECu/s4NsMjZOb9aZr+V
oQshr4POoQESNvTEFoyaEoypYhA+mh0BeOrjQm01052ZECfMNsqr7wOF+4qmG+Ws9FlUodAqC/rN
9hW/qpvxcuEoy29XE9irmD5nG0a7X+ak8wEj+qd9QMrYnnk2qM63baszjsxCsIX5vZZh/X+VFEp9
8O9i5j9FonWkJCz3IYmfw83h9Ijol1svQhCNUqA13HFAUD1nkNerjoM4tUxfHvaDtZkvz7dNhpl9
fOEZbzhfiXQmlVk9cyl1Fq3/HW7j8mkc2wHsO/xE0T9iKCQ9rwPoH3FuNsuPymwbDVKBkBuKy+Ua
0dLJcyscKldxW8Qoj/+M1yUOUy8NmRuSg2Y1I7Fzfs2tL0O2owXXOUcqtqVLorWLrPBLwcoynALN
Q1Lmz5KF+4T6rvSHBO/Lzhv+YbqhFI4Uf+owu/TuaRWrH2eKFFx38WbQb5EU+rOOeBVeHL4Ne9z/
nw4sNPwyHqVkY7LpoLuQjN3EgAonJhWA/jt0iK+gvoj/3GciU+N6Yv9R/KC6W6oRmckDznxPU1m5
Hhgw8nL/z0J3Fz2Rhq145BEwHYL4TMqBurqa+U4q7JDMGoSccS1dRk2IngBTeSYae3cXOaLOylmf
fKx/bVCydUsE23Ne8UFyGNJjK7U1QkV03PY77RZb7B1SBdL4rA62Jy+T42BcGLR68vI79KAxg8Xq
8UcWBYbbYzGvUOVfX+5pocWlhR8naMo/RWdB7eGJfCF1l021SrFxkkrQ++4I+e84HT92FJjhhu4f
FoHEJiwM5//VNdLVTUvVXE//1hSC2S+WcXaiRly5iVlOIAFdPl8SfwvsC+kFDynMfCUgFe/dJgt6
/22M0C+eFRxrqUwotMNapf9mFxIvgfJeSkrDaGGUEd5WhkqatEwrEje/AhSjq5lKcON0v66MSPCV
3ETmo0ADbeNwrXV+2EcjtrdpHRjQ4mMW7vJpMHejk6yKRL8EdCrPyJEl+XPih4luNY+MYuK3Ybm/
05oJtRwzUu4D7TI+Rkjzyfhw9UMHMpNQ9FgF0KdhJTmiXkHvWnv0Rx4pK+xSnssEB3Q/f+bWGwgl
9hJlDuHA6dUxWE0vtOXO2h1fGNih5onvdx2KnweJXXBjJ1eynEcgVKCYCBf6XZNV4qZokhYV4dXN
eAq7WxR1JxsanBnMgNmqFhJChBPFcuwvySzgphDGjPKl7KIkyF2UtXGGQvHeOJnsz6eNPyjQNrmw
qDn3hPyjMdbp72G6rh/fnVdkOTEw0vGGlHKKk+ZqlVTPM8FeBac6DN/oNIeuDxZv1nCKgHiq0tWg
i/OGtj9MCryjWNweDlt3x9PxjV6/yqflZbTIA9RjjgYFNGKIkl6p5PXbt8/lpb761lrBfpOnr0PN
vPD1349Ee90K7AMG+g4VjMVpbrcIqhlUi0NPYHKi1IejY2ppLCRe6nE0y9PVa774YjLVcj0qyQhF
nCoTzW7kOYnWkZ0t/wf0C0/5xVrweeQ6+4r5XB1dMMN3DupRpw0ySEkJZL5O2w6YAFBTsuSnbue1
S5MzrzB+REPSa7K0r09Z6zwS3NOqVF54meEUiaOWNRUZ+P5h1xxOF9bH2mRyFiU+VqOLOKMnuhDF
FL4wSsgI8bKn4abH711AgTsUAAyD/GqEBsOAAYw67VwphVzGNqeLsnIjn7/7GAau2+Vfb2xQ2t4H
XI/XfxzWnKOzl/pJJeInmo4/FisNJ5E34LhbJFaNxkV/3fxV0fTzWWXOrpHnnUAA6cULoMxuT8yU
ta7HVflrGdZNpBO0wIJmWpNVKHu/7tap6DKhRtmjEQuWx7jSe2Ulnh6szaOK2d/fBwsnzXtdtlTk
vuMknzbwKnPSVvsp00prIgAyCk1iXrJAYM95HqzrHsBkkCszL3dKFArJiTxpwhnx7zE1CSVGbTZr
XY5+EGKXfuDL10hDHVCRPnYKLaE3YpOQfxdpPHoYyEfpJrWfMBg+QD4ONpL1v/CPz/d6E+pvDp1V
5+OMGqlkcw43IwHQZpa5Boa5fHkqbhUQiU1v+Tc/XmUtj7maYn1cLwrP7hvyzeMWuz8ft0vW0S6m
k0aB4lAlUB7ahQiDW8Jom8S5dlgRod7dpiu9LUiDDvD8sRWqyU+vbzJLzLEMPYJaOPdZdj5mT4Ao
t2lH64EEeohYXdP+jqiGmy9Dn/v9cIfRRgKOwxiYssrhHbrh0ma/1RbTnBdwOynWm5P5u2JDi3s6
YDK5uGC10SukOBc+0kNg9S/jJ2mmB/hkqaTo/x3XiGfFdrxruC4sPNkSAvZaSbwGx8zU9x7UiwIf
MliVCDdKtTWnEE0M+16D4fYsXSjJRyYI0uWZL/2ZxWp4R4nCc6/AUtnPN9NRQeGInhs2DAgT3KV7
hvnJs8qG2P2+kvCBGV48j+zsojaayMmd6xT4WIqvUnb3gt2Op0C4gYwCsmlFle1PkA+LSvlC4CjO
zuRkARO0wC3di/gAh6BRqDIHqxKBBURfU1uf/g43CxDZAWsAGUIFKabhgWQ+6n21syC2JlJn+Rv1
7emlWA==
`protect end_protected
|
<gh_stars>10-100
-------------------------------------------------------------------------------
-- Title : Package for Ultrasonic transmitter
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bus_pkg.all;
use work.motor_control_pkg.all;
package uss_tx_pkg is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component uss_tx_module
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#);
port (
uss_tx0_out_p : out half_bridge_type;
uss_tx1_out_p : out half_bridge_type;
uss_tx2_out_p : out half_bridge_type;
clk_uss_enable_p : out std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic);
end component;
component serialiser is
generic (
BITPATTERN_WIDTH : positive);
port (
pattern_in_p : in std_logic_vector(BITPATTERN_WIDTH - 1 downto 0);
bitstream_out_p : out std_logic;
clk_bit : in std_logic;
clk : in std_logic);
end component serialiser;
end uss_tx_pkg;
|
----------------------------------------------------------------------------------
-- Company: -
-- Engineer: <NAME>
--
-- Create Date: 13:00:21 05/13/2010
-- Design Name:
-- Module Name: bscan_spi - Behavioral
-- Project Name:
-- Target Devices: Spartan 3e 100/250/500 VQ100
-- Tool versions: ISE 11.4
-- Description: a simple implementation of the BSCAN_SPARTAN3E module to access
-- external SPI Flash via JTAG.
--
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Added header recognation of header and TDO alignment (requires
-- 4 bytes of preamble and 1 byte post). Based on design
-- of xc3sprog (changes made to CS handling and header length).
-- Additional Comments: tested on Butterfly One with xc3s250e
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity bscan_spi is
Port ( SPI_MISO : in STD_LOGIC;
SPI_MOSI : inout STD_LOGIC;
SPI_CS : inout STD_LOGIC;
SPI_SCK : inout STD_LOGIC);
end bscan_spi;
architecture Behavioral of bscan_spi is
--component BSCAN_SPARTAN6
-- port (CAPTURE : out STD_ULOGIC;
-- DRCK1 : out STD_ULOGIC;
-- DRCK2 : out STD_ULOGIC;
-- RESET : out STD_ULOGIC;
-- SEL1 : out STD_ULOGIC;
-- SEL2 : out STD_ULOGIC;
-- SHIFT : out STD_ULOGIC;
-- TDI : out STD_ULOGIC;
-- UPDATE : out STD_ULOGIC;
-- TDO1 : in STD_ULOGIC;
-- TDO2 : in STD_ULOGIC);
-- end component;
signal user_CAPTURE : std_ulogic;
signal user_DRCK1 : std_ulogic;
signal user_DRCK2 : std_ulogic;
signal user_RESET : std_ulogic;
signal user_SEL1 : std_ulogic;
signal user_SEL2 : std_ulogic;
signal user_SHIFT : std_ulogic;
signal user_TDI : std_ulogic;
signal user_UPDATE : std_ulogic;
signal user_TDO1 : std_ulogic;
signal user_TDO2 : std_ulogic;
signal tdi_mem : std_logic_vector(31 downto 0);
signal tdo_mem : std_logic_vector(7 downto 0);
signal len : std_logic_vector(15 downto 0);
signal CS_GO_PREP : std_logic;
signal CS_GO : std_logic;
signal CS_STOP_PREP : std_logic;
signal CS_STOP : std_logic;
signal reset : std_logic;
signal have_header : std_logic;
begin
reset<=user_CAPTURE or user_RESET or user_UPDATE or not(user_SEL1);
BS : BSCAN_SPARTAN6
port map (
CAPTURE => user_CAPTURE,
DRCK => user_DRCK1,
--DRCK2 => user_DRCK2,
RESET => user_RESET,
SEL => user_SEL1,
--SEL2 => user_SEL2,
SHIFT => user_SHIFT,
TDI => user_TDI,
UPDATE => user_UPDATE,
TDO => user_TDO1
--TDO2 => user_TDO2
);
process(SPI_MISO, user_SEL1, user_TDI, user_SHIFT, user_DRCK1)
begin
-- default assignments (put outputs in High-Z state if not in USER1)
--user_TDO1<=SPI_MISO;
user_TDO1<=tdo_mem(tdo_mem'high);
SPI_MOSI<='Z';
SPI_SCK<='Z';
SPI_CS<='Z';
if (user_SEL1='1') then
SPI_MOSI<='0';
SPI_SCK<='1';
--SPI_CS<='1';
SPI_CS<=not(CS_GO and not(CS_STOP));
if(user_SHIFT='1') then
SPI_SCK<=user_DRCK1;
--SPI_CS<='0';
SPI_MOSI<=user_TDI;
end if;
end if;
end process;
process(user_DRCK1)
variable i : integer;
begin
if(reset = '1')then
have_header<='0';
CS_GO<='0';
elsif(falling_edge(user_DRCK1))then
if ( have_header='0') then
if (tdi_mem(tdi_mem'high downto tdi_mem'high-15)="0101100110100110") then
len <= tdi_mem(15 downto 0);
have_header <= '1';
if (to_integer(unsigned(tdi_mem(15 downto 0)))> 0 ) then
CS_GO <= '1';
end if;
end if;
elsif (len /= 0) then
len <= len - 1;
end if;
end if;
end process;
process(user_DRCK1)
variable i : integer;
variable j : integer;
begin
if(reset ='1') then
tdo_mem<=(others => '0');
tdi_mem<=(others => '0');
CS_STOP<='0';
elsif(rising_edge(user_DRCK1))then
tdi_mem(0)<=user_TDI;
for j in 1 to tdi_mem'high loop
tdi_mem(j)<=tdi_mem(j-1);
end loop;
tdo_mem(0)<=SPI_MISO;
for i in 1 to tdo_mem'high loop
tdo_mem(i)<=tdo_mem(i-1);
end loop;
if(CS_GO='1' and len=0)then
CS_STOP<='1';
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all; -- Imports the standard textio package.
entity IO_TB is
generic ( IO_TB_WIDTH : integer := 32 );
end IO_TB;
architecture behavioral of IO_TB is
-- signals --
constant half_period : integer := 20; -- ns
signal TB_rsn : std_logic := '0';
signal TB_clk : std_logic := '0'; -- make sure you initialise!
signal test_data : std_logic_vector(IO_TB_WIDTH-1 downto 0)
:= (0 downto 0 => '1', others => '0');
signal test_tvalid : std_logic := '0';
signal test_out_data : std_logic_vector(IO_TB_WIDTH-1 downto 0);
signal test_out_tvalid : std_logic;
signal sdat : std_logic;
component io_8b10b
generic (
C_AXIS_TDATA_WIDTH : integer
);
port (
rstn : in std_logic;
clk : in std_logic;
lclk : in std_logic;
S0_AXIS_TREADY : out std_logic;
S0_AXIS_TDATA : in std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0);
S0_AXIS_TVALID : in std_logic;
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0);
M0_AXIS_TREADY : in std_logic;
s_out : out std_logic;
s_in : in std_logic
);
end component io_8b10b;
begin
TB_rsn <= '1' after 100 ns;
TB_clk <= not TB_clk after 20 ns;
-- PROCESS: generate_test_data
generate_test_data: process
begin
test_tvalid <= '1';
wait for 50 us;
test_data <= std_logic_vector(unsigned(test_data) + 1);
report "test_data: " & integer'image(to_integer(unsigned(test_data)));
end process generate_test_data;
-- test_tvalid <= '1';
-- -- PROCESS: tdat
-- tdat: process (TB_rsn,TB_clk)
-- begin
-- if TB_rsn = '0' then
-- report "TB_RESET";
-- elsif rising_edge(TB_clk) then
-- report "[tb_clk] test_data = " &
-- integer'image(to_integer(unsigned(test_data)));
-- end if;
-- end process tdat;
io_8b10b_i : io_8b10b
generic map (
C_AXIS_TDATA_WIDTH => IO_TB_WIDTH
)
port map (
rstn => TB_rsn,
clk => TB_clk,
lclk => TB_clk,
-- S0_AXIS_TREADY =>
S0_AXIS_TDATA => test_data,
S0_AXIS_TVALID => test_tvalid,
M0_AXIS_TDATA => test_out_data,
M0_AXIS_TVALID => test_out_tvalid,
M0_AXIS_TREADY => '1',
s_out => sdat,
s_in => sdat
);
end behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01/27/2022 08:17:13 PM
-- Design Name:
-- Module Name: tb_banco_reg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_banco_reg is
generic(n:integer:=32; nreg:integer:=32);
-- Port ( );
end tb_banco_reg;
architecture Behavioral of tb_banco_reg is
component banco_reg
port (read_reg1 : in std_logic_vector (4 downto 0);
read_reg2 : in std_logic_vector (4 downto 0);
regwrt : in std_logic_vector (4 downto 0);
dato : in std_logic_vector (n-1 downto 0);
clk : in std_logic;
rst : in std_logic;
ctrl_wr : in std_logic;
rd_data1 : out std_logic_vector (n-1 downto 0);
rd_data2 : out std_logic_vector (n-1 downto 0));
end component;
signal read_reg1 : std_logic_vector (4 downto 0);
signal read_reg2 : std_logic_vector (4 downto 0);
signal regwrt : std_logic_vector (4 downto 0);
signal dato : std_logic_vector (n-1 downto 0);
signal clk : std_logic;
signal rst : std_logic;
signal ctrl_wr : std_logic;
signal rd_data1 : std_logic_vector (n-1 downto 0);
signal rd_data2 : std_logic_vector (n-1 downto 0);
constant TbPeriod : time := 100 ns; -- EDIT Put right period here
signal TbClock : std_logic := '0';
signal TbSimEnded : std_logic := '0';
begin
dut : banco_reg
port map (read_reg1 => read_reg1,
read_reg2 => read_reg2,
regwrt => regwrt,
dato => dato,
clk => clk,
rst => rst,
ctrl_wr => ctrl_wr,
rd_data1 => rd_data1,
rd_data2 => rd_data2);
-- Clock generation
TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
-- EDIT: Check that clk is really your main clock signal
clk <= TbClock;
stimuli : process
begin
-- EDIT Adapt initialization as needed
-- read_reg1 <= (others => '0');
-- read_reg2 <= (others => '0');
-- regwrt <= (others => '0');
dato <= x"00800450";
ctrl_wr <= '0';
-- Reset generation
-- EDIT: Check that rst is really your reset signal
rst <= '1';
wait for TbPeriod;
rst <= '0';
ctrl_wr <= '0';
wait for TbPeriod;
-- for loop to insert to registers
read_reg1 <= (others => '0');
read_reg2 <= (others => '0');
regwrt <= (others => '0');
-- EDIT Add stimuli here
ctrl_wr <= '1';
regwrt <= "00000";
wait for TbPeriod;
ctrl_wr <= '0';
dato <= dato + 1;
wait for TbPeriod;
ctrl_wr <= '1';
regwrt <= "00001";
wait for TbPeriod;
ctrl_wr <= '0';
dato <= dato + 1;
wait for TbPeriod;
read_reg1 <= "00001";
wait for TbPeriod;
read_reg2 <= "00001";
wait for TbPeriod;
read_reg1 <= "00000";
wait for TbPeriod;
read_reg2 <= "00000";
wait for TbPeriod;
-- Stop the clock and hence terminate the simulation
TbSimEnded <= '1';
-- wait;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Transmisor is
Port ( clk_Div_Freq : in STD_LOGIC;
Habilitador_Transferencia : in STD_LOGIC;
Registro : in STD_LOGIC_VECTOR (7 downto 0);
Transferencia_Completa : out STD_LOGIC;
Bit_Salida : out STD_LOGIC := '1');
end Transmisor;
architecture Behavioral of Transmisor is
signal cont : integer range 7 downto 0 := 7;
signal estado : integer range 1 to 3 := 1;
begin
process(clk_Div_Freq)
begin
if Rising_edge(clk_Div_freq) then
if Habilitador_Transferencia = '1' then
if estado = 1 then
Bit_Salida <= '0';
Transferencia_Completa <= '0';
estado <= 2;
end if;
if estado = 2 then
if (cont >= 0 and cont <= 7) then
Bit_Salida <= Registro(cont);
cont <= cont - 1;
Transferencia_Completa <= '0';
end if;
if(cont = 0) then
Transferencia_Completa <= '1';
estado <= 3;
end if;
end if;
if estado = 3 then
Bit_Salida<='1';
cont <= 7;
Transferencia_Completa <= '0';
estado <= 1;
end if;
end if;
end if;
end process;
end Behavioral;
|
<filename>ControlUnit.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.ALL;
entity ControlUnit is
port(
opcode: in std_logic_vector(5 downto 0);
regDst: out std_logic;
jump: out std_logic;
branch: out std_logic;
memRead: out std_logic;
memToReg: out std_logic;
aluOp: out std_logic_vector(1 downto 0);
memWrite: out std_logic;
aluSrc: out std_logic;
regWrite: out std_logic
);
end ControlUnit;
architecture behavior of ControlUnit is
begin
ctrl_unit: process(opcode) -- The control unit will provide new signals each time the opcode has changed (which indeed is every clock cycle if needed).
begin
case opcode is -- The following case statement is simply providing control lines based on the opcode.
when "000000" => -- All R-Type have common control lines and the their ALU function is specified in the instruction handled by the ALU Control Unit.
regDst <= '1';
aluSrc <= '0';
memToReg <= '0';
regWrite <= '1';
memRead <= '0';
memWrite <= '0';
branch <= '0';
jump <= '0';
aluOp <= "10"; -- See IR[5:0] which is funct
when "001000" => -- I-Type addi
regDst <= '0';
jump <= '0';
branch <= '0';
memRead <= '0';
memToReg <= '0';
aluOp <= "00"; -- ADD
memWrite <= '0';
aluSrc <= '1';
regWrite <= '1';
when "101011" => -- I-Type sw
aluSrc <= '1';
regWrite <= '0';
memRead <= '0';
memWrite <= '1';
branch <= '0';
jump <= '0';
aluOp <= "00"; -- ADD
when "100011" => -- I-Type lw
regDst <= '0';
aluSrc <= '1';
memToReg <= '1';
regWrite <= '1';
memRead <= '1';
memWrite <= '0';
branch <= '0';
jump <= '0';
aluOp <= "00"; -- ADD
when "000100" => -- I-Type beq
aluSrc <= '0';
regWrite <= '0';
memRead <= '0';
memWrite <= '0';
branch <= '1';
jump <= '0';
aluOp <= "01"; -- SUB
when "001111" => -- I-Type lui
regDst <= '0';
aluSrc <= '1'; -- We will have to shift it to the left by 16
memToReg <= '0';
regWrite <= '1';
memRead <= '0';
memWrite <= '0';
branch <= '0';
jump <= '0';
aluOp <= "11"; -- SHIFT LEFT BY 16
when others => null;
end case;
end process ctrl_unit;
end architecture behavior;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- This block computes the distance between two points.
-- The latency through the block is 4 clock cycles.
entity dist is
generic (
G_RESOLUTION : integer;
G_SIZE : integer
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
x1_i : in std_logic_vector(G_SIZE-1 downto 0);
y1_i : in std_logic_vector(G_SIZE-1 downto 0);
x2_i : in std_logic_vector(G_SIZE-1 downto 0);
y2_i : in std_logic_vector(G_SIZE-1 downto 0);
dist_o : out std_logic_vector(G_SIZE+G_RESOLUTION-1 downto 0)
);
end dist;
architecture synthesis of dist is
signal xmin_s : std_logic_vector(G_SIZE-1 downto 0);
signal xmax_s : std_logic_vector(G_SIZE-1 downto 0);
signal ymin_s : std_logic_vector(G_SIZE-1 downto 0);
signal ymax_s : std_logic_vector(G_SIZE-1 downto 0);
-- These contain the horizontal and vertical displacements.
signal xdist_s : std_logic_vector(G_SIZE-1 downto 0);
signal ydist_s : std_logic_vector(G_SIZE-1 downto 0);
-- Stage 1
signal xdist_1 : std_logic_vector(G_SIZE-1 downto 0);
signal ydist_1 : std_logic_vector(G_SIZE-1 downto 0);
signal dist_1 : std_logic_vector(G_SIZE+G_RESOLUTION-1 downto 0) := (others => '0');
-- Stage 4
signal dist_4 : std_logic_vector(G_SIZE+G_RESOLUTION-1 downto 0);
begin
-- Sort the x coordinates.
i_minmax_x : entity work.minmax
generic map (
G_SIZE => G_SIZE
)
port map (
a_i => x1_i,
b_i => x2_i,
min_o => xmin_s,
max_o => xmax_s
);
-- Sort the y coordinates.
i_minmax_y : entity work.minmax
generic map (
G_SIZE => G_SIZE
)
port map (
a_i => y1_i,
b_i => y2_i,
min_o => ymin_s,
max_o => ymax_s
);
-- Calculate the x and y displacements.
xdist_s <= std_logic_vector(unsigned(xmax_s) - unsigned(xmin_s));
ydist_s <= std_logic_vector(unsigned(ymax_s) - unsigned(ymin_s));
p_stage1 : process(clk_i)
begin
if rising_edge(clk_i) then
xdist_1 <= xdist_s;
ydist_1 <= ydist_s;
end if;
end process p_stage1;
-- Calculate the distance.
i_rms : entity work.rms
generic map (
G_RESOLUTION => G_RESOLUTION,
G_SIZE => G_SIZE
)
port map (
clk_i => clk_i,
rst_i => rst_i,
x_i => xdist_1,
y_i => ydist_1,
rms_o => dist_4
); -- i_rms
dist_o <= dist_4;
end architecture synthesis;
|
<filename>rtl/lxp32c_top.vhd
---------------------------------------------------------------------
-- LXP32C CPU top-level module (C-series, with instruction cache)
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by <NAME>
--
-- This version uses Wishbone B3 interface for the instruction bus
-- (IBUS). It is designed for high-latency program memory, such as
-- external SDRAM chips.
--
-- Parameters:
-- DBUS_RMW: Use RMW cycle instead of SEL_O() signal
-- for byte-granular access to data bus
-- DIVIDER_EN: enable divider
-- IBUS_BURST_SIZE: size of the burst
-- IBUS_PREFETCH_SIZE: initiate read burst if number of words
-- left in the buffer is less than specified
-- MUL_ARCH: multiplier architecture ("dsp", "opt"
-- or "seq")
-- START_ADDR: address in program memory where execution
-- starts
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity lxp32c_top is
generic(
DBUS_RMW: boolean:=false;
DIVIDER_EN: boolean:=true;
IBUS_BURST_SIZE: integer:=16;
IBUS_PREFETCH_SIZE: integer:=32;
MUL_ARCH: string:="dsp";
START_ADDR: std_logic_vector(29 downto 0):=(others=>'0');
USE_RISCV : boolean := false;
REG_RAM_STYLE : string := "block";
ENABLE_ICACHE : boolean := false; -- Enable "true" instruction Cache
CACHE_SIZE_WORDS : natural := 2048
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
ibus_cyc_o: out std_logic;
ibus_stb_o: out std_logic;
ibus_cti_o: out std_logic_vector(2 downto 0);
ibus_bte_o: out std_logic_vector(1 downto 0);
ibus_ack_i: in std_logic;
ibus_adr_o: out std_logic_vector(29 downto 0);
ibus_dat_i: in std_logic_vector(31 downto 0);
dbus_cyc_o: out std_logic;
dbus_stb_o: out std_logic;
dbus_we_o: out std_logic;
dbus_sel_o: out std_logic_vector(3 downto 0);
dbus_ack_i: in std_logic;
dbus_adr_o: out std_logic_vector(31 downto 2);
dbus_dat_o: out std_logic_vector(31 downto 0);
dbus_dat_i: in std_logic_vector(31 downto 0);
irq_i: in std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of lxp32c_top is
signal lli_re: std_logic;
signal lli_adr: std_logic_vector(29 downto 0);
signal lli_dat: std_logic_vector(31 downto 0);
signal lli_busy: std_logic;
signal dbus_cyc : std_logic; -- TH
begin
dbus_cyc_o <= dbus_cyc; -- TH
cpu_inst: entity work.lxp32_cpu(rtl)
generic map(
DBUS_RMW=>DBUS_RMW,
DIVIDER_EN=>DIVIDER_EN,
MUL_ARCH=>MUL_ARCH,
START_ADDR=>START_ADDR,
USE_RISCV=>USE_RISCV,
REG_RAM_STYLE=>REG_RAM_STYLE
)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
lli_re_o=>lli_re,
lli_adr_o=>lli_adr,
lli_dat_i=>lli_dat,
lli_busy_i=>lli_busy,
dbus_cyc_o=>dbus_cyc,
dbus_stb_o=>dbus_stb_o,
dbus_we_o=>dbus_we_o,
dbus_sel_o=>dbus_sel_o,
dbus_ack_i=>dbus_ack_i,
dbus_adr_o=>dbus_adr_o,
dbus_dat_o=>dbus_dat_o,
dbus_dat_i=>dbus_dat_i,
irq_i=>irq_i
);
en_cache: if ENABLE_ICACHE generate
icache_inst: entity work.bonfire_dm_icache
generic map(
LINE_SIZE=>IBUS_BURST_SIZE,
CACHE_SIZE=>CACHE_SIZE_WORDS
)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
lli_re_i=>lli_re,
lli_adr_i=>lli_adr,
lli_dat_o=>lli_dat,
lli_busy_o=>lli_busy,
wbm_cyc_o=>ibus_cyc_o,
wbm_stb_o=>ibus_stb_o,
wbm_cti_o=>ibus_cti_o,
wbm_bte_o=>ibus_bte_o,
wbm_ack_i=>ibus_ack_i,
wbm_adr_o=>ibus_adr_o,
wbm_dat_i=>ibus_dat_i,
dbus_cyc_snoop_i=>dbus_cyc -- TH
);
end generate;
NO_CACHE: if not ENABLE_ICACHE generate
icache_inst: entity work.lxp32_icache(rtl)
generic map(
BURST_SIZE=>IBUS_BURST_SIZE,
PREFETCH_SIZE=>IBUS_PREFETCH_SIZE
)
port map(
clk_i=>clk_i,
rst_i=>rst_i,
lli_re_i=>lli_re,
lli_adr_i=>lli_adr,
lli_dat_o=>lli_dat,
lli_busy_o=>lli_busy,
wbm_cyc_o=>ibus_cyc_o,
wbm_stb_o=>ibus_stb_o,
wbm_cti_o=>ibus_cti_o,
wbm_bte_o=>ibus_bte_o,
wbm_ack_i=>ibus_ack_i,
wbm_adr_o=>ibus_adr_o,
wbm_dat_i=>ibus_dat_i,
dbus_cyc_snoop_i=>dbus_cyc -- TH
);
end generate;
end architecture;
|
<filename>projects/video/20180219-tmc-test_pattern/vivado/test_pattern_5/test_pattern_5.ip_user_files/bd/design_1/ip/design_1_v_tpg_0_1/hdl/vhdl/design_1_v_tpg_0_1_tpgForeground.vhd
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
<KEY>
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect key_keyowner = "Synopsys", key_keyname= "<KEY>", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
`protect key_keyowner = "Xilinx", key_keyname= "xilinxt_2017_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64192)
`protect data_block
CxXUVqS0kfzWYQZhk3wAT+Ov5ELGJtOZ1fZq7OjN2N4iETZHMQgmclLYD8G2Y5d/o7XctOFFjg/5
<KEY>
<KEY>
Go1uQrizLcs0SPpACyD8za2eMlW3ym56M3miKulDWcTx54qyMwF2vofsv6a8mTWiNE2xrj3wWuMz
nGV7DuFcNczkqhrYSKSw0mbhta4nCeUrzRaubpqUkmU/FaTz3IiF8QJvI/zm/cpf/MR7z9AmZTZo
baP+ZvlwtGSeoRa5TPunM7thGSIWRm7unbFTWGUT4GbZSqk6QiLmAjBPkipKBJHwy83wDPgUfgld
rTBRKRdFIN763UbWcZlw+sfKScbO40aYUihL3zP88sz6Gv04xCwibkeh4KYGKTmsvaRSbmF7IjKZ
tTouUTAharqOss+SkL8ua4FgbSybMku7hpOaXj1kp00wgDhTG5rHpvwWtUna8KMk+kVI6A4x1lsR
Lkd26+NELFtWyMr8KITa9A01Hwzp7RLyWk9R75RndoyiQGbGd4P+BulcBmBcmFuUg46Y02eUMcV5
3TyIxMjXMKmpb8W9DCNfpPPowLbUxStsxMsuu1p/GadUXHCtKa3Z26twRbLZoPXQG1ctZNOpKys5
JBN5iA2YCXFh8AScyNClOjMj2J1Unoibn+VffRuboRaaba/ZnKXpMXFz2fkrdYx6PfnDqzgilRF7
LgNqtAvGsa8koFCTmF0qafBySBbigaGvlhRN4/IiR+PO2ChuPiPmNU5cN9l5CZPmG+UKeLZq2+Xe
kJZR3OjhuNn3kPaZZK83x54YPlrG3wMzvp/IDCowgWchCuHtvS26U2iWPYBEA+WYqfWEw052OXY8
jf0V8Y5Ovk9o0HSjxGGzasqNBiZQUttTbNwtU7PmyEAn3Oi/Ddsxgb5x3irLe8caVJXB/H8DXIcO
kK/8pzynF7QZ7jF3ZbAwFkApv2cZoVGVkHgWdN4DZIHcpa4uur5Y++I+DQGZBAwtNXE36PpjpC51
pSPIDMlmq6t8T83il8BV04hsUwrNCsIWBvpanrpdR9rUJeOtPEzagIUF4NaQUU677PAsq278JUEZ
+zy4EmN11XFsxV9Py6UEAL6RMAbnCP4HF+dgyjummtgFBzB/6infrvPMGMs4NyrAuhKGLei3Eggy
J8yePb4HBAW4u14WkEzeLffpx5Mp07p3Pp68kfENOKj4p4qh4HKM2TDCpMua9BTGkgRG+kHpdDGd
eGU0/vjMi5rQ4YCqWcYU87xZAN2x/VkO18jsTXbCWX/9EA7SEmGyYyFcd1rvrZgrfBpVcAh3owJ4
UgF7dYfMDy6ZaL8QKYZ4Q4phballGtzckBfO9Av5r6IY+tzLr/u6FHiisdClSLObkWV9UU2WQPHn
Dbzx6PWWC+RHPNMVi1CshrEwQNAsLtN/3QoNc2vsY82+B3d/UFMC2UG8uPzfV8iOJfq2O7Eftf3N
+skgVPLvgfPLO075lH6LBQZTRJktxdYXFx2Wvq+rSnaY0h8WV22vCl2yRJBqyFuY9/rXIW5eREWw
i02pAHcqQgvS2BzzMsZ+8oe2CmxSqVV8q58bDQU4B2m0cUagzXbHuRKnper0+be/5ohNypWPsUID
9coRfDQKKPNnIT95jbgKPsdp5Sb7LnuNMQRECG9BZH4rjsXl7m/SDpl+NH1ac5y6tXiP8GQfGlcG
zSFBwnlzl4N97rx7TxS+t5CZvbfjsj/7aPprqhw9TNRFo4ZSMBSQI48R9KSiwqM2NO2s3FJRZ87D
WOMOYPjN4OdrMKMKfdwDk2QmZbIrzB79m44lEcFtCdJ7E2fi3PboXlld7+SQjtvUE0e9AK1Nv3KL
Ager+dqnpZJjWTOLLMOlgE8NLPZriYkUVS0XRO7EP6v8e4fFJ7K4btZo948GSrXf9yo0Zb9BQDGT
P8BWlVWf6f/j/yeciUOrMWSFsslEIVW5EfaEYP+QbsZKJWX96VKdGQE2UOtUgyiJUjAlLOdoV4Bc
Mb64L5016u38LkA2vc6MFqo+ADOM3ozKoZq+ZvCHaPMp8jN86zSV3I3IbXWZJmDHszqycWaoldp2
TaNdPuKV6YbzlKpkXCTZLjrL2L1BLXjvnmoWkM7fONDVxvwzNMrtxWJb46kMauoWJCTBOJDuOcdZ
/H9FAXqasHWXoEqwy950K0Lfpft3l7YQFlXz2cAS2huko31eORMWVPwwbsFz1rUAdo3lI9ZKYJyh
2FbskMJf3ZIzhnBZ1EMuby0zdUn1E4PKHSDVBVIOYpZFAgG995UCdOO/PrjORHYShdOD1DCzU2U9
X97ASpYCaPqQKpv6V3OsNn/e3tnsC2RT3Vo4B+VcKJp0CuYHyVlIdm5Ur1HKBi1EwFQ33wOB5VgF
ixSgB5k5kLJcgkr9KNuTeX3bTvy0G+1J2VJzKT2U9OuuF/rL7MSI4DFJKqSoeJPvc3GPguZwsd9I
rHfYUJR+LCs+qMLPs4vaBHuMAmn/8t5MjWeZpa8QW/ttro9rMllxaky/NCRbdL6A5BFplG5BhLx9
skaou9L3IZNc41Dg4qYxaN2KKKg5R/TIw5TNl8EboPEeJzNCUSqr+/KybXF2HwyVZQp5VddIqqws
JJOV1ia7Kq5CcwRsg3LhDdoZQdAQX3KFUQfQBH+P9ux6JKEkCsTrFgzbTgwR5SrITgfd64A/KuH2
NJzBNDaulzxW0EiscQLeU/e/QM4U3w5prFFI/7jwme6SIvYP4sUe17ChRwyU5tQUzRYn8kPbAm/3
8DnvPvY0wr0HVM4X1s3Loiy2D1LFH1tSIEqLDzgEAeC+hK/0Sl8gI3XJpOKPofF55wRmLw44Vzm1
ALV6RJ7P1ZOHMGOHKrGtC3TNLnUYYylWUkICrFyFLwA/6iG4jXV24qNqIfWpJ9wirXKTWDyAu+zQ
KAeJyzkr50f2UUq1rBTwDWx7DfXmpL5kRYVWcfrN6PXf4/kU6zy9p9r/txIsxWRhUyTlUcMoWFwc
5ymeIHJhZng0ff2SW3Hul3fxTchPB/qMsj0yUsxjd9FWua5A+PzeHVG2STQi1z2s9anrqhHX/jis
uiR0iCXBAkwMaHK97cbpbYlQxuA/KygRtVhBP+NH44+bgt68TGzU1ykOZk0fHaKL+dPP7Os6DvBr
P03ElF1RpTtpRBobaN0p1oMfaODC/XPZ79AsABThUnskqWmUcJsWVonJrWA/iOx6tnvAL7RHFTHB
DR12F26E50GMYY/tzKdQUjLWzoCBP65gNGwavYlX+CmttjcOfnmrPmlqyCqgw9qYZWVci5rs5kwI
zm4LF856VVyEJyUyJzBUv4Np7/4yDkbB/SPFGtrPOvNV/kNJeh04jbiyeHVMpKcOQvWJZ4Xvyl+A
NJAMhgz26EqqQ2vVLY0flwV2gmo/QMkCpZ3a8jorIEt6AAau3fmKw2/9DJf0wAHdoLPUriFCIlzs
HtCdnkTVmaOLE8wOccY8eDPP1Jmv4sen+cIUVW5//J7bNjCbLXRr8S+NcfpMqMH6jQQnyCz5Sk5L
0nkHiqgzHmUtA54ulAtWqfKHMSEy0zyt/3SDBy97CL428UEmmwiJMCn3ySiXC/aDBRJRx7IlxWOG
yU82J0X7zj99Nzw+WAuaEN+5ojJJaa5gSTT+OgU0g4KLiYdmzFG364RQ+XEDAhD2VoqlNEIUDG42
eEOu/m3QjrFpRO5DaVfpzNzGPXm3ywM3MikzQR+IkkHWc6+YKpvF8pdxgmwfR0Oo0KDUAwl6/cSA
1brYQW6dSeS1+IPaESHVDUOAXAJZpSRpdDsJ/vgGbpf0+7MGHNEFmV8mTjT7KMX3836cnPkTVc4I
RltpQRSMmvg63xlOlAy1xe3pLV4lnWatIY6uFkcUiLVVbZN1qTUOh8MM5BirXBOmVGHMYTea8dHd
BgHdIVTkQH37vR6goU+vj0KU1zpH3JQw51/aiX4dBm0irgP2Fk6rmd02lOh+BXjO/7nTjQVmKSiN
Igkfyp3Ma2NDKD4HBEX5sYEqdr2abAQVscC4xry9tZiW0ArPp4MBOMj8NfsV4ZzFtz0YEnkte+76
5ICpCDqoG5L0AMpRSFu1Yp0iPDqQ0jazkvJXzaW4T59BxlLbIfMD3b4be73oGrADzdYblpR5n1Mu
yAZPMurHd3z/3/Xp4MMuIcTHCJyR8y5lRLw09FVLRYhyKUocNe8NmHPmYcQJI+LHqPcjupNgBaVK
6fgF6wcyObNDsesfuUVe6oG+CgbGD7Hf+70hLDqXJkFL4FDRmd5Ich+Kfd37/pVsJjEz9pkN+9Ma
vlZWO7gDz6ujpj7qPy2ZrRbMYNuFXqpiOlaxqpaJlIujbaTZIYvE+FfdDRq48SaTtbLsBj5NIjlV
kr5KrfX60lUWv+t5UVydravlHN2bSkgQy8dUyOJwMNziDbMxEuz3LqkusATMoTFHqTWwGZ6rcMBk
MX2vRi0ypR8Fh+Q1QWxTOUshFaZfx2Q7+ePjO1Caqk8zbAaIcs/TqSRNtR+dCVPFbFJSUwbaIVRX
QNlKdohS4Hioi1vebyN4lb6N/WgU46cxqpjQczjVTrpRg38b2G7L7dM2DBSrdJIgT02awAbQEuq9
LKkxtlwzGo28JGktbqO5Ud5YLXMSyg4FRnK8LqZG6xy/b7gPoxntUJIxwwhBqx4E53haUp5fYw3q
GB64ET6iO/SKBvKgLTUWBLuaHO0zC5ePljt3lXl8tcCsRUBpQVgP4ORKczNbvFQMkiR8j9/mNlvI
pRCEYqKFpve/GZDKq6/K4OZUzWp5I7bYTjNlWJCPrkQOfCC9HRcKUXp27AMtwO5oMfqcjL3tmFNs
BafoPAT/2F5TqiRm2R7qdfs7opAlKxYtcW2MqMostHhjNscKoh21a5llSMqm0cFv+LoOr3EoOgNP
sHNvsPZGmgbOHjGulDPeeanPYJZFvYcik+39U12FpI3Bhw8eIncl0UfCrnBhHAkfqeQ3DcyNUXfv
mgFmVq4yahCdcuhaEBC5CSz948B0Gc1z8nlRpO7306YV+3RnDVwlNRqwxRj78d3aabZfeJCWG9x5
sBuDy6tEmqub8uzmUeFJhB6g5C7hljdQrC+KaYX5YV8x67vah+KfDaVvk6q+Bnq3zEMdIeYSBBSf
IFNjSCYqwNW9PqBRsxmczhiWnXmXv6u1qmgp2P7O1Q7uNgmEXG+yvq9DirL7NwYMP9Ydx82XqV75
KrZNi1OEjpeZ94P8nzqSY0k8Z2D6XxpTkY8Anoo/iEOVmoyQVGbkEW0U9aFRNuIuuzAGvU6R8d7W
kO9qd2jprTFKTeUth3DrL5nzJ5Z5w9bOzRyWFsajAF6cSxb4BIZb5pgwaDY1vkbUvT34DFbQxm5W
U+QAP9pL0Alkr/DLdHXiF/T13LQfZ9gwur3bBR4UevjZPtORch911zn/cmVhDTQhwyQvS5VK0oaN
KAXyBifCIIrPDcPuk/V4Av099cjuyOqjr5VwY/jO0uT+gBNe/gR77MgUUvZL2DZO4mww6iRDnvrD
PDIDpg+qnuUvJGjlzsmre3mHeS2OUx/kcKTPAKKhYbNCTUfBFEu1l1852fKta3uRS5t79QMYye8l
yLFmXbYqG5uP2LNH2JJml7guTgc3v/w6HU6K9fVkwn9QIm41lDkJUQNTO6g8TJggbSh2jgWD8Rhb
VDFxQWXiCme6wJzSGxqzAUAIbMwXUTmSyw1cixl0eSTu16E8tptrOCrK5+ApwxqRvR20gW9GXiXW
QY3l/FY0HzSBf1jaYeNEihjh8vetFoqB0yEtPMNNluv5XjFWa2ihuuj9XPSBwin0sEjb4SpO41iI
6MIW/egMhqvjMeC87SEd59t1/abKgS/fJ8UOayzKjOqr99JOwH9E0PKVrz/quIjrh0Ft2Rbbzmw4
QD26PPxkp1xe+nf84D5O6fPjWQbwxGEAMBNgt70cdP8gPRFSG2O8uUTW/L1zXgAEsP1l0EMb6tUP
hGhNJfp2sJkRgnSHXpdvrcYvwOgNsMexEBZvUgTNt+erR6ZvEiwlNC1qPEGrL/SGexCKwRyyyGhh
zGy77fNwv+mRMR1nhmov4iZqyNjZi1olrHJqzf4nRWdUfU98Q7A73HA118hZQn1rwHt08kved2t6
JdJIck+krzJHXofpcPfTy3qWPDd09ma7/NKUfq0SnzmL0dfhBnCWJ5GgN3+QYYIT+oy1rdvV5AcH
diM6R+F5W1NwPMmHQZVJlJ0ajrbxi2HWMzhioy8dYIxKbx6EIWMwloIkbyEywWefInvBsDYBlF2l
+/AXaey1gtU7185CELQjymEy92Ls/2FxCLZ5ZfWnPk/mmMoX+gFzzgQg/CKpNdpwRJ0iZ3Sz1YOm
U7Fc6uY6OCS06Ps8AeP42dtkGJzpF6o0OtYK4KL1ophDcXyjNgsSzKs9cMk3LUmOaeuwFrjf7bC5
P7K5mC5GfhGTWWCAQCwxnDux8+DLjmLhQ7GTuUqAnLjg2Cw7SgrXJYtYMkfKzM9nBVuo5bx7o6j5
syEcV4C6471+Rt/uxbm42Q/ZxVerJ/f7AMMQlVYZ5UeEgIE5fOixsYiWX8Xze4LBW7ldmLEzLtBI
77A3+R3P94Kc/oZ6GjgWIPvB36UKjgGfqPnhlCV4pJMxkr6ahsJhQC9+NFqSvS2ztlLmnXFbT/ni
ptitF4r7CXPUMCIUtyhQBGm1r3w+Qvh62s+ONp1T1dx0kctYZCmpkqwX/g+35X3dm4jQ8CPPLd3E
N2ewm3ll7GYNNiLOUejIb7t/wdwEjhCs+7+2xzDX07QY7+L1Lkt2dEhfzqbOzXRyxYkSZjaHoWLW
tL4aqE9zwoEM/YHHPil26ySL2pfS9BirucDwCfzOGhyJ0CaJPM4rJ2HtpnIF/rJKrVHbouAZ11vw
oe0NCzuCLv4lfDZAxEyiXN9N1cNeb6b4CkxZzJzFTMeC8CtM/tZSQ1ygDcirAl58k6EkzAFFyrkd
2611PxZg15K3EpZWMbcPFrMEhaKO7eoynrjMxJOILfnL5o302oHSty8yD4txm8JAQQFqFREfTQPu
LzISSTpmGlF7u+gdU9bk09X4vsabZabndqO3XGQ9abp9ScqHQ7KJsDOvPAhl3OUilXPLMVPx1Gov
SwjcHoctlmqUcWASko+iW33PTpXQZbqtJuvF+6CCV4OjCsD+bSZuwzimmdIVfjEbPzS8NPPOHBQR
aNWG1OqEjk2VBnirEgRSZro0d/AuWzRs2Tx/IGwnd7tXZvZp3dqw2b2yrXY2xJ/EyeLW6mZivJoi
1+y1wb2Dj6irDdG8SL9Add9xwaQfMzqx8M6ktHdt0Rrb9FG1l0qTTek0s4OGx1fg5RqjeqtA61dR
vs2gM+hpov4Lx2rhSf97NafYB2YuPsoeBx+wIsx6HL/bxT9F14yZ2A1WdK2szH7rU76T61smuEM5
y81BxVeIGH1BzfPsZ5akLl0n9acczc9/pbtFLgJvzjmS644bL/RdiuiPqUXiesYQXq7BXsCUlAYI
bL686Fe3YEhw+4koeFKSLk3A7dHg3rWknPhfL365fY9dyf1NYERz+kTXj6tzyp+8OiAT5XdsBK4Z
vJybzWSyygkcB+JmiJv4RNRP70rCzj9cWppgOAXXmgCPMiN0asbFTyZ1FsSccjL5xFQP6AqHxea5
U+mMk7a71tU/zmOdjoc46Kk+CfHeNbHhcWt3VZg+S247NQaeQg841DUzpDs/QG33yUDALoKpZ2jt
j27pD8aBBO6af5oojFjOLy7HCzKinEVnKeZZZkFCvC5uMI6gTuyNdEDfWIjzWQQkj5LV1orX9yJr
JBJqDb0H8ZKc2Gfs5womw/wwuunCDe4XymsPCT91A7C1IphGzxTmo7WmEYpaPvXlMiUSUBujpp75
kM/OFiyWvcBdm1tq3xx/g095vvW4ZawPfuRyUBgR6Tct34GhekM9uzcM91qc526NxY2plejcWXsT
d/EXGmJDf5s6KD8GE31PX91DmjZ7vn5Lct9WaYgUiSbFOXTT4tpDZtLWUkI9pmsOy1v1n1rp3QEY
/5d5n2/OBSFF1fFHCPeSm38qk5rMCP2PbvwVA32hMuruViZeB5kxYrw/ofYKRXaZEaBfzva2wuSQ
wnOxPDwh7coHPddMpA4azQ1tneZsV2fWRLXY+4Hpak2RZB/KQuK1O8NUkJv8Rsl6E90hRnobIRCU
lfudtyI4n71sau1phk4WY9hX5aCi0tNWH8mC5+4MVkp+meg3Gr77EMzHWwXTH2ci5UTl6MhQ9Prr
NYhy/FUG/npspIp/zZIT9zFOc6aNo3BE5lKKzvLwGoHXb7O/bbM1NJ/hqMA305KQlfL7u0Fj4MXI
+u97A42iqTsr8DB8s0b7BqGFj99EPv/Yywqi4W8COB8kLefuPK3iAWQmcJT7tGtBJOF3dVYKPtfM
4WN9o97TfaeLbgBuSLhV1YipASQnbCTPtrXdg+3qkgLfme7C9jUkNYADOvE3HfoEIbRpn9fQJaUW
KoivBLXcJPvYtGrdJ6xPVREYcGF+UwnS+QP75gyvwNevZ3hqdDVZQ1ab3ljU3cHN34gmn82SGHxh
awD19ylg0ePly55Q3trWSqu0FziEmZoEKFarhTewhv+ns5BvqJyUa8LoHxQ/gRPesiGbe0shCDXb
qKONbQF4LK8lKcVlIVuLjHg24p0vPoawWzuB3f7ij6//qoey6myzfVj+DSl88EWkRcqsTEXyCTef
qtKPSDm0ilffRbcIA1ZoDoUrBzVpw4uFlmtrsqkQQ2H+WsP9YLw7gf205nhLDSP/YlvsjydcFLh4
lOtH0L/j3kfQ8SRstWH0b9f7kt07LXZt9AtK+XQ76ZWUJldl9EZNqTkZRq6wxrBZhIzUMeRcpvgV
/v1vc7jQ3NlloF0Nqle8Ghii5YWPfbu+zrvuw8fbgyOV1a+EOZ/geLbpd0ddjGbimm8L2hjGFsii
LBYnJJvFfVhLlT8Av6ISU7Hi44Z+giK4Z2OA8nQBe2OKj2XuT40/rq+dTmQlNCseuhBIAAHjtNfu
34eNdr3/2S851QAQHzHfp5HpOqNeO7+6TCzzBR1Vjt5nhjSm5xOLZiaZHUsWZ7QMfu2HhqRL3tI9
Muv0qS4wIL+nwzDP2tynOJjqCFfkp4f1eUU3h5Ifrn/5vDbFLfLgfzZjY10PO3b0E0lXCxSkn4px
Ie4FLvuZ6hTbZEOirOOyo27aeR4eehJaVSThXmN64WfCwM63d2duufCip5A1/KnRLt5Fx6Sh+Z/W
YhGD9hiA1xZJ0df+QZiyBpK9Jvgl9WXwlFU5MK57WM4w35T9SSe9DCelbwXyceKYwFNh3SBkXkDn
NUpRyBzZSZuZz64KqeFReXSnHdTLUd1THUDOtKLSx99qw6Xd0o7ysFAE6w5byKKeNlDIYCXINLEt
XuGukieI9zJLIqfMsp0g9Hr/6mXNQnSXBOqoMKjp9HqtcygnrNp3aofzngE15/409JrhyrSw+8ZK
GXQiSyHOtCQPdbyz/d42L5h1kiFBfNG9628Gfj0aAiIm1hEYQGYOoo9tHKP5WYG70HlS70o4Kps6
4ZLtGIffaQqTu76l7f1+SI1EU7McBy88N3VoKi9jD2HERXxvZegSvNTdLbfv8RVW9St4oeJKpGhw
S5yL8HgXuF0wGfzsnrTHwcvlkLq0Hx8MBfn+nrh48PCEwy+JFbD3GVXyIxBXDPUHu3VBkTDFnrHY
v3iGZVxnfwoMGbZ5u31IjeY4/L7G5bBcXZbviG4POnhBv8OPiOZN9pJ9CGuGZVEibnjPJngMNa8+
VFDyXVIBVQvDNb19zqKuLV1GYa/yWlzDTeUqUAANt031hl6bzUceEJwkOB6pNzvdSSSaEdMERoQU
haZVfaBvpV9ftjBlXiDz1eoPMn6W0TovP/cC6Mf3GWjENvmeU8+UP+poeW5A6dtBNP6+86ar3mjw
jnazv+XuzksWZmHzXsgzXb5VE/KGK+HYniNq25w2VYPlMVtMOyMahR7P6n2O4e/CVBSLOvIX+sZn
BdsA2eO6EEpNPdpYQU9zswbi9BCwfLIa2xA6Q4+FsRlDRDywO21vuHPYyhHrKfqW+Nf6AT2ge0gb
YDF48+bjqKYvUaWstnSlZcNJFa8tEFlk4zhvundJC3CM5d5OepF4jAXK0vWOrTSBUW8dNnlHLk9G
KWE+1Q8pX8JsDgdKtVPo3tnpTxBJ2QV/PA20KLEQjLJJsEMkm4Zvglv7w3jCWu0RFIA7/EE84iuc
88MAP9lkYJn9hMR57OcdFk82ayAGToi4ZjpGGtlPJ5d8devXxZJDYpYNeMy91oW0fjMwpaZpphAs
ZF6nMD1suJczwcGsHVbejYkvCyQ68bP52JJOyFgEIaFfI5fr8Rp/HGib6e+WoSwI05D0oFUKyYaw
z9BmT1fC6q8Ko1Kcg3YezOgeQDXpcV+6dEIvD4HPNPDkUHSfy9gzBxNLV3j+cm4GwzCCbmCwDaop
55k/xV6nCXC4gUGXpGDX0r42nQQE/cU4lSjc3/iIS5Oz5ZLLBrk+kW0B5Nu3dPVZxlf/mFjDns0q
baY3x4F12uOVDJCe+hF4rUyWkTdySfriSajZ/KWTTwvCa622U6x1XvF37yBFnknSL6MVb+SaC0zJ
WUJ4OPuq3v23NJsp1mGOT3Y/cVKHVhhoQcVL4gQN0MeHy7QNlArWDccCeNdGOEwp5iPub45NrHmP
iLBrL6ZmvlMXw0Wtj90a9Iu6d+UHqbbLGSUI66UZ6mXjEWKjligi++36zfZ88q8h+lEteRyHvoSJ
RJAdQ/YM9a28R0RP0Hv7wCm47qUQnpXygeo8OnGH5Rz4idV1HUykB4aNX1NDuqL0tKTOg76DDIm/
oVjTYvFO/a7B9jLG9W8BUO8j5CVvDNzGMvUdxe7uuKLzOLCqLkQG/A1Pyum8Nf4lqq8uTEm6O53i
M8GjNNeWg/uXjZP6JvSYPFnoOfaPJUKXy2MVhdlfcTuUMc2y+2vcZj4Ybfs4n0BNmJa2/rUxTmut
lPiNRK0pFI6Xavlfzfe0f9WDuVVVkyuCAO68AlVnC5ViRC/qkBWBQJgvGixoWH234MGvHNbgXcvP
IGC30BEBKQi9nAIN8RTp8iQaW6OnK9KyTRobKDyS8bM9OQvCUi/ViZ5GE2qVLdYSjkPuey/M7BRf
4UA6VVeZzPA34UdvI7HojdSCV7DJhJmCNtC7Fmg8gqrH0upOnCPICG10wc7Slvt5yh+Ta4F8RZA9
Bk2TNUJNedpyjGZBL4545kZL2xDnUWD2uUKXXjv4VT2LzTBaXhUUjsGViR3qW7oPVzXMabMRpCbN
xTgc9UKBuoYlsyVmq5/dNNu1UYgZvcsRVrMpxA/KpiHvbHXF/0BajxUOnJ6Fgj11E2LtHKbi2Yvo
HTGVnqWho91xFJbwzDPAWtR6axrJxdKnsRWaxAC6h1rPYePDpLOUtnl3U0uiUNamBf/3K3z8oY8O
DNeC04nZn6EFQz0D7nYJmLox9bPdGSlo/keCqLw4eDOl2DPYFxCWQ/S0eCfpYov8pi4zJEMsX9xA
1Fq8MPloJ+fTfJuR8SrqHR8WCHGVAk+UDH4/CPUG5jlvAKO2hs8iUc2+O4MaU/c0pTGM+BuloqBV
j153vu68I0FJErJ5IuOuvuXuc8ZqKPWk0NO8DjfmDdsBhHis8jfutkgvPLfuygDIaar0hqq3OTcs
USiPFsOlQPNZXuYlTus6+WzBPZehPFSU2HefjVphnWd6mCtyBGO6xtZb/OnoNGvn7nWycqQxA2S3
NCVz2KNqvde4PboNm43fmVGW0rLKQelVe8URYO0GqIegdvGrCEb5uCXFlWvQgq9f4cuIVDiiphPj
oF52P9W5PHeu4ngtYkI/l5lkMgnGndam2JZzWoTQ+RaxEMiV22myiBZKw0zFmTeK0Mk1SOr+6Ycr
g+iGJz/ZVy2jHAI4CD81q3dCNOLAyBopYkK8Xb3U3SQQS36g/8g4txo2QW3hJJvVbJ1YGl2100H+
3sUt9HSwZu6zZL2nXxN+KLHlFfCohmwmM3fZyy9GqvXTCh2GLCMLpwofTsTEpgoHBC13oIcspwZQ
PkkwepbYq1Oz/wDZiyOz5eFTHfU4P0/d7aN184hOEB5OKubzknI9e8P6J0a6vlVxRC2K5Y7q3zV6
jhwAn0QEgxNh3/jq1YonJxVs7biP+qO3FAsV3+JY1Toxwk4skgJiekVJweMss0oZVI8tNwIy/UrM
+aqfCK50L/S7aQUSl3afCWNFkCXwCFW/Wxar4TGVhXkoBR2Eb5kX4qxH/9tppvCObkRs9jFTCTRM
eBi6SsNeaj8ycXNie960uQYOs56nGAJFBmJb0+6qfPeas28PKxUBuFrkNpFrxW5uxb+/yFQA4u7x
LBnq9pxitTcWe2S0kK1tEJ9ejvR1yNgBg6OXY40XuY7WF5O+bH62fuJ/8JaWmih9quZBIkIoo/IC
uQJvKWp665Xa6kWdRrRgzi1pJO2bubb/Zms6OwrKJXZ16+YgvxqpqdVTBCfx3HFxnTf2h7iYqb4p
ItjETlctkzSapEfv4iBljjo9vElc3zIHEZ+xEY2eOuT3P2SVjwvjXoBLLkiq6bW4yTfMmh9qk3tr
DqzreZaKllmFNiE76CZK+gf0bGNAhVmoS/HT9pC4C5UcWMHCOeB0YdNmK8tcMJ5Lh1szzHevRy7b
PKip9+NCCPvHSVXrZOUu9GvXFRjyUGFiqxGeHfSZNQD4FIUUoDGq5wChm18UiwWfyknfeRYCMXxi
8DF2e7dGp7uEnYprXsheufzkAGehntuhRpijZ7NIRUglc9moPWzivpCfTBkb9ltsJNdVzA95WLyh
iFpgjvKjkBHJHYoZgrS473M97jUGmoX5eTnKpi/NheotG1JRAQaXl8lWCGpJ6YhDBZviQhVzDutJ
OpuQIq+W4LJWt5EpPVrvK09GVcrfXuAgV5T8DEalc6Kz+gwHlw5p36SNaD8Rm487o12N/AWKwSAJ
nyLWtHoolC5j29TtSp1t8ubWSvOJHGnxy85gd+GxqsW9jEwuU8kCT8lvM6gys/wM6DRVeANMgmuo
IqAdxUGWvYOqQoNUSnuxBl5J2lHHHLB/brRgp+qNTME3PdHUzXUZ5Ss0EZ9sSQKjtBNTqMRL0qxC
vSCfVXO8dSnSQMu9p5x5Jw34XWv3cNNTAK7PynZM50HnlBhwmBQlfXcRiNn1t2c5/qAs0ayNvH2x
Hh18OEpnwS6aVOTF+sFnNXCFQ40Idt+yC47otvM+Zh+7bcBoTKaXW4XhRlzneOrMtxojCDPEtYCy
h2enmGlVTmlTQPKBXlTxbZzmWXC8GZWRVgU3hdd0bVg0kzcNgxFJujmpylVOywVQZAI34bnlvr86
5Ym8MExENbYDq8DyA7wE/w+uHT67LeG1TjeE/jOqKwSntdF/pj1uxZvTSVmpXTLWYgWbjoDB9utr
eV8nfLFrfhNY6+KvBUY3GSt4hkcsEqniVu/U473EqxFBXbOrbZRqcCkV4u3LbvTFAWGnVDTZBaHD
fL8tAyNuezi8N2cOakGf19zQ4pwAXwZL//zftPpvnuX+B23A3dr05KhQqlUYfnCRdS3IbWgFor+7
2WTLoYxqaGAV3YrrJhtDbou7qkjQiorwuMYnKUF1XZiVJ8H5syjneXEjSpWSWzA49YR6fVAnP7KN
C4GPAmeKjYl3Ja+KikxihIwovR9Sxy+16DkUZq/YPuSwfY6Hqr5MOWwxysMzBvhuca5yeqUyMz7D
4LsK8DzVh+6YyEYU/uV+Re+j5i2WPz5Dpi/XY4MWlgWGHerrpuoXZVGup76Qn1d59pcPRgo3ngeP
wk308fxxeYV+eohLW3Zd3NAe2GbWfd5AnmVXMec/3XIssn8GN/XveaF6Kr7knqdN26YEPJnY3kmT
v/MRbwtSeZ/hPfGA5/cBd5JWqxm5w6Ra8NGct043MFZQOK8AR0SiebQeKSk71umYdfCRh0MBbrkd
Uo8xsvFxgu/Sj2RYONZq91w61WWsfyzIia3o+2t4Zd/23zWrA18Rb2jAYSI+L4bwC7iTqQxa+VPs
HTw5W6b0qBf1NuSIrz9h0kG9Wz54iiB82XHXmYxM5IwYU4BGVpxeOjym8BBBX8eHNnZjMWCLOivE
krwTzpV/h31XqmAwnNCz5SzXIu9WEbwy3e5gavH1hp7fwYzIj0RPDc18v63UAqiFvpAtJymUN3hs
P00tqxjhrLfGpwCrgJLzW0lv5g5fjRpuhM6Nt0cmzLx0KhecV922sYM2oNOwBYzEv1RznnINtJEU
RFZGgGKN66IWd3Mb+f8K+xmOu6gOAcWEqYiQ4klkruF0j8x6t2XleOtEdUA2shuWiMAil4eY/r8l
qjj0Te+sbpHmHSMPEbomzKc8v9JN7D+KONxyTeSMbNVWfiogmujlOBkH7H0gpo1FlDnJ3JKjbpQN
NIwdTcESiQR35G4cP4c8uyr8Cotw7krIye6d4uDHi8AyC7iwQp6Pj7UNp+zVyJNxg0/3PtFLnfE2
whfgdIdFpsQsQay0xI9b0wt/C6H0+FbWVVK2Lc0GlsXtlZLuzIzpJELRFTVq0ZW6URh+dAN3yrvk
75xBIOX69ETXPIQrP9S1r3cY9WJFojxUF0xAfz9Vp+NLSGWlCetc1R2gagnOj0rWheXkO4KTQaPJ
h+SkPNos5XW0rhtdS0HnA489NkumO3r/B/SyO5BxnszJE8k+CKSX51nkQFDEoyhgPwSmasItGh+M
WEKG31WoxzkvxaZs0SnsannQ8CkAWA5kFlJLFB72MSl1xkXdlNZMdmzk4X7LrIlnw9iEwLjUoR4V
/AStztOPcXSlE9JU5bc6jgLHs4qhYQnzgYpXpc5ye7fnDmCWrQXzdXdQF/60FU7Gqwfro9iRZReH
QjA68FYxtFYh0XmXVHVYGbAOehiM8eh+RCjqJV4weyOlv30CXiH4C4tfjWW+9gVedwHWzJ/dE7l/
5TcpHZEfFJd4SAWSGJfTUJLw+LYW0nT08uAumrLJ1cSHGXUoTKy769k//hhIz14QxxOyQ/XwhN/f
3dyi13UBYJR+c0jHvnH8SgAg9mAwi0YkhkzxxnMumiYO1Rnjbm//s39r8RtgC5dRqF/9uo9R5U3V
KxyU4JJmS66//zVCAZYIajn+QTDS6cYDCNPE1gU2pgNuXRTPCEdAhjjVOcyiaSE12SZ55jQWSKGi
OUm0983eBhoafxcHNw8rFxLs0OifTQ9bKsy052NUSmWu3Q2z+jpxsbuUNULjtMdvt9fa3JqWwUzH
I5mBw1Sw0C0jLhLadbRusK0NuRJLXskG/SChQW/+s8oRPMs0VVyQI/0XLG+8fKG2skyt5y6HQYzT
lYePSbGJwHwMGaxqEx/4R798kc4AKHY9nYgtGzhgHiUSobzoUpMLHR4XwAVlHGMDn3Dw3nbGdHtc
81xHj4hsyCK9qhpyhG3JrY1TAZthZTwdVQUMd9UtawDfOaGGKrkI9stnRWBpmfQucTdabpiwDs/O
R6VqUSQjuL4RE9NqYGqqZ7VtgW78nElvaAsu3VcNhOlW20ZBAUERlK/an1XKLQdFGSfchfy24t5B
CLhGrB1EceSY6PWHj/XEv4iHeQq23QYehZ2gL4Tgbi8oaM76NryCiVzG8AWQ85eHsWZCgHYhVTj0
vLyQVxowSBP6Ju34Eqlg/lDmqmGnoBg9yOWf30NKYv/CT5o/LdOIOCljzZP2jEmgKJrpdI5dflx3
2tJ6v2uo9olp4Msb7aVeeCCsGuPcfQfpeapAyKLfJbau79XqONPNOoLmDbACdx933I7capb309vY
S1PO9BsCu0oTz5PBNqnnPN5pT9tz9ZCdEYkXsi0BCPEzD8l8bJhfcnglkKQb2A67E6sgrMb6vK0L
DP6jmIQ51aZHPIIwM9mz6M08l12Z2o9ql/7AmIGGGn6lGtKk4B5vaEfhjklAqn3DW83iOhiUtcYb
gBl32LEoTP6m13vB+Yn4LMfTPxoZL4AHfOQxm6Xg1aeDGqGILI/R9Nm14ui9fGv+EAz7c9QD/jni
Rm4ALaGQRiPz+XvMfmuvQiJrQY7h+vohKxerZcS0f9LuEVbSzCS2fAeGBB8QRhDBQTQCdLjBDyN/
zGR0CcXoKHcqbNDlqrYPKPfCigxpUv9mfRb2Tb+OlATQRDCTuvF9xBy9hgwINIwrP0EYoPNAsCuN
BsFJUZ+/J/L2B6g9PiyS7IcMW/kK1r3susTlEDHhK9ye3Ajp5UYkoIHaaEcO6vtrrolZwyKnu/8x
1KIBEpQeyuJvtEY/IL7OOngkxSRavFUxtnoOTY0H8EYslFyGnxl5VJem7jCiSvY+rkiVzo9plYRN
FfPj9RgYLwRWifuWs1cZ9mChdRNOlXIbT3gdXBH9fweSiPr5h/g+WR/kUzRYKx1cq2XCuD8WGfvY
ymBomxpdjBYysPiyAaewiD5o7dpFfAk6wiqLtRWEetqcBrWfLQrRMqmr/ZDlS8gP6THjuEzIyrde
w4cSczqhen87uPjEZ9SDV7b27VTmirzzHtAXMhbwRuoTMSe7uFRGC1i18sWeCzlJflNXBVYtZSOI
QB3psW2j+kHOkISSc5eC+9fbB9tx+zV0zovR0ohzntpawagTA+UyFT4Wba098w7QXVL4XaH0pGCO
kGVgXnLvN9F9DE45uJdaqcs2/Q6YgI3eSUDbjeUml2fa/X/GDk4602BLOrleyzZ7ELlHYJUpzdXf
tQuYn+z9d5wAH9e2YDT6nPYtKH9coQ80trFWbmAsrr/puXoiZTPbHsUuJUp1obARXTi8VhSca9f7
aaaPJyhdxZxCAbNSygzMC+gHo1tDvSW8QTx+gxreqBdHUUtTOb4CdyEPzdj6/0kScyx/GemyVUz1
BS2h/roszY6PRBV8Q7KQFbVM/nf0NnYx9AxXJ2e0kFFIZC2ZHTgRbKc2XE/9GB+TeT+2ql8CfAJL
cKO5YYUX+D+17/44Bj34lTaDOP6SmcIMxQnfm0/I1IkNnFhjwvy9PBMVqVppSEGutx5zJL6gTySW
Ms+a55nlcytozPaJs83EOkdp3pnwRj8DOsIhgWWCXIKZ+RegNEUvNnks/7vZZdC6EzGAgWEij+io
tx/ivXjQ8aQ/Mftc1RN0iGm53Cf3s0ycrHXC2CwwJP5whp1J9wxy94qbgVNEaJ7zEC5lQCpXJwqW
8v8F51o0kY2FUzULhXlXS8LYd/ARa4eKQOW959pfmgJ4uyhqmk6MJk1XKGFrrVmBTDOsxPmVnLoE
vviBwgiorN+2O80h6f6P2QPf2JQQnvP1i5CVmf3Ztk2nFqEE64lI6C8cnmPXvVlf5QF7e0Qss8l/
eVRyT3+Y60EC5MHDyoEBcM+3oxjy58i1ZR+V8eKmu51/2AQ3ia2NW+8SkDCmZRHSWx9Ak97hFfat
ViwQ+n5usKDWQg9AK/XK9dn/dCge+0kvCEWoLuK39d98eGrzF1w9/sZeUPVU5BP/9Ohtm9dZytkH
M3DQLewelaVDqilfJuol7nRTZ2lJs2FD1JidYppibDNazn1ntIBzZ1Fr/zY2Pm2m8xeocIsLGrl1
v/psqvjnkOoVNpJ+1OkZPnAS4PDBXU9PbrycS++9Ud4OHyX5Egf0nrUHeBPUgHiPOGuFlO8aJsn9
3JJAQtHfyIg1fa5xCRZH6JK2XJVjYrmK3CyHpZKsvdXff7Y1NSPLqAcZzlcmGDoLxfDuQbe4odb7
FPU4iuCk45pbLn1W37O/MGcam6NGXjIEZC9Odu/3jjgGcEwArPZ3Q2X2pdt7cDmYZoj4QmN1GFZx
aT5kALH3wPTIrUnEEzhlD1wxdIVnEBYpkdy2AISFXlPWQfqCW8KtJrhe+OUwjkZ6FlDHsI/taVKF
+HvMcIJKZO2GbvhBLbGS3rGYd39aRw3+trRZXUoPAvp4arcA1Iu5MNcrdNWAXzTAAjrnTxnpySzM
lvvTWs4FdOTWRlD2K5xBDyCCPaR9cLmbVoYxiJqzSBmVc8R2aPbUIGUw31iZ9vidjriCq3rYvSwG
KKWHargaPU8BA52BTxgMFiKU3As7NvVuP77q12vlr3fgZF3Pq7oPAxmrgfBTfwVzdVUcGrdpHHW5
QXNsQrcSdOSWwgJ64kA4wByN9zedimUXTu+ENxxxyVwXhDb+T1jkPZj3+mo26qdOvdsO4GndMZXe
FJdpkEX99ZfQGlsclzQH3IOhW8L6jkLMrJTMQcBof3Ep1/sRhKbdcOl2+X4mrETju6brlY8+pRdi
ReSbbNSSO53Rsv1LhuRFBmZz1WUoBcNqFUs8bU30vOJLHLPejkGKkXqRS2zAPyNFiuX39jRVqaUu
Wf2oJNumcZhwWJebo9f06o/nYcMI1fQLopfpfF37mokBMhmJcbKSVhmbV7CjTXJED9e3Noh/bcB3
ngBD+LvcyjRKfiL0tIQrIPn8AMu7o5QN1+p+eoXZFeFXP3mKhQWijHrfaKzsIGAFdfQfnFifAog7
WrNg0y3Zuo8hCuRbZUfWgVOt2G1ASoYryIotO7iEsRdqynwQrrIO7EkN0E+lJtPrTiGQSiZQkJjh
eICL2JEwNqI/CvJ0jatTjWVz69kz1oVY/BAPM/MyJ/l77Z8UfMlA/HlBowwz5Uc5K06fjN4LHv9D
+PfcV4Wavkis3qAyUhp1RnJyz/B5je6Fb13cSjIRaaZfO5/GaupBya+f3j1sSQx27FLVERbjfoXM
qk36mys0i+BRY3imcZiTQik5Q/1myh9oYCaJsLxpzDjjKNPDZ8e2UrCz9D8iHGg7C5wk/c7WXz+8
f6uhzGhm/JIN6dWHD9XnX3EdZHGt71/qZFJZ6nU8dvHA2M1MQTzSmw1kKx3pC6VXy7z2JG7hvSI2
1B1V2iXr4JCq0LUQbmQksHe9oiPsUL4Uy00eRByP26MBh0b8nXAYdlMJu56T0p5KpWrPOSLXlCm/
Cb5RBmTc/aB2IFJTMzSawucIxgK6+S36XOyqf7+hLPdhZzzPL5LP5jn66c+jOkARDcuv85ewHS8R
jygwTQom3ZYu+uC8Z9uhQKzXNbwfkDwsHm6PlZjBTtwUW4dqeJhBu4yQvwXTXbPqKJ5w/BYpXzPY
kQWUrs8sdaWJ4aWzTSS7v51avL4dcf5wVV3QFNI6oZkrXtbigX8dvhhT2+hX95mQzbbpwB5rdnYO
GrW7My/IhWhrmQb+U7ttg/q4dXeiJaYecj1FHckomZZHChbl/2GC/jR39hOEccrEsmOagpoelkoZ
wnzXVqxHepR4ExMbW9JI8JkqVSh7kduf5XGtSv9aRfV1ba0F6vGoP5zc/pKkbxE4F/hZJhVCzLmP
+QQYJk1tlDQPFsQaok8NUos9xfAgt+EXzTRBeNaQ9XthJKPVfVJx6dC1qyv5BP37NvdOWmPpqOY+
ykQ3qsJ2PC5vQS9/xFECnMa1ZGqPeGFldsiZ+hZFtnpiojPjYrVjF1Iij9k+8sh5759fxaFElBcX
yPuwj8rhRcrePpg5Fe5u0lITFWh0fvUKBoDkexNt8gkC/H9ex4VNRuE0zysvRGnXAgA87GOMK0xN
XW3S8SBZu33JeuRhwaUrw+gcNLWwhp0IMvPE5u49uZ9zQ4Y7haiAfZmjNmCz4d9I2Ycj2CL4Ag+u
uekvqV7dVyE5Oct3qPfu5IwL6chditL4UY1mWOk2lG3+rnNs7V4D6ncISrtM2xpnY0ixNtPR0w5P
ZolJUV2dtlGORtlDbdDLqD2QDjEM59Y2Uw18AX148urohY7/mucW1nDGdRUa6m+lH3UEbwHla73p
3YRjMKBvETCOx+oxdAvnwFlMKW/L26o3ly3pUPn4HDU/k0sTLVGEv2U1j+S9jIDLmytshmDuHqyM
Q8jCH9vDh6ps8U4YaW2pCQuWl6rOnipqyB5hOfi0J66OafWLbXPzKvOo/QSnzIthEAqUIfx3ZEiq
ipK0O88ojvyZmA2jjPQA92tDhZQkAyJgJQmAv3g/6VruMFh4orV+LDGEsYTBwQszePikT/YM2a2S
Ys2hqu/1XVa+WvlJ6/ZoklCp34klp9xickCHsHaMPVSK8QUf0EmMqoRiariYTVm7ycbdKGDZpS5b
DXuAJe4MVwOqA8DFZoOPEmB58VuYeF+G/sLXsf0arOWEJOFcA1nkZm5x0Mc3SscCaCxFzhTFgLHK
idA2yoTcWdtlGCoGgGsrQr7rktu9QQowZBhTY6hUTkL11rWpp/2URuFfm/zGfYHY6VVG5HTSAM6S
ftfWcUQVgWM6+cyx4buqms429tAlY5HLU9cFZ+2l35qa1Dk+jqqB7X4YoHR4WTyydBStOiW/RRQg
ZhZ+hmxLEv43uHIrHEZRQAhmoB1OQtd6owRke9shfKAK4RYU7IHzDWU02Jf/y3xMih6AKJcSp2AT
xk8oD1fxmufXV2pECpnOY9TUKOsXpts9Dnit+Ziencse06m4bdmfi3e7iAlYX6p27Y+z3Qh/lQpo
rYB7TPNsJJkehSxSEzI8FehS/45kwpFDdOgjTJz8tgkGBGLyT05BZcGCIWAWVkQI3wq9EUcDwpCd
JFQmBi6rhNGrQ0TaUD9rru5pZMb4iSFdj+/USlsHgXieBNLdoJLulpSRTJNUTnICt76hlWzOwfs4
ZYxfSz2x2g+ANIEPQUfWZ6oMv26y+s99G3GvcCyNAvYBbhNfUQQADltP34C33qNCVzKqDdN3nzlQ
RTDXdOVyvQ8Zaj41R7n9QLthSRuNTnZ1JOLsFzFZ+HOFhJqK5rgsMp9CzKUElXX1iq4iyQFYsxCQ
XkQcqIiFYzRWlgI8XfmHMgJmxHJPRoVmmjXobVfqrLxuKcfYpxtn/LxqBPSp93RQtMNOh/2YHenD
fMr8BJ7gNdAl4jkDm8vfj7T+5QLhcM2OtkB3lbfm1F1HpHAphSjlVqauu5OrIlNwE+lKJPpHh7y8
xwfmzit/qcZjHa6Po+85VOxNS9Ty9WC5o3C3oUV4qMsGX9SIlvQhoBzx/QDKIv4/4kBvj2KaEAfP
MUb7JUE+RiR3NGMlQ4xkoaTlgTp8woSf/8uxFCSK91uMlIJPdzIcQ9nd8MAbwQRcqt/juMtnQbBg
bcY1xnOv2af02rw/2K7SXWa3NP2fGWw4tWrz48Mv6a0GdLwL7rBPbB+ztQenAKbT995zx2YX3uXO
jp44SZYjPTXEZZWMPn3N6EmD8hgxymlYTTg/XZz8LjqOhxa1GYDLSUetkQ4xJkDKhRT7opXDO5gI
mnaWiQQuDlnUii/2ecKR2N2fs4JfSAsYphHs1TgHuZPiKqqrUmAminySfqteHgszsrbDXB5KrHVC
SAEcbGJ1glajs0m53I2nCWQn0t4jIoUyqdyabquh2k+zpKrTFZvQAg2pdS5/7gaJGWZJf9cPh1qb
S5GDVYY98jLoZhu8x10gzbzU4uFM0NF5KrlUH06813+gV5rY0O0f0z9Arp+Vy9EKpi3ANngKQPv7
ZyRGhIkx5UZYFUEfjCuaqabETVHEONCOGpKMeQb6p3aSXHym2dEZSFPg8wVa+tFYN0cSPEMwnbnN
+h5bHFVkWnsO90BJdFi/4vfixGrvL20eezFyYR7LiNLPOWTefXXMdh/K6Lp1SF/FwqYZdFFAp/Ll
kBc5PVATR17ZxBurxHCuGPp3EZpPI7fpmlaRIpTdKNSXanZWJrjh/nvvdBShy6RwM9Azu2VLnXT9
m7fcHAJK6PH2aJJZ9zwJGbO5eHKdfp75dw/JJifMezcX2O4Lu/1an3+fGnDGKNtF7X2Q1Pw8Akt6
ozg/PSwSKUmxuLBJpiXasto1Yjjk4NqPJUVXwgFghqAuhmxReOBxqshxfPkLFVQle9cxxfvh3i3t
m66XcGk921rIe3ZTHQ5cSNkPWs+9pLeVOcopBYdBFghKSl/RsPbBk+xxc5txhaIdEEg1mVMvD/Lt
zb4hZ+2wkLjpS+A+hGNHr1x4c7RMarHvBwSRCsuK00Qg//wMifPZ6KTKbRo7UaEkRrKd8drXevTc
k4JdksYsTwFOLuFlJ95//I7m9mzA3eyXP2hIen/jvg2MqIYK6xeZz0atVLwhNuF++Rj/hQ4vMwLs
4CJXfytKSmFFU6fmV8WEklfHwrfH6lWdSGjBZxZq3e7TJ7Uk1TMf06UuvR0El6XS9LjJFmxaroDs
5eLE88AE0it7y09+OmeWaH40RjpYQBCnhAsrpnEZ3xHeUnO6b4qVaPyZ6SGTPkm+UBkkJOqFngPG
hPljvlbF5TF+dXQkxg6vvUmQDlwi/h2nVXMHbZ/430rTC8bGnaaSW2bC0BuoKQHffcKL0uLl4ouZ
Cct53OQjI9bhmW3Iy6rUlAScDLJgLbq9ZHTzM4aAg4rgyh/TR7dt321QgvGbnIDyyspPaCQuwVGv
MX7+qtef7WLjUeaYygRMjFT/pZvNxVNkIptQ6SX7aeGc5cbXobU/xWOjwdumxncECLwevUL0ksYL
aGhVG3zrc5jBo4mRwALv1OuOI5/tQBYQxkQ6XwLDus4uOpl4fTGoarD1S+bMY3BgRRk3HuQ7Agmd
qEUgLb7T2svFFljtvaIVRV5vP1Akchjo1ekV8aibNj3oBNmXP6FgZc8upEbuz2wC6+joV8iMs6Dw
ORbyhYBVvJWwPHJgkTUCXsNh6t12Hur9Kw+YjNt3+CRZajlN3tY3omnl2JGpm0p/C+uBB9oSCaDL
CWHP0ae6EAmJmVeqZ5fIAKGmgu3/SyiCQTeoDZK1B5M89kBwAes7VSLMkLe/57dX1UTOHx00zYQn
WoISNBFpnWEiuzuRWxqZdOUYalLdYD1My220axycUFELIygpXohhB8KpAr+l6dYya7U/wLDJxcik
+V+wUCKCnxzeiTTO86URSETxFygmYeGVkgrjPaRs+glYsxR1rfv8oS+vo8xBbfAue5rZlqFgM1tK
Ivy3fm7vtRZmxG72yKII/G9Z29xLNce54ZX+zWkn7un0bDTEs28jRGHLUN2EmZVsRZ0meGF+RECH
fSsPTtofRLIsVWfy4xuMMOyeO7l26L7H0vSMpFof+jRGHLNAeBPBYnF76k0zU1xbpSsD+IeOyvOB
7tpnPhkCAH7xm0UBmUSxXO5eLQkiCNU54vZVsyayWKEacen6qar5PInmcewJuNbA7FbW2zn3/5fq
E4Oz1nt9S8d2NZhGUP7H1i7+emjDR9NlVNmMrPIOSGMMshg/gfp1T1PNvBPn4PR9W80Uaow2K6tk
nnUC5HzcmOT8PORQm4xXeB8jAKpbj3fI6PETQpiDm4JLtIrfGMU3HFBNcipPBlIdkm850b08/Ucf
3NCMQEVFSCoIa8oWwzWS+ug50Whc/a/SsH5CEXvcChx4lz/Rbcv1s1sP4RFz1qT44XIkfjUgta18
u6DTHCKsXXKY6OYZAln14wtnjNbBCZLGgEaOMqDX1SAAO557w8naw7OAFDaqs0Ai2ZbZ1Fm1BZg1
yCh8LYIYNdOIbMpGkGo0HjV1O0R1NeFujquTKkI9xlqKICZSZUrZuNO4geTRy9A2cxl561KlYZ/6
1ycemQ5NKmi26tGkQaN4Q4i4t9NqbJOoERa0DxP9R1BhCXA6QAONU766SkU5Ejn5+6Kz5nB84gF3
XuaTddRIgqepP/GTog+NY3SG+W25uYCVhWY9GUVSUJeFsaFgYNVFDEDVR25HlBWUjNcghAAQ6Ogk
SGCPU2YIQlGtrnQ0AltSR3cH/cmPEtNgjgpTuYDlOBBh8qyAmVIJJmaD5UGqAPCpxVQ2IuVu9EXh
oF753uDB6QzAZL4iOTp9rS8IfkOfnKwCjd/J7lASdOiINXPwAGAom5IeBkmh3CUQXZaQndIQeRe9
98WiVeAhu84FEKOl+ZVjovr8KKW7L8MHzmA01v4275oxMmsTCroapMqWW42JhOs3yRVHPlxDvXXw
D/K+GYZ0nWYZ5QDiWFKw+81lJgzYR830LcffVGVGJUE7wUX1nR+TdEaIuvuDy63Dfhb/LyBGW69g
T78/aSqDhx67vf3dcKjxdnXaiUVoF7BpLu8PzbigVLDjf3UzxgyZ/XB1YR5/lzoLCQpofqiwV/CT
sNFDQ58J0pFPeYxC3DhTM8J5z9yEdVTWn3t8rJMgqrTbLTP9+A8svKyql1v+dDo8/N2P4zVcWxAq
vRqDxlZxfo0FERFAuADicCEUPoRyGqqaBGbezhv7XDe88RXfpDpDnbu+DL/rIIAt247eFzzbIXNr
Ub4QuH+IyGWr1gy8NVc2xjwsXcstUT5X3d/1kg8yyvSw+esS3ReF5qk7WbclSIYLlDG6W5rto63z
IgrWIz138afLtI/nZw7rBuv1D8DORxMnpIa9eOkaYewmvJqLH6PlUSZRNMhaDcaiFKWmuddw/UWl
5Dt4w3izWNoRKZ/CKrLqdf5u+x9dNq5NV0mnP/2y7L7H9rrD3kodX/wuwH2mqsficNb6NxUB/t2F
XEK3I3HsKVtNFOmGbcgdPMPakd/LN1L29udILkC0y5ZvwR/h6VgBEy9qSBZWryuG1lxSsJ25zQ63
VVCr7dSU/JEUdeAxJH/TXSyju7MHB/i40bci9sCBhitEACofzHWMCHlGN8sQbUCqAeLmHa/alCyY
EXkAkIG4tQVGzk5xsunrLXOxj+SLG35CMnWhvGrppF0v59lSC7GAU1ysRt18FYqsq4MWT+6/mrJY
xnY4keehJ5nakl4v8r1QeR1wditlJq+nGj/dMakVxj9XQQ6GgRWAPdSeSLAPzLdbZGvi+Vwdaith
CuqSyqdmlwI9gX/r79zMygOSMyQVM/YFnnMR440e17GJ7caqUNB/vwUe6ixzqfJbA25/NGDBUIqV
/MNsliD0cRc216GmyaRxaTs2C9sA6IoFNVpJS00Uu2pEmQIvhfpVo7F/tu1U0hrPernhw9e7mkXT
WMJzDXQj2KzzrnjN7lri1BLBErVWBXxTW4omrPA3W5yXMi2sSTMejWRVqjBAXVjMamzj+5zYdrw/
g//HphEv1njVrlcXvFYBkJ4biA2zCTbLF9Sx+cp4jOeTMamw1XaMb/X4pk0HqLu7pJbgqjwwfFiQ
O0l75xjo1zT+hsvZlDjJ9g8pcqAf5Bj+PV9iOqdc1rm8to152bb/5FuR2m37Ehm8WXTaglHCqZeT
JO0xNkcoT8riNDBvhXAsl9e4TRjBuXsSgcE+QB+sfvYqrP4jQZpXaXVjoc7ij6M3xv0jHxHaFwMI
awsFFRMEbyckfSvNa5jI+b+SXH3ALojjEoVHJBAl4QF+E83BHK46UKnb8C/rYbjPOunuM3fZQCY/
eZaPgCJaMgjngq4infeE8XRqcrnEyc5zcsRcM5raHvBNx3wVJiK1FIIrrhLc2B7L7AqVj2D5n4CN
XcD5TcyVEy9Muri+b2gA+wLGf2m77iWb9m4MLvCGuFAkaSXP4vCxgcbY8qLV2ULZR399Y48jCkLd
dChGW+eYTdcukTQFdDC7sJLPph3sCNOaNbaS4/eLnJ1bRz9FmUJ3BHsuDRl1fWC96ObtOFeNPj3q
YAymADaeAntaGzltxnEr+iUB+e8dvXGMH0GOz7D8G06R3Fu/chPLO14X/GXEuBw5VudRUvyygtsW
DZ6rRjbEaG44UFsoO5WFy1i+E2PM1ndTLCo7iqp0GGOsD4K2IsiK3B5nlOb9W6IH1X6PLoF1IEF/
wBBgFWvp4xKaSREjnx1auGC9kCGLTpQC1kI4iBWRMqZsJanG0N/yGVV4LEzkbI0oeDQRNCZ8xAr0
R2pVZ5gmqIhbSt+rBf5wcCjzUsX0G30Um/vn8PjEBb+MT26z7kOiEQSqteZx6NhZ23w/X9O3x95E
xfI/InrfOJ5gcpBc8CQr2r8+zxOPmGLFc2jt/S5/jscX9O9k7D8UqHZIEAPfN0477OwDhuG5yVg/
uq+/sQGlg8VfqgQ6EkI6HGPR42BfRYAjRXC5/BQlls09xpBL494WhVUnyJsmK/CX/nAJoQebmlxV
140DK8C5957dxFU2g5kA7CDZWEDxftdgefnxerAoWmdmQN61A18Vp2lGKlhScccQRrwYSl1haw7G
DwUK07zaZmxLBeos+hZUWKbOuVbmi1wLjtFhrWeM7UX+/zA3hpg4K5LLha92iWeJLAgEdDwm9GF4
hdiOx+MnjimXSMyccRWGzPatBEeYR0Ts+adpa5i00tYW699pyw6v17l1s9sjL+yuX7ufMtEnffkU
C7BZYN9Oerh66fGrkvca3mORfxaNwkrXxJR6Fsul3dwCnNWAvMD9Zr4eeSh8lG11plJkUrqLEs3P
PKYIHRFXc9VoIQn8pJhp6M7gzMs7p2mgiury1TdS5XG9PEhAv4Fvw+wtPNvipvM+ftUvZ8bgoDla
ufD4tBDaCI8aCKaiCdFb/oIBsYQqWTxMfzzz3e9QcEETDUtLajptl2PtcJDqDYOHP6WRrkLoiN5O
awgA3YDKqITyeCzidyGX4u+Aj1nmiChAYgeSinPJvEEbmV0WCSbGeNFyn7+HbWM/sBC7teKEMb4p
E8uz6OEtGRV6MIEfIy5zqLl9XADMF9VnpMYrHypfHns1dM4j45WcOJVRi3Jb4ZP4dYAKITGhKVGS
1657drye7FC1HkiBdlr6wnOTmlnlA5nV9seGpM0Jdwe1rNpbDcAanh9AYGDOevPPV2SvU0hROlMo
DkHCb93g2FMEfXnFZtopdcge50p89epZNG48XieO6WnlcxDycdshjOJSFX+EvOKrPx/2l+sRPZ53
gcrEybZA6lmPhk/WDVxT1fTl60EG3HU06KazgFV8dgWWsKNTa8HkfNpiv/WhW3Gv/2NMzV4dzG/9
Wk3X/uNMD0tnQogDkwSNO8CakCB9RrB6uY6FWDrMzf5W4TTapzAog0u0yhylU2wyvaLRyzHUuUSZ
IoZTC5ybhHYhSLaVyw1BhCqpBzPgJXYzki9I5q0xuCY0d7mPw33Vxo84WPAI50KJD2XqLgx1LGa8
7fEyHhopMxmxfVtkhZxZAtOXn7N2pWIo0wYASGp1Mhd3OZvdRPsV+ZKd047pF+sCbe3ywhTdln83
TQBZWyLu1p7dVtoVwiKi2WPr6ivxhag71xTZOgikGeoB1v5Nxim9JYHlSHdgoTZiSYLKWlruODRo
DWKYVfG6lyJ3UH3BBV7eop/vwullFf39ZbE+ugtxmlJsjTPC3d/aiHhWqd/NDLCqi9F8iBnMZTiN
y9umpUWoBufIhTUylYAs7oQUQtrFqMB9c2u7cjb0bbzw/GEDWs51HLzoaMysUUe65uDHZyX+kf/a
HX5sL0U77aQHG3DV/xxUNPCk4cKASZpp7N/j7+zZp8xPCN6QkQ/yyo9NEF1COh69h4zqahIH4+YM
oacwEwA4gHfdck69e1XxvJzhxBxmINBdn9UKNIPMubrG6mbUctEczJygfCDEWhLVus9eL6DBmd57
of/ugw4VNNWgng3nb94b3ufdAZISd08dPgqrt6AF1lacrMmSIBN4Xb9z9wQBTNKMELzUq6S5JhkV
LZb0FrboPxTphC51ewRMfjsAFCwx0KabiH8knWZ+rFcK+Dei/L5GIz/10FCnq01ZVqAhQrZZD+56
gsDvUP8/ShrUjLGL/G0q/Z4o0veugyg3qbcQe+cPShmxQyCKna4Trv7GgbxVV7x5sS/gsJvsWz+9
1Zw5/RydOaoUt1a8fqR8iv34G7nFFFi0QUN0xrTqI86L7Ufx/GnXE62q628xreGYJIJRa1pZKPWM
ZVskwn+kRO0/XTAzsoK/t+fh/yj+rWHlOuSLmDyoyC8cXS8aLm/SvU2V5RzMKj7dSjTaHrRsKPfO
ehbC8lA70bczDG8KpZieOobKHkxQpV+48jumSTbBHD80rLt1JUuLz1nKkEj6BJkk0g8S4c1bYFLd
xt+cvPpxoUA1Z77mZsF1S0nGrA4Ti2hKhotGbU3j4ZsBSTKMGBAW0B0h6s4qLsZjdunqUlMsZtVp
aTpYEJ56074WZGuLydzTZ8fx9KFNsxjmMUG5hRBPdqrhIUROKFbPIwLjf1F2pMZMQGScvwo0rVmE
7PgFddc4t6plGZBv2qrTS7/gfgHLAHaGLmVJrGq0JJtMEIhRzSiW/C4zkPJG6AI9sfGK0fgZbYlJ
F/Ko6kN5/wTxuoVBxbrrpvprE24dpliGx+PSVVbL0a1j8GdtfcQ8Bd+V8QDAkdTDQUgDv2XrvgBk
3JfjAyXCyZm0IgHeguazkUDQbhwL7uVi4IOWdhK76VKDpquNRipSmccb9m3sbGxWoSkyRZDWD7bB
CoKvRaDxpxrwDpPjAuEnD5tks41E+qCnlB3KswnzkKYqHjGpNtoqKhdfKdDcYJRC35nvpG/Dbh2T
2A0LzS4x3phOctAmGGu7x/Y2AxZI88ZbZ5wI6I+7V8vaZOgEHuvzsulcYmk6SDN2Z5P1QJOnyjoI
nho6gFV1s3ShzS7eeHrSkLDXaoiYofvNmB9xl0vSrVXuIKplUnHZM5AQiKzGxrVO1NR58qnJRRpF
k2H2Lw8wzHA8ojM321ArPApbWP19VfqbsxTzarXOWoHPguYZWQiHFvRIyAz9y0ybQ39T3gujuQ8F
MFW4ugflDFcBPenOUKBj75/Bc3VWDSvkFNzsZevMGMnd5u/9Z0mrWf4zd89j/4FOhBbtfx6wysM2
PXxwFuLUqAO0UHtabmtCSXojzW3ZcVCfAJcUOi0QC/hQIXnJOeuD0kNPxgaCnlmOTHmRNlohhbc5
Mra1iSwzE8Y9UnxuunyxfV332WM27XLg8VLWamTI2zIa1FHK40njFLVW9Mt7iPXdoshVDWJ4BPYm
42XkESF/CcY/lrjS/I4xXi7eY9uBY7CO5SayIa2Naoimu5sDA4TL+hFJXDN6+MtvjwFG3XaBsJGN
VawsMpdhvfF/NTM08eQBza1qFvlGH7qTzJ/XlEexgCoc/mVnDZqlCgLp6SpqC4IkE2rGAqctTwTW
ITxvNeWppMiKAhVDM9qn19CD4v/8nRUG1D1G2lyhQy7MOkg6Gh+v7Yl4jKMFw8+QiaOThe/QXw+R
iPPrxJZHDKq0KRfzmv9IukQH7bMMmqKYSmi13X6UpgNWJbA4mZ/dTX5YjXbdve8MCksrxrLiMvLs
5IMahUxuC+SOOp5VtE0EBwfuUZ4tr6gAr78ADq1A1s1h4prc8N8iNOliKzoKJpcCFqTLdKqoyZHl
DZMQg5GTUcDqVL5PI7ThyPtixm5J3O2tBBwqGukgbLUJYrfcnoq7v1gGfo6rlU2ihz0wpI3JxUUN
Up8svRLCr43rjxblsp3J9Cm0qgz8hdELAe/MdtO3WGq3Ryu7AKlEkop71o6tndzC2iKjLSJtc296
9+juLoNMqkZzWhhnBMW18xK46qZJdqIUDZTps61TqbYcUY5x/KgGAtzC3ZizgjARnL/vkIWMBPYM
/sdXpve0z/eGRS4Kgx6bYaETxh5Nmm5lrxsQJMOrd4rD2+2gC6JNOKfLyrZrR0//DKqDmFG7Sokl
DtDaHUc18N5QmKuTORpsdfvRlB0YTRwMC/xFstZbDIcRmBn32SKAS/G46XqdOgXB04W73DrQ9DXT
E7HsRxJNLcnfp/rR9yaMhHq/2+OgIQryq22nC3Yo5Z7peHMBLiF7DAHK99NT8tQFd/zWL7t1Et+I
3ABLKC6fXhOrFNIoUn/KXCKXhmDh/tHLWZFgQCtG36oDo4elm0HoUKROuqnw5GH+Tw7uMAPNtlor
ZaGWH1kQS6Izgbj+SmpcoFdjZLFgiSuu2Ltxb5i0Fkno9d/s4esvUExZS1vYqUVl4kTKlF251R7N
HLRvTzjpK8ElT3OdcWpxKlWN5IoShf5ea7GRuHwkp4GNwUBhHe8TT8vD5ZtxX4uRPEjLQ357zFrz
Ir8uwU/+uBZZsoDhFAH10hw8dJll6f1A6kCpCAQnSWMjWKdLXNcElQYtWlM7vQ2Hy4tz1tvB5+YL
gtXh53RDqpk3hpYM0HBAFczG01b0+6A1mfz8Cgvy0FbZSG0zaH6nYMUQxCKwxb9E2+MYOvA4t+m3
biSfvoCr0eX0nrfhRVRDidKgwHXe+m8T8JisM97IAoG2UJwLTmywou+CU0zTp7OTrLxF4Eukuus2
01zf0dGnP75oo+TLbBpCBXlr+jYNDK2DBrUc8vzoXg7Nez4qJF8DoibIVfOcMWv9GFWMmfbu3oYV
kutCNmeenR5jSHV2D2s8Hya5z5l64BVhj1AApYq3IS/0mpIHEB37+On1/zl6SocyyFob87NIRyEy
YB2D2PXtz9fm7px/iRlK7hdFLMv11VCo7qEQQeKlfXmEuPZxl+h7TkPCsjqGfx1SeHVbzFwl4GEy
HYFjA1uZR2YOXe9mD1zJvCDqwSgfxR5aIuaYkxxwAG+PkbvwdApUQxEdazfQokf7yxC7k+Idmp6f
JjbjFn6tuHAa/gps3oG7FAWE4jie4jHCPG3XyJwzoEUMtCXLh5p+zaCOM3bBNX5sbW9A1/8kUdD/
FekBoWEhX9iqFXDWF3JcGXb4oHadbOKJGoac7ahxwuYjaqHRnwNxoBzDkS9L4KEjcfnb6B8dxW0p
oQrRCvFTXUKT3d09IxelYfNlJT1JqXD17en8kqrMGuNBiC2hvAijZnKIz91yv9X0RUaWTgxIy7qR
9iVVnNkhnfL7mhSTQF7solXos7+NIkabOGAMwvS5k7QMFN9cchtvZz2R5IzDwAw+PoQX/USpVD3H
LusqxaQokgIsws/9ax0whPHba6fvnf2Wp8jH4EAhm6oC+kG0urlaHSMvdzYSeQyGTgwZy7pNg41X
WqDJP4IgXbeMOpz6dJ4IQuwZvS4gm+2XHuUteb6w9CptpQuCbX39q8B4N2qUyBJ4gzlMegxkXU5D
OqdiS+DT+FMiNBrKW4fvLoHjuePICel0uVF8AonZzd8b/EhqAtx9EJJO5UgxHLqwvq2klArFUWdS
H3gyQe0vap4fesn2g9iBUkU6hUQGr0mm67g/kf/WHr+XH/dmqTCoFD+VF2/tFjj654Kl+gufTE9J
xqEI9hXtuFcWwopy23ugjnu4IVjE+nF6UyDWVUPa2CHrKdlKNVvEOcv2vpxveBEAtkg1ezd+OqMZ
QeFiPYhUS54xwOOZHopTJO1d9BnGsAanRblS5BFsEZUNtvB9+CPsDXpN9DP5oyqPseDWJBSUMOXR
Ww743BV6X7OPK8pMkQ1JFe7+to+NM/1Pvl/CY2E7bK4OZ0XlX8PMpPOW8C4qBJvBahPQwksbEgPB
nRIsnxh53foqSTf7babUnx6DwzWZXHCSi2h4QfyhQNdlC1sK5cs/NEjh2suq9+3L7gvAK9D/QHO0
dQqb4je1219iE8Orc3DFcJe+xYAVO8UFx8BDgZaBuU6pl9vn45KnhbjXiVYRPWn5LpAsCV9ZYqK9
r7Ni8bJtruDWebgKtKZhq6OJ12ViZbuJ3Kan3ySTEx1WkLSO6x1JbdhMuk3Sa84eYZfpYa8rTxeR
m+VfrlRJoneU5VOhC6eXxRStPJ0Zz9mtOvjo7X/xLybNGiL7mv4eo3TfB936PkRTHur7DEnnt0u0
MV7P2cRMP5xAC1gzQCxB9h946VDauEf64S/tHtx6ZMaOJ6cgKYLbhiRIcxC0Bl+jj3MhNpJTecHh
6xXLgLfQ3g8nqlaVAlCs7isGC0gVZIww9cuCYN2pdhRXxDx3s2DOd9NQR09ze+PBxv3R6vuh4U79
VzrwLTuc8FumiG1UZDEcUNot+fKdSFfrg8RYYFgcfPfyOdZ+GeVkUosZivIzs0DfbNcLC0J6d541
7HIp/778UCBBCRTRwOGLub2rnw7mpXsoeUvWkcz52ZSy+dlXWrvu7YxcGWJBUp7M2QZQGDifkZFC
jDJsmve+Q3rpM7y0hAJJ3f0kBfSUeokfNF07cDthT5sP7p4UNm5KZniH0mq2GNZDOpCzJ8y7kWee
UlG5PBnaKJIkoOyG2tPhIA7P1tCfCsaX6xuKtdnSO4YHBVOstQM2dtq4TzKUYKumh5xZr64Og9hu
P8g8fn5prIN+tlHJUGMVbnDIpWX6ij6eIR0YzJjU4jXl87zhc8k7PcG5yD5jSZ3HoLBRtPxKUd3I
/JyU9N08kFgNTZm+Zi0TgcPs/KD9/BxC6fgdAHXmLX2Z3N0AVREvb0sKnOZ2RmzCfWIfelLCxfc2
jkBx0/TacFTqDGONAZQsv+eYMbU4Ny5ZYyCHX8fd6J3tUNg0C2qA67HCUJLxSOOctZx+jK7+qmDi
wWzXRqiJZS76saDHoI8GUCFvOaT50XzfoTaraBb5OLskQCUNYsulfmisKn5CJNQ6IJF/Tzzcfs/n
E+extgiN19+SxbL7UYi+3RJbxKIj9ZIXCshQvGBMkVIHRWCAkb4w2sb/kCMH7jDk4liZYZPYzzrM
RiZM274XYENwPKMRRdC/0nzfIr5oiaMvzFGbKZ4leJgx+tfJat78xDek/u6RIet/7E0jf/376eXl
dnjxP2nPiacdh/ZzfZzz5NQBMry/qwg2D+Wg2KPV7WvSghzDZT5xfRSxnsrw4FVxXGpDOJkAoIoe
1xPMCLBZOKeVcHWK+Yh8E9fQChyesLE7CN5wC/lxFkh65qJRNdf2DHaAWotARpKsxhMca/bkLgso
4G56w2+8Xk5M4pOa7fKGLpMRkWymMyDLJH6jK8Kvwbd7QJxfcedjtZsUtmdoZFOJWMc9224mKb/w
9J4S6hPRr3ny/kbzGG9UT6ZcKAscPqh5qDknx0vAlUhCWLt5ZSF7zWGcZGgj6oI4I5nDzihzzkAX
4x4vwGNQerelRe8b2nzp1dIkgcLdQ+5a6I/fP/cKO0VWz06k/T+xtaV6AYhJ2U8xCdH7XWCZLZxt
f8KtQe45sgjebhmLaq5rrTZTcCC7B3aaj/1hOdkixUe5peDjFakZS6FcFcv34TA2WngChk2rMefE
3N2xe3zuVhXwNBUUFzbg4dI07P479hnMWnA839S1jhHyAQrD6s+FP1EvBDpsF/VD5aUMxYa5kt98
c5lJ2vU6esEkqzI4pYudbksGigj+0lJLbDTA225IE0SxCQujyGy9AYqXy/yxyS7EvHBIwwcNziAS
VdRu5VCPsZqe8BoW8m7ysrMmawh7p5rIfPaXvulSSXfuzT0G3fL3fgMowtXuozxsG1D7X5itQgpk
QKir6jnZS3hVGCPZxz7jVdRbD7aILCOkYXWa83U7WWodThRteOUK8EpgXMVAbj3xI7aQ5f7h/mnp
H4gWSJqY4N3gVUk2bHNNsn+w4Gf0UcQH+4VD3XwwymonwdPLuTspSDwM8sZacoZSZRvTzG6YiJmE
+P3u1d1Uxslkp1pVHrsQj2+Sn8nYlzUo7sB8DshYAC8RFIC1HQmqRfLYmyHpv4ik/bU2BgLthHtr
fHptW5fhC+Khn54Pkgwgqwl+62zK7qJP4x3K8772iAonc0BdCg4moOB3NUTOx0UELgSgFMGIUgti
DI3fQIuvRumvfq5ss3FM/jPvoZD/rSA/F63eWFZkJS3eX3qSDUQShJXexM9SFJKppPblXbPKYip/
8UFS9YwjvOB8e6obO8IYETE3TmyksDw8bS7ZX0lcgF22Khjo/hv2HVtBh3W4EERCgXX4RSTJM2WO
N9d1F50DwvbO79sMn7nwztb9GnYAfxZ77+o3lZQojEFTDuywrVDXORbkJljHxVqLwT0mbfAUde2D
l5E1rCIbfU6fvbmujTDaiGhwCcFPCxOquFeBvkkWVnzle+b+L6V6c2GWwpQ8GeLgnnijTOgo7gP1
FpFrgx9/Rvi/4rLSXXwfpucBtz1QSWAqOiAOnD3rjggvlzxElmP5TH1tAGbf/5bQr+aPYzUsNuk9
LExzYSByTJJaXuWPFjgxWhse//mjqbj2gIgaC6xYLhsS2w8Jir1wXvKQjVOSQ5QBIPzDXOn4Tkfa
oM+xUubshRDDa90t7AIebEgtewDytgYgNz4QBY5Kvz4ivGoFNm1xcrAZ1d+qF/74lhjAnynHIi4i
vPNkUU7IXBtKidXbks4XHyDu36+PRWqj8VF/CFnjWAsFZ0zfUOFh1SsZt7Z6IuCdciQDWKUGmyWB
WGzBBW4cHmNJoj9doSRzj1Tq2EsV5zlX9WnEtJ0DU9jXzpJtib6/RSI6ebdPGTI05nn66GP+Ojth
PpVmYz+XWBFU2IjWBJfuDedDvG9voZHC6T2CrGUDqvpYcfKdzAfzYB9cC9Gqbpe8Sk0JlyrRz4Wb
dU2ijKIcf9lgvfjYzxPzb/+8mZiZPT1+ine0RpQ1Pc8BArCm9Sj8O11JmSNJzVUhQgOx2vFqpf17
nslvrgrydZ9dFKEl1ePpyhF3y0urzmy6qm4AY1lDt6DUuFx5bUiboupyAHQ6hghFP4Gef2yylVdP
5Fw0UhynE6pkpv/rG9vd/bbDM+lpQ0rFkS42yqM9OOKFvMRh0VuqtGmlQXe3ZA/6eU/sfX0aEkYv
QNsv1YWz3Gdn+I3/PP+a4w9Up5nNY/CNnkZlRGAWdq7Vm3EAmTkV2iAyt4uj6Rqtn5bYcB7BoZsf
FYM98UoeJKUNyeclONk4WmSNPppvKG0jLJn90Q/G84PycO+ltrFQREm1kFS0NXNCS8OhOpNvUrhA
rAbQSrzqbaIiLHvJqN2EKeneHlVwXmHi097QLYtGTR5aVx7HFgLN85yM0d4T+jeVCjTH/TdkIcjD
xLj1P5Hao2op93Y4dRc+E80P79qaC03jKNSCZTK2/t2DXTTMvYgsGytCFXPynZ1vZeLk72uSRokQ
pz6gkNDh3FUcOkfNVkh6f+vQskQUl+VX8UpioEEvkWrriP25f1Jom+gG2wlxBBjqkqfiNcTZ1Ju0
9YcK3gxwb7A8G80FsECii3ywsuhYvdS6doY4byNkFQEDB+90fPEYPlRnLu82cf/RgeFr90bNBm7t
elCCH0Grv716bg13Vb22H4sjfkjikTHUXa8bzXbb10sigVxeZnbRz/JHmFpw0bvMZMFcN6FEvY2d
FlgFLmzD7PaCMoYHzd1Km0tpAYFo0j/R32FsaVNqFXNN6zvrVa4tr/juFJVQR6p2lH4QzycQih/N
StD8t76wp2vXPMoTbfbvMpebK4Jg7BLrfrQfJ4wVtxvtgmR7VygagAyTwjv9P5xPwB8S8Jp8b2wu
sX1rrT2aijpns8pRGQ/lX9ToCPix0QL2xflQ0j8mxwA9bTRdUymfNnXXyHkRicLYr/QyzqvItUST
LI6Q7MnxeVCaBCc50AcZhNdD9kZMhkc0LV1ZI2Wa7KsiYKKnq++L5tExTJi0DjRd6sKd+kfn1ktL
Sjb4xm1z7eUVie5k/u86wG3S2RtH0kcsTZ+xFp97fYODdCJeDm5Yu4tGhR2FmZwHqByjw0FuJOtG
N3lpWfw7iPbNcpFRhJLBdTGGlTeuTjRhFHfShCKyExGpM754PEnjySnKFWMRTl9k8Pct/1TKBugD
ZcoPQ4tD6IenTySqHraR1AK8aCKOLDXXDjQ4+/2f2RPp0Xtq1bbal0QJO0MY8n/BQki6NceK1xfD
j3xI2U42eGJjfNg4zbxxef9CE0roFSp2D83kDiBK3FIc5FMGZCZ+8Y/+B17iV7fFkUQzwapL6th9
U0kw4OyOz7sO49/pz2t6s0SStONzipsAr0E3/rZDrkaBtRyiHUmFYIdHgHkCSgDwYYAlmi7UXtGO
ji/M4FqFXgPV9qzmnhWGOnqTGSnASGmjE5UxdHBM80VMD38rePzw1bT43NvuqRTLT2qB3BvP96Qn
JXDTVbr6N+4yJfKZvsNxIb9ljNF+7j+cjbM50I5kmLNuYyLt8U7rRci5iYA63vO0yV5tAaIZXqL7
0RN9I11Ez2qeBKut7O5F1MTimvFYGPkf6dlIem83+i/0aJbm34V8JbZRDxHykWguRDzUAB5SwWCN
mFoVW20/SJVRV/OXCv3ZbKFiFBbC70+/lYPAKytwb2JSn+BfbSL8QjcqkpT3TSBiNzJJz8PzwERV
FYxBGREWFlO2HPQeLc04ZtnzPDUe2kCL41iXJ734g1qVlkgNQTVvKPH1YajBPZxlIQfmiwNcjHYm
VGBrQz/+MA/8HiB+YCZccdB4TOkxGz9JDgEY07PsESVFJjoaNQ2GoCyr4OuYRZJ93KzPRTSh77W2
J5x5DDZITophEr97utDmVNMU8XDt0LMhIN4tLNRRCLN3KpJtEv/m24jzaY+lSeSBfECPGECMEeM0
YBFxsMnqVjXDPFqwKL34rw4A6p1Q+u0WYL7alTWx9eEZDV98aCloOjvdMmzi5/fMVZkNx340ZkNA
jpZ7rbpZSAyPdZ6g5DHxikQfEjDwCTzOcHJH24w6XwtCwDa8taP+FB4O/mOkjNHC/C+8YUniSoXh
VkXtAalNNI2vqtNUDUDWq+ZfrezoZKXCvILOxxoivS4YV7fYuLIOnlawwKEMN8EvhmOaWXjMmtOQ
Wic/mJ7KD1vlHhsbZ9TJ1d2ElHn+rueDvqdiMzTXFDKw5fhhSk2LcLzg5zTkInJJ+kJTNB38ncJU
xAY3RcXQ7MyWorK3r8ic4tIb1eR71WdlH9K88GlzemBHgxkei36SvV0hFUyUFztY/APxMO+ElQxm
kbtusnGLOA5wF3HhYEB13Zk7AZAbpXKi+5ZBl0mix8Q/DAlKw9oDZgVMkdqJ38QvsVCfhjfvAFyc
CY6XL16kWo1qgD/9mufgWuAOdcOXAxGUE+wZW8gzZw07VshK7hfRHVaF+LDRKmjp7YWizW6LJ4+8
/6WYbgm5CjLehnpWrD6fYfAF/3x3/u0QrDkXKMSqFzI25w6t9rThBydt8ER3kfOIALdpCHY5HZ8E
K9mkSjDep89S50daDpmt9DodOyLMJ544stUZhWrhpPr23C0iue+sffsACyca+LrlY+1rAn1riPwb
T3xkMwEiOUeLaU6yjGqanrvXxws2wGtYSxZ50Hvh2nJblGowf44e6wCQG3565LyEvZILmD1A7nRX
uVBzN5n0Qg0L2DXs0cgMxeokZUO2mUPHGnvskKna0BdjoBKWPQvaHhIqTsBsOwRdGXlEzN86QKvP
9WYeHnVj50CUXtnT4KseE5X0ubWA2tvhRrRwTxNWJpMc9yKRVWTgBF1kQ163/ob0R5+lAuYOIyv/
P1oc38CehbHv0siPIuf+Xc4xPDbgrwyl42sYQvIwz1eBtw9rvEy8af4vVQnqutXLUR/wlA60F4gW
mON+FLxeetdHTq2/KmUkIEixzCV6x9anJzxwcFGy3Kt95Ib0/dBiHzQjFGYjWRSmBLr7bXxH2UTD
or/Dh0aLqW/be9I2dWm8UOFoQb5jvNN6g5KT6MYddbNgj8AVguhaZl86yit/GDsu0hszYcJJwaVD
mcBUCtikcJkV1cyw7pt4EJx7UxRwhIhZuCfZknP3S9gKECwbf0IHgUos5rM9JEYTofkQEBi+uq7R
RwUNiWq3EPQb8Q4MuNKokeERfVRzBHO/XnVb7IeXiz+owZwVhBKxGpQE19jVB1QT1cbafD8NXjJP
oKhxSO2sQY8kneC5SOc8AmwOOzV/6tBoStb8ZOh3Jq7G1DDE0kSFTKlXHVqvPWfkP+AG/4UkKiDz
hLIK9SbnTO/vA1yKCNxyliCpidT4nXopIIvso0ovsUuESnOK8F2X73qtD7rQTGYUVtDlAvrkq1pc
D1JxUYifphp+shefwzQI7V1nPBX2F1vl68ESLw8ffnIsOswLrU0bHtErBMjpjSIs7YKpAfvcGDi4
3tKQnL4pQ52kxPjl27jcTHPbd6APwd0RSo80uwDQTCAklOLGm+hZrMMtwa+TaXBeS497KO9et93e
aj7fLWOJJJdKemGt0SV861HpSO8WLtcrWQZBmOJqTw3ku/cVbK3Nxa4ItIGGYWHRBVSJAtTVqL6a
SrAHXn2EYLV86VVj3zIcrcgRoxZj5GVr3mLC8YrARH1c6jg1XuNxYPptJ1ARUSSeQFJ8/b4Boi0W
lcWmcIRLkjyRq8kB9miUC9uiBZVMj9W9lZZF8TQuby/ZiMZivJgBNGsK9fheeAgVto8fIBR0p9WK
1WPwF8eXiSYuysdrTDRqQzTtwMiYSnrxr3mI9DQnCkd0SyfmdBt3sGPiwnwSae1SLDqxqcmBNEnm
mGoE2pS1RWqG1ULVN1oQShiwn1qymx811FPikasOlalyAb7cafg3SlnifTeJMQ4/9HEAWvRVQaEP
XngcSM1Y+34XSZYsn/iTl+nBNdsXeTp1rH7G2eAsWEEPvCWvuSI7tiyViE27q8rC5QQ+wpFwo2zl
Ppz5CU8+Rc3QXvHdJsCsyZi6CHTzUqSMdmxNX1NGpKaTiSpc4PYgIjS0qx9QsIZEn+BzHrrm94lL
Rnkzw4hy5EDmPb1636Cf8O1W65Wa+hHnmULDIfTpJg06uP/OYI83aO9dYjzAcCgiGRNCkJiPvaze
iza80fWXlHdys62FOaFRnwyTlvk3Vk8LE1IpdGlkIfWqXgzovjXfbVvidOYAQ2SPtFpYRisMXVi1
pqFkGzLQV7TVV45OyA8TyKP9+nP1U5TxEMSWWTTu2Q9Muxlow+vEtiyMPtrH8PJptzXkU7aPFVb5
c4py0lU489j06xyWkk519QjS2SuEZ1OUJnWPIU8uLGjsGBfl/HUi9LwZU3Avh/NK9lj7Mkq7nsab
UNo8t9B2Q/iE6T1/Q/JOLsyMAzmR6buYAsCQcIjX2wZPwt+5rrodOEi8whJyeVNjMMPxIt5OP6gn
8F/iuvBJdYWM2EXcPNRKr1N1YfVQpIF1KRqtNDjeIBOvfyTcicgdK9psiqfSHv4pxdCmDsx8jyyi
PoMMlnbbh8hohkw3wu7UcQ5oU3T3V3YV4V04vBT5twkN5B4zqOgrF3G9l1MsQjc3yMGly9XLmgU8
/BI7Gt/1ozx3CW++eC/O406yf4fXCqic+M3oqZr7jZ3Ch6n4iCLm07WRid2GUjfHaDztaYYGYqVm
mFtflyLDMhRv4DkZ4lCgXiK6FnU6FrPiluPICU+qmeJ0z9n31Pcakabs+sOCLkUxkhn0l9xfQ76W
E6ett9eZNStZwtcmJrbtGI2fcuhdGSeEicNiBT4pNks6veDl+4c82jp2Ab2aSCCOfKnRVfi0768c
SkZ2+2JNmkSpUbuhRylxVIsnDZLUCHoPWA00JHrwUgHehg/FeJqKBiixdWwj1bX+XcXAxqgbSAbu
0w/YBb/vlZ+T1cAj7AnaDaLz2jbwBkLVMB+jKLbYhinE2q0W4YMpElaZWJer81SpcxrSXsKV4EzW
c4UG0KNzCRCTFz91uHt8Pk8MoHTXiC9TrO6/I6mB4RDQ6PUv4j+DIYpPPMjuhinaXkufr+Rc2l6X
tadUaNd+nGGRbpTIYqDcE6o4G/m+AewyFsR9CG/lQ56ZwI2p9MHG3Q2ozRuw9m2Uab+CaGCP2/f9
NxL4EfxXQcmEU3cp1IAzdmU7bUvmXSrHZ6DCNFOL9l/ZEo5WuiPgo4Q0aISfLjEua40ESwAoPpFh
kkAmKNr9torlrCfn3mQZNBLlv6zFHeyjjW0Ua8u+dOGJT8hVVG47bm32G+Qp1ZIDCSoaXtVpwmCY
KPdXnQyHw3chGGA+iSr+u9AfC6hXE6mWb1TseY5V441SoNcHNgWzpSZYuMf+4/FEAdX7m/E96vqm
s+0PC3ORw02dyvjViVC9+4tEhSw70AbjaFdhFE49zyNlnA7vRoTt7/IVxhLIrqgh8LJX+JV3XQGt
pNCXj4HN5b6cK8X+2nyRjxwDXVDib9i1Y5OdCt08qDxBzJx1+syQGNbigS2ohgOKzWbxKRPkYDzb
4kkbNGJtx8axD3PPG5TW8qG/nSSlyQT9gVSwdOTxFfGp6fZCXmu2n7qE69L2MXhTbeq/m9rOrGiH
7uRu/9GXBVPjKDdeU1ZRvQO+JP4d1JtditlE+PU560uAzFTqejwVCrixZvdhd1LGrE7UOODgZvb2
zl2rCcBPYPcM6JtSCp1+qprRbw+YH88Erw1/62VC93Hbwtc7/FTg1T5xa669gmGAOFrEi9VnrgHb
UZJVgMlv/IOCz+cxsKvDwz6Hm8yawAIN5KLmNpbpibUxQj/FJfYvakdHruJ3nWyalrl4LRiHZu2K
PUZsKs3QzLSQ6JWZoBYnDrJR/+1FrkFCX2JqfYRw3HdJqLH/fUZ/yOoPUZviCZyrEsvOeg3dq63u
aPcQsRDAiHL011P/Mwek2Yuo2OE9A2CLnqPEHN3nvlBpqMGD+6hJ2ApJa6lJej9CF3hMnGoBe9rF
Xe//v/BQjW/3kOFKC35MP7ozXjAqh/Off1L0wIpGn01A6H1X2SGS6pKO3y+yS50YF8/AFwDk7tge
eGTiJhzyK7Y8y47YLdxXlcoU8zoEK2ux3ltQcK9M8XxbAJaBsthDr3FxQ1ZWEUnJ+Vy2wBFxXEaK
Sf3SWMX3sKbliu2k1r5AtUKjsz/VAVLPp5llS61p/wsCSBIdWQUfTH8pVtyDxLSAEsa6k6YsTflC
MwdZ5R32Ohym0/MJnqiT/UE4QEHupuyl5gkNNMdHCUn4lKLq2LGzs6abqSO8t398hZiroRgyayGt
PTHuSAHGs8OOAtkKx+EQBL0tjDyVgkTmw5qtlfFML5IseMinSSTaFvpWpfHAT0f634Hgkd1FBbBv
lj5JFbZ4/cj5utJLucgM7em5zbtCHpIQE9OxBy1nnnimkXwJDtI8XcA3PrRLOhPu8UsYQuQAsKB8
KIvMxWe+oPnFC6vKDIbm6shLoMModFb3tLZCoKqJaAz5k5nx1GeuFoEwVueYjYYoZWmzwnr8kGFO
FXS8rIgGuyRwA1g+F7ke1k3Wok5WATyfOykCZguH6DcHDy2yax5OR9PMlRb60bKWzYlkfJJoR9xi
xHreWauq7gci0duspdmYvvvh2oQ+WRKoRlGoC3S93R7QOHY24+XPisKeYyACHXVLUMjnJV29C7tL
PA7lLO2fwIz96ZPdSdtOfrGmwlaoCY8+Sp1iYvn3vqLu4Duh7ZJIe9Aqexbvx238xulyFl/yBqVE
RjVOzL4i51lWw1O/tCw0Bfs4AGDCmWfPBttITBEIfXFX1Z3rCkFEhukTx8ktPV/Ll8KNd0N/LcRp
gp7e9RwFf6FJi0gXoH8Em1ROlAsZfaPlBjTy5PfeDvbUM8Q7x6tell/NL2U91mVr0zJDFuN6VgAM
LMgMC+tK3Hg98cWnmlw5b4YpJLHGrwZNx8ymhk/6QMOOQuYKL4bjc6XbqY7xZSYpIUUg7UTfM3V5
COWZkDxKnOvLvyzfOQXe1Gfob0cL79G9i3O72wvZrPhS5E58DB9J3jUvr9e9zE2z0qCsTL6YTkJG
lgHzrq2jKpyFkCUQJDmc9MFV2zbuI3Q8ApK5n30v6oZKCPVNJvn1oucc+OBA/ZsWnV7VU7v8VN6+
WLFH4TJEl3wUOk5Bkccl70v8QiKKxKBDGQ4E7L+ig6roIXeL2oqJJA/gkQBT2+9551PWtO7wjSZ/
mezWuiuq/r4DvNjvyvIx8gJ5E8Rj/VPy14NaJnuUp9I+ltObDw7LeKajFvSyr1XbvuMmgDnbDLft
rpNIQP1aKdarlYoLX4LDYkqgWzinHyQYzevGHEBorrsI0wGL+pk/1ZH48rHhA5vgu64WxcSO6BX/
eJMXrtqJ/Z6wDAqImPC1xRhZUAjlhJGXiCuQtlUhV+nP+cAqmcL/PKEahU/G7AuExbuV9341impk
QCSkqRtjfybWjGUbi7/myXreQA2McfX2YUW4lHJTaN384J2nIsYtu1c5BoJnYA20LcG4TPef/WuK
CjBbjOapvM3YMB+EcYTAg/uUcMScmNFNLpEH4VL3QelAdPqOpRg90CexbJU7+ud8qyIkE2b9y1Nb
UJhsc1wy66U2nuV6HYWE6E0hiwl0ZnMn+JkBQEy4UJpeWiDQzllN6QnmVWZtlTBhAq3WkrKTVM/N
O2pWo7YzQc4xlw4GjPiR9aa+HfINApr7r/K9aWBnn+3bwFgCGdNV3KckCmTFeHTlFLYK3D3xRO8x
FTfOwqbqs4JKSlMcOUSHFZyoi/lOPl+0iv3iTfCCrWPpimbOVvZSOB92mrsSBSMJs+l96zq8VaKF
uDUCWpCWa3E02niDGPWp/VBRY0pwLATggyexBqSUCRoGWBptIwe/SUsjEGnKWaUUyIW6xfGG8RX8
OvxWbj+2R3O/Ks5FLJGu8OYAvf0Ue8yCQZGjR7nX67xsK++vcfb3RteDmMRurUamLPIJUfAU6gUu
lAj6jWaSvKmQkTB21M7mIkvogF7QbxyH7BwPjR+mOSsCyuodRihAqOL4DKwDl4k2CN9kl6XERp6I
D/ncSCW4Mf0ZzU4monIQIrXxdVynVxNjkCERkgu6Ftz6ekz4ZngvM9cRVLKGWpB+AhxxyV4pNQX4
U8ue15V8I1M0o4ZMOw9Bi/ft5i6QaIBPURyoZwxtrsm7p32WTIYCogD60iZ4Tj/M58o5Atup03so
4whY35dQKHS+TGcvbszkNz+DcU4Pj7SGjn8rSUlzxIzbZDmDXEww4GWftisUzHXKE4I7sBx9rZhe
i9lltyymiGlpjxPKPAYvvGV+7fyeCSHCRC4vjXvJozXZPBf4aF6odFZYW1ifVE4fUo7+Xx7MnHiH
Rxoi059mVY2FP3d5OdZ6JSpLJHJc9moGO84mklZnynQQfGIAZdV/YNCpAV5FdpYV6txldxh3hi+T
og+RxdsccvgD0NXrCiTTB7H8BnQnoV3RLKZv7VLNK7DZ0P5UJ0SaCDpLUCDPaHdWvn1Fyuzz5MEw
f1AxC6E4o0pz4nWF/2M50amvzaVL4q2Ce6N5XVlVipT/Ak92CEd4Nog2nOJtzf6AeECnsd55a7Lh
GmRMpaKt2TMe84t1TB6nhDwPBzBIrw7YbLvhPDzrwSvN/QSkT7ZX+1JCDC8c3zB1fcQ1o+F0qH5l
vdFZkH5Sw2Mftxnq3g78lmaw8EbbHvwq5PvO83bMOsTG4RTFr03Nvm6/iaHIM96vLAH5L7eFU9Pt
CmBv/kgoh7foXILErfe+9J2HnkVPIp1QlbXDIvAnJmU0tSlsb86KcmobuTWE7xaQVSlW5RKX+F4A
JnH3zf6ri0lhCzBQU9onPBMT3uS5FQjmedN8uOaRSXUthNKlUC7AHZfpiZ4a8VXGGB7WLMk7+ShU
/TjGA8OiUqy+K6T+vYPIRFVX7xYafW8qhBAx4SmNXdew09lGZXwqLuIb1R7rAVy59o1rs++n9Rlj
IE2DG1fdTmBSIN8gjgEURKO9GdvPZ+V/Drl4W+iECL7Y4FM5uCsvCBPqTYTfi5cK/YraVpeTpSsq
nyZ6JaFfoHLC3j5bmJs1G+2BVna66QAgB8poPROD9uFX7jN8aX9V2QcKiunygQ0psh1JUxFApCbs
vK23xaGzeOnyT6MsG/40v0/4KYCvFvsfiJeNFq8tu7iGm1HAgXdyQM2RbR8ir0l2qVmUxrr4F//f
BqnK+yvv/s0MHSMGPaeEVoKWcEgoX0Hdnu1NJiQyfNldmDNmsUMFhBlpOGYRUtYmkn3jyI5evOWm
3gkwZ/++2O+gtnx7id8qddlmJAmPMzPwjzA8xU+AFIFeYyCsCC7wLbtHBQSs8rPHTIu3ayUZibkh
W4RFQnGAqXocxB0t4FyFa+n2TC582r8hGZXXlSpyNmvcag2PEiuv1jW/C2z4JOhDF2f17/7euWaA
d3qpmBUQIYgipfDDarqGEruQ2KNArP5bfAORj4+hN/3253U3yyAkpfGOvokEnpudnuvbJF/2cLXE
8o3uUPSnbH9j+HtYCfgHQVUi+3AbrHpej4+GTufmc6mqSPtSBmTqWF2A+TR+29s5sl1LuzTU5n9B
oQk000ILJsk5S234Mzq/rrApsmqBYmclJp6JLm6maSeQ1retlWWili9YmkAuznCJFFhwmLbZkRm7
SKlCYgSx5pzbbxJ9qOjZePWUlHdNFuP7jvgibPr6p0SVoqdt1DFnnlGDvC4F339hjvpdSmMSWNPO
i7E30kWOF279guMHiFIkYhUmDNZKxSZPU4cA7qUNhUZwS4Af4vE0NTTxDQt/idassIEOJTrn3eQ6
C7k2DSxfR5pPn95/77Eyo+uSVCRg9rpr/A8/p/JNzT2r7Rp+rxr3tVPccEm89LEyNngc0qyuuzpV
gQvbT4C2djbQdKmKul1jqx7J/Ol871Qt5ohsg+oexuX3pBtsl2+E+v7h+ghAFc+DZPWpUCLOt0qu
1qUvhiKe8ncpggDscJvXLC63c6C+6c6RmSIGWVRoBXYdOPvi2pSeOz8m6jI92uvFlWMmTC3Zo5JA
Meap+M6xzBMUyuMrKyTSeX2Bku76oOfJ5qEl+6E/AMwEPO315IaaMa3g5kB0Ttd5GKhVwiUF4Qrp
qO++XwexaZzXjAhb5JQ7u/JMr1Z82byPKK8DlYp1HM1/byM24ni/CpMSvRkO8NfNG8ZtTmbS3Ay4
ieB9EvCpFF6fWPS3K2ayCGZI0laFww2LxsYc95GQLQvzVuyTVus9DtXefa0gK4SGFSW3S78pU5Pb
IJJiaeJw57urcE9+KrbTZy6wWhDnAaYcjBr1fDJuPFHzzYMy84IrUlJMGbxxjde7FwUq66OegAiB
hz/6LpiqRAk4Ho1fwVXwrkH9zH8hjql4Sp/+ICE/QcmrJaFu2F679VNTl7lLSEN2Aeguz4Ymb/P2
xOrfhVmLl2t1wiyd3q/mVLxuG68vziTYME28P09/EGFoN9/BX5Hs3vcG69BAkEggoiTl8O1JKsND
nehGW/E6li92UaqdmHclZFWos55W9vcwNF29avlQ1o/55L9gDUry12hBFLwP4jaK+ZgwBu2vymc5
f9DSltg+GViV53xP9usL+9CGZJ9ZtfE1lpym3E4SZbZet+bknxfMbN3s3oSWc9Bwng73EyGyf/9F
aNKBZY9YvInj/Hp+hAv1X8Z61X0/GJI3kDwd1aPlpcRkO9OEqkBjaGMKh3pvPDUqaA1AZ3IV2qE0
kYN4bgAOcN7pC1Ib3EkDS7xFR/Asu5hSWoAZ2hL5+rjTbM616ZzMY75nfrZM5NNyM2MpMna3NEDx
RxnSU/vFP9U3sb+oyxFscJB3NDfuujS0XzI3MwW3//BD9S1l0LI2kxpwejZi8HJJwVrWwOb089aK
CF7YlJMWw4HkdaksHt3RFLelTHFWieop5E3T8+OOtzhpa3vRyXWJ2fXXIVqOmCd7LMBSRO2CzJMi
NjmMEVhRcmwpb7RnYg65S1ojeGXiPc5JcFrXIeMiza6AqZ0Exv3YN0SBD2SdIBRcdIoQEY6gkdVX
eJ8IoXxd570hs64XdkfIquH786qowTXYXQOBjLIHCZExVgxQuYxIMrhi726UPlg2LewpDnQ7QMhO
wbnqKHPgl+yBLYIKjEWArLtWyKNPZ3tZb9N//T/BFCkU4+OZ86vRyXZXCEjY4Y8DhE4WzX2lehhN
O0HEgJoAjC1stW8JrSab2Xuc5/sdDOcG2mzv9F9odoZx/jmcRBIeMAZwYYd5BYcQk0PVnrlidqEk
jwHakzUQDfEN5/sW6nLWBZ6/UVcU1R1BB+OhwNiuUeZReqy3iZNE6uCeNs0i2M9OtouFECfPbB1r
4Bq4yGcp3QaRBqFEwpj2mqbHVmKf/FB45l0DcoEkCAaRigsTPW2hKNu/POJiULCHZaaKxn+CoFRW
TEv/l3jt4nyXykMw3rl+0TOicPvNRbWK4xgFzIdmMK1XGGEnydfesBVY9C/UkiPZlSLOatYth2gJ
Cu0KZAD71sOMnXJhaJb9aehvOrgh3G/CAWLjqIo420F+o5xojNsz0WXQORdEwZGofNGQm+3w3p5M
aeUdU5YQ2nvagoNJe567GZtZLd4odVJz0y2Cg4W6cDS/MN2Y+sEq/yFCLc03tmhzK+Sdrhzdk9bY
1JrIkqtK8qLQ9yLf05U5qvKYwnPOPra8zaCt27eq3yOBxae3jbM6lAuq0bRioREncqTAWCaZps5P
lKckUACHNKf70rdz3CNgcc+lIpKsqRV50BF+JL2N2HKGDShXJ8XpUHRiaZmUksA2SjldA+SDsgMS
76FdZwdERkKVQUa+TYp3Ds/BjsQo7ovzGQSX0gvucopfMxN9WcPlHt0gM7Kl/HcGNv4luZT7Cjjc
AldSHGq+BnzMIL7wbjFqzRfk4mMRnQqzaZUb65JxhFTRGPKdjaMDWdZfW/YkA9y/f4QaLxMrOiYz
Qsx5bFU1a/N0TXqmtXVy4z3m0MFP2OfxtnyXm3YNDCO32tirm2RNlFQJinXYom1RMBGk1ivrF+6z
sp4Zj4699QW4KCdDuwpE4SCShSnTYebc8HulQPXeRcCSX6PUHOy19IIePWkMNrrBNWYP53E0QR9N
Wn4Qynl0B5NLHca40Ua0bKSRBJmsNX3jjFJpBIdxPEaNN3SZdWNMM2OiX+86b38YaTc1BJ4IRPUa
9ZkgAWLV1JFl+C7p7nHI/3T1GQI2yi+VVKwXitkMycyMgD2Vtt03Pd+EbHmasuL8gV2VV6rdRUOX
DVtJwgzAsaN/IVg+dlF2bOz9lr29Q0ZXS/ZO3Npnq+Pt16+N4MvWlrl7L3pwPVBHGAhSZvRztnNn
4mMHWloN3CpoFHsQ4syqSAx4bbLqBwLQl/VT2jmhSu1zCpg4rCvmVYS4yEAVgBYzl2GQdqG7XiC0
W1rgkk6unY+t9fqsjcVXpAEY4rXYG81MnRlFA0lirUGmTWM97HTpPofqZcxOkEPn6NAU/KzelOTE
kRtEkbJEx+JjRKF5TsFveHOYytpn8dphK9hlb5opOe0zOcvRkN3+EwUzcO/n7Lg6Y29pSxgk1QdJ
TLcRqm1cJEOV3jTkldmusgSXHhb1UPqRqGZ8vl79ZicOmT/yKx/1X0xcJXdUpsI/Q8Wg3GEeRluv
bxrLItz7DyzFjMQMIiR/W2sVyLst9NV0xXEUcjgVzSujpMGU4eblTB6fWR/FuhHPNDnTUA3eZzZA
gzjNlpQOuQc2cYing7gtq0AFZmN9yuIJH9+6ypgcRj9oXcG3Fu/LepT6GTrk/DosUlvwjFiz6ca2
Ip0R7WS9UXZbPUz8eyBzqjbHGABIscCvRwQkBvCUxpg7V0LIixD5Fsl+y3DFbvGIZ0FCMMk0i6m+
qlHiS91m9mjTuglM5iqbesyaZhoQuiCTw2V9NScpsoPjTOnFPokgXkTOn9FxpsQ8NIF5hpwqVOHz
Yvl43Aw2QoN7yvOzy9OsK1mnArjh/0DpCWtRkOXNvNr1gjACZrwW/JelHFOnYNu48r59Tz0D8nzz
r1WzxTItSlbNyKPOAzria1FJBILYLtjwKME7IVjCl6VC2DnH34fGxC/g9l1xzbRTJ284wmd7sZOs
JBCySGclHzqq4f23OfI6jXik4n+qlAW5SOzilxYG3OS6LJ9e2ut2sWMg1z90s4uiQB1JyIeuvecv
cjGRvvWEb19PxgcamCFOzqpbspGqJv4a6rBLf9x3tyz98dYrP+oZSFgoLK4FY9qIGaqyTnSNeaAP
2CwLgBi3aF9T6fvLIPj5SQcCgdialcZGm0dtzTFfFqLhUlJV0ggDL4LGh2XQa5NOmn3FGwdYdDO4
ZpCXI3fftFYYLRqdiXfywegDPNHzyKBnLiPn6wXIJXrNhIADZk+KsAR1yed5egj9x04KbHjkDkGF
NsUuHXBSev7Phq0yqVRdj8u72evkP25V2m4eJaJRatHZ/VbfY9TE/6sLawzSZviQvYqIYE+8chE2
+M4dfnfl/uO9Ojo2Uk1muxT91UIjKLfS6ACk06ja9Y2yjEHmFT6359HAnWFEnNRY4rRAOXtvEpjP
/b7CISnQ+/pWv2QOT/5idWXuoJono9U78BOWnDrbGg3aAgtR6rAd8+6ntPODrZ1zQzVdD6QtmSy1
8iN5cWQeBdGdV4hDtsyb96kQAtZA9Ep71V1NS6E9D4WYjniRvWA5T84eF88aP4RPhvZatBtdGznf
bVjaL9AqsCMcxG8gOCKY/1SESZaH1yJtHyOgJNTMvyt8XpJwbFLb5ASrzxLUmIzc6qpGLqUg2tsj
hcbK44Xv3yRFuEv5/zIwUMLC0A/KrGwEcpgftOn/gYZHaaWnnzf7NLlYXwxudNBtXQaBBndW++CF
RlpWPkj3QbnU2ialXMGTPE7yeMrMwxGkxbxtxNiVR7basXU9Kib9qRtkfZbvZceCGNFA0WxHKw3U
lgluFBywU4Pt6ubxaeava07WTAvHqqpUTCcqKi+gNuh4GkR6jPYTCVvR1688eo6RGZ2fQ5uuCngi
5MFSDucOh+IZAnh9UzY/FjZzYC0pvlxBrHJX7VLPZDifv97p54kVQtq8l/DA1ONo0ML7MDEIqF4T
efzQd1i5CO8o3Vwz9FMXlNc9198GGNu8n4QgIv6AtTKKCgI3tGND3Z7KSqHu8/FIGryzM7B8J2/H
8anZemdYM/cRL5sRAKXVqw+LY1WWtl5kEgpSw9tMjRQBT00Plum67l5BGj7Deah4q3mC22poMHf4
phLiFl9TqcvAjs90ECwyVfNjAlrqP0wPo1gTD73RZjt4IcN6pRoWpC/e+QN85gIYjomlIXUK0E/u
RlMXAJwI+4yBaEz8WBGRni3Ql18adCvUPgGajTcri+26dTdEHnzU2N2ksDYqN8jKzIvFZVMWuCk8
eGxE8xrOKwVZzbuepDvCKuNxar2O/KOxSl3mc+mR29jwOnSMgI5PqPvGS+t3wZmfIjNmB4OBchlK
QTtsZ9c8PuON2ZPF2FyXh41+aAMF4+xiiMKraCYgtR1J5FnxNr58MH798iQXSbF+JeX+mGoXkDQO
bYR4U1m4nGYOhm9SP8vKw8rMliXXXiuOa+VMG0wJIZfiBR/3ybH0607FSkLEefs8fdT3alx+l+E7
peVvA5Yq9KurVqHvExE9fEMHvi+eakcSuAUpGsHDl9iIFKgPCIPl8QjspHqdkxDt7UOUg3qude0L
m7WiOfKw/NK+2nzJaSd87gI1xYV9NYktAGoiSM4gfnGHUIVA59rOEXNIqKah0UnqWK3l9Po/43gW
k64Qw9xjtkMsisbwRM6JrTT8/04iTS8K+suz/Gg/I1t6CITtUbhqRxISGfB9Lt6wjHfQVA6dfhCL
R0va78wSeLGizp1u4WprCk6rcQw3pZeDdg9IS/VT555DPWdiXpelpyz3XTR8KCnKwWJFeSodK2MS
Tx1sFyD+PL4A8FotnMmjDkm+F99gZsQg5dFt1E71GsjfB5kN7Rno5zz9ZNbeiCzW4hzpJ0bse+qm
M2Mj7O5L1U4NlrFUhdgMpn1bBF7rFgeyjW0JM8I5yTmU02wZNcViHSFZALlriEGoSDYtGLtGKXZ+
hKhXCyes8YggsFbUTGiKgfN7HV6l88ATvVdPwrh8LsFMIIKvZE0yj4Glf96PRm9IqCjPN4Vwqs8H
EPxEasEJD9pps+rlhphU6c4AgEfCt1DY3MfUUfWl5p6e6KqaIxIjprqaVShxtExGTClS8mM9nT5M
l/Wy8u1BawfIKIq8P+8qoOBRqibEenPQidEUYbM/9FxWnyFKreFMMAQQJDylvSUN6Z6dLgky/Qm6
WOtB+W/SnWiFHpN7a/rHVoLB9jW+2r/wWXFe6TjItplYB5aDAL4GlyYeuhJ2LU5Gw1jtdFTO1lLs
mOmQ+58CntF6Y6CJzOtcXj2HLbbxYrn3pZyK/Km8vV76OYoMTtf/CDcZpxHILG71jJ1FGBJrLuG1
YtLQV4TjhfBmDk5gHhD6GrEmGYqDNQ+0nYm0w3T7rgf6BIuAgfHy7kY6TcX0dFFkpRP9XcCL+tDs
42rA2WBMJhlUuX5AEmIZrjhXnpyOR3tI28H9qNxiO2XxlGeD6IZOOHemm9pNCPXuWPHfv/F2BSzZ
kcs6tnQKC+eCKNTL9F7q3UWbKLd9m0Nyn/9WrFWlnLNCBPGKDIMyF2caEeR2jPjAJvd36ih46zza
Jhu0ylfCoPkga+k9eltI5nUo9isK4XVdYMHn6ZNTFich+B1ds3kYdvYEkVw+UZhFOZCXFJ0eU3EK
ZU2dPQI9DEbKLCJw+HV0ER8RXrf/CQM5LVWMSr8/YMMD5UpfyCUt7Ov3OlejbzxuVq612s9xQmAw
j4vBDsRLmGWkRLElMJDWsIM6TucAvVVeHdM2wkDBPkMBe28TsrAFB3qepb3b/fuTpPcCLbbdtggt
z5djv+vOpfGZKk6tt1AhTOij3MF70SuARsuOU8P4BQETAS3D8X/Shyx3jGjhbqx6JO30h2cuiPyb
Rc/YYdVQTnpibSlEpN+Qe+gIDHlRRJz1OeaC0WvGZxT1Gl1ZNP0SwyuGM14jnpns9n+MI6H8WYYc
oRWS2wECDnZZj+3kEtK2V2KzM+PtW1/gFOfMa7feaoLpq9X/Jba4zgjlgFjk+OHsz0wWAw3osIvD
5w1ZrBxIZbQuEdt6iivhN1QuS5+jYwxFWM+ucROF5IP9OQh0wJhaX74jdH2pzlA3Z/x1i7pDtoxx
GY9VUcoO019VgxYbm0IfknmTdrZaMJ0yeXPEzJLbS7JBo1rbuaVzFtRfAJxH43zT6+004/sVuWBO
HoSZltP7W/DIfJSf5ijn60UbDsbYYJdEGufOfdKwJaZSrbqwdi7yKjr1gHcK7q/FteCQ/JboClnI
BHLTK4dTTzBQSYGJBJq0SdYOoQpZhh89Mxd74nanTA31QPtIdLNlIAWlHwIIDCWs9GysspteGh4y
+7KWRouWT1wQ2swEk77O0HfKBvPXHeGtCqw/MknkO6cBLwHzaZu2Ef1h26ylUaN/2c9TOHwTw9xp
reKWXiTHCdsllDW7o3+GQ70jkNV4Sd3Ye6I3FgH7KRf/Q/tq8r1oeCr1GWQWDEHO8gMBfjIouSdy
IEal/LjNh79hcCUUebj87dOgp90iqg1L9wgRK/2ejtm7zl4k6hpjgjAQSM0piqeBP4Hebl3rwg5y
b1o96ApVaeYL+xEBhFVMq4Sqo0wuYtw2XrHTY4AWZup1pf39RxW/O27n/YSykblnnFkX2GxZ/Ab9
X7UMygcCwONyMN0NktD3ufORAD47SX/hBZPAIY8HlKwRqHo2iCqYyaDUS8Yv9m1GNdV0hV/AmsHL
jK6gWVtUrgQT9MOcegbudFZWaXXwrI5BehcVC/Of8YLemKR6VVghtsZuds/vfUkPgdXVw+iIce+H
3/sjkGTewx63+F0er7o/KreMkHc8kHzcBz5murVFBz5Y9WFU2PXrxAzj6Rmiasdfx0AnfH7cuBRa
WIz757GzID2pOLVrorHPspob7HnHOR2xtqFT5GeqwNwzh1MDR4dXFo0P+LhE+B7OJcQjM4rmaNGr
9gIayQlh3YB+cKAKqOsQsCP7OrlFDAZ/AkBiq2R9+j45X9j46goPp3OijAzdXZyYadFWo3mXW1wk
ipXVIrORo0+y/HnKGL/Gk0hrcahEfiaPX/PkVzxoSeu+RLSM6vYExuw+u1hpE3ulGgBfcIXKtWZi
Yqr/de1ukuFdgcYEQn8p5m1E31L8xuwoeGShmjy/e38WT3QLCOhtH1PPZ4ZIZik49UyTw6/G/s2U
RFEVXdkik8/aujnRQDT+3TVhMksu6ePAjMsc/qDQ9dRdQw88KJp0+1vpR8zzY//sbyB+QjF/ICCt
uV7mj11/qlZQu5Jy3CIMLlTutKdYmnmHrfVXG/1PGVm9DHtJGMT90vLWbC7P6Zb9/43SyzznTYcw
MbjJeEn0ZrFrDfJAKww/uy068/MdPFyEsmyPZdOdvu6YOC/xAumG7igA1ddUlNEfynDqu4SVsivv
xPoldWBEBUHOV6VRqLgzgz0haZAYseqBCK9ObtvcEg5AYl+0kajmKDlL9H4IdW6BIuKcp1xK0Ihw
3t1wcFO75msT4IYPZAmYSs4ewDiM9sK13/YDexHFjQMiWLVXwJzDS1jXlGbpSgr95Jp3MUj8k/OA
4z/ovGAO/hLHvNwVwtbJXxIjUWV4DSTLJpYHuBycIRGeEWIdRw5p1GqTXRBSbHp7RJthaEejTiSc
8ELdN1QFWgH62EZyFar0q1/hOzoCz4sdAqizdrpT+siwrMuvzhNXyEWizldXtKneyCVnce7SSVlx
poQInjUCdbkZHKcQSb7AhM6zWIoDeEDJxql19NBce/rv06P42uinAqM9HUFMlS9f5DgG8wNP41X9
Oo4GfVavfqNkI4QU/DGjJ3aJbmODMeDL9BC5CE9S1gYhhGN8/ycpkAtHMb6JwCakYVVaEPwkbXbk
/hZMfs/XHtoitsM8166hkhZyPR3ZS1iBQIDs5PoY+SzLRRK8kSQzmHw/cGgeyJ0UzdVBOdiPVZH5
Q8nPopKG8eFnRcKSkK3z+I9CAawpIxQmZuzqWtIytkiYVnuVHMiGMiPQ33ycJ9WD9XaqEpFqttN8
idtbZll4jrueq1BwiO2Jz/PpbtxSDFSLjam5Ae03DEycdF6OwGl6M6Vs3CaweOaDk4iENxE4MyaI
7qzwcUCUDeEDo7WN8+1Blb8+emusVrZ8cHIZqZTxJc50naNTdZmATaNbD3roZXDVnXTKNJBrOGKI
olO2Y9SKoytFH9VJbpyZDFS82ftKcLJsM3nGijSrldKUoFEO7gVfjc8YieYLYTQ6am7MEI7fMSE0
/LE7/uAyzcer3dD/4FBjBTXlVD7BvOk6K8cBdCpPEAYBbT8UnWg3hgVeiSAQ2lYjLGhLD8hoQxc3
9TN0p59EUj/t44QhCT2+iLpayR0KbgbxDJ+YcA0EM30YGz7Ncj2jZQoAL0CWZ0ybCP9pYTOvkGJD
SJzrkfFi4Le5jwJ7zkN/dcE7JO1pzAGEX42bItIHbDXHAe7xnLXL4h8EjUw01piN6A0s4fJCS2V8
b6iYJrUjJ4Y8fyB/TNvudJXqeCQ1fxv2QaQ2Du25cS0GM+SQdRz3eM1Yh1GWZmHy6kxUmN6NxMN2
mLcyGuQ0IQUpH3pB4UCn3ZP0HGdhyXA8P/xStrrmvG4ZSiJRJIFr0vDVLgEE4MprmhFNgTLrE/RX
OChqZZcwpdEZ/yPwOKUnkCXY08RQlP1uu8Wuc3BbtoqF/Ep/f+zvxCaCHIE/Yg7sG9LQWNwbAMkC
FshkNlsLlYd+APz+qLPGZfhFteC2F7H5w/Lhxqq9kopU7cPMlX4tCB9cWYqsfKST+PvIVr9jgwhF
AMIFSyi05BT98Esp0porwPpGAMkTRNVFfTqe9gvbQ6T39hI1WfGLJp5Xw3/XIa0PHCKao+a5jEQH
ZJLuAPg6AvyGbMmniAJ827JFbnkQy1p0KZzR936MMxqZjOa0Eq+8i7nuIvlKVPadGZmuEeKn0nVd
eryaS2nu8kQUH3cVTK2jC7K+CuuFbesLR7giGRUgi/3j1h/cuqTv+i079TgMfuXcgvtmvAHgWk91
UzOXxtllH2IIPzcn2bQqsJnn9/exxLqYq3sPK2yPa9JNps5gi3qACvHQxjsLftEG8/9JxXT4W4Bq
rsN7XfpqCFPlvhib8w7CuPucZFTkXwsmGPStka5ghlqR4InFbtwjfvCveXR4J18akiwKiTJ2w3O+
6eRipHKuxfuJYUd2j5u7DncY0uhWprV61R7eGhV90joL91kc1I083U4DL+sdEHIXjhBLy+zDSk59
GezP15KjMMjpaFrrAs/dUpwKkTalEp2hO/LnKamuxmkt1JQK6CezfdXsZmEGpQiPAj6l2D3Y8YYm
NM/pyrg3KATC4GEu89S5y3u9UjnT/DmQS0CNY6R4ubCGh3Fxy+OznPluSL+uOOWxSH6e/mrO/fa/
Bhn9jIa55K7iBO+uHV9GY2puDIuPlgo9OaySE+Ez5VgsaH0oB4D4qq55h7hJ5WTQarbL8xwfdlcp
4VFsZ9jG2Ki5x7uvSZnnz8oQGNyK9yhyo59EGZJj3HQaR0xDi5cxcPuGRc8cIXv5anWJZQ9jGpiO
hm9qNNlFi2ySDWhip/hJkY9gYfEJGNrAAOotL1iDNhs0pHiasiWbHyN8MhTQ3U1065EMcLcxXfLO
IfwqvFyOKYp/9MulmkhK8xI/2yFLZ9yvG93YwFi55Z2czdt++odkJaPPl8GXETCV2uY4IpHp+4lf
DowjhlPrCi1beFESDMGCC2CBeNWWceAR/KC5zXtygfLGerFI1P5mMZM+Bb+9OkwYFI1RAW6Hr2OK
LEKaaI949sZeEUcDaUPLXwZcSkGLZ/AnWQs8aEAOI6PAjh/KI0rtCfkxs8GL5JvxrY/6x4Q7D1ni
NCfdfb/ZDq6a0UjjGklWFzZ0g5Hfh8RDHxVzPDNcR2umXd3f8lOJXTOapKjC3FJ5MocZj1CJ/jf0
Wk0/EV0+Whc9bUUtaNTWXgy+seOfTYubChnTaO95EX5JTgMstB8fsduKX3vjC+hefW/oZ0ydECCH
jDor8GMAWHOyWUAYPBtGdKn5StauREtM4tt9WsWhujwIWlAJUBbzjDODPfeQbMx+9mtqtPsTY4eO
qPHFVC96WMWuOoK6LBdwGADeuMPcCEbiGpbvMhIDA3n3Diw0WWoWwxC7j9c5ZXLH+OHZhBg78dun
82GFeeovBdAeAGQ1IlV96V1aLxEQjbCEQ9DVg/+BWDOQIabPUr1h0Jvw/r/0UyR7I+L6PsGDcqxq
dHspZDvlv4biO0yl6Dwm7iyxmM+xLx14d4mYnIjivacEV6tHz496y1f0rfnvqFWgJtZKA0J5DuXP
ndjLM+kc+8oZ72OakhOaAMkyOdrt4B8f6f6Lt40ASDTnYbvI0oDFKKj5nUKBcNkgvEjEYmpy9HAH
uRhK8Xx5T+qdoDRPWuQsNDsbllJ3+mKou6Ek5jfpYIuduYwEYxiNxWFzMfbUNQg1/jwWOSZQfffX
eQR16aXY307+evPfUa1KAph2aRelaogGT6SCgLH82xFRqNQBe7ruUaxrqVoZwmxPoa7e099kyoKN
Z3/YFA9DhsF7CjOCa0uYBx/+bzZVG2k0Ss/+bVrJ76MIJ+VNnazIkkaDkSVcC4TpOVqkIN4OFXUN
LmJ849J3AnpLKzBOHj0ikRjA87wKSgaBycL6Ra+fNuUKvwqQq2NRiHtQUZaTsp52HOYIzdEz9Z/A
Ql34X6UDSxvkez68y0Y6phn2aPZLkJBbxZfe4mXooZGjqmegGBU53VIuu9Ba+hBYwanCD9E7T1Vk
2I0IbHbDRITbw3cxT4N/DXrpcOgAdHv6MyOa8u3dwkwgLt+C7iB0oUkfC6eZ0z6U59qFOIIzhCcu
+Wleu08dTiDVixaVZzzY0djIXHWvdzcCfh3ASp2HBuEbkw8rz++XAbnamj8Yhdz/AlQn9La+7wD5
9Pe3LeoG1OG/hux4WtYFMP6QkZ7vOcOoxdxBvHVUB2LF6n51bf6nElpP2pwJ32TEw0B9tt7B//Xk
9l0M4G03hu+z/xfkHAIjz4wwAjFEdZS7Omyw1/x90gFey7pP8Cg2xnGv95jqHJ99h8ZGgzY6WDxk
IkH0/072qWCso8jqAsHzhaxFPJdMXF2GbYgzX/X4+RZTPPiJebnJUqtqXKcnclri4Veo4LwJYuE/
od9fO1LbeiytCiD6CVlZADsS3gxdgs3c9QP+posOC2rX8QMFlrxnkeo82k5G2cD9TD1yfnSjkFiP
GBI+wUPYbgVvjr6OkWdwZ8HduB963Qvu0bKCIgU1I0Gzutm1Fcvj3YMMlgmAeIBxUloW1zVUg2i2
Xm43UpVlrIYnjggURhEeIzSqWwy2h0twYJUI15h7xHHmCUtFqnIkfIIMle7XDMhwFgDmVqhsq/Vl
lEos3Xvj44BVDNykbBmmv9tyqY2yo6NTdzkBQBMBs8CqWvfauzavuLFwvD52VyrjpQwK4DAt6VJ8
40JBAr32vnUUTxvw2pB/4onaeQmZLvL2hbBO5ShKxDf/kul1ckxPsDDi4wP9OjNgS+QDwjjaNNRG
KJkJ9gLl5Kq0WCOUlSxGCwE8sjIwZ47gqQYCkITbBrFsIT+0meoVDayHDrJOPngVksBBr4n7D7U+
oBl+I5Uhu2G/qo0dzaLeQbqKz3wxTNUyZ4dduNUzhDm+J0NHldP0RV2GLMq83OBbhBm43ErSta8t
QixMACKD2KScPscqO+3aQCyufnmyIGZUGg8eDUF4VahLCrxv+tdPq4C0CEkk72yCL+TB597KRYOb
1R+3l3Hmck1tbo6l1x3f4HklLPOcvUwcswkJX9G8kIO/o+4sH4h5SxjMpVAhLRCUGcRPKOjqxa3I
tyih27Df6ENT9Bet897IhnXQEeyzN2RsiPsTqWl4zk0jbKqILzkYxZXpqot4zHAen2CL65sobt9n
Q8D/cj4t50dEwHMGs5dfVXZ794Tea1GTw6gSA+wOqbMs7Vcto10Kw99y0xccFfUBSxw7tJK60gC5
WxiB9rW0WMoQidTRffhU5bK4GWk4e5JSeX1xL94cQRwbjX7UJfOi+sVV0xW0HOox70NXgSmb1jK+
npmtup23NC5dEXPvc2aBNyUkJhgOzcI2u9khZCzcSqocaie15Aw4LbCYfgue9vKaEMt/Oo8H2BwI
UvmsA2Axfnh0/i5KB7zVZi+UqL0J/jM739qq3VpP09mk84i2tYVF6rhswrAQDhPPmmbr5xVC3Xke
OBjXgA4dGUm49uHGzLq43FH3zy0VVwpM7ZqQkYi1dFQi5F6ZI+2D0ll1LyhgS7mD/U9be64mpM7K
VbslvSvUpecRkYh9wyJqNrj68ejQ8hONY84MGBIXBOW559NsLh1JfFXklbXvqBD80MhIxbGsCVAI
VXH43zku0vMdh+Itjdgyc2/rzA1L/ItHtyFb037+fJvmzLgmgUSuLDI+/ko4UX/k4TWlAN2AZ/qG
qpKso518yGzuSJXSEOxIaZ06jD5Iw4Ym/xkOBRpKK7x8NqefvdHi5k/vvJaNPjpl3/e1oTPLnQEQ
AMRPdB94WqVnqRox2P/qkgxTBvUfwusmw9wvaobDL4MpV1dBK8utp62XnTl7X84fT21zKiurBlvg
Ch8hCDmUuKS+2U1JanHR1NT1dpou2KKRAReSJEsTnNwsBfP/Qf72loLFyihI4VnJ6ckQ16S4V/g9
uWZXfnvXki5LI9O2yt+dZGfJKo84V9kBFXNFidbSpiVtfHrCHRaVxNMBekZBRmLvnVfiVcie820/
6Qg4IjmNTN1yg33ROHIz1pWTavgHGt91sxKWD5514RBL30uWl9z33Nvh9gMRXQxvnwOUAAbmMWv6
F7nCwUmgVD8rqh1ql114khlo7fyUwO3QH7YEReaeFU6Z1GPjXWezHBzasJ66jwBAH0kSonPvBvsl
o8UXE2aNilY3r+Dvj55WuUaSlzP41GCCbuKWMfvdLPJ7KfbxEKoFetIQ3u8q/pZS97qpymddtqxR
IoplQVlL5F8MjrlGtrWmHT1vTz7+4h6slrFy6SU2qTeQnDp5116Fqa5MxV0/YhQrDqdAnFbGeIrF
zFq7ODKoJtHlMB4dv/kGz6srFRMHSbDgG8QG6wM0MxzFc3ANngj5ia1KwNGVgJ5XzxAHRFl8K7ZR
t5PHpROGQrndsQpaXE2x2aLiP3hwYTfwtDVGlB+XU7dbLLKq86NSF3DXs1U/go1qGGQ1rDtBrkHl
fsI657hwSIIYIXBPRJ0f4qRAj9xoFwGr6V+h1sC0TLHOHmvAPY7YTM6DL46DfWtVBMxt5yH4q6al
MaTCLQ286lANz8hqh487ZtQTWbMk1pXVv446X5aZr2T1tlpbYu2NXmVl2Tyaneb8F0hSKaLIzaYg
yNE6Z7tcC0OfT+jooz/CgrIk+8/ZDa+8GJoJAPVlXYQd9LodWk5787LUoumrylWKJGibipSte1A6
a55bJAOTcFAgwOeXlofEMD/whZ6jD7DgRh4Pf9pUMaS4CK/kDlCzwD2gpAOW50BQC6nfxc8ocv+m
72Q0zLOv61vJMkgIZBHpkh9E/hHYl7ArUhH5yBjV2FyRMwR1AC0yo2d9HRbfND1e4c2/iu769jPH
OF8BJYJPeTH3AbA9lOpLMQE0DB+nthUUwNv5EmKoUkgza8lkgq8S0gI2s4gOaD4Mj20c7SuC5KAm
sXHEYcg5rfyQ1XyA050FWn2lI+Wd6fqwKV/Qr0iGHt71c6crNbUNGfrSFxqB/1mzlM/FnJcnZmco
AKpfpSfKpxXYxl+y4KicHHRpnTMAnFNOcbmzeHZGYp9Qoh9kR7ZCXSqUe/fWHIbXIroT4Pr9U81r
YplvyGlRhslwucLx++gxh9Yn2TSM1F+f+i6Vd7OUEz8g6Q2Fu6UAXYMhkrQ4Ne1EDndbmCTnuoG0
Z1S5dC/ryBQWvvCzB/RJg/3R1LJNpJtmplLRJIOXW4bpPq4I2feRknTu9Ddy+A5NlI8MuWe/eR3u
a8nC5uwKjnFhW4LtaCHc/3GRlymbMY1nTSYA6eu1aDARxtL0P4+7NIanGnMNBH7l3kmcCmRd7eOt
SMoC/Zmj77yii+mH/DNEzQYQqGlVZI8QpUMjCiaoQb882jCZkHTIlxa3URJWHnUQy57Vwtw6HvrG
kAQvyGTwZ7vlqP2+BhuKlwSkrr250hKzKs+pvQvLq4p+gcle+rplwwsrxVGFRr7R6kkRS/XgbZt2
TxDVV9E7Vc9XE+qSazOkzJ2Jg6yeqjKs4plxdOQdK09rzhMxW7qURneoAUkc2/0AdKItFMb3JSSA
9AD2UaypnV70nigst0oC3PCzeiLo1YjUJ+1Xmdpf/uSpdN84lnkH8aUK+MIqeLf8L15peJDPWkVQ
BPN4sN1Pu7jtVyRLlIjab7tbaIezQOdq9hG7TA+6YM1daa7UhS/oIqQgyQjModiEJMn5f0ymIh7N
wtvszMinAWhEyIuCjIuSFm1Gksxtzxd7wXXATv17Gghr0XKgY178qRQ2xdFtod/gh1ZIFSm71zEN
Sy67VGCjoeA0D3o0Moy0tnDqfwXwBUzSr+BdRE1jX78HE/EGQGBZvuFz9oc/MwgyM8uHyO11XMmh
qX5izqtiQWAaxEBT/XOgyscvUotFawVXkP15Dfl2bQUVSKFuUcerKjeW36Fh/7cEYiLOPVibDu6q
eCWcqTl3xgspBQSqGefx37PCPReaHTDnNXpEjdLX+gM828ttIOTxs7MH2NYnXTsQ/B8JEYYdZyD1
CmOuQj2u2s/oyDQix35DPXmqW+y+m02isjPP/xoHbXBqCSWwZ/RyOeCzjNY4NQkVAPfnJH+PVj/j
KJFuFh79kn+sHaW7tKtNb6yvXGmeCkjw/Ady2SQjcT5dH5xE2gSxSk8xG4D0Hip3I6MO0shMQNtp
tLkX1Gf1InEI5+NgucRUUeyIkdPH68C5LgOBbDHyoiwCGSX5HbDesqCSEu4Svd3WT+GNLx1mYn0u
xNXxQD6h38/HMeWkCLEjHSp3jZlCQwqqbmCCoQetEMeeTRGt9OgQYi3vTxlDBO8xOr3sN8ufz15X
4B5LVQ3qqIrgDXQXSvkspn/ti0ZX1hLQU4jswAa1CiicFWZ5PBX0pTPoMpSpsGS5dKLFO0KA/YEi
3fkgnNkbFd5MOsVMwLdqo6QoQe6h57N1KNgA6B0aLpHkGv+j3/V1cdN5RWwqc1d/pbVKWK4hFCrL
sydvGayEfAzqmzwPnf5XatiphdrGWkM+KZcXrdWshKhSyreB1V+sJRFxPAnIJLGsyWiZ6c64a5i2
QbL0xovOaajUW79n1E32+mjdh3pjQHi2HntUfhPFEVD87VTKNe3zTd3QT0Vcby71o8EAOBlwZvqh
xBwc/CdRLc1QNUKZ3dT6QlZ1TECdMF58Bn96LlI+WpzX4vXCpbyEYXKkvA29TkCAAP8pb4xES4UN
g38QWzuQxXK6nmWP+u52WwHqAGN7D7d2RhGQoom3fhw0tUSnmPnjNjVn3w4gHV2PGKqsWNP7ABJo
+aGc0SHX3m4r3bgcBdotfTawwBlJalLh0Gtq8X6/pCFaG6WeHQUI5VOhdjvgIlpeC7gBn2n+QGLb
hlpq1ZYDmDI69Jl8PNOf02pCCEhquJvk24ziSwYvZrsvz9FFQx+hAoPA/eAv9o5fjQ5Xpw9LzJIE
19yyYkXDAm9qbPvj2PsniRW528BOi5eRQ0z1XQh9jtnw7wdqPIxUnBW1yECRleFBuBhZyiPmkBRW
coC6G6oeodDnadrH/BitDjiRxjpc4uvo81pYy+huGIV0GWlBwAASsUzKojxZdLu2zFgC6+PbTqv3
U8b7EfHIn58K6rlvx5aYoGKbd+jtc+O24NyfEdJdZh2yZkMmPVjm38WqtAzONh5DP5SkToHF+KBf
N30gMpVasHRwy3Ap+YjnpJjkNRc5/hKTmhgb1zftTKBv/qd/vMWsbHwV7jEf+WeIt0tGGGUumxva
cYB14izSAighLxywdbDTG9aFNWcFQny1Xzg36zlIMC+t/I858Ln3wm78u/XzVWvWs5BHXKHU4vqR
8bBOBtcEV+RLGLJkBLkPFUZlpLcT3rCBDwHR5HfI+GbpJKhpdpKMeBVpSmIdpvBxyKneW8feBHJc
Yo/SU+P0qJT3MQturdnHNPU2HNJeXa3RgT7oDM7elPnd1IYriNXNmeFYXJgJJNer2yBHZz8qQYj0
l8UmocNqMJreOfvND7LRPhZaatnAllXFcpAJgOpHFK2MT5NjHmPgrTl/s9hAqUDwf4utFmbgS7Rh
8f5g3jRDRS5+i54C44vZcymFUtIcCHYPVbaJVCWAWP06SIwf7sg4QwITxeUp4C6lG/srbtlUjqwG
CuKRqYSIcZsFCRQH4gRduhXRiFFvgNXpyTmVBce4mq63D1NZ5jhMAwArBHWg4VCDHeYXozfTR3O3
3mtR6TGBYspoqjluni7FvWcueXFVCMTVEe+F6gdpCHrjI6DvbjOsLEa+urUaf9VGrmfEbmXMJYgp
qQ4KOxjx1ceyPKMXmp/o+hj8PHu+pQ3kudmi7I0/nDJqU+1WqYhSh+OKjmlDGozr0mOpPJxDysQL
3RDaq1OvwOTjL9BvaVxphAhvtnowoZ/UzJ8Ep8rBBmS6LQWnhOD9tFbTd/z0/2rr1ST6A8q3IW+U
CugVya51kGILWcU432aEUoAkU7Dq0WJ3KtkaeJqAgF8iv5dKh7hUZN/+vd7KFnkHQnQ5mn5yZsKN
0jwKe7moR1kH1/x9VhJ61AbllvQfsXTlWBZlKirNjytc8pNL7BBkEpfdNOWOQFKrrPUO3lwoEqY4
e736bSNndRHz5yjoP1P7cZqZ1uJu5wyCtD7GQGFal/VoO86kOrpKMhoeU7j5nQJhV2MVPnKUvnIQ
kqLIb917tNTOyhAb2V3AZTjUZmRcPwvU9pi9lpmQ+9zr4XrWxzuYaKGGiIQqwD6GGPFlrnGu831S
7u8fWo7E/d54uSm+w/nY28wFsXN3Q2xgZAq9DENkHvg/PkVtZ5h8wj3CHLd2B3NDa2ELNBdvPAWz
4ahNSDIOellUKeU4IUPH5MIOU71xPtnSwHOky+AwWIxzDc8YkMZvVGiSYndhOmIsf+AfUwm+8rsz
EWpiAeNSiDIvn9nHJSpj53lo9l0MuYF2uIZYrJp8sdOy1GEBx/0JZYLKUGG+hqxK6NySTfP49vqJ
7UE+hv1A/CjwiUf3BQ99Q3UFs8tB9wRHnKlxcnt0z0Pw+tyCqvxxaJYzhCK4Wh9ZFktpviz+nOgW
7IJwQwvD418qbBYx+uaFjKxpNW3j01+Lb7Sr/iB0zViY+Vs/3i0kbA94oTU2aIWoeQ/7T90Cu241
XTl24kl0WPcVBdT4m+6sGk3WfzzDyYbo/6RF4P31rVjVRdfpujVhFCnKKKAR2K6XtutzJ8jodMnC
LE0omoQoErNtVkxymPgS/p7VuQwgdvIuQrKXbnjCXP4H4Oishi4IRzin3qK6R2Sa4A5qSyaoYkRG
pDxGTrWYwFkSR5tyEs11elylSlg11d0YjktIfd4tdW7Th7ygb5WdJVv8PCBUC8tg7yxkaOG3Qa/c
ybjP17kDtco2RViw3XlP+NUgtO2JIGZbdMfZJy7FGWi+XyA1ihK9kWaDNbYS/4e9sgLgc/mfILyN
PSjBCXJ2Bo71fileNpeYqvzcshqhsgF8Tt/K5Ys1plH+JhEiaE25hONNs6fuvQB4LTZV9+9dGLkR
igZrJyBhfgomTCdPyFvrZYaP1VZ2ZCjIGwSY52tPb5swDNLIFRNosfyuysQaOmYBObeyMgelPo4q
bsThCXKuTvBBUrKx9gTO4TzyARn/rNk6uk7U+aL/eIl++c1+9ptxI7ZjpjcMy7IXuunzZhSHy0fV
MiHGZAkonOkDFW7oD9KAZcW9/1JByH5lCYBafMqoArJjlGRMnLBL+Kf9NMiqXmM5lnFLlCBLvuCM
OvIRrSlNBA0l6IXccPjJDNWoG/OJ7Oz7M2T0Bk8CbkGtw9Cdh/EQbag7zTEMhmkUd+5b7qPS/mDn
d9qj8kC6JhGArmOSiE/ghVSrD8onV0BiG3AeIG26lNXuuDHoBCx3uwX82/HRjQ1Lkb/nuUJVfWfU
SGrm/xIdB+2S7w6SQyfJZ6agSifudivL/zUTo53ebMqqhD13aT4gkLB9spZMYn+E023vOQ0K5OXZ
+ShCTFWPZt03ByA1DcGS1l+rGot4Ew6Q17falazpsU0RTqd/H/A42xp3hni9z1UTmtXe3q2ubWsy
/lA5l+tcrg02GaWdM6Wv36PbJGlgT7bcHA5CZLKToSBt+G2yrNLFhi+FazIUsSkiI5MEFLAoSh9T
88DV2PSWtI2xmuhdyK0Ttg11zk/LYsgW9VD8cbqrc+yB54SNiN4UiIUy+KW5n4oOvM4uxJAyzzbm
F34RXqh9p2r//VDsrtaYUObI0iuE5gOg8KsnMGV+gdZZoqoH8R57k/nGVfMTzy0cJZUZatU5YJ+3
x8YXenawvTBOhMCpLcZV3bxt3Y67xSVcO+487mwSPPx1xUy1LpNXRmykpf9DFPAWL+mx/snNRM5S
32urNY0thzbFMQgcO7obpo/bFPp9Yxy1qpefDRHVLl2E/tCtFqkFGr826bqMG3R7XlVsSKfCFsy9
9XIV6Ib7ZCyJBnQEUPvfs02ZKZr5MxplmEpSxNSDh1UTxS3jKixshmS3/DYlWhxCqsUAYke1NWwD
zZyS6APhkIGX632DNYZi/TyuUfjbL2tQ1LkVp7+Wxibb8I9lGnPypMBgpixWkeRg6TwUEZecusee
flP3jIh1be4328+MATUpBY+9Jy7I2fYKWt3hZ+UfZV0+KFVJVEuI/mM8ImPPGjDkxmGI5pfN6cCx
iUUhgIJNI7iQJNczVWOxrZ73Q81E0OLlIJFiUvIk3aqGjl7LR56E37Uink5b4ZXOG69mkm6lpM6Y
DiknbViYE20/H89w0a+uDzp/NgAr4EX/+La5ny7YPsulmK+oi/PcW0yIjeeefFrwVNljehf6/V44
6mWNGEvj+pH9qOjgyVnox4fJMtJE8jZDbsktv2E3h/H36gA1scEbyh5W24GrXzrSE76Kv08Yf2EP
Ck/LiC6asyiP9ZZKAHf53HhWCQQu2wSq0d0fDpofD5Bk5E5niaaBETZFzG8ldBpEdh7+wmL0UrZm
xcZzILExASYGkKCsGSShre3Amv84iPYAtt1saQcuXiuw9qnwNqqAtAubNxKZHMyBvgm9/PSXMd6S
eh64p4lwRTm6wyLYj9CDDiIXuvc8Bk8+Wkb8ASik7SWl2BV08FwrKu++n29qAz5i7D4gcCLq3onN
DUYb2DucT2+tm7jZVfPYdiFYipfbFFYH8A5hqW70IFFxcYcmpVrMujd9beNxSd+HD2pcxuqYmih3
w6QtD6mgnOkzz/wGP4VYr7CmyjZWyW0TC0pYSdrQ9Q5Vkw+9uy1O4sR6YxYvKQ/XEK1ti2oaNVDy
vM3cFPdeek6KMA4ogYQQteXa740bL0ViDA4hjboNTVf+83kdNWU6GM+DCwfsXJ0zgWrLKxGB5oi2
1VwPanxv7R5isRckjlUtjF23labwA04hKKTnbTtyD3lSVC44LfeWTprV8iR6TNvpluAtGhACq0Vm
eNVldW2exnBbs1AJ+NEo4MZdJKQlXvowVkWl8aj9rs6R6wqYLVsFkQW3WiBPcudAdzAYoEjuQbua
V3VGBFHDTih8Sa64UFvX8d0wc7itAmM1W6jMKaiBvnJqKjm/07nGys8R8HiKa8xTV5jEhLJGGFz1
cgxnpcMaq+708cKSHATImqkn4FXL0kJpa0ByUvnyqamGHg1MgW9mS/VweNkc2ZKbEoESEjd3qg56
rJDymiiTQQaQdz8vYMb3zKpciC54348TTQSmI7t5z25ywcZ6rxy2sdRGX+tZ7KG54diAA7agx2YV
Djc3rmScLNZOySbQdaPrj8GujS48lJ1vs/T6M/nMEyKbB+3qm9AQI0BmtWgEX3zUqEQ46FPfckst
4yPAvL5KoyniZBlOQ/CazLT0PQPkIzr+eqpAVGdsYFLiipQPG1YXGDszrK1AFXCOJ9HmkrxEVSh9
BUMQ5aNr+oQ2zV4OT82ApUIZt9dLAkLlzPTdTZDDQ3LNEVh48h5PdNFHNVDR3gzrAQzRboVozBJk
bIu3M2vxY5xDwR8qzBk/BpiXKPr4RgMLrUG9sEj0kNs7fbuox+/NP59b4J/UwRTldYNRAjaa24i/
ISftAOsReDNi9Sce1jaKtNjylyxQJ4IwtKo6LaZroHHOJcTg4G4zykW7oxF/bpUlTeTjlhD1sNPx
I+ImESFDKKMGsZKetP0jryw82eVbZEdB57rfVxYKNGxD5AUPIwDnE/k6OL6s8+0uqPfqsnkA5DF8
wzTRtK0q7xawsvbzqYI2vimH7ybRKVr0Bu6ZflVE5VbU7S5sDWKsgLpfLEFh+FLRJEa2YzE5fC6W
HQLIbFm3Qs7qXp83Q1qiKdkEXlZz3wwr2V7Y0hk5SPucQPUVBWMt49ZD0EhAIe9Klk0s6KKxSUbm
wH00fZ/eF4iw8NF/PsF6CIUZH8VsSVx9IVmKxtYotoTnPXhXB9gte/9Mwj2sDMmVqQ5gWO5e9vZD
DFaVP67JrzN8TNdnxSpzq7wjXLNPJkphgDJ+KAO1MHBMyu3pGwM/o4iS9hk0P0oqPDbO6gFsAmql
lKMRHkIRmruVL6R7j332sP3BCqSjF81e5gGvMpLWYKRIIZO8qTyOTKONgvHIZJjRMV1AKWWqmZqr
jL5Y41Ea+Z4vAoX5oaGKla2bhqVvV3CEvQov3OC/iyDOxb32mVbD8KTPuzLT/k0xvCVeI5ppw3PO
hrxSMk3c9gSiyf3G9bM6913S3HsoTWn+PgF3RFt9XLS2IEXjQWVtYJI7QaXMCq9y4QJB8Eu6d7R2
8VKnzY0Aw03Wx2VzEaQ+vmtSsk7mCJxXzhNNRMVgb4lxx7d9QY7JRPLQS4n+zLcLl6TlH2Vyqh+d
LhLkNNBEnMBx9+l66xb7dGGJYc/v3w6iA1a5Ywq9rhbgXLxJ7k0BFGsPfOnzhvcE78ZDIUhu56o7
KQAZIK2XYsPcrCb7IT2AhZ4+vyK4QXpmH4RTKKKK1R8S/hGFBQ83TyGM/DY6Wsile7Bv7LWmx5wq
iVHP2hi33wyT0s/6LsGDOBxbTuHftbJJyNbPl0RyjqUj02JuZHC9HWAzk56Hl7w2pcPGTY++Pp1e
cO665wUAmXJrrhxSv81L0mUAFaiWIWNHzYtO3WtHCSaYPGQPIri+40mAf+1H7c3+eyKTbm77aubX
m0i2PHyS76ag62bUUv/EH54L4sRdOBDS1RE//3xeazwSi2MxnsWTI9Y5z1uOsyO6lmknd7dmgesp
7GS+YCxF6Bk52ABbABnYeiTgNDtHxOu0PQzMlB6IVhPzME6D00rBOF3oGT8ZGcJHyPCl95emuZRU
KWvdgGSzqV2a7fNKqbnzaePRfohpALZUNKu+8mipLEQx8m2m42J/N2B4M5pmFBBn43slmJowSi4d
oqsjYPN6NEcxGWtMSv6LPiPXi+pkb6DGgaAdY3pv58M/52osqusSV/oPRlmWYXB/nR5cAoLd9Nxv
WWXgOBuLo6S+/JjgA21gWWsM3Hs1DDaXo8wL6XLf6HoGKX7XtixNJQXYSt7HupJ+unWIh639EtIt
cXP0lsOdpiwxgrIvbBM1/VQCDcHNfHH6WLY7uVCbUD6HXIOwCcYuri+lIZ6LnGJZ1Gv4EOYyUC8g
KtV2+s/tsJdItPjzsWEA08VC6G1C/nSNA3BCO65UP82zJR09SIxR8lxtL1cCvaNqGudpmQz8wi21
hC1q1in173WINBJWhtPRHuqECRl3oRxpwbpKSBGjKgJFq6F4qEH6Vlz/YDhir4ALVC38koWLg/cg
shPSWxKgtRqCx+LvUpmYn1vLZEyr3QQkOxFyS8IMWqgjsdhApSxeHJfmhfdH1wdOPWvDUuz8rkTk
ATSEK1vehY0k54Wp1ZEVyp9kIb6imoSIN9DMyIoogC+cW48vF1DwSGn4wLauzScOEQQbXFjUoteX
hv9k3pNOyjgdIO4ECKkUeedC+Mjzf+3a26zfL9EisjQPkCCVTQ9o/aZobuEmKJzCp8TbFPVTtQYJ
A2v6RdLoesKJPaTrkFdP96NW1rHHGiu1rGA64icokyA/3XGXjD3PzKly9OJK/auQyWsJA/oO1I9j
0i+qYI2zD1f6/5kyy7RkiHqusMGJKZX6G43P8RL5gFCwfsZOGwrPYH5aUtOtDYhmNmJCZ0RkaSMB
xau3w9KnF7/7usNftyZXV1R/4H2GtCrVJ+VMXaso4Bsu4o1Xs43trFwGo15LZjvq7GJbhxOs0OHT
cEB2IvMmOudU/WxtINGhgqRb1yAsjwM+9XYy9eD5uvk+BP69w6P3Q7uPGQ7g+QxoLX7K0TfQyLnY
1vI57/RnpVlbaNxr4YHblFvHJUtRnzXNBv0cjAeiVxIx1phRE11Mw1qSYuOXZJysIUXz9iyhbbgD
9Ozgz7KsKh3stHOLq2YEDCAqLp4sJvJeOFkF7jzjkhfPUyVaG6hKVC/CTAZM+Z9d/NR2OOaoWY5n
bYrAAG9x+CzM916/yjXG5IDhLL+axuqydKzOfYKFS50kwXsFIxv5r/uedxYv1aGmZYpzrDKB7mgt
L8Z8QsFQsqdvowCt0D3LZbx6jqqHOemz0coQ5aUuvSODC88yeAu3vvAveZPCri+Mjhaz4q2atPoQ
b+x9sacZsMchwg974V4+Jr3jVatylXVi1p2IgYe0sXxS4HCLE4R06XAx1SzZkUPoB6jX/XXtCLaP
3vDHMwHABVXpNpjHg6rCYlQ3vru4FaeJ+01socM53BVKHedSPhslGAm/XA90u26PnxEBZjccH+qg
SNSIFfqVDPM3bxBWsU5hGLrM/ALMl8bcJ+pPbiCHiOXB8k+xribAclNJ3gjMj9phJ101F2+w78k2
a8J5YewlrAkWt/IWZbmFn4ZYXbquO0vlh/m6A8yqVD0ZhiHRxhou9x2vVnnRsHZtwN+qouedgOtp
Q/<KEY>
`protect end_protected
|
/* ALUV1S1_unsigned.vhd */
/* a first level fully parametric ALU */
/* designed for modular use within the K1 standard */
/* based on a standard OP code set for unsigned work */
/* (c) <NAME> 2017 */
/* All software is written under the MIT license */
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use work.global.all;
entity ALUV1S1_unsigned is
generic(
data_width: integer := 1; -- q port width
op_width: integer := 1; -- opertaion port width
active_v : std_logic := '1' -- what active level for the status IQ
);
port (
Q1, Q2 : in std_logic_vector(data_width-1 downto 0); -- data ports input
OP : in std_logic_vector(op_width-1 downto 0); -- operation port
output : out std_logic_vector(data_width-1 downto 0); -- data ports output
overflow : buffer std_logic; -- overflow
zero : out std_logic; -- Zero
EQ : out std_logic; -- Equal
Greater : out std_logic -- 1 Greater than 2
);
end ALUV1S1_unsigned;
architecture behavioral of ALUV1S1_unsigned is
signal overbus: std_logic_vector(data_width downto 0);
begin
process(all) begin
-- vector for calculations that overflow
overbus <= (others => '0');
-- vector for overflowing value
case to_integer(unsigned(OP)) is
when 0 =>
-- Follow through operation (access to data bus from reg file)(default)
output <= Q1;
-- reset overflow
overflow <= '0';
when 1 =>
-- ADD operation
overbus <= std_logic_vector(unsigned('0' & Q1) + unsigned('0' & Q2));
output <= overbus(data_width-1 downto 0);
overflow <= overbus(data_width);
when 2 =>
-- SUB operation
if unsigned(Q1) < unsigned(Q2) then
overflow <= '1';
end if;
output <= std_logic_vector(unsigned(Q1) - unsigned(Q2));
when 3 =>
-- AND operation
output <= Q1 and Q2;
overflow <= '0';
when 4 =>
-- NOT operation
output <= not Q1;
overflow <= '0';
when 5 =>
-- XOR operation
output <= Q1 xor Q2;
overflow <= '0';
when 6 =>
-- OR operation
output <= Q1 or Q2;
overflow <= '0';
when 7 =>
-- INC operation
output <= std_logic_vector(unsigned(Q1) + 1);
overflow <= '0';
when others =>
-- Follow through operation (access to data bus from reg file)(default)
output <= Q1;
end case;
if unsigned(output) = 0 then
zero <= active_v;
else
zero <= not active_v;
end if;
if Q1 = Q2 then
EQ <= active_v;
else
EQ <= not active_v;
end if;
end process;
end behavioral;
|
<reponame>mkotormus/G3_OrchestraConductorDemo<filename>src/ov7670_marker_tracker_use/ov7670_marker_tracker_use.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_3/7b6e2d75/hdl/vhdl/debug_trace.vhd
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
<KEY>
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
<KEY>
`protect key_keyowner = "Synopsys", key_keyname= "<KEY>", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
<KEY>
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
<KEY>
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 46496)
`protect data_block
n0ejRewX+LTbbSYVIzunMtZ3xY+WS4eKb/Ji1jQWGYoXlYgnaXy6vpdeSsZZBGHV17KL+90Ubnrp
aaj/Qgn0Z8TSTj76O2WLrJ8aTy60p0HIw+K8xF0xBnYVhzLXcojp6fjFBLuQLtM1QelaKJ/bgl6A
ynxLRFaEvZPKKnZ0Z2p9Eykj3th/452jTmwOVa+xLMi/q5oxakqhalu2abCR0/mqAEOLAR3OH90Z
v4nCI5bK/qf8QKeY54H2aDGqhXNT/vv/lJL+IdidfdVVHtKI3VTSmzI56UDRj+HFVC5DzkSVCmg0
S8szjZGLUBj151kFzY4+4r2TzA0Id0fRzSjQyHzrH1ziDe3iv1/aMx1/fJRkhtSke3GyK7O96iin
1ZMjOCXn1DBpr49NlZoaN6u5v/w+1GZz8nMfzZfl6Ku3BQctvy+Ge0qCXcXKiuZl0MatqjW7kaCo
eJxtNoa/wAil8m2MnQo3ffyWh+4sr7q8d9uIxkSCJZyxfYCSC9OYR4rFuivgBs3CR7uYJbFb2Snl
HekJBy/zk9lf99Zm0ikbxaMAHq/c1dSj/gKlXsaW8gA7TSY47I/FAT90k3u8smm+y9fwvQgaMRmY
z/rX9YRjpJA0ZssIIU7negjitjtoQxiBrINPXJpRCf5Nd+cy8nMocy6GBCJzkalmkASdoYHOnj3a
klZTTEoiLyPns36vmlVn1Un51aQfifK19kW332y9fycU4G58qtX8nMz/yC3FR1QMmzu3eBOIgJEA
Rdqn2OByFQX1D2e/uGkkbduKmaRFvbqi/IbL6iFfa8DSYvLyGt8vqDJW2r/lXj72G6/TUHhatxLW
Dc+M7QkkMnxExLDBYDxoSDo3nXWbYbK09jK0CMPYXw8XDNqCRJHly4HJMLaZjjQ1edTUKGP0rwBC
8SKgyn22d5h/ARo/N30YiURRKnRIjN6FVpLXSi6uqK2BszDEhQFRuYdbE2fizhB1BNHqm0W5dGL9
P6Y/5PnSbfXJRCC/H1z8+NvCdiIGHEGEW00xoK0WMgrUzoZvAeFpe4tbCjyzlUbndtkjnDyyp4ov
hZrHAZzqRo4FMJyqmaAkLnr2TiJPzcSoFrVgaT/jDVFMKFj9/9UESz+fVvVPg/MqzvEiqfyuwFWI
Yw9hq8uyQGGaOWUDvUrxUZNaQpT5BAZRdWnVNN+NE56C92HAunSS2AMhNvZE25VMOcjaIJjUmf1Z
ddtdT0jkln9grDOzONxDruZnDu0j5ut0NbSNWelbHbQQKO8lyEn5Wrbyy8Ro1p1awYGk9jAYqKNM
4zfyNxORfu34Rkgp8MPeFUdU3Rqb+idsGt9LCabkcFx6xQIEyD2peJBD4XfQtZP0Oel1IcIEA35i
54JNXgom+wEDN3hsQkdrFnNee2D1CSSqp3GZdyo/mTCQYZGeFezIecjjVMyuOnoiyx37C40rK1tI
QM8Y/tfxKXv41MoWmMhIjRJCvcyaEjdWAyEjUkbJtsWkEmfVuE8U6NvX2gOxCqVlD6kAvn7ufy7S
GDoRgtHSV5GSwmOTv5wmNbF9h3TAlIUt55B0xHdELJS5qCWYP5GnoLe4f1xF54kLuLHtRdIjM+XQ
GnVpb3EnqVLhrmwsIfUitRu8Z+EoHJzpR5F0zhu+TtctzjHe/l1F1zL1mpOEDFNlbZBg4g8Ey20v
+tc22tCICtaEEssGBVjWlDYgnVLVWp4inCAOjB5BS3KqaOZ1veNMvEQXwr3uYUuv/hyuH1ehwk3Q
lVtTI6hbyY0U8vnEkIFBjLVpKEXWmT5kNYN0k38kFM8CdcdDCBc51dhh/v2WB5E2mwtzDhj76zXh
t2zN4ZNeqrccPN2SC0ci/F7Wq+krbNMn2Ub6FjMjqj1P9eVAcQEok9xHZnTucPn/pdtAYfMIxYNC
1IXEv10k7ovneAVtiTt+PcfRtUujsyUKxpSTsvhXRfUEl9jDEeo8MfEXv7xMjhmZj0lbKrv7EUuf
gI9p2GifSuz4Au0bgArQD10AwLAX8XY/he637n2okIeay+FRP3FdWENmRPCqEGeVOmsoILuupQRp
ZRfsm01FcSMNUnj1BfvgcRpS4kAaVARIrtpT6JjgeKmfHN3L3N30oj8jZUwmyIc7J3SlLx7+eXRx
0/eVVpadY/qP97eAe0AfGEMVsnQuRcz84ABnkvDzZzNIShe50TtVwZ9mWhGXjjnJe2rZjZPal28b
BhpdUwc5MH78Um9Ou4rWj24DOf8vpZqobz3VkVUhhXJr5l2NWqS4E+3KO4zF1dhNc00gmMw3CdF5
qOn5HII3ALJStojwvgmP2nrb8un9ERBRAS4PlYAFtOOZ56GQtEf0atISrB2EAqJp62krZvaJ1GMM
Cq3u2PNLuuifz1M5FHXkN/fAQhEWUzbTGXv72jQG/1lsHS/fjQFzP3wDbVw+pu+fdEoJb0tmuXTt
xy40ZPMcZGayOS3BzTOpCGvCiaUekZQDdLyhKC2I/nqBFBtFygjrK/5tZ1ORrpAXA3Y8ngG+DtKU
tbmJyyY+V4G+YjwOaEHReqjSc29AllU3hBIUyuf4FFSI+T6K5+LkBLueG4ipjmi1tmE39AGH0EU+
ME3QeQiPfYVW+Pr7wjFccGuwuU9p29rd6nlCrdcwBVm8jSYEA7GS69vIO5W/+12oAuTN1PGmb3J7
+9bZiwcR+5w0cJeRcthsRlGxph3ONgHt7ivt1nXGzM15s2KG7J3Exs67rhe1qOFB1z8OGJvDV1bQ
HJ7PzfU3FkZaiF7bYlVqEW/4iaSMkIARL5qkYmJVQg5oD0As73p2UhvNiHByt7lBzNeP+4mOZ4y2
/P69SMk2yLewtfUMKEBxcoslZuRLCHIxt4Kuwcu0hUN4/yOZAA3tnBQT7H1JK0taGNiBRkb5vo4Y
1WRtE77PAgByTe4bT23JAvXuUjjYdUlSeg8gRMcFYPWJpD5wY+Y3n1tvZI85i8S/pn/e62MBqAMh
40z2jiEZAX4qk/WTBh2pQNwJgFvLb9MiPE25cyprWABM9zA/mp2lWmd0o9DY9fe/td7zsq9Im9xH
Dxxl2hIUE9Tek0rdl61xPuoPyHySVX7ATAWKIG1s6JXO5CZaW10kK9jYJmFEPETJXVTC4p4IXVtx
IBMA62wfWjMLO2sLGm0jSA31KwxLF363z/f0kBmL8Ba44wHwlkt8P7yq6ZjR9RecRqVEbUPEmFGv
EMpX4GP67WJ/EMe/pJweiggN4pY9JzgmzjTpjrNSu3WzE3ZoXvG5PbJdMiJcDzOrTLnFcK4fyOIk
Zvdivni+kZYdf0Z4vShO1aQO7luuQCIlNxpHDi7YheVh+KGt/p6d/Y60QduoeN8pXG7kGwxB8XmY
GOE0+BDsZ73EhDjB086MQGWFlNpkt+fl6tgaoW9q13fayOKgR2soV6CKzb/cEDZRIGVGg+r+hRCu
MfHZDCIB+O3S51IrLVXofpf7dZymYgnDKx72izuhYhKiIYXwiEcBMLsWgvmcFaPbrgzcrEGQU/SP
VkgzsNjhDBBuj0GapjMoU63/8x9gm1oEEkerH3CI04kkx0oiA7kJAnh/qSfbekW5t6biZ8G6hYGa
LFePW1hPnfrd8M36vTU5534oLslSXXPTPwFfMuzCq6u4nw8An/30b1C8dj8iQdcgVc505ehWsJ0C
L6I9smmc3Yg+QsoTj+JN6OAoPb1aA1J1j6xAyCO6yDe3dNh0i0LB6pq68pMh9prpfkR3/kb+AHcB
bwz2BGlMPxDKwGm6UWrvAUo5wzf+fjWogdYeHTCa3k3rZkFgpnp8bYU49pjUn4N/9VaySbmqkeZT
WvKYcqQowGQptTkjDxWR81QMSJ5bEMxGHVUZ2CCebjynxBlhzdwnU70eBE4cVHgBtCkYmi7cEtfy
/n3qvk28cDb6YO/qvYBYGaMn2VccUc4EGttY+9C40kimxvybyN/fHoju30bWjFW8atZnpv20pz+R
4ai0bdsy3n7IzahqZs8z6V4hACTIIS3SK39JJIdsTUJiBqjYt/tvIM/EYVW8dm4qa0H5TtbbGTrT
Dvb+YyKYbFqGnByp0UgIbl60Tw/M82P1WXkwVBW1gJmTyiUiQ6j6JPxMf7aogvTH68ZltMCjD+hs
mCZi5J+/4k2XX7gliBUqiD0n9tnFO8rCv145AJivQbEN7zCsJBKnmuzLuvkP6DI1TEr3quWbfSsD
ERucsDk4ovi4aprTBr5jW546w7y14FMyoiu/Et8tVWwdnf7cZdFU4V7s9HQTpAQK3mfD5DLIBkWD
aByzT5/zD8F+wqQrHu1GHhEz8tYtMphIuM1pcy0+aDymEy6JNCt3fRBxZs1NGZeb8RoVd+NKqFbx
MPIxQYWd5xEJiXAFkPCj4dZ+AEVcLJPEs8DaPe78agJinF5VgjFCC0N8uf7RdJ0sXM3LZTaTRBaM
PvWmoFxOMYeum3oQ9Ys1jZXnIux04MWfvDHYa1wPmfTbAClnikSZvYDJj2tGyMAN8gc7dak+E6BY
fcL9AtHu9wjh4cAIVB7WJMbCqxEFaz/ilAv0XUkALwtqljSmBwBRVJ/ZP48L5IbZ4s0jAvpzxDfW
SDqBVbPI0kZOzUbYzboKsCriUC9Yy8ux1Y3i3YLQSMn6oKvRdXYlIpInIi3IWU0v5QE/D3t/AMOi
OnSCemGRTGe9+sFolgrBQ7wfqgskOrHuljUXlIdcI1cgfzLw/bdImdgNSZ+m6qlRc6ZF4m1Cg+GY
p7z141USaRN/9t1TRNlv6ElDlHV+26TxqQm2HGFtFJGdfLpiud5X5oRfr/88DbnFhPJcBKidMa0H
vLd5q6e9qGWEyS3VU1VYPWR0KQ2yHt3cYINvhBlD3KdaImQbqxBLB7s4mX3CVJpJHdjdlbl3V6So
14oP916uH6lkYhImx3cogTKWEWlg0z7gE1gMDUI1pNe9vj4QexnOOSvEn5WZTOtyuSaBcqR8wYo6
m9NJ/0cljOCRg73RSSOXrWgesGsQeaKziKUexZjVN+wmTAAB1FBvfWDghc8ABdZdRbq+nftiNn3t
2MRz3IFvsPLKJBTkB1TzICA/uCIKmuvYcssMcezqe51lI21wa1pPueIkV/xqPFLj2UkyJucFIive
7FrVFU81ZXrHSuZsHywY1sGFx63U0n3IL2pK1Ro/l9JFRa8f3qIizgz3d6ZDDsK+ovE9S0yNMpMJ
ipbgSXFL5/XM0ZKkpjj5L2MBCglNojG5+qN+klRTGel8Esmp3xmgNMuviVBiNx/YgYIaxfdbye06
TO6sV1ST4z116tnh+3JniTGVvh954rKX7tCMYxJ0lOEkn6jvwaKH5YhDsjM4dej527JipGrRvLdl
3/D73TnPe5eErs4aNrk1v3aOQ2qjH8KyVQqEwhZzkTqC8Yr8Kwxl7fuXZjzSq/8SivELcHf+/Ix6
j8Hun6+01JC7KfsyQ1BoftaEyULgmWVQqpFIRxPIvjpLXAMTvd4qkoAF7+XWCZg1ZGCGznkVn29C
qWq1CHycElUvEaininu8arHUFGDbV9sDlx8/v3M2NNGCQ8lZneMMEAIMsHLcIwdvGAHe0TFcqwAq
nEVedz3TJtbuGyztnELSUqsCOrBEaczcE+hpC7atESKCYw326mwkt1A437dcj+hd6PCd6PIdrqVW
98qF9o6x10i6YhH1q0g9bwcTwNl3wyN8Myx9B8/dBr1BGUN6L6DReEYlXq+h4AaN9NhojQS4nGO6
jqMshuCZe/tPb2ZVpObzIHS3RXgSkvkYLmIrZIDCSCnvcVDjcY3pT0sdiFOzQjst0yxN9mTgRX9A
QF0JZxv0ocFtSN/1SsdYFknWWmcbeFz6egTHOQyaYNVa1f6IKWoSoWfRKk44JhXrnbjUgXySYlVd
lnmRMlAv2+OPuO/zm6kuXBpd6EcdL5Ro0NWHYSUf2bwf2JDnY8ypKV81mEvizMyLKBrj6diS1MCD
lu7br8+2I5DnUYzH0ED/c/9kgrBWBl06Byd4NArsDAxfo7H+cD/j/2rnZRlX1G+ayfSXEfPtqVgG
oaqxsuHg0EfxH80S1mEYReXQc5GPHVILPULivJ6qxGTSuRq6LcTN1hHBg2rZUCDGPbncVIBCDz7P
kWpxrtmiIKauLZ0WkUGjn2Td7ekW0tPMHfKQWakZqD1xmvQoSGbt3bJEbPiXJXiie0mnXr87ODt/
FjAfa4xlZoDhwsYmXxaDD9tB3lnvDmu4Vh3meVQ3DvODNEL8OBKMnBGvXUMq9+msAxzUdJw0Nxe/
YebAI4yOPTgR62zyro4meiQgqGnG5dY7SvryKpzlGxLdbaIIJjd+iFQLeC8QRN8SNQXbU1qoxQnw
ZRdapxAJP+BFlJ81LKUBSIpJ5rF67QZaSEdyWD0OWJ6Umj0r8wm7NqHBPA8YzaTfSDSNCBJPW4HN
Uk75cjsoWnTYnD2ZZOq4Pl/lwbgDaKnFIdEi4vS/1sieq/C+DE2uNBenf4PRo97BgYY8CbxFyE3T
PgaSTr9P1X5u6f3CRvFLsL0BUoTxsOrdEatiGkMF3MfveznOQtK6z4BZ21t6ZAdlGW/YkjfuelG6
M9ynnJZlA24vkHavyvgBB0y1EIgQFtPnWg+Taljrdx/5G34CftNlwd+32inI7lJ4dpkcMsB8h2Pd
h+j+VMKb2UUXtn3OVJcuFBU4KeZJ/IYJQFMFb2YPP6aUqH9bvAwSx14/R87rsue2OEFstlsWuROn
MiMkXHl1kr+3cvlx6iwOeaKMwnJYTRCnn0he+EyMWubN/yBLpzMFG576YVpHNIJ3//uT8VNDZaZ1
lMZoXGKo9VUJD0JKWxWD+IRUN970O4yh3xfWrisu1imfaatyUlGc67ZykhRvbUrTULLUW6D/G4dr
c4z4PsMqejAd0FqTFceB1CJCr32u+aQx1GfFlKZ6+ueoovghiQ1SC5rmGIZQJdV7U3X5zVRlI+x3
AdG7v9iiWz0bC5j03ysJSZ+uKvIPteSkSh4wwG8OWIDtIvsWTkyPRHA/wrZMmJguXrFAYlOPP2//
9zle5RkYGtlNkXFQ7If9xs7Yfz6Al6vobBUIosjzZ9unikdWv7oIXOCw17tsUSei1umhx9BW5adv
Lf9AfJZzS3ZNEsVdlYAk1w3ARJP4aOSSSDByjS0lEAteV67S80UojfpxEfnn+xBqZ0/QRf5vtkBL
ildtD8yCeWr6Z24KxY1sEmJub+VLuHguGlFJzR3/FJ2WzhgLNnElj2QW3bWyDBF4HRl1SlKNpeCb
fdAnqn/PdLBuoF6jw30CuhvmmmoDbHR1onj8HbUXrcQkN0vR7TOId7fpRtj4cuw6cgpOHbCTt+Il
dsKyA4E2ajKFxgNEZ7B5R7gMHvWdLn2m3k+fWHgdaHrCTdK/nROg84amKVGbj2CnnFVKn/xxqzaE
MqFKJUBYFKfc/18Dj4aTH9ql4ld7lJA5sml6Kr5GB9u0XPY77XhnpP8Uo+2vauZkorXj1d9Hqy9c
r7TwqhlagPf8hP90J/auo11CbH5qqT9bfBKVBEV1wQv/CokzNgrLMNT+Ctdyo6dAPFelrFNR6c/G
j/hCB81VnLYhW7koyStf0J8gfczQT5+yPoPXJ6q75cJ/lzF2pRwePkkcfxJXabmcEdzILxAcjPFd
BeKEYplUyqCGmIwBR8gkFDSa2sXpmp56D5MVZEK47RNWUoiDj1bP2NXmwCdOuNLzgYpNcacx4/lM
z8ekTs3KpWFDkns3TSkez8WiOI4IuEqr9E7HBLqobJBVTSCBUdL5J1JqVXkwTjs1Mw3XXAsvZG7S
3eXLoj35QG3voqTh4j3S/iz1+yUbRFu8nTCFFRQkT8txwstLHcUw/1TY3mVfGft7GyzXNv9SnWuY
EnghEchdZVHyQf7OuQhwNebyzNP2o1H0yz2N0VEZA5gHWYHE3bpIB9vQ3cldQI0x1Zs6l9AEy8HY
gr2SgKAwLStYJA945UMAk3QLj/r/4dwtL+5FeAsf3S/AuU1WdaU/DkSrPyhXWLTQk7gqQ+8RSLHO
91Y/2layat+MLo8VU0yIp/0SCrazD8X3i85Bhim+gwyHQMQufc5T1H9ADiDYSXQnrX+uctLnwWxo
I0BXkkZsLa6Caes+r822GzqlRUqsNP1Qey0j+wc7kdRhtG5ZjNi6Me2nwRYGk/FSzVyZeV8/H6c5
EvSxW5QbUC3vWuHFB5Uw8U0w3DGbwK7k9IdzZXzZ4OIn965ZbM+mGW54Py7lxZASeeofC2IvdPkN
qfkZC3ehazLr+0mv7d0yxT4tGnjIhs0CkDiKwWvamX5sYzjOCmOi6qV+ANmLwgqrigmo/H41EUXs
oqDyzl31H5k5HKM0pwqHWr8R2SdDch3m1nFQQBrBBJ/NxSWAAwvLOBocSqIhZvZO+boZmRdwP04c
rhlGvcwbOXM/SXnWDLT4Q8BCLbTpTzxhNbdUFZqayPuTIE6ucxDEeryZyM00ce78ipQzmR82QVIA
UWjvLY6QoikkKVKSLIIC3L2TW+RAwLiPCyTBWeytPppjolm3pubaPZYkqnCPnTiUhOW1H7XsCV82
B8BuKsKbn7Zuwr4+TgOAPXyRWNvkRz13PqYnnG3Uy2FVbco4bOuYnocnrr2Pi+lNu+dPBmdk+hcS
d5vixyc87XowyJy+/qS+b2FOYI+ccfazBA1BPNPCVV8xnHeHJDEqvErnTUXH/DvJ5jJf9al9x5YZ
13bdneTdcT7nda9bhecTBUiM3+2ihxBqx5/+SgDlCCP/lYietUUJnW67uSHzRx4gUUQ7QofiS/dq
MtruxFy8bJk5orI5xSRmcuyB4nCuBtemQJ8ox5m9kO5GUxdk6qlhXPSqBPgSWb3nDV0GnCURan1j
JjkgEhZJaTfv9Fp0Pk3R2dr6o+mSeL2Gmxz7PHk9MXsPpSk3LjMQ55y6XVvlgLyM/2odBWg5Ua8L
38q+JwwIXdQ+ZejO3uOINJ6MBXSOjwV7VyRGu3Uel4FhgpHl138TTXOkaT4MBUsSPub3UT1PiMd1
DvplJJ9ej2/584ID/Ej+yrz4SZUZ0ek2MJ210NXfumjAYqXUbrGdtq7nBZpZXOoGI0CO/f/WE1Tz
n6ro7arGHJkpIegYr+e2LvpXQsTAVx1mL/zl5BaukpmZuIr7ofRZ729Ly+ShDKw0zQ9DlH8NrPul
Up0EiTQZph808ofI9n0VY6a9t+WGDfa2UZ4pGOW1gH0FARcWgEF6j1WXrTYMYRhhzKb7MqErk9Kp
ng9dTibxyWao9RDkHl59cXxWr3KoVf6S/If3UZm5rqSJk4JC06IhK91ZZljp1Yh5yBGQWwm18Gm4
Xvqh4jQ0+ix+tJszDRyCWv8FoqsdQsojj8IMIkCaRiZCOHz/uDWqbLUzYkAvT5JufXMtv++gBk8K
OjaSFdGMoXDzpvSrzJYzp+JKauwQg0ssWUDfAQuGjU2j+0VBzeo8oNvgAaCBJQV83SGaLKNIzjfO
BIkh8V4+YH7C/T1opFiWgGWVudqIdD8CM9KLlJ3KcTV7iHtMlIY22n7tLLzm0vy9FnqQVDqCEbs6
xGs+KDidOtt3jkW1ciG54fpigFobV4Tcz9EtBWWlKgdVkZlG42jDVwoRldPwRUnz3UzsM7GICa4J
ynjqwMvJlsisOaDEM28abSUlSwqqVDip0MB+RcvneB0Z+KW4IWd/7lpOlwoJpGUha1u70MKYOYQt
d3U5+WHwbwDG8WCx2DYqt76s5532wFxcu/afO/TMDFvntWMtKm0U+hjsuWbVxh09DlYRfUrCxz3g
h3Qk4KstveRSg3WWFRzYQdh1OC6A5bQzH+W18hnDmMQBvNSGPuxcvs4JnuCfdtUgtH8l3sBOjiU/
Grt5dx/Uc1voIY116XEsbDuT6/iu9JyxqYi1V8Di3jjKhsQ0kQQO/0GJOfvdviFdKHMkDIweLr/s
WLiQBdiiQ4Ost5fCUFFbSXh6X4v4u3I5aGDf8k5NtvCJxOQY9QW1tq9jMHsXTqYCJUdZQknIsiv/
z1N+9dY+f9cSgukVFIhk8zrFXaQaSc8iNm9pDehZKihcnoPoSriJDtpsDQ1ls1viyyf9Dvqup9Jk
7jfr8AiRUpq0kVUMK8K+/pH27vnazIc49QOpZy2G06naToKFtACRIm02rSkR880/Rpi0bhP2o+q1
979t5WtGm+VWPduR0s4NS9I0P5hR0i0m3XPejVstFdCG/opAcdOvrAUwwpZWrdL6dm+UzDf/MM/0
R4ljxdRG52C8tWE/eFhpJAZn3LH/iHZoIuSg1jlt27cKCRGsYSICj56K8AaSAQs7oXi9O0ISh5UG
NxyU0RqF3xNtB5FM2Hg5oA+yOwmne/nY/x5cWz9t2QhOybC7yEJUz6MCEQWwIF/dnIoM5T0/q9nJ
Rrqe8SkhsiD+XYa0jGwTMA0uILwBO/KCyfIvF7jckRHO6jWRBUnFReXffMXE2JWpus6F0LRNrKK+
L/wQ7IEEuLOEEi5UEeW5DQm412q7P/yl2+MYLUBB3mnhRDGivMUgtsvYbd3d7PiKBb7SzSYZON93
8NaMKy8+PORttWxCcXsFu3jbNRj678OuRs/crpjl5i3dubdmtEwz0U2Bvt2WzCd8NUDRUX3HhZLU
2zrbICu+djP9W2K0u++Jsw473fZDZZ68JE+vDyC1im1QqcPEeeO30WrkQ988XXRkGnb6TzaS46Ra
7uLWAgmQ0OPADNfto3VyPykkC3u6A7qOm8Vjo5osFcpqWPDncT8VFT0ZR0k7H/cvP2+fKWxRK7Cw
Yp1ldHPVVc3lUoza9Pb+d6Ysy47etlcKepRMr+Jjqiy37nEuVXdOftpWieWJGRG1o9RFod7Ve0kX
teElMfIC/o67C/CFDKoO1EwUOGUSAZjS8hOw/r0xI75Up8ffFYXtPNAaNaoh01v9sLkehgM+U8Oy
0MHqxfNAcEZ0JH2VBEyFxnFZRp915bSF9Z/LwyNLqErnRHMPC9H6TntzeNsNPOkDb7z2qmuk/HKN
oRUXOSCB33ZmI+H2JVVSamv4xZTXGZJhGcH4cArjeSEoi2ddH6j8eDzE2AybHeTia6LueFnktIRF
g3URSKvJmA2Pt2iXlBisEGZyWEga4MJp+xzqc0ZkMOZE2HlfNB6UGNRKUSeWC1CepGA3YsYU4ARB
lgpw8MtnYXP2Xcw64d0/Pc5aJQjxxG3/Q9694UQ+ZOeV4lx4avcVqJ/K+uslSvMMN9EDq3VtF9kf
FuriwY6opyTxBs88Zkdp+iC37zBoseFXuPgUl2h201Rsoa1j/T0F2gwUrF2ufIFO23rT/4TdGh7L
1tcPDpxKzqB84tMoHctWkkapb9wpF+6UH63s1GF5MTqOYZb/NZItTsdUOmZJcxf2l4vJmwr1xyVv
dZaOa3iGwV+kz3Q7YNLHF5St4kuD7KYzTupmQILkuTX2LkcB2+3gktnMNDB9AnIEqQ4LHnglLZKc
/hUr4j++SqgiFmf0EVHG2/I2Pp5H/4cwCaW1nlj5GN5eU9FPlO0FJpOTZmt9dcC8bvaUJ2jLhV0N
Yt195GYm8Kurytr+hsGL+YeGxzsNowYfZy44CQJKXRofgtPnw5OEYTORZV2/1vjL+hEFUDkeTyRV
9oVa4kqNV3+vQUwVP7Y3TkM9r9CVsNtbToPVWPEZgnq/C0++j1sW5QAtZAQ0WBD+nAfu9eaIxLnm
/ANKUbR57vtc824wn/wOBjZ+7ORCLjLIQFS1GPsMjyEWwwRJOavW67ENlZzZdii1Oc6jiJnbqchB
mN2KBLe9pCix54urd3tGVK973A15FWzBi5Pdo+y1C4ewBUrt7/FWXNwRElnSbhAsaeFxo14eVthz
ftZLhla+Lxh/2YNR7O+474OU8oGQmLxM+l6a0GCJaeqJLS9/NwfMZpwvfZGM/7ClgSKm9jQQyTMP
K/r9hGbLYr/cU69eiO2/997RAuukt4wUW2Wppmti+/SSuMVgcemUbLY7IRpLllJdZdwPWwmeXW8N
/qVGBAJYwZWIH4QvDoXX1b5alfCL69hUt5XS7y10vxg/PjRd+sk+bI5xriYp6P7VjnGrleREZqcR
I7oGRqmFv/mUMuwNQ++pBdbub4m4RUvbx/3lO9gNx88P/uSi+Tkx8FD0nEv4/pn88fPQcbltUSGR
Azdb1UBpaEEkKjznFWOxRJx3J6cMcK5hgYKDgpGqcAfCAcH9CsN4GlfWaICmWquKIOVlYp6spzjP
gneR1BuoCakNoFSFaHpp/0RBGmOZrhk+xTaJ0YWc2ERdXPGaxpFKRrg6sjSCNvIxn9C9AsqTkUGD
QIedTWHCRABhjWmUSaxPsWFDwpdPdxozJNlc+GvO5aN9rXz9FX2qG407oNVe5Mn4pjUtd6UKmSob
EBYbv484OyXAh4KoqOtZJPStNyuzHBr1RU7sqgiON5bOSGX7vVfaSOuxlRvkCb3yqze3YMViO18i
qypGQ+mdJ8wiS+peCivhrS246ygPLOfirA2R7XBq/oBQnZFQPLPDRrUqQ6Q8qrHd5LkhJs/ppMqE
jRyFtKjKK8sVjO02vcarX0AO3n0G7ML4Bx4bCbfr2ffhr/TBsQXWeDj2EHq0wRX5omlhXc2FQg5/
zHBmfXIvVxGLZvhZi6FXuO0yZILaaGjtcymvSL4Y5jkHDeBiNl4X7nAHrigeVQgkgibMG9l4hBfk
eTGwHPs1kW0VRMAavYdP34bZwawtC6eDLbYqoGgCVBHz/6vcSwlkK1OJhFyHNBaJeFwsFm+Pk6SE
1Z7uJ1xRSI1kgMCOefCazJSPEhcE0uh3I/XmC/rYlRA/tW0WEAkfDO1Jzt8sCLymFFGDMPdRCuAL
4oPI2Hje/bKdK4INw8n70Ny0BPKe1WSgJc6J6YhfGj5KNx+x496E9V8AGVsg0Gss7VxZcp+eXprA
gDnkw6S6HuPM/IvmCVYIY4DrdIsAWY3/2r2ySNNOimHah+10kO7ng/E4t3X2ktBpV8o9f2+PDpzE
DqgXVSbnCIhYTg94bp3cPNWhKdV7e30E9198mc9l2nQpxkApizfd5KXkY1eULVdkvrwdiZxtcG/3
MQUNp8RMQseT5O/b7/kFf2kZkmqirBoo54Efoi4d2dGNBOFSssuvn3CEvdnpwzNgdaHe8HkXZK/R
cdNKh3ijSqBRRTNZMeyiLH0UIgCQ78Y+BKwIZkhjflglSSRcTLjWrwFhHGYOPCPcUWX15lX/RoMV
2yP+9sXZYetNuZUja8RlQf6ISkmFsIU5uhTC9QfsFUAlkTPXVtAhJ7WbTf9kU7dCNF3RcbjiZ7Ab
F2eIcg+0hsy37n+A/MlUKt6d/1KfsRXnR9C+d3uVoR9IjZYaLeGi7auugPKPJELdfd0XZFWP9ngr
f582dMb7PJri7y2lTvdit4r4hmWrb5AfSXiLZ9LgTPZGNRDRvGHTBZ+IA1bLS1qw0HynLPei7Xmh
wnA0G/MIATNZ9Zj942drpWUAeeKx+BfnUIUKyaNs8Fm+Bli/NO2Mk/EA+9VHXVHIiEMK40nW/guW
wF5K2EDy4uawVqGy7VJ4GDeYDy8/i+C7e3h4Oa50cmRosPGvRU4QGjakJmfTSlOXvxMOndwG/hNS
zo8hWPTzk5gnsqzCXjzZqVniAQH6Puxz/pK/1x9+JM4M4EbiVzaZFD+fnDqz6jTpB/d9z7PiE3OP
5C6+JAZgR36PXP2E2OHQX1E8grzY5E3Ljlq9GoNF0/VezkhaTE4Jgd2mO+Vuxk5ah1mdEQO+0PjE
ggr/9lsegntjE6nTQWm43VDU3mOxo9+Sluoqnqk9AtI/4ElZJH5Ah5Gi3C14H4Y4J/LgkmPPMU8N
FA17uQU9cQhp4zTpNTOORcREhYK+IdvkXaZTuJcxKEPk7r1N6ReOoTbLE26wt34TTJzcwEnfBxuH
tZA+mLJirIilYvkdgUcgaTsb3cwjwXHPqnDixAV56dtoPjaXGtL5JZTx1cpug5fQAX78ZcC2P94L
bNoHWJ4Impj4d0Gfy8hHtEP7p/7nh1TZBdf3bAlt2HK9PIASWzuu5Q6b3ApJaWjT44lddu1SfTZO
yCL8wC65v8v1f6PX4q9shpw8VcOKTFCrhVfCyvEkhR8XnOBqbKyELnowKVoU6CZp9zWsyJvqNK2t
ZOlmSaNsm/cuAHq/Y2XhvCpxGbs8Ur98dkIENIyrDvgnbhlSGa0hkWPpmxvAF1s4/qrLsjFjkoHo
SeoFD25hdy8YzvbvBd2mbfB5X2M55kW0neHAanlEKW1aL3k0IhjSzXIu4uHE6+aw4nf28qUu+PZ2
vTliwUYQJr4WXDC9VhaeRT26I3AOzZHaMBgJUTk+tMi6rrCbXTT1eIsJ9VAzvOfossuHHoZc9/TO
gT3FeNzzP/x0SQ00qmaMVK7zLHgZuXfsuRwjt3hfmh/13Akg2gejWgASpz4L8CS1qRla+Ls7Rhaq
1QsIdvFTFJ5oPgbMZodKodzOekkggeH5yoPtarS8Xjn+bhAAAEZxFys6U6nYfEYBMnJlkjI6vfbl
OrJ5aKiZ/ShBe9ENgv+q/64Q95B5S42VGjqNom4V4vxPNkL5asc0UCiyEd13c5Sthx05PufCHnKE
CfAZ87IoB92UY/XOLHyJVOg/5oN/xYXTtxgjRCv0wVj7XjS0uJADL03Q20gNLyoWq1dmS4Gz7djW
aP3O7/sr0oJCzB1/6aKVheD/ewF1QGPgoMOYKztsH1VkNxIHCldq1zr+GyV0cNncbVM6hluRQ6be
EDA6ivmKpgkO7vFQyl7miusmi7l1nqxNV3BuE0wmyjHggFuLL/c4ZHlwTv+i9p2SVr8SR4ubcgm4
lxrHE0hFWVHwjsx1DNny+Jm2GzAlCG2Bje5b7D0UOMyjtMWg8bj+tQ3xD7elUSu0uGWD+q+ksYWi
DDUABszyD4UDGxFn1UAxBe2SYYIIpo+zBk1KD7K6uRhX1gHCk4oaJNUaE84CsyBLnP02yXlc0roQ
VsW1Ie4R1dMIE2Zon5CMheCHlk8Jaw60O1os7c5gHQZsaYc4O8dF33FlU+hXplBFZStTVRQb6q37
B2sjKtMj7NiTihz960D5kHsirKDx39zsTg0Ws8UjwcOFSVC+2rm8lLO4DHljHKWiqmRdU5G+p/dk
JURSYpvsNUswZmRqKlgGtaUer8jITloVXmlFvqosHaQ7cFSwrROWETBAMRX3SWDTuRNf39QNEphV
wQacXg8mxBHSpVS3JM4FKs9kZ4kvbVlbh0IFt2cI7B5QXUgv+LMBj29vSexHl6dbIsknchW6d6TC
G7c9XlmzpwdTPTmV9JMUgpGDSWIiU4SzUuL72IGkeJ/2hhxb40JRa0Gb/ZZmQ/gb4vrePNlcVkCL
jNFALKNEQs8ZxhA0MydWpvtXaTqUZLqNllp1VfST+4Eq2YXmFJYQuQdn5uAJlbgrITfzfs4JssGy
WQ10m3lJqSsuVSuZKi36HHSYyl5g1ex1ksTEOf7KjMcYIF0zoQiQXy/gdx21VMHMuT7gFwKfLnOI
rMQrTvbUgdTavFNnLSNwdISkxpBtPM5numCtROyY9/TY6IGgrCPnORYLTedyQbopjUdc1Y5JNs9V
FZVnp2Zhrrd5XbiPmfLHmjxP01FutNOFZFfqZoi1WHlo4o1suM7/+kDeuTeFKwFQOo7eibR0eJSe
haI7YYShrmdILRap5UpD5M9G4FzokJBtAQDX4SwE25ZZxyMuzpuQ2bnnkZ530Z08S4fiwwh3CGo5
8x7uiavQKpfG5xcETVRJ3x0WJTsdEAnfEekDL5543C46IaKE5VkBErz8T1Xih1onpCsC/Uz6U4Jz
v7hU16DGyDra9u7W8kr1QSup9+Dtzo5RVsPm8IvfojTomdKSMDmP5WMSUQ0Rz0Nt3ByPaz5dCu8V
ONzm3veaGdKDxVwQNaBmd3yW4x1RxmlddMxBSIusbO063/1Z4bE7rRxs3/fyAsi2fifgqVeUOkuV
FcJX6GBB5Ix9F/A550FF9lHy2A3sJHU/pSyaBbm+fP8j1EdQ9At5FROFCvMxiI8uuyjEf+51KFgi
XMLpXvyLOJiAGR/A8vLe7Ez2wPbNziDN/q2XPFqVOIiWuavew/Ka6OFzbT6sHEQB62MMfhY2bZSR
EZc1JMzP/naihUOdM01xZ3bC29lpLQu2v/BoH9rtDm3rznHMGXKqhhwNz8ZJLn3m8tCfGe6kkIRZ
yq0wQjBUmJe11bJvdlkRdSxYoj7CYlIztLxfn6+NaN2ybWIwAeQ/4fZNJhf0E8Kd4NQisxq9j+T4
w83/6LVHBf34f+qZXZ1JADJD6D0WIVrBZ7G2FzOqapJ4rrPWcWkmSNyjeiaQ70SZRmoWMzzBaY9E
q4RIQvk1ZQY97048LMmWycVIGGVxPT16muvfql4yIqEW+R+XvWq2JkZnen2kvnT6x68sG3/fPDdx
c41GSr+VrNkpgBPcVg9rn7zM2RfNnPBQl4fnT4V/0o20hhMtvRsAuzWcCpafpqCCEqUkMjPxN8e6
oUtOSLEXJL4R2fRJAZ0ez4MpMvbp5yjBgwL86GQyed5KCHMWJS5ddwS3gQYNJZXwztam2Ch8LlLT
ItoZX5C3DmHvbTn7CP+g3r3ZckMAsrKSYsnrbqnnqspB/LDlJFbbdd81tClPUd/lGEeXRfSMGgos
aNNtuQfzyAA/hbXwlKd1kx//HeJUYxPdvQhITT19fN+Z/3s1eSaq0gnrwvAJnnuTJuAYHFnUw2IX
6LsCWT1wiz6uf4QLiYaIHgJaQupvXLuE4p0OzNA+bKmNpu/F8cz1bZAQIydabrWG0kS0gJ0UvEo2
LkXskMasZDL6B2oi7UC8KqXi+oqQGVk9T5ol3Wuc+E/hNoo1vSAAIeSlR/+aSCiD3fF2KXJcVotR
Kk0tS5j4SLUR4cMhpCIQVRs8WRsG9qtD0oXPCbaIUHD29dfl/rnRGGc+qT4NrEtlmcyAljn059cM
HXm7wxi6MrbCMXtBhebECZMrfmw5PdGr/hmG5wcl9Q2ZgxnNB68I+bmXtVBrAOTWhN3nYgf8tRD1
GcK8NIwg6KKPUikAh4alB9yn1dotqYRknn2M+SbZtxrOqC35keGuWnM5WY4yLWufYQj0CsN5dlmZ
rNLmAr0UcmB0ICBh6H2TQA5NTfheOsla5RxDPUVGDunXwCJzW803MMf9PTV3O7et7PMrY+3I3Crz
J9mP+skyaBSD/zlYmUDmnO3nxVH5g2MO+Y/VDt4jU1abF4pP7qUT6E3mmPqLZU9e8jWTaVhTtp+t
G/IkFynBAzS5VZy0PQTUOvC+/xFM9PVQzj1c1fPJyBrDv6tXGpxD7c66Wg/aJ7U4KaOMKuFy2qJ4
I4A7UhSjYVklxU327xAUsEsUjQLLO1dUpecRIzxPtKoBQrRHkeSXt8hbdSo7RuvEr3Q+KqZ48s4z
Ukj613QBWQ4XyPZ5R+67+coRbas2mqOR8ojVtaVIiolffhzio9YdaQqfiCAW+W5ZIho3ARpfblUE
WhuPSn1JlcSsWOySV61zHJ5GYJJcjnOBM9P8ncLrDI4/sEy7zodA/MKftVOXVHsYLQ8Djtiw7+J9
OFMumIGV4v5otzj95MHXaQZR7I8FalVkx9Alk5aSVQY5eomVlmgQ0XgLzmb5F89QYbwrhhmBwV24
Sq4EMxICYJ1d3GHM1nsfQXh2ap3C1pM4XtQ52X0z1TiMpJK2yQXmJyf2au3s5rEQI/VJpcq9YZE3
edvYmPkeHPD7cw+EM4EB5kCy3kldbWPfRq+4KE1XsO2mlWzRozhOOY3MFK197gTGtGT5D7UtGEhE
t2q6JLjmnW+1ft2y+d5xrnusOXBkvkZYl4iOe/qQ1oyJG6GdomfnTv+UH8QGtX2+DoInms8UUPdc
DPSw90QKkoXtW9t0iOLin3mWeL9K++P9jxZyYOIM7n+i9/4uhMzC1S9/EjQDvQtY1QxY7TbxhZMP
j7KLDs3rY1nt7X61voetifJxnBG5r274yRL01/LnruEc8j+kMCbsCOwRctoHcm8RoD8CV/0Bl7wN
Z0M7yuRDM5l5FlD4pzgvMzDUjysmP9Ej4vw4UgXN2rOurDTzyL2R6y4TZE4+0srfCNQOjH8a3c07
JpKbusVMbyfTtaa8Ya/sLEMNy82WHYJ4wuRIvVdX71TUhNFarkAFFQ5Hoa1oRPtRUn1HD+/+nFZ2
v6CNyY8BbXlwjdWZPIV6djz/C6QmYDzKZBrAB+SsCDnNKcNpj32N6YDStmucWeBuQ7R6I//fjW9q
HmEjor2NZ9reiJdPmDDgypRNDgTKrpRbxKy6RF4q7v0nmeJEzZlWdaFkJoS3epXrYTGPxnYBtapD
4DxNcG1m6lchWWTMbRrFmjfZo4f1/9NZ3FSNvi7LcJpw2syGxKY2bHp82+1ETnnmjKeH1/N5rwHy
DtWZXrlyNqk8pnwJ2sklM9Ac8d8sdAc3bzcCRBFN8CTxspS6z3yseOYSs6ptrKgj7F2SHn4zw8mV
jktn2pVD4mFPsm2XOJXXyKgRBczgsC0n58EJDpsu61F4MSwz1rwWF1kZuqFPt6LmB5lGm9QzvLEK
CqAOdizd1r0MCAz9cyE5y1maz2PhkQVo6n7vcLxx4ukEasFAMe/kA0q+lxnRepo/VZ3MNrFPDD6Y
7ZEqvTT1uY6AFVZ2WaXAHiRq6lqpTzOQL34PQlVS0qGumSce2D7F0aR0MwWbBKa9IWuuYqlJCrvt
0yiTqSLy6mdfC9WoaPsbdtfweAzvMgZoxs1R8RmMYBCbH/UX9UyK4NxB1F5AY3Snt/hfxpvASI+A
62/95b0qZ+iL63fwX2yqV8C1bAX57RPyBhvjMJZGo53hzDuzvmCVE/wKIqM+1DlszteoU2of0pbF
UZQnCz+GLlk4d8Ynx28Q19wHWLNjuMUNnVLZ4+RJzYeVTMg2UNsAiq9/Cf6xYmTm45cDq8Onyqqx
s/SQsQF5+ZKlQ8G2zeIC/iAQKPL9BWIheBay7p5aRRwb2YNoaSYcV/j+j2Mtib/hYvjWye/pWESf
Va1oftPt/kfah8kUBcRc1pQIVwkO9OY2UCg/DYJwUnKsOnv3pNsvL33FirD3xB6POvcCmsm3gibB
KOOq1T6AeYEhYPnPzMEA36ShdCBFbQZKgbNy8cx/9Qf+9VXYG+tuFVqBxu5k3gircDJ6VITDyx40
<KEY>
G/<KEY>
`protect end_protected
|
----------------------------------------------------------------------------
--! @file FE_CPLD_Microphone_Encoder_Decoder.vhd
--! @brief CPLD microphone array encoder/decoder component
--! @details This component translates data from a variable array of microphones as well as a temperature, humidity,
-- pressure sensor and transmits that data to an decoder on another system. The component also translates a
-- serial stream of data into commands to configure the microphone array.
--! @author <NAME>
--! @date 2020
--! @copyright Copyright 2020 Audio Logic
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- IN the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is furnished
-- to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included IN all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-- SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
--
-- <NAME>
-- Audio Logic
-- 985 Technology Blvd
-- Bozeman, MT 59718
-- <EMAIL>
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FE_CPLD_Microphone_Encoder_Decoder is
generic (
avalon_data_width : integer := 32;
mic_data_width : integer := 24;
bme_data_width : integer := 96;
rgb_data_width : integer := 16;
cfg_data_width : integer := 16;
ch_width : integer := 4;
n_mics : integer := 16
);
port (
sys_clk : in std_logic := '0';
reset_n : in std_logic := '0';
busy_out : out std_logic := '0';
bme_input_data : in std_logic_vector(bme_data_width-1 downto 0) := (others => '0');
bme_input_valid : in std_logic := '0';
bme_input_error : in std_logic_vector(1 downto 0) := (others => '0');
mic_input_data : in std_logic_vector(avalon_data_width-1 downto 0) := (others => '0');
mic_input_channel : in std_logic_vector(ch_width-1 downto 0) := (others => '0');
mic_input_error : in std_logic_vector(1 downto 0) := (others => '0');
mic_input_valid : in std_logic := '0';
rgb_out_data : out std_logic_vector(rgb_data_width-1 downto 0) := (others => '0');
rgb_out_valid : out std_logic := '0';
rgb_out_error : out std_logic_vector(1 downto 0) := (others => '0');
cfg_out_data : out std_logic_vector(cfg_data_width-1 downto 0) := (others => '0');
cfg_out_valid : out std_logic := '0';
cfg_out_error : out std_logic_vector(1 downto 0) := (others => '0');
led_sd : out std_logic := '0';
led_ws : out std_logic := '0';
serial_data_out : out std_logic;
serial_data_in : in std_logic := '0';
serial_clk_in : in std_logic := '0'
);
end entity FE_CPLD_Microphone_Encoder_Decoder;
architecture rtl of FE_CPLD_Microphone_Encoder_Decoder is
-- Instantiate the component that shifts the data
component Generic_Shift_Container
generic (
data_width : integer := 8
);
port (
clk : in std_logic;
input_data : in std_logic_vector(data_width-1 downto 0);
output_data : out std_logic_vector(data_width-1 downto 0);
load : in std_logic
);
end component;
-- Data byte width definitions
signal header_byte_width : integer := 4;
signal packet_cntr_byte_width : integer := 4;
signal n_mic_byte_width : integer := 1;
signal temp_byte_width : integer := 4;
signal humid_byte_width : integer := 4;
signal pressure_byte_width : integer := 4;
signal mic_byte_width : integer := 3;
signal cfg_byte_width : integer := 2;
signal rgb_byte_width : integer := 2;
-- BME word division definitions
signal temp_byte_location : integer := 12;
signal humid_byte_location : integer := 8;
signal pressure_byte_location : integer := 4;
-- Packet DATA_HEADER ID
signal header_width : integer := 32;
signal DATA_HEADER : std_logic_vector(header_width-1 downto 0) := x"43504C44";
signal CMD_HEADER : std_logic_vector(header_width-1 downto 0) := x"46504741";
-- Shift state signals
constant shift_width : integer := 8;
signal shift_data : std_logic_vector(31 downto 0) := (others => '0');
signal shift_data_in : std_logic_vector(shift_width-1 downto 0) := (others => '0');
signal shift_data_out : std_logic_vector(shift_width-1 downto 0) := (others => '0');
signal byte_counter : integer range 0 to 4 := 0;
signal n_bytes : integer range 0 to 4 := 0;
signal bit_counter : integer range 0 to 7 := 0;
signal mic_counter : integer range 0 to 64 := 0;
signal mic_counter_follower : integer range 0 to 64 := 0;
signal shift_out : std_logic;
signal shift_en_n : std_logic := '0';
signal load_data : std_logic := '0';
signal packet_counter : unsigned(31 downto 0) := (others => '0');
signal sdo_mics : integer range 0 to 64 := 16;
-- TODO change the "trigger" to start shifting
signal channel_trigger : std_logic_vector(ch_width-1 downto 0) := std_logic_vector(to_unsigned(1,ch_width));
-- Deserialization signals
signal MAX_SDI_SIZE : integer := 64;
signal parallel_data_r : std_logic_vector(MAX_SDI_SIZE-1 downto 0) := (others => '0');
signal header_found : std_logic := '0';
signal read_bits : integer range 0 to MAX_SDI_SIZE := 0;
signal read_word_bits : integer range 0 to MAX_SDI_SIZE := 0;
signal send_valid : std_logic := '0';
signal busy : std_logic := '0';
-- Control signals
signal start_shifting : std_logic := '0';
signal end_shifting : std_logic := '0';
signal shift_busy : std_logic := '0';
-- Avalon streaming signals
type mic_array_data is array (n_mics-1 downto 0) of std_logic_vector(mic_data_width-1 downto 0);
-- Workaround for a memory initialization error associated with defining an array
-- Assignments -> Device -> Device and Pin Options -> Configuration -> Configuration Mode: Single uncompressed image with Memory Initialization
signal mic_input_data_r : mic_array_data := (others => (others => '0'));
signal bme_input_data_r : std_logic_vector(bme_data_width-1 downto 0) := (others => '0');
signal sdo_mics_r : integer range 0 to 32 := 16;
signal cfg_data_r : std_logic_vector(8*cfg_byte_width-1 downto 0) := (others => '1');
signal cfg_out_valid_r : std_logic := '0';
signal rgb_data_r : std_logic_vector(8*rgb_byte_width-1 downto 0) := (others => '0');
signal rgb_out_valid_r : std_logic := '0';
-- Create states for the output state machine
type serializer_state is ( idle, load_header, load_packet_number, load_n_mics, load_temp, load_pressure, load_humidity,
load_mics, load_shift_reg, shift_wait );
-- Enable recovery from illegal state
attribute syn_encoding : string;
attribute syn_encoding of serializer_state : type is "safe";
signal cur_sdo_state : serializer_state := idle;
signal next_sdo_state : serializer_state := idle;
-- Create the states for the deserialzier state machine
type deser_state is (idle, read_mics, read_enable, read_rgb, valid_pulse);
-- Enable recovery from illegal state
attribute syn_encoding of deser_state : type is "safe";
signal cur_sdi_state : deser_state := idle;
type valid_state is (idle, pulse, low_wait);
-- Enable recovery from illegal state
attribute syn_encoding of valid_state : type is "safe";
signal sdi_valid_state : valid_state := idle;
begin
-- Create a serializer for the data using the shift width
serial_shift_map: Generic_Shift_Container
generic map (
data_width => shift_width
)
port map (
clk => serial_clk_in,
input_data => shift_data_in,
output_data => shift_data_out,
load => load_data
);
-- Process to push the data into the register
mic_in_process : process(sys_clk,reset_n)
begin
if reset_n = '0' then
mic_input_data_r <= (others => (others => '0'));
elsif rising_edge(sys_clk) then
-- Accept new data only when the valid is asserted
--if mic_input_valid = '1' and busy = '0' then
if mic_input_valid = '1' then
mic_input_data_r(to_integer(unsigned(mic_input_channel))) <= mic_input_data;
-- Otherwise, reset the write enable and keep the current data
else
mic_input_data_r <= mic_input_data_r;
end if;
end if;
end process;
bme_in_process : process(sys_clk,reset_n)
begin
if reset_n = '0' then
bme_input_data_r <= (others => '0');
elsif rising_edge(sys_clk) then
--if bme_input_valid = '1' and busy = '0' then
if bme_input_valid = '1' then
bme_input_data_r <= bme_input_data;
else
bme_input_data_r <= bme_input_data_r;
end if;
end if;
end process;
-- Process to start the bit shifting
shift_start_process : process(serial_clk_in,reset_n)
begin
if reset_n = '0' then
start_shifting <= '0';
shift_busy <= '0';
elsif rising_edge(serial_clk_in) then
-- When the first data packet is received, start shifting the DATA_HEADER out
if mic_input_channel(ch_width-1 downto 0) = channel_trigger then -- TODO: Find a better start condition.
start_shifting <= '1';
packet_counter <= packet_counter + 1;
else
start_shifting <= '0';
end if;
-- When the shifting has started, assert the shift busy signal
if start_shifting = '1' then
shift_busy <= '1';
-- When the final bit has been shifted, assert the end shifting signal
elsif end_shifting = '1' then
shift_busy <= '0';
else
shift_busy <= shift_busy;
end if;
end if;
end process;
data_out_transition_process : process(serial_clk_in,reset_n)
begin
if reset_n = '0' then
cur_sdo_state <= idle;
next_sdo_state <= idle;
elsif rising_edge(serial_clk_in) then
case cur_sdo_state is
when idle =>
-- Wait for the start_shifting signal to load the header
if start_shifting = '1' then
cur_sdo_state <= load_header;
-- Otherwise, stay idle
else
cur_sdo_state <= idle;
end if;
when load_header =>
-- Transition to the shift states, then set the next state to load
cur_sdo_state <= load_shift_reg;
next_sdo_state <= load_packet_number;
when load_packet_number =>
-- Transition to the shift states, then set the next state
cur_sdo_state <= load_shift_reg;
next_sdo_state <= load_n_mics;
when load_n_mics =>
-- Transition to the shift states, then set the next state
cur_sdo_state <= load_shift_reg;
next_sdo_state <= load_temp;
when load_temp =>
-- Transition to the shift states, then set the next state
cur_sdo_state <= load_shift_reg;
next_sdo_state <= load_pressure;
when load_pressure =>
-- Transition to the shift states, then set the next state
cur_sdo_state <= load_shift_reg;
next_sdo_state <= load_humidity;
when load_humidity =>
-- Transition to the shift states, then set the next state
cur_sdo_state <= load_shift_reg;
next_sdo_state <= load_mics;
when load_mics =>
-- Transition to the shift states, decide whether another set of mic data needs to be loaded
cur_sdo_state <= load_shift_reg;
-- If the last mic data hasn't been loaded, keep loading the mics
if mic_counter < sdo_mics - 1 then
next_sdo_state <= load_mics;
-- Otherwise, go idle after the transfer
else
next_sdo_state <= idle;
end if;
when load_shift_reg =>
-- Immediately transition to the wait state
cur_sdo_state <= shift_wait;
when shift_wait =>
-- If the specified number of bytes have been sent, transition to the next load state before the shift register
-- "empties"
if byte_counter = n_bytes and bit_counter = shift_width - 3 then
cur_sdo_state <= next_sdo_state;
-- If there are still more bytes to load, load the next byte into the register
elsif byte_counter < n_bytes and bit_counter = shift_width - 2 then
cur_sdo_state <= load_shift_reg;
-- Otherwise, stay in the wait state
else
cur_sdo_state <= shift_wait;
end if;
when others =>
end case;
end if;
end process;
data_out_process : process(serial_clk_in,reset_n)
begin
if reset_n = '0' then
elsif rising_edge(serial_clk_in) then
case cur_sdo_state is
when idle =>
-- Reset the counters and signal the component is no longer busy
bit_counter <= 0;
mic_counter <= 0;
busy <= '0';
when load_header =>
-- Load the header into the shift register
shift_data <= DATA_HEADER;
-- Set the number of bytes to transfer and reset the byte counter
n_bytes <= header_byte_width;
byte_counter <= 0;
when load_packet_number =>
-- Load the packet counter into the shift register
shift_data <= std_logic_vector(packet_counter);
-- Set the number of bytes to transfer and reset the byte counter
n_bytes <= packet_cntr_byte_width;
byte_counter <= 0;
when load_n_mics =>
-- Load the number of mics into the shift register
shift_data(7 downto 0) <= std_logic_vector(to_unsigned(sdo_mics,8));
-- Set the number of bytes to transfer and reset the byte counter
n_bytes <= n_mic_byte_width;
byte_counter <= 0;
when load_temp =>
-- Load the temperature into the shift register
shift_data(8*temp_byte_width-1 downto 0) <= bme_input_data_r(8*temp_byte_location-1 downto 8*(temp_byte_location-temp_byte_width));
-- Set the number of bytes to transfer and reset the byte counter
n_bytes <= temp_byte_width;
byte_counter <= 0;
when load_pressure =>
-- Load the pressure into the shift register
shift_data(8*pressure_byte_width-1 downto 0) <= bme_input_data_r(8*pressure_byte_location-1 downto 8*(pressure_byte_location-pressure_byte_width));
-- Set the number of bytes to transfer and reset the byte counter
n_bytes <= pressure_byte_width;
byte_counter <= 0;
when load_humidity =>
-- Load the humidity into the shift register
shift_data(8*humid_byte_width-1 downto 0) <= bme_input_data_r(8*humid_byte_location-1 downto 8*(humid_byte_location-humid_byte_width));
-- Set the number of bytes to transfer and reset the byte counter
n_bytes <= humid_byte_width;
byte_counter <= 0;
when load_mics =>
-- Load the next microphone into the shift register
mic_counter <= mic_counter + 1;
shift_data(8*mic_byte_width-1 downto 0) <= mic_input_data_r(mic_counter_follower);
-- Set the number of bytes to transfer and reset the byte counter
n_bytes <= mic_byte_width;
byte_counter <= 0;
when load_shift_reg =>
-- Update the microphone follower
mic_counter_follower <= mic_counter;
-- Reset the bit counter and increment the byte counter
bit_counter <= 0;
byte_counter <= byte_counter + 1;
-- Load the next set of data into the shift component
shift_data_in <= shift_data(8*(n_bytes-byte_counter)-1 downto 8*(n_bytes-byte_counter-1));
load_data <= '1';
-- Signal the component is busy
busy <= '1';
when shift_wait =>
-- Increment the bit counter and reset the shift component load signal
bit_counter <= bit_counter + 1;
load_data <= '0';
when others =>
end case;
end if;
end process;
shift_process: process(serial_clk_in,reset_n)
begin
if reset_n = '0' then
parallel_data_r <= (others => '0');
elsif rising_edge(serial_clk_in) then
-- Always shift the new serial bit into the end of the register
parallel_data_r <= parallel_data_r(MAX_SDI_SIZE-2 downto 0) & serial_data_in;
end if;
end process;
bit_counter_process : process(serial_clk_in,reset_n)
begin
if reset_n = '0' then
read_bits <= 0;
elsif rising_edge(serial_clk_in) then
-- If the input state machine is idle, don't count the bits coming into the component
if cur_sdi_state = idle then
read_bits <= 1;
-- When the counter reaches the current number of expected bits, reset it
elsif read_bits = read_word_bits - 1 then
read_bits <= 0;
-- Otherwise, increment the bit counter
else
read_bits <= read_bits + 1;
end if;
end if;
end process;
data_in_transition_process : process(serial_clk_in, reset_n)
begin
if reset_n = '0' then
elsif rising_edge(serial_clk_in) then
case cur_sdi_state is
when idle =>
-- If the header has been read, transition to reading the number of mics
if parallel_data_r(8*header_byte_width-1 downto 0) = CMD_HEADER then
cur_sdi_state <= read_mics;
-- Otherwise, remain idle
else
cur_sdi_state <= idle;
end if;
when read_mics =>
-- Once the number of microphones have been read, read the mic configuration
if read_bits = read_word_bits - 1 then
cur_sdi_state <= read_enable;
else
cur_sdi_state <= read_mics;
end if;
when read_enable =>
-- Once the mic configuration has been read, read the rgb configuration
if read_bits = read_word_bits - 1 then
cur_sdi_state <= read_rgb;
else
cur_sdi_state <= read_enable;
end if;
when read_rgb =>
-- Once the rbg LED configuration has been read, send the valid pulse
if read_bits = read_word_bits - 1 then
cur_sdi_state <= valid_pulse;
else
cur_sdi_state <= read_rgb;
end if;
-- Immediately go idle
when valid_pulse =>
cur_sdi_state <= idle;
when others =>
end case;
end if;
end process;
data_in_process : process(serial_clk_in, reset_n)
begin
if reset_n = '0' then
elsif rising_edge(serial_clk_in) then
case cur_sdi_state is
when idle =>
send_valid <= '0';
when read_mics =>
-- "Shift in" the number of microphones
sdo_mics_r <= to_integer(unsigned(parallel_data_r(8*n_mic_byte_width-1 downto 0)));
read_word_bits <= 8*n_mic_byte_width;
when read_enable =>
-- "Shift in" the mic configuration
cfg_data_r <= parallel_data_r(8*cfg_byte_width-1 downto 0);
read_word_bits <= 8*cfg_byte_width;
when read_rgb =>
-- "Shift in" the rbg LED configuration
rgb_data_r <= parallel_data_r(8*rgb_byte_width-1 downto 0);
read_word_bits <= 8*rgb_byte_width;
when valid_pulse =>
--sdo_mics <= sdo_mics_r;
send_valid <= '1';
when others =>
end case;
end if;
end process;
sdi_data_valid_transition_process : process(sys_clk,reset_n)
begin
if reset_n = '0' then
sdi_valid_state <= idle;
elsif rising_edge(sys_clk) then
case sdi_valid_state is
when idle =>
-- Once the data has been read in, send a valid pulse at the system clock frequency (Avalon streaming)
if send_valid = '1' then
sdi_valid_state <= pulse;
-- Otherwise, stay idle
else
sdi_valid_state <= idle;
end if;
when pulse =>
-- Transition to the wait state
sdi_valid_state <= low_wait;
when low_wait =>
-- When "send" signal goes low (slower clock frequency), go idle again
if send_valid = '0' then
sdi_valid_state <= idle;
-- Otherwise, wait for the valid to go low
else
sdi_valid_state <= low_wait;
end if;
when others =>
end case;
end if;
end process;
sdi_data_valid_process : process(sys_clk,reset_n)
begin
if reset_n = '0' then
rgb_out_valid_r <= '0';
cfg_out_valid_r <= '0';
elsif rising_edge(sys_clk) then
case sdi_valid_state is
when idle =>
-- Do nothing
when pulse =>
-- Pulse the valid Avalon streaming signals
rgb_out_valid_r <= '1';
cfg_out_valid_r <= '1';
when low_wait =>
rgb_out_valid_r <= '0';
cfg_out_valid_r <= '0';
end case;
end if;
end process;
-- Map the RJ45 signals to the output ports
serial_data_out <= shift_data_out(shift_width-1);
-- Map the busy signal
busy_out <= busy;
-- Map the valid signals
rgb_out_valid <= rgb_out_valid_r;
cfg_out_valid <= cfg_out_valid_r;
-- Map the data signals
cfg_out_data <= cfg_data_r;
rgb_out_data <= rgb_data_r;
end architecture rtl;
|
<reponame>va1ery/f32c<gh_stars>1-10
--
-- Copyright (c) 2015 <NAME>
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-- OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-- SUCH DAMAGE.
--
-- $Id$
--
-- EMARD advanced timer
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity timer is
generic (
-- warning: C_ocps + C_icps = 4
C_ocps: integer range 0 to 4 := 2; -- number of ocp units 0-4
C_icps: integer range 0 to 2 := 2; -- number of icp units 0-2
C_period_frac: integer range 0 to 16 := 0; -- period resolution enhancement bits (1-16)
C_have_afc: boolean := true; -- if you don't need AFC, set to false and save some LUTs
C_afc_immediate_sp: boolean := true; -- set to true to save some LUTs, setpoint will be compared against Rtmp instead of R - apply not needed
C_have_intr: boolean := true;
-- setting C_period_frac to 0 will disable both period and frac
-- period and frac registers can be used for AFC limits
C_pres: integer range 0 to 32 := 10; -- number of prescaler bits (0-32)
C_bits: integer range 2 to 32 := 12 -- bit size of the timer (2-32)
);
port (
ce, clk: in std_logic;
bus_write: in std_logic;
addr: in std_logic_vector(3 downto 0); -- address 16 registers
byte_sel: in std_logic_vector(3 downto 0);
bus_in: in std_logic_vector(31 downto 0);
bus_out: out std_logic_vector(31 downto 0);
timer_irq: out std_logic; -- interrut requuest line (active level high)
sign: out std_logic; -- output MSB (sign) bit
icp_enable: out std_logic_vector(C_icps-1 downto 0); -- input enable bits
ocp_enable: out std_logic_vector(C_ocps-1 downto 0); -- output enable bits
icp: in std_logic_vector(C_icps-1 downto 0); -- input capture signals
ocp: out std_logic_vector(C_ocps-1 downto 0) -- output compare signals
);
end timer;
architecture arch of timer is
constant C_addr_bits: integer := 4; -- number of register address bits
constant C_registers: integer := 16; -- total number of timer registers
-- register R(0) counter is kept in separated register so it
-- can be incremented in processs block seprate from R(x)
-- R(15) is apply and it doesn't need to be kept in memory
-- however we will create all 16 registers and leave it up
-- to optimizer to reduce unused rather than make code more complex
constant C_ext_registers: integer := 3; -- total number of extended registers by C_pres bits
-- normal registers
type timer_reg_type is array (C_registers-1 downto 0) of std_logic_vector(C_bits-1 downto 0);
signal R, Rtmp: timer_reg_type; -- register access from mmapped I/O R: active register, Rtmp temporary
-- extended registers
type timer_ext_reg_type is array (C_ext_registers-1 downto 0) of std_logic_vector(C_pres-1 downto 0);
signal Rx, Rxtmp: timer_ext_reg_type; -- register access from mmapped I/O Rx: active register, Rxtmp temporary
-- active registers for the timer logic (copied when writing to apply register
signal commit: std_logic; -- detects a write cycle to apply register
-- period enhancement register and its next value
signal R_fractional, L_fractional_next: std_logic_vector(C_period_frac downto 0);
constant C_ctrl_bits: integer := 24; -- number of control bits
-- extension for increment register for missing prescaler bits in addressable storage
-- extended increment register naming
signal R_increment, R_inc_min, R_inc_max, R_increment_faster, R_increment_slower:
std_logic_vector(C_bits+C_pres-1 downto 0);
-- aggregate signal to run increment faster or slower
signal R_faster, R_slower: std_logic;
-- extension for control register (this extension is different than C_ext_registers)
signal Rtmp_ctrl_ext, R_ctrl_ext: std_logic_vector(C_ctrl_bits-C_bits-1 downto 0);
-- complete control register (extended if needed)
signal Rtmp_control, R_control: std_logic_vector(C_ctrl_bits-1 downto 0);
-- max number of ocp/icp units determined by fixed
-- register locations in address space - to allocate address space
constant C_icps_max: integer := 2;
constant C_ocps_max: integer := 4;
-- max combined icps and ocps. Condition:
-- C_iocps_max >= C_icps_max
-- C_iocps_max >= C_ocps_max
-- C_iocps_max <= C_icps_max+C_ocps_max
constant C_iocps_max: integer := 4;
-- *** REGISTERS ***
-- named constants for the timer registers
-- this improves code readability
-- and provides flexible register (re)numbering
constant C_counter: integer := 0;
constant C_increment: integer := 1;
constant C_inc_min: integer := 2; -- used as minimum AFC increment
constant C_inc_max: integer := 3; -- used as maximum AFC increment
constant C_period: integer := C_inc_min; -- unused if C_period_frac=0
constant C_fractional: integer := C_inc_max; -- unused if C_period_frac=0
type ocp_array is array (0 to C_ocps_max-1) of integer range 0 to C_registers-1;
constant C_ocpn_start: ocp_array := (4, 6, 8, 10);
constant C_ocpn_stop: ocp_array := (5, 7, 9, 11);
type icp_array is array (0 to C_icps_max-1) of integer range 0 to C_registers-1;
constant C_icpn_start: icp_array := (10, 8); -- numbering goes downwards
constant C_icpn_stop: icp_array := (11, 9);
constant C_icpn: icp_array := (12, 13); -- 2 input capture registers, memory used for AFC ICP setpoint
constant C_control: integer := 14;
constant C_apply: integer := 15; -- no need for memory
-- extended registers by C_pres bits
-- array of registers R and Rtmp that have extension
-- required in the for-generate loop for register extension
type ext_array is array (0 to C_ext_registers-1) of integer range 0 to C_registers-1;
constant C_ext: ext_array := (C_increment, C_inc_min, C_inc_max);
-- named indexes of the Rx extended registers
constant C_xincrement: integer := 0;
constant C_xinc_min: integer := 1;
constant C_xinc_max: integer := 2;
-- *** CONTROL BITS ***
-- constants to name bit position in control register
type ctrl_ocp_array is array (0 to C_ocps_max-1) of integer range 0 to C_ctrl_bits-1;
type ctrl_icp_array is array (0 to C_icps_max-1) of integer range 0 to C_ctrl_bits-1;
constant C_ocpn_intr: ctrl_ocp_array := (0,1,2,3); -- ocp interrupt flags (must occupy lowest index)
constant C_icpn_intr: ctrl_icp_array := (3,2); -- icp interrupt flags (must occupy lowest index)
constant C_ocpn_and: ctrl_ocp_array := (4,5,6,7); -- ocp 1=and,0=or condition (for wraparound)
constant C_icpn_and: ctrl_icp_array := (7,6); -- icp 1=and,0=or condition (for wraparound)
constant C_ocpn_ie: ctrl_ocp_array := (8,9,10,11); -- ocp interrupt enable
constant C_icpn_ie: ctrl_icp_array := (11,10); -- icp interrupt enable
constant C_ocpn_xor: ctrl_ocp_array := (12,13,14,15); -- ocp xor 1=inverted,0=normal
constant C_icpn_xor: ctrl_icp_array := (15,14); -- icp xor 1=inverted,0=normal
constant C_icpn_afcen: ctrl_icp_array := (16,18); -- enable ICP AFC
constant C_icpn_afcinv: ctrl_icp_array := (17,19); -- invert ICP AFC logic
constant C_ocpn_enable: ctrl_ocp_array := (20,21,22,23); -- ocp physical output enable bits
constant C_icpn_enable: ctrl_icp_array := (23,22); -- icp physical input enable bits
signal R_counter: std_logic_vector(C_bits+C_pres-1 downto 0); -- handled specificaly (auto-increments)
-- input capture related registers
type icp_reg_type is array (0 to C_icps-1) of std_logic_vector(C_bits-1 downto 0);
signal R_icp: icp_reg_type;
constant C_icp_sync_depth: integer := 3; -- number of shift register stages (default 3) for icp clock synchronization
type T_icp_sync_shift is array (0 to C_icps-1) of std_logic_vector(C_icp_sync_depth-1 downto 0); -- icp synchronizer type
signal R_icp_sync_shift: T_icp_sync_shift;
signal R_icp_rising_edge: std_logic_vector(C_icps-1 downto 0);
signal R_icp_hit: std_logic_vector(C_icps-1 downto 0); -- becomes 1 when icp condition is met
signal R_icp_lt_sp: std_logic_vector(C_icps-1 downto 0); -- becomes 1 when icp is less than setpoint
signal R_icp_wants_faster: std_logic_vector(C_icps-1 downto 0);
signal R_icp_wants_slower: std_logic_vector(C_icps-1 downto 0);
-- output compare related registers
--type ocp_reg_type is array (0 to C_ocps_max-1) of std_logic_vector(C_bits-1 downto 0);
--signal R_ocp_start, R_ocp_stop: ocp_reg_type;
constant C_ocp_sync_depth: integer := 2; -- number of shift register stages (default 2) for ocp edge detection
type T_ocp_sync_shift is array (0 to C_ocps-1) of std_logic_vector(C_ocp_sync_depth-1 downto 0); -- ocp synchronizer type
signal R_ocp_sync_shift: T_ocp_sync_shift;
signal R_ocp_rising_edge: std_logic_vector(C_ocps-1 downto 0);
signal R_ocp: std_logic_vector(C_ocps-1 downto 0);
-- interrupt flag register (both icp and ocp)
-- addressed by C_ocpn_intr and C_icpn_intr
signal Rintr: std_logic_vector(C_iocps_max-1 downto 0);
signal internal_ocp: std_logic_vector(C_ocps-1 downto 0); -- non-inverted ocp signal
-- both true and false should provide the same result
-- with different number of LUTs used
constant C_afc_joint_register : boolean := true;
-- true: afc joint register is true combinatorial logic
-- false: if optimizer is good it will produce combinatorial logic
-- function to join all interrupt bits into one
impure function interrupt(n_ocps, n_icps: integer) return std_logic is
variable i: integer;
variable intr: std_logic;
begin
intr := '0';
if C_have_intr then
for i in 0 to n_ocps-1 loop
intr := intr or (R_control(C_ocpn_ie(i)) and Rintr(C_ocpn_intr(i)));
end loop;
for i in 0 to n_icps-1 loop
intr := intr or (R_control(C_icpn_ie(i)) and Rintr(C_icpn_intr(i)));
end loop;
end if;
return intr;
end interrupt;
-- function to return value to the bus when reading registers
-- flexible for variable number of icps
impure function busoutput(a: std_logic_vector(C_addr_bits-1 downto 0)) return std_logic_vector is
variable i, adr: integer;
variable retval: std_logic_vector(31 downto 0);
begin
adr := conv_integer(a);
retval := ext(Rtmp(adr),32); -- default value
if adr = C_counter then
-- counter is separate from R
retval := ext(R_counter(C_bits+C_pres-1 downto C_pres), 32);
end if;
if adr = C_increment then
-- increment is separate from R
retval := ext(R_increment, 32);
end if;
if adr = C_control then
-- control has extended bits - separate from R
retval := ext(Rtmp_control(C_ctrl_bits-1 downto C_iocps_max) & Rintr,32);
end if;
for i in 0 to C_icps-1 loop
-- input capture value is read (from R)
-- setpoint in Rtmp is unreadable
if adr = C_icpn(i) then
retval := ext(R_icp(i), 32);
end if;
end loop;
return retval;
end busoutput;
begin
bus_out <= busoutput(addr);
sign <= R_counter(C_bits+C_pres-1); -- output sign (MSB bit of the counter)
-- this will save us some typing
commit <= '1' when ce = '1' and bus_write = '1' and addr = C_apply else '0';
-- next value of the enhancement register
next_fractional_value: if C_period_frac > 0 generate
with R_fractional(C_period_frac) select
L_fractional_next <= R_fractional - ('0' & R(C_fractional)(C_period_frac-1 downto 0)) + ('1' & (C_period_frac-1 downto 0 => '0')) when '1',
R_fractional - ('0' & R(C_fractional)(C_period_frac-1 downto 0)) when others;
end generate;
-- extended increment
R_increment <= Rx(C_xincrement) & R(C_increment);
-- AFC increment control and extended limits
afc_faster_slower: if C_have_afc generate
R_inc_min <= Rx(C_xinc_min) & R(C_inc_min);
R_inc_max <= Rx(C_xinc_max) & R(C_inc_max);
R_increment_faster <= R_increment+1;
R_increment_slower <= R_increment-1;
end generate;
faster_slower_afc: if C_have_afc and C_afc_joint_register generate
-- takes more LUT than old_faster_slower_afc?
for_icp_afc: for i in 0 to C_icps-1 generate
R_icp_wants_faster(i) <= '1'
when R_icp_hit(i) = '1' -- icp hit
-- previous icp value less than the setpoint
and ( R_icp_lt_sp(i)='1' xor R_control(C_icpn_afcinv(i))='1' )
and R_control(C_icpn_afcen(i)) = '1' -- and afc is enabled
else '0';
R_icp_wants_slower(i) <= '1'
when R_icp_hit(i) = '1' -- icp hit
-- previous icp value greater than the setpoint
and ( R_icp_lt_sp(i)='0' xor R_control(C_icpn_afcinv(i))='1' )
and R_control(C_icpn_afcen(i)) = '1' -- and afc is enabled
else '0';
end generate;
R_faster <= '1' when R_increment < R_inc_max and R_icp_wants_faster /= 0 else '0';
R_slower <= '1' when R_increment > R_inc_min and R_icp_wants_slower /= 0 else '0';
end generate;
old_faster_slower_afc: if C_have_afc and not C_afc_joint_register generate
-- looks like it could be written shorter
-- optimizer should recognize this as combinatorial logic
process(clk)
variable faster : std_logic;
variable slower : std_logic;
begin
faster := '0';
slower := '0';
for i in 0 to C_icps-1 loop
if R_icp_hit(i) = '1' -- afc hit
-- previous icp value less than the setpoint
and ( R_icp_lt_sp(i)='1' xor R_control(C_icpn_afcinv(i))='1' )
and R_control(C_icpn_afcen(i)) = '1' -- and afc is enabled
then
faster := '1';
end if;
if R_icp_hit(i) = '1' -- afc hit
-- previous icp value less than the setpoint
and ( R_icp_lt_sp(i)='0' xor R_control(C_icpn_afcinv(i))='1' )
and R_control(C_icpn_afcen(i)) = '1' -- and afc is enabled
then
slower := '1';
end if;
end loop;
if R_increment < R_inc_max and faster = '1' then
R_faster <= '1';
else
R_faster <= '0';
end if;
if R_increment > R_inc_min and slower = '1' then
R_slower <= '1';
else
R_slower <= '0';
end if;
end process;
end generate;
-- extended control register
extended_control_register: if C_ctrl_bits > C_bits generate
R_control <= R_ctrl_ext & R(C_control);
Rtmp_control <= Rtmp_ctrl_ext & Rtmp(C_control);
end generate;
trimmed_control_register: if C_ctrl_bits <= C_bits generate
R_control <= R(C_control)(C_ctrl_bits-1 downto 0);
Rtmp_control <= Rtmp(C_control)(C_ctrl_bits-1 downto 0);
end generate;
-- join all interrupt request bits into one bit
timer_irq <= interrupt(C_ocps, C_icps);
-- counter
process(clk)
begin
if rising_edge(clk) then
-- writing bit in apply register will commit change to counter
if commit = '1' and bus_in(C_counter)='1' then
R_counter(C_bits+C_pres-1 downto C_pres) <= Rtmp(C_counter); -- write from temporary to counter
else
if C_period_frac = 0 then
R_counter <= R_counter + R_increment;
else
if R_counter(C_bits+C_pres-1 downto C_pres) < R(C_period) + R_fractional(C_period_frac) then
R_counter <= R_counter + R_increment;
else
R_counter <= (others => '0');
R_fractional <= L_fractional_next;
end if;
end if;
end if;
-- debug purpose: increment when reading LSB
-- if ce = '1' and bus_write = '0' and byte_sel(0) = '1' then
-- R(counter) <= R(counter) + 1;
-- end if;
end if;
end process;
output_compare: for i in 0 to C_ocps-1 generate
internal_ocp(i) <= '1' when
( R_control(C_ocpn_and(i))='0'
and ( R_counter(C_bits+C_pres-1 downto C_pres) >= R(C_ocpn_start(i))
or R_counter(C_bits+C_pres-1 downto C_pres) < R(C_ocpn_stop(i)) ) )
or ( R_control(C_ocpn_and(i))='1'
and ( R_counter(C_bits+C_pres-1 downto C_pres) >= R(C_ocpn_start(i))
and R_counter(C_bits+C_pres-1 downto C_pres) < R(C_ocpn_stop(i)) ) )
else '0';
glitchfree_ocp_if_not_have_interrupt:
if not C_have_intr generate
process(clk)
begin
-- Store the OCP in output register to avoid possible nanosecond glitch
-- in "OR" mode at zero-crossing of the counter. Glitch is a side-effect of
-- propagation delay in the combinatorial logic of internal_ocp(i).
if rising_edge(clk) then
R_ocp(i) <= internal_ocp(i) xor R_control(C_ocpn_xor(i)); -- output optionally inverted
end if;
end process;
ocp(i) <= R_ocp(i);
end generate;
glitchfree_ocp_if_have_interrupt:
if C_have_intr generate
-- similar as above but with less LUTs
-- R_ocp_sync_shift(i)(0) is internal_ocp(i) stored in register
-- and it should be glitch-free
ocp(i) <= R_ocp_sync_shift(i)(0) xor R_control(C_ocpn_xor(i)); -- output optionally inverted
end generate;
ocp_enable(i) <= R_control(C_ocpn_enable(i));
ocp_interrupt: if C_have_intr generate
-- ocp synchronizer (2-stage shift register)
process(clk)
begin
if rising_edge(clk) then
R_ocp_sync_shift(i)(C_ocp_sync_depth-1 downto 1) <= R_ocp_sync_shift(i)(C_ocp_sync_depth-2 downto 0);
R_ocp_sync_shift(i)(0) <= internal_ocp(i); -- non-iverted ocp is fed here
end if;
end process;
-- difference in 2 last bits of the shift register detect synchronous rising edge
-- when at C_ocp_sync_depth-1 is 0, and one clock earlier at C_ocp_sync_depth-2 is 1
R_ocp_rising_edge(i) <= '1' when
R_ocp_sync_shift(i)(C_ocp_sync_depth-1) = '0' -- it was 0
and R_ocp_sync_shift(i)(C_ocp_sync_depth-2) = '1' -- 1 is coming after 0
else '0';
-- *** OCP INTERRUPT ***
-- write cycle with bits 0 to Rtmp(C_control) register will reset interrupt flag
-- no write to apply register is needed to clear the flag
process(clk)
begin
if rising_edge(clk) then
-- chack for rising edge of ocp
if R_ocp_rising_edge(i) = '1' then
Rintr(C_ocpn_intr(i)) <= '1';
else
-- writing 1 to Rtmp(C_control)(C_ocpn_intr(i))
-- will immediately reset interrupt flags
-- (without need for writing to apply register)
if ce = '1' and bus_write = '1' and addr = C_control
and bus_in(C_ocpn_intr(i)) = '1' and byte_sel(C_ocpn_intr(i)/8) = '1' then
Rintr(C_ocpn_intr(i)) <= '0';
end if;
end if;
end if;
end process;
end generate; -- end ocp_interrupt
end generate; -- end output_compare
-- warning - asynchronous external icp rising edge
-- should be passed to async->sync filter to match
-- the input clock and then be processed.
-- here is theory and schematics about 3-stage shift register
-- https://www.doulos.com/knowhow/fpga/synchronisation/
-- here is vhdl implementation of the 3-stage shift register
-- http://www.bitweenie.com/listings/vhdl-shift-register/
input_capture: for i in 0 to C_icps-1 generate
icp_enable(i) <= R_control(C_icpn_enable(i));
-- icp synchronizer (3-stage shift register)
process(clk)
begin
if rising_edge(clk) then
R_icp_sync_shift(i)(C_icp_sync_depth-1 downto 1) <= R_icp_sync_shift(i)(C_icp_sync_depth-2 downto 0);
R_icp_sync_shift(i)(0) <= icp(i);
end if;
end process;
-- difference in 2 last bits of the shift register detect synchronous rising edge
-- when at C_icp_sync_depth-1 is 0, and one clock earlier at C_icp_sync_depth-2 is 1
R_icp_rising_edge(i) <= '1' when
(R_icp_sync_shift(i)(C_icp_sync_depth-1) = ('0' xor R_control(C_icpn_xor(i))) ) -- it was 0
and (R_icp_sync_shift(i)(C_icp_sync_depth-2) = ('1' xor R_control(C_icpn_xor(i))) ) -- 1 is coming after 0
else '0';
-- detect ICP HIT condition
R_icp_hit(i) <= '1' when R_icp_rising_edge(i) = '1' and
( ( R_control(C_icpn_and(i))='0' -- OR combination
and ( R_counter(C_bits+C_pres-1 downto C_pres) >= R(C_icpn_start(i))
or R_counter(C_bits+C_pres-1 downto C_pres) < R(C_icpn_stop(i)) ) )
or ( R_control(C_icpn_and(i))='1' -- AND combination
and ( R_counter(C_bits+C_pres-1 downto C_pres) >= R(C_icpn_start(i))
and R_counter(C_bits+C_pres-1 downto C_pres) < R(C_icpn_stop(i)) ) )
) else '0';
-- process based on clock synchronous icp
process(clk)
begin
-- icp-initiated copying of R_counter register must be
-- clock synchronous. When content of R_counter
-- becomes stable then it can be copied to R_icp(i)
if rising_edge(clk) then
if R_icp_hit(i) = '1' then
R_icp(i) <= R_counter(C_bits+C_pres-1 downto C_pres);
end if;
end if;
end process;
icp_interrupt: if C_have_intr generate
-- *** ICP INTERRUPT ***
-- write cycle with bits 0 to Rtmp(C_control) register will reset interrupt flag
-- no write to apply register is needed to clear the flag
process(clk)
begin
if rising_edge(clk) then
-- chack for rising edge of ocp
if R_icp_rising_edge(i) = '1' then
Rintr(C_icpn_intr(i)) <= '1';
else
-- writing 1 to Rtmp(C_control)(C_icpn_intr(i))
-- will immediately reset interrupt flags
-- (without need for writing to apply register)
if ce = '1' and bus_write = '1' and addr = C_control
and bus_in(C_icpn_intr(i)) = '1' and byte_sel(C_icpn_intr(i)/8) = '1' then
Rintr(C_icpn_intr(i)) <= '0';
end if;
end if;
end if;
end process;
end generate; -- end icp_interrupt
applied_sp: if C_have_afc and not C_afc_immediate_sp generate
-- AFC: compare actual ICP value (R_icp) with setpoint (R), need apply to activate
R_icp_lt_sp(i) <= '1' when R_icp(i) < R(C_icpn(i)) else '0'; -- test: is icp less than setpoint?
end generate;
immediate_sp: if C_have_afc and C_afc_immediate_sp generate
-- AFC: compare actual ICP value (R_icp) with setpoint (Rtmp), immediately active, no apply
R_icp_lt_sp(i) <= '1' when R_icp(i) < Rtmp(C_icpn(i)) else '0'; -- test: is icp less than setpoint?
end generate;
end generate; -- end input capture
-- writing from temporary registers to active registers
-- this is 'apply' register actually this is not a real register
-- just a location to write
commit_Rtmp_to_R: for i in 0 to C_registers-1 generate
process(clk)
begin
if rising_edge(clk) then
if commit = '1' then
if bus_in(i) = '1' and byte_sel(i/8) = '1' then
R(i) <= Rtmp(i);
end if;
else
-- if not commit (begin)
-- if ICP hit, copy counter value to active register
-- emard: doin this here is dirty but allows to write ICP
--for j in 0 to C_icps-1 loop
-- if i = C_icpn(j) then
-- if R_icp_hit(j) = '1' then
-- R(i) <= R_counter(C_bits+C_pres-1 downto C_pres);
-- end if;
-- end if;
--end loop;
-- special case for AFC
-- AFC of the increment step using ICP
-- R(C_increment) contains lower bits
if C_have_afc then
if i = C_increment then
if R_faster = '1' and R_slower = '0' then
R(i) <= R_increment_faster(C_bits-1 downto 0);
end if;
if R_slower = '1' and R_faster = '0' then
R(i) <= R_increment_slower(C_bits-1 downto 0);
end if;
end if;
end if;
-- if not commit (end)
end if;
end if;
end process;
end generate; -- end writing Rtmp to R
-- commit extra prescaler bits for increment
commit_extended_Rtmp_to_R: for i in 0 to C_ext_registers-1 generate
process(clk)
begin
if rising_edge(clk) then
if commit = '1' then
if bus_in(C_ext(i)) = '1' and byte_sel(C_ext(i)/8) = '1' then
Rx(i) <= Rxtmp(i);
end if;
end if;
-- special case for AFC
-- Rx(C_xincrement) contains extended higher bits
if C_have_afc and i = C_xincrement then
if R_faster = '1' and R_slower = '0' then
Rx(i) <= R_increment_faster(C_bits+C_pres-1 downto C_bits);
end if;
if R_slower = '1' and R_faster = '0' then
Rx(i) <= R_increment_slower(C_bits+C_pres-1 downto C_bits);
end if;
end if;
end if;
end process;
end generate; -- end writing Rxtmp to Rx
-- commit extra control bits for increment
commit_extra_control_bits: if C_ctrl_bits > C_bits generate
process(clk)
begin
if rising_edge(clk) then
if commit = '1' then
if bus_in(C_control) = '1' and byte_sel(C_control/8) = '1' then
R_ctrl_ext <= Rtmp_ctrl_ext;
end if;
end if;
end if;
end process;
end generate;
-- writing from bus to temporary registers
process(clk)
variable i: integer := 0;
begin
if rising_edge(clk) then
if ce = '1' and bus_write = '1' then
byte_write: for i in 0 to C_bits/8-1 loop
if byte_sel(i) = '1' then
Rtmp(conv_integer(addr))(8*i+7 downto 8*i) <= bus_in(8*i+7 downto 8*i);
end if;
end loop;
-- partial byte remaining?
if (C_bits mod 8) > 0 then
if byte_sel(C_bits/8) = '1' then
Rtmp(conv_integer(addr))(C_bits-1 downto (C_bits/8)*8) <= bus_in(C_bits-1 downto (C_bits/8)*8);
end if;
end if;
end if;
end if;
end process;
-- write extended temporary bits to Rxtmp(i)(C_pres-1 downto 0)
-- TODO/FIXME do we need byte_write here, same as above?
write_Rxtmp: for i in 0 to C_ext_registers-1 generate
process(clk)
begin
if rising_edge(clk) then
if ce = '1' and bus_write = '1' and addr = C_ext(i) then
Rxtmp(i)(C_pres-1 downto 0) <= bus_in(C_bits+C_pres-1 downto C_bits);
end if;
end if;
end process;
end generate;
-- write extra control bits to Rtmp_ctrl_ext(C_ctrl_bits-C_bits-1 downto 0)
write_Rtmp_extra_control_bits: if C_ctrl_bits > C_bits generate
process(clk)
begin
if rising_edge(clk) then
if ce = '1' and bus_write = '1' and addr = C_control then
Rtmp_ctrl_ext(C_ctrl_bits-C_bits-1 downto 0) <= bus_in(C_ctrl_bits-1 downto C_bits);
end if;
end if;
end process;
end generate;
end;
-- todo
-- additional resolution for the period
-- extra 4 or 8 bits
-- timer registers can be up to 32 bits,
-- lower bit width is possible
-- they can be written with a single 32-bit write
-- registers (multply C_register_name by 4 to get byte offset)
-- timer control register
-- 1: R_timer_control
-- *** byte 0 : interrupts flags, output mixing ***
-- bit 0: interrupt ocp0 flag 1=pending 0=resolved (write 1 to resolve)
-- bit 1: interrupt ocp1 flag 1=pending 0=resolved (write 1 to resolve)
-- bit 2: interrupt icp1 flag 1=pending 0=resolved (write 1 to resolve)
-- bit 3: interrupt icp0 flag 1=pending 0=resolved (write 1 to resolve)
-- bit 4: output compare 0 filter select 1=and 0=or (ocpc1)
-- 0 (or): ocpc1 = (R_counter >= R_ocp0_start or R_counter < R_ocp1_start)
-- 1 (and): ocpc1 = (R_counter >= R_ocp1_start and R_counter < R_ocp1_start)
-- bit 5: output compare 1 filter select 1=and 0=or (ocpc2 similar as above)
-- bit 6: input capture 1 filter select 1=and 0=or (icp0 as above)
-- bit 7: input capture 0 filter select 1=and 0=or (icp1 as above)
-- *** byte 1 : interrupt enable, AFC enable ***
-- bit 0: interrupt ocp0 1=enable 0=disable
-- bit 1: interrupt ocp1 1=enable 0=disable
-- bit 2: interrupt icp1 1=enable 0=disable
-- bit 3: interrupt icp0 1=enable 0=disable
-- bit 4: interrupt ocp0 xor (physical output line invert)
-- bit 5: interrupt ocp1 xor (pyhsical output line invert)
-- bit 6: interrupt icp1 xor 0-rising edge, 1-falling edge
-- bit 7: interrupt icp0 xor 0-rising edge, 1-falling edge
-- *** byte 2 : input/output inverters ***
-- bit 0: AFC icp0 enable. 0=Off 1=On
-- bit 1: AFC icp0 invert. 0=normal 1=inverted
-- bit 2: AFC icp1 enable. 0=Off 1=On
-- bit 3: AFC icp1 invert. 0=normal 1=inverted
-- apply: registar to apply timer changes
-- writing bit 1 to this register will apply changes
-- to appropriate timer register
-- except itself, applied immediately :)
-- bit 0: counter
-- bit 1: period
-- ...
-- etc. bits, the same order as in the register R()
-- output compare register components muxing to physical output:
-- hardcoded in hdl
-- physical output A = ocpc1 or ocpc2
-- physical output B = ocpc1 and ocpc2
-- filter for input capture (lower and upper limit register)
-- input capture will happen in selectable and/or condition
-- when counter is within this range
-- R_icp_low <= counter < R_icp_high
-- purpose of AND/OR:
-- when R_icp_low < R_icp_high, use AND
-- when R_icp_low > R_icp_high, use OR (outputs signal during wraparound phase)
-- todo
-- [x] selectable inverter for input
-- [ ] input inverter testing
-- [x] selectable inverter for output
-- [ ] output inverter testing
-- [x] make variable C_bits work for values other than 32
-- [x] generate icp/ocp units: if no units, all registers are generated
-- can save some LE to also leave out unused registers
-- [x] signals for interrupts
-- [x] prescaler for R_increment
-- [x] different number of bits for control and apply register
-- [x] separate temporary and active registers, apply to copy
-- [x] the period, with resolution enhancement
-- [x] generalized apply to registers, one for-generate loop
-- [x] can leave out period and fractional
-- [ ] optionally with or without Rtmp and apply
-- [x] different number of bits for increment,
-- different number of control, apply
-- [ ] possible optimizations in R, Rtmp
-- counter, period, apply, control -- some memory is not used
-- [x] AFC icp -> increment steering
-- [x] AFC control bits for AFC icp
-- [x] AFC upper and lower limits of increment
-- [x] replace R(C_control) with R_control
-- [x] R_control needs testing
-- [x] afc controlled icrement is now readable
-- [x] flags to enable/disable icp/ocp interrupts
-- [x] extend afc limit registers, remove C_afc_limit_shift
-- [ ] 8-bit write maybe doesn't work for extended registers - need testing
-- [x] reorder registers: ocp rising addr, icp falling addr
-- [x] AFC setpoint in icp hidden memory, one ICP sufficient for AFC
-- [x] inverse AFC
-- [ ] one-shot operation
-- [x] R_icp_intr_flag has different numbering than C_icpn_intr
-- [ ] allow interrupt at stop of ocp
-- [ ] separate register write for control word
-- [ ] allow shared use of ocp and icp registers (e.g. 3 ocp and 1 icp)
-- [ ] support bus_out for 0-2 icps (now errors if C_icps not 2)
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_package.all;
entity TB_wkn_selector is
end entity TB_wkn_selector;
architecture TB_wkn_selector_ARCH of TB_wkn_selector is
component WKN_SELECTOR is
port(
input : in std_logic_vector(5 downto 0);
output : out complex12 := ( c => '0', l => (s => '0', m => "000000000000"), r => (s => '0', m => "000000000000"))
);
end component WKN_SELECTOR;
signal input : std_logic_vector (5 downto 0);
signal output : complex12 := (c => '0', l => (s => '0', m => "000000000000"), r => (s => '0', m => "000000000000"));
begin
ws : WKN_SELECTOR port map(input=> input, output=> output);
process
begin
for i in 0 to 63 loop
input <= std_logic_vector(to_unsigned(i,input'length));
wait for 50 ns;
end loop;
wait;
end process;
end TB_wkn_selector_ARCH;
|
------------------------------------------------------
--! @file comp4.vhdl
--! @brief
--! @author <NAME> (<EMAIL>)
--! @date 06/2020
-------------------------------------------------------
entity comp4 is
port
(
A, B: in bit_vector (3 downto 0);
igual, diferente: out bit;
maior, maior_igual: out bit;
menor, menor_igual: out bit
);
end entity;
architecture comportamental of comp4 is
begin
process (A, B)
begin
igual<= '0'; diferente<= '0'; maior<= '0';
maior_igual<= '0'; menor <= '0'; menor_igual <= '0';
if A = B then igual<= '1'; end if;
if A /= B then diferente<= '1'; end if;
if A > B then maior<= '1'; end if;
if A >= B then maior_igual<= '1'; end if;
if A < B then menor <= '1'; end if;
if A <= B then menor_igual <= '1'; end if;
end process;
end architecture;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
-- Version: 2020.1
-- Copyright (C) 1986-2020 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dummy_fe is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
din_i_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
din_i_V_empty_n : IN STD_LOGIC;
din_i_V_read : OUT STD_LOGIC;
din_q_V_dout : IN STD_LOGIC_VECTOR (15 downto 0);
din_q_V_empty_n : IN STD_LOGIC;
din_q_V_read : OUT STD_LOGIC;
out_V_din : OUT STD_LOGIC_VECTOR (15 downto 0);
out_V_full_n : IN STD_LOGIC;
out_V_write : OUT STD_LOGIC );
end;
architecture behav of dummy_fe is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
constant ap_const_lv12_9C4 : STD_LOGIC_VECTOR (11 downto 0) := "100111000100";
constant ap_const_lv12_1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_boolean_1 : BOOLEAN := true;
signal real_start : STD_LOGIC;
signal start_once_reg : STD_LOGIC := '0';
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (2 downto 0) := "001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal internal_ap_ready : STD_LOGIC;
signal din_i_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal icmp_ln140_fu_65_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal din_q_V_blk_n : STD_LOGIC;
signal out_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal i_fu_71_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal i_reg_80 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_block_state2 : BOOLEAN;
signal din_q_V_read_reg_85 : STD_LOGIC_VECTOR (15 downto 0);
signal i_0_reg_54 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_block_state1 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (2 downto 0);
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif ((not((((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_q_V_empty_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (out_V_full_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_i_V_empty_n = ap_const_logic_0)))) and (icmp_ln140_fu_65_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
start_once_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
start_once_reg <= ap_const_logic_0;
else
if (((internal_ap_ready = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_once_reg <= ap_const_logic_1;
elsif ((internal_ap_ready = ap_const_logic_1)) then
start_once_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_0_reg_54_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((out_V_full_n = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
i_0_reg_54 <= i_reg_80;
elsif ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
i_0_reg_54 <= ap_const_lv12_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_q_V_empty_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (out_V_full_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_i_V_empty_n = ap_const_logic_0)))) and (icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
din_q_V_read_reg_85 <= din_q_V_dout;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not((((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_q_V_empty_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (out_V_full_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_i_V_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
i_reg_80 <= i_fu_71_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, din_i_V_empty_n, din_q_V_empty_n, out_V_full_n, ap_CS_fsm_state2, icmp_ln140_fu_65_p2, ap_CS_fsm_state3)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if ((not((((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_q_V_empty_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (out_V_full_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_i_V_empty_n = ap_const_logic_0)))) and (icmp_ln140_fu_65_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state1;
elsif ((not((((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_q_V_empty_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (out_V_full_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_i_V_empty_n = ap_const_logic_0)))) and (icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state2;
end if;
when ap_ST_fsm_state3 =>
if (((out_V_full_n = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when others =>
ap_NS_fsm <= "XXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_block_state1_assign_proc : process(real_start, ap_done_reg)
begin
ap_block_state1 <= ((real_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state2_assign_proc : process(din_i_V_empty_n, din_q_V_empty_n, out_V_full_n, icmp_ln140_fu_65_p2)
begin
ap_block_state2 <= (((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_q_V_empty_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (out_V_full_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_i_V_empty_n = ap_const_logic_0)));
end process;
ap_done_assign_proc : process(ap_done_reg, din_i_V_empty_n, din_q_V_empty_n, out_V_full_n, ap_CS_fsm_state2, icmp_ln140_fu_65_p2)
begin
if ((not((((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_q_V_empty_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (out_V_full_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_i_V_empty_n = ap_const_logic_0)))) and (icmp_ln140_fu_65_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
begin
if (((real_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready <= internal_ap_ready;
din_i_V_blk_n_assign_proc : process(din_i_V_empty_n, ap_CS_fsm_state2, icmp_ln140_fu_65_p2)
begin
if (((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
din_i_V_blk_n <= din_i_V_empty_n;
else
din_i_V_blk_n <= ap_const_logic_1;
end if;
end process;
din_i_V_read_assign_proc : process(din_i_V_empty_n, din_q_V_empty_n, out_V_full_n, ap_CS_fsm_state2, icmp_ln140_fu_65_p2)
begin
if ((not((((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_q_V_empty_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (out_V_full_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_i_V_empty_n = ap_const_logic_0)))) and (icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
din_i_V_read <= ap_const_logic_1;
else
din_i_V_read <= ap_const_logic_0;
end if;
end process;
din_q_V_blk_n_assign_proc : process(din_q_V_empty_n, ap_CS_fsm_state2, icmp_ln140_fu_65_p2)
begin
if (((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
din_q_V_blk_n <= din_q_V_empty_n;
else
din_q_V_blk_n <= ap_const_logic_1;
end if;
end process;
din_q_V_read_assign_proc : process(din_i_V_empty_n, din_q_V_empty_n, out_V_full_n, ap_CS_fsm_state2, icmp_ln140_fu_65_p2)
begin
if ((not((((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_q_V_empty_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (out_V_full_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_i_V_empty_n = ap_const_logic_0)))) and (icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
din_q_V_read <= ap_const_logic_1;
else
din_q_V_read <= ap_const_logic_0;
end if;
end process;
i_fu_71_p2 <= std_logic_vector(unsigned(i_0_reg_54) + unsigned(ap_const_lv12_1));
icmp_ln140_fu_65_p2 <= "1" when (i_0_reg_54 = ap_const_lv12_9C4) else "0";
internal_ap_ready_assign_proc : process(din_i_V_empty_n, din_q_V_empty_n, out_V_full_n, ap_CS_fsm_state2, icmp_ln140_fu_65_p2)
begin
if ((not((((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_q_V_empty_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (out_V_full_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_i_V_empty_n = ap_const_logic_0)))) and (icmp_ln140_fu_65_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
internal_ap_ready <= ap_const_logic_1;
else
internal_ap_ready <= ap_const_logic_0;
end if;
end process;
out_V_blk_n_assign_proc : process(out_V_full_n, ap_CS_fsm_state2, icmp_ln140_fu_65_p2, ap_CS_fsm_state3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state3) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
out_V_blk_n <= out_V_full_n;
else
out_V_blk_n <= ap_const_logic_1;
end if;
end process;
out_V_din_assign_proc : process(din_i_V_dout, din_i_V_empty_n, din_q_V_empty_n, out_V_full_n, ap_CS_fsm_state2, icmp_ln140_fu_65_p2, ap_CS_fsm_state3, din_q_V_read_reg_85)
begin
if (((out_V_full_n = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
out_V_din <= din_q_V_read_reg_85;
elsif ((not((((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_q_V_empty_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (out_V_full_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_i_V_empty_n = ap_const_logic_0)))) and (icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
out_V_din <= din_i_V_dout;
else
out_V_din <= "XXXXXXXXXXXXXXXX";
end if;
end process;
out_V_write_assign_proc : process(din_i_V_empty_n, din_q_V_empty_n, out_V_full_n, ap_CS_fsm_state2, icmp_ln140_fu_65_p2, ap_CS_fsm_state3)
begin
if ((((out_V_full_n = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state3)) or (not((((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_q_V_empty_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (out_V_full_n = ap_const_logic_0)) or ((icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (din_i_V_empty_n = ap_const_logic_0)))) and (icmp_ln140_fu_65_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2)))) then
out_V_write <= ap_const_logic_1;
else
out_V_write <= ap_const_logic_0;
end if;
end process;
real_start_assign_proc : process(ap_start, start_full_n, start_once_reg)
begin
if (((start_once_reg = ap_const_logic_0) and (start_full_n = ap_const_logic_0))) then
real_start <= ap_const_logic_0;
else
real_start <= ap_start;
end if;
end process;
start_out <= real_start;
start_write_assign_proc : process(real_start, start_once_reg)
begin
if (((start_once_reg = ap_const_logic_0) and (real_start = ap_const_logic_1))) then
start_write <= ap_const_logic_1;
else
start_write <= ap_const_logic_0;
end if;
end process;
end behav;
|
-- Copyright 2017 <NAME>
-- OpenGPU
-- -- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
-- http://www.apache.org/licenses/LICENSE-2.0
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package ogpu_data_record_pkg is
type ogpu_float is
record
-- TODO: implement float point conversion to fix notation
-- sig: std_logic;
-- exp: std_logic_vector(30 downto 23);
-- frac: std_logic_vector(22 downto 0);
int: unsigned(15 downto 0); -- fixed notation for initial implementation
end record;
type ogpu_vertex is
record
x,y,z: ogpu_float;
end record;
type ogpu_box is
record
--x0,y0: ogpu_float;
--x1,y1: ogpu_float;
x0,y0: unsigned(15 downto 0);
x1,y1: unsigned(15 downto 0);
end record;
type ogpu_tile is
record
x0,y0: unsigned(15 downto 0);
x1,y1: unsigned(15 downto 0);
end record;
type ogpu_edge is
record
x0,y0: unsigned(15 downto 0);
x1,y1: unsigned(15 downto 0);
end record;
type ogpu_quad is
record
x0,y0,x1,y1: unsigned(15 downto 0);
x2,y2,x3,y3: unsigned(15 downto 0);
end record;
type ogpu_depth_coefficients is
record
a,b,c: signed(31 downto 0);
end record;
type ogpu_depth_quad is array(0 to 3) of signed(31 downto 0);
type ogpu_setup_in_type is
record
vx0: ogpu_float;
vy0: ogpu_float;
vx1: ogpu_float;
vy1: ogpu_float;
vx2: ogpu_float;
vy2: ogpu_float;
start_raster: std_logic;
end record;
type ogpu_setup_out_type is
record
setup_done: std_logic;
e0: ogpu_edge;
e1: ogpu_edge;
e2: ogpu_edge;
end record;
type ogpu_quad_generator_in_type is
record
clip_rect: ogpu_box;
tile: ogpu_tile;
start_raster: std_logic;
next_quad: std_logic;
end record;
type ogpu_quad_generator_out_type is
record
end_tile: std_logic;
quad_ready: std_logic;
quad: ogpu_quad;
end record;
type ogpu_quad_edge_test_in_type is
record
edge_test: std_logic;
quad: ogpu_quad;
e: ogpu_edge;
end record;
type ogpu_quad_edge_test_out_type is
record
edge_ready: std_logic;
edge_mask: std_logic_vector(0 to 3);
end record;
type ogpu_triangle_edge_test_in_type is
record
edge_ready: std_logic_vector(0 to 2);
edge_mask0: std_logic_vector(0 to 3);
edge_mask1: std_logic_vector(0 to 3);
edge_mask2: std_logic_vector(0 to 3);
end record;
type ogpu_triangle_edge_test_out_type is
record
draw_quad: std_logic;
discard_quad: std_logic;
quad_mask: std_logic_vector(0 to 3);
end record;
type ogpu_depth_test_in_type is
record
depth_coef: ogpu_depth_coefficients;
quad: ogpu_quad;
depth_test: std_logic;
end record;
type ogpu_depth_test_out_type is
record
depth_ready: std_logic;
depth_quad: ogpu_depth_quad;
end record;
type ogpu_quad_store_in_type is
record
quad_mask: std_logic_vector(0 to 3);
quad: ogpu_quad;
depth_quad: ogpu_depth_quad;
start_raster: std_logic;
store_quad: std_logic;
buffer_ack: std_logic;
addr: std_logic_vector(63 downto 0);
end record;
type ogpu_quad_store_out_type is
record
quad_stored: std_logic;
quad_buffer_length: std_logic_vector(23 downto 0);
buffer_address: std_logic_vector(15 downto 0);
buffer_byte_enable: std_logic_vector(7 downto 0);
buffer_write: std_logic;
buffer_write_data: std_logic_vector(63 downto 0);
end record;
type ogpu_command is (OGPU_CMD_NOP,OGPU_CMD_PREPARE,OGPU_CMD_RASTER,OGPU_CMD_ERROR);
function ogpu_std_logic_to_command_func (s: std_logic_vector(7 downto 0)) return ogpu_command;
type ogpu_raster_control_in_type is
record
command: ogpu_command;
setup_done: std_logic;
end_tile: std_logic;
quad_ready: std_logic;
depth_ready: std_logic;
quad_stored: std_logic;
draw_quad: std_logic;
discard_quad: std_logic;
end record;
type ogpu_raster_control_out_type is
record
start_raster: std_logic;
next_quad: std_logic;
edge_test: std_logic;
depth_test: std_logic;
store_quad: std_logic;
busy: std_logic;
done: std_logic;
end record;
end package ogpu_data_record_pkg;
package body ogpu_data_record_pkg is
function ogpu_std_logic_to_command_func (s: std_logic_vector(7 downto 0)) return ogpu_command is
variable r : ogpu_command;
begin
case s is
when "00000000" => r:=OGPU_CMD_NOP;
when "10100101" => r:=OGPU_CMD_PREPARE;
when "10101010" => r:=OGPU_CMD_RASTER;
when others => r:=OGPU_CMD_ERROR;
end case;
return r;
end function;
end package body;
|
<reponame>z1514/Minisystem-Computer-Design
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017
-- Date : Sat Jan 16 02:14:47 2021
-- Host : DESKTOP-HB7J7JB running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ data_memory_0_stub.vhdl
-- Design : data_memory_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tfgg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clock : in STD_LOGIC;
reset : in STD_LOGIC;
Address : in STD_LOGIC_VECTOR ( 31 downto 0 );
Write_data : in STD_LOGIC_VECTOR ( 31 downto 0 );
Mem_write_en_0 : in STD_LOGIC;
Mem_write_en_1 : in STD_LOGIC;
Mem_write_en_2 : in STD_LOGIC;
Mem_write_en_3 : in STD_LOGIC;
Read_data : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clock,reset,Address[31:0],Write_data[31:0],Mem_write_en_0,Mem_write_en_1,Mem_write_en_2,Mem_write_en_3,Read_data[31:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "data_memory,Vivado 2017.4";
begin
end;
|
<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity test_multip is
generic (width:integer:=32);
end entity;
architecture test of test_multip is
component multip
port (ma,mb : in std_logic_vector (width-1 downto 0);--4/8/16/32
clk, rst : in std_logic;
mp : out std_logic_vector (2*width-1 downto 0);--8/16/32/64
done : out std_logic);
end component;
signal mat : std_logic_vector (width-1 downto 0) :="00000000000000000000000000000000";--4/8/16/32
signal mbt : std_logic_vector (width-1 downto 0) :="00000000000000000000000000000000";
signal clkt, rstt, tdone : std_logic;
signal mpt : std_logic_vector (2*width-1 downto 0);--8/16/32/64
signal count : std_logic_vector (width-1 downto 0);
begin
uut : multip port map (ma => mat, mb => mbt, clk => clkt, rst => rstt, mp => mpt, done => tdone);
rstt <='0', '1' after 10 ns;
process
begin
clkt <= '0';
wait for 10 ns;
clkt <= '1';
wait for 10 ns;
end process;
process (clkt, rstt)
begin
if rstt='0' then count <="00000000000000000000000000000000";
elsif (rising_edge(clkt)) then
if count ="00000000000000000000000001100001" then --13 pt 4 biti/25 pt 8 biti/97 pt 32 biti (N*3+1)
count <="00000000000000000000000000000000";
mat <= mat + '1';
mbt <= mbt + '1';
else
count <= count + 1;
end if;
end if;
end process;
end architecture;
|
<gh_stars>1-10
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
<KEY>
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
VV6NOtxC/fftDKl7dQWVSG4bgqElu5t1AjEvQiis5i5O9l0jSMxEdNneTd4fm+42w5c3pRG3EYqY
<KEY>
`protect key_keyowner = "Synopsys", key_keyname= "<KEY>", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16672)
`protect data_block
gqcZQQaSE55q6uwisb/36uKsnLI3TT4A2APgZjnG0L9PIvF32im49VTRIvetA2lhpE41NOa9h0fB
G<KEY>
<KEY>
`protect end_protected
|
----------------------------------------------------------------------------------
-- Company: Univerity of Massachusetts
-- Engineer: <NAME>
--
-- Create Date: 17:50:27 09/19/2010
-- Module Name: scalar_processor - arch
-- Project Name: GPGPU
-- Target Devices:
-- Tool versions: ISE 10.1
-- Description:
--
----------------------------------------------------------------------------
-- Revisions:
-- REV: Date: Description:
-- 0.1.a 9/13/2010 Created Top level file
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.gpgpu_package.all;
entity scalar_processor is
port(
alu_opcode_in : in alu_opcode_type;
instr_subop_in : in std_logic_vector(2 downto 0);
instr_marker_in : in instr_marker_type; -- ADDED GIANLUCA ROASCIO
src1_in : in std_logic_vector(31 downto 0);
src2_in : in std_logic_vector(31 downto 0);
src3_in : in std_logic_vector(31 downto 0);
src1_neg_in : in std_logic; -- NOT USED
src2_neg_in : in std_logic; -- NOT USED
src3_neg_in : in std_logic;
carry_in : in std_logic;
saturate_in : in std_logic;
w32_in : in std_logic;
is_signed_in : in std_logic;
abs_saturate_in : in std_logic_vector(1 downto 0);
cvt_neg_in : in std_logic;
cvt_type_in : in std_logic_vector(2 downto 0);
set_cond_in : in std_logic_vector(2 downto 0);
carry_out : out std_logic;
overflow_out : out std_logic;
sign_out : out std_logic;
zero_out : out std_logic;
result_out : out std_logic_vector(31 downto 0)
);
end scalar_processor;
architecture arch of scalar_processor is
signal srca_i : std_logic_vector(31 downto 0);
signal srcb_i : std_logic_vector(31 downto 0);
signal srca_iaddsub_i : std_logic_vector(31 downto 0);
signal srcb_iaddsub_i : std_logic_vector(31 downto 0);
signal src_a_neg_i : std_logic;
signal src_b_neg_i : std_logic;
signal src_c_neg_i : std_logic;
signal sub_en_i : std_logic;
signal carry_i : std_logic;
signal w32_i : std_logic;
signal is_signed_i : std_logic;
signal saturate_i : std_logic;
signal sum_o : std_logic_vector(31 downto 0);
signal carry_o : std_logic;
signal overflow_o : std_logic;
signal product_o : std_logic_vector(31 downto 0);
signal sll_o : std_logic_vector(31 downto 0);
signal srl_o : std_logic_vector(31 downto 0);
signal neg_o : std_logic_vector(31 downto 0);
signal and_o : std_logic_vector(31 downto 0);
signal or_o : std_logic_vector(31 downto 0);
signal xor_o : std_logic_vector(31 downto 0);
signal max_o : std_logic_vector(31 downto 0);
signal min_o : std_logic_vector(31 downto 0);
signal convert_o : std_logic_vector(31 downto 0);
signal compute_pred_o : std_logic_vector(31 downto 0);
signal sign_o : std_logic;
signal zero_o : std_logic;
-- ADDED <NAME>
signal sign_fl : std_logic;
signal zero_fl : std_logic;
begin
srca_i <= src1_in;
srcb_i <= src2_in;
srca_iaddsub_i <= product_o when (alu_opcode_in = IMAD24) else src1_in;
srcb_iaddsub_i <= src3_in when (alu_opcode_in = IMAD24 or alu_opcode_in = IMAD24C) else src2_in;
--MM: removed "or (is_full_normal_in = '1')" from the condition statement
src_a_neg_i <= '1' when (alu_opcode_in = ISUB) else '0';
src_b_neg_i <= src3_neg_in when (alu_opcode_in = IADD) else '0';
src_c_neg_i <= src3_neg_in;
-- MODIFIED <NAME> - REDUNDANCE OF INFORMATION, IF src_a_neg_i IS ALREADY SET, sub_en_i MUST NOT BE SET OTHERWISE THE NEGATION IS MADE TWICE
--sub_en_i <= '1' when (alu_opcode_in = ISUB) else '0';
sub_en_i <= '0';
w32_i <= '1' when ((alu_opcode_in = IMAD24) or (alu_opcode_in = IMAD24C)) else w32_in;
carry_i <= carry_in when ((alu_opcode_in = IADDC) or (alu_opcode_in = IMAD24C)) else '0';
is_signed_i <= is_signed_in when (alu_opcode_in = IMAD24 and instr_marker_in = IMM) -- ADDED CONDITION GIANLUCA ROASCIO - SPECIFIC FOR IMAD32I
else '1' when (((alu_opcode_in = IMAD24) or (alu_opcode_in = IMAD24C)) and
((instr_subop_in = "001") or (instr_subop_in = "100") or (instr_subop_in = "111")))
else '0' when (((alu_opcode_in = IMAD24) or (alu_opcode_in = IMAD24C)) and
((instr_subop_in = "000") or (instr_subop_in = "010") or (instr_subop_in = "011") or (instr_subop_in = "101") or (instr_subop_in = "110")))
else is_signed_in;
saturate_i <= '1' when (((alu_opcode_in = IMAD24) or (alu_opcode_in = IMAD24C))
and (instr_subop_in = "101")) else
'0' when (((alu_opcode_in = IMAD24) or (alu_opcode_in = IMAD24C)) and
((instr_subop_in = "000") or (instr_subop_in = "001") or
(instr_subop_in = "010") or (instr_subop_in = "011") or
(instr_subop_in = "100") or (instr_subop_in = "110") or
(instr_subop_in = "111"))) else
saturate_in;
uIAddSubtract : integer_add_subtract
port map(
a_in => srca_iaddsub_i,
a_neg_in => src_a_neg_i,
b_in => srcb_iaddsub_i,
b_neg_in => src_b_neg_i,
carry_in => carry_i,
saturate_in => saturate_i,
sub_en => sub_en_i,
w32_in => w32_i,
carry_out => carry_o,
overflow_out => overflow_o,
result_out => sum_o
);
uIMult24 : integer_mult_24
port map(
a_in => srca_i,
a_neg_in => src_a_neg_i,
b_in => srcb_i,
b_neg_in => src_b_neg_i,
is_signed_in => is_signed_i,
--w32_in => w32_i, -- MODIFIED <NAME>
w32_in => w32_in,
result_out => product_o
);
uShiftLogical : shift_logical
port map(
a_in => srca_i,
b_in => srcb_i,
is_signed_in => is_signed_i,
w32_in => w32_i,
sll_out => sll_o,
srl_out => srl_o
);
uBoolean : boolean_functions
port map(
a_in => srca_i,
b_in => srcb_i,
and_out => and_o,
neg_out => neg_o,
or_out => or_o,
xor_out => xor_o
);
uMinMax : min_max -- is this new for the processor???
port map(
a_in => srca_i,
b_in => srcb_i,
is_signed_in => is_signed_i,
w32_in => w32_i,
max_out => max_o,
min_out => min_o
);
uConvertIntInt : convert_int_int
port map(
a_in => srca_i,
abs_saturate_in => abs_saturate_in,
cvt_neg_in => cvt_neg_in,
cvt_type_in => cvt_type_in,
w32_in => w32_i,
result_out => convert_o
);
uComputeSetPredI : compute_set_pred_i
port map(
is_signed_in => is_signed_i,
set_cond_in => set_cond_in,
src_1_in => srca_i,
src_2_in => srcb_i,
w32_in => w32_i,
result_out => compute_pred_o,
sign_out => sign_o,
zero_out => zero_o
);
result_out <= sum_o when ((alu_opcode_in = IADD) or (alu_opcode_in = IADDC) or (alu_opcode_in = ISUB) or
(alu_opcode_in = IMAD24) or (alu_opcode_in = IMAD24C)) else
min_o when (alu_opcode_in = work.gpgpu_package.MIN) else
max_o when (alu_opcode_in = MAX) else
sll_o when (alu_opcode_in = SHL) else
srl_o when (alu_opcode_in = SHR) else
and_o when (alu_opcode_in = AND_OP) else
or_o when (alu_opcode_in = OR_OP) else
xor_o when (alu_opcode_in = XOR_OP) else
neg_o when (alu_opcode_in = NEG_OP) else
product_o when (alu_opcode_in = IMUL24) else
convert_o when (alu_opcode_in = CVT) else
compute_pred_o when (alu_opcode_in = SET) else
x"00000000";
-- ADDED <NAME>
zero_fl <= '1' when (result_out = x"00000000") else '0';
sign_fl <= '1' when (is_signed_i = '1' and result_out(31) = '1' and w32_i = '1')
else '1' when (is_signed_i = '1' and result_out(15) = '1' and w32_i = '0')
else '0';
carry_out <= carry_o;
overflow_out <= overflow_o;
-- MODIFIED <NAME>
--sign_out <= sign_o;
sign_out <= sign_o when (alu_opcode_in = SET) else sign_fl;
--zero_out <= zero_o;
zero_out <= zero_o when (alu_opcode_in = SET) else zero_fl;
end arch;
|
<filename>rtl/core/neorv32_trng.vhd
-- #################################################################################################
-- # << NEORV32 - True Random Number Generator (TRNG) >> #
-- # ********************************************************************************************* #
-- # This unit implements a true random number generator which uses an inverter chain as entropy #
-- # source. The inverter chain is constructed as GARO (Galois Ring Oscillator) TRNG. The single #
-- # inverters are connected via simple latches that are used to enbale/disable the TRNG. Also, #
-- # these latches are used as additional delay element. By using unique enable signals for each #
-- # latch, the synthesis tool cannot "optimize" one of the inverters out of the design. Further- #
-- # more, the latches prevent the synthesis tool from detecting combinatorial loops. #
-- # The output of the GARO is de-biased by a simple von Neuman random extractor and is further #
-- # post-processed by a 16-bit LFSR for improved whitening. #
-- # #
-- # Sources: #
-- # - GARO: "Experimental Assessment of FIRO- and GARO-based Noise Sources for Digital TRNG #
-- # Designs on FPGAs" by <NAME>, <NAME> and <NAME>, 2017 #
-- # - Latches for platform independence: "Extended Abstract: The Butterfly PUF Protecting IP #
-- # on every FPGA" by <NAME>, <NAME>, <NAME>, <NAME> and #
-- # Pim Tuyls, Philips Research Europe, 2008 #
-- # - Von Neumann De-Biasing: "Iterating Von Neumann's Post-Processing under Hardware #
-- # Constraints" by <NAME>, <NAME>, <NAME> and <NAME>, 2016 #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, <NAME>. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) <NAME> #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neorv32;
use neorv32.neorv32_package.all;
entity neorv32_trng is
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
addr_i : in std_ulogic_vector(31 downto 0); -- address
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic -- transfer acknowledge
);
end neorv32_trng;
architecture neorv32_trng_rtl of neorv32_trng is
-- advanced configuration --------------------------------------------------------------------------------
constant num_inv_c : natural := 16; -- length of GARO inverter chain (default=16, max=16)
constant lfsr_taps_c : std_ulogic_vector(15 downto 0) := "1101000000001000"; -- Fibonacci LFSR feedback taps
-- -------------------------------------------------------------------------------------------------------
-- control register bits --
constant ctrl_taps_lsb_c : natural := 0; -- -/w: TAP 0 enable
constant ctrl_taps_msb_c : natural := 15; -- -/w: TAP 15 enable
constant ctrl_en_c : natural := 31; -- r/w: TRNG enable
-- data register bits --
constant ctrl_data_lsb_c : natural := 0; -- r/-: Random data bit 0
constant ctrl_data_msb_c : natural := 15; -- r/-: Random data bit 15
constant ctrl_rnd_valid_c : natural := 31; -- r/-: Output byte valid
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(trng_size_c); -- low address boundary bit
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(31 downto 0); -- access address
signal wren : std_ulogic; -- full word write enable
signal rden : std_ulogic; -- read enable
-- random number generator --
signal rnd_inv : std_ulogic_vector(num_inv_c-1 downto 0); -- inverter chain
signal rnd_enable_sreg : std_ulogic_vector(num_inv_c-1 downto 0); -- enable shift register
signal rnd_enable : std_ulogic;
signal tap_config : std_ulogic_vector(15 downto 0);
signal rnd_sync : std_ulogic_vector(02 downto 0); -- metastability filter & de-biasing
signal ready_ff : std_ulogic; -- new random data available
signal rnd_sreg : std_ulogic_vector(15 downto 0); -- sample shift reg
signal rnd_cnt : std_ulogic_vector(04 downto 0);
signal new_sample : std_ulogic; -- new output byte ready
signal rnd_data : std_ulogic_vector(15 downto 0); -- random data register (read-only)
-- Randomness extractor (von Neumann De-Biasing) --
signal db_state : std_ulogic;
signal db_enable : std_ulogic; -- valid data from de-biasing
signal db_data : std_ulogic; -- actual data from de-biasing
begin
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = trng_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= trng_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
wren <= acc_en and wren_i;
rden <= acc_en and rden_i;
-- Read/Write Access ----------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
rw_access: process(clk_i)
begin
if rising_edge(clk_i) then
ack_o <= acc_en and (rden_i or wren_i);
-- write access --
if (wren = '1') then
if (addr = trng_ctrl_addr_c) then
if (ben_i(0) = '1') then
tap_config(07 downto 00) <= data_i(ctrl_taps_lsb_c+7 downto ctrl_taps_lsb_c+0);
end if;
if (ben_i(1) = '1') then
tap_config(15 downto 08) <= data_i(ctrl_taps_lsb_c+15 downto ctrl_taps_lsb_c+8);
end if;
-- if (ben_i(2) = '1') then
-- NULL;
-- end if;
if (ben_i(3) = '1') then
rnd_enable <= data_i(ctrl_en_c);
end if;
end if;
end if;
-- read access --
data_o <= (others => '0');
if (rden = '1') then
if (addr = trng_ctrl_addr_c) then
data_o(ctrl_taps_msb_c downto ctrl_taps_lsb_c) <= tap_config;
data_o(ctrl_en_c) <= rnd_enable;
else -- trng_data_addr_c
data_o(ctrl_data_msb_c downto ctrl_data_lsb_c) <= rnd_data;
data_o(ctrl_rnd_valid_c) <= ready_ff;
end if;
end if;
end if;
end process rw_access;
-- True Random Generator ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
entropy_source: process(rnd_enable_sreg, rnd_enable, rnd_inv, tap_config)
begin
for i in 0 to num_inv_c-1 loop
if (rnd_enable = '0') then -- start with a defined state (latch reset)
rnd_inv(i) <= '0';
-- uniquely enable latches to prevent synthesis from removing chain elements
elsif (rnd_enable_sreg(i) = '1') then -- latch enable
-- here we have the inverter chain --
if (i = num_inv_c-1) then -- left most inverter?
if (tap_config(i) = '1') then
rnd_inv(i) <= not rnd_inv(0); -- direct input of right most inverter (= output signal)
else
rnd_inv(i) <= '0';
end if;
else
if (tap_config(i) = '1') then
rnd_inv(i) <= not (rnd_inv(i+1) xor rnd_inv(0)); -- use final output as feedback
else
rnd_inv(i) <= not rnd_inv(i+1); -- normal chain: use previous inverter's output as input
end if;
end if;
end if;
end loop; -- i
end process entropy_source;
-- unique enable signals for each inverter latch --
inv_enable: process(clk_i)
begin
if rising_edge(clk_i) then
-- using individual enable signals for each inverter - derived from a shift register - to prevent the synthesis tool
-- from removing all but one inverter (since they implement "logical identical functions")
-- this also allows to make the trng platform independent
rnd_enable_sreg <= rnd_enable_sreg(num_inv_c-2 downto 0) & rnd_enable; -- activate right most inverter first
end if;
end process inv_enable;
-- Processing Core ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
processing_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- synchronize output of GARO --
rnd_sync <= rnd_sync(1 downto 0) & rnd_inv(0); -- no more metastability
-- von Neumann De-Biasing state --
db_state <= (not db_state) and rnd_enable; -- just toggle -> process in every second cycle
-- sample random data & post-processing --
if (rnd_enable = '0') then
rnd_cnt <= (others => '0');
rnd_sreg <= (others => '0');
elsif (db_enable = '1') then -- valid de-biased output?
if (rnd_cnt = "10000") then
rnd_cnt <= (others => '0');
else
rnd_cnt <= std_ulogic_vector(unsigned(rnd_cnt) + 1);
end if;
rnd_sreg <= rnd_sreg(rnd_sreg'left-1 downto 0) & (xnor_all_f(rnd_sreg and lfsr_taps_c) xor db_data); -- LFSR post-processing
-- rnd_sreg <= rnd_sreg(rnd_sreg'left-1 downto 0) & db_data; -- LFSR post-processing
end if;
-- data output register --
if (new_sample = '1') then
rnd_data <= rnd_sreg;
end if;
-- data ready flag --
if (rnd_enable = '0') or (rden = '1') then -- clear when deactivated or on data read
ready_ff <= '0';
elsif (new_sample = '1') then
ready_ff <= '1';
end if;
end if;
end process processing_core;
-- <NAME> De-Biasing --
debiasing: process(db_state, rnd_sync)
variable tmp_v : std_ulogic_vector(2 downto 0);
begin
-- check groups of two non-overlapping bits from the input stream
tmp_v := db_state & rnd_sync(2 downto 1);
case tmp_v is
when "101" => db_enable <= '1'; db_data <= '1'; -- rising edge -> '1'
when "110" => db_enable <= '1'; db_data <= '0'; -- falling edge -> '0'
when others => db_enable <= '0'; db_data <= '0'; -- invalid
end case;
end process debiasing;
-- new valid byte available? --
new_sample <= '1' when (rnd_cnt = "10000") and (rnd_enable = '1') and (db_enable = '1') else '0';
end neorv32_trng_rtl;
|
-- reg.vhd
--
-- A generic register component used in CprE 381 fall. It may be used for PC,
-- pineline registers and so on.
--
-- <NAME>, fall 2013
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.mips32.all;
entity reg is
generic (M : integer := 32); -- Size of the register
port (D : in m32_vector(M-1 downto 0); -- Data input
Q : out m32_vector(M-1 downto 0); -- Data output
WE : in m32_1bit; -- Write enableenable
reset : in m32_1bit; -- The clock signal
clock : in m32_1bit); -- The reset signal
end reg;
architecture behavior of reg is
begin
REG : process (clock)
begin
if (rising_edge(clock)) then
if (reset = '1') then
-- Clear all bits of latch
Q <= std_logic_vector(to_unsigned(0, Q'length));
elsif (WE = '1') then
Q <= D;
end if;
end if;
end process;
end behavior;
|
<reponame>daxadal/computer-102
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity decodificadorTeclado is
port(
reset: in std_logic;
PS2DATA: in std_logic;
PS2CLK : in std_logic;
salida : out std_logic_vector (6 downto 0) -- "Up-Down-Left-Right-Lv3-Lv2-Lv1"
);
end decodificadorTeclado;
architecture Behavioral of decodificadorTeclado is
signal registro: std_logic_vector (20 downto 0); -- Registro que guarda los bits que llegan del teclado
signal salida_aux: std_logic_vector(6 downto 0); -- Salida multiplexada
begin
process (PS2CLK, reset)
begin
if reset = '1' then
registro <= (others => '0');
elsif PS2CLK'event and PS2CLK = '0' then
registro <= registro (19 downto 0) & PS2DATA;
end if;
end process;
with registro(9 downto 2) select
salida_aux <= "1000000" when "10111000", --up is W (1D) al reves
"0100000" when "11011000", --down is S (1B)al reves
"0010000" when "00111000", --left is A (1C)al reves
"0001000" when "11000100", --right is D (23) al reves
"0000001" when "01101000", --Lv1 is 1 (16) al reves
"0000010" when "01111000", --Lv2 is 2 (1E) al reves
"0000100" when "01100100", --Lv3 is 3 (26) al reves
"0000000" when others;
with registro(20 downto 13) select -- Lo sacamos por salida cuando hayamos dejado de pulsar la tecla (F0)
salida <= salida_aux when "00001111",
"0000000" when others;
end Behavioral;
|
--------------------------------------Slow Clock with pushbutton for more comfortable counter implementation-------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
ENTITY slowClock IS
PORT(
clk_fast : in std_logic;
clk_slow : out std_logic
);
END ENTITY;
ARCHITECTURE slowClock_arc OF slowClock IS
signal prescaler : std_logic_vector(16 downto 0) := "00000000000000000";
BEGIN
process(clk_fast)
begin
if rising_edge(clk_fast) then -- rising clock edge
prescaler <= prescaler + 1;
end if;
clk_slow <= prescaler(16);
end process;
END ARCHITECTURE;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clock IS
PORT(
clk: IN std_logic;
pushbutton: IN std_logic;
finClk: OUT std_logic
);
END ENTITY;
ARCHITECTURE clock_arc OF clock IS
signal slowClock: std_logic;
BEGIN
y: ENTITY WORK.slowClock(slowClock_arc) port map(
clk_fast => clk,
clk_slow => slowClock
);
PROCESS(clk, pushbutton)
BEGIN
if(pushbutton = '1') then finclk <= clk;
elsif(pushbutton = '0') then finclk <= slowClock;
end if;
END PROCESS;
END ARCHITECTURE;
---------------------------------------Seven Segment Display for counters--------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.all;
ENTITY anode_gen IS
PORT(
clk : in std_logic;
--rst : in std_logic;
anode : out std_logic_vector(3 downto 0)
);
END ENTITY;
ARCHITECTURE anode_gen_arc OF anode_gen IS
signal danode : std_logic_vector(3 downto 0);
BEGIN
PROCESS(clk)
variable j : integer range 0 to 7 := 0;
BEGIN
if rising_edge(clk) then
if j=0 then
danode <= "1110";
j := 1;
elsif j=1 then
danode <= "1101";
j := 2;
elsif j=2 then
danode <= "1011";
j := 3;
elsif j=3 then
danode <= "0111";
j := 0;
end if;
end if;
END PROCESS;
anode <= danode;
END Architecture;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.all;
ENTITY ssd IS
PORT(
clk: In STD_logic;
off_count: IN std_logic_vector(3 downto 0);
idle_count: IN std_logic_vector(3 downto 0);
anode: OUT std_logic_vector(3 downto 0);
cathode: OUT std_logic_vector(6 downto 0)
);
END ENTITY;
ARCHITECTURE ssd_logic OF ssd IS
signal dumAnode: std_logic_vector(3 downto 0);
SIGNAL off_no: std_logic_vector(3 downto 0);
SIGNAL idle_status: std_logic_vector(3 downto 0);
signal dummy: std_logic;
BEGIN
a2: ENTITY WORK.anode_gen(anode_gen_arc) port map(
clk => clk,
anode => dumAnode
);
anode <= dumAnode;
PROCESS(off_count, idle_count, dumAnode)
BEGIN
if dumAnode="1110" then
if idle_count = "0000" then cathode <= "1000000";
elsif idle_count = "0001" then cathode <= "1111001";
elsif idle_count = "0010" then cathode <= "0100100";
elsif idle_count = "0011" then cathode <= "0110000";
elsif idle_count = "0100" then cathode <= "0011001";
elsif idle_count = "0101" then cathode <= "0010010";
elsif idle_count = "0110" then cathode <= "0000010";
elsif idle_count = "0111" then cathode <= "1111000";
elsif idle_count = "1000" then cathode <= "0000000";
elsif idle_count = "1001" then cathode <= "0010000";
elsif idle_count = "1010" then cathode <= "1000000";
else dummy <= '0';
end if;
elsif dumAnode="1101" then
if idle_count="1010" then cathode <= "1111001";
else cathode <= "1000000";
end if;
elsif dumAnode="1011" then
if off_count = "0000" then cathode <= "1000000";
elsif off_count = "0001" then cathode <= "1111001";
elsif off_count = "0010" then cathode <= "0100100";
elsif off_count = "0011" then cathode <= "0110000";
end if;
elsif dumAnode="0111" then
cathode <= "1000000";
end if;
END PROCESS;
END ARCHITECTURE;
---------------------------------------Light Controller Logic (1 sec = 763 counts)-----------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY controller IS
PORT(
clk: IN std_logic;
SW_ON : IN std_logic;
SW_OFF : IN std_logic;
SW_DOOR : IN std_logic;
-- reset: IN std_logic; it's useless
D: IN std_logic_vector(3 DOWNTO 0);
door_key: IN std_logic;
ignition: IN std_logic;
counter_delay_bit: OUT std_logic_vector(3 DOWNTO 0);
door_delay_bit: OUT std_logic_vector(3 DOWNTO 0);
invalid: OUT std_logic;
light: OUT std_logic);
END controller;
--each state is either a box or a diamond
ARCHITECTURE logic_controller OF controller IS
signal counter_delay, door_delay: integer;
signal cur_state: integer;
signal prev_D: std_logic_vector(3 DOWNTO 0);
signal templight, tempinvalid: std_logic;
BEGIN
PROCESS(clk)
BEGIN
IF rising_edge(clk) THEN
IF SW_ON = '0' AND SW_OFF = '0' AND SW_DOOR = '0' THEN -- means reset
counter_delay <= 0;
door_delay <= 0;
cur_state <= 0;
tempinvalid <= '1';
templight <= '0';
ELSIF SW_ON = '1' THEN
IF SW_OFF = '1' OR SW_DOOR = '1' THEN
tempinvalid <= '1';
templight <= '0';
ELSE
tempinvalid <= '0';
templight <= '1';
END IF;
ELSIF SW_OFF = '1' THEN
IF SW_ON = '1' OR SW_DOOR = '1' THEN
tempinvalid <= '1';
templight <= '0';
ELSE
tempinvalid <= '0';
templight <= '0';
END IF; --------------------------------------------ALL EASY TILL HERE----------------------------------------------------
ELSIF SW_DOOR = '1' THEN
IF SW_OFF = '1' OR SW_ON = '1' THEN
tempinvalid <= '1';
templight <= '0';
ELSE
tempinvalid <= '0';
IF cur_state = 0 THEN
IF door_key = '1' THEN
cur_state <= 1;
ELSE
cur_state <= 0; -- let it be what it is right now.
END IF;
ELSIF cur_state = 1 THEN
IF D /= "0000" THEN
cur_state <= 2;
ELSE
cur_state <= 1;
END IF;
ELSIF cur_state = 2 THEN
templight <= '1';
door_delay <= 0;
counter_delay <= 0;
cur_state <= 3;
ELSIF cur_state = 3 THEN
IF D /= "0000" THEN
IF prev_D /= D THEN --a new door is opened
cur_state <= 2;
ELSE
cur_state <= 4;
END IF;
ELSE
door_delay <= 0;
counter_delay <= 0;
cur_state <= 6;
END IF;
ELSIF cur_state = 4 THEN
IF D = "0000" THEN
cur_state <= 2;
ELSE
IF prev_D /= D THEN --a new door is opened
cur_state <= 2;
ELSE
cur_state <= 5;
END IF;
END IF;
ELSIF cur_state = 5 THEN
IF prev_D /= D THEN --a new door is opened
cur_state <= 2;
ELSE
IF counter_delay <= 7630 THEN --10 s
counter_delay <= counter_delay + 3;
cur_state <= 3;
ELSE
IF door_delay <= 2289 THEN --3 s
door_delay <= door_delay + 3;
cur_state <= 3;
ELSE
templight <= '0';
cur_state <= 4;
END IF;
END IF;
END IF;
ELSIF cur_state = 6 THEN
IF templight = '1' THEN
IF D /= "0000" THEN
cur_state <= 2;
ELSE
IF door_delay <= 2289 THEN --3 s
door_delay <= door_delay + 1;
ELSE
templight <= '0';
cur_state <= 7;
END IF;
END IF;
ELSE
cur_state <= 7;
END IF;
ELSIF cur_state = 7 THEN -------------------------------------CORRECT TILL HERE-------------------------------------------------
IF D /= "0000" THEN
cur_state <= 2;
ELSE
IF ignition = '1' THEN
counter_delay <= 0;
door_delay <= 0;
cur_state <= 8;
ELSE
IF door_key = '1' THEN
cur_state <= 0;
ELSE
cur_state <= 7;
END IF;
END IF;
END IF;
ELSIF cur_state = 8 THEN
IF D /= "0000" THEN
cur_state <= 2;
ELSE
counter_delay <= 0;
door_delay <= 0;
cur_state <= 9;
END IF;
ELSIF cur_state = 9 THEN
IF D /= "0000" THEN
cur_state <= 2;
ELSE
IF ignition = '1' THEN
IF templight = '1' THEN
IF counter_delay <= 7630 THEN
counter_delay <= counter_delay + 1;
cur_state <= 9;
ELSE
IF door_delay <= 2289 THEN
door_delay <= door_delay + 1;
ELSE
templight <= '0';
cur_state <= 9;
END IF;
END IF;
ELSE
cur_state <= 9;
END IF;
ELSE
cur_state <= 10;
END IF;
END IF;
ELSIF cur_state = 10 THEN
templight <= '1';
door_delay <= 0;
counter_delay <= 0;
cur_state <= 11;
ELSIF cur_state = 11 THEN
IF ignition = '1' THEN
cur_state <= 8;
ELSE
IF D = "0000" THEN
IF counter_delay <= 7630 THEN
counter_delay <= counter_delay + 1;
cur_state <= 11;
ELSE
IF door_delay <= 2289 THEN
door_delay <= door_delay + 1;
ELSE
templight <= '0';
cur_state <= 11;
END IF;
END IF;
ELSE
cur_state <= 12;
END IF;
END IF;
ELSIF cur_state = 12 THEN
IF templight = '0' THEN
templight <= '1';
cur_state <= 12;
ELSE
door_delay <= 0;
counter_delay <= 0;
cur_state <= 13;
END IF;
ELSIF cur_state = 13 THEN
IF D /= "0000" THEN
IF prev_D /= D THEN --a new door is opened
cur_state <= 12;
ELSE
cur_state <= 14;
END IF;
ELSE
door_delay <= 0;
counter_delay <= 0;
cur_state <= 16; --come back here
END IF;
ELSIF cur_state = 14 THEN
IF D = "0000" THEN
cur_state <= 12;
ELSE
IF prev_D /= D THEN --a new door is opened
cur_state <= 12;
ELSE
cur_state <= 15;
END IF;
END IF;
ELSIF cur_state = 15 THEN
IF prev_D /= D THEN --a new door is opened
cur_state <= 12;
ELSE
IF counter_delay <= 7630 THEN --10 s
counter_delay <= counter_delay + 3;
cur_state <= 13;
ELSE
IF door_delay <= 2289 THEN --3 s
door_delay <= door_delay + 3;
ELSE
templight <= '0';
cur_state <= 14;
END IF;
END IF;
END IF;
ELSIF cur_state = 16 THEN
IF templight = '1' THEN
IF D /= "0000" THEN
cur_state <= 12;
ELSE
IF door_delay <= 2289 THEN --3 s
door_delay <= door_delay + 1;
ELSE
templight <= '0';
cur_state <= 17;
END IF;
END IF;
ELSE
cur_state <= 17;
END IF;
ELSIF cur_state = 17 THEN
IF D /= "0000" THEN
cur_state <= 12;
ELSE
IF ignition = '1' THEN
counter_delay <= 0;
door_delay <= 0;
cur_state <= 8;
ELSE
IF door_key = '1' THEN
cur_state <= 18;
ELSE
cur_state <= 17;
END IF;
END IF;
END IF;
ELSIF cur_state = 18 THEN
IF door_key = '0' THEN
cur_state <= 0;
ELSE
cur_state <= 18;
END IF;
END IF;
END IF;
END IF;
prev_D <= D;
counter_delay_bit <= std_logic_vector(to_unsigned((counter_delay)/763, 4));
door_delay_bit <= std_logic_vector(to_unsigned((door_delay)/763, 4));
light <= templight;
invalid <= tempinvalid;
END IF;
END PROCESS;
END ARCHITECTURE logic_controller;
---------------------------------------------------Main Component-----------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.numeric_std.ALL;
ENTITY mini_project IS
PORT (pushbutton: IN std_logic;
SW_DOOR: IN std_logic;
clk: IN std_logic;
SW_ON : IN std_logic;
SW_OFF : IN std_logic;
-- reset: IN std_logic; it's useless
D: IN std_logic_vector(3 DOWNTO 0);
door_key: IN std_logic;
ignition: IN std_logic;
anode: OUT std_logic_vector(3 DOWNTO 0);
cathode: OUT std_logic_vector(6 DOWNTO 0);
invalid: OUT std_logic;
light: OUT std_logic);
END mini_project;
ARCHITECTURE logic_mini OF mini_project IS
signal slow_clk: std_logic;
signal counter_delay_bit: std_logic_vector(3 DOWNTO 0);
signal door_delay_bit: std_logic_vector(3 DOWNTO 0);
BEGIN
C: ENTITY WORK.clock(clock_arc)
PORT MAP(clk => clk,
finClk => slow_clk,
pushbutton => pushbutton);
M: ENTITY WORK.controller(logic_controller)
PORT MAP(SW_DOOR => SW_DOOR,
clk => slow_clk,
SW_ON => SW_ON,
SW_OFF => SW_OFF,
D => D,
door_key => door_key,
ignition => ignition,
counter_delay_bit => counter_delay_bit,
door_delay_bit => door_delay_bit,
invalid => invalid,
light => light);
SSD: ENTITY WORK.ssd(ssd_logic)
PORT MAP(clk => slow_clk,
idle_count => counter_delay_bit,
off_count => door_delay_bit,
anode => anode,
cathode => cathode);
END ARCHITECTURE;
|
<reponame>nwrkbiz/jcore-cpu<filename>core/cpu.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.cpu2j0_pack.all;
use work.decode_pack.all;
use work.cpu2j0_components_pack.all;
use work.datapath_pack.all;
use work.mult_pkg.all;
entity cpu is
generic (
COPRO_DECODE : boolean := true);
port (
clk : in std_logic;
rst : in std_logic;
db_o : out cpu_data_o_t;
db_lock : out std_logic;
db_i : in cpu_data_i_t;
inst_o : out cpu_instruction_o_t;
inst_i : in cpu_instruction_i_t;
debug_o : out cpu_debug_o_t;
debug_i : in cpu_debug_i_t;
event_o : out cpu_event_o_t;
event_i : in cpu_event_i_t;
cop_o : out cop_o_t;
cop_i : in cop_i_t);
end entity cpu;
architecture stru of cpu is
signal slot, if_stall : std_logic;
signal mac_i : mult_i_t;
signal mac_o : mult_o_t;
signal reg : reg_ctrl_t;
signal func : func_ctrl_t;
signal mem : mem_ctrl_t;
signal instr : instr_ctrl_t;
signal mac : mac_ctrl_t;
signal pc : pc_ctrl_t;
signal buses : buses_ctrl_t;
signal t_bcc : std_logic;
signal ibit : std_logic_vector(3 downto 0);
signal if_dr : std_logic_vector(15 downto 0);
signal enter_debug, debug, mask_int : std_logic;
signal event_ack : std_logic;
signal slp_o : std_logic;
signal sr : sr_ctrl_t;
signal illegal_delay_slot : std_logic;
signal illegal_instr : std_logic;
signal coproc : coproc_ctrl_t;
signal coproc_decode : coproc_ctrl_t;
signal copreg : std_logic_vector(7 downto 0);
begin
event_o.ack <= event_ack;
event_o.lvl <= ibit;
event_o.slp <= slp_o;
event_o.dbg <= debug;
u_decode: decode
port map (clk => clk, rst => rst, slot => slot,
enter_debug => enter_debug, debug => debug,
if_dr => if_dr, if_stall => if_stall,
illegal_delay_slot => illegal_delay_slot,
illegal_instr => illegal_instr,
mac_busy => mac_o.busy,
reg => reg, func => func, sr => sr, mac => mac, mem => mem, instr => instr, pc => pc,
buses => buses,
coproc => coproc_decode, copreg => copreg,
t_bcc => t_bcc,
event_i => event_i, event_ack => event_ack,
ibit => ibit,
slp => slp_o,
mask_int => mask_int);
u_mult : mult port map (clk => clk, rst => rst, slot => slot, a => mac_i, y => mac_o);
mac_i.wr_m1 <= mac.com1; mac_i.command <= mac.com2;
mac_i.wr_mach <= mac.wrmach; mac_i.wr_macl <= mac.wrmacl;
u_datapath : datapath port map (clk => clk, rst => rst, slot => slot,
debug => debug, enter_debug => enter_debug,
db_lock => db_lock, db_o => db_o, db_i => db_i, inst_o => inst_o, inst_i => inst_i,
debug_o => debug_o, debug_i => debug_i,
reg => reg, func => func, sr_ctrl => sr, mac => mac, mem => mem, pc_ctrl => pc,
buses => buses, coproc => coproc, instr => instr,
macin1 => mac_i.in1, macin2 => mac_i.in2, mach => mac_o.mach, macl => mac_o.macl,
mac_s => mac_i.s,
t_bcc => t_bcc, ibit => ibit, if_dr => if_dr, if_stall => if_stall,
mask_int => mask_int,
illegal_delay_slot => illegal_delay_slot,
illegal_instr => illegal_instr,
copreg => copreg,
cop_i => cop_i, cop_o => cop_o);
coproc.cpu_data_mux <= coproc_decode.cpu_data_mux when COPRO_DECODE
else DBUS;
coproc.coproc_cmd <= coproc_decode.coproc_cmd when COPRO_DECODE
else NOP;
end architecture stru;
|
<gh_stars>1-10
library IEEE;
use IEEE.std_logic_1164.all;
package temp_sensor_pkg is
component i2c_master
GENERIC(
input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC); --serial clock output of i2c bus
END component i2c_master;
component seven_segments
port (
clk : in std_logic; -- clock signal
rst_n : in std_logic; -- synchronous reset active low
value : in std_logic_vector(31 downto 0); -- hex data to display (4 bits per display)
point : in std_logic_vector(7 downto 0); -- point control
an : out std_logic_vector(7 downto 0); -- display anode selection
segment : out std_logic_vector(7 downto 0) -- segments control
);
end component seven_segments;
component temp2bcd
port (
value_in : in std_logic_vector(12 downto 0);
negative : out std_logic;
bcd : out std_logic_vector(19 downto 0)
);
end component;
function all_bits_in_one(slv : in std_logic_vector) return std_logic;
end temp_sensor_pkg;
package body temp_sensor_pkg is
function all_bits_in_one(slv : in std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in slv'range loop
result := result and slv(i);
end loop;
return result;
end function;
end temp_sensor_pkg;
|
-------------------------------------------------------------------
-- A 2-to-1 multiplexor with a configurable (generic) bus width
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- mux entity
entity mux2to1 is
-- generic parameter for bus width
generic (g_BUS_WIDTH: positive);
-- two input buses, a select bit and an output bus
port (
i_data0, i_data1: in std_logic_vector(g_BUS_WIDTH-1 downto 0);
i_sel: in std_logic;
o_data: out std_logic_vector(g_BUS_WIDTH-1 downto 0)
);
end mux2to1;
-- mux architecture
architecture behav1 of mux2to1 is
begin
-- 0 selects first data input, 1 selects second
o_data <= i_data0 when i_sel = '0' else i_data1;
end architecture behav1;
-- explicit logical architecture
architecture behav2 of mux2to1 is
-- signal for expanding select bit to bus width
signal sel_expanded: std_logic_vector(g_BUS_WIDTH-1 downto 0);
begin
sel_expanded <= (others => i_sel);
o_data <= (i_data0 and not sel_expanded) or
(i_data1 and sel_expanded);
end behav2;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.utils.all;
use virtual_button_lib.midi_pkg.all;
entity track_decoder is
generic(
max_read_bytes : integer
);
port(
ctrl : in ctrl_t;
midi_pulses : in midi_pulse_arr;
midi_pulse_acks : out midi_pulse_arr;
playing_en : in std_logic;
chunk_data : in chunk_data_t_arr;
num_chunks : in integer range 0 to max_num_tracks - 1;
-- ram read interface
read_start_addr : out unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0) := (others => '0');
read_num_bytes : out integer range 0 to max_read_bytes;
read_en : out std_logic;
read_busy : in std_logic;
midi_ram_out : in std_logic_vector((max_read_bytes * 8) - 1 downto 0);
midi_nos : out midi_note_arr_t
);
end;
architecture rtl of track_decoder is
constant read_addr_length : integer := integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1;
type internals_t is record
first_event : std_logic;
read_start_addr : unsigned(integer(ceil(log2(real(midi_file_rx_bram_depth)))) - 1 downto 0);
status : std_logic_vector(7 downto 0);
last_byte_was_status : std_logic;
unknown_midi_event : std_logic;
midi_no : midi_note_t;
volume : unsigned(7 downto 0);
delta_counter : unsigned(27 downto 0);
end record;
type internals_t_arr is array(1 to max_num_tracks - 1) of internals_t;
signal internals : internals_t_arr;
signal current_internal : internals_t;
type state_t is (
wait_en,
init_read_addrs_1,
init_read_addrs_2,
read_variable_length_1,
read_variable_length_2,
read_variable_length_3,
apply_delta_time,
wait_delta_time_and_cede_control,
wait_delta_time_and_cede_control_delay,
increment_current_internal_1,
increment_current_internal_2,
read_status_1,
read_status_2,
read_status_3,
dispatch_event,
dispatch_meta_1,
dispatch_meta_2,
skip_over_meta_event_1,
skip_over_meta_event_2,
read_note_on_1,
read_note_on_2,
read_note_on_3,
read_note_on_4,
done,
error_state
);
signal state : state_t;
signal return_state : state_t;
signal read_num_bytes_int : integer range 0 to max_read_bytes;
signal variable_length : unsigned(27 downto 0);
signal current_track : integer range 1 to max_num_tracks - 1;
signal read_busy_d1 : std_logic;
-----------------------------------------------------------------------------
-- Enumeration of known events
constant meta_event : std_logic_vector(7 downto 0) := x"FF";
constant note_on_event : std_logic_vector(3 downto 0) := x"9";
constant end_of_track : std_logic_vector(7 downto 0) := x"2F";
constant track_name : std_logic_vector(7 downto 0) := x"03";
constant prefix_port : std_logic_vector(7 downto 0) := x"21";
begin
delay_read_busy : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
read_busy_d1 <= read_busy;
end if;
end process;
fsm : process(ctrl.clk)
procedure increment_current_track is
begin
if current_track = num_chunks then
current_track <= 1;
else
current_track <= current_track + 1;
end if;
end;
impure function ram_read_finished return boolean is
begin
return read_busy = '0' and read_busy_d1 = '1';
end;
begin
if rising_edge(ctrl.clk) then
if ctrl.reset_n = '0' then
internals <= (
others => (
first_event => '1',
read_start_addr => (others => '0'),
status => (others => '0'),
last_byte_was_status => '0',
unknown_midi_event => '0',
midi_no => midi_note_t'low,
volume => (others => '0'),
delta_counter => (others => '0')
));
current_internal <= (
first_event => '1',
read_start_addr => (others => '0'),
status => (others => '0'),
last_byte_was_status => '0',
unknown_midi_event => '0',
midi_no => midi_note_t'low,
volume => (others => '0'),
delta_counter => (others => '0')
);
state <= wait_en;
return_state <= error_state;
variable_length <= (others => '0');
read_en <= '0';
current_track <= 1;
for i in 1 to max_num_tracks - 1 loop
midi_pulse_acks(i) <= '0';
end loop;
else
case state is
when wait_en =>
if playing_en = '1' then
state <= init_read_addrs_1;
end if;
when init_read_addrs_1 =>
for i in internals'range loop
internals(i).read_start_addr <= chunk_data(i).base_addr + 8;
end loop;
state <= init_read_addrs_2;
when init_read_addrs_2 =>
current_internal <= internals(current_track);
return_state <= apply_delta_time;
state <= read_variable_length_1;
when read_variable_length_1 =>
variable_length <= (others => '0');
state <= read_variable_length_2;
when read_variable_length_2 =>
read_en <= '1';
read_num_bytes_int <= 1;
state <= read_variable_length_3;
when read_variable_length_3 =>
read_en <= '0';
if ram_read_finished then
variable_length <= variable_length(variable_length'left - 7 downto 0) & unsigned(midi_ram_out(6 downto 0));
current_internal.read_start_addr <= current_internal.read_start_addr + read_num_bytes_int;
if midi_ram_out(7) = '1' then
state <= read_variable_length_2;
else
state <= return_state;
end if;
end if;
when apply_delta_time =>
current_internal.delta_counter <= variable_length;
state <= wait_delta_time_and_cede_control;
when wait_delta_time_and_cede_control =>
midi_pulse_acks(current_track) <= '0';
if current_internal.delta_counter = 0 then
state <= read_status_1;
elsif midi_pulses(current_track) = '1' then
current_internal.delta_counter <= current_internal.delta_counter - 1;
midi_pulse_acks(current_track) <= '1';
state <= wait_delta_time_and_cede_control_delay;
else
-- Now we are switching midi track, so we must put the current
-- track back in storage and get another one out.
internals(current_track) <= current_internal;
internals(current_track).first_event <= '0';
state <= increment_current_internal_1;
increment_current_track;
end if;
-- This state prevents the delta counters from accidentally double
-- decrementing.
when wait_delta_time_and_cede_control_delay =>
state <= wait_delta_time_and_cede_control;
when increment_current_internal_1 =>
current_internal <= internals(current_track);
state <= increment_current_internal_2;
when increment_current_internal_2 =>
if current_internal.first_event = '1' then
state <= read_variable_length_1;
return_state <= apply_delta_time;
else
state <= wait_delta_time_and_cede_control;
end if;
when read_status_1 =>
read_en <= '1';
read_num_bytes_int <= 1;
state <= read_status_2;
when read_status_2 =>
read_en <= '0';
if ram_read_finished then
current_internal.read_start_addr <= current_internal.read_start_addr + read_num_bytes_int;
--here we implement the running status
if midi_ram_out(7) = '1' then
current_internal.status <= midi_ram_out(7 downto 0);
current_internal.last_byte_was_status <= '1';
else
current_internal.last_byte_was_status <= '0';
end if;
state <= dispatch_event;
end if;
-- If last_byte_was_status = '1', then the last byte we read from
-- ram was a data byte, If last_byte_was_status = '0', then that
-- data byte was read and the pointer is looking at the next data
-- byte.
--
-- To remove confusion, in this state, we subtract 1 from the ram
-- read pointer to unify that situation and make sure that the read
-- pointer is at the first data byte.
when dispatch_event =>
if current_internal.last_byte_was_status = '0' then
current_internal.read_start_addr <= current_internal.read_start_addr - 1;
end if;
if current_internal.status = meta_event then
state <= dispatch_meta_1;
elsif current_internal.status(7 downto 4) = note_on_event then
state <= read_note_on_1;
else
current_internal.unknown_midi_event <= '1';
state <= error_state;
end if;
when dispatch_meta_1 =>
read_en <= '1';
read_num_bytes_int <= 1;
state <= dispatch_meta_2;
when dispatch_meta_2 =>
read_en <= '0';
if ram_read_finished then
current_internal.read_start_addr <= current_internal.read_start_addr + read_num_bytes_int;
if midi_ram_out(7 downto 0) = end_of_track then
state <= done;
elsif midi_ram_out(7 downto 0) = track_name or
midi_ram_out(7 downto 0) = prefix_port then
state <= skip_over_meta_event_1;
else
state <= error_state;
end if;
end if;
when skip_over_meta_event_1 =>
state <= read_variable_length_1;
return_state <= skip_over_meta_event_2;
when skip_over_meta_event_2 =>
current_internal.read_start_addr <= current_internal.read_start_addr +
resize(variable_length, read_addr_length);
state <= read_variable_length_1;
return_state <= apply_delta_time;
when read_note_on_1 =>
read_en <= '1';
read_num_bytes_int <= 2;
state <= read_note_on_2;
when read_note_on_2 =>
read_en <= '0';
if ram_read_finished then
current_internal.read_start_addr <= current_internal.read_start_addr + read_num_bytes_int;
current_internal.midi_no <= to_integer(unsigned(midi_ram_out(15 downto 8)));
midi_nos(current_track - 1) <= to_integer(unsigned(midi_ram_out(15 downto 8)));
current_internal.volume <= unsigned(midi_ram_out(7 downto 0));
state <= read_variable_length_1;
return_state <= apply_delta_time;
end if;
when done =>
increment_current_track;
null;
when error_state =>
null;
when others =>
null;
end case;
end if;
end if;
end process;
-- mux the read address output
read_start_addr <= current_internal.read_start_addr;
read_num_bytes <= read_num_bytes_int;
end architecture;
|
<reponame>KPU-RISC/KPU<filename>VHDL/Xor8Bits.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/20/2015 05:26:44 PM
-- Design Name:
-- Module Name: Xor8Bits - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Xor8Bit is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end Xor8Bit;
architecture Behavioral of Xor8Bit is
begin
Output(0) <= InputA(0) xor InputB(0);
Output(1) <= InputA(1) xor InputB(1);
Output(2) <= InputA(2) xor InputB(2);
Output(3) <= InputA(3) xor InputB(3);
Output(4) <= InputA(4) xor InputB(4);
Output(5) <= InputA(5) xor InputB(5);
Output(6) <= InputA(6) xor InputB(6);
Output(7) <= InputA(7) xor InputB(7);
end Behavioral;
|
<reponame>zweed4u/Hardware-Description-Language
-------------------------------------------------------------------------------
-- Dr. Kaputa
-- alias test bench
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity aliases_tb is
end aliases_tb;
architecture beh of aliases_tb is
signal word : std_logic_vector(15 downto 0);
alias opcode : std_logic_vector(3 downto 0) is word(15 downto 12);
alias arg1 : std_logic_vector(3 downto 0) is word(11 downto 8);
alias arg2 : std_logic_vector(3 downto 0) is word(7 downto 4);
alias arg3 : std_logic_vector(3 downto 0) is word(3 downto 0);
begin
process
begin
word <= x"1234";
wait;
end process;
end beh;
|
<filename>homework1/eight_bit_nor_conditional.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity eight_bit_nor_conditional is
port(input : in std_logic_vector(7 downto 0); output : out std_logic);
end entity eight_bit_nor_conditional;
architecture behavioral of eight_bit_nor_conditional is
begin
output <= '1' when input = "11111111" else '0';
end architecture behavioral;
|
-------------------------------------------------------------------
-- Note: This is machine generated code. Do not hand edit.
-- Modify Matlab function fxpt_log_vhdl_code_gen.m instead.
-- This file was auto generated on 08-Jul-2017 16:05:00
-- This VDHL file computes the fixed-point log() function
-- (natural log) using multiplicative normalization.
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fxpt_log_compute_W26F24 is
port (
clock : in std_logic;
reset : in std_logic;
x : in std_logic_vector(25 downto 0);
start : in std_logic;
y : out std_logic_vector(25 downto 0); -- y=ln(x)
done : out std_logic
);
end entity;
architecture rtl of fxpt_log_compute_W26F24 is
component fxpt_log_ROM_b_coef_W26F24
port (
clock : in std_logic;
address : in std_logic_vector( 4 downto 0);
b_coef : out std_logic_vector(25 downto 0)
);
end component;
component fxpt_log_ROM_lnb_coef_W26F24
port (
clock : in std_logic;
address : in std_logic_vector( 4 downto 0);
lnb_coef : out std_logic_vector(25 downto 0)
);
end component;
type state_type is (state_wait, state_start, state_pcompute, state_xyupdate, state_done);
signal state : state_type;
signal xi : signed(25 downto 0);
signal yi : signed(25 downto 0);
signal p : signed(51 downto 0);
signal b_coef : std_logic_vector(25 downto 0);
signal lnb_coef : std_logic_vector(25 downto 0);
signal lnb_coef_z1 : signed(25 downto 0);
signal step_counter : unsigned(6 downto 0);
signal flag_done : std_logic;
signal flag_zero_counter : std_logic;
signal flag_counter_enable : std_logic;
constant y0 : signed(25 downto 0) := (others => '0');
constant c1 : signed(51 downto 0) := "0001000000000000000000000000000000000000000000000000";
constant c26 : unsigned(6 downto 0) := "0011010";
begin
ROM1 : fxpt_log_ROM_b_coef_W26F24
port map (
clock => clock,
address => std_logic_vector(step_counter(4 downto 0)),
b_coef => b_coef
);
ROM2 : fxpt_log_ROM_lnb_coef_W26F24
port map (
clock => clock,
address => std_logic_vector(step_counter(4 downto 0)),
lnb_coef => lnb_coef
);
-- Logic to advance to the next state
process (clock, reset)
begin
if reset = '1' then
state <= state_wait;
elsif (rising_edge(clock)) then
case state is
when state_wait =>
if start = '1' then
state <= state_start;
else
state <= state_wait;
end if;
when state_start =>
state <= state_pcompute;
when state_pcompute =>
state <= state_xyupdate;
when state_xyupdate =>
if flag_done = '1' then
state <= state_done;
else
state <= state_pcompute;
end if;
when state_done =>
state <= state_wait;
when others =>
state <= state_wait;
end case;
end if;
end process;
-- Perform Computations that are state dependent
compute : process (clock)
begin
if (rising_edge(clock)) then
done <= '0';
flag_zero_counter <= '0';
flag_counter_enable <= '0';
y <= (others => '0');
case state is
when state_wait =>
flag_zero_counter <= '1';
when state_start =>
xi <= signed(x); -- xi starts with x=x
yi <= y0; -- yi starts with y=0
when state_pcompute =>
p <= xi * signed(b_coef); -- first comparison P = X0 * (1+2^(-i)) (i=0)
lnb_coef_z1 <= signed(lnb_coef); -- first comparison P = X0 * (1+2^(-i)) (i=0)
flag_counter_enable <= '1';
when state_xyupdate =>
if p <= c1 then -- if p is less than 1, except changes
xi <= p( 49 downto 24);
yi <= yi - lnb_coef_z1;
else -- otherwise result is greater than 1 so don't change and try again with new b coefficent
xi <= xi;
yi <= yi;
end if;
when state_done =>
y <= std_logic_vector(yi);
done <= '1'; -- signal that the computation is finished.
flag_zero_counter <= '1';
when others =>
end case;
end if;
end process;
-- Convergence step counter
step_count1 : process (clock) is
begin
if(rising_edge(clock)) then
if flag_zero_counter = '1' then
step_counter <= (others => '0');
elsif flag_counter_enable = '1' then
step_counter <= step_counter + 1;
end if;
end if;
end process;
-- Check when to stop convergence
step_threshold : process (clock) is
begin
if(rising_edge(clock)) then
flag_done <= '0';
if step_counter >= c26 then
flag_done <= '1';
end if;
end if;
end process;
end rtl;
|
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_serdes
---- Version: 1.0.0
---- Description:
---- Constant rate data serialiser/deserialiser
---- Input: 1 clk / [SER2PAR: dat_ser_val_i <= '1' / dat_ser_i <= 'NEXTSERIALDATA' ] / [PAR2SER: dat_par_val_i <= '1' / dat_par_i <= "PARALLELDATA"]
---- Timing requirements: SER2PAR: 1 clock cycle - PAR2SER: CCSDS_RXTX_SERDES_DEPTH clock cycles
---- Output: [SER2PAR: dat_par_val_o <= "1" / dat_par_o <= "PARALLELIZEDDATA"] / [PAR2SER: dat_ser_val_o <= "1" / dat_ser_o <= "SERIALIZEDDATA"]
---- Ressources requirements: CCSDS_RXTX_SERDES_DEPTH + 2*|log(CCSDS_RXTX_SERDES_DEPTH-1)/log(2)| + 2 registers
-------------------------------
---- Author(s):
---- <NAME>
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/18: initial release
---- 2016/10/27: review + add ser2par
-------------------------------
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ccsds_rxtx_parameters.all;
--=============================================================================
-- Entity declaration for ccsds_rxtx_serdes / data serialiser/deserialiser
--=============================================================================
entity ccsds_rxtx_serdes is
generic (
constant CCSDS_RXTX_SERDES_DEPTH : integer
);
port(
-- inputs
clk_i: in std_logic; -- parallel input data clock
dat_par_i: in std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0); -- parallel input data
dat_par_val_i: in std_logic; -- parallel data valid indicator
dat_ser_i: in std_logic; -- serial input data
dat_ser_val_i: in std_logic; -- serial data valid indicator
rst_i: in std_logic; -- system reset input
-- outputs
bus_o: out std_logic; -- par2ser busy indicator
dat_par_o: out std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0); -- parallel output data
dat_par_val_o: out std_logic; -- parallel output data valid indicator
dat_ser_o: out std_logic; -- serial output data
dat_ser_val_o: out std_logic -- serial output data valid indicator
);
end ccsds_rxtx_serdes;
--=============================================================================
-- architecture declaration / internal processing
--=============================================================================
architecture rtl of ccsds_rxtx_serdes is
-- internal variable signals
signal wire_busy: std_logic := '0';
signal wire_data_par_valid: std_logic := '0';
signal wire_data_ser_valid: std_logic := '0';
signal serial_data_pointer: integer range 0 to CCSDS_RXTX_SERDES_DEPTH-1 := CCSDS_RXTX_SERDES_DEPTH-1;
signal parallel_data_pointer: integer range 0 to CCSDS_RXTX_SERDES_DEPTH-1 := CCSDS_RXTX_SERDES_DEPTH-1;
begin
-- components instanciation and mapping
bus_o <= wire_busy;
dat_par_val_o <= wire_data_par_valid;
dat_ser_val_o <= wire_data_ser_valid;
-- presynthesis checks
-- internal processing
--=============================================================================
-- Begin of par2serp
-- Serialization of parallel data received starting with MSB
--=============================================================================
-- read: clk_i, rst_i, dat_par_i, dat_par_val_i
-- write: dat_ser_o, wire_data_ser_valid, wire_busy
-- r/w: parallel_data_pointer
PAR2SERP : process (clk_i)
variable serdes_memory: std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0) := (others => '0');
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
-- reset all
wire_busy <= '0';
dat_ser_o <= '0';
wire_data_ser_valid <= '0';
parallel_data_pointer <= CCSDS_RXTX_SERDES_DEPTH-1;
-- serdes_memory := (others => '0');
else
if (dat_par_val_i = '1') and (parallel_data_pointer = CCSDS_RXTX_SERDES_DEPTH-1) then
wire_busy <= '1';
serdes_memory := dat_par_i;
-- serialise data on output_bus
dat_ser_o <= dat_par_i(parallel_data_pointer);
-- decrement position pointer
parallel_data_pointer <= (parallel_data_pointer - 1) mod CCSDS_RXTX_SERDES_DEPTH;
wire_data_ser_valid <= '1';
else
if (parallel_data_pointer /= CCSDS_RXTX_SERDES_DEPTH-1) then
wire_busy <= '1';
-- serialise data on output_bus
dat_ser_o <= serdes_memory(parallel_data_pointer);
-- decrement position pointer
parallel_data_pointer <= (parallel_data_pointer - 1) mod CCSDS_RXTX_SERDES_DEPTH;
wire_data_ser_valid <= '1';
else
-- nothing to do
wire_busy <= '0';
wire_data_ser_valid <= '0';
end if;
end if;
end if;
end if;
end process;
--=============================================================================
-- Begin of ser2parp
-- Parallelization of serial data received
--=============================================================================
-- read: clk_i, rst_i, dat_ser_i, dat_ser_val_i
-- write: dat_par_o, wire_data_par_valid
-- r/w: serial_data_pointer
SER2PARP : process (clk_i)
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
-- reset all
dat_par_o <= (others => '0');
wire_data_par_valid <= '0';
serial_data_pointer <= CCSDS_RXTX_SERDES_DEPTH-1;
else
if (dat_ser_val_i = '1') then
-- serialise data on output_bus
dat_par_o(serial_data_pointer) <= dat_ser_i;
if (serial_data_pointer = 0) then
wire_data_par_valid <= '1';
else
wire_data_par_valid <= '0';
end if;
-- decrement position pointer
serial_data_pointer <= (serial_data_pointer - 1) mod CCSDS_RXTX_SERDES_DEPTH;
else
wire_data_par_valid <= '0';
end if;
end if;
end if;
end process;
end rtl;
--=============================================================================
-- architecture end
--=============================================================================
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity registers is
port(
Clk : in std_logic;
s_decode : in std_logic;
i_fct1 : in std_logic_vector(3 downto 0);
i_fct2 : in std_logic_vector(3 downto 0);
i_fct3 : in std_logic_vector(3 downto 0);
i_fct4 : in std_logic_vector(3 downto 0);
i_unit1 : in std_logic_vector(3 downto 0);
i_unit2 : in std_logic_vector(3 downto 0);
i_unit3 : in std_logic_vector(3 downto 0);
i_unit4 : in std_logic_vector(3 downto 0);
o_unit1 : out std_logic_vector(3 downto 0);
o_unit2 : out std_logic_vector(3 downto 0);
o_unit3 : out std_logic_vector(3 downto 0);
o_unit4 : out std_logic_vector(3 downto 0);
i_registerid1_w : in std_logic_vector(6 downto 0);
i_registerid2_w : in std_logic_vector(6 downto 0);
i_registerid3_w : in std_logic_vector(6 downto 0);
i_registerid4_w : in std_logic_vector(6 downto 0);
i_registerid1_r1 : in std_logic_vector(6 downto 0);
i_registerid2_r1 : in std_logic_vector(6 downto 0);
i_registerid3_r1 : in std_logic_vector(6 downto 0);
i_registerid4_r1 : in std_logic_vector(6 downto 0);
i_registerid1_r2 : in std_logic_vector(6 downto 0);
i_registerid2_r2 : in std_logic_vector(6 downto 0);
i_registerid3_r2 : in std_logic_vector(6 downto 0);
i_registerid4_r2 : in std_logic_vector(6 downto 0);
i_register1_w : in std_logic_vector(63 downto 0);
i_register2_w : in std_logic_vector(63 downto 0);
i_register3_w : in std_logic_vector(63 downto 0);
i_register4_w : in std_logic_vector(63 downto 0);
o_register1_r1 : out std_logic_vector(63 downto 0);
o_register2_r1 : out std_logic_vector(63 downto 0);
o_register3_r1 : out std_logic_vector(63 downto 0);
o_register4_r1 : out std_logic_vector(63 downto 0);
o_register1_r2 : out std_logic_vector(63 downto 0);
o_register2_r2 : out std_logic_vector(63 downto 0);
o_register3_r2 : out std_logic_vector(63 downto 0);
o_register4_r2 : out std_logic_vector(63 downto 0);
-----------
i_pregister1_w : in std_logic_vector(127 downto 0);
i_pregister2_w : in std_logic_vector(127 downto 0);
o_pregister1_r1 : out std_logic_vector(127 downto 0);
o_pregister2_r1 : out std_logic_vector(127 downto 0);
o_pregister1_r2 : out std_logic_vector(127 downto 0);
o_pregister2_r2 : out std_logic_vector(127 downto 0);
i_flagrw : in std_logic_vector(127 downto 0)
);
end entity;
architecture behaviour of registers is
begin
process (s_decode)
variable v_opcode : std_logic_vector(63 downto 0);
variable v_flagrw : std_logic;
variable id : integer;
type t_Register is array (0 to 63) of std_logic_vector(63 downto 0);
variable r_Reg : t_Register;
type t_Register2 is array (0 to 63) of std_logic_vector(125 downto 0);
variable r_Reg2 : t_Register;
begin
id := to_integer(unsigned(i_registerid1_r1));
o_register1_r1 <= r_Reg(id);
id := to_integer(unsigned(i_registerid1_r2));
o_register1_r2 <= r_Reg(id);
--ADD/SUB
if i_unit1="0001" then
o_unit1 <= i_unit1;
--ALU (OR/XOR/MOVE etc etc)
elsif i_unit1="0010" then
o_unit1 <= i_unit1;
--MUL
--elsif i_unit1="0011" then
--DIV
--elsif i_unit1="0100" then
--LSU
--elsif i_unit1="0101" then
--VPU MULADD PS/FS/FD
--elsif i_unit1="0110" then
--VPU MOVE
--elsif i_unit1="0111" then
--VDIV(VSQRT)
--elsif i_unit1="1000" then
--CMP
--elsif i_unit1="1110" then
--MMU -> DMA
--elsif i_unit1="1111" then
else
o_unit1 <= i_unit1;
end if;
end process;
end architecture;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY KCVGA IS PORT
(
pin_nRESET : IN STD_LOGIC;
pin_CLK : IN STD_LOGIC;
pin_PIC32_DATA : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
pin_PIC32_ADDRESS : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
pin_PIC32_nWR : IN STD_LOGIC;
pin_PIC32_nRD : IN STD_LOGIC;
-- pin_KC_CLK : IN STD_LOGIC; -- external video clock 7.09 MHz
-- pin_KC_R, pin_KC_G, pin_KC_B : IN STD_LOGIC; -- pixel colors
-- pin_KC_EZ : IN STD_LOGIC; -- foreground/background bit
-- pin_KC_EX : IN STD_LOGIC; -- intensity bit
-- pin_KC_HSYNC : IN STD_LOGIC; -- horizontal sync input
-- pin_KC_VSYNC : IN STD_LOGIC; -- vertical sync input
-- pin_VGA_R, pin_VGA_G, pin_VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-- pin_VGA_VSYNC, pin_VGA_HSYNC : OUT STD_LOGIC;
-- pin_JUMPER0 : IN STD_LOGIC -- SCANLINES
-- pin_JUMPER1: in STD_LOGIC;
-- pin_JUMPER2: in STD_LOGIC;
-- pin_JUMPER3: in STD_LOGIC;
-- pin_JUMPER4: in STD_LOGIC;
-- pin_JUMPER5: in STD_LOGIC
pin_SRAM_A : OUT STD_LOGIC_VECTOR (16 DOWNTO 0); -- SRAM address output
pin_SRAM_D : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0); -- SRAM data output
pin_SRAM_nCE : OUT STD_LOGIC; -- SRAM chip enable
pin_SRAM_nOE : OUT STD_LOGIC; -- SRAM output enable
pin_SRAM_nWE : OUT STD_LOGIC; -- SRAM write enable
pin_SRAM_nBHE : OUT STD_LOGIC; -- SRAM H byte enable
pin_SRAM_nBLE : OUT STD_LOGIC -- SRAM L byte enable
);
END KCVGA;
ARCHITECTURE Behavioral OF KCVGA IS
SIGNAL sig_CLK_108MHZ, sig_RESET : STD_LOGIC;
-- SIGNAL sig_FRAMESYNC : STD_LOGIC; -- start of frame from VGA module for screensaver
-- SIGNAL sig_PIC32_WR_FIFO_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0);
-- SIGNAL sig_PIC32_WR_FIFO_IN : STD_LOGIC_VECTOR (31 DOWNTO 0);
-- SIGNAL sig_PIC32_WR_FIFO_WR : STD_LOGIC;
-- SIGNAL sig_PIC32_WR_FIFO_FULL : STD_LOGIC;
-- SIGNAL sig_PIC32_WR_FIFO_RD : STD_LOGIC;
-- SIGNAL sig_PIC32_WR_FIFO_EMPTY : STD_LOGIC;
-- signal sig_PIC32_RD_FIFO_OUT: STD_LOGIC_VECTOR (31 downto 0);
-- signal sig_PIC32_RD_FIFO_IN: STD_LOGIC_VECTOR (31 downto 0);
-- signal sig_PIC32_RD_FIFO_WR: STD_LOGIC;
-- signal sig_PIC32_RD_FIFO_FULL: STD_LOGIC;
-- signal sig_PIC32_RD_FIFO_RD: STD_LOGIC;
-- signal sig_PIC32_RD_FIFO_EMPTY: STD_LOGIC;
-- SIGNAL sig_KC_FIFO_WR : STD_LOGIC;
-- SIGNAL sig_KC_FIFO_FULL : STD_LOGIC;
-- SIGNAL sig_KC_FIFO_RD : STD_LOGIC;
-- SIGNAL sig_KC_FIFO_EMPTY : STD_LOGIC;
-- SIGNAL sig_KC_FIFO_OUT : STD_LOGIC_VECTOR (4 DOWNTO 0);
-- SIGNAL sig_KC_FIFO_IN : STD_LOGIC_VECTOR (4 DOWNTO 0);
-- SIGNAL sig_KC_ADDR_WR : STD_LOGIC;
-- SIGNAL sig_KC_ADDR : STD_LOGIC_VECTOR(16 DOWNTO 0);
-- SIGNAL sig_VGA_ADDR_WR : STD_LOGIC;
-- SIGNAL sig_VGA_ADDR : STD_LOGIC_VECTOR(16 DOWNTO 0);
-- SIGNAL sig_VGA_FIFO_RST : STD_LOGIC;
-- SIGNAL sig_VGA_FIFO_RST_COMBINED : STD_LOGIC;
-- SIGNAL sig_VGA_FIFO_RD : STD_LOGIC;
-- SIGNAL sig_VGA_FIFO_WR : STD_LOGIC;
-- SIGNAL sig_VGA_FIFO_IN : STD_LOGIC_VECTOR(4 DOWNTO 0);
-- SIGNAL sig_VGA_FIFO_OUT : STD_LOGIC_VECTOR(4 DOWNTO 0);
-- SIGNAL sig_VGA_FIFO_EMPTY : STD_LOGIC;
-- SIGNAL sig_VGA_FIFO_FULL : STD_LOGIC;
-- SIGNAL sig_FLAG_REGISTER : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- -- SIGNAL sig_DEBUG_REGISTER : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- SIGNAL suppress_no_load_pins_warning : STD_LOGIC;
BEGIN
--
-- +-------------------+
-- | KCVIDEO_INTERFACE |
-- | |
-- ====>| R,G,B,EX,EZ |
-- | |
-- ---->| KC_CLK |
-- ---->| HSYNC |
-- ---->| VSYNC |
-- +-------------------+
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-- suppress_no_load_pins_warning <=
-- pin_KC_EX
-- OR pin_KC_EZ
-- OR pin_KC_HSYNC
-- OR pin_KC_VSYNC
-- OR pin_KC_R
-- OR pin_KC_G
-- OR pin_KC_B
-- OR pin_JUMPER0
-- OR pin_KC_CLK;
i_CLK : ENTITY work.CLK PORT MAP
(
reset => sig_RESET,
clk_input => pin_CLK,
clk_output => sig_CLK_108MHZ
);
sig_RESET <= NOT pin_nRESET;
-- sig_FLAG_REGISTER <= '1' & '1'
-- & sig_PIC32_WR_FIFO_FULL & sig_PIC32_WR_FIFO_EMPTY
-- & sig_KC_FIFO_FULL & sig_KC_FIFO_EMPTY
-- & sig_VGA_FIFO_FULL & sig_VGA_FIFO_EMPTY;
-- always drive SRAM chip enable, high byte enable and low byte enable with
-- active signals
-- pin_SRAM_nCE <= '0';
-- pin_SRAM_nBHE <= '0';
-- pin_SRAM_nBLE <= '0';
i_PIC32_INTERFACE : ENTITY work.PIC32_INTERFACE PORT
MAP
(
CLK => sig_CLK_108MHZ,
RESET => sig_RESET,
A => pin_PIC32_ADDRESS,
D => pin_PIC32_DATA,
-- SRAM => sig_PIC32_WR_FIFO_IN,
-- OUT_FIFO_WR => sig_PIC32_WR_FIFO_WR,
-- OUT_FIFO_FULL => sig_PIC32_WR_FIFO_FULL,
nWR => pin_PIC32_nWR,
nRD => pin_PIC32_nRD,
-- FLAGS => sig_FLAG_REGISTER,
-- DEBUG => sig_DEBUG_REGISTER,
SRAM_A => pin_SRAM_A,
SRAM_D => pin_SRAM_D,
SRAM_nOE => pin_SRAM_nOE,
SRAM_nWE => pin_SRAM_nWE,
SRAM_nCE => pin_SRAM_nCE,
SRAM_nBLE => pin_SRAM_nBLE,
SRAM_nBHE => pin_SRAM_nBHE
-- suppress_no_load_pins_warning => suppress_no_load_pins_warning
);
-- i_PIC32_WR_FIFO : ENTITY work.FIFO GENERIC
-- MAP(
-- RAM_WIDTH => 32,
-- RAM_DEPTH => 128
-- ) PORT
-- MAP(
-- clk => sig_CLK_108MHZ,
-- rst => sig_RESET,
-- wr_en => sig_PIC32_WR_FIFO_WR,
-- wr_data => sig_PIC32_WR_FIFO_IN,
-- rd_en => sig_PIC32_WR_FIFO_RD,
-- rd_data => sig_PIC32_WR_FIFO_OUT,
-- empty => sig_PIC32_WR_FIFO_EMPTY,
-- full => sig_PIC32_WR_FIFO_FULL
-- );
-- i_KCVIDEO_INTERFACE : ENTITY work.KCVIDEO_INTERFACE PORT
-- MAP(
-- CLK => sig_CLK_108MHZ,
-- KC_CLK => pin_KC_CLK,
-- R => pin_KC_R,
-- G => pin_KC_G,
-- B => pin_KC_B,
-- EZ => pin_KC_EZ,
-- EX => pin_KC_EX,
-- HSYNC => pin_KC_HSYNC,
-- VSYNC => pin_KC_VSYNC,
-- nRESET => pin_nRESET,
-- FIFO_WR => sig_KC_FIFO_WR,
-- FIFO_FULL => sig_KC_FIFO_FULL,
-- FRAMESYNC => sig_FRAMESYNC,
-- DATA_OUT => sig_KC_FIFO_IN,
-- SRAM_ADDR => sig_KC_ADDR,
-- SRAM_ADDR_WR => sig_KC_ADDR_WR
-- );
-- i_KC_FIFO : ENTITY work.FIFO GENERIC
-- MAP(
-- RAM_WIDTH => 5,
-- RAM_DEPTH => 512
-- ) PORT
-- MAP(
-- clk => sig_CLK_108MHZ,
-- rst => sig_RESET,
-- wr_en => sig_KC_FIFO_WR,
-- wr_data => sig_KC_FIFO_IN,
-- rd_en => sig_KC_FIFO_RD,
-- rd_data => sig_KC_FIFO_OUT,
-- empty => sig_KC_FIFO_EMPTY,
-- full => sig_KC_FIFO_FULL
-- );
-- -- video mode definition
-- -- 1280x1024 @ 60 Hz, 108 MHz pixel clock, positive sync
-- i_VGA_OUTPUT : ENTITY work.VGA_OUTPUT GENERIC
-- MAP(
-- -- see https://www.mythtv.org/wiki/Modeline_Database
-- 1280, 1328, 1440, 1688, 1024, 1025, 1028, 1066, '1', '1'
-- ) PORT
-- MAP(
-- CLK => sig_CLK_108MHZ,
-- HSYNC => pin_VGA_HSYNC,
-- VSYNC => pin_VGA_VSYNC,
-- R => pin_VGA_R, G => pin_VGA_G, B => pin_VGA_B,
-- nRESET => pin_nRESET,
-- SCANLINES => pin_JUMPER0,
-- FRAMESYNC => sig_FRAMESYNC,
-- FIFO_RD => sig_VGA_FIFO_RD,
-- VGA_ADDR_WR => sig_VGA_ADDR_WR,
-- VGA_ADDR => sig_VGA_ADDR,
-- DATA_IN => sig_VGA_FIFO_OUT,
-- VGA_FIFO_EMPTY => sig_VGA_FIFO_EMPTY
-- );
-- sig_VGA_FIFO_RST_COMBINED <= sig_VGA_FIFO_RST OR sig_RESET;
-- i_VGA_FIFO : ENTITY work.FIFO GENERIC
-- MAP(
-- RAM_WIDTH => 5,
-- RAM_DEPTH => 512
-- ) PORT
-- MAP(
-- clk => sig_CLK_108MHZ,
-- rst => sig_VGA_FIFO_RST_COMBINED,
-- wr_en => sig_VGA_FIFO_WR,
-- wr_data => sig_VGA_FIFO_IN,
-- rd_en => sig_VGA_FIFO_RD,
-- rd_data => sig_VGA_FIFO_OUT,
-- empty => sig_VGA_FIFO_EMPTY,
-- full => sig_VGA_FIFO_FULL
-- );
-- i_SRAM_INTERFACE : ENTITY work.SRAM_INTERFACE PORT
-- MAP(
-- VGA_ADDR => sig_VGA_ADDR, -- address requested from VGA module
-- VGA_DATA => sig_VGA_FIFO_IN, -- data out to VGA module
-- VGA_ADDR_WR => sig_VGA_ADDR_WR, -- VGA address write input
-- VGA_FIFO_WR => sig_VGA_FIFO_WR, -- VGA FIFO write output
-- VGA_FIFO_RST => sig_VGA_FIFO_RST,
-- VGA_FIFO_FULL => sig_VGA_FIFO_FULL,
-- KCVIDEO_DATA => sig_KC_FIFO_OUT,
-- KCVIDEO_FIFO_RD => sig_KC_FIFO_RD,
-- KCVIDEO_FIFO_EMPTY => sig_KC_FIFO_EMPTY,
-- PIC32_DATA => sig_PIC32_WR_FIFO_OUT,
-- PIC32_FIFO_RD => sig_PIC32_WR_FIFO_RD,
-- PIC32_FIFO_EMPTY => sig_PIC32_WR_FIFO_EMPTY,
-- A => pin_SRAM_A,
-- D => pin_SRAM_D,
-- nOE => pin_SRAM_nOE,
-- nWE => pin_SRAM_nWE,
-- nCE => pin_SRAM_nCE,
-- nBLE => pin_SRAM_nBLE,
-- nBHE => pin_SRAM_nBHE,
-- reset => sig_RESET,
-- CLK => sig_CLK_108MHZ,
-- KCVIDEO_ADDR => sig_KC_ADDR,
-- KCVIDEO_ADDR_WR => sig_KC_ADDR_WR,
-- DEBUG => sig_DEBUG_REGISTER
-- );
END Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;
entity pwm_encoder_tb is
end pwm_encoder_tb;
architecture testbench of pwm_encoder_tb is
constant clock_period: time := 10 ns;
-- 10 MHz sampling frequency (100ns sampling period)
-- such an high sampling rate will allow only 10 datapoints
constant sampling_frequency: positive := 10_000_000;
constant sample_bits: positive := 4;
signal clock: std_logic;
signal sample: std_logic_vector(sample_bits-1 downto 0);
signal pwm_out: std_logic;
signal stop_write: boolean := false;
begin
clock_proc: entity work.tb_clock_process generic map (clock_period)
port map(
clock => clock
);
uut: entity work.pwm_encoder
generic map (
input_sampling_frequency => sampling_frequency,
input_sample_bits => sample_bits
)
port map (
i_clk => clock,
i_sample => sample,
o_pwm_signal => pwm_out
);
test_process: process
begin
sample <= 4b"1010";
wait for clock_period * 50;
sample <= 4b"0010";
wait for clock_period * 50;
sample <= 4b"0000";
wait for clock_period * 50;
stop_write <= true;
end process test_process;
logger: entity work.tb_logger
generic map(
clock_frequency => 100_000_000,
filename => "pwm_out.txt"
)
port map(
i_clock => clock,
i_pwm => pwm_out,
i_stop => stop_write
);
end testbench;
|
<gh_stars>1-10
----------------------------------------------------------------------------------
-- Engineer: <NAME>
-- Company: Politecnico di Torino
-- Design units: CARRY_SELECT_BLOCK
-- Function: Carry select block, used by Adder/Subtractor
-- Input: A,B (4-bit), Ci (1-bit)
-- Output: S (4-bit)
-- Architecture: structural
-- Library/package: ieee.std_logic_ll64, work.globals
-- Date: 14/04/2020
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.std_logic_1164.all;
use work.globals.all;
entity CSB is
generic (RADIX: integer := radix_size);
port (A: in std_logic_vector(RADIX-1 downto 0);
B: in std_logic_vector(RADIX-1 downto 0);
Ci: in std_logic;
S: out std_logic_vector(RADIX-1 downto 0));
end entity;
architecture STRUCTURAL of CSB is
-- Components
component RCA
generic (WIDTH: integer := word_size);
port (A: in std_logic_vector(WIDTH-1 downto 0);
B: in std_logic_vector(WIDTH-1 downto 0);
Ci: in std_logic;
S: out std_logic_vector(WIDTH-1 downto 0);
Co: out std_logic);
end component;
component MUX21_GENERIC
generic (NBIT: integer:= 4);
port (S0: in std_logic_vector(NBIT-1 downto 0);
S1: in std_logic_vector(NBIT-1 downto 0);
SEL: in std_logic;
Y: out std_logic_vector(NBIT-1 downto 0));
end component;
--Signals
signal S0, S1: std_logic_vector(RADIX-1 downto 0) := (others => '0');
begin
-- Instatiations
RCA0: RCA
generic map(RADIX)
port map(A, B, '0', S0);
RCA1: RCA
generic map(RADIX)
port map(A, B, '1', S1);
MUX21_SUM: MUX21_GENERIC
generic map(RADIX)
port map(S0, S1, Ci, S);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity %%%NAME%%% is
port (
clk : in std_logic;
--rst : in std_logic;
--en : in std_logic;
addr : in std_logic_vector(%%%ADDR_LEN%%%-1 downto 0);
dout : out std_logic_vector(%%%DATA_SIZE%%%-1 downto 0)
);
end %%%NAME%%%;
architecture rtl of %%%NAME%%% is
type mem_type is array ( (2**%%%ADDR_LEN%%%)-1 downto 0 ) of std_logic_vector(%%%DATA_SIZE%%%-1 downto 0);
-- Shared memory
shared variable mem : mem_type := (
%%%DATA%%%
);
begin
process(clk)
begin
if(clk'event and clk='1') then
dout <= mem(conv_integer(addr));
end if;
end process;
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: eth_ahb_mst
-- File: eth_ahb_mst.vhd
-- Author: <NAME> - Gaisler Research
-- Description: Ethernet MAC AHB master interface
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end entity;
architecture rtl of eth_ahb_mst is
type reg_type is record
bg : std_ulogic; --bus granted
bo : std_ulogic; --bus owner, 0=rx, 1=tx
ba : std_ulogic; --bus active
bb : std_ulogic; --1kB burst boundary detected
retry : std_ulogic;
end record;
signal r, rin : reg_type;
begin
comb : process(rst, r, tmsti, rmsti, ahbmi) is
variable v : reg_type;
variable htrans : std_logic_vector(1 downto 0);
variable hbusreq : std_ulogic;
variable hwrite : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable nbo : std_ulogic;
variable tretry : std_ulogic;
variable rretry : std_ulogic;
variable rready : std_ulogic;
variable tready : std_ulogic;
variable rerror : std_ulogic;
variable terror : std_ulogic;
variable tgrant : std_ulogic;
variable rgrant : std_ulogic;
begin
v := r; htrans := HTRANS_IDLE; rready := '0'; tready := '0'; tretry := '0';
rretry := '0'; rerror := '0'; terror := '0'; tgrant := '0'; rgrant := '0';
if r.bo = '0' then hwdata := rmsti.data;
else hwdata := tmsti.data; end if;
hbusreq := tmsti.req or rmsti.req;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
if r.retry = '0' then
nbo := tmsti.req and not (rmsti.req and not r.bo);
else
nbo := r.bo;
end if;
if nbo = '0' then
haddr := rmsti.addr; hwrite := rmsti.write;
if (rmsti.req and r.ba and not r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (rmsti.req and r.bg and ahbmi.hready and not r.retry) = '1'
then rgrant := '1'; end if;
else
haddr := tmsti.addr; hwrite := tmsti.write;
if (tmsti.req and r.ba and r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ;
end if;
if (tmsti.req and r.bg and ahbmi.hready and not r.retry) = '1'
then tgrant := '1'; end if;
end if;
--1 kB burst boundary
if ahbmi.hready = '1' then
if haddr(9 downto 2) = "11111111" then
v.bb := '1';
else
v.bb := '0';
end if;
end if;
if (r.bb = '1') and (htrans /= HTRANS_IDLE) then
htrans := HTRANS_NONSEQ;
end if;
if r.bo = '0' then
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => rready := '1';
when HRESP_SPLIT | HRESP_RETRY => rretry := '1';
when HRESP_ERROR => rerror := '1';
when others => null;
end case;
end if;
end if;
else
if r.ba = '1' then
if ahbmi.hready = '1' then
case ahbmi.hresp is
when HRESP_OKAY => tready := '1';
when HRESP_SPLIT | HRESP_RETRY => tretry := '1';
when HRESP_ERROR => terror := '1';
when others => null;
end case;
end if;
end if;
end if;
if (r.ba = '1') and
((ahbmi.hresp = HRESP_RETRY) or (ahbmi.hresp = HRESP_SPLIT))
then v.retry := not ahbmi.hready; else v.retry := '0'; end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if ahbmi.hready = '1' then
v.bo := nbo; v.bg := ahbmi.hgrant;
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else
v.ba := '0';
end if;
end if;
if rst = '0' then
v.bg := '0'; v.ba := '0'; v.bo := '0'; v.bb := '0';
end if;
rin <= v;
tmsto.data <= ahbmi.hrdata;
rmsto.data <= ahbmi.hrdata;
tmsto.error <= terror;
tmsto.retry <= tretry;
tmsto.ready <= tready;
rmsto.error <= rerror;
rmsto.retry <= rretry;
rmsto.ready <= rready;
tmsto.grant <= tgrant;
rmsto.grant <= rgrant;
ahbmo.htrans <= htrans;
ahbmo.hbusreq <= hbusreq;
ahbmo.haddr <= haddr;
ahbmo.hwrite <= hwrite;
ahbmo.hwdata <= hwdata;
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
ahbmo.hlock <= '0';
ahbmo.hsize <= HSIZE_WORD;
ahbmo.hburst <= HBURST_INCR;
ahbmo.hprot <= "0011";
end architecture;
|
-- Implements a basic analog sine wave generator. The output of the frequency synthesizer is
-- used as an enable signal to a counter which controls the output of a ROM. The ROM
-- stores precomputed value for a shifted sine wave. The update signal must be asserted for
-- N clock cycles when changing the frequency_control input in order to avoid phase discontinuity.
--
-- The output frequency is related to frequency_control and the clock rate by
-- output frequency = 1/10 * frequency_control * clock_rate / 2 ** N
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity analog_waveform_generator is
generic (N : integer := 5);
port (clock : in std_logic;
reset : in std_logic;
update : in std_logic;
frequency_control : in std_logic_vector(N-1 downto 0);
analog_waveform : out std_logic_vector(7 downto 0));
end analog_waveform_generator;
architecture arch of analog_waveform_generator is
component pipelined_frequency_synthesizer is
generic (N : integer := 5);
port (clock : in std_logic;
reset : in std_logic;
update : in std_logic;
frequency_control : in std_logic_vector(N-1 downto 0);
frequency : out std_logic);
end component;
-- MATLAB generated sine wave (shifted to range [0, 256))
-- t = 0:9;
-- sine = ( 128 * ( sin(2*pi/10*t) + 1 ) );
type rom is array(0 to 9) of std_logic_vector(7 downto 0);
constant sine_wave : rom := (
"10000000", "11001011",
"11111010", "11111010",
"11001011", "10000000",
"00110101", "00000110",
"00000110", "00110101");
signal frequency : std_logic;
signal cnt : unsigned(3 downto 0);
begin
synthesizer : pipelined_frequency_synthesizer
generic map (N => N)
port map (clock => clock,
reset => reset,
update => update,
frequency_control => frequency_control,
frequency => frequency);
counter : process (clock, reset)
begin
if (reset = '1') then
cnt <= (others => '0');
elsif (rising_edge(clock)) then
-- frequency acts as an enable signal
if (frequency = '1') then
if (cnt = x"9") then
cnt <= (others => '0');
else
cnt <= cnt + 1;
end if;
end if;
end if;
end process;
analog_waveform <= sine_wave(to_integer(unsigned(cnt)));
end architecture;
|
-- file Sramemu_wrp.vhd
-- Sramemu_wrp wrapper implementation
-- author <NAME>
-- date created: 22 Sep 2017
-- date modified: 22 Sep 2017
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Dbecore.all;
use work.Bss3.all;
entity Sramemu_wrp is
port (
lw_clk_wrp: out std_logic;
lw_snc_wrp: out std_logic;
lw_d1_wrp: out std_logic;
lw_d2_wrp: out std_logic;
lw_extsnc_wrp: in std_logic;
extclk: in std_logic;
led: out std_logic_vector(15 downto 0);
sw: in std_logic_vector(15 downto 0);
JA: out std_logic_vector(7 downto 0);
btnC: in std_logic;
btnL: in std_logic;
btnR: in std_logic;
RsRx: in std_logic;
RsTx: out std_logic;
clk: in std_logic;
snc: in std_logic;
d1: in std_logic;
d2: in std_logic;
extsnc: out std_logic;
JC: out std_logic_vector(7 downto 0);
JB: out std_logic_vector(7 downto 0);
an: out std_logic_vector(3 downto 0);
dp: out std_logic;
seg: out std_logic_vector(6 downto 0);
JXADC: out std_logic_vector(7 downto 0)
);
end Sramemu_wrp;
architecture Sramemu_wrp of Sramemu_wrp is
------------------------------------------------------------------------
-- component declarations
------------------------------------------------------------------------
component Spbram_v1_0_size160kB is
port (
clk: in std_logic;
en: in std_logic;
we: in std_logic;
a: in std_logic_vector(17 downto 0);
drd: out std_logic_vector(7 downto 0);
dwr: in std_logic_vector(7 downto 0)
);
end component;
component Top is
generic (
fExtclk: natural range 1 to 1000000 := 100000;
fMclk: natural range 1 to 1000000 := 50000
);
port (
lw_clk_wrp: out std_logic;
lw_snc_wrp: out std_logic;
lw_d1_wrp: out std_logic;
lw_d2_wrp: out std_logic;
lw_extsnc_wrp: in std_logic;
extclk: in std_logic;
led: out std_logic_vector(15 downto 0);
sw: in std_logic_vector(15 downto 0);
JA: out std_logic_vector(7 downto 0);
btnC: in std_logic;
btnL: in std_logic;
btnR: in std_logic;
RsRx: in std_logic;
RsTx: out std_logic;
clk: in std_logic;
snc: in std_logic;
d1: in std_logic;
d2: in std_logic;
extsnc: out std_logic;
JC: out std_logic_vector(7 downto 0);
nce: out std_logic;
noe: out std_logic;
nwe: out std_logic;
a: out std_logic_vector(17 downto 0);
d: inout std_logic_vector(7 downto 0);
JB: out std_logic_vector(7 downto 0);
an: out std_logic_vector(3 downto 0);
dp: out std_logic;
seg: out std_logic_vector(6 downto 0);
JXADC: out std_logic_vector(7 downto 0)
);
end component;
------------------------------------------------------------------------
-- signal declarations
------------------------------------------------------------------------
---- myBuf
signal enBuf: std_logic;
signal weBuf: std_logic;
signal drdBuf: std_logic_vector(7 downto 0);
---- other
signal emuclk: std_logic;
signal sr_nce: std_logic;
signal sr_noe: std_logic;
signal sr_nwe: std_logic;
signal sr_a: std_logic_vector(17 downto 0);
signal sr_d: std_logic_vector(7 downto 0);
-- IP sigs.oth.cust --- INSERT
begin
------------------------------------------------------------------------
-- sub-module instantiation
------------------------------------------------------------------------
myBuf : Spbram_v1_0_size160kB
port map (
clk => emuclk,
en => enBuf,
we => weBuf,
a => sr_a,
drd => drdBuf,
dwr => sr_d
);
myTop : Top
generic map (
fExtclk => 100000,
fMclk => 50000
)
port map (
lw_clk_wrp => lw_clk_wrp,
lw_snc_wrp => lw_snc_wrp,
lw_d1_wrp => lw_d1_wrp,
lw_d2_wrp => lw_d2_wrp,
lw_extsnc_wrp => lw_extsnc_wrp,
extclk => extclk,
led => led,
sw => sw,
JA => JA,
btnC => btnC,
btnL => btnL,
btnR => btnR,
RsRx => RsRx,
RsTx => RsTx,
clk => clk,
snc => snc,
d1 => d1,
d2 => d2,
extsnc => extsnc,
JC => JC,
nce => sr_nce,
noe => sr_noe,
nwe => sr_nwe,
a => sr_a,
d => sr_d,
JB => JB,
an => an,
dp => dp,
seg => seg,
JXADC => JXADC
);
------------------------------------------------------------------------
-- implementation: other
------------------------------------------------------------------------
-- IP impl.oth.cust --- IBEGIN
emuclk <= not extclk;
enBuf <= not sr_nce;
weBuf <= not sr_nwe;
sr_d <= drdBuf when (sr_nce='0' and sr_noe='0') else "ZZZZZZZZ";
-- IP impl.oth.cust --- IEND
end Sramemu_wrp;
|
<reponame>zxb-0/FPGA2<filename>simulation/modelsim/verilog_libs/cycloneive_ver/cycloneive_mac_mult_internal/_primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneive_mac_mult_internal is
generic(
dataa_width : integer := 18;
datab_width : integer := 18;
dataout_width : vl_notype
);
port(
dataa : in vl_logic_vector;
datab : in vl_logic_vector;
signa : in vl_logic;
signb : in vl_logic;
dataout : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of dataa_width : constant is 1;
attribute mti_svvh_generic_type of datab_width : constant is 1;
attribute mti_svvh_generic_type of dataout_width : constant is 3;
end cycloneive_mac_mult_internal;
|
<filename>ip/argsort_axi_0.7/src/PIPEWORK/register_access_syncronizer.vhd
-----------------------------------------------------------------------------------
--! @file register_access_syncronizer.vhd
--! @brief REGISTER ACCESS SYNCRONIZER MODULE :
--! 異なるクロックドメイン間でレジスタアクセスを中継するモジュール.
--! @version 1.5.5
--! @date 2014/3/20
--! @author <NAME> <<EMAIL>>
-----------------------------------------------------------------------------------
--
-- Copyright (C) 2014 <NAME>
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-- OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------------------------
--! @brief REGISTER ACCESS SYNCRONIZER MODULE
--! 異なるクロックドメイン間でレジスタアクセスを中継するモジュール.
--! * 入力側のクロック(I_CLK)に同期化された入力データを
--! 出力側クロック(O_CLK)に同期化して出力する.
--! * 入力側のクロック(I_CLK)と出力側のクロック(O_CLK)との関係は、
--! ジェネリック変数I_CLK_RATEとO_CLK_RATEで指示する.
--! 詳細は O_CLK_RATE を参照.
-----------------------------------------------------------------------------------
entity REGISTER_ACCESS_SYNCRONIZER is
generic (
ADDR_WIDTH : --! @brief REGISTER ADDRESS WIDTH :
--! レジスタアクセスインターフェースのアドレスのビット幅を指
--! 定する.
integer := 32;
DATA_WIDTH : --! @brief REGISTER DATA WIDTH :
--! レジスタアクセスインターフェースのデータのビット幅を指定
--! する.
integer := 32;
I_CLK_RATE : --! @brief INPUT CLOCK RATE :
--! O_CLK_RATEとペアで入力側のクロック(I_CLK)と出力側のクロッ
--! ク(O_CLK)との関係を指定する.
--! 詳細は PipeWork.Components の SYNCRONIZER を参照.
integer := 1;
O_CLK_RATE : --! @brief OUTPUT CLOCK RATE :
--! I_CLK_RATEとペアで入力側のクロック(I_CLK)と出力側のクロッ
--! ク(O_CLK)との関係を指定する.
--! 詳細は PipeWork.Components の SYNCRONIZER を参照.
integer := 1;
O_CLK_REGS : --! @brief REGISTERD OUTPUT :
--! 出力側の各種信号(O_REQ/O_WRITE/O_WDATA/O_BEN)をレジスタ
--! 出力するかどうかを指定する.
--! * この変数は I_CLK_RATE > 0 の場合のみ有効.
--! I_CLK_RATE = 0 の場合は、常にレジスタ出力になる.
--! * O_CLK_REGS = 0 の場合はレジスタ出力しない.
--! * O_CLK_REGS = 1 の場合はレジスタ出力する.
integer range 0 to 1 := 0
);
port (
-------------------------------------------------------------------------------
-- リセット信号
-------------------------------------------------------------------------------
RST : --! @brief RESET :
--! 非同期リセット信号(ハイ・アクティブ).
in std_logic;
-------------------------------------------------------------------------------
-- 入力側のクロック信号/同期リセット信号
-------------------------------------------------------------------------------
I_CLK : --! @brief INPUT CLOCK :
--! 入力側のクロック信号.
in std_logic;
I_CLR : --! @brief INPUT CLEAR :
--! 入力側の同期リセット信号(ハイ・アクティブ).
in std_logic;
I_CKE : --! @brief INPUT CLOCK ENABLE :
--! 入力側のクロック(I_CLK)の立上りが有効であることを示す信号.
--! * この信号は I_CLK_RATE > 1 の時に、I_CLK と O_CLK の位相
--! 関係を示す時に使用する.
--! * I_CLKの立上り時とOCLKの立上り時が同じ時にアサートするよ
--! うに入力されなければならない.
--! * この信号は I_CLK_RATE > 1 かつ O_CLK_RATE = 1の時のみ有
--! 効. それ以外は未使用.
in std_logic := '1';
-------------------------------------------------------------------------------
-- 入力側のレジスタアクセスインターフェース
-------------------------------------------------------------------------------
I_REQ : --! @brief INPUT REGISTER ACCESS REQUEST :
--! レジスタアクセス要求信号.
in std_logic;
I_SEL : --! @brief INPUT REGISTER ACCESS SELECT :
--! レジスタアクセス選択信号.
--! * I_REQ='1'の際、この信号が'1'の時にのみレジスタアクセス
--! を開始する.
in std_logic := '1';
I_WRITE : --! @brief INPUT REGISTER WRITE ACCESS :
--! レジスタライトアクセス信号.
--! * この信号が'1'の時はライトアクセスを行う.
--! * この信号が'0'の時はリードアクセスを行う.
in std_logic;
I_ADDR : --! @brief INPUT REGISTER ACCESS ADDRESS :
--! レジスタアクセスアドレス信号.
in std_logic_vector(ADDR_WIDTH -1 downto 0);
I_BEN : --! @brief INPUT REGISTER BYTE ENABLE :
--! レジスタアクセスバイトイネーブル信号.
in std_logic_vector(DATA_WIDTH/8-1 downto 0);
I_WDATA : --! @brief INPUT REGISTER ACCESS WRITE DATA :
--! レジスタアクセスライトデータ.
in std_logic_vector(DATA_WIDTH -1 downto 0);
I_RDATA : --! @brief INPUT REGISTER ACCESS READ DATA :
--! レジスタアクセスリードデータ.
out std_logic_vector(DATA_WIDTH -1 downto 0);
I_ACK : --! @brief INPUT REGISTER ACCESS ACKNOWLEDGE :
--! レジスタアクセス応答信号.
out std_logic;
I_ERR : --! @brief INPUT REGISTER ACCESS ERROR ACKNOWLEDGE :
--! レジスタアクセスエラー応答信号.
out std_logic;
-------------------------------------------------------------------------------
-- 出力側のクロック信号/同期リセット信号
-------------------------------------------------------------------------------
O_CLK : --! @brief OUTPUT CLK :
--! 出力側のクロック信号.
in std_logic;
O_CLR : --! @brief OUTPUT CLEAR :
--! 出力側の同期リセット信号(ハイ・アクティブ).
in std_logic;
O_CKE : --! @brief OUTPUT CLOCK ENABLE :
--! 出力側のクロック(O_CLK)の立上りが有効であることを示す信号.
--! * この信号は I_CLK_RATE > 1 の時に、I_CLK と O_CLK の位相
--! 関係を示す時に使用する.
--! * I_CLKの立上り時とO_CLKの立上り時が同じ時にアサートする
--! ように入力されなければならない.
--! * この信号は O_CLK_RATE > 1 かつ I_CLK_RATE = 1の時のみ有
--! 効. それ以外は未使用.
in std_logic := '1';
-------------------------------------------------------------------------------
-- 出力側のレジスタアクセスインターフェース
-------------------------------------------------------------------------------
O_REQ : --! @brief OUTNPUT REGISTER ACCESS REQUEST :
--! レジスタアクセス要求信号.
out std_logic;
O_WRITE : --! @brief OUTPUT REGISTER WRITE ACCESS :
--! レジスタライトアクセス信号.
--! * この信号が'1'の時はライトアクセスを行う.
--! * この信号が'0'の時はリードアクセスを行う.
out std_logic;
O_ADDR : --! @brief OUTPUT REGISTER ACCESS ADDRESS :
--! レジスタアクセスアドレス信号.
out std_logic_vector(ADDR_WIDTH -1 downto 0);
O_BEN : --! @brief OUTPUT REGISTER BYTE ENABLE :
--! レジスタアクセスバイトイネーブル信号.
out std_logic_vector(DATA_WIDTH/8-1 downto 0);
O_WDATA : --! @brief OUTPUT REGISTER ACCESS WRITE DATA :
--! レジスタアクセスライトデータ.
out std_logic_vector(DATA_WIDTH -1 downto 0);
O_RDATA : --! @brief OUTPUT REGISTER ACCESS READ DATA :
--! レジスタアクセスリードデータ.
in std_logic_vector(DATA_WIDTH -1 downto 0);
O_ACK : --! @brief OUTPUT REGISTER ACCESS ACKNOWLEDGE :
--! レジスタアクセス応答信号.
in std_logic;
O_ERR : --! @brief OUTPUT REGISTER ACCESS ERROR ACKNOWLEDGE :
--! レジスタアクセスエラー応答信号.
in std_logic
);
end REGISTER_ACCESS_SYNCRONIZER;
-----------------------------------------------------------------------------------
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library PIPEWORK;
use PIPEWORK.COMPONENTS.SYNCRONIZER;
use PIPEWORK.COMPONENTS.SYNCRONIZER_INPUT_PENDING_REGISTER;
architecture RTL of REGISTER_ACCESS_SYNCRONIZER is
constant I2O_WDATA_LO : integer := 0;
constant I2O_WDATA_HI : integer := I2O_WDATA_LO + DATA_WIDTH - 1;
constant I2O_BEN_LO : integer := I2O_WDATA_HI + 1;
constant I2O_BEN_HI : integer := I2O_BEN_LO + DATA_WIDTH/8 - 1;
constant I2O_ADDR_LO : integer := I2O_BEN_HI + 1;
constant I2O_ADDR_HI : integer := I2O_ADDR_LO + ADDR_WIDTH - 1;
constant I2O_WRITE_POS : integer := I2O_ADDR_HI + 1;
constant I2O_BITS : integer := I2O_WRITE_POS - I2O_WDATA_LO + 1;
signal i2o_i_data : std_logic_vector(I2O_BITS-1 downto 0);
signal i2o_i_valid : std_logic;
signal i2o_i_ready : std_logic;
signal i2o_o_data : std_logic_vector(I2O_BITS-1 downto 0);
signal i2o_o_valid : std_logic;
signal o2i_i_rdata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal o2i_i_valid : std_logic_vector(1 downto 0);
signal o2i_i_ready : std_logic;
signal o2i_o_rdata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal o2i_o_valid : std_logic_vector(1 downto 0);
begin
-------------------------------------------------------------------------------
-- 入力側の制御回路
-------------------------------------------------------------------------------
I: block
type STATE_TYPE is (IDLE_STATE, REQ_STATE, RUN_STATE);
signal curr_state : STATE_TYPE;
signal next_state : STATE_TYPE;
begin
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
process (curr_state, I_REQ, I_SEL, i2o_i_ready, o2i_o_valid)
variable request : boolean;
variable acknowledge : boolean;
begin
request := (I_REQ = '1' and I_SEL = '1');
acknowledge := (o2i_o_valid(0) = '1' or o2i_o_valid(1) = '1');
case curr_state is
when IDLE_STATE =>
if (request = TRUE) then
if (acknowledge = TRUE) then
next_state <= IDLE_STATE;
elsif (i2o_i_ready = '1') then
next_state <= RUN_STATE;
else
next_state <= REQ_STATE;
end if;
i2o_i_valid <= '1';
else
next_state <= IDLE_STATE;
i2o_i_valid <= '0';
end if;
when REQ_STATE =>
if (acknowledge = TRUE) then
next_state <= IDLE_STATE;
elsif (i2o_i_ready = '1' ) then
next_state <= RUN_STATE;
else
next_state <= REQ_STATE;
end if;
i2o_i_valid <= '1';
when RUN_STATE =>
if (acknowledge = TRUE) then
next_state <= IDLE_STATE;
else
next_state <= RUN_STATE;
end if;
i2o_i_valid <= '0';
when others =>
next_state <= IDLE_STATE;
i2o_i_valid <= '0';
end case;
end process;
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
process (I_CLK, RST) begin
if (RST = '1') then
curr_state <= IDLE_STATE;
elsif (I_CLK'event and I_CLK = '1') then
if (I_CLR = '1') then
curr_state <= IDLE_STATE;
else
curr_state <= next_state;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
i2o_i_data(I2O_WDATA_HI downto I2O_WDATA_LO) <= I_WDATA;
i2o_i_data(I2O_BEN_HI downto I2O_BEN_LO ) <= I_BEN;
i2o_i_data(I2O_ADDR_HI downto I2O_ADDR_LO ) <= I_ADDR;
i2o_i_data(I2O_WRITE_POS ) <= I_WRITE;
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
I_RDATA <= o2i_o_rdata when (I_SEL = '1') else (others => '0');
I_ACK <= o2i_o_valid(0) when (I_SEL = '1') else '0';
I_ERR <= o2i_o_valid(1) when (I_SEL = '1') else '0';
end block;
-------------------------------------------------------------------------------
-- 入力側から出力側への同期回路
-------------------------------------------------------------------------------
I2O: SYNCRONIZER --
generic map ( --
DATA_BITS => I2O_BITS , --
VAL_BITS => 1 , --
I_CLK_RATE => I_CLK_RATE , --
O_CLK_RATE => O_CLK_RATE , --
I_CLK_FLOP => 1 , --
O_CLK_FLOP => 1 , --
I_CLK_FALL => 0 , --
O_CLK_FALL => 0 , --
O_CLK_REGS => O_CLK_REGS --
) --
port map ( --
RST => RST , -- In :
I_CLK => I_CLK , -- In :
I_CLR => I_CLR , -- In :
I_CKE => I_CKE , -- In :
I_DATA => i2o_i_data , -- In :
I_VAL(0) => i2o_i_valid , -- In :
I_RDY => i2o_i_ready , -- Out :
O_CLK => O_CLK , -- In :
O_CLR => O_CLR , -- In :
O_CKE => O_CKE , -- In :
O_DATA => i2o_o_data , -- Out :
O_VAL(0) => i2o_o_valid -- Out :
);
-------------------------------------------------------------------------------
-- 出力側から入力側への同期回路
-------------------------------------------------------------------------------
O2I: SYNCRONIZER --
generic map ( --
DATA_BITS => DATA_WIDTH , --
VAL_BITS => 2 , --
I_CLK_RATE => O_CLK_RATE , --
O_CLK_RATE => I_CLK_RATE , --
I_CLK_FLOP => 1 , --
O_CLK_FLOP => 1 , --
I_CLK_FALL => 0 , --
O_CLK_FALL => 0 , --
O_CLK_REGS => 0 --
) --
port map ( --
RST => RST , -- In :
I_CLK => O_CLK , -- In :
I_CLR => O_CLR , -- In :
I_CKE => O_CKE , -- In :
I_DATA => o2i_i_rdata , -- In :
I_VAL => o2i_i_valid , -- In :
I_RDY => o2i_i_ready , -- Out :
O_CLK => I_CLK , -- In :
O_CLR => I_CLR , -- In :
O_CKE => I_CKE , -- In :
O_DATA => o2i_o_rdata , -- Out :
O_VAL => o2i_o_valid -- Out :
);
-------------------------------------------------------------------------------
-- 出力側の制御回路
-------------------------------------------------------------------------------
O: block
constant pause : std_logic := '0';
signal req_pending : boolean;
signal req_valid : boolean;
signal req_ready : boolean;
begin
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
req_valid <= (req_pending = FALSE and i2o_o_valid = '1') or
(req_pending = TRUE );
req_ready <= (O_ACK = '1' or O_ERR = '1');
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
process (O_CLK, RST) begin
if (RST = '1') then
req_pending <= FALSE;
elsif (O_CLK'event and O_CLK = '1') then
if (O_CLR = '1') then
req_pending <= FALSE;
else
req_pending <= (req_valid and not req_ready);
end if;
end if;
end process;
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
O_REQ <= '1' when (req_valid) else '0';
O_WDATA <= i2o_o_data(I2O_WDATA_HI downto I2O_WDATA_LO);
O_BEN <= i2o_o_data(I2O_BEN_HI downto I2O_BEN_LO );
O_ADDR <= i2o_o_data(I2O_ADDR_HI downto I2O_ADDR_LO );
O_WRITE <= i2o_o_data(I2O_WRITE_POS );
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
ACK_REGS: SYNCRONIZER_INPUT_PENDING_REGISTER
generic map ( --
DATA_BITS => DATA_WIDTH , --
OPERATION => 0 --
) --
port map ( --
CLK => O_CLK , -- In :
RST => RST , -- In :
CLR => O_CLR , -- In :
I_DATA => O_RDATA , -- In :
I_VAL => O_ACK , -- In :
I_PAUSE => pause , -- In :
P_DATA => open , -- Out :
P_VAL => open , -- Out :
O_DATA => o2i_i_rdata , -- Out :
O_VAL => o2i_i_valid(0), -- Out :
O_RDY => o2i_i_ready -- In :
); --
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
ERR_REGS: SYNCRONIZER_INPUT_PENDING_REGISTER
generic map ( --
DATA_BITS => 1 , --
OPERATION => 1 --
) --
port map ( --
CLK => O_CLK , -- In :
RST => RST , -- In :
CLR => O_CLR , -- In :
I_DATA(0) => O_ERR , -- In :
I_VAL => O_ERR , -- In :
I_PAUSE => pause , -- In :
P_DATA => open , -- Out :
P_VAL => open , -- Out :
O_DATA => open , -- Out :
O_VAL => o2i_i_valid(1), -- Out :
O_RDY => o2i_i_ready -- In :
); --
end block;
end RTL;
|
<gh_stars>0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity register is
generic(
G_WIDTH : integer := 8
)
port(
clk_in : in std_logic;
d_in : in std_logic_vector(G_WIDTH-1 dowto 0);
d_out : out std_logic_vector(G_WIDTH-1 dowto 0);
);
end register;
architecture behavioural of register is
begin
main : process(clk_in) is
begin
if rising_edge(clk_in) then
d_out <= d_in;
end if;
end process main;
end behavioural;
|
CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity transmitmain is
Port ( clk : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
serial_out : out STD_LOGIC);
end transmitmain;
architecture Behavioral of transmitmain is
type s is (idle,start,data,stop);
signal st:s:=idle;
signal temp:std_logic_vector(7 downto 0);
signal temp2:std_logic;
begin
process(clk)
variable count : integer range 0 to 100 :=0;
variable data_bit : integer range 0 to 7 :=0;
begin
case st is
when idle=>
if rising_edge(clk) then
temp<=data_in;
count:=0;
data_bit:=0;
st<=start;
end if;
when start=>
temp2<='0';
if rising_edge(clk) then
count:=count+1;
end if;
if count=100 then
count:=0;
st<=data;
end if;
when data=>
temp2<=temp(data_bit);
if rising_edge(clk) then
count:=count+1;
end if;
if count=100 then
data_bit:=data_bit+1;
count:=0;
end if;
if data_bit=8 then
st<=stop;
else
st<=data;
end if;
when stop=>
temp2<='1';
if rising_edge(clk) then
count:=count+1;
end if;
if count=100 then
count:=0;
st<=idle;
end if;
when others => st<=idle;
end case;
end process;
serial_out<=temp2;
end Behavioral;
|
-------------------------------------------------------------------------------
-- Title : MDIO Support
-------------------------------------------------------------------------------
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description:
-- Execute sequence(s) of MDIO transaction(s). A list (array) of all possible
-- transaction sequences is passed in the MDIO_PROG_G generic. Individual (sub-)
-- sequences are separated by the asserted 'theLast' flag in the last instruction
-- of each individual sequence.
--
-- A typical MDIO_PROG_G is a concatenation of sequences:
--
-- constant MDIO_PROG_C : MdioProgramArray := ( SEQ_1_C & SEQ_2_C & SEQ_3_C );
--
-- where each sequence (SEQ_1_C, SEQ_2_C, ...) is itself a MdioProgramArray and
-- has in its last instruction the 'last' flag set. E.g.,:
--
-- constant SEQ_1_C : MdioProgramArray := (
-- mdioWriteInst( PHY, REG_0, DATA_0 );
-- mdioWriteInst( PHY, REG_1, DATA_2 );
-- mdioReadInst ( PHY, REG_2, true);
-- );
--
--
-- The user would then trigger execution of a particular sequence by
--
-- 1) setting 'pc' to the index of the starting position of the first instruction of
-- the desired sequence.
-- 2) asserting 'trg' high for one clock cycle.
--
-- The sequencer then executes all instructions up to (and including) the last one
-- of a sequence.
-- When done, 'don' is asserted for a single clk cycle.
-- When any read transaction completes 'rs' is asserted for one cycle and readback
-- data is presented at 'din' (valid while 'don' is asserted).
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC Firmware Standard Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library surf;
use surf.StdRtlPkg.all;
use surf.MdioPkg.all;
entity MdioSeqCore is
generic (
TPD_G : time := 1 ns;
-- half-period of MDC in clk cycles
DIV_G : natural range 1 to natural'high := 1;
-- see above...
MDIO_PROG_G : MdioProgramArray
);
port (
-- clock and reset
clk : in sl;
rst : in sl;
-- programming interface;
trg : in sl; -- assert trg for ONE clock
pc : in natural;
rs : out sl; -- read back data valid
din : out slv(15 downto 0); -- read back data - valid during 'rs'
don : out sl; -- program completed
-- MDIO interface
mdc : out sl;
mdo : out sl;
mdi : in sl
);
end entity MdioSeqCore;
architecture MdioSeqCoreImpl of MdioSeqCore is
type StateType is ( IDLE, TRIG, PROG );
type RegType is record
state : StateType;
inst : MdioInstType;
pc : natural;
trg : sl;
end record;
constant REG_INIT_C : RegType := (
state => IDLE,
inst => mdioReadInst(0,0,true),
pc => 0,
trg => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal oneDone : sl;
begin
don <= oneDone and r.inst.lst;
rs <= oneDone and r.inst.cmd.rdNotWr;
U_MdioCore : entity surf.MdioCore
generic map (
TPD_G => TPD_G,
DIV_G => DIV_G
)
port map (
clk => clk,
rst => rst,
trg => r.trg,
cmd => r.inst.cmd,
din => din,
don => oneDone,
mdc => mdc,
mdi => mdi,
mdo => mdo
);
COMB : process(r, trg, pc, oneDone)
variable v : RegType;
begin
v := r;
case (r.state) is
when IDLE =>
if ( trg /= '0' ) then
v.state := TRIG;
v.pc := pc;
end if;
when TRIG =>
v.trg := '1';
v.inst := MDIO_PROG_G( r.pc );
v.state := PROG;
when PROG =>
if ( oneDone /= '0' ) then
if ( r.inst.lst /= '0' ) then
v.state := IDLE;
else
v.pc := r.pc + 1;
v.state := TRIG;
end if;
end if;
v.trg := '0';
end case;
rin <= v;
end process COMB;
SEQ : process( clk )
begin
if ( rising_edge( clk ) ) then
if ( rst /= '0' ) then
r <= REG_INIT_C;
else
r <= rin after TPD_G;
end if;
end if;
end process SEQ;
end architecture MdioSeqCoreImpl;
|
-- args: --std=08 --ieee=synopsys
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.configure.all;
use work.constants.all;
use work.wire.all;
use work.functions.all;
use work.comp_wire.all;
use work.csr_wire.all;
use work.int_wire.all;
use work.fp_wire.all;
entity decode_stage is
port(
reset : in std_logic;
clock : in std_logic;
int_decode_i : out int_decode_in_type;
int_decode_o : in int_decode_out_type;
comp_decode_i : out comp_decode_in_type;
comp_decode_o : in comp_decode_out_type;
fp_dec_i : out fp_dec_in_type;
fp_dec_o : in fp_dec_out_type;
csr_eo : in csr_exception_out_type;
fpu_dec_o : in fpu_dec_out_type;
fpu_dec_i : out fpu_dec_in_type;
a : in decode_in_type;
d : in decode_in_type;
y : out decode_out_type;
q : out decode_out_type
);
end decode_stage;
architecture behavior of decode_stage is
signal r : decode_reg_type := init_decode_reg;
signal rin : decode_reg_type := init_decode_reg;
begin
combinational : process(a, d, r, int_decode_o, comp_decode_o, fp_dec_o, csr_eo, fpu_dec_o)
variable v : decode_reg_type;
begin
v := r;
v.fpu := '0';
v.fpu_op := init_fp_operation;
v.pc := d.f.pc;
v.instr := d.f.instr;
v.taken := d.f.taken;
v.exc := d.f.exc;
v.etval := d.f.etval;
v.ecause := d.f.ecause;
if (d.d.stall or d.e.stall or d.m.stall or d.w.stall) = '1' then
v := r;
end if;
if d.f.exc = '1' then
v.instr := nop;
end if;
v.inc := "100";
if and_reduce(v.instr(1 downto 0)) = '0' then
v.inc := "010";
end if;
v.npc := std_logic_vector(unsigned(v.pc) + v.inc);
v.stall := '0';
v.clear := csr_eo.exc or csr_eo.mret or d.w.clear;
if d.e.jump = '1' and d.f.taken = '0' then
v.clear := '1';
elsif d.e.jump = '0' and d.f.taken = '1' then
v.clear := '1';
elsif d.e.jump = '1' and d.f.taken = '1' and or_reduce(d.e.address xor d.f.pc) = '1' then
v.clear := '1';
end if;
v.opcode := v.instr(6 downto 0);
v.funct3 := v.instr(14 downto 12);
v.funct7 := v.instr(31 downto 25);
v.fmt := v.instr(26 downto 25);
v.rm := v.instr(14 downto 12);
v.raddr1 := v.instr(19 downto 15);
v.raddr2 := v.instr(24 downto 20);
v.raddr3 := v.instr(31 downto 27);
v.waddr := v.instr(11 downto 7);
v.caddr := v.instr(31 downto 20);
v.csr_mode := v.instr(29 downto 28);
int_decode_i.instr <= v.instr;
v.imm := int_decode_o.imm;
v.int_rden1 := int_decode_o.int_rden1;
v.int_rden2 := int_decode_o.int_rden2;
v.int_wren := int_decode_o.int_wren;
v.csr_rden := int_decode_o.csr_rden;
v.csr_wren := int_decode_o.csr_wren;
v.load := int_decode_o.load;
v.store := int_decode_o.store;
v.int := int_decode_o.int;
v.int_op := int_decode_o.int_op;
v.load_op := int_decode_o.load_op;
v.store_op := int_decode_o.store_op;
v.csr := int_decode_o.csr;
v.ecall := int_decode_o.ecall;
v.ebreak := int_decode_o.ebreak;
v.mret := int_decode_o.mret;
v.wfi := int_decode_o.wfi;
v.fence := int_decode_o.fence;
v.valid := int_decode_o.valid;
v.fpu_rden1 := '0';
v.fpu_rden2 := '0';
v.fpu_rden3 := '0';
v.fpu_wren := '0';
v.fpu_load := '0';
v.fpu_store := '0';
v.fpu := '0';
v.fpu_op := init_fp_operation;
comp_decode_i.instr <= v.instr;
if comp_decode_o.valid = '1' then
v.imm := comp_decode_o.imm;
v.raddr1 := comp_decode_o.raddr1;
v.raddr2 := comp_decode_o.raddr2;
v.waddr := comp_decode_o.waddr;
v.int_rden1 := comp_decode_o.int_rden1;
v.int_rden2 := comp_decode_o.int_rden2;
v.int_wren := comp_decode_o.int_wren;
v.fpu_rden2 := comp_decode_o.fpu_rden2;
v.fpu_wren := comp_decode_o.fpu_wren;
v.load := comp_decode_o.load;
v.store := comp_decode_o.store;
v.int := comp_decode_o.int;
v.fpu := comp_decode_o.fpu;
v.csr := comp_decode_o.csr;
v.ebreak := comp_decode_o.ebreak;
v.int_op := comp_decode_o.int_op;
v.load_op := comp_decode_o.load_op;
v.store_op := comp_decode_o.store_op;
v.valid := comp_decode_o.valid;
end if;
v.comp := comp_decode_o.valid;
fp_dec_i.instr <= v.instr;
if fp_dec_o.valid = '1' then
v.imm := fp_dec_o.imm;
v.int_rden1 := fp_dec_o.int_rden1;
v.int_wren := fp_dec_o.int_wren;
v.fpu_rden1 := fp_dec_o.fpu_rden1;
v.fpu_rden2 := fp_dec_o.fpu_rden2;
v.fpu_rden3 := fp_dec_o.fpu_rden3;
v.fpu_wren := fp_dec_o.fpu_wren;
v.fpu_load := fp_dec_o.fpu_load;
v.fpu_store := fp_dec_o.fpu_store;
v.fpu := fp_dec_o.fpu;
v.fpu_op := fp_dec_o.fpu_op;
v.load_op := fp_dec_o.load_op;
v.store_op := fp_dec_o.store_op;
v.valid := fp_dec_o.valid;
end if;
if csr_eo.fs = "00" then
v.fpu_wren := '0';
v.fpu_load := '0';
v.fpu_store := '0';
end if;
fpu_dec_i.instr <= v.instr;
fpu_dec_i.rden1 <= v.fpu_rden1;
fpu_dec_i.rden2 <= v.fpu_rden2;
fpu_dec_i.rden3 <= v.fpu_rden3;
fpu_dec_i.wren <= v.fpu_wren;
fpu_dec_i.load <= v.fpu_load;
fpu_dec_i.op <= v.fpu_op;
fpu_dec_i.frm <= csr_eo.frm;
v.link_waddr := (v.waddr = "00001") or (v.waddr = "00101");
v.link_raddr1 := (v.raddr1 = "00001") or (v.raddr1 = "00101");
v.raddr1_eq_waddr := v.raddr1 = v.waddr;
v.zero_waddr := (v.waddr = "00000");
if v.waddr = "00000" then
v.int_wren := '0';
end if;
v.return_pop := '0';
v.return_push := '0';
v.jump_uncond := '0';
v.jump_rest := '0';
if v.int_op.jal ='1' then
if v.link_waddr then
v.return_push := '1';
elsif v.zero_waddr then
v.jump_uncond := '1';
else
v.jump_rest := '1';
end if;
end if;
if v.int_op.jalr ='1' then
if not(v.link_waddr) and v.link_raddr1 then
v.return_pop := '1';
elsif v.link_waddr and not(v.link_raddr1) then
v.return_push := '1';
elsif v.link_waddr and v.link_raddr1 then
if v.raddr1_eq_waddr then
v.return_push := '1';
elsif not(v.raddr1_eq_waddr) then
v.return_pop := '1';
v.return_push := '1';
end if;
else
v.jump_rest := '1';
end if;
end if;
if v.int_op.jal = '1' then
end if;
if v.exc = '0' then
if v.valid = '0' then
v.exc := '1';
v.etval := X"00000000" & v.instr;
v.ecause := except_illegal_instruction;
elsif v.ecall = '1' then
v.exc := '1';
if csr_eo.priv_mode = u_mode then
v.ecause := except_env_call_user;
elsif csr_eo.priv_mode = m_mode then
v.ecause := except_env_call_mach;
end if;
elsif v.ebreak = '1' then
v.exc := '1';
v.ecause := except_breakpoint;
elsif v.csr = '1' then
if unsigned(v.csr_mode) > unsigned(csr_eo.priv_mode) then
v.exc := '1';
v.etval := X"00000000" & v.instr;
v.ecause := except_illegal_instruction;
end if;
end if;
end if;
case v.funct3 is
when "001" | "101" =>
v.csr_rden := v.csr_rden and (or_reduce(v.waddr));
when "010" | "110" =>
v.csr_wren := v.csr_wren and (or_reduce(v.raddr1));
when "011" | "111" =>
v.csr_wren := v.csr_wren and (or_reduce(v.raddr1));
when others => null;
end case;
if (d.d.csr_wren or d.e.csr_wren) = '1' then
v.stall := '1';
elsif (d.d.load) = '1' then
if (nor_reduce(d.d.waddr xor v.raddr1) and ((d.d.int_wren and v.int_rden1))) = '1' then
v.stall := '1';
end if;
if (nor_reduce(d.d.waddr xor v.raddr2) and ((d.d.int_wren and v.int_rden2))) = '1' then
v.stall := '1';
end if;
elsif (v.csr_rden) = '1' then
if (nor_reduce(v.caddr xor csr_fflags) and (d.d.fpu or d.e.fpu)) = '1' then
v.stall := '1';
end if;
elsif (d.d.int_op.mcycle) = '1' then
v.stall := '1';
end if;
if (d.m.stall or d.w.stall) = '1' then
if d.e.load = '1' then
if (nor_reduce(d.e.waddr xor d.d.raddr1) and ((d.e.int_wren and d.d.int_rden1))) = '1' then
v.stall := '1';
end if;
if (nor_reduce(d.e.waddr xor d.d.raddr2) and ((d.e.int_wren and d.d.int_rden2))) = '1' then
v.stall := '1';
end if;
end if;
end if;
fpu_dec_i.stall <= v.stall;
fpu_dec_i.clear <= v.clear;
if (fpu_dec_o.stall) = '1' then
v.stall := '1';
end if;
if (v.stall or v.clear) = '1' then
v.int_wren := '0';
v.fpu_wren := '0';
v.csr_wren := '0';
v.int := '0';
v.fpu := '0';
v.csr := '0';
v.comp := '0';
v.int_op := init_int_operation;
v.fpu_op := init_fp_operation;
v.return_pop := '0';
v.return_push := '0';
v.jump_uncond := '0';
v.jump_rest := '0';
v.load := '0';
v.store := '0';
v.fpu_load := '0';
v.fpu_store := '0';
v.taken := '0';
v.exc := '0';
v.mret := '0';
v.fence := '0';
v.valid := '0';
end if;
if v.clear = '1' then
v.stall := '0';
end if;
rin <= v;
y.pc <= v.pc;
y.npc <= v.npc;
y.funct3 <= v.funct3;
y.funct7 <= v.funct7;
y.fmt <= v.fmt;
y.rm <= v.rm;
y.imm <= v.imm;
y.int_rden1 <= v.int_rden1;
y.int_rden2 <= v.int_rden2;
y.csr_rden <= v.csr_rden;
y.int_wren <= v.int_wren;
y.fpu_wren <= v.fpu_wren;
y.csr_wren <= v.csr_wren;
y.raddr1 <= v.raddr1;
y.raddr2 <= v.raddr2;
y.raddr3 <= v.raddr3;
y.waddr <= v.waddr;
y.caddr <= v.caddr;
y.load <= v.load;
y.store <= v.store;
y.fpu_load <= v.fpu_load;
y.fpu_store <= v.fpu_store;
y.int <= v.int;
y.fpu <= v.fpu;
y.csr <= v.csr;
y.comp <= v.comp;
y.load_op <= v.load_op;
y.store_op <= v.store_op;
y.int_op <= v.int_op;
y.fpu_op <= v.fpu_op;
y.return_pop <= v.return_pop;
y.return_push <= v.return_push;
y.jump_uncond <= v.jump_uncond;
y.jump_rest <= v.jump_rest;
y.taken <= v.taken;
y.etval <= v.etval;
y.ecause <= v.ecause;
y.exc <= v.exc;
y.ecall <= v.ecall;
y.ebreak <= v.ebreak;
y.mret <= v.mret;
y.wfi <= v.wfi;
y.fence <= v.fence;
y.valid <= v.valid;
y.stall <= v.stall;
y.clear <= v.clear;
q.pc <= r.pc;
q.npc <= r.npc;
q.funct3 <= r.funct3;
q.funct7 <= r.funct7;
q.fmt <= r.fmt;
q.rm <= r.rm;
q.imm <= r.imm;
q.int_rden1 <= r.int_rden1;
q.int_rden2 <= r.int_rden2;
q.csr_rden <= r.csr_rden;
q.int_wren <= r.int_wren;
q.fpu_wren <= r.fpu_wren;
q.csr_wren <= r.csr_wren;
q.raddr1 <= r.raddr1;
q.raddr2 <= r.raddr2;
q.raddr3 <= r.raddr3;
q.waddr <= r.waddr;
q.caddr <= r.caddr;
q.load <= r.load;
q.store <= r.store;
q.fpu_load <= r.fpu_load;
q.fpu_store <= r.fpu_store;
q.int <= r.int;
q.fpu <= r.fpu;
q.csr <= r.csr;
q.comp <= r.comp;
q.load_op <= r.load_op;
q.store_op <= r.store_op;
q.int_op <= r.int_op;
q.fpu_op <= r.fpu_op;
q.return_pop <= r.return_pop;
q.return_push <= r.return_push;
q.jump_uncond <= r.jump_uncond;
q.jump_rest <= r.jump_rest;
q.taken <= r.taken;
q.etval <= r.etval;
q.ecause <= r.ecause;
q.exc <= r.exc;
q.ecall <= r.ecall;
q.ebreak <= r.ebreak;
q.mret <= r.mret;
q.wfi <= r.wfi;
q.fence <= r.fence;
q.valid <= r.valid;
q.stall <= r.stall;
q.clear <= r.clear;
end process;
process(clock)
begin
if rising_edge(clock) then
if reset = '0' then
r <= init_decode_reg;
else
r <= rin;
end if;
end if;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:01:44 10/22/2017
-- Design Name:
-- Module Name: SEU_CALL_MODULE - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SEU_CALL_MODULE is
Port ( DISP30 : in STD_LOGIC_VECTOR (29 downto 0);
SDISP30 : out STD_LOGIC_VECTOR (31 downto 0));
end SEU_CALL_MODULE;
ARCHITECTURE SEU OF SEU_CALL_MODULE IS
BEGIN
PROCESS(DISP30)
BEGIN
CASE DISP30(29) IS
WHEN '0' => SDISP30 <= STD_LOGIC_VECTOR("00000000000000000000000000000000"+DISP30);
WHEN OTHERS => SDISP30 <= STD_LOGIC_VECTOR("11000000000000000000000000000000"+DISP30);
END CASE;
END PROCESS;
END SEU;
|
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity MISR_tb is
end;
architecture bench of MISR_tb is
constant X : integer := 16;
component MISR
generic (X: integer := 16);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
mac_out : in STD_LOGIC_VECTOR ((2*X)-1 downto 0);
signature : out STD_LOGIC_VECTOR ((2*X)-1 downto 0)
);
end component;
signal clk: STD_LOGIC;
signal rst: STD_LOGIC;
signal enable: STD_LOGIC;
signal mac_out: STD_LOGIC_VECTOR ((2*X)-1 downto 0);
signal signature: STD_LOGIC_VECTOR ((2*X)-1 downto 0) ;
constant clock_period: time := 10 ns;
signal stop_the_clock: boolean;
begin
-- Insert values for generic parameters !!
uut: MISR generic map ( X => 16)
port map ( clk => clk,
rst => rst,
enable => enable,
mac_out => mac_out,
signature => signature );
stimulus: process
begin
-- Put initialisation code here
enable <= '1';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
mac_out <= X"00000001";
wait for clock_period;
mac_out <= X"00000002";
wait for clock_period;
mac_out <= X"00000002";
wait for clock_period;
mac_out <= X"00000003";
-- Put test bench stimulus code here
wait;
end process;
clocking: process
begin
while not stop_the_clock loop
clk <= '0', '1' after clock_period / 2;
wait for clock_period;
end loop;
wait;
end process;
end;
|
-- safe_path for CosPiDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosPiDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosPiDPStratixVf400_safe_path;
PACKAGE body CosPiDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosPiDPStratixVf400_safe_path;
|
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity gf_inv is
port ( a_in : std_logic_vector (3 downto 0);
d : out std_logic_vector (3 downto 0));
end gf_inv;
-- Architecture of the Component
architecture a_gf_inv of gf_inv is
begin
process (a_in)
begin
case a_in is
when "0000" => d <= "0000";
when "0001" => d <= "0001";
when "0010" => d <= "1001";
when "0011" => d <= "1110";
when "0100" => d <= "1101";
when "0101" => d <= "1011";
when "0110" => d <= "0111";
when "0111" => d <= "0110";
when "1000" => d <= "1111";
when "1001" => d <= "0010";
when "1010" => d <= "1100";
when "1011" => d <= "0101";
when "1100" => d <= "1010";
when "1101" => d <= "0100";
when "1110" => d <= "0011";
when "1111" => d <= "1000";
when others => null;
end case;
end process;
end a_gf_inv;
|
-------------------------------------------------------------------------------
-- Model: capacitor
--
-- Author: <NAME>, LMGT, TU Chemnitz
-- <<EMAIL>>
--
-- Date: 21.06.2011
-- Library: kvl in hAMSter
-------------------------------------------------------------------------------
-- ID: capacitor.vhd
-- Rev. 1.0
-------------------------------------------------------------------------------
use work.electromagnetic_system.all;
use work.all;
library ieee;
entity capacitor is
generic (capacitance:real); -- capacitance value
port (terminal p,n:electrical); -- interface ports
end entity capacitor;
architecture basic of capacitor is
quantity v across i through p to n;
begin
i == capacitance*v'dot;
end architecture basic;
|
<reponame>justingallagher/fpga-trace
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
<KEY>
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect key_keyowner = "Synopsys", key_keyname= "<KEY>", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
K3+UOwlCwx3t7FyQuvXVOuOLSf79w8H29kYesB4t4ENU7w/cJ+3jINJp3g7+Mw/l3pow2eggqoBf
<KEY>
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
<KEY>
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5296)
`protect data_block
elC6rN01XHSEyfPLJwYgOlN9xTU9oLsjci8OS4jAxO+wXMQUq6IC/kTkez/R1+yG72uNjSe4P/Tg
fVe+8Eu7QpAk6j7PAM1RO5igJ04V8PsaeYRghFkvTBTs/7gEi94VfM1TlNBJJHahzkdbpCqaGEGi
u2RghreMqupRP/Upi5o8OZ5XU8UXbYqF/MzG5J+P/lY0U5Uew71+hajiovME4Y3HqZRytrLpTPqT
EiUnKkKulcIkiBIg3M8A1QhQJObXH0oABEUMLNBAddXOeyH5Oalq+gexHdGdF2oQAdyk8oN9c5kD
y7C/7q9aN0pOek6xYfNveviTfCACAsl7kh5eE8CffLiJE232cwvNuXUB2VJwNu/dgkcf9Btyu1a8
muj3xgcrGEgIipqjsuNlpCgFz94g4HYLFFl7SL04b9WWEEAGmQYs4hPGiAznHlTdHD+Ue7qzBN8+
kKCKQSTHcC0OKkHBWbYV8JdQeZHHOAaHDbpIURi6gG8MdBIr4m3eqUTwUYtl81MqnpCEZWXbLz1c
+J698tjoZ1qaaZVPIu16l6NBhuzt7z/WvlIEXPi7l8meUEdHJ8DQroXg0RUx3xtARHPDOMcU1mIQ
E0c8KzOuSFmsX7p9/y/yHdYKPgQJPAZdZLo0aMxPLIlCULn9/iSY+9B6upcqWurdYEukb/U1cFj5
2cgDYJOuZEm5RGYtvlodP9LSA3tmon+2Fsg3YyO6JOz74GHeKYg+suEwmRZrwzyucWOetV6P9Ih8
NTFBF/0UXA9e7xUEfBjFFTxyi+6TtCZa/jZqe2Y7WLpfXTjCHq83G5Tv08xOveGD0IVPy5Dm3w0g
dsul24Q8oWkHvQNMn+6OuoG2HrVkZqeOSuDlVhwSHk0iWNHdxEhadixL5c5EajKHSqzR0Ok2xfYO
1SziVwk6ouHtMAR7RGSV4J+OCyNC3hBw/N+vNSromflAPUTBX8sTyK9mxE0lMdgXPjQ/bJo/lh5l
Wn/siQeFSA5pujjs2pZ7GDmdpdMpdLvaiCLUrjHCUcUwccxNds8pzYnqSJjiNgkaifQEBxFe5sB4
CRZK/WJr9lGySgPLc4WMUOPIJNuZfRx4UrRPbXxxNuF7UJuAzQ3MK9XFMo5lHIkpD46050ixCgkN
1AGDVg6xlipPF853yYLktjPkG2ZGLec6uaRZfwRZSqzbCk4PRK8KviHkRtupy/Fs4WE3KjUv6xIh
JupkDDkjTMOm/TnmB6O4F2xdumfMgq1eb/uOfXltgeqjMPq+RPl8l2PhmeJbyjaZstxoaxHVOaY6
Xnrcg+iZa6gF4+Qw+HUNapnqsqI8kxBg7DV0tRo7rkrav630iR8J2KsmSj9GYsziNbFHOM53d/o/
9QtrN0aeuasrs/RRHFFwPpZeIeePbpZx8lhH3gBa/U9xZp30tUX9+bdr94YcoMvGgT2eRU9LManJ
qVotozwW4Lu4XR1IU9auroSlanx7oFAwBnjiqablXOahXRYsjAYaqeQBTM5p9DTOW3uesflCYJ1x
KCGg00t8iNLQqgDnKIxfUD24jQHHNlpcA16qJxQrOirxPUXMCdSrA4DvBJ/ktPW1GfH9lV4dDdJc
qtSLJV1qNW17XomZAQ0b+0WUHSPu5ygUajaoRnDdJCcgaGVXSJt0OFSsYfHSyL8D4+r/Z+iDJgsH
plUuN+3Rs2g4TUl5RlmF21BK9HxWpqZjxWYeJsy+IsUl682UciLxm6lS+YQbHpNs23S/HSsS/Req
iwjzGRotnQlNzvmtsLY7nK/fobvRpZ7X4LAqaEPTmV0uo92jOeCeKDh0Sc06bncHY9z7xIY+Dz8u
YbaV5Gnv/vTz0ghirL3RuIyISS/EDWkNHjaablKZthB6vwVAhA/tp/hBUPLn24dop10CtmEt05np
xNRludjelnINrBfljVuPkIvquuXNJ8I0hartJ4hMn5fUWne3K2lmYQVe/bGjQDrU5JNsgLh0OS89
fN3L/Jjk8b8RH6tifI4obWelSDvZmfygD6/N4vpdI/tdkXu54hI6P3VV8BwB2vlIwI9xGVMtDYrP
rkz7MvFh6R6MPEseLzTLywi3SjKSS877dHXbCZYfD7ya2aHhtpa3oemU0LyW3n87ekFfqwehG+/q
xzQG1pfPWsD9FSMwgn9UrI3kwprI+tqojQrnegr1CoDWCeTn7CLjOsWMqcIGIlMTsT2S79Jqqqoh
3rJOY1CgrU1K8f1e7wJx8d5vXlGRli3CkUjl9PE23qWAIzqdBH22/MCWGQIU6h3xlga2bs4hntSe
urCO8BFznNLSc/TgR2aX9XZt5vealcL9aVixWiyZND/gcS/Ap4Ke++K9A2EiDFtqnOtIZcCmUlLX
Rcctl+mFy/M3xvC9g3cR4vyBD4HDnv9aSssKr+uwYB/+ude8xhwB7B8SEGpQaAwO35Q9OmXfYMsc
qk68rVCicCIbyNzVKbYX3xVtairqAgkGuKwAmE45ZrWXDOH3y4YdxLUIMpze7u0+DDTyMQv71WtR
OwW1nJ4Tytg+cBHlgBXExx6yoN8kqgv12/xSab2jNYHyt8RfW6aoj6o7UpVUKKXSl8ZYnS1pVh8m
p9uVU2ll5BtPRe/oj7jLmiZu9eD6a/BI0p6girc1o1L8WHtu0miSZZamkdsGR2OMcLdyqxeLECMt
yK5VZt/tF8mFJ9xG4cZasSx9h7OPHq+bRfxnDA8dMiFne8XMP417nFwG+5JCwkXA6Bfkgcq4/aei
iwH6brOw4//8cQPrnBxt0D5l5Eh/vfKSffGQH8CEB/F70yf01mTCZyh6gr+wSpsqVr7Xe4kwlGoU
3bmzBRw4xP5Ns0vD5DJVt8eCYYeBuqaHzn0vI7gW38ANLCZB/fpGVtxH8YbDKBNOPrA6CpMLJZ2h
vic2pugvXkZ0/XVxiW4OJ1X/fCHfu9QOA34/CnVPzcc75xWvhoE9LEkKgZJ99EGIdpa/+hu4WNdj
KJwkM/1oBnt8oUgAY4bgDL1J+XaOYRP5RlmVceBYFP7RpmND2PSdCnfcIjgN57L5uREsgwOW/QJV
Rx+fH9uUS99JDJvaVwSrcm8wKOwIbvaFu+Ua9vEM9Wzq1XcUo51uSf3qBq57KF7OYigtj1PYSyQo
n4Ra051pTJmADImWcioHQDdNezNugK6easZFDo03ByfFckl+vnxYXCY3zwAlst4IpOMUgHaD9KxS
0ZSQUz9rNtEk4QF4kkg4H7+WL4+x/cDYGof+xbLTREIWfQtrJoclodUQ9LnuS5D86Thnm8kHjKuG
iPN2CiUhzQmEqZjbvoSe1asbyXCwULGfIGma6t70EXf8QBFPjrVdCfcDDu2sPJcfNLd2+ciqpqel
LjLjOltzEvDBGWjtnzNdufhj7gYfrvjUbuliIhmubz+JpMK7bKL1ouvR10le5+nFgGn572UJLlIe
crPaUg5cIY2Atf0J0j+z5B5W61N35s6108bbzyifCNv3VP0G7t+R9iPMriR/+Nkr0Aj3fMpBG5eM
fnqBiHob8G5fFzfbXbb1/ZuQ5XDOjb99AmjeWJChZnZw4he2V+Vw2fuEmZUqqvY+nJS3JHdWj6D9
cIImegpO3SQbskW8ENTqZibl7Bg0RBuLrMC7ozBp61XGUzdk6OTyEC2JRv3COV1GLa31BJ4kru8m
ozoZEoverkoADnX2Gd5tEfBvYg7hqDpkzf48O1KdbSH6Evx8E80WX3PAKMjTRTizRl+UlNX+HKNA
wc1SZMmWdmJ7+6qNltvCSH3zTvr+LPxzlABMuXs4XzceMHNTpTHF56PDqvbS+YDQRwzOxFynhejJ
zbWRBtuUTqjJK+l+giTZHZW+yM1lscIiEU9Tp4x5oBFN0N5DcxqQJvIQPOB7Cc3D81KrDb82nXYi
DaSqZmmmC2bkILREPdSu1ocUb8afGPLsXHAfLw4o5sDWww0FPF2RRUu56Bd6TlF+BJjABjK6ZWhx
Ck1omqPeovauTnFdwE0L2TZBL5SEASDc35LNExLuJ1ipG5SfXeFwagiPXbwceKMrkziCuABAme4s
2MLV5SMsTUsk4vm72hQhPBP2w/OTUhzEqbdWeHePLwr97k/87AXrO3Eq7pv8hPWyEEdLjUbfolLK
kxVdW8pyueSpGRxkFgxfS38MGqen0b3AQgB/WKvzqnVIn7gcruvjnOMB+RexqdgF8HX9JJhw/ryM
srl6PZ/hByOkSBlAVVq8QDAKvqKX2MgAhq8zVHkY20E+ycqceCqssxF2nGJ81RhYb0inFdWZk0BV
+aWaTzC+7kR2WkvVh2LTrJMOugH3TJ6kN1DLCSBSWFWyrLJdZnYr8B7E1upb+z2r8S496PLOEmxi
t7A877sqPmmmum34WMfceRaoqyPy8OQZ5oBxImbvbwPJTpV4IyBlMor0WTT/Pmd+wOsSw33LQIWV
OyTC+oJrYBrYfD10d9v0iKLUINSKiFx38+HraC8TIDv3Q/rU0EqyRMZPLrW2EIR5VoCQ3MM6bbvM
sk5hkIUMhN5kqIRRzdW23MAx6MwTtWS5WWKNecDixaHDCi6M1e92getYryHKL6df1qD3q5dq1eQO
bVgLUXDDf/EVdOyUKXaZTpeWUDzkRpX4qf93P773XQz95Ljyg8Io10XShUoeBKE18ZNKt9JYvsRu
dzEiBHQwRI+4QtlH2X1eORSxklvWgvep+hUwymT1c0WCawuiG0DkfOQs9kPKhwCmm7g4J80TfyaT
6Ukl9hUb67uxztk1w6JtoQDVZPxRmKislwbIYOD2zvK3jBbUeugk5iJG9As41tm6z2Br/p2YwUvv
ZXjpeRGvd54WIIoYA9F8gWL7rR7nUb5BWfbjXslaraot/SA3xrtkCo3/D3OGlvpiUFC3NViql0R3
h0Drjyco6WKefWdqVT7nWq0PJklSoLidpkZBG9mdtz5p3j5SpxZ/tPCw58nyvo0hcF9XhkY6WIjs
Vb1OQL9mmPaCkPIBUEdjVT1ezVZ8bvylucIk6Kd35xQ7I+n4CdmiKc4D8pB2MGU0b0JsLsr/mT8D
Gw5rgnYiFh4JhOVcvascwgiHmA8Y1T1zByJyhg74zsvHCPFM7Z/KMpZlSl7RL1poTpw0GHPpPd7H
BK3SxlsK1GndcqHjst7GVFfutM3RUHRwTFO1Wj/CDaaHDSCAzhlhXd0nFnWCa/498VCuiSjXT75C
AbJ754Ot6rdPjj5TRpc/fDSyWbOc0Xi5rXcLcRH4z5omWeZGM6IstMjWyqirqhe3Vk8dZId3rls4
3r7MqfXskUEaOzFV0ua6g1pLHeTUwDkPkZpmCMTih9ZZe0fDG2uf0Vfn6XxXsPGCtlFKE/g2MYNN
wConiQhvmeOR+HqWbM7GTXhSpBukxhQqx5luskz8VlsQrDg0lOr7G1RHveZdiGjpr6RFCe7D3aAq
9arT7E38SV2OSJ9i/V1lr6vdb4B0COCODo9UBXMerzyV1KFj1YtM+uJ6JsO0VD+AqvVH0YGwBL1/
2nEvkd5YeMN94JjEEHey+6zckKN/3ld0S3WIrzb159KO0CC17rE+2RaO/7Q6Rewfz11Hp9bvou5P
Ht+tfyj1v4uU3x0QGy+Lk4eK33rY63qJ28EVcqFsaZkxRdS6Uv6DQ7oJuT64IgovWTgwelpeRCjn
Dlq5AGS1tCMF1rJGLDbah9Yub3rhJj9QffxguH/+MavYqI0Sf5hYTiWqWIW9TXsyMdJIgL1UtJqH
YfxckxLOH9kuWuHhYPhPPlfAmZL2fJ9Zir9uD+Re+mX48m7aU7PLUb6sTj+8YHVGfKOSypxkL1+0
rVpLVUmB4TbLRVO8RofmbgUUwL7qUxQcXAZwhTljV2KR9k4LbzYE8vLZ93TwKLHMPqSgkiazKz+J
51ng8TizSrG37sZ/r04qe7/zEbWhsf2H4N7gAu/NFtHIf5nLRySWXL+5MllBcyewdRdNiXYwS2hn
rAOONZ5jHQRt6MK35DA3laWoi7W8WK1bId7WpHg9CGZYsg+fx7FmYLCEpWKirrxVKkR/RybdOkXA
iQ+gTYuGsEr/ldV29ScTBIEZhaQdJNUpT6gFYy5kaxhWyfYnSu277watgCiCykSMncBb6FWjexcT
HhraGkSswmnqt4fg7NBlnz2FWKpvRkbIJepAxL0llnXtlMiSiYvu2Zf1doH6ZfZavVfOpX8o66Df
sAcTwtfXWH4y6HcKvQ+5+ppiKRHMVbJdMlJE1A8+a9cTmf6v+YjMF0iuOtDPZtRAAL9ZXtQOY1TB
ggFEyKPwDIu/D0Pr65ayfelXiNWLONmFnFN4autHDmzLx21hETXZkFZJu9biOYldrBTiHbUqFaee
P5KyHGbIaIJ1HmV5zmMZpPVgwAQqpp/PBneD+dmFOJxa/SsgMnCwY0DT6kdJAvKTIVAt3/tthBqk
qATDibie2j1lHINXQBm8G+R0BmUHjcelRwmNd2Xl9gw9M6nZaiHgtwfoufAE78xobBj3ShVHJJPS
qed4fmkULBNDu/CUI/b8yt9ZLEza3TbHg+OPlVIHHfYdfhyjsbPCS6aIk+P14qq30+sNpRLoUr8G
GVRblt6FeFDRQ2Lfx/hDB/MY99eg0Z78tVv9U+TknT2mfOkzcShPwlV2Tn29PRtJaL9KqLv2R2Fd
jUHKIEw7D0Fz4VZGfl/grKVATMBc1GSQYCf4mgA/15zfbfqxUDRlh2QvHE01CkcShzZDYIj8n5/r
TSAKVVxe5l6W8z2nTpcFASuQOhanH7MW3HkB5MveZhObX4zZKOn7wq0xpL6Zs2sYY0mzynvia6rS
Sm+4huR0Hw3T/rO9t6ROgU73Tnn725C8YeF8Lu0/AHn6C1xteLRiy7JhPcWMxwodBQxFHarO1Un+
aIe1NODnxz4VcQTeDkoUbTrszsaJK2cTY8JHSmyQrH/HhJrthC/fXgzmhC4aJreu7UI/aDx00XI2
OYcBksmzEtgm81KrEU3Gmq/6b7Tj2j3hwHlmujjPhiRu1LBNsqH82Nb2aiUwggymEHaib16xYX5D
1NLLpM8/ZRBsqC+QRKwcLCBy+kafgbnEeKXdI7wERXX2aroZHlM/zj0SuFTe9S095frUaA==
`protect end_protected
|
<reponame>andrewparlane/masters_uba<gh_stars>0
-- preuba parar flipFlopN_srst
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flipFlopN_srst_tb is
end entity flipFlopN_srst_tb;
architecture synth of flipFlopN_srst_tb is
component flipFlopN_srst
generic (WIDTH: integer);
port (clk: in std_ulogic;
d: in std_ulogic_vector((WIDTH - 1) downto 0);
en: in std_ulogic;
srst: in std_ulogic;
q: out std_ulogic_vector((WIDTH - 1) downto 0));
end component flipFlopN_srst;
constant WIDTH: integer := 4;
signal clk: std_ulogic := '0';
signal en, srst: std_ulogic;
signal d, q, expectedQ: std_ulogic_vector((WIDTH - 1) downto 0);
begin
-- clk period = 100ns
clk <= not clk after 50 ns;
dut: flipFlopN_srst generic map (WIDTH => WIDTH)
port map (clk => clk,
d => d,
en => en,
srst => srst,
q => q);
-- comprobación
process
begin
wait for 51 ns;
loop
assert (q = expectedQ)
report "q = " & integer'image(to_integer(unsigned(q))) &
" esperado " & integer'image(to_integer(unsigned(expectedQ)))
severity error;
wait for 100 ns;
end loop;
end process;
-- codigo de preuba
process
begin
srst <= '1';
en <= '1';
d <= "1111";
expectedQ <= "0000";
wait for 500 ns;
srst <= '0';
expectedQ <= d;
wait for 500 ns;
en <= '0';
wait for 500 ns;
d <= "0000";
wait for 500 ns;
en <= '1';
expectedQ <= d;
wait for 500 ns;
en <= '0';
wait for 500 ns;
d <= "0101";
wait for 500 ns;
en <= '1';
expectedQ <= d;
wait for 500 ns;
srst <= '1';
expectedQ <= "0000";
wait for 500 ns;
srst <= '0';
expectedQ <= d;
wait for 500 ns;
std.env.stop;
end process;
end architecture synth;
|
<filename>cont_sinc_package.vhdl
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY work;
USE work.ffjk_package.all;
ENTITY cont_sinc_mod6 IS
PORT(entrada, clr, clk : IN BIT;
q, qbar : BUFFER BIT_VECTOR (2 DOWNTO 0));
END cont_sinc_mod6;
USE work.ffjk_package.all;
ENTITY cont_sinc_mod10 IS
PORT(entrada, clr, clk : IN BIT;
q, qbar : BUFFER BIT_VECTOR (3 DOWNTO 0));
END cont_sinc_mod10;
ENTITY and_2 IS
PORT(a, b : IN BIT;
s : OUT BIT);
END and_2;
ARCHITECTURE arch_and_2 OF and_2 IS
BEGIN
s <= a AND b;
END arch_and_2;
ARCHITECTURE arch_cont_sinc_mod6 OF cont_sinc_mod6 IS
COMPONENT and_2 IS
PORT(a, b : IN BIT;
s : OUT BIT);
END COMPONENT;
SIGNAL and_mod_6_1, and_mod_6_2 : BIT;
BEGIN
FF0 : ffjk PORT MAP(entrada, entrada, clr, clk, q(0), qbar(0));
AND1: and_2 PORT MAP(q(0), qbar(2), and_mod_6_1);
FF1 : ffjk PORT MAP(and_mod_6_1, q(0), clr, clk, q(1), qbar(1));
AND2: and_2 PORT MAP(q(0), q(1), and_mod_6_2);
FF2 : ffjk PORT MAP(and_mod_6_2, q(0), clr, clk, q(2), qbar(2));
END arch_cont_sinc_mod6;
ARCHITECTURE arch_cont_sinc_mod10 OF cont_sinc_mod10 IS
COMPONENT and_2 IS
PORT(a, b : IN BIT;
s : OUT BIT);
END COMPONENT;
SIGNAL and_mod_10_1, and_mod_10_2, and_mod_10_3 : BIT;
BEGIN
FF0 : ffjk PORT MAP(entrada, entrada, clr, clk, q(0), qbar(0));
AND1: and_2 PORT MAP(q(0), qbar(3), and_mod_10_1);
FF1 : ffjk PORT MAP(and_mod_10_1, q(0), clr, clk, q(1), qbar(1));
AND2: and_2 PORT MAP(q(0), q(1), and_mod_10_2);
FF2 : ffjk PORT MAP(and_mod_10_2, and_mod_10_2, clr, clk, q(2), qbar(2));
AND3: and_2 PORT MAP(and_mod_10_2, q(2), and_mod_10_3);
FF3 : ffjk PORT MAP(and_mod_10_3, q(0), clr, clk, q(3), qbar(3));
END arch_cont_sinc_mod10;
PACKAGE cont_sinc_package IS
COMPONENT cont_sinc_mod6
PORT(entrada, clr, clk : IN BIT;
q, qbar : OUT BIT_VECTOR(2 DOWNTO 0));
END COMPONENT;
COMPONENT cont_sinc_mod10 IS
PORT(entrada, clr, clk : IN BIT;
q, qbar : BUFFER BIT_VECTOR (3 DOWNTO 0));
END COMPONENT;
COMPONENT and_2 IS
PORT(a, b : IN BIT;
s : OUT BIT);
END COMPONENT;
END cont_sinc_package;
|
<gh_stars>100-1000
-------------------------------------------------------------------------------
-- Company : SLAC National Accelerator Laboratory
--------------------------------------------------------------------------------------------------------------------------------------------------------------
-- Description: AD9467 Package File
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC Firmware Standard Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library surf;
use surf.StdRtlPkg.all;
package AxiAd9467Pkg is
type AxiAd9467InType is record
clkP : sl;
clkN : sl;
orP : sl;
orN : sl;
dataP : slv(7 downto 0);
dataN : slv(7 downto 0);
end record;
type AxiAd9467InArray is array (natural range <>) of AxiAd9467InType;
type AxiAd9467InVectorArray is array (integer range<>, integer range<>)of AxiAd9467InType;
constant AXI_AD9467_IN_INIT_C : AxiAd9467InType := (
clkP => '0',
clkN => '1',
orP => '0',
orN => '1',
dataP => (others => '0'),
dataN => (others => '1'));
type AxiAd9467InOutType is record
sdio : sl;
end record;
type AxiAd9467InOutArray is array (natural range <>) of AxiAd9467InOutType;
type AxiAd9467InOutVectorArray is array (integer range<>, integer range<>)of AxiAd9467InOutType;
constant AXI_AD9467_IN_OUT_INIT_C : AxiAd9467InOutType := (
sdio => 'Z');
type AxiAd9467OutType is record
cs : sl;
sck : sl;
clkP : sl;
clkN : sl;
end record;
type AxiAd9467OutArray is array (natural range <>) of AxiAd9467OutType;
type AxiAd9467OutVectorArray is array (integer range<>, integer range<>)of AxiAd9467OutType;
constant AXI_AD9467_OUT_INIT_C : AxiAd9467OutType := (
cs => '1',
sck => '1',
clkP => '0',
clkN => '1');
type AxiAd9467SpiInType is record
req : sl;
RnW : sl;
din : slv(7 downto 0);
addr : slv(11 downto 0);
end record;
constant AXI_AD9467_SPI_IN_INIT_C : AxiAd9467SpiInType := (
'0',
'0',
(others => '0'),
(others => '0'));
type AxiAd9467SpiOutType is record
ack : sl;
dout : slv(7 downto 0);
end record;
constant AXI_AD9467_SPI_OUT_INIT_C : AxiAd9467SpiOutType := (
'0',
(others => '0'));
type AxiAd9467DelayInType is record
dmux : sl;
load : sl;
rst : sl;
data : Slv5Array(0 to 7);
end record;
constant AXI_AD9467_DELAY_IN_INIT_C : AxiAd9467DelayInType := (
dmux => '0',
load => '0',
rst => '0',
data => (others => "00000"));
type AxiAd9467DelayOutType is record
rdy : sl;
data : Slv5Array(0 to 7);
end record;
constant AXI_AD9467_DELAY_OUT_INIT_C : AxiAd9467DelayOutType := (
rdy => '0',
data => (others => "00000"));
type AxiAd9467StatusType is record
pllLocked : sl;
adcData : slv(15 downto 0);
adcDataMon : Slv16Array(0 to 15);
spi : AxiAd9467SpiOutType;
delay : AxiAd9467DelayOutType;
end record;
constant AXI_AD9467_STATUS_INIT_C : AxiAd9467StatusType := (
pllLocked => '0',
adcData => x"0000",
adcDataMon => (others => x"0000"),
spi => AXI_AD9467_SPI_OUT_INIT_C,
delay => AXI_AD9467_DELAY_OUT_INIT_C);
type AxiAd9467ConfigType is record
spi : AxiAd9467SpiInType;
delay : AxiAd9467DelayInType;
end record;
constant AXI_AD9467_CONFIG_INIT_C : AxiAd9467ConfigType := (
spi => AXI_AD9467_SPI_IN_INIT_C,
delay => AXI_AD9467_DELAY_IN_INIT_C);
end package;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
<KEY>
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
f1byLYq8pe1a0V3QEoBx8blmzSnvKken1tPfzWCnd3lkNKO8N3M1stH9dHgZk1MM3922jhGhFwqS
<KEY>
`protect key_keyowner = "Synopsys", key_keyname= "<KEY>", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ilzwMzytBCMeq29f+OGAmSgUJOJN1EdMmAt4A8BKjq9qgF4DYyQdh4cYlIr18snWec/yY7YzhGHQ
<KEY>
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8000)
`protect data_block
Ik4dgdconARbw8uxUPPf0rXRkCTYc4V9b6LZSZez9JLmtUHEUUarzS4BR5AO/qAndqAUZCIDdocv
qiYuhlQhK10cE3+rsZTj7Fx2SVWNKEsaW+gi5cek35RMiksmrql/CAPeoEarv+ek7Nx6Qfq/Va+g
q/lqsWW3nOeFS2RIjvJcyanlU0YXfJx9GVwVVRpkl9hsVWS0+P+m8oorhPjRy2t86FagW9pcOtGc
EtIBgx5jPi7/tMYO0Xzhalor+STd7kbZ4ldNvQh+0K6eXhyEvhlvMmoJwHZEyVUQBlD1unK6ZnMO
M5+0fgDuLj6/7MxxjNqSOtDtJ+NQMaesIuKDiNvF7DxY0F6QRuU3TobjwY7FNsbU2MQGhgRLF2F+
Y9CatA4sPacAhgxI48onudX+zuR0ukb/gNlnsfvqLuU1n5X9nvuaDCPb6RmrYy1EkbQxAerNB5a6
H41BCoQhJqqa3pc8Pa3Jm5e8/UgNgqDZYMii2yXhzrC4Kf2xCfABw2yM5Q6cRU+6L7+R3eL01Ief
GfRAjxVxEj+UnMUVSGat9qNtGn614Kwm0EZ7HNib/Sbgen/JFY5Jx6yFF00JmKSkblaQjOVQKEkE
Z7iugr1B5Zqe1XXVQOAcLTkX+pkfmKhw4srBPR969A4bDigR9ZtGBJrGk51LGpd1wJFEtZzUAubp
STu7LYOgaOLZ4imzzf1ZE32AfBbs6lwXYJLlFEQX+LeMaip9z9CB2/O0sMPm6IszXLFLFnuyQPcM
kxrKKEhlk7e1oTng3EcBqTiq/G1SwrQwYJxritGZEHEmTA9vClDE/a5x1Mm2o5zDIA5qL6FWt5Pm
sYjBOccCtf4pN/pcPj112JigKll1yalXUKslDeDoUXVHBjf9vIDZQB9Aq8rxmdzOGXHYdyFP7FYp
RVgkx32sBib2FF6c4/4qM08X1BYD0HgeccERrZr9ohaJH8fSk9dPNvHToWWPtkFBaIC/xkjacAwp
Mc9bTlvLGSHQ2ucE5D+ZMXNFKrKGUT/oa75a/SbtdTZN6Tou23v0/U0ps6VpiiNqm5jm9X5l2EOd
ffgGNTQIqOvIFoEd+SK9NkgwFeWwQxR4Do9cqTg5soYlbNcNMiffoU8JRSj76h2cEcl90SaT8ZV0
nrWowZIx3+oPfv0QX2DZmcSpp0tBtKwFWf0Lm/V0coLIS6+39SDuxKLHEnYiFURcnYzcoY4a2VWp
+wJpIs3MjUoK8crubFvQ0X9sP4+f6AgOrPHc7OpPJRxSpje0OKwPUz0Dps2q8mee0nnjLLIyPUyt
dvUmUsRt1vAnn09xFG+Y1uzsFIDRNjMEeZzKLr7b1al2OM4K91t45Nal/JoSzvSuoGDd6dccyQBN
iNrPBmTGaSkBHMB+XVT1SByBrK+0fX5GiDLh2RrWQ8vX5eB+48o/Qk2GjR0TDO2uml4Kp91+zMg0
pBwHhDo82Cdaf5VhNMfn/nPXmKrlq8IKgnNF/2vU4jWT8NIW6aZJVnMYfwIQCqyrCQdxIktWE7zs
+yvXe+LhXiSDQEhOgnbSacnxXCc/2x2qccmj3j2E7oL1lagQHTryYgrJ4+0xIHEb2ZRBnMJCIGtg
hFxnB5R0yhjs5GqHqUntF3W8l4luC5g3CWyV6bHuPHI32IXJeaVszhT13IumI1pmQQVNiRXPOMDz
bpcdI6MTLVtePlrjaLAhHx+Sifw30ofrUPvqbeCxAbbUH5r/wE+BOQ52xtY/zxtH3L5dftN2mTjx
z+ZJ1WyEH77YUD83PoqEwDvqG8Tloti76w3a8MSVK5uQKGlSMWJ8X+MbSAGFTRmN87vjtD5U742d
Lc9RPLmEoPOiJl1a4V6fE7gC0Gyz3Q7tDjtYqnDHWecUrDGhRdK3Z6rVP1bjmTmw76xEcbtD/wIO
RK7syTSLs3sMPHRYI8Wkr+bzcY83MomL5pKvcdcW6sSX1E7Z1B0uBJozrgX6nXVUg+wBYPyx7Tse
dMt8gQCM+HFSbIV3fKof4Z8SNO9pvKh4z2la+WNj90v70Ih6hAty6wfoKISLPKHOjkA9H5FIHtAQ
MqYzk685mlhYBHSwDQ0jaFzIZS+uhjksTUX7PXS/bkZBrO9hFvIQ1+xtkrpp2UJGVigGKS52A8pk
XsoOkzaxl2kMY40hQ/4++FmsLTJJrOJxrvLyHprngOKrA0vsjfj0C5XCQJJHKt5my2u17KLo4rr6
Ly+E2K4k8rHXdFXC/xZzlor6I5/R+MUYD8GQwQE6NNdRixmXxQxkj9DzabYoBSFZJdd7nSYzTex8
VhDzgoLSS00W+diAnRl+NkpX1a2cGz3jFZuXQvaUTjpbgkMX5a1q0XtfnvfJBBNNGyM8+nHYAqxH
Su3WTASQWgCaH7IcsbR60h0CQnkjjbvC/gur5kor806LDae4H1Lx3f4AWEmrWRyi8rV2zYIohKNk
UXl/085c0fySzYwzgtAN9fsodc/SaTKam60ag52VZKsLZuXW+XK6cYRtRuBLytq7k+t20hDR8zqN
cAE9fz3G7k5qK1XT6du1wLERWIwr096yrBo7ZQQGO20p/jUJL4mRGz+o/dE11gyWKYxex9xtvdiF
Do2UBljLUF/vq97drgPVlOdjSVJ/cGRH7P6z2Eam8NbOB7u7xG9RV4WvO8azvp4k2OsdcI5dDfSx
nkH36GM1wzkx6Bx/P+6LmqtLrHkXew8Z9oD1MinnAcp+nv7EJ8Mn1bUQHVCy9wgDnLWrLFqvZtlo
l4oILRCeVwIlB3Y87fD1yd+7OMXB5HDmBRaOJCam7bVQJMEMCdBiBK3AnwlYdFIzH5zNMZsZlQqg
Xq22kC6kPoxlAnSFyYJ2JBPPhJffhEI6DNXOTQOS68m5tp9qeG6V51W++QJ2OHrODVEnDFqOjeHn
wBf0bFRaKDw+YgWxaf/AURAe7eDKlqP/XpRxqWCICQKI+pLZbyYySObLZwVGD+A9UoyzdKUxGgZm
la1qWoCpZYYOLCTQRz33+uwW/vntrs/FbffwN1v3jq3byGgNPSYUbazZW37kcP9buFCekmDlpheD
lopnQidjWTZ0CWTiz916v5D6nhj39u14iSmWWrLka0jf8ko9tHdUGeF0WoXRQ1ZnBPw0R5YFICwS
9OrNCAKvGNjBiw4uSeaH6auei3xeorPnzLkDvx2WU5KDrQdtV31uVZ0QORdbwHnaaXnZ8uJzyeee
Erdk81ChYfbWH+L8DdoPWxUU1nnJeSIPM6m0aUVZeMYgLrLiWSfPJF2RAvozRssJI9lG/R0GrgS8
tJoVxHVi125F8x/qOIiFhNtLOPpsJtEhUqczxLx+95LkmTB46qWGplfawYBKXTppEP1eefDqBdQ2
WM5qeIEJ/2XJU+cSieVMACrFKE2t1oOvI7dl2Kln42k4uzg6NCDFaUN/kpTOZv+rYvlTKDX15ynF
HU3AyUF8WTG5W/n+g06+WOkW2ckQOyMtLUhhCi2uwadOIL7YfIseS5AffBUDaP23VPq+y/r0HotQ
aHCJnSzes4RjZUDR8CLJJysXOwVvfAV44CM0/e13ESP9MdsR5g0uSbZ5CbZLur4PIbTJStaamlqd
ZVp671dVrMc2Dl3K5KV7AP92QDyHsUiiE9Ti0thOY9z4tYlrcBEtamHh/GQHDFG+BLV25n/o+BoG
/CbD/do8V1hNqszMG16oIuLTs4O+0XPHdFf2/f0Usrol4b6k3g6rQM87F4AnkdChxK4vKLh20EmF
9uPRGaJqdV56PKyv0SFKmfcflLiBrnAvU4gHxCvONuCBedyMuXGLjrzRn1lAs1fRpyVGzMVKFSC2
5xKm6ELr9Wu6/4kKHGNH1Y+nprVErxZqDWIBemHLR9HEB8WU+MJV0filTq7X9xwzovhR4xRRYW01
Fp+O4YK/6BXtNs33a8JrtVw/xoDopx+Q2JX5ID7dOZST9i8jFIzwb7s9glHUxSJf77V4YzPelvjo
Txyg0Kr7xusv69M7k1MclzWXjpS8EOmEeRKSppHZk2P3tH32LIDCFX59j5sHKr4L4GTJRMz5tw6I
qqdTYfXLz6H+5wvjoGqK5GDJJnlO3R3Kcdh6W+SMsO3qTLhiFKarb+xrNwn/7+tz9dp8TvTZj/s7
d9GJDS5gj9Cy8JlWpdQv6xavfZUMUal5LKThGO2ILXmQ/YhulIhdLHxwJP0KNh5pmRZFT5agCWwt
+mz+1IMrHRwZZsFjgPcXESpZS6ynwIJAGfsaJD2/JUDHYqy6YPhTDJewr8YMSykSfkiRdN985hBd
h16wT+V44Z3B7T44mkQ1MTm8/L9PnNUx3vKrpFr73/94D549X1ouuewYXRbatZVI4jklHR6Tzoob
BsdSvoWY80UF1JallREDas1UnEepqOrb6VI9jxDlmmYAeDKlu+tLQZC/TxYxU6b8EP88Fdjh8bpp
RXOSSwDOXyBeXrTbUgtwpZxfuS9Fy59IFHaHjXHEseWoJa5QdJdH1gFaDcLwr/gNKDytasKQBMfb
Am4NAtmPY0FuJ+5DULNDIGp9Kqd0KeZr7LZSX+BC2ywhE7IFBrB4o7PDYRGBNtYu5DP5ehWn4G5Q
dF/lPEf1psVTWnBtGy//9kG1Klt27n+MoyFEhdV2sTH0ItIHptTuWQG0yzHr/ZXmiTIm5f3xY/Zx
JS5eNOdHVJbFGKyqBAzZP8pDJqP/CD7Mtn0p3zhNvaLwttgtvUGO4CNyPuG838DDBn5a99+jx+Q/
<KEY>
`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Arithmetic is
PORT( A : in std_logic_vector( 7 downto 0 );
B : in std_logic_vector( 7 downto 0 );
S0 : in std_logic;
S1 : in std_logic;
CIN : in std_logic;
F : out std_logic_vector( 7 downto 0 );
COUT : out std_logic);
end Arithmetic;
architecture Behavioral of Arithmetic is
COMPONENT Obitfulladder
PORT(
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
CIN : IN std_logic;
C : OUT std_logic;
O : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
signal ST1 : std_logic_vector(7 downto 0);
begin
ST1 <= "00000000" when(S1 = '0' and S0 = '0') else
B when(S1 = '0' and S0 = '1') else
not B when(S1 = '1' and S0 = '0') else
"11111111";
obitfulladder1: Obitfulladder PORT MAP(
A => A,
B => ST1,
CIN => CIN,
C => COUT,
O => F
);
end Behavioral;
|
-- (C) 2001-2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License Subscription
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Intel and sold by
-- Intel or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
entity NF_PHYIP_RESET_MODEL is
port (
clk :in std_logic;
reset :in std_logic;
tx_serial_clk :out std_logic_vector (0 downto 0);
tx_analogreset :out std_logic_vector (0 downto 0);
tx_digitalreset :out std_logic_vector (0 downto 0);
tx_ready :out std_logic;
rx_analogreset :out std_logic_vector (0 downto 0);
rx_digitalreset :out std_logic_vector (0 downto 0);
rx_ready :out std_logic;
tx_cal_busy :in std_logic_vector (0 downto 0);
rx_is_lockedtodata :in std_logic_vector (0 downto 0);
rx_cal_busy :in std_logic_vector (0 downto 0)
);
end NF_PHYIP_RESET_MODEL;
architecture behave of NF_PHYIP_RESET_MODEL is
signal clk_1250MHz :std_logic_vector (0 downto 0);
signal tx_digital_reset_count :std_logic_vector (31 downto 0);
signal rx_digital_reset_count :std_logic_vector (31 downto 0);
signal tx_ready_count :std_logic_vector (31 downto 0);
signal rx_ready_count :std_logic_vector (31 downto 0);
signal tx_analogreset_int :std_logic_vector (0 downto 0);
signal rx_analogreset_int :std_logic_vector (0 downto 0);
signal tx_digitalreset_int :std_logic_vector (0 downto 0);
signal rx_digitalreset_int :std_logic_vector (0 downto 0);
begin
-- 1250 MHz TX serial clock
process
begin
clk_1250MHz (0) <= '1' ;
wait for 400 ps;
clk_1250MHz (0) <= '0' ;
wait for 400 ps ;
end process ;
tx_serial_clk <= clk_1250MHz;
-- TX digital reset duration
process (clk, tx_analogreset_int)
begin
if (tx_analogreset_int(0) = '1') then
tx_digital_reset_count <= conv_std_logic_vector (625, 32); -- 5000ns
elsif (clk = '1') and (clk 'event) then
if (tx_digital_reset_count /= 0) and (tx_cal_busy(0) = '0') then
tx_digital_reset_count <= tx_digital_reset_count - 1;
end if;
end if;
end process;
-- RX digital reset duration
process (clk, rx_analogreset_int)
begin
if (rx_analogreset_int(0) = '1') then
rx_digital_reset_count <= conv_std_logic_vector (500, 32); -- 4000ns
elsif (clk = '1') and (clk 'event) then
if (rx_digital_reset_count /= 0) and (rx_cal_busy(0) = '0') and (rx_is_lockedtodata(0) = '1') then
rx_digital_reset_count <= rx_digital_reset_count - 1;
end if;
end if;
end process;
-- TX ready duration
process (clk, reset)
begin
if (reset = '1') then
tx_ready_count <= conv_std_logic_vector (10, 32); -- 80ns
elsif (clk = '1') and (clk 'event) then
if (tx_digitalreset_int(0) = '0') and (tx_ready_count /= 0) then
tx_ready_count <= tx_ready_count - 1;
end if;
end if;
end process;
-- RX ready duration
process (clk, reset)
begin
if (reset = '1') then
rx_ready_count <= conv_std_logic_vector (10, 32); -- 80ns
elsif (clk = '1') and (clk 'event) then
if (rx_digitalreset_int(0) = '0') and (rx_ready_count /= 0) then
rx_ready_count <= rx_ready_count - 1;
end if;
end if;
end process;
-- TX and RX analog reset
process (clk, reset)
begin
if (reset = '1') then
tx_analogreset_int(0) <= '1';
rx_analogreset_int(0) <= '1';
elsif (clk = '1') and (clk 'event) then
tx_analogreset_int(0) <= '0';
rx_analogreset_int(0) <= '0';
end if;
end process;
tx_analogreset(0) <= tx_analogreset_int(0);
rx_analogreset(0) <= rx_analogreset_int(0);
-- TX digital reset
process (clk, reset)
begin
if (reset = '1') then
tx_digitalreset_int(0) <= '1';
elsif (clk = '1') and (clk 'event) then
if (tx_digital_reset_count = 0) then
tx_digitalreset_int(0) <= '0';
end if;
end if;
end process;
-- RX digital reset
process (clk, reset)
begin
if (reset = '1') then
rx_digitalreset_int(0) <= '1';
elsif (clk = '1') and (clk 'event) then
if (rx_digital_reset_count = 0) then
rx_digitalreset_int(0) <= '0';
end if;
end if;
end process;
tx_digitalreset(0) <= tx_digitalreset_int(0);
rx_digitalreset(0) <= rx_digitalreset_int(0);
process (tx_ready_count, rx_ready_count)
begin
if (tx_ready_count = 0) then
tx_ready <= '1';
else
tx_ready <= '0';
end if;
if (rx_ready_count = 0) then
rx_ready <= '1';
else
rx_ready <= '0';
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- the unsigned method (dec,bits)
use IEEE.math_real.all; -- op **
entity decoder_3x8 is
port( A: in std_logic_vector(2 downto 0);
Q: out std_logic_Vector(7 downto 0));
end;
architecture decoder of decoder_3x8 is
begin
Q <= std_logic_vector(to_unsigned(2** to_integer(unsigned(A)),8)); --
end;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
entity RGBtoYCbCr_test is
end RGBtoYCbCr_test;
architecture behavioral of RGBtoYCbCr_test is
constant SYSCLK_PERIOD : time := 10 ns; -- 10MHZ
-----------------------------------------------------------
-- Core parameters
-----------------------------------------------------------
constant G_RGB_DATA_BIT_WIDTH : INTEGER := 10;
constant G_YCbCr_DATA_BIT_WIDTH : INTEGER := 10;
signal SYSCLK : STD_LOGIC := '0';
signal NSYSRESET : STD_LOGIC := '0';
signal RED_I : STD_LOGIC_VECTOR ((G_RGB_DATA_BIT_WIDTH - 1) DOWNTO 0):="00" & x"00";
signal GREEN_I : STD_LOGIC_VECTOR ((G_RGB_DATA_BIT_WIDTH - 1) DOWNTO 0):="00" & x"00";
signal BLUE_I : STD_LOGIC_VECTOR ((G_RGB_DATA_BIT_WIDTH - 1) DOWNTO 0):="00" & x"00";
signal DATA_VALID_I : STD_LOGIC;
signal Y_OUT_O : STD_LOGIC_VECTOR ((G_YCbCr_DATA_BIT_WIDTH - 1) DOWNTO 0);
signal Cb_OUT_O : STD_LOGIC_VECTOR ((G_YCbCr_DATA_BIT_WIDTH - 1) DOWNTO 0);
signal Cr_OUT_O : STD_LOGIC_VECTOR ((G_YCbCr_DATA_BIT_WIDTH - 1) DOWNTO 0);
signal DATA_VALID_O : STD_LOGIC;
component RGB2YCbCr
generic (G_RGB_DATA_BIT_WIDTH : INTEGER := 10;
G_YCbCr_DATA_BIT_WIDTH : INTEGER := 10
);
port (
CLOCK_I : IN STD_LOGIC;
RESET_N_I : IN STD_LOGIC;
RED_I : IN STD_LOGIC_VECTOR ((G_RGB_DATA_BIT_WIDTH - 1) DOWNTO 0);
GREEN_I : IN STD_LOGIC_VECTOR ((G_RGB_DATA_BIT_WIDTH - 1) DOWNTO 0);
BLUE_I : IN STD_LOGIC_VECTOR ((G_RGB_DATA_BIT_WIDTH - 1) DOWNTO 0);
DATA_VALID_I : IN STD_LOGIC;
Y_OUT_O : OUT STD_LOGIC_VECTOR ((G_YCbCr_DATA_BIT_WIDTH - 1) DOWNTO 0);
Cb_OUT_O : OUT STD_LOGIC_VECTOR ((G_YCbCr_DATA_BIT_WIDTH - 1) DOWNTO 0);
Cr_OUT_O : OUT STD_LOGIC_VECTOR ((G_YCbCr_DATA_BIT_WIDTH - 1) DOWNTO 0);
DATA_VALID_O : OUT STD_LOGIC
);
end component;
begin
-- Clock Driver
SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );
PROCESS
BEGIN
NSYSRESET <= '0';
WAIT FOR(SYSCLK_PERIOD * 10);
NSYSRESET <= '1';
WAIT;
END PROCESS;
PROCESS
BEGIN
DATA_VALID_I <= '0';
WAIT FOR(SYSCLK_PERIOD * 10);
DATA_VALID_I <= '1';
WAIT FOR(SYSCLK_PERIOD * 40);
DATA_VALID_I <= '0';
WAIT;
END PROCESS;
PROCESS
BEGIN
WAIT FOR 100 ns;
RED_I <="00" & x"06";
GREEN_I <="00" & x"09";
BLUE_I <="00" & x"0C";
WAIT FOR 100 ns;
RED_I <="00" & x"17";
GREEN_I <="00" & x"2A";
BLUE_I <="00" & x"3B";
WAIT FOR 100 ns;
RED_I <="00" & x"4D";
GREEN_I <="00" & x"53";
BLUE_I <="00" & x"A8";
WAIT FOR 100 ns;
RED_I <="00" & x"77";
GREEN_I <="00" & x"8A";
BLUE_I <="00" & x"98";
WAIT;
END PROCESS;
-- Instantiate Unit Under Test: test
test_RGBYCbCr : RGB2YCbCr
generic map(
G_RGB_DATA_BIT_WIDTH => G_RGB_DATA_BIT_WIDTH,
G_YCbCr_DATA_BIT_WIDTH => G_YCbCr_DATA_BIT_WIDTH
)
port map(
CLOCK_I => SYSCLK,
RESET_N_I => NSYSRESET,
RED_I => RED_I,
GREEN_I => GREEN_I,
BLUE_I => BLUE_I,
DATA_VALID_I => DATA_VALID_I,
Y_OUT_O => Y_OUT_O,
Cb_OUT_O => Cb_OUT_O,
Cr_OUT_O => Cr_OUT_O,
DATA_VALID_O => DATA_VALID_O
);
end behavioral;
|
<filename>uart_tx.vhd
library ieee;
use ieee.std_logic_1164.all;
entity UART_TX is
port(
SS : in std_logic;
DA : in std_logic_vector(7 downto 0);
CLK : in std_logic;
RST : in std_logic;
DS : out std_logic;
TX : out std_logic
);
end entity UART_TX;
architecture BEHAVORIAL of UART_TX is
type STATES is (IDLE,START,DATA0,DATA1,DATA2,DATA3,DATA4,DATA5,DATA6,DATA7,STOP);
signal Q, D : STATES;
begin
SEND: process(DA,CLK,RST)
begin
if RST = '0' Then
Q <= IDLE;
DS <= '1';
elsif rising_edge(CLK) then
Q <= D;
end if;
case Q is
when IDLE =>
TX <= '1';
if SS = '1' then
D <= START;
else
D <= IDLE;
end if;
when START =>
TX <= '0';
D <= DATA0;
DS <= '0';
when DATA0 =>
TX <= DA(0);
D <= DATA1;
when DATA1 =>
TX <= DA(1);
D <= DATA2;
when DATA2 =>
TX <= DA(2);
D <= DATA3;
when DATA3 =>
TX <= DA(3);
D <= DATA4;
when DATA4 =>
TX <= DA(4);
D <= DATA5;
when DATA5 =>
TX <= DA(5);
D <= DATA6;
when DATA6 =>
TX <= DA(6);
D <= DATA7;
when DATA7 =>
TX <= DA(7);
D <= STOP;
when STOP =>
TX <= '0';
D <= IDLE;
DS <= '1';
end case;
end process;
end architecture BEHAVORIAL;
|
<gh_stars>10-100
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rubik_tb is
end entity rubik_tb;
architecture simulation of rubik_tb is
signal clk : std_logic;
signal rst : std_logic;
signal cmd : std_logic_vector(3 downto 0);
signal done : std_logic;
constant C_CMD_FP : std_logic_vector(3 downto 0) := "0101";
constant C_CMD_F2 : std_logic_vector(3 downto 0) := "0110";
constant C_CMD_FM : std_logic_vector(3 downto 0) := "0111";
constant C_CMD_RP : std_logic_vector(3 downto 0) := "1001";
constant C_CMD_R2 : std_logic_vector(3 downto 0) := "1010";
constant C_CMD_RM : std_logic_vector(3 downto 0) := "1011";
constant C_CMD_UP : std_logic_vector(3 downto 0) := "1101";
constant C_CMD_U2 : std_logic_vector(3 downto 0) := "1110";
constant C_CMD_UM : std_logic_vector(3 downto 0) := "1111";
-- Random number generator with initial seed
signal prbs255 : std_logic_vector(254 downto 0) := (others => '1');
begin
p_clk : process
begin
clk <= '1', '0' after 5 ns;
wait for 10 ns;
end process p_clk;
p_rst : process
begin
rst <= '1';
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
rst <= '0';
wait until clk = '1';
wait;
end process p_rst;
--------------------------------------------
-- Random number generator, based on a PRBS
--------------------------------------------
p_prbs255 : process (clk)
begin
if rising_edge(clk) then
prbs255 <= prbs255(253 downto 0)
& (prbs255(254) xor prbs255(13) xor prbs255(17) xor prbs255(126));
end if;
end process p_prbs255;
p_test : process
procedure repeat(cmd_p : std_logic_vector(3 downto 0); count_p : integer) is
begin
for i in 1 to count_p loop
cmd <= cmd_p;
wait until clk = '1';
cmd <= "0000";
wait until clk = '1';
wait until clk = '1';
wait until clk = '1';
end loop;
end procedure repeat;
begin
cmd <= "0000";
wait until rst = '0';
wait until clk = '1';
assert done = '1';
-- Test period of each rotation.
-- I.e. verify that after repeating the rotation we get back the original cube.
repeat(C_CMD_FP, 4); assert done = '1';
repeat("0000", 1);
repeat(C_CMD_F2, 2); assert done = '1';
repeat("0000", 1);
repeat(C_CMD_FM, 4); assert done = '1';
repeat("0000", 2);
repeat(C_CMD_RP, 4); assert done = '1';
repeat("0000", 1);
repeat(C_CMD_R2, 2); assert done = '1';
repeat("0000", 1);
repeat(C_CMD_RM, 4); assert done = '1';
repeat("0000", 2);
repeat(C_CMD_UP, 4); assert done = '1';
repeat("0000", 1);
repeat(C_CMD_U2, 2); assert done = '1';
repeat("0000", 1);
repeat(C_CMD_UM, 4); assert done = '1';
repeat("0000", 2);
-- Generate some random rotations.
-- Any illegal commands will just be skipped.
for i in 1 to 50 loop
repeat(prbs255(3 downto 0), 1);
end loop;
wait;
end process p_test;
i_rubik : entity work.rubik
port map (
clk_i => clk,
rst_i => rst,
cmd_i => cmd,
done_o => done
); -- i_rubik
end architecture simulation;
|
-------------------------------------------------------------------------------
-- Title : Gigabit Ethernet reception pipeline
-- Project : White Rabbit MAC/Endpoint
-------------------------------------------------------------------------------
-- File : ep_rx_path.vhd
-- Author : <NAME>
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2017-02-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: RX path unit:
-- - provides elastic buffering between RX and system clock
-- - checks frame CRC and size
-- - inserts/removes 802.1q headers when necessary
-- - parses packet headers and generates RTU requests
-- - performs programmable packet inspection and classifying
-- - distinguishes between HP and non-HP frames
-- - issues RTU requests
-- - embeds RX OOB block with timestamp information
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009-2011 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2009-06-22 0.1 twlostow Created
-- 2011-10-18 0.5 twlostow WB rev B4 - compatible data path
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.genram_pkg.all;
use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
use work.ep_wbgen2_pkg.all;
use work.wr_fabric_pkg.all;
entity ep_rx_path is
generic (
g_with_vlans : boolean := true;
g_with_dpi_classifier : boolean := true;
g_with_rtu : boolean := true;
g_with_rx_buffer : boolean := true;
g_with_early_match : boolean := false;
g_rx_buffer_size : integer := 1024;
g_use_new_crc : boolean := false);
port (
clk_sys_i : in std_logic;
clk_rx_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_n_rx_i : in std_logic;
-- physical coding sublayer (PCS) interface
pcs_fab_i : in t_ep_internal_fabric;
pcs_fifo_almostfull_o : out std_logic;
pcs_busy_i : in std_logic;
-- Wishbone I/O
src_wb_o : out t_wrf_source_out;
src_wb_i : in t_wrf_source_in;
-- flow control signals
fc_pause_p_o : out std_logic;
fc_pause_quanta_o : out std_logic_vector(15 downto 0);
fc_pause_prio_mask_o : out std_logic_vector(7 downto 0);
fc_buffer_occupation_o : out std_logic_vector(7 downto 0);
-- RMON/statistic counters signals
rmon_o : out t_rmon_triggers;
regs_i : in t_ep_out_registers;
regs_o : out t_ep_in_registers;
-- info for TRU module
pfilter_pclass_o : out std_logic_vector(7 downto 0);
pfilter_drop_o : out std_logic;
pfilter_done_o : out std_logic;
-------------------------------------------------------------------------------
-- RTU interface
-------------------------------------------------------------------------------
rtu_rq_o : out t_ep_internal_rtu_request;
rtu_full_i : in std_logic;
rtu_rq_valid_o : out std_logic;
rtu_rq_abort_o : out std_logic;
nice_dbg_o : out t_dbg_ep_rxpath
);
end ep_rx_path;
architecture behavioral of ep_rx_path is
type t_rx_deframer_state is (RXF_IDLE, RXF_DATA, RXF_FLUSH_STALL, RXF_FINISH_CYCLE, RXF_THROW_ERROR);
signal state : t_rx_deframer_state;
signal gap_cntr : unsigned(3 downto 0);
-- new sigs
signal counter : unsigned(7 downto 0);
signal rxdata_saved : std_logic_vector(15 downto 0);
signal next_hdr : std_logic;
signal is_pause : std_logic;
signal data_firstword : std_logic;
signal flush_stall : std_logic;
signal stb_int : std_logic;
signal fab_int : t_ep_internal_fabric;
signal dreq_int : std_logic;
signal ack_count : unsigned(7 downto 0);
signal src_out_int : t_wrf_source_out;
signal tmp_sel : std_logic;
signal tmp_dat : std_logic_vector(15 downto 0);
signal fab_pipe : t_fab_pipe(0 to 9);
signal dreq_pipe : std_logic_vector(9 downto 0);
signal ematch_done : std_logic;
signal ematch_is_hp : std_logic;
signal ematch_is_pause : std_logic;
signal fc_pause_p : std_logic;
signal pfilter_pclass : std_logic_vector(7 downto 0);
signal pfilter_drop : std_logic;
signal pfilter_done : std_logic;
signal vlan_tclass : std_logic_vector(2 downto 0);
signal vlan_vid : std_logic_vector(11 downto 0);
signal vlan_tag_done : std_logic;
signal vlan_is_tagged : std_logic;
signal pcs_fifo_almostfull : std_logic;
signal mbuf_rd, mbuf_valid, mbuf_we, mbuf_pf_drop, mbuf_is_hp : std_logic;
signal mbuf_is_pause, mbuf_full : std_logic;
signal mbuf_pf_class : std_logic_vector(7 downto 0);
signal rtu_rq_valid : std_logic;
signal stat_reg_mbuf_valid : std_logic;
signal rxbuf_full : std_logic;
signal rxbuf_dropped : std_logic;
signal src_wb_out : t_wrf_source_out;
signal src_wb_cyc_d0 : std_logic;
signal rst_n_rx_match_buff : std_logic;
begin -- behavioral
fab_pipe(0) <= pcs_fab_i;
fc_pause_p_o <= fc_pause_p;
gen_with_early_match : if(g_with_early_match) generate
U_early_addr_match : ep_rx_early_address_match
port map (
clk_sys_i => clk_sys_i,
clk_rx_i => clk_rx_i,
rst_n_sys_i => rst_n_sys_i,
rst_n_rx_i => rst_n_rx_i,
snk_fab_i => fab_pipe(0),
src_fab_o => fab_pipe(1),
match_done_o => ematch_done,
match_is_hp_o => ematch_is_hp,
match_is_pause_o => ematch_is_pause,
match_pause_quanta_o => fc_pause_quanta_o,
match_pause_prio_mask_o => fc_pause_prio_mask_o,
match_pause_p_o => fc_pause_p,
regs_i => regs_i);
end generate gen_with_early_match;
gen_without_early_match : if(not g_with_early_match) generate
fab_pipe(1) <= fab_pipe(0);
ematch_done <= '0';
ematch_is_hp <= '0';
ematch_is_pause <= '0';
fc_pause_quanta_o <= (others =>'0');
fc_pause_prio_mask_o <= (others =>'0');
fc_pause_p <= '0';
end generate gen_without_early_match;
gen_with_packet_filter : if(g_with_dpi_classifier) generate
U_packet_filter : ep_packet_filter
port map (
clk_sys_i => clk_sys_i,
clk_rx_i => clk_rx_i,
rst_n_sys_i => rst_n_sys_i,
rst_n_rx_i => rst_n_rx_i,
snk_fab_i => fab_pipe(1),
src_fab_o => fab_pipe(2),
done_o => pfilter_done,
pclass_o => pfilter_pclass,
drop_o => pfilter_drop,
regs_i => regs_i);
end generate gen_with_packet_filter;
gen_without_packet_filter : if(not g_with_dpi_classifier) generate
fab_pipe(2) <= fab_pipe(1);
pfilter_drop <= '0';
pfilter_done <= '1';
pfilter_pclass <= (others => '0');
end generate gen_without_packet_filter;
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if (rst_n_sys_i = '0') then
mbuf_we <= '0';
-- if rx_buffer has dropped a frame (e.g. because it was full) we
-- shouldn't store pfilter decision in the mbuf as well
elsif( ((ematch_done='1' and g_with_early_match) or
(pfilter_done='1' and g_with_dpi_classifier)) and
rxbuf_dropped='0') then
mbuf_we <= '1';
elsif(mbuf_rd = '1' or mbuf_full = '0') then
mbuf_we <= '0';
end if;
end if;
end process;
gen_with_match_buff: if( g_with_early_match or g_with_dpi_classifier) generate
U_Sync_Rst_match_buff : gc_sync_ffs
port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_n_rx_i,
synced_o => rst_n_rx_match_buff);
U_match_buffer : generic_shiftreg_fifo
generic map (
g_data_width => 8 + 1 + 1 + 1,
g_size => 16)
port map (
rst_n_i => rst_n_rx_match_buff,
clk_i => clk_sys_i,
d_i (0) => ematch_is_hp,
d_i (1) => ematch_is_pause,
d_i (2) => pfilter_drop,
d_i (10 downto 3) => pfilter_pclass,
we_i => mbuf_we,
q_o (0) => mbuf_is_hp,
q_o (1) => mbuf_is_pause,
q_o (2) => mbuf_pf_drop,
q_o (10 downto 3) => mbuf_pf_class,
rd_i => mbuf_rd,
full_o => mbuf_full,
q_valid_o => mbuf_valid);
end generate;
gen_without_match_buf: if(not (g_with_early_match or g_with_dpi_classifier)) generate
mbuf_is_hp <= '0';
mbuf_is_pause <= '0';
mbuf_pf_drop <= '0';
mbuf_pf_class <= (others=>'0');
mbuf_full <= '0';
mbuf_valid <= '1';
end generate;
-- don't block ep_rx_status_reg_insert when pfilter is disabled and early
-- match is not used
stat_reg_mbuf_valid <= '1' when (not g_with_early_match and g_with_dpi_classifier
and regs_i.pfcr0_enable_o='0') else
mbuf_valid;
U_Rx_Clock_Align_FIFO : ep_clock_alignment_fifo
generic map (
g_size => 128,
g_almostfull_threshold => 112)
port map (
rst_n_rd_i => rst_n_sys_i,
rst_n_wr_i => rst_n_rx_i,
clk_wr_i => clk_rx_i,
clk_rd_i => clk_sys_i,
dreq_i => dreq_pipe(3),
fab_i => fab_pipe(2),
fab_o => fab_pipe(3),
full_o => nice_dbg_o.pcs_fifo_full,
empty_o => nice_dbg_o.pcs_fifo_empty,
almostfull_o => pcs_fifo_almostfull,
pass_threshold_i => std_logic_vector(to_unsigned(32, 7))); -- fixme: add
-- register
pcs_fifo_almostfull_o <= pcs_fifo_almostfull;
U_Insert_OOB : ep_rx_oob_insert
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
snk_fab_i => fab_pipe(3),
snk_dreq_o => dreq_pipe(3),
src_dreq_i => dreq_pipe(4),
src_fab_o => fab_pipe(4),
regs_i => regs_i);
U_crc_size_checker : ep_rx_crc_size_check
generic map (
g_use_new_crc => g_use_new_crc)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
snk_fab_i => fab_pipe(4),
snk_dreq_o => dreq_pipe(4),
src_dreq_i => dreq_pipe(5),
src_fab_o => fab_pipe(5),
regs_i => regs_i,
rmon_pcs_err_o => rmon_o.rx_pcs_err,
rmon_giant_o => rmon_o.rx_giant,
rmon_runt_o => rmon_o.rx_runt,
rmon_crc_err_o => rmon_o.rx_crc_err);
gen_with_vlan_unit : if(g_with_vlans) generate
U_vlan_unit : ep_rx_vlan_unit
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
snk_fab_i => fab_pipe(5),
snk_dreq_o => dreq_pipe(5),
src_fab_o => fab_pipe(6),
src_dreq_i => dreq_pipe(6),
tclass_o => vlan_tclass,
vid_o => vlan_vid,
tag_done_o => vlan_tag_done,
is_tagged_o => vlan_is_tagged,
regs_i => regs_i,
regs_o => regs_o);
end generate gen_with_vlan_unit;
gen_without_vlan_unit : if(not g_with_vlans) generate
fab_pipe(6) <= fab_pipe(5);
dreq_pipe(5) <= dreq_pipe(6);
vlan_tclass <= (others => '0');
vlan_vid <= (others => '0');
vlan_tag_done <= '0';
vlan_is_tagged <= '0';
regs_o <= c_ep_in_registers_init_value;
end generate gen_without_vlan_unit;
U_RTU_Header_Extract : ep_rtu_header_extract
generic map (
g_with_rtu => g_with_rtu)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
snk_fab_i => fab_pipe(6),
snk_dreq_o => dreq_pipe(6),
src_fab_o => fab_pipe(7),
src_dreq_i => dreq_pipe(7),
mbuf_is_pause_i => mbuf_is_pause, -- this module is in the pipe before ep_rx_status_reg_insert,
-- however, we know that mbuf_is_pause is valid when it
-- is used by this module -- this is because blocks the pipe
-- untill mbuf_valid is HIGH, and rtu_rq_valid_o is inserted HIGH
-- at the end of the header... (clear ??:)
vlan_class_i => vlan_tclass,
vlan_vid_i => vlan_vid,
vlan_tag_done_i => vlan_tag_done,
vlan_is_tagged_i => vlan_is_tagged,
rmon_drp_at_rtu_full_o => rmon_o.rx_drop_at_rtu_full,
rtu_rq_o => rtu_rq_o,
rtu_full_i => rtu_full_i,
rtu_rq_abort_o => rtu_rq_abort_o,
rtu_rq_valid_o => rtu_rq_valid,
rxbuf_full_i => rxbuf_full);
gen_with_rx_buffer : if g_with_rx_buffer generate
U_Rx_Buffer : ep_rx_buffer
generic map (
g_size => g_rx_buffer_size,
g_with_fc => false)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
snk_fab_i => fab_pipe(7),
snk_dreq_o => dreq_pipe(7),
src_fab_o => fab_pipe(8),
src_dreq_i => dreq_pipe(8),
level_o => fc_buffer_occupation_o,
full_o => rxbuf_full,
drop_req_i => mbuf_we, -- if mbuf_we is high that means it waits to be
-- stored in mbuf => mbuf is probably full so we
-- should drop this frame
dropped_o => rxbuf_dropped,
regs_i => regs_i);
end generate gen_with_rx_buffer;
gen_without_rx_buffer : if (not g_with_rx_buffer) generate
fab_pipe(8) <= fab_pipe(7);
dreq_pipe(7) <= dreq_pipe(8);
rxbuf_full <= '0';
end generate gen_without_rx_buffer;
U_Gen_Status : ep_rx_status_reg_insert
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
snk_fab_i => fab_pipe(8),
snk_dreq_o => dreq_pipe(8),
src_fab_o => fab_pipe(9),
src_dreq_i => dreq_pipe(9),
mbuf_valid_i => stat_reg_mbuf_valid,
mbuf_ack_o => mbuf_rd,
mbuf_drop_i => mbuf_pf_drop,
mbuf_pclass_i => mbuf_pf_class,
mbuf_is_hp_i => mbuf_is_hp,
mbuf_is_pause_i => mbuf_is_pause,
rmon_pfilter_drop_o => rmon_o.rx_pfilter_drop);
U_RX_Wishbone_Master : ep_rx_wb_master
generic map (
g_ignore_ack => true)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
snk_fab_i => fab_pipe(9),
snk_dreq_o => dreq_pipe(9),
src_wb_i => src_wb_i,
src_wb_o => src_wb_out
);
src_wb_o <= src_wb_out;
-- direct output of packet filter data (for TRU)
pfilter_pclass_o <= pfilter_pclass;
pfilter_drop_o <= pfilter_drop;
pfilter_done_o <= pfilter_done;
rtu_rq_valid_o <= rtu_rq_valid;
-----------------------------------------
-- RMON events
-----------------------------------------
rmon_o.rx_pause <= fc_pause_p;
GEN_PCLASS_EVT: for i in 0 to 7 generate
rmon_o.rx_pclass(i) <= pfilter_pclass(i) and pfilter_done;
end generate;
rmon_o.rx_tclass(0) <= rtu_rq_valid when (vlan_tclass = "000" and vlan_is_tagged = '1') else '0';
rmon_o.rx_tclass(1) <= rtu_rq_valid when (vlan_tclass = "001" and vlan_is_tagged = '1') else '0';
rmon_o.rx_tclass(2) <= rtu_rq_valid when (vlan_tclass = "010" and vlan_is_tagged = '1') else '0';
rmon_o.rx_tclass(3) <= rtu_rq_valid when (vlan_tclass = "011" and vlan_is_tagged = '1') else '0';
rmon_o.rx_tclass(4) <= rtu_rq_valid when (vlan_tclass = "100" and vlan_is_tagged = '1') else '0';
rmon_o.rx_tclass(5) <= rtu_rq_valid when (vlan_tclass = "101" and vlan_is_tagged = '1') else '0';
rmon_o.rx_tclass(6) <= rtu_rq_valid when (vlan_tclass = "110" and vlan_is_tagged = '1') else '0';
rmon_o.rx_tclass(7) <= rtu_rq_valid when (vlan_tclass = "111" and vlan_is_tagged = '1') else '0';
GEN_DBG: for i in 0 to 9 generate
nice_dbg_o.fab_pipe(i) <= fab_pipe(i);
nice_dbg_o.dreq_pipe(i)<= dreq_pipe(i);
end generate GEN_DBG;
nice_dbg_o.pcs_fifo_afull <= pcs_fifo_almostfull;
nice_dbg_o.rxbuf_full <= rxbuf_full;
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if (rst_n_sys_i = '0') then
src_wb_cyc_d0 <= '0';
else
src_wb_cyc_d0 <= src_wb_out.cyc;
end if;
end if;
end process;
rmon_o.rx_frame <= '1' when (src_wb_out.cyc = '1' and src_wb_cyc_d0 = '0') else
'0';
-- drive unused signals and outputs
dreq_pipe(2 downto 0) <= (others => '0');
rmon_o.rx_sync_lost <= '0';
rmon_o.rx_invalid_code <= '0';
rmon_o.rx_overrun <= '0';
rmon_o.rx_ok <= '0';
rmon_o.rx_buffer_overrun <= '0';
rmon_o.rx_rtu_overrun <= '0';
rmon_o.rx_path_timing_failure <= '0';
rmon_o.tx_pause <= '0';
rmon_o.tx_underrun <= '0';
rmon_o.tx_frame <= '0';
end behavioral;
|
<reponame>njohnson1996/Microblaze_1
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3.1 (win64) Build 2035080 Fri Oct 20 14:20:01 MDT 2017
-- Date : Tue Oct 31 08:27:59 2017
-- Host : DESKTOP-N5QQ8EU running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ Top_Level_view_xbip_multadd_0_1_stub.vhdl
-- Design : Top_Level_view_xbip_multadd_0_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7s50csga324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
CLK : in STD_LOGIC;
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 19 downto 0 );
B : in STD_LOGIC_VECTOR ( 19 downto 0 );
C : in STD_LOGIC_VECTOR ( 47 downto 0 );
SUBTRACT : in STD_LOGIC;
P : out STD_LOGIC_VECTOR ( 47 downto 0 );
PCOUT : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,CE,SCLR,A[19:0],B[19:0],C[47:0],SUBTRACT,P[47:0],PCOUT[47:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "xbip_multadd_v3_0_11,Vivado 2017.3.1";
begin
end;
|
<filename>digital_clock_final/digital_clock_final.srcs/sim_1/new/tb_digital_clock.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_digital_clock IS
END tb_digital_clock;
ARCHITECTURE behavior OF tb_digital_clock IS
COMPONENT digital_clock
PORT(
clk : IN std_logic;
rst_n : IN std_logic;
H_in1 : IN std_logic_vector(1 downto 0);
H_in0 : IN std_logic_vector(3 downto 0);
M_in1 : IN std_logic_vector(3 downto 0);
M_in0 : IN std_logic_vector(3 downto 0);
S_in1 : IN std_logic_vector(3 downto 0);
S_in0 : IN std_logic_vector(3 downto 0);
H_out1 : OUT std_logic_vector(6 downto 0);
H_out0 : OUT std_logic_vector(6 downto 0);
M_out1 : OUT std_logic_vector(6 downto 0);
M_out0 : OUT std_logic_vector(6 downto 0);
S_out1 : OUT std_logic_vector(6 downto 0);
S_out0 : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst_n : std_logic := '0';
signal H_in1 : std_logic_vector(1 downto 0) := (others => '0');
signal H_in0 : std_logic_vector(3 downto 0) := (others => '0');
signal M_in1 : std_logic_vector(3 downto 0) := (others => '0');
signal M_in0 : std_logic_vector(3 downto 0) := (others => '0');
signal S_in1 : std_logic_vector(3 downto 0) := (others => '0');
signal S_in0 : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal H_out1 : std_logic_vector(6 downto 0);
signal H_out0 : std_logic_vector(6 downto 0);
signal M_out1 : std_logic_vector(6 downto 0);
signal M_out0 : std_logic_vector(6 downto 0);
signal S_out1 : std_logic_vector(6 downto 0);
signal S_out0 : std_logic_vector(6 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ps;
BEGIN
uut: digital_clock PORT MAP (
clk => clk,
rst_n => rst_n,
H_in1 => H_in1,
H_in0 => H_in0,
M_in1 => M_in1,
M_in0 => M_in0,
S_in1 => S_in1,
S_in0 => S_in0,
H_out1 => H_out1,
H_out0 => H_out0,
M_out1 => M_out1,
M_out0 => M_out0,
S_out1 => S_out1,
S_out0 => S_out0
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
rst_n <= '0';
H_in1 <= "01";
H_in0 <= x"0";
M_in1 <= x"0";
M_in0 <= x"0";
S_in1 <= x"0";
S_in0 <= x"0";
wait for 100 ns;
rst_n <= '1';
wait for clk_period*10;
wait;
end process;
END;
|
<reponame>anserion/RNS_filter_ax309
------------------------------------------------------------------
--Copyright 2019 <NAME> (<EMAIL>)
--Licensed under the Apache License, Version 2.0 (the "License");
--you may not use this file except in compliance with the License.
--You may obtain a copy of the License at
-- http://www.apache.org/licenses/LICENSE-2.0
--Unless required by applicable law or agreed to in writing, software
--distributed under the License is distributed on an "AS IS" BASIS,
--WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--See the License for the specific language governing permissions and
--limitations under the License.
------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Engineer: <NAME> <<EMAIL>>
--
-- Description: keys supervisor.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keys_supervisor is
Port (
clk : in std_logic;
en : in std_logic;
key : in std_logic_vector(3 downto 0);
key_rst: in std_logic;
k1,k2,k3,k4,k5,k6,k7,k8,k9 : out std_logic_vector(5 downto 0);
pow2_div : out std_logic_vector(7 downto 0);
sector : out std_logic_vector(3 downto 0);
video_out: out std_logic
);
end keys_supervisor;
architecture ax309 of keys_supervisor is
signal fsm: natural range 0 to 7 := 0;
signal debounce_cnt: natural range 0 to 1023 :=0;
signal k1_reg: std_logic_vector(5 downto 0):=conv_std_logic_vector(-1,6);
signal k2_reg: std_logic_vector(5 downto 0):=conv_std_logic_vector(-1,6);
signal k3_reg: std_logic_vector(5 downto 0):=conv_std_logic_vector(-1,6);
signal k4_reg: std_logic_vector(5 downto 0):=conv_std_logic_vector(-1,6);
signal k5_reg: std_logic_vector(5 downto 0):=conv_std_logic_vector(8,6);
signal k6_reg: std_logic_vector(5 downto 0):=conv_std_logic_vector(-1,6);
signal k7_reg: std_logic_vector(5 downto 0):=conv_std_logic_vector(-1,6);
signal k8_reg: std_logic_vector(5 downto 0):=conv_std_logic_vector(-1,6);
signal k9_reg: std_logic_vector(5 downto 0):=conv_std_logic_vector(-1,6);
signal pow2_div_reg: std_logic_vector(7 downto 0):=conv_std_logic_vector(2,8);
signal sector_reg: std_logic_vector(3 downto 0):=conv_std_logic_vector(10,4);
signal video_out_reg: std_logic:='0';
begin
k1<=k1_reg; k2<=k2_reg; k3<=k3_reg;
k4<=k4_reg; k5<=k5_reg; k6<=k6_reg;
k7<=k7_reg; k8<=k8_reg; k9<=k9_reg;
pow2_div<=pow2_div_reg;
video_out<=video_out_reg;
sector<=sector_reg;
process(clk)
begin
if rising_edge(clk) and en='1' then
case fsm is
-- wait for press any control key
when 0 =>
if (key(0)='0')or(key(1)='0')or(key(2)='0')or(key(3)='0')or(key_rst='0')
then debounce_cnt<=0; fsm<=1;
end if;
-- debounce
when 1 =>
if debounce_cnt=500
then fsm<=2;
else debounce_cnt<=debounce_cnt+1;
end if;
-- change registers
when 2 =>
if (key(0)='0')and(sector_reg>1) then sector_reg<=sector_reg-1; end if;
if (key(1)='0')and(sector_reg<10) then sector_reg<=sector_reg+1; end if;
if (key(2)='0')and((k1_reg>55)or(k1_reg<10))and(sector_reg=1) then k1_reg<=k1_reg-1;end if;
if (key(2)='0')and((k2_reg>55)or(k2_reg<10))and(sector_reg=2) then k2_reg<=k2_reg-1;end if;
if (key(2)='0')and((k3_reg>55)or(k3_reg<10))and(sector_reg=3) then k3_reg<=k3_reg-1;end if;
if (key(2)='0')and((k4_reg>55)or(k4_reg<10))and(sector_reg=4) then k4_reg<=k4_reg-1;end if;
if (key(2)='0')and((k5_reg>55)or(k5_reg<10))and(sector_reg=5) then k5_reg<=k5_reg-1;end if;
if (key(2)='0')and((k6_reg>55)or(k6_reg<10))and(sector_reg=6) then k6_reg<=k6_reg-1;end if;
if (key(2)='0')and((k7_reg>55)or(k7_reg<10))and(sector_reg=7) then k7_reg<=k7_reg-1;end if;
if (key(2)='0')and((k8_reg>55)or(k8_reg<10))and(sector_reg=8) then k8_reg<=k8_reg-1;end if;
if (key(2)='0')and((k9_reg>55)or(k9_reg<10))and(sector_reg=9) then k9_reg<=k9_reg-1;end if;
if (key(2)='0')and(pow2_div_reg/=1)and(sector_reg=10) then pow2_div_reg<='0'&pow2_div_reg(7 downto 1);end if;
if (key(3)='0')and((k1_reg>54)or(k1_reg<9))and(sector_reg=1) then k1_reg<=k1_reg+1;end if;
if (key(3)='0')and((k2_reg>54)or(k2_reg<9))and(sector_reg=2) then k2_reg<=k2_reg+1;end if;
if (key(3)='0')and((k3_reg>54)or(k3_reg<9))and(sector_reg=3) then k3_reg<=k3_reg+1;end if;
if (key(3)='0')and((k4_reg>54)or(k4_reg<9))and(sector_reg=4) then k4_reg<=k4_reg+1;end if;
if (key(3)='0')and((k5_reg>54)or(k5_reg<9))and(sector_reg=5) then k5_reg<=k5_reg+1;end if;
if (key(3)='0')and((k6_reg>54)or(k6_reg<9))and(sector_reg=6) then k6_reg<=k6_reg+1;end if;
if (key(3)='0')and((k7_reg>54)or(k7_reg<9))and(sector_reg=7) then k7_reg<=k7_reg+1;end if;
if (key(3)='0')and((k8_reg>54)or(k8_reg<9))and(sector_reg=8) then k8_reg<=k8_reg+1;end if;
if (key(3)='0')and((k9_reg>54)or(k9_reg<9))and(sector_reg=9) then k9_reg<=k9_reg+1;end if;
if (key(3)='0')and(pow2_div_reg/=128)and(sector_reg=10) then pow2_div_reg<=pow2_div_reg(6 downto 0)&'0';end if;
if key_rst='0' then
video_out_reg<=not(video_out_reg);
end if;
fsm<=3;
-- wait for release all control keys
when 3 =>
if (key(0)='1')and(key(1)='1')and(key(2)='1')and(key(3)='1')and(key_rst='1')
then debounce_cnt<=0; fsm<=4;
end if;
-- debounce
when 4 =>
if debounce_cnt=500
then fsm<=0;
else debounce_cnt<=debounce_cnt+1;
end if;
when others => null;
end case;
end if;
end process;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity audiobuffer is
generic(word_length: integer:= 8);
port(
clk: in std_logic;
data_in: in std_logic_vector(word_length-1 downto 0);
data_out: out std_logic_vector(word_length-1 downto 0)
);
end audiobuffer;
|
<reponame>anserion/Hopfield_VHDL<gh_stars>0
------------------------------------------------------------------
--Copyright 2019 <NAME> (<EMAIL>)
--Licensed under the Apache License, Version 2.0 (the "License");
--you may not use this file except in compliance with the License.
--You may obtain a copy of the License at
-- http://www.apache.org/licenses/LICENSE-2.0
--Unless required by applicable law or agreed to in writing, software
--distributed under the License is distributed on an "AS IS" BASIS,
--WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--See the License for the specific language governing permissions and
--limitations under the License.
------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Engineer: <NAME> <<EMAIL>>
--
-- Description: vhdl description of sign activation neural function
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_signed.all;
entity sgn_function is
generic (bitwide:integer range 0 to 31:=8);
Port (
X: in std_logic_vector(bitwide-1 downto 0);
res: out std_logic
);
end sgn_function;
architecture Behavioral of sgn_function is
begin
res<='1' when X>0 else '0';
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity lab12_vlg_vec_tst is
end lab12_vlg_vec_tst;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cad<NAME> Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
<KEY>
`protect key_keyowner = "Synopsys", key_keyname= "<KEY>", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect key_keyowner = "Xilinx", key_keyname= "xilinxt_2017_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VELOCE-RSA", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 129920)
`protect data_block
P7q9GkARSt3k1Twtpc3ibC90P1J79fjroagtUd7fTFPjEVC1msq84pEZuNDB6tjk/k1raoleWwNr
7PR4fpVKmBx4W0Jnjhch1u45BxUazrNQpm4aXIQ/VbG6EORXy/yVVf9h4n37LLPLuuRl0RpWq5fF
fnPPl2UvFztPZNEBCDMTCwy9bdozneD058Q0xgZG1aQhTqpdvisJFmoUpGqduSf1uQ4IUX0EWUpc
KUyzfi3f/dNPTNmUqGKlLy3TSoi0MzUiGy3hphTfTpYGvkJhag7cN7/plXGVkR8CQB9a1JAy0EF2
1i2FYQe/TBVDFOjAOzn/8fpKgmxDRVnBcYhszlnOzEbIHtuzJ4/CyGBqkq5xR9IElOlqmyTPQRZm
c8oqFi2XEjvy7leOmEyAlKLECA5Gzb8ms6ijMe/gvWKSdGkgB+/aqNNVY1o943D4F0rmDE3D7/9z
9uIC0bScRt9xlVKRgbt0w3J3QgIOhHf27jVlrlHcmBeQhKSgUxwaNCGQUTcqN9IgP4NrCEnxAmcL
zX14D19p1WRLkiVH3eg2+KJLJTtsZlgjgVsfpWIKydKwR9pqRgBJqyDED4T191/Akn6Oc3oZehqZ
AHeLZLVT/jxHUoyMVag829hOz+HyuMtBXrMyZT2RjLsFf3i3ZszfzBXYuqYiqrik9HjHjn5GlAv0
8cy8sIeGhoWmoR2/GZdbOYMpYQYxf2so83vL75f1NDimOehKWYi1g35FWVFENoRlM4aphAeDfJnq
HSaVW8+lR/JcFflCYHflv+gZ3aqdtzFYDcTRPxXL1U4beXA1d09T4NHaO+/jCbMR1M7RpJVyZ5Q/
TlwmbQv58h87cBkXbppMkAaJUoyspq6/Kw5b9ErQV+4z44NHaN9+K57FA9K5ewB7yJ6N8Xdcfy3d
xLFgqBQ+fczPQ3P7vJlZYdPX7pJ5yRrCi9h9nu6h4S9h9AsDRByrUzUDE9RFlLxfMu+yZyPb9QSG
duNe0VJlB0goAjZQoAqDXSrVrz9EP0/1R8YyNzhSybzjoY9SN6yoABLvZ2lN9L54T+M0MPt/dx3O
5N3plOoqpgCu3aRdnCWRDJbFyF1kO5imq6IcjkMFsDU7nJt46vEL9/8lcDtt42AuUfQ/KlTekiZu
Aalj8aTnuCYJVE7bm6eIudyTXF2CBjMbXO1WTVIzhBOQJWGxieePstu71G5/kYEUNteRnSzCbdBu
1Q2Ike5ofSWcI7uaD4Z+6prygFiw5rZwkXIGXWT6wD9AYdmSf8m0/ljqgnY/SEkr9cYKp2GAnvH5
cYyJ3bOzdIGf/bXDRXRbHHKl9VmzHoBGOjwOVxFe5stftosoI5vRPeOAKS39W5apaBFdQP0Z7tHt
flUeUkjustEpBucHH7lY7objuqXwyovt1HgZTpXzwlndi3qSlyVQLvapHCzXFVL+73fCM44kxrwQ
jaf2T1VfTD5ZBdbQeX9pyLHCHIh6VpD+/kR4fIHjf4rYVb1gqOwSs3jPLwwayXUnvH6zBPBfgR0S
loie04/Pg9oci6sOSyTt0Rii9WoXGYsgtUEqPW62DjxexNrb+y458Yb+pFlcsXriigDlk2Y6qwot
1bdKPXZSzG4nesbye7vMhbYB+exBJMjSdmRDk6GdM/gq8Cg2oeqNBb0tVWNrwI/zGR9WkNfiQ13j
RxrY+hOkXOEnkjMemViKJmblwmzcOgD825ugoqvEKWFGNda2tnoXwODsoYaCnHgJgNWoQCcef0U2
xCoVGb0S6y9yLdsAXfkhliE0Y3nKdGoaWmQ0rFsOV/cUYIdcRVp8tJeDaPBEemeD55UYfmQTMcQT
2qudbCO5Ce1oPbE2uJH9/MFUfs7qw84/imwm6AoHDeEhqduN0MIUPsjceaEpi5jjf7Gc9rHOegvR
QE9mRv2+/DMQEROy31z1gLddJsyNGEUIDsUarmvV82IrCUPbdsJzqZ+sVQicBu85u/AQA8oTAo4Z
XkUTPpmqVDcns3gsm7jHuWC9SpYUmP0T12ULZXY+0+ikrldUP3++3v98/OQoCfbJTNEM4sw8peqi
nql5lADwMMn0JEjwsm6Bg3nGBsGBC5XpmyYfPRFklDFhWBZD6mZ+2MCsbJsI+2V6jKpDwCv0/Z7b
luplvgZhcacPmc15X1SilffZhBM1gNVVTP94rk8ydqOCz3igQl0GPHPMd4k/BYcKlCx834v+VVCC
Eev5kZsaqlAd3TgkzlonVCyL+BUW5WQ1B6gzvO+B0YdwA59joPhjnfvq4yYXmMTcx1jXLpJHhPbs
Xdvr7Sqyafg1QPzwoVrw1ORfcQZcagD6LKuIOfW3jFTjtvYpdLNb0xYQBajvFfBklhQ7tILjeK6q
jgoDlsqQ7+K/xsfolf8eUcD1e8s+SIcbv220GczrQZpTiF/UF6BHX8S8KLI2lLll21vp8r54zsIi
Ouk1wrr6wcPgU3qrJhY/1kEhXKDDRAtMyWvdvO+ABPpAguxI4Qn2bCdlWU2QsKaDMwunBujEO8mZ
jZcObaJf9OuLbDSKBOLStKhz6fOq37DORyD1LgdKMJY60lbUrFr7x7rWGvmS4EDk/7RFoEW9mZE/
WtHCZsDC/HtUXfoj7wY6lj5ab3SlioRGP2murFPsNfXCNwwrOUfFpPWMcdddiQ62Uxuqeg7UYkam
/NF30Tjkoo/3IXTHwsAIRjRZGUZ3JgRXRUC6a1kb2HwndmkYW5LJTUlWI5qFjLCjLERhiRylCPpS
qWvv9+8JEpKc8iah5cPoIDhwiCTjniUV8V/d6zh/SLKycjR0PfPDYL7mtNHtSXwHUXCzWIg8cJnS
GoXkOsVJpbIhCEq8YOOYDN4/Pw8Htzh45f1BvZjWR9/Fa6/K/ydPGRY2qmtcamRHDjrhpsYf+sKC
G7aqFrupVc17sU7WYWxGFYARKaTZZSlS9BDSDOTNpPk1StXYu8zyzdpacFpFuFe+o9HlXbE4LiD3
oQRXYfYgirUUnaKkHNFUkX0jLBuGkgack/nlkBliiL9PAGH95g+QJzrdavMYZVFh2/mAhnQYpdNg
Bt9S5VHoO+C0k6PDvtXgT31EjLl0GnsCTPBDETex0uFBxdJER5T6S/ndkjNRcnnz60V+Q8X09Al6
E0Pl1wFp2ZTpTrSqIICF14Gj6YLFsSpVnPWIcgWGB26rDdnMhnGZ6suQEtrxxK5PENUAaR/1chic
0JYv+E4KOcRA04AiZxcOBKp9NLfjiIFIvjFSmwhFLmF1dJXVwXx3vkKDFGRu/8ZnuEOQWklD1kHY
gHNnBNI72yX0ZXg7kqXrlQ86Vo99NNrLZ610QkTNQj0zaxqK4pokguQcCJ1Z3SPexJsRcjFrN1m8
64W8jeybZHFLzfRGWnY7Z+8yKKX17TZStOdUWwXaf98ajE5HHlkFpGD7+rQqQp5CUIYx3xEeAmRk
kB51g0kKSKdqZqiIrZ9GD4jXbzVJpjaYTUX4XOpVWVNV83IHvM7gP7svcj2yaFidWZI6k8AO2uVv
QnLhSpDpxn8AtMJLZ70R3wx+wCpsqfrikkR4flS1/Ijr66vqJbwFuAYnS1soCbe0x33v+JJYo6bd
h8823N9CiYMM/4v/SPx1Igp+KBfpyfqYK8C2q5HtuVlJ9HgOaiPrGlIjfrRtwikUcv2mIBbM8Obj
hc5LD4V3hhtCOs/QrFbiFZuPgyusmtaGc/XVvFZHOwVFM7WsnStu4HT6D93rIbbsSmaMbMobSb4Q
xyViSDSiRmKmFgD4gZMrXzX+2sN4uCmFoB2KUPBj6p+ko/A3HsaR+jJwXDK8kMMB2ryoNtN4zTkN
Evf/kUdLTLux2PBWRJAyTPGAttAY/jTM892n06SUbWJaKYAEAa2r13qiY6IUgMKNZb3V841kWBGd
FawNftAYylbuO+Loiwq4NNkkNlbV78DJ75bsQj7S2+E/DXrQET/RMVtQ8uxficH6VChVZhqC5PHD
kf7w5cZB7JN734DdPHf3ulFidJ/RVoseAhlyR41B4vBxcc68eeHbZpxdTx89AoZf0XdjxHbC3Zzc
pwID+ignTC8WGu6Ia7KEgOxQ4qOTGfgOq3FjLOM0RLEbAtAt7hTwayA5kpAAgo/22gtrHggV84MG
doNQstGQt4m1YBJyPYpWXTigGpsmIc/C9F2Al7ffJ5klGjyR7opkSmQB621KZtbEygWLFo3oIMeH
f5yyjHIEZUjXpcnGEXeV3PXq38akgrgSGJfvGJRNnP/QLO2u0qcD0Hpq/zU3OjT5Tjlr1YGhdRY0
6VqXtAyeBPiyBDVMAa1NZXBWSBD293RwoilFqSITEODHSUXoaQGIx6IuneO6kKABHmUMKNecKpzf
8BZDiA9Lhhm2wKVwLgpFXUDIDBRkm4/Dp+LKNcPKIrIR8q1BfmoM+opBF2xEaIWjauSfFr5u4IyN
+TLUIqxzdYUT+heaDXVsyGrvuflWviiXuiQnxycY5z0HsM4AhtOkiHqnEc1y7aN54vo4Kef0KzH8
wGBxaHoJTvjCiUUeeep8RCMHEnpFTN5oqt6RdckJdgmaFI/KXcy/m6mQLbXtDtqZAZKApIxWhWig
X1zRuYfrFn09KwT93sHSzRU43xugH+6XYiwdLLVF1/mRdPRkmatsjhLUQS9dj1aypQdGZSM0urI6
UeF4yv0dXsvKLwxmmaEQC21OtmE7dH4JwSk6OTeTJ31dDqavt/diFKA9VUTpPsAUC6Cos3Rna2le
Vi4Os4MB9fJrAquzPBL+6H17ZmDMExrtedMIvlGiulU0ddVVsfnH9mBdcQRPjGf551Q8G7eaUv8m
b9S0xQSh0yeo+5psNQQEpIIGP0Gr+3WmOzzYF9tFo1kdSrjOPDElgo9MQmCL7P8h+lu9LcLaU/MP
ytQwUpUuKcEqUFkRBDDoqu+GxAhX107kn4ZOULbG31KWS4/0MSMIRFXqzVUg7d+NUwJLXTnNiclm
EwBChPI6QMOfMT7IIpZHlU6heoA2V79L8LNeaxnJXFG9eLSTwktNfonBokLxQ41475CfHvfgdYQp
SLQ+CclAHkcZSzRXNfJHUt7firaCT/vWY3DWejzVnwi2a6W4yzE3+BwTBjgv4EZB86TgVqeFYky3
OfIizfPzkGp8udMC7dcmrV7O0kKFsJF2gK2ponD2uSCFJfeP1mF2shgJOdnWwR2VYI7iwkWB7vKM
FQolJyEG2J+JAYDP6RY84V67JfHUooA4dyAyNQq2zkKN4LB7c+1wTTTXPM4/tt31SYNRjb/mUB6P
wXrCeI4XJcMXqM0756Ysq4kSpRsF/L1lB3SuY6eBIBs5ky/QNxd1+nBNzCVI0iyGvfDNHy6njZ8Z
1ypMSS9Bt7iGumSbIpn+npkwffS6uyGJ49RsB5vBnyUv4cPGhSNx7iowr2nknFL36czuFnvj0Up4
KnwmioOMhxwrRRRgjTniEos+t+6jpHNfu+0j2e3K1+ODY0nLfXPs9gEmncGlYND3pkKdDpN+fVtm
GcJp7313eifu2W3Zz6m6ZwwFzOfbQuA2XGvWzHtr5Aln1dBDo9JjozxiqW4XRSWUMLgVojMlWulS
gU7QEhnVWM7wJibHd417tC86+KaYTxcGPzJwBkmMOpjcxEMWV1Oq+uGOxnmJgINXuRib1y5myaUn
2efTaF5vLTXqjVK04y+JEYdJ9SzWHq9Tj6oXN7BNkz+WbO5FJCOLCDsG/ePv778r0OYWF2stUiXf
4LHeSF7OZjKwxyRZpN/bsKTkubNT5LHBW7QwfUEUFRMiUIRo9Ad24NaFTS+IBlMo/Wbs45xVo52O
LgwOnn+77c9bhXGuNx7DU80m3/cqYrglMAdJVvU96WRcMS9ghfdqdMPZ6GbgHZFKHZRO1ecEcDYb
QLYAbqtOvc3n5uM/TIDDMLrexq1uHuuCq+y5TzXSlmehwqy9j/Rfrvlf8+qazRm0i01LX81ocX2t
vKSVGY9eXda6T4P5zqWEzeOaUyJbajcAqnRxp26ZXcuRYURGR7989XkA5FSlO60xOAWteodIUS7C
8nIPddIF+YU6dD7HXQnj9qYEzEGrPgJEdZwWaFTOOV1ONTtT6vTAIrPwjxdhxNs/rp8GOnPU3Jim
hVZ0JBotIQkECb+oqWNRX/sFCdUUP6FOS28Ydl/64AOqDbFJzwaWOI+LgjZDno48SRTZc73TUOk+
1ckNLqFLe2+GLfzDQa63E8vJfXY0Lhb5dYFBHP/wK1wQgaEcFUE+R0xEydceXYx+ysnUXCGCWZd3
wvwBxE1+bRHHeIeaoUwokaFTFnXjU3r7bIbrJUmCUiDNxz6dIHJPgoVYwAKLrX7X+0jseuULbZht
6sM3nBqWa1sYj/lt+QN/XeE8BZpTxcoEypXuEtwtISCu0itDxeRYa3jbpgnnhMAo+u2p6p0gpeO+
HyrEmw+S2su3pyopFRD8JjEK/aNjud/b0FrzJzKcCdBQ5npwtUv2Fk837iPAltoKneexUw+8QaTq
k4yqk7bHCPNeRbReuR1XGwdjhmQp29Pj7edZjrXy+1IfJKNAfLHrF9rkLGOnK5uynXG7w7YI0VeF
38LCMxCUuIIOm8lT5XLdD2Yb8V417yQoQYyWCy6Rjmd72dZ6f6DD41kf3txsLoqneeSLAG4Kw7vT
HoXhBbyywWIDjIohnVTG251yjJeriRh1hWwDtF2yWpwRhvLQ7yJsc9+/qGUqV4RjfDsyTrvDiw3Z
d7b4PndK0MwpTP/RNhNZuYO8ux8prUpTtF7DlVCYWg8egKQUlblrcAiBfZaAY1b3txy7gmDS83bz
JeMzYg6apQH88zw08QMYJyuHQJ2C7/ZxRF8UKoyyUzrRLWk0IdPEXKzKH359Goq9GsPMfTg669OQ
sD56Jbi8SEIEWcHD5CCd6N1IPRKOAK+MOKEdICRf6v/DZJf3uU9+ziT64kma8DjCH1/JBCQvTCU1
O4eIhQrTduLhOiD2/1V+ksKeZ4EYF7SEaZTxdtexsS9LF8bb4GQAmwQQS4dMjClgq5U54GuYGkjg
ZBIU5hspc2j0xVBjY73BYsZ55MuCOlh1gphJbHxSNhIVspBEFloeBvMtSPKqQ/jjmfdfL8Ictb8L
LZRLz9z/Drymee31wzKL6lLs/LWmytxcPzYTMH3DN3gMQrp9/NW/uaABYSlewjtluOv9Vk+GzmcO
n/395sf6hcVOfmb5SVO8YH9pYFSjRcOX5/Rs0Xu7zCieTSetRt+APdDIpgAWUZZqBa6v2PM2jdjL
4Pe4RAatmi1+iA0O4OT+u1cmJ9fuEAS29DkgOv4WPgBH7MdsNJDjZLWFsxH3xpFqoZMlZy6xrMAk
UC137s8GEwXmsFiRkQHikrSpKITt1n59lE/azs95pM6D/hlQ/Qgl5AP1kQbDASCzkgxN7gHbuMAD
aJEedEkUWKegE6ddRNxWjTJOLIhAfJTCF0nbV+zE3BRvEFpX+q/NXWN2tac8lmFHRLqWzX8bQI3T
W9ai544y+VLDtDO8eNVStFfrebq8f/cB6KXwCU8U2YgsFrE+l1aZ59tUj944JMIf+0kqsyMvrMxE
lJKVybJaOEoE8HwAmQQhNWmbdyvF0JHJ5xm4rzgHlptLKKNihjb9w8rW83wswsdlcDP52ZAFwt1d
YZQhHoxJ/vNvxHZ5iGHtTp8ksL+tjdz2qEvh8Bi+zwGCHVuranp4Wjm3rgzuB9HYyPLdO7XuzRyC
zkc+01LPjV2d16/jBYPx6/ZOePJjy5vlV6iBH6kaayMNsMYx0AtGEsIDQBVotCbIwu9Jyf1scd2A
EJx9Gn/jw4NKrhYJgPi0qKzMeJuPp5fU2qF6rvPJpjv0HXb5jlUwOcrO2ioVfeItuPFivklQDCIc
QXhdip/mOQzv8pEEjLWPqI+ASEi6Ut5r4zZo4BACls/CU0O/7m90/HMK9CpiZUEp/q/weNre0aSa
F8GSKd1v6rJM4Dsko2h7/QBRE17KI5edpTloOMZ4sDE4ZlR6pzbwcZwCcs+Ogzg3pSYYaL2zKL3/
ajOosTzHwv4wRZll/kY4raOJL5U4F6yWl7FnRe7yZNCyvhZcUNn6vp+BGrstJJAuhM46obAs0asi
HEMzQbbU2FzOv+AaCoMavG5WQYV9PoOz0Lmz4L0UMY9T0rKzDBI58BCV+OnQU9mkWFWSVp0KmheS
pI6EBVTxDLo1xRlrwqjBFQLijyNMO3soJb6h/tJXMR71Ay+4wbYV/fnPUMcGEvbIzDhSUFOrMzY3
GwP38Kqhd343Noa0lflPiluACh4Pyxvi6ea+7wHFeI8FIGf3zHBArK8AjnhK2EnifjQiS/Da9veR
Ps1p0VsuL7yNVw4xzeMjs2puIZcx048TZPjy6iKbviXfrniOKNbIb7rdCNWOEKvc/wxN4UDlmss+
NXfLnexdB91eS0A5n8btWnqj1AYFXnhwYL5cNk+fP1rC06cw9u1QiRuS5mpUmhMsMcjzqJ4Ohyjd
TLe4kyXqeYWcMYjG3dE4x7NMEOI7iAlc7Tgz0FAzLkRbZ4bRWQFkY4u7oGCfJqGCKA9RJOzSPwvo
PujKApmy3yhpbDbUK9clSwCtOLJqEqOWaFLz9YKTk13HSwxpCTPcA7KY6f796JoM6ZKHjJmQeXzd
aPYMrnsuTArUQC2IhlA/1dmg1T4DsfJYuuOdiHgJrAozzljYPaDCugcbpOuwahAsEZ7bCOf3oBvK
SPTucAzcP0p9gN4B94CXoRC0TZ+TJT+apQwXHwXyoJy/KXDT7q/hIqMVZq9VG/WA6c1byh17JIL3
Xfyc5zXWE5CylOgQeheBi3BDnlXOAYNLTdAlnkdlOBTde2xmv1NjnKLeMf6o4QHc3K9GmkvN2kUi
3a2+NVuLVve4vNHO3sNd/eYoIfo/DOlYhkHypKFRTZrJKSjnaFWYAzjvNYj/YOG+lMPPO1GFWryB
lUnrUUh1Sjfa1/dQKG8PiG9zo+NNbyj+jzwp2J5rPRaJq05mzH8DS2FLuuS6liCt0oTsUq8Ya3Cb
LUH3IO8wZWMZ7nIL9bCnh7MqJZRfSFsZS+WbAJqJqeBZqcG7swKqtY/F7JZiQ7Vv0CP3ElVsZElX
74ao43F9zbdwCkWWOpqdNJHeq6IlQ4E4UZP5OYbnDyoIW1D+1QmpIY94uYWJQ7E/ds2dOkgNBnLz
0dorZInEDT3HHuAwk7oK2SbehbsusLzDmaIF7pNe/Ttqa0w+IYd/A3PNnuqb3k8Um83x7hW42wlJ
e0HVIgWFJH6alFJ8uDfFv1tpgZy+7ITYG6YJkHPtWKYi0yg2Mz2EZW3UZ3UgcaeKOGDB8OVtT+Vs
0lBci0HjawRznDQ8L0/2FGjG1lAsPC0CLCImzAqJoMG9CcNVVnCZk7x/9YuvXc7Z3tVddoZw0tip
tgVFgFve+GfMK64fnRPrlVLqGPnaYiJRWJCRFy+iU3Da16sddJudHrJPWtxoFdW/NTuOU/uJskLl
JIYnhs2I0k/24+ZlbwjRqPmOP1LEC3KOsiX4znwC4uTOvR+XkzbVd3uuT2jgGrv/XkBn1j1o5QuQ
8IzfrnwobISlsO7BqiaKlW9OAaM0P33y7cqyNRqSH2s0czCWd12Q92KRcfSz7ZjB5TDL6zkFQykt
w9C+taSFJAUPyqnIPik8Smble9OOi0wlfq6s8R6F41JqFs1BytUePZbuG8K68DtrC67iyrpf2otR
qtC8sGGZlQ5oqvaveYSXn4Vv9kunGGD4BtFdwnCIR0lp0//MO4YrK6G/MKMEIeYwZPOT45qGUfHq
tzCspgTcg4hGjWsJl4QLS2S9SQh9erTkWvtUOCTK+LcevvJgZgFJmOHphm1vx4lFQkO7SxiGFDSm
LsvFe7miR1W7Elsr7dAykKuXr4NURYZWUgw2rj6NYlb0EtDHDyk5ufjZYfcAr0HGzsUm7r3dsd95
IfeJrBfZJy0Wd0DEIVYeXVV+h/KlUIHTwIWWchmABjYW+OSR0PXvYcS5KzKxJaMVGtwPVedBZ3T+
wFI6XhLVw9NTZWM1zUL0DvpFYShJHcq75JdEtJaNoOBEICm8suzZwYqBshVzlE7s0GNsyCYKvzDw
NOSXtf52k6casEmu8hiSPhX5KKZoZJsFTF0mm8rGI6JGoI+L1ayK4FJBIOqgve+4j9cCddFS1RuU
dS/cxufL5WJVTEA99DWqwA5nTtOHLNQXyQNmqPqO5CuBWs43rvZ8UPy62DHBkXKCXZHkaSsCfvvA
4Upz0zAaZQIBb8VgBKOreTSoBZCilgeQTvO6Hp2wTfmVGGULMakjQnmorApWmcCRi8Vp5Q5/eZUl
EJLAAoOpICeG0PqcHmozJmMyPphk0huvNOKrBL3N84kURb7cXovJTGFHEV8dEl9ME1qJufOmCvYR
KUBgBAjyjUUl7YUXYn/cWkXo5P5QsY3IXfHUyTALwanWwjv1ws0e2MlU1oEDQF57dsPgwq/RxmaB
U4K1md3U5UalrFnR3V7ZIqj80mrRuzuj/uZciCVJ68o1h5sOFgev1HgUCuZ7d5zx4haOaLllF44n
ofE9JsGBE7yplnKMmpQ+xBaOd5maSnPWLbxBRXDOLFTcMwFwi1EamYJeCkjCkC2vsoPaQ+1yZtoW
E1NpPp03A/MlDA4pc3AEFXctSCLTwWJR/n8K46iOL1TMntXf4r6yPpMtyWZBUjjXgPyiCMc2HtjO
EulYoya6ZgCgv6jCIpFT1hPGWjws3DEBoNEOx/I8qFHRr+lABafQKKbk8pOPso0NK00GVyr28uUF
6wmmxLLelgQNHZa4eYsB4++3IyXXUlDkCxchsYhc6ur1DGNhn+kIUp/zwkkfI1c4VdbRZ35IJl65
LZXNtxXF1DhMDt2riG/s9lVpR7s08G0ETcSRMvYkrkVmvdykD7zKkLdwNXU7lQFq4hwTDsrqiQVI
KFFD76bVMc0yXkQcM2h5Sl72Huoo4/sXUPtJgltseaJGLZGfGK1OpyHuR72ZPdWuL3nw1EjaMFEv
qDj3i8j2Pd3dOBfDs4nfIyKZpmbfYO2xnyYkCddeX9ajgxGl7ZPSwmOloc9Zmk4UWL2LdNZCOOyn
r1i01mbxmUcNn2JgYhZI0WR5eb4UO9ip09JhvNm3wWNOAs22CatdoXH4A0QYr9wkm2Nwi4kOgQwm
77P2Mh/spnTGdti7wm0XJA2UJbazBMzzGUaS9Zmpv2seArMl+bXXLCnsqQNofRpgN9+hwoxmvwTK
PpgpbWKaAbQRKwx0tLhUeOQw/wjif39L1o17GzC8gXwml9vr+azLjeEsCVLFM+YSmGfhggTMCk5o
f5Yc5c4xyxf+QHUGCZKsWqsFKeCxsPMdd1joeKyyaM19i4JAlEZJaAiN2/ouEmfoExMVj1NccmEw
DouDN2oCEAVwZYkK9j++OzBrKqWdlmoiuC7A68aajFmmw3HOHed81gSArxyI3u+6SvXbSrdUDRLQ
XFrDnNK/bZGEculwZ01sR1JldenuCQhx7p3tL/3l+LQE3UamXMHTxctqoUJXfJ3Q9VhPUWZj2GBT
B7svCXdw2jIiFOAIT/HpTowXxNSP74Uy+XAajYZftUPHmbgqj3Ab0FZrtS9LlrMX2I22QOOcrQnN
XEpKtME3p4bDLbExgyitas9IB+qRMG1pH6zCrBY/kIRhwnNci7KfdVLdZHiRTk/S34Bv9WXRhmen
1f9PA5JoLW+Zt+SDyIqRMvYwlbB2R7pHJ8tHMZpAMB7Uhn+UUN4YSC/1l036ovpV3NwR7SwjWsVK
NkNoabr1f39Fz04tPZhSM6whUzYH8H50JikahwnPSMuK7//fWdKih47yFaBNudJzJY9gSLgJiGl4
sSdYqwBGLr5PRbF9F3fbOaXCPxrRzgbg42oLJJez7EpdhgrdIzXz/Xr176E5AHgm7lzlAMEFfUgc
Do3l4hfbLXh2k5Z3smfl2q1Ve1mXYB1tNW3ScZhJ/owUj3ixaiGDmV0PT5F8uRy3q4Myndf+ZDPT
eJaTB8mVfJRxZqPDesqgbbwJqagE0D54vNgz/UcyqBgK+SuFw2gbKPgKUaepZgnyARCdaQf+0ZfZ
4Zj7vD+wXgYbFmvGWBpqCmkkm5le3/93sQOaaVy39lfYktJcC9qKczv7QsZRmWe9TU9luvo2agzy
0IxnKPGVmkAj+HP9WYACmQEJobRDLPKSi9yGVb27VYLyBniYmLFXF0uwjqgre82VF6J77y+nGbwN
2YHpXAbpPjX/l9ElcNadgNEG11aFu1ewsSXaUEH1rIqSTOHkcQ4xlwM3pWW8NEZ1g3MkNwCr5CUK
q9vuhykdktawVeD2oNmF/+Qqm7TZyAOCQeCeBXhqWnnL0/uqpSWn3YNC6b5At+khEfzLiK7/Xnph
5lxFXnAL1pAWKCuh2XwqAeBu+YvR5yhlaFOQAvH41t9f01lvj+0BATQ265wFvv0hN2pE5Un72ZN8
KmZW5h2IqFrOFkCPaeg5UyyAMAibDeGVwaTL3SiOvgP+xoYu3BTbtfH+Gph0oVwrbearU8bY0bZm
DLZvqxUgZpCtVGRcO8lDMGdNLnxnPGxtuF0xvQtXwsY2jk1AI9WMilJVagih307UCI00QsacjBqb
Ug7aOpY5Elou5URXu7Ni5IVW0Jd04atOkYtU51jBiD6dYG2eSHQnUwRXYfh1fODichO7k5EdoOCD
anKlYU9VDVaHXLqjrZ3K+VN40bajq99efkzzjvTy55RN8OuTqhmt4XLN9kOB6wHjvww6JWr4B8a7
/84u7s2zH36mNUTXpFgFDuEQOe4mNWGscguj1ocQJrLz1aDJGLIUXmu3rOKpD9gfzVXyF0Oio5YA
WsrQJysvOjJrPQXN30k16gQYIDmPTW1Lsqk1b1kjPpqJicC2igPfjPxJ4xGaVTOYnSgeHudW/cxk
1Rdfl866VNGKV3J7R1DX+vGB1veC2POLWwGkwvYygq/uX09BVeAtOAZI6Yo1rDW4xWGNRqm6GCvL
U8PW0a8kvMnRdFkvWLI+G5TMV1IBGecLGIv09EN+KF3IMA+5/clnzKkF12O5YGQYro5V4Jmrm0xk
WBjlUkHfvWNBw2p2f0q7MYkwjlmJodmVQFnW4fZwYYbtCJGLl4LlYC0DorBixyCzvXB4ioTlM/Fu
PyluD9PgMdUSZkQfnXtKVlIQ8SAJ16aR4SSt5TA2ZBDV0H7X2ykHY/BQXtMl0jvWMxGG0Ekiby4J
3IHT4/XSaG+5o6KHgH4gXWGYrjmH3/jqV8avQrKO9GvZ66/8QXtVRaQAKIl883BP4OeXsGh6CzdT
d/rs9fs4WGXrQBGAg/cJ3/CbXEghAXo5xiAPJ0E9SOASZZwpIJYXVqPPc3SA0Yi2MVwrn0Zor4mE
YtGyJZoxQ+NWpNJ1E4DOoRo0wcCnORIPMCCc50Avr7M5UEUSTKKGs8D/AIGw+UsDkiw/KNOSUola
ucU9MigmzcpU/7N++5/cE0y/X5k+CSB4LH9tRtmyzi/Vi+6V96nya2Xiv38k6NDU+0TB4tMdDmnp
ovb1wRKEAJH0//iP1fCkN2EmjXl5odtZGtw34rdMcjU1q8A6Rw0Srthryd5z4iMYsE15eARbC/xH
U3kr07zTq0TbcFklSo8QWF+3B02OTKOe8FzBrZVdprOA3KDkNh3iMTvdxm2G/4fnZgfXK6XZXk3u
/TUAceTqJ84WF06rRtUfH65oypI+cHies5ZVzDg4ceFSKw8BZDNRhA1+K4Kq0DgHv6S1NXW8Xz8n
px7DitEe7f6c0Jg08rNlJ23uycR4Shh3B3K6xsABxbzWw9dXi5lDdP2PX0zoJSSqBQOBGXlmo9ka
YGDs+W6gohy9Zfc45B8T/MQStgvthSWXufQRq0QpZqNE9d5/lDHCusMMtV+9r0R3hvspOf8S1wAY
UrEVi00ax1BGaf6sn2hvEPc1Izsbu+qeIS7tz+vL+MX0hyjRVNJLvwwQULnX1qlmxskCONfwKcTP
j9Gqn5WM5+ukd6dMVOB0VuEvGfqXILkU/QH9+ujcZVzyzyqFBUfq/CAmeey6DbLp1hdok/NDWdxh
CFydDyMoHwVT5tvQ36k8/9alH1bN85OmLZd3M9KWS5/vhfYle/pF2WiM+1Y+K7gc81xIySIC6Psf
NUNEMxqxLNn0+QCcPTkBTKJq8JB1jlI7EYVLf8NY+Tg9gJ6suJKCJXv/8SFGx8Y/jN9WUfafL5rV
CpkdHmNeBw9uSOpiZdJ9b1yfvwIhZZvUgwf881xocb3GcgiV9kMOHcVKrJgOWvYIf+9grzhHX/6a
gQUnVGcauO0umDdn6sn8YBoUEllA0ML84GOUT3QBLtRfYHYWtDXXrzIY09slxIRhmo4q8WmWWHNZ
wzSHMNGJOl/vODwATcxz37qRUYAkxVaMxzUMXW7ROwd0oNjnU2Gf/xULrOCnMpoUelpF/dkO83KS
hpuUgVbrggMw2c/9bd06xnDO/BuJ+0PtAcTbqDkgkkZL5JtTBok8FA7bWB5yVPMuLsn0fExmBTy8
wFlteGgGnyoYpoUqnxfJhBP8EslK1sPDZDAYVS8pb/In6olyQA8/uACTUVfdy0rVEKFkQ8uHnXAv
OYF6Z2CCFEbU00Zr7nA58TRsZrez6NZAiopxHPTSUb3wMjGfX14l26nPHSHtpLWtqtmQvVetvLqi
4EHhdIjwyrrTsLGXCyONYnz56dDqu/vszGanIg0WWuxb4EhdwMKmAlDpWi98KubyJquY5By/edvq
hgAKIxPdpkD2ZA9y/33mUE5TcqNrXTw9MFeFu/x0mbUwBiFR3BLPlp/fMZYtMq45aOqQ+0k2/63p
7wMPTZsCkU4Lb6/RxpXsfWcDfVc7ppZR9C90dK6o6nkTfVN5GimU3Id7U68q9veRuc2nklKLqAkO
4yxZBpBljbCtJ0Cgpe2b9yP0SOjqYB+dpIUuv/xpgWZF7jq3FjyewEqCPENo3xzBToD802vxocCN
R/BWRX4LVtGyWW1K1EN29hKZcKeuFKaUQNc3//Ew9eLlmigjemYVf1yw7BImqdiYDepc5oQ3BZQm
AsOjQB5MDKPl24UEiHypsvhbIXqS/2oGRxYbn+H4mtCfCxDMIyO2x8R/zh5VJtsLTpTCTtUwex8P
WBMInHXU3hM/qzAALEPebtufI9qfMD5dvS2P6FGchS5AavsWLpTizgb/qRMt39e7fEx/I3OqDUH0
zBn66URur2ZQE9KEj+lh6CW43XO4LL9YdA8e4OQMxFHXU7OBAEHpUxCCy7pseG8J1DEscE2pyYbx
97/gkHH1EPFwoL6SCFVoo4FF04lciRn/cL71dcs5jLoRLc1UgMN0vria1Gs20C/a2mbK5o4qn05D
Qn5OqRmXy6LYg44EaRP2x5kKSqotREU6wc0cknLjjOSk3cWIH4rElXmXrOsJdJ0K7Jzp2zMdxy+z
3v4Z3SMadfaBiPCjYRtSqol2A3R2h6rLa//6JpePT9QWUAoCLgHX/U2Y7xqJwJ1HAuLhXXP2h9zx
Z9zKRFj1hrKFvdSXCAU/9LfK9T+nEgJkCFUgnjEQaXlIs+3yEXsTDMJGgC6kbTorwBzyjUUE/Nx6
Uf5jvJhk/ZOSedjcYDqgQ2qUiU7u0jibsdQISfGAe7muYqRbBuFgNXcXwDY0fME7ZwvKcU45Snz+
n64ahY5gG7AEnFrklVcEysudf0xKwgFTYCznn+Vs9IhBwUKlM1krjhJ8C9nfjUEl6+CsA0T1YQtl
RPzh49jNsZO4aW0MnGeZDDHKsWKj5Um5rBNTrP09155AzVm2SQy/W381AaGpGNJ8KbV5jPwZvhYN
Er8aXlrqJYMPun/A60QXDT/0ro3N0qrtJ42HOnX4EDaUbeDY5TdvDFlx2zOYpBlrJrNDY7JoL4FU
fH0a3nJ1m2HdnfJVr68H3qsCwwGkm2ptFpYVSBYZiM9GIH1qChZQsXEMOmw/1QvQyClsuerEWYlO
eIjRzhq+AMqrc1OyHNV53mf0yBNdu10WSmchdjbc8TjyHUsHAbFwBZbLybYsKwGh0vWOkWAf5ZwF
7iMqBxMMCFyipl8+LEgQ2+T1Zs8uyrdR/JzbvLFWrC3/xeXPlkCjPAfRdBMg3W3HyY5cAy+cpsJL
82EatgzwqP4dGgTGKQ+M/K+PylTAc6Cq6FEGP/lCFhqmLeRWFSb8Wy1pxXSjXJ7f2b872l+OOki7
wuvdKWSERrQNceu+mILUqLK3vLjb8UiHUXjePdLS9KZiPpsrLWx3p8owrjqDbueVhYjydfDlCHAd
X85aP2y9bTayBkfvEF1crtB+GKgQcEvnqBI4xdKhR0A661IqS44HEu3nDRZ1u/Ll1LEZOF0zzSFe
auRbIc85LoihuV5YQf5pFVodT5c74ukpnG0GkmDP/ERSdqUdRO9TYkPP5kRc4OMJet73UFzTOST4
jLnjMqq1auF0V7kYp12ztijog6hkdKkr/X5gK/R530xvyYH66l+WCJOJkjxWC7AZG9Tt7t/reogl
4fRuZ7uuZtaRDGE9JrbI/jj3DvZ9takyWbOgKw/JOBOVvgQWRvRTZwtb1oyfktFVlE2xeu1cTMtX
SfooNdq8MkMlLVG3mp9mZAkGbZtbh+7Srwc6Ps3PvLZ4zzcC9/ti0p0oj2+D/N3wShks25iV3HAw
MazR+sZZAWQol7ItPTmJG0G9EGROnak0PRYiD8/aqEzpirTeNN5AUA/XJafoYase9e1E4z5RG+KU
0D7O5dA+8HafCWsosS0F+BxOJTbw+ZqE+qYqTJzsaP7AO6UaRaDppuAhqum9DURty+Y/87MVc9kL
K6kKmUYzyzMK5a3XjTcg6yqOhQWLGf/3UMg1lvk6kM2lnI/nH3iC80nD6Nt8nWMvWaPGcv0cuDtq
dOKnN4fud+Lj787w73SuIkS2EHLAHMdAzc7FTFVWAZY+nahXG/L4P34w6xQNYbcJuIWaAv41VMnf
49sTCwNIczyUM+XJUEb+e8JwSSQ+Pm4deFhwDQUprcRzELmXvrkx74Iw329vN9yKMloouCo1HZLK
CkKpcIl0JVmeT2yA758y4DfMZDkqZB2yNkXdJJNyOyWrYYOyQO6wd4Pp1OVqjKrj+Hi17rXklCzh
l4mtSf2PB1DMA7g4Jzpysci23PFEyWqXoS6SPH79AALpPMDrLQXyUs0SqI5tS7NZr+1rUKBqQxD3
DkweLrEoHPVzUcOeCvGlE/uTuebvuFrofe5IqkbaUR1FYF8WBsy3z4+fu9a5c8KjPDfUuk6OC/GD
gUzqSxNaViG6KHfZx+NrI2CplRtKBL6gYd3k199a03gKR18aOrQHUwAcrPxYgZlCKGuycsQtcOkh
JMRNNk9cc49Oqp5lH7WRcqvO/HNVAjHCLkyIHo6jdThzyC80pv5qBBPEYaCxbcjmgY+vNfFnrVL4
xSAXEtKLQTkH0fiLl4rsv+a47+/lbfQvw7Ugl9h8oZkUjJGvdmtvlYYdLzkEGdZYts3RKXRHsvqZ
qELvmIYw5jB6sqx5yJwGsM48DnbQs+WEk2D3zAbAFwUEnwlZftueJe6z0iIJi3k+0BwPVUgCDe4s
y7sJXoO7SGD3HA7XcT+sXQebPSpntPvi1FyuBxtpFN28c7z9NoU0VpjXCQsSjwNZaYBek0b+wNYK
ADMxNKpYm5GSHRbeDf2sNaFdi/xYph1GM8Y6LxdpIAuCP5Vp+puasnYdl5tfF6wTuJeabq22rjef
+qsIPXVq/xpbrMIQuG9I65E/apOnp0Fpuc0x5eD0uKLUCXa5z6C6ZLDozxC7cpIhX8p4vS3QrWnc
4VPbEjYdjMd/BFVHU1tV+93Idnep3qJgi6MBYu+6BrzGGFB8eJUqMhqhRvQ3vGr5aLwH5qNsSyy3
Ty1kbfxu/0FzVJSQan/5AS3KWZKP5/Juq38alNTLQw9jVMrD0R4axUqyuCruCv7K2lMvzWxBTqpf
2XSQbLT+0pvToykKa1WMWAv9CrvMaSe0ycy3vkKHbKSMKtBYtF5DJAPi/k1PMgoUeKC8ix3PzVY9
KC2lF6jl/HLcLWZPwj6gvQS456+BQgCNukgOcpe6fDMyAO5GVWyGCdvJePkDvpFkA4ESBC51qeAM
QOOO4fhKzKuwQY6a1Pf+BdDn5E4TMPbpX7EQzHX5En8E8/sQRAZOiRA6xENChIG1CQ8bMwdnQUvR
QD+hp2Ye/q1zL+i02wpJgEbFKbXFxltP6P7/jX6nBOs5x+UaGbGYs6t9vWwHS646KguYN4/xk7Tp
ROm373VT56orHV/ot4BmQ+J3eMez5uNXRbWypQMBat8vPcbRXQgNPeydWrIAgofMkNzSQVxKGmPu
jU/ZRr3IXq/VQrktccF/his0/eXzvtHNf9hqkqxKmwAp1OYOYd5XIrHYbvZ18C9ijHz1N9GBeaRh
Q0VLvEYJuZfa6BgSf9QVyxgOhxjnl+6gC1Dg5Iv+HaqFvoPuMMV0s7bLGzpWF6PmnkvQtcMclbMk
f/wRDJPDyKEC7n7TXtbYB5wkvAltm3Szb0hMrx/4PR5GPV8SVpEcy4W+bJP3S0GvIAlrOLVraNm6
O2el5FHaLbnjtzxKUQPQozoT1872/XaHxnmTNGP9KI5UOA6N4gsFihx0KCsDcCaDGepEUPoD2pWf
zQ2+fc09JK2XzXUMErGiFY9eYnwZ789tIWqbe86pTAPcaHhD8qeEQ59NDtDpqOrZbtk0M+hwrwis
zh/BEx1E44v3c0Lp2AW6YvpLtFkexFZD1cvMdORGpHW4frH0EgM+Xk1G5fdUn8EK+c6J6NjC7ZUy
3uEgfVWMMbQLgE63/W+o1j/aH4fYdn1HwUpM3On04w2xrvPvhgRtWBDPhi+MHgk4qDHpDdcCcRkq
E7n4sv1Zwk8SFB8IjSkn/AnrBuj7NKUhZrNfqlOvt83falTUqwFmVm6rflq/hEo3deE/K3Dy9BYr
H1emnlW624cCJWinOn+ja2OWu6k2e/CS8VGjIBf6wj/iB6qVohABvBMwJgOAEbxPdLzc5LJh32fh
3JP1b/2t0rkO9S75vkPMlDOluGsjUK1qldvtJpVUIjzfGiLrXNDBh/q5gb+SD7o9KHWA7/DiCmNt
0TB/KJKPqOQvNWCsSSUROdC/rXzNyH4sgJgl3iwgjUCHqrjmKeAadeS0jmESKhy/DEl4aubFJIoK
ovbKBw13Q3Hssw2AaxEK7y0d0SraGcVgJGwPDQMUB9tDsOTMOc0pfF+4YKV1tm6tym1wcqP3j6bW
UHW6GMuVRRYveNM18ckmULnH4PJXoJlQrZgPGIKL8Z0+zkVyECt0GYoI2Zk+AM3WkzaUdKT5fWMW
619BEneTrTqROC/6n9yL0poDkwXN2UP0yA4u8HmN4aurNI0xRjC3dJKOofU/3Bw8YbJdieBMaKUL
SIAeVKIELIcgFa4zb9DwIcu5GKK6QPmCOu5rW+ak8l37qychOayarB7n5cZjCu6inqw3k/0awouH
vXmBhAaeWpNEGdSJP6zrB+7kb16m1C/n3BN7aHxRfrzrWWHVyZTnaP+wXYP1Sri6ZG9Pj+Vwabye
hbhgYiYzW9LIeI+xZi0+IDzwJ35ztuPAfVqBa5NiOGRjvt5iIi69HGHNcR3c8Fxz1rZ2zfDTQMrq
xacSgOsUYcDT9j3j0a3CVctGtbGi8diS7ai99V1ITXFZJhRAcWirnAEq27IIy0jYDkzeZnEsBvaX
EKCovCXFfovlTH/auWTLVyZ9ezejcDBVOXuB6VBli44LhYkeZ81B3syUeGcZ6pIh4sMg/6EJk6BT
fE4NdrM/AHcz2ivhQeYIN57iYxg24kXIvn8hEnAkMSYvBU+gP8iRDstzIU0KizeTZY1+FqE3ICbp
aeA526T3iai4tfa3MfOZydKk1EjR+m0MKj1g/1Df7iYV+KPLeOxWeeY/UcnZC5i8uhtwB75WLfG4
NJSf8k+PnHpnqz71Y5o5ttr3ZXqkzJ/Kw/05ymExwO7M+uzll0bPaZNsRDvtWLN3m3TqDhm1Q5+V
I4GH/xLxn98s+l7gjMKFfQumBDzQsItzdJhPy1C9iuJgtEPhQ70ftI/IPTBDmnlAaJxYG9c2gLJT
cMKK9aLhJfjxNxsG8ymrMJwwyk9TF1NrFKHJm0+Wn0iR3/tmvP4ChSrscErXcjzQPeiXZyZYRJ8h
YwdhWYsutK3rTB8sZHPi4iE/YxV8Dzk7G3t+pBFt3pMomtttowxSfvZwe/LmojA39bW6mt67YjnG
1Sngg56ri6DTJB1kXpHOxlmeeI7aLqhQDxX8ImLzAYUFu9gMUdQBdOLbPUrg88lKuuYoaQCouNQj
FIposIUPLKF86q4SoTxdbp6TypMjGf1O3CWO3oRQVc/hKfj5AfiQHdeyQoGHh7ye3TE5NZiJx71d
lq9fMmYxDm/DIAAGnuGKSydEw9Puxd+DTQXeoUHabn35qsbOHFJOUPaDO1aB9RPDs9Vb8cf35ebH
kU3+350MT7AbOaPZxvTGtPBeajWEn2DXeXUHjNDkitBgvGuzwKiv5FLt5pTM85ZVV+XGWxeqxW+d
pGP/r6tc+IqXwpSVAaQQEs5xCdbTWhGNnZUtIKR+jyhf3PJPsZT9cVq6jgyBJY5+/ELOEnMli5AS
hxSJSgpoE5C2xa++v7JpINmr6vGo2j9yv9Go8sI4Onyg5xYSDNOLFW2/jfIm0LdmL5fGTElX8kYN
5GKr1QFIvIrCbjw4K3j5ElXl+0X8zEM6/T2mjkwWRREYo9M9Lqk9Dobfues6Y+hKYmfFZ7BtOehE
rzLt7OrTlLXiDZSMNwYGH7RUjl1KKZUk2HWc5ODOcryWfnN/T3jslO+veXnXDCYFs4h9HxAaFchh
kyI5YLcMppiBbOidak5T90Q5bvdd5w27AsJZfUTZCm4LpvHbL8VXMgb1wKGCpaTA+w0UkN9Y2bVy
SPWLHHsJ6DSM9LmXbGP24xOvU/QhGm9uCK7IMVeVYA8FJQf6lPbC3G+ASaP5Gq5c3o9rVNievAjl
ITSFTlWLyfWONVclxKyAo190zn9C+N46tQU1jViXTPZ4IxQODesqZXZtsVij71wOL0YQYSCMokyK
BbPb27CPnJAL1JZoGuENMBJ03kBFRsQKDu0jxWVWx8qt/YjCOMpkmsZuQ+YX+WDnNihQyYP298tC
I+IyJ/5IJ8FCwVHntFRMQHGSd8o+5GS2u4mucOQRgMEKvh8Lj9lw4Q72C/kGUq5Kg+dDZOOLY3wf
zbse/7nZXJWQt2tLZipVY/RhXq5R2GJhufka/SJcBDfMMOjinjydJFUifrXm3z1JPo9c6zgPhjDv
ZY9Au8BOAM67RkgSz4TIQVw6QpEI/o+km27oU9rX7SAjkLFMl8OiqDfuydpOkNHVy+tcU26DSg2G
SJvXcmbESJPHLTxNUleP4pEbinjYJwsd8w060j6DIDpSPBIlwpc4zNhvYpSE4z0++9jDKV5+1P9j
MK+NbZU0INu4iMy+Lm91hsXhuceMOlc3Ygwx743UpPjQJITTHatvNkEC/7CtP6xPUF/RRXqN4s9s
eBZHI7s5x6SuzldqYNHMiyproHs5cFM4M7W4CC2Xjbii7CJkO80FuGr9Szve3xWJJhuUH+SKnO13
87f6SlpOsG2BKp50yhUVrCL+A3k6MLuTHdhDJIHxIWUG30UzsolGpn+Kdccitq1zgs0knyRUdH08
kPRjfzh/qQfBtplBTQjxLIOU1dmqbV4G3YLeBDI+RfgALUkfSGzt9UMAW5XS1TEKSjxgtr6MxO44
9dS8SwCIlH7I2YEEdxDxTluP2PD8l3RjehGieFOLWWzQ7Ngz7gJQfvFMODYs/fsfNcGhAY11c8P3
hCg9uIYeVvS2YMv74Cpvq//Qaw6C0ZSwMzSwvFVqS59SAdz6wfYC/IQXKnFEzIh6cISwG42dgojW
v0wSZq8feeIQqe4avpLYp2Fdiy/W7AKzNsmH+tSs1SoiIw6cIC1pv09Sxb7gHruFOcX9iM7UEWUK
dKYgp9O1H8tne0Rrh6TQzUcA7edMrkKxrWbRZz6M2vegcjgrdkB+ozY0lpaAu7u+hmlTcRlm7p60
Y6ubhR6ye8YJUZUVXjCJklfjIUhky79kOlYDVIYGCJJ+z0tUkV7Qqa+H9fQgdOU6JYAPtyBsvqfs
EoKgrfO2NeCy0SLeEw+AM3NnW+kCBo9bnMYtwApDjhKfjEhh5awE7Qg7mGnifqXen6PZYbhWKPoW
W/0b8eYFNt36mEc8JoEhD4AJ8wJyNZRD5t4U7aN8ZJ6QXrkgDkyKjlkMPfUAPMMgHkzTZtTUwJlb
X9EV1p8EyteHCN+lg38VtKc9oxObfYM2lEOzpNagrBG68Eq6ox7V4hckwlNX93HkmcFoTe++UNKF
1gfpKsGM+CUMLwYm7EE/bCstuJpT9SfSq5ztum3kNtsMTKKr1yIuRR1P7aJp05NCZrPBUc71JDlU
Q8EBNzhO/iVzYwAl2SW8YyEJ6mcjV4Mxufxtsb8IKciASOIhIBN+k4/8skYcN7lUtqNnm5VbPQJI
dzqpT+gFpyaoY6AXUK31utwMVYWzNkMSWR5a/ySUBi8I0uBvWPAl+3x2JPedzVpcZD8SpZhraLax
zfV14/F+GRXANgGieysJpbEgWyZwfV3sYtmgz5R/L3LVRcbpemcUIXk/HCB58SBUO41AUMulZMgt
mGTqI7FY3OpAG8W9ld9aif6HnIHgrWu+quxm//3QVzp+LA10N+TNYKXS6pid/cJ/9uvnqoClanaA
VzZZ6WWNa9Q23sPcBJYDbAN303d+SKhIRcxMVUKgF/k9LbvN8S1bxDIkomNs4b8G4N6GgxcUOHqs
EYm1iBXvVxSpQgS2w4VLm56R7O2VDNHKTvVtPFpSMimMBcS94GgYhSQoT9p83e96cWG1Y2ion7Uz
Ueda3szWOgljtENUchzhvpAXW7y921PkMochgvPngsHDc6pMDpD+H2IrKEI6wb3sVsWcfLshSkvA
FJh9DeSTiNlGtyrq80oBKqJUsglSr8GisvDarKUL/uNpJv/sCk07ss8OboTVKjDclip7pIBFC3Pr
iGds2YybMYa+nWZataKSHppdWeEC2BrIhvMUb9NmXrM+1ODceDQ/n0GouybiXe/UlJm8HpHatMTw
AJnKPpuUGQTNfvWmnP6rKPjWYQi/fG257Tbcnyky1QU3mlq2jU6NKmPV56zAdFo6x+6VM7itwBb/
j1pX+7PS/F3P61BXa/Ko2kNonHOTGrcnShV9zkEv+TTAyFJph0AsyYXJgeB9UaW1ykq148wtZmoL
TYLleqvo7kziyVHdSU39BNzHkkG9uyffTMrgmDXYoRz0yagHPcJXMgphq/owQlEWQStBSwj6qbFe
bIN1HR+mkqXiX5JTPt0Oa8XA462FKZR8JgNpaJvI9MyDPH+PlZUi/dvzq45gE+8D4a07DNeMso6Y
e+Zq7zunFdN5L1nJe3cuROs+2/KwV/JmqcspFi3y374njl5fEszg4oChEIMGkcujzL61VGU/VFHy
LvFBhnlz50w6SAQL332xPXcR99/urafjN42My4fd3c0nAvqoXe/VIY/zw+rYazwMWp5mjZcqx5+0
9RGEEqJd4aZTwB0vC/e1ZOCAjFaMdhqPSomXzR9/9PqflSwLRPfdfAYs/QdbgX4mkm89e/4zCRd3
rPIts5wLN2qKFruha1TjJgOqrm2H7ZbRGIEylNs/482GtWQ/8M9CVx4NChvKmtgMp7P7kM5VvgkD
J6JZZfAy6RD3rfgls7uWa63/jFybwgnhddQL6sKxLkJHfVE6b6Iwa1oGqE6KDoTQS8iaXDXvO4Z4
j4onGSWOoEthyuK2liqnlpr887d2PEzsHK/r+q3fks9Tz3MdU+x8MAu2U3BsTE4La5II8iaKtfZz
GwFiSSE8Pgykk5Gzr/mvw0LM8Gpq1arHi2J13b1rQ0a4vgviTq2TtyxsXwj7bSuqZzvGGm8GKBqr
UDTrvZszIL97spk4jtuoXB+0PsTfwEjzUAzp9oI0AoE+ijOcyLDK+jRmI/XlhQeJ+2bY+Uwq3ufu
8GGP25mEXQDNEnR1nTI2JpDQ0vCHEK4WV4mrtbvh3bvVAu8Rk+lQHuYXIWRGtLxpJ7BkhAVBzzwS
TUpETrTw49J6ysa+jQqNcAAup39D3e0YytsrCgETWplR806nyYhN0nBZPPBwmKpyL1hIhyjQGFcO
SzXe7k6dNHz93sujAqx7KGWfUjoldjr8jj3ZMDZg8YG4KjY3LHxAzfEXavy3PHXATY4pgoy5URuc
3PE19Wg3CK1mTleVcv7bBMP5KTkemI3m6o0ZydHy5cuqrUvtPkrCPSKtasrSoSc9MwwDOXhpgIvS
Md1/N3eS3Yfo4jOtcNh72bFfqDtgIRx2uKGbrAp/TVx+2i+gHz6gPYWSTuIScSS5t4++qu8jPJN+
xd6/sIPq6x6SbAtOYHqmjURzeGCYEUncYVEx4tmmRpe3Gdjc5ZGorfjO6hWA/XOjBfOdLJjQAVYc
FRzQzJb+k6TyoX6UT5C4k+9WdEMGTRmE5UUdjmvoGxQbq4orRvaEDq7+KTPP5zyxQs3UFaD6nzj6
1lP7kB9MktDGgD+gg6Ps2NAcOtwpoL3RLxi3UkgPS8DKqup/4hgMwCF+gSQPgwFspAe6ypig/Lyf
nsyn9ixto3pUnRcfglPrLJv3KSzRQH1QEDySbkV9F/3jwx1zzBph6YbvgOCYFh7FPaY9AoxfG/zM
7F4R0Yt8SY+8IxUExFPQbBLhG5sKDRVSBfLYFeSLp8NAgSmJvE6P0KiZ5vOdA0MqusbIpjEvW+Xb
I6E3XJmujVP5ZGugvUlM6YJKF8lqG6ZT6PfwilwMw9xffh228bX0sbniO6VZ/E4n7ssBHZUaWBfs
OwPYcKYX3dbAUkyBkeeJvJ2l2cv4S2xUXex4R2qiCOLrERC+GnYBCqQUwZsAWaKPXm1Hp5NJvQRM
WK7rGDXA6SZPvX7ScCzt3MXcjOXfRbpjV81R9z7Aw1q1WA6wHnU7xI8t7ajhN5WcXZ51H8EDrgWv
tSXjzg/wEadi5qRxS6S2wj8sGQUFTKAmD1agS69KHaQMYYpuBUFmIIO2sCfB2B/bH7sQdj4gizKt
De42dVLLOCRsH4wM1WJ0e52ly24if9KTU1FWXbnOJ+HwOu9ta4HXxpip9idJZo63/1UAnPuNOofH
mADdxsSqeDu6WbLf6KwqQm23IRjENdvI/ArtfL416b+CoaPSSsnbZA/eMd8jBTqSgbQRoOIfXuBr
p+ie7oQppHYHfHO3YT3F+N0lkhJUmviGCvuCnig9RBVgqVwiKkfhtoDA0tTU0Ehn6Lbvmuim5xIR
G6IDVcKoUBqKF48kjbLxwIycvQ4Ocee3rRqnbMkDFz0m9Ys56n+1FpJSMHe17aEFaxiABPzEfKyQ
m4Rn4bCWGNP0bjA9OucO1zE3eYdeL4C3eTKS5Qw5fSejYTK72hxIE9Uom4uXhTZRdnhkFemy6TwH
Tb20tlZc6RyZF+zBW/jMoDo+7dL2HsrmDP1XwDo5iOdUk47g5uuK5ogJHYnRNnCK99YQ6prn5r95
tc9VxIQNYd0z4z+i3DE0UMWt6WdwaMV3wTdVAemYx/fIpelaQr+6PQJXC07uY0jC3beJtjku1V7N
1bl+NOwY68Aiy8ivZE+IabhLmYq3SNUdmHejnnWoA4BusQ1toGmsuZnS9B0fCOGLQ82MBKMC2Q3S
3NdllaZsoIbJZMezY0jLFBGp//jyuV7L3dxCmGxxwaDfFeYBt5lp1Zz/LqFTuR+yAB14//BW6249
a/n1OePYQZBL3L3mk0qXwB/WmE/ykfnAFqtZjAclC98lvar0bzw5TeDPklHxFvU44biwHDxp9M/z
pVUJ6JeVcpnzYiyq7EJi8v8QV6gtElbGjuB1DQtEuPKvFKV9cD08BJQfy2HAbfpqznjIZqoICt9/
USSdWpsXWK+DpYN1l4xUz6rNCWQo/SZ0ElPv7yxf9trw8F0ENFEkgLB1ClnrjT+Mbj5WB88C4t+6
h0SfX/lHHWVDAB/GGqCAWGX5dBoOt5muPE+sHR+4creFCti/UgjsxOFiX12l8LycNKRoCvtmm9hI
3Awhht/W35DC8mYioYmCF5amlP8UP+lKT4NXb/SBxDht0JjoLcGsvseoaQXewhzReusIuSQHBZBp
z9fLhwU3ABN9cUIlI/gBFJmtjeWsqc6le6WUID8kJt2G4amBlCRnyUfv/qt4lb5qKXo5ep/OWY4u
eI5t4jTGqiF784eFSCbVcPBldGLEgBmWG2lavagKp3+PamVaXimXejbVuQ43gs3bAotF75mOLIGG
rz7CAx+Jmo5dfCk4oE2c8b1VpkNNf5Ocd1RjX0kjPX7zmHZkXXGGzug4hZSlfSUmx/u1hG2znzSt
ueoTYb4rrf/6uB8zz7af/cjfXS6Nq8wGvNKkAls57VdexN3qz7Kr5D1yDN1jRjQsbyfzDzBrFXZj
G57U66Bmj+ZQocMcDzZ8CufR4XZJmMvOAZcvn2pHE/MOwVqq3VDY/2lVcthSiBPgKkU0JNPAT+v6
WNfmUw9NSrYiy+ShiFxgSxqTi7jQEQ8HX43MFFX7nuMr8X2M7Adn5Bm5o8+poL9WtvkceQraAFLL
ioYzmC0a+eToFHn+ap2kMFLERSwkr2XqNtYidVdYmpceG9qcaI0bLLI9uAlZ88PwVJ6Hr2o0/8+e
uEuVBrK95la2YSSXK1tEymCwVgwEnfDw3lGxjpl+AxXzCbvr04EAtp7iDC2itr8vwDV1B2aR7tny
q8t2HyJonR98sM/2kcHotZZFIA2D3Y0ZX+Tm/zOJhCouoiFmFv1Nf5lyglZSeWotFH0oiqTdsTle
B1ZlXeVinyvktxMrdkolDGOhsGctgKB364UTYchVdL5SzgqcuZmqa/EwwPLugy8qSmFsRvHvKtUo
buKNgalxTUp+wA4ICE1QJID9QMrkqijdmAztovelExQLRpqMfEa7bEdOwSLa49P3mRMVWR3KlIGo
JrwwIOwYJZyHFOQ7zbcSi9s2s4AZbL7Or3s+BOFkiqqHXA2nIAmJhFi2FmKlqMd2vU6476aL6LKx
wEfvNuI5Pp2zsFzroTpuBmrUZR/PjVNRXPq8SiAsQg9EK8DYKCgsEnk0MlsLB3Fmxj+gfM7Kf2YI
y3ARDx6LVl7kjfXxSjyaD9O7/r1IyWEdAYxA+ck6nQwLvMZv1bHI8vhgibcB7oiAzvpsgONHwyYg
TO/0JzeQGm7IYjFISqGA5HMmEyq5LL1lA8oyARQ/7w6CPSsm6KFKuwV21QbeVs++9++mcyRe7Fj/
5YNmX7otaWp//KfU0Zhewbu0URYQ6u2ImjSuqKjeuVHZWqpIn9NZgul79+eRiRdUkRiU3JZYpc9q
ipH/1hdEbafKJCn4KP+kYbNz/X/DP6dG74oLKgxY+V+5BVI+/fqigHoV9VBgQq7ynbItAQjYLGgS
/GrozOuD3UI0T5ljhNqC33Z2lsPSwfv8eFb86VnGH2WURL38G0ts098S+vcQ0X3u9oueYB6XmCoP
Cb03Qyub/f7rIf5JMhPn/7bvRY3NsIdsBgIfhqPawUfDhULypteedIpsxpPIwhLdbsl34O3d+9yE
oPz/rK3LCXjfQ6eGZ4OmV1pxle0WM8hraSwsxB0n+qs60TuC7lhj/XRlgRv7g02uYlDyx9yxSIi3
oFY/haOGE0hJY1qxZ8/ZuHuMUn9wtXnSGo+Xx0Re7BzJXxvxkbQ0st2mSq0dz9o/j3H5HqKGoqoh
E9zD+Gv5ZHTUgx9LajWVf+EOrV4I3bWNPMYBQDe7kN3fQwH16tp94wikTmxF3v+vUyEQOW4uUuWI
RpZGEkD5jJ2Lv3bdFmUjjXFF3cci9X6P1Ix0AFUvGtmh40VqNqhiPUbcjmdVGVydI29IeNOdHk+L
p1QUlEQqTMu3HxFXqEVRKS1y8C9F+q24u+1/3sS4wavzQa8nmYqWVHdpzYNhs792pqoC7gR9pOxj
5nym4bK9fvVRu1TW23hVtrbI3bXHlOC70PGbsYuELl1j0IwNZrQraVZV0Gl3FCe0GMxjJ52o/SUp
thr3YSB8aPe3AlJSv7SZF12M2bK8iy+0WBIQ7n/anvqxDtqoQWwetc9c51GXHsn1U++UCxXB+Fj3
STLrK/kBP3Cf3UqF4jsWJ2YjsZlz+CW4uFlX1CmpaYmRdsdkz8L1LJIx5pcWrn9qiVNZhjuJNJKO
pUxbdeHgb6X32Xh5onNAbNaWHCW2DR0SoKzkJgIoH30/WlD6kIHTKqSbYKZfCudcivzgd+oQ/Qif
leeUJnlIz1wRl9b+kHgWDa6ZQNgwybrhkJzGChlBO8HigRMC1A7x5tRrK87XEY62Mt3teGw/n6+N
1eey474MbQ2ZfyYu326VdPvvO50qfPdB7YbrICiCZK/lWijydqK/kizI+LG4Xnt+/yT2Nt/JwAQq
0w9YhSegpzB7DcreDhbGBdaO9cBqK+l1vYu35ZAphpqsqaoDZXsLhbTl5m0mNGzcw8lBoQCn1VRS
YjluOSK3UvD6/aB7BklYK20n6sMWo8W7RSWP24IAEEy8q/ezqHAOW7eTD1AmkS4TpJ4lBd76x65P
PyENgnSIGbgL1+Y/3JajGjHp4hwNhSbqNDnJI/yzOzpHAsXF22Y+9CG1/Nu/lW0SFLKZg0cSD49l
1zs6HZU2IJLxzGw/JYoIrXZfdypCur10C5Xr6llSC60wYK+r9sNVl6447jy8g3NSamYKNp3hJLeZ
8n5SMMDU5p88ftk79UMPxevBPjfWVRG/bGwzWzKCgX5BAwq5CkrIeC/gUXBwZxJ2Fnat3JXilqQZ
yauBsjbHcNZvIFZ9ZdERt77CdmDiERNHkgbNAp8FhsBoJ/jP/ad6GCPdkFoSTpsnm9Yb5zBAzPH7
S87sHGEyAsoylO19f5CxQUpXM41bxn1ZHxwftWieKg+m53kzobJ1yRqiuboMPuB4gT+lb0ULHdf+
LmpC9E5zG0nfUsiuMuJatzGsMfES7Y1/azeTI15oobmxvL7FlPm1f8Hhc8C6oGV+24ZExyRSvC/1
cDpRHjxCFPj38giwYx9x5FNVjnh5Zpa0T3ela4iPbY1Ri4DxW+beuYNB3/ZeUmMoXCDb9TiR/KgS
vJ5OOxMJVX0/9G7Wt139jBZlXNNQNr8MWmuiQmkk7e3/hxiVC+rlol7iZtEK6GyCPcILLd4YneJV
lyVdeuXQ4RZtq0GMf25VpWpFecCPg8knrjeZlTvb28W2+aIO5+7zUJ0orQyjj8wNvmrUt9HIzuXG
15mEDBUm9axaeb1YStTbxz3qlYXo7OwDmytLre/W7HgVA3syEHF2pxJkoOZe+Gqa3TmfE26v9kM0
YkaXMnx6IvdAz6c1RIvGqNmPvoTW/uFZYPYyptarqydhRnnyAQk5NACrL7aaIRC1NGM5ltnwNmpA
bES24H+2M8ugycIx8JIAH/Fd3N9Kv4QTfJYmgaJStynHzPbsCRIkM4VULM9Dz4FMFN/iU4gewBWU
IPJ2b30Y/dcPAYuUfTzEBwmonAvUeSWwWTnMD9iVLPt8SIUBVy8FRZ9kf+8XL3tUOhJW37O9Vhga
XN8JkHWeSmj0zpjfAtzSzHjMwFIzouJMdXv1PL6ot9TKGjhNm6p3IVp0fWEIZZIAp+TbDNtUH47i
HYQtHY1tyz/CvZ7k6sqEZa2kLuQ2WF/o4Php87VXj6eG0mkW+fasH3AqNYYSK/htOiuSPa3UwN3v
hmoDkyfObpqAQni3OcVxgzoXuO/PfzJVkkl/GeM3pYhQI7PrtzY2O8KdTeHUJrdPL2HHCUWe07Vl
VDse6Ot1bng4TKy9T2nJ6GMmlDMeZcTC3wPqec9BlrWA1R3QdDG+zqzkj5bQPhD9DUJXTMwW/ogf
AWY2riDR7z+xfSs7AiKN0JGJs8gPqDKN/ZHtl9NJ/73Nc8zcQv7BouqH4nt3cE2KYkH9kjf1lTdh
cRBMFykiseIH9+A3mBhb70ZfzwpmWQ/knFHFJXCRPwB6qlPwu/OOiCrYGnoISmVa2pmuZGLPE6b2
hEwRkq2OfAzhnIahV4MH3yS7hyd6oQY0goET1iXoNohjcgP7tWdQ/Cmyy8HvpJZCs7FBuvqoZ6lk
hQwvySGev6YZYbaNvT41bjz7qkSQK+K+C7V1EKT4PgQHMcDP+g+w7fJ6g96a8ghZA5uEi3rf7CQV
rBO2rMLpCvncycnsYlZ1G+foMbIDD2BlQwu8F8PKnXb1HhpiWxDCAnzf0mFPHNh+i46UyYKyz2Mz
j+Ma8cOYZBNJU4dEyvEfBZIna6R6oRj0EgvyVStWB5kyb9jehozJTUqI++/f0eW6McfVIIyHaegS
07h+OhmReOECh7rAdqNMAjpz9n2dQo6kMgKf3REzJaUzu8AsgctElHPhFRDATy40brZ0pXeQe95G
B4GSkt5O4Q8TuEwz1TWlvZhOx3XzZRsh2t0oBvMqHOxtU3Fvs47ICAMJSW6dxD+iwSxSNaZ33D3F
PWT0YeVPtAgEtprz9mFxf0oAqyeKysnHbt3gxrhUFYbc1ewzlnUGxUACDxVQ8OR4KjygJKLZ+G1y
GA5gu/rRwrvelZHeCR8mwAoDY4pMPacpCpZtHecNzZYx+J7sLXuVgB0wmDGP1UdAfOWv3lEcfqvn
JblELEK2a8MD7r1hSDvuYPjZrV0+6VVHR/ZUhSMoQj+q4TMXsFndThv7ET18POocJHXDP5TKLE9U
vftsQ+mv9RAqFgJRAACVXIBipGV0gWsvk+pclFKlrIXoCU4eK0kH8ZGpEXQsLMV2J0nH2037YUCt
+SAde4kCeUi+wS6+3/gFN2IudNYxJahixJpwT64g0pkPljhTnkchnqGsl33iW1w6vQmj92ZA2UIz
ZTeFzSvLzWQLpuumgA1qHM9aKrXQdM0BgOO+3YQRrr5swD+gW3rmH7Mv0wDuLb4L1hrmlr9Vx4Od
7YEIimZF3jyLvDEtjmovg9lLZTBpZVw36mz74AqNATsn8JK7b/Kj5wWUO8BQFV10GeZH31EMe0Ko
ucxXWkVYhMbOclyIlY9BMPZIyLXevQBCYjo8TIx5xIj7+3PxOhjDSnHFkZBJgTCE1m7lh0j/tMXZ
BuH8J0+1LPtP+F4bKaxwy0OxmlLydDEntQG0EaoSO03+3kgPR0k2oVl3OIoKuTNU6SaKfGzptaT3
LHeUEHLEGnRkXbBnd6AJUVMszRXwu4x0JfJ2/CusZ809/HJlEcT4qbPsLuCC7tug5Mw3OCFbokTs
dX9Aebl7Nh+KsYne6pDwY/IamZt/WQ/v4hVvqp7qJVnmiRO6wB1pQfQqW04gYsmTHSwOvRF9AnOZ
eNtxIyYOZsn3iYR7ngG5VQptLmU3dcNLqXvAVIHcr9gYRxortOtxtJWIgroRUZzeK2T2+8qS2oUT
m5eo6JDhPIj9tJOxWDSSQIeGvt3R2n05CvdQd1/GhgAkvECmbcu3rsDycwEbMj9R6qqszPvjm3Fo
2LhN/40cTe4hW6ZSVjWP8K5qMy6/kDEOqruQN3qimlmLXF3Mwak+CZpzPbt1vSOOj4BmzmYQUPtL
zURmpb+bRpWKkqAmqsqaOx/aLqi2OCdDBz64xwxzuLwMIor5zAPej5MqLIpvkby8u/qIyjWT8Qwu
NY7Ogft/rA6kL2EBUaMHKXcykiaB5KfKUjMKEYQq46RuOk7ePAMpBfrbJwjhN+AGgJe4pY0ADjDo
NjXU+fbApdQc6zviJ8lZpwOuLvbjTk4kuIZsONs4puXaF9ARJTStxovxfjxK3W0nxKgJSkSPFpLo
vjwVofIl9g4StAxqntiLWkYHNMmzeLKPUgGOlkn4c3+9IYySQZ7HV5PAazHc8uhd0ckvkC3LJKF1
dgrgFgPJTAHpL3ZX1jwBqKjFvTlVh0Nz8b2L4S/YpcqM76Lbrgegews2BnDkXrJrLJX0y1gW0r7H
GPvj4dEy+G6gMHdRm8hf/m+5oY0PjXdw++SdPo5QQAvnFS3cgDLt2HbNaosSf2Aa9oxM+FIOM6N2
IkhJcqYDoL45owU0BL6/++whzqu84oEASPNVtlgtxIFy8gAqLvjuHNp4ymq5uOnqPNGk9J9Ok7WC
lRTK+kyvKWzc++spJickvyzxeY8P5agcO3XYnaBslY5DEn5JKhD/o3RLcn8BnBjfCva2IBq+KGlg
XwmumIL70Sa+hoehxXNOia1HbWi1K/Rt0dlUknRogr3QqQTLERC/hO6wwAITk6PRkfzbVUCEkIm0
Lzk5mVtsgHGlgdu+tbt3gBsKW6pkYvCV/10VI6ye/k6pe/LZaxNcyE9Dx/C010KdeogPZ/8iTD/2
b2mt4r9Ro762oX/nqW9hadVGsrAqyOnNF03J2o40qO3MdHUO1pHdGI8le6fzt+DCjitFGwt7UCl6
QWrcnwufoInQHWl6pKQHmg4+D2WMSVz+ECxylD4OR/bklXkvA8ixy+M6UoMeD9DeDX9toyl+TRc4
egs/LZP5ViMexcWh0K7wdnuG8iJ5nSkaKwTMrhN3qbDv7dr7p3pr5QSoYcYNFvgIUkrMFgEyQQyB
mTU0s4Ci//xRGIIWYU39W1F3rw+kLyxoQepSd7cO5fVZOeORVXGbq1uYHWF8C/XiyElBXbljGY5D
N4fPGiILj/JlQp0dpiP0Yo6RmiKSZT4E01zjM6fgBNlzbeOux7+BJKGCnPc8t8JoyC70dmyfFiN1
ORcKx58KqJ/yiwp5tKhW7Nkto7vCzbZ7t0Utb9lZihUvXLJ9wvqubEzdDM9AtWoIAyEYTHQB/9Wl
iJ/9JtF2gqrT1S33Ic0UdHQEOUsDqenpoankUe+PpTx9QAEv3J+chcbsyJK5xZ4seIKggAY+uhqY
rTBW7MitEf9Lk8BYGKIBnHcll5g8txBYl5bVFG5kflDHYi2X1yvRstGLXu1Yhk15NIHOejCzhaU1
IpFvtyyPwtIuO7uGQGRROKCm5EVnx6l4inDRXBRfkpBjIv3JcfCBQi6LKvpGYk9q1MyOOutEcceE
FrCIQrq7Uu4recsR5FO7VyBWOtGcLrBC+y9fz5VGUw2s6EWy2nF9tbLCoJ0lnXF5ULzlXle1oY6w
4lJVvKnY99ZI9uCTahuu8+sbhgD5RVYc4aXe/uP18O94XGbzc5ujFI2YCAPSET0YbA8kWKAPSwoO
juEW6eoe6ch5+SPrgOGBCA0XwGf4UaKgc9gVF+vRo/GzwuPTvOFLgUq9JVFj2WXriwA/wOA92Sxw
Dl91TI39ZGOeU7e53TGm63nMbV8aR1W8e1ZP1nVTLIF3Q6PGUnQrUhDlkIeqe39A4a0AiCyO4kdh
pXe2o1l+yTvOI/e4lXAmzlU0l2OCPz69reUjHhRcrPlb80dSBfEi2ILIvB4ysMVj6TZ7VfY3LA56
Rj7nrdqorsqnlpxxDRnqJ6LztxIgm87lUBpXovzTvAdYJeL0V+xZKAHWyJLPzgCc/Gw4VcxLsAvv
a3dVv54tR6luwA2uvqib4ztdTo2UW72idYE/sXTUqhCYo8sgYDz4YeCQatgZXt/qHRr/+mxeLS8y
Grt1khqTaDxmk1997y0ARikgP7PwJolPEuCvspYVZP758G9JFpcmsw549t0T/ctXf5hnOexdGPBM
PELS6+ojZxf5Vcx5ZbcchRZEab5PEJ1b2CQNUV8bbDLxbfPUVnpnf8CNj9C/CdElHlxuRbMtcx7w
1+ri6SP6RT6gCnSDLyYnI8pWJiffgs6A4NwdizdRC9NcXOJK3JpNM2xqUzgxShQdGmucvaBvUDZc
JebSp/ndMgO9/f6Jqy+M3FRUpuyTqSSWUZLxF1RZGZa0rHNc/MGydujFoQEz4FGjdEL306iFrddm
Gx0bNNaDM/zDQyTqZGDHeoncHfzG4GazhhD6yutgHSLb9o0Q6Juw81RkJiCLz8kf2m7csvw33ULI
paW92nptc1elmYo4dgj00XdGy4F4GxuuTxLvKJBPsH/CZP9lyVxpBUMOEtFrtsPvVDGAGLpNV9so
NtfFpn+4M0KrGSz2ry9TyVWmHRTVV5Wx7K8uzBgPP4fw3lOTVG3ppGvRI9835AtuMvxdiPdw0EjY
xNr6CtZpPxiMafy42EX9e8mIQZQ5uCA5rmi1aB9DzIznW0noZs4lpbAkz/kTPcPym+3d44oHJ8xR
+OYs+hDamLhafU5HQmYmugso2hffnSeGhsO6I01jZ7zbbu2CBVgq6ctB5VbHa5CU4m6wmsEHU1Rz
oppOWV+VJG2oG2jZuCEvMX6Cm6qWX6qKBE4WqPVAU5Yqa+s9H72JEKnWalsooktKUXlmUtwi6exs
Ipzt06DFtDHux4TmDB27x07hYde5Pn2rnXL/pDt/r9ym1VA4rD4AMmPhuPVbhytmPZVuwGASsRMC
EjYmIgZdoNU3IaoYGWCzEgrA75ewiLjt9uvBwLG1ws9As2nJTVNeKclTlLwoZZb7aS2UVLt2y5XX
H5n+LdnCpv/waG07BAoBSlEpRIcKRt3I4XY8FvfcT1mgzlKwMNdW46BZnVTnBJBLVhcn81fXIa8Y
gNgq26tLaaUCy3naktfD+gT7j/GR0XLIAAaYO2R8mhV1QXqjJX2Ye9YZn8UBWw4eUBI4uQpzSLef
ZT/fz0yWlNoS1EcIz7zKFcpxZeHbtcX0MbWkmLu1N+KaCH4+JizYzv1VyS2OVOLHxt4Hj3MaOJx/
M6BVRG05vwWQVhaNtXfFTCVMbqNSaquH6q7OK+KH1kZAIymGPJkbAuodtULgxxZTgZOQbX1GvS9S
miKHrG6J8AxduqEot8Hxu9D/G7lZOqmFm1n4wRNwUHqKv549whWeFnNOkRkSpotwKTNXbHe9dEY7
8sY5GmSI4kxT0DXFiZv2wQTcSW/gLO+IDBitJLeZhcTURZ19L73aA9OQt8V+mMKT0s7EChIM1vHm
Ynhpd6iuTh8Q+CcrIjJU/3b8Tl318MvBYYGj9gT1MxmOxhuPZok4NOkl4uAO+el5EcrG44xeLqeo
E4XHe2RC6frb5XJkAFavLVuz+azSDcrkgAoxkqRI18S4hC6l9drz/0dIn8xsDVFPQDiB/ALgUt9v
fNLdwpF7FveZIGUIfPSBpLVAS8bIHPKkJAbZJZKDr/9MKk4EwbaVK6LToaVPN+RahUzfYMao4AeC
FvyTEL+WDYOil141ZXpy0OTBMefi8axpoD5zjgmWp7nd6LjXZFdDYjQYibvoi09b5/79xk8V8GZq
kvN1e3kbtfrIFx97PkImIEA19ihHnxr47wJuftQaUpVK2hcc4P1hx7E733NhDQqu07avuKU6CWoR
w9inF3ZI6ZH56EqbnyL808iZmkyLx2ymxX0SiUFjaneM/XrbQlm9VTPXwAiAXKRXdsaH/wdqxRh5
vKSSHaELaODjgaRv7Cx3bW6ZkUva2lxiYpm3vABjneuKak4aROoL00cw8Ab9NpKOuh5zlb1FZbSm
a1cnJSqkoDo7dgAI/lkQpk2G2t9293Z23zucHNAlQc2r8DDz/ayBf/ByICO6HalFHKLabosd3m+l
ZS9tZD0qDpneVeXME7AhXmQt0Rw3HaFCibUuchCvA7tjFJ8uWIQODNS1XcJtlOo2TdWC1wSIlzCa
W1iVZAH0xBpu54Enshz8u4iMTnQwJEwa8wHHN0D2zehPTwfNIPzWIDjbEy/gDu9y6qkobKZ4Zg8S
MGE/vYakeI20yICp/Cz5wPbip5jWjyb4V42J62PybS5HwCRCGE9bPNLMA/tbAJrEeAsUqoslF27R
CydNMInVCX0ISJQ9LI/MWXukwrWxyAwCQdj4J1AgWOIDDl6oyb6Nnv8Lcv9yc0te7IGfKsfSKZoR
KeJEGfZ8wK2wslsoMPL9d1ntSbxmexDdjPA7BrLz5g9khjbH6x3I7xjXno/nYzbhoDPa8i4kG1/N
PgeQqA3tkPdoDcfuSBLu9U4ImNbym7pjraPQQyF3kxEo3VSZ1C78E5MgkPNIHlQmol6fpXuMH84c
Zx9g8g40gGSYlMDTW6X+qjevNgMxSTZ0A88gaZXcK3p7X2LI/CiatgliauY6ZvxSKEWk53/WQ0lp
71tzldy3NtZ7zeVX7Oo2kR8DleboHZbplq0MKQYzlPeSPZTTjozOpyshJqRC5SxgyZKJz+T3IDzY
IfiI/ttK1HlXZzrrWJQZ/5JFHygdhIwHJork6wBs3symO/PCBq7lRUcGs3RmiEwUftI/7wfj8HHI
vN6BNT6q9WnolVr5UmorqGNWfGN6ezJbV9nEgIh8CCycPWDlzMLsmQKCBl//HUtVPM+PawfdC/YQ
bu5Vioz4MPcGVZDbFrwoKeeN+CgAAgkrtO/Cr5jOZHgvTRxeA7dEJ5tK1RB8nsexxG0niY/JDLX5
YGIYGyBX63nL55NWoGnlP3JRu97T1KaWeyEsERrDnczFlYiMdwvUTm6v5/0wWkODymB6wKoY4daH
VDee9THFFpQ7yoAhGfO/OK3Y9V38URlFHVXFhi+ONiGm0cwVLpe09usKOgmfTbuOKLldHXmtvxnm
o13LOP8mnhi2S7ZMIED8KZ10fT3pQpApSQ6/vURWxyYmRPZA17lf77To0tvBltRKgK1NVqbTun5c
6X4J9v0MJw1nCANBrNvzIXAPeHQmCw1c5X2QiafVOcynakjDSvr+GkUdsAYVZFjNwsm5cxNBHj3N
u/G9gm5gpd6yWusavipuNPDuuc29l2yDvTSF4AmUNib22cG7keKSQNHW6M2H51BML85eVE6ZkhT2
Y8Byzawwg5d5Me+qa6wXnhYzB9EvdYj5rIuSBnelX7BHGOCWkLpegiIZlsUZ5vP4Xu37ytRkSWbY
57MrPMa9EhVAq0K195wRHH55FsbafFZ+fGdi8NneMEHocvT93g0ZDjIpd2W/oU1NLxYDi1ebZiB1
Rhn55G+q9xepHajDfA3SUGGnP41ANi1NJaUNwXCWrv7phWBgxfD9RyZilZMi1nMcbnNvFCBFEvJU
zmWuGR3RGbeooUmXA84zfv6xg/pX2frhU3ZojKzHEYV/zcDA91peQHff2tlmhkVBde+m/mZxM31T
Ck9y2mMpB70otlpUS9pHLVG96Y9e6gs/xwfiScAAAPiHHt4QtnuA44h0Z0LjUls40a7eDMomBhfn
NpJdzV3q2/RS+lTWDjstmu+06qDaTeugLzazCmJej2ajq3Hma6k3vyynKSWma86S3F5Pm7jr7MxR
Csmn+nBv/rF+/HojCzsqla08sCwzIin1+JVSCPheMdl+2Gqcw94MRmmzVPLHlHja+1Rn+7mCliR+
o3ua72tvzlOTzv59e5b4I6rNt4JjoaApVGujUiXvQIgf3XVO4Vj77Lpthpa63Yq7N4RpUHBWihAZ
J2khYU8uTMsGJBYSXr4JZpzoJKfg4623cGDZvXGcDym8BoYaDS+1ppm06v+d7ynkHjMlfFpIYIS4
gCefN88bkNneQcHh3yqASQMZ6ATEL6JN+cLEp3lM286KNbbvFZpNRHH9t6cR5hezNCoiAFGq4Ggz
1iU4uYd8wwDxSjioKdOMryo9Xchfy3BtRUSZMr9fC8A30pfm2Ae3RKp6hJuxv1N0s04JugwzAASp
F/3zlL/xpHeWgaYp/0icuPrugRjWakdU3KVET/u4K9OKdvdeJOetTzyNL/3x7uPbC1rImSGMXtU1
Jqrl/KjAFg/7C/XKrfNw8+eOHcjAxWwRkyTJ923ao5SI99NVVLkxhwxvUcL3jjvG4ihzqjAQg1I/
HU0y0lgtPV3VLSmnqT7Xn4/FjurMysxItC9gaYdb5hft62GuW3Ihv1RWM8guI/W5JsUuT3t61cBs
MWhJRbkEI5F11DyqZk06DNTxf5BlOs4iRKTpRmXjIjplHtL4PeEdg3UqPq34gVlMI1a22KZJPCYa
yHQPEyWuZsZFqMh1os5b7E4zGCQif8bVy1elAffHcHMiVjDArhoD2Bk7oaUZ0iQcEOMOMZIBzRSE
BoW1ASIr8DInBuHewH1ai/RfM6BTn89EXW0+5TGmIgWwAijzxyiZPUwE0j2dpnXIlnzhXLPmmDMo
G8cW/sOHVk9yC3VzQg2rxXPx6OuXQXJI8zYUbWKad1AYwLKnxxjACdhlgC2h+kub+kysVhLo1Q04
n3rwgBY1vRHGo8OgHXNEgx8biIxHcOp4Vj0Qf+7w6XbhmbQIS0NTIMV5g6QT9LmjZPcwCNKGETo/
TunelYbxmZeWx8uV+2kxOKJeCYGsjEmdAS9QPzCTq/H86Pt7Pz7RnV/1WLGCo2smkMw5UR28/U+d
Ir5G5wFbdv8RqxAMw+ZjZyacHZknALVlelH6D9EqVKT4AH2Zf7kD6GhOI4wJFlo94zGMFNYuxWvv
cm9Q2XluY18E+hQdtjT6sW9zB8Ovzjbsb13034ZstM/n4BIY2s9vXgt+jj61BcOerRE9X7qqQS3P
gBq7XnIDsIZpXO5oI3YW7aZDyShFt9GktqdtX4snNGndrncxY80/vr5CjibU5huVKE1V+ZnOttuN
X1cayWJnifFdZuVVKxMe6v9PhBztd13GWPOY+SJlieZrny1Y8cGM08boxIFIn137CmjvfohjvhUX
zzrbs833I4PBlZyCpUYZBV2ZiMXAaluMf1b13kjSFWwJKLUdJet17MdjxA9/rM2QjNiRQTVsTd3F
3lMXXU3v/KfulmzPlgAddvovrqHIW3SjVyuSGCqRGZ9iQ8F2XfVKUTOmJaFtXgvzPVmSloyy1HJV
Q0JJbMQjBK5/xrUTff7Oogx6g6qxAL/Ydt6+Zwl530M8AStWrDY86vcrX8SHKaj2zTXPOAhwFUSY
ZtfLBq69xMI7bMzj7aIjx5H7SIIjZpVroA54/y/4ZfOSTUj4bYDWXPRnaHKF9Ay5l4M5qPlGIiPL
r83TGBEF3+EWbJjpmi7Gu6xj9GMCl7UhgqxuoAzFLwwMI54lnrImYKvIob2MFYmKmjEyM/T7sAW7
B43gq930KnIz9gFhpCC7MndhPTyAzrl6l81uK2S99Zc2I8PSQoYwA9NKB4vKodFU4pRESkpHi9wN
8l3z+yZOPMsNaEtrgwgQ7IRDSV1C7UngBkUCyLimCMhU7HL6n6zgY/SYZovWTOgtW1ni32Nkf40+
Jl2NH0xOHqs2bCKDYdxImWeBbpYaEgEnbG8RWqvYB0LJIjZoSxDoB17YUmHbE6VgN2EthgKzI5Sj
vedF9rAWEWEc/Rqez0j56hbf2+CxVFGfz0kAPoutKwg74cjCfhcMyEF58QzMBWpVB9meGL6MxHHp
rII6Ihds/EArZqAFkJXStS/5o7bcWsUOf3PmA9onKsJ23o6sPyvGjvF6Ek1aQFdKFRvjy0ScwUMj
U8QH2DsKGZ8QTznYD6Z1z65x6/PBZb7ADPTAFJwIKv2X+M8fHJvHnwG3CD1yeAt49bGSv8LOB5CQ
BzR2jkWmMMseJOyUS2Ed0S8yD4XlZN7T+B7BK8upJ3xlhh05qAVb7y8vBeyGBxGhWNCUto15bksW
53jkYf26CJ3z3LPywRWZ86zVYbXEv3yGq0HIl7/7BjLrTMC61xZQHgnxAK6atcliEAD2cS5gf5Gm
b4ycvgxh4fF5p6PvZM6mAJTdiJhgxqIZTnKjageaXwPCHcP1tkp/vJu1pLlI72tpjKc1/i4qsFln
5wtfh6viVa3j+jdWlB2OjInnUG9fy9fKMbpCQ+Ursd90krgiHZsF9lD3mUBKXyxEeyDx+z/8V1oi
LUTi25NFnj6o2OurVYyXzNV/X+p1E0OHN1vA5ta9z9GWaOZcPTeykZ2ywpRiRaNFLnZc6+O8rk45
b/OkzhRwXLkEsHwukPt0qG6JqnWys20TueCDfQkQHqZw0sUhD2o41lvBFPxLM5HdVcs6anJCMPQ/
h5obw/Ic/IWT6zU6z00aRmjKXevuflVwDqLPsvcEkW4e95ej9JFihDv/4NGcg/E+84dCJH86HNxh
94rmqZdYwNj7/bMGJPu7iYCOpsaTgkloR/2WgLrZQGx2Tc5QFg82tnC3+1oC4CEH1LX+NbSDazUL
w4Y0JNOvyl4O4jwBkbJuaWkMreENfkABtckVV8k4Ya1rD5yQ8Uj9B1Jc9CIOF7vMUAJjBGOcSfuC
x/NGZuwAv3q8zoOCC8D1phz50sF/P3nLKg+mFqchRZ2SFLrgRlYxSZc7ihInv8wLivhXXLI7jrpn
L2tqs/DiTalgdcr90XnuHAP+cz5Yx2LUCfmpeeC6eM+CmgwxP3b76i/Y1YSpsd/NnNx+MD6GdEk4
0viZIsFHRLmX5ZDzHlday4OmVhy4MOzuo4bGlGL4NnOe4DkHwgzDxOojMDlAKKAE0qi9FZ/Awv4q
mLVFm1K4vE+6EQSGLLwKrircFasDNcS0YfbCKR48FD4soMnIXR/CERkwJmp2xbss74G3Fae/S9Hs
P5R9kgQKRt1HfQnS/hINz0ehWbSGx84wPH4LkLEGEg+aRYLWsxBOYks9urqpHLqgdYjgV5zSwLsR
zGZAvhDFnI2FmX68iS/ILFrlpmyAtzdZ9J6SQl5FUqxtkKf2CJJx498qPaUZZ/MhwvEgRoskIir1
IKj33FncCo5r01yVdOh+BuF8Q63++d6DeH4q7lRmjcF1Gxe/TuJr+0HNMadZ2TSBvfUBVFNdTgfS
N8etFRMQOK1IEkIhvO4i3BYAHDahnVe4VZc+zMhGEnwl7Ui+TxbvZQxHqTg66br7W86+6KrNqZvG
/ttBPj5JGjaIXBZtiC4CLKnoXNms33aXupf86s0ZXT1fO6oriozcD7zvzyQRYKVefz6xZm3mZxxI
mxzWlxcj6LDcPElt/USS/XYNzyoTRR1rh/Si764jihw/oKgyAxzFnWWmNbEFPWkVW6i+rbvZwH/h
Sd2g0ILvPk/3vCMFPn2ulU39NU/V1BE90B5IOQRwFozzQAW61cULdPt2yZhSD8qLZl4sHllQzro9
9KVX+iAUECiEm4AXn0UDTilk4mEI9IdXwCJUMh5GCV8KOjLCrbEUnTcOCEpNbFVVexWG5fR8tOjB
fv9ncWWbCT6XOrFgPKqg8nHFhZsl3GKy9IONOkKZTFUfSr+hgNu7SNEzNggobrEpqHLtgvG0Ugf2
2NSdJYHEgp36yDhba4+5sYgQhdS5EQnFx/GOwU2xa7Sg4LgmpvqRyO9QiRTKzfOYT0bbd43CL3uH
vKv0uLivfDK9MxwRiArw8kNWHZcKYP6RCmiuFkziKE5+RziJFAsht2LLc4UaKZPm8yOaejdJfEmt
H85Y+Tj3rPDSdXFup1fi1vw2XqUjIOINvGEH91OZLNpZogtTdTM3aqvpmANmHHR126bMkTHtS0W5
dgKKNSEDXTvIXS+SJRTgdnx+tlGBGdiVfgex3CUwVxZt0dpjotvTukQYnv6PcOV+c/PyPHJZBjGT
7+Wbakcy/bsi/39d1n55Ww2Rd/jLtEljSxB7s/E9Kak6cqbeIN42XFmRuAPSCbmYbnf49lrY/7ns
L1n4i1bQlaHrZAe4pkQFWsl6pgPErMO+3geLbNu/QC9mt/Hkr9fn2l6DHLTOcEG+/6AFZN/w79Nf
MeYfDSeX9mhQZow3m4LC/BjMqjlaWaNdPoO728StfRdTIchV+7x+rfr8IWMhQLUcUwTb0pMafb+g
AuFSgR4pp+7D9jv73gvhPInxv7vJ5SADW7JPTB9NQ9TD06RaIsmI8GK1BW5TIbIE9/vKOaP8xrFQ
y6tY5SfbhadLJBDC7u4iiAvyiGM/YFHtxWnVLuIA2vIHuUPCYe5g2gG0Rgq5c7+qnKobghs+JUVR
+2NZSEeG58xqIJrtOieFvKvD+PMvNBi4daTPQYAU1EW/SIR14Yy9Muyg/Cyzdq7s3c1mxmIPBxBT
gZt24ncT6Wa86L1c5HSy8Hkleqzu/snO4OUyGNKCDAJOonSKaNZkMBWQgyBx3Lz5xbHUX14ZooDy
YaVnuKDbK3/8SniLO/8l1Cyz+X9uXWVxYGLg9yEH9HISuXtmhbEnQ6E3iekcMDrs14kdw2Clf2cG
qJU4FEW2PKgBPWo99tOCh8ZDNN8xX/MkC5Eub66PgxEh7pZzSZUiD+9ik+sRF4NAR2FaSwzKGjqC
x3cfyR63eOCULawHTYgnh7qvQWXTT59Qutfvdz5o/jzssaZujATTEq79W3cMgfr78+sCnfN5JMlx
nS4kvliP2iFOq8py+buAogG6m+nsPOvf08GKJA5Q+uaeCoMmX3VG0ly3cSh1WpNUOPytqqkhuRMM
V5ueS0DAJqUkzv9+fSzGMwPXBPBtmUNr6ZyW5qeiGlwU6RT+nq23yUmizO5CjggkSteQn+g2XZyy
RkE8sD8lNfW/vmXIcqFK7rKKFtFHLuCA6DSvTOVxXexvmOpcXmtD/SMrqJI9EvkQM/0MH0NEj6KZ
oqHRgdn+M9bh1acbeQ7WTcP6kZ7+FTJcZhpG2dVEAf/edsgrojzDsrCiPPa9zra5+1FcqRmI5i5R
T6QkD+XD3CWZa1FILvFLP/ngduk3wALJI8BNYoNSWQKM8cXG1k/j63YnagrhGj3YXq1baTxiTpkY
hIYDKbFEL/v7MuEnw9nSh38926osZX6ti2qXISnZc5QWuzvdxi8si1EaYm7tvKOiz1q1khK8B5aU
00wMaC8Nm9e7gKB+de0sqnbhqzNxGfhxOO3euJPVLkr/MvI/iC9C5JrIXBrhhoNW5a7/cM6CSLWn
5mMP0C++9DQWWA2cWzxRfoQJnvftXr0m7NMZNJMU5uz0nXzN8MaFFagAsJ1tnRXbSeRTvwNFAKBy
uWj/fER4HgNXQJ9wAnvTYMfd2WZyPE5Un1r2z3z6vXBcrdPNIvqB3kl+laXUmFHtwOXOt3hDy/t4
EnNw0GM5f6lG4h/r7+eZ8VXwGZIZjxIaVT/N1Ny1dE82YsOot2F2404E72OsucdO098hyJjiFFdI
wPVls20S5ydpoJrNq8GfB6lZMVp4KIKbgIv1LzxF2QPn7UZXSuFNWO3OYRsUz2ugAhge0WAitzQX
0Gw5vrHdY+4o2YHngBXZFGPC1Kq/EawL6c6lbP3cSw6xcebMzhhgrlqRnacKB+Ls546dCqKkuQ2E
hUP+Sm+RXhhOP81k+FufQhm5rOBvTJm7iSEcWrbM7MQ5EliE4AzVYo98Vsi0/89/Exqhyls5EyD9
3Sj9FbgMpv9N7KSJAjNBOfYWx7IJXq2+xsE+dv3vO2hYyDIsFYx/SQy/ifOr9ubuMb+nT4T2wqkN
C1gNFa/EhwI6DrJ4/4SEWx+/EkhbR1dkD3lsLTIf7P4mBL520VsLPloaKCEBh/YP7EwHI5Xj/yb3
Jv5S6aC48zhqIPDOPGYuTeMl//ruACHQ2aBlFEcVTI2DBL9n+cvBHQeC/Thh87yEWa492FurXpwH
Cna6cu/REPdRY4BPhYWk4YHXjKXWyDwgiRpjPYoWSjVj9Ne3ovZEbOyHHgfhIxW5RVhL8j5OBpup
QSW1ax5Gminj7zxw5w/FLFncJ64WiX8PnMRdQKG+Xyp8yYFUwfUkuH+tC2dLSrteioHOFAN09UTj
qiRyDMFfSSniuBaJ2YJRm9nRJuf13vsRlZwr6ZamD0ZdgRfT3THTvdtChupRjb3sDJv71UMqzalx
sBHRxe3dz6qHLtWqCRezT2pQRweknp4/xhH0dgt+gOg6hkxDTws7Pdr36nMiV3u3mqtqtV8Q77fQ
kkkJR3776lIW4qRWkMVGbShoHKrQZfufrJaI5x4XzxDu3CzYapSOCjMMvSOq+wAxncZkvx53w4xp
pdH7FolcrO+4+YnXpU7Mb47wO/8FxsukKRmGrXdKL/6d5MZgeyrhaneuWecS3r9J/jGFax5stkkJ
AkVKHJmeATwTEAvUu/5h6ZczIYxETUPeauGi4+0X5Ti+ljWxDHumKRqCDqCshK5i0lvDFCEv9zpy
oaMqzKzmHTw8y+YPo8odA5KNjBMK+ZKwo8jIp4HrcK1sgyAZCuFoWSqfWYHgveFd5MhuoKThU0Yh
BzwCZoGtwy7mdPFb5wLx9V36T+Zan9DqAJTZ2mJtb1JIBv3BNvclXTVaC5CY7MwgGc/n0sJTaAGP
rYX6ReCAu+KFJSPF3ifAzjCAC6k4WwUyPfNOEIkQs9ks+8IyJ6ecF6ETodmyuLwDbQTQV4pygEb9
ioyig3AGuklk6EF4bFu0fs9M4jiticpaqRHAAI4skxmCRlDS1yHExvEcJt1sBBcDA4U9EdqfJVip
xRWQGyGUpepbTDJfGSEUQL5cuTgnhq3rE0sbwNgPGn5j53C+bwwLF13/c+Vlm9JsP/651ARlJDlV
oJNMCXy0ulxbk5q1uwHP+XgSKq3vGKLEpx2m2+vHiLBYgKzEkeWd0K5M8b66gm53xj+YauZ294PW
CsXiuoJkBOsUtiFLttxZuXII+c+hI2RkPCKuS64lt5tWMRxv8BRR2qkMyPvapI1N+xUxJT2qnlxP
AoG+waSN6GNubCkbBt0C6UAkwFwySn1HKEF0mQIrYmve5yXxpYIIa+A6VcUHwJQ6qb0ZjgG8JIU8
3Ty1tGzC5k3o3ElA4O+KAfoB53AriqK5/rD1l3eKk+Ndq9e/S4GW091Wpr1qG58w4UOvP18G6jJG
oRj419k8H4ONcheyN3Z22mQXai+RfAOQpSZbm1j5eyVV1BMWxnk2PQsp+ff9tjyzEqe1/hINX3Qe
99j1dsPvv2pgCLtFPCLm+dUPzq5n0frSdL/VF31G7nvirQM/uzPDxLG9ztzbk1Cl8uBm7kuluq43
xQPRhxiDC4FLN1eDPvz/Cxz9uQVc/nU3c/P5NfZadJGECLwAkzX65Odc1TB5HExwvHj4FDzdC9Id
GxBbKmXY+9C/SvmylRZl2u3Rp7iQSxBPw+vBMYJtdAJmAgshQk6FH7gOMBNCz6BXoktGPNxeZyQb
sXbctc3RLkKQs4ssj4o/WWOZkEp3KGo+jpRJLklGtIYVkftywrJA7Wyla4jjPVNGa/ir1nMLmUKQ
rSApUIggBH3ScTSVqsU9aO2RsffmAkOwdzAeYqSfqF3ZDrtdQDjZ4WWwQVPPH6I0bWv4pv+u6jHe
b+uvugjEvYrZkpDunxVYpJIzHlMgVJbHx3yKtVFnJRpYoNLnO/EVRYLAdaFrooLdd/asUX8aL/Rw
8QhH7BG3F80IsKAiNSkDFq2/4iKfsGginY7UWkDFsO4Qi+UMDqxUMO6Yl+DbtRjT3+UKBFlK9n/q
nIwYL5pPkGsBtjXNViwPjfDnO34LTXgq1ZlMuf3heylEcJD9JyD7oXBHc0EO2fb0fAqEOcHdwKiK
TZ/4hn5TCYHNGetsESjAWQLWB4z4qaq1UXfQ6sEpeD+5JXVjrgUTx8aqZNMPklmVjn2FMH6y6/nJ
XyL7cXizOQoY6sTm0H4V9qrAHIw2yflOZqTXuAKwzaiBHxE+2lCNEuLEvKXU8GmmdEvjtSFgKwHg
QVOlB2J3LHCwGKgXxB972Ajue8QAUXtZ9KKYCR3JxO/l89q9q8jnVvbyYxOqVaQ21S481p84ddQM
ORfU8jqT03GqFmx38YhAIaLVbZBTe0RHUjW13yrVMjMDz7Urrhp0COfR5cG8gGx9cmi2xMZDcf7r
0b0tqM/txcRJUmaV8+/x6cqBatpAgCjCoXcpyh37m/YDJ7tKuB8rah6Yicmy4MluEWARip9Zd2Oq
8vsbhioK/iuJVbcBNofaG2jUxkJuj8VDt/j+uNgb8K/nm6Wjf7bPGoSQoxCtpRQNWuZMukXQbYe3
bgfLjyp+7U5MogNk83iCuMiFo/a+3Y5WOVHzThvdHCqjQZrSBNpHKlpPh3igOaeow5PbXRBGlII6
xi4U6Nm3s7Bj+PU9IqZYfpkY4QO16fPOlQr2gwBorW8Dn2o8/jjVw7m23ySuAXnj7dAbD9Qht3aJ
GOVCndRDZtgF9PN8HxZsNYu+PdZV8yzsHfDTsz4V4hIyYzZ7t9glyZR3ZFDqNECgchRQCUwVbAiZ
RhclIciaCs4ZArqA+nHhED24NIP3HE45peLbADxohEO2Pyv43nsb4OIxnQ2menmibbWCvzoawSut
4aHqZV5UfN5DWLaOBxGZg7xOYBhXRWvtIzWGJv2tqb9yFFS4hmC8RZG1m3uyOPffbLDEy48VN1GF
aGX/wD4tYGHoxAG+7pEDdPjJtxEowiPmiMXBeW5tB/okLfxF3OyTDoUyRvrbuSiSN7l0turLaMbM
pjqxp1njDo9JNrqK66i2Z3JQ5zga0M6v7oPT0oUNz9nGsOjIbc++VsjAfO8h7uP0ACEbTi498JVT
UxGzU4mYj2XKxEPcK04JKWw5GHzC5lYzg5Ov64YMAlC1Rh/UWl89EqKi+4kd/JjqTHgtWda1rsio
h2qMOYBwx3cFpp/e+gidneUdvpQYyyWW8xiJnZcvTZS57JPglrslXeJjPrJPAbvlSty1vJtaAoD9
6CDLBtcyGY2aVOslbDite2NIy7dQ12FywffGmjGLI1YTxuOk+iFSvPkzWjiF47Osq9oaqrlt6Wcq
pBk1YEBAZgLpo+suHXoQ9Ljf9ojBxbJ5c8i2aWZQoAgewxJAFr9cuPlPIm2gYckvoAdGtFlaQupz
IRON+HLrIjRPPIVQ4+GHj+VUhZ/71WsIjOXk8pY8WsiNIZY5x39KIu3mjxPTYY5UEDkJ5Y9Szn10
qGtAJfTanAp7audDqEwREB+SrRNoBH7mAW2cLplP5LF5pvvUz2MdRwlWmDVXUcyKvsgj7OGhPQMX
0zmajWiyagqwGoI57KSb2sZp4gUDLDcOZNvHSWvre8yzMPOzBsYAZn29aK0GgsGXK9zlFk6XrtKf
i8RjbHaEYWc5FmiDS8frlvcTz4TK96ZHLQ4ByG3ec3OaDp6eXk4o2FvoPOSFDqPKhmEcL08bn3o/
buDZxToIntuSrfTfo/08MAYus0zmpys4vWvVWGaHBgWKzE5LWRno/1XOSe9xvq/jgMRPcnZQDxea
Wa928iAYgV/zsDdnErXNH6rghWAn60iQ+bLtN/eq5Z1IKgFDbDaeYBAsyBifNMhuzqxHG4Wu/oUu
zH4uF9LRohJrrjV2F7VhZ7EpPdHrnHamArJBNx5sMRtMVXXFQz4stHQwfPqaOGZHtbi+a5QjWWwe
0Ub1NuSY4zJ4/Npk930qT60z/wNb2MhXLYoPxdqZHUycHuWyPyODLvOBJEOc6xVg/aHHEPyMwn1m
yYr7IAewIxow7tzHnSp9mH5BhxRadlWaAaxBOLbsVEDxVX5LdD+zrKnMQyX0tVd3Arz8Itfda+YG
dsN9fJ+S2hq7u/ptOwU0IAC/ewB1f6ynFtYuw81RXOfcAQupgIQcMM53nLFcmNjZ8yGYFCisKwig
h7V+J65SozT3cX9FoO5gdssQvgFpC3LEld8m73uhwLMZqpaGAoGiIg+Td1BacgqUlEFyBDkXSZ2e
Sfl2zx67uOoEfUx2J0Yhq5bj8agXVouBXdTbCrLaZNjeSSWb/Ps0BioALpSn28qljkeZzp687yd9
gHb7nhwuH921o/ZBLiIGgypl5YVx0VI8LRaoV57FuzwgWCLaJp03qcQTqXhJj+TzTBW+yayOEBBB
y8JMhg0eLIBtzcSaIaGnTUQV1NkdObhXAIxye2iBDO9D7JfnjJM567fWjG9Bj8BurxwdQWepcn+2
Ph8mD1WJZ90jUOWNHV/zn2EEoT0OuV+WoDKYD8yaL2bEeVjr9Ts9IBbxo1wP7BDF6fRoDs9pvc03
6+4rm6d2p47kXfhw4aIu7lSI14Wy0fLZMWnbHTgD8yjHZnZn50AecrHZP7lO3SljQsr/eNPvDxTf
PmF6gGlRfRoHQpnToe8dLA3RfpiC+VLgrWM2fUSkb0iBaowZOM6GJ7tgz4lOIvNKhoctmdXdHqhT
tvA1y4WsXOJ/PTm5C0HgiLY3uXg1A3EAu0GnEEGQCqSoh+bS6S0suYAhZEe2Pp2IT6aiY7GYrdbh
yH1OJo3J8hhkLFHpJrv14qmsqDjHAcwODOCVEFQGOn0gBu9SeikpmUnoXPZyEGHyw984xf9x54VS
5VelHmraNznEt83UBObmghC6stQy/OPY1V2CQuMEElgFLYZbL5Q1w4myyvNtLxKaFKGw7cvMUCYF
qIvX70xBGJzfQfuetxpFkDrHP4lj5u42rIu4YOqElelaw07EmaNHdynTlZxZ7d5NxUfrYrbGU7+E
DXtfd3aaR7bz/Amvp85i0F57lAah2viLYRUGGfPuWKgsmI5/JSykcHqRQo/eL42c1G0M/cbqaBXi
uJfD1j2+4rn7X6UU3gEQPWvikHr6edwEh97xW+tbBzuEb6l7+FJLdhNoZKSzIOrUQEHhNQxsu8By
27s2MesFE6+5JEaf2Y/WhFe4GvphZdaotX35aBQ6S2TJvLrEjgJ7KBKwRAT2QBFauvUXnhrK2byg
ZNIzD9kU+dh0zIAM7rTgk729uSCQU9o/Xl8yd0qNRWb/qyOr4VY0aqYZtt70DKwT8PtnmujG1jfp
4Rel/TjUZxnHmd18m12K8lI1Fhcg8CyHUlhFf3Nvo9ZqujFJaqDfBYgxQaU/mQ9IBSu1cdpTB9nT
IuwOmzJTF/qFiMuoEb0EaCk+6yEDOZ/GKpr4TRbWTBtgUKrX9AFaaz8ejelErxMkzDZ0lzzhSSc8
gI8MimvBYF9DBbjq44FxzxAwhp4zToVJVlfAn04ZsoWk2FstnCVjgw7CvWI/EvCOtmC95adt9baj
d/+zT62Jd2ts1apCnyLOcXiZTCVBe819syEa/6k241+VWtAEx/zUY6LHTr6IPhKE+ud1WHziACnu
xKyCM8x+PlrcOSlt3OM6/xxGhfPyTcKyUPJb7bJp1xF0wHzpOI7kJrw/Nk/xQE/Vs2FUKWHrkZnx
OLV/xB1OfPuP8cAJfE020dnbj1dDAY1u9r4ZlJ46Rl3qNCyAOAeReZG5ZXOKyS6AMoACzifhRnNB
apozNrWCm1BWF/33vpKGp8Ai257XtRZFvj6E9UWhyCeKbhdBVjOgQCjGPqjQvzROZjX91nkX5L0s
YJ+DUYc1uw3Tv1oznamotL+wW1KmJkRA7tPA/9wBkF1PHGgpy+3lsmIvaPWEdYmWeu1F8H6Vhj1F
I/rZV/JFkFtiRWqx6Cq3dZZR7ZsaSSiDSOyEHZM++ZG5AAMmZq3jI1WBEydISqinkaUA8c8RumIV
IK8NJ4NUFcSOngLuTU0fcROIM26veaXjpJxvrWxWtCDYvAVhUMW0myXLPxt8i1nMtPUax5asjb4s
6RsvGo7h2ySIB/NbGNVa9j2NXjRGg3BtTzotKwEtKRq1AwiXhhlXk8YsA5G28HtONiWbhLsKAhxn
IimbFYVxEZoTkvEfyKx3Y7ABb9YUvLQQQaIYu39ulYYdAw9+2/ZHmksHK6Zv9JGrNoeJqQ0Dvdsf
yi664cs9tNjPM3KwnvTZS/O1YIdUdKqMifx/kbi/1efsVnmVo98CO4IejLVVbYDocX6qR9jd60og
Rd2CO+7l8XXtt/ny+/W79COtxXeoSz9AXkLF5M6NeeJeKr36Tl57G3MXfbA+NzvHslbJp3bRAm3Z
AjHzpt3MWQUgaro5bpmYwU0O1IKyYvhJEWi+tSBhUd9lK4ccp0a/3dulwmLcC8JqdGjScrcnv0hJ
yElObe45hUpcJhnUH08MiGUb9geZtQndhdwYaC4N5n8JVMIKVg5QJ7P5ffJmSoqS6djWr/Ptecq4
FRR3hGB/rYUmICrMdoqq0PX2LvlgYP7NQMaqK87fV0pCuTOOIP7wUImObQmjN4+OBNj/WhX6tO74
HFkhTXxXOyEkY3MJR6AnFtcK9KEDD/yvIMz8QLk6i94uhzyQls0h9G+Uy2xg5565y8nOCp1zQEaD
dn5qsYBbgB6+KY+PhjpqcuiKejxbPsTNjInivhtGhuS0cF5lMqVQC16OFH3utIMxB0K8EKfKSDlj
hoR9MYzuwOiYFKTe8D3Xtin/XwxQT6FFdUo1yQDKGdbRdogeGwRegCCb6eOjT7DMnEsp1ZEaxpSW
5e3iEAw6Bn727arap84i7zmsDo68x/ZJiW+QcpVatrWPTNAmedi+lOQdWBUSeYnGB4O08NFYT1Ni
FJf6Zzc/5/poBqS9eGm6ewxvhF1knQwIEcAy1dDNbqlslrMPYBxdKZcf15rdPM7uNZ8LeyMj8Vlr
ACxeKZQxxDaRsiuYk4kKYuyORJ2YWp9AXLytmuikMXUFrMFPe1Ww3wSPR/w2H9Zs5O9F8iv3xqAL
jUiXhTeEQqYWCsiIVZ1/cB7S0CWL3dc8b7yA9vJipX4EChNDe29ltBc84+a0HTgInx1ChguEHAxO
Q5fQEe7uGV7Q3ylXBCOTdV2Gy03O7SxgJO4Q4nnr9NivMQWiDcoQ1lcEhwtrJRqplFO+1f60aPFD
yqwa03aQTQWHm+y6hCQIFXeyq+vhSKVaFZXVTLaDQt9tzZYWZoUzvlDhsJ/rQUTKYkKh73EvSRLD
9PgvUXG/iAkYUleI4zqV4oYk7zmyAfU7lddbZqGVGHrlNCLN6lyCRcNS485f35iYRKQs6q7wj6gh
VdOzrmTnyHvlU+VwPgnOqrwJaji4HRS06tQUufeJL4Vet+ZnM9aIL8fAhcDb8fC10S8heYso08TN
FngCuT4fmbbeWxhOJ79MIrtUtbkMV4WGj4VPIHvfPIOyPttQgqEYR4CJ1F/BWlEk82HgMC4qppH4
K+DLlWcHiIEHjajopK4k/F6o3FEuMddqIGYkucA8vjYLQttG64MWBJEdQy2bgpIlJLVMq0iWhwgo
i0UyU3DrOeBRR/icrA21HfNrRRxRXwkdmd9AGjAw6xFrBwrh7NFTCwOhwSExaEAN9QlioqbvrOih
/51WxFmQoh4prTNwbE5yt1tZ/GFbOlxdHakHx2emDWTSsSncs8hZ31BLVKo694B3DyAWNIWT1Y94
Rv7YFPSDqA+MIggZQSZpwIa3oelTqpQGbpIPQ2bOvcYdJel04zWqwbo5KEbFIxS7EEQZsOve2LfK
I0yO2oOOHA7iOY9PjuljHe+F08NjilOQTAcgWfBGObDgTj0orTT8kRsrMuHBv7V2Bc5rLKPtH/bP
+AbPduCg2y316tN1dTPDkZ46J71erWorIWAEDP1oSQMCHRnX25gxb7wOwELNXfF54WKyCULhig/B
+jCnfr5h4XTLhCcRnjyEix8l93i74MMKCXKBaZwubn8Mg0SbDret8eiwZ2SRGknCs2ORnl6c7pSV
R5VRKMK/5f3VNrIsHtQIymvJBTtOxcBNlCnCqfsVoaHMXKg0QOoaf/tFmnMaV8y6UlxO4B8+1D46
F3ZoSz7Nko8lRitdJcxA3y+Q5pbrHoxzv/ynMkraqiV6yYo75OJ21Uuhbyql2epNPW33kAszS5Y3
oaQCLL4imauHiGKqe1ABqkTyzFOekmvDYxiXlDZ23vII3ywMWOkstVrl7wkq0vMfSxPyda9eijq5
JUevaCZIjefui6M43FCuuO0suBcFz95JWAUG57gNjYiISbm1jGLiTQIGX2ELE3Nt7opwzBao8mWm
SLNC/7N7txgiH6gwWjNvJByrd03iFhhb2IJCaYvVxn0/eu0nFG1r2Au+kzZhBKyUWhGMeRkt32fT
HnIt5W5nWsuAWDXWkVJ5d/KcGskAOK7+nuJCkWDEhI7kplO6EVZgid0oF6+ytSvbSpguy03Uunu4
9fpAytFS6kNzZMTVAsKrmoM2mq23VCFe4PDRElQllIi1PwpjGlS2zaM2ZYHs1tfiDfMIcRmhuw+B
cQPGuKvOCM3ugiOKdfhIkxObNbIWAXvNi9kiyxpuJWaWoQJBS8AYH7lgqeLNxjDssY4oyO2y7I+Z
S8AR/GeRMc9s0QqNIGIAHlUwFrqo8AmAQJeFi9OW7WsrRxamhoGUwqU59fymTNS9zOVskouPuPhM
usQX4Uyc5yXAbjqTOe+cdKPLjU4D8L9vmfVolpxW67MdRE8xH/87jFKLg6zsMHMyKYCJMZIbic5M
SIG64W6ARSc7q+c39HBN2AKtxNG7xXMIf/TDb/5ZoO0neIXx2Ojy3KW37AmYi6h3lae8K7g5yBqZ
UbLsIUPV0ISn2q/Jnhwwt31r2E8fL8qvv1KGLfthqH0cORzBU7HXO4mFUtUPLPsnflmpmApHhNU1
tHQGJlFl/MIgDeOb5TFjUt871aFOkb+jDJK6iSukLb+lj1OsrtCn1VQ0QtPJytcCgkz2TFH2AeAy
rskrjACnnAf7wtRWZwlh5/vpaaTDw1OqbC9otwPjjSU00rNJW5u08Arc3eKbUQ3odWqA8eZkbS+I
h3AI9Sf3M0ot5UdCBHzVVTSY7kIRYC9aDi9CKfMCvT+jxZaTXDxKSGGyqvK+w8Di7ZVibUbg6ds2
TdKF52RlKwdXc/C4AzCmdV2uy+vV1IPt/ofjnNNMI8jK8QXJHmFfJWn05Us60PAvpy++1VEzQTMU
jTKwqsNRHOM1+JU7ZyfltDU53bcdDCGmnfsXbN9d0VmK3lQIX34A9L2blTyyKlpNw2x3HT0KXFU0
kFy2AyWf1LB9vgcSaXFChgznLvTCpgg89FyoxNRMxy1WzknOW5n69LASdhOchMOzqCTOz1dRoEvX
eG/Yq1NPlI3LS7+Vc7b7vAbv0BdGc5JRAhNCxMa/iVlQhUiiMuP3hkvTshsfrTkvfNLUNOvwVmUs
UtBIgAdV6byW+LpB7uzZF2nqYCnqkQMleoj0bu2kvrtPMJEfWu/8ad/HdzN5zfjs8InRL4SQtpdV
6Amo3yOr0FYHXiO9zAiZvQyuC26o5LcNVMcYzVkSUvZACSS7ejC9Aqw2NqestFSmBxVB/OLjW8tP
CB4T2+8lczu0j7zNjdPvZB9NZdqIA6QbaBC4HIYvB5yLvP+Q/dBFXGiwYFl8z3uTrgySN+6d1s5Q
+Kic3A0MQTbFUon7Q/GZh7uuQDyPYLkw7Hxf0Y/vIMqJ32lTGOGK4nQeY6+mIqxRv54xMdNSGlAi
0kOd7TzWg/VUvAwypinpFzTkP5fnguM2KdUx5h+QX1nEWHWeMS+w38Jz+2dZ2I95X6yo8JLvByvG
ZOVt30Ncw5vu14a1VsRH3pZjLv3EsHXPqiZi6lk1Gzn3Fx7yDpub0lvyJjl1LH2inn46cknK0ERv
XSRh1wrUgEUCdZktLbH+WNX+oJh1xzhHlZRwJs1jIhbYO7phkvPdX1fYT9qrfnZBCRdR7hOMQwjf
TomBL6D7EyyuaA60Bzn2h6+dQvNHHEYtmttec2qRrHv4mFuv+sSyRif5FXOxZjpS98X1rOmj1Zaw
No4cydQSAKW7NdWP2kugFFfm1QA8wmaNyliRJCji4386im4M5QzQJ4zJvJeUQFqzlrOx8lPnwI+4
0VhUeWZy0Q25OxJeNiI0uFW0T/sJm31cCGklmWdTMq4vSRbxm3xxW/ULELVt+cwhEmDvFzphQuNZ
r8aO7XOGMwBFcwIk+w18HtpUnGmhk+EhU1uId9pcJdsXFrRqmnUMxUlgH6QTjEkWi+ONzB997DOb
mrBZc35W1HeB7vP8jXyJ10qf4MmWe+6yQbd9LDdNG7iALwqeyx6DDvzgFmyV0TIEH33GnOGBfDfE
owvB1pLMBKKuDW3cRcmWAMDAYIBhvdL7lOmVbJuHAf5EM+YasB6UAOBs/aTHcKsRy1ARbyEQABPp
oZYM+yiRq81r95by8OBYGacDuQUyn2fJpuhuZBeb/jQdc45LuBOC5hiBTMu6Z9TR6u1bSSf+X8jB
DdqpklCcxJJyO619JQHVwjCwVM7ZpvDGuF+6n/luCcqe6Pi74OWXV99Xru52kG1AKzp9OGNBve+k
OjRUYk312gU1326X5iRvG2ewCAkA77bo9zWgjxLJYyMXnHgveitLxMS1Noxh3AY3XrF2CHJo2CMC
sdS1bH48ekP8xuSr26gL/9r2r+wrAesRInQxEWzg8FVYb0snzhMGeymegn0l5/TPMSGbSNHKcKss
TfrMOPMsq8qPCW6lLjmMf4jq63t2M5Qqd7k4KuUgXVmP5NxD/kb2i7HD/tXC0aqX15umbTnAyuvM
1DTsFhIfWeWNLTnYoNuVlArKjak73EsvjE+pIX/hKFCZN9M7e/CanxLCus8eMicFTwt4tqKVS6PK
XqHcdeaWCm6dP3+SdClTmRISsXVLqOaE2B4ASTPyd8u5BYpDJKqxT2evpyxqgppYCb6HvYD6l5sY
9/Z6mXlynfYuofNl+6Z2dxGY+TPo0o2bQ1cPypUnnzAurMYNj45hZuO9AASDUlOz9oFa7F/LAzSm
zuiMmQ3XggEFhcteNll+pyCX06SEN/2gpTRyBa3HG41yjk8AlQ6gMYNctQmBa88CoZfjFXpoVr3b
27ilnIhb/8mS6nqWiZCCaFGwaI+KeepyXc7h0JNmMLVq2Ckzr1dcmkOjtoIEgFE+ImqfNr6A9g0u
kDJFvP8QUQeyFtszYcLayBc3BU46wYtXwNEc9anpFhUrSTrBnPtJCu5Rxcp/Wh197+vS2R0SUl2X
v5sQ5XdtcgPPBYXYX76QRG4QCqxwDPO1sDpFWa5wLuth6aareRD+rH7VMvXklLcFFMAytPMjqScu
oac8+Ro+OMnH7w8WUNHRm7kIZ+rBkod268glhqiKSY+ELoLatPupeZQzDCsXbAiZDuHtmi/F0dI7
pNA2oauH+J30rnkKKJwGZi0kCbYezFUs5fxQ4XdlmTeSdmCPloCfrkH7DkN5bjntW38Jm1qTmKCb
+KbUHUsPC11WKA1y2wZgST2IYBDj9UH+nCqkk9u+2MsL75T/APvF5tW9THIQXjHXBcjpJHFwxJzS
yAQtvYiNN0OyXAr/llOs4n7U1XBUFPXxp7/ZO9XEijpfkymqUkjyaJc+C1tyqb+1K1vTSrpBb+dj
/10jEgGwPxaT/7dn7xwBnhoRgNVyYKA9oEJjqt4Cq2NQe6sBQVTivKtHIlTkhYoYg1P0BGJJpaNq
A88rL/vRELotKI9X+KF9cAcXB99mu/Tl285aDvaJxCoarRDNwv4NVL5RAociB9dBdjOhsrnfU49k
0hxBrbn/7k8aUS+ntBRw7vLjI9qU1HC431/f+S44hcGZEgbodbSsW3yqpjUXMniULuCZoLipzJux
8F75KHxJhvAZJ2J/WBZyBsVkllcI+Msj2v6zHgObupqwHRn20izVSpeAmSGvR1i40PDcO5hNOHSL
faP1hksIWf1EVOoniV2cY2Yd/8u33vAz/cyBaAbrrbMp8SflVYsNKm9InTTCZRzvsaaCIMvz2pVT
Zpt2BYgDUrcpCR7icQHBrZBoM3jw450UacfTehr5TY7aOKin182mpSs3e/ivAwkoJcKT0xdqLrws
XDGG3EM9ynGw3Iov/y5JnNK8Y1Vs93kSKpLuV7eQdhZxJhu9pyDVHM1oaBPKwBM83aIXEuBq7ye8
vvn0//aK5peJY0HcIg82kP82FySREuYTXE+bncm2Ez8caRp7bXk9KkZroIEoRWVgHDjMvevTmtZZ
L2CH1fDyAKRAkj18w3KD+BdUhEUYwhnHKFjbiEfGIGYRe8U61K3yN0MkzNmQDP3TW4eA8Gd9kMqY
w/9NT6ikydpxO9Jv26lcgzYPJ7BmpjeZyle9yRc9lb4rv+CBuZ/+hNSJALVZdf619Do+fz4VZ6AH
TYPBbq73TtNQ7bcPLG0+U3CdvnEmECoH3dl3yo83deElWNeBnn4Xg3h/Kh/xIRyR9tZPZnvw4tEu
aNrlfWQ1HqYAmuagWtHyA5h7JHuWBlx/8NFJLkydDWo3f7B5UKLEePtGfopyhZmZIcoCVWyjFFg6
d5E8oA3a2BUM++i2cpPkKUZwr4MXTFzSj5sGJbz4D10rfAa/i71LMyzzqdcH9eNkdRuXIIWcInZQ
5dUeMJaaeWnWAgDZ2tj66RNkLwQY7I4yNSxmy17BsI+x1R03NNAKOZuzR6eZb53UZvvPm3e1SbaZ
DCH2U1/cHvQL1pm1wNWLCjiHL2KoSHByOfAkJ0KaRABDDiVff4hCJfIOzPFEfmmZdISlA99T25RU
L11z3ahmFvJ7i/8c1FTJRclgrLwKlz62lmgQZGuBNwuPfN2wMXv0rijD2kyET8HCrSuQxX7W7Vtl
nqQllu96kU6iF+REm88pvJjWJvX/YihYC7qO9gDBRTix/qFXedKqaUlIB/kL0Sal5sBsj8+kQB5N
4ZwljC9uPkxGmcr6cCfX4KfoQgaHsQS/cWL1Py5mexblRXOWf1s0t8Sd3QAlTqmDEMvtrcciPYxh
OPyfsW8ioGCoCccBm8koRtHRuYAD7ysrzoDCotM2NPeQ5lOEfSXQapmLf4813RfMpSR0G7j5pl6I
LPItbA9/PMMAELD4gYaz5xNSXgVN8UvGMN/sQSJQHMqukzGiUoC5lS2e8k53ZN0v0jko20NVvUmz
qgyQaViUUj1lbbcZbC3lsm2nP8OZHGzYiQmcNvDqUfLKyGqeh11KHI6yfnIpeMIjcLC/zWHbwe8d
EuSZBpruBlUvhTX8r2zD4Cbf4H3j1mRqH+qspuDoRgKcmzwf1nJ/uV8bordWGiHf5+ll6UwxKh9+
P8IRBBjTKjClnMwlX1oGyRtPOFUunO1B4RkhlJk8zsfKzKbRhCqsNCtthY4Gve0oJQLaolUPTS36
F2C5PxqrwnbLdIxEOX7xCaTdKJWd5XNxSz7QV8FC2Zb1niVqo25Nb/n2a2HNJurao8ash7I3gRAU
lAi5f+KGBpFOn05hJU+LFxOg+SBqZGsZdfpN6jrDhOJOfOJwSs9amIn9vkL+WfZDdCGRXVrnQB8G
i3ILCGGw3pZ6ob5p6fBsqG+yRBXxYtelO8mID+sUzN8DZsyLQc4Uo3DcHkkORes9PEJtJI+4ve+a
vaOYBcpCTE145cayTR5FGXdMLJnppfzuopakq9VoRAY6guwvWNjDN/9COY+VddVBOtUTxgCu+CZ9
gdtVOYFu1PxS2QoUH6CHTR1lSH0+lCw96PN0QN7H8xqzZvtrKrwj8OKdMOOupYhftMq5TY1jmzSW
zviEButrGwlXmWCoOSbWlA4py+t9imVKP4LwTc71q13WQDocN/FRP5AGOhr15CO2RkLLV+LdfqPP
oGUJKq8dOLTeiiCVUmEonUmofPt3VwzKknHS8+niWYRNuGTORxZOvQjOPTctJOAjjqz5ZWzih9cL
FjRjnZa8V70RT8Shh0BFq+fSiiKpiX7tTGhI9dsV+jUUQ/gGwRoEj8RTBL0lHRAkaBINCD6CiNcb
sRfL9RekwITLJuyIR8e0ma+fx+b9KCCE61iWespIR+G99c5wp91GNd3S5bxVwqVTG6IkjEaGxs1y
tm+e4H6SiQpUL6S0pRIucZQMsTKjsyPKLAv7xS4uCIx3rUfbJY0fQyaPRNnvqq52Lxat4fGUB/g4
L48C63EFtT1oO3z4MOna2X3qdiKmKKVeRNiVVwZ+n7OMo15u6+HbE5c1ChqGQo1IWXzdip+BqJsP
6w2Xf63uR8X7su+N/qUAXJPVv/9tgW5qeDnqQTUd7nCwNNg2SRbXJ1AeUDa6O8U03tGb9xH2RWM3
gBTw619rqffORe6LKDdJ/0a2dFeATGShDOeyTeWpukmDRmQHxyCKbNZbiQmJGnvpwGGEXDCW/P/3
9plps/S5NTDXFdp8ReTdldJmXgKoRN6DQQLaOw0b0f+v2g8g4+NG8xv0WwI+PxelYxa1kxtKKD54
FYmSdysB0OFwTg1p8yNE3d64/eLB/0O8I6oCeH2bpg8Gdeidfma1OvikLNlcUvz8RZtV6KXXzHiX
NXP96w83IY39DE2qWYqvfSPzYItmmqniL2m0syPqBOG9pRyo8Z7RZLvf5wXazrHs2u0VWpG9l8D8
MqJ3BZQr2oZgpr7wNzKkU97fildQ+GjJgL0iQEHo2kYtf9ocptQpN5kxfPbcyiJaKUr3upBAS2dr
3jUUhK7EGHCvUoDYM9aL6P2x4m3sd7YO5OxaGEyX58XKbKbFJlhqCry/2RvTTwzyyGdIACpQ/bCc
QG/5zDASh6RNkbdCOnqKja0rbc20o/Q64LkiiOx3aMNQ0sYYdlHOpeZ1eWgYwdYeM9yytR//7fs0
FdYY1ac5HdbwoNO888UCD7YXIwUnjykklpCsCaeR239FvX/nmGEgOBRiXx9ObmbBTIvBqcNNudOf
Tn98ByQoaurno0nfciwIgNN9TIF4jTw5oPQ+o1K69lVvSS8xSyS9kOt+g5lA/zh25KdW6Wlde8E7
PyjGsS7oQyTzwkXzHlc/vqfU5AZ+mjGzYMWGc9JjZEZZPMuxs/WTrwAv+v295ebFx6afmJlo0N4s
AxvFPUbpjXuO7XZaa1aOhBVZfHb2DeX7A0m91xKTRj2jSt59GWwXPp42mvB9495oDPr2wldgh6Qh
WuB8vM4l5fY+1grKnLgTHSpqciGSWx9fvpKOj5PPVIh+VQSiOd3NKcTzNiqyDGyyiYwLcNHaI60a
T6+ZFxcsRKoVj5+7Wc5RkeePRL+BuE+YoEgozZJNAp8uetjmrW8rEX8rmBFM+lIzaV7OeNaAWH7s
E0vMZYSqSeBHyo2CxRzO/s7Y7xUwyNYH6b/6K3gF/b45oVDxrXjlBYfTO+CJuk+anF7S0uBhYWe4
ElWTaihbpgH3Upkcbz3bpuqaeUm2hmnvmGfiA06GjmrOAv54HnXpgFUJe49LCh7r2ioTtxSTgb4T
4MBVe2NZxeNUCA7o5478EbnxEI6Vt5+zZRiG373GvdQZ+45LAnyEi2vgOOS3MshG88C9oKhcB5ey
nKwdjp4FGPGhoX+DSWlahBKRAgvjVR68DQQbtJymIpzHjJNt/twygci1aXZfk/4xXTR+wQe1xyeS
LCoChhzC9jNMMw1M0OTaHuPsoY6fytR+IUf7SA6Rpb+Nscjap10okwKL5UEvJKrJinz31PQuZUvf
03P1DbEOHtOy0of8DllZt1shZE6WnnuivnP7T2cNiZZZUGmoElR7ohCKugH6Pj+KjZapfGYDNNhc
zwrq7JF4LHUqCBRB8BftZ242WAQ4afOkQFs8vyCCgueVBp39jM7658Qi0KB8WwoijCTIFlI0QsY0
t48It/V8w+/Olh2H95GgHOH9fa3U9F7UuyRy4KdUWlXiioudCB1AHVmSA589eAGBNMB7T2l1qeu0
T2dfEl/JDk3UMaZxVUt9Ksrgp7rqKooMqat2LCexHwVLRQXSmzh0eZZrFFeRJvGdCuf0y8HW5tSl
Q280HUAxgm/OlenGzAT+KHCx+Q3SrN2r9zdEjcPcxpuwRZlHFWJfgXGfc2htPyAgilKam1CprAAr
omBOmaNKDXfXg4d7F4/7X0p43/+1+lU7aPHLqi1kyb5sSOq7UPZao3vvKAaRQadGwp60CiR/LBQo
RHt6ZwSqGwEjjLSiKPEjbr/M1Bgrp7C77I/Y1fdcz8oYQwAw5jWflrAM7LmdQs+pBnzHGz4waZfK
p8W6mQ5AL6ucB95xNHotVDyryqyLKswRKHC9BSsizlUE4kuKZQiCb7CUDCH5QKzrDk6kEiDHVLlU
mkspS1awTkwDFexEjJfk8nQwZLfiSH3q/t3Syk4mvKDY3I7OgO6UgXGSNbfQm9r+93iinyCSnQP3
Tyh9Deevi9JRh1hp5LOmjEjJglzE2DFog0WTGuqQTOY2MzdjlrStzjdkmAqcls5jHu2UAhqZsHBQ
kfGsXiVOdfrIQIUG4OtHTTgi5V4AFgyXzqwvJ6XkI2kR36DRNy7R7lFuxegqQ5YrABASyIT63nSU
qlxBIPfyH3LSLhnxUYoAtx3sccfyhsTyA5FRHNHLfGpTgh7zEdfq6uTk2C51gC/VgGS2BCHGappu
CYGMaTa4fu+dCiKZ9tLpc55chcS/AD5Bdmzik4xWOJ+5/NqQ1Uuuo1FDQTER17aFKm/9So3M5iX+
DaxRetbIA6xVaYiiaKL4IhiOCh8bV+GtbvbPj2pXcoDDJddCQhF0xXGmhCsTExk/Wljmxq9IuVXz
I0iye8FlB/CBRwVrIqh/n5aWV3oqUbJyENPfF91s6Mvz2MKbiLt0A0a3V78lzuDh912TN/r1sqr/
wqdcAFVnJoC3PflWWC1nLIP08oTfN74WL4OiCakOI7aPDuF/9IWwHoBPPYXcC1pyqd6zqExWbqz9
XVIdjqBxhIpiaOIXdfpZLohSP9qSe7uGe0Q1EqwOk26zGN+SoGhbioMYYV7nA2din65XVZ+aRyfn
nX3SY2jmRzFPsRMRsry1sVenEidsM9o3icNN/nIyEkLCJvFWDDqG6/TXwnCyKfEbBe7NvAKQRhtl
/AWjzPCWhjZszyXrHyzvC58ECpYDsyMMYUjUEyI80l9Lqawfm8f/gwVB+siWp8af5j18Xomdylik
vnbl20E1seCHRDZXNQC1c3cHNVgZkiQr4gt936OtLJI2QaoaUyYSQ2BSCS94K6zOb8dRszISRr+Y
yRrC85Oqav7W9K3ivh/9mwevJo2RWWh1fvjNPRUOSHWPQibHUWdCOBgZQniVOihBSG8MDJh0eY19
xDUm7uHX0z+4xca/I/dG8F46radpkRdewToNa+UOrmrIeuwAfxSO6OJni1novo8y6s3d+zX1RaTi
UqlAugKwnaXT5+3SyjM+XKx6SYUW92RX7bd0cE9199mSFGCx0o1ks/42YtsuEfCGSgrHzZpXI8ih
JheOpasibQa7Ovc2n2olBF4jV6TBR5/ZrTNkQ6J9YjXIsxHJuckaQVMBWvbEnSvo9+gEvZ3wENkE
kxnVJAAdVccrebtkMNACIfcE50+8zKeYTP2dcY/kDS0yqIkD7SMMCIiX4w8cBkAld0oZO3lZaCOS
YY6F692LJLeKUbituKStQCvZqgI5vvc4lSBvopNkIyRR9yjPKrK2FBwFqMpbqmT+++99Og1YTHpw
GRjLZM3BQmtmdx1Nl2havzjc9ixvPLV3EClX3xzlNu6sEWhmRYWk4k+A1/4yzYTp59DF11rTjwoR
Nc2/VXgho/LFNej6pmzjkaEOvYdL+L4l5ljS9M52K90+PUUvrs5ReZ2SV3VD/hOzNrI5s4gIsYp8
cqdFKZiVBQm0FI0Kr0Ur0Mjt/ada5pwZkU8A0O8AxSG+84ho+WY8pDPOZvGYM9NdwHB8NtkpPcu/
lyG6ScCh6RkH+vcxJiVDMsA3qlZ6b2u/k2hY9OirV5CEbj7NP3LP78LroWS+RpOsbShdBrectE/z
6FoKKGN5AYmMiozBaaGETL/rb/LawmyP7Ar+UulTMaaO5RLtLcZp/2iRvCzYUpddXD2AnbYD7qPp
PzHbfVbeeYiBeGGJBEbM9MsT+MSIhCIxQaeOPUXGJy5qw0D5mkqPh4YGNmMfGMI7vddxshIN953m
o53hkqOlHN4SvS+id0t9cV9ABU2bf/aFj+YAS2uvTKuZ7GP0Ll09RNIe0l6nv0vd+zpFId0tSA4f
U+1EbtpTfhqMe2FNfojLywMdhZCjE7ie5PGBi5qFslAA7bZVTDHaUJuAc3vQ3AU8V00aY/Y5OEsL
8G6LHVgQDdMK+rZoat4TlM5nS9kreDGuUqZ2t5Xukk4VnPsg9cMeTxQ84NFxkQ1cqbivHeYQTF1k
hhBX5W0J35D6T2ncmhz+nsJXZaT6y6e0PEjMV2f2JAXP0ihCy5+oECHqlgMNEujeBItmy+yMxciS
Al4IhHgZKupHN1syvh5D/vxi7naomBcRYvYXoJRaVoElqmFGG1l4Jd53ma5VS3gTB8Qjuv1ANZ5t
LISjTAW4DomNTMLWNX5FGJkYXIAOcaD5vX4qGhA5bP+jbkVrjlKGFWks2fsSWnlMp5UZ3RfWSjwy
kDEpUyU/E+u5QwZLMXgQBrNGFL4e1385gKsl+TcOsOlMhVyLBxTB+yb4Hme8dBcRHR9meK3jTkmJ
c9OnZsr5O8mfO94JoHZ/eyJ1dFup2twqnf3sp8d/YTFw0GlS9uzsRNDQgVMcjhIlame0a4Tbb5F7
CYOOczqAAIXaltvtOW97a2JX2PIpGSMLyXn0g8PFP8WvHDWWD+NtE58WtYZu7tNjaZXq1XMwz2aS
OAY6SKFg6gH2FWroyog58uxHym/g8r9jF4SxR6IuRtXRiC3QTIUIBeUqGG4y1XVAsWuhXLs+ICyU
CUpOk5K5KIpwLjJALxHcQdIQzLZJSiHepbP4abB1rWSYzW/KhQK/5q1vv1vk4c9Vc9G8WU56X3Og
ZrKlwL10BaUwiaFSqlurvgBwJQKr2/P70njdE5S3zylSm1MHuHK2RPx4RW9HSMGapZ5L79Mz3qg8
HYqYcyEQjwXdGzl2cC0pEGdwRy6IcI3IGWM/lKS5k/Xg3djQhZH/P8HsDyGCMGo3qYelB0o1bbuc
7JlXBOSIAlPqkT2sMNGEJq+SvV6FtgJTC7irxoTJxOlHphXiaHBBLLMjvkRxGmNviFdpvyKT1pzE
XaSnAnynV2Wzan4IpEMZfMZB2EkpbUdUVa/finsmvPUwggDAPXCXuY+I8UwlMhRvH1cw+zpThF+n
OyNmUiRj1XlX/199S1n9oGowt5awTO8ncPzD+df+uKdyozwSzn7u+GA1zpeo205iSS45jEgSI4oF
BkEWXRaGlhSGzKjYsI2BUZSU0EYUp4CZ+PivTCQoh6uOQARCjQRxSjrFVG0oqD94wIKXYkw1UBtw
hwamlS9byQrDmu2ZjZ8659nzg2OFrssbpJ4+C175eJ47k6YgMjjrOCrYewL975tpgfUXIde4ZpK+
CGfnhedG047xSN+UW9Wwkdbyuobs/NdVgEoNtsedQlQmugD5oy3js566/W6AisplDKCowbAkZQCG
6YHPPecEGu4TMGv8j+L58yq17rznJ2QRoaQxyG7+m5WJ/GzLQzwueJPhE8lDXEZlwpVDRUVpYTU0
dZog5RpwLLLMg6OzmHLAg5prE0S2fuen9xEKgSbUlBBeRUY5s6g1Qf57eWb3GjKgydCuxjq30lA9
Wuk7s7XvVb1zvkZDs/oHBXF6wOnL3UGFLOKcIBZMpZQ2iM26cq1p/wuKXYT6lgTEwS9v/uJNI879
0XAbuozNwJ0Ojo8ju1z1Bb2Maumq8xJn8ohLCrSTSEXpvFhwKpaDkM1XcbWqGHm6FY3EaazT7dL+
Y++Neytwwz5kPIc1zWD1amEhT/pTjACCQrP7z/kgq+o95GdV1PX9pZMdeDq0VHAnMRSB9+Z+t0ak
Te1fYsbnidtbxsJ0o80sfCDDglMXGEsapfE9CqEe7V/LtwDnpcjqoXyI5e4FW2DvxAd5nI0laxR1
U3qonOAz+g7zInx0I2zzC429g6r2/GjRXyas/TlChYsg14anP+lzMn8bFJPjSUcOsnm8T1OWTe8c
B1u04FUCyYLiEFDa8TprSUdZNH8z/Fz/VbyPEyfrtErpU7Z1VNqSbrAyx7A5LTbbe7QESnp7Plwm
xeC5HUhCn9Bmasd5P2Ew3OhSHCUh92ZCVqT6XEwkKb06k8GpVvhsPNiXYAlfs+tRwuxvPiWYr/Cv
5E+K2e9oCCUsmc1zozXIlVPWnSh238cOw3TbTzibm7J1IZrWPvL7QF4diQe29n9utxNOrrTYvSFI
CIpqGrtPEF/rSJGDMMkJY3iRgmb3ZjI/nrh1oDkpRnRiD7UHd3WLT5d246veXuSGA2pCGot+7hpf
WHDiGYQs1pXTQf4FEvOt0/aJt3Sjv6plG4fGFyMvmUTcSkTbnABVuB+wJUfcEEr5lq04UaQZr0NB
2gyrgUiSJh54I1LR3eKz7UFlmZyMmDg4pF8k1Iq4DeNnNBqyc9H7KXXTPxcqkNzn2fgpQ8VuEeHb
4fzFGi2zRQnqbCtT0ZfADYu7KRnD/SI0osCv+K7mHUtH5ReXGsP+TBcxpnB01IF9xgzNfx8bHTDy
AuNQNlFGvqeXz670nng7GsZPSqzjQouIRBFwp6VCVtU6gva/4aL8XzvgiiYzdcBrP/EcMe0IFCBq
Utdb9ewJ/cEbA8MR8apyZSqoHeITdCEIP7jVZkYTucgNQb2GVpZ3/g75oGY9Sdy2xfubLOggL1EV
WXAyqH/o9uyeLo7PXcXYomWALCikUBCF8aksBFJV2z8wnnjK0ACEUiZTAJFKN4B0K4AhyZWJ2t9J
sCsRPK1KfVaS7AclfdvSTZf3BjsVcfDfXwDQhVJhaUkmeq0Nx5LbvFVsUidBi2zkSe++pBeD3+cl
H4NAw5oQfhi3UR+opkbUhBxrtJJBV3JPPzmns6eRqbkmGafoBDdCFRTYYBhAx4+87LL+LM20KI4T
XtAFOtYrW2Kv2KY61ly3P1rTcTnFDnrC8y0MRvY0RNsoPhKDRuvcyzpW78dhVDFUFoyIZGPbsBWB
1zBTFHgpkhZHNq/6Wnr7uabD9n5u3a7FbFAxUmU+zYk2O2Uji6BUzWjlL5Y2r4jWqHuOe3wcdaet
3K40RMKHbsqypOIzJA4Wf0pCMcvVcl/fReroV0I5KYZhsVobWJMNFT82rRC/oL4iv9ootZADBm2w
tmg8FuI91iGj+FKXTXV9jM5UmggkvWNVREUEXbf29owWS2CWkzpu5ikhInU4k92p5ba+FUwX60X+
GJIRX/f1D5yWRNS14W11PIkMAn7IGK4gUjJ6hZP+CWclObjXo5rEOcIs7as5GPy3zT2+H18+AkKm
K/xPTuH/C/WLNvI8fKty76Em3zNNOx6gaac/odTABFA1CLz2ltrb5CHoJVgjZ8khNLdKrS9hxiCr
ehJ5jPP0y5ymbZLWrXrwc3rS+9hJKkiYSJe/hWm/IJ3Mdc8osccE+GaST7WrLeDTbQA7piu1ne+R
rrZt59S/b2L5ozOb+N/jjFjCK6xLJ+JU9Yo2zwxFBCmHiNkbPln5fl+SvqlSznaHiCxlbQMxEY4U
DJsO2lG1/fur+wNP9wRdtpDPqR7+XVA6Ol/reDEn0Jp6ZvhxiMtzI7+Uf6rwVp5h35i9GMkXiWhc
6j/QAz0F7UeL8CuXc4EidLc5BQvVQrs66Du9HPAlb/kq8LHwtacLbZGfOvEEtxIUyeL5eDAUwqch
2Tt4Bpbow2K0dD9akfQzr3La0Of6I6L3+ysCkiP5Jpi7nX0wF1lOIb7H3d1mD7m40gED4fFNgYEZ
xvpm3w9xIAfGolKr0h5cj1BAHTHv8uQTs3cJgvSyEL1sYM5vsUV8B/3lyB/sbl39ezI3EGaRgLmN
rz60pZYC+DozemikKOHKB9uiV6iiQ1fOZl7KcyMrlWcFRaJxBflVWYfkZn+K9HH8HXHaJ8rNp6WZ
PZrwKxTJ7mEjUc9lgxth/9EM9x2IResoptdX5kmrACu5/cb0LNNbHncT9AOux0jhw4kPBDGLITQA
B2HNUmk+KE7z4/jTmii99GDthQC87CJSMBBO/AtbqWy8IUkn4TFBehZgjSOUCJzGjFLTuXVznlMg
PyFA0Y+0wUyhApYaW/ejNKpeoskTT/LSo99QertLR1F7Kiy7EFF7NqY3kJ57wHN0m5MCyqSOsr6m
fWLPtysqZQy19g6C1T3fnZsxqZpaXPnDNMMkj1H0nP+FvtaReH6VyWTJ88AFnrFUMrWjM6balrau
P0nMRwfDSrVtPAl9ZIfB6qqpZ6hH0KBDKTPPoifSGT4hSf/tt8Vv4jNsGKUOiUEtjoJ39SiXJs0n
UstBJ5kkNflQ/WDOCjJ3bc5TdwpF4CCUvOIVx6SGBCGOksG/7TBKWmlSMDvPM/+S5g+cGwgm5nYV
SuDQ8FjZBOjzlqIGgbTXZdx233lJYTlVqlqEjCNuL1bYpUk0dd/DoXRQ88Tz6uARXK9QqiGwreyl
cWACKRw0EG4zz/9u1nK6sDzxxCwqXsHJ0GdkaGdTlG4VzNynnQXjoDShNsUAwED+poyytLFtdomw
DpdEH+a0/T7nj1eYWHH5EXlFO+aJkj9IaKrKEjcIDPV91Pl+xcblvLD/RxPwu+9PnPhp8l1B3KOq
qdC635kuOL7Ig3Cx+op37uzhlSSQUn1io3GJIfstvT0EOPvNusmL052s9Qi06xuHvfsWTwTOj+Fl
Gi6KA2GdGk7mWQcRwuLZaTc56pYEbd7Qv5a7Iu+vw9D5n+6BCpJ8DcQwsbcJOPMJy5QF6ed5QJO4
spP0AJqkSCHbEpx7H9hERhDrIX1tTVFo/xIqWKvfOhup379HtiF0IhWVuOzv1174e0lqgar1kybz
LunmO5u6G8icd7E5/82mPFFgAn9BAYyYckygZSQZqJ/HT3Trz7HAg7SH0YRoJoJ5sanzdUGcldld
KykTxQxXsobqJUv8u6Tka+UMCNvZ4cO7ROPloAOFF+cZxKlHrMn4rxPABPGzAwsu02+rTCBwoKfh
vxMNbJndxGU3cU9XHs1t5L1pAjS/tZcqUSq5n5O8Kz0Mm5+pDnhH0UKXu1WNo1sXfZD6fbN1SRu4
mFFVOFUfxMPOsuFX+SHUdElio/w6vyrfFVnJTMqA59vxApd5QG4Mq/j/T9SJLT4X5zlnXLl+NZTY
woEIqSGBfMQ6I4DbApmUI3VXCuNkYaV4bbIOwmoIwt5eT0bDWvPZxZlyzwby9YsCaoyCuh85MIHd
iS+KSuJ00jwxy/YyHvUidduoHt63ozczdev/7kas8gdyUBVKrvR8mVbpBHeCMF+Tp8CzUqnKEssM
sXiRYA9CcMJ+qzqlXuDzoXulnVGs4igDQ0irrlepTAS6VLdbYQXpD607OfAneXvIdOzkV+xdn6TQ
GldwVnhyLTuP0J/4Gd3fyafuQHcC0RrTXNLR3Gq903ax3gfrCfxhs7rIB8nh+MgCj8fOzMfXbFDD
dJkxkdbe4ZOpe62/5bMyUYX3Dv3Vyq9//s61XJt3sYyr6DgR8GFZ+jW3PWJP5MSJLKmz69/0Ysed
wX4eF2n5SXDHE4fqwCGf1GJBexR+5lmCS6Z8ec0Z1ortYT85OvFonwRAVXrzGAy6HLzKUb2UacjS
jnELdJJM3CHXCdQsSYv2fks7qiAtXgnUcBxPg8fQNtQT2Zgs1LiUNGeIG5x6keUda08u8XOonxz3
FvJTfp1LBSfUrJmXdmdFOxDbgJMZYXX3WRry71W5OpeNbP4t95gqn1jemC9RCHXr6O5N6zULkAQE
UeF5OMVRttBpLd3/MNVx/HWp/oIMgLqTxRzPl8yW9R400Vpr1kJMD1RWxv92IHJnPMhN5RvIhyDf
NYNRKeRc3DqGxat3C7uoSeIbJ+j7tMNQJTEtTTavBKOq1kqko2BzYAiefkGofAotc5sRTY7yyHTW
uf2XnHSgDvvlwSFnofOmMOW/y5dAp1PJhtCbucMpHdw5cUgqMr6tYlrTJzK6kb4P40TvEsO5857M
Gfdf0Jxr9WG6d7r9z9DYmWKnqyW+8dIIch5iQsjg3qSV3ADzM/6VZEuzA5VBG/CoEyFWA+qXp95G
L3RJ9/OVp6RAqcavVpAkAlSuSHA5t8T1gTkiqGzu9p/g9TFkdWnnY5RlTR4B4mdkQpDJ+b+AdP7H
BGfugZzAiziMzjE/D+zGaWcoo0oM3j+/XmNCWO/SuWWrxhowfwveHvzxCUHrEuMtPih9ZaFwjsML
wz+xoHreTfFboh7QNrdymOHk4vTfVIRkmToBYLvWXcC79pXSsR7DDQl6ep5SkiQJed1FZKCOUsi4
dRos4/V2OUpwkQhzxnzLil/aep+ooTE2yK6Z2Yeo4AOOyoTWaM53UUGfWqZCXhs1se6sWdPBi2PP
aFTJEg0IJ3/4Zsxl4nZ+dcQ9dFnjdKGK68aHiVgwqsQZ1Y9JsFM9fcdAG1UizxtNoSGsfsU+sK3F
snklPhuhhiU9d5n2Hvtk/S+hT5XiWVtVFxYn2of514FqHl8PR4s8Sp+tKZ5GTY0nQHsd8NrdXpsy
xh23v4omKnkhuxKug/Zdma/xBUnyLN0lOeaGrEHn+WEWkvpRGM7V7pJ8U5zquMPDfn4Nn2yOQC16
NQ7pWvP0opyctfLdy52eeKfLsxz3qV+mtjVcVKYlW6xGX3yVfOfyBhdnD/uBKm5CK1S4gx1/xlp9
uqyQlXSw3YyiwOD1g1k7QtV2vxgALnn8OtvgSju6z4lfW3Fh5jAOWO3hyoCfQ8BpGZNXnXThWdNk
xMLXNQrUD7nGBetFRQH/BWfFjko7L6WyXATRKtdmjj3KE9LCyJhe/URFAfl1H5hAJENtbNVlhwaU
jDHucJ9dRjrkPDnK3v/G/qLtOgarMUArMBA68kMkSc2reBJQOu9vGno4PhsQ1/9Q+M/bsuoaOhsy
4eUlD0d4JYt4W+9ZjP8IcmhIqlkg06v8EwEagDE+gUq2nwu63loaYdebjWHoqa51Re0C2sz/p+6B
dYYulTFhjbtUIa08MpylqRd7TVS5t5X0EpnNc59hoDeSVPiaYF5w1kuYf77y2V5XK1sraXAjOyF/
2i44MyDdT53KZTNdE2SKQeZD4UGsTzsZnngrIvWN6sEa9JzGsp39J4vN+k8+/KTj3Gb5i+qmtSfB
pf4jNyslbOpYW2SnsV4zRcyISVIKpdCp0SOZiYO/E1z52ahjHWXZQypv+KQ6rsSdYCrYUiYj56cb
JuyhnF/6yxt56JXcOPenkFKVZyt+lhOGBiXWT3QbLZ9/4iREhuLGS0Rt1o2Nl3gS4YUF0p31y+PZ
3H2B8YRXdwCOTYlOrNTWJuHu/rWJvlR7hrxEmdR22t9rpiVl3IDwn/zi5fVOyjuIDCwt3//J+uc1
rSrSeCdKcX7CqHr0ckbT5AK1hA9F56KSyMqruL27/Ot0AfI6Gre4Cv5toeCGEmbjesW0ASQXnLsB
OIb+co/SHm2FRZiPJ6bqAzJKnimmmpqDlEnto9RPW9Y+BZkykJ8gGVghsKaLa9MztLDf0OscBY74
Ww9y+ju/OLQQSlO+GF4hAw+WZyvjyCqHVLnG5TfcmZFMb5XW4RprFYuJDXhd3NAhUp05OLHYnIjc
zLU7frTFqMis1v5UEXoOHe+WMiHVObuo6Jy2NbqWmVySCog0toYAdJTEJy4itBe6tEydtN2ax5ZU
YZpFgDU0AGoC8lirWW1GeVL19+i2uZpA+m7JCweU6xRiUhlL7HFKEwvYiMUncUzfYWftwDRDIZAU
0hnWnx6gX8IEMFbGT+0AZB9FGEU4nDIhQAxMVnMZaYzbq71/A9ydk9gaPQq+GNT4/67KbJ5z1H5k
X/T7k4siuHGamojRwE2tXczIgjq5UJBfqlhZsRblJv1GfmQFehFHi+byFJ7cLzQht0mOOHJWkZyy
T0nznaSJNEEQ3jocGX43PXDQxt+OiaahpH8WOMCgcbbuiD8tWsyM62cnrlaEkdOmH4eUDh0BSMRg
v2C3ISfNz8wi4Bx0sFYQxxxskuu8z9B9Ej/u/YriulGzn3sSDUsgDIt5y+HUBh7jvqEG7uMX2395
elRxWnpgqpA0vo0heIdjFYIkCSmeG0Y/yK4Ocm23Z851eHQNH3tTOpJOoY2AoqFrdf4N9P/Zct8b
cnC0WNOr9b80BMto9wIlYv6x1FudytpxKSdA6DCDRFYjulBGrqARofOcajVF1H4KqY68guACSXVY
RsVS+jnW/nFxzKllTVYOfzKAg3FWNPJtnOzZSstMHLIXQjH7BJ9fEuarkbB3kpV/R+kcJlAkz/Sn
CtGpN9NSpbMbEDZxga1PjaIsX/wfQARk7IqZ+5APL+pFqTVPbuJSLblP0CHwZoMIBDghburn1H5J
ycmxE89BKtUPLC8Xu02dYUeAkeq27S/xnUsWFDVy/L6MYgH34+Kpfdh0CxFeC6dqXibOXo3yiekO
OttdSXgTIVliolNMt3ASJYiviwHaUsmWY6o92DNYDTMogsxPnq6ggm/9KkUHWJ4jUyplj7SE6CeJ
IDCKMg6AN395vtD6KqAR4OEiRUF9fLoY3nMHSDyW0Gwn++5KAianoLCi347TIiq/nMKH1Q6IRjpf
JkEUz16vS2hoeusgjHjcI/kkjlOnvrvkFmDPkZpAXV+rveqkrBZSaF6tcm6yQJkTy6Wn0hC+VOUF
SPqtjaZeed2Pc5Bjb9CEMiRtFmVdZ2N3JO4O9nrBbFcpxgnONODATd53pMcfoPnmqds2xSJzuqqC
bgQ8oQrIgfdvl4qFfkQRGjoa4nvP2xjUboQZgtcIHqhaA2+SrqdGenjOhi8DfGnAz7t89/uDCgyn
CY4I/EHxbvmVDS44urtfAI0qxQ7egVIaKehfjSvxbKNrZ+U8enT8kRPCOWERtZMMv/jxROY+KDUo
v73X/4Tdc8lOBX+0tvZOD4KeTDhvYMhF+v7cmYcucPx2wWZnuwyHwj/o/sR69C99fPFS+nHyyXPH
f7/lgCgYVreHqX3oLXbhohhj1+tdHSNfGEDfWtryoV+U+rlIDbTB/lL8/gEmMLg8ydUWspPxJfjE
O0m51oyhX/qcMqHeYI0sPnOWc+vLKQ2jrP5HsCrhh5ysq0GSOUJy3S/UiT52YGkISPki7kZ57Om6
uighhSP0kkN19VaWj1I7T9Y6mr7aNZZMdFH9dpmz8pmpBLfAN+VVWWd0hIHIv77cv5TbO2HNmV1h
1f2h3Tj1f5JChWsH+TujtKZFBORvuPKbkZF6jz7WL/yC+LgJI5J7ah5ybDq0DKooJQrq6Xw54sO6
9DY45/1g5Xdf39YTPv2HqtRoNKgMUd2/HgQpYnRHJj2a6y3dBniNJ5indADRYWe917NppV673MEh
Ug+pWBISqMerBw7T+XCGquZ+YFJ4N+2R66jrul6XgYdXWCgteCVW7K0PX84AafZCdEkplYA9db25
iW55jdzBz5SmS4DJbDzoknao7KfdREmGeVRkeHjg3AP8nZgT4VCfeuGa0BKmRhW6LkFGkKWhmheF
DtS+tVtAIzf5bIDDhYbE3PoetpVJAu+7MzxAr2Ni3jBVnynYLJC5JHnpxhDeO0LzcJ772Grl4Rh+
7To71ACav2PpTCaenhz22FE1hsE0mp8+YVouWsVy/vczqB6IE1tz4B7NHq6KnbpAiZgdrsuCG3qu
HBi7SXS50FSgJJ6z5jrGThvCS5zBWbzBIxevM2vxDgB/B6tw5irg6g/LwWOcUaEc/bpP/616UFvp
2x0B9yU/gDkUZsnKvYJQ2CmXI1AX1ti9fKseEvOsM3QQBWZAmZmo8OlD8M6kZNAxNWcAEfbWi9hY
JD9xzJgTNdaaxx58a8yXzpV7HwH7QHxP1Lz3QhqE/CFREI/7K8MI7Ne/ju2j/W18hWr1UqVXvcsA
67rh38FECPbymvJ14LfeT7QugDpUx6/1oavOeT854VMSTLLmwy9mjgPYPT+aoZw6FfUC3zedVFnc
AZbNJu/zrRLnflA2/ISZLM1Zek7ySJ3VnVawuPir/5d3YWMezInJ0Hqjmx9eOBDgGmOn/Js5fa5s
/edEwYJxuU794Xv005nAKzSSWMsh450wbWsQc0dd+JKdCVFwY6K+ux9zGD/T92GkrzSUpsJw4iWh
J39L0I5TSw/+qcMWbmd6FlvDbT3vbIkM8fd5Oc3h2MawWaR0RqvX3cqGurpGgJ6QDZJ60Y9CQH8v
lGVT2cd3K0u8qAqsOPYU7B3GKHNmUikh0sfTDFta9DWyEWZGNfFLCO2dBHRxhS4TlhO6Hi0Y5R5e
XsPsIoadTqARKjIe/Box4Rb52RA1d0cIRsFUQns2+GJw1mFq+din/LlMFIamKQuDrExGypPbZh1o
PE8129seTGHzvBWR4AbWeqjzTMXF1UJvGoiwgXS4W1oMcPaANuAeeLlIvSVO/DFdZJw6MQmx4zd3
oXBEjVXhpgQ3EJV3mcEclyxYy/5+Z7ZjrwitT3a8aUMyqAfpAemrEzlacNJvWqcnCqeO3xjlMLFI
pzpsozJieOCJRLSqNDGoRmzoARnQI6aFawY3nSeKZ+MYUtfM8H8aAT6HrhZiZv6OgcXa1eOwRZCQ
OAjIL4mVbOBV73Gk+5VqKIOQ6Y2pX1BrvjOXnYgd/It6Yy1Wk/MetSjXFUatF51h8mX1RzNs5NIb
pnJmkE3wui8oSdbJWSlic82iT9ZU17vOP0rrjGcZMTE/2c7FkfA2IDMAwlYmoKvcI3b4lPwO5Vzq
oA2fxqztir6CjXxbosU5xo1FOJl9+VtLTjwfpkekE34oOMC7A8q7HniJo0vrCdg79+daQmCAobUU
gXlPHpqJVPQD0VG2lwfDR4M3vWUbMMm7nCR6Kx+JGBeMOFY2hK4qkEH7TQ6FC8qIHcHIHxvEtaPf
nWcNusLKbqbEsU60xP9WQ5NehU/+idVRw0kaN5MMU3DWyQ/ARoygYX8ziJieZQuq3yhmeCGHm9jk
3PcAed173hbwPp+HVlBpB5WRELrS4aHn4GhAVvcvh6+xcefczN/a/OSfCwl7oeUuHs7IE4gex2An
5QFquOoS4MOKCQ6U07018GR2YpyTQFjheQzNVFSKfeFW1EqTy6i+esXyuG0nr8V3sq/A9m/J0ts3
6DLDmX1t1sBJstnVEd9zhbQB6Ie0VbCa6qaG6jZhso2f/7mohEdVC3B4sR1JGZpIIb2tqYVXTruU
OKfhPguIZqSAT//oYSLAvr1L9NV18JuB4sf4xUlktreIfxU5vGpe8qtBuasKwuw8hcYU71MLbZeT
0lXuEfsxIe0/yzZYpqG6uIPHauZrbR4XeN8oLqd+I/XfueKyZPKCFmyli0wKlnxOflldOzvZpevY
F7HElMw7FJDKv4sqLBxeyZuhrujzz8oAVRL4Cz/ejS7His1BXbY64EdRNFF6Ww2GH+Sf65agw7pn
1Jnkcic9JtOST95kF0x+BJCcvmaW93hK5AEWbj7XJ+lKNMHpC53wQji1x6o/i0ZnZhUxvF0VmMeG
MM2DyIx+eQWBLr7NIpSUj4Hr+6EOFWhT9uUpkzE7QdeBbOSPJUTv6Beua5SNvwXgxNK0mR8lLCGL
ajVmb8MpM8WxNkxNehAuCkqMLljwLhVv2VU7bNm2a2vi+k3lagDVlvui0quGIliicqdT/Uc8K6A4
g9rHUo0SX+XC33SbrabSTU291Dlnk2EvK3JXcDLh3oIBLUy5MpIDJ+4EamZGQ6s64UWPgcs9gcKV
j/lMOsBsXRoNa5MJ6WtCAtnKAZIPnIGUkEduYULd9W6rlCVfNiAp2gaBoNqQQ0ZbaVoDsuDEPUND
8Tvfs9BtuOdzPSG0fWKTtR8RjLGhcVbvQwGozbj3U7rHNqOCTqEjZUhlQ+y6FUncWOdu9i8viDRd
mz3pUMmkIu3L/uX+lls3Us7HRgEk06TfVWy7smKCBTZSSvbNb55+ObfNT7VNIRxg+u6jPnhS73Kp
BXcCx4+oQtdoZIxiKrAmP2pO5hIgakkpXBCbnZZIN98AOaZ/jtj9CH/mZdHUTcssuY+4nEpu3R+W
d7HQii7Dox5H5NO0oV3T3huu178DeIKJDThlg5V9aTMTTLLLVw7r4QA9xz9JfhAW8izwB+11ZXdt
MrxMx1CS/5c/YGD3/wGDh9kAJwefY4FZfP9qvdPBaUIts8CaatK0K643r0voBE3rfSizRQOZGA8q
d/uoUajXjfP5FpOdI5sgpukDnfI5NYOaoSCG6fU0sOlplPz6dzTkwpiSgdaoRDiNNFbEW3kxLnGK
fGp9z+qhFQGiE/212Swe3jV17gUla8adF07FX9uC/NCQNlbJ9LC0vZg7nN/zcWkSV153e4f2zmH/
toiY4R1iIgrvEpIdR44gTVcrLPS7G0pi44WVapETgDnClvva8sk2srrBgRF9UTgevSDn1Yn68ZJ8
nYxkawkgMjhjfk7kzThwI44Nt9uEWztpyw0GO6SH0qqfSWmI3sKqYpxma4oT3cW5sf7gwuFft+nc
/uQ5ekNhZINpbnEjbnLBWL8ItKsHBELqrXtf/EDug/Z4RUHB7OLzH4HTAttKzK54JDvjwdlY4QNa
PBrlcMu1wtRCdZ4QFuGPPFPaNKvLCtq0aeBXeLpVOzDHvVr/U9udWTgx92tI2ea2MELs2RYIzajc
Oihz8RCv4RrIWc1jMiGEIWCVWy7MhSCjtYSOsnWPuBekaNLOSAEDrmpCOWHEv7JG4X0Y3+ImHOCp
GiyK+ofuS0pIuVJDD45sJ1FgXh/UQ1NKaQw/9eHEVQ59bvrmddZroB0KgdB3CfIG/RrUZuTRnjTr
7el0nJ2F7U8lBmZUQFLTaGO5hbHKVHD5RWci2s98DzyFGOggGhsWrHosn14AOVBoTp0oTp8AQo2u
yO5lNRJBuj0r4UOO2jOAsMoWRlnFrAF1PqWNogd7DQIzx+J62dl2ELAXnqlaCV5DSEWW2iWuAEBU
UfxAn0GKO/9bSyK/+BRMWRDFlxelqYJ35GwpW7QmmHuCUyOD1DNl0z05uHlZR3Vm9WF09fPCwDxw
OMb98UaTEqreJi04gZH0z1rjmOwX1e0mv8ch9WKkt7j4ZXc+XjfR9+JaO/OpYs6eBBor+VpJjQtM
snFLTn7q76GOhcb40gl9YyEMNMGhDW/9KD4nLaDiNqlS3JxV+kLKbnvcIgE+e1w29TMlbH3DfRv7
Dro5VvUfGsK4XFWirmpsIslpX6GuyMGz9vFYyVAAOkxdW5laETUr+DEeOLw68v97NxL0uND2hjyq
vH41Spm1kbBl88D8Ys3N8aK+26+arbrOmwtP7tSYLCJzxrs5hwlcstoWO4OTW8SnKsYOknQYdJgz
NTPlo5A+EZdd5sqdbNyC9WojKRLnmNZhbH3ggEU8gnC6YC1xP0gYOAxec/Bsd6xdFZL4SpBBiwW/
Di4Fziw4F+bvCGRk7jocl8eGIt7+lswmSm8I7cJXy/V35ufoUOqLmB0jXLXaut8wNeKm/W411mUA
6ttO71R+uonRTSh//4JKzQQeL758doh4vQ3jAlD5D9o8IYhLFYQWyHH62mpE6yPOsfnt5Sa6/9rO
f4YxAcOQqNBe8YfAqNy687PRHTAV2HbYnnAABOf0fiyMGRS6fmqDu4+VilttZVRqUQzXZAqGwY8O
qZqh9I8jrBr2mivUHabBDf/I4TBii33/ZFdFH80JiBdMyfWpgt/xFWm/ZfGTpANyMR6tFLoNMs1t
yV1AFI2NwHsBQ97ThQmffkG1vi9E4nF2s/A+FsHL99F3yWtn71E6avRp1zb8Eztu6N6/hV27A/MF
h/yepLsSXVH/VEpJfZ8F8XhiZN1Bvx9PcyhUKDFgac9QsvgLKsI5US0XqjtN07DqrhHgCdfV+8Xp
ikUyRplyXK159aEvi9kK3LL+Vkm/2hLAPTa74gGCU7UMSVnj7ZuW413fUbAZdCus2CQaZtZsjlx9
UNI2py/XyTaI9NpCPv/H7TsBUt4tymZZ97Gylu8u9No+aXxsVrtrI10cgYllHJnbLjg9UeCyD89N
KS2pktC7yLu3CzyAhbiMDPPTA9+y3OU8IHpmhNPzexClp7QpKbMCCRFUNQkj7D0X72BJp/NHPFdu
FWzjS9jqVM0cWOzPOJMtrPkvTw1V0KVC5cvGl8oX7Nq3x861p3dSaCcVETQhlV0J4ZJqoPRPK4AE
kkYpVgycweau8buxtIy9TZKLBvYmYOGWGB9Jwg4e77mFCl/W8gmXM+uwlrL1BRR0lSdjVFxJt6lB
A86EafC26SrqIb6u9ufwK57ZcHoGiT0kyD7+bbeiAfGkz2wjxZq6AuqqYfRtZkLEKitllAQxXgWm
wZla8cUME8oYibOGkm4KuxUqbHiIBVMovlozgmu0GuyQO1l4cdAeN0QTsRbSyuuXcvPhTEnxwLDJ
gTEQ0JoaHNxpmtlOTOXmwXPIDeTWZuyBNcX8y057oiXHYxd6DepRKOnBEltklaFznVaa7Nrq5NIQ
ml6UaTHxvDCBR3bnSYFcMNVCjHnWcrigvBLH1G7vJi6LRnvoV/zDRH+NkuwjPM7I0qHy9thfVW6E
6QZbJ2vo0hZN1Lgjh6CpxYyeyhiS6ZRElxgJtuwpQpfD3dAyned050arQk3PUcN6uOCBN9v12s1L
DVhidqZ4qJXkUCQnilGCxNUwGMGuBEyM27NJCjYVR3NfiL1cEj6RoDl2sV58sTlj5l/nzHqy5/Q2
IIFxYPgcKb3v/7Cj/BXp6hMdQAUDVN3yQSrtGqntg/NKCNLy0zFprOguPZqo6ZHJoQBxXQL37SLN
9l1F9YY6Cfj24QLno8ww1+C3yEnF8Ti8av9vJHQkwTmXjv7+haPIS2RiPap6Et2QNDb5mrIfJaPB
2x1EYQ6dtyd3oOUMIQTpNtxQMrnjH1S2Hc4UR3hlER3blreBPo3z1LgKtTQg/8qnE2g0vtKohqKZ
gZb7t/dXEOq8oDuFZNKvKWP36YcLnc5W5EAPNnrZYb+0VBc/vsxN23VGgTgl+nB7slbCGdHBcl+H
OlAc0uPRQ0uxGzPpVJ1Q8iVhI59Bgzi9+vx70TFN9NwQsJJA7UDRgup6Ro1BPuKu4tYVnlMJC70Y
nYI7femDvBGOIydtcSIAOFYSnEw74Pzwy3nlTNQmF7N8L/w19YisX4JlwXgP9+C7EANiQt99i1eA
BWcS9g38eBTuU8ixebs26TtNpK67lqzK6f5uhXVRRGQrqrZt+6TF/2oMgoAh8AuFlnscS7x0uw4M
0KeHYUyDxpe7ScKCTWlufyh95B8qDo3D8I375hmLLbwgQ6D0H5oyZZxlwA0Cu3ZVlQc17tyRoN20
1BotDhI0XJaCqZR9563XmmnhWuEjr4bOwt/nYaltOU1VBJx4aHN88vetiILrteUjS+AMscT5Da06
WcI52n29PWrG/FMhMW6GoptjjcGbluJ8nL17EmdJOWSdwJjTmTMbhSXO/WEIudrjRnieTMrWzckx
JYJ0BAK9yKWBiKUNAl4G+9Ht8kasBwwFF3wyt1f+h60daV+kyKyzF1ynP9ZtgTvSgyus+OvEthn3
jbeQRwZfT/zZs/eK/0DRwidUORcjy2VlNROqNYHCVa/ZCpsCOu1INtblRiwYS8Dk08QZjLZWA+Js
hlqKDqLUkKoS00/kYx9vlhfXiJvxABAh7FHoHOhIw5b9qFPyTnqVZgOIKXfVTe47DMggKwi6/pFr
BCDMi3kTWX+VGam2O/0KHTjcN/CXTRwo+M0ibB6yMOXyrdVp4aQLBLN6O3i9oJGQucYgTPH5sTzG
w0GTB45n2xuVTn9q5WxJFbV3oyFLHoFe2cC+c57yxCzuQ0mLogOtOXc2w2VYnHVyYkJBwBmcuKj+
GGF5zVW4z8h7EwMV3xJ4aQ+fitu7MEaD1+6v7jygxt2cPdiK/cn+Mt5cozDRnQLhsBnea/OyyxRx
ZaUX5nrJs7RudupDHU0NGkKFgjStFodomlhdovUQdBbIwUzkgQBYLC2EViy+g5a67pVaP9UvWyQm
jML/1vo2utIdH6TENlc4Qwf0OdbowamMmX0HGptGvgtxy7U+GWAIIQklFq2dfatzymHhVROF6Kdy
hIgP6MGSsPc3yAVIah21ipQAiViIcQmb82VvKnGmZu9VclqcPtlBFE0yU8mQcjkZaIXjq1Ep8T17
GdT4VzmMYElf3WTXKdi2NSvltB8YnI38Ef06jwQ9eMI3bVOtK65NCEt+BL3M1/uImlK7qJONWP8X
zh0XLtuzPps8EwHnH7VBi94NuDd9Rbo79DbGJ4wchyJVoCZSqEUhlS3xa6kYBzhNHFdSvwb01A4e
j6VUE0+aPDRenkIe6414A3IZZfd0hc738Y89nrDKGRdl3CPAcVibqk1XJducDR7e4+RKqsqBeLZN
wvvOf1BJu6wwGo/hjVRbKbr6Bq32bkhSjAeUAaHuShKwtLldeuiei1n2OZBi0oP+fhT7aLg3yXAq
yULhAf2m3uirJbt1heHTlVByiCwlsxWmM6S//CRX14k2RiypUvyXMkDe4g4mmjzzLHd7H8b0cS9d
vN1kIKF+5rPs4ptuwPruXBS0J2rO68iZeF70fw0JRGbFTaFDkcYuoCl4NfGuAhTmTCT3OZ5qxcp8
LYbyB4l0xRZ+fDPcyqAUmZ9dL5z6sY6uLt7jrs/oKvP+XAu2rrRry7+M7m0TqjxcbxNBgW5E44Yx
MS1N5W1aOaq0oa9EoQl6JV5Dujy5E5M5NFouvHMb43l7IYQqiRlh9cwMc5R4s2lbJpwyiGqe3zNc
/htC9ewn30AcMAm9df+DCcD2sQIbYfOIx3sri6LYcsJT+wWkxkUMS2C5moxHSOgy2xoot4hOayp0
AkU6gB6yuCm8ih8SwO5cF+sHdqydSzeBhxhqYWZ7Kg+xylgRsagmMGxIXparZmKi29SyjpJ44WsJ
EpldGsemGhA5dCnn8uhlUdeYyBXd/zHKJkoIpQSPezFajaiGLCJPQU1ViUML8j8/PPOqUwKyz24v
6NBO5OIK5GjbE0jJGP9yQmkKqwOirfIe0+Sp7x//5Xr2ciZe0h+XvN4LRbN6h0LJ4xFNLUanN5xT
MbuI+nlzgjQKEiGoy/Rx/n43Ii2tNRHR2YgUsdnp8Uuq8HKAev4DLvWU9udP6+R8ohUQYIL7W1rL
yIV4P0UwQamO2GQRpFY5NNHQAbVliEJ2nptXnrZq1kxwKRe7PbRa4Cuh7l++msXUdWXsCGjTYAD9
UCDbKKtCk61O74qRdCO6F6Ap/iQPfVXVvwGNQSY7Ra0xB1Z3uX05mdyU3WIgIrt/bpolR3d7N+t4
BM/33pvJ/4hYhQIxqE5bNur9azFUnk258TYr8AfGS5seIMAY0t/4DqeBTdMbCUTCzYTC4m9cQEq0
idX/pUxRcEm5RkvVDrYOiQxBM0rhcQ6fc8owsd4zajwDaCoVP38Ung9xovXxmIua4P3iacw+ZEsK
0rT4IdzD3uDPyumOyIILzl9OygGr9SurnaeS5+lerZ3MMg3MAw89cidiQ51YECj4vDCe7FFOXKWp
MbE8j9pPQ5sXyTMb8MRYXCiL64gvbrA/eKiqb52lKocIVgWm/BQAUR5ljDmOw2d7yzcQ3YrvQvDb
UOoYQ9CsRM+vIFB2x26dNfKSSkBgcSvStJJZXS0H1qchadnWrZyb8Xxw8TZ2mafGn7Wq5oWwVCAh
pM9MU0WdSStIVf0+lj/p9Hjcrn5VThPFyWwnxWUEVbPNgVOMOOQxUdCkWG2b2faGKp9yu+JkCfHD
atore7l9fhOF8oJNanBqwOH30/ch4XNzD1ZP4DlH8wi+fTTc3Vm8327n9WP//IjIs+0FWdhQeRdJ
+Cug3KClMgdE4FCaZooeqUCARk1H4g/TldWjFTfXW1xks/EYoJZF8Sll2kUQ+PoAOaQfVQjnoiR+
zaswoKbQWbwmdHw6xJOXtQH9fTQ/wxCT1V2ZVk11MbqKUp/1TBLgOWv6vzlFoUxsVa0jLxSbe7nq
5XLWURWdTjbX3NmfUoLM/hzKFMhJxVxjFufIyotm9mydyvds0iqm0sjtB+vgDA+edDZGfqYGYZ/s
KuaPn9+MjAHfpNB+Pv0q+sN62HsDIx6FnafAJgsxtBtESR27Pv4GwTjCmfXd08PriQ5mhkk4bxYR
Qkeat20tjHr0SqL/FRZLquAV1eCPEU3Ie+DxkzmmixGuoBDR02R6mDK4FLCTlpEA8MyRBTwT72XQ
SZrnc2AMcQ7edQelm7/cg26VBsek1n3yogx+pOlEvuBpbAgu1SDOp/bgA2nW0P1sqo/TWu0OPMXv
PpD2r4MpnFm5JcAMX0tTszA6cUgVwJQY1DuN3Py9FXNMD7Kki9bPqkKVASuFV/GKcigfkkpIHb/3
4SXxiScvedduu2Xuz2QrYT1jv1ThfK36EdZDCxhkyJBV2FOalEJTn20ZI9PQ2U4K0mKDV7U0DYZ0
OmZ2xoB/fDzjlzyrij0oxKYosM5lsV/4iE6RIflcdTFaaaDw0fXvDL+xikhKRJA/C7hyZnCnrvZC
uVBuXr1kFk3oGlO3ELGBtQK3qDkXyOvsWY57VYLpk9waF1Yw9k2vrzYTEr2GPTcLF/92fRuXrgud
VhqgCqu1Sx9xqIV8T2ARehgsFVcKTrW1WSi9nMgTchIXgkasWKK8LSFh4QIPklJvl6kjDDYMtGKr
Uftk28Ep+CI843AUsCX+pDZ+hyU6+PGlNEUEIva1d4/m42FMasfi6DdZHG6ro+rgIyrdNICSUC1A
aIFC/77p/DZneWOyGIB5SxzuSONAiI7v8pXKFc401j925AKx5YyyuUim5QJ0uzaXMIJrl68kgJht
FiOJMR1b1HzwG2p7zc+ftylOMeNny/40jCq1Az97B+pkE+Eucb47ipr2tB0shOTtBhkZGYHfhvET
dzAToW1zQewlNUzz8Mv55kbZxaFr51XKFFPgUB4AdVdZY2QD/5Nynn5YEmspInXfgjRiVdp4So0V
OZnIRNsoqQIp9IbbAaQlfqjzF0v+Op70ifPKaY1ZSb0CKZx+fUxQsVmUGf/wFYNjtaTVaek/ZbYf
hlhKqFgfQi01/JeE4N+Gxg0ED7aeJ/nf+zP5xG+ZcTmFCXlBncEf2YotRNjJ6QaAtUDBiJAf/5Hs
ZsEOizeHltoCn4cEjIAW91dCnV/D9JCPktZ8cg0wo07aUl5ezSQksT2CY+JC2pUZXR17cLO9mpeu
oZLsoHtD5zXh8jCd2WJQS+kIUTKsthprJR+XiVor68KuaaeyFaCr3oUMOBU2fh4K8wMRwMShqP8X
lNcGU6CQcqT/p1HrkcqUN7lJVgYZ2b7w92Er2uUa69a3kLnEm5dWCtRd4c8tykrlyVUQg97sBmtY
rU1I4TmVSn1RYzM+ahSfbWOfM1Qkh9bevQolOx32SQTpSkjJ0lkALomUv3xV9YMOhxWyhWbEgEE+
8FJZYcT38kyXgjgypgrd2yqXmSbb/xC8uhKUskiVpJuOeJEy/FctQ9NPWXcaQahv/51UmhL7CgKD
PpI2reJbjqFJ9eu3Y1l1KnxSI88ujVhGXo7T2KKJtUKCRuIypu6RuvV2vEti1eCQhh2AbRgOjjoB
Q9P1RGtoDydMpfhPZBys3lWfLbj2XyjIIKkIjbPGP5NuO/B5TLETkEJz9pzNaL5YD3EthkH3eY8f
taNXPWGe8dKILA3ELXqJjay2oJgUCh8U6yBeF87OEnsTpA4krpTKyxjziGgfDA5x/nf11ovhWqV+
t4NUurk0u0HYPimNhY1J+AnJjiqXCYMS9lzMcouqpXGEQPcTy776sGhKmmkvh5A9WjgIqivggxSH
bxvJ+hX1NluVvlrdY77P+8pI+UPp2MiOeG5Jjpp+RgjC6xJU9WVB7XseV/D/q9SUuuW9Tp79Mg8x
zRFEX3O4jweTnobI1q/rsN+RLC0AuS5pT1j4tAPrCwbkGjBPC+SWZnPPtX5J3yraz/hq3EoC9KNp
vHmTDfy7j65p9yv5iJEeSvUZj5iUc32qBNf3AH/OLph21+Vmhp9FUexf913nIk5EEq0hy6d/K4E5
VnM9HnMQ7eygDZtWICP3bmiRkr/3ckjjOYDDHj9e9bCGOyRyI/25fSPchYdm68Bo7dZrVpBU0rYf
AjztfjoxK2P34WFcJA6Tvft1htAZ8eMLM40U9TYAmjnsD4LlModD03DGVYQdwQrzhRTeazCapENC
1scY97fzZdpywV9jtl5d9NsfXpD3IaMSfDO4zR/5dV5XZ2jNR+JdjC1aEfbX4hCbFU39cUT1qaGj
o945s4ZdCbpaB0PialEC8R4wYTUyntSWWEHcQOg1v0/p2MjqDt9bclKuHPU+w2jg0XARY9YKz2Ma
J5H2/5w0hxH7ZOFcUn9D3tE3akVNzL9+QGrfI9+tlbJ9qPx2+rwAZkopi1FVbPlQzamYy+RbNyv6
rvx/CAEE1K1bu9eHgHOgU2fpzOO+pTT6seSivmrMmC84JrmnfRi7g2I9etTMvt+U7CPN2bARXUAf
gQI7Tdskp6u/+hsmEL7bIC04QrvJb9pt6otrbYq+yERbxNSt7ngYrNvs1ZncAe30VO7JG5aq4mCv
/247Jv/4FV29ZQUCtxIYUf9IG43DYGjUXCZ/K3y91oqVF3i4anQZ60Pl9j/0HHW6tx5VkMDoI7qZ
aX6BoI0FgACCKUC3IAnOrGeVkDepWyQhIusBG0iMNMeXmihLoJQ4M5zJySyid+k0S1xfpRnJ058I
gZy6pnrXitznhYlbQ9EhzXQVE+9NsmmwvKpUxf9Pr8QzTofRuMkx8wgS6pnsBHc+UPl0AQUzu9FA
j3OnYJQJFS+3s5cN29cYcckcMfPO1l56q3ndJSmnZ/s5ymeLsn5vwPfpj0aNJkov7zdUcFvp9LLq
+oQYE2gXk8Sqh9mj2TTAd8RQuFOoGLI/UyOtzdzZnOMF4hNaU9dSphghG4oJ6aBBKZI80/h4izp4
BsmNlzrgQIUNkyK77SBtz8i/n08cf5ysUk63Ef7wXlyLSNH8fdA+3T6Dr5od6KhZ+BjgPEKZ6eIG
CD4H7lpxG+LVu6kEICL4bboRLLYMTZjRHu8vpXG6u3Ve7RbD+jPslGuS/g+Qc25nLK4ewd+jevKy
bdhKDr6Mcysiex1i7yrTO81rXz6wVtneguJUqu25J5U8PXzBufsdAyRzx9mGBjQL6CP60rKV1O0Y
JuvkPIOoQ/eyDvefxHaJcSJJcLzKu68rPYVEQXFAMp3ZPzmySGj7CKVup07TVlc5/xhrFpEaVDei
TOIW+K+FB1Vb46Su73MPVNHHsCRKpgPf2IYnx5HBCapO+t4ygBDblsICjdgIy62Q+bj2fWPSeHRx
EqSVaVCVA0z6nEvOwiJnFf1w8nPkt2nffEAcRTCYaY+sA0AJxK0hoZ/CMbT9GtEiDiLWQxEmKbMr
TGqaqICC44WqUb76LU8jsN63huTEZNX7ew2G037MUaa9Kiu6RMXe8BRBEWRrkWqfmD/lh9q6pJNP
4m5ech90oPorzxeqbeQEMtc14Jtdxa/wYlWBOpoHt7DrW4p1cgTwh67HYXPCDqqTP/aB536nwBqV
zgdj0O+oBKgHg7jt2lQhFnEP3bmEJu9BozphIeTv2KcqWJrULgEmeKYIbUJkAYqJsTR9799mhZtS
RLpQVxKBxysqq9aHP1QyR1nFrykEakOZvgy2Vjd6nyCLJNQ2tzbpX0JtD+ZoVCDKV6S4v1NcLbvd
aqi0mTDgG0B+DlnAk/B1VVvjdtnJJTJq8rETduWh9D2qnliPnaQOM1TaqCmQsy+JVnRF/tt3E01L
cV93qsvGilz75a2odxUT5BQDQ3vABSCvRQpg22njjXXAveaSGn0d+pkwRI5V61O/WuviUD32t5iP
zWZgwH7C1ZRTlnVLGWjpqPMCh7jGTUtbpRY/EVNFc4tHibdLDIIFLCbb08169wT/BcA4fDGbtP9W
VJK0n5QK7yNFZgL7VQmu9CQzUvgyG4XHmhqydSQimTsBcMypKC1b54rhqBv5627dA6NUAdghKWui
dAkrp+smEhNdQqzf83baH9TLPdniu4M6aLasbAqrUdfVPGOowvAvv3a+fd9xJsddUHKw0UYD4PxJ
Fni06jf2brpzwI/g6ISVnZ1IMCQCJ0rQTmRem/glhO+azWVopRhIT0fIHzR7+1CU5QzAtLE6uVyg
7nLQ/eCS494PiJt+Sh3Yd/yItMFCGX5lRxJfTo7S/uiX1h7frHF6kRdcG19B57TANh6aSCYr+6bx
OGlK5h+iODRWl8t+C63bSoLtAVKAvAuVIEcxEWrpk9CoI3/xJYEdnZeBvClYb4+0nuXVte+Tgckf
6+FkvtmJV1n6FtkbyhFkP+Tp1Ohk1uLaWY6rirGH5zp6oegA6bFt/Fm1Elr6BxJdsn09fsixwTWQ
r/4kLXxFwi1Sl2YToacuYpPerxVR4BRFglGFv8+2mOJJ8ClS9b6w0spyTCYiAE/Czajc1px9omst
9hivW47gJJSHvQ13az8iQsYewmitD7L7mxZCGZsFnAXuRCR8LR3UjKVdQ615cC23xQXZONA8gxKy
zZHFQ7AfexWX3V1QdC8PrMYhUW2EKAhs8C4g4ZsLlLADlrX1kBU76oPj8H5riyj/k0D69vkUtv5E
QcBbYPmIbtGRGfd5Cxu1+i377kyUCAyuRr1T6AUWI9pE49xr7BHlGzrdhYTT74kQEJgmtUFNQnWe
UtKBYoSOtJqohn0tYsPyWHtuZH3vhkCZvxFR/CohEK2xWPxhAyrFxqz7ltpJCllAhYRnXLkA+tJa
uQPNcSv+XSuSmjTDxBcoPHMIpB/aw+AyRnlFzScalJjkAQcvGceVgoRd4H394mw9FGEPKxfqmpyT
gF7H1Ga0jlRG4mFOsvc/0uZ9/n+Z/qllvd7N8nLr6y1Irym1j1AbG9V6kBt/PAIW5ftaYCz9h3bu
KKdpvtYwjK7Ujp4gT3p2O2kQaEz3QUSp+FgzbFZnr4EwHNk8GHI65L5jZ9JrjYXgcoztc6EkjeFw
XOIbpaPoQ+/X2uyxMn7o+bsdw+eIxkmpMiTZDQZvcTuqyNeLiWXZY9M9dRxr3mHVGR/+bYDA0sBc
e2FOC8Ec8oLmQCo/xTXDE7eu5CTNaBVy7H7/3EoVNYXnsPIC8J8XiG5znVa2NJMCnByg6m4qhnqo
B+IWI0pgtnryjOmZr9g4sjcWhG3HXe2dSLX4FNjWk5vivz7grXMr/ICGJZC8nLCECIDJG61POQPP
lGCXzJJ0A+9TBXkuTms7n2iYu9uAv67B+T8rfHofUMau0MtGmRTadcdKUZYIqEXMNHpvu/GpXHml
GlgDkUGmXtGz6Q5eYdQKjUav24alZ/I1ah67B8ONF1TcichKNs1DqTwH7A09DPmqXE60CtQmzlv7
ZybKovx00ZoNIyRCveHF4UriuXMg6uOphjzqw7mG3CbKFDjZ5f1GXdxM4qrCuwQVFvXz8AMbVW+T
/AnWNxp2jDj9zvj1U9Tl3jJfDvpKmagD0OC9Zbh4/V2nxtEOGFg8ShFxco4sEdJ4jurP5iD5qLyV
gEd7+1DI93L18Zv/SJ6nJZhcLZSwJ7CdPulM1XbeEJ//JgETvc5RCdhGO8QXf7zX4JGm4k582l3o
Zmr2pcuxE/e9d3LenJPU/bE/XmsJUwG2tKHMCUvdv2PrgqpCKPkUl8ICClG+oPAcgKKfffjHLmaM
gOUcdUwjpd6nCNwkS3Ld1clWluu8aQm+W29bcQ1yuZwy10+gtobIe1F7AWgXy3OsENbV0+1Rg9cl
oKq3csUEEoUV6afuNv/RctPxdUiLxQTvJVxU4uU16N1XKbyMUZwKxI3FnF78xaI6sDOc4RRA+QMo
srjgfHswtocH4TTB969D1jSrNCzndj4tBXIXBCcM3QQ4QyZ4F5HQa7J4cZjbnbK+9dvnEWZHSSi4
YN6YGvWtxxahEHvdw9ht6IEk27bSFpRaoBelC0s70pvqOUHYbzJCS4WkpxpTp2m+Bqq136k1Qe9I
xDSR987nKw+XFHHMHHw0qyYmUnn5dl6SPE2alczkHBASZoJ3jRK3EK5SUUUt55ZS0yFbYiwi79Ri
AG5iTVAeTZQ/o7KqX1DHzb/IGzMFIJdcfzH5NqcrXAS5D4QLnthnZStZNRoKLGktEi6KC49nWVc9
KNSWhQl/pZTpz9gLdH3R5YQOVfcIkvnTn+p9/5WtyXO4y7P09oVuIFnG71CeXaHts+7UQzyyezyS
Y6t0VGQWT4WXIa5wffKZJKtkvRLMP0OgUemhN4QDDnPEH32GahtikDAWUD+gGM/9QIU/YLHWAbit
12/7eaKwZek0DW3HFxCNgfTb66KcDx8Hx2lXbhI9ACgJRhNPR2c/8oGbdwkWLCPFU2+ZnXNJlfuq
YfHq3uOsV+tiFIn4KGwo47/LLEUBiYVIC3Hx48FT8A5E+A9NkzXTcRbzOs9tGKlhfiavDMpKPxkh
4XCTDMHccPK4n+Ut17laOaKehTmJzQx1vc7G3j2JSqJpOSmy7oZ6mWchUOpIA6j9J/fEEeCLDQxL
4Uhz5FholOIFZw4S1OSuJyVjCX9SPtX3Tb9mIQDTYjuzdJm3/QCw19i+155Xb2BVNDbVg6ZjxQ6y
Rk7Jc3c/MffFM5lmjg6rGFWz9DqpB8+ab7MJQ7Wbc/eHl5F2RKKqgFBqxPzkFFgV+1WB7Pes4W1N
go/d+jsJfkKWETiEVUPKSMxy5lCa3qvxgBaNO6PoiNw/nfWCMyzdQ0o6yidmMVx+Oads0SwrZ5ir
7Gnw9/mxlO3I9T4YsfE2joWgq6UnhdbRpQW1SbcatvaZTGmdFPbM9qZoSFd24mWfDz0mMNTVwZzm
zpoEaNX+37Hm1JQSPJtLEtLoRdK8eIvUUAqjMUzBZMMSrVihdnPxLSuX6U41M7B1j6NrRIAqTs5M
r3JuBERunv0FlAkuess54xGemovvD+UblpJd8pcCJ+ScksG1mYFA5LC5M4Bk60+xF9qejMkDwGQg
pPwK40FkBntwK92B/Yb0nbV/xM0pJamWw4j8UtQl1Un/ANB4bYvZsroDHD/++Syhnu1E7fbiJlv2
bUe8zb++x7fxYiLm42lMVUgAGqE6zsNRvQ5zno625t9qH5I5qH0BbDqSig1C2GNKTt6aehnrE7Kq
a1meVoZ8rH3AwcqzRXv/5ErR3WjUHZX3lSaOtToaWxPbDMGtvGkrgggSWjfKq5G/LqGYUo4MaP8n
m3zFtbkRA8XWpTb0XdMhSZMUTnWZBbaTKgsNphfejj7RMmY2oOzlFa0e++dQS75F0982ejjjVjf9
bc013FtI2MzZ3vp4bya9o7BvcRxFXRInctfcyOoq3A/BzJ3inMlP65tgtaLigIZEw/E3l3H08rFa
FZEzs9J5QPQ41oMr0XSmFV9jc9eVDkyccgI0M7IXo0TKWiZ5vXlYkSJ2jYRUKPs/wvfp+kDk5xbC
sckXVSkUQA032T2QMY/lchwGyLqDsbJbMw9cShDTzckUpC+HPc1GKsG2EzJyfa/GXS4aHrS4TYO0
/8q1qbGd5yQkFJKBOjPYk6wkksGd94B/YZsGMGqzxRAT1Dmjf1JpBtIbDcoQE3iehdFEghRBMsAC
pcv8zoojmiWM7WH6mA9gyMAZ7GVY1ja7Eo9ME244RwXjw9HDWDiqdl1EdBst4LsZnwsNQQeojzYI
gqZIffnE9ulOS/lr40kjDz9EG+LJDWT6d6dVWg5rfLE5lUaHuYaQ2KWOnezaoPbt/semumdGfOJB
1WvhbKC0dMPbHApmnSmm29irSiTcGUlbD4Rlz66WT+9I/XXdhgK3gzbA3M7LPKzCA8qR1nUGvreH
7wRk4Znv99FN9gEBQvvMBjb3WyxZV+SzJrGb91mk1LGPza3gM3p2rkyHm9YuYucGq4fhtMgQblB+
seZD7PI8kRYhTraujKzAdxARWgOUSdzdVvmncoLxP27aztPlSgeOlR6k05bygheCQVJH8CyR9qsZ
YMlRf1OCfNtYIqUpA7Bz1S++NmDdQosZZyGXOwOvAyVA6oejOdTp0ZMMJJHsNky0rMdWldbOzE1V
z1OUfI6jtt9UvAif+RpQcC+GyCvT6NgdVYgUrleDrdWkCb8DznMPutOdtVmU7iG/VEZAtgPmC60c
yfpajOEbTtQKxOqvHsOOZW748zk4RmUng9pqCJXQxQUZwDJ869OC7TbFd4JMf4zzKSTtkZnf7vOm
HGIIBFzHUFm80HLJ87oCbGNag0LTs9Dt6+heFpAlouLqQ+W2eofU6u/dmHdevMLlFabZvNrfO1BU
HbV9lU2do0mwkx5gQ0kW2ujEWw6fGgQXbzpUh5+maQkX+WJLBB5aJPQ8j6LsDYaGLCJj6vfki29M
ZTphhw9ZVNqFXtWbfEjhxhhGSy1Htk3Cg5cFqk1mO3A8EfwZ2OabiN7E3/8EDodnw1go6ewDlRPT
bC6cQGxgamSut7TgXfjkiF+3idEONBwH43NnfAhHVVrd3fSrRLwHyY4/msSzsTKQzE9X/Hhg+mSv
C2ozn82HyEdAiv+BA3KuMGQ5vv73SJB7TFqPlP++guyF+QqigXeneYGHA0xDZie/YaOGudGsa+e1
nEG5YqJFi2ib4ISTGc129IW5KA+V1L1+7X7oe01VfxkVTMFMV70iF0Fq64s2+YWkEZ92VOnulz61
o04RaODaNkDHaPFSP8Bxx97IM/B8Nb5CQPgTMsWiZMlR9NL3CCDY0LdeRxDIvkcY+g8sOw01FvW+
l02sHFVuATk0GlL3M2/EEMSK74kjEmurXKnOpjpEDYDFQLgvj48970rvjMXx2jV1YJF6oe4buHhg
lJztNdYoYXCn351ge5OZz3rT/KD0en8/YWGbr/uCSfUVWPWIVxvC/ElOBUakZ6jWVwN17y+5E56y
b5Skd0Z8I2BTRB8uXZr1gD6NQ8U+tU7Vy7F+b5IJqDNPsdJwy51+dVJl6AFP2C0i3cWA6hiQF3YZ
qM/Bt3yaBiOXW+Om8BDqYuS9UK5bJsA9DIfNPKy452fYsLf+V/vXQ3ugPGTwJs0QbQ0b1KZTyLeK
ht52j9Y8g9KbCfyTNOcZFrFUm1IPxFIVJxPeL/2pr0rCtQdtfzVEbICgBRGg6VJzCjOVZORcnPRO
92HBlY/afk2Tdd38O/b6nC6MxN2M1525RbXklv9VtFPUIhCez/sA4VCSe9Rtqqt582MRSQzGxRL1
K73lrFVf7MLt6n1jLNwmCIEQlMS1+lM6W1BDVqzn7wmB9D8TKvWzIVtRCJxc7wOpbQRCYDEvvBwi
4FHYiaMubcQOiWNRrHpWYT1r8KjBDgiHMbynpA+1ukBGuROdaQgSdE0berToerglGzdGolY4zG5p
/LnZhKL5PYbmU/NI0y0InYSIO3SFEdRpyar6W5yuv3d612roqT/tiqi/HJWyaBdeNvJBrdXhK0Pi
uhYVuSHfZAEPxfrphXUicXeJfjHL9bq5rP5FAjGPiKAaOo321vbQVFdkmOci+H41yKF4WHot8ez2
Oq43lwu7nyR9bau0d76RKJLki+uLJs8leRGrUhKgFjL/XUNbXkWZhzv4q4708kmIXtlECR10xOsr
Sa99LB/iznW3lvAtpV7xbQVtUScxA1JXHgTHW7kyhi9O+vmGKf9R8AuMhVs6Jjka+oZnJD9dT4Bq
JnSuIw0sRASvYfa5JzvZ8or7sNUAoj3lbinZ0XymoNJkEzrxps1bS8Y/951ynsPqK/F1w1jOV9XT
hUgPAUFgFMv0RJ1OJM4tM9UvUDsk4qlLX40TeWnHQiZoRELEBEHg0563KViql4CIyinrDsQPbZ2c
lMJkOsrxKCaEFakW4XFQhSAh7OotF/Ysbii13MZBp8/oPpMDfsdJI+IhRG51J31Ghefh9rrHlgLn
3INjjIPGWSpMiaAy4uYvMutC+c3FTijfl8Q+A8NTf4Dof8PV6cJJvJt0wc1Y/vzSpi8E8mLu1FCr
XbXT0m7Xz1SqdpHWiqUPSg7xVcjDez0qI16HkPhDYtRGYzqmXsgpprbIz42lTEapM4YMwczlPbcK
qgCA3QblXsl1pV0bPWn8yF5M4i/XiaJD4lJIW6YIUVodYVCURtCd428Y7VlbmHPVun1Hl8v81Y9Y
YgFLM8SfMleV+WfyVJtjhJ4jY4B2qfGusreIdijuaSe9g4vuzMDNNW0nSzfWu6ljdi/aUULyjROm
sTRVTWEgoq1OQ6/5SLD4smUdfcofgfxonPiaYKn/0PUBo3GuYbQfUui63J5/vB8IWvsrHcFHdGIw
xaJgvkwNpBwCZ8wbTfoUjm6Ls4DrP+upANcMe+c1OHh66rPloA29orKhTu0BRKjgIdFJH/IIitNk
mVOUTiXdJM6RCBEJU03YnKJSZb/n14aHBUWdVI85tEfP0vs3OHoRaxoHV7EGZnWUnY5Q6AYHUtNT
sSZn+N8BgYKdmZx6SBsZAxDVQnhqbnF/zAW6hy77WXL+8JHtRVUhb+4EpchOy9swxeqdliwRHnyC
JHftxax8ucFiUlDfDLewsKbbphEyoAj0Tgc67wiYN1myBlkSo6/O+piyZpJi24f1d+O3oUl/iCzK
R/AiWDEjpBUpv5+B+YLBNmC3yEfUNpgqZRpPGPtV5JVhiSMEtWcYV7Fr6VyXZBWSqWa+rt6X+ei7
5GUJPyYOqkvl1flbQTSYuyv1yXGfxrPFYDI89DLMB7V+WjzfvsqCGKgLNh7ql9juPVeGhi5UTwq/
iYm/fGLl/e5qdjBuD85yI8ekHJ/4jjxhh9swddnLzZP3FjKRUpEaKZuq59zGZpRi2RIxLBtZ6kc/
AUJD19pdr/Z/r00rUXf0ZxPW0L+g0iHzy7TPaii7qLAmqBqV3M0QiVdjVSEqpJZlQwV8Gxt2F/tD
FcyqZmMtpEYvBWUBl5sMfCoSvlUGbx+fk+OrAkbDxQVOCgP3mbH3P6MFrRCHhNI3vOhiLhLl57kw
DHk2elXUnhy5IN+FhWoTlj9EkI0Twz+xOv9YETUrCKjlNwb+JLRcEqwz1UZsjwM468XOOb4PQs3W
hLlMcWkhwuSSjSwxoJvKzL42yVeYHh2R1Vv69upOkndrICfvsOyd4qMf0j5MlJBrBD7b+UkCwsDC
aCs/DLM1LzsGudln+xXlWQ/IQIdg92HrVjsSBxRqfh8DErN2jQMOK3FtIUqVmwLhACCyFQII62vV
5B7zNgnd6AIytxo5QO9r7urncvwDLINe24GjW02ikgrta9IBxLhpX4q5McRJnQ3c4dLlM6qpfFCM
ekcAZDiJqp5+gD1A1rs2r2NZXiNMXU1AgMklpAnho0qTHs/iV9zITwoMa6l0JfNXoARo2P0CtU6g
rER7rf8HKKhnSIz3w0iuhDz2yZhaf1OuyN/Rmx9v1cXM3U8FkGbiEevvwZk+Yn6ofdaLT8ay7Ut8
Q/0l8vp0sGIf4/Kfc1rRXDphAvN1kFPkkvuy18tJ2Fq06pz5IfhHfZjxpfRpVrdUAlmJnOhcQFxY
Xg1XJupEETpcB+2F9MXAMPuu1vjezjqzsHjusLy/fkAlPASeSwNaLxl613RauEMM+4zOcR4SpraB
0a2ftOBJPEV8g1KHInYdSJF8dDhEQu1zXherR4DKGm9AHs90T91cXKR9HTaArz6/5WPC8OBI2Z80
HlRpm/jANawGDtZEmVcKmt29r1Cey/629ORYrfSnj8DMxzpP0lsdkTlEXsexp9boP9VcBn/xtdSU
RR/Ufoq/VsLYliwcFVkgqq/jkpX7MgZpf0KM2+U1hvdEb5lmh1wDzxeiIN8zpPkW+PQp7pEIrpP7
EqJBIujMyeDUp4RLsqaugDn7t//JSbGvSzFkL7Gpn9jODV0AVSMWkACkFyf/8LmHb/CjIcPsE6ZP
P6vu+dSSfjwU0gtUmh3AmXqsPkMQc+LGpAX7U3zYOJL/RpKiqBJGNPfDT/91KVb5UlwbD7PUYRJp
Hrb0WtIxe/l80ucRcuWOR2za+aB7L6zAh8gk82z4sdKZH57HbZUokDrRr88vxdV4QskYNxBNySo1
HqnzSashjlUTe3Jn91Gh2XSggXegBI/CiWYDrYszvRhgNXMhCKCSzkjA4Pl36SdbZ2uBsy15qjuW
29ouFiOMCfRF8XxlUZVHetQukMLw4q3J6kzz3S+fONHyqjXkZcGDom0iEV2sQbQc2UcAVNgQFNsT
qbNKOP7v9IKWPHHRbfWelvyI66nTObvfwer7OzJpdO3Ve1eqw8PDMgb/UsP6PySdu9tDDqmXjDMF
K8mGl9dXeKMZYhq19kHDLTobnbsCGNhfHRnN1SyTEIOTi0ztD9OZFxnDBDXynL3xYfWx/uwGbP6u
reMXi5CvxjXAybeRGVbCM61m52hxBgJs5QpMDYM4eZgbBUx7C4NuhBxW+lJbfRRj3eE78s6kMLQF
ReE+XE00i+7lVKQV/YG0upqCo0yHrPSXWG6sOTYe/EagS7Sq7iwd/EswNIxn7IfF9CY514QeyHjr
tdJxWN/KywEDawmQjBZ0mxPBVv/dL4DOp8GmLH1gPCcGYagOMDBVz8Cjqii603aiqLq+MJUPlp3L
K4HfAEDeeRZKjTfu9eL0ZmbOL+GjtEIpThMd1g6TdxrkU7gR8vbMOd2DFOfcR1lHY27njN6VHNKQ
Kd8k36sWXmxs0inUNqbkS/RPx9JKVVd9cO2pBl3046Nfze12tdtI/giNYIy/DktAnwKX9a88MuCl
5NGorNSa+Tyl6kcxUu+PfgfiUSc07/5KglUVAJZorriNZcwLkFZhdewlZlZolnJiRGW3cX/kMEzF
W7FEIYnnKk3q8arkEbKvREn/Ng7f0klfj8l511oY8Rt+SaTcxzeIuegAplA0AGP+K4DXWXKkGAzU
Y282znFSHsy9YQur3DUIdIcXsBdi1uXbuCmTA+jUQVG48Ncanx5tUdNOk1IVqDZ6J5ti8SR1r5JO
DivFDUg/uFdxDC5GQ1K6gBLN8DKGC3gChzegBVsoprcagtjqEsSD9JTFvStvPxXz4NBnzI0dwOSh
a/t6+5I6ff1VS3ORgGV1GIJoLGbytA2Rugn2IfvBIF+8f/ybVLNBcZddSB0IR7HZCtPLPSb1k/71
rJYLST8BVbX/+E7XFqsCWetuAnPQ8eizxB8DeKAmMnQxFWJw1LGaZjK8Dv5u4lufoTq0b1Y3gS8i
hrJsMmzAwuqe7KuO8R1kw6Frok9uSwdCVr10NzqbkD1K9VMVfsNnB5b7zBqXtcDULfxFxX+pf92+
Xx6wIfwi65wFxIyiko/oGtycmuQ/XM0V8L78MRCL+8yDb110nbADbpfhbmjAvzv+NwtCU5P5ldsq
KR9F2bQNC74cxfqkXx+r8TWI3RJACUAHftmwAH6Pv3twjLp5k6semC3V0WeD0pAukLXnJK5X/VvR
yYXmP1hPTabG6k9/x2rvDovr7oxnI5Q8nyaPB4/Z2dP14WIDKpnznY9JDaTYfAk5r64lwzeQmIkS
zH8JNG6yzqJfXW4u9z96aLJepsp19TLYTXOEhIhgneqYCXwaOxLyJPg4yrPdcBy/SM8rIVIG3iAu
baZtaBGu72yYOIRB6/UDtuc5h83mweC7MxXm/7BlS+yPlTbitudREDsY3KPtps+WGaWKakQv5ogR
USSe4ti1/TwgHcUf4zUAbGg0v6tmgQmfjGSkkuFdkw1f8F5c8cM9xHmNtxIfnPqo91x0H9joL+Y6
0pk5qYv3l8mPgq+gbb5pq2uAy2CnCo+jxLRp1xTqhrhWNTZHf9hQ1Jv31r92XOru+1expoVEzTbe
Gxzrh6HzUk3aNeBKCtXgaVNqCM1dEv2C89t0QSteUqfEGCB16dZw6cEPttHDXsk7yk+I5ri+NnYk
KQFgMMQGxZ5dHuaWAJm0QJN9t89UDbuXGf+WGOgmitsexD4hYG/hvX6o5VxRBCZ8JAX2xTFAoV6F
zU6aeh6CyttfGf8SxJtBTe4nz04KbCF7DgJd//FTwhzfLTQL4NutzO1RiJI+5M42wHbg1VSfvYSD
ejSYDS2W8XyvQo+dFBGBI94xwvgosb6uS7aAMUWhmdjg3XE1rYt9Np27i8oC4hQLXshYwLPwTSob
mre8mMR1Y2GHnBB16pbIGK5vOdZkbG5Ygx35LsAYyD/SvHLD9HVM2y7jHEjZqsWf40NZGymvy5yq
PLaL//gDYrCwApQV/DjHB7BOGJmJqLuYuVq3eGqz7qrN6tWDoLvyd+NaEy1IL9bJm6Vz61i2xz4V
Oy/8h6hblZ75wAhxJaEL1NwUn6WeD3eYuDfuHMNVIrB4+sHhoCSCLzH7dDMJ/4ALmSzvz/uHY4rn
K8HDZ3ha11j5uPaMZSytX0G4G91z93vqYcX87qzLKKUejHeuDa9z+1FRacrm5OIQ7pfhkjK+ecPV
0D3gZIT3mMEKEWKreH9H2YH9scPsCkz2DQkx63A0QZgiR21CTyNf+rDmFd4nCS7bMhwB8rXktRkr
OHpW3PwwrsVyHwm181ByeGHnsEZpkxR7OwZzPZHhxr8KiPwSQzBgz2sDPEY6AfP8QhFJ16rRB9+5
dGFV/a4Sngl6sdal4dVw3j+ONu/dcM0nLQc3BXZFfSLvz/1mQy/lIG/85ltfUBTaKgWs8I9E0tW5
ml1rjmHy2uH60Kecu9T0X5dPu7ME/T7HfUXu+Y8COvcqMf1Ye6NpqBsZAlEP61tzO0I69Q2aXnsv
0J9MWo2kjR6k1rSmjgcpqfn2Qv5Zs7N3qm0BDYdzQXSFVVv978VHIn9KoSpWh8wAgDR7iWkF9A0a
vJgnrUcc8mUNVMpAK08ZTCmX3ku7QDDRXU+45c0esSMObAloUA4riE7Yeyy/EQMY2S7Szc6w7wMx
xkbuPxFHWSGfc8sIQQ3HrNoDqbyZJYelhSgB5KdZmtfr5JF3vsypTp23OuGe22HoQXoxBnCbM7vK
JmTTXYhKkHvK9JtLU1vFSdTw9wNcv6iur9WaRD9ljk6a81WEZZhjQtJh1uo4BsRdi148r6an93sb
WyLE8kRs8hVqp9lKA9DDTmSZo28P/u7Pl3ZFBWYY3ebft5ZCSNSTMD2B54n2Q1OiLan8GljfMZDO
LGhCHlJFp5i05RG/4L5ML3neorPF9JIsayLUdlg645bm0Q/eXN8KhLJF9rNRYNGkgCHkswstVkQE
9+CMNZHXDZRglQFZHLBA505w4PpTKpZKqt25ZEHGRpmPK3WnehVKSAhzUgWxOdWvJ6lesXw9wFl9
GGp6vLEwRpIupHvMdOYhGzacvIx22nY2C5gVzfh4K+8u1ugDzeCTGWYMDry7HsME6MkE1sCfEB5i
1SLADJj7H9T6L+Cq7Qn7pDKVqFAOzhdYeGAeDypcwwmExUnxLIm3Bm6DNXr6PsWN69hZZLFvw8za
Tmv6jifxZ47/GfJaiiyJe5Y7/5WU9TOEKalqWVy/TdZfKuiPdOpaacPu2jnELHy5iCPANkDjt0+y
T30G4VHecxjFWJg/JBYS6rHOLw++bARWyPhEaV74n2bYVV+hNvLa0i70KjLntXIzziWf6BzZIJxp
ul9ShR548fQT4Iq5pSc32v4QYubk69BokbxYcNCl55nYJxA2K3hkx71qUmpX21QLebNnPg0pQL3Y
LIlVd7aomLRq5sY/bfW/mpILhZBnb0eG3OZdrEicT9cD6XD7a3Uj74aaf6PXoF6AANQYR0UR2QhP
BJzhajquucwz443FQj6I2rMXGrKBRSzylsFiEstq61elVSfjAIaDaOWSXe8nfCdjh1TbvHWxPzdM
N9SIWFqaD9O53lt6n1Vgf7tD/b1JO/Xp/u04j9pbFqliZnt4CzjxJ+R6Oi2wV+Z9yqY3FqaO9SD6
sqRbUGgF1RmD+6R0EKIVlCo+72qVbc3lB7nqwNfOl06+ppU4fEbBwxjL/iCDRQwQAGWksIFvkEhs
15oHBUiMA4dh0y0uBCx2sR2HcUAtT/zg5vJ0vO/5dEt5EwRDyHQBi5fwY5AjdRrX590qKsRpCfYY
lCbJuofT0teZiM2FjC2wlB7P6t9+6fiWYwBu7Pfo++vqkSjwRLLxwIapAYWFTF+aCp3UusXiUJqI
YdIiVqCPZZEr4YUvUCKuN0EINEtwzgZ7fcBtsJH8g7qJFVH3wGfL3Jy0DII0MGl4zjP5dSrJerZS
jvfQRtAHpDPlHn2SZACT+PvFF4DdCzEa3GPTBedspzNsNS7Vwzb0DM75Lh+bnBF1r5i7CvXE9PUb
5D9MFc+Q1q99+z9n4kUemOjSgUWNsvBrlYSy2m10BBiQVHcY7cS3rLKStPRyBOOEWFBjJm1Ov1LI
dyhNS38D2tr7wNU/vQEcBPH6vWz96Ia4DXlIuMDvV1zWqQPGSXTmW/bvonE8qtgMFq/4jXXQ4OCc
YWfoJz3IpSUu/whXBoaZ0tvrBKO1BnFhn0cm5pUb8XO4UTaDTCzxwSgGUM+eCftc0ASXco/eIV/W
oID+6zmRvlsxYjai7g5eMMgry5HJRg8VcvsnbD5N7CgTuGSJKrUI4kamJY1gO0Ffg32t2HW0aov6
r2vRNKeCyXuA2r842yQBOxcxet6w05QxSqhnBVdJzjyhrWgfpGQOeFwk1sdDuMj6yLsIbn7ZOLmM
WjGq/d0Bv5E1i6SjCUw7OIHkCneRqjOXdNf3iXwFHPJXnuv64bkN/ACE0Fvjo7G8SivqsmKGyhPj
BbU/b0vk9M08VO9BPZ1ECYY9Pddvzp1S+HErfdK7YQzlJiPdSEctOl8L5Gn83POY+3wJu2Czx1pc
OmGcz0Rpa0PmYNoet5luRLQ5+o1JD07YWJv1tbWP+p+5F4wZZebnj0of+Rr6j5SyWtZTouVtJg29
VtK419mV+D9vOhSuxYuGMNa9patDtzpc8mhTYALKUykejtoRJtT5uKOsJ5fbkT6nofZWFkxZoNiE
3zi5XIW1HQzfTv/5kz2dWWiRFyISfv+abMoy8cCaFvPy5Om19NFgqMIr3PlNXDfOv1AtnvVY47ZX
gU+jHiS4h47Dm4j1JEnkFI34q0LHxldlg6DOLl09V/Ltpm+cyoPYRJXefCFsAtmMQOcqlsqhd/uj
eTQ4D1I7HWysEP1n1LSndrOkOWnz8klhUzCjGKMoz1WZWdTzGFvy62edMEW8RpXFhMYbewjnghLT
UJH7M7MOoOIztHwTgSfTjnBhPG0Q0MGmYfxp1K9Erj/8KTU/QoQk9rNAhzizY3dW+4PQoklCqPV+
iYLqSK+602GLFFOJ6ppDz0o7f+8eKXoaR/vSbftjLOdRBMO7CxIfFKkWU8HztV2Rlfuh41nlRnpb
NtnasZIV2iibkPj4OdrmzlwiDq35oLXS4n25sWe2H5X79YsfDy5dk4xCPq6/QcMQlDlNvxINoud6
nyd9rSY/x3QzOEDolTUAhtiCguzLZPAomkezVBvCMmQ03YcIL5XG6TIXknDJdXlkUh3VJWnEXwXy
5IsLCY610VUJJeM9KetsiZY7dFr1/J5/Z0hoZtmJmPVri1Mhv1YcnY5upxl5IyYyHjG3J3XIkF5P
4PposeUd9YelTZ6jaUcHStdy0mlJPfkXHtEzftSDB3yUD1cSKVs0UEemk7FCi6tBNN3bIjXey9mT
8yB78Cx6dzir2FmDzbiGruRx+kjHiunbdmQwdX8Jh1XTR6JoyyFgHVoXlmyl7BrI22tlM7TUd8Ix
wzdW2MYwFM1o0MfFH4iD3UyU0X8WKq5eRgDr90dbUP/Z40BnPXQIIMriIlVyyfu7staU8XNC8rMd
BMBnY/2FROEdVFcXgGhGpxiiK/DlsY2sFXsbc+CqyxiFUTRA2DB29XiALmc/PHadiPxcHDB5T2Da
hw99oe9+697Zw0H8LbTW++OwfrfMecapZC2X4UMU3ak4S8/pQ8pQf0C2w523Oum+4nKF7upGG2oK
UiMw0mnogj1Jgw4Or1wICKh2a4yFYUBAo4IUKLXBvjV2o9HZqhGf39141sc/LNpoMrbcRO0LiVA0
u9tXvHwKyaVhh3911Qtglje7znWdBmRrk2O7KEMa2yqLctv/W8fqgZyrAup9+koJvB3lO3sISpaJ
PPrm0c7cMGBQajHToBQ0hjX+ljLhNR3fuP7XvzG2uX3+T8vW0PMA1AETjKgF3vGsArjhe3vvC6nR
/TTdQb0XqJPjcshofr7xctZKhuL6FTY+y6bgtHbKwVJSUtQnmbUHdKOOsxWqvzrR6IdSmrOw/JvO
OOLhV9Jmx4eu2tp0lRQstq5eu5SqfLtBPBF5tUnS2A3nAMoMRlAWXKbTjOhhu+jjckt7V15IXqn3
nSShxeYAWeABMyNVyfNp9MCe6/TOojHE+dIpU8GEE70CX+D590LXM6mbKwpnfaVeGU+PfSM//eK7
kFbpafejdDSeCGBE6oT8NLUJFV3xzpYQBJrVQ+IJBUF51fdwd3e/RM3AB4KkRCKMj69grnp6IoHe
GegubecPswf6akq5Gg+XfTxrrqaLSArqWStDFNEVmZ9aP5AyRiXAi2yUeK1yY/wCmiXURxnl0oYY
xPrzDBxjiH1n9ax8QZYLjnk4F81E9TvgTsWQ4t2t4ookCCoZ9oBspiMZ6gmy4qqgRMBthI75qtXj
JhkVk6AFXgUJ5tMwHTl07UPNvJOjQ3NCsvF7ax+PIzBXvsA/nFFkg7IODyPvMKi8MqNRnZoSpTd1
7y2p6Z2S1nk7Ym5K1vWL6lD8Td83UZcwyfXuvrJxpF+9e2qed4b+zTQkHY32WehKtEKrmtGzJ31+
VXE5aQNBUghg9t8ac5kirmsxxVOJniKF8FPNLRwHuMIA7Ccwl54X8CpMaK/KZWWAA1H3eNh0sDMx
ktLp1VmulEi+DkkHoWVbz6UH/Y3dkvWsp40HvgEvbWjh+kJUbyS1pkL4LccqSKRqEIALF/OoHctY
vxgqRtd2VnRdGl9dwwdzQhdu+Fr09W6n+ySVWEoFyMtnBZw0Y+aD6EtPAezFKx/eQPTmnbYsPLES
4tuGmQJQPY02Hb6D776y0FuAgKjGpTX3zTdWjmce/wc0xUeK45LMPPCl/jDMxhiEI71NJpitnXvL
G0K6BxRoiW+IgP9r9FvrAjZvAK/b7pWfKiGciroa2xQp7rleyrFdm/7UYRVIdCt5kSMJQdcAcSrY
m8KCbxItAqBupTB4kyjIZMNfdZIsPdGfAvD7fd4JOJDdqxqOWb3V1ETudcgXKgalaZiT7t52Lfj+
nIVqEvQc9ihdjUNfQgMYEX+DVrL2EeXYTU4wIkiA8OhXWjLnfPA0CO5+JcbVwKHlQTJXmynIsb4p
+6U4I3EOT/anle9GU5mACM3LaKcBaDADFia+LFwT08NdhB63NH+OrJZF/MOymVae1t7mQh72Wsd0
ANHd9aSz9/p/VQb6iJ/r+kM+/NbcgJ4nXIW3qsYC7w48h7L46MQhXrlElgnYeZAjTSv8u8iD6zG/
PQJxJPzabirDh4PIVWZEvCH1xnHZluoV0v2lCWkdGMYhjH5Z13iue+Q/oNCUDDryYUefNGQIsEd6
tqyv0uSZnVlEN3SVcZcOyApAb3bQY4CwemQh591pRM8d0ywgrgcvkDYwLF8bFtY1WIppFGyffDRm
+FGfksTdpZauFMQ9uA0qNVidrexPFXXNYvRwXijE8bGXbKTx5eA6hI4eu5HzI42w+kcAEmL9y0Qm
HmE4oTo/taErEJphxVmbaNlqb1oLU4va5jWSIQQiffR2VHmnqX//thaq/itVR/2MWAHP+qJhmANF
v5dQLd+6k2/J2CZLWH2b5lQN8bB0nWZluzq7LfPqufD4D1rcKDskqcUzG36KnP7y2i47Vc9BHT9P
rK5NNrUsrKZap/60k5QoZFogMl1R3cBTYH5TbjXpn7+yNyiuGzDvxbzLKdcBJYLAIc3Dj3olonOp
+6ZHY2tZ1u+3cfq3GVYbjGmHt56+XkjTWMmri2zt6PsFlyXGslAatQTAhUNGrqEHSdPUf4NshSgG
qXggq63lcMrwLs6N2p3pM9Ejp+fu/9ECdN8EboSFWEnNZaWvX7zmss/OMCA23gqSXpHG7a1ccPVX
KtGlkd7dzNLzowkEwdLquK5vfexq+/Tjn6rFcp08VuY/Lv02Es2t2LRCfwc0whbQau4aGWJYxxAT
BfsLHJ377B1ACkCPbaw6Fdxr+IUWfxTP4GKPkx5bBamkfs7f5VRB/l2K8UKlpRev1CFWzqVkYrrs
BGx86AHGvlItjfbHH4hdfEzKQgMn/Q1Rks1456NYn/ZUVM0soKem+JkjaZWe2JbR3hB1eNFn4UoM
PXG4v4uFimdjAOUA7Qs4VkzUH6TpNBdanTqXLqXSev7e9KvjgUf16nmdOEQhyuhliwrDhb1C324Q
66czw/N5WaDDFmYafzODN8yHGEncSFrrPeYW7yR88Ps0Ttin/I+oQSkJ+t1f+Y+lnCG5+2NR5asR
bT9DaFlTwyTSqnjSW3T0R7HiSxaM0uC6jq7nYEfWcc3J6/MuKUxJxK8LvxJylkHa03DwsI5zhO38
6OFn10Kt6TAXYIOuE6rFLm5Q1FuFMBpUgY2HsfftdsEinMK96c6u9SO53fk/VkI1t9DOsNkoTw9F
Jmut028wB3XaY2xAPyvRIrPbthaJ1/K5DJVxx2TvGkehkfA0itGS5CpMoVTwHbjA1ZWvcZQRwMR0
f9KaOZSCxly9roCBBC0ndV6TJr8Ozf09COJol9fgfvcyq2jFub8b+7ObYtJNU0lwg1hR394qab2w
GY3Y1Z8bwDk+m4c0KBf0GZMcyqVH82/KflInOy6GzWGRbA88xCcqQiYdhusODgUpGk0P8HgJY1uI
h9tyhtCJWl1Uzdt+A/8Fe3j3e+91DudffLyRPaGZAWd6QbLN/vp0VcOv5Lj4uadbNZ/gv+7nFrJ2
Fa9rwXbSG9c4VYKJ/hqmqhaNsEncoUxcUVFz4Er/NnqH8Q4gRvCpxEL6sQzNM5d+Rx/M/CuxgGFQ
WtZiIhYZE+9QkKCCslAtdyNQMs5S1uVmDpxjaB172A1CXYhTI6Wvjonfrkw0JwK0infiFqE8KTNk
Q7OVh03UWh37N2jUalTS+Gv8HaQ1ygg0pnoryMAUNinb2OHNvnTeHRHHAi9DrkKz2V2jbe917jKZ
DUyoom+wgD8VmpolPgD5S5e2I49rfRzbehZjWdZ6EhNB/vXCJjE2zDicJ+VvGnPyXz9kBW8eF8KM
wjH2k5p0/MvO/oFuo5aSwvnlf+E/pWEPjfWuc4y6RJt861g4wk3fv6yJmHfs2tXP87nUIFeXIHh0
szH5OI/tGkSNMx8i9JEavLS6oaTYBTliu7DYdHLsro7cZDav2zlmLzFLJQtYD7ozOaC+cvjDKHsr
gdRrTsjiNK/5CzIc8sy95gcoonoAh2YUyTRWtz39JH3CON0PCaQAW8xvGpDgMVJiOsm6CUIyIODt
LLYYac1xQjguJpNmXhZK8EBvbMqMXEJQ5lQVyG7plqZ4O3h+LV485vzB872TdUUWfVblp5pDJzqw
JLMSc7TMJCqlZdBOxbzq7B7I7/a/20Vj8rPN+wtsV9p8Fg/aIKidH3doW3XRzwHEAVBBpcUIkmHs
5cSppPgcMpPrXnjCmtGWWAX+xXHGsPtrLY3Biqbi7TmdldyHPJiwUCG9QWsVvdyTgGAXUJb+EV7n
ltNho2PJcHCCXRR7mTlZllL+9iKFO6l8SApSUY6BNNbeo/yVfwRqkt0T7YkBrPvd7T/DizXeMxjK
<KEY>
<KEY>
`protect end_protected
|
<gh_stars>1-10
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/17/2015 05:17:03 PM
-- Design Name:
-- Module Name: MOV8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MOV8 is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end MOV8;
architecture Behavioral of MOV8 is
component SHL8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end component SHL8Bit;
signal OutputSHL1 : BIT_VECTOR(7 downto 0);
signal OutputSHL2 : BIT_VECTOR(7 downto 0);
signal OutputSHL3 : BIT_VECTOR(7 downto 0);
signal OutputSHL4 : BIT_VECTOR(7 downto 0);
begin
-- Shift InputA 4 bits to the left
SHL_Impl1: SHL8Bit port map(InputA, OutputSHL1);
SHL_Impl2: SHL8Bit port map(OutputSHL1, OutputSHL2);
SHL_Impl3: SHL8Bit port map(OutputSHL2, OutputSHL3);
SHL_Impl4: SHL8Bit port map(OutputSHL3, OutputSHL4);
Output <= OutputSHL4 or InputB;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_TX_FSM is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
tx : out STD_LOGIC;
txData : in STD_LOGIC_VECTOR (7 downto 0);
fifoEmpty : in STD_LOGIC;
txDone : out STD_LOGIC
);
end UART_TX_FSM;
architecture Behavioral of UART_TX_FSM is
component UART_TX_Control is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
status : in STD_LOGIC_VECTOR (2 downto 0); -- empty, delay, done
control : out STD_LOGIC_VECTOR (2 downto 0) -- reset counter, incr index, done
);
end component;
component UART_TX_Datapath is
Port(
clk : in STD_LOGIC;
tx : out STD_LOGIC;
txData : in STD_LOGIC_VECTOR (7 downto 0);
control : in STD_LOGIC_VECTOR (2 downto 0);
status : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;
signal status : STD_LOGIC_VECTOR (2 downto 0);
signal control : STD_LOGIC_VECTOR (2 downto 0);
signal datapathStatus : STD_LOGIC_VECTOR (1 downto 0);
begin
status <= datapathStatus & fifoEmpty;
txDone <= control(0);
txControl: UART_TX_Control port map (
clk => clk,
rst => rst,
status => status,
control => control
);
txDatapath: UART_TX_Datapath port map (
clk => clk,
tx => tx,
txData => txData,
control => control,
status => datapathStatus
);
end Behavioral;
|
-- Copyright 2018 <NAME>.
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the “License”); you may not use this file except in
-- compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
-- or agreed to in writing, software, hardware and materials distributed under
-- this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
-- CONDITIONS OF ANY KIND, either express or implied. See the License for the
-- specific language governing permissions and limitations under the License.
----------------------------------------------------------------------------------
-- Author: <NAME>
--
-- Create Date(mm/aaaa): 04/2018
-- Module Name: GP_Unit.vhd
-- Project: interpolation filter project for HEVC
-- Description: Parallel_Prefix_Adders
-- Dependencies: none
--
-- Revision:
-- 1.0 created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity GP_Unit is
port(
A,B :IN std_logic; -- adder inputs
G,P :OUT std_logic -- generate and propagate output
);
end entity GP_Unit;
architecture structure of GP_Unit is
begin
G <= A AND B;
P <= A XOR B;
end structure;
|
------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: <NAME> --
-- <NAME> --
------------------------------------------------------------
--
-- Create Date: Spring 2014
-- Module Name: Mem32Byte
-- Project Name: UMD-RISC 24
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- Code was modified from Handout Code: Dr.Fortier(c)
-- [Description]
--
-- Notes:
-- [Insert Notes]
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - [Insert]
--
-- Additional Comments:
-- [Insert Comments]
--
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VGA_RAM is
generic(
ADDR_WIDTH: integer:=12;
DATA_WIDTH: integer:=7
);
port(
CLOCK: in std_logic;
WRITE_ENABLE: in std_logic;
CLEAR : in std_logic;
ADDRESS_A: in std_logic_vector(ADDR_WIDTH-1 downto 0);
ADDRESS_B: in std_logic_vector(ADDR_WIDTH-1 downto 0);
DATA_IN_A: in std_logic_vector(DATA_WIDTH-1 downto 0);
--DATA_OUT_A: out std_logic_vector(DATA_WIDTH-1 downto 0);
--DATA_IN_B: in std_logic_vector(DATA_WIDTH-1 downto 0);
DATA_OUT_B: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end VGA_RAM;
architecture RAM_ARCH of VGA_RAM is
type ram_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal ram: ram_type:=(others=> x"00");
signal ADDRESS_A_REG: std_logic_vector(ADDR_WIDTH-1 downto 0);
signal ADDRESS_B_REG: std_logic_vector(ADDR_WIDTH-1 downto 0);
begin
process(CLOCK)
begin
if(CLEAR = '1') then
--ram <= (others => '0');
else
if (CLOCK'event and CLOCK = '1') then
if (WRITE_ENABLE = '1') then
ram(to_integer(unsigned(ADDRESS_A))) <= DATA_IN_A;
end if;
ADDRESS_A_REG <= ADDRESS_A;
ADDRESS_B_REG <= ADDRESS_B;
end if;
end if;
end process;
--DATA_OUT_A <= ram(to_integer(unsigned(ADDRESS_A_REG)));
DATA_OUT_B <= ram(to_integer(unsigned(ADDRESS_B_REG)));
end RAM_ARCH;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY comparator4 IS
PORT (
a, b : IN std_logic_vector (3 DOWNTO 0);
result : OUT std_logic_vector (2 DOWNTO 0)
);
END comparator4;
ARCHITECTURE behavior OF comparator4 IS
BEGIN
PROCESS (a, b)
BEGIN
IF a < b THEN
result <= "001";
ELSIF a = b THEN
result <= "010";
ELSIF a > b THEN
result <= "100";
ELSE
result <= "000";
END IF;
END PROCESS;
END behavior;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.