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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
entity clockDivider is
port (
CLK_50MHz : in std_logic; -- clock signal
clk : out std_logic); -- clk to blink
end clockDivider;
architecture Behavior of clockDivider is
signal counter : std_logic_vector(24 downto 0); -- signal that does the
-- counting
signal CLK_1HZ : std_logic; -- to drive the clk
begin -- Behavior
-- purpose: clk blinking
-- type : sequential
-- inputs : CLK_50MHz, <reset>
-- outputs:
Prescaler: process (CLK_50MHz)
begin -- process Prescaler
if CLK_50MHz'event and CLK_50MHz = '1' then -- rising clock edge
if counter < "100110001001011010000000" then -- Binary value is
-- 25e6
counter <= std_logic_vector(unsigned(counter) + 1);
else
CLK_1HZ <= not CLK_1HZ;
counter <= (others => '0');
end if;
end if;
end process Prescaler;
clk <= CLK_1HZ;
end Behavior;
|
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity sync_dpram is
port(
clk_l : in std_logic;
wrn : in std_logic;
waddr : in std_logic_vector( 9 downto 0);
data_in : in std_logic_vector( 7 downto 0);
clk_r : in std_logic;
rdn : in std_logic;
raddr : in std_logic_vector( 9 downto 0);
data_out : out std_logic_vector( 7 downto 0)
);
end sync_dpram;
architecture u_dpram of sync_dpram is
type mem_tbl is array (0 to 640) of std_logic_vector( 7 downto 0);
signal mem : mem_tbl;
begin
process (clk_l)
variable I_A : natural;
begin
I_A := conv_integer (waddr);
if rising_edge (clk_l) then
if (wrn = '1') then
mem (I_A) <= data_in;
end if;
end if;
end process;
process(clk_r)
variable I_A : natural;
begin
I_A := conv_integer(raddr);
if rising_edge (clk_r) then
if (rdn = '1') then
data_out <= mem(I_A);
else
data_out <= (others=>'0');
end if;
end if;
end process;
end u_dpram;
|
<filename>ECE351_final_project/clk_divider.vhd
----------------------------------------------------------------------------------
--
-- Author: <NAME> - <EMAIL>, <NAME> - <EMAIL>
-- ECE-351: Course Project - Greenhouse Monitor
-- Notes: Clock divider
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity clk_divider is
Port (
rst: in std_logic;
clk_in : in std_logic;
clk_out : out std_logic;
const : in INTEGER
);
end clk_divider;
architecture clk_divider_arch of clk_divider is
signal counter : integer := 0;
signal clk_tp : std_logic := '0';
begin
clk_out <= clk_tp;
DIVIDER: process(clk_in, rst) is
begin
if (rst = '1') then
counter <= 0;
clk_tp <= '0';
elsif (rising_edge(clk_in)) then
if counter = const then
counter <= 0;
clk_tp <= not clk_tp;
else
counter <= counter + 1;
end if;
end if;
end process DIVIDER;
end clk_divider_arch;
|
-- Creates a DDR output with implementations for different platforms.
--
-- TODO: Test the 'asic' architecture. Decide if this is even the right
-- approach for the asic.
library ieee;
use ieee.std_logic_1164.all;
entity ddr_output is
generic (
-- DDR_ALIGNMENT = OPPOSITE_EDGE or SAME_EDGE
DDR_ALIGNMENT : string := "OPPOSITE_EDGE";
INIT : std_logic := '0';
-- SRTYPE = ASYNC or SYNC
SRTYPE : string := "SYNC");
port (
clk : in std_logic;
rst : in std_logic;
d1 : in std_logic;
d2 : in std_logic;
q : out std_logic);
begin
assert DDR_ALIGNMENT = "OPPOSITE_EDGE" or DDR_ALIGNMENT = "SAME_EDGE"
report "Invalid DDR_ALIGNMENT" severity failure;
assert SRTYPE = "ASYNC" or SRTYPE = "SYNC"
report "Invalid SRTYPE" severity failure;
end entity;
-- This 'asic' implementation is untested
architecture asic of ddr_output is
signal d2_latch : std_logic := INIT;
begin
oppedge : if DDR_ALIGNMENT = "OPPOSITE_EDGE" generate
-- synch reset and latches d1 at the rising clk edge and d2 at the
-- falling edge
sync_gen : if SRTYPE = "SYNC" generate
p : process(clk, rst, d1, d2)
begin
if clk'event then
if rst = '1' then
q <= INIT;
elsif clk = '1' then
q <= d1;
else
q <= d2;
end if;
end if;
end process;
end generate;
async_gen : if SRTYPE = "ASYNC" generate
-- asynch reset and latches d1 at the rising clk edge and d2 at the
-- falling edge
p : process(clk, rst, d1, d2)
begin
if rst = '1' then
q <= INIT;
elsif clk'event then
if clk = '1' then
q <= d1;
else
q <= d2;
end if;
end if;
end process;
end generate;
end generate;
sameedge : if DDR_ALIGNMENT = "SAME_EDGE" generate
sync_gen : if SRTYPE = "SYNC" generate
-- synch reset and latches d1 and d2 at the rising clk edge
p : process(clk, rst, d1, d2)
begin
if clk'event then
if rst = '1' then
q <= INIT;
d2_latch <= INIT;
elsif clk = '1' then
q <= d1;
d2_latch <= d2;
else
q <= d2_latch;
end if;
end if;
end process;
end generate;
async_gen : if SRTYPE = "ASYNC" generate
-- asynch reset and latches d1 and d2 at the rising clk edge
p : process(clk, rst, d1, d2)
begin
if rst = '1' then
q <= INIT;
d2_latch <= INIT;
elsif clk'event then
if clk = '1' then
q <= d1;
d2_latch <= d2;
else
q <= d2_latch;
end if;
end if;
end process;
end generate;
end generate;
end architecture;
|
<filename>src/sap1.vhd<gh_stars>1-10
library IEEE;
use IEEE.std_logic_1164.ALL;
entity sap1 is
port (
in_clk : in std_logic;
-- start/clear 1/0
s5 : in std_logic;
sap_out : out std_logic_vector(7 downto 0)
);
end entity sap1;
architecture structure of sap1 is
------------------------------
-- Components declaration --
------------------------------
component pc is
port (
-- The output port to W bus
w_bus : out std_logic_vector ( 3 downto 0);
-- Outputs the counter value to w_bus
ep : in std_logic;
-- Increment program counter by 1
cp : in std_logic;
bar_clk : in std_logic;
-- Reset counter to 0000 asynchronously
bar_clr : in std_logic
);
end component pc;
component regb is
port (
-- Read from W bus
bar_lb : in std_logic;
-- Clock
clk : in std_logic;
-- The input port from W bus
w_bus : in std_logic_vector(7 downto 0);
-- The output to the addsub
out_to_addsub : out std_logic_vector(7 downto 0)
);
end component regb;
component regout is
port (
-- Read from W bus
bar_Lo : in std_logic;
-- Clock
clk : in std_logic;
-- The input port from W bus
w_bus : in std_logic_vector(7 downto 0);
-- The output of the sap
sap_out : out std_logic_vector(7 downto 0)
);
end component regout;
component mar is
port (
-- Enable read from w_bus
bar_lm : in std_logic;
-- Clock
clk : in std_logic;
-- Input from W bus
w_bus : in std_logic_vector(3 downto 0);
-- Output to ram
out_to_ram : out std_logic_vector(3 downto 0)
);
end component mar;
component ir is
port (
-- Enable read from W bus
bar_li : in std_logic;
-- Enable write to W bus and controller sequencer
bar_ei : in std_logic;
-- Clock
clk : in std_logic;
-- Clear instruction register
clr : in std_logic;
-- Send to controller sequencer an instruction code
out_to_conseq: out std_logic_vector(3 downto 0);
-- Send and receive data from W bus
w_bus : inout std_logic_vector(7 downto 0)
);
end component ir;
component ctrlseq is
port (
-- Control words
microinstruction : out std_logic_vector(11 downto 0);
-- LDA, ADD, SUB, HLT or OUT in binary form
macroinstruction : in std_logic_vector(3 downto 0);
-- clk
clk : in std_logic;
-- clr
bar_clr : in std_logic;
-- Halt
bar_hlt : out std_logic
);
end component ctrlseq;
component accumulator is
port (
-- When LOW read from W bus
bar_la : in std_logic;
-- When HIGH write to the W bus
ea : in std_logic;
-- Clock signal
clk : in std_logic;
-- The input and output port to W bus
w_bus : inout std_logic_vector (7 downto 0);
-- The output to the addsub
out_to_addsub: out std_logic_vector (7 downto 0)
);
end component accumulator;
component addsub is
port (
-- Input from accumulator register
in_from_acc : in std_logic_vector ( 7 downto 0);
-- Input from B register
in_from_bReg : in std_logic_vector (7 downto 0);
-- The output port to the W bus
w_bus : out std_logic_vector(7 downto 0);
-- When high, performs subtraction and sends the results to
-- W bus
su : in std_logic;
-- When high, adds accumulator and B register contents and
-- sends the results to w_bus
eu : in std_logic
);
end component addsub;
component ram is
port (
-- Enable read from MAR
bar_ce : in std_logic;
-- Input from MAR
in_from_mar : in std_logic_vector(3 downto 0 );
-- Output to W bus
w_bus : out std_logic_vector(7 downto 0 )
);
end component ram;
component debounce is
-- How many clock cycles to wait before transfer in_switch to out_switch
generic (debounce_ticks : integer);
port(
-- Clock
clk : in std_logic;
-- Input from Switch
in_switch : in std_logic;
-- Debounce signal
out_switch : out std_logic);
end component debounce;
----------------------------------------
-- Intermediate signals declaration --
----------------------------------------
signal microinstruction : std_logic_vector ( 11 downto 0);
-- cp : microinstruction(11) -
-- ep : microinstruction(10) -
-- bar_lm : microinstruction(9) -
-- bar_ce : microinstruction(8) -
-- bar_li : microinstruction(7) -
-- bar_ei : microinstruction(6) -
-- bar_la : microinstruction(5) -
-- ea : microinstruction(4) -
-- su : microinstruction(3) -
-- eu : microinstruction(2) -
-- bar_lb : microinstruction(1) -
-- bar_Lo : microinstruction(0) -
signal w_bus : std_logic_vector(7 downto 0);
-- signal bar_clr : std_logic;
signal ram_mar_bus : std_logic_vector ( 3 downto 0);
signal acc_addsub_bus : std_logic_vector ( 7 downto 0);
signal regb_addsub_bus : std_logic_vector ( 7 downto 0);
signal ir_ctrlseq_bus : std_logic_vector ( 3 downto 0);
signal clk, bar_clk, bar_clr, clr , bar_hlt: std_logic;
signal ds5 : std_logic;
constant debounce_ticks: integer := 3;
begin
-- Debounce
debounce5: debounce generic map(debounce_ticks => debounce_ticks)
port map(
clk => in_clk,
in_switch => s5,
out_switch => ds5);
-- s5 start/clear 1/0
clr <= '1' when ds5 = '0' else '0';
bar_clr <= not clr;
-- stop the clock when bar_hlt is 0
clk <= in_clk and bar_hlt;
bar_clk <= not clk;
------------------------------
-- Components instantiation --
------------------------------
accumulator0: accumulator port map (
bar_la => microinstruction(5),
ea => microinstruction(4),
clk => clk,
w_bus => w_bus,
out_to_addsub => acc_addsub_bus
);
addsub0: addsub port map (
su => microinstruction(3),
eu => microinstruction(2),
w_bus => w_bus,
in_from_bReg => regb_addsub_bus,
in_from_acc => acc_addsub_bus
);
pc0: pc port map (
cp => microinstruction(11),
ep => microinstruction(10),
w_bus => w_bus(3 downto 0),
bar_clk => bar_clk,
bar_clr => bar_clr
);
regb0 : regb port map (
bar_lb => microinstruction(1),
w_bus => w_bus,
clk => clk,
out_to_addsub => regb_addsub_bus
);
regout0 : regout port map (
bar_Lo => microinstruction(0),
w_bus => w_bus,
clk => clk,
sap_out => sap_out
);
mar0 : mar port map(
bar_lm => microinstruction(9),
w_bus => w_bus(3 downto 0),
clk => clk,
out_to_ram => ram_mar_bus
);
ram0 : ram port map (
bar_ce => microinstruction(8),
w_bus => w_bus,
in_from_mar => ram_mar_bus
);
ir0 : ir port map (
bar_li => microinstruction(7),
bar_ei => microinstruction(6),
w_bus => w_bus,
clk => clk,
clr => clr,
out_to_conseq => ir_ctrlseq_bus
);
ctrlseq0 : ctrlseq port map(
microinstruction => microinstruction,
macroinstruction => ir_ctrlseq_bus,
clk => clk,
bar_clr => bar_clr,
bar_hlt => bar_hlt
);
end structure;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
entity timer is
port(
-- INPUTS
-- input signals from State Machine
clock, reset : in std_logic;
start_timer_reset, start_timer_timeout: in std_logic;
-- OUTPUTS
-- output signals to State Machine
after_1_us: out std_logic;
no_signal_timeout: out std_logic;
timer_out: out std_logic_vector (7 downto 0)
);
end timer;
architecture rtl of timer is
-- Internal signal declarition goes HERE
signal ticks : integer := 0;
-- assumes a 100ns input clock ie 10MHz
signal tick_1_us : integer := 10;
begin
timer_proc: process(clock, reset, start_timer_reset)
begin
if(reset = '1') then
after_1_us <= '0';
ticks <= 0;
elsif(rising_edge(clock)) then
if(start_timer_reset = '1') then
if(ticks = (tick_1_us - 1)) then
after_1_us <= '1';
ticks <= 0;
else
ticks <= ticks + 1;
after_1_us <= '0';
end if;
elsif(start_timer_timeout = '1') then
if(ticks = (tick_1_us - 1)) then
after_1_us <= '1';
ticks <= 0;
else
ticks <= ticks + 1;
after_1_us <= '0';
end if;
end if;
end if;
timer_out <= std_logic_vector(to_unsigned(ticks, timer_out'length));
end process timer_proc;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_tx is
generic(
DBIT: integer := 8; -- Anzahl Datenbits
PARITY_EN: std_logic := '1'; -- Parity bit (1 = enable, 0 = disable)
SB_TICK: integer := 16 -- Anzahl s_tick f stopbbit
);
port(
clk, reset: in std_logic;
tx_start: in std_logic;
s_tick: in std_logic;
din: in std_logic_vector(7 downto 0);
tx_done_tick: out std_logic;
tx: out std_logic;
parity_bit: in std_logic
);
end uart_tx ;
architecture main of uart_tx is
type state_type is (idle, start, data, parity, stop);-- FSM status typen
signal state_reg, state_next: state_type; -- Status Register
signal s_reg, s_next: unsigned(4 downto 0); -- Register für Stop Bit
signal n_reg, n_next: unsigned(3 downto 0); -- Anzahl empfangener bits
signal b_reg, b_next: std_logic_vector(7 downto 0); -- Datenwort
signal tx_reg, tx_next: std_logic; -- tx_reg: transmission register, routed to tx
begin
-- register
process(clk,reset)
begin
if (rising_edge(clk) and clk='1') then
if reset = '1' then
state_reg <= idle;
s_reg <= (others=>'0');
n_reg <= (others=>'0');
b_reg <= (others=>'0');
tx_reg <= '1';
elsif reset = '0' then
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
tx_reg <= tx_next;
end if;
end if;
end process;
-- next-state logic & data path functional units/routing
process(state_reg,s_reg,n_reg,b_reg,s_tick,
tx_reg,tx_start,din, parity_bit)
begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
tx_next <= tx_reg ;
tx_done_tick <= '0';
case state_reg is -- state machine (idle, start, data, stop)
when idle => --idle
tx_next <= '1'; -- tx = 1 während idle
if tx_start='1' then -- tx_start = 1 => state: data
state_next <= start;
s_next <= (others=>'0');
b_next <= din; --b_next = 8 bit Datenwort aus din
end if;
when start => --start
tx_next <= '0'; --startbit
if (s_tick = '1') then
if s_reg=7 then --nach 15 sample ticks status => data
state_next <= data;
s_next <= (others=>'0');
n_next <= (others=>'0');
else
s_next <= s_reg + 1;
end if;
end if;
when data => --data
tx_next <= b_reg(0);
if (s_tick = '1') then
if s_reg=15 then
s_next <= (others=>'0');
b_next <= '0' & b_reg(7 downto 1) ; --shift register
if n_reg=(DBIT-1) then --then n_reg = 8 => stop
if PARITY_EN = '1' then
state_next <= parity;
elsif PARITY_EN = '0' then
state_next <= stop;
end if;
else
n_next <= n_reg + 1;
end if;
else
s_next <= s_reg + 1;
end if;
end if;
when parity =>
tx_next <= parity_bit;
if s_tick = '1' then
if s_reg = 15 then
s_next <= (others=>'0');
state_next <= stop;
else
s_next <= s_reg + 1;
end if;
end if;
when stop => --stop
tx_next <= '1';
if (s_tick = '1') then
if s_reg=(SB_TICK-1) then
state_next <= idle;
tx_done_tick <= '1';
else
s_next <= s_reg + 1;
end if;
end if;
end case;
end process;
tx <= tx_reg;
end main;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ASM is
port (reset, clk, ini: in std_logic; a_in, b_in: in std_logic_vector (3 downto 0);
fin: out std_logic;r: out std_logic_vector (7 downto 0));
end ASM;
architecture Structural of ASM is
component Controller
port (clk, reset, ini: in std_logic; zero: in std_logic;
control: out std_logic_vector (4 downto 0); fin: out std_logic);
end component Controller;
component data_path
port (clk, reset: in std_logic; a_in, b_in: in std_logic_vector (3 downto 0);
control: in std_logic_vector (4 downto 0);zero: out std_logic; r: out std_logic_vector (7 downto 0));
end component data_path;
signal zero: std_logic;
signal control: std_logic_vector (4 downto 0);
begin
mod_Controller: Controller port map (
clk => clk,
reset => reset,
ini => ini,
zero => zero,
control => control,
fin => fin
);
mod_data_path: data_path port map (
clk => clk,
reset => reset,
a_in => a_in,
b_in => b_in,
control => control,
zero => zero,
r => r
);
end Structural;
|
<gh_stars>10-100
-- async / sync 1R sync 1W register file
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture inferred of RF1_BW is
type mem_t is array ( natural range <> ) of std_logic_vector(WIDTH-1 downto 0);
signal mem : mem_t(0 to DEPTH-1);
signal la0 : integer range 0 to DEPTH-1;
begin
-- clock in and capture input data / address / write enable : sync write
pw : process(clk, rst, D, WE, RA0, WA)
begin
if rst = '1' then
la0 <= 0;
elsif clk'event and clk = '1' then
la0 <= RA0;
for i in 0 to (D'length / 8)-1 loop
if WE(i) = '1' then mem(WA)(8 * i + 7 downto 8 * i) <=
D (8 * i + 7 downto 8 * i); end if;
end loop;
end if;
end process;
grb : if sync = false generate
-- output buffers : async read
q0 <= mem(ra0);
end generate;
grr : if sync = true generate
-- output buffers : sync read
q0 <= mem(la0);
end generate;
end inferred;
|
--*****************************************************************************
--* Copyright (c) 2012 by <NAME>. All rights reserved.
--*
--* Redistribution and use in source and binary forms, with or without
--* modification, are permitted provided that the following conditions
--* are met:
--*
--* 1. Redistributions of source code must retain the above copyright
--* notice, this list of conditions and the following disclaimer.
--* 2. Redistributions in binary form must reproduce the above copyright
--* notice, this list of conditions and the following disclaimer in the
--* documentation and/or other materials provided with the distribution.
--* 3. Neither the name of the author nor the names of its contributors may
--* be used to endorse or promote products derived from this software
--* without specific prior written permiSS_asyncion.
--*
--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
--* "AS IS" AND ANY EXPRESS_async OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS_async
--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS_async
--* OF USE, DATA, OR PROFITS; OR BUSINESS_async INTERRUPTION) HOWEVER CAUSED
--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSS_asyncIBILITY OF
--* SUCH DAMAGE.
--*
--*****************************************************************************
--* History:
--*
--* 14.07.2011 mifi First Version
--*****************************************************************************
--*****************************************************************************
--* DEFINE: Library *
--*****************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
--*****************************************************************************
--* DEFINE: Entity *
--*****************************************************************************
entity sc_fpga is
port(
CLOCK_50 : in std_logic;
LED_GREEN : out std_logic_vector(7 downto 0);
KEY : in std_logic_vector(1 downto 0);
SW : in std_logic_vector(3 downto 0);
RPI : in std_logic_vector(3 downto 0);
SS_async : in std_logic;
SCLK_async : in std_logic;
MOSI_async : in std_logic;
MISO_async : out std_logic;
SS_out : out std_logic;
SCLK_out : buffer std_logic;
MOSI_out : out std_logic;
MISO_out : out std_logic;
UART0_out : out std_logic;
UART0_in : in std_logic;
UART0_rts : out std_logic;
UART1_out : out std_logic;
UART1_in : in std_logic;
UART1_rts : out std_logic
);
end entity sc_fpga;
--*****************************************************************************
--* DEFINE: Architecture *
--****************************************************************************
architecture syn of sc_fpga is
type uartstate_type is (IDLE0,UART0TX,UART1RX,IDLE1,UART1TX,UART0RX);
signal uartstate : uartstate_type;
--
-- Define all components which are included here
--
component pll
port (
inclk0 : in std_logic := '0';
c0 : out std_logic ;
locked : out std_logic
);
end component pll;
component spi
port(
clk : in std_logic;
rst : in std_logic;
SS_async : in std_logic;
SCLK_async : in std_logic;
MOSI_async : in std_logic;
MISO_async : out std_logic;
data_out : buffer std_logic_vector(7 downto 0); --from rpi
data_in : in std_logic_vector(7 downto 0); --to rpi
data_out_valid : buffer std_logic
);
end component;
component spi_decoder
port(
clk : in std_logic;
rst : in std_logic;
spidata_out : out std_logic_vector(7 downto 0); --to rpi
spidata_in : in std_logic_vector(7 downto 0); --from rpi
spidata_valid_in : in std_logic;
leds : out std_logic_vector(7 downto 0);
pll_locked : in std_logic;
version : in std_logic_vector(7 downto 0);
extreg_dataout : out std_logic_vector(7 downto 0);
extreg_addressout : out std_logic_vector(7 downto 0);
extreg_read_req : out std_logic;
extreg_enable : out std_logic;
extreg_datain : in std_logic_vector(7 downto 0);
extreg_data_valid : in std_logic;
extreg_addressin : out std_logic_vector(7 downto 0)
);
end component;
component registerfile is
port(
clk : in std_logic;
rst : in std_logic;
writer_data : in std_logic_vector(7 downto 0);
writer_address : in std_logic_vector(7 downto 0);
writer_enable : in std_logic;
writer2_data : in std_logic_vector(7 downto 0);
writer2_address: in std_logic_vector(7 downto 0);
writer2_enable : in std_logic;
reader_data : out std_logic_vector(7 downto 0);
reader_data_valid : out std_logic;
reader_read_req : in std_logic;
reader_address : in std_logic_vector(7 downto 0);
reader2_data : out std_logic_vector(7 downto 0);
reader2_data_valid : out std_logic;
reader2_read_req : in std_logic;
reader2_address : in std_logic_vector(7 downto 0)
);
end component;
component uart_halfduplex is
port(
clk : in std_logic;
rst : in std_logic;
parallell_data_out : out std_logic_vector(7 downto 0);
parallell_data_out_valid : out std_logic;
uart_data_in : in std_logic;
parallell_data_in : in std_logic_vector(7 downto 0);
parallell_data_in_valid : in std_logic;
parallell_data_in_sent : out std_logic;
uart_data_out : out std_logic;
rts : out std_logic
);
end component;
component uart_controller
port (
clk : in std_logic;
rst : in std_logic;
rts_screen : out std_logic;
datarec_screen : in std_logic;
data_from_screen : in std_logic_vector(7 downto 0);
data_to_screen : out std_logic_vector(7 downto 0);
write_address : out std_logic_vector(7 downto 0);
write_data : out std_logic_vector(7 downto 0);
write_en : out std_logic;
read_req : out std_logic;
read_address : out std_logic_vector(7 downto 0);
read_data : in std_logic_vector(7 downto 0);
read_data_valid : in std_logic;
rts_track : out std_logic;
datarec_track : in std_logic;
data_from_track : in std_logic_vector(7 downto 0);
data_to_track : out std_logic_vector(7 downto 0)
);
end component uart_controller;
signal clk : std_logic;
signal rst : std_logic;
signal rst_cnt : std_logic_vector(15 downto 0):= "0000000000000000";
signal pll_locked : std_logic;
signal spidata_from_master : std_logic_vector(7 downto 0);
signal spidata_to_master : std_logic_vector(7 downto 0);
signal spidata_valid_from_master : std_logic;
constant VERSION : std_logic_vector(7 downto 0):= "00001001";
signal uart_controller_to_rf_write_data : std_logic_vector(7 downto 0);
signal uart_controller_to_rf_write_address : std_logic_vector(7 downto 0);
signal uart_controller_to_rf_write_valid : std_logic;
signal uart_controller_to_rf_read_req : std_logic;
signal rf_to_uart_controller_read_address : std_logic_vector(7 downto 0);
signal rf_to_uart_controller_read_data : std_logic_vector(7 downto 0);
signal rf_to_uart_controller_data_valid : std_logic;
signal spi_decoder_to_rf_data_valid : std_logic;
signal spi_decoder_to_rf_data : std_logic_vector(7 downto 0);
signal rf_to_spi_decoder_read_req : std_logic;
signal spi_decoder_to_rf_address : std_logic_vector(7 downto 0);
signal rs485data_to_spi : std_logic_vector(7 downto 0);
signal rf_to_spi_decoder_data_valid : std_logic;
signal rs485address_to_spi : std_logic_vector(7 downto 0);
--UART
signal UART0_parallell_data_out : std_logic_vector(7 downto 0);
signal UART0_parallell_data_out_valid : std_logic;
signal UART0_parallell_data_in : std_logic_vector(7 downto 0);
signal UART0_parallell_data_in_valid : std_logic;
signal UART0_parallell_data_in_sent : std_logic;
signal UART1_parallell_data_out : std_logic_vector(7 downto 0);
signal UART1_parallell_data_out_valid : std_logic;
signal UART1_parallell_data_in : std_logic_vector(7 downto 0);
signal UART1_parallell_data_in_valid : std_logic;
signal UART1_parallell_data_in_sent : std_logic;
signal UART_payload : std_logic_vector(7 downto 0);
begin
inst_pll : pll
port map (
inclk0 => CLOCK_50,
c0 => clk,
locked => pll_locked
);
inst_spi : spi
port map (
clk => clk,
rst => rst,
SS_async => SS_async,
SCLK_async => SCLK_async,
MOSI_async => MOSI_async,
MISO_async => MISO_async,
data_out => spidata_from_master,
data_in => spidata_to_master,
data_out_valid => spidata_valid_from_master
);
inst_spi_decoder : spi_decoder
port map (
clk => clk,
rst => rst,
spidata_out => spidata_to_master,
spidata_in => spidata_from_master,
spidata_valid_in => spidata_valid_from_master,
pll_locked => pll_locked,
version => VERSION,
leds => LED_GREEN,
extreg_dataout => spi_decoder_to_rf_data, --should later come from rs485 block
extreg_addressout => spi_decoder_to_rf_address, --should later come from rs485 block
extreg_read_req => rf_to_spi_decoder_read_req,
extreg_enable => spi_decoder_to_rf_data_valid,
extreg_datain => rs485data_to_spi,
extreg_data_valid => rf_to_spi_decoder_data_valid,
extreg_addressin => rs485address_to_spi
);
inst_registerfile : registerfile
port map(
clk => clk,
rst => rst,
writer_data => spi_decoder_to_rf_data,
writer_address => spi_decoder_to_rf_address,
writer_enable => spi_decoder_to_rf_data_valid,
writer2_data => uart_controller_to_rf_write_data,
writer2_address => uart_controller_to_rf_write_address,
writer2_enable => uart_controller_to_rf_write_valid,
reader_read_req => rf_to_spi_decoder_read_req,
reader_data => rs485data_to_spi,
reader_data_valid => rf_to_spi_decoder_data_valid,
reader_address => rs485address_to_spi,
reader2_read_req => uart_controller_to_rf_read_req,
reader2_data => rf_to_uart_controller_read_data,
reader2_data_valid => rf_to_uart_controller_data_valid,
reader2_address => rf_to_uart_controller_read_address
);
inst_UART0 : uart_halfduplex
port map(
clk => clk,
rst => rst,
parallell_data_out => UART0_parallell_data_out,
parallell_data_out_valid => UART0_parallell_data_out_valid,
uart_data_in => UART0_in,
parallell_data_in => UART0_parallell_data_in,
parallell_data_in_valid => UART0_parallell_data_in_valid,
parallell_data_in_sent => UART0_parallell_data_in_sent,
uart_data_out => UART0_out,
rts => UART0_rts
);
inst_UART1 : uart_halfduplex
port map(
clk => clk,
rst => rst,
parallell_data_out => UART1_parallell_data_out,
parallell_data_out_valid => UART1_parallell_data_out_valid,
uart_data_in => UART1_in,
parallell_data_in => UART1_parallell_data_in,
parallell_data_in_valid => UART1_parallell_data_in_valid,
parallell_data_in_sent => UART1_parallell_data_in_sent,
uart_data_out => UART1_out,
rts => UART1_rts
);
inst_UART_CONTROLLER : uart_controller
port map(
clk => clk,
rst => rst,
rts_screen => UART1_parallell_data_in_valid,
datarec_screen => UART1_parallell_data_out_valid,
data_from_screen => UART1_parallell_data_out,
data_to_screen => UART1_parallell_data_in,
write_address => uart_controller_to_rf_write_address,
write_data => uart_controller_to_rf_write_data,
write_en => uart_controller_to_rf_write_valid,
read_req => uart_controller_to_rf_read_req,
read_address => rf_to_uart_controller_read_address,
read_data => rf_to_uart_controller_read_data,
read_data_valid => rf_to_uart_controller_data_valid,
rts_track => UART0_parallell_data_in_valid,
datarec_track => UART0_parallell_data_out_valid,
data_from_track => UART0_parallell_data_out,
data_to_track => UART0_parallell_data_in
);
--async trigg of reset, sync release
process(clk,pll_locked)
begin
if(pll_locked = '0') then
rst <= '1';
elsif(clk'event and clk = '1') then
if(rst_cnt = x"FFFF") then
rst <= '0';
else
rst_cnt <= rst_cnt + 1;
end if;
end if;
end process;
--UART1_parallell_data_in <= UART0_parallell_data_out;
--UART0_parallell_data_in <= UART1_parallell_data_out;
--SS_out <= '0';
--SCLK_out <= '0';
MOSI_out <= '0';
MISO_out <= '0';
-- LED_GREEN <= uart_controller_to_rf_write_address;
-- LED_GREEN <= UART1_parallell_data_in;
-- LED_GREEN <= UART0_parallell_data_out;
end architecture syn;
-- *** EOF ***
|
<filename>vhdl/fetchbuffer/fetchctrl.vhd
-- args: --std=08 --ieee=synopsys
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.configure.all;
use work.constants.all;
use work.wire.all;
entity fetchctrl is
generic(
fetchbuffer_depth : integer := fetchbuffer_depth
);
port(
reset : in std_logic;
clock : in std_logic;
fetchctrl_i : in fetchbuffer_in_type;
fetchctrl_o : out fetchbuffer_out_type;
fetchram_i : out fetchram_in_type;
fetchram_o : in fetchram_out_type;
imem_o : in mem_out_type;
imem_i : out mem_in_type
);
end fetchctrl;
architecture behavior of fetchctrl is
type reg_type is record
pc : std_logic_vector(63 downto 0);
npc : std_logic_vector(63 downto 0);
fpc : std_logic_vector(63 downto 0);
nfpc : std_logic_vector(63 downto 0);
instr : std_logic_vector(31 downto 0);
rdata : std_logic_vector(63 downto 0);
rdata1 : std_logic_vector(63 downto 0);
rdata2 : std_logic_vector(63 downto 0);
wdata : std_logic_vector(63 downto 0);
incr : std_logic;
oflow : std_logic;
wden1 : std_logic;
wden2 : std_logic;
rden1 : std_logic;
rden2 : std_logic;
ready : std_logic;
flush : std_logic;
busy : std_logic;
wren : std_logic;
valid : std_logic;
spec : std_logic;
fence : std_logic;
clear : std_logic;
nspec : std_logic;
nfence : std_logic;
waddr : natural range 0 to 2**fetchbuffer_depth-1;
raddr1 : natural range 0 to 2**fetchbuffer_depth-1;
raddr2 : natural range 0 to 2**fetchbuffer_depth-1;
stall : std_logic;
end record;
constant init_reg : reg_type := (
pc => bram_base_addr,
npc => bram_base_addr,
fpc => bram_base_addr,
nfpc => bram_base_addr,
instr => nop,
rdata => (others => '0'),
rdata1 => (others => '0'),
rdata2 => (others => '0'),
wdata => (others => '0'),
incr => '0',
oflow => '0',
wden1 => '0',
wden2 => '0',
rden1 => '0',
rden2 => '0',
ready => '0',
flush => '0',
busy => '0',
wren => '0',
valid => '0',
spec => '0',
fence => '0',
clear => '0',
nspec => '0',
nfence => '0',
waddr => 0,
raddr1 => 0,
raddr2 => 1,
stall => '0'
);
signal r, rin : reg_type := init_reg;
begin
process(r,fetchctrl_i,fetchram_o,imem_o)
variable v : reg_type;
begin
v := r;
v.instr := nop;
v.stall := '0';
v.incr := '0';
v.wren := '0';
v.wden1 := '0';
v.wden2 := '0';
v.rden1 := '0';
v.rden2 := '0';
v.valid := fetchctrl_i.valid;
v.clear := fetchctrl_i.clear;
v.spec := fetchctrl_i.spec;
v.fence := fetchctrl_i.fence;
v.pc := fetchctrl_i.pc;
v.npc := fetchctrl_i.npc;
v.rdata := imem_o.mem_rdata;
v.ready := imem_o.mem_ready;
v.flush := imem_o.mem_flush;
v.busy := imem_o.mem_busy;
if v.ready = '1' then
if v.oflow = '1' and v.waddr < v.raddr1 then
v.wren := '1';
elsif v.oflow = '0' then
v.wren := '1';
end if;
v.wdata := v.rdata;
end if;
if v.oflow = '0' and v.raddr1 < v.waddr then
v.rden1 := '1';
elsif v.oflow = '1' then
v.rden1 := '1';
end if;
if v.oflow = '0' and v.raddr2 < v.waddr then
v.rden2 := '1';
elsif v.oflow = '1' and v.raddr2 /= v.waddr then
v.rden2 := '1';
end if;
if v.wren = '1' and v.rden1 = '0' and v.waddr = v.raddr1 then
v.wden1 := '1';
end if;
if v.wren = '1' and v.rden2 = '0' and v.waddr = v.raddr2 then
v.wden2 := '1';
end if;
if (v.nfence or v.nspec or v.busy or v.flush) = '1' then
v.wren := '0';
v.wden1 := '0';
v.wden2 := '0';
v.rden1 := '0';
v.rden2 := '0';
end if;
fetchram_i.wren <= v.wren;
fetchram_i.waddr <= v.waddr;
fetchram_i.wdata <= v.wdata;
fetchram_i.raddr1 <= v.raddr1;
fetchram_i.raddr2 <= v.raddr2;
v.rdata1 := fetchram_o.rdata1;
v.rdata2 := fetchram_o.rdata2;
if v.wden1 = '1' then
v.rden1 := v.wden1;
v.rdata1 := v.wdata;
end if;
if v.wden2 = '1' then
v.rden2 := v.wden2;
v.rdata2 := v.wdata;
end if;
if v.pc(2 downto 1) = "00" then
if v.rden1 = '1' then
v.instr := v.rdata1(31 downto 0);
else
v.stall := '1';
end if;
elsif v.pc(2 downto 1) = "01" then
if v.rden1 = '1' then
v.instr := v.rdata1(47 downto 16);
else
v.stall := '1';
end if;
elsif v.pc(2 downto 1) = "10" then
if v.rden1 = '1' then
v.instr := v.rdata1(63 downto 32);
else
v.stall := '1';
end if;
elsif v.pc(2 downto 1) = "11" then
if v.rden1 = '1' then
if v.rdata1(49 downto 48) = "11" then
if v.rden2 = '1' then
v.instr := v.rdata2(15 downto 0) & v.rdata1(63 downto 48);
else
v.stall := '1';
end if;
else
v.instr := X"0000" & v.rdata1(63 downto 48);
end if;
else
v.stall := '1';
end if;
end if;
if v.valid = '1' then
if v.stall = '0' then
if v.pc(2 downto 1) = "10" then
if v.instr(1 downto 0) = "11" then
v.incr := '1';
end if;
elsif v.pc(2 downto 1) = "11" then
v.incr := '1';
end if;
end if;
end if;
if v.ready = '1' then
if v.wren = '1' then
if v.waddr = 2**fetchbuffer_depth-1 then
v.oflow := '1';
v.waddr := 0;
else
v.waddr := v.waddr + 1;
end if;
v.fpc := std_logic_vector(unsigned(v.fpc) + 8);
end if;
end if;
if v.valid = '1' then
if v.incr = '1' then
if v.raddr1 = 2**fetchbuffer_depth-1 then
v.oflow := '0';
v.raddr1 := 0;
else
v.raddr1 := v.raddr1 + 1;
end if;
if v.raddr2 = 2**fetchbuffer_depth-1 then
v.raddr2 := 0;
else
v.raddr2 := v.raddr2 + 1;
end if;
end if;
end if;
if v.valid = '1' then
if v.spec = '1' then
v.nfpc := v.npc(63 downto 3) & "000";
v.nspec := '1';
v.spec := '0';
v.oflow := '0';
v.waddr := 0;
v.raddr1 := 0;
v.raddr2 := 1;
elsif v.fence = '1' then
v.nfpc := v.npc(63 downto 3) & "000";
v.nfence := '1';
v.fence := '0';
v.oflow := '0';
v.waddr := 0;
v.raddr1 := 0;
v.raddr2 := 1;
end if;
end if;
if v.ready = '1' then
if v.valid = '1' then
if v.nspec = '1' or v.nfence = '1' then
v.fpc := v.nfpc;
v.spec := v.nspec;
v.fence := v.nfence;
v.nspec := '0';
v.nfence := '0';
end if;
end if;
end if;
fetchctrl_o.instr <= v.instr;
fetchctrl_o.stall <= v.stall;
fetchctrl_o.flush <= v.flush;
imem_i.mem_valid <= not(v.clear);
imem_i.mem_instr <= '1';
imem_i.mem_spec <= v.spec;
imem_i.mem_invalid <= v.fence;
imem_i.mem_addr <= v.fpc;
imem_i.mem_wdata <= (others => '0');
imem_i.mem_wstrb <= (others => '0');
rin <= v;
end process;
process(clock)
begin
if rising_edge(clock) then
if reset = reset_active then
r <= init_reg;
else
r <= rin;
end if;
end if;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:57:44 09/16/2008
-- Design Name:
-- Module Name: functie_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity functie_tb is
end functie_tb;
architecture BENCH of functie_tb is
signal w : Std_logic;
signal x : Std_logic;
signal y : Std_logic;
signal z : Std_logic;
signal f : Std_logic;
begin
process
begin
w <= '0'; x <= '0'; y <= '0'; z <= '0';wait for 20 NS;
w <= '0'; x <= '0'; y <= '0'; z <= '1';wait for 20 NS;
w <= '0'; x <= '0'; y <= '1'; z <= '0';wait for 20 NS;
w <= '0'; x <= '0'; y <= '1'; z <= '1';wait for 20 NS;
w <= '0'; x <= '1'; y <= '0'; z <= '0';wait for 20 NS;
w <= '0'; x <= '1'; y <= '0'; z <= '1';wait for 20 NS;
w <= '0'; x <= '1'; y <= '1'; z <= '0';wait for 20 NS;
w <= '0'; x <= '1'; y <= '1'; z <= '1';wait for 20 NS;
w <= '1'; x <= '0'; y <= '0'; z <= '0';wait for 20 NS;
w <= '1'; x <= '0'; y <= '0'; z <= '1';wait for 20 NS;
w <= '1'; x <= '0'; y <= '1'; z <= '0';wait for 20 NS;
w <= '1'; x <= '0'; y <= '1'; z <= '1';wait for 20 NS;
w <= '1'; x <= '1'; y <= '0'; z <= '0';wait for 20 NS;
w <= '1'; x <= '1'; y <= '0'; z <= '1';wait for 20 NS;
w <= '1'; x <= '1'; y <= '1'; z <= '0';wait for 20 NS;
w <= '1'; x <= '1'; y <= '1'; z <= '1';wait for 20 NS;
wait;
end process;
M: entity work.functie(dataflow)
port map(
w => w,
x => x,
y => y,
z => z,
f => f
);
end architecture BENCH;
|
<gh_stars>10-100
-- signextender whichs preserves the msb
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SignExtender IS
PORT (
se_in : IN STD_logic_vector(15 DOWNTO 0);
se_out : OUT STD_logic_vector(31 DOWNTO 0)
);
END SignExtender;
ARCHITECTURE Behavioral OF SignExtender IS
BEGIN
-- concat hex 0000 with se_in if msb is 0 else ...
se_out <= x"0000" & se_in WHEN se_in(15) = '0'
ELSE
x"FFFF" & se_in;
END Behavioral;
|
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Fletcher streams library for use of the pipelined barrel shifter
use work.Stream_pkg.all;
-- The ShifterRecombiner can shift and recombine its input words with an arbitrary amount of bits. For this it uses the PipelineBarrelShifter from the Fletcher streams library.
-- To be used when unaligned data crosses bus word boundaries as seen in this example:
-- INPUT -> OUTPUT
-- ----------------------------------------- -> -----------------------------------------
-- - X | bw1 - -> - bw1 -
-- ----------------------------------------- -> -----------------------------------------
-- ----------------------------------------- -> -----------------------------------------
-- - bw1 | bw2 - -> - bw2 -
-- ----------------------------------------- -> -----------------------------------------
-- ----------------------------------------- -> -----------------------------------------
-- - bw2 | bw3 - -> - bw3 -
-- ----------------------------------------- -> -----------------------------------------
-- ----------------------------------------- ->
-- - bw3 | X - ->
-- ----------------------------------------- ->
entity ShifterRecombiner is
generic (
-- Bus data width
BUS_DATA_WIDTH : natural := 512;
-- Width of shifting amount input (alignment)
SHIFT_WIDTH : natural := 6;
-- Width of elements to shift. (A byte for the ptoa use case).
ELEMENT_WIDTH : natural := 8;
-- Number of stages in the barrel shifter pipeline
NUM_SHIFT_STAGES : natural := 6
);
port (
-- Rising-edge sensitive clock.
clk : in std_logic;
-- Active-high synchronous reset.
reset : in std_logic;
clear : in std_logic;
-- Stream data in
in_valid : in std_logic;
in_ready : out std_logic;
in_data : in std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
-- Stream data out
out_valid : out std_logic;
out_ready : in std_logic;
out_data : out std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
alignment : in std_logic_vector(SHIFT_WIDTH-1 downto 0)
);
end ShifterRecombiner;
architecture behv of ShifterRecombiner is
signal reset_pipeline : std_logic;
signal s_pipe_delete : std_logic;
signal s_pipe_valid : std_logic_vector(0 to NUM_SHIFT_STAGES);
signal s_pipe_input : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
signal s_pipe_output : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
signal shifter_out_valid : std_logic;
signal shifter_out_data : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
signal recombiner_r_in_ready : std_logic;
signal recombiner_r_out_data : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
signal recombiner_r_out_valid : std_logic;
-- Signal copy of out_valid output
signal s_out_valid : std_logic;
begin
-- Pipeline can be flushed/cleared by both the hardware reset or the clear signal
reset_pipeline <= reset or clear;
-- Unnecessary signal
s_pipe_delete <= '0';
-- Data presented at the output is a combination of the shifter output and the recombiner register.
-- In other words: a new (aligned) bus word is created from parts of two input bus words.
-- out_data <= recombiner_r_out_data when alignment = std_logic_vector(to_unsigned(0, SHIFT_WIDTH)) else
-- recombiner_r_out_data(BUS_DATA_WIDTH-1 downto ELEMENT_WIDTH*to_integer(unsigned(alignment))) & shifter_out_data(ELEMENT_WIDTH*to_integer(unsigned(alignment))-1 downto 0);
out_data_p: process(alignment, recombiner_r_out_data, shifter_out_data)
begin
out_data <= recombiner_r_out_data;
for i in 1 to BUS_DATA_WIDTH/8-1 loop
if i = to_integer(unsigned(alignment)) then
out_data <= recombiner_r_out_data(BUS_DATA_WIDTH-1 downto ELEMENT_WIDTH*i) & shifter_out_data(ELEMENT_WIDTH*i-1 downto 0);
end if;
end loop;
end process;
shifter_ctrl_inst: StreamPipelineControl
generic map (
IN_DATA_WIDTH => BUS_DATA_WIDTH,
OUT_DATA_WIDTH => BUS_DATA_WIDTH,
NUM_PIPE_REGS => NUM_SHIFT_STAGES,
INPUT_SLICE => false, -- Todo: Maybe supposed to be true?
RAM_CONFIG => ""
)
port map (
clk => clk,
reset => reset_pipeline,
in_valid => in_valid,
in_ready => in_ready,
in_data => in_data,
out_valid => shifter_out_valid,
out_ready => recombiner_r_in_ready,
out_data => shifter_out_data,
pipe_delete => s_pipe_delete,
pipe_valid => s_pipe_valid,
pipe_input => s_pipe_input,
pipe_output => s_pipe_output
);
shifter_barrel_inst: StreamPipelineBarrel
generic map (
ELEMENT_WIDTH => ELEMENT_WIDTH,
ELEMENT_COUNT => BUS_DATA_WIDTH/ELEMENT_WIDTH,
AMOUNT_WIDTH => SHIFT_WIDTH,
DIRECTION => "left",
OPERATION => "rotate",
NUM_STAGES => NUM_SHIFT_STAGES
)
port map (
clk => clk,
reset => reset_pipeline,
in_data => s_pipe_input,
in_amount => alignment,
out_data => s_pipe_output
);
-- Recombiner_r is ready to receive data when downstream can consume its stored data or when no stored data is present (recombiner_r_out_valid = '0')
recombiner_r_in_ready <= out_ready or not recombiner_r_out_valid;
-- The output of the entire entity is only valid when both the shifter and the recombiner register have valid data. Unless alignment is 0, in which case no recombining is needed.
s_out_valid <= recombiner_r_out_valid when alignment = std_logic_vector(to_unsigned(0, SHIFT_WIDTH)) else
recombiner_r_out_valid and shifter_out_valid;
out_valid <= s_out_valid;
reg_p: process (clk)
begin
if rising_edge(clk) then
-- Both the shifter and the recombiner register have valid data on their output, and downstream is ready to consume
if s_out_valid = '1' and out_ready = '1' then
recombiner_r_out_valid <= '0';
end if;
-- Recombiner register can receive data
if recombiner_r_in_ready = '1' and shifter_out_valid = '1' then
recombiner_r_out_data <= shifter_out_data;
recombiner_r_out_valid <= '1';
end if;
if reset_pipeline = '1' then
recombiner_r_out_data <= (others => '0');
recombiner_r_out_valid <= '0';
end if;
end if;
end process;
end architecture;
|
<reponame>crawben20/fpga-serial-mem-tester-1<gh_stars>1-10
--------------------------------------------------------------------------------
-- MIT License
--
-- Copyright (c) 2020 <NAME>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--------------------------------------------------------------------------------
-- \file multi_input_debounce.vhdl
--
-- \brief A 4-button multiple input debouncer and filter allowing only one
-- button to be depressed at a time.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--------------------------------------------------------------------------------
entity multi_input_debounce is
generic(
FCLK : natural := 20_000_000 -- system clock frequency in Hz
);
port(
i_clk_mhz : in std_logic; -- system clock
i_rst_mhz : in std_logic; -- synchronized reset
ei_buttons : in std_logic_vector(3 downto 0); -- the raw buttons input
o_btns_deb : out std_logic_vector(3 downto 0) -- logic level switch value indicator
);
end entity multi_input_debounce;
--------------------------------------------------------------------------------
architecture moore_fsm of multi_input_debounce is
-- FSM State enumeration
type t_minp_state is (ST_A, ST_B, ST_C, ST_D);
-- FSM State register
signal s_minp_pr_state : t_minp_state;
signal s_minp_nx_state : t_minp_state;
-- Xilinx FSM Encoding attribute:
attribute fsm_encoding : string;
attribute fsm_encoding of s_minp_pr_state : signal is "auto";
attribute fsm_safe_state : string;
attribute fsm_safe_state of s_minp_pr_state : signal is "default_state";
--Timer-related declarations:
constant c_T : natural := FCLK * 1 / 1000; -- 1 millisecond debounce
constant c_tmax : natural := c_T-1;
signal s_t : natural range 0 to c_tmax;
signal si_buttons_meta : std_logic_vector(3 downto 0);
signal si_buttons_sync : std_logic_vector(3 downto 0);
signal si_buttons_prev : std_logic_vector(3 downto 0);
signal si_buttons_store : std_logic_vector(3 downto 0);
signal so_btns_deb : std_logic_vector(3 downto 0);
begin
--FSM input signals synchronized to prevent meta-stability
p_sync_buttons_input : process(i_clk_mhz)
begin
if rising_edge(i_clk_mhz) then
si_buttons_sync <= si_buttons_meta;
si_buttons_meta <= ei_buttons;
end if;
end process p_sync_buttons_input;
--FSM Timer (Strategy #1)
p_fsm_timer1 : process(i_clk_mhz, i_rst_mhz)
begin
if rising_edge(i_clk_mhz) then
if (i_rst_mhz = '1') then
s_t <= 0;
else
if (s_minp_pr_state /= s_minp_nx_state) then
s_t <= 0;
elsif (s_t /= c_tmax) then
s_t <= s_t + 1;
end if;
end if;
end if;
end process p_fsm_timer1;
-- FSM state register:
p_fsm_state : process(i_clk_mhz)
begin
if rising_edge(i_clk_mhz) then
if (i_rst_mhz = '1') then
s_minp_pr_state <= ST_A;
si_buttons_prev <= "0000";
si_buttons_store <= "0000";
else
if ((s_minp_nx_state = ST_C) and
(s_minp_pr_state = ST_B)) then
si_buttons_store <= si_buttons_prev;
end if;
si_buttons_prev <= si_buttons_sync;
s_minp_pr_state <= s_minp_nx_state;
end if;
end if;
end process p_fsm_state;
-- FSM combinational logic:
p_fsm_comb : process(s_minp_pr_state, s_t, si_buttons_sync, si_buttons_prev,
si_buttons_store)
begin
case (s_minp_pr_state) is
when ST_B =>
so_btns_deb <= "0000";
if (si_buttons_sync /= si_buttons_prev) then
s_minp_nx_state <= ST_A;
elsif (s_t = c_T - 2) then
s_minp_nx_state <= ST_C;
else
s_minp_nx_state <= ST_B;
end if;
when ST_C =>
so_btns_deb <= si_buttons_store;
if (si_buttons_sync /= si_buttons_store) then
s_minp_nx_state <= ST_D;
else
s_minp_nx_state <= ST_C;
end if;
when ST_D =>
so_btns_deb <= si_buttons_store;
if (si_buttons_sync = si_buttons_store) then
s_minp_nx_state <= ST_C;
elsif (s_t = c_T - 3) then
s_minp_nx_state <= ST_A;
else
s_minp_nx_state <= ST_D;
end if;
when others => -- ST_A
so_btns_deb <= "0000";
if ((si_buttons_sync = "0000") or
(si_buttons_sync = "1000") or
(si_buttons_sync = "0100") or
(si_buttons_sync = "0010") or
(si_buttons_sync = "0001")) then
s_minp_nx_state <= ST_B;
else
s_minp_nx_state <= ST_A;
end if;
end case;
end process p_fsm_comb;
-- Direct unregistered output with no output registers
o_btns_deb <= so_btns_deb;
end architecture moore_fsm;
--------------------------------------------------------------------------------
|
<gh_stars>1-10
--------------------------------------------------------------------------------
-- Copyright (C) 2018 <NAME>
-- SPDX-License-Identifier: MIT
--------------------------------------------------------------------------------
-- Compliant: IEEE Std 1076-1993
-- Target: independent
--------------------------------------------------------------------------------
-- Description:
-- Initializes the ROM memory from the linear_vector.txt file, which matches
-- pattern [address]=address and simulation will verify it with standard
-- sequential reading memory addresses. The simulation uses nibbles as data
-- width (4 bits).
--------------------------------------------------------------------------------
-- Notes:
-- 1. The file path defined by g_MEM_IMG_FILENAME is relative to the file
-- where the rom module is defined in.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.string_pkg.all;
use work.rom;
entity rom_tb is
end entity rom_tb;
architecture behavioral of rom_tb is
-- uut generics
constant g_ADDR_WIDTH : positive := 4;
constant g_DATA_WIDTH : positive := 4;
constant g_MEM_IMG_FILENAME : string := "../data/mem_img/linear_4_4.txt";
-- uut ports
signal i_clk : std_ulogic := '0';
signal i_re : std_ulogic := '0';
signal i_addr : std_ulogic_vector(g_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal o_data : std_ulogic_vector(g_DATA_WIDTH - 1 downto 0);
-- clock period definition
constant c_CLK_PERIOD : time := 10 ns;
-- simulation completed flag to stop the clk_gen process
shared variable v_verif_done : boolean := false;
begin
-- instantiate the unit under test (uut)
uut : entity work.rom(rtl)
generic map (
g_ADDR_WIDTH => g_ADDR_WIDTH,
g_DATA_WIDTH => g_DATA_WIDTH,
g_MEM_IMG_FILENAME => g_MEM_IMG_FILENAME
)
port map (
i_clk => i_clk,
i_re => i_re,
i_addr => i_addr,
o_data => o_data
);
clk_gen : process is
begin
i_clk <= '0';
wait for c_CLK_PERIOD / 2;
i_clk <= '1';
wait for c_CLK_PERIOD / 2;
if (v_verif_done) then
wait;
end if;
end process clk_gen;
stim_and_verif : process is
begin
i_re <= '1';
-- read every unique address value, one value per each c_CLK_PERIOD from 0 address
for i in 0 to integer((2 ** g_ADDR_WIDTH) - 1) loop
i_addr <= std_ulogic_vector(to_unsigned(i, i_addr'length)); -- read memory
wait for c_CLK_PERIOD; -- wait for i_clk rising edge to read the desired data
-- asserting to verify the ROM module function
assert (o_data = std_ulogic_vector(to_unsigned(i, o_data'length)))
report "Expected the data from the " &
integer'image(to_integer(unsigned(i_addr))) & " address to be equal to """ &
to_string(std_ulogic_vector(to_unsigned(i, o_data'length))) & """, what matches " &
"the [address]=address pattern!"
severity error;
end loop;
v_verif_done := true;
wait;
end process stim_and_verif;
end architecture behavioral;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:32:39 12/30/2009
-- Design Name:
-- Module Name: /media/My Passport/work/PhD/myHDL_tests/my_conversion/Plex_test/new_code_2/ISE_func_comps/simple_filt_tb.vhd
-- Project Name: ISE_func_comps
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: simple_filt
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY simple_filt_tb IS
END simple_filt_tb;
ARCHITECTURE behavior OF simple_filt_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT simple_filt
PORT(
clk : IN std_logic;
rst : IN std_logic;
filt_in : IN std_logic_vector(8 downto 0);
filt_out : OUT std_logic_vector(18 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal filt_in : std_logic_vector(8 downto 0) := (others => '0');
--Outputs
signal filt_out : std_logic_vector(18 downto 0);
-- Clock period definitions
constant clk_period : time := 100ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: simple_filt PORT MAP (
clk => clk,
rst => rst,
filt_in => filt_in,
filt_out => filt_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100ms.
wait for 50ns;
wait for clk_period*0;
-- insert stimulus here
rst <= '1';
wait for 50ns;
rst <= '0';
wait for 50ns;
filt_in <= conv_std_logic_vector(10, 9);
wait for 100ns;
filt_in <= conv_std_logic_vector(8, 9);
wait for 100ns;
filt_in <= conv_std_logic_vector(0, 9);
wait for 100ns;
-- insert stimulus here
wait;
end process;
END;
|
<filename>ch11/ex_11.8/src/pb_sequence_detector.vhd<gh_stars>0
----------------------------------------------------------------------------------
-- Company: None
-- Engineer: <NAME>
--
-- Create Date: 18:17:00 05/04/2020 (mm/dd/yyyy)
-- Design Name: Abacus
-- Module Name: top - Behavioral
-- Project Name: < >
-- Target Devices: Basys 3
-- Tool versions: Vivado 2019.1
-- Description:
--
-- Dependencies:
--
--
-- Revision History:
-- 05/04/2020 v0.01 File created
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pb_sequence_detector is
generic (
a : std_logic_vector(2 downto 0) := "011"; --"011","101",or"110"
b : std_logic_vector(2 downto 0) := "101"; --"011","101",or"110"
c : std_logic_vector(2 downto 0) := "110"; --"011","101",or"110"
none: std_logic_vector(2 downto 0) := "111"; --always "111"
T : integer := 150_000_000 --delay=3s with 50 MHz clock
);
port (
-- input ports
clk : in std_logic;
rst : in std_logic;
pb1 : in std_logic;
pb2 : in std_logic;
pb3 : in std_logic;
-- output ports
led_idle : out std_logic;
led_win : out std_logic
);
end pb_sequence_detector;
architecture fsm of pb_sequence_detector is
type state is (idle, wait1, key1, wait2, key2, wait3, key3);
signal pr_state : state;
signal nx_state : state;
attribute enum_encoding: string;
attribute enum_encoding of state: type is "sequential";
signal x : std_logic_vector(2 downto 0);
signal timer : integer range 0 to T;
begin
----construction of x:----------------
x <= (pb1 & pb2 & pb3);
----lower section of fsm:-------------
process (clk, rst)
variable count: integer range 0 to T;
begin
if (rst = '1') then
pr_state <= idle;
count := 0;
elsif (clk'event and clk = '1') then
count := count + 1;
if (count >= timer) then
pr_state <= nx_state;
count := 0;
end if;
end if;
end process;
----upper section of fsm:------------
process (pr_state, x)
begin
case pr_state is
when idle =>
led_idle <= '1';
led_win <= '0';
timer <= 1;
if (x = a) then
nx_state <= wait1;
else
nx_state <= idle;
end if;
when wait1 =>
led_idle <= '0';
led_win <= '0';
if (x = none) then
timer <= 1;
nx_state <= key1;
else
timer <= T;
nx_state <= idle;
end if;
when key1 =>
led_idle <= '0';
led_win <= '0';
if (x = b) then --x=b test must be before x=a test
timer <= 1;
nx_state <= wait2;
elsif (x = a) then
timer <= 1;
nx_state <= wait1;
elsif (x /= none) then
timer <= 1;
nx_state <= idle;
else
timer <= T;
nx_state <= idle;
end if;
when wait2 =>
led_idle <= '0';
led_win <= '0';
if (x = none) then
timer <= 1;
nx_state <= key2;
else
timer <= T;
nx_state <= idle;
end if;
when key2 =>
led_idle <= '0';
led_win <= '0';
if (x = c) then --x=c test must be before x=a test
timer <= 1;
nx_state <= wait3;
elsif (x = a) then
timer <= 1;
nx_state <= wait1;
elsif (x /= none) then
timer <= 1;
nx_state <= idle;
else
timer <= T;
nx_state <= idle;
end if;
when wait3 =>
led_idle <= '0';
led_win <= '1';
if (x = none) then
timer <= 1;
nx_state <= key3;
else
timer <= T;
nx_state <= idle;
end if;
when key3 =>
led_idle <= '0';
led_win <= '1';
timer <= T;
nx_state <= idle;
end case;
end process;
end fsm;
|
<gh_stars>1-10
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 18.0 (Release Build #614)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from acoustic_delay_buffer_adb_delay_buffer
-- VHDL created on Fri Apr 05 13:33:36 2019
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY altera_lnsim;
USE altera_lnsim.altera_lnsim_components.altera_syncram;
LIBRARY lpm;
USE lpm.lpm_components.all;
library twentynm;
use twentynm.twentynm_components.twentynm_fp_mac;
entity acoustic_delay_buffer_adb_delay_buffer is
port (
in_1_valid_in : in std_logic_vector(0 downto 0); -- ufix1
in_2_channel_in : in std_logic_vector(7 downto 0); -- ufix8
in_3_din : in std_logic_vector(31 downto 0); -- sfix32_en28
out_1_valid_out : out std_logic_vector(0 downto 0); -- ufix1
out_2_channel_out : out std_logic_vector(7 downto 0); -- ufix8
out_3_dout : out std_logic_vector(31 downto 0); -- sfix32_en28
in_4_delay_compensation : in std_logic_vector(11 downto 0); -- ufix12
clk : in std_logic;
areset : in std_logic
);
end acoustic_delay_buffer_adb_delay_buffer;
architecture normal of acoustic_delay_buffer_adb_delay_buffer is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_PostCast_primWireOut_sel_x_b : STD_LOGIC_VECTOR (7 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Add_x_a : STD_LOGIC_VECTOR (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Add_x_b : STD_LOGIC_VECTOR (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Add_x_o : STD_LOGIC_VECTOR (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Add_x_q : STD_LOGIC_VECTOR (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_And_x_q : STD_LOGIC_VECTOR (0 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_CmpEQ1_x_q : STD_LOGIC_VECTOR (0 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Const1_x_q : STD_LOGIC_VECTOR (7 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Const3_x_q : STD_LOGIC_VECTOR (4 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_cnt : UNSIGNED (4 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_dec : UNSIGNED (4 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_dn : UNSIGNED (5 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_en : STD_LOGIC_VECTOR (0 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_i : STD_LOGIC_VECTOR (4 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_inc : UNSIGNED (4 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_l : STD_LOGIC_VECTOR (4 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_ld : STD_LOGIC_VECTOR (0 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_q : STD_LOGIC_VECTOR (4 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_s : STD_LOGIC_VECTOR (4 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_up : UNSIGNED (4 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Select1_x_q : STD_LOGIC_VECTOR (0 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Sub_x_a : STD_LOGIC_VECTOR (7 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Sub_x_b : STD_LOGIC_VECTOR (7 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Sub_x_o : STD_LOGIC_VECTOR (7 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Sub_x_q : STD_LOGIC_VECTOR (7 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_reset0 : std_logic;
signal acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_ia : STD_LOGIC_VECTOR (31 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_aa : STD_LOGIC_VECTOR (11 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_ab : STD_LOGIC_VECTOR (11 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_iq : STD_LOGIC_VECTOR (31 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_q : STD_LOGIC_VECTOR (31 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_Const2_x_q : STD_LOGIC_VECTOR (11 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_Const4_x_q : STD_LOGIC_VECTOR (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_cnt : UNSIGNED (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_dec : UNSIGNED (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_dn : UNSIGNED (13 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_en : STD_LOGIC_VECTOR (0 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_i : STD_LOGIC_VECTOR (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_inc : UNSIGNED (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_l : STD_LOGIC_VECTOR (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_ld : STD_LOGIC_VECTOR (0 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_q : STD_LOGIC_VECTOR (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_s : STD_LOGIC_VECTOR (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_up : UNSIGNED (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_cnt : UNSIGNED (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_dec : UNSIGNED (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_dn : UNSIGNED (13 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_en : STD_LOGIC_VECTOR (0 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_i : STD_LOGIC_VECTOR (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_inc : UNSIGNED (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_l : STD_LOGIC_VECTOR (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_ld : STD_LOGIC_VECTOR (0 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_q : STD_LOGIC_VECTOR (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_s : STD_LOGIC_VECTOR (12 downto 0);
signal acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_up : UNSIGNED (12 downto 0);
signal CmpNE_q : STD_LOGIC_VECTOR (0 downto 0);
signal Or_rsrvd_fix_qi : STD_LOGIC_VECTOR (0 downto 0);
signal Or_rsrvd_fix_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist0_GPIn_in_4_delay_compensation_1_q : STD_LOGIC_VECTOR (11 downto 0);
signal redist1_CmpNE_q_1_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist2_CmpNE_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist3_ChannelIn_in_1_valid_in_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist4_ChannelIn_in_2_channel_in_2_q : STD_LOGIC_VECTOR (7 downto 0);
signal redist6_acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_q_2_q : STD_LOGIC_VECTOR (12 downto 0);
signal redist7_acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_q_1_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist8_acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_q_3_q : STD_LOGIC_VECTOR (4 downto 0);
signal redist9_acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_And_x_q_4_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist5_ChannelIn_in_3_din_3_mem_reset0 : std_logic;
signal redist5_ChannelIn_in_3_din_3_mem_ia : STD_LOGIC_VECTOR (31 downto 0);
signal redist5_ChannelIn_in_3_din_3_mem_aa : STD_LOGIC_VECTOR (0 downto 0);
signal redist5_ChannelIn_in_3_din_3_mem_ab : STD_LOGIC_VECTOR (0 downto 0);
signal redist5_ChannelIn_in_3_din_3_mem_iq : STD_LOGIC_VECTOR (31 downto 0);
signal redist5_ChannelIn_in_3_din_3_mem_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist5_ChannelIn_in_3_din_3_rdcnt_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist5_ChannelIn_in_3_din_3_rdcnt_i : UNSIGNED (0 downto 0);
attribute preserve : boolean;
attribute preserve of redist5_ChannelIn_in_3_din_3_rdcnt_i : signal is true;
signal redist5_ChannelIn_in_3_din_3_wraddr_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist5_ChannelIn_in_3_din_3_cmpReg_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist5_ChannelIn_in_3_din_3_notEnable_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist5_ChannelIn_in_3_din_3_nor_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist5_ChannelIn_in_3_din_3_sticky_ena_q : STD_LOGIC_VECTOR (0 downto 0);
attribute preserve_syn_only : boolean;
attribute preserve_syn_only of redist5_ChannelIn_in_3_din_3_sticky_ena_q : signal is true;
signal redist5_ChannelIn_in_3_din_3_enaAnd_q : STD_LOGIC_VECTOR (0 downto 0);
begin
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_Const4_x(CONSTANT,26)
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_Const4_x_q <= "1000000000000";
-- acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_Const2_x(CONSTANT,24)
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_Const2_x_q <= "111111111111";
-- redist0_GPIn_in_4_delay_compensation_1(DELAY,47)
redist0_GPIn_in_4_delay_compensation_1 : dspba_delay
GENERIC MAP ( width => 12, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => in_4_delay_compensation, xout => redist0_GPIn_in_4_delay_compensation_1_q, clk => clk, aclr => areset );
-- CmpNE(LOGICAL,40)@0
CmpNE_q <= "1" WHEN redist0_GPIn_in_4_delay_compensation_1_q /= in_4_delay_compensation ELSE "0";
-- redist1_CmpNE_q_1(DELAY,48)
redist1_CmpNE_q_1 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => CmpNE_q, xout => redist1_CmpNE_q_1_q, clk => clk, aclr => areset );
-- redist2_CmpNE_q_2(DELAY,49)
redist2_CmpNE_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => redist1_CmpNE_q_1_q, xout => redist2_CmpNE_q_2_q, clk => clk, aclr => areset );
-- redist3_ChannelIn_in_1_valid_in_2(DELAY,50)
redist3_ChannelIn_in_1_valid_in_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => in_1_valid_in, xout => redist3_ChannelIn_in_1_valid_in_2_q, clk => clk, aclr => areset );
-- acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Add_x(ADD,5)@1
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Add_x_a <= STD_LOGIC_VECTOR("000000000000" & VCC_q);
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Add_x_b <= STD_LOGIC_VECTOR("0" & redist0_GPIn_in_4_delay_compensation_1_q);
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Add_x_o <= STD_LOGIC_VECTOR(UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Add_x_a) + UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Add_x_b));
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Add_x_q <= acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Add_x_o(12 downto 0);
-- acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x(LOADABLECOUNTER,34)@0 + 1
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_en <= in_1_valid_in;
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_ld <= CmpNE_q;
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_i <= STD_LOGIC_VECTOR("000000000000" & GND_q);
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_s <= STD_LOGIC_VECTOR("000000000000" & VCC_q);
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_l <= acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_Const4_x_q;
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_up <= acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_cnt + acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_inc;
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_dn <= UNSIGNED(resize(unsigned(acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_cnt(12 downto 0)), 14)) - UNSIGNED(resize(unsigned(acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_dec(12 downto 0)), 14));
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_cnt <= "0111111111111";
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_inc <= "0000000000001";
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_dec <= "0111111111111";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_ld = "1") THEN
IF (FALSE and acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_s(12) = '1') THEN
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_inc <= UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_l) + UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_s);
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_dec <= UNSIGNED(TO_UNSIGNED(0, 13)) - UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_s);
ELSE
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_inc <= UNSIGNED(TO_UNSIGNED(0, 13)) + UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_s);
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_dec <= UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_l) - UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_s);
END IF;
END IF;
IF (acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_ld = "1" or acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_en = "1") THEN
IF (acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_ld = "1") THEN
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_cnt <= UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_i);
ELSE
IF (acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_dn(13) = '1') THEN
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_cnt <= acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_up;
ELSE
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_cnt <= acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_dn(12 downto 0);
END IF;
END IF;
END IF;
END IF;
END PROCESS;
acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_q <= STD_LOGIC_VECTOR(acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_cnt);
-- acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_CmpEQ1_x(LOGICAL,7)@1
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_CmpEQ1_x_q <= "1" WHEN acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_q = acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Add_x_q ELSE "0";
-- GND(CONSTANT,0)
GND_q <= "0";
-- acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Select1_x(SELECTOR,16)@1 + 1
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Select1_x_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Select1_x_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Select1_x_q <= acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Select1_x_q;
IF (acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_CmpEQ1_x_q = "1") THEN
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Select1_x_q <= VCC_q;
END IF;
IF (redist1_CmpNE_q_1_q = "1") THEN
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Select1_x_q <= GND_q;
END IF;
END IF;
END PROCESS;
-- acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_And_x(LOGICAL,6)@2
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_And_x_q <= acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Select1_x_q and redist3_ChannelIn_in_1_valid_in_2_q;
-- acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x(LOADABLECOUNTER,28)@2 + 1
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_en <= acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_And_x_q;
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_ld <= redist2_CmpNE_q_2_q;
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_i <= STD_LOGIC_VECTOR("0" & acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_Const2_x_q);
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_s <= STD_LOGIC_VECTOR("000000000000" & VCC_q);
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_l <= acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_Const4_x_q;
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_up <= acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_cnt + acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_inc;
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_dn <= UNSIGNED(resize(unsigned(acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_cnt(12 downto 0)), 14)) - UNSIGNED(resize(unsigned(acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_dec(12 downto 0)), 14));
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_cnt <= "0111111111111";
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_inc <= "0000000000001";
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_dec <= "0111111111111";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_ld = "1") THEN
IF (FALSE and acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_s(12) = '1') THEN
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_inc <= UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_l) + UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_s);
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_dec <= UNSIGNED(TO_UNSIGNED(0, 13)) - UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_s);
ELSE
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_inc <= UNSIGNED(TO_UNSIGNED(0, 13)) + UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_s);
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_dec <= UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_l) - UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_s);
END IF;
END IF;
IF (acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_ld = "1" or acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_en = "1") THEN
IF (acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_ld = "1") THEN
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_cnt <= UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_i);
ELSE
IF (acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_dn(13) = '1') THEN
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_cnt <= acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_up;
ELSE
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_cnt <= acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_dn(12 downto 0);
END IF;
END IF;
END IF;
END IF;
END PROCESS;
acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_q <= STD_LOGIC_VECTOR(acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_cnt);
-- redist5_ChannelIn_in_3_din_3_notEnable(LOGICAL,61)
redist5_ChannelIn_in_3_din_3_notEnable_q <= STD_LOGIC_VECTOR(not (VCC_q));
-- redist5_ChannelIn_in_3_din_3_nor(LOGICAL,62)
redist5_ChannelIn_in_3_din_3_nor_q <= not (redist5_ChannelIn_in_3_din_3_notEnable_q or redist5_ChannelIn_in_3_din_3_sticky_ena_q);
-- redist5_ChannelIn_in_3_din_3_cmpReg(REG,60)
redist5_ChannelIn_in_3_din_3_cmpReg_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
redist5_ChannelIn_in_3_din_3_cmpReg_q <= "0";
ELSIF (clk'EVENT AND clk = '1') THEN
redist5_ChannelIn_in_3_din_3_cmpReg_q <= STD_LOGIC_VECTOR(VCC_q);
END IF;
END PROCESS;
-- redist5_ChannelIn_in_3_din_3_sticky_ena(REG,63)
redist5_ChannelIn_in_3_din_3_sticky_ena_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
redist5_ChannelIn_in_3_din_3_sticky_ena_q <= "0";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (redist5_ChannelIn_in_3_din_3_nor_q = "1") THEN
redist5_ChannelIn_in_3_din_3_sticky_ena_q <= STD_LOGIC_VECTOR(redist5_ChannelIn_in_3_din_3_cmpReg_q);
END IF;
END IF;
END PROCESS;
-- redist5_ChannelIn_in_3_din_3_enaAnd(LOGICAL,64)
redist5_ChannelIn_in_3_din_3_enaAnd_q <= redist5_ChannelIn_in_3_din_3_sticky_ena_q and VCC_q;
-- redist5_ChannelIn_in_3_din_3_rdcnt(COUNTER,58)
-- low=0, high=1, step=1, init=0
redist5_ChannelIn_in_3_din_3_rdcnt_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
redist5_ChannelIn_in_3_din_3_rdcnt_i <= TO_UNSIGNED(0, 1);
ELSIF (clk'EVENT AND clk = '1') THEN
redist5_ChannelIn_in_3_din_3_rdcnt_i <= redist5_ChannelIn_in_3_din_3_rdcnt_i + 1;
END IF;
END PROCESS;
redist5_ChannelIn_in_3_din_3_rdcnt_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(redist5_ChannelIn_in_3_din_3_rdcnt_i, 1)));
-- redist5_ChannelIn_in_3_din_3_wraddr(REG,59)
redist5_ChannelIn_in_3_din_3_wraddr_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
redist5_ChannelIn_in_3_din_3_wraddr_q <= "1";
ELSIF (clk'EVENT AND clk = '1') THEN
redist5_ChannelIn_in_3_din_3_wraddr_q <= STD_LOGIC_VECTOR(redist5_ChannelIn_in_3_din_3_rdcnt_q);
END IF;
END PROCESS;
-- redist5_ChannelIn_in_3_din_3_mem(DUALMEM,57)
redist5_ChannelIn_in_3_din_3_mem_ia <= STD_LOGIC_VECTOR(in_3_din);
redist5_ChannelIn_in_3_din_3_mem_aa <= redist5_ChannelIn_in_3_din_3_wraddr_q;
redist5_ChannelIn_in_3_din_3_mem_ab <= redist5_ChannelIn_in_3_din_3_rdcnt_q;
redist5_ChannelIn_in_3_din_3_mem_reset0 <= areset;
redist5_ChannelIn_in_3_din_3_mem_dmem : altera_syncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altera_syncram",
width_byteena_a => 1,
address_reg_b => "CLOCK0",
indata_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "TRUE",
intended_device_family => "Arria 10"
)
PORT MAP (
clocken1 => redist5_ChannelIn_in_3_din_3_enaAnd_q(0),
clocken0 => VCC_q(0),
clock0 => clk,
aclr1 => redist5_ChannelIn_in_3_din_3_mem_reset0,
clock1 => clk,
address_a => redist5_ChannelIn_in_3_din_3_mem_aa,
data_a => redist5_ChannelIn_in_3_din_3_mem_ia,
wren_a => VCC_q(0),
address_b => redist5_ChannelIn_in_3_din_3_mem_ab,
q_b => redist5_ChannelIn_in_3_din_3_mem_iq
);
redist5_ChannelIn_in_3_din_3_mem_q <= redist5_ChannelIn_in_3_din_3_mem_iq(31 downto 0);
-- Or_rsrvd_fix(LOGICAL,42)@2 + 1
Or_rsrvd_fix_qi <= redist3_ChannelIn_in_1_valid_in_2_q or redist2_CmpNE_q_2_q;
Or_rsrvd_fix_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => Or_rsrvd_fix_qi, xout => Or_rsrvd_fix_q, clk => clk, aclr => areset );
-- redist6_acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_q_2(DELAY,53)
redist6_acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_q_2 : dspba_delay
GENERIC MAP ( width => 13, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_q, xout => redist6_acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_q_2_q, clk => clk, aclr => areset );
-- acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x(DUALMEM,18)@3 + 2
acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_ia <= STD_LOGIC_VECTOR(redist5_ChannelIn_in_3_din_3_mem_q);
acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_aa <= redist6_acoustic_delay_buffer_adb_delay_buffer_write_addr_counter_LoadableCounter_x_q_2_q(11 downto 0);
acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_ab <= acoustic_delay_buffer_adb_delay_buffer_read_addr_counter_LoadableCounter_x_q(11 downto 0);
acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_reset0 <= areset;
acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_dmem : altera_syncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 12,
numwords_a => 4096,
width_b => 32,
widthad_b => 12,
numwords_b => 4096,
lpm_type => "altera_syncram",
width_byteena_a => 1,
address_reg_b => "CLOCK0",
indata_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "D:/trevor/research/NIH_SBIR_R44_DC015443/Audio_Beamforming/hw/library/acoustic_delay_buffer/./rtl/acoustic_delay_buffer/acoustic_delay_buffer_adb_delay_buffer_acoustic_delay_buffer_adb_delay_buffer_ciA0Zbuffer_DualMem_x.hex",
init_file_layout => "PORT_B",
intended_device_family => "Arria 10"
)
PORT MAP (
clocken0 => '1',
aclr0 => acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_reset0,
clock0 => clk,
address_a => acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_aa,
data_a => acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_ia,
wren_a => Or_rsrvd_fix_q(0),
address_b => acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_ab,
q_b => acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_iq
);
acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_q <= acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_iq(31 downto 0);
-- redist7_acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_q_1(DELAY,54)
redist7_acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_q_1 : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_q, xout => redist7_acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_q_1_q, clk => clk, aclr => areset );
-- acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Const3_x(CONSTANT,11)
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Const3_x_q <= "10000";
-- acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Const1_x(CONSTANT,9)
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Const1_x_q <= "00000001";
-- redist4_ChannelIn_in_2_channel_in_2(DELAY,51)
redist4_ChannelIn_in_2_channel_in_2 : dspba_delay
GENERIC MAP ( width => 8, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => in_2_channel_in, xout => redist4_ChannelIn_in_2_channel_in_2_q, clk => clk, aclr => areset );
-- acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Sub_x(SUB,17)@2
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Sub_x_a <= redist4_ChannelIn_in_2_channel_in_2_q;
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Sub_x_b <= acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Const1_x_q;
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Sub_x_o <= STD_LOGIC_VECTOR(UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Sub_x_a) - UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Sub_x_b));
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Sub_x_q <= acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Sub_x_o(7 downto 0);
-- acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x(LOADABLECOUNTER,14)@2 + 1
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_en <= acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_And_x_q;
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_ld <= redist2_CmpNE_q_2_q;
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_i <= acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Sub_x_q(4 downto 0);
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_s <= STD_LOGIC_VECTOR("0000" & VCC_q);
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_l <= acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_Const3_x_q;
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_up <= acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_cnt + acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_inc;
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_dn <= UNSIGNED(resize(unsigned(acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_cnt(4 downto 0)), 6)) - UNSIGNED(resize(unsigned(acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_dec(4 downto 0)), 6));
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_cnt <= "01111";
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_inc <= "00001";
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_dec <= "01111";
ELSIF (clk'EVENT AND clk = '1') THEN
IF (acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_ld = "1") THEN
IF (FALSE and acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_s(4) = '1') THEN
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_inc <= UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_l) + UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_s);
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_dec <= UNSIGNED(TO_UNSIGNED(0, 5)) - UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_s);
ELSE
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_inc <= UNSIGNED(TO_UNSIGNED(0, 5)) + UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_s);
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_dec <= UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_l) - UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_s);
END IF;
END IF;
IF (acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_ld = "1" or acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_en = "1") THEN
IF (acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_ld = "1") THEN
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_cnt <= UNSIGNED(acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_i);
ELSE
IF (acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_dn(5) = '1') THEN
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_cnt <= acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_up;
ELSE
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_cnt <= acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_dn(4 downto 0);
END IF;
END IF;
END IF;
END IF;
END PROCESS;
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_q <= STD_LOGIC_VECTOR(acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_cnt);
-- redist8_acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_q_3(DELAY,55)
redist8_acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_q_3 : dspba_delay
GENERIC MAP ( width => 5, depth => 3, reset_kind => "ASYNC" )
PORT MAP ( xin => acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_q, xout => redist8_acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_q_3_q, clk => clk, aclr => areset );
-- acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_PostCast_primWireOut_sel_x(BITSELECT,2)@6
acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_PostCast_primWireOut_sel_x_b <= std_logic_vector(resize(unsigned(redist8_acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_x_q_3_q(4 downto 0)), 8));
-- redist9_acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_And_x_q_4(DELAY,56)
redist9_acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_And_x_q_4 : dspba_delay
GENERIC MAP ( width => 1, depth => 4, reset_kind => "ASYNC" )
PORT MAP ( xin => acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_And_x_q, xout => redist9_acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_And_x_q_4_q, clk => clk, aclr => areset );
-- ChannelOut(PORTOUT,39)@6 + 1
out_1_valid_out <= redist9_acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_And_x_q_4_q;
out_2_channel_out <= acoustic_delay_buffer_adb_delay_buffer_channel_valid_generator_LoadableCounter_PostCast_primWireOut_sel_x_b;
out_3_dout <= redist7_acoustic_delay_buffer_adb_delay_buffer_circular_buffer_DualMem_x_q_1_q;
END normal;
|
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE work.common.all;
ENTITY cpu_codyale_ph3_tb IS
END ENTITY;
ARCHITECTURE behavioural OF cpu_codyale_ph3_tb IS
SIGNAL Pres_State_tb : State;
SIGNAL clk_tb, reset_tb, stop_tb, Strobe_tb, d_Run_tb : std_logic;
SIGNAL Inport_tb, OutPort_tb,
d_PCOut_tb, d_IROut_tb, d_MDROut_tb, d_MARout_tb,
d_C_sign_extended_tb, d_BusMuxOut_tb,d_YOut_tb,
d_ZLoOut_tb, d_ZHiOut_tb,
d_R00Out_tb, d_R01Out_tb, d_R02Out_tb, d_R03Out_tb, d_R04Out_tb, d_R05Out_tb, d_R06Out_tb, d_R07Out_tb,
d_R08Out_tb, d_R09Out_tb, d_R10Out_tb, d_R11Out_tb, d_R12Out_tb, d_R13Out_tb, d_R14Out_tb, d_R15Out_tb,
d_HIOut_tb, d_LOOut_tb : std_logic_vector(31 downto 0);
COMPONENT cpu_codyale
PORT(
Present_State : OUT State;
--CONTROL PORTS
clk, reset, stop, Strobe : IN STD_LOGIC;
InPort : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
--END CTL PORTS
--DEMONSTRATION PORTS
d_Run : OUT STD_LOGIC;
d_R00Out, d_R01Out, d_R02Out, d_R03Out, d_R04Out, d_R05Out, d_R06Out, d_R07Out,
d_R08Out, d_R09Out, d_R10Out, d_R11Out, d_R12Out, d_R13Out, d_R14Out, d_R15Out,
d_HIOut, d_LOOut, d_PCOut, d_MDROut, d_BusMuxOut, d_IROut, d_YOut, d_C_sign_extended,
d_ZLoOut, d_ZHiOut, d_MARout,
OutPort : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
--END DEMO PORTS
);
END COMPONENT;
BEGIN
DUT : cpu_codyale
PORT MAP (
Present_State => Pres_State_tb,
clk=>clk_tb,
reset=>reset_tb,
stop=>stop_tb,
Strobe=>Strobe_tb,
InPort=>InPort_tb,
--END CTL PORTS
--DEMONSTRATION PORTS
d_Run=>d_Run_tb,
d_R00Out=>d_R00Out_tb, d_R01Out=>d_R01Out_tb, d_R02Out=>d_R02Out_tb, d_R03Out=>d_R03Out_tb,
d_R04Out=>d_R04Out_tb, d_R05Out=>d_R05Out_tb, d_R06Out=>d_R06Out_tb, d_R07Out=>d_R07Out_tb,
d_R08Out=>d_R08Out_tb, d_R09Out=>d_R09Out_tb, d_R10Out=>d_R10Out_tb, d_R11Out=>d_R11Out_tb,
d_R12Out=>d_R12Out_tb, d_R13Out=>d_R13Out_tb, d_R14Out=>d_R14Out_tb, d_R15Out=>d_R15Out_tb,
d_HIOut=>d_HIOut_tb, d_LOOut=>d_LOOut_tb, d_PCOut=>d_PCOut_tb, d_MDROut=>d_MDROut_tb,
d_BusMuxOut=>d_BusMuxOut_tb, d_IROut=>d_IROut_tb, d_YOut=>d_YOut_tb,
d_C_sign_extended=>d_C_sign_extended_tb, d_ZLoOut=>d_ZLoOut_tb, d_ZHiOut=>d_ZHiOut_tb, d_MARout=>d_MARout_tb
);
clk_process :PROCESS
BEGIN
clk_tb <= '0','1' after 5 ns;
wait for 10 ns;
END PROCESS;
tb : PROCESS
BEGIN
reset_tb <= '1'; stop_tb <='1';
wait until rising_edge(clk_tb);
reset_tb <= '0'; stop_tb <='0';
wait;
END PROCESS;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use work.constants.all;
package LibNode is
type Address is record
X : std_logic_vector(Address_Length_X - 1 downto 0);
Y : std_logic_vector(Address_Length_Y - 1 downto 0);
end record;
type AddressPort is record
AddressReceiver : Address;
AddressSender : Address;
end record;
type P_PORT_VERTICAL is record
Data : std_logic_vector(Data_Length - 1 downto 0);
--Address: std_logic_vector((Address_Length_X + Address_Length_Y)*2-1 DOWNTO 0);
Address : AddressPort;
DataAvailable : std_logic;
Marked : std_logic;
--Request : std_logic;
end record;
type P_PORT_VERTICAL_BACK is record
--Address: std_logic_vector((Address_Length_X + Address_Length_Y)*2-1 DOWNTO 0);
--Address : AddressPort;
Request : std_logic;
end record;
type P_PORT_HORIZONTAL is record
Data : std_logic_vector(Data_Length - 1 downto 0);
--Address: std_logic_vector((Address_Length_X + Address_Length_Y)*2-1 DOWNTO 0);
Address : AddressPort;
DataAvailable : std_logic;
Marked : std_logic;
--Request : std_logic;
end record;
type P_PORT_HORIZONTAL_BACK is record
--Address: std_logic_vector((Address_Length_X + Address_Length_Y)*2-1 DOWNTO 0);
--Address : AddressPort;
Request : std_logic;
end record;
type REQUEST_PORT is record
Address : std_logic_vector((Address_Length_X + Address_Length_Y) - 1 downto 0);
Request : std_logic;
SpecificRequest : std_logic;
ProbeRequest : std_logic; --als peek, daten rückliefern aber nicht entfernen
end record;
type P_PORT_BUFFER is record
Data : std_logic_vector(Data_Length - 1 downto 0);
Address : std_logic_vector((Address_Length_X + Address_Length_Y) - 1 downto 0);
DataAvailable : std_logic;
end record;
type FIFOEntry is record
Data : std_logic_vector(Data_Length - 1 downto 0);
Address : AddressPort;
end record;
type BusyCounterReceive_T is array (0 to Dimension - 1) of natural;
component NODE
port(Clk : in std_logic;
Rst : in std_logic;
NorthIn : in P_PORT_VERTICAL_BACK;
NorthOut : out P_PORT_VERTICAL;
SouthIn : in P_PORT_VERTICAL;
SouthOut : out P_PORT_VERTICAL_BACK;
EastIn : IN P_PORT_HORIZONTAL_BACK;
EastOut : out P_PORT_HORIZONTAL;
WestIn : in P_PORT_HORIZONTAL;
WestOut : out P_PORT_HORIZONTAL_BACK;
LocalOut : out P_PORT_BUFFER;
LocalIn : in P_PORT_BUFFER;
BufferOverflow : out std_logic;
RecvBufferFull : in std_logic;
CoreAddress : in Address;
ProcessorToBuffer : in P_PORT_BUFFER;
SendBufferFull : out std_logic
);
end component;
component NetworkInterfaceReceive
port(
Clk : in std_logic;
Rst : in std_logic;
NodeToBuffer : in P_PORT_BUFFER;
StallNode : out std_logic;
BufferToProcessor : out P_PORT_BUFFER;
ProcessorRequest : in REQUEST_PORT
);
end component;
end LibNode;
|
<reponame>Accelize/GettingStarted_Examples<filename>Hardware/Xilinx_Vitis/02_hls_kernel/rtl_adder_pipes_c_dual_clock/src/drm_hdk/activator0/core/drm_ip_activator_package_0x1003000e00010001.vhdl
---------------------------------------------------------------------
----
---- AUTOGENERATED FILE - DO NOT EDIT
---- DRM SCRIPT VERSION 2.2.0
---- DRM HDK VERSION 6.0.0.0
---- DRM VERSION 6.0.0
---- COPYRIGHT (C) ALGODONE
----
---------------------------------------------------------------------
`protect begin_protected
`protect version=1
`protect encrypt_agent="ipecrypt"
`protect encrypt_agent_info="http://ipencrypter.com Version: 19.2.4"
`protect author="Algodone"
`protect data_method="aes128-cbc"
`protect key_keyowner="Xilinx"
`protect key_keyname="xilinx_2016_05"
`protect key_method="rsa"
`protect encoding=(enctype="base64", line_length=64, bytes=256)
`protect key_block
<KEY>
`protect key_keyowner="Xilinx"
`protect key_keyname="xilinxt_2017_05"
`protect key_method="rsa"
`protect encoding=(enctype="base64", line_length=64, bytes=256)
`protect key_block
<KEY>
`protect key_keyowner="Xilinx"
`protect key_keyname="xilinxt_2019_02"
`protect key_method="rsa"
`protect encoding=(enctype="base64", line_length=64, bytes=256)
`protect key_block
<KEY>
`protect key_keyowner="Intel Corporation"
`protect key_keyname="Intel-FPGA-Quartus-RSA-1"
`protect key_method="rsa"
`protect encoding=(enctype="base64", line_length=64, bytes=256)
`protect key_block
<KEY>
`protect key_keyowner="Mentor Graphics Corporation"
`protect key_keyname="MGC-VERIF-SIM-RSA-1"
`protect key_method="rsa"
`protect encoding=(enctype="base64", line_length=64, bytes=128)
`protect key_block
<KEY>
`protect encoding=(enctype="base64", line_length=64, bytes=320)
`protect data_block
<KEY>
`protect end_protected
|
-------------------------------------------------------------------------------
-- Title : Wishbone package
-- Project : General Cores
-------------------------------------------------------------------------------
-- File : wishbone_pkg.vhd
-- Company : CERN
-- Platform : FPGA-generics
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Copyright (c) 2011-2017 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
package wishbone_pkg is
constant c_wishbone_address_width : integer := 32;
constant c_wishbone_data_width : integer := 32;
subtype t_wishbone_address is
std_logic_vector(c_wishbone_address_width-1 downto 0);
subtype t_wishbone_data is
std_logic_vector(c_wishbone_data_width-1 downto 0);
subtype t_wishbone_byte_select is
std_logic_vector((c_wishbone_address_width/8)-1 downto 0);
subtype t_wishbone_cycle_type is
std_logic_vector(2 downto 0);
subtype t_wishbone_burst_type is
std_logic_vector(1 downto 0);
type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
type t_wishbone_address_granularity is (BYTE, WORD);
type t_wishbone_master_out is record
cyc : std_logic;
stb : std_logic;
adr : t_wishbone_address;
sel : t_wishbone_byte_select;
we : std_logic;
dat : t_wishbone_data;
end record t_wishbone_master_out;
subtype t_wishbone_slave_in is t_wishbone_master_out;
type t_wishbone_slave_out is record
ack : std_logic;
err : std_logic;
rty : std_logic;
stall : std_logic;
int : std_logic;
dat : t_wishbone_data;
end record t_wishbone_slave_out;
subtype t_wishbone_master_in is t_wishbone_slave_out;
subtype t_wishbone_device_descriptor is std_logic_vector(255 downto 0);
type t_wishbone_byte_select_array is array(natural range <>) of t_wishbone_byte_select;
type t_wishbone_data_array is array(natural range <>) of t_wishbone_data;
type t_wishbone_address_array is array(natural range <>) of t_wishbone_address;
type t_wishbone_master_out_array is array (natural range <>) of t_wishbone_master_out;
--type t_wishbone_slave_in_array is array (natural range <>) of t_wishbone_slave_in;
subtype t_wishbone_slave_in_array is t_wishbone_master_out_array;
type t_wishbone_slave_out_array is array (natural range <>) of t_wishbone_slave_out;
--type t_wishbone_master_in_array is array (natural range <>) of t_wishbone_master_in;
subtype t_wishbone_master_in_array is t_wishbone_slave_out_array;
constant cc_dummy_address : std_logic_vector(c_wishbone_address_width-1 downto 0) :=
(others => 'X');
constant cc_dummy_data : std_logic_vector(c_wishbone_data_width-1 downto 0) :=
(others => 'X');
constant cc_dummy_sel : std_logic_vector(c_wishbone_data_width/8-1 downto 0) :=
(others => 'X');
constant cc_dummy_slave_in : t_wishbone_slave_in :=
('0', '0', cc_dummy_address, cc_dummy_sel, 'X', cc_dummy_data);
constant cc_dummy_master_out : t_wishbone_master_out := cc_dummy_slave_in;
-- Dangerous! Will stall a bus.
constant cc_dummy_slave_out : t_wishbone_slave_out :=
('X', 'X', 'X', 'X', 'X', cc_dummy_data);
constant cc_dummy_master_in : t_wishbone_master_in := cc_dummy_slave_out;
constant cc_dummy_address_array : t_wishbone_address_array(0 downto 0) := (0 => cc_dummy_address);
-- A generally useful function.
function f_ceil_log2(x : natural) return natural;
function f_bits2string(s : std_logic_vector) return string;
function f_string2bits(s : string) return std_logic_vector;
function f_string2svl (s : string) return std_logic_vector;
function f_slv2string (slv : std_logic_vector) return string;
function f_string_fix_len( s : string; ret_len : natural := 10; fill_char : character := '0'; justify_right : boolean := true ) return string;
function f_hot_to_bin(x : std_logic_vector) return natural;
-- *** Wishbone slave interface functions ***
-- f_wb_wr:
-- processes an incoming write reqest to a register while honoring the select lines
-- valid modes are overwrite "owr", set "set" (bits are or'ed) and clear "clr" (bits are nand'ed)
function f_wb_wr(pval : std_logic_vector; ival : std_logic_vector; sel : std_logic_vector; mode : string := "owr") return std_logic_vector;
------------------------------------------------------------------------------
-- SDB declaration
------------------------------------------------------------------------------
constant c_sdb_device_length : natural := 512; -- bits
subtype t_sdb_record is std_logic_vector(c_sdb_device_length-1 downto 0);
type t_sdb_record_array is array(natural range <>) of t_sdb_record;
type t_sdb_product is record
vendor_id : std_logic_vector(63 downto 0);
device_id : std_logic_vector(31 downto 0);
version : std_logic_vector(31 downto 0);
date : std_logic_vector(31 downto 0);
name : string(1 to 19);
end record t_sdb_product;
type t_sdb_component is record
addr_first : std_logic_vector(63 downto 0);
addr_last : std_logic_vector(63 downto 0);
product : t_sdb_product;
end record t_sdb_component;
constant c_sdb_endian_big : std_logic := '0';
constant c_sdb_endian_little : std_logic := '1';
type t_sdb_device is record
abi_class : std_logic_vector(15 downto 0);
abi_ver_major : std_logic_vector(7 downto 0);
abi_ver_minor : std_logic_vector(7 downto 0);
wbd_endian : std_logic; -- 0 = big, 1 = little
wbd_width : std_logic_vector(3 downto 0); -- 3=64-bit, 2=32-bit, 1=16-bit, 0=8-bit
sdb_component : t_sdb_component;
end record t_sdb_device;
type t_sdb_msi is record
wbd_endian : std_logic; -- 0 = big, 1 = little
wbd_width : std_logic_vector(3 downto 0); -- 3=64-bit, 2=32-bit, 1=16-bit, 0=8-bit
sdb_component : t_sdb_component;
end record t_sdb_msi;
type t_sdb_bridge is record
sdb_child : std_logic_vector(63 downto 0);
sdb_component : t_sdb_component;
end record t_sdb_bridge;
type t_sdb_integration is record
product : t_sdb_product;
end record t_sdb_integration;
type t_sdb_repo_url is record
repo_url : string(1 to 63);
end record t_sdb_repo_url;
type t_sdb_synthesis is record
syn_module_name : string(1 to 16);
syn_commit_id : string(1 to 32);
syn_tool_name : string(1 to 8);
syn_tool_version : std_logic_vector(31 downto 0);
syn_date : std_logic_vector(31 downto 0);
syn_username : string(1 to 15);
end record t_sdb_synthesis;
-- If you have a Wishbone master that does not receive MSI,
-- list it in the layout as 'f_sdb_auto_msi(c_null_msi, false)'
constant c_null_msi : t_sdb_msi := (
wbd_endian => c_sdb_endian_big,
wbd_width => x"0",
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000000",
product => (
vendor_id => x"0000000000000000",
device_id => x"00000000",
version => x"00000000",
date => x"00000000",
name => " ")));
-- general crossbar building functions
function f_sdb_create_array(g_enum_dev_id : boolean := false;
g_dev_id_offs : natural := 0;
g_enum_dev_name : boolean := false;
g_dev_name_offs : natural := 0;
device : t_sdb_device;
instances : natural := 1) return t_sdb_record_array;
function f_sdb_join_arrays(a : t_sdb_record_array; b : t_sdb_record_array) return t_sdb_record_array;
function f_sdb_extract_base_addr(sdb_record : t_sdb_record) return std_logic_vector;
function f_sdb_extract_end_addr(sdb_record : t_sdb_record) return std_logic_vector;
function f_sdb_automap_array(sdb_array : t_sdb_record_array; start_offset : t_wishbone_address := (others => '0')) return t_sdb_record_array;
function f_align_addr_offset(offs : unsigned; this_rng : unsigned; prev_rng : unsigned) return unsigned;
function f_sdb_create_rom_addr(sdb_array : t_sdb_record_array) return t_wishbone_address;
-- Used to configure a device at a certain address
function f_sdb_embed_device(device : t_sdb_device; address : t_wishbone_address) return t_sdb_record;
function f_sdb_embed_bridge(bridge : t_sdb_bridge; address : t_wishbone_address) return t_sdb_record;
function f_sdb_embed_msi(msi : t_sdb_msi; address : t_wishbone_address) return t_sdb_record;
function f_sdb_embed_integration(integr : t_sdb_integration) return t_sdb_record;
function f_sdb_embed_repo_url(url : t_sdb_repo_url) return t_sdb_record;
function f_sdb_embed_synthesis(syn : t_sdb_synthesis) return t_sdb_record;
function f_sdb_extract_device(sdb_record : t_sdb_record) return t_sdb_device;
function f_sdb_extract_bridge(sdb_record : t_sdb_record) return t_sdb_bridge;
function f_sdb_extract_msi(sdb_record : t_sdb_record) return t_sdb_msi;
function f_sdb_extract_integration(sdb_record : t_sdb_record) return t_sdb_integration;
function f_sdb_extract_repo_url(sdb_record : t_sdb_record) return t_sdb_repo_url;
function f_sdb_extract_synthesis(sdb_record : t_sdb_record) return t_sdb_synthesis;
-- Automatic crossbar mapping functions
function f_sdb_auto_device(device : t_sdb_device; enable : boolean := true; name: string := "") return t_sdb_record;
function f_sdb_auto_bridge(bridge : t_sdb_bridge; enable : boolean := true; name: string := "") return t_sdb_record;
function f_sdb_auto_msi (msi : t_sdb_msi; enable : boolean := true) return t_sdb_record;
function f_sdb_auto_layout(records: t_sdb_record_array) return t_sdb_record_array;
function f_sdb_auto_layout(slaves : t_sdb_record_array; masters : t_sdb_record_array) return t_sdb_record_array;
function f_sdb_auto_sdb (records: t_sdb_record_array) return t_wishbone_address;
function f_sdb_auto_sdb (slaves : t_sdb_record_array; masters : t_sdb_record_array) return t_wishbone_address;
-- For internal use by the crossbar
function f_sdb_bus_end(g_wraparound : boolean; g_layout : t_sdb_record_array; g_sdb_addr : t_wishbone_address; msi : boolean) return unsigned;
function f_sdb_embed_product(product : t_sdb_product) return std_logic_vector; -- (319 downto 8)
function f_sdb_embed_component(sdb_component : t_sdb_component; address : t_wishbone_address) return std_logic_vector; -- (447 downto 8)
function f_sdb_extract_product(sdb_record : std_logic_vector(319 downto 8)) return t_sdb_product;
function f_sdb_extract_component(sdb_record : std_logic_vector(447 downto 8)) return t_sdb_component;
------------------------------------------------------------------------------
-- Components declaration
-------------------------------------------------------------------------------
component wb_slave_adapter
generic (
g_master_use_struct : boolean;
g_master_mode : t_wishbone_interface_mode;
g_master_granularity : t_wishbone_address_granularity;
g_slave_use_struct : boolean;
g_slave_mode : t_wishbone_interface_mode;
g_slave_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
sl_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := cc_dummy_address;
sl_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := cc_dummy_data;
sl_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := cc_dummy_sel;
sl_cyc_i : in std_logic := '0';
sl_stb_i : in std_logic := '0';
sl_we_i : in std_logic := '0';
sl_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
sl_err_o : out std_logic;
sl_rty_o : out std_logic;
sl_ack_o : out std_logic;
sl_stall_o : out std_logic;
sl_int_o : out std_logic;
slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
slave_o : out t_wishbone_slave_out;
ma_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
ma_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
ma_sel_o : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
ma_cyc_o : out std_logic;
ma_stb_o : out std_logic;
ma_we_o : out std_logic;
ma_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := cc_dummy_data;
ma_err_i : in std_logic := '0';
ma_rty_i : in std_logic := '0';
ma_ack_i : in std_logic := '0';
ma_stall_i : in std_logic := '0';
ma_int_i : in std_logic := '0';
master_i : in t_wishbone_master_in := cc_dummy_slave_out;
master_o : out t_wishbone_master_out);
end component;
component wb_async_bridge
generic (
g_simulation : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cpu_address_width : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
cpu_cs_n_i : in std_logic;
cpu_wr_n_i : in std_logic;
cpu_rd_n_i : in std_logic;
cpu_bs_n_i : in std_logic_vector(3 downto 0);
cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
cpu_data_b : inout std_logic_vector(31 downto 0);
cpu_nwait_o : out std_logic;
wb_adr_o : out std_logic_vector(c_wishbone_address_width - 1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_sel_o : out std_logic_vector(3 downto 0);
wb_cyc_o : out std_logic;
wb_dat_i : in std_logic_vector (c_wishbone_data_width-1 downto 0);
wb_ack_i : in std_logic;
wb_stall_i : in std_logic := '0');
end component;
component xwb_async_bridge
generic (
g_simulation : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cpu_address_width : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
cpu_cs_n_i : in std_logic;
cpu_wr_n_i : in std_logic;
cpu_rd_n_i : in std_logic;
cpu_bs_n_i : in std_logic_vector(3 downto 0);
cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
cpu_data_b : inout std_logic_vector(31 downto 0);
cpu_nwait_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in);
end component;
component xwb_bus_fanout
generic (
g_num_outputs : natural;
g_bits_per_slave : integer;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_slave_interface_mode : t_wishbone_interface_mode := CLASSIC);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
master_i : in t_wishbone_master_in_array(0 to g_num_outputs-1);
master_o : out t_wishbone_master_out_array(0 to g_num_outputs-1));
end component;
component xwb_crossbar
generic (
g_num_masters : integer;
g_num_slaves : integer;
g_registered : boolean;
g_address : t_wishbone_address_array;
g_mask : t_wishbone_address_array);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0);
sdb_sel_o : out std_logic_vector(g_num_masters-1 downto 0)); -- leave open!
end component;
-- Use the f_xwb_bridge_*_sdb to bridge a crossbar to another
function f_xwb_bridge_manual_sdb( -- take a manual bus size
g_size : t_wishbone_address;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge;
function f_xwb_bridge_layout_sdb( -- determine bus size from layout
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge;
function f_xwb_msi_manual_sdb( -- take a manual bus size
g_size : t_wishbone_address) return t_sdb_msi;
function f_xwb_msi_layout_sdb( -- determine MSI size from layout
g_layout : t_sdb_record_array) return t_sdb_msi;
component xwb_sdb_crossbar
generic (
g_num_masters : integer;
g_num_slaves : integer;
g_registered : boolean := false;
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address;
g_sdb_name : string := "WB4-Crossbar-GSI ");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in_array (g_num_masters-1 downto 0);
slave_o : out t_wishbone_slave_out_array (g_num_masters-1 downto 0);
msi_master_i : in t_wishbone_master_in_array (g_num_masters-1 downto 0) := (others => cc_dummy_master_in);
msi_master_o : out t_wishbone_master_out_array(g_num_masters-1 downto 0);
master_i : in t_wishbone_master_in_array (g_num_slaves -1 downto 0);
master_o : out t_wishbone_master_out_array(g_num_slaves -1 downto 0);
msi_slave_i : in t_wishbone_slave_in_array (g_num_slaves -1 downto 0) := (others => cc_dummy_slave_in);
msi_slave_o : out t_wishbone_slave_out_array (g_num_slaves -1 downto 0));
end component;
component xwb_register_link -- puts a register of delay between crossbars
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out);
end component;
-- skidpad. acts like a fifo in wb flow control, but costs less
component wb_skidpad is
generic(
g_adrbits : natural := 32
);
Port(
clk_i : std_logic;
rst_n_i : std_logic;
push_i : in std_logic;
pop_i : in std_logic;
full_o : out std_logic;
empty_o : out std_logic;
adr_i : in std_logic_vector(g_adrbits-1 downto 0);
dat_i : in std_logic_vector(32-1 downto 0);
sel_i : in std_logic_vector(4-1 downto 0);
we_i : in std_logic;
adr_o : out std_logic_vector(g_adrbits-1 downto 0);
dat_o : out std_logic_vector(32-1 downto 0);
sel_o : out std_logic_vector(4-1 downto 0);
we_o : out std_logic
);
end component;
component sdb_rom is
generic(
g_layout : t_sdb_record_array;
g_masters : natural;
g_bus_end : unsigned(63 downto 0);
g_sdb_name : string := "WB4-Crossbar-GSI ");
port(
clk_sys_i : in std_logic;
master_i : in std_logic_vector(g_masters-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out);
end component;
constant c_xwb_dma_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001f",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"cababa56",
version => x"00000001",
date => x"20120518",
name => "WB4-Streaming-DMA_0")));
component xwb_dma is
generic(
-- Value 0 cannot stream
-- Value 1 only slaves with async ACK can stream
-- Value 2 only slaves with combined latency <= 2 can stream
-- Value 3 only slaves with combined latency <= 6 can stream
-- Value 4 only slaves with combined latency <= 14 can stream
-- ....
logRingLen : integer := 4
);
port(
-- Common wishbone signals
clk_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- Master reader port
r_master_i : in t_wishbone_master_in;
r_master_o : out t_wishbone_master_out;
-- Master writer port
w_master_i : in t_wishbone_master_in;
w_master_o : out t_wishbone_master_out;
-- Pulsed high completion signal
interrupt_o : out std_logic
);
end component;
-- If you reset one clock domain, you must reset BOTH!
-- Release of the reset lines may be arbitrarily out-of-phase
component xwb_clock_crossing is
generic(
g_size : natural := 16);
port(
-- Slave control port
slave_clk_i : in std_logic;
slave_rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- Master reader port
master_clk_i : in std_logic;
master_rst_n_i : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out;
-- Flow control back-channel for acks
slave_ready_o : out std_logic;
slave_stall_i : in std_logic := '0');
end component;
-- g_size is in words
function f_xwb_dpram(g_size : natural) return t_sdb_device;
component xwb_dpram
generic (
g_size : natural;
g_init_file : string := "";
g_must_have_init_file : boolean := true;
g_slave1_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_slave2_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_slave1_granularity : t_wishbone_address_granularity := WORD;
g_slave2_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out;
slave2_i : in t_wishbone_slave_in;
slave2_o : out t_wishbone_slave_out);
end component;
component xwb_dpram_mixed
generic(
g_size : natural := 16384;
g_init_file : string := "";
g_must_have_init_file : boolean := true;
g_swap_word_endianness : boolean := true;
g_slave1_interface_mode : t_wishbone_interface_mode;
g_slave2_interface_mode : t_wishbone_interface_mode;
g_dpram_port_a_width : integer := 16;
g_dpram_port_b_width : integer := 32;
g_slave1_granularity : t_wishbone_address_granularity;
g_slave2_granularity : t_wishbone_address_granularity);
port(
clk_slave1_i : in std_logic;
clk_slave2_i : in std_logic;
rst_n_i : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out;
slave2_i : in t_wishbone_slave_in;
slave2_o : out t_wishbone_slave_out);
end component;
-- Just like the DMA controller, but constantly at address 0
component xwb_streamer is
generic(
-- Value 0 cannot stream
-- Value 1 only slaves with async ACK can stream
-- Value 2 only slaves with combined latency = 2 can stream
-- Value 3 only slaves with combined latency = 6 can stream
-- Value 4 only slaves with combined latency = 14 can stream
-- ....
logRingLen : integer := 4
);
port(
-- Common wishbone signals
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Master reader port
r_master_i : in t_wishbone_master_in;
r_master_o : out t_wishbone_master_out;
-- Master writer port
w_master_i : in t_wishbone_master_in;
w_master_o : out t_wishbone_master_out);
end component;
constant c_xwb_gpio_port_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"441c5143",
version => x"00000001",
date => x"20121129",
name => "WB-GPIO-Port ")));
component wb_gpio_port
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256;
g_with_builtin_tristates : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
end component;
component xwb_gpio_port
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256;
g_with_builtin_tristates : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
end component;
constant c_xwb_i2c_master_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"123c5443",
version => x"00000001",
date => x"20121129",
name => "WB-I2C-Master ")));
component wb_i2c_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_interfaces : integer := 1);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
scl_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
scl_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0);
sda_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
sda_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
sda_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0));
end component;
component xwb_i2c_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_interfaces : integer := 1);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
scl_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
scl_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0);
sda_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
sda_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
sda_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0));
end component;
component xwb_lm32
generic (
g_profile : string;
g_reset_vector : std_logic_vector(31 downto 0) := x"00000000";
g_sdb_address : std_logic_vector(31 downto 0) := x"00000000");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
irq_i : in std_logic_vector(31 downto 0);
dwb_o : out t_wishbone_master_out;
dwb_i : in t_wishbone_master_in;
iwb_o : out t_wishbone_master_out;
iwb_i : in t_wishbone_master_in);
end component;
constant c_xwb_onewire_master_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"779c5443",
version => x"00000001",
date => x"20121129",
name => "WB-OneWire-Master ")));
component wb_onewire_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string := "1.0";
g_ow_btp_overdrive : string := "5.0");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0));
end component;
component xwb_onewire_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string := "5.0";
g_ow_btp_overdrive : string := "1.0");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0));
end component;
constant c_xwb_spi_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"e503947e", -- echo "WB-SPI.Control " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-SPI.Control ")));
component wb_spi
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_divider_len : integer := 16;
g_max_char_len : integer := 128;
g_num_slaves : integer := 8);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
pad_cs_o : out std_logic_vector(g_num_slaves-1 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
pad_miso_i : in std_logic);
end component;
component xwb_spi
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_divider_len : integer := 16;
g_max_char_len : integer := 128;
g_num_slaves : integer := 8);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
pad_cs_o : out std_logic_vector(g_num_slaves-1 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
pad_miso_i : in std_logic);
end component;
component wb_simple_uart
generic (
g_with_virtual_uart : boolean := false;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_vuart_fifo_size : integer := 1024);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic);
end component;
component xwb_simple_uart
generic (
g_with_virtual_uart : boolean := false;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_vuart_fifo_size : integer := 1024);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic);
end component;
component wb_simple_pwm
generic (
g_num_channels : integer range 1 to 8;
g_regs_size : integer range 1 to 16 := 16;
g_default_period : integer range 0 to 255 := 0;
g_default_presc : integer range 0 to 255 := 0;
g_default_val : integer range 0 to 255 := 0;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
pwm_o : out std_logic_vector(g_num_channels-1 downto 0));
end component;
component xwb_simple_pwm
generic (
g_num_channels : integer range 1 to 8;
g_regs_size : integer range 1 to 16 := 16;
g_default_period : integer range 0 to 255 := 0;
g_default_presc : integer range 0 to 255 := 0;
g_default_val : integer range 0 to 255 := 0;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pwm_o : out std_logic_vector(g_num_channels-1 downto 0));
end component;
component wb_tics
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_period : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic);
end component;
component xwb_tics
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_period : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor);
end component;
component wb_vic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_interrupts : natural;
g_init_vectors : t_wishbone_address_array := cc_dummy_address_array;
g_retry_timeout : integer := 0
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0);
irq_master_o : out std_logic);
end component;
constant c_xwb_vic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000013",
version => x"00000002",
date => x"20120113",
name => "WB-VIC-Int.Control ")));
component xwb_vic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_interrupts : natural;
g_init_vectors : t_wishbone_address_array := cc_dummy_address_array;
g_retry_timeout : integer := 0);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0);
irq_master_o : out std_logic);
end component;
constant c_wb_serial_lcd_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"b77a5045",
version => x"00000001",
date => x"20130222",
name => "SERIAL-LCD-DISPLAY ")));
component wb_serial_lcd
generic(
g_cols : natural := 40;
g_rows : natural := 24;
g_hold : natural := 15; -- How many times to repeat a line (for sharpness)
g_wait : natural := 1); -- How many cycles per state change (for 20MHz timing)
port(
slave_clk_i : in std_logic;
slave_rstn_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
di_clk_i : in std_logic;
di_scp_o : out std_logic;
di_lp_o : out std_logic;
di_flm_o : out std_logic;
di_dat_o : out std_logic);
end component;
function f_wb_spi_flash_sdb(g_bits : natural) return t_sdb_device;
component wb_spi_flash is
generic(
g_port_width : natural := 1; -- 1 for EPCS, 4 for EPCQ
g_addr_width : natural := 24; -- log of memory (24=16MB)
g_idle_time : natural := 3;
g_dummy_time : natural := 8;
-- leave these at defaults if you have:
-- a) slow clock, b) valid constraints, or c) registered in/outputs
g_input_latch_edge : std_logic := '1'; -- rising
g_output_latch_edge : std_logic := '0'; -- falling
g_input_to_output_cycles : natural := 1); -- between 1 and 8
port(
clk_i : in std_logic;
rstn_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- For properly constrained designs, set clk_out_i = clk_in_i.
clk_out_i : in std_logic;
clk_in_i : in std_logic;
ncs_o : out std_logic;
oe_o : out std_logic_vector(g_port_width-1 downto 0);
asdi_o : out std_logic_vector(g_port_width-1 downto 0);
data_i : in std_logic_vector(g_port_width-1 downto 0);
external_request_i : in std_logic := '0'; -- JTAG wants to use SPI?
external_granted_o : out std_logic);
end component;
-----------------------------------------------------------------------------
-- I2C to Wishbone bridge, following protocol defined with ELMA
-----------------------------------------------------------------------------
component wb_i2c_bridge is
generic
(
-- FSM watchdog timeout, see Appendix A in the component documentation for
-- an example of setting this generic
g_fsm_wdt : positive
);
port
(
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- I2C address
i2c_addr_i : in std_logic_vector(6 downto 0);
-- Status outputs
-- TIP : Transfer In Progress
-- '1' when the I2C slave detects a matching I2C address, thus a
-- transfer is in progress
-- '0' when idle
-- ERR : Error
-- '1' when the SysMon attempts to access an invalid WB slave
-- '0' when idle
-- WDTO : Watchdog timeout (single clock cycle pulse)
-- '1' -- timeout of watchdog occured
-- '0' -- when idle
tip_o : out std_logic;
err_p_o : out std_logic;
wdto_p_o : out std_logic;
-- Wishbone master signals
wbm_stb_o : out std_logic;
wbm_cyc_o : out std_logic;
wbm_sel_o : out std_logic_vector(3 downto 0);
wbm_we_o : out std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_adr_o : out std_logic_vector(31 downto 0);
wbm_ack_i : in std_logic;
wbm_rty_i : in std_logic;
wbm_err_i : in std_logic
);
end component wb_i2c_bridge;
------------------------------------------------------------------------------
-- MultiBoot component
------------------------------------------------------------------------------
component xwb_xil_multiboot is
port
(
-- Clock and reset input ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone ports
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
-- SPI ports
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component xwb_xil_multiboot;
constant c_xwb_xil_multiboot_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001f",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"11da333d", -- echo "WB-Xilinx-MultiBoot" | md5sum | cut -c1-8
version => x"00000001",
date => x"20140313",
name => "WB-Xilinx-MultiBoot")));
constant cc_dummy_sdb_device : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"ffffffff",
version => x"00000001",
date => x"20150722",
name => "Unused-Device ")));
end wishbone_pkg;
package body wishbone_pkg is
-- f_wb_wr: processes a write reqest to a slave register with select lines. valid modes are "owr", "set" and "clr"
function f_wb_wr(pval : std_logic_vector; ival : std_logic_vector; sel : std_logic_vector; mode : string := "owr") return std_logic_vector is
variable n_sel : std_logic_vector(pval'range);
variable n_val : std_logic_vector(pval'range);
variable result : std_logic_vector(pval'range);
begin
for i in pval'range loop
n_sel(i) := sel((i-pval'low) / 8); -- subtract the low index for when register width > wishbone data width
n_val(i) := ival(i-pval'low);
end loop;
if(mode = "set") then
result := pval or (n_val and n_sel);
elsif (mode = "clr") then
result := pval and not (n_val and n_sel);
else
result := (pval and not n_sel) or (n_val and n_sel);
end if;
return result;
end f_wb_wr;
function f_ceil_log2(x : natural) return natural is
begin
if x <= 1
then return 0;
else return f_ceil_log2((x+1)/2) +1;
end if;
end f_ceil_log2;
function f_sdb_embed_product(product : t_sdb_product)
return std_logic_vector -- (319 downto 8)
is
variable result : std_logic_vector(319 downto 8);
begin
result(319 downto 256) := product.vendor_id;
result(255 downto 224) := product.device_id;
result(223 downto 192) := product.version;
result(191 downto 160) := product.date;
for i in 0 to 18 loop -- string to ascii
result(159-i*8 downto 152-i*8) :=
std_logic_vector(to_unsigned(character'pos(product.name(i+1)), 8));
end loop;
return result;
end;
function f_sdb_extract_product(sdb_record : std_logic_vector(319 downto 8))
return t_sdb_product
is
variable result : t_sdb_product;
begin
result.vendor_id := sdb_record(319 downto 256);
result.device_id := sdb_record(255 downto 224);
result.version := sdb_record(223 downto 192);
result.date := sdb_record(191 downto 160);
for i in 0 to 18 loop -- ascii to string
result.name(i+1) := character'val(to_integer(unsigned(sdb_record(159-i*8 downto 152-i*8))));
end loop;
return result;
end;
function f_sdb_embed_component(sdb_component : t_sdb_component; address : t_wishbone_address)
return std_logic_vector -- (447 downto 8)
is
variable result : std_logic_vector(447 downto 8);
constant first : unsigned(63 downto 0) := unsigned(sdb_component.addr_first);
constant last : unsigned(63 downto 0) := unsigned(sdb_component.addr_last);
variable base : unsigned(63 downto 0) := (others => '0');
begin
base(address'length-1 downto 0) := unsigned(address);
result(447 downto 384) := std_logic_vector(base);
result(383 downto 320) := std_logic_vector(base + last - first);
result(319 downto 8) := f_sdb_embed_product(sdb_component.product);
return result;
end;
function f_sdb_extract_component(sdb_record : std_logic_vector(447 downto 8))
return t_sdb_component
is
variable result : t_sdb_component;
begin
result.addr_first := sdb_record(447 downto 384);
result.addr_last := sdb_record(383 downto 320);
result.product := f_sdb_extract_product(sdb_record(319 downto 8));
return result;
end;
function f_sdb_embed_device(device : t_sdb_device; address : t_wishbone_address)
return t_sdb_record
is
variable result : t_sdb_record;
begin
result(511 downto 496) := device.abi_class;
result(495 downto 488) := device.abi_ver_major;
result(487 downto 480) := device.abi_ver_minor;
result(479 downto 456) := (others => '0');
result(455) := device.wbd_endian;
result(454 downto 452) := (others => '0');
result(451 downto 448) := device.wbd_width;
result(447 downto 8) := f_sdb_embed_component(device.sdb_component, address);
result(7 downto 0) := x"01"; -- device
return result;
end;
function f_sdb_extract_device(sdb_record : t_sdb_record)
return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := sdb_record(511 downto 496);
result.abi_ver_major := sdb_record(495 downto 488);
result.abi_ver_minor := sdb_record(487 downto 480);
result.wbd_endian := sdb_record(452);
result.wbd_width := sdb_record(451 downto 448);
result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
assert sdb_record(7 downto 0) = x"01"
report "Cannot extract t_sdb_device from record of type " & integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity failure;
return result;
end;
function f_sdb_embed_msi(msi : t_sdb_msi; address : t_wishbone_address)
return t_sdb_record
is
variable result : t_sdb_record;
begin
result(511 downto 456) := (others => '0');
result(455) := msi.wbd_endian;
result(454 downto 452) := (others => '0');
result(451 downto 448) := msi.wbd_width;
result(447 downto 8) := f_sdb_embed_component(msi.sdb_component, address);
result(7 downto 0) := x"03"; -- msi
return result;
end;
function f_sdb_extract_msi(sdb_record : t_sdb_record)
return t_sdb_msi
is
variable result : t_sdb_msi;
begin
result.wbd_endian := sdb_record(452);
result.wbd_width := sdb_record(451 downto 448);
result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
assert sdb_record(7 downto 0) = x"03"
report "Cannot extract t_sdb_msi from record of type " & integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity failure;
return result;
end;
function f_sdb_embed_integration(integr : t_sdb_integration)
return t_sdb_record
is
variable result : t_sdb_record;
begin
result(511 downto 320) := (others => '0');
result(319 downto 8) := f_sdb_embed_product(integr.product);
result(7 downto 0) := x"80"; -- integration record
return result;
end f_sdb_embed_integration;
function f_sdb_extract_integration(sdb_record : t_sdb_record)
return t_sdb_integration
is
variable result : t_sdb_integration;
begin
result.product := f_sdb_extract_product(sdb_record(319 downto 8));
assert sdb_record(7 downto 0) = x"80"
report "Cannot extract t_sdb_integration from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity Failure;
return result;
end f_sdb_extract_integration;
function f_sdb_embed_repo_url(url : t_sdb_repo_url)
return t_sdb_record
is
variable result : t_sdb_record;
begin
result(511 downto 8) := f_string2svl(url.repo_url);
result( 7 downto 0) := x"81"; -- repo_url record
return result;
end;
function f_sdb_extract_repo_url(sdb_record : t_sdb_record)
return t_sdb_repo_url
is
variable result : t_sdb_repo_url;
begin
result.repo_url := f_slv2string(sdb_record(511 downto 8));
assert sdb_record(7 downto 0) = x"81"
report "Cannot extract t_sdb_repo_url from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity Failure;
return result;
end;
function f_sdb_embed_synthesis(syn : t_sdb_synthesis)
return t_sdb_record
is
variable result : t_sdb_record;
begin
result(511 downto 384) := f_string2svl(syn.syn_module_name);
result(383 downto 256) := f_string2bits(syn.syn_commit_id);
result(255 downto 192) := f_string2svl(syn.syn_tool_name);
result(191 downto 160) := syn.syn_tool_version;
result(159 downto 128) := syn.syn_date;
result(127 downto 8) := f_string2svl(syn.syn_username);
result( 7 downto 0) := x"82"; -- synthesis record
return result;
end;
function f_sdb_extract_synthesis(sdb_record : t_sdb_record)
return t_sdb_synthesis
is
variable result : t_sdb_synthesis;
begin
result.syn_module_name := f_slv2string(sdb_record(511 downto 384));
result.syn_commit_id := f_bits2string(sdb_record(383 downto 256));
result.syn_tool_name := f_slv2string(sdb_record(255 downto 192));
result.syn_tool_version := sdb_record(191 downto 160);
result.syn_date := sdb_record(159 downto 128);
result.syn_username := f_slv2string(sdb_record(127 downto 8));
assert sdb_record(7 downto 0) = x"82"
report "Cannot extract t_sdb_repo_url from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity Failure;
return result;
end;
function f_sdb_embed_bridge(bridge : t_sdb_bridge; address : t_wishbone_address)
return t_sdb_record
is
variable result : t_sdb_record;
constant first : unsigned(63 downto 0) := unsigned(bridge.sdb_component.addr_first);
constant child : unsigned(63 downto 0) := unsigned(bridge.sdb_child);
variable base : unsigned(63 downto 0) := (others => '0');
begin
base(address'length-1 downto 0) := unsigned(address);
result(511 downto 448) := std_logic_vector(base + child - first);
result(447 downto 8) := f_sdb_embed_component(bridge.sdb_component, address);
result(7 downto 0) := x"02"; -- bridge
return result;
end;
function f_sdb_extract_bridge(sdb_record : t_sdb_record)
return t_sdb_bridge
is
variable result : t_sdb_bridge;
begin
result.sdb_child := sdb_record(511 downto 448);
result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
assert sdb_record(7 downto 0) = x"02"
report "Cannot extract t_sdb_bridge from record of type " & integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity failure;
return result;
end;
function f_sdb_auto_device(device : t_sdb_device; enable : boolean := true; name: string := "")
return t_sdb_record
is
constant c_zero : t_wishbone_address := (others => '0');
variable v_device: t_sdb_device := device;
variable v_empty : t_sdb_record := (others => '0');
begin
v_empty(7 downto 0) := x"f1";
if name /= "" then
v_device.sdb_component.product.name := f_string_fix_len(name , 19, ' ', false);
end if;
if enable then
v_empty := f_sdb_embed_device(v_device, c_zero);
end if;
return v_empty;
end f_sdb_auto_device;
function f_sdb_auto_bridge(bridge : t_sdb_bridge; enable : boolean := true; name: string := "")
return t_sdb_record
is
constant c_zero : t_wishbone_address := (others => '0');
variable v_bridge: t_sdb_bridge := bridge;
variable v_empty : t_sdb_record := (others => '0');
begin
v_empty(7 downto 0) := x"f2";
if name /= "" then
v_bridge.sdb_component.product.name := f_string_fix_len(name , 19, ' ', false);
end if;
if enable then
v_empty := f_sdb_embed_bridge(v_bridge, c_zero);
end if;
return v_empty;
end f_sdb_auto_bridge;
function f_sdb_auto_msi(msi : t_sdb_msi; enable : boolean := true)
return t_sdb_record
is
constant c_zero : t_wishbone_address := (others => '0');
variable v_empty : t_sdb_record := (others => '0');
begin
v_empty(7 downto 0) := x"f3";
if enable then
return f_sdb_embed_msi(msi, c_zero);
else
return v_empty;
end if;
end f_sdb_auto_msi;
subtype t_usdb_address is unsigned(63 downto 0);
type t_usdb_address_array is array(natural range <>) of t_usdb_address;
-- We map devices by placing the smallest ones first.
-- This is guaranteed to pack the maximum number of devices in the smallest space.
-- If a device has an address != 0, we leave it alone and let the crossbar confirm
-- that the address does not cause a conflict.
function f_sdb_auto_layout_helper(records : t_sdb_record_array)
return t_usdb_address_array
is
alias c_records : t_sdb_record_array(records'length-1 downto 0) is records;
constant c_zero : t_usdb_address := (others => '0');
constant c_used_entries : natural := c_records'length + 1;
constant c_rom_entries : natural := 2**f_ceil_log2(c_used_entries);
constant c_rom_bytes : natural := c_rom_entries * c_sdb_device_length / 8;
variable v_component : t_sdb_component;
variable v_sizes : t_usdb_address_array(c_records'length downto 0);
variable v_address : t_usdb_address_array(c_records'length downto 0);
variable v_bus_map : std_logic_vector(c_records'length downto 0) := (others => '0');
variable v_bus_cursor: unsigned(63 downto 0) := (others => '0');
variable v_msi_map : std_logic_vector(c_records'length downto 0) := (others => '0');
variable v_msi_cursor: unsigned(63 downto 0) := (others => '0');
variable v_increment : unsigned(63 downto 0) := (others => '0');
variable v_type : std_logic_vector(7 downto 0);
begin
-- First, extract the length of the devices, ignoring those not to be mapped
for i in c_records'range loop
v_component := f_sdb_extract_component(c_records(i)(447 downto 8));
v_sizes(i) := unsigned(v_component.addr_last);
v_address(i) := unsigned(v_component.addr_first);
-- Silently round up to a power of two; the crossbar will give a warning for us
for j in 62 downto 0 loop
v_sizes(i)(j) := v_sizes(i)(j+1) or v_sizes(i)(j);
end loop;
-- Only map devices/bridges at address zero
if v_address(i) = c_zero then
v_type := c_records(i)(7 downto 0);
case v_type is
when x"01" => v_bus_map(i) := '1';
when x"02" => v_bus_map(i) := '1';
when x"03" => v_msi_map(i) := '1';
when others => null;
end case;
end if;
end loop;
-- Assign the SDB record a spot as well
v_address(c_records'length) := (others => '0');
v_sizes(c_records'length) := to_unsigned(c_rom_bytes-1, 64);
v_bus_map(c_records'length) := '1';
-- Start assigning addresses
for j in 0 to 63 loop
v_increment := (others => '0');
v_increment(j) := '1';
for i in 0 to c_records'length loop
if v_bus_map(i) = '1' and v_sizes(i)(j) = '0' then
v_bus_map(i) := '0';
v_address(i) := v_bus_cursor;
v_bus_cursor := v_bus_cursor + v_increment;
end if;
if v_msi_map(i) = '1' and v_sizes(i)(j) = '0' then
v_msi_map(i) := '0';
v_address(i) := v_msi_cursor;
v_msi_cursor := v_msi_cursor + v_increment;
end if;
end loop;
-- Round up to the next required alignment
if v_bus_cursor(j) = '1' then
v_bus_cursor := v_bus_cursor + v_increment;
end if;
if v_msi_cursor(j) = '1' then
v_msi_cursor := v_msi_cursor + v_increment;
end if;
end loop;
return v_address;
end f_sdb_auto_layout_helper;
function f_sdb_auto_layout(records : t_sdb_record_array)
return t_sdb_record_array
is
alias c_records : t_sdb_record_array(records'length-1 downto 0) is records;
variable v_typ : std_logic_vector(7 downto 0);
variable v_result : t_sdb_record_array(c_records'range) := c_records;
constant c_address : t_usdb_address_array := f_sdb_auto_layout_helper(c_records);
variable v_address : t_wishbone_address;
begin
-- Put the addresses into the mapping
for i in v_result'range loop
v_typ := c_records(i)(7 downto 0);
v_address := std_logic_vector(c_address(i)(t_wishbone_address'range));
case v_typ is
when x"01" => v_result(i) := f_sdb_embed_device(f_sdb_extract_device(v_result(i)), v_address);
when x"02" => v_result(i) := f_sdb_embed_bridge(f_sdb_extract_bridge(v_result(i)), v_address);
when x"03" => v_result(i) := f_sdb_embed_msi (f_sdb_extract_msi (v_result(i)), v_address);
when others => null;
end case;
end loop;
return v_result;
end f_sdb_auto_layout;
function f_sdb_auto_layout(slaves : t_sdb_record_array; masters : t_sdb_record_array)
return t_sdb_record_array
is begin
return f_sdb_auto_layout(masters & slaves);
end f_sdb_auto_layout;
function f_sdb_auto_sdb(records : t_sdb_record_array)
return t_wishbone_address
is
alias c_records : t_sdb_record_array(records'length-1 downto 0) is records;
constant c_address : t_usdb_address_array(c_records'length downto 0) := f_sdb_auto_layout_helper(c_records);
begin
return std_logic_vector(c_address(c_records'length)(t_wishbone_address'range));
end f_sdb_auto_sdb;
function f_sdb_auto_sdb(slaves : t_sdb_record_array; masters : t_sdb_record_array)
return t_wishbone_address
is begin
return f_sdb_auto_sdb(masters & slaves);
end f_sdb_auto_sdb;
--**************************************************************************************************************************--
-- START MAT's NEW FUNCTIONS FROM 18th Oct 2013
------------------------------------------------------------------------------------------------------------------------------
function f_sdb_create_array(g_enum_dev_id : boolean := false;
g_dev_id_offs : natural := 0;
g_enum_dev_name : boolean := false;
g_dev_name_offs : natural := 0;
device : t_sdb_device;
instances : natural := 1)
return t_sdb_record_array is
variable result : t_sdb_record_array(instances-1 downto 0);
variable i,j, pos : natural;
variable dev, newdev : t_sdb_device;
variable serial_no : string(1 to 3);
variable text_possible : boolean := false;
begin
dev := device;
report "### Creating " & integer'image(instances) & " x " & dev.sdb_component.product.name
severity note;
for i in 0 to instances-1 loop
newdev := dev;
if(g_enum_dev_id) then
dev.sdb_component.product.device_id :=
std_logic_vector( unsigned(dev.sdb_component.product.device_id)
+ to_unsigned(i+g_dev_id_offs, dev.sdb_component.product.device_id'length));
end if;
if(g_enum_dev_name) then
-- find end of name
for j in dev.sdb_component.product.name'length downto 1 loop
if(dev.sdb_component.product.name(j) /= ' ') then
pos := j;
exit;
end if;
end loop;
-- convert i+g_dev_name_offs to string
serial_no := f_string_fix_len(integer'image(i+g_dev_name_offs), serial_no'length);
report "### Now: " & serial_no & " of " & dev.sdb_component.product.name severity note;
-- check if space is sufficient
assert (serial_no'length+1 <= dev.sdb_component.product.name'length - pos)
report "Not enough space in namestring of sdb_device " & dev.sdb_component.product.name
& " to add serial number " & serial_no & ". Space available " &
integer'image(dev.sdb_component.product.name'length-pos-1) & ", required "
& integer'image(serial_no'length+1)
severity Failure;
end if;
if(g_enum_dev_name) then
newdev.sdb_component.product.name(pos+1) := '_';
for j in 1 to serial_no'length loop
newdev.sdb_component.product.name(pos+1+j) := serial_no(j);
end loop;
end if;
-- insert
report "### to: " & newdev.sdb_component.product.name severity note;
result(i) := f_sdb_embed_device(newdev, (others=>'0'));
end loop;
return result;
end f_sdb_create_array;
function f_sdb_join_arrays(a : t_sdb_record_array; b : t_sdb_record_array) return t_sdb_record_array is
variable result : t_sdb_record_array(a'length+b'length-1 downto 0);
variable i : natural;
begin
for i in 0 to a'left loop
result(i) := a(i);
end loop;
for i in 0 to b'left loop
result(i+a'length) := b(i);
end loop;
return result;
end f_sdb_join_arrays;
function f_sdb_extract_base_addr(sdb_record : t_sdb_record) return std_logic_vector is
begin
return sdb_record(447 downto 384);
end f_sdb_extract_base_addr;
function f_sdb_extract_end_addr(sdb_record : t_sdb_record) return std_logic_vector is
begin
return sdb_record(383 downto 320);
end f_sdb_extract_end_addr;
function f_align_addr_offset(offs : unsigned; this_rng : unsigned; prev_rng : unsigned)
return unsigned is
variable this_pow, prev_pow : natural;
variable start, env, result : unsigned(63 downto 0) := (others => '0');
begin
start(offs'left downto 0) := offs;
--calculate address envelopes (next power of 2) for previous and this component and choose the larger one
this_pow := f_hot_to_bin(std_logic_vector(this_rng));
prev_pow := f_hot_to_bin(std_logic_vector(prev_rng));
-- no max(). thank you very much, std_numeric :-/
if(this_pow >= prev_pow) then
env(this_pow) := '1';
else
env(prev_pow) := '1';
end if;
--round up to the next multiple of the envelope...
if(prev_rng /= 0) then
result := start + env - (start mod env);
else
result := start; --...except for first element, result is start.
end if;
return result;
end f_align_addr_offset;
-- generates aligned address map for an sdb_record_array, accepts optional start offset
function f_sdb_automap_array(sdb_array : t_sdb_record_array; start_offset : t_wishbone_address := (others => '0'))
return t_sdb_record_array is
constant len : natural := sdb_array'length;
variable this_rng : unsigned(63 downto 0) := (others => '0');
variable prev_rng : unsigned(63 downto 0) := (others => '0');
variable prev_offs : unsigned(63 downto 0) := (others => '0');
variable this_offs : unsigned(63 downto 0) := (others => '0');
variable device : t_sdb_device;
variable bridge : t_sdb_bridge;
variable sdb_type : std_logic_vector(7 downto 0);
variable i : natural;
variable result : t_sdb_record_array(sdb_array'length-1 downto 0); -- last
begin
prev_offs(start_offset'left downto 0) := unsigned(start_offset);
--traverse the array
for i in 0 to len-1 loop
-- find the fitting extraction function by evaling the type byte.
-- could also use the component, but it's safer to use Wes' embed and extract functions.
sdb_type := sdb_array(i)(7 downto 0);
case sdb_type is
--device
when x"01" => device := f_sdb_extract_device(sdb_array(i));
this_rng := unsigned(device.sdb_component.addr_last) - unsigned(device.sdb_component.addr_first);
this_offs := f_align_addr_offset(prev_offs, this_rng, prev_rng);
result(i) := f_sdb_embed_device(device, std_logic_vector(this_offs(31 downto 0)));
--bridge
when x"02" => bridge := f_sdb_extract_bridge(sdb_array(i));
this_rng := unsigned(bridge.sdb_component.addr_last) - unsigned(bridge.sdb_component.addr_first);
this_offs := f_align_addr_offset(prev_offs, this_rng, prev_rng);
result(i) := f_sdb_embed_bridge(bridge, std_logic_vector(this_offs(31 downto 0)) );
--other
when others => result(i) := sdb_array(i);
end case;
-- doesnt hurt because this_* doesnt change if its not a device or bridge
prev_rng := this_rng;
prev_offs := this_offs;
end loop;
report "##* " & integer'image(sdb_array'length) & " Elements, last address: " & f_bits2string(std_logic_vector(this_offs+this_rng)) severity Note;
return result;
end f_sdb_automap_array;
-- find place for sdb rom on crossbar and return address. try to put it in an address gap.
function f_sdb_create_rom_addr(sdb_array : t_sdb_record_array) return t_wishbone_address is
constant len : natural := sdb_array'length;
constant rom_bytes : natural := (2**f_ceil_log2(sdb_array'length + 1)) * (c_sdb_device_length / 8);
variable result : t_wishbone_address := (others => '0');
variable this_base, this_end : unsigned(63 downto 0) := (others => '0');
variable prev_base, prev_end : unsigned(63 downto 0) := (others => '0');
variable rom_base : unsigned(63 downto 0) := (others => '0');
variable sdb_type : std_logic_vector(7 downto 0);
begin
--traverse the array
for i in 0 to len-1 loop
sdb_type := sdb_array(i)(7 downto 0);
if(sdb_type = x"01" or sdb_type = x"02") then
-- get
this_base := unsigned(f_sdb_extract_base_addr(sdb_array(i)));
this_end := unsigned(f_sdb_extract_end_addr(sdb_array(i)));
if(unsigned(result) = 0) then
rom_base := f_align_addr_offset(prev_base, to_unsigned(rom_bytes-1, 64), (prev_end-prev_base));
if(rom_base + to_unsigned(rom_bytes, 64) <= this_base) then
result := std_logic_vector(rom_base(t_wishbone_address'left downto 0));
end if;
end if;
prev_base := this_base;
prev_end := this_end;
end if;
end loop;
-- if there was no gap to fit the sdb rom, place it at the end
if(unsigned(result) = 0) then
result := std_logic_vector(f_align_addr_offset(this_base, to_unsigned(rom_bytes-1, 64),
this_end-this_base)(t_wishbone_address'left downto 0));
end if;
return result;
end f_sdb_create_rom_addr;
------------------------------------------------------------------------------------------------------------------------------
-- END MAT's NEW FUNCTIONS FROM 18th Oct 2013
------------------------------------------------------------------------------------------------------------------------------
function f_sdb_bus_end(
g_wraparound : boolean;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address;
msi : boolean) return unsigned
is
alias c_layout : t_sdb_record_array(g_layout'length-1 downto 0) is g_layout;
-- How much space does the ROM need?
constant c_used_entries : natural := c_layout'length + 1;
constant c_rom_entries : natural := 2**f_ceil_log2(c_used_entries); -- next power of 2
constant c_sdb_bytes : natural := c_sdb_device_length / 8;
constant c_rom_bytes : natural := c_rom_entries * c_sdb_bytes;
variable result : unsigned(63 downto 0) := (others => '0');
variable typ : std_logic_vector(7 downto 0);
variable last : unsigned(63 downto 0);
begin
if not msi then
-- The ROM will be an addressed slave as well
result := (others => '0');
result(g_sdb_addr'range) := unsigned(g_sdb_addr);
result := result + to_unsigned(c_rom_bytes, 64) - 1;
end if;
for i in c_layout'range loop
typ := c_layout(i)(7 downto 0);
last := unsigned(f_sdb_extract_component(c_layout(i)(447 downto 8)).addr_last);
case typ is
when x"01" => if not msi and last > result then result := last; end if;
when x"02" => if not msi and last > result then result := last; end if;
when x"03" => if msi and last > result then result := last; end if;
when others => null;
end case;
end loop;
-- round result up to a power of two -1
for i in 62 downto 0 loop
result(i) := result(i) or result(i+1);
end loop;
if not g_wraparound then
result := (others => '0');
for i in 0 to c_wishbone_address_width-1 loop
result(i) := '1';
end loop;
end if;
return result;
end f_sdb_bus_end;
function f_xwb_bridge_manual_sdb(
g_size : t_wishbone_address;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge
is
variable result : t_sdb_bridge;
begin
result.sdb_child := (others => '0');
result.sdb_child(c_wishbone_address_width-1 downto 0) := g_sdb_addr;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := (others => '0');
result.sdb_component.addr_last(c_wishbone_address_width-1 downto 0) := g_size;
result.sdb_component.product.vendor_id := x"0000000000000651"; -- GSI
result.sdb_component.product.device_id := x"eef0b198";
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120511";
result.sdb_component.product.name := "WB4-Bridge-GSI ";
return result;
end f_xwb_bridge_manual_sdb;
function f_xwb_bridge_layout_sdb( -- determine bus size from layout
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge
is
variable address : t_wishbone_address;
begin
address := std_logic_vector(f_sdb_bus_end(g_wraparound, g_layout, g_sdb_addr, false)(address'range));
return f_xwb_bridge_manual_sdb(address, g_sdb_addr);
end f_xwb_bridge_layout_sdb;
function f_xwb_msi_manual_sdb(
g_size : t_wishbone_address) return t_sdb_msi
is
variable result : t_sdb_msi;
begin
result.wbd_endian := '0';
result.wbd_width := x"7";
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := (others => '0');
result.sdb_component.addr_last(c_wishbone_address_width-1 downto 0) := g_size;
result.sdb_component.product.vendor_id := x"0000000000000651"; -- GSI
result.sdb_component.product.device_id := x"aa7bfb3c";
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20160422";
result.sdb_component.product.name := "WB4-MSI-Bridge-GSI ";
return result;
end f_xwb_msi_manual_sdb;
function f_xwb_msi_layout_sdb( -- determine MSI size from layout
g_layout : t_sdb_record_array) return t_sdb_msi
is
constant zero : t_wishbone_address := (others => '0');
variable address : t_wishbone_address;
begin
address := std_logic_vector(f_sdb_bus_end(true, g_layout, zero, true)(address'range));
return f_xwb_msi_manual_sdb(address);
end f_xwb_msi_layout_sdb;
function f_xwb_dpram(g_size : natural) return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := x"0001"; -- RAM device
result.abi_ver_major := x"01";
result.abi_ver_minor := x"00";
result.wbd_width := x"7"; -- 32/16/8-bit supported
result.wbd_endian := c_sdb_endian_big;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := std_logic_vector(to_unsigned(g_size*4-1, 64));
result.sdb_component.product.vendor_id := x"000000000000CE42"; -- CERN
result.sdb_component.product.device_id := x"66cfeb52";
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120305";
result.sdb_component.product.name := "WB4-BlockRAM ";
return result;
end f_xwb_dpram;
function f_bits2string(s : std_logic_vector) return string is
--- extend length to full hex nibble
variable result : string((s'length+7)/4 downto 1);
variable s_norm : std_logic_vector(result'length*4-1 downto 0) := (others=>'0');
variable cut : natural;
variable nibble: std_logic_vector(3 downto 0);
constant len : natural := result'length;
begin
s_norm(s'length-1 downto 0) := s;
for i in len-1 downto 0 loop
nibble := s_norm(i*4+3 downto i*4);
case nibble is
when "0000" => result(i+1) := '0';
when "0001" => result(i+1) := '1';
when "0010" => result(i+1) := '2';
when "0011" => result(i+1) := '3';
when "0100" => result(i+1) := '4';
when "0101" => result(i+1) := '5';
when "0110" => result(i+1) := '6';
when "0111" => result(i+1) := '7';
when "1000" => result(i+1) := '8';
when "1001" => result(i+1) := '9';
when "1010" => result(i+1) := 'a';
when "1011" => result(i+1) := 'b';
when "1100" => result(i+1) := 'c';
when "1101" => result(i+1) := 'd';
when "1110" => result(i+1) := 'e';
when "1111" => result(i+1) := 'f';
when others => result(i+1) := 'X';
end case;
end loop;
-- trim leading 0s
strip : for i in result'length downto 1 loop
cut := i;
exit strip when result(i) /= '0';
end loop;
return "0x" & result(cut downto 1);
end f_bits2string;
-- Converts string (hex number, without leading 0x) to std_logic_vector
function f_string2bits(s : string) return std_logic_vector is
constant len : natural := s'length;
variable slv : std_logic_vector(s'length*4-1 downto 0);
variable nibble : std_logic_vector(3 downto 0);
begin
for i in 0 to len-1 loop
case s(i+1) is
when '0' => nibble := X"0";
when '1' => nibble := X"1";
when '2' => nibble := X"2";
when '3' => nibble := X"3";
when '4' => nibble := X"4";
when '5' => nibble := X"5";
when '6' => nibble := X"6";
when '7' => nibble := X"7";
when '8' => nibble := X"8";
when '9' => nibble := X"9";
when 'a' => nibble := X"A";
when 'A' => nibble := X"A";
when 'b' => nibble := X"B";
when 'B' => nibble := X"B";
when 'c' => nibble := X"C";
when 'C' => nibble := X"C";
when 'd' => nibble := X"D";
when 'D' => nibble := X"D";
when 'e' => nibble := X"E";
when 'E' => nibble := X"E";
when 'f' => nibble := X"F";
when 'F' => nibble := X"F";
when others => nibble := "XXXX";
end case;
if s'ascending then
slv(slv'length-(i*4)-1 downto slv'length-(i+1)*4) := nibble;
else
slv(((i+1)*4)-1 downto i*4) := nibble;
end if;
end loop;
return slv;
end f_string2bits;
-- Converts string to ascii (std_logic_vector)
function f_string2svl (s : string) return std_logic_vector is
constant len : natural := s'length;
variable slv : std_logic_vector((s'length * 8) - 1 downto 0);
begin
for i in 0 to len-1 loop
slv(slv'high-i*8 downto (slv'high-7)-i*8) :=
std_logic_vector(to_unsigned(character'pos(s(i+1)), 8));
end loop;
return slv;
end f_string2svl;
-- Converts ascii (std_logic_vector) to string
function f_slv2string (slv : std_logic_vector) return string is
constant len : natural := slv'length;
variable s : string(1 to slv'length/8);
begin
for i in 0 to (len/8)-1 loop
s(i+1) := character'val(to_integer(unsigned(slv(slv'high-i*8 downto (slv'high-7)-i*8))));
end loop;
return s;
end f_slv2string;
-- pads a string of unknown length to a given length (useful for integer'image)
function f_string_fix_len ( s : string; ret_len : natural := 10; fill_char : character := '0'; justify_right : boolean := true ) return string is
variable ret_v : string (1 to ret_len);
constant pad_len : integer := ret_len - s'length ;
variable pad_v : string (1 to abs(pad_len));
begin
if pad_len < 1 then
ret_v := s(ret_v'range);
else
pad_v := (others => fill_char);
if justify_right then
ret_v := pad_v & s;
else
ret_v := s & pad_v ;
end if;
end if;
return ret_v;
end f_string_fix_len;
-- do not synthesize
function f_hot_to_bin(x : std_logic_vector) return natural is
variable rv : natural;
begin
rv := 0;
-- if there are few ones set in _x_ then the most significant will be
-- translated to bin
for i in 0 to x'left loop
if x(i) = '1' then
rv := i+1;
end if;
end loop;
return rv;
end function;
function f_wb_spi_flash_sdb(g_bits : natural) return t_sdb_device is
variable result : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"02",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000ffffff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"5cf12a1c",
version => x"00000002",
date => x"20140417",
name => "SPI-FLASH-16M-MMAP ")));
begin
result.sdb_component.addr_last := std_logic_vector(to_unsigned(2**g_bits-1, 64));
return result;
end f_wb_spi_flash_sdb;
end wishbone_pkg;
|
<reponame>afaber999/Altera_board_tutorial<filename>SegCounter/SegCounterTop.vhd<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SegCounterTop is
port (
clk : in std_logic;
led7 : out std_logic_vector(7 downto 0);
led7s : out std_logic_vector(7 downto 0)
);
end SegCounterTop;
architecture RTL of SegCounterTop is
signal r_clk1Hz : std_logic := '0';
signal r_clk762Hz : std_logic := '0';
signal r_acounter : std_logic_vector(15 downto 0) := x"FACE";
signal r_bcounter : std_logic_vector(15 downto 0) := x"BABE";
begin
-- An instance of T15_Mux with architecture rtl
INST_SEGCOUNTER : entity work.SegCounter(rtl) port map(
i_clk => r_clk762Hz,
i_digit_0 => r_acounter(15 downto 12),
i_digit_1 => r_acounter(11 downto 8),
i_digit_2 => r_acounter( 7 downto 4),
i_digit_3 => r_acounter( 3 downto 0),
i_digit_4 => r_bcounter(15 downto 12),
i_digit_5 => r_bcounter(11 downto 8),
i_digit_6 => r_bcounter( 7 downto 4),
i_digit_7 => r_bcounter( 3 downto 0),
o_led7 => led7,
o_led7s => led7s
);
-- Process to generate 7 clock, bases on 50 Mhz system clock
P_CLK762HZ : process (clk)
variable counter_762Hz : INTEGER range 0 to ((2**15)-1) := 0;
begin
if rising_edge(clk) then
if counter_762Hz = ((2**15)-1) then
r_clk762Hz <= not r_clk762Hz;
counter_762Hz := 0;
else
counter_762Hz := counter_762Hz + 1;
end if;
end if;
end process P_CLK762HZ;
P2 : process (r_clk762Hz)
variable counter_1Hz : INTEGER range 0 to ((762/2)-1) := 0;
begin
if rising_edge(r_clk762Hz) then
if counter_1Hz = ((762/2)-1) then
r_clk1Hz <= not r_clk1Hz;
counter_1Hz := 0;
else
counter_1Hz := counter_1Hz + 1;
end if;
end if;
end process P2;
P2b : process (r_clk1Hz)
begin
if rising_edge(r_clk1Hz) then
if r_acounter = x"FFFF" then
r_acounter <= (others => '0');
else
r_acounter <= std_logic_vector( unsigned(r_acounter) + 1 );
end if;
if r_bcounter = x"0000" then
r_bcounter <= x"FFFF";
else
r_bcounter <= std_logic_vector( unsigned(r_bcounter) - 1 );
end if;
end if;
end process P2b;
end RTL;
|
<reponame>PFigs/portfolio<filename>Advanced Computer Architecture (VHDL)/CODE/16 Bit RISC with Pipeline/mask_addr.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:08:27 05/12/2010
-- Design Name:
-- Module Name: mask_addr - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mask_addr is
Port ( I : in STD_LOGIC_VECTOR (15 downto 0);
Z : out STD_LOGIC_VECTOR (15 downto 0));
end mask_addr;
architecture Behavioral of mask_addr is
begin
Z(0) <= I(0);
Z(1) <= I(1);
Z(2) <= I(2);
Z(3) <= I(3);
Z(4) <= I(4);
Z(5) <= I(5);
Z(6) <= I(6);
Z(7) <= I(7);
Z(8) <= I(8);
Z(9) <= I(9);
Z(10) <= '0';
Z(11) <= '0';
Z(12) <= '0';
Z(13) <= '0';
Z(14) <= '0';
Z(15) <= '0';
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's SN76489AN.
--
-- $Id: sn76489_latch_ctrl.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
--
-- Latch Control Unit
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2005, 2006, <NAME> (<EMAIL>)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity sn76489_latch_ctrl is
port (
clock_i : in std_logic;
clk_en_i : in boolean;
res_n_i : in std_logic;
ce_n_i : in std_logic;
we_n_i : in std_logic;
d_i : in std_logic_vector(0 to 7);
ready_o : out std_logic;
tone1_we_o : out boolean;
tone2_we_o : out boolean;
tone3_we_o : out boolean;
noise_we_o : out boolean;
r2_o : out std_logic
);
end sn76489_latch_ctrl;
library ieee;
use ieee.numeric_std.all;
architecture rtl of sn76489_latch_ctrl is
signal reg_q : std_logic_vector(0 to 2);
signal we_q : boolean;
signal ready_q : std_logic;
begin
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements.
--
seq: process (clock_i, res_n_i)
begin
if res_n_i = '0' then
reg_q <= (others => '0');
we_q <= false;
ready_q <= '0';
elsif clock_i'event and clock_i = '1' then
-- READY Flag Output ----------------------------------------------------
if ready_q = '0' and we_q then
if clk_en_i then
-- assert READY when write access happened
ready_q <= '1';
end if;
elsif ce_n_i = '1' then
-- deassert READY when access has finished
ready_q <= '0';
end if;
-- Register Selection ---------------------------------------------------
if ce_n_i = '0' and we_n_i = '0' then
if clk_en_i then
if d_i(0) = '1' then
reg_q <= d_i(1 to 3);
end if;
we_q <= true;
end if;
else
we_q <= false;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
tone1_we_o <= reg_q(0 to 1) = "00" and we_q;
tone2_we_o <= reg_q(0 to 1) = "01" and we_q;
tone3_we_o <= reg_q(0 to 1) = "10" and we_q;
noise_we_o <= reg_q(0 to 1) = "11" and we_q;
r2_o <= reg_q(2);
ready_o <= ready_q
when ce_n_i = '0' else
'1';
end rtl;
|
<filename>burst_mode/hw/hdl/swap.vhd
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity swap is
port
(
-- avalon bus
Clk : in std_logic;
nReset : in std_logic;
-- slave avalon
sAddress : in std_logic_vector(2 downto 0);
sChipSelect : in std_logic;
sWrite : in std_logic;
sWriteData : in std_logic_vector(31 downto 0);
sRead : in std_logic;
sReadData : out std_logic_vector(31 downto 0);
-- master avalon
mAddress : out std_logic_vector(31 downto 0);
mByteEnable : out std_logic_vector(3 downto 0);
mWrite : out std_logic;
mWriteData : out std_logic_vector(31 downto 0);
mRead : out std_logic;
mReadData : in std_logic_vector(31 downto 0);
mWaitRequest : in std_logic
);
end swap;
architecture swap_logic of swap is
signal RegAddStart, RegLgt, Result, ResultRegAddStart: std_logic_vector(31 downto 0);
signal DataRd : std_logic_vector(31 downto 0);
signal start, finish : std_logic;
signal CntAdd, CntLgt, CntResultAdd : unsigned(31 downto 0);
type states_t is (IDLE, LOAD_PARAMETERS, RD_ACC, WAIT_RD, CALCULATE, SEND_WRITE_REQUEST, WAIT_FOR_WRITE);
signal state : states_t;
begin
slaveWriteProcess : Process(Clk, nReset)
begin
if nReset='0' then
RegAddStart <= (others => '0');
RegLgt <= (others => '0');
start <= '0';
ResultRegAddStart <= (others => '0');
elsif rising_edge(Clk) then
start <= '0'; -- in FSM, there is no zeroing Start, by doing that here Start is an impuls
if sChipSelect = '1' and sWrite = '1' then
case sAddress is
when "000" => RegAddStart <= sWriteData;
when "001" => RegLgt <= sWriteData;
when "010" => start <= sWriteData(0);
when "011" => ResultRegAddStart <= sWriteData;
when others => null;
end case;
end if;
end if;
end process slaveWriteProcess;
slaveReadProcess : process(Clk)
begin
if rising_edge(Clk) then
if sChipSelect = '1' and sRead = '1' then
sReadData <= (others => '0');
case sAddress is
when "000" => sReadData <= RegAddStart;
when "001" => sReadData <= RegLgt;
when "010" => sReadData(0) <= start;
when "011" => sReadData <= ResultRegAddStart;
when "101" => sReadData(0) <= finish;
when others => null;
end case;
end if;
end if;
end process slaveReadProcess;
transitionMasterFSM : process(Clk, nReset)
begin
if nReset = '0' then
finish <= '0';
CntAdd <= (others => '0');
CntLgt <= (others => '0');
CntResultAdd <= (others => '0');
Result <= (others => '0');
elsif rising_edge(Clk) then
case state is
when IDLE =>
-- init master
mAddress <= (others => '0');
mByteEnable <= "0000";
mWrite <= '0';
mRead <= '0';
if start = '1' then
state <= LOAD_PARAMETERS;
finish <= '0';
end if;
when LOAD_PARAMETERS =>
CntAdd <= unsigned(RegAddStart);
CntLgt <= unsigned(RegLgt);
CntResultAdd <= unsigned(ResultRegAddStart);
result <= (others => '0');
state <= RD_ACC;
when RD_ACC =>
mAddress <= std_logic_vector(CntAdd); -- from that address data will be read directly from the memory
mByteEnable <= "1111";
mRead <= '1';
mWrite <= '0';
state <= WAIT_RD;
when WAIT_RD =>
if mWaitRequest = '0' then
DataRd <= mReadData;
mRead <= '0';
state <= CALCULATE;
end if;
when CALCULATE =>
-- 0x12345678 => 0x786A2C12
Result <= DataRd;
state <= SEND_WRITE_REQUEST;
when SEND_WRITE_REQUEST =>
mAddress <= std_logic_vector(CntResultAdd);
mByteEnable <= "1111"; -- can be all the 111, because we want to write/read all bytes
mWrite <= '1';
mWriteData <= Result;
state <= WAIT_FOR_WRITE;
when WAIT_FOR_WRITE =>
if mWaitRequest = '0' then
mWrite <= '0'; -- all the time
if CntLgt > 0 then
CntAdd <= CntAdd + 174;--4*44
CntResultAdd <= CntResultAdd + 174;
CntLgt <= CntLgt - 1;
state <= RD_ACC; -- if write only here it means that when I go to the IDLE I will still have write at 1
else -- and for 1 cc more what was on the bus will be written into the memory. If it was trush, then that
-- trash will be written as well.
mByteEnable <= "0000";
finish <= '1';
state <= IDLE;
end if;
end if;
when others =>
state <= IDLE;
end case;
end if;
end process transitionMasterFSM;
end swap_logic;
|
--------------------------------------------------------------------------------
--
-- FileName: i2c_master.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/01/2012 <NAME>
-- Initial Public Release
-- Version 2.0 06/20/2014 <NAME>
-- Added ability to interface with different slaves in the same transaction
-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
-- Corrected timing of when ack_error signal clears
-- Version 2.1 10/21/2014 <NAME>
-- Replaced gated clock with clock enable
-- Adjusted timing of SCL during start and stop conditions
-- Version 2.2 02/05/2015 <NAME>
-- Corrected small SDA glitch introduced in version 2.1
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY i2c_master IS
GENERIC(
input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 100_000); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC; --serial clock output of i2c bus
byte_counter : OUT INTEGER RANGE 0 TO 7; --how many bytes have been sent or received
number_of_bytes : IN INTEGER RANGE 0 TO 7); --how many bytes should be sent or received in tota
END i2c_master;
ARCHITECTURE logic OF i2c_master IS
CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
SIGNAL state : machine; --state machine
SIGNAL data_clk : STD_LOGIC; --data clock for sda
SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
SIGNAL counter : INTEGER RANGE 0 TO 7 := 0; --tracks bit number in transaction
BEGIN
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
PROCESS(clk, reset_n)
VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
BEGIN
IF(reset_n = '0') THEN --reset asserted
stretch <= '0';
count := 0;
ELSIF(clk'EVENT AND clk = '1') THEN
data_clk_prev <= data_clk; --store previous value of data clock
IF(count = divider*4-1) THEN --end of timing cycle
count := 0; --reset timer
ELSIF(stretch = '0') THEN --clock stretching from slave not detected
count := count + 1; --continue clock generation timing
END IF;
CASE count IS
WHEN 0 TO divider-1 => --first 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '0';
WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking
scl_clk <= '0';
data_clk <= '1';
WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
scl_clk <= '1'; --release scl
IF(scl = '0') THEN --detect if slave is stretching clock
stretch <= '1';
ELSE
stretch <= '0';
END IF;
data_clk <= '1';
WHEN OTHERS => --last 1/4 cycle of clocking
scl_clk <= '1';
data_clk <= '0';
END CASE;
END IF;
END PROCESS;
--state machine and writing to sda during scl low (data_clk rising edge)
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_ena <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
ack_error <= '0'; --clear acknowledge error flag
bit_cnt <= 7; --restarts data bit counter
counter <= 0;
ELSIF(clk'EVENT AND clk = '1') THEN
IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
CASE state IS
WHEN ready => --idle state
IF(ena = '1') THEN --transaction requested
busy <= '1'; --flag busy
IF(rw = '1') THEN
addr_rw <= addr & (not rw); --we need to write the register we want to read from first
ELSE
addr_rw <= addr & rw; --collect requested slave address and command
END IF;
data_tx <= data_wr(7 downto 0) ; --collect requested data to write
state <= start; --go to start bit
ELSE --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
END IF;
counter <= 0; --reset byte counter
WHEN start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
sda_int <= addr_rw(bit_cnt); --set first address bit to bus
state <= command; --go to command
WHEN command => --address and command byte of transaction
IF(bit_cnt = 0) THEN --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
ELSE --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
state <= command; --continue with command
END IF;
WHEN slv_ack1 => --slave acknowledge bit (command)
IF(addr_rw(0) = '0') THEN --write command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --read command
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
END IF;
WHEN wr => --write byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --write byte transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack2; --go to slave acknowledge (write)
counter <= counter+1; --increase byte counter
ELSE --next clock cycle of write state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= data_tx(bit_cnt-1); --write next bit to bus
state <= wr; --continue writing
END IF;
WHEN rd => --read byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --read byte receive finished
IF( counter < number_of_bytes-1 AND addr_rw = addr & rw ) THEN --continuing with another read at same address
sda_int <= '0'; --acknowledge the byte has been received
ELSE --stopping or continuing with a write
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
END IF;
bit_cnt <= 7; --reset bit counter for "byte" states
case counter is --output received data (MSB first)
when 4 => data_rd(7 downto 0) <= data_rx;
when 3 => data_rd(15 downto 8) <= data_rx;
when 2 => data_rd(23 downto 16) <= data_rx;
when 1 => data_rd(31 downto 24) <= data_rx;
when others => NULL;
end case;
state <= mstr_ack; --go to master acknowledge
counter <= counter+1; --increase byte counter
ELSE --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
END IF;
WHEN slv_ack2 => --slave acknowledge bit (write)
IF( counter < number_of_bytes ) THEN --continue transaction
busy <= '0'; --continue is accepted
case counter is --collect requested data to write (MSB first)
when 3 => data_tx <= data_wr(7 downto 0) ;
when 2 => data_tx <= data_wr(15 downto 8);
when 1 => data_tx <= data_wr(23 downto 16);
when 0 => data_tx <= data_wr(31 downto 24);
when others => NULL;
end case;
IF(addr_rw = addr & rw) THEN --continue transaction with another write
sda_int <= data_wr(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --continue transaction with a read or new slave
state <= start; --go to repeated start
addr_rw <= addr & rw; --here we use the true rw value (in case of read = 1)
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN mstr_ack => --master acknowledge bit after a read
IF( counter < number_of_bytes ) THEN --continue transaction
busy <= '0'; --continue is accepted and data received is available on bus
addr_rw <= addr & rw; --collect requested slave address and command
case counter is --collect requested data to write (MSB first)
when 3 => data_tx <= data_wr(7 downto 0) ;
when 2 => data_tx <= data_wr(15 downto 8);
when 1 => data_tx <= data_wr(23 downto 16);
when 0 => data_tx <= data_wr(31 downto 24);
when others => NULL;
end case;
IF(addr_rw = addr & rw) THEN --continue transaction with another read
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
ELSE --continue transaction with a write or new slave
state <= start; --repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN stop => --stop bit of transaction
busy <= '0'; --unflag busy
state <= ready; --go to idle state
counter <= number_of_bytes;
END CASE;
ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
CASE state IS
WHEN start =>
IF(scl_ena = '0') THEN --starting new transaction
scl_ena <= '1'; --enable scl output
ack_error <= '0'; --reset acknowledge error output
END IF;
WHEN slv_ack1 => --receiving slave acknowledge (command)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN rd => --receiving slave data
data_rx(bit_cnt) <= sda; --receive current slave data bit
WHEN slv_ack2 => --receiving slave acknowledge (write)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN stop =>
scl_ena <= '0'; --disable scl
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS;
--set sda output
WITH state SELECT
sda_ena_n <= data_clk_prev WHEN start, --generate start condition
NOT data_clk_prev WHEN stop, --generate stop condition
sda_int WHEN OTHERS; --set to internal sda signal
--set scl and sda outputs
scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
byte_counter <= counter;
END logic;
|
<reponame>ashoward/ipbus-firmware
---------------------------------------------------------------------------------
--
-- Copyright 2017 - <NAME>leton Laboratory and University of Bristol
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- - - -
--
-- Additional information about ipbus-firmare and the list of ipbus-firmware
-- contacts are available at
--
-- https://ipbus.web.cern.ch/ipbus
--
---------------------------------------------------------------------------------
-- <NAME>, June 2018
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ipbus_transport_multibuffer_tx_dpram is
generic (
-- corresponds to 32b data
ADDRWIDTH : natural
);
port (
clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(ADDRWIDTH - 1 downto 0);
dia : in std_logic_vector(31 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(ADDRWIDTH - 2 downto 0);
dob : out std_logic_vector(63 downto 0)
);
end entity ipbus_transport_multibuffer_tx_dpram;
architecture rtl of ipbus_transport_multibuffer_tx_dpram is
type ram_type is array (2**ADDRWIDTH - 1 downto 0) of std_logic_vector(31 downto 0);
signal ram : ram_type;
begin
write: process (clka)
begin
if rising_edge(clka) then
if (wea = '1') then
ram(to_integer(unsigned(addra))) <= dia;
end if;
end if;
end process write;
read: process (clkb)
begin
if rising_edge(clkb) then
dob(31 downto 0) <= ram(to_integer(unsigned(addrb & '0')));
dob(63 downto 32) <= ram(to_integer(unsigned(addrb & '1')));
end if;
end process read;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.multiplier_pkg.all;
package ab_to_abc_transform_pkg is
------------------------------------------------------------------------
type alpha_beta_to_abc_transform_record is record
alpha_beta_to_abc_multiplier_process_counter : natural range 0 to 15;
alpha_beta_to_abc_calculation_process_counter : natural range 0 to 15;
phase_a : int18;
phase_b : int18;
phase_c : int18;
phase_a_sum : int18;
phase_b_sum : int18;
phase_c_sum : int18;
alpha_beta_to_abc_transform_is_ready : boolean;
end record;
constant init_alpha_beta_to_abc_transform : alpha_beta_to_abc_transform_record :=
(0, 0, 0, 0, 0,
0, 0, 0, false);
------------------------------------------------------------------------
function get_phase_a ( alpha_beta_to_abc_object : alpha_beta_to_abc_transform_record)
return integer;
------------------------------------------------------------------------
function get_phase_b ( alpha_beta_to_abc_object : alpha_beta_to_abc_transform_record)
return integer;
------------------------------------------------------------------------
function get_phase_c ( alpha_beta_to_abc_object : alpha_beta_to_abc_transform_record)
return integer;
------------------------------------------------------------------------
function ab_to_abc_transform_is_ready ( alpha_beta_to_abc_object : alpha_beta_to_abc_transform_record)
return boolean;
------------------------------------------------------------------------
procedure request_alpha_beta_to_abc_transform (
signal alpha_beta_to_abc_object : inout alpha_beta_to_abc_transform_record);
------------------------------------------------------------------------
procedure create_alpha_beta_to_abc_transformer (
signal hw_multiplier : inout multiplier_record;
signal alpha_beta_to_abc_object : inout alpha_beta_to_abc_transform_record;
alpha : integer;
beta : integer;
gamma : integer);
------------------------------------------------------------------------
end package ab_to_abc_transform_pkg;
package body ab_to_abc_transform_pkg is
------------------------------------------------------------------------
function get_phase_a
(
alpha_beta_to_abc_object : alpha_beta_to_abc_transform_record
)
return integer
is
begin
return alpha_beta_to_abc_object.phase_a;
end get_phase_a;
------------------------------------------------------------------------
function get_phase_b
(
alpha_beta_to_abc_object : alpha_beta_to_abc_transform_record
)
return integer
is
begin
return alpha_beta_to_abc_object.phase_b;
end get_phase_b;
------------------------------------------------------------------------
function get_phase_c
(
alpha_beta_to_abc_object : alpha_beta_to_abc_transform_record
)
return integer
is
begin
return alpha_beta_to_abc_object.phase_c;
end get_phase_c;
------------------------------------------------------------------------
function ab_to_abc_transform_is_ready
(
alpha_beta_to_abc_object : alpha_beta_to_abc_transform_record
)
return boolean
is
begin
return alpha_beta_to_abc_object.alpha_beta_to_abc_transform_is_ready;
end ab_to_abc_transform_is_ready;
------------------------------------------------------------------------
procedure request_alpha_beta_to_abc_transform
(
signal alpha_beta_to_abc_object : inout alpha_beta_to_abc_transform_record
) is
begin
alpha_beta_to_abc_object.alpha_beta_to_abc_multiplier_process_counter <= 0;
alpha_beta_to_abc_object.alpha_beta_to_abc_calculation_process_counter <= 0;
end request_alpha_beta_to_abc_transform;
------------------------------------------------------------------------
procedure create_alpha_beta_to_abc_transformer
(
signal hw_multiplier : inout multiplier_record;
signal alpha_beta_to_abc_object : inout alpha_beta_to_abc_transform_record;
alpha : integer;
beta : integer;
gamma : integer
) is
alias abc_multiplier_process_counter is alpha_beta_to_abc_object.alpha_beta_to_abc_multiplier_process_counter;
alias abc_transform_process_counter is alpha_beta_to_abc_object.alpha_beta_to_abc_calculation_process_counter;
alias phase_a is alpha_beta_to_abc_object.phase_a;
alias phase_b is alpha_beta_to_abc_object.phase_b;
alias phase_c is alpha_beta_to_abc_object.phase_c;
alias phase_a_sum is alpha_beta_to_abc_object.phase_a_sum;
alias phase_b_sum is alpha_beta_to_abc_object.phase_b_sum;
alias phase_c_sum is alpha_beta_to_abc_object.phase_c_sum;
alias alpha_beta_to_abc_transform_is_ready is alpha_beta_to_abc_object.alpha_beta_to_abc_transform_is_ready;
begin
------------------------------------------------------------------------
alpha_beta_to_abc_transform_is_ready <= false;
------------------------------------------------------------------------
CASE abc_multiplier_process_counter is
WHEN 0 => multiply_and_increment_counter(hw_multiplier , abc_multiplier_process_counter , alpha , 65536 );
WHEN 1 => multiply_and_increment_counter(hw_multiplier , abc_multiplier_process_counter , beta , 0 );
WHEN 2 => multiply_and_increment_counter(hw_multiplier , abc_multiplier_process_counter , gamma , 65536 );
WHEN 3 => multiply_and_increment_counter(hw_multiplier , abc_multiplier_process_counter , alpha , -32768 );
WHEN 4 => multiply_and_increment_counter(hw_multiplier , abc_multiplier_process_counter , beta , 56756 );
WHEN 5 => multiply_and_increment_counter(hw_multiplier , abc_multiplier_process_counter , gamma , 65536 );
WHEN 6 => multiply_and_increment_counter(hw_multiplier , abc_multiplier_process_counter , alpha , -32768 );
WHEN 7 => multiply_and_increment_counter(hw_multiplier , abc_multiplier_process_counter , beta , -56756 );
WHEN 8 => multiply_and_increment_counter(hw_multiplier , abc_multiplier_process_counter , gamma , 65536 );
WHEN others => -- wait for restart
end CASE;
------------------------------------------------------------------------
CASE abc_transform_process_counter is
WHEN 0 =>
if multiplier_is_ready(hw_multiplier) then
phase_a_sum <= get_multiplier_result(hw_multiplier,16);
abc_transform_process_counter <= abc_transform_process_counter + 1;
end if;
WHEN 1 =>
phase_a_sum <= phase_a_sum + get_multiplier_result(hw_multiplier,16);
abc_transform_process_counter <= abc_transform_process_counter + 1;
WHEN 2 =>
phase_a <= phase_a_sum + get_multiplier_result(hw_multiplier,16);
abc_transform_process_counter <= abc_transform_process_counter + 1;
WHEN 3 =>
phase_b_sum <= get_multiplier_result(hw_multiplier,16);
abc_transform_process_counter <= abc_transform_process_counter + 1;
WHEN 4 =>
phase_b_sum <= phase_b_sum + get_multiplier_result(hw_multiplier,16);
abc_transform_process_counter <= abc_transform_process_counter + 1;
WHEN 5 =>
phase_b <= phase_b_sum + get_multiplier_result(hw_multiplier,16);
abc_transform_process_counter <= abc_transform_process_counter + 1;
WHEN 6 =>
phase_c_sum <= get_multiplier_result(hw_multiplier,16);
abc_transform_process_counter <= abc_transform_process_counter + 1;
WHEN 7 =>
phase_c_sum <= phase_c_sum + get_multiplier_result(hw_multiplier,16);
abc_transform_process_counter <= abc_transform_process_counter + 1;
WHEN 8 =>
phase_c <= phase_c_sum + get_multiplier_result(hw_multiplier,16);
abc_transform_process_counter <= abc_transform_process_counter + 1;
alpha_beta_to_abc_transform_is_ready <= true;
WHEN others => -- wait for restart
end CASE;
------------------------------------------------------------------------
end create_alpha_beta_to_abc_transformer;
------------------------------------------------------------------------
end package body ab_to_abc_transform_pkg;
|
<gh_stars>0
-- Plain NxN bit unsigned compare less than or equal
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity top is
generic (
N : natural := 128
);
port (
CLK : in std_logic;
RST : in std_logic;
IO_A : in std_logic_vector(N-1 downto 0);
IO_B : in std_logic_vector(N-1 downto 0);
IO_O : out std_logic
);
end top;
architecture Behavioral of top is
signal a: std_logic_vector(N-1 downto 0);
signal b: std_logic_vector(N-1 downto 0);
signal o_next : std_logic;
begin
process (CLK)
begin
if rising_edge(CLK) then
if RST = '1' then
a <= (others => '0');
b <= (others => '0');
IO_O <= '0';
else
a <= IO_A;
b <= IO_B;
IO_O <= o_next;
end if;
end if;
end process;
process(a, b)
begin
if unsigned(a) <= unsigned(b) then
o_next <= '1';
else
o_next <= '0';
end if;
end process;
end Behavioral;
|
<reponame>ispras/hdl-benchmarks
-------------------------------------------------------------------------------
-- Title : Zero Insertion
-- Project : HDLC controller
-------------------------------------------------------------------------------
-- File : zero_ins.vhd
-- Author : <NAME> (<EMAIL>)
-- Organization: OpenIPCore Project
-- Created : 2001/01/12
-- Last update: 2001/05/27
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers:
-- Target :
-- Dependency : ieee.std_logic_1164
--
-------------------------------------------------------------------------------
-- Description: Zero Insertion
-------------------------------------------------------------------------------
-- Copyright (c) 2000 <NAME>
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 12 Jan 2001
-- Modifier : <NAME> (<EMAIL>)
-- Desccription : Created
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 2
-- Version : 0.2
-- Date : 27 May 2001
-- Modifier : <NAME> (<EMAIL>)
-- Desccription : Tx zero insertion bug fixed
-- Zero is inserted after 5 sequence of 1's insted of 6 1's
-------------------------------------------------------------------------------
-- $Log: /pvcs/designs/hdl/oc_hdlc/zero_ins.vh_ $
--
-- Rev 1.0 22 Sep 2004 19:09:10 kbrunham
-- initial version
-- TO, Wed Sep 22 03:08:42 2004
--
-- Rev 1.0 09 Sep 2003 15:10:24 kbrunham
-- initial version
-- TO, Mon Sep 08 23:10:14 2003
-- Revision 1.2 2001/05/28 19:14:22 khatib
-- TX zero insertion bug fixed
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ZeroIns_ent is
port (
TxClk : in std_logic; -- Tx clock
rst_n : in std_logic; -- system reset
enable : in std_logic; -- enable (Driven by controller)
inProgress : out std_logic; -- Data in progress
BackendEnable : in std_logic; -- Backend Enable
-- backend interface
abortedTrans : out std_logic; -- aborted Transmission
ValidFrame : in std_logic; -- Valid Frame signal
Writebyte : in std_logic; -- Back end write byte
rdy : out std_logic; -- data ready
TXD : out std_logic; -- TX serial data
Data : in std_logic_vector(7 downto 0)); -- TX data bus
end ZeroIns_ent;
-------------------------------------------------------------------------------
architecture zero_ins_beh of ZeroIns_ent is
signal data_reg : std_logic_vector(7 downto 0); -- Data register (used as
-- internal buffer)
signal flag : std_logic; -- control signal between processes
signal delay_TX : std_logic; -- Delayed output
begin -- zero_ins_beh
-- purpose: Parallel to Serial
-- type : sequential
-- inputs : TxClk, rst_n
-- outputs:
P2S_proc : process (TxClk, rst_n)
variable tmp_reg : std_logic_vector(15 downto 0); -- Temp Shift register
variable counter : integer range 0 to 8; -- Counter
variable OnesDetected : std_logic; -- 6 ones detected
begin -- process P2S_proc
if rst_n = '0' then -- asynchronous reset (active low)
tmp_reg := (others => '0');
Counter := 0;
flag <= '1';
OnesDetected := '0';
TXD <= '1';
delay_TX <= '1';
inProgress <= '0';
elsif TxClk'event and TxClk = '1' then -- rising clock edge
if enable = '1' then
OnesDetected := tmp_reg(0) and tmp_reg(1) and tmp_reg(2) and tmp_reg(3) and tmp_reg(4);
delay_TX <= tmp_reg(0);
TXD <= delay_TX;
if OnesDetected = '1' then
-- Zero insertion
tmp_reg(4 downto 0) := '0' & tmp_reg(4 downto 1);
else
-- Total Shift
tmp_reg(15 downto 0) := '0' & tmp_reg(15 downto 1);
Counter := Counter +1;
end if; -- ones detected
if counter = 8 then
counter := 0;
flag <= '1';
inProgress <= '0';
tmp_reg(15 downto 8) := data_reg;
else
inProgress <= '1';
flag <= '0';
end if; -- counter
end if; -- enable
end if; -- clk
end process P2S_proc;
-------------------------------------------------------------------------------
-- purpose: Baclend Interface
-- type : sequential
-- inputs : TxClk, rst_n
-- outputs:
Backend_proc : process (TxClk, rst_n)
variable state : std_logic; -- Backend state
begin -- process Backend_proc
if rst_n = '0' then -- asynchronous reset (active low)
state := '0';
data_reg <= (others => '0');
rdy <= '0';
abortedTrans <= '0';
elsif TxClk'event and TxClk = '1' then -- rising clock edge
if enable = '1' then
if BackendEnable = '1' then
if ValidFrame = '1' then
case state is
when '0' => -- wait for reading the register
if flag = '1' then -- Register has been read
state := '1';
rdy <= '1';
data_reg <= "00000000"; -- set register to known pattern to
-- avoid invalid read (upon valid
-- read this value will be overwritten)
end if;
when '1' =>
if WriteByte = '1' then
state := '0';
rdy <= '0';
data_reg <= Data;
elsif flag = '1' then -- Another flag but without read
state := '0';
rdy <= '0';
data_reg <= "00000000";
abortedTrans <= '1';
end if;
when others => null;
end case;
else
abortedTrans <= '0';
end if; -- ValidFrame
else
data_reg <= (others => '0');
end if; -- Backend enable
end if; -- enable
end if; -- Txclk
end process Backend_proc;
end zero_ins_beh;
|
<filename>rtl/quartus-synthesis/pkg-types.vhdl
/*
Tauhop Solutions common types.
Author(s):
- <NAME>, <EMAIL> | <EMAIL>
Copyright (C) 2012-2013 Authors and OPENCORES.ORG
This source file may be used and distributed without
restriction provided that this copyright statement is not
removed from the file and that any derivative work contains
the original copyright notice and the associated disclaimer.
This source file is free software; you can redistribute it
and/or modify it under the terms of the GNU Lesser General
Public License as published by the Free Software Foundation;
either version 2.1 of the License, or (at your option) any
later version.
This source is distributed in the hope that it will be
useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the GNU Lesser General Public License for more
details.
You should have received a copy of the GNU Lesser General
Public License along with this source; if not, download it
from http://www.opencores.org/lgpl.shtml.
*/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package types is
type byte is array(7 downto 0) of std_logic;
type byte_vector is array(natural range <>) of byte;
/* VHDL-2008 datatypes.
Comment out for simulation. Questa/ModelSim already supports this.
*/
type boolean_vector is array(natural range <>) of boolean;
type integer_vector is array(natural range <>) of integer;
/* [end]: VHDL-2008 datatypes. */
end package types;
package body types is
end package body types;
|
<filename>networklayer/synthesis_results_HMB/UDP_prj/ultrascale_plus/syn/vhdl/udp_fifo_w16_d256_A.vhd
-- ==============================================================
-- Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2021.1 (64-bit)
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity udp_fifo_w16_d256_A_ram is
generic (
DATA_WIDTH : natural := 16;
ADDR_WIDTH : natural := 8;
DEPTH : natural := 255
);
port (
clk : in std_logic;
reset : in std_logic;
we : in std_logic;
waddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
din : in std_logic_vector(DATA_WIDTH-1 downto 0);
raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
rden : in std_logic;
dout : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end entity;
architecture arch of udp_fifo_w16_d256_A_ram is
type memtype is array (0 to DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem : memtype;
attribute rw_addr_collision : string;
attribute rw_addr_collision of mem : signal is "yes";
signal raddr_reg : std_logic_vector(ADDR_WIDTH - 1 downto 0) := (others => '0');
begin
-- read from mem
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout <= ( others=> '0');
elsif (rden = '1') then
dout <= mem(conv_integer(raddr_reg));
end if;
end if;
end process;
-- write to mem
process (clk) begin
if clk'event and clk = '1' then
if we = '1' then
mem(conv_integer(waddr)) <= din;
end if;
end if;
end process;
-- buffer the raddr
process (clk) begin
if clk'event and clk = '1' then
raddr_reg <= raddr;
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity udp_fifo_w16_d256_A is
generic (
DATA_WIDTH : natural := 16;
ADDR_WIDTH : natural := 8;
DEPTH : natural := 255
);
port (
clk : in std_logic;
reset : in std_logic;
if_full_n : out std_logic;
if_write_ce : in std_logic;
if_write : in std_logic;
if_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
if_empty_n : out std_logic;
if_read_ce : in std_logic;
if_read : in std_logic;
if_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end entity;
architecture arch of udp_fifo_w16_d256_A is
-- component
component udp_fifo_w16_d256_A_ram is
generic (
DATA_WIDTH : natural := 16;
ADDR_WIDTH : natural := 8;
DEPTH : natural := 255
);
port (
clk : in std_logic;
reset : in std_logic;
we : in std_logic;
waddr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
raddr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
rden : in std_logic;
dout : out std_logic_vector(DATA_WIDTH - 1 downto 0));
end component;
-- signals
signal waddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal raddr : unsigned(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal wnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal rnext : unsigned(ADDR_WIDTH - 1 downto 0);
signal push : std_logic;
signal pop : std_logic;
signal mOutPtr : unsigned(ADDR_WIDTH downto 0) := (others => '0');
signal full_n : std_logic := '1';
signal empty_n : std_logic := '0';
signal dout_vld : std_logic := '0';
begin
----------------------- Instantiation -----------------------
U_udp_fifo_w16_d256_A_ram : udp_fifo_w16_d256_A_ram
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
reset => reset,
we => push,
waddr => std_logic_vector(waddr),
din => if_din,
raddr => std_logic_vector(rnext),
rden => pop,
dout => if_dout);
--------------------------- Body ----------------------------
if_full_n <= full_n;
if_empty_n <= dout_vld;
push <= full_n and if_write_ce and if_write;
pop <= empty_n and if_read_ce and (not dout_vld or if_read);
wnext <= waddr when push = '0' else
(others => '0') when waddr = DEPTH - 1 else
waddr + 1;
rnext <= raddr when pop = '0' else
(others => '0') when raddr = DEPTH - 1 else
raddr + 1;
-- waddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
waddr <= (others => '0');
else
waddr <= wnext;
end if;
end if;
end process;
-- raddr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
raddr <= (others => '0');
else
raddr <= rnext;
end if;
end if;
end process;
-- mOutPtr
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '0');
elsif push = '1' and pop = '0' then
mOutPtr <= mOutPtr + 1;
elsif push = '0' and pop = '1' then
mOutPtr <= mOutPtr - 1;
end if;
end if;
end process;
-- full_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
full_n <= '1';
elsif push = '1' and pop = '0' then
if mOutPtr = DEPTH - 1 then
full_n <= '0';
else
full_n <= '1';
end if;
elsif push = '0' and pop = '1' then
full_n <= '1';
end if;
end if;
end process;
-- empty_n
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
empty_n <= '0';
elsif push = '1' and pop = '0' then
empty_n <= '1';
elsif push = '0' and pop = '1' then
if mOutPtr = 1 then
empty_n <= '0';
else
empty_n <= '1';
end if;
end if;
end if;
end process;
-- dout_vld
process (clk) begin
if clk'event and clk = '1' then
if reset = '1' then
dout_vld <= '0';
elsif pop = '1' then
dout_vld <= '1';
elsif if_read_ce = '1' and if_read = '1' then
dout_vld <= '0';
end if;
end if;
end process;
end architecture;
|
<reponame>jeanthom/potato
-- The Potato Processor - A simple processor for FPGAs
-- (c) <NAME> 2014 - 2015 <<EMAIL>>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_types.all;
use work.pp_utilities.all;
--! @brief Simple read-only direct-mapped instruction cache.
entity pp_icache is
generic(
LINE_SIZE : natural := 4; --! Number of words per cache line
NUM_LINES : natural := 128 --! Number of lines in the cache
);
port(
clk : in std_logic;
reset : in std_logic;
-- Memory interface:
mem_address_in : in std_logic_vector(31 downto 0);
mem_data_out : out std_logic_vector(31 downto 0);
mem_read_req : in std_logic;
mem_read_ack : out std_logic;
-- Wishbone interface:
wb_inputs : in wishbone_master_inputs;
wb_outputs : out wishbone_master_outputs
);
end entity pp_icache;
architecture behaviour of pp_icache is
-- Counter types:
subtype line_counter_type is natural range 0 to NUM_LINES;
subtype word_counter_type is natural range 0 to LINE_SIZE;
-- Cache line types:
subtype cache_line_type is std_logic_vector((LINE_SIZE * 32) - 1 downto 0);
type cache_line_word_array is array(0 to LINE_SIZE - 1) of std_logic_vector(31 downto 0);
type cache_line_array is array(0 to NUM_LINES - 1) of cache_line_type;
-- Cache tag type:
subtype cache_tag_type is std_logic_vector(31 - log2(LINE_SIZE * 4) - log2(NUM_LINES) downto 0);
type cache_tag_array is array(0 to NUM_LINES - 1) of cache_tag_type;
-- Cache memories:
signal cache_memory : cache_line_array;
signal tag_memory : cache_tag_array;
signal valid : std_logic_vector(NUM_LINES - 1 downto 0) := (others => '0');
attribute ram_style : string;
attribute ram_style of cache_memory: signal is "block";
-- Cache controller signals:
type state_type is (IDLE, CACHE_READ_STALL,
LOAD_CACHELINE_START, LOAD_CACHELINE_WAIT_ACK, LOAD_CACHELINE_FINISH);
signal state : state_type := IDLE;
-- Input address components:
signal input_address_line : std_logic_vector(log2(NUM_LINES) - 1 downto 0);
signal input_address_word : std_logic_vector(log2(LINE_SIZE) - 1 downto 0);
signal input_address_tag : cache_tag_type;
-- Cacheline matching the current input address:
signal current_cache_line, cache_lookup : cache_line_type;
signal current_cache_line_words : cache_line_word_array;
-- Base address to load a cacheline from:
signal cl_load_address : std_logic_vector(31 downto log2(LINE_SIZE * 4));
-- Cache line to load:
signal cl_current_line : line_counter_type;
-- Current word being loaded:
signal cl_current_word : word_counter_type;
-- Buffer for holding a cache line while loading:
signal load_buffer : cache_line_type;
signal load_buffer_tag : cache_tag_type;
-- Causes a cache line to be stored in the cache memory:
signal store_cache_line : std_logic;
-- Set when the current input address matches a cache line:
signal cache_hit : std_logic;
begin
assert is_pow2(LINE_SIZE) report "Cache line size must be a power of 2!" severity FAILURE;
assert is_pow2(NUM_LINES) report "Number of cache lines must be a power of 2!" severity FAILURE;
mem_data_out <= current_cache_line_words(to_integer(unsigned(input_address_word)));
mem_read_ack <= (cache_hit and mem_read_req) when state = IDLE or state = CACHE_READ_STALL else '0';
input_address_line <= mem_address_in(log2(LINE_SIZE * 4) + log2(NUM_LINES) - 1 downto log2(LINE_SIZE * 4));
input_address_tag <= mem_address_in(31 downto log2(LINE_SIZE * 4) + log2(NUM_LINES));
decompose_cache_line: for i in 0 to LINE_SIZE - 1 generate
current_cache_line_words(i) <= current_cache_line(32 * i + 31 downto 32 * i);
end generate decompose_cache_line;
find_indices: process(clk)
begin
if rising_edge(clk) then
input_address_word <= mem_address_in(log2(LINE_SIZE * 4) - 1 downto 2);
end if;
end process find_indices;
cacheline_lookup: process(clk)
begin
if rising_edge(clk) then
if store_cache_line = '1' then
cache_memory(cl_current_line) <= load_buffer;
end if;
current_cache_line <= cache_memory(to_integer(unsigned(input_address_line)));
end if;
end process cacheline_lookup;
tag_lookup: process(clk)
begin
if rising_edge(clk) then
if store_cache_line = '1' then
tag_memory(cl_current_line) <= load_buffer_tag;
end if;
cache_hit <= valid(to_integer(unsigned(input_address_line)))
and to_std_logic(tag_memory(to_integer(unsigned(input_address_line))) = input_address_tag);
end if;
end process tag_lookup;
controller: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
state <= IDLE;
wb_outputs.cyc <= '0';
wb_outputs.stb <= '0';
store_cache_line <= '0';
valid <= (others => '0');
else
case state is
when IDLE =>
if mem_read_req = '1' and cache_hit = '0' then
wb_outputs.adr <= mem_address_in(31 downto log2(LINE_SIZE * 4)) & (log2(LINE_SIZE * 4) - 1 downto 0 => '0');
wb_outputs.cyc <= '1';
wb_outputs.we <= '0';
wb_outputs.sel <= (others => '1');
load_buffer_tag <= input_address_tag;
cl_load_address <= mem_address_in(31 downto log2(LINE_SIZE * 4));
cl_current_line <= to_integer(unsigned(input_address_line));
cl_current_word <= 0;
state <= LOAD_CACHELINE_START;
end if;
when CACHE_READ_STALL =>
state <= IDLE;
when LOAD_CACHELINE_START =>
wb_outputs.stb <= '1';
wb_outputs.we <= '0';
wb_outputs.adr <= cl_load_address & std_logic_vector(to_unsigned(cl_current_word, log2(LINE_SIZE))) & b"00";
state <= LOAD_CACHELINE_WAIT_ACK;
when LOAD_CACHELINE_WAIT_ACK =>
if wb_inputs.ack = '1' then
wb_outputs.stb <= '0';
load_buffer(cl_current_word * 32 + 31 downto cl_current_word * 32) <= wb_inputs.dat;
if natural(cl_current_word) = LINE_SIZE - 1 then
wb_outputs.cyc <= '0';
store_cache_line <= '1';
state <= LOAD_CACHELINE_FINISH;
else
cl_current_word <= cl_current_word + 1;
state <= LOAD_CACHELINE_START;
end if;
end if;
when LOAD_CACHELINE_FINISH =>
store_cache_line <= '0';
valid(cl_current_line) <= '1';
state <= CACHE_READ_STALL;
end case;
end if;
end if;
end process controller;
end architecture behaviour;
|
<gh_stars>0
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.2.2 (lin64) Build 3118627 Tue Feb 9 05:13:49 MST 2021
-- Date : Wed Mar 16 11:34:47 2022
-- Host : ubuntu3 running 64-bit Ubuntu 20.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top video_cp_pr_0_out1_0 -prefix
-- video_cp_pr_0_out1_0_ video_cp_pr_join_out0_0_sim_netlist.vhdl
-- Design : video_cp_pr_join_out0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axisc_register_slice is
port (
s_axis_tready : out STD_LOGIC;
\state_reg[0]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 27 downto 0 );
aclk : in STD_LOGIC;
m_axis_tready : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 27 downto 0 );
areset_r : in STD_LOGIC
);
end video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axisc_register_slice;
architecture STRUCTURE of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axisc_register_slice is
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \aresetn_d_reg_n_0_[1]\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 27 downto 0 );
signal p_1_out : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axis_tready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal s_ready_i_i_1_n_0 : STD_LOGIC;
signal s_ready_i_i_2_n_0 : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \^state_reg[0]_0\ : STD_LOGIC;
signal \state_reg_n_0_[1]\ : STD_LOGIC;
signal storage_data1 : STD_LOGIC;
signal storage_data2 : STD_LOGIC_VECTOR ( 27 downto 0 );
signal storage_data2_0 : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \aresetn_d_reg[0]\ : label is "no";
attribute equivalent_register_removal of \aresetn_d_reg[1]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of s_ready_i_i_3 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \state[0]_i_2\ : label is "soft_lutpair0";
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of \state_reg[0]\ : label is "none";
attribute FSM_ENCODING of \state_reg[1]\ : label is "none";
begin
s_axis_tready <= \^s_axis_tready\;
\state_reg[0]_0\ <= \^state_reg[0]_0\;
\__2/i_\: unisim.vcomponents.LUT4
generic map(
INIT => X"E420"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \^state_reg[0]_0\,
I2 => s_axis_tvalid,
I3 => m_axis_tready,
O => storage_data1
);
\aresetn_d[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => areset_r,
O => p_1_out(0)
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => p_1_out(0),
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg_n_0_[0]\,
Q => \aresetn_d_reg_n_0_[1]\,
R => '0'
);
s_ready_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2E2EEE2"
)
port map (
I0 => \^s_axis_tready\,
I1 => s_ready_i_i_2_n_0,
I2 => s_ready_i0,
I3 => m_axis_tready,
I4 => \state_reg_n_0_[1]\,
I5 => areset_r,
O => s_ready_i_i_1_n_0
);
s_ready_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"2808FFFF00000000"
)
port map (
I0 => \^state_reg[0]_0\,
I1 => m_axis_tready,
I2 => \state_reg_n_0_[1]\,
I3 => s_axis_tvalid,
I4 => \aresetn_d_reg_n_0_[1]\,
I5 => \aresetn_d_reg_n_0_[0]\,
O => s_ready_i_i_2_n_0
);
s_ready_i_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => \aresetn_d_reg_n_0_[1]\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i_i_1_n_0,
Q => \^s_axis_tready\,
R => '0'
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000D8F8F0F0"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => s_axis_tvalid,
I2 => \^state_reg[0]_0\,
I3 => m_axis_tready,
I4 => \aresetn_d_reg_n_0_[0]\,
I5 => \state[0]_i_2_n_0\,
O => \state[0]_i_1_n_0\
);
\state[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => areset_r,
I1 => \aresetn_d_reg_n_0_[1]\,
I2 => \aresetn_d_reg_n_0_[0]\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF2FAAAA"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => s_axis_tvalid,
I2 => \^state_reg[0]_0\,
I3 => m_axis_tready,
I4 => \aresetn_d_reg_n_0_[0]\,
I5 => \state[0]_i_2_n_0\,
O => \state[1]_i_1_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => \^state_reg[0]_0\,
R => '0'
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => \state_reg_n_0_[1]\,
R => '0'
);
\storage_data1[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(0),
I1 => D(0),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(0)
);
\storage_data1[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(10),
I1 => D(10),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(10)
);
\storage_data1[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(11),
I1 => D(11),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(11)
);
\storage_data1[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(12),
I1 => D(12),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(12)
);
\storage_data1[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(13),
I1 => D(13),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(13)
);
\storage_data1[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(14),
I1 => D(14),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(14)
);
\storage_data1[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(15),
I1 => D(15),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(15)
);
\storage_data1[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(16),
I1 => D(16),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(16)
);
\storage_data1[17]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(17),
I1 => D(17),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(17)
);
\storage_data1[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(18),
I1 => D(18),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(18)
);
\storage_data1[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(19),
I1 => D(19),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(19)
);
\storage_data1[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(1),
I1 => D(1),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(1)
);
\storage_data1[20]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(20),
I1 => D(20),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(20)
);
\storage_data1[21]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(21),
I1 => D(21),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(21)
);
\storage_data1[22]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(22),
I1 => D(22),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(22)
);
\storage_data1[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(23),
I1 => D(23),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(23)
);
\storage_data1[24]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(24),
I1 => D(24),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(24)
);
\storage_data1[25]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(25),
I1 => D(25),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(25)
);
\storage_data1[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(26),
I1 => D(26),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(26)
);
\storage_data1[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(27),
I1 => D(27),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(27)
);
\storage_data1[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(2),
I1 => D(2),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(2)
);
\storage_data1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(3),
I1 => D(3),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(3)
);
\storage_data1[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(4),
I1 => D(4),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(4)
);
\storage_data1[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(5),
I1 => D(5),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(5)
);
\storage_data1[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(6),
I1 => D(6),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(6)
);
\storage_data1[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(7),
I1 => D(7),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(7)
);
\storage_data1[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(8),
I1 => D(8),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(8)
);
\storage_data1[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => storage_data2(9),
I1 => D(9),
I2 => \^state_reg[0]_0\,
I3 => \state_reg_n_0_[1]\,
O => p_0_in(9)
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(0),
Q => Q(0),
R => '0'
);
\storage_data1_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(10),
Q => Q(10),
R => '0'
);
\storage_data1_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(11),
Q => Q(11),
R => '0'
);
\storage_data1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(12),
Q => Q(12),
R => '0'
);
\storage_data1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(13),
Q => Q(13),
R => '0'
);
\storage_data1_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(14),
Q => Q(14),
R => '0'
);
\storage_data1_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(15),
Q => Q(15),
R => '0'
);
\storage_data1_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(16),
Q => Q(16),
R => '0'
);
\storage_data1_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(17),
Q => Q(17),
R => '0'
);
\storage_data1_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(18),
Q => Q(18),
R => '0'
);
\storage_data1_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(19),
Q => Q(19),
R => '0'
);
\storage_data1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(1),
Q => Q(1),
R => '0'
);
\storage_data1_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(20),
Q => Q(20),
R => '0'
);
\storage_data1_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(21),
Q => Q(21),
R => '0'
);
\storage_data1_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(22),
Q => Q(22),
R => '0'
);
\storage_data1_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(23),
Q => Q(23),
R => '0'
);
\storage_data1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(24),
Q => Q(24),
R => '0'
);
\storage_data1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(25),
Q => Q(25),
R => '0'
);
\storage_data1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(26),
Q => Q(26),
R => '0'
);
\storage_data1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(27),
Q => Q(27),
R => '0'
);
\storage_data1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(2),
Q => Q(2),
R => '0'
);
\storage_data1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(3),
Q => Q(3),
R => '0'
);
\storage_data1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(4),
Q => Q(4),
R => '0'
);
\storage_data1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(5),
Q => Q(5),
R => '0'
);
\storage_data1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(6),
Q => Q(6),
R => '0'
);
\storage_data1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(7),
Q => Q(7),
R => '0'
);
\storage_data1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(8),
Q => Q(8),
R => '0'
);
\storage_data1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data1,
D => p_0_in(9),
Q => Q(9),
R => '0'
);
\storage_data2[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axis_tvalid,
I1 => \^s_axis_tready\,
O => storage_data2_0
);
\storage_data2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(0),
Q => storage_data2(0),
R => '0'
);
\storage_data2_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(10),
Q => storage_data2(10),
R => '0'
);
\storage_data2_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(11),
Q => storage_data2(11),
R => '0'
);
\storage_data2_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(12),
Q => storage_data2(12),
R => '0'
);
\storage_data2_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(13),
Q => storage_data2(13),
R => '0'
);
\storage_data2_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(14),
Q => storage_data2(14),
R => '0'
);
\storage_data2_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(15),
Q => storage_data2(15),
R => '0'
);
\storage_data2_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(16),
Q => storage_data2(16),
R => '0'
);
\storage_data2_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(17),
Q => storage_data2(17),
R => '0'
);
\storage_data2_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(18),
Q => storage_data2(18),
R => '0'
);
\storage_data2_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(19),
Q => storage_data2(19),
R => '0'
);
\storage_data2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(1),
Q => storage_data2(1),
R => '0'
);
\storage_data2_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(20),
Q => storage_data2(20),
R => '0'
);
\storage_data2_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(21),
Q => storage_data2(21),
R => '0'
);
\storage_data2_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(22),
Q => storage_data2(22),
R => '0'
);
\storage_data2_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(23),
Q => storage_data2(23),
R => '0'
);
\storage_data2_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(24),
Q => storage_data2(24),
R => '0'
);
\storage_data2_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(25),
Q => storage_data2(25),
R => '0'
);
\storage_data2_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(26),
Q => storage_data2(26),
R => '0'
);
\storage_data2_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(27),
Q => storage_data2(27),
R => '0'
);
\storage_data2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(2),
Q => storage_data2(2),
R => '0'
);
\storage_data2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(3),
Q => storage_data2(3),
R => '0'
);
\storage_data2_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(4),
Q => storage_data2(4),
R => '0'
);
\storage_data2_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(5),
Q => storage_data2(5),
R => '0'
);
\storage_data2_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(6),
Q => storage_data2(6),
R => '0'
);
\storage_data2_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(7),
Q => storage_data2(7),
R => '0'
);
\storage_data2_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(8),
Q => storage_data2(8),
R => '0'
);
\storage_data2_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => storage_data2_0,
D => D(9),
Q => storage_data2(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice is
port (
aclk : in STD_LOGIC;
aclk2x : in STD_LOGIC;
aresetn : in STD_LOGIC;
aclken : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AXIS_SIGNAL_SET : integer;
attribute C_AXIS_SIGNAL_SET of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 243;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 24;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is "zynq";
attribute C_NUM_SLR_CROSSINGS : integer;
attribute C_NUM_SLR_CROSSINGS of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 0;
attribute C_PIPELINES_MASTER : integer;
attribute C_PIPELINES_MASTER of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 0;
attribute C_PIPELINES_MIDDLE : integer;
attribute C_PIPELINES_MIDDLE of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 0;
attribute C_PIPELINES_SLAVE : integer;
attribute C_PIPELINES_SLAVE of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 0;
attribute C_REG_CONFIG : integer;
attribute C_REG_CONFIG of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 8;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is "yes";
attribute G_INDX_SS_TDATA : integer;
attribute G_INDX_SS_TDATA of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 1;
attribute G_INDX_SS_TDEST : integer;
attribute G_INDX_SS_TDEST of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 6;
attribute G_INDX_SS_TID : integer;
attribute G_INDX_SS_TID of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 5;
attribute G_INDX_SS_TKEEP : integer;
attribute G_INDX_SS_TKEEP of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 3;
attribute G_INDX_SS_TLAST : integer;
attribute G_INDX_SS_TLAST of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 4;
attribute G_INDX_SS_TREADY : integer;
attribute G_INDX_SS_TREADY of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 0;
attribute G_INDX_SS_TSTRB : integer;
attribute G_INDX_SS_TSTRB of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 2;
attribute G_INDX_SS_TUSER : integer;
attribute G_INDX_SS_TUSER of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 7;
attribute G_MASK_SS_TDATA : integer;
attribute G_MASK_SS_TDATA of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 2;
attribute G_MASK_SS_TDEST : integer;
attribute G_MASK_SS_TDEST of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 64;
attribute G_MASK_SS_TID : integer;
attribute G_MASK_SS_TID of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 32;
attribute G_MASK_SS_TKEEP : integer;
attribute G_MASK_SS_TKEEP of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 8;
attribute G_MASK_SS_TLAST : integer;
attribute G_MASK_SS_TLAST of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 16;
attribute G_MASK_SS_TREADY : integer;
attribute G_MASK_SS_TREADY of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 1;
attribute G_MASK_SS_TSTRB : integer;
attribute G_MASK_SS_TSTRB of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 4;
attribute G_MASK_SS_TUSER : integer;
attribute G_MASK_SS_TUSER of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 128;
attribute G_TASK_SEVERITY_ERR : integer;
attribute G_TASK_SEVERITY_ERR of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 2;
attribute G_TASK_SEVERITY_INFO : integer;
attribute G_TASK_SEVERITY_INFO of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 0;
attribute G_TASK_SEVERITY_WARNING : integer;
attribute G_TASK_SEVERITY_WARNING of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 1;
attribute P_TPAYLOAD_WIDTH : integer;
attribute P_TPAYLOAD_WIDTH of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice : entity is 28;
end video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice;
architecture STRUCTURE of video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice is
signal \<const0>\ : STD_LOGIC;
signal areset_r : STD_LOGIC;
signal areset_r_i_1_n_0 : STD_LOGIC;
begin
m_axis_tkeep(2) <= \<const0>\;
m_axis_tkeep(1) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tstrb(2) <= \<const0>\;
m_axis_tstrb(1) <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
areset_r_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_r_i_1_n_0
);
areset_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_r_i_1_n_0,
Q => areset_r,
R => '0'
);
axisc_register_slice_0: entity work.video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axisc_register_slice
port map (
D(27) => s_axis_tuser(0),
D(26) => s_axis_tdest(0),
D(25) => s_axis_tid(0),
D(24) => s_axis_tlast,
D(23 downto 0) => s_axis_tdata(23 downto 0),
Q(27) => m_axis_tuser(0),
Q(26) => m_axis_tdest(0),
Q(25) => m_axis_tid(0),
Q(24) => m_axis_tlast,
Q(23 downto 0) => m_axis_tdata(23 downto 0),
aclk => aclk,
areset_r => areset_r,
m_axis_tready => m_axis_tready,
s_axis_tready => s_axis_tready,
s_axis_tvalid => s_axis_tvalid,
\state_reg[0]_0\ => m_axis_tvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity video_cp_pr_0_out1_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of video_cp_pr_0_out1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of video_cp_pr_0_out1_0 : entity is "video_cp_pr_join_out0_0,axis_register_slice_v1_1_22_axis_register_slice,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of video_cp_pr_0_out1_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of video_cp_pr_0_out1_0 : entity is "axis_register_slice_v1_1_22_axis_register_slice,Vivado 2020.2.2";
end video_cp_pr_0_out1_0;
architecture STRUCTURE of video_cp_pr_0_out1_0 is
signal NLW_inst_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute C_AXIS_SIGNAL_SET : integer;
attribute C_AXIS_SIGNAL_SET of inst : label is 243;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of inst : label is 24;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of inst : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of inst : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_NUM_SLR_CROSSINGS : integer;
attribute C_NUM_SLR_CROSSINGS of inst : label is 0;
attribute C_PIPELINES_MASTER : integer;
attribute C_PIPELINES_MASTER of inst : label is 0;
attribute C_PIPELINES_MIDDLE : integer;
attribute C_PIPELINES_MIDDLE of inst : label is 0;
attribute C_PIPELINES_SLAVE : integer;
attribute C_PIPELINES_SLAVE of inst : label is 0;
attribute C_REG_CONFIG : integer;
attribute C_REG_CONFIG of inst : label is 8;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute G_INDX_SS_TDATA : integer;
attribute G_INDX_SS_TDATA of inst : label is 1;
attribute G_INDX_SS_TDEST : integer;
attribute G_INDX_SS_TDEST of inst : label is 6;
attribute G_INDX_SS_TID : integer;
attribute G_INDX_SS_TID of inst : label is 5;
attribute G_INDX_SS_TKEEP : integer;
attribute G_INDX_SS_TKEEP of inst : label is 3;
attribute G_INDX_SS_TLAST : integer;
attribute G_INDX_SS_TLAST of inst : label is 4;
attribute G_INDX_SS_TREADY : integer;
attribute G_INDX_SS_TREADY of inst : label is 0;
attribute G_INDX_SS_TSTRB : integer;
attribute G_INDX_SS_TSTRB of inst : label is 2;
attribute G_INDX_SS_TUSER : integer;
attribute G_INDX_SS_TUSER of inst : label is 7;
attribute G_MASK_SS_TDATA : integer;
attribute G_MASK_SS_TDATA of inst : label is 2;
attribute G_MASK_SS_TDEST : integer;
attribute G_MASK_SS_TDEST of inst : label is 64;
attribute G_MASK_SS_TID : integer;
attribute G_MASK_SS_TID of inst : label is 32;
attribute G_MASK_SS_TKEEP : integer;
attribute G_MASK_SS_TKEEP of inst : label is 8;
attribute G_MASK_SS_TLAST : integer;
attribute G_MASK_SS_TLAST of inst : label is 16;
attribute G_MASK_SS_TREADY : integer;
attribute G_MASK_SS_TREADY of inst : label is 1;
attribute G_MASK_SS_TSTRB : integer;
attribute G_MASK_SS_TSTRB of inst : label is 4;
attribute G_MASK_SS_TUSER : integer;
attribute G_MASK_SS_TUSER of inst : label is 128;
attribute G_TASK_SEVERITY_ERR : integer;
attribute G_TASK_SEVERITY_ERR of inst : label is 2;
attribute G_TASK_SEVERITY_INFO : integer;
attribute G_TASK_SEVERITY_INFO of inst : label is 0;
attribute G_TASK_SEVERITY_WARNING : integer;
attribute G_TASK_SEVERITY_WARNING of inst : label is 1;
attribute P_TPAYLOAD_WIDTH : integer;
attribute P_TPAYLOAD_WIDTH of inst : label is 28;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLKIF CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLKIF, FREQ_HZ 142857132, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN video_cp_ps7_0_0_FCLK_CLK1, ASSOCIATED_BUSIF S_AXIS:M_AXIS, ASSOCIATED_RESET aresetn, INSERT_VIP 0, ASSOCIATED_CLKEN aclken";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RSTIF RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT";
attribute X_INTERFACE_INFO of m_axis_tlast : signal is "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
attribute X_INTERFACE_INFO of s_axis_tlast : signal is "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
attribute X_INTERFACE_INFO of m_axis_tdest : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDEST";
attribute X_INTERFACE_INFO of m_axis_tid : signal is "xilinx.com:interface:axis:1.0 M_AXIS TID";
attribute X_INTERFACE_INFO of m_axis_tuser : signal is "xilinx.com:interface:axis:1.0 M_AXIS TUSER";
attribute X_INTERFACE_PARAMETER of m_axis_tuser : signal is "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 3, TDEST_WIDTH 1, TID_WIDTH 1, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 142857132, PHASE 0.000, CLK_DOMAIN video_cp_ps7_0_0_FCLK_CLK1, LAYERED_METADATA undef, INSERT_VIP 0";
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
attribute X_INTERFACE_INFO of s_axis_tdest : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDEST";
attribute X_INTERFACE_INFO of s_axis_tid : signal is "xilinx.com:interface:axis:1.0 S_AXIS TID";
attribute X_INTERFACE_INFO of s_axis_tuser : signal is "xilinx.com:interface:axis:1.0 S_AXIS TUSER";
attribute X_INTERFACE_PARAMETER of s_axis_tuser : signal is "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 3, TDEST_WIDTH 1, TID_WIDTH 1, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 142857132, PHASE 0.000, CLK_DOMAIN video_cp_ps7_0_0_FCLK_CLK1, LAYERED_METADATA undef, INSERT_VIP 0";
begin
inst: entity work.video_cp_pr_0_out1_0_axis_register_slice_v1_1_22_axis_register_slice
port map (
aclk => aclk,
aclk2x => '0',
aclken => '1',
aresetn => aresetn,
m_axis_tdata(23 downto 0) => m_axis_tdata(23 downto 0),
m_axis_tdest(0) => m_axis_tdest(0),
m_axis_tid(0) => m_axis_tid(0),
m_axis_tkeep(2 downto 0) => NLW_inst_m_axis_tkeep_UNCONNECTED(2 downto 0),
m_axis_tlast => m_axis_tlast,
m_axis_tready => m_axis_tready,
m_axis_tstrb(2 downto 0) => NLW_inst_m_axis_tstrb_UNCONNECTED(2 downto 0),
m_axis_tuser(0) => m_axis_tuser(0),
m_axis_tvalid => m_axis_tvalid,
s_axis_tdata(23 downto 0) => s_axis_tdata(23 downto 0),
s_axis_tdest(0) => s_axis_tdest(0),
s_axis_tid(0) => s_axis_tid(0),
s_axis_tkeep(2 downto 0) => B"111",
s_axis_tlast => s_axis_tlast,
s_axis_tready => s_axis_tready,
s_axis_tstrb(2 downto 0) => B"111",
s_axis_tuser(0) => s_axis_tuser(0),
s_axis_tvalid => s_axis_tvalid
);
end STRUCTURE;
|
<gh_stars>0
--Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2018.3 (lin64) Build 2405991 Thu Dec 6 23:36:41 MST 2018
--Date : Mon Oct 28 17:03:38 2019
--Host : rabida running 64-bit Ubuntu 16.04.6 LTS
--Command : generate_target turing_bombe_without_zynq_wrapper.bd
--Design : turing_bombe_without_zynq_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity turing_bombe_without_zynq_wrapper is
port (
ADDRESS_BRAM_A : in STD_LOGIC_VECTOR ( 9 downto 0 );
CLK : in STD_LOGIC;
DATA_IN_BRAM_A : in STD_LOGIC_VECTOR ( 31 downto 0 );
DATA_OUT_BRAM_A : out STD_LOGIC_VECTOR ( 31 downto 0 );
ENABLE_BRAM_A : in STD_LOGIC;
LED_FIRST_STOP_OUT : out STD_LOGIC;
LED_FOURTH_STOP_OUT : out STD_LOGIC;
LED_SECOND_STOP_OUT : out STD_LOGIC;
LED_THIRD_STOP_OUT : out STD_LOGIC;
WRITE_ENABLE_BRAM_A : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end turing_bombe_without_zynq_wrapper;
architecture STRUCTURE of turing_bombe_without_zynq_wrapper is
component turing_bombe_without_zynq is
port (
CLK : in STD_LOGIC;
LED_FIRST_STOP_OUT : out STD_LOGIC;
LED_FOURTH_STOP_OUT : out STD_LOGIC;
LED_SECOND_STOP_OUT : out STD_LOGIC;
LED_THIRD_STOP_OUT : out STD_LOGIC;
ENABLE_BRAM_A : in STD_LOGIC;
DATA_IN_BRAM_A : in STD_LOGIC_VECTOR ( 31 downto 0 );
DATA_OUT_BRAM_A : out STD_LOGIC_VECTOR ( 31 downto 0 );
WRITE_ENABLE_BRAM_A : in STD_LOGIC_VECTOR ( 3 downto 0 );
ADDRESS_BRAM_A : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component turing_bombe_without_zynq;
begin
turing_bombe_without_zynq_i: component turing_bombe_without_zynq
port map (
ADDRESS_BRAM_A(9 downto 0) => ADDRESS_BRAM_A(9 downto 0),
CLK => CLK,
DATA_IN_BRAM_A(31 downto 0) => DATA_IN_BRAM_A(31 downto 0),
DATA_OUT_BRAM_A(31 downto 0) => DATA_OUT_BRAM_A(31 downto 0),
ENABLE_BRAM_A => ENABLE_BRAM_A,
LED_FIRST_STOP_OUT => LED_FIRST_STOP_OUT,
LED_FOURTH_STOP_OUT => LED_FOURTH_STOP_OUT,
LED_SECOND_STOP_OUT => LED_SECOND_STOP_OUT,
LED_THIRD_STOP_OUT => LED_THIRD_STOP_OUT,
WRITE_ENABLE_BRAM_A(3 downto 0) => WRITE_ENABLE_BRAM_A(3 downto 0)
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
library seven_seg_types;
use seven_seg_types.seven_seg_types.all;
use work.seven_seg.all;
entity seven_seg_display is
port (
clk : in std_ulogic;
digits : in digit_array_t(SEVEN_SEG_RANGE);
to_board : out seven_seg_interface_t
);
end;
architecture impl of seven_seg_display is
begin
assignments: for ii in SEVEN_SEG_RANGE generate
to_board(ii) <= SEVEN_SEG_MAP(digits(ii));
end generate;
end;
|
<filename>Practicas/Practica 6 - Contador Registro/code.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RC IS
PORT( CLR,CLK: IN STD_LOGIC;
C,E: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Q: INOUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE A_RC OF RC IS
SIGNAL AUX: STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL GRAY: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
conversorGray: process(aux)
BEGIN
gray<=to_stdlogicvector(to_bitvector(aux) xor to_bitvector(aux) srl 1);
END PROCESS conversorGray;
PROCESS(CLR,CLK,C)
BEGIN
IF(CLR='0')THEN
AUX<="000";
ELSIF(CLK'EVENT AND CLK='1')THEN
CASE C IS
--CARGA DE DATO
WHEN "000" => AUX<=E;
--CONTEO ASCENDENTE
WHEN "001" => AUX<=AUX+1;
--CONTEO DESCENDENTE
WHEN "010" => AUX<=AUX-1;
--RETENER
WHEN "011" => AUX<=AUX;
--CORRIMIENTO A LA DERECHA
WHEN "100"=> AUX<=TO_STDLOGICVECTOR(TO_BITVECTOR(AUX) SRL 1);
--CORRIMIENTO A LA IZQUIERDA
WHEN "101" => AUX<=TO_STDLOGICVECTOR(TO_BITVECTOR(AUX) SLL 1);
--CONTEO ASCENDENTE GRAY
WHEN "110" => AUX<=AUX+1;
--CONTEO DESCENDENTE GRAY
WHEN OTHERS => AUX<=AUX-1;
END CASE;
END IF
END PROCESS;
PROCESS(C,GRAY,AUX)
BEGIN
IF(C="110" OR C="111")THEN
Q<=GRAY;
ELSE
Q<=AUX;
END IF;
END PROCESS;
END A_RC;
|
library verilog;
use verilog.vl_types.all;
entity bcd_behavioral_vlg_sample_tst is
port(
Av : in vl_logic_vector(3 downto 0);
sampler_tx : out vl_logic
);
end bcd_behavioral_vlg_sample_tst;
|
library ieee;
use ieee.std_logic_1164.all;
entity mc is
port (
A : in std_logic_vector(1 downto 0); -- input
B : in std_logic_vector(1 downto 0); -- input
AequalB : out std_logic; -- A=B
AlessthanB : out std_logic; -- A<B
AmorethanB : out std_logic); -- A>B
end entity mc;
architecture mc_arc of mc is
component my_xnor is
port (
A : in std_logic; -- input
B : in std_logic; -- input
Y : out std_logic); -- output
end component my_xnor;
component my_or is
port (
A : in std_logic; -- input
B : in std_logic; -- input
Y : out std_logic); -- output
end component my_or;
component my_3ands is
port (
A : in std_logic; -- input
B : in std_logic; -- input
Y : out std_logic); -- output
end component my_3ands;
component my_not is
port (
A : in std_logic; -- input
Y : out std_logic); -- output
end component my_not;
signal temp : std_logic_vector(0 to 11);
begin -- architecture mc_arc
u0 : my_not port map (
A => A(0),
Y => temp(0));
u1 : my_not port map (
A => A(1),
Y => temp(1));
u2 : my_not port map (
A => B(0),
Y => temp(2));
u3 : my_not port map (
A => B(1),
Y => temp(3));
u4 : my_xnor port map (
A => A(1),
B => B(1),
Y => temp(4));
u5 : my_xnor port map (
A => A(0),
B => B(0),
Y => temp(5));
u6 : my_3ands port map (
A => temp(4),
B => temp(5),
Y => AequalB);
u7 : my_3ands port map (
A => temp(1),
B => B(1),
Y => temp(6));
u8 : my_3ands port map (
A => temp(0),
B => B(0),
Y => temp(7));
u9 : my_3ands port map (
A => temp(7),
B => temp(4),
Y => temp(8));
u10 : my_or port map (
A => temp(6),
B => temp(8),
Y => AlessthanB);
u11 : my_3ands port map (
A => A(1),
B => temp(3),
Y => temp(9));
u12 : my_3ands port map (
A => A(0),
B => temp(2),
Y => temp(10));
u13 : my_3ands port map (
A => temp(4),
B => temp(10),
Y => temp(11));
u14 : my_or port map (
A => temp(9),
B => temp(11),
Y => AmorethanB);
end architecture mc_arc;
|
------------------------------------------------------------------------------
-- Copyright [2014] [Ztachip Technologies Inc]
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except IN compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to IN writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
------------------------------------------------------------------------------
--------
--- Delay a vector by a number of clocks
--------
library std;
use std.standard.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.hpc_pkg.all;
entity delayv is
generic(
SIZE : integer;
DEPTH : integer
);
port(
SIGNAL clock_in : IN STD_LOGIC;
SIGNAL reset_in : IN STD_LOGIC;
SIGNAL in_in : IN STD_LOGIC_VECTOR(SIZE-1 DOWNTO 0);
SIGNAL out_out : OUT STD_LOGIC_VECTOR(SIZE-1 DOWNTO 0);
SIGNAL enable_in : IN STD_LOGIC
);
end delayv;
architecture delay_behaviour of delayv is
type fifo_t is array(natural range <>) of std_logic_vector(SIZE-1 downto 0);
signal fifo_r:fifo_t(DEPTH-1 downto 0);
begin
out_out <= fifo_r(0);
process(reset_in,clock_in)
begin
if reset_in='0' then
for I in 0 to DEPTH-1 loop
fifo_r(I) <= (others=>'0');
end loop;
else
if clock_in'event and clock_in='1' then
if DEPTH > 1 then
for I in 0 to DEPTH-2 loop
if enable_in='1' then
fifo_r(I) <= fifo_r(I+1);
end if;
end loop;
end if;
if enable_in='1' then
fifo_r(DEPTH-1) <= in_in;
end if;
end if;
end if;
end process;
end delay_behaviour;
|
<gh_stars>0
------------------------------------------------------------------------
-- Copyright (c) 2021-Present <NAME>
-- This work is licensed under the terms of the MIT license.
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tire_diameter is
port(
sw_i : in std_logic_vector(3 - 1 downto 0); -- Switches to select tire diameter
tire_diameter_o : out std_logic_vector(5 - 1 downto 0) -- Output to send selected value
);
end tire_diameter;
architecture testbench of tire_diameter is
begin
p_diameter : process(sw_i)
begin
case sw_i is
when "000" =>
tire_diameter_o <= "11101"; -- Combination "00" corresponds to the diameter of 29'' (737 mm)
when "001" =>
tire_diameter_o <= "11100"; -- Combination "01" corresponds to the diameter of 28'' (711 mm)
when "010" =>
tire_diameter_o <= "11011"; -- Combination "10" corresponds to the diameter of 27,5'' (699 mm)
when "011" =>
tire_diameter_o <= "11010"; -- Combination "10" corresponds to the diameter of 26'' (660 mm)
when "100" =>
tire_diameter_o <= "11000"; -- Combination "10" corresponds to the diameter of 24'' (610 mm)
when "101" =>
tire_diameter_o <= "10100"; -- Combination "10" corresponds to the diameter of 20'' (508 mm)
when "110" =>
tire_diameter_o <= "10000"; -- Combination "10" corresponds to the diameter of 16'' (406 mm)
when others =>
tire_diameter_o <= "01100"; -- Combination "11" corresponds to the diameter of 12'' (305 mm)
end case;
end process p_diameter;
end architecture testbench;
|
--------------------------------------------------------------------------------
-- Test : tb_avg16.vhd
-- Description:
-- This test verifies the avg16 block.
--
--------------------------------------------------------------------------------
-- library std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library work;
use work.tb_pkg.all;
entity tb is
end entity tb;
architecture sim of tb is
constant NUM_INPUTS : integer := 16;
constant DWIDTH : integer := 16;
signal clk : std_logic;
signal rst : std_logic;
type data_type is array(0 to NUM_INPUTS-1) of std_logic_vector(DWIDTH-1 downto 0);
signal i_data_array : data_type := (others => (others => '0'));
signal i_data_0 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal i_data_1 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal i_data_2 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal i_data_3 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal i_data_4 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal i_data_5 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal i_data_6 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal i_data_7 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal i_data_8 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal i_data_9 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal i_data_10 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal i_data_11 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal i_data_12 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal i_data_13 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal i_data_14 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal i_data_15 : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
signal o_avg : std_logic_vector(DWIDTH-1 downto 0);
signal test_done : std_logic := '0';
begin
u_avg16: entity work.avg16
generic map (
DWIDTH => DWIDTH
)
port map (
clk => clk, -- std_logic;
rst => rst, -- std_logic;
i_data_0 => i_data_array(0), -- in std_logic_vector(DWIDTH-1 downto 0);
i_data_1 => i_data_array(1), -- in std_logic_vector(DWIDTH-1 downto 0);
i_data_2 => i_data_array(2), -- in std_logic_vector(DWIDTH-1 downto 0);
i_data_3 => i_data_array(3), -- in std_logic_vector(DWIDTH-1 downto 0);
i_data_4 => i_data_array(4), -- in std_logic_vector(DWIDTH-1 downto 0);
i_data_5 => i_data_array(5), -- in std_logic_vector(DWIDTH-1 downto 0);
i_data_6 => i_data_array(6), -- in std_logic_vector(DWIDTH-1 downto 0);
i_data_7 => i_data_array(7), -- in std_logic_vector(DWIDTH-1 downto 0);
i_data_8 => i_data_array(8), -- in std_logic_vector(DWIDTH-1 downto 0);
i_data_9 => i_data_array(9), -- in std_logic_vector(DWIDTH-1 downto 0);
i_data_10 => i_data_array(10), -- in std_logic_vector(DWIDTH-1 downto 0);
i_data_11 => i_data_array(11), -- in std_logic_vector(DWIDTH-1 downto 0);
i_data_12 => i_data_array(12), -- in std_logic_vector(DWIDTH-1 downto 0);
i_data_13 => i_data_array(13), -- in std_logic_vector(DWIDTH-1 downto 0);
i_data_14 => i_data_array(14), -- in std_logic_vector(DWIDTH-1 downto 0);
i_data_15 => i_data_array(15), -- in std_logic_vector(DWIDTH-1 downto 0);
o_avg => o_avg -- out std_logic_vector(DWIDTH+3 downto 0)
);
-- generate clocks until test_done is asserted
process
begin
clkgen(clk,test_done);
wait; -- Simulation stops stop after clock stops
end process;
main_test: process
begin
report("reset dut");
pulse(rst, clk, 10);
report("After reset");
wait_re(clk,10);
for i in 0 to 15 loop
i_data_array(i) <= std_logic_vector(to_unsigned(i, DWIDTH));
end loop;
wait_re(clk,10);
for i in 0 to 15 loop
i_data_array(i) <= std_logic_vector(to_unsigned(3*i, DWIDTH));
end loop;
wait_re(clk,20);
report("test done"); -- severity NOTE, WARNING, ERROR, FAILURE (NOTE is default)
set(test_done);
wait;
end process main_test;
end architecture sim;
|
<filename>Ficheros VHD/GEN_COLOR.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity GEN_COLOR is
Port(
blank_h : in STD_LOGIC;
blank_v : in STD_LOGIC;
RED_in : in STD_LOGIC_VECTOR (2 downto 0);
GRN_in : in STD_LOGIC_VECTOR (2 downto 0);
BLUE_in : in STD_LOGIC_VECTOR (1 downto 0);
RED : out STD_LOGIC_VECTOR (2 downto 0);
GRN : out STD_LOGIC_VECTOR (2 downto 0);
BLUE : out STD_LOGIC_VECTOR (1 downto 0)
);
end GEN_COLOR;
architecture Behavioral of GEN_COLOR is
begin
gen_color:process(Blank_H, Blank_V, RED_in, GRN_in,BLUE_in)
begin
if (Blank_H='1' or Blank_V='1') then
RED<=(others => '0');
GRN<=(others => '0');
BLUE<=(others => '0');
else
RED<=RED_in;
GRN<=GRN_in;
BLUE<=BLUE_in;
end if;
end process;
end Behavioral;
|
-- © IBM Corp. 2020
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
-- the terms below; you may not use the files in this repository except in
-- compliance with the License as modified.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
--
-- Modified Terms:
--
-- 1) For the purpose of the patent license granted to you in Section 3 of the
-- License, the "Work" hereby includes implementations of the work of authorship
-- in physical form.
--
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
-- necessary for implementation of the Work that are available from OpenPOWER
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
-- of the EULA.
--
-- Unless required by applicable law or agreed to in writing, the reference design
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
-- for the specific language governing permissions and limitations under the License.
--
-- Additional rights, including the ability to physically implement a softcore that
-- is compliant with the required sections of the Power ISA Specification, are
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
--********************************************************************
--*
--* TITLE: Instruction buffer wrapper
--*
--* NAME: iuq_ib_buff_wrap.vhdl
--*
--*********************************************************************
library ieee;
use ieee.std_logic_1164.all;
library support;
use support.power_logic_pkg.all;
library work;
use work.iuq_pkg.all;
library tri;
use tri.tri_latches_pkg.all;
entity iuq_ib_buff_wrap is
generic(expand_type : integer := 2;
uc_ifar : integer := 21);
port(
vdd : inout power_logic;
gnd : inout power_logic;
nclk : in clk_logic;
pc_iu_func_sl_thold_2 : in std_ulogic_vector(0 to 3);
pc_iu_sg_2 : in std_ulogic_vector(0 to 3);
clkoff_b : in std_ulogic_vector(0 to 3);
an_ac_scan_dis_dc_b : in std_ulogic_vector(0 to 3);
tc_ac_ccflush_dc : in std_ulogic;
delay_lclkr : in std_ulogic_vector(5 to 8);
mpw1_b : in std_ulogic_vector(5 to 8);
iuq_b0_scan_in : in std_ulogic;
iuq_b0_scan_out : out std_ulogic;
iuq_b1_scan_in : in std_ulogic;
iuq_b1_scan_out : out std_ulogic;
iuq_b2_scan_in : in std_ulogic;
iuq_b2_scan_out : out std_ulogic;
iuq_b3_scan_in : in std_ulogic;
iuq_b3_scan_out : out std_ulogic;
spr_dec_mask_pt_in_t0 : in std_ulogic_vector(0 to 31);
spr_dec_mask_pt_in_t1 : in std_ulogic_vector(0 to 31);
spr_dec_mask_pt_in_t2 : in std_ulogic_vector(0 to 31);
spr_dec_mask_pt_in_t3 : in std_ulogic_vector(0 to 31);
spr_dec_mask_pt_out_t0 : out std_ulogic_vector(0 to 31);
spr_dec_mask_pt_out_t1 : out std_ulogic_vector(0 to 31);
spr_dec_mask_pt_out_t2 : out std_ulogic_vector(0 to 31);
spr_dec_mask_pt_out_t3 : out std_ulogic_vector(0 to 31);
fdep_dbg_data_pt_in : in std_ulogic_vector(0 to 87);
fdep_dbg_data_pt_out : out std_ulogic_vector(0 to 87);
fdep_perf_event_pt_in_t0 : in std_ulogic_vector(0 to 11);
fdep_perf_event_pt_in_t1 : in std_ulogic_vector(0 to 11);
fdep_perf_event_pt_in_t2 : in std_ulogic_vector(0 to 11);
fdep_perf_event_pt_in_t3 : in std_ulogic_vector(0 to 11);
fdep_perf_event_pt_out_t0 : out std_ulogic_vector(0 to 11);
fdep_perf_event_pt_out_t1 : out std_ulogic_vector(0 to 11);
fdep_perf_event_pt_out_t2 : out std_ulogic_vector(0 to 11);
fdep_perf_event_pt_out_t3 : out std_ulogic_vector(0 to 11);
pc_iu_trace_bus_enable : in std_ulogic;
pc_iu_event_bus_enable : in std_ulogic;
ib_dbg_data : out std_ulogic_vector(0 to 63);
ib_perf_event_t0 : out std_ulogic_vector(0 to 1);
ib_perf_event_t1 : out std_ulogic_vector(0 to 1);
ib_perf_event_t2 : out std_ulogic_vector(0 to 1);
ib_perf_event_t3 : out std_ulogic_vector(0 to 1);
xu_iu_flush : in std_ulogic_vector(0 to 3);
uc_flush_tid : in std_ulogic_vector(0 to 3);
fdec_ibuf_stall_t0 : in std_ulogic;
fdec_ibuf_stall_t1 : in std_ulogic;
fdec_ibuf_stall_t2 : in std_ulogic;
fdec_ibuf_stall_t3 : in std_ulogic;
ib_ic_below_water : out std_ulogic_vector(0 to 3);
ib_ic_empty : out std_ulogic_vector(0 to 3);
bp_ib_iu4_t0_val : in std_ulogic_vector(0 to 3);
bp_ib_iu4_t1_val : in std_ulogic_vector(0 to 3);
bp_ib_iu4_t2_val : in std_ulogic_vector(0 to 3);
bp_ib_iu4_t3_val : in std_ulogic_vector(0 to 3);
bp_ib_iu4_ifar_t0 : in EFF_IFAR;
bp_ib_iu3_0_instr_t0 : in std_ulogic_vector(0 to 31);
bp_ib_iu4_0_instr_t0 : in std_ulogic_vector(32 to 43);
bp_ib_iu4_1_instr_t0 : in std_ulogic_vector(0 to 43);
bp_ib_iu4_2_instr_t0 : in std_ulogic_vector(0 to 43);
bp_ib_iu4_3_instr_t0 : in std_ulogic_vector(0 to 43);
bp_ib_iu4_ifar_t1 : in EFF_IFAR;
bp_ib_iu3_0_instr_t1 : in std_ulogic_vector(0 to 31);
bp_ib_iu4_0_instr_t1 : in std_ulogic_vector(32 to 43);
bp_ib_iu4_1_instr_t1 : in std_ulogic_vector(0 to 43);
bp_ib_iu4_2_instr_t1 : in std_ulogic_vector(0 to 43);
bp_ib_iu4_3_instr_t1 : in std_ulogic_vector(0 to 43);
bp_ib_iu4_ifar_t2 : in EFF_IFAR;
bp_ib_iu3_0_instr_t2 : in std_ulogic_vector(0 to 31);
bp_ib_iu4_0_instr_t2 : in std_ulogic_vector(32 to 43);
bp_ib_iu4_1_instr_t2 : in std_ulogic_vector(0 to 43);
bp_ib_iu4_2_instr_t2 : in std_ulogic_vector(0 to 43);
bp_ib_iu4_3_instr_t2 : in std_ulogic_vector(0 to 43);
bp_ib_iu4_ifar_t3 : in EFF_IFAR;
bp_ib_iu3_0_instr_t3 : in std_ulogic_vector(0 to 31);
bp_ib_iu4_0_instr_t3 : in std_ulogic_vector(32 to 43);
bp_ib_iu4_1_instr_t3 : in std_ulogic_vector(0 to 43);
bp_ib_iu4_2_instr_t3 : in std_ulogic_vector(0 to 43);
bp_ib_iu4_3_instr_t3 : in std_ulogic_vector(0 to 43);
uc_ib_iu4_val : in std_ulogic_vector(0 to 3);
uc_ib_iu4_ifar_t0 : in std_ulogic_vector(62-uc_ifar to 61);
uc_ib_iu4_instr_t0 : in std_ulogic_vector(0 to 36);
uc_ib_iu4_ifar_t1 : in std_ulogic_vector(62-uc_ifar to 61);
uc_ib_iu4_instr_t1 : in std_ulogic_vector(0 to 36);
uc_ib_iu4_ifar_t2 : in std_ulogic_vector(62-uc_ifar to 61);
uc_ib_iu4_instr_t2 : in std_ulogic_vector(0 to 36);
uc_ib_iu4_ifar_t3 : in std_ulogic_vector(62-uc_ifar to 61);
uc_ib_iu4_instr_t3 : in std_ulogic_vector(0 to 36);
rm_ib_iu4_val : in std_ulogic_vector(0 to 3);
rm_ib_iu4_force_ram_t0 : in std_ulogic;
rm_ib_iu4_instr_t0 : in std_ulogic_vector(0 to 35);
rm_ib_iu4_force_ram_t1 : in std_ulogic;
rm_ib_iu4_instr_t1 : in std_ulogic_vector(0 to 35);
rm_ib_iu4_force_ram_t2 : in std_ulogic;
rm_ib_iu4_instr_t2 : in std_ulogic_vector(0 to 35);
rm_ib_iu4_force_ram_t3 : in std_ulogic;
rm_ib_iu4_instr_t3 : in std_ulogic_vector(0 to 35);
ib_ic_iu5_redirect_tid : out std_ulogic_vector(0 to 3);
iu_au_ib1_instr_vld_t0 : out std_ulogic;
iu_au_ib1_instr_vld_t1 : out std_ulogic;
iu_au_ib1_instr_vld_t2 : out std_ulogic;
iu_au_ib1_instr_vld_t3 : out std_ulogic;
iu_au_ib1_ifar_t0 : out EFF_IFAR;
iu_au_ib1_ifar_t1 : out EFF_IFAR;
iu_au_ib1_ifar_t2 : out EFF_IFAR;
iu_au_ib1_ifar_t3 : out EFF_IFAR;
iu_au_ib1_data_t0 : out std_ulogic_vector(0 to 49);
iu_au_ib1_data_t1 : out std_ulogic_vector(0 to 49);
iu_au_ib1_data_t2 : out std_ulogic_vector(0 to 49);
iu_au_ib1_data_t3 : out std_ulogic_vector(0 to 49)
);
end iuq_ib_buff_wrap;
architecture iuq_ib_buff_wrap of iuq_ib_buff_wrap is
begin
ibuff0 : entity work.iuq_ib_buff
generic map(
uc_ifar => uc_ifar,
expand_type => expand_type )
port map(
vdd => vdd,
gnd => gnd,
nclk => nclk,
pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(0),
pc_iu_sg_2 => pc_iu_sg_2(0),
clkoff_b => clkoff_b(0),
an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(0),
tc_ac_ccflush_dc => tc_ac_ccflush_dc,
delay_lclkr => delay_lclkr(5+0),
mpw1_b => mpw1_b(5+0),
scan_in => iuq_b0_scan_in,
scan_out => iuq_b0_scan_out,
spr_dec_mask_pt_in => spr_dec_mask_pt_in_t0,
spr_dec_mask_pt_out => spr_dec_mask_pt_out_t0,
fdep_dbg_data_pt_in => fdep_dbg_data_pt_in(22*0 to 22*0+21),
fdep_dbg_data_pt_out => fdep_dbg_data_pt_out(22*0 to 22*0+21),
fdep_perf_event_pt_in => fdep_perf_event_pt_in_t0,
fdep_perf_event_pt_out => fdep_perf_event_pt_out_t0,
pc_iu_trace_bus_enable => pc_iu_trace_bus_enable,
pc_iu_event_bus_enable => pc_iu_event_bus_enable,
ib_dbg_data => ib_dbg_data(16*0 to 16*0+15),
ib_perf_event => ib_perf_event_t0,
xu_iu_ib1_flush => xu_iu_flush(0),
uc_flush => uc_flush_tid(0),
fdec_ibuf_stall => fdec_ibuf_stall_t0,
ib_ic_below_water => ib_ic_below_water(0),
ib_ic_empty => ib_ic_empty(0),
bp_ib_iu4_ifar => bp_ib_iu4_ifar_t0,
bp_ib_iu4_val => bp_ib_iu4_t0_val,
bp_ib_iu3_0_instr => bp_ib_iu3_0_instr_t0,
bp_ib_iu4_0_instr => bp_ib_iu4_0_instr_t0,
bp_ib_iu4_1_instr => bp_ib_iu4_1_instr_t0,
bp_ib_iu4_2_instr => bp_ib_iu4_2_instr_t0,
bp_ib_iu4_3_instr => bp_ib_iu4_3_instr_t0,
uc_ib_iu4_ifar => uc_ib_iu4_ifar_t0,
uc_ib_iu4_val => uc_ib_iu4_val(0),
uc_ib_iu4_instr => uc_ib_iu4_instr_t0,
rm_ib_iu4_val => rm_ib_iu4_val(0),
rm_ib_iu4_force_ram => rm_ib_iu4_force_ram_t0,
rm_ib_iu4_instr => rm_ib_iu4_instr_t0,
ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid(0),
iu_au_ib1_valid => iu_au_ib1_instr_vld_t0,
iu_au_ib1_ifar => iu_au_ib1_ifar_t0,
iu_au_ib1_data => iu_au_ib1_data_t0
);
ibuff1 : entity work.iuq_ib_buff
generic map(
uc_ifar => uc_ifar,
expand_type => expand_type )
port map(
vdd => vdd,
gnd => gnd,
nclk => nclk,
pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(1),
pc_iu_sg_2 => pc_iu_sg_2(1),
clkoff_b => clkoff_b(1),
an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(1),
tc_ac_ccflush_dc => tc_ac_ccflush_dc,
delay_lclkr => delay_lclkr(5+1),
mpw1_b => mpw1_b(5+1),
scan_in => iuq_b1_scan_in,
scan_out => iuq_b1_scan_out,
spr_dec_mask_pt_in => spr_dec_mask_pt_in_t1,
spr_dec_mask_pt_out => spr_dec_mask_pt_out_t1,
fdep_dbg_data_pt_in => fdep_dbg_data_pt_in(22*1 to 22*1+21),
fdep_dbg_data_pt_out => fdep_dbg_data_pt_out(22*1 to 22*1+21),
fdep_perf_event_pt_in => fdep_perf_event_pt_in_t1,
fdep_perf_event_pt_out => fdep_perf_event_pt_out_t1,
pc_iu_trace_bus_enable => pc_iu_trace_bus_enable,
pc_iu_event_bus_enable => pc_iu_event_bus_enable,
ib_dbg_data => ib_dbg_data(16*1 to 16*1+15),
ib_perf_event => ib_perf_event_t1,
xu_iu_ib1_flush => xu_iu_flush(1),
uc_flush => uc_flush_tid(1),
fdec_ibuf_stall => fdec_ibuf_stall_t1,
ib_ic_below_water => ib_ic_below_water(1),
ib_ic_empty => ib_ic_empty(1),
bp_ib_iu4_ifar => bp_ib_iu4_ifar_t1,
bp_ib_iu4_val => bp_ib_iu4_t1_val,
bp_ib_iu3_0_instr => bp_ib_iu3_0_instr_t1,
bp_ib_iu4_0_instr => bp_ib_iu4_0_instr_t1,
bp_ib_iu4_1_instr => bp_ib_iu4_1_instr_t1,
bp_ib_iu4_2_instr => bp_ib_iu4_2_instr_t1,
bp_ib_iu4_3_instr => bp_ib_iu4_3_instr_t1,
uc_ib_iu4_ifar => uc_ib_iu4_ifar_t1,
uc_ib_iu4_val => uc_ib_iu4_val(1),
uc_ib_iu4_instr => uc_ib_iu4_instr_t1,
rm_ib_iu4_val => rm_ib_iu4_val(1),
rm_ib_iu4_force_ram => rm_ib_iu4_force_ram_t1,
rm_ib_iu4_instr => rm_ib_iu4_instr_t1,
ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid(1),
iu_au_ib1_valid => iu_au_ib1_instr_vld_t1,
iu_au_ib1_ifar => iu_au_ib1_ifar_t1,
iu_au_ib1_data => iu_au_ib1_data_t1
);
ibuff2 : entity work.iuq_ib_buff
generic map(
uc_ifar => uc_ifar,
expand_type => expand_type )
port map(
vdd => vdd,
gnd => gnd,
nclk => nclk,
pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(2),
pc_iu_sg_2 => pc_iu_sg_2(2),
clkoff_b => clkoff_b(2),
an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(2),
tc_ac_ccflush_dc => tc_ac_ccflush_dc,
delay_lclkr => delay_lclkr(5+2),
mpw1_b => mpw1_b(5+2),
scan_in => iuq_b2_scan_in,
scan_out => iuq_b2_scan_out,
spr_dec_mask_pt_in => spr_dec_mask_pt_in_t2,
spr_dec_mask_pt_out => spr_dec_mask_pt_out_t2,
fdep_dbg_data_pt_in => fdep_dbg_data_pt_in(22*2 to 22*2+21),
fdep_dbg_data_pt_out => fdep_dbg_data_pt_out(22*2 to 22*2+21),
fdep_perf_event_pt_in => fdep_perf_event_pt_in_t2,
fdep_perf_event_pt_out => fdep_perf_event_pt_out_t2,
pc_iu_trace_bus_enable => pc_iu_trace_bus_enable,
pc_iu_event_bus_enable => pc_iu_event_bus_enable,
ib_dbg_data => ib_dbg_data(16*2 to 16*2+15),
ib_perf_event => ib_perf_event_t2,
xu_iu_ib1_flush => xu_iu_flush(2),
uc_flush => uc_flush_tid(2),
fdec_ibuf_stall => fdec_ibuf_stall_t2,
ib_ic_below_water => ib_ic_below_water(2),
ib_ic_empty => ib_ic_empty(2),
bp_ib_iu4_ifar => bp_ib_iu4_ifar_t2,
bp_ib_iu4_val => bp_ib_iu4_t2_val,
bp_ib_iu3_0_instr => bp_ib_iu3_0_instr_t2,
bp_ib_iu4_0_instr => bp_ib_iu4_0_instr_t2,
bp_ib_iu4_1_instr => bp_ib_iu4_1_instr_t2,
bp_ib_iu4_2_instr => bp_ib_iu4_2_instr_t2,
bp_ib_iu4_3_instr => bp_ib_iu4_3_instr_t2,
uc_ib_iu4_ifar => uc_ib_iu4_ifar_t2,
uc_ib_iu4_val => uc_ib_iu4_val(2),
uc_ib_iu4_instr => uc_ib_iu4_instr_t2,
rm_ib_iu4_val => rm_ib_iu4_val(2),
rm_ib_iu4_force_ram => rm_ib_iu4_force_ram_t2,
rm_ib_iu4_instr => rm_ib_iu4_instr_t2,
ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid(2),
iu_au_ib1_valid => iu_au_ib1_instr_vld_t2,
iu_au_ib1_ifar => iu_au_ib1_ifar_t2,
iu_au_ib1_data => iu_au_ib1_data_t2
);
ibuff3 : entity work.iuq_ib_buff
generic map(
uc_ifar => uc_ifar,
expand_type => expand_type )
port map(
vdd => vdd,
gnd => gnd,
nclk => nclk,
pc_iu_func_sl_thold_2 => pc_iu_func_sl_thold_2(3),
pc_iu_sg_2 => pc_iu_sg_2(3),
clkoff_b => clkoff_b(3),
an_ac_scan_dis_dc_b => an_ac_scan_dis_dc_b(3),
tc_ac_ccflush_dc => tc_ac_ccflush_dc,
delay_lclkr => delay_lclkr(5+3),
mpw1_b => mpw1_b(5+3),
scan_in => iuq_b3_scan_in,
scan_out => iuq_b3_scan_out,
spr_dec_mask_pt_in => spr_dec_mask_pt_in_t3,
spr_dec_mask_pt_out => spr_dec_mask_pt_out_t3,
fdep_dbg_data_pt_in => fdep_dbg_data_pt_in(22*3 to 22*3+21),
fdep_dbg_data_pt_out => fdep_dbg_data_pt_out(22*3 to 22*3+21),
fdep_perf_event_pt_in => fdep_perf_event_pt_in_t3,
fdep_perf_event_pt_out => fdep_perf_event_pt_out_t3,
pc_iu_trace_bus_enable => pc_iu_trace_bus_enable,
pc_iu_event_bus_enable => pc_iu_event_bus_enable,
ib_dbg_data => ib_dbg_data(16*3 to 16*3+15),
ib_perf_event => ib_perf_event_t3,
xu_iu_ib1_flush => xu_iu_flush(3),
uc_flush => uc_flush_tid(3),
fdec_ibuf_stall => fdec_ibuf_stall_t3,
ib_ic_below_water => ib_ic_below_water(3),
ib_ic_empty => ib_ic_empty(3),
bp_ib_iu4_ifar => bp_ib_iu4_ifar_t3,
bp_ib_iu4_val => bp_ib_iu4_t3_val,
bp_ib_iu3_0_instr => bp_ib_iu3_0_instr_t3,
bp_ib_iu4_0_instr => bp_ib_iu4_0_instr_t3,
bp_ib_iu4_1_instr => bp_ib_iu4_1_instr_t3,
bp_ib_iu4_2_instr => bp_ib_iu4_2_instr_t3,
bp_ib_iu4_3_instr => bp_ib_iu4_3_instr_t3,
uc_ib_iu4_ifar => uc_ib_iu4_ifar_t3,
uc_ib_iu4_val => uc_ib_iu4_val(3),
uc_ib_iu4_instr => uc_ib_iu4_instr_t3,
rm_ib_iu4_val => rm_ib_iu4_val(3),
rm_ib_iu4_force_ram => rm_ib_iu4_force_ram_t3,
rm_ib_iu4_instr => rm_ib_iu4_instr_t3,
ib_ic_iu5_redirect_tid => ib_ic_iu5_redirect_tid(3),
iu_au_ib1_valid => iu_au_ib1_instr_vld_t3,
iu_au_ib1_ifar => iu_au_ib1_ifar_t3,
iu_au_ib1_data => iu_au_ib1_data_t3
);
end iuq_ib_buff_wrap;
|
library ieee;
use ieee.std_logic_1164.all;
package branch_prediction is
constant DEFAULT_BHT_BITS : integer := 4;
component bp_predict_not_taken is
port(
clock : in std_logic;
reset : in std_logic;
pc : in std_logic_vector(31 downto 0);
update : in std_logic; -- '1' if a prediction should be updated, '0' otherwise
previous_pc : in std_logic_vector(31 downto 0);
previous_prediction : in std_logic;
prediction_incorrect : in std_logic; -- '1' if prediction was incorrect, '0' otherwise
prediction : out std_logic -- '1' = predict taken, '0' = predict not taken
);
end component;
component bp_predict_taken is
port(
clock : in std_logic;
reset : in std_logic;
pc : in std_logic_vector(31 downto 0);
update : in std_logic; -- '1' if a prediction should be updated, '0' otherwise
previous_pc : in std_logic_vector(31 downto 0);
previous_prediction : in std_logic;
prediction_incorrect : in std_logic; -- '1' if prediction was incorrect, '0' otherwise
prediction : out std_logic -- '1' = predict taken, '0' = predict not taken
);
end component;
component bp_1bit_predictor is
generic(BHT_BITS : integer := DEFAULT_BHT_BITS);
port(
clock : in std_logic;
reset : in std_logic;
pc : in std_logic_vector(31 downto 0);
update : in std_logic; -- '1' if a prediction should be updated, '0' otherwise
previous_pc : in std_logic_vector(31 downto 0);
previous_prediction : in std_logic;
prediction_incorrect : in std_logic; -- '1' if prediction was incorrect, '0' otherwise
prediction : out std_logic -- '1' = predict taken, '0' = predict not taken
);
end component;
component bp_2bit_predictor is
generic(BHT_BITS : integer := DEFAULT_BHT_BITS);
port(
clock : in std_logic;
reset : in std_logic;
pc : in std_logic_vector(31 downto 0);
update : in std_logic; -- '1' if a prediction should be updated, '0' otherwise
previous_pc : in std_logic_vector(31 downto 0);
previous_prediction : in std_logic;
prediction_incorrect : in std_logic; -- '1' if prediction was incorrect, '0' otherwise
prediction : out std_logic -- '1' = predict taken, '0' = predict not taken
);
end component;
component bp_correlating_2_2 is
generic(BHT_BITS : integer := DEFAULT_BHT_BITS);
port(
clock : in std_logic;
reset : in std_logic;
pc : in std_logic_vector(31 downto 0);
update : in std_logic; -- '1' if a prediction should be updated, '0' otherwise
previous_pc : in std_logic_vector(31 downto 0);
previous_prediction : in std_logic;
prediction_incorrect : in std_logic; -- '1' if prediction was incorrect, '0' otherwise
prediction : out std_logic -- '1' = predict taken, '0' = predict not taken
);
end component;
component bp_tournament_2_2 is
generic(BHT_BITS : integer := DEFAULT_BHT_BITS);
port(
clock : in std_logic;
reset : in std_logic;
pc : in std_logic_vector(31 downto 0);
update : in std_logic; -- '1' if a prediction should be updated, '0' otherwise
previous_pc : in std_logic_vector(31 downto 0);
previous_prediction : in std_logic;
prediction_incorrect : in std_logic; -- '1' if prediction was incorrect, '0' otherwise
prediction : out std_logic -- '1' = predict taken, '0' = predict not taken
);
end component;
end branch_prediction;
|
<reponame>Jonacodez/EPO-3
library IEEE;
use IEEE.std_logic_1164.ALL;
architecture tb of shift_reg_tb is
component shift_reg
port(input : in std_logic_vector(4 downto 0);
clk : in std_logic;
shift : in std_logic;
output0 : out std_logic_vector(4 downto 0);
output1 : out std_logic_vector(4 downto 0);
output2 : out std_logic_vector(4 downto 0);
output3 : out std_logic_vector(4 downto 0);
output4 : out std_logic_vector(4 downto 0);
output5 : out std_logic_vector(4 downto 0);
output6 : out std_logic_vector(4 downto 0);
output7 : out std_logic_vector(4 downto 0));
end component;
signal input : std_logic_vector(4 downto 0);
signal clk : std_logic;
signal shift : std_logic;
signal output0 : std_logic_vector(4 downto 0);
signal output1 : std_logic_vector(4 downto 0);
signal output2 : std_logic_vector(4 downto 0);
signal output3 : std_logic_vector(4 downto 0);
signal output4 : std_logic_vector(4 downto 0);
signal output5 : std_logic_vector(4 downto 0);
signal output6 : std_logic_vector(4 downto 0);
signal output7 : std_logic_vector(4 downto 0);
begin
test: shift_reg port map (input, clk, shift, output0, output1, output2, output3, output4, output5, output6, output7);
clk <= '0' after 0 ns,
'1' after 5 ns when clk /= '1' else '0' after 5 ns;
input <= "10101" after 20 ns,
"01010" after 41 ns,
"00000" after 101 ns;
shift <= '0' after 0 ns,
'1' after 20 ns,
'0' after 37 ns,
'1' after 60 ns,
'0' after 67 ns,
'1' after 120 ns,
'0' after 127 ns,
'1' after 160 ns,
'0' after 167 ns,
'1' after 200 ns,
'0' after 207 ns,
'1' after 240 ns,
'0' after 247 ns,
'1' after 280 ns,
'0' after 287 ns,
'1' after 320 ns,
'0' after 327 ns;
end tb;
|
--=============================================================================
--company : www.fpga-systems.ru
--developer : KeisN13
--e-mail : <EMAIL>
--description : simple D-flipflop
--version : 1.0
--=============================================================================
-- CHANGES LOG --
-------------------------------------------------------------------------------
-- who/when | ver | changes description --
-------------------------------------------------------------------------------
-- KeisN13 | 1.0 | Initial version of module
-------------------------------------------------------------------------------
--
--=============================================================================
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.parameters.all;
entity dff is
port (
id : in std_logic ;
iclk : in std_logic ;
oq : out std_logic
);
end dff;
architecture rtl of dff is
begin
dff_generic: if C_DFF_TYPE = "GENERIC" generate
begin
dff: process(iclk)
begin
if rising_edge (iclk) then
oq <= id;
end if;
end process;
end generate;
dff_macro: if C_DFF_TYPE = "MACRO" generate
begin
inst_fdre : fdre
generic map (
init => '0') -- initial value of register ('0' or '1')
port map (
q => oq, -- data output
c => iclk, -- clock input
ce => '1', -- clock enable input
r => '0', -- synchronous reset input
d => id -- data input
);
end generate;
end rtl;
|
<gh_stars>0
--------------------------------------------------------------------------------
-- Author : Xilinx
--------------------------------------------------------------------------------
-- (c) Copyright 2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- Device: Ultrascale
-- Entity Name: gig_ethernet_pcs_pma_0_BaseX_Byte
-- Purpose: Create a byte (two nibbles) that can be used for 1000BaseX designs
--
-- Tools: Vivado_2015.1
-- Limitations: none
--
-- Vendor: Xilinx Inc.
-- Version: 0.01
-- Filename: gig_ethernet_pcs_pma_0_BaseX_Byte.vhd
-- Date Created: Feb 2015
-- Date Last Modified: Jun 2015
-- Revision History:
-- Rev. Jun 2015
-- Following the new rules, changed IO delay lines to TIME mode and BISC needs to be
-- turned on. It is required that SERIAL mode uses TIME mode for the delay lines.
-- VTC control must be turned OFF in order to make it possible to step
-- through the delay lines an not get corrected by BISC VTC tracking.
--
-- Rev 2.0 01-13-2016 - <NAME>
-- Changed C_Rx_Self_Calibrate to ENABLE
-- Changed C_Rx_Delay_Format to TIME
-- Added BaseX_Riu_Prsnt port
-- Removed Tx_EnVtcPip Logic (moved to Clock_Reset)
-- Changed Tx_En_Vtc to Tx_Bs_En_Vtc
-- Changed Rx_En_Vtc to Rx_Bs_En_Vtc
-- Changed C_Rx_Clk_Phase_p|n to SHIFT_0
--
-- Rev 2.0 02-05-2016 - <NAME>
-- Changed Tx_Data_Width to 8
-- Changed C_Div_Mode to 4 for Tx_Nibble
-- Changed C_Output_Phase_90 to TRUE for Tx_Nibble
-- Changed IntTx_Riu_Nibble_Sel to always be (1) or Low
-- Changed IntRx_Riu_Nibble_Sel to always be (0) or Low
--
---------------------------------------------------------------------------------------------
-- Naming Conventions:
-- Generics start with: "C_*"
-- Ports
-- All words in the label of a port name start with a upper case, AnInputPort.
-- Active low ports end in "*_n"
-- Active high ports of a differential pair end in: "*_p"
-- Ports being device pins end in _pin "*_pin"
-- Reset ports end in: "*Rst"
-- Enable ports end in: "*Ena", "*En"
-- Clock ports end in: "*Clk", "ClkDiv", "*Clk#"
-- Signals and constants
-- Signals and constant labels start with "Int*"
-- Registered signals end in "_d#"
-- User defined types: "*_TYPE"
-- State machine next state: "*_Ns"
-- State machine current state: "*_Cs"
-- Counter signals end in: "*Cnt", "*Cnt_n"
-- Processes: "<Entity_><Function>_PROCESS"
-- Component instantiations: "<Entity>_I_<Component>_<Function>"
---------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_UNSIGNED.all;
library UNISIM;
use UNISIM.vcomponents.all;
library gig_ethernet_pcs_pma_v16_2_6;
use gig_ethernet_pcs_pma_v16_2_6.NativePkg.all;
---------------------------------------------------------------------------------------------
-- Entity pin description
---------------------------------------------------------------------------------------------
-- C_IoBank : Number of the IO-Bank in which to place to byte.
-- C_BytePosition : Position of the byte in the chosen IO-Bank (0, 1, 2 or 3)
-- C_UseTxRiu : Use the TX side RIU when set to 1.
-- C_UseRxRiu : Use the RX side RIU when set to 1.
-- C_TxInUpperNibble : Place the transmitter in the upper or lower nibble in the byte.
-- : When the transmitter is in the upper byte the receiver is in the
-- : lower and vice versa. 1=TX in Upper nibble of the byte.
-- C_Tx_UsedBitslices : A '1' inserts a BITSLICE. Always seven positions must be given.
-- C_Rx_UsedBitslices : When one is placed in the lower nibble, bit seven must be set to '0'.
-- : Exmpl: TX in upper, RX in Lower = "1111111" - "0111111"
-- : TX in lower, RX in upper = "0111111" - "1111111"
-- C_Tx_BtslceTr : Define the input of the 3-state of the transmitter, "T" or "TBYTE"
-- : 'T' uses the fabric 3-state input on the TX_BITSLICE.
-- : "TBYTE" uses the serialized 3-state on the BITSLICE_CONTROL.
-- C_Tx_BtslceUsedAsT : When "TBYTE" is defined above, TX_BITSLICES can be used with the 'T'
-- : input. Define here (set '1') what TX_BITSLICES used 'T', all other
-- : will use "TBYTE". Default this is set to "0000000" (use none).
-- C_Rx_BtslcNulType : Define the function of RX_BITSLICE_0, "DATA_AND_CLOCK", "DATA" or
-- : "CLOCK". Not applicable to SERIAL mode (SGMII).
--
-- The different buses switch with the value of the C_TxInUpperNibble attribute.
-- The switch means that the size of some buses will change depending the position of the
-- transmitter or receiver of that the position of bits in a bus will flip depending the
-- position of transmitter or receiver.
-- Example:
-- BaseX_Rx_Fifo_Empty, when C_TxInUpperNibble = 1, the Receiver is placed in the lower
-- nibble. The width of the bus is then [5:0] = 6 bit. When C_TxInUpperNibble = 0 the
-- Receiver goes in teh upper nibble and the bus will have 7 bits.
--
-- BaseX_Riu_Rd_Data: This bus is 32 bit wide. When C_TxInUpperNibble = 1 the RIU_RD_DATA
-- output of the BITSLICE_CONROL of the transmitter will be in the upper [31:16} word of
-- the bus. The lower part is for the RIU_RD_DATA of the receiver. When C_TxInUpperNibble
-- equals 0, the RIU_RD_DATA of the receiver is put at [31:0].
--
-- The BITSLICEs are used in SERIAL mode, 4-bits,
---------------------------------------------------------------------------------------------
entity gig_ethernet_pcs_pma_0_BaseX_Byte is
generic (
C_Part : string := "XCKU060";
C_IoBank : integer := 44;
C_BytePosition : integer := 0;
C_UseTxRiu : integer := 0;
C_UseRxRiu : integer := 1;
C_TxInUpperNibble : integer := 1;
C_Tx_UsedBitslices : std_logic_vector(6 downto 0) := "0111111";
C_Rx_UsedBitslices : std_logic_vector(6 downto 0) := "0111111";
C_Tx_BtslceTr : string := "T";
C_Tx_BtslceUsedAsT : std_logic_vector(6 downto 0) := "0000000";
C_Rx_BtslcNulType : string := "DATA"; -- "SERIAL"
C_Tx_Self_Calibrate : string := "DISABLE";
C_Tx_Serial_Mode : string := "FALSE";
C_Tx_Data_Width : integer := 8;
C_Tx_Delay_Format : string := "COUNT";
C_Tx_Delay_Type : string := "FIXED";
C_Tx_Delay_Value : integer := 0;
C_Tx_RefClk_Frequency : real := 1250.000;
C_Rx_Self_Calibrate : string := "ENABLE";
C_Rx_Serial_Mode : string := "TRUE";
C_Rx_Data_Width : integer := 4;
C_Rx_Delay_Format : string := "COUNT";
C_Rx_Delay_Type : string := "VAR_LOAD";
C_Rx_Delay_Value : integer := 0;
C_Rx_RefClk_Frequency : real := 312.500
);
port (
BaseX_Tx_Bsc_Rst : in std_logic; --
BaseX_Rx_Bsc_Rst : in std_logic; --
BaseX_Tx_Bs_Rst : in std_logic; --
BaseX_Rx_Bs_Rst : in std_logic; --
BaseX_Tx_Rst_Dly : in std_logic; --
BaseX_Rx_Rst_Dly : in std_logic; --
BaseX_Tx_Bsc_En_Vtc : in std_logic; --
BaseX_Rx_Bsc_En_Vtc : in std_logic; --
BaseX_Tx_Bs_En_Vtc : in std_logic; --
BaseX_Rx_Bs_En_Vtc : in std_logic; --
BaseX_Riu_Clk : in std_logic; --
BaseX_Riu_Addr : in std_logic_vector(5 downto 0); --
BaseX_Riu_Wr_Data : in std_logic_vector(15 downto 0); --
BaseX_Riu_Rd_Data : out std_logic_vector(15 downto 0); --
BaseX_Riu_Valid : out std_logic; --
BaseX_Riu_Prsnt : out std_logic; --
BaseX_Riu_Wr_En : in std_logic; --
BaseX_Riu_Nibble_Sel : in std_logic_vector(1 downto 0); --
BaseX_Tx_Pll_Clk : in std_logic; --
BaseX_Rx_Pll_Clk : in std_logic; --
BaseX_Tx_Dly_Rdy : out std_logic; --
BaseX_Rx_Dly_Rdy : out std_logic; --
BaseX_Tx_Vtc_Rdy : out std_logic; --
BaseX_Rx_Vtc_Rdy : out std_logic; --
BaseX_Tx_Phy_Rden : in std_logic_vector(3 downto 0); --
BaseX_Rx_Phy_Rden : in std_logic_vector(3 downto 0); --
-- Control the BITSLICEs
BaseX_Rx_Fifo_Rd_Clk : in std_logic; --
BaseX_Rx_Fifo_Rd_En : in std_logic_vector((7-C_TxInUpperNibble)-1 downto 0); --
BaseX_Rx_Fifo_Empty : out std_logic_vector((7-C_TxInUpperNibble)-1 downto 0); --
-- Delay lines
BaseX_Dly_Clk : in std_logic; --
BaseX_Idly_Ce : in std_logic_vector((7-C_TxInUpperNibble)-1 downto 0); --
BaseX_Idly_Inc : in std_logic_vector((7-C_TxInUpperNibble)-1 downto 0); --
BaseX_Idly_Load : in std_logic_vector((7-C_TxInUpperNibble)-1 downto 0); --
BaseX_Idly_CntValueIn : in std_logic_vector(((7-C_TxInUpperNibble)*9)-1 downto 0); --
BaseX_Idly_CntValueOut : out std_logic_vector(((7-C_TxInUpperNibble)*9)-1 downto 0); --
BaseX_Odly_Ce : in std_logic_vector((6+C_TxInUpperNibble)-1 downto 0); --
BaseX_Odly_Inc : in std_logic_vector((6+C_TxInUpperNibble)-1 downto 0); --
BaseX_Odly_Load : in std_logic_vector((6+C_TxInUpperNibble)-1 downto 0); --
BaseX_Odly_CntValueIn : in std_logic_vector(((6+C_TxInUpperNibble)*9)-1 downto 0); --
BaseX_Odly_CntValueOut : out std_logic_vector(((6+C_TxInUpperNibble)*9)-1 downto 0); ---
BaseX_TriOdly_Ce : in std_logic; --
BaseX_TriOdly_Inc : in std_logic; --
BaseX_TriOdly_Load : in std_logic; --
BaseX_TriOdly_CntValueIn : in std_logic_vector(8 downto 0); --
BaseX_TriOdly_CntValueOut : out std_logic_vector(8 downto 0); --
-- FPGA fabric connections
BaseX_Tx_TbyteIn : in std_logic_vector(3 downto 0); --
BaseX_Tx_T_In : in std_logic_vector((6+C_TxInUpperNibble)-1 downto 0); --
BaseX_Tx_D_In : in std_logic_vector(((6+C_TxInUpperNibble)*8)-1 downto 0); --
BaseX_Rx_Q_Out : out std_logic_vector(((7-C_TxInUpperNibble)*4)-1 downto 0); --
BaseX_Rx_Q_CombOut : out std_logic_vector((7-C_TxInUpperNibble)-1 downto 0); --
-- Connections to/from IOBs
BaseX_Tx_Tri_Out : out std_logic_vector((6+C_TxInUpperNibble)-1 downto 0); --
BaseX_Tx_Data_Out : out std_logic_vector((6+C_TxInUpperNibble)-1 downto 0); --
BaseX_Rx_Data_In : in std_logic_vector((7-C_TxInUpperNibble)-1 downto 0); --
Tx_RdClk : in std_logic
--
);
end gig_ethernet_pcs_pma_0_BaseX_Byte;
---------------------------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------------------------
architecture BaseX_Byte_arch of gig_ethernet_pcs_pma_0_BaseX_Byte is
---------------------------------------------------------------------------------------------
-- Component Instantiation
---------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Constants, Signals and Attributes Declarations
---------------------------------------------------------------------------------------------
-- Functions
-- Constants
constant Low : std_logic := '0';
constant High : std_logic := '1';
constant LowVec : std_logic_vector(127 downto 0) := (others => '0');
constant HighVec : std_logic_vector(127 downto 0) := (others => '1');
-- Signals
signal IntTx_Riu_Rd_Data : std_logic_vector(15 downto 0);
signal IntTx_Riu_Valid : std_logic;
signal IntTx_Riu_Wr_En : std_logic;
signal IntTx_Riu_Nibble_Sel : std_logic;
signal IntRx_Riu_Rd_Data : std_logic_vector(15 downto 0);
signal IntRx_Riu_Valid : std_logic;
signal IntRx_Riu_Prsnt : std_logic;
signal IntRx_Riu_Wr_En : std_logic;
signal IntRx_Riu_Nibble_Sel : std_logic;
signal IntRx_Fifo_Rd_Clk : std_logic_vector((7-C_TxInUpperNibble)-1 downto 0);
signal IntBaseX_Tx_Dly_Rdy : std_logic;
signal IntBaseX_Rx_Dly_Rdy : std_logic;
signal IntBaseX_Tx_Vtc_Rdy : std_logic;
signal IntBaseX_Rx_Vtc_Rdy : std_logic;
signal IntActTx_TByteinPip : std_logic_vector(1 downto 0);
signal IntActiveTx_TBytein : std_logic_vector(3 downto 0);
-- Attributes
attribute ASYNC_REG :string;
attribute ASYNC_REG of IntActTx_TByteinPip: signal is "TRUE";
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of BaseX_Byte_arch : architecture is "TRUE";
attribute LOC : string;
-- attribute LOC of : label is ;
---------------------------------------------------------------------------------------------
component gig_ethernet_pcs_pma_0_Rx_Nibble
generic (
-- Globals
C_Part : string := "XCKU060"; -- Part number
C_IoBank : integer := 44; -- Number of the IO-Bank.
C_NibbleType : integer := 7; -- Upper = 7 or Lower = 6
C_BytePosition : integer := 0; -- 0, 1, 2 or 3 (View PDF page 8)
C_UsedBitslices : std_logic_vector(6 downto 0) := "1111111";
-- A BITSLICE is used when indicated by "1" (view PDF page 18)
-- When C_NibbleType = 6, MSB bit of C_UsedBitslices MUST be "0".
-- The bits in input or output buses by a TX or RX BITSLICE will
-- be tied to GND(outputs) or left unconnected (inputs).
-- BE CAREFUL TO NOT USE THESE BITS IN THE FPGA FABRIC.
C_BtslcNulType : string := "SERIAL"; -- "DATA", "CLOCK", "SERIAL"
---------------------------------------------------------------------------------------------
-- BITSLICE_Control
C_Ctrl_Clk : string := "EXTERNAL";
C_Div_Mode : string := "DIV2";
C_En_Clk_To_Ext_North : string := "DISABLE";
C_En_Clk_To_Ext_South : string := "DISABLE";
C_En_Dyn_Odly_Mode : string := "FALSE";
C_En_Other_Nclk : string := "FALSE";
C_En_Other_Pclk : string := "FALSE";
C_Idly_Vt_Track : string := "TRUE";
C_Inv_Rxclk : string := "FALSE";
C_Odly_Vt_Track : string := "TRUE";
C_Qdly_Vt_Track : string := "TRUE";
C_Read_Idle_Count : std_logic_vector(5 downto 0) := "000000";
C_RefClk_Src : string := "PLLCLK";
C_Rounding_Factor : integer := 16;
C_RxGate_Extend : string := "FALSE";
C_Rx_Clk_Phase_n : string := "SHIFT_0";
C_Rx_Clk_Phase_p : string := "SHIFT_0";
C_Rx_Gating : string := "DISABLE";
C_Self_Calibrate : string := "ENABLE";
C_Serial_Mode : string := "FALSE";
C_Tx_Gating : string := "DISABLE";
-- RX and TX common BITSLICE attributes / generics
C_Rx_Data_Width : integer := 4;
-- RX and TX common delay line attributes.
C_Delay_Format : string := "COUNT";
C_Delay_Type : string := "VAR_LOAD";
C_Delay_Value : integer := 0;
C_RefClk_Frequency : real := 312.5;
C_Update_Mode : string := "ASYNC";
C_Is_Clk_Inverted : bit := '0';
C_Is_Rst_Dly_Inverted : bit := '0';
C_Is_Rst_Inverted : bit := '0';
-- RX_BITSLICE (For now all RX_BITSLICEs need to have the same arguments of operation)
C_Cascade : string := "FALSE";
C_Delay_Value_Ext : integer := 0;
C_Update_Mode_Ext : string := "ASYNC";
C_Fifo_Sync_Mode : string := "FALSE";
C_Is_Clk_Ext_Inverted : bit := '0';
C_Is_Rst_Dly_Ext_Inverted : bit := '0';
---------------------------------------------------------------------------------------
-- ! DO NOT CHANGE THE GENERICS GIVEN BELOW !
---------------------------------------------------------------------------------------
-- In and out buses, part of the ribbon cable.
C_BusRxBitCtrlOut : integer := 40;
C_BusRxBitCtrlIn : integer := 40;
C_BusTxBitCtrlOut : integer := 40;
C_BusTxBitCtrlIn : integer := 40;
C_BusTxBitCtrlOutTri : integer := 40;
C_BusTxBitCtrlInTri : integer := 40;
C_CntValue : integer := 9
);
port (
-- Global
Rx_Bsc_Rst : in std_logic;
Rx_Bs_Rst : in std_logic;
Rx_Rst_Dly : in std_logic;
Rx_Bsc_En_Vtc : in std_logic;
Rx_Bs_En_Vtc : in std_logic;
-- Bitslics_control
Rx_Riu_Clk : in std_logic;
Rx_Riu_Addr : in std_logic_vector(5 downto 0);
Rx_Riu_Wr_Data : in std_logic_vector(15 downto 0);
Rx_Riu_Rd_Data : out std_logic_vector(15 downto 0);
Rx_Riu_Valid : out std_logic;
Rx_Riu_Prsnt : out std_logic;
Rx_Riu_Wr_En : in std_logic;
Rx_Riu_Nibble_Sel : in std_logic;
--
Rx_Pll_Clk : in std_logic;
Rx_RefClk : in std_logic;
Rx_Dly_Rdy : out std_logic;
Rx_Vtc_Rdy : out std_logic;
Rx_Dyn_Dci : out std_logic_vector(6 downto 0);
--
Rx_Tbyte_In : in std_logic_vector(3 downto 0);
Rx_Phy_Rden : in std_logic_vector(3 downto 0);
--
Rx_Clk_From_Ext : in std_logic := '1';
Rx_Pclk_Nibble_In : in std_logic;
Rx_Nclk_Nibble_In : in std_logic;
Rx_Nclk_Nibble_Out : out std_logic;
Rx_Pclk_Nibble_Out : out std_logic;
Rx_Clk_To_Ext_North : out std_logic;
Rx_Clk_To_Ext_South : out std_logic;
-- BITSLICEs from IO
-- Depending the C_NibbleType these buses will have seven or six bits.
Rx_Data_In : in std_logic_vector(C_NibbleType-1 downto 0);
-- BITSLICEs to the FPGA Fabric
-- The size of FPGA fabric side input and output buses depends from different
-- attributes (C_NibbleType, C_Rx_Data_Width and C_CntValue). These buses can thus
-- Have different widths.
-- Depending the C_UsedBitslices attribute, when a '0' is inserted to not instantiate
-- a BITSLICE, these buses can contain C_Rx_Data_Width parts
-- being pulled low or left floating.
-- View the synthesis log files to find what C_Rx_Data_Width wide part of a bus is
-- pulled low or left floating.
Rx_Q_Out : out std_logic_vector((C_NibbleType*C_Rx_Data_Width)-1 downto 0);
-- RX_Q_CombOut is only available when the RX_BITSLICE is put in 4-bit mode.
-- This output is the Q(5) output of the BITSLICE. [3:0] are used as 4-bit output and
-- (5) is equal to the serial input of the RX_BITSLICE.
Rx_Q_CombOut : out std_logic_vector(C_NibbleType-1 downto 0);
--
Fifo_Rd_Clk : in std_logic_vector(C_NibbleType-1 downto 0);
Fifo_Wrclk_Out : out std_logic;
Fifo_Rd_En : in std_logic_vector(C_NibbleType-1 downto 0);
Fifo_Empty : out std_logic_vector(C_NibbleType-1 downto 0);
-- IO-DELAY RX_BITSLICEs
Rx_Ce : in std_logic_vector(C_NibbleType-1 downto 0);
Rx_Clk : in std_logic;
Rx_Inc : in std_logic_vector(C_NibbleType-1 downto 0);
Rx_Load : in std_logic_vector(C_NibbleType-1 downto 0);
Rx_CntValueIn : in std_logic_vector((C_NibbleType*C_CntValue)-1 downto 0);
Rx_CntValueOut : out std_logic_vector((C_NibbleType*C_CntValue)-1 downto 0);
Rx_Ce_Ext : in std_logic_vector(C_NibbleType-1 downto 0);
Rx_Inc_Ext : in std_logic_vector(C_NibbleType-1 downto 0);
Rx_Load_Ext : in std_logic_vector(C_NibbleType-1 downto 0);
Rx_CntValueIn_Ext : in std_logic_vector((C_NibbleType*C_CntValue)-1 downto 0);
Rx_CntValueOut_Ext : out std_logic_vector((C_NibbleType*C_CntValue)-1 downto 0)
);
end component;
component gig_ethernet_pcs_pma_0_Tx_Nibble
generic (
-- Globals
C_Part : string := "XCKU060"; -- Used part number
C_IoBank : integer := 44; -- Number of the IO-Bank.
C_NibbleType : integer := 7; -- Upper = 7 or Lower = 6
C_BytePosition : integer := 0; -- 0, 1, 2 or 3 (View PDF page 8)
C_UsedBitslices : std_logic_vector(6 downto 0) := "1111111";
-- A BITSLICE is used when indicated by "1".
-- When C_NibbleType = 6, the Lower Nibble in a byte is used.
-- When C_NibbleType = 7, the Upper Nibble in a byte is used.
-- When C_NibbleType = 6, MSB bit of C_UsedBitslices MUST be "0".
-- Each bit represents a BITSLICE, a BITSLICE has a single ended IO
-- connected to it. When using differential IO make sure to not
-- instantiate the n-side BITSLICE.
-- The bits in input or output buses facing the FPGA logic for
-- TX or RX BITSLICE will be tied to GND(outputs) or left
-- unconnected (inputs).
-- BE CAREFUL TO NOT USE THESE BITS IN THE FPGA FABRIC.
C_Tx_BtslceTr : string := "T";
C_BtslceUsedAsT : std_logic_vector(6 downto 0) := "0000000";
-- The above attributes have only sense when used in transmit mode.
-- T : Defines per used BITSLICE that the tristate is coming
-- straight from the FPGA logic. All used BITSLICEs are using T
-- or direct FPGA logic input tristate.
-- TBYTE_IN: Defines that the used BITSLICEs are tristate by a
-- connected TX_BIYTSLICE_TRI. The TX_BITSLICE_TRI serializes the
-- Tx_Tbyte_In[3:0] input to all used BITSLICEs.
-- C_BtslceUsedAsT: defines what BITSLICEs are used in T mode when
-- C_Tx_BtslceTr is set as "TBYTE_IN".
-- Example:
-- C_Tx_BtslceTr = "TBYTE_IN" and C_BtslceUsedAsT = "0000001"
-- when C_UsedBitslices = "1111111". Will result in all BITSLICEs
-- Being connected as TBYTE_IN, except BITSLICE_0.
---------------------------------------------------------------------------------------------
-- BITSLICE_Control
C_Ctrl_Clk : string := "EXTERNAL";
C_Div_Mode : string := "DIV4";
C_En_Clk_To_Ext_North : string := "DISABLE";
C_En_Clk_To_Ext_South : string := "DISABLE";
C_En_Dyn_Odly_Mode : string := "FALSE";
C_En_Other_Nclk : string := "FALSE";
C_En_Other_Pclk : string := "FALSE";
C_Idly_Vt_Track : string := "FALSE";
C_Inv_Rxclk : string := "FALSE";
C_Odly_Vt_Track : string := "FALSE";
C_Qdly_Vt_Track : string := "FALSE";
C_Read_Idle_Count : std_logic_vector(5 downto 0) := "000000";
C_RefClk_Src : string := "PLLCLK";
C_Rounding_Factor : integer := 16;
C_RxGate_Extend : string := "FALSE";
C_Rx_Clk_Phase_n : string := "SHIFT_90";
C_Rx_Clk_Phase_p : string := "SHIFT_90";
C_Rx_Gating : string := "DISABLE";
C_Self_Calibrate : string := "ENABLE";
C_Serial_Mode : string := "TRUE";
C_Tx_Gating : string := "DISABLE";
-- RX and TX common BITSLICE attributes / generics
C_Tx_Data_Width : integer := 8;
-- RX and TX common delay line attributes.
C_Delay_Format : string := "COUNT";
C_Delay_Type : string := "FIXED";
C_Delay_Value : integer := 0;
C_RefClk_Frequency : real := 1250.0;
C_Update_Mode : string := "ASYNC";
C_Is_Clk_Inverted : bit := '0';
C_Is_Rst_Dly_Inverted : bit := '0';
C_Is_Rst_Inverted : bit := '0';
-- TX BITSLICE (For now all TX_BITSLICEs need to have the same arguments of operation)
C_Init : bit := '0';
C_Native_Odelay_Bypass : string := "FALSE";
C_Output_Phase_90 : string := "FALSE";
C_Enable_Pre_Emphasis : string := "FALSE";
---------------------------------------------------------------------------------------
-- ! DO NOT CHANGE THE GENERICS GIVEN BELOW !
---------------------------------------------------------------------------------------
-- DATA_TYPE setting for all BITSLICEs except BITSLICE_0
C_Data_Type : string := "DATA";
-- In and out buses, part of the ribbon cable.
C_BusRxBitCtrlOut : integer := 40;
C_BusRxBitCtrlIn : integer := 40;
C_BusTxBitCtrlOut : integer := 40;
C_BusTxBitCtrlIn : integer := 40;
C_BusTxBitCtrlOutTri : integer := 40;
C_BusTxBitCtrlInTri : integer := 40;
C_CntValue : integer := 9
);
port (
-- Global
Tx_Bsc_Rst : in std_logic;
Tx_Bs_Rst : in std_logic;
Tx_Rst_Dly : in std_logic;
Tx_Bsc_En_Vtc : in std_logic;
Tx_Bs_En_Vtc : in std_logic;
-- Bitslics_control
Tx_Riu_Clk : in std_logic;
Tx_Riu_Addr : in std_logic_vector(5 downto 0);
Tx_Riu_Wr_Data : in std_logic_vector(15 downto 0);
Tx_Riu_Rd_Data : out std_logic_vector(15 downto 0);
Tx_Riu_Valid : out std_logic;
Tx_Riu_Wr_En : in std_logic;
Tx_Riu_Nibble_Sel : in std_logic;
--
Tx_Pll_Clk : in std_logic;
Tx_RefClk : in std_logic;
Tx_Dly_Rdy : out std_logic;
Tx_Vtc_Rdy : out std_logic;
Tx_Dyn_Dci : out std_logic_vector(6 downto 0);
--
Tx_Tbyte_In : in std_logic_vector(3 downto 0);
Tx_Phy_Rden : in std_logic_vector(3 downto 0);
--
Tx_Clk_From_Ext : in std_logic := '1';
Tx_Pclk_Nibble_In : in std_logic;
Tx_Nclk_Nibble_In : in std_logic;
Tx_Nclk_Nibble_Out : out std_logic;
Tx_Pclk_Nibble_Out : out std_logic;
Tx_Clk_To_Ext_North : out std_logic;
Tx_Clk_To_Ext_South : out std_logic;
-- BITSLICEs to and from IO
-- Depending the C_NibbleType these buses will have seven or six bits.
Tx_Tri_Out : out std_logic_vector(C_NibbleType-1 downto 0);
Tx_Data_Out : out std_logic_vector(C_NibbleType-1 downto 0);
-- BITSLICEs to and from the FPGA Fabric
-- The size of FPGA fabric side input and output buses depends from different
-- attributes (C_NibbleType,C_Tx_Data_Width and C_CntValue). These buses can thus
-- Have different widths.
-- Depending the C_UsedBitslices attribute, when a '0' is inserted to not instantiate
-- a BITSLICE, these buses can containC_Tx_Data_Width parts
-- being pulled low or left floating.
-- View the synthesis log files to find whatC_Tx_Data_Width wide part of a bus is
-- pulled low or left floating.
Tx_T_In : in std_logic_vector(C_NibbleType-1 downto 0);
Tx_D_In : in std_logic_vector((C_NibbleType*C_Tx_Data_Width)-1 downto 0);
-- IO-DELAY TX_BITSLICEs
Tx_Ce : in std_logic_vector(C_NibbleType-1 downto 0);
Tx_Clk : in std_logic;
Tx_Inc : in std_logic_vector(C_NibbleType-1 downto 0);
Tx_Load : in std_logic_vector(C_NibbleType-1 downto 0);
Tx_CntValueIn : in std_logic_vector((C_NibbleType*C_CntValue)-1 downto 0);
Tx_CntValueOut : out std_logic_vector((C_NibbleType*C_CntValue)-1 downto 0);
-- TX_BITSLICE_TRI
TxTri_Ce : in std_logic;
TxTri_Clk : in std_logic;
TxTri_Inc : in std_logic;
TxTri_Load : in std_logic;
TxTri_CntValueIn : in std_logic_vector(8 downto 0);
TxTri_CntValueOut : out std_logic_vector(8 downto 0)
);
end component;
begin
--
---------------------------------------------------------------------------------------------
-- RIU arrangements
---------------------------------------------------------------------------------------------
Gen_0 : if C_TxInUpperNibble = 0 and C_UseRxRiu = 1 and C_UseTxRiu = 1 generate
-- attribute LOC of BaseX_Byte_I_Riu_Or_TxLow : label is
-- "RIU_OR_X" & integer'image(Calc_RiuOrX(C_IoBank, C_Part)) & "Y" & integer'image(Calc_Y(C_IoBank, C_BytePosition, 7, 3, C_Part));
begin
--ng BaseX_Riu_Rd_Data <= IntTx_Riu_Rd_Data or IntRx_Riu_Rd_Data;
--ng BaseX_Riu_Valid <= IntRx_Riu_Valid and IntTx_Riu_Valid;
BaseX_Byte_I_Riu_Or_TxLow : RIU_OR
generic map (
SIM_DEVICE => "ULTRASCALE_PLUS_ES1"
)
port map (
RIU_RD_DATA_LOW => IntTx_Riu_Rd_Data, -- in [15:0]
RIU_RD_DATA_UPP => IntRx_Riu_Rd_Data, -- in [15:0]
RIU_RD_VALID_LOW => IntTx_Riu_Valid, -- in
RIU_RD_VALID_UPP => IntRx_Riu_Valid, -- in
RIU_RD_DATA => BaseX_Riu_Rd_Data, -- out [15:0]
RIU_RD_VALID => BaseX_Riu_Valid -- out
);
IntTx_Riu_Wr_En <= BaseX_Riu_Wr_En;
IntRx_Riu_Wr_En <= BaseX_Riu_Wr_En;
IntTx_Riu_Nibble_Sel <= BaseX_Riu_Nibble_Sel(1);
IntRx_Riu_Nibble_Sel <= BaseX_Riu_Nibble_Sel(0);
IntRx_Fifo_Rd_Clk <= BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk &
BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk;
end generate Gen_0;
--
Gen_1 : if C_TxInUpperNibble = 1 and C_UseRxRiu = 1 and C_UseTxRiu = 1 generate
-- attribute LOC of BaseX_Byte_I_Riu_Or_TxHig : label is
-- "RIU_OR_X" & integer'image(Calc_RiuOrX(C_IoBank, C_Part)) & "Y" & integer'image(Calc_Y(C_IoBank, C_BytePosition, 7, 3, C_Part));
begin
--ng BaseX_Riu_Rd_Data <= IntTx_Riu_Rd_Data or IntRx_Riu_Rd_Data;
--ng BaseX_Riu_Valid <= IntRx_Riu_Valid and IntTx_Riu_Valid;
BaseX_Byte_I_Riu_Or_TxHig : RIU_OR
generic map (
SIM_DEVICE => "ULTRASCALE_PLUS_ES1"
)
port map (
RIU_RD_DATA_LOW => IntRx_Riu_Rd_Data, -- in [15:0]
RIU_RD_DATA_UPP => IntTx_Riu_Rd_Data, -- in [15:0]
RIU_RD_VALID_LOW => IntRx_Riu_Valid, -- in
RIU_RD_VALID_UPP => IntTx_Riu_Valid, -- in
RIU_RD_DATA => BaseX_Riu_Rd_Data, -- out [15:0]
RIU_RD_VALID => BaseX_Riu_Valid -- out
);
IntTx_Riu_Wr_En <= BaseX_Riu_Wr_En;
IntRx_Riu_Wr_En <= BaseX_Riu_Wr_En;
IntTx_Riu_Nibble_Sel <= BaseX_Riu_Nibble_Sel(1);
IntRx_Riu_Nibble_Sel <= BaseX_Riu_Nibble_Sel(0);
IntRx_Fifo_Rd_Clk <= BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk &
BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk;
end generate Gen_1;
--
Gen_2 : if C_TxInUpperNibble = 1 and C_UseRxRiu = 1 and C_UseTxRiu = 0 generate
-- attribute LOC of BaseX_Byte_I_Riu_Or_TxHig : label is
-- "RIU_OR_X" & integer'image(Calc_RiuOrX(C_IoBank, C_Part)) & "Y" & integer'image(Calc_Y(C_IoBank, C_BytePosition, 7, 3, C_Part));
begin
--ng BaseX_Riu_Rd_Data <= IntTx_Riu_Rd_Data or IntRx_Riu_Rd_Data;
--ng BaseX_Riu_Valid <= IntRx_Riu_Valid and IntTx_Riu_Valid;
BaseX_Byte_I_Riu_Or_TxHig : RIU_OR
generic map (
SIM_DEVICE => "ULTRASCALE_PLUS_ES1"
)
port map (
RIU_RD_DATA_LOW => IntRx_Riu_Rd_Data, -- in [15:0]
RIU_RD_DATA_UPP => IntTx_Riu_Rd_Data, -- in [15:0]
RIU_RD_VALID_LOW => IntRx_Riu_Valid, -- in
RIU_RD_VALID_UPP => IntTx_Riu_Valid, -- in
RIU_RD_DATA => BaseX_Riu_Rd_Data, -- out [15:0]
RIU_RD_VALID => BaseX_Riu_Valid -- out
);
IntTx_Riu_Wr_En <= BaseX_Riu_Wr_En; --Low;
IntRx_Riu_Wr_En <= BaseX_Riu_Wr_En;
IntTx_Riu_Nibble_Sel <= Low;
IntRx_Riu_Nibble_Sel <= BaseX_Riu_Nibble_Sel(0);
IntRx_Fifo_Rd_Clk <= BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk &
BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk;
end generate Gen_2;
--
Gen_3 : if C_TxInUpperNibble = 1 and C_UseRxRiu = 0 and C_UseTxRiu = 1 generate
-- attribute LOC of BaseX_Byte_I_Riu_Or_TxHig : label is
-- "RIU_OR_X" & integer'image(Calc_RiuOrX(C_IoBank, C_Part)) & "Y" & integer'image(Calc_Y(C_IoBank, C_BytePosition, 7, 3, C_Part));
begin
--ng BaseX_Riu_Rd_Data <= IntTx_Riu_Rd_Data or IntRx_Riu_Rd_Data;
--ng BaseX_Riu_Valid <= IntRx_Riu_Valid and IntTx_Riu_Valid;
BaseX_Byte_I_Riu_Or_TxHig : RIU_OR
generic map (
SIM_DEVICE => "ULTRASCALE_PLUS_ES1"
)
port map (
RIU_RD_DATA_LOW => IntRx_Riu_Rd_Data, -- in [15:0]
RIU_RD_DATA_UPP => IntTx_Riu_Rd_Data, -- in [15:0]
RIU_RD_VALID_LOW => IntRx_Riu_Valid, -- in
RIU_RD_VALID_UPP => IntTx_Riu_Valid, -- in
RIU_RD_DATA => BaseX_Riu_Rd_Data, -- out [15:0]
RIU_RD_VALID => BaseX_Riu_Valid -- out
);
IntTx_Riu_Wr_En <= BaseX_Riu_Wr_En;
IntRx_Riu_Wr_En <= BaseX_Riu_Wr_En; --Low;
IntTx_Riu_Nibble_Sel <= BaseX_Riu_Nibble_Sel(1);
IntRx_Riu_Nibble_Sel <= Low;
IntRx_Fifo_Rd_Clk <= BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk &
BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk;
end generate Gen_3;
--
Gen_4 : if C_TxInUpperNibble = 1 and C_UseRxRiu = 0 and C_UseTxRiu = 0 generate
IntTx_Riu_Wr_En <= Low;
IntRx_Riu_Wr_En <= Low;
IntTx_Riu_Nibble_Sel <= Low;
IntRx_Riu_Nibble_Sel <= Low;
IntRx_Fifo_Rd_Clk <= BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk &
BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk;
end generate Gen_4;
--
Gen_5 : if C_TxInUpperNibble = 0 and C_UseRxRiu = 1 and C_UseTxRiu = 0 generate
-- attribute LOC of BaseX_Byte_I_Riu_Or_TxLow : label is
-- "RIU_OR_X" & integer'image(Calc_RiuOrX(C_IoBank, C_Part)) & "Y" & integer'image(Calc_Y(C_IoBank, C_BytePosition, 7, 3, C_Part));
begin
--ng BaseX_Riu_Rd_Data <= IntTx_Riu_Rd_Data or IntRx_Riu_Rd_Data;
--ng BaseX_Riu_Valid <= IntRx_Riu_Valid and IntTx_Riu_Valid;
BaseX_Byte_I_Riu_Or_TxLow : RIU_OR
generic map (
SIM_DEVICE => "ULTRASCALE_PLUS_ES1"
)
port map (
RIU_RD_DATA_LOW => IntTx_Riu_Rd_Data, -- in [15:0]
RIU_RD_DATA_UPP => IntRx_Riu_Rd_Data, -- in [15:0]
RIU_RD_VALID_LOW => IntTx_Riu_Valid, -- in
RIU_RD_VALID_UPP => IntRx_Riu_Valid, -- in
RIU_RD_DATA => BaseX_Riu_Rd_Data, -- out [15:0]
RIU_RD_VALID => BaseX_Riu_Valid -- out
);
IntTx_Riu_Wr_En <= BaseX_Riu_Wr_En; --Low;
IntRx_Riu_Wr_En <= BaseX_Riu_Wr_En;
IntTx_Riu_Nibble_Sel <= Low;
IntRx_Riu_Nibble_Sel <= BaseX_Riu_Nibble_Sel(0);
IntRx_Fifo_Rd_Clk <= BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk &
BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk;
end generate Gen_5;
--
Gen_6 : if C_TxInUpperNibble = 0 and C_UseRxRiu = 0 and C_UseTxRiu = 1 generate
-- attribute LOC of BaseX_Byte_I_Riu_Or_TxLow : label is
-- "RIU_OR_X" & integer'image(Calc_RiuOrX(C_IoBank, C_Part)) & "Y" & integer'image(Calc_Y(C_IoBank, C_BytePosition, 7, 3, C_Part));
begin
--ng BaseX_Riu_Rd_Data <= IntTx_Riu_Rd_Data or IntRx_Riu_Rd_Data;
--ng BaseX_Riu_Valid <= IntRx_Riu_Valid and IntTx_Riu_Valid;
BaseX_Byte_I_Riu_Or_TxLow : RIU_OR
generic map (
SIM_DEVICE => "ULTRASCALE_PLUS_ES1"
)
port map (
RIU_RD_DATA_LOW => IntTx_Riu_Rd_Data, -- in [15:0]
RIU_RD_DATA_UPP => IntRx_Riu_Rd_Data, -- in [15:0]
RIU_RD_VALID_LOW => IntTx_Riu_Valid, -- in
RIU_RD_VALID_UPP => IntRx_Riu_Valid, -- in
RIU_RD_DATA => BaseX_Riu_Rd_Data, -- out [15:0]
RIU_RD_VALID => BaseX_Riu_Valid -- out
);
IntTx_Riu_Wr_En <= BaseX_Riu_Wr_En;
IntRx_Riu_Wr_En <= BaseX_Riu_Wr_En; --Low;
IntTx_Riu_Nibble_Sel <= BaseX_Riu_Nibble_Sel(1);
IntRx_Riu_Nibble_Sel <= Low;
IntRx_Fifo_Rd_Clk <= BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk &
BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk &
BaseX_Rx_Fifo_Rd_Clk;
end generate Gen_6;
--
Gen_7 : if C_TxInUpperNibble = 0 and C_UseRxRiu = 0 and C_UseTxRiu = 0 generate
IntTx_Riu_Wr_En <= Low;
IntRx_Riu_Wr_En <= Low;
IntTx_Riu_Nibble_Sel <= Low;
IntRx_Riu_Nibble_Sel <= Low;
IntRx_Fifo_Rd_Clk <= BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk &
BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk & BaseX_Rx_Fifo_Rd_Clk;
end generate Gen_7;
---------------------------------------------------------------------------------------------
BaseX_Tx_Dly_Rdy <= IntBaseX_Tx_Dly_Rdy;
BaseX_Rx_Dly_Rdy <= IntBaseX_Rx_Dly_Rdy;
BaseX_Tx_Vtc_Rdy <= IntBaseX_Tx_Vtc_Rdy;
BaseX_Rx_Vtc_Rdy <= IntBaseX_Rx_Vtc_Rdy;
-- TX TBYTE_IN=
BaseX_Byte_I_TxTBytein_PROCESS : process (Tx_RdClk, BaseX_Tx_Bsc_Rst)
begin
if (BaseX_Tx_Bsc_Rst = '1') then
IntActTx_TByteinPip <= (others => '0');
elsif (Tx_RdClk'event and Tx_RdClk = '1') then
IntActTx_TByteinPip(0) <= IntBaseX_Tx_Vtc_Rdy;
IntActTx_TByteinPip(1) <= IntActTx_TByteinPip(0);
end if;
end process;
IntActiveTx_TBytein <= IntActTx_TByteinPip(1) & IntActTx_TByteinPip(1) &
IntActTx_TByteinPip(1) & IntActTx_TByteinPip(1);
---------------------------------------------------------------------------------------------
BaseX_Byte_I_Tx_Nibble : gig_ethernet_pcs_pma_0_Tx_Nibble
generic map (
C_Part => C_Part,
C_IoBank => C_IoBank,
C_NibbleType => WhatTxNibble(C_TxInUpperNibble),
C_BytePosition => C_BytePosition,
C_UsedBitslices => C_Tx_UsedBitslices,
C_Tx_BtslceTr => C_Tx_BtslceTr,
C_BtslceUsedAsT => C_Tx_BtslceUsedAsT,
C_Ctrl_Clk => "EXTERNAL",
C_Div_Mode => "DIV4",
C_En_Clk_To_Ext_North => "DISABLE",
C_En_Clk_To_Ext_South => "DISABLE",
C_En_Dyn_Odly_Mode => "FALSE",
C_En_Other_Nclk => "FALSE",
C_En_Other_Pclk => "FALSE",
C_Idly_Vt_Track => "FALSE",
C_Inv_Rxclk => "FALSE",
C_Odly_Vt_Track => "FALSE",
C_Qdly_Vt_Track => "FALSE",
C_Read_Idle_Count => "000000",
C_RefClk_Src => "PLLCLK",
C_Rounding_Factor => 16,
C_RxGate_Extend => "FALSE",
C_Rx_Clk_Phase_n => "SHIFT_0",
C_Rx_Clk_Phase_p => "SHIFT_0",
C_Rx_Gating => "DISABLE",
C_Self_Calibrate => C_Tx_Self_Calibrate,
C_Serial_Mode => C_Tx_Serial_Mode,
C_Tx_Gating => "ENABLE",
C_Tx_Data_Width => C_Tx_Data_Width,
C_Delay_Format => C_Tx_Delay_Format,
C_Delay_Type => C_Tx_Delay_Type, --<-- TX doesn't use delay lines.
C_Delay_Value => C_Tx_Delay_Value, --<-- TX doesn't use delay lines.
C_RefClk_Frequency => C_Tx_RefClk_Frequency,
C_Update_Mode => "ASYNC",
C_Is_Clk_Inverted => '0',
C_Is_Rst_Dly_Inverted => '0',
C_Is_Rst_Inverted => '0',
C_Init => '0',
C_Native_Odelay_Bypass => "FALSE",
C_Output_Phase_90 => "TRUE",
C_Enable_Pre_Emphasis => "FALSE"
)
port map (
Tx_Bsc_Rst => BaseX_Tx_Bsc_Rst, -- in
Tx_Bs_Rst => BaseX_Tx_Bs_Rst, -- in
Tx_Rst_Dly => BaseX_Tx_Rst_Dly, -- in
Tx_Bsc_En_Vtc => BaseX_Tx_Bsc_En_Vtc,
Tx_Bs_En_Vtc => BaseX_Tx_Bs_En_Vtc, -- in
Tx_Riu_Clk => BaseX_Riu_Clk, -- in
Tx_Riu_Addr => BaseX_Riu_Addr, -- in [5:0]
Tx_Riu_Wr_Data => BaseX_Riu_Wr_Data, -- in [15:0]
Tx_Riu_Rd_Data => IntTx_Riu_Rd_Data, -- out [15:0]
Tx_Riu_Valid => IntTx_Riu_Valid, -- out
Tx_Riu_Wr_En => IntTx_Riu_Wr_En, -- in
Tx_Riu_Nibble_Sel => IntTx_Riu_Nibble_Sel, -- in
Tx_Pll_Clk => BaseX_Tx_Pll_Clk, -- in
Tx_RefClk => Low, -- in
Tx_Dly_Rdy => IntBaseX_Tx_Dly_Rdy, -- out
Tx_Vtc_Rdy => IntBaseX_Tx_Vtc_Rdy, -- out
Tx_Dyn_Dci => open, -- out [6:0]
Tx_Tbyte_In => IntActiveTx_TBytein,
Tx_Phy_Rden => BaseX_Tx_Phy_Rden, -- in [3:0]
Tx_Clk_From_Ext => High, -- in
Tx_Pclk_Nibble_In => High, -- in
Tx_Nclk_Nibble_In => High, -- in
Tx_Nclk_Nibble_Out => open, -- out
Tx_Pclk_Nibble_Out => open, -- out
Tx_Clk_To_Ext_North => open, -- out
Tx_Clk_To_Ext_South => open, -- out
Tx_Tri_Out => BaseX_Tx_Tri_Out, -- out [C_NibbleType-1:0]
Tx_Data_Out => BaseX_Tx_Data_Out, -- out [C_NibbleType-1:0]
Tx_T_In => BaseX_Tx_T_In, -- in [C_NibbleType-1:0]
Tx_D_In => BaseX_Tx_D_In, -- in [(C_NibbleType*C_Tx_Data_Width)-1:0]
Tx_Ce => BaseX_Odly_Ce, -- in [C_NibbleType-1:0]
Tx_Clk => BaseX_Dly_Clk, -- in
Tx_Inc => BaseX_Odly_Inc, -- in [C_NibbleType-1:0]
Tx_Load => BaseX_Odly_Load, -- in [C_NibbleType-1:0]
Tx_CntValueIn => BaseX_Odly_CntValueIn, -- in [(C_NibbleType*C_CntValue)-1:0]
Tx_CntValueOut => BaseX_Odly_CntValueOut, -- out[(C_NibbleType*C_CntValue)-1:0]
TxTri_Ce => BaseX_TriOdly_Ce, -- in
TxTri_Clk => BaseX_Dly_Clk, -- in
TxTri_Inc => BaseX_TriOdly_Inc, -- in
TxTri_Load => BaseX_TriOdly_Load, -- in
TxTri_CntValueIn => BaseX_TriOdly_CntValueIn, -- in [8:0]
TxTri_CntValueOut => BaseX_TriOdly_CntValueOut -- out [8:0]
);
--
BaseX_Byte_I_Rx_Nibble : gig_ethernet_pcs_pma_0_Rx_Nibble
generic map (
C_Part => C_Part,
C_IoBank => C_IoBank,
C_NibbleType => WhatRxNibble(C_TxInUpperNibble),
C_BytePosition => C_BytePosition,
C_UsedBitslices => C_Rx_UsedBitslices,
C_BtslcNulType => C_Rx_BtslcNulType,
C_Ctrl_Clk => "EXTERNAL",
C_Div_Mode => "DIV2",
C_En_Clk_To_Ext_North => "DISABLE",
C_En_Clk_To_Ext_South => "DISABLE",
C_En_Dyn_Odly_Mode => "FALSE",
C_En_Other_Nclk => "FALSE",
C_En_Other_Pclk => "FALSE",
C_Idly_Vt_Track => "TRUE", -- "FALSE", --<-- VT tracking must be turned off
C_Inv_Rxclk => "FALSE",
C_Odly_Vt_Track => "TRUE", --"FALSE", --<-- VT tracking must be turned off
C_Qdly_Vt_Track => "TRUE", --"FALSE", --<-- VT tracking must be turned off
C_Read_Idle_Count => "000000",
C_RefClk_Src => "PLLCLK",
C_Rounding_Factor => 16,
C_RxGate_Extend => "FALSE",
C_Rx_Clk_Phase_n => "SHIFT_90",
C_Rx_Clk_Phase_p => "SHIFT_90",
C_Rx_Gating => "DISABLE",
C_Self_Calibrate => C_Rx_Self_Calibrate,
C_Serial_Mode => C_Rx_Serial_Mode,
C_Tx_Gating => "DISABLE",
C_Rx_Data_Width => C_Rx_Data_Width,
C_Delay_Format => C_Rx_Delay_Format,
C_Delay_Type => C_Rx_Delay_Type,
C_Delay_Value => C_Rx_Delay_Value,
C_RefClk_Frequency => C_Rx_RefClk_Frequency,
C_Update_Mode => "ASYNC",
C_Is_Clk_Inverted => '0',
C_Is_Rst_Dly_Inverted => '0',
C_Is_Rst_Inverted => '0',
C_Cascade => "FALSE",
C_Delay_Value_Ext => 0,
C_Update_Mode_Ext => "ASYNC",
C_Fifo_Sync_Mode => "FALSE",
C_Is_Clk_Ext_Inverted => '0',
C_Is_Rst_Dly_Ext_Inverted => '0'
)
port map (
Rx_Bsc_Rst => BaseX_Rx_Bsc_Rst, -- in
Rx_Bs_Rst => BaseX_Rx_Bs_Rst, -- in
Rx_Rst_Dly => BaseX_Rx_Rst_Dly, -- in
Rx_Bsc_En_Vtc => BaseX_Rx_Bsc_En_Vtc, -- in
Rx_Bs_En_Vtc => BaseX_Rx_Bs_En_Vtc, -- in
Rx_Riu_Clk => BaseX_Riu_Clk, -- in
Rx_Riu_Addr => BaseX_Riu_Addr, -- in [5:0]
Rx_Riu_Wr_Data => BaseX_Riu_Wr_Data, -- in [15:0]
Rx_Riu_Rd_Data => IntRx_Riu_Rd_Data, -- out [15:0]
Rx_Riu_Valid => IntRx_Riu_Valid, -- out
Rx_Riu_Prsnt => BaseX_Riu_Prsnt, -- out
Rx_Riu_Wr_En => IntRx_Riu_Wr_En, -- in
Rx_Riu_Nibble_Sel => IntRx_Riu_Nibble_Sel, -- in
Rx_Pll_Clk => BaseX_Rx_Pll_Clk, -- in
Rx_RefClk => Low, -- in
Rx_Dly_Rdy => IntBaseX_Rx_Dly_Rdy, -- out
Rx_Vtc_Rdy => IntBaseX_Rx_Vtc_Rdy, -- out
Rx_Dyn_Dci => open, -- out [6:0]
Rx_Tbyte_In => LowVec(3 downto 0), -- in [3:0]
Rx_Phy_Rden => BaseX_Rx_Phy_Rden, -- in [3:0]
Rx_Clk_From_Ext => High, -- in '1';
Rx_Pclk_Nibble_In => High, -- in
Rx_Nclk_Nibble_In => High, -- in
Rx_Nclk_Nibble_Out => open, -- out
Rx_Pclk_Nibble_Out => open, -- out
Rx_Clk_To_Ext_North => open, -- out
Rx_Clk_To_Ext_South => open, -- out
Rx_Data_In => BaseX_Rx_Data_In, -- in [C_NibbleType-1:0]
Rx_Q_Out => BaseX_Rx_Q_Out, -- out [C_NibbleType*C_Rx_Data_Width)-1:0]
Rx_Q_CombOut => BaseX_Rx_Q_CombOut, -- out [C_NibbleType-1:0]
Fifo_Rd_Clk => IntRx_Fifo_Rd_Clk, -- in [C_NibbleType-1:0]
Fifo_Wrclk_Out => open, -- out
Fifo_Rd_En => BaseX_Rx_Fifo_Rd_En, -- in [C_NibbleType-1:0]
Fifo_Empty => BaseX_Rx_Fifo_Empty, -- out [C_NibbleType-1:0]
Rx_Ce => BaseX_Idly_Ce, -- in [C_NibbleType-1:0]
Rx_Clk => BaseX_Dly_Clk, -- in
Rx_Inc => BaseX_Idly_Inc, -- in [C_NibbleType-1:0]
Rx_Load => BaseX_Idly_Load, -- in [C_NibbleType-1:0]
Rx_CntValueIn => BaseX_Idly_CntValueIn, -- in [(C_NibbleType*C_CntValue)-1:0]
Rx_CntValueOut => BaseX_Idly_CntValueOut, -- out [(C_NibbleType*C_CntValue)-1:0]
Rx_Ce_Ext => LowVec((7-C_TxInUpperNibble)-1 downto 0), -- in [C_NibbleType-1:0]
Rx_Inc_Ext => LowVec((7-C_TxInUpperNibble)-1 downto 0), -- in [C_NibbleType-1:0]
Rx_Load_Ext => LowVec((7-C_TxInUpperNibble)-1 downto 0), -- in [C_NibbleType-1:0]
Rx_CntValueIn_Ext => LowVec(((7-C_TxInUpperNibble)*9)-1 downto 0), -- in [(C_NibbleType*C_CntValue)-1:0]
Rx_CntValueOut_Ext => open -- out [(C_NibbleType*C_CntValue)-1:0]
);
--
---------------------------------------------------------------------------------------------
end BaseX_Byte_arch;
--
|
<gh_stars>0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity decoder4_16_tb is
end decoder4_16_tb;
architecture Behavioral of decoder4_16_tb is
component decoder4_16_tl
port ( enable : in STD_LOGIC;
sw : in STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC_VECTOR (15 downto 0));
end component;
signal en : STD_LOGIC := '1';
signal switch : STD_LOGIC_VECTOR(3 downto 0) := X"0";
signal led_out : STD_LOGIC_VECTOR(15 downto 0) := X"0000";
signal count_int : UNSIGNED(3 downto 0) := X"0";
begin
decoder: decoder4_16_tl PORT MAP ( enable => en,
sw => switch,
led => led_out);
comb_process: process
begin
wait for 50 ns;
switch <= STD_LOGIC_VECTOR(count_int);
wait for 10 ns;
count_int <= count_int + X"1";
end process;
end Behavioral;
|
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
--*******************************
entity Add_4bit_1 is
port ( A,B : in std_logic_vector(3 downto 0) ;
S : out std_logic_vector(3 downto 0) ;
Cout : out std_logic ) ;
end Add_4bit_1;
--*******************************
architecture A_arith of Add_4bit_1 is
signal Temp : std_logic_vector(4 downto 0) ;
begin
Temp <= ( '0' + A ) + B ;
S <= Temp(3 downto 0);
Cout <= Temp(4);
end A_arith ;
|
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
entity Testbench is
end entity;
architecture Behave of Testbench is
----------------------------------------------------------------
-- edit the following lines to set the number of i/o's of your
-- DUT.
----------------------------------------------------------------
constant number_of_inputs : integer := 16; -- # input bits to your design.
constant number_of_outputs : integer := 16; -- # output bits from your design.
----------------------------------------------------------------
----------------------------------------------------------------
-- Note that you will have to wrap your design into the DUT
-- as indicated in class.
component DUT is
port(input_vector: in std_logic_vector(number_of_inputs-1 downto 0);
output_vector: out std_logic_vector(number_of_outputs-1 downto 0));
end component;
signal input_vector : std_logic_vector(number_of_inputs-1 downto 0);
signal output_vector : std_logic_vector(number_of_outputs-1 downto 0);
-- create a constrained string
function to_string(x: string) return string is
variable ret_val: string(1 to x'length);
alias lx : string (1 to x'length) is x;
begin
ret_val := lx;
return(ret_val);
end to_string;
-- bit-vector to std-logic-vector and vice-versa
function to_std_logic_vector(x: bit_vector) return std_logic_vector is
alias lx: bit_vector(1 to x'length) is x;
variable ret_val: std_logic_vector(1 to x'length);
begin
for I in 1 to x'length loop
if(lx(I) = '1') then
ret_val(I) := '1';
else
ret_val(I) := '0';
end if;
end loop;
return ret_val;
end to_std_logic_vector;
function to_bit_vector(x: std_logic_vector) return bit_vector is
alias lx: std_logic_vector(1 to x'length) is x;
variable ret_val: bit_vector(1 to x'length);
begin
for I in 1 to x'length loop
if(lx(I) = '1') then
ret_val(I) := '1';
else
ret_val(I) := '0';
end if;
end loop;
return ret_val;
end to_bit_vector;
begin
process
variable err_flag : boolean := false;
File INFILE: text open read_mode is "/home/sc/altera_lite/16.0/Projects/exp/TRACEFILE.txt";
FILE OUTFILE: text open write_mode is "/home/sc/altera_lite/16.0/Projects/exp/OUTPUTS.txt";
-- bit-vectors are read from the file.
variable input_vector_var: bit_vector (number_of_inputs-1 downto 0);
variable output_vector_var: bit_vector (number_of_outputs-1 downto 0);
variable output_mask_var: bit_vector (number_of_outputs-1 downto 0);
-- for comparison of output with expected-output
variable output_comp_var: std_logic_vector (number_of_outputs-1 downto 0);
constant ZZZZ : std_logic_vector(number_of_outputs-1 downto 0) := (others => '0');
-- for read/write.
variable INPUT_LINE: Line;
variable OUTPUT_LINE: Line;
variable LINE_COUNT: integer := 0;
begin
while not endfile(INFILE) loop
-- will read a new line every 5ns, apply input,
-- wait for 1 ns for circuit to settle.
-- read output.
LINE_COUNT := LINE_COUNT + 1;
-- read input at current time.
readLine (INFILE, INPUT_LINE);
read (INPUT_LINE, input_vector_var);
read (INPUT_LINE, output_vector_var);
read (INPUT_LINE, output_mask_var);
-- apply input.
input_vector <= to_std_logic_vector(input_vector_var);
-- wait for the circuit to settle
wait for 55 ns;
-- check output.
output_comp_var := (to_std_logic_vector(output_mask_var) and
(output_vector xor to_std_logic_vector(output_vector_var)));
if (output_comp_var /= ZZZZ) then
write(OUTPUT_LINE,to_string("ERROR: line "));
write(OUTPUT_LINE, LINE_COUNT);
writeline(OUTFILE, OUTPUT_LINE);
err_flag := true;
end if;
write(OUTPUT_LINE, to_bit_vector(input_vector));
write(OUTPUT_LINE, to_string(" "));
write(OUTPUT_LINE, to_bit_vector(output_vector));
writeline(OUTFILE, OUTPUT_LINE);
-- advance time by 4 ns.
wait for 105 ns;
end loop;
assert (err_flag) report "SUCCESS, all tests passed." severity note;
assert (not err_flag) report "FAILURE, some tests failed." severity error;
wait;
end process;
dut_instance: DUT
port map(input_vector => input_vector, output_vector => output_vector);
end Behave;
|
<gh_stars>10-100
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;
-- This is the top level module of the Nexys4DDR. The ports on this entity are mapped
-- directly to pins on the FPGA.
entity nexys4ddr_tb is
end nexys4ddr_tb;
architecture sim of nexys4ddr_tb is
signal clk_s : std_logic;
signal led_s : std_logic_vector(15 downto 0);
begin
p_clk : process
begin
clk_s <= '1', '0' after 5 ns;
wait for 10 ns; -- 100 MHz
end process p_clk;
-- Instantiate DUT
i_nexys4ddr : entity work.nexys4ddr
port map (
clk_i => clk_s,
led_o => led_s
);
end architecture sim;
|
-- Copyright 2018 Delft University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
library work;
-- Fletcher
use work.UtilInt_pkg.all;
use work.Arrow_pkg.all;
use work.Array_pkg.all;
use work.Interconnect_pkg.all;
use work.Wrapper_pkg.all;
use work.ArrayConfig_pkg.all;
use work.ArrayConfigParse_pkg.all;
-- Ptoa
use work.Encoding.all;
use work.Thrift.all;
use work.Ingestion.all;
use work.Alignment.all;
-- This ParquetReader is currently set up to work for Parquet arrays containing primitives (int32, int64, float, double).
-- Therefore, CFG should be of the form "prim(<width>)" (see Fletcher's ArrayConfig.vhd). In the future, once more
-- CFG's are supported, this file will be expanded with generate statements ensuring the correct functionality (or version) of the
-- ValuesDecoder, rep level decoder, def level encoder are selected.
entity ParquetReader is
generic(
BUS_ADDR_WIDTH : natural;
BUS_DATA_WIDTH : natural;
BUS_LEN_WIDTH : natural;
BUS_BURST_STEP_LEN : natural;
BUS_BURST_MAX_LEN : natural;
---------------------------------------------------------------------------
INDEX_WIDTH : natural;
---------------------------------------------------------------------------
TAG_WIDTH : natural;
CFG : string;
ENCODING : string;
COMPRESSION_CODEC : string
);
port(
clk : in std_logic;
reset : in std_logic;
---------------------------------------------------------------------------
bus_rreq_valid : out std_logic;
bus_rreq_ready : in std_logic;
bus_rreq_addr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
bus_rreq_len : out std_logic_vector(BUS_LEN_WIDTH-1 downto 0);
---------------------------------------------------------------------------
bus_rdat_valid : in std_logic;
bus_rdat_ready : out std_logic;
bus_rdat_data : in std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
bus_rdat_last : in std_logic;
---------------------------------------------------------------------------
bus_wreq_valid : out std_logic;
bus_wreq_len : out std_logic_vector(BUS_LEN_WIDTH-1 downto 0);
bus_wreq_addr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
bus_wreq_ready : in std_logic;
---------------------------------------------------------------------------
bus_wdat_valid : out std_logic;
bus_wdat_ready : in std_logic;
bus_wdat_data : out std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
bus_wdat_strobe : out std_logic_vector(BUS_DATA_WIDTH/8-1 downto 0);
bus_wdat_last : out std_logic;
---------------------------------------------------------------------------
-- Pointer to the first page in a contiguous list of Parquet pages in memory
base_pages_ptr : in std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
-- Total size in bytes of the contiuous list of Parquet pages
max_data_size : in std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
-- How many values to read from the pages before stopping
total_num_values : in std_logic_vector(31 downto 0);
-- Pointer to Arrow values buffer
values_buffer_addr : in std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
-- Pointer to Arrow offsets buffer
offsets_buffer_addr : in std_logic_vector(BUS_ADDR_WIDTH-1 downto 0) := (others => '0');
---------------------------------------------------------------------------
start : in std_logic;
stop : in std_logic;
---------------------------------------------------------------------------
done : out std_logic
);
end ParquetReader;
architecture Implementation of ParquetReader is
constant PRIM_WIDTH : natural := strtoi(parse_arg(CFG, 0));
-- Metadata signals
signal mdi_rl_byte_length : std_logic_vector(31 downto 0);
signal mdi_dl_byte_length : std_logic_vector(31 downto 0);
signal mdi_dc_uncomp_size : std_logic_vector(31 downto 0);
signal mdi_dc_comp_size : std_logic_vector(31 downto 0);
signal mdi_dd_num_values : std_logic_vector(31 downto 0);
----------------------------------------------------------------------------
-- Streams
----------------------------------------------------------------------------
----------------------------------
-- Ingester <-> DataAligner
----------------------------------
-- Ingester to DataAligner data
signal ing_da_valid : std_logic;
signal ing_da_ready : std_logic;
signal ing_da_data : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
-- Ingester to DataAligner alignment
signal prod_align_valid : std_logic;
signal prod_align_ready : std_logic;
signal prod_align_data : std_logic_vector(log2ceil(BUS_DATA_WIDTH/8)-1 downto 0);
----------------------------------
-- DataAligner <-> consumers
----------------------------------
constant NUM_CONSUMERS : natural := 2;
-- DataAligner to consumers data
signal da_cons_valid : std_logic_vector(NUM_CONSUMERS-1 downto 0);
signal da_cons_ready : std_logic_vector(NUM_CONSUMERS-1 downto 0);
signal da_cons_data : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
-- Consumers to DataAligner bytes_consumed/alignment
signal bytes_cons_valid : std_logic_vector(NUM_CONSUMERS-1 downto 0);
signal bytes_cons_ready : std_logic_vector(NUM_CONSUMERS-1 downto 0);
signal bytes_cons_data : std_logic_vector(NUM_CONSUMERS*(log2ceil(BUS_DATA_WIDTH/8)+1)-1 downto 0);
----------------------------------
-- ValuesDecoder <-> ArrayWriter
----------------------------------
-- Command stream
signal cmd_valid : std_logic;
signal cmd_ready : std_logic;
signal cmd_firstIdx : std_logic_vector(INDEX_WIDTH-1 downto 0);
signal cmd_lastIdx : std_logic_vector(INDEX_WIDTH-1 downto 0);
signal cmd_ctrl : std_logic_vector(arcfg_ctrlWidth(CFG, BUS_ADDR_WIDTH)-1 downto 0);
signal cmd_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
-- Unlock stream
signal unl_valid : std_logic;
signal unl_ready : std_logic;
signal unl_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
-- Data stream
signal vd_cw_valid : std_logic_vector(arcfg_userCount(CFG)-1 downto 0);
signal vd_cw_ready : std_logic_vector(arcfg_userCount(CFG)-1 downto 0);
signal vd_cw_last : std_logic_vector(arcfg_userCount(CFG)-1 downto 0);
signal vd_cw_data : std_logic_vector(arcfg_userWidth(CFG, INDEX_WIDTH)-1 downto 0);
signal vd_cw_dvalid : std_logic_vector(arcfg_userCount(CFG)-1 downto 0);
begin
Ingester_inst: Ingester
generic map(
BUS_DATA_WIDTH => BUS_DATA_WIDTH,
BUS_ADDR_WIDTH => BUS_ADDR_WIDTH,
BUS_LEN_WIDTH => BUS_LEN_WIDTH,
BUS_BURST_MAX_LEN => BUS_BURST_MAX_LEN,
BUS_FIFO_DEPTH => 8*BUS_BURST_MAX_LEN
)
port map(
clk => clk,
reset => reset,
bus_rreq_valid => bus_rreq_valid,
bus_rreq_ready => bus_rreq_ready,
bus_rreq_addr => bus_rreq_addr,
bus_rreq_len => bus_rreq_len,
bus_rdat_valid => bus_rdat_valid,
bus_rdat_ready => bus_rdat_ready,
bus_rdat_data => bus_rdat_data,
bus_rdat_last => bus_rdat_last,
out_valid => ing_da_valid,
out_ready => ing_da_ready,
out_data => ing_da_data,
pa_valid => prod_align_valid,
pa_ready => prod_align_ready,
pa_data => prod_align_data,
start => start,
stop => stop,
base_address => base_pages_ptr,
data_size => max_data_size
);
DataAligner_inst: DataAligner
generic map(
BUS_DATA_WIDTH => BUS_DATA_WIDTH,
BUS_ADDR_WIDTH => BUS_ADDR_WIDTH,
NUM_CONSUMERS => NUM_CONSUMERS,
NUM_SHIFT_STAGES => log2ceil(BUS_DATA_WIDTH/8)
)
port map(
clk => clk,
reset => reset,
in_valid => ing_da_valid,
in_ready => ing_da_ready,
in_data => ing_da_data,
out_valid => da_cons_valid,
out_ready => da_cons_ready,
out_data => da_cons_data,
bytes_consumed => bytes_cons_data,
bc_valid => bytes_cons_valid,
bc_ready => bytes_cons_ready,
prod_alignment => prod_align_data,
pa_valid => prod_align_valid,
pa_ready => prod_align_ready,
data_size => max_data_size
);
MetadataInterpreter_inst: V2MetadataInterpreter
generic map(
BUS_DATA_WIDTH => BUS_DATA_WIDTH
)
port map(
clk => clk,
hw_reset => reset,
in_valid => da_cons_valid(0),
in_ready => da_cons_ready(0),
in_data => da_cons_data,
da_valid => bytes_cons_valid(0),
da_ready => bytes_cons_ready(0),
da_bytes_consumed => bytes_cons_data(log2ceil(BUS_DATA_WIDTH/8) downto 0),
rl_byte_length => mdi_rl_byte_length,
dl_byte_length => mdi_dl_byte_length,
dc_uncomp_size => mdi_dc_uncomp_size,
dc_comp_size => mdi_dc_comp_size,
dd_num_values => mdi_dd_num_values
);
ValuesDecoder_inst: ValuesDecoder
generic map(
BUS_DATA_WIDTH => BUS_DATA_WIDTH,
BUS_ADDR_WIDTH => BUS_ADDR_WIDTH,
INDEX_WIDTH => INDEX_WIDTH,
MIN_INPUT_BUFFER_DEPTH => 16,
CMD_TAG_WIDTH => TAG_WIDTH,
CFG => CFG,
ENCODING => ENCODING,
COMPRESSION_CODEC => COMPRESSION_CODEC,
PRIM_WIDTH => PRIM_WIDTH
)
port map(
clk => clk,
reset => reset,
ctrl_start => start,
ctrl_done => done,
in_valid => da_cons_valid(1),
in_ready => da_cons_ready(1),
in_data => da_cons_data,
compressed_size => mdi_dc_comp_size,
uncompressed_size => mdi_dc_uncomp_size,
total_num_values => total_num_values,
page_num_values => mdi_dd_num_values,
values_buffer_addr => values_buffer_addr,
offsets_buffer_addr => offsets_buffer_addr,
bc_data => bytes_cons_data(2*log2ceil(BUS_DATA_WIDTH/8)+1 downto log2ceil(BUS_DATA_WIDTH/8)+1),
bc_ready => bytes_cons_ready(1),
bc_valid => bytes_cons_valid(1),
cmd_valid => cmd_valid,
cmd_ready => cmd_ready,
cmd_firstIdx => cmd_firstIdx,
cmd_lastIdx => cmd_lastIdx,
cmd_ctrl => cmd_ctrl,
cmd_tag => cmd_tag,
unl_valid => unl_valid,
unl_ready => unl_ready,
unl_tag => unl_tag,
out_valid => vd_cw_valid,
out_ready => vd_cw_ready,
out_last => vd_cw_last,
out_dvalid => vd_cw_dvalid,
out_data => vd_cw_data
);
fletcher_cw_inst: ArrayWriter
generic map (
BUS_ADDR_WIDTH => BUS_ADDR_WIDTH,
BUS_LEN_WIDTH => BUS_LEN_WIDTH,
BUS_DATA_WIDTH => BUS_DATA_WIDTH,
BUS_BURST_STEP_LEN => BUS_BURST_STEP_LEN,
BUS_BURST_MAX_LEN => BUS_BURST_MAX_LEN,
INDEX_WIDTH => INDEX_WIDTH,
CFG => CFG,
CMD_TAG_ENABLE => true,
CMD_TAG_WIDTH => TAG_WIDTH
)
port map (
bcd_clk => clk,
bcd_reset => reset,
kcd_clk => clk,
kcd_reset => reset,
cmd_valid => cmd_valid,
cmd_ready => cmd_ready,
cmd_firstIdx => cmd_firstIdx,
cmd_lastIdx => cmd_lastIdx,
cmd_ctrl => cmd_ctrl,
cmd_tag => cmd_tag,
in_valid => vd_cw_valid,
in_ready => vd_cw_ready,
in_last => vd_cw_last,
in_data => vd_cw_data,
in_dvalid => vd_cw_dvalid,
bus_wreq_valid => bus_wreq_valid,
bus_wreq_ready => bus_wreq_ready,
bus_wreq_addr => bus_wreq_addr,
bus_wreq_len => bus_wreq_len,
bus_wdat_valid => bus_wdat_valid,
bus_wdat_ready => bus_wdat_ready,
bus_wdat_data => bus_wdat_data,
bus_wdat_strobe => bus_wdat_strobe,
bus_wdat_last => bus_wdat_last,
unl_valid => unl_valid,
unl_ready => unl_ready,
unl_tag => unl_tag
);
end architecture;
|
-- or_a gate
-- OR - when/else structure
-- author: <NAME>
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- entity declaration
entity or_a is
port(
input_port : in std_logic_vector(3 downto 0);
output_port : out std_logic
);
end or_a;
-- architecture
architecture circuit of or_a is
begin
output_port <= '0' when input_port = "0000" else
'1' when input_port = "0001" else
'1' when input_port = "0010" else
'1' when input_port = "0011" else
'1' when input_port = "0100" else
'1' when input_port = "0101" else
'1' when input_port = "0110" else
'1' when input_port = "0111" else
'1' when input_port = "1000" else
'1' when input_port = "1001" else
'1' when input_port = "1010" else
'1' when input_port = "1011" else
'1' when input_port = "1100" else
'1' when input_port = "1101" else
'1' when input_port = "1110" else
'1' when input_port = "1111" ;
end architecture circuit;
|
<gh_stars>0
-- file Sub_v1_0.vhd
-- Sub_v1_0 module implementation
-- copyright: (C) 2021 MPSI Technologies GmbH
-- author: <NAME>
-- date created: 25 Aug 2021
-- IP header --- ABOVE
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sub_v1_0 is
generic (
signNotUnsign: boolean := false;
wA: natural range 1 to 128 := 8;
wB: natural range 1 to 128 := 8;
wD: natural range 1 to 128 := 9
);
port (
reset: in std_logic;
mclk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(wA - 1 downto 0);
b: in std_logic_vector(wB - 1 downto 0);
d: out std_logic_vector(wD - 1 downto 0)
);
end Sub_v1_0;
architecture Sub_v1_0 of Sub_v1_0 is
begin
process (reset, mclk)
begin
if reset='1' then
d <= (others => '0');
elsif rising_edge(mclk) then
if ce='1' then
if not signNotUnsign then
d <= std_logic_vector(resize(unsigned(a), wD) - resize(unsigned(b), wD));
else
d <= std_logic_vector(resize(signed(a), wD) - resize(signed(b), wD));
end if;
end if;
end if;
end process;
end Sub_v1_0;
|
-- ZX Spectrum for Altera DE1
--
-- Copyright (c) 2009-2011 <NAME>
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- * Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- * Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written agreement from the author.
--
-- * License is granted for non-commercial use only. A fee may not be charged
-- for redistributions as source code or in synthesized/hardware form without
-- specific prior written agreement from the author.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- PS/2 interface (input only)
-- Based loosely on ps2_ctrl.vhd (c) ALSE. http://www.alse-fr.com
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- This is input-only for the time being
entity ps2_intf is
generic (filter_length : positive := 8);
port(
CLK : in std_logic;
nRESET : in std_logic;
-- PS/2 interface (could be bi-dir)
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
-- Byte-wide data interface - only valid for one clock
-- so must be latched externally if required
DATA : out std_logic_vector(7 downto 0);
VALID : out std_logic;
ERROR : out std_logic
);
end ps2_intf;
architecture ps2_intf_arch of ps2_intf is
subtype filter_t is std_logic_vector(filter_length-1 downto 0);
signal clk_filter : filter_t;
signal ps2_clk_in : std_logic;
signal ps2_dat_in : std_logic;
-- Goes high when a clock falling edge is detected
signal clk_edge : std_logic;
signal bit_count : unsigned (3 downto 0);
signal shiftreg : std_logic_vector(8 downto 0);
signal parity : std_logic;
begin
-- Register input signals
process(nRESET,CLK)
begin
if nRESET = '0' then
ps2_clk_in <= '1';
ps2_dat_in <= '1';
clk_filter <= (others => '1');
clk_edge <= '0';
elsif rising_edge(CLK) then
-- Register inputs (and filter clock)
ps2_dat_in <= PS2_DATA;
clk_filter <= PS2_CLK & clk_filter(clk_filter'high downto 1);
clk_edge <= '0';
if clk_filter = filter_t'(others => '1') then
-- Filtered clock is high
ps2_clk_in <= '1';
elsif clk_filter = filter_t'(others => '0') then
-- Filter clock is low, check for edge
if ps2_clk_in = '1' then
clk_edge <= '1';
end if;
ps2_clk_in <= '0';
end if;
end if;
end process;
-- Shift in keyboard data
process(nRESET,CLK)
begin
if nRESET = '0' then
bit_count <= (others => '0');
shiftreg <= (others => '0');
parity <= '0';
DATA <= (others => '0');
VALID <= '0';
ERROR <= '0';
elsif rising_edge(CLK) then
-- Clear flags
VALID <= '0';
ERROR <= '0';
if clk_edge = '1' then
-- We have a new bit from the keyboard for processing
if bit_count = 0 then
-- Idle state, check for start bit (0) only and don't
-- start counting bits until we get it
parity <= '0';
if ps2_dat_in = '0' then
-- This is a start bit
bit_count <= bit_count + 1;
end if;
else
-- Running. 8-bit data comes in LSb first followed by
-- a single stop bit (1)
if bit_count < 10 then
-- Shift in data and parity (9 bits)
bit_count <= bit_count + 1;
shiftreg <= ps2_dat_in & shiftreg(shiftreg'high downto 1);
parity <= parity xor ps2_dat_in; -- Calculate parity
elsif ps2_dat_in = '1' then
-- Valid stop bit received
bit_count <= (others => '0'); -- back to idle
if parity = '1' then
-- Parity correct, submit data to host
DATA <= shiftreg(7 downto 0);
VALID <= '1';
else
-- Error
ERROR <= '1';
end if;
else
-- Invalid stop bit
bit_count <= (others => '0'); -- back to idle
ERROR <= '1';
end if;
end if;
end if;
end if;
end process;
end ps2_intf_arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY cacheTest IS
END cacheTest;
ARCHITECTURE behavior OF cacheTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Cache
PORT(
clk : IN std_logic;
index : IN std_logic_vector(4 downto 0);
dout : OUT std_logic_vector(131 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal index : std_logic_vector(4 downto 0) := (others => '0');
--Outputs
signal dout : std_logic_vector(131 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Cache PORT MAP (
clk => clk,
index => index,
dout => dout
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- #################################################################################################
-- # << NEORV32 - Pulse Width Modulation Controller (PWM) >> #
-- # ********************************************************************************************* #
-- # Simple PWM controller with 8 bit resolution for the duty cycle and programmable base #
-- # frequency. The controller supports up to 60 PWM channels. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, <NAME>. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) <NAME> #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neorv32;
use neorv32.neorv32_package.all;
entity neorv32_pwm is
generic (
NUM_CHANNELS : natural -- number of PWM channels (0..60)
);
port (
-- host access --
clk_i : in std_ulogic; -- global clock line
addr_i : in std_ulogic_vector(31 downto 0); -- address
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic; -- write enable
data_i : in std_ulogic_vector(31 downto 0); -- data in
data_o : out std_ulogic_vector(31 downto 0); -- data out
ack_o : out std_ulogic; -- transfer acknowledge
-- clock generator --
clkgen_en_o : out std_ulogic; -- enable clock generator
clkgen_i : in std_ulogic_vector(07 downto 0);
-- pwm output channels --
pwm_o : out std_ulogic_vector(NUM_CHANNELS-1 downto 0)
);
end neorv32_pwm;
architecture neorv32_pwm_rtl of neorv32_pwm is
-- IO space: module base address --
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
constant lo_abb_c : natural := index_size_f(pwm_size_c); -- low address boundary bit
-- Control register bits --
constant ctrl_enable_c : natural := 0; -- r/w: PWM enable
constant ctrl_prsc0_bit_c : natural := 1; -- r/w: prescaler select bit 0
constant ctrl_prsc1_bit_c : natural := 2; -- r/w: prescaler select bit 1
constant ctrl_prsc2_bit_c : natural := 3; -- r/w: prescaler select bit 2
-- access control --
signal acc_en : std_ulogic; -- module access enable
signal addr : std_ulogic_vector(31 downto 0); -- access address
signal wren : std_ulogic; -- write enable
signal rden : std_ulogic; -- read enable
-- accessible regs --
type pwm_ch_t is array (0 to NUM_CHANNELS-1) of std_ulogic_vector(7 downto 0);
signal pwm_ch : pwm_ch_t; -- duty cycle (r/w)
signal enable : std_ulogic; -- enable unit (r/w)
signal prsc : std_ulogic_vector(2 downto 0); -- clock prescaler (r/w)
type pwm_ch_rd_t is array (0 to 60-1) of std_ulogic_vector(7 downto 0);
signal pwm_ch_rd : pwm_ch_rd_t; -- duty cycle read-back
-- prescaler clock generator --
signal prsc_tick : std_ulogic;
-- pwm core counter --
signal pwm_cnt : std_ulogic_vector(7 downto 0);
begin
-- Sanity Checks --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
assert not (NUM_CHANNELS > 60) report "NEORV32 PROCESSOR CONFIG ERROR! <IO.PWM> invalid number of channels! Has to be 0..60.!" severity error;
-- Access Control -------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = pwm_base_c(hi_abb_c downto lo_abb_c)) else '0';
addr <= pwm_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
rden <= acc_en and rden_i;
wren <= acc_en and wren_i;
-- Write access ---------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
wr_access: process(clk_i)
begin
if rising_edge(clk_i) then
ack_o <= acc_en and (rden_i or wren_i);
-- write access --
if (wren = '1') then
-- control register --
if (addr = pwm_ctrl_addr_c) then
enable <= data_i(ctrl_enable_c);
prsc <= data_i(ctrl_prsc2_bit_c downto ctrl_prsc0_bit_c);
end if;
-- duty cycle registers --
for i in 0 to NUM_CHANNELS-1 loop -- channel loop
if (addr(5 downto 2) = std_ulogic_vector(to_unsigned((i/4)+1, 4))) then -- 4 channels per register; add ctrl reg offset
pwm_ch(i) <= data_i((i mod 4)*8+7 downto (i mod 4)*8+0);
end if;
end loop;
end if;
-- read access --
data_o <= (others => '0');
if (rden = '1') then
case addr(5 downto 2) is
when x"0" => data_o(ctrl_enable_c) <= enable; data_o(ctrl_prsc2_bit_c downto ctrl_prsc0_bit_c) <= prsc;
when x"1" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(3) & pwm_ch_rd(2) & pwm_ch_rd(1) & pwm_ch_rd(0); else NULL; end if;
when x"2" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(7) & pwm_ch_rd(6) & pwm_ch_rd(5) & pwm_ch_rd(4); else NULL; end if;
when x"3" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(11) & pwm_ch_rd(10) & pwm_ch_rd(9) & pwm_ch_rd(8); else NULL; end if;
when x"4" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(15) & pwm_ch_rd(14) & pwm_ch_rd(13) & pwm_ch_rd(12); else NULL; end if;
when x"5" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(19) & pwm_ch_rd(18) & pwm_ch_rd(17) & pwm_ch_rd(16); else NULL; end if;
when x"6" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(23) & pwm_ch_rd(22) & pwm_ch_rd(21) & pwm_ch_rd(20); else NULL; end if;
when x"7" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(27) & pwm_ch_rd(26) & pwm_ch_rd(25) & pwm_ch_rd(24); else NULL; end if;
when x"8" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(31) & pwm_ch_rd(30) & pwm_ch_rd(29) & pwm_ch_rd(28); else NULL; end if;
when x"9" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(35) & pwm_ch_rd(34) & pwm_ch_rd(33) & pwm_ch_rd(32); else NULL; end if;
when x"a" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(39) & pwm_ch_rd(38) & pwm_ch_rd(37) & pwm_ch_rd(36); else NULL; end if;
when x"b" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(43) & pwm_ch_rd(42) & pwm_ch_rd(41) & pwm_ch_rd(40); else NULL; end if;
when x"c" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(47) & pwm_ch_rd(46) & pwm_ch_rd(45) & pwm_ch_rd(44); else NULL; end if;
when x"d" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(51) & pwm_ch_rd(50) & pwm_ch_rd(49) & pwm_ch_rd(48); else NULL; end if;
when x"e" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(55) & pwm_ch_rd(54) & pwm_ch_rd(53) & pwm_ch_rd(52); else NULL; end if;
when x"f" => if (NUM_CHANNELS > 0) then data_o <= pwm_ch_rd(59) & pwm_ch_rd(58) & pwm_ch_rd(57) & pwm_ch_rd(56); else NULL; end if;
when others => NULL;
end case;
end if;
end if;
end process wr_access;
-- duty cycle read-back --
pwm_dc_rd_gen: process(pwm_ch)
begin
pwm_ch_rd <= (others => (others => '0'));
for i in 0 to NUM_CHANNELS-1 loop
pwm_ch_rd(i) <= pwm_ch(i);
end loop;
end process pwm_dc_rd_gen;
-- PWM clock select --
clkgen_en_o <= enable; -- enable clock generator
prsc_tick <= clkgen_i(to_integer(unsigned(prsc)));
-- PWM Core -------------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
pwm_core: process(clk_i)
begin
if rising_edge(clk_i) then
-- pwm base counter --
if (enable = '0') then
pwm_cnt <= (others => '0');
elsif (prsc_tick = '1') then
pwm_cnt <= std_ulogic_vector(unsigned(pwm_cnt) + 1);
end if;
-- channels --
for i in 0 to NUM_CHANNELS-1 loop
--if (pwm_cnt = pwm_ch(i)) or (pwm_ch(i) = x"00") or (enable = '0') then
-- pwm_o(i) <= '0';
--elsif (pwm_cnt = x"00") then
-- pwm_o(i) <= '1';
--end if;
if (unsigned(pwm_cnt) >= unsigned(pwm_ch(i))) or (enable = '0') then
pwm_o(i) <= '0';
else
pwm_o(i) <= '1';
end if;
end loop;
end if;
end process pwm_core;
end neorv32_pwm_rtl;
|
<gh_stars>1-10
--------------------------------------------------------------------------------
-- __ _ _ _ --
-- / _(_) | | | | --
-- __ _ _ _ ___ ___ _ __ | |_ _ ___| | __| | --
-- / _` | | | |/ _ \/ _ \ '_ \| _| |/ _ \ |/ _` | --
-- | (_| | |_| | __/ __/ | | | | | | __/ | (_| | --
-- \__, |\__,_|\___|\___|_| |_|_| |_|\___|_|\__,_| --
-- | | --
-- |_| --
-- --
-- --
-- Peripheral-NTM for MPSoC --
-- Neural Turing Machine for MPSoC --
-- --
--------------------------------------------------------------------------------
-- Copyright (c) 2020-2021 by the author(s)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
--------------------------------------------------------------------------------
-- Author(s):
-- <NAME> <<EMAIL>>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ntm_math_pkg.all;
entity ntm_matrix_cosine_similarity_function is
generic (
DATA_SIZE : integer := 512
);
port (
-- GLOBAL
CLK : in std_logic;
RST : in std_logic;
-- CONTROL
START : in std_logic;
READY : out std_logic;
DATA_A_IN_MATRIX_ENABLE : in std_logic;
DATA_A_IN_VECTOR_ENABLE : in std_logic;
DATA_A_IN_SCALAR_ENABLE : in std_logic;
DATA_B_IN_MATRIX_ENABLE : in std_logic;
DATA_B_IN_VECTOR_ENABLE : in std_logic;
DATA_B_IN_SCALAR_ENABLE : in std_logic;
DATA_OUT_MATRIX_ENABLE : out std_logic;
DATA_OUT_VECTOR_ENABLE : out std_logic;
DATA_OUT_SCALAR_ENABLE : out std_logic;
-- DATA
MODULO_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_I_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_J_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
LENGTH_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
DATA_A_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
DATA_B_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
DATA_OUT : out std_logic_vector(DATA_SIZE-1 downto 0)
);
end entity;
architecture ntm_matrix_cosine_similarity_function_architecture of ntm_matrix_cosine_similarity_function is
-----------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------
type cosine_similarity_ctrl_fsm is (
STARTER_STATE, -- STEP 0
INPUT_MATRIX_STATE, -- STEP 1
INPUT_VECTOR_STATE, -- STEP 2
INPUT_SCALAR_STATE, -- STEP 3
ENDER_STATE -- STEP 4
);
-----------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------
constant ZERO : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(0, DATA_SIZE));
constant ONE : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_unsigned(1, DATA_SIZE));
-----------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------
-- Finite State Machine
signal cosine_similarity_ctrl_fsm_int : cosine_similarity_ctrl_fsm;
-- Internal Signals
signal index_matrix_loop : std_logic_vector(DATA_SIZE-1 downto 0);
signal index_vector_loop : std_logic_vector(DATA_SIZE-1 downto 0);
signal index_scalar_loop : std_logic_vector(DATA_SIZE-1 downto 0);
signal data_a_in_matrix_cosine_similarity_int : std_logic;
signal data_a_in_vector_cosine_similarity_int : std_logic;
signal data_a_in_scalar_cosine_similarity_int : std_logic;
signal data_b_in_matrix_cosine_similarity_int : std_logic;
signal data_b_in_vector_cosine_similarity_int : std_logic;
signal data_b_in_scalar_cosine_similarity_int : std_logic;
-- COSINE SIMILARITY
-- CONTROL
signal start_vector_cosine_similarity : std_logic;
signal ready_vector_cosine_similarity : std_logic;
signal data_a_in_vector_enable_vector_cosine_similarity : std_logic;
signal data_a_in_scalar_enable_vector_cosine_similarity : std_logic;
signal data_b_in_vector_enable_vector_cosine_similarity : std_logic;
signal data_b_in_scalar_enable_vector_cosine_similarity : std_logic;
signal data_out_vector_enable_vector_cosine_similarity : std_logic;
signal data_out_scalar_enable_vector_cosine_similarity : std_logic;
-- DATA
signal modulo_in_vector_cosine_similarity : std_logic_vector(DATA_SIZE-1 downto 0);
signal size_in_vector_cosine_similarity : std_logic_vector(DATA_SIZE-1 downto 0);
signal length_in_vector_cosine_similarity : std_logic_vector(DATA_SIZE-1 downto 0);
signal data_a_in_vector_cosine_similarity : std_logic_vector(DATA_SIZE-1 downto 0);
signal data_b_in_vector_cosine_similarity : std_logic_vector(DATA_SIZE-1 downto 0);
signal data_out_vector_cosine_similarity : std_logic_vector(DATA_SIZE-1 downto 0);
begin
-----------------------------------------------------------------------
-- Body
-----------------------------------------------------------------------
ctrl_fsm : process(CLK, RST)
begin
if (RST = '0') then
-- Data Outputs
DATA_OUT <= ZERO;
-- Control Outputs
READY <= '0';
-- Assignations
index_matrix_loop <= ZERO;
index_vector_loop <= ZERO;
index_scalar_loop <= ZERO;
data_a_in_matrix_cosine_similarity_int <= '0';
data_a_in_vector_cosine_similarity_int <= '0';
data_a_in_scalar_cosine_similarity_int <= '0';
data_b_in_matrix_cosine_similarity_int <= '0';
data_b_in_vector_cosine_similarity_int <= '0';
data_b_in_scalar_cosine_similarity_int <= '0';
elsif (rising_edge(CLK)) then
case cosine_similarity_ctrl_fsm_int is
when STARTER_STATE => -- STEP 0
-- Control Outputs
READY <= '0';
if (START = '1') then
-- Assignations
index_matrix_loop <= ZERO;
index_vector_loop <= ZERO;
index_scalar_loop <= ZERO;
-- FSM Control
cosine_similarity_ctrl_fsm_int <= INPUT_MATRIX_STATE;
end if;
when INPUT_MATRIX_STATE => -- STEP 1
if (DATA_A_IN_MATRIX_ENABLE = '1') then
-- Data Inputs
data_a_in_vector_cosine_similarity <= DATA_A_IN;
-- Control Internal
data_a_in_vector_enable_vector_cosine_similarity <= '1';
data_a_in_matrix_cosine_similarity_int <= '1';
else
-- Control Internal
data_a_in_vector_enable_vector_cosine_similarity <= '0';
end if;
if (DATA_B_IN_MATRIX_ENABLE = '1') then
-- Data Inputs
data_b_in_vector_cosine_similarity <= DATA_B_IN;
-- Control Internal
data_b_in_vector_enable_vector_cosine_similarity <= '1';
data_b_in_matrix_cosine_similarity_int <= '1';
else
-- Control Internal
data_b_in_vector_enable_vector_cosine_similarity <= '0';
end if;
if (data_a_in_matrix_cosine_similarity_int = '1' and data_b_in_matrix_cosine_similarity_int = '1') then
if (index_matrix_loop = ZERO) then
-- Control Internal
start_vector_cosine_similarity <= '1';
end if;
-- Data Inputs
modulo_in_vector_cosine_similarity <= MODULO_IN;
-- FSM Control
cosine_similarity_ctrl_fsm_int <= ENDER_STATE;
end if;
-- Control Outputs
DATA_OUT_MATRIX_ENABLE <= '0';
DATA_OUT_VECTOR_ENABLE <= '0';
DATA_OUT_SCALAR_ENABLE <= '0';
when INPUT_VECTOR_STATE => -- STEP 2
if (DATA_A_IN_VECTOR_ENABLE = '1') then
-- Data Inputs
data_a_in_vector_cosine_similarity <= DATA_A_IN;
-- Control Internal
data_a_in_vector_enable_vector_cosine_similarity <= '1';
data_a_in_vector_cosine_similarity_int <= '1';
else
-- Control Internal
data_a_in_vector_enable_vector_cosine_similarity <= '0';
end if;
if (DATA_B_IN_VECTOR_ENABLE = '1') then
-- Data Inputs
data_b_in_vector_cosine_similarity <= DATA_B_IN;
-- Control Internal
data_b_in_vector_enable_vector_cosine_similarity <= '1';
data_b_in_vector_cosine_similarity_int <= '1';
else
-- Control Internal
data_b_in_vector_enable_vector_cosine_similarity <= '0';
end if;
if (data_a_in_vector_cosine_similarity_int = '1' and data_b_in_vector_cosine_similarity_int = '1') then
if (index_vector_loop = ZERO) then
-- Control Internal
start_vector_cosine_similarity <= '1';
end if;
-- Data Inputs
modulo_in_vector_cosine_similarity <= MODULO_IN;
size_in_vector_cosine_similarity <= SIZE_J_IN;
-- FSM Control
cosine_similarity_ctrl_fsm_int <= ENDER_STATE;
end if;
-- Control Outputs
DATA_OUT_VECTOR_ENABLE <= '0';
DATA_OUT_SCALAR_ENABLE <= '0';
when INPUT_SCALAR_STATE => -- STEP 2
if (DATA_A_IN_SCALAR_ENABLE = '1') then
-- Data Inputs
data_a_in_vector_cosine_similarity <= DATA_A_IN;
-- Control Internal
data_a_in_vector_enable_vector_cosine_similarity <= '1';
data_a_in_scalar_cosine_similarity_int <= '1';
else
-- Control Internal
data_a_in_vector_enable_vector_cosine_similarity <= '0';
end if;
if (DATA_B_IN_SCALAR_ENABLE = '1') then
-- Data Inputs
data_b_in_vector_cosine_similarity <= DATA_B_IN;
-- Control Internal
data_b_in_vector_enable_vector_cosine_similarity <= '1';
data_b_in_scalar_cosine_similarity_int <= '1';
else
-- Control Internal
data_b_in_vector_enable_vector_cosine_similarity <= '0';
end if;
if (data_a_in_scalar_cosine_similarity_int = '1' and data_b_in_scalar_cosine_similarity_int = '1') then
if (index_vector_loop = ZERO) then
-- Control Internal
start_vector_cosine_similarity <= '1';
end if;
-- Data Inputs
modulo_in_vector_cosine_similarity <= MODULO_IN;
length_in_vector_cosine_similarity <= LENGTH_IN;
-- FSM Control
cosine_similarity_ctrl_fsm_int <= ENDER_STATE;
end if;
-- Control Outputs
DATA_OUT_SCALAR_ENABLE <= '0';
when ENDER_STATE => -- STEP 4
if (ready_vector_cosine_similarity = '1') then
if (unsigned(index_matrix_loop) = unsigned(SIZE_I_IN)-unsigned(ONE) and unsigned(index_vector_loop) = unsigned(SIZE_J_IN)-unsigned(ONE) and unsigned(index_scalar_loop) = unsigned(LENGTH_IN)-unsigned(ONE)) then
-- Control Outputs
READY <= '1';
DATA_OUT_VECTOR_ENABLE <= '1';
-- FSM Control
cosine_similarity_ctrl_fsm_int <= STARTER_STATE;
elsif (unsigned(index_matrix_loop) < unsigned(SIZE_I_IN)-unsigned(ONE) and unsigned(index_vector_loop) = unsigned(SIZE_J_IN)-unsigned(ONE) and unsigned(index_scalar_loop) = unsigned(LENGTH_IN)-unsigned(ONE)) then
-- Control Internal
index_matrix_loop <= std_logic_vector(unsigned(index_matrix_loop) + unsigned(ONE));
index_vector_loop <= ZERO;
-- Control Outputs
DATA_OUT_MATRIX_ENABLE <= '1';
DATA_OUT_VECTOR_ENABLE <= '1';
DATA_OUT_SCALAR_ENABLE <= '1';
-- FSM Control
cosine_similarity_ctrl_fsm_int <= INPUT_MATRIX_STATE;
elsif (unsigned(index_matrix_loop) < unsigned(SIZE_I_IN)-unsigned(ONE) and unsigned(index_vector_loop) < unsigned(SIZE_J_IN)-unsigned(ONE) and unsigned(index_scalar_loop) = unsigned(LENGTH_IN)-unsigned(ONE)) then
-- Control Internal
index_vector_loop <= std_logic_vector(unsigned(index_vector_loop) + unsigned(ONE));
index_vector_loop <= ZERO;
-- Control Outputs
DATA_OUT_VECTOR_ENABLE <= '1';
DATA_OUT_SCALAR_ENABLE <= '1';
-- FSM Control
cosine_similarity_ctrl_fsm_int <= INPUT_VECTOR_STATE;
elsif (unsigned(index_matrix_loop) < unsigned(SIZE_I_IN)-unsigned(ONE) and unsigned(index_vector_loop) < unsigned(SIZE_J_IN)-unsigned(ONE) and unsigned(index_scalar_loop) < unsigned(LENGTH_IN)-unsigned(ONE)) then
-- Control Internal
index_scalar_loop <= std_logic_vector(unsigned(index_scalar_loop) + unsigned(ONE));
-- Control Outputs
DATA_OUT_SCALAR_ENABLE <= '1';
-- FSM Control
cosine_similarity_ctrl_fsm_int <= INPUT_SCALAR_STATE;
end if;
-- Data Outputs
DATA_OUT <= data_out_vector_cosine_similarity;
else
-- Control Internal
start_vector_cosine_similarity <= '0';
data_a_in_matrix_cosine_similarity_int <= '0';
data_a_in_vector_cosine_similarity_int <= '0';
data_a_in_scalar_cosine_similarity_int <= '0';
data_b_in_matrix_cosine_similarity_int <= '0';
data_b_in_vector_cosine_similarity_int <= '0';
data_b_in_scalar_cosine_similarity_int <= '0';
data_a_in_vector_enable_vector_cosine_similarity <= '0';
data_a_in_scalar_enable_vector_cosine_similarity <= '0';
data_b_in_vector_enable_vector_cosine_similarity <= '0';
data_b_in_scalar_enable_vector_cosine_similarity <= '0';
end if;
when others =>
-- FSM Control
cosine_similarity_ctrl_fsm_int <= STARTER_STATE;
end case;
end if;
end process;
-- COSINE SIMILARITY
vector_cosine_similarity_function : ntm_vector_cosine_similarity_function
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_vector_cosine_similarity,
READY => ready_vector_cosine_similarity,
DATA_A_IN_VECTOR_ENABLE => data_a_in_vector_enable_vector_cosine_similarity,
DATA_A_IN_SCALAR_ENABLE => data_a_in_scalar_enable_vector_cosine_similarity,
DATA_B_IN_VECTOR_ENABLE => data_b_in_vector_enable_vector_cosine_similarity,
DATA_B_IN_SCALAR_ENABLE => data_b_in_scalar_enable_vector_cosine_similarity,
DATA_OUT_VECTOR_ENABLE => data_out_vector_enable_vector_cosine_similarity,
DATA_OUT_SCALAR_ENABLE => data_out_scalar_enable_vector_cosine_similarity,
-- DATA
MODULO_IN => modulo_in_vector_cosine_similarity,
SIZE_IN => size_in_vector_cosine_similarity,
LENGTH_IN => length_in_vector_cosine_similarity,
DATA_A_IN => data_a_in_vector_cosine_similarity,
DATA_B_IN => data_b_in_vector_cosine_similarity,
DATA_OUT => data_out_vector_cosine_similarity
);
end architecture;
|
-- ipbus_spi
--
-- Wrapper for opencores spi wishbone slave
--
-- http://opencores.org/project/spi
--
-- <NAME>, Jul 2015
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
entity ipbus_spi is
generic(
N_SS: positive := 8
);
port(
clk: in std_logic;
rst: in std_logic;
ipb_in: in ipb_wbus;
ipb_out: out ipb_rbus;
ss: out std_logic_vector(N_SS - 1 downto 0);
mosi: out std_logic;
miso: in std_logic;
sclk: out std_logic
);
end ipbus_spi;
architecture rtl of ipbus_spi is
signal stb, ack, err, onebit, miso_sig: std_logic;
signal ss_i: std_logic_vector(7 downto 0);
component spi_top
port(
wb_clk_i: IN std_logic;
wb_rst_i: IN std_logic;
wb_adr_i : IN std_logic_vector(4 downto 0);
wb_dat_i : IN std_logic_vector(31 downto 0);
wb_dat_o : OUT std_logic_vector(31 downto 0);
wb_sel_i : IN std_logic_vector(3 downto 0);
wb_we_i : IN std_logic;
wb_stb_i : IN std_logic;
wb_cyc_i : IN std_logic;
wb_ack_o : OUT std_logic;
wb_err_o : OUT std_logic;
wb_int_o : OUT std_logic;
ss_pad_o : OUT std_logic_vector(7 downto 0);
sclk_pad_o: OUT std_logic;
mosi_pad_o: OUT std_logic;
miso_pad_i: IN std_logic
);
end component;
begin
miso_sig <= miso;
stb <= ipb_in.ipb_strobe and not (ack or err);
spi: spi_top
port map(
wb_clk_i => clk,
wb_rst_i => rst,
wb_adr_i(4 downto 2) => ipb_in.ipb_addr(2 downto 0),
wb_adr_i(1 downto 0) => std_logic_vector'("00"),
wb_dat_i => ipb_in.ipb_wdata,
wb_dat_o => ipb_out.ipb_rdata,
wb_sel_i => std_logic_vector'("1111"),
wb_we_i => ipb_in.ipb_write,
wb_stb_i => stb,
wb_cyc_i => std_logic'('1'),
wb_ack_o => ack,
wb_err_o => err,
wb_int_o => open,
ss_pad_o => ss_i,
sclk_pad_o => sclk,
mosi_pad_o => mosi,
miso_pad_i => miso_sig
);
ss <= ss_i(N_SS - 1 downto 0);
ipb_out.ipb_ack <= ack;
ipb_out.ipb_err <= err;
end rtl;
|
<filename>Embedded LABs/LAB4/q3-be.vhd<gh_stars>1-10
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY q3 IS PORT (
X1, X2, X3 : IN STD_LOGIC;
F : OUT STD_LOGIC
);
END q3;
ARCHITECTURE behavioral OF q3 IS
SIGNAL A1, A2, A3 : STD_LOGIC;
BEGIN
PROCESS (X1, X2, X3, A1, A2, A3)
BEGIN
A1 <= X1 AND X2 AND NOT X3;
A2 <= X1 XOR X2;
A3 <= A2 AND X3;
F <= A1 OR A3;
END PROCESS;
END behavioral;
|
<reponame>mariaeduardabicalho/Z01
-- Elementos de Sistemas
-- by <NAME>
-- Ram8.vhd
Library ieee;
use ieee.std_logic_1164.all;
entity Ram8 is
port(
clock: in STD_LOGIC;
input: in STD_LOGIC_VECTOR(15 downto 0);
load: in STD_LOGIC;
address: in STD_LOGIC_VECTOR( 2 downto 0);
output: out STD_LOGIC_VECTOR(15 downto 0)
);
end entity;
architecture rtl of Ram8 is
component Mux8Way16 is -- inserindo mux8way16
port(
a: in STD_LOGIC_VECTOR(15 downto 0);
b: in STD_LOGIC_VECTOR(15 downto 0);
c: in STD_LOGIC_VECTOR(15 downto 0);
d: in STD_LOGIC_VECTOR(15 downto 0);
e: in STD_LOGIC_VECTOR(15 downto 0);
f: in STD_LOGIC_VECTOR(15 downto 0);
g: in STD_LOGIC_VECTOR(15 downto 0);
h: in STD_LOGIC_VECTOR(15 downto 0);
sel: in STD_LOGIC_VECTOR(2 downto 0);
q: out STD_LOGIC_VECTOR(15 downto 0));
end component;
component DMux8Way is --inserindo dmux8way
port(
a: in STD_LOGIC;
sel: in STD_LOGIC_VECTOR(2 downto 0);
q0: out STD_LOGIC;
q1: out STD_LOGIC;
q2: out STD_LOGIC;
q3: out STD_LOGIC;
q4: out STD_LOGIC;
q5: out STD_LOGIC;
q6: out STD_LOGIC;
q7: out STD_LOGIC
);
end component;
component Register16 is -- inserindo register16
port(
clock: in STD_LOGIC;
input: in STD_LOGIC_VECTOR(15 downto 0);
load: in STD_LOGIC;
output: out STD_LOGIC_VECTOR(15 downto 0));
end component;
signal x0, x1, x2, x3, x4, x5, x6, x7: STD_LOGIC_VECTOR(15 downto 0); -- variaveis usadas para o output de cada register16
signal r0, r1, r2, r3, r4, r5, r6, r7: std_logic; -- variaveis usadas para passar o load para cada register16
begin
dmux: DMux8Way port map( -- dmux8way define para qual register o load (a) vai de acordo com o address (sel)
a => load,
sel => address,
q0 => r0,
q1 => r1,
q2 => r2,
q3 => r3,
q4 => r4,
q5 => r5,
q6 => r6,
q7 => r7
);
-- atribuindo os outputs e inputs a cada register, sendo que apenas o register que receber o load pelas variaveis r[0-7], vai sofrer alteracao
reg1: Register16 port map(
clock => clock,
input => input,
load => r0,
output => x0
);
reg2: Register16 port map(
clock => clock,
input => input,
load => r1,
output => x1
);
reg3: Register16 port map(
clock => clock,
input => input,
load => r2,
output => x2
);
reg4: Register16 port map(
clock => clock,
input => input,
load => r3,
output => x3
);
reg5: Register16 port map(
clock => clock,
input => input,
load => r4,
output => x4
);
reg6: Register16 port map(
clock => clock,
input => input,
load => r5,
output => x5
);
reg7: Register16 port map(
clock => clock,
input => input,
load => r6,
output => x6
);
reg8: Register16 port map(
clock => clock,
input => input,
load => r7,
output => x7
);
--
mux: Mux8Way16 port map( -- mux recebe a saida de cada register16 e de acordo com o address, libera determina como output alguma dessas variaveis recebidas dos registers
a => x0,
b => x1,
c => x2,
d => x3,
e => x4,
f => x5,
g => x6,
h => x7,
sel => address,
q => output
);
end rtl;
|
---------------------------------------------------------------------------
-- ID/EX Pipeline Register
-- It propagates inputs coming from the decode stage to the ex stage
-- Note the use of the flush control signal: it used to flush the pipeline
-- register in case of control hazards(fluhs when the signal is asseted).
-- The reset is synchronous with respet to the clock, whereas the flush is
-- asynchronous.
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
entity idex_reg is
port (
-- INPUTS
cw_to_ex_dec : in std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word directed to the ex stage (note -2 since unsigned control signal is alredy used in decode thus no need to propagate)
jump_address_dec : in std_logic_vector(31 downto 0); -- jump address extended
pc_4_dec : in std_logic_vector(31 downto 0); -- PC incremented by 4 from decode
read_data_1_dec : in std_logic_vector(31 downto 0); -- reg 1 read from decode
read_data_2_dec : in std_logic_vector(31 downto 0); -- reg 2 read from decode
immediate_ext_dec : in std_logic_vector(31 downto 0); -- immediate sign extended from decode
immediate_dec : in std_logic_vector(15 downto 0); -- immediate for lui instrucion from decode
rt_dec : in std_logic_vector(4 downto 0); -- rt address from decode
rd_dec : in std_logic_vector(4 downto 0); -- rs address from decode
rs_dec : in std_logic_vector(4 downto 0); -- rd address from decode
clk : in std_logic; -- global clock signal
rst : in std_logic; -- global reset signal
-- OUTPUTS
cw_to_ex : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word for ex stage
jump_address : out std_logic_vector(31 downto 0); -- jump address to ex stage
pc_4 : out std_logic_vector(31 downto 0);
read_data_1 : out std_logic_vector(31 downto 0);
read_data_2 : out std_logic_vector(31 downto 0);
immediate_ext : out std_logic_vector(31 downto 0);
immediate : out std_logic_vector(15 downto 0);
rt : out std_logic_vector(4 downto 0);
rd : out std_logic_vector(4 downto 0);
rs : out std_logic_vector(4 downto 0)
);
end idex_reg;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
architecture behavioral of idex_reg is
begin
------------------------
-- Reg Proc
-- Type: Sequiential
-- Purpose: Implement
-- the behavior of the
-- pipeline register
-- Reset is synchronous
------------------------
Reg_proc: process(clk)
begin
if (clk = '1' and clk'event) then
if (rst = '1') then
cw_to_ex <= (others => '0');
jump_address <= (others => '0');
pc_4 <= (others => '0');
read_data_1 <= (others => '0');
read_data_2 <= (others => '0');
immediate_ext <= (others => '0');
immediate <= (others => '0');
rt <= (others => '0');
rd <= (others => '0');
rs <= (others => '0');
else
cw_to_ex <= cw_to_ex_dec;
jump_address <= jump_address_dec;
pc_4 <= pc_4_dec;
read_data_1 <= read_data_1_dec;
read_data_2 <= read_data_2_dec;
immediate_ext <= immediate_ext_dec;
immediate <= immediate_dec;
rt <= rt_dec;
rd <= rd_dec;
rs <= rs_dec;
end if;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- Company: Amirkabir University of Technology
-- Engineer: <NAME>
--
-- Module Name: ALU_1bit - Behavioral
-- Description: 1-bit ALU unit based on Mano architecture
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_1bit is
Port ( AC_i : in STD_LOGIC;
AC_iplus1 : in STD_LOGIC;
AC_iMin1 : in STD_LOGIC;
DR_i : in STD_LOGIC;
Control_Cmd : in STD_LOGIC_VECTOR (6 downto 0);
INPR_i : in STD_LOGIC;
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
ALU_OUT_i : out STD_LOGIC);
end ALU_1bit;
architecture Behavioral of ALU_1bit is
component FullAdder is
Port(
a:in STD_LOGIC;
b:in STD_LOGIC;
Cin:in STD_LOGIC;
Sum:out STD_LOGIC;
Cout:out STD_LOGIC);
end component;
signal Y:STD_LOGIC_VECTOR(6 downto 0);
signal FAResult:STD_LOGIC := '0';
begin
Y(0) <= Control_Cmd(0) AND AC_i;
U0: FullAdder
Port map(
a => AC_i,
b => DR_i,
Cin => Cin,
Sum => FAResult,
Cout => Cout);
Y(1) <= Control_Cmd(1) AND FAResult;
Y(2) <= Control_Cmd(2) AND DR_i;
Y(3) <= Control_Cmd(3) AND INPR_i;
Y(4) <= Control_Cmd(4) AND (not AC_i);
Y(5) <= Control_Cmd(5) AND AC_iPlus1;
Y(6) <= Control_Cmd(6) AND AC_iMin1;
ALU_OUT_i <= Y(0) OR Y(1) OR Y(2) OR Y(3) OR Y(4) OR Y(5) OR Y(6);
end Behavioral;
|
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level ----
---- ----
---- ----
---- Author: <NAME> ----
---- <EMAIL> ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 <NAME> ----
---- <EMAIL> ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_top.vhd,v 1.8 2009-01-20 10:38:45 rherveille Exp $
--
-- $Date: 2009-01-20 10:38:45 $
-- $Revision: 1.8 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- Revision 1.7 2004/03/14 10:17:03 rherveille
-- Fixed simulation issue when writing to CR register
--
-- Revision 1.6 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.5 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.4 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.3 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.2 2001/11/10 10:52:44 rherveille
-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_master_top is
generic(
ARST_LVL : std_logic := '0' -- asynchronous reset level
);
port (
-- wishbone signals
wb_clk_i : in std_logic; -- master clock input
wb_rst_i : in std_logic := '0'; -- synchronous active high reset
arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
wb_adr_i : in std_logic_vector(2 downto 0); -- lower address bits
wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
wb_we_i : in std_logic; -- Write enable input
wb_stb_i : in std_logic; -- Strobe signals / core select signal
wb_cyc_i : in std_logic; -- Valid bus cycle input
wb_ack_o : out std_logic; -- Bus cycle acknowledge output
wb_inta_o : out std_logic; -- interrupt request output signal
-- i2c lines
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_top;
architecture structural of i2c_master_top is
component i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
i2c_busy : out std_logic;
i2c_al : out std_logic;
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_byte_ctrl;
-- registers
signal prer : unsigned(15 downto 0); -- clock prescale register
signal ctr : std_logic_vector(7 downto 0); -- control register
signal txr : std_logic_vector(7 downto 0); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 0); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
-- internal reset signal
signal rst_i : std_logic;
-- wishbone write access
signal wb_wacc : std_logic;
-- internal acknowledge signal
signal iack_o : std_logic;
-- done signal: command completed, clear command register
signal done : std_logic;
-- command register signals
signal sta, sto, rd, wr, ack, iack : std_logic;
signal core_en : std_logic; -- core enable signal
signal ien : std_logic; -- interrupt enable signal
-- status register signals
signal irxack, rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
signal i2c_busy : std_logic; -- i2c bus busy (start signal detected)
signal i2c_al, al : std_logic; -- arbitration lost
begin
-- generate internal reset signal
rst_i <= arst_i xor ARST_LVL;
-- generate acknowledge output signal
gen_ack_o : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
end if;
end process gen_ack_o;
wb_ack_o <= iack_o;
-- generate wishbone write access signal
wb_wacc <= wb_we_i and iack_o;
-- assign wb_dat_o
assign_dato : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
case wb_adr_i is
when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));
when "010" => wb_dat_o <= ctr;
when "011" => wb_dat_o <= rxr; -- write is transmit register TxR
when "100" => wb_dat_o <= sr; -- write is command register CR
-- Debugging registers:
-- These registers are not documented.
-- Functionality could change in future releases
when "101" => wb_dat_o <= txr;
when "110" => wb_dat_o <= cr;
when "111" => wb_dat_o <= (others => '0');
when others => wb_dat_o <= (others => 'X'); -- for simulation only
end case;
end if;
end process assign_dato;
-- generate registers (CR, SR see below)
gen_regs: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
case wb_adr_i is
when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
when "010" => ctr <= wb_dat_i;
when "011" => txr <= wb_dat_i;
when "100" => null; --write to CR, avoid executing the others clause
-- illegal cases, for simulation only
when others =>
report ("Illegal write address, setting all registers to unknown.");
prer <= (others => 'X');
ctr <= (others => 'X');
txr <= (others => 'X');
end case;
end if;
end if;
end process gen_regs;
-- generate command register
gen_cr: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
cr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
cr <= (others => '0');
elsif (wb_wacc = '1') then
if ( (core_en = '1') and (wb_adr_i = "100") ) then
-- only take new commands when i2c core enabled
-- pending commands are finished
cr <= wb_dat_i;
end if;
else
if (done = '1' or i2c_al = '1') then
cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
end if;
cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0'
cr(0) <= '0'; -- clear IRQ_ACK bit
end if;
end if;
end process gen_cr;
-- decode command register
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
iack <= cr(0);
-- decode control register
core_en <= ctr(7);
ien <= ctr(6);
-- hookup byte controller block
byte_ctrl: i2c_master_byte_ctrl
port map (
clk => wb_clk_i,
rst => wb_rst_i,
nReset => rst_i,
ena => core_en,
clk_cnt => prer,
start => sta,
stop => sto,
read => rd,
write => wr,
ack_in => ack,
i2c_busy => i2c_busy,
i2c_al => i2c_al,
din => txr,
cmd_ack => done,
ack_out => irxack,
dout => rxr,
scl_i => scl_pad_i,
scl_o => scl_pad_o,
scl_oen => scl_padoen_o,
sda_i => sda_pad_i,
sda_o => sda_pad_o,
sda_oen => sda_padoen_o
);
-- status register block + interrupt request signal
st_irq_block : block
begin
-- generate status register bits
gen_sr_bits: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
al <= i2c_al or (al and not sta);
rxack <= irxack;
tip <= (rd or wr);
-- interrupt request flag is always generated
irq_flag <= (done or i2c_al or irq_flag) and not iack;
end if;
end if;
end process gen_sr_bits;
-- generate interrupt request signals
gen_irq: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
wb_inta_o <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
wb_inta_o <= '0';
else
-- interrupt signal is only generated when IEN (interrupt enable bit) is set
wb_inta_o <= irq_flag and ien;
end if;
end if;
end process gen_irq;
-- assign status register bits
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5) <= al;
sr(4 downto 2) <= (others => '0'); -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end block;
end architecture structural;
|
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bus_pkg.all;
use work.adc_ltc2351_pkg.all;
-------------------------------------------------------------------------------
package signalprocessing_pkg is
constant CALC_WIDTH : natural := 18; -- Width of all calculations.
constant INPUT_WIDTH : natural := 14; -- Width of ADC values
-- All calculations are based on that type:
subtype goertzel_data_type is signed(CALC_WIDTH-1 downto 0);
-- The result of the Goertzel Algorithm are always a pair of two values
type goertzel_result_type is array (1 downto 0) of goertzel_data_type;
-- The result for more channels and frequencies:
type goertzel_results_type is array (natural range <>, natural range <>) of goertzel_result_type;
-- One input to the algorithm.
subtype goertzel_input_type is signed(INPUT_WIDTH-1 downto 0);
-- The input for many different channels
type goertzel_inputs_type is array (natural range <>) of goertzel_input_type;
-- One goertzel coefficient corresponds to a certain frequency.
subtype goertzel_coef_type is signed(CALC_WIDTH-1 downto 0);
-- The input for different frequencies
type goertzel_coefs_type is array (natural range <>) of goertzel_coef_type;
component goertzel
generic (
Q : natural;
SAMPLES : natural
);
port (
clk : in std_logic;
coef_p : in unsigned(17 downto 0);
start_p : in std_logic;
adc_value_p : in signed(13 downto 0);
result_p : out goertzel_result_type;
done_p : out std_logic
);
end component;
component goertzel_pipelined
generic (
Q : natural;
CHANNELS : natural;
FREQUENCIES : natural;
SAMPLES : natural);
port (
coefs_p : in goertzel_coefs_type;
inputs_p : in goertzel_inputs_type;
start_p : in std_logic;
results_p : out goertzel_results_type;
done_p : out std_logic;
clk : in std_logic);
end component;
----------------------------------------------------------------------------
-- New version, consists of pipeline, muxes and control_unit
----------------------------------------------------------------------------
component goertzel_pipeline is
generic (
Q : natural);
port (
coef_p : in goertzel_coef_type;
input_p : in goertzel_input_type;
delay_p : in goertzel_result_type;
result_p : out goertzel_result_type;
clk : in std_logic);
end component goertzel_pipeline;
component goertzel_muxes is
generic (
CHANNELS : positive;
FREQUENCIES : positive);
port (
mux_delay1_p : in std_logic;
mux_delay2_p : in std_logic;
mux_coef : in natural range FREQUENCIES-1 downto 0;
mux_input : in natural range CHANNELS-1 downto 0;
bram_data : in goertzel_result_type;
coefs_p : in goertzel_coefs_type;
inputs_p : in goertzel_inputs_type;
delay1_p : out goertzel_data_type;
delay2_p : out goertzel_data_type;
coef_p : out goertzel_coef_type;
input_p : out goertzel_input_type);
end component goertzel_muxes;
component goertzel_control_unit is
generic (
SAMPLES : positive;
FREQUENCIES : positive;
CHANNELS : positive);
port (
start_p : in std_logic;
ready_p : out std_logic := '0';
bram_addr_p : out std_logic_vector(7 downto 0) := (others => '0');
bram_we_p : out std_logic := '0';
mux_delay1_p : out std_logic := '0';
mux_delay2_p : out std_logic := '0';
mux_coef_p : out natural range FREQUENCIES-1 downto 0 := 0;
mux_input_p : out natural range CHANNELS-1 downto 0 := 0;
clk : in std_logic);
end component goertzel_control_unit;
component goertzel_pipelined_v2 is
generic (
FREQUENCIES : positive;
CHANNELS : positive;
SAMPLES : positive;
Q : positive);
port (
start_p : in std_logic;
bram_addr_p : out std_logic_vector(7 downto 0);
bram_data_i : in std_logic_vector(35 downto 0);
bram_data_o : out std_logic_vector(35 downto 0);
bram_we_p : out std_logic;
ready_p : out std_logic;
enable_p : in std_logic;
coefs_p : in goertzel_coefs_type(FREQUENCIES-1 downto 0);
inputs_p : in goertzel_inputs_type(CHANNELS-1 downto 0);
clk : in std_logic);
end component goertzel_pipelined_v2;
----------------------------------------------------------------------------
-- Helpers
----------------------------------------------------------------------------
constant TIMESTAMP_WIDTH : natural := 48; -- 2**48 - 1 * 20 us = 65 days. This counter will not overflow.
subtype timestamp_type is signed(TIMESTAMP_WIDTH-1 downto 0);
component timestamp_generator is
port (
timestamp_o_p : out timestamp_type;
clk : in std_logic);
end component timestamp_generator;
component timestamp_taker is
generic (
BASE_ADDRESS : integer);
port (
timestamp_i_p : in timestamp_type;
trigger_i_p : in std_logic;
bank_x_i_p : in std_logic;
bank_y_i_p : in std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic);
end component;
end signalprocessing_pkg;
|
<filename>firmware/wib_fw_xil_proj_from_dune/wib_zu6cg_cryo/wib_zu6cg.srcs/sources_1/bd/design_1/ip/design_1_axi_bram_ctrl_0_1/design_1_axi_bram_ctrl_0_1_sim_netlist.vhdl
-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
-- Date : Thu Feb 4 22:14:39 2021
-- Host : endcap-tf1.phys.ufl.edu running 64-bit CentOS Linux release 7.8.2003 (Core)
-- Command : write_vhdl -force -mode funcsim -rename_top design_1_axi_bram_ctrl_0_1 -prefix
-- design_1_axi_bram_ctrl_0_1_ design_1_axi_bram_ctrl_0_0_sim_netlist.vhdl
-- Design : design_1_axi_bram_ctrl_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xczu6cg-ffvb1156-1-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_bram_ctrl_0_1_SRL_FIFO is
port (
bid_gets_fifo_load : out STD_LOGIC;
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[1]\ : out STD_LOGIC;
\axi_bid_int_reg[0]\ : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
bid_gets_fifo_load_d1_reg : in STD_LOGIC;
Data_Exists_DFF_0 : in STD_LOGIC;
Arb2AW_Active : in STD_LOGIC;
aw_active_re : in STD_LOGIC;
bid_gets_fifo_load_d1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
Data_Exists_DFF_1 : in STD_LOGIC;
bid_gets_fifo_load_d1_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
axi_wdata_full_reg : in STD_LOGIC;
axi_wr_burst : in STD_LOGIC;
s_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end design_1_axi_bram_ctrl_0_1_SRL_FIFO;
architecture STRUCTURE of design_1_axi_bram_ctrl_0_1_SRL_FIFO is
signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal D : STD_LOGIC;
signal Data_Exists_DFF_i_2_n_0 : STD_LOGIC;
signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC;
signal \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[1]\ : STD_LOGIC;
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal \axi_bid_int[0]_i_2_n_0\ : STD_LOGIC;
signal axi_bvalid_int_i_4_n_0 : STD_LOGIC;
signal bid_fifo_not_empty : STD_LOGIC;
signal bid_fifo_rd : STD_LOGIC;
signal \^bid_gets_fifo_load\ : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_2_n_0 : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CARRY8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CARRY8_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CARRY8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CARRY8_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[0].MUXCY_L_I_CARRY4_CARRY8\ : label is "PRIMITIVE";
attribute OPT_MODIFIED : string;
attribute OPT_MODIFIED of \Addr_Counters[0].MUXCY_L_I_CARRY4_CARRY8\ : label is "MLO";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4_CARRY8\ : label is "(CARRY4)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4_CARRY8\ : label is "LO:O";
attribute BOX_TYPE of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of Data_Exists_DFF : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute BOX_TYPE of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I ";
begin
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[1]\ <= \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[1]\;
bid_gets_fifo_load <= \^bid_gets_fifo_load\;
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_3,
Q => \Addr_Counters[0].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[0].MUXCY_L_I_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
port map (
CI => CI,
CI_TOP => '0',
CO(7 downto 3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CARRY8_CO_UNCONNECTED\(7 downto 3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
DI(7 downto 3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CARRY8_DI_UNCONNECTED\(7 downto 3),
DI(2) => \Addr_Counters[2].FDRE_I_n_0\,
DI(1) => \Addr_Counters[1].FDRE_I_n_0\,
DI(0) => \Addr_Counters[0].FDRE_I_n_0\,
O(7 downto 4) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CARRY8_O_UNCONNECTED\(7 downto 4),
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(7 downto 4) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CARRY8_S_UNCONNECTED\(7 downto 4),
S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[1].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => aw_active_re,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[0].FDRE_I_n_0\,
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAAAAAAAAAA"
)
port map (
I0 => aw_active_re,
I1 => \axi_bid_int[0]_i_2_n_0\,
I2 => \Addr_Counters[0].FDRE_I_n_0\,
I3 => \Addr_Counters[1].FDRE_I_n_0\,
I4 => \Addr_Counters[3].FDRE_I_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => CI
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_2,
Q => \Addr_Counters[1].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => aw_active_re,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[1].FDRE_I_n_0\,
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_1,
Q => \Addr_Counters[2].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => aw_active_re,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_0,
Q => \Addr_Counters[3].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => aw_active_re,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[3].FDRE_I_n_0\,
O => \Addr_Counters[3].XORCY_I_i_1_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D,
Q => bid_fifo_not_empty,
R => SR(0)
);
Data_Exists_DFF_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF20022"
)
port map (
I0 => Arb2AW_Active,
I1 => Data_Exists_DFF_0,
I2 => Data_Exists_DFF_i_2_n_0,
I3 => Data_Exists_DFF_i_3_n_0,
I4 => bid_fifo_not_empty,
O => D
);
Data_Exists_DFF_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AA3F"
)
port map (
I0 => \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[1]\,
I1 => Data_Exists_DFF_1,
I2 => s_axi_bready,
I3 => bid_gets_fifo_load_d1_i_2_n_0,
I4 => bid_gets_fifo_load_d1,
O => Data_Exists_DFF_i_2_n_0
);
Data_Exists_DFF_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => \Addr_Counters[2].FDRE_I_n_0\,
O => Data_Exists_DFF_i_3_n_0
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => s_axi_awid(0),
Q => bid_fifo_rd
);
\axi_bid_int[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ACAFACA0"
)
port map (
I0 => s_axi_awid(0),
I1 => bid_fifo_rd,
I2 => \^bid_gets_fifo_load\,
I3 => \axi_bid_int[0]_i_2_n_0\,
I4 => s_axi_bid(0),
O => \axi_bid_int_reg[0]\
);
\axi_bid_int[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A888888AAA8A8A8"
)
port map (
I0 => bid_fifo_not_empty,
I1 => bid_gets_fifo_load_d1,
I2 => bid_gets_fifo_load_d1_i_2_n_0,
I3 => s_axi_bready,
I4 => Data_Exists_DFF_1,
I5 => \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[1]\,
O => \axi_bid_int[0]_i_2_n_0\
);
axi_bvalid_int_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"000F7F7F7F7F7F7F"
)
port map (
I0 => bid_gets_fifo_load_d1_reg_0(1),
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
I3 => axi_wdata_full_reg,
I4 => Arb2AW_Active,
I5 => axi_bvalid_int_i_4_n_0,
O => \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[1]\
);
axi_bvalid_int_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"08A8"
)
port map (
I0 => bid_gets_fifo_load_d1_reg_0(0),
I1 => s_axi_wlast,
I2 => axi_wdata_full_reg,
I3 => axi_wr_burst,
O => axi_bvalid_int_i_4_n_0
);
bid_gets_fifo_load_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000010100010"
)
port map (
I0 => bid_gets_fifo_load_d1_reg,
I1 => Data_Exists_DFF_0,
I2 => Arb2AW_Active,
I3 => bid_fifo_not_empty,
I4 => bid_gets_fifo_load_d1_i_2_n_0,
I5 => \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[1]\,
O => \^bid_gets_fifo_load\
);
bid_gets_fifo_load_d1_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => Q(2),
I1 => Q(1),
I2 => Q(0),
O => bid_gets_fifo_load_d1_i_2_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_bram_ctrl_0_1_sng_port_arb is
port (
s_axi_awready : out STD_LOGIC;
axi_awready_cmb : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
axi_arready_cmb : out STD_LOGIC;
last_arb_won : out STD_LOGIC;
Arb2AW_Active : out STD_LOGIC;
Arb2AR_Active : out STD_LOGIC;
s_axi_arlen_2_sp_1 : out STD_LOGIC;
ar_active_re : out STD_LOGIC;
s_axi_awaddr_1_sp_1 : out STD_LOGIC;
aw_active_re : out STD_LOGIC;
curr_narrow_burst_en : out STD_LOGIC;
s_axi_araddr_1_sp_1 : out STD_LOGIC;
\s_axi_arlen[2]_0\ : out STD_LOGIC;
\GEN_NO_RD_CMD_OPT.axi_rlast_int_reg\ : out STD_LOGIC;
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[2]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
last_arb_won_reg_0 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
ar_active_reg_0 : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
last_arb_won_reg_1 : in STD_LOGIC;
aw_active_reg_0 : in STD_LOGIC;
ar_active_reg_1 : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
\GEN_NO_RD_CMD_OPT.act_rd_burst_two_reg\ : in STD_LOGIC;
\GEN_NARROW_CNT.narrow_addr_int_reg[1]\ : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_NARROW_EN.curr_narrow_burst_reg\ : in STD_LOGIC;
\GEN_NARROW_EN.curr_narrow_burst_reg_0\ : in STD_LOGIC;
aw_active_d1 : in STD_LOGIC;
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]\ : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
ar_active_d1 : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_awready_int_reg_0 : in STD_LOGIC;
axi_awready_int_reg_1 : in STD_LOGIC;
\FSM_sequential_arb_sm_cs_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
axi_arready_int_reg_0 : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
\bram_we_a[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end design_1_axi_bram_ctrl_0_1_sng_port_arb;
architecture STRUCTURE of design_1_axi_bram_ctrl_0_1_sng_port_arb is
signal \^arb2ar_active\ : STD_LOGIC;
signal \^arb2aw_active\ : STD_LOGIC;
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[2]\ : STD_LOGIC;
signal \FSM_sequential_arb_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \^gen_no_rd_cmd_opt.axi_rlast_int_reg\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^ar_active_re\ : STD_LOGIC;
signal arb_sm_ns : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^aw_active_re\ : STD_LOGIC;
signal \^axi_arready_cmb\ : STD_LOGIC;
signal axi_arready_int_i_4_n_0 : STD_LOGIC;
signal \^axi_awready_cmb\ : STD_LOGIC;
signal \^last_arb_won\ : STD_LOGIC;
signal s_axi_araddr_1_sn_1 : STD_LOGIC;
signal s_axi_arlen_2_sn_1 : STD_LOGIC;
signal s_axi_awaddr_1_sn_1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[2]_i_3\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \FSM_sequential_arb_sm_cs[1]_i_2\ : label is "soft_lutpair0";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_sequential_arb_sm_cs_reg[0]\ : label is "wr_data:01,idle:00,rd_data:10";
attribute FSM_ENCODED_STATES of \FSM_sequential_arb_sm_cs_reg[1]\ : label is "wr_data:01,idle:00,rd_data:10";
attribute SOFT_HLUTNM of axi_arready_int_i_2 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of axi_arready_int_i_3 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of axi_arready_int_i_4 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \bram_we_a[1]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \bram_we_a[2]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \bram_we_a[3]_INST_0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[19]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[19]_i_1__0\ : label is "soft_lutpair2";
begin
Arb2AR_Active <= \^arb2ar_active\;
Arb2AW_Active <= \^arb2aw_active\;
D(0) <= \^d\(0);
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[2]\ <= \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[2]\;
\GEN_NO_RD_CMD_OPT.axi_rlast_int_reg\ <= \^gen_no_rd_cmd_opt.axi_rlast_int_reg\;
Q(1 downto 0) <= \^q\(1 downto 0);
ar_active_re <= \^ar_active_re\;
aw_active_re <= \^aw_active_re\;
axi_arready_cmb <= \^axi_arready_cmb\;
axi_awready_cmb <= \^axi_awready_cmb\;
last_arb_won <= \^last_arb_won\;
s_axi_araddr_1_sp_1 <= s_axi_araddr_1_sn_1;
s_axi_arlen_2_sp_1 <= s_axi_arlen_2_sn_1;
s_axi_awaddr_1_sp_1 <= s_axi_awaddr_1_sn_1;
\ADDR_SNG_PORT.bram_addr_int[2]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^arb2ar_active\,
I1 => s_axi_araddr(2),
O => ar_active_reg_0
);
\FSM_sequential_arb_sm_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAC0FF"
)
port map (
I0 => axi_awready_int_reg_1,
I1 => \^last_arb_won\,
I2 => s_axi_awvalid,
I3 => s_axi_arvalid,
I4 => \^q\(1),
I5 => \^q\(0),
O => arb_sm_ns(0)
);
\FSM_sequential_arb_sm_cs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFFECCFECFCECCCE"
)
port map (
I0 => axi_awready_int_reg_1,
I1 => axi_arready_int_i_4_n_0,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => axi_awready_int_reg_0,
I5 => \FSM_sequential_arb_sm_cs_reg[0]_0\(0),
O => \FSM_sequential_arb_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_arb_sm_cs[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00F03070"
)
port map (
I0 => \^last_arb_won\,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
I3 => \^q\(1),
I4 => \^q\(0),
O => \^d\(0)
);
\FSM_sequential_arb_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FSM_sequential_arb_sm_cs[1]_i_1_n_0\,
D => arb_sm_ns(0),
Q => \^q\(0),
R => SR(0)
);
\FSM_sequential_arb_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FSM_sequential_arb_sm_cs[1]_i_1_n_0\,
D => \^d\(0),
Q => \^q\(1),
R => SR(0)
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDFDDDFDDDFFFFF"
)
port map (
I0 => \^aw_active_re\,
I1 => \GEN_NARROW_CNT.narrow_addr_int_reg[1]\,
I2 => s_axi_awaddr(1),
I3 => s_axi_awaddr(0),
I4 => s_axi_awburst(0),
I5 => s_axi_awburst(1),
O => s_axi_awaddr_1_sn_1
);
\GEN_NARROW_EN.curr_narrow_burst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00E000E000E00000"
)
port map (
I0 => \GEN_NARROW_EN.curr_narrow_burst_reg\,
I1 => \GEN_NARROW_EN.curr_narrow_burst_reg_0\,
I2 => \^arb2aw_active\,
I3 => aw_active_d1,
I4 => s_axi_awburst(0),
I5 => s_axi_awburst(1),
O => curr_narrow_burst_en
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDFDDDFDDDFFFFF"
)
port map (
I0 => \^ar_active_re\,
I1 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]\,
I2 => s_axi_araddr(1),
I3 => s_axi_araddr(0),
I4 => s_axi_arburst(0),
I5 => s_axi_arburst(1),
O => s_axi_araddr_1_sn_1
);
\GEN_NO_RD_CMD_OPT.act_rd_burst_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"00010000FFFFFFFF"
)
port map (
I0 => s_axi_arlen(2),
I1 => s_axi_arlen(3),
I2 => s_axi_arlen(1),
I3 => s_axi_arlen(0),
I4 => \GEN_NO_RD_CMD_OPT.act_rd_burst_two_reg\,
I5 => \^ar_active_re\,
O => s_axi_arlen_2_sn_1
);
\GEN_NO_RD_CMD_OPT.brst_one_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8AAAAAAAAAA"
)
port map (
I0 => \^ar_active_re\,
I1 => s_axi_arlen(2),
I2 => s_axi_arlen(3),
I3 => s_axi_arlen(0),
I4 => s_axi_arlen(1),
I5 => \GEN_NO_RD_CMD_OPT.act_rd_burst_two_reg\,
O => \s_axi_arlen[2]_0\
);
ar_active_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF007000000070"
)
port map (
I0 => \^last_arb_won\,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => axi_awready_int_reg_0,
O => last_arb_won_reg_0
);
ar_active_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => ar_active_reg_1,
Q => \^arb2ar_active\,
R => SR(0)
);
aw_active_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => aw_active_reg_0,
Q => \^arb2aw_active\,
R => SR(0)
);
axi_arready_int_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF020"
)
port map (
I0 => \^gen_no_rd_cmd_opt.axi_rlast_int_reg\,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
I3 => \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[2]\,
I4 => axi_arready_int_i_4_n_0,
O => \^axi_arready_cmb\
);
axi_arready_int_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => axi_arready_int_reg_0,
I1 => s_axi_rready,
I2 => \^q\(1),
I3 => \^q\(0),
O => \^gen_no_rd_cmd_opt.axi_rlast_int_reg\
);
axi_arready_int_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \FSM_sequential_arb_sm_cs_reg[0]_0\(0),
I1 => \^q\(0),
I2 => \^q\(1),
O => \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[2]\
);
axi_arready_int_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"00101010"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => s_axi_arvalid,
I3 => s_axi_awvalid,
I4 => \^last_arb_won\,
O => axi_arready_int_i_4_n_0
);
axi_arready_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \^axi_arready_cmb\,
Q => s_axi_arready,
R => SR(0)
);
axi_awready_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AA000000F300"
)
port map (
I0 => axi_awready_int_reg_0,
I1 => s_axi_arvalid,
I2 => \^last_arb_won\,
I3 => axi_awready_int_reg_1,
I4 => \^q\(0),
I5 => \^q\(1),
O => \^axi_awready_cmb\
);
axi_awready_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \^axi_awready_cmb\,
Q => s_axi_awready,
R => SR(0)
);
\bram_we_a[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^arb2aw_active\,
I1 => \bram_we_a[3]\(0),
O => bram_we_a(0)
);
\bram_we_a[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^arb2aw_active\,
I1 => \bram_we_a[3]\(1),
O => bram_we_a(1)
);
\bram_we_a[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^arb2aw_active\,
I1 => \bram_we_a[3]\(2),
O => bram_we_a(2)
);
\bram_we_a[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^arb2aw_active\,
I1 => \bram_we_a[3]\(3),
O => bram_we_a(3)
);
last_arb_won_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => last_arb_won_reg_1,
Q => \^last_arb_won\,
R => SR(0)
);
\save_init_bram_addr_ld[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^arb2aw_active\,
I1 => aw_active_d1,
O => \^aw_active_re\
);
\save_init_bram_addr_ld[19]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^arb2ar_active\,
I1 => ar_active_d1,
O => \^ar_active_re\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_bram_ctrl_0_1_ua_narrow is
port (
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_NARROW_CNT.narrow_addr_int_reg[0]\ : in STD_LOGIC;
\GEN_NARROW_CNT.narrow_addr_int_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_NARROW_CNT.narrow_addr_int_reg[0]_0\ : in STD_LOGIC;
\GEN_NARROW_CNT.narrow_addr_int_reg[1]_0\ : in STD_LOGIC;
\GEN_NARROW_CNT.narrow_addr_int_reg[1]_1\ : in STD_LOGIC
);
end design_1_axi_bram_ctrl_0_1_ua_narrow;
architecture STRUCTURE of design_1_axi_bram_ctrl_0_1_ua_narrow is
signal \GEN_NARROW_CNT.narrow_addr_int[0]_i_2_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_7_n_0\ : STD_LOGIC;
signal \ua_narrow_load1_carry_i_1__0_n_0\ : STD_LOGIC;
signal ua_narrow_load1_carry_i_2_n_0 : STD_LOGIC;
signal ua_narrow_load1_carry_i_3_n_0 : STD_LOGIC;
signal ua_narrow_load1_carry_i_4_n_0 : STD_LOGIC;
signal ua_narrow_load1_carry_n_6 : STD_LOGIC;
signal ua_narrow_load1_carry_n_7 : STD_LOGIC;
signal NLW_ua_narrow_load1_carry_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
signal NLW_ua_narrow_load1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
\GEN_NARROW_CNT.narrow_addr_int[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7474747774747444"
)
port map (
I0 => Q(0),
I1 => \GEN_NARROW_CNT.narrow_addr_int_reg[0]\,
I2 => \GEN_NARROW_CNT.narrow_addr_int_reg[1]\(0),
I3 => \GEN_NARROW_CNT.narrow_addr_int_reg[0]_0\,
I4 => \GEN_NARROW_CNT.narrow_addr_int_reg[1]_0\,
I5 => \GEN_NARROW_CNT.narrow_addr_int[0]_i_2_n_0\,
O => D(0)
);
\GEN_NARROW_CNT.narrow_addr_int[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA2A0A0AAA2A0AA"
)
port map (
I0 => ua_narrow_load1_carry_n_6,
I1 => s_axi_awaddr(1),
I2 => s_axi_awsize(2),
I3 => s_axi_awsize(1),
I4 => s_axi_awsize(0),
I5 => s_axi_awaddr(0),
O => \GEN_NARROW_CNT.narrow_addr_int[0]_i_2_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8BBB8B8B888"
)
port map (
I0 => \GEN_NARROW_CNT.narrow_addr_int_reg[1]_1\,
I1 => \GEN_NARROW_CNT.narrow_addr_int_reg[0]\,
I2 => \GEN_NARROW_CNT.narrow_addr_int_reg[1]\(1),
I3 => \GEN_NARROW_CNT.narrow_addr_int_reg[0]_0\,
I4 => \GEN_NARROW_CNT.narrow_addr_int_reg[1]_0\,
I5 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_7_n_0\,
O => D(1)
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA80AA82"
)
port map (
I0 => ua_narrow_load1_carry_n_6,
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(1),
I3 => s_axi_awsize(2),
I4 => s_axi_awaddr(1),
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_7_n_0\
);
ua_narrow_load1_carry: unisim.vcomponents.CARRY8
port map (
CI => '1',
CI_TOP => '0',
CO(7 downto 2) => NLW_ua_narrow_load1_carry_CO_UNCONNECTED(7 downto 2),
CO(1) => ua_narrow_load1_carry_n_6,
CO(0) => ua_narrow_load1_carry_n_7,
DI(7 downto 2) => B"000000",
DI(1) => \ua_narrow_load1_carry_i_1__0_n_0\,
DI(0) => ua_narrow_load1_carry_i_2_n_0,
O(7 downto 0) => NLW_ua_narrow_load1_carry_O_UNCONNECTED(7 downto 0),
S(7 downto 2) => B"000000",
S(1) => ua_narrow_load1_carry_i_3_n_0,
S(0) => ua_narrow_load1_carry_i_4_n_0
);
\ua_narrow_load1_carry_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00010003"
)
port map (
I0 => s_axi_awaddr(0),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(1),
I3 => s_axi_awsize(2),
I4 => s_axi_awaddr(1),
O => \ua_narrow_load1_carry_i_1__0_n_0\
);
ua_narrow_load1_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => s_axi_awsize(0),
I1 => s_axi_awsize(1),
I2 => s_axi_awsize(2),
I3 => s_axi_awaddr(1),
O => ua_narrow_load1_carry_i_2_n_0
);
ua_narrow_load1_carry_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFEFFFC"
)
port map (
I0 => s_axi_awaddr(1),
I1 => s_axi_awsize(2),
I2 => s_axi_awsize(1),
I3 => s_axi_awsize(0),
I4 => s_axi_awaddr(0),
O => ua_narrow_load1_carry_i_3_n_0
);
ua_narrow_load1_carry_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"003E0030"
)
port map (
I0 => s_axi_awaddr(0),
I1 => s_axi_awsize(0),
I2 => s_axi_awsize(1),
I3 => s_axi_awsize(2),
I4 => s_axi_awaddr(1),
O => ua_narrow_load1_carry_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_bram_ctrl_0_1_ua_narrow_0 is
port (
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[0]\ : in STD_LOGIC;
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[0]_0\ : in STD_LOGIC;
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]_0\ : in STD_LOGIC;
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]_1\ : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of design_1_axi_bram_ctrl_0_1_ua_narrow_0 : entity is "ua_narrow";
end design_1_axi_bram_ctrl_0_1_ua_narrow_0;
architecture STRUCTURE of design_1_axi_bram_ctrl_0_1_ua_narrow_0 is
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[0]_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_8_n_0\ : STD_LOGIC;
signal ua_narrow_load1_carry_i_1_n_0 : STD_LOGIC;
signal \ua_narrow_load1_carry_i_2__0_n_0\ : STD_LOGIC;
signal \ua_narrow_load1_carry_i_3__0_n_0\ : STD_LOGIC;
signal \ua_narrow_load1_carry_i_4__0_n_0\ : STD_LOGIC;
signal ua_narrow_load1_carry_n_6 : STD_LOGIC;
signal ua_narrow_load1_carry_n_7 : STD_LOGIC;
signal NLW_ua_narrow_load1_carry_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
signal NLW_ua_narrow_load1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7474747774747444"
)
port map (
I0 => Q(0),
I1 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[0]\,
I2 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]\(0),
I3 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[0]_0\,
I4 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]_0\,
I5 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[0]_i_2_n_0\,
O => D(0)
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCCCCCCC000C44"
)
port map (
I0 => s_axi_araddr(0),
I1 => ua_narrow_load1_carry_n_6,
I2 => s_axi_araddr(1),
I3 => s_axi_arsize(0),
I4 => s_axi_arsize(1),
I5 => s_axi_arsize(2),
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[0]_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8BBB8B8B888"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]_1\,
I1 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[0]\,
I2 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]\(1),
I3 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[0]_0\,
I4 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]_0\,
I5 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_8_n_0\,
O => D(1)
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAA002"
)
port map (
I0 => ua_narrow_load1_carry_n_6,
I1 => s_axi_araddr(1),
I2 => s_axi_arsize(0),
I3 => s_axi_arsize(1),
I4 => s_axi_arsize(2),
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_8_n_0\
);
ua_narrow_load1_carry: unisim.vcomponents.CARRY8
port map (
CI => '1',
CI_TOP => '0',
CO(7 downto 2) => NLW_ua_narrow_load1_carry_CO_UNCONNECTED(7 downto 2),
CO(1) => ua_narrow_load1_carry_n_6,
CO(0) => ua_narrow_load1_carry_n_7,
DI(7 downto 2) => B"000000",
DI(1) => ua_narrow_load1_carry_i_1_n_0,
DI(0) => \ua_narrow_load1_carry_i_2__0_n_0\,
O(7 downto 0) => NLW_ua_narrow_load1_carry_O_UNCONNECTED(7 downto 0),
S(7 downto 2) => B"000000",
S(1) => \ua_narrow_load1_carry_i_3__0_n_0\,
S(0) => \ua_narrow_load1_carry_i_4__0_n_0\
);
ua_narrow_load1_carry_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00010003"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(1),
I3 => s_axi_arsize(2),
I4 => s_axi_araddr(1),
O => ua_narrow_load1_carry_i_1_n_0
);
\ua_narrow_load1_carry_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => s_axi_arsize(0),
I1 => s_axi_arsize(1),
I2 => s_axi_arsize(2),
I3 => s_axi_araddr(1),
O => \ua_narrow_load1_carry_i_2__0_n_0\
);
\ua_narrow_load1_carry_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFEFFFC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_arsize(2),
I2 => s_axi_arsize(1),
I3 => s_axi_arsize(0),
I4 => s_axi_araddr(0),
O => \ua_narrow_load1_carry_i_3__0_n_0\
);
\ua_narrow_load1_carry_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000FC8"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_araddr(1),
I2 => s_axi_arsize(0),
I3 => s_axi_arsize(1),
I4 => s_axi_arsize(2),
O => \ua_narrow_load1_carry_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_bram_ctrl_0_1_wrap_brst is
port (
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[1]\ : out STD_LOGIC;
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
aw_active_d1_reg : out STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[3]\ : out STD_LOGIC;
s_axi_awsize_0_sp_1 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\save_init_bram_addr_ld_reg[19]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
ar_active_re : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC;
Arb2AW_Active : in STD_LOGIC;
curr_fixed_burst_reg_reg : in STD_LOGIC;
curr_fixed_burst_reg_reg_0 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
aw_active_re : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
\ADDR_SNG_PORT.bram_addr_int[8]_i_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\ADDR_SNG_PORT.bram_addr_int_reg[5]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[2]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[3]_0\ : in STD_LOGIC;
Arb2AR_Active : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[5]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\ADDR_SNG_PORT.bram_addr_int_reg[4]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[5]_1\ : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 17 downto 0 );
curr_narrow_burst : in STD_LOGIC;
\save_init_bram_addr_ld[19]_i_3_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
narrow_bram_addr_inc_d1 : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
end design_1_axi_bram_ctrl_0_1_wrap_brst;
architecture STRUCTURE of design_1_axi_bram_ctrl_0_1_wrap_brst is
signal \ADDR_SNG_PORT.bram_addr_int[19]_i_8_n_0\ : STD_LOGIC;
signal \ADDR_SNG_PORT.bram_addr_int[2]_i_2_n_0\ : STD_LOGIC;
signal \ADDR_SNG_PORT.bram_addr_int[3]_i_3_n_0\ : STD_LOGIC;
signal \ADDR_SNG_PORT.bram_addr_int[4]_i_3_n_0\ : STD_LOGIC;
signal \ADDR_SNG_PORT.bram_addr_int[5]_i_3_n_0\ : STD_LOGIC;
signal \^addr_sng_port.bram_addr_int_reg[3]\ : STD_LOGIC;
signal \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[1]\ : STD_LOGIC;
signal WrChnl_BRAM_Addr_Ld : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^aw_active_d1_reg\ : STD_LOGIC;
signal data0 : STD_LOGIC_VECTOR ( 17 downto 1 );
signal s_axi_awsize_0_sn_1 : STD_LOGIC;
signal \save_init_bram_addr_ld[19]_i_3_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[19]_i_4_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[19]_i_5_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[19]_i_6_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[19]_0\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_burst_total[0]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_2_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[2]_i_2\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[10]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[11]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[12]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[13]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[14]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[15]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[16]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[17]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[18]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[19]_i_2\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[7]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[8]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[9]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_3\ : label is "soft_lutpair60";
begin
\ADDR_SNG_PORT.bram_addr_int_reg[3]\ <= \^addr_sng_port.bram_addr_int_reg[3]\;
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[1]\ <= \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[1]\;
aw_active_d1_reg <= \^aw_active_d1_reg\;
s_axi_awsize_0_sp_1 <= s_axi_awsize_0_sn_1;
\save_init_bram_addr_ld_reg[19]_0\(13 downto 0) <= \^save_init_bram_addr_ld_reg[19]_0\(13 downto 0);
\ADDR_SNG_PORT.bram_addr_int[10]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \ADDR_SNG_PORT.bram_addr_int[8]_i_2\(1),
I1 => \ADDR_SNG_PORT.bram_addr_int[8]_i_2\(0),
I2 => \ADDR_SNG_PORT.bram_addr_int[8]_i_2\(2),
I3 => \ADDR_SNG_PORT.bram_addr_int[8]_i_2\(3),
O => \^addr_sng_port.bram_addr_int_reg[3]\
);
\ADDR_SNG_PORT.bram_addr_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAEAAAEAFFFFAAEA"
)
port map (
I0 => ar_active_re,
I1 => Q(0),
I2 => s_axi_wvalid,
I3 => \ADDR_SNG_PORT.bram_addr_int[19]_i_8_n_0\,
I4 => Arb2AW_Active,
I5 => curr_fixed_burst_reg_reg,
O => \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[1]\
);
\ADDR_SNG_PORT.bram_addr_int[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"40FF"
)
port map (
I0 => curr_fixed_burst_reg_reg_0,
I1 => Q(1),
I2 => \^aw_active_d1_reg\,
I3 => s_axi_aresetn,
O => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[2]\(0)
);
\ADDR_SNG_PORT.bram_addr_int[19]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0BBBBBB"
)
port map (
I0 => curr_fixed_burst_reg_reg,
I1 => Arb2AW_Active,
I2 => \ADDR_SNG_PORT.bram_addr_int[19]_i_8_n_0\,
I3 => s_axi_wvalid,
I4 => Q(0),
O => \^aw_active_d1_reg\
);
\ADDR_SNG_PORT.bram_addr_int[19]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF54FF"
)
port map (
I0 => \save_init_bram_addr_ld[19]_i_6_n_0\,
I1 => \^addr_sng_port.bram_addr_int_reg[3]\,
I2 => \save_init_bram_addr_ld[19]_i_5_n_0\,
I3 => curr_wrap_burst_reg,
I4 => \save_init_bram_addr_ld[19]_i_4_n_0\,
O => \ADDR_SNG_PORT.bram_addr_int[19]_i_8_n_0\
);
\ADDR_SNG_PORT.bram_addr_int[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDF0010FFDF3313"
)
port map (
I0 => \ADDR_SNG_PORT.bram_addr_int[8]_i_2\(0),
I1 => \ADDR_SNG_PORT.bram_addr_int_reg[5]\,
I2 => \^aw_active_d1_reg\,
I3 => ar_active_re,
I4 => \ADDR_SNG_PORT.bram_addr_int[2]_i_2_n_0\,
I5 => \ADDR_SNG_PORT.bram_addr_int_reg[2]\,
O => D(0)
);
\ADDR_SNG_PORT.bram_addr_int[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I1 => s_axi_awaddr(0),
I2 => Arb2AR_Active,
O => \ADDR_SNG_PORT.bram_addr_int[2]_i_2_n_0\
);
\ADDR_SNG_PORT.bram_addr_int[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFD01FD010101FD"
)
port map (
I0 => \ADDR_SNG_PORT.bram_addr_int_reg[3]_0\,
I1 => \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[1]\,
I2 => \ADDR_SNG_PORT.bram_addr_int_reg[5]\,
I3 => \ADDR_SNG_PORT.bram_addr_int[3]_i_3_n_0\,
I4 => Arb2AR_Active,
I5 => \ADDR_SNG_PORT.bram_addr_int_reg[5]_0\(0),
O => D(1)
);
\ADDR_SNG_PORT.bram_addr_int[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"37F3000037F3FFFF"
)
port map (
I0 => wrap_burst_total(0),
I1 => data0(1),
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
I4 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I5 => s_axi_awaddr(1),
O => \ADDR_SNG_PORT.bram_addr_int[3]_i_3_n_0\
);
\ADDR_SNG_PORT.bram_addr_int[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFE02FE020202FE"
)
port map (
I0 => \ADDR_SNG_PORT.bram_addr_int_reg[4]\,
I1 => \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[1]\,
I2 => \ADDR_SNG_PORT.bram_addr_int_reg[5]\,
I3 => \ADDR_SNG_PORT.bram_addr_int[4]_i_3_n_0\,
I4 => Arb2AR_Active,
I5 => \ADDR_SNG_PORT.bram_addr_int_reg[5]_0\(1),
O => D(2)
);
\ADDR_SNG_PORT.bram_addr_int[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"5D7500005D75FFFF"
)
port map (
I0 => data0(2),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
I4 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I5 => s_axi_awaddr(2),
O => \ADDR_SNG_PORT.bram_addr_int[4]_i_3_n_0\
);
\ADDR_SNG_PORT.bram_addr_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFD01FD010101FD"
)
port map (
I0 => \ADDR_SNG_PORT.bram_addr_int_reg[5]_1\,
I1 => \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[1]\,
I2 => \ADDR_SNG_PORT.bram_addr_int_reg[5]\,
I3 => \ADDR_SNG_PORT.bram_addr_int[5]_i_3_n_0\,
I4 => Arb2AR_Active,
I5 => \ADDR_SNG_PORT.bram_addr_int_reg[5]_0\(2),
O => D(3)
);
\ADDR_SNG_PORT.bram_addr_int[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"557500005575FFFF"
)
port map (
I0 => data0(3),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
I4 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I5 => s_axi_awaddr(3),
O => \ADDR_SNG_PORT.bram_addr_int[5]_i_3_n_0\
);
\save_init_bram_addr_ld[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(8),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => s_axi_awaddr(8),
O => \^save_init_bram_addr_ld_reg[19]_0\(4)
);
\save_init_bram_addr_ld[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(9),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => s_axi_awaddr(9),
O => \^save_init_bram_addr_ld_reg[19]_0\(5)
);
\save_init_bram_addr_ld[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(10),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => s_axi_awaddr(10),
O => \^save_init_bram_addr_ld_reg[19]_0\(6)
);
\save_init_bram_addr_ld[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(11),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => s_axi_awaddr(11),
O => \^save_init_bram_addr_ld_reg[19]_0\(7)
);
\save_init_bram_addr_ld[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(12),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => s_axi_awaddr(12),
O => \^save_init_bram_addr_ld_reg[19]_0\(8)
);
\save_init_bram_addr_ld[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(13),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => s_axi_awaddr(13),
O => \^save_init_bram_addr_ld_reg[19]_0\(9)
);
\save_init_bram_addr_ld[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(14),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => s_axi_awaddr(14),
O => \^save_init_bram_addr_ld_reg[19]_0\(10)
);
\save_init_bram_addr_ld[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(15),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => s_axi_awaddr(15),
O => \^save_init_bram_addr_ld_reg[19]_0\(11)
);
\save_init_bram_addr_ld[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(16),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => s_axi_awaddr(16),
O => \^save_init_bram_addr_ld_reg[19]_0\(12)
);
\save_init_bram_addr_ld[19]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(17),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => s_axi_awaddr(17),
O => \^save_init_bram_addr_ld_reg[19]_0\(13)
);
\save_init_bram_addr_ld[19]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"1010101000000010"
)
port map (
I0 => aw_active_re,
I1 => \save_init_bram_addr_ld[19]_i_4_n_0\,
I2 => curr_wrap_burst_reg,
I3 => \save_init_bram_addr_ld[19]_i_5_n_0\,
I4 => \^addr_sng_port.bram_addr_int_reg[3]\,
I5 => \save_init_bram_addr_ld[19]_i_6_n_0\,
O => \save_init_bram_addr_ld[19]_i_3_n_0\
);
\save_init_bram_addr_ld[19]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAA2A"
)
port map (
I0 => curr_narrow_burst,
I1 => s_axi_wvalid,
I2 => Q(0),
I3 => \save_init_bram_addr_ld[19]_i_3_0\(1),
I4 => \save_init_bram_addr_ld[19]_i_3_0\(0),
I5 => narrow_bram_addr_inc_d1,
O => \save_init_bram_addr_ld[19]_i_4_n_0\
);
\save_init_bram_addr_ld[19]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => wrap_burst_total(1),
I1 => wrap_burst_total(2),
I2 => wrap_burst_total(0),
O => \save_init_bram_addr_ld[19]_i_5_n_0\
);
\save_init_bram_addr_ld[19]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00C000"
)
port map (
I0 => \ADDR_SNG_PORT.bram_addr_int[8]_i_2\(2),
I1 => \ADDR_SNG_PORT.bram_addr_int[8]_i_2\(1),
I2 => wrap_burst_total(1),
I3 => \ADDR_SNG_PORT.bram_addr_int[8]_i_2\(0),
I4 => wrap_burst_total(0),
I5 => wrap_burst_total(2),
O => \save_init_bram_addr_ld[19]_i_6_n_0\
);
\save_init_bram_addr_ld[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E2EE2222E22E2222"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
I4 => data0(1),
I5 => wrap_burst_total(0),
O => WrChnl_BRAM_Addr_Ld(3)
);
\save_init_bram_addr_ld[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE2EE2EE22222222"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
I4 => wrap_burst_total(0),
I5 => data0(2),
O => WrChnl_BRAM_Addr_Ld(4)
);
\save_init_bram_addr_ld[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEE2EE22222222"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
I4 => wrap_burst_total(0),
I5 => data0(3),
O => WrChnl_BRAM_Addr_Ld(5)
);
\save_init_bram_addr_ld[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(4),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => s_axi_awaddr(4),
O => \^save_init_bram_addr_ld_reg[19]_0\(0)
);
\save_init_bram_addr_ld[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(5),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => s_axi_awaddr(5),
O => \^save_init_bram_addr_ld_reg[19]_0\(1)
);
\save_init_bram_addr_ld[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(6),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => s_axi_awaddr(6),
O => \^save_init_bram_addr_ld_reg[19]_0\(2)
);
\save_init_bram_addr_ld[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(7),
I1 => \save_init_bram_addr_ld[19]_i_3_n_0\,
I2 => s_axi_awaddr(7),
O => \^save_init_bram_addr_ld_reg[19]_0\(3)
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \^save_init_bram_addr_ld_reg[19]_0\(4),
Q => data0(8),
R => SR(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \^save_init_bram_addr_ld_reg[19]_0\(5),
Q => data0(9),
R => SR(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \^save_init_bram_addr_ld_reg[19]_0\(6),
Q => data0(10),
R => SR(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \^save_init_bram_addr_ld_reg[19]_0\(7),
Q => data0(11),
R => SR(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \^save_init_bram_addr_ld_reg[19]_0\(8),
Q => data0(12),
R => SR(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \^save_init_bram_addr_ld_reg[19]_0\(9),
Q => data0(13),
R => SR(0)
);
\save_init_bram_addr_ld_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \^save_init_bram_addr_ld_reg[19]_0\(10),
Q => data0(14),
R => SR(0)
);
\save_init_bram_addr_ld_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \^save_init_bram_addr_ld_reg[19]_0\(11),
Q => data0(15),
R => SR(0)
);
\save_init_bram_addr_ld_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \^save_init_bram_addr_ld_reg[19]_0\(12),
Q => data0(16),
R => SR(0)
);
\save_init_bram_addr_ld_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \^save_init_bram_addr_ld_reg[19]_0\(13),
Q => data0(17),
R => SR(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => WrChnl_BRAM_Addr_Ld(3),
Q => data0(1),
R => SR(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => WrChnl_BRAM_Addr_Ld(4),
Q => data0(2),
R => SR(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => WrChnl_BRAM_Addr_Ld(5),
Q => data0(3),
R => SR(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \^save_init_bram_addr_ld_reg[19]_0\(0),
Q => data0(4),
R => SR(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \^save_init_bram_addr_ld_reg[19]_0\(1),
Q => data0(5),
R => SR(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \^save_init_bram_addr_ld_reg[19]_0\(2),
Q => data0(6),
R => SR(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \^save_init_bram_addr_ld_reg[19]_0\(3),
Q => data0(7),
R => SR(0)
);
\wrap_burst_total[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3030013000000303"
)
port map (
I0 => s_axi_awsize(1),
I1 => \wrap_burst_total[0]_i_2_n_0\,
I2 => s_axi_awlen(2),
I3 => s_axi_awsize(0),
I4 => s_axi_awlen(3),
I5 => s_axi_awlen(1),
O => \wrap_burst_total[0]_i_1_n_0\
);
\wrap_burst_total[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFDD5DFFFFFDFF"
)
port map (
I0 => \wrap_burst_total[0]_i_3_n_0\,
I1 => s_axi_awlen(3),
I2 => s_axi_awsize(0),
I3 => s_axi_awsize(1),
I4 => s_axi_awsize(2),
I5 => s_axi_awlen(1),
O => \wrap_burst_total[0]_i_2_n_0\
);
\wrap_burst_total[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_awlen(0),
O => \wrap_burst_total[0]_i_3_n_0\
);
\wrap_burst_total[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000003120010"
)
port map (
I0 => s_axi_awsize(0),
I1 => s_axi_awsize(2),
I2 => s_axi_awsize(1),
I3 => \wrap_burst_total[1]_i_2_n_0\,
I4 => s_axi_awlen(2),
I5 => \wrap_burst_total[1]_i_3_n_0\,
O => \wrap_burst_total[1]_i_1_n_0\
);
\wrap_burst_total[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_awlen(3),
O => \wrap_burst_total[1]_i_2_n_0\
);
\wrap_burst_total[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => s_axi_awlen(1),
I1 => s_axi_awlen(0),
I2 => s_axi_awvalid,
O => \wrap_burst_total[1]_i_3_n_0\
);
\wrap_burst_total[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_awlen(0),
I2 => s_axi_awlen(1),
I3 => s_axi_awlen(2),
I4 => s_axi_awlen(3),
I5 => s_axi_awsize_0_sn_1,
O => \wrap_burst_total[2]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => s_axi_awsize(0),
I1 => s_axi_awsize(1),
I2 => s_axi_awsize(2),
O => s_axi_awsize_0_sn_1
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \wrap_burst_total[0]_i_1_n_0\,
Q => wrap_burst_total(0),
R => SR(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \wrap_burst_total[1]_i_1_n_0\,
Q => wrap_burst_total(1),
R => SR(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => \wrap_burst_total[2]_i_1__0_n_0\,
Q => wrap_burst_total(2),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_bram_ctrl_0_1_wrap_brst_1 is
port (
s_axi_arsize_0_sp_1 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_NO_RD_CMD_OPT.GEN_NARROW_EN.curr_narrow_burst_reg\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_bram_addr_inc_d1_reg\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs_reg[2]\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
curr_narrow_burst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
\ADDR_SNG_PORT.bram_addr_int_reg[6]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[11]\ : in STD_LOGIC;
Arb2AR_Active : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[19]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\ADDR_SNG_PORT.bram_addr_int_reg[7]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[8]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[9]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[10]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[11]_0\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[11]_1\ : in STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[11]_2\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[19]_0\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[19]_1\ : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 16 downto 0 );
narrow_bram_addr_inc_d1 : in STD_LOGIC;
\save_init_bram_addr_ld_reg[19]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[0]\ : in STD_LOGIC;
brst_zero : in STD_LOGIC;
end_brst_rd : in STD_LOGIC;
\save_init_bram_addr_ld[11]_i_3_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
axi_rd_burst : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
curr_wrap_burst_reg : in STD_LOGIC;
\save_init_bram_addr_ld_reg[11]_0\ : in STD_LOGIC;
\save_init_bram_addr_ld[11]_i_4_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ar_active_re : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of design_1_axi_bram_ctrl_0_1_wrap_brst_1 : entity is "wrap_brst";
end design_1_axi_bram_ctrl_0_1_wrap_brst_1;
architecture STRUCTURE of design_1_axi_bram_ctrl_0_1_wrap_brst_1 is
signal \^fsm_sequential_gen_no_rd_cmd_opt.rd_data_sm_cs_reg[2]\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_bram_addr_inc_d1_i_3_n_0\ : STD_LOGIC;
signal \^gen_no_rd_cmd_opt.gen_narrow_cnt.narrow_bram_addr_inc_d1_reg\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\ : STD_LOGIC;
signal RdChnl_BRAM_Addr_Ld : STD_LOGIC_VECTOR ( 19 downto 6 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal data0 : STD_LOGIC_VECTOR ( 17 downto 1 );
signal s_axi_arsize_0_sn_1 : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_10_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_11_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_3_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_4_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_5_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_6_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_7_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_8_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_9_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2_n_0\ : STD_LOGIC;
signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_burst_total[0]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[12]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[13]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[14]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[15]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[16]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[17]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[18]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[19]_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[11]_i_8\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[11]_i_9\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[12]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[13]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[14]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[15]_i_1__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[16]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[17]_i_1__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[18]_i_1__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[19]_i_2__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2__0\ : label is "soft_lutpair14";
begin
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs_reg[2]\ <= \^fsm_sequential_gen_no_rd_cmd_opt.rd_data_sm_cs_reg[2]\;
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_bram_addr_inc_d1_reg\(2 downto 0) <= \^gen_no_rd_cmd_opt.gen_narrow_cnt.narrow_bram_addr_inc_d1_reg\(2 downto 0);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_EN.curr_narrow_burst_reg\ <= \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\;
SR(0) <= \^sr\(0);
s_axi_arsize_0_sp_1 <= s_axi_arsize_0_sn_1;
\ADDR_SNG_PORT.bram_addr_int[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE02FEFEFE020202"
)
port map (
I0 => \ADDR_SNG_PORT.bram_addr_int_reg[10]\,
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => \ADDR_SNG_PORT.bram_addr_int_reg[11]\,
I3 => RdChnl_BRAM_Addr_Ld(10),
I4 => Arb2AR_Active,
I5 => \ADDR_SNG_PORT.bram_addr_int_reg[19]\(4),
O => D(4)
);
\ADDR_SNG_PORT.bram_addr_int[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEFFFEFFEEEEFEEE"
)
port map (
I0 => \ADDR_SNG_PORT.bram_addr_int_reg[11]\,
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => \ADDR_SNG_PORT.bram_addr_int_reg[11]_1\,
I3 => Arb2AR_Active,
I4 => curr_fixed_burst_reg,
I5 => \ADDR_SNG_PORT.bram_addr_int_reg[11]_2\,
O => E(0)
);
\ADDR_SNG_PORT.bram_addr_int[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE02FEFEFE020202"
)
port map (
I0 => \ADDR_SNG_PORT.bram_addr_int_reg[11]_0\,
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => \ADDR_SNG_PORT.bram_addr_int_reg[11]\,
I3 => RdChnl_BRAM_Addr_Ld(11),
I4 => Arb2AR_Active,
I5 => \ADDR_SNG_PORT.bram_addr_int_reg[19]\(5),
O => D(5)
);
\ADDR_SNG_PORT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => data0(10),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(9),
I3 => Arb2AR_Active,
I4 => \ADDR_SNG_PORT.bram_addr_int_reg[19]\(6),
O => D(6)
);
\ADDR_SNG_PORT.bram_addr_int[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => data0(11),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(10),
I3 => Arb2AR_Active,
I4 => \ADDR_SNG_PORT.bram_addr_int_reg[19]\(7),
O => D(7)
);
\ADDR_SNG_PORT.bram_addr_int[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => data0(12),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(11),
I3 => Arb2AR_Active,
I4 => \ADDR_SNG_PORT.bram_addr_int_reg[19]\(8),
O => D(8)
);
\ADDR_SNG_PORT.bram_addr_int[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => data0(13),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(12),
I3 => Arb2AR_Active,
I4 => \ADDR_SNG_PORT.bram_addr_int_reg[19]\(9),
O => D(9)
);
\ADDR_SNG_PORT.bram_addr_int[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => data0(14),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(13),
I3 => Arb2AR_Active,
I4 => \ADDR_SNG_PORT.bram_addr_int_reg[19]\(10),
O => D(10)
);
\ADDR_SNG_PORT.bram_addr_int[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => data0(15),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(14),
I3 => Arb2AR_Active,
I4 => \ADDR_SNG_PORT.bram_addr_int_reg[19]\(11),
O => D(11)
);
\ADDR_SNG_PORT.bram_addr_int[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => data0(16),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(15),
I3 => Arb2AR_Active,
I4 => \ADDR_SNG_PORT.bram_addr_int_reg[19]\(12),
O => D(12)
);
\ADDR_SNG_PORT.bram_addr_int[19]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF4F"
)
port map (
I0 => \ADDR_SNG_PORT.bram_addr_int_reg[19]_0\,
I1 => Arb2AR_Active,
I2 => \ADDR_SNG_PORT.bram_addr_int_reg[19]_1\,
I3 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
O => E(1)
);
\ADDR_SNG_PORT.bram_addr_int[19]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => data0(17),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(16),
I3 => Arb2AR_Active,
I4 => \ADDR_SNG_PORT.bram_addr_int_reg[19]\(13),
O => D(13)
);
\ADDR_SNG_PORT.bram_addr_int[19]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000011111113"
)
port map (
I0 => curr_narrow_burst,
I1 => \^fsm_sequential_gen_no_rd_cmd_opt.rd_data_sm_cs_reg[2]\,
I2 => narrow_bram_addr_inc_d1,
I3 => \save_init_bram_addr_ld_reg[19]_0\(0),
I4 => \save_init_bram_addr_ld_reg[19]_0\(1),
I5 => \save_init_bram_addr_ld[11]_i_4_n_0\,
O => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\
);
\ADDR_SNG_PORT.bram_addr_int[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE02FEFEFE020202"
)
port map (
I0 => \ADDR_SNG_PORT.bram_addr_int_reg[6]\,
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => \ADDR_SNG_PORT.bram_addr_int_reg[11]\,
I3 => RdChnl_BRAM_Addr_Ld(6),
I4 => Arb2AR_Active,
I5 => \ADDR_SNG_PORT.bram_addr_int_reg[19]\(0),
O => D(0)
);
\ADDR_SNG_PORT.bram_addr_int[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE02FEFEFE020202"
)
port map (
I0 => \ADDR_SNG_PORT.bram_addr_int_reg[7]\,
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => \ADDR_SNG_PORT.bram_addr_int_reg[11]\,
I3 => RdChnl_BRAM_Addr_Ld(7),
I4 => Arb2AR_Active,
I5 => \ADDR_SNG_PORT.bram_addr_int_reg[19]\(1),
O => D(1)
);
\ADDR_SNG_PORT.bram_addr_int[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE02FEFEFE020202"
)
port map (
I0 => \ADDR_SNG_PORT.bram_addr_int_reg[8]\,
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => \ADDR_SNG_PORT.bram_addr_int_reg[11]\,
I3 => RdChnl_BRAM_Addr_Ld(8),
I4 => Arb2AR_Active,
I5 => \ADDR_SNG_PORT.bram_addr_int_reg[19]\(2),
O => D(2)
);
\ADDR_SNG_PORT.bram_addr_int[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE02FEFEFE020202"
)
port map (
I0 => \ADDR_SNG_PORT.bram_addr_int_reg[9]\,
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => \ADDR_SNG_PORT.bram_addr_int_reg[11]\,
I3 => RdChnl_BRAM_Addr_Ld(9),
I4 => Arb2AR_Active,
I5 => \ADDR_SNG_PORT.bram_addr_int_reg[19]\(3),
O => D(3)
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_bram_addr_inc_d1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FEFEF0F0FFF5"
)
port map (
I0 => Q(2),
I1 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[0]\,
I2 => \save_init_bram_addr_ld[11]_i_6_n_0\,
I3 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_bram_addr_inc_d1_i_3_n_0\,
I4 => Q(0),
I5 => Q(1),
O => \^fsm_sequential_gen_no_rd_cmd_opt.rd_data_sm_cs_reg[2]\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_bram_addr_inc_d1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => s_axi_rready,
I1 => \save_init_bram_addr_ld[11]_i_3_0\,
I2 => end_brst_rd,
I3 => brst_zero,
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_bram_addr_inc_d1_i_3_n_0\
);
bram_rst_a_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\save_init_bram_addr_ld[10]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBBBA0000888A"
)
port map (
I0 => data0(8),
I1 => \save_init_bram_addr_ld[11]_i_2_n_0\,
I2 => narrow_bram_addr_inc_d1,
I3 => \save_init_bram_addr_ld[11]_i_3_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_4_n_0\,
I5 => s_axi_araddr(7),
O => RdChnl_BRAM_Addr_Ld(10)
);
\save_init_bram_addr_ld[11]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \save_init_bram_addr_ld_reg[19]_0\(0),
I1 => \save_init_bram_addr_ld_reg[19]_0\(1),
O => \save_init_bram_addr_ld[11]_i_10_n_0\
);
\save_init_bram_addr_ld[11]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008FC00000"
)
port map (
I0 => \save_init_bram_addr_ld[11]_i_4_0\(2),
I1 => \save_init_bram_addr_ld[11]_i_4_0\(1),
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(0),
I4 => \save_init_bram_addr_ld[11]_i_4_0\(0),
I5 => wrap_burst_total(2),
O => \save_init_bram_addr_ld[11]_i_11_n_0\
);
\save_init_bram_addr_ld[11]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBBBA0000888A"
)
port map (
I0 => data0(9),
I1 => \save_init_bram_addr_ld[11]_i_2_n_0\,
I2 => narrow_bram_addr_inc_d1,
I3 => \save_init_bram_addr_ld[11]_i_3_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_4_n_0\,
I5 => s_axi_araddr(8),
O => RdChnl_BRAM_Addr_Ld(11)
);
\save_init_bram_addr_ld[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0101010101010001"
)
port map (
I0 => curr_narrow_burst,
I1 => \save_init_bram_addr_ld[11]_i_5_n_0\,
I2 => \save_init_bram_addr_ld[11]_i_6_n_0\,
I3 => \save_init_bram_addr_ld[11]_i_7_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_8_n_0\,
I5 => Q(0),
O => \save_init_bram_addr_ld[11]_i_2_n_0\
);
\save_init_bram_addr_ld[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF75FFFFFFFF"
)
port map (
I0 => curr_narrow_burst,
I1 => \save_init_bram_addr_ld[11]_i_9_n_0\,
I2 => \save_init_bram_addr_ld[11]_i_7_n_0\,
I3 => \save_init_bram_addr_ld[11]_i_6_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_5_n_0\,
I5 => \save_init_bram_addr_ld[11]_i_10_n_0\,
O => \save_init_bram_addr_ld[11]_i_3_n_0\
);
\save_init_bram_addr_ld[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFDFF"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => \save_init_bram_addr_ld_reg[11]_0\,
I2 => wrap_burst_total(0),
I3 => wrap_burst_total(2),
I4 => wrap_burst_total(1),
I5 => \save_init_bram_addr_ld[11]_i_11_n_0\,
O => \save_init_bram_addr_ld[11]_i_4_n_0\
);
\save_init_bram_addr_ld[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFF000000000000"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
I2 => \save_init_bram_addr_ld[11]_i_3_0\,
I3 => s_axi_rready,
I4 => Q(0),
I5 => Q(1),
O => \save_init_bram_addr_ld[11]_i_5_n_0\
);
\save_init_bram_addr_ld[11]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEECCCCEEEFCCCC"
)
port map (
I0 => Q(2),
I1 => Q(3),
I2 => axi_rd_burst,
I3 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[0]\,
I4 => Q(0),
I5 => Q(1),
O => \save_init_bram_addr_ld[11]_i_6_n_0\
);
\save_init_bram_addr_ld[11]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEFFFFFFF"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
I2 => \save_init_bram_addr_ld[11]_i_3_0\,
I3 => s_axi_rready,
I4 => Q(2),
I5 => Q(1),
O => \save_init_bram_addr_ld[11]_i_7_n_0\
);
\save_init_bram_addr_ld[11]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[0]\,
I1 => Q(1),
I2 => Q(2),
O => \save_init_bram_addr_ld[11]_i_8_n_0\
);
\save_init_bram_addr_ld[11]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"AABA"
)
port map (
I0 => Q(0),
I1 => Q(2),
I2 => Q(1),
I3 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[0]\,
O => \save_init_bram_addr_ld[11]_i_9_n_0\
);
\save_init_bram_addr_ld[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(10),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(9),
O => RdChnl_BRAM_Addr_Ld(12)
);
\save_init_bram_addr_ld[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(11),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(10),
O => RdChnl_BRAM_Addr_Ld(13)
);
\save_init_bram_addr_ld[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(12),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(11),
O => RdChnl_BRAM_Addr_Ld(14)
);
\save_init_bram_addr_ld[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(13),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(12),
O => RdChnl_BRAM_Addr_Ld(15)
);
\save_init_bram_addr_ld[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(14),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(13),
O => RdChnl_BRAM_Addr_Ld(16)
);
\save_init_bram_addr_ld[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(15),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(14),
O => RdChnl_BRAM_Addr_Ld(17)
);
\save_init_bram_addr_ld[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(16),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(15),
O => RdChnl_BRAM_Addr_Ld(18)
);
\save_init_bram_addr_ld[19]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => data0(17),
I1 => \^gen_no_rd_cmd_opt.gen_narrow_en.curr_narrow_burst_reg\,
I2 => s_axi_araddr(16),
O => RdChnl_BRAM_Addr_Ld(19)
);
\save_init_bram_addr_ld[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBBBA0000888A"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2_n_0\,
I1 => \save_init_bram_addr_ld[11]_i_2_n_0\,
I2 => narrow_bram_addr_inc_d1,
I3 => \save_init_bram_addr_ld[11]_i_3_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_4_n_0\,
I5 => s_axi_araddr(0),
O => \^gen_no_rd_cmd_opt.gen_narrow_cnt.narrow_bram_addr_inc_d1_reg\(0)
);
\save_init_bram_addr_ld[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"C80C"
)
port map (
I0 => wrap_burst_total(0),
I1 => data0(1),
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
O => \save_init_bram_addr_ld[3]_i_2_n_0\
);
\save_init_bram_addr_ld[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBBBA0000888A"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2_n_0\,
I1 => \save_init_bram_addr_ld[11]_i_2_n_0\,
I2 => narrow_bram_addr_inc_d1,
I3 => \save_init_bram_addr_ld[11]_i_3_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_4_n_0\,
I5 => s_axi_araddr(1),
O => \^gen_no_rd_cmd_opt.gen_narrow_cnt.narrow_bram_addr_inc_d1_reg\(1)
);
\save_init_bram_addr_ld[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => data0(2),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[4]_i_2_n_0\
);
\save_init_bram_addr_ld[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBBBA0000888A"
)
port map (
I0 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I1 => \save_init_bram_addr_ld[11]_i_2_n_0\,
I2 => narrow_bram_addr_inc_d1,
I3 => \save_init_bram_addr_ld[11]_i_3_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_4_n_0\,
I5 => s_axi_araddr(2),
O => \^gen_no_rd_cmd_opt.gen_narrow_cnt.narrow_bram_addr_inc_d1_reg\(2)
);
\save_init_bram_addr_ld[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => data0(3),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[5]_i_2_n_0\
);
\save_init_bram_addr_ld[6]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBBBA0000888A"
)
port map (
I0 => data0(4),
I1 => \save_init_bram_addr_ld[11]_i_2_n_0\,
I2 => narrow_bram_addr_inc_d1,
I3 => \save_init_bram_addr_ld[11]_i_3_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_4_n_0\,
I5 => s_axi_araddr(3),
O => RdChnl_BRAM_Addr_Ld(6)
);
\save_init_bram_addr_ld[7]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBBBA0000888A"
)
port map (
I0 => data0(5),
I1 => \save_init_bram_addr_ld[11]_i_2_n_0\,
I2 => narrow_bram_addr_inc_d1,
I3 => \save_init_bram_addr_ld[11]_i_3_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_4_n_0\,
I5 => s_axi_araddr(4),
O => RdChnl_BRAM_Addr_Ld(7)
);
\save_init_bram_addr_ld[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBBBA0000888A"
)
port map (
I0 => data0(6),
I1 => \save_init_bram_addr_ld[11]_i_2_n_0\,
I2 => narrow_bram_addr_inc_d1,
I3 => \save_init_bram_addr_ld[11]_i_3_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_4_n_0\,
I5 => s_axi_araddr(5),
O => RdChnl_BRAM_Addr_Ld(8)
);
\save_init_bram_addr_ld[9]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBBBA0000888A"
)
port map (
I0 => data0(7),
I1 => \save_init_bram_addr_ld[11]_i_2_n_0\,
I2 => narrow_bram_addr_inc_d1,
I3 => \save_init_bram_addr_ld[11]_i_3_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_4_n_0\,
I5 => s_axi_araddr(6),
O => RdChnl_BRAM_Addr_Ld(9)
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => RdChnl_BRAM_Addr_Ld(10),
Q => data0(8),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => RdChnl_BRAM_Addr_Ld(11),
Q => data0(9),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => RdChnl_BRAM_Addr_Ld(12),
Q => data0(10),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => RdChnl_BRAM_Addr_Ld(13),
Q => data0(11),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => RdChnl_BRAM_Addr_Ld(14),
Q => data0(12),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => RdChnl_BRAM_Addr_Ld(15),
Q => data0(13),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => RdChnl_BRAM_Addr_Ld(16),
Q => data0(14),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => RdChnl_BRAM_Addr_Ld(17),
Q => data0(15),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => RdChnl_BRAM_Addr_Ld(18),
Q => data0(16),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => RdChnl_BRAM_Addr_Ld(19),
Q => data0(17),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => \^gen_no_rd_cmd_opt.gen_narrow_cnt.narrow_bram_addr_inc_d1_reg\(0),
Q => data0(1),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => \^gen_no_rd_cmd_opt.gen_narrow_cnt.narrow_bram_addr_inc_d1_reg\(1),
Q => data0(2),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => \^gen_no_rd_cmd_opt.gen_narrow_cnt.narrow_bram_addr_inc_d1_reg\(2),
Q => data0(3),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => RdChnl_BRAM_Addr_Ld(6),
Q => data0(4),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => RdChnl_BRAM_Addr_Ld(7),
Q => data0(5),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => RdChnl_BRAM_Addr_Ld(8),
Q => data0(6),
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => RdChnl_BRAM_Addr_Ld(9),
Q => data0(7),
R => \^sr\(0)
);
\wrap_burst_total[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0010FF10001000"
)
port map (
I0 => \wrap_burst_total[0]_i_2__0_n_0\,
I1 => s_axi_arsize(2),
I2 => s_axi_arlen(0),
I3 => s_axi_arlen(1),
I4 => s_axi_arlen(2),
I5 => \wrap_burst_total[0]_i_3__0_n_0\,
O => \wrap_burst_total[0]_i_1__0_n_0\
);
\wrap_burst_total[0]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F6FB"
)
port map (
I0 => s_axi_arlen(3),
I1 => s_axi_arlen(2),
I2 => s_axi_arsize(1),
I3 => s_axi_arsize(0),
O => \wrap_burst_total[0]_i_2__0_n_0\
);
\wrap_burst_total[0]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00100000"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(1),
I3 => s_axi_arlen(3),
I4 => s_axi_arlen(0),
O => \wrap_burst_total[0]_i_3__0_n_0\
);
\wrap_burst_total[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0003000000060004"
)
port map (
I0 => s_axi_arsize(0),
I1 => s_axi_arsize(1),
I2 => \wrap_burst_total[1]_i_2__0_n_0\,
I3 => s_axi_arsize(2),
I4 => s_axi_arlen(2),
I5 => s_axi_arlen(3),
O => \wrap_burst_total[1]_i_1__0_n_0\
);
\wrap_burst_total[1]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi_arlen(0),
I1 => s_axi_arlen(1),
O => \wrap_burst_total[1]_i_2__0_n_0\
);
\wrap_burst_total[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => s_axi_arsize_0_sn_1,
I1 => s_axi_arlen(0),
I2 => s_axi_arlen(1),
I3 => s_axi_arlen(3),
I4 => s_axi_arlen(2),
O => \wrap_burst_total[2]_i_1_n_0\
);
\wrap_burst_total[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => s_axi_arsize(0),
I1 => s_axi_arsize(1),
I2 => s_axi_arsize(2),
O => s_axi_arsize_0_sn_1
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => \wrap_burst_total[0]_i_1__0_n_0\,
Q => wrap_burst_total(0),
R => \^sr\(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => \wrap_burst_total[1]_i_1__0_n_0\,
Q => wrap_burst_total(1),
R => \^sr\(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => \wrap_burst_total[2]_i_1_n_0\,
Q => wrap_burst_total(2),
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_bram_ctrl_0_1_rd_chnl is
port (
ar_active_d1 : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
\GEN_NO_RD_CMD_OPT.axi_rvalid_int_reg_0\ : out STD_LOGIC;
\GEN_NO_RD_CMD_OPT.axi_rlast_int_reg_0\ : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
BRAM_En_B_i : out STD_LOGIC;
s_axi_arsize_0_sp_1 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_NO_RD_CMD_OPT.GEN_NARROW_EN.curr_narrow_burst_reg_0\ : out STD_LOGIC;
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_bram_addr_inc_d1_reg_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlen_6_sp_1 : out STD_LOGIC;
s_axi_rready_0 : out STD_LOGIC;
Arb2AR_Active : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
ar_active_re : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rready : in STD_LOGIC;
\GEN_NO_RD_CMD_OPT.act_rd_burst_two_reg_0\ : in STD_LOGIC;
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
\ADDR_SNG_PORT.bram_addr_int_reg[6]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[11]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[19]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\ADDR_SNG_PORT.bram_addr_int_reg[7]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[8]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[9]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[10]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[11]_0\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[11]_1\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[19]_0\ : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 18 downto 0 );
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]_0\ : in STD_LOGIC;
\GEN_NO_RD_CMD_OPT.brst_one_reg_0\ : in STD_LOGIC;
\save_init_bram_addr_ld_reg[11]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end design_1_axi_bram_ctrl_0_1_rd_chnl;
architecture STRUCTURE of design_1_axi_bram_ctrl_0_1_rd_chnl is
signal \ADDR_SNG_PORT.bram_addr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \^bram_en_b_i\ : STD_LOGIC;
signal \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_4_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_4_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_5_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_i_3_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_reg_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_10_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_11_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_12_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_13_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_14_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_15_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_16_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_17_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_18_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_19_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_20_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_21_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_22_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_23_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_3_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_4_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_5_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_6_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_9_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_EN.curr_narrow_burst_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_NARROW_EN.curr_narrow_burst_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_i_3_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_reg_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_UA_NARROW.I_UA_NARROW_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.GEN_UA_NARROW.I_UA_NARROW_n_1\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.I_WRAP_BRST_n_21\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.act_rd_burst_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.act_rd_burst_i_3_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.act_rd_burst_i_4_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.act_rd_burst_i_6_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.act_rd_burst_two_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.axi_rlast_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.axi_rlast_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.axi_rlast_int_i_3_n_0\ : STD_LOGIC;
signal \^gen_no_rd_cmd_opt.axi_rlast_int_reg_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.axi_rvalid_clr_ok_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.axi_rvalid_clr_ok_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.axi_rvalid_int_i_1_n_0\ : STD_LOGIC;
signal \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.bram_en_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.bram_en_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.bram_en_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.bram_en_int_i_4_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.bram_en_int_i_5_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.bram_en_int_i_6_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.bram_en_int_i_7_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.bram_en_int_i_8_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.brst_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.brst_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.brst_cnt[6]_i_3_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.brst_cnt_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \GEN_NO_RD_CMD_OPT.brst_one_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.brst_one_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.brst_one_i_3_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.brst_zero_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.disable_b2b_brst_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.disable_b2b_brst_i_3_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.end_brst_rd_clr_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.end_brst_rd_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.last_bram_addr_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.last_bram_addr_i_3_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.last_bram_addr_i_4_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.last_bram_addr_i_5_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.last_bram_addr_i_6_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.pend_rd_op_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.pend_rd_op_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.pend_rd_op_i_4_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.pend_rd_op_i_5_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.pend_rd_op_i_6_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.pend_rd_op_reg_i_3_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.rddata_mux_sel_i_1_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.rddata_mux_sel_i_2_n_0\ : STD_LOGIC;
signal \GEN_NO_RD_CMD_OPT.rddata_mux_sel_i_3_n_0\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal act_rd_burst : STD_LOGIC;
signal act_rd_burst_set : STD_LOGIC;
signal act_rd_burst_two : STD_LOGIC;
signal \^ar_active_d1\ : STD_LOGIC;
signal axi_rd_burst : STD_LOGIC;
signal axi_rd_burst0 : STD_LOGIC;
signal axi_rd_burst_two : STD_LOGIC;
signal axi_rdata_en : STD_LOGIC;
signal axi_rid_temp : STD_LOGIC;
signal axi_rvalid_clr_ok : STD_LOGIC;
signal axi_rvalid_set : STD_LOGIC;
signal axi_rvalid_set_cmb : STD_LOGIC;
signal brst_cnt_max_d1 : STD_LOGIC;
signal brst_one : STD_LOGIC;
signal brst_zero : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_narrow_burst : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal disable_b2b_brst : STD_LOGIC;
signal disable_b2b_brst_cmb : STD_LOGIC;
signal end_brst_rd : STD_LOGIC;
signal end_brst_rd_clr : STD_LOGIC;
signal last_bram_addr : STD_LOGIC;
signal last_bram_addr0 : STD_LOGIC;
signal narrow_addr_int : STD_LOGIC_VECTOR ( 1 downto 0 );
signal narrow_bram_addr_inc : STD_LOGIC;
signal narrow_bram_addr_inc_d1 : STD_LOGIC;
signal narrow_burst_cnt_ld_reg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \p_0_in__0\ : STD_LOGIC;
signal pend_rd_op : STD_LOGIC;
signal rd_data_sm_cs : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_data_sm_ns : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_skid_buf : STD_LOGIC_VECTOR ( 31 downto 0 );
signal rd_skid_buf_ld : STD_LOGIC;
signal rd_skid_buf_ld_cmb : STD_LOGIC;
signal rd_skid_buf_ld_reg : STD_LOGIC;
signal rddata_mux_sel : STD_LOGIC;
signal rlast_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rlast_sm_ns : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s_axi_arlen_6_sn_1 : STD_LOGIC;
signal s_axi_arsize_0_sn_1 : STD_LOGIC;
signal \^s_axi_rid\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[11]_i_4\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_2\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_5\ : label is "soft_lutpair29";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs_reg[0]\ : label is "sec_addr:0010,sng_addr:0001,last_data_ar_pend:1000,idle:0000,last_addr:0101,last_data:0111,full_throttle:0100,last_throttle:0110,full_pipe:0011";
attribute FSM_ENCODED_STATES of \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs_reg[1]\ : label is "sec_addr:0010,sng_addr:0001,last_data_ar_pend:1000,idle:0000,last_addr:0101,last_data:0111,full_throttle:0100,last_throttle:0110,full_pipe:0011";
attribute FSM_ENCODED_STATES of \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs_reg[2]\ : label is "sec_addr:0010,sng_addr:0001,last_data_ar_pend:1000,idle:0000,last_addr:0101,last_data:0111,full_throttle:0100,last_throttle:0110,full_pipe:0011";
attribute FSM_ENCODED_STATES of \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs_reg[3]\ : label is "sec_addr:0010,sng_addr:0001,last_data_ar_pend:1000,idle:0000,last_addr:0101,last_data:0111,full_throttle:0100,last_throttle:0110,full_pipe:0011";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[1]_i_2\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[2]_i_2\ : label is "soft_lutpair22";
attribute FSM_ENCODED_STATES of \FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs_reg[0]\ : label is "idle:000,w8_last_data:100,w8_2nd_last_data:011,w8_throttle:010,w8_throttle_b2:001";
attribute FSM_ENCODED_STATES of \FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs_reg[1]\ : label is "idle:000,w8_last_data:100,w8_2nd_last_data:011,w8_throttle:010,w8_throttle_b2:001";
attribute FSM_ENCODED_STATES of \FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs_reg[2]\ : label is "idle:000,w8_last_data:100,w8_2nd_last_data:011,w8_throttle:010,w8_throttle_b2:001";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_11\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_15\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_16\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_17\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_18\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_19\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_21\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_22\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_23\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_3\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_bram_addr_inc_d1_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_i_3\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_i_2\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.act_rd_burst_i_3\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.act_rd_burst_i_4\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.act_rd_burst_i_6\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.act_rd_burst_i_7\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.act_rd_burst_two_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.axi_rlast_int_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.axi_rvalid_clr_ok_i_2\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.axi_rvalid_set_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.bram_en_int_i_8\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.brst_cnt[5]_i_2\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.brst_cnt[6]_i_2\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.brst_zero_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.curr_fixed_burst_reg_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.curr_wrap_burst_reg_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.last_bram_addr_i_2\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.last_bram_addr_i_6\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.pend_rd_op_i_2\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.pend_rd_op_i_6\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \GEN_NO_RD_CMD_OPT.rddata_mux_sel_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of axi_awready_int_i_2 : label is "soft_lutpair21";
begin
BRAM_En_B_i <= \^bram_en_b_i\;
\GEN_NO_RD_CMD_OPT.axi_rlast_int_reg_0\ <= \^gen_no_rd_cmd_opt.axi_rlast_int_reg_0\;
\GEN_NO_RD_CMD_OPT.axi_rvalid_int_reg_0\ <= \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\;
SR(0) <= \^sr\(0);
ar_active_d1 <= \^ar_active_d1\;
s_axi_arlen_6_sp_1 <= s_axi_arlen_6_sn_1;
s_axi_arsize_0_sp_1 <= s_axi_arsize_0_sn_1;
s_axi_rid(0) <= \^s_axi_rid\(0);
\ADDR_SNG_PORT.bram_addr_int[11]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"000100FF"
)
port map (
I0 => narrow_addr_int(1),
I1 => narrow_addr_int(0),
I2 => narrow_bram_addr_inc_d1,
I3 => \GEN_NO_RD_CMD_OPT.I_WRAP_BRST_n_21\,
I4 => curr_narrow_burst,
O => \ADDR_SNG_PORT.bram_addr_int[11]_i_4_n_0\
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000D0F3F0F3F"
)
port map (
I0 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_2_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(1),
I4 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_3_n_0\,
I5 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_4_n_0\,
O => rd_data_sm_ns(0)
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => axi_rd_burst,
I1 => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_reg_n_0\,
O => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_2_n_0\
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"F700F700F7000000"
)
port map (
I0 => \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\,
I1 => s_axi_rready,
I2 => ar_active_re,
I3 => rd_data_sm_cs(2),
I4 => act_rd_burst_two,
I5 => act_rd_burst,
O => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_3_n_0\
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBFBBBB00000000"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
I1 => rd_data_sm_cs(1),
I2 => pend_rd_op,
I3 => ar_active_re,
I4 => rd_data_sm_cs(2),
I5 => rd_data_sm_cs(0),
O => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_4_n_0\
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4445444444444444"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[1]_i_2_n_0\,
I2 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_4_n_0\,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => rd_data_sm_cs(2),
O => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000FAFF0F3300"
)
port map (
I0 => axi_rd_burst,
I1 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_5_n_0\,
I2 => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_reg_n_0\,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[1]_i_2_n_0\
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4445444444444444"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[2]_i_2_n_0\,
I2 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_4_n_0\,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => rd_data_sm_cs(2),
O => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F083F083C083C38"
)
port map (
I0 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_5_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => axi_rd_burst,
I5 => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_reg_n_0\,
O => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[2]_i_2_n_0\
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0705070507050735"
)
port map (
I0 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_3_n_0\,
I1 => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(0),
I5 => rd_data_sm_cs(1),
O => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_1_n_0\
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C08000000080000"
)
port map (
I0 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_4_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
O => rd_data_sm_ns(3)
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555FF5502000255"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
I2 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_5_n_0\,
I3 => rd_data_sm_cs(1),
I4 => ar_active_re,
I5 => rd_data_sm_cs(2),
O => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_3_n_0\
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440000000000000"
)
port map (
I0 => \^ar_active_d1\,
I1 => Arb2AR_Active,
I2 => act_rd_burst_two,
I3 => act_rd_burst,
I4 => \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\,
I5 => s_axi_rready,
O => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_4_n_0\
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
O => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_5_n_0\
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_1_n_0\,
D => rd_data_sm_ns(0),
Q => rd_data_sm_cs(0),
R => \^sr\(0)
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_1_n_0\,
D => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[1]_i_1_n_0\,
Q => rd_data_sm_cs(1),
R => \^sr\(0)
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_1_n_0\,
D => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[2]_i_1_n_0\,
Q => rd_data_sm_cs(2),
R => \^sr\(0)
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_1_n_0\,
D => rd_data_sm_ns(3),
Q => rd_data_sm_cs(3),
R => \^sr\(0)
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAA80AA88"
)
port map (
I0 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[1]_i_2_n_0\,
I1 => axi_rd_burst,
I2 => act_rd_burst_two,
I3 => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_reg_n_0\,
I4 => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
I5 => rlast_sm_cs(1),
O => rlast_sm_ns(0)
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA0008AA88"
)
port map (
I0 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[1]_i_2_n_0\,
I1 => axi_rd_burst,
I2 => act_rd_burst_two,
I3 => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_reg_n_0\,
I4 => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
I5 => rlast_sm_cs(1),
O => rlast_sm_ns(1)
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
O => \FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[1]_i_2_n_0\
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F3E000200020002"
)
port map (
I0 => last_bram_addr,
I1 => rlast_sm_cs(0),
I2 => rlast_sm_cs(2),
I3 => rlast_sm_cs(1),
I4 => s_axi_rready,
I5 => \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\,
O => \FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F000001"
)
port map (
I0 => axi_rd_burst,
I1 => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_reg_n_0\,
I2 => rlast_sm_cs(2),
I3 => rlast_sm_cs(0),
I4 => rlast_sm_cs(1),
O => rlast_sm_ns(2)
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[2]_i_1_n_0\,
D => rlast_sm_ns(0),
Q => rlast_sm_cs(0),
R => \^sr\(0)
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[2]_i_1_n_0\,
D => rlast_sm_ns(1),
Q => rlast_sm_cs(1),
R => \^sr\(0)
);
\FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \FSM_sequential_GEN_NO_RD_CMD_OPT.rlast_sm_cs[2]_i_1_n_0\,
D => rlast_sm_ns(2),
Q => rlast_sm_cs(2),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_AR_SNG.ar_active_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => Arb2AR_Active,
Q => \^ar_active_d1\,
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00B00000"
)
port map (
I0 => \^ar_active_d1\,
I1 => Arb2AR_Active,
I2 => s_axi_aresetn,
I3 => end_brst_rd_clr,
I4 => \GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_i_2_n_0\,
O => \GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00015555"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_i_3_n_0\,
I1 => narrow_addr_int(0),
I2 => narrow_addr_int(1),
I3 => \GEN_NO_RD_CMD_OPT.I_WRAP_BRST_n_21\,
I4 => curr_narrow_burst,
I5 => \GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_reg_n_0\,
O => \GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"BF"
)
port map (
I0 => pend_rd_op,
I1 => brst_zero,
I2 => Arb2AR_Active,
O => \GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_i_3_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_i_1_n_0\,
Q => \GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_reg_n_0\,
R => '0'
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.I_WRAP_BRST_n_21\,
I1 => curr_narrow_burst,
I2 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_3_n_0\,
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008888FFF44444"
)
port map (
I0 => s_axi_arsize(0),
I1 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_17_n_0\,
I2 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_14_n_0\,
I3 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_15_n_0\,
I4 => s_axi_arsize(2),
I5 => s_axi_arsize(1),
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_10_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"1F441144"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_18_n_0\,
I1 => s_axi_arsize(0),
I2 => s_axi_arsize(2),
I3 => s_axi_arsize(1),
I4 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_19_n_0\,
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_11_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F1FFFFFFF1FFF5F5"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_20_n_0\,
I1 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_21_n_0\,
I2 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_22_n_0\,
I3 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_17_n_0\,
I4 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_23_n_0\,
I5 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_18_n_0\,
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_12_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000303000023037"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arlen(6),
I2 => s_axi_arsize(0),
I3 => s_axi_arlen(7),
I4 => s_axi_arlen(4),
I5 => s_axi_arlen(5),
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_13_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => s_axi_arsize(0),
I2 => s_axi_arlen(5),
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_14_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => s_axi_arsize(0),
I2 => s_axi_arlen(1),
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_15_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA80CFC0"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arlen(2),
I2 => s_axi_arsize(0),
I3 => s_axi_arlen(3),
I4 => s_axi_arsize(1),
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_16_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => s_axi_arlen(2),
I1 => s_axi_arlen(3),
I2 => s_axi_arlen(6),
I3 => s_axi_arsize(0),
I4 => s_axi_arlen(7),
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_17_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arlen(0),
I1 => s_axi_arlen(1),
I2 => s_axi_arlen(4),
I3 => s_axi_arsize(0),
I4 => s_axi_arlen(5),
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_18_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => s_axi_arlen(3),
I1 => s_axi_arlen(2),
I2 => s_axi_arlen(7),
I3 => s_axi_arsize(0),
I4 => s_axi_arlen(6),
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_19_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"D757"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(1),
I2 => s_axi_arsize(0),
I3 => s_axi_arlen(1),
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_20_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_21\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => s_axi_arsize(0),
I2 => s_axi_arlen(2),
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_21_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_22\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(1),
I2 => s_axi_arsize(0),
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_22_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(0),
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_23_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF04FFFF"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(1),
I2 => s_axi_arsize(0),
I3 => \^ar_active_d1\,
I4 => Arb2AR_Active,
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_3_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => narrow_addr_int(0),
I1 => narrow_addr_int(1),
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_4_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA2"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_3_n_0\,
I1 => curr_narrow_burst,
I2 => \GEN_NO_RD_CMD_OPT.I_WRAP_BRST_n_21\,
I3 => narrow_addr_int(1),
I4 => narrow_addr_int(0),
I5 => narrow_bram_addr_inc_d1,
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_5_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888A88888888"
)
port map (
I0 => s_axi_arburst(1),
I1 => s_axi_arburst(0),
I2 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_9_n_0\,
I3 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_10_n_0\,
I4 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_11_n_0\,
I5 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_12_n_0\,
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_6_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF113011"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_13_n_0\,
I1 => s_axi_arsize(2),
I2 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_14_n_0\,
I3 => s_axi_arsize(1),
I4 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_15_n_0\,
I5 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_16_n_0\,
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_9_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_1_n_0\,
D => \GEN_NO_RD_CMD_OPT.GEN_UA_NARROW.I_UA_NARROW_n_1\,
Q => narrow_addr_int(0),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_1_n_0\,
D => \GEN_NO_RD_CMD_OPT.GEN_UA_NARROW.I_UA_NARROW_n_0\,
Q => narrow_addr_int(1),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_bram_addr_inc_d1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => narrow_addr_int(0),
I1 => narrow_addr_int(1),
I2 => \GEN_NO_RD_CMD_OPT.I_WRAP_BRST_n_21\,
I3 => curr_narrow_burst,
O => narrow_bram_addr_inc
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_bram_addr_inc_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => narrow_bram_addr_inc,
Q => narrow_bram_addr_inc_d1,
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF1F0010"
)
port map (
I0 => s_axi_arsize(1),
I1 => s_axi_arsize(2),
I2 => Arb2AR_Active,
I3 => \^ar_active_d1\,
I4 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg_n_0_[0]\,
O => narrow_burst_cnt_ld_reg(0)
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF01FF00000100"
)
port map (
I0 => s_axi_arsize(2),
I1 => s_axi_arsize(1),
I2 => s_axi_arsize(0),
I3 => Arb2AR_Active,
I4 => \^ar_active_d1\,
I5 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg_n_0_[1]\,
O => narrow_burst_cnt_ld_reg(1)
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => narrow_burst_cnt_ld_reg(0),
Q => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg_n_0_[0]\,
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => narrow_burst_cnt_ld_reg(1),
Q => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg_n_0_[1]\,
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_EN.curr_narrow_burst_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFBA"
)
port map (
I0 => pend_rd_op,
I1 => \^ar_active_d1\,
I2 => Arb2AR_Active,
I3 => \GEN_NO_RD_CMD_OPT.axi_rlast_int_i_3_n_0\,
I4 => \GEN_NO_RD_CMD_OPT.GEN_NARROW_EN.curr_narrow_burst_i_2_n_0\,
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_EN.curr_narrow_burst_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_EN.curr_narrow_burst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7F7775757577"
)
port map (
I0 => s_axi_aresetn,
I1 => curr_narrow_burst,
I2 => \GEN_NO_RD_CMD_OPT.act_rd_burst_two_reg_0\,
I3 => s_axi_arburst(0),
I4 => s_axi_arburst(1),
I5 => s_axi_arsize_0_sn_1,
O => \GEN_NO_RD_CMD_OPT.GEN_NARROW_EN.curr_narrow_burst_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_NARROW_EN.curr_narrow_burst_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_NO_RD_CMD_OPT.GEN_NARROW_EN.curr_narrow_burst_i_1_n_0\,
Q => curr_narrow_burst,
R => '0'
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(0),
I1 => bram_rddata_a(0),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\,
Q => s_axi_rdata(0),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(10),
I1 => bram_rddata_a(10),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\,
Q => s_axi_rdata(10),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(11),
I1 => bram_rddata_a(11),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\,
Q => s_axi_rdata(11),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(12),
I1 => bram_rddata_a(12),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\,
Q => s_axi_rdata(12),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(13),
I1 => bram_rddata_a(13),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\,
Q => s_axi_rdata(13),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(14),
I1 => bram_rddata_a(14),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\,
Q => s_axi_rdata(14),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(15),
I1 => bram_rddata_a(15),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\,
Q => s_axi_rdata(15),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(16),
I1 => bram_rddata_a(16),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\,
Q => s_axi_rdata(16),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(17),
I1 => bram_rddata_a(17),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\,
Q => s_axi_rdata(17),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(18),
I1 => bram_rddata_a(18),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\,
Q => s_axi_rdata(18),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(19),
I1 => bram_rddata_a(19),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\,
Q => s_axi_rdata(19),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(1),
I1 => bram_rddata_a(1),
I2 => rddata_mux_sel,
O => \p_0_in__0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \p_0_in__0\,
Q => s_axi_rdata(1),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(20),
I1 => bram_rddata_a(20),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\,
Q => s_axi_rdata(20),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(21),
I1 => bram_rddata_a(21),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\,
Q => s_axi_rdata(21),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(22),
I1 => bram_rddata_a(22),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\,
Q => s_axi_rdata(22),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(23),
I1 => bram_rddata_a(23),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\,
Q => s_axi_rdata(23),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(24),
I1 => bram_rddata_a(24),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\,
Q => s_axi_rdata(24),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(25),
I1 => bram_rddata_a(25),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\,
Q => s_axi_rdata(25),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(26),
I1 => bram_rddata_a(26),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\,
Q => s_axi_rdata(26),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(27),
I1 => bram_rddata_a(27),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\,
Q => s_axi_rdata(27),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(28),
I1 => bram_rddata_a(28),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\,
Q => s_axi_rdata(28),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(29),
I1 => bram_rddata_a(29),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\,
Q => s_axi_rdata(29),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(2),
I1 => bram_rddata_a(2),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\,
Q => s_axi_rdata(2),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(30),
I1 => bram_rddata_a(30),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\,
Q => s_axi_rdata(30),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000003B33F00"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\,
I1 => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(2),
I5 => rd_data_sm_cs(3),
O => axi_rdata_en
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(31),
I1 => bram_rddata_a(31),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\,
I1 => s_axi_rready,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
Q => s_axi_rdata(31),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(3),
I1 => bram_rddata_a(3),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\,
Q => s_axi_rdata(3),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(4),
I1 => bram_rddata_a(4),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\,
Q => s_axi_rdata(4),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(5),
I1 => bram_rddata_a(5),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\,
Q => s_axi_rdata(5),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(6),
I1 => bram_rddata_a(6),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\,
Q => s_axi_rdata(6),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(7),
I1 => bram_rddata_a(7),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\,
Q => s_axi_rdata(7),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(8),
I1 => bram_rddata_a(8),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\,
Q => s_axi_rdata(8),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(9),
I1 => bram_rddata_a(9),
I2 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => axi_rdata_en,
D => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\,
Q => s_axi_rdata(9),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAABA"
)
port map (
I0 => rd_skid_buf_ld_reg,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(2),
I3 => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
I4 => rd_data_sm_cs(3),
I5 => rd_data_sm_cs(1),
O => rd_skid_buf_ld
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(0),
Q => rd_skid_buf(0),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(10),
Q => rd_skid_buf(10),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(11),
Q => rd_skid_buf(11),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(12),
Q => rd_skid_buf(12),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(13),
Q => rd_skid_buf(13),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(14),
Q => rd_skid_buf(14),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(15),
Q => rd_skid_buf(15),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(16),
Q => rd_skid_buf(16),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(17),
Q => rd_skid_buf(17),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(18),
Q => rd_skid_buf(18),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(19),
Q => rd_skid_buf(19),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(1),
Q => rd_skid_buf(1),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(20),
Q => rd_skid_buf(20),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(21),
Q => rd_skid_buf(21),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(22),
Q => rd_skid_buf(22),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(23),
Q => rd_skid_buf(23),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(24),
Q => rd_skid_buf(24),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(25),
Q => rd_skid_buf(25),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(26),
Q => rd_skid_buf(26),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(27),
Q => rd_skid_buf(27),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(28),
Q => rd_skid_buf(28),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(29),
Q => rd_skid_buf(29),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(2),
Q => rd_skid_buf(2),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(30),
Q => rd_skid_buf(30),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(31),
Q => rd_skid_buf(31),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(3),
Q => rd_skid_buf(3),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(4),
Q => rd_skid_buf(4),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(5),
Q => rd_skid_buf(5),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(6),
Q => rd_skid_buf(6),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(7),
Q => rd_skid_buf(7),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(8),
Q => rd_skid_buf(8),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_a(9),
Q => rd_skid_buf(9),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D0FF"
)
port map (
I0 => Arb2AR_Active,
I1 => \^ar_active_d1\,
I2 => brst_zero,
I3 => s_axi_aresetn,
O => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_i_3_n_0\,
I1 => s_axi_arlen(7),
I2 => s_axi_arlen(5),
I3 => s_axi_arlen(1),
I4 => s_axi_arlen(4),
I5 => s_axi_arlen(6),
O => axi_rd_burst0
);
\GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi_arlen(3),
I1 => s_axi_arlen(2),
O => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_i_3_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => axi_rd_burst0,
Q => axi_rd_burst,
R => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_i_2_n_0\,
I1 => s_axi_arlen(0),
I2 => s_axi_arlen(3),
I3 => s_axi_arlen(2),
O => axi_rd_burst_two
);
\GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => s_axi_arlen(6),
I1 => s_axi_arlen(4),
I2 => s_axi_arlen(1),
I3 => s_axi_arlen(5),
I4 => s_axi_arlen(7),
O => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => axi_rd_burst_two,
Q => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_reg_n_0\,
R => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^gen_no_rd_cmd_opt.axi_rlast_int_reg_0\,
I1 => s_axi_rready,
I2 => s_axi_aresetn,
O => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFAACFCFC0AAC0C0"
)
port map (
I0 => s_axi_arid(0),
I1 => axi_rid_temp,
I2 => axi_rvalid_set,
I3 => \^ar_active_d1\,
I4 => Arb2AR_Active,
I5 => \^s_axi_rid\(0),
O => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_2_n_0\,
Q => \^s_axi_rid\(0),
R => \GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_int[0]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.GEN_RID_SNG.axi_rid_temp_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => s_axi_arid(0),
Q => axi_rid_temp,
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.GEN_UA_NARROW.I_UA_NARROW\: entity work.design_1_axi_bram_ctrl_0_1_ua_narrow_0
port map (
D(1) => \GEN_NO_RD_CMD_OPT.GEN_UA_NARROW.I_UA_NARROW_n_0\,
D(0) => \GEN_NO_RD_CMD_OPT.GEN_UA_NARROW.I_UA_NARROW_n_1\,
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[0]\ => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_5_n_0\,
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[0]_0\ => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_6_n_0\,
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]\(1 downto 0) => narrow_burst_cnt_ld_reg(1 downto 0),
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]_0\ => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]_0\,
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]_1\ => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int[1]_i_4_n_0\,
Q(0) => narrow_addr_int(0),
s_axi_araddr(1 downto 0) => s_axi_araddr(1 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0)
);
\GEN_NO_RD_CMD_OPT.I_WRAP_BRST\: entity work.design_1_axi_bram_ctrl_0_1_wrap_brst_1
port map (
\ADDR_SNG_PORT.bram_addr_int_reg[10]\ => \ADDR_SNG_PORT.bram_addr_int_reg[10]\,
\ADDR_SNG_PORT.bram_addr_int_reg[11]\ => \ADDR_SNG_PORT.bram_addr_int_reg[11]\,
\ADDR_SNG_PORT.bram_addr_int_reg[11]_0\ => \ADDR_SNG_PORT.bram_addr_int_reg[11]_0\,
\ADDR_SNG_PORT.bram_addr_int_reg[11]_1\ => \ADDR_SNG_PORT.bram_addr_int[11]_i_4_n_0\,
\ADDR_SNG_PORT.bram_addr_int_reg[11]_2\ => \ADDR_SNG_PORT.bram_addr_int_reg[11]_1\,
\ADDR_SNG_PORT.bram_addr_int_reg[19]\(13 downto 0) => \ADDR_SNG_PORT.bram_addr_int_reg[19]\(13 downto 0),
\ADDR_SNG_PORT.bram_addr_int_reg[19]_0\ => \^ar_active_d1\,
\ADDR_SNG_PORT.bram_addr_int_reg[19]_1\ => \ADDR_SNG_PORT.bram_addr_int_reg[19]_0\,
\ADDR_SNG_PORT.bram_addr_int_reg[6]\ => \ADDR_SNG_PORT.bram_addr_int_reg[6]\,
\ADDR_SNG_PORT.bram_addr_int_reg[7]\ => \ADDR_SNG_PORT.bram_addr_int_reg[7]\,
\ADDR_SNG_PORT.bram_addr_int_reg[8]\ => \ADDR_SNG_PORT.bram_addr_int_reg[8]\,
\ADDR_SNG_PORT.bram_addr_int_reg[9]\ => \ADDR_SNG_PORT.bram_addr_int_reg[9]\,
Arb2AR_Active => Arb2AR_Active,
D(13 downto 0) => D(13 downto 0),
E(1 downto 0) => E(1 downto 0),
\FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs_reg[2]\ => \GEN_NO_RD_CMD_OPT.I_WRAP_BRST_n_21\,
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[0]\ => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_reg_n_0\,
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_bram_addr_inc_d1_reg\(2 downto 0) => \GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_bram_addr_inc_d1_reg_0\(2 downto 0),
\GEN_NO_RD_CMD_OPT.GEN_NARROW_EN.curr_narrow_burst_reg\ => \GEN_NO_RD_CMD_OPT.GEN_NARROW_EN.curr_narrow_burst_reg_0\,
Q(3 downto 0) => rd_data_sm_cs(3 downto 0),
SR(0) => \^sr\(0),
ar_active_re => ar_active_re,
axi_rd_burst => axi_rd_burst,
brst_zero => brst_zero,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_narrow_burst => curr_narrow_burst,
curr_wrap_burst_reg => curr_wrap_burst_reg,
end_brst_rd => end_brst_rd,
narrow_bram_addr_inc_d1 => narrow_bram_addr_inc_d1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(16 downto 0) => s_axi_araddr(18 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arsize_0_sp_1 => s_axi_arsize_0_sn_1,
s_axi_rready => s_axi_rready,
\save_init_bram_addr_ld[11]_i_3_0\ => \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\,
\save_init_bram_addr_ld[11]_i_4_0\(2 downto 0) => Q(2 downto 0),
\save_init_bram_addr_ld_reg[11]_0\ => \save_init_bram_addr_ld_reg[11]\,
\save_init_bram_addr_ld_reg[19]_0\(1 downto 0) => narrow_addr_int(1 downto 0)
);
\GEN_NO_RD_CMD_OPT.act_rd_burst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"02000004FFFFFFFF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => \GEN_NO_RD_CMD_OPT.act_rd_burst_i_4_n_0\,
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
I5 => s_axi_aresetn,
O => \GEN_NO_RD_CMD_OPT.act_rd_burst_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.act_rd_burst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0101000100000001"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(1),
I3 => \GEN_NO_RD_CMD_OPT.act_rd_burst_two_reg_0\,
I4 => rd_data_sm_cs(0),
I5 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_2_n_0\,
O => act_rd_burst_set
);
\GEN_NO_RD_CMD_OPT.act_rd_burst_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA3A"
)
port map (
I0 => axi_rd_burst,
I1 => \GEN_NO_RD_CMD_OPT.act_rd_burst_i_6_n_0\,
I2 => Arb2AR_Active,
I3 => \^ar_active_d1\,
O => \GEN_NO_RD_CMD_OPT.act_rd_burst_i_3_n_0\
);
\GEN_NO_RD_CMD_OPT.act_rd_burst_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"777F"
)
port map (
I0 => s_axi_rready,
I1 => \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\,
I2 => act_rd_burst,
I3 => act_rd_burst_two,
O => \GEN_NO_RD_CMD_OPT.act_rd_burst_i_4_n_0\
);
\GEN_NO_RD_CMD_OPT.act_rd_burst_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000020"
)
port map (
I0 => s_axi_arlen_6_sn_1,
I1 => s_axi_arlen(1),
I2 => s_axi_arlen(0),
I3 => s_axi_arlen(3),
I4 => s_axi_arlen(2),
O => \GEN_NO_RD_CMD_OPT.act_rd_burst_i_6_n_0\
);
\GEN_NO_RD_CMD_OPT.act_rd_burst_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_arlen(6),
I1 => s_axi_arlen(4),
I2 => s_axi_arlen(5),
I3 => s_axi_arlen(7),
O => s_axi_arlen_6_sn_1
);
\GEN_NO_RD_CMD_OPT.act_rd_burst_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => act_rd_burst_set,
D => \GEN_NO_RD_CMD_OPT.act_rd_burst_i_3_n_0\,
Q => act_rd_burst,
R => \GEN_NO_RD_CMD_OPT.act_rd_burst_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.act_rd_burst_two_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.act_rd_burst_i_6_n_0\,
I1 => Arb2AR_Active,
I2 => \^ar_active_d1\,
I3 => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_reg_n_0\,
O => \GEN_NO_RD_CMD_OPT.act_rd_burst_two_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.act_rd_burst_two_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => act_rd_burst_set,
D => \GEN_NO_RD_CMD_OPT.act_rd_burst_two_i_1_n_0\,
Q => act_rd_burst_two,
R => \GEN_NO_RD_CMD_OPT.act_rd_burst_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.axi_rlast_int_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D0DF0000"
)
port map (
I0 => s_axi_rready,
I1 => \GEN_NO_RD_CMD_OPT.axi_rlast_int_i_2_n_0\,
I2 => \^gen_no_rd_cmd_opt.axi_rlast_int_reg_0\,
I3 => \GEN_NO_RD_CMD_OPT.axi_rlast_int_i_3_n_0\,
I4 => s_axi_aresetn,
O => \GEN_NO_RD_CMD_OPT.axi_rlast_int_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.axi_rlast_int_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => s_axi_rready,
I1 => \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(2),
O => \GEN_NO_RD_CMD_OPT.axi_rlast_int_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.axi_rlast_int_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF77FFFFFF77F0FF"
)
port map (
I0 => \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\,
I1 => s_axi_rready,
I2 => \^gen_no_rd_cmd_opt.axi_rlast_int_reg_0\,
I3 => rlast_sm_cs(2),
I4 => rlast_sm_cs(0),
I5 => rlast_sm_cs(1),
O => \GEN_NO_RD_CMD_OPT.axi_rlast_int_i_3_n_0\
);
\GEN_NO_RD_CMD_OPT.axi_rlast_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_NO_RD_CMD_OPT.axi_rlast_int_i_1_n_0\,
Q => \^gen_no_rd_cmd_opt.axi_rlast_int_reg_0\,
R => '0'
);
\GEN_NO_RD_CMD_OPT.axi_rvalid_clr_ok_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEEEEE"
)
port map (
I0 => ar_active_re,
I1 => \GEN_NO_RD_CMD_OPT.axi_rvalid_clr_ok_i_2_n_0\,
I2 => \GEN_NO_RD_CMD_OPT.disable_b2b_brst_i_2_n_0\,
I3 => disable_b2b_brst,
I4 => last_bram_addr,
I5 => axi_rvalid_clr_ok,
O => \GEN_NO_RD_CMD_OPT.axi_rvalid_clr_ok_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.axi_rvalid_clr_ok_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(3),
O => \GEN_NO_RD_CMD_OPT.axi_rvalid_clr_ok_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.axi_rvalid_clr_ok_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_NO_RD_CMD_OPT.axi_rvalid_clr_ok_i_1_n_0\,
Q => axi_rvalid_clr_ok,
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.axi_rvalid_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7F0000000000"
)
port map (
I0 => s_axi_rready,
I1 => \^gen_no_rd_cmd_opt.axi_rlast_int_reg_0\,
I2 => axi_rvalid_clr_ok,
I3 => axi_rvalid_set,
I4 => \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\,
I5 => s_axi_aresetn,
O => \GEN_NO_RD_CMD_OPT.axi_rvalid_int_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.axi_rvalid_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_NO_RD_CMD_OPT.axi_rvalid_int_i_1_n_0\,
Q => \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\,
R => '0'
);
\GEN_NO_RD_CMD_OPT.axi_rvalid_set_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(3),
O => axi_rvalid_set_cmb
);
\GEN_NO_RD_CMD_OPT.axi_rvalid_set_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_set_cmb,
Q => axi_rvalid_set,
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.bram_en_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00BBFFFB00BB000B"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.bram_en_int_i_2_n_0\,
I1 => \GEN_NO_RD_CMD_OPT.bram_en_int_i_3_n_0\,
I2 => \GEN_NO_RD_CMD_OPT.bram_en_int_i_4_n_0\,
I3 => rd_data_sm_cs(3),
I4 => \GEN_NO_RD_CMD_OPT.bram_en_int_i_5_n_0\,
I5 => \^bram_en_b_i\,
O => \GEN_NO_RD_CMD_OPT.bram_en_int_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.bram_en_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABABBBAAAAAA"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.bram_en_int_i_6_n_0\,
I1 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_5_n_0\,
I2 => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => rd_data_sm_cs(2),
O => \GEN_NO_RD_CMD_OPT.bram_en_int_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.bram_en_int_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCFFFC7171717D"
)
port map (
I0 => ar_active_re,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(2),
I3 => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_reg_n_0\,
I4 => axi_rd_burst,
I5 => rd_data_sm_cs(1),
O => \GEN_NO_RD_CMD_OPT.bram_en_int_i_3_n_0\
);
\GEN_NO_RD_CMD_OPT.bram_en_int_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0FFFFF00004F43"
)
port map (
I0 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_4_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
I3 => \GEN_NO_RD_CMD_OPT.bram_en_int_i_7_n_0\,
I4 => \GEN_NO_RD_CMD_OPT.bram_en_int_i_6_n_0\,
I5 => rd_data_sm_cs(1),
O => \GEN_NO_RD_CMD_OPT.bram_en_int_i_4_n_0\
);
\GEN_NO_RD_CMD_OPT.bram_en_int_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000007FFF7F00"
)
port map (
I0 => brst_one,
I1 => rd_data_sm_cs(0),
I2 => \GEN_NO_RD_CMD_OPT.bram_en_int_i_7_n_0\,
I3 => rd_data_sm_cs(1),
I4 => ar_active_re,
I5 => \GEN_NO_RD_CMD_OPT.bram_en_int_i_8_n_0\,
O => \GEN_NO_RD_CMD_OPT.bram_en_int_i_5_n_0\
);
\GEN_NO_RD_CMD_OPT.bram_en_int_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888880000000"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(2),
I2 => pend_rd_op,
I3 => s_axi_rready,
I4 => \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\,
I5 => ar_active_re,
O => \GEN_NO_RD_CMD_OPT.bram_en_int_i_6_n_0\
);
\GEN_NO_RD_CMD_OPT.bram_en_int_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"0007"
)
port map (
I0 => s_axi_rready,
I1 => \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\,
I2 => end_brst_rd,
I3 => brst_zero,
O => \GEN_NO_RD_CMD_OPT.bram_en_int_i_7_n_0\
);
\GEN_NO_RD_CMD_OPT.bram_en_int_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
O => \GEN_NO_RD_CMD_OPT.bram_en_int_i_8_n_0\
);
\GEN_NO_RD_CMD_OPT.bram_en_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_NO_RD_CMD_OPT.bram_en_int_i_1_n_0\,
Q => \^bram_en_b_i\,
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.brst_cnt[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FB"
)
port map (
I0 => s_axi_arlen(0),
I1 => Arb2AR_Active,
I2 => \^ar_active_d1\,
I3 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(0),
O => p_0_in(0)
);
\GEN_NO_RD_CMD_OPT.brst_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FB0808FB"
)
port map (
I0 => s_axi_arlen(1),
I1 => Arb2AR_Active,
I2 => \^ar_active_d1\,
I3 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(0),
I4 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(1),
O => p_0_in(1)
);
\GEN_NO_RD_CMD_OPT.brst_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB08FB08FB0808FB"
)
port map (
I0 => s_axi_arlen(2),
I1 => Arb2AR_Active,
I2 => \^ar_active_d1\,
I3 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(2),
I4 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(1),
I5 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(0),
O => p_0_in(2)
);
\GEN_NO_RD_CMD_OPT.brst_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => s_axi_arlen(3),
I1 => ar_active_re,
I2 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(3),
I3 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(2),
I4 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(0),
I5 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(1),
O => p_0_in(3)
);
\GEN_NO_RD_CMD_OPT.brst_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"08FBFB08"
)
port map (
I0 => s_axi_arlen(4),
I1 => Arb2AR_Active,
I2 => \^ar_active_d1\,
I3 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(4),
I4 => \GEN_NO_RD_CMD_OPT.brst_cnt[5]_i_2_n_0\,
O => p_0_in(4)
);
\GEN_NO_RD_CMD_OPT.brst_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB0808FBFB08FB08"
)
port map (
I0 => s_axi_arlen(5),
I1 => Arb2AR_Active,
I2 => \^ar_active_d1\,
I3 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(5),
I4 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(4),
I5 => \GEN_NO_RD_CMD_OPT.brst_cnt[5]_i_2_n_0\,
O => p_0_in(5)
);
\GEN_NO_RD_CMD_OPT.brst_cnt[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(2),
I1 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(0),
I2 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(1),
I3 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(3),
O => \GEN_NO_RD_CMD_OPT.brst_cnt[5]_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.brst_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBB8BB88888B88"
)
port map (
I0 => s_axi_arlen(6),
I1 => ar_active_re,
I2 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(3),
I3 => \GEN_NO_RD_CMD_OPT.brst_cnt[6]_i_2_n_0\,
I4 => \GEN_NO_RD_CMD_OPT.brst_cnt[6]_i_3_n_0\,
I5 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(6),
O => p_0_in(6)
);
\GEN_NO_RD_CMD_OPT.brst_cnt[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(1),
I1 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(0),
I2 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(2),
O => \GEN_NO_RD_CMD_OPT.brst_cnt[6]_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.brst_cnt[6]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(5),
I1 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(4),
O => \GEN_NO_RD_CMD_OPT.brst_cnt[6]_i_3_n_0\
);
\GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^ar_active_d1\,
I1 => Arb2AR_Active,
I2 => \GEN_NO_RD_CMD_OPT.I_WRAP_BRST_n_21\,
O => \GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"08FBFB08"
)
port map (
I0 => s_axi_arlen(7),
I1 => Arb2AR_Active,
I2 => \^ar_active_d1\,
I3 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(7),
I4 => \GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_3_n_0\,
O => p_0_in(7)
);
\GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(5),
I1 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(4),
I2 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(6),
I3 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(3),
I4 => \GEN_NO_RD_CMD_OPT.brst_cnt[6]_i_2_n_0\,
O => \GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_3_n_0\
);
\GEN_NO_RD_CMD_OPT.brst_cnt_max_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_reg_n_0\,
Q => brst_cnt_max_d1,
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.brst_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_1_n_0\,
D => p_0_in(0),
Q => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(0),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.brst_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_1_n_0\,
D => p_0_in(1),
Q => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(1),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.brst_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_1_n_0\,
D => p_0_in(2),
Q => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(2),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.brst_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_1_n_0\,
D => p_0_in(3),
Q => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(3),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.brst_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_1_n_0\,
D => p_0_in(4),
Q => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(4),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.brst_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_1_n_0\,
D => p_0_in(5),
Q => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(5),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.brst_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_1_n_0\,
D => p_0_in(6),
Q => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(6),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.brst_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_NO_RD_CMD_OPT.brst_cnt[7]_i_1_n_0\,
D => p_0_in(7),
Q => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(7),
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.brst_one_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000044444440"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.last_bram_addr_i_5_n_0\,
I1 => s_axi_aresetn,
I2 => brst_one,
I3 => \GEN_NO_RD_CMD_OPT.brst_one_i_2_n_0\,
I4 => \GEN_NO_RD_CMD_OPT.brst_one_i_3_n_0\,
I5 => \GEN_NO_RD_CMD_OPT.brst_one_reg_0\,
O => \GEN_NO_RD_CMD_OPT.brst_one_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.brst_one_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => s_axi_arlen(2),
I1 => s_axi_arlen(3),
I2 => s_axi_arlen(0),
I3 => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_i_2_n_0\,
I4 => \^ar_active_d1\,
I5 => Arb2AR_Active,
O => \GEN_NO_RD_CMD_OPT.brst_one_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.brst_one_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000100000"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(2),
I1 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(7),
I2 => \GEN_NO_RD_CMD_OPT.last_bram_addr_i_6_n_0\,
I3 => \GEN_NO_RD_CMD_OPT.I_WRAP_BRST_n_21\,
I4 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(1),
I5 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(0),
O => \GEN_NO_RD_CMD_OPT.brst_one_i_3_n_0\
);
\GEN_NO_RD_CMD_OPT.brst_one_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_NO_RD_CMD_OPT.brst_one_i_1_n_0\,
Q => brst_one,
R => '0'
);
\GEN_NO_RD_CMD_OPT.brst_zero_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A800"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.act_rd_burst_two_reg_0\,
I1 => \GEN_NO_RD_CMD_OPT.last_bram_addr_i_5_n_0\,
I2 => brst_zero,
I3 => s_axi_aresetn,
O => \GEN_NO_RD_CMD_OPT.brst_zero_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.brst_zero_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_NO_RD_CMD_OPT.brst_zero_i_1_n_0\,
Q => brst_zero,
R => '0'
);
\GEN_NO_RD_CMD_OPT.curr_fixed_burst_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_arburst(0),
I1 => s_axi_arburst(1),
O => curr_fixed_burst
);
\GEN_NO_RD_CMD_OPT.curr_fixed_burst_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => curr_fixed_burst,
Q => curr_fixed_burst_reg,
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.curr_wrap_burst_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_arburst(1),
I1 => s_axi_arburst(0),
O => curr_wrap_burst
);
\GEN_NO_RD_CMD_OPT.curr_wrap_burst_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ar_active_re,
D => curr_wrap_burst,
Q => curr_wrap_burst_reg,
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.disable_b2b_brst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABFAAAAAABBAAAA"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.disable_b2b_brst_i_2_n_0\,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst,
I5 => rd_data_sm_cs(2),
O => disable_b2b_brst_cmb
);
\GEN_NO_RD_CMD_OPT.disable_b2b_brst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FBFBFBBB"
)
port map (
I0 => disable_b2b_brst,
I1 => rd_data_sm_cs(1),
I2 => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
I3 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[3]_i_5_n_0\,
I4 => brst_one,
I5 => \GEN_NO_RD_CMD_OPT.disable_b2b_brst_i_3_n_0\,
O => \GEN_NO_RD_CMD_OPT.disable_b2b_brst_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.disable_b2b_brst_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF04FF"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_reg_n_0\,
I1 => axi_rd_burst,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(3),
I5 => rd_data_sm_cs(2),
O => \GEN_NO_RD_CMD_OPT.disable_b2b_brst_i_3_n_0\
);
\GEN_NO_RD_CMD_OPT.disable_b2b_brst_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => disable_b2b_brst_cmb,
Q => disable_b2b_brst,
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.end_brst_rd_clr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEEEF11000000"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(3),
I2 => ar_active_re,
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => end_brst_rd_clr,
O => \GEN_NO_RD_CMD_OPT.end_brst_rd_clr_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.end_brst_rd_clr_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_NO_RD_CMD_OPT.end_brst_rd_clr_i_1_n_0\,
Q => end_brst_rd_clr,
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.end_brst_rd_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"55300000"
)
port map (
I0 => end_brst_rd_clr,
I1 => brst_cnt_max_d1,
I2 => \GEN_NO_RD_CMD_OPT.GEN_BRST_MAX_W_NARROW.brst_cnt_max_reg_n_0\,
I3 => end_brst_rd,
I4 => s_axi_aresetn,
O => \GEN_NO_RD_CMD_OPT.end_brst_rd_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.end_brst_rd_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_NO_RD_CMD_OPT.end_brst_rd_i_1_n_0\,
Q => end_brst_rd,
R => '0'
);
\GEN_NO_RD_CMD_OPT.last_bram_addr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF2F220000"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.last_bram_addr_i_2_n_0\,
I1 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_2_n_0\,
I2 => \GEN_NO_RD_CMD_OPT.last_bram_addr_i_3_n_0\,
I3 => \GEN_NO_RD_CMD_OPT.act_rd_burst_two_reg_0\,
I4 => \GEN_NO_RD_CMD_OPT.last_bram_addr_i_4_n_0\,
I5 => \GEN_NO_RD_CMD_OPT.last_bram_addr_i_5_n_0\,
O => last_bram_addr0
);
\GEN_NO_RD_CMD_OPT.last_bram_addr_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => s_axi_rready,
I3 => \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\,
O => \GEN_NO_RD_CMD_OPT.last_bram_addr_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.last_bram_addr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0F0F0FFFFFDFF"
)
port map (
I0 => pend_rd_op,
I1 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_2_n_0\,
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(2),
I4 => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
I5 => ar_active_re,
O => \GEN_NO_RD_CMD_OPT.last_bram_addr_i_3_n_0\
);
\GEN_NO_RD_CMD_OPT.last_bram_addr_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"81"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
O => \GEN_NO_RD_CMD_OPT.last_bram_addr_i_4_n_0\
);
\GEN_NO_RD_CMD_OPT.last_bram_addr_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000040000"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(1),
I1 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(0),
I2 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(2),
I3 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(7),
I4 => \GEN_NO_RD_CMD_OPT.last_bram_addr_i_6_n_0\,
I5 => \GEN_NO_RD_CMD_OPT.I_WRAP_BRST_n_21\,
O => \GEN_NO_RD_CMD_OPT.last_bram_addr_i_5_n_0\
);
\GEN_NO_RD_CMD_OPT.last_bram_addr_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(3),
I1 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(6),
I2 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(4),
I3 => \GEN_NO_RD_CMD_OPT.brst_cnt_reg\(5),
O => \GEN_NO_RD_CMD_OPT.last_bram_addr_i_6_n_0\
);
\GEN_NO_RD_CMD_OPT.last_bram_addr_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => last_bram_addr0,
Q => last_bram_addr,
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.pend_rd_op_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D000FFFFD0000000"
)
port map (
I0 => \FSM_sequential_GEN_NO_RD_CMD_OPT.rd_data_sm_cs[0]_i_2_n_0\,
I1 => rd_data_sm_cs(2),
I2 => \GEN_NO_RD_CMD_OPT.pend_rd_op_i_2_n_0\,
I3 => ar_active_re,
I4 => \GEN_NO_RD_CMD_OPT.pend_rd_op_reg_i_3_n_0\,
I5 => pend_rd_op,
O => \GEN_NO_RD_CMD_OPT.pend_rd_op_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.pend_rd_op_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
O => \GEN_NO_RD_CMD_OPT.pend_rd_op_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.pend_rd_op_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1010101010000000"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => \^gen_no_rd_cmd_opt.axi_rlast_int_reg_0\,
I4 => pend_rd_op,
I5 => ar_active_re,
O => \GEN_NO_RD_CMD_OPT.pend_rd_op_i_4_n_0\
);
\GEN_NO_RD_CMD_OPT.pend_rd_op_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"000022000000000F"
)
port map (
I0 => pend_rd_op,
I1 => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
I2 => \GEN_NO_RD_CMD_OPT.pend_rd_op_i_6_n_0\,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(3),
I5 => rd_data_sm_cs(2),
O => \GEN_NO_RD_CMD_OPT.pend_rd_op_i_5_n_0\
);
\GEN_NO_RD_CMD_OPT.pend_rd_op_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"0F0F0F0D"
)
port map (
I0 => Arb2AR_Active,
I1 => \^ar_active_d1\,
I2 => pend_rd_op,
I3 => axi_rd_burst,
I4 => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_reg_n_0\,
O => \GEN_NO_RD_CMD_OPT.pend_rd_op_i_6_n_0\
);
\GEN_NO_RD_CMD_OPT.pend_rd_op_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_NO_RD_CMD_OPT.pend_rd_op_i_1_n_0\,
Q => pend_rd_op,
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.pend_rd_op_reg_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \GEN_NO_RD_CMD_OPT.pend_rd_op_i_4_n_0\,
I1 => \GEN_NO_RD_CMD_OPT.pend_rd_op_i_5_n_0\,
O => \GEN_NO_RD_CMD_OPT.pend_rd_op_reg_i_3_n_0\,
S => rd_data_sm_cs(0)
);
\GEN_NO_RD_CMD_OPT.rd_skid_buf_ld_reg_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000080F0F00"
)
port map (
I0 => s_axi_rready,
I1 => \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\,
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => rd_data_sm_cs(2),
O => rd_skid_buf_ld_cmb
);
\GEN_NO_RD_CMD_OPT.rd_skid_buf_ld_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rd_skid_buf_ld_cmb,
Q => rd_skid_buf_ld_reg,
R => \^sr\(0)
);
\GEN_NO_RD_CMD_OPT.rddata_mux_sel_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FD01"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.rddata_mux_sel_i_2_n_0\,
I1 => rd_data_sm_cs(3),
I2 => \GEN_NO_RD_CMD_OPT.rddata_mux_sel_i_3_n_0\,
I3 => rddata_mux_sel,
O => \GEN_NO_RD_CMD_OPT.rddata_mux_sel_i_1_n_0\
);
\GEN_NO_RD_CMD_OPT.rddata_mux_sel_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF55FFFC00FFFF"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => act_rd_burst,
I2 => act_rd_burst_two,
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => \GEN_NO_RD_CMD_OPT.GEN_RDATA_NO_ECC.GEN_RDATA_NO_RL_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
O => \GEN_NO_RD_CMD_OPT.rddata_mux_sel_i_2_n_0\
);
\GEN_NO_RD_CMD_OPT.rddata_mux_sel_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCC00000FFF7777"
)
port map (
I0 => \GEN_NO_RD_CMD_OPT.GEN_RD_BURST_NORL.axi_rd_burst_two_reg_n_0\,
I1 => rd_data_sm_cs(1),
I2 => \^gen_no_rd_cmd_opt.axi_rvalid_int_reg_0\,
I3 => s_axi_rready,
I4 => rd_data_sm_cs(2),
I5 => rd_data_sm_cs(0),
O => \GEN_NO_RD_CMD_OPT.rddata_mux_sel_i_3_n_0\
);
\GEN_NO_RD_CMD_OPT.rddata_mux_sel_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_NO_RD_CMD_OPT.rddata_mux_sel_i_1_n_0\,
Q => rddata_mux_sel,
R => \^sr\(0)
);
axi_awready_int_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_rready,
I1 => \^gen_no_rd_cmd_opt.axi_rlast_int_reg_0\,
O => s_axi_rready_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_bram_ctrl_0_1_wr_chnl is
port (
aw_active_d1 : out STD_LOGIC;
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
axi_bvalid_int_reg_0 : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[1]_0\ : out STD_LOGIC;
\GEN_NARROW_CNT.narrow_bram_addr_inc_d1_reg_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
aw_active_d1_reg_0 : out STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[3]\ : out STD_LOGIC;
s_axi_awsize_0_sp_1 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\save_init_bram_addr_ld_reg[19]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awlen_5_sp_1 : out STD_LOGIC;
s_axi_awlen_0_sp_1 : out STD_LOGIC;
\bvalid_cnt_reg[2]_0\ : out STD_LOGIC;
s_axi_awvalid_0 : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
\GEN_WR_NO_ECC.bram_we_int_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
Arb2AW_Active : in STD_LOGIC;
aw_active_re : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
ar_active_re : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 19 downto 0 );
curr_narrow_burst_en : in STD_LOGIC;
\GEN_NARROW_CNT.narrow_addr_int_reg[1]_0\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int[8]_i_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\ADDR_SNG_PORT.bram_addr_int_reg[5]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[2]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[3]_0\ : in STD_LOGIC;
Arb2AR_Active : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[5]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\ADDR_SNG_PORT.bram_addr_int_reg[4]\ : in STD_LOGIC;
\ADDR_SNG_PORT.bram_addr_int_reg[5]_1\ : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
last_arb_won_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
BRAM_En_B_i : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end design_1_axi_bram_ctrl_0_1_wr_chnl;
architecture STRUCTURE of design_1_axi_bram_ctrl_0_1_wr_chnl is
signal \ADDR_SNG_PORT.bram_addr_int[19]_i_7_n_0\ : STD_LOGIC;
signal AW2Arb_BVALID_Cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
signal BID_FIFO_n_1 : STD_LOGIC;
signal BID_FIFO_n_2 : STD_LOGIC;
signal BRAM_En_A_i : STD_LOGIC;
signal \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[2]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[0]\ : STD_LOGIC;
signal \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[1]\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_10_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_11_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_12_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_13_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_14_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_15_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_16_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_17_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_18_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_19_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_20_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_21_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_22_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_23_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_24_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_25_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_26_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_27_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_3_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_4_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_5_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_8_n_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT.narrow_addr_int[1]_i_9_n_0\ : STD_LOGIC;
signal \^gen_narrow_cnt.narrow_bram_addr_inc_d1_reg_0\ : STD_LOGIC;
signal \GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \GEN_NARROW_EN.curr_narrow_burst_i_1_n_0\ : STD_LOGIC;
signal \GEN_UA_NARROW.I_UA_NARROW_n_0\ : STD_LOGIC;
signal \GEN_UA_NARROW.I_UA_NARROW_n_1\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.bram_en_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^aw_active_d1\ : STD_LOGIC;
signal axi_bvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_2_n_0 : STD_LOGIC;
signal \^axi_bvalid_int_reg_0\ : STD_LOGIC;
signal axi_wdata_full_cmb : STD_LOGIC;
signal axi_wdata_full_reg : STD_LOGIC;
signal axi_wlast_d1 : STD_LOGIC;
signal axi_wr_burst : STD_LOGIC;
signal axi_wr_burst_i_1_n_0 : STD_LOGIC;
signal axi_wr_burst_i_2_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_1_n_0 : STD_LOGIC;
signal bid_gets_fifo_load : STD_LOGIC;
signal bid_gets_fifo_load_d1 : STD_LOGIC;
signal \bvalid_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[2]_i_2_n_0\ : STD_LOGIC;
signal bvalid_cnt_inc : STD_LOGIC;
signal clr_bram_we : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_narrow_burst : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal narrow_addr_int : STD_LOGIC_VECTOR ( 1 downto 0 );
signal narrow_bram_addr_inc : STD_LOGIC;
signal narrow_bram_addr_inc_d1 : STD_LOGIC;
signal narrow_burst_cnt_ld_reg : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_8_in : STD_LOGIC;
signal s_axi_awlen_0_sn_1 : STD_LOGIC;
signal s_axi_awlen_5_sn_1 : STD_LOGIC;
signal s_axi_awsize_0_sn_1 : STD_LOGIC;
signal \^s_axi_bid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[19]_i_7\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[1]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_2\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_3\ : label is "soft_lutpair64";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[0]\ : label is "idle:001,brst_wr_data:010,sng_wr_data:100";
attribute FSM_ENCODED_STATES of \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[1]\ : label is "idle:001,brst_wr_data:010,sng_wr_data:100";
attribute FSM_ENCODED_STATES of \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[2]\ : label is "idle:001,brst_wr_data:010,sng_wr_data:100";
attribute SOFT_HLUTNM of \GEN_NARROW_CNT.narrow_addr_int[1]_i_10\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \GEN_NARROW_CNT.narrow_addr_int[1]_i_13\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \GEN_NARROW_CNT.narrow_addr_int[1]_i_15\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \GEN_NARROW_CNT.narrow_addr_int[1]_i_17\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \GEN_NARROW_CNT.narrow_addr_int[1]_i_19\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \GEN_NARROW_CNT.narrow_addr_int[1]_i_20\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \GEN_NARROW_CNT.narrow_addr_int[1]_i_21\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \GEN_NARROW_CNT.narrow_addr_int[1]_i_23\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \GEN_NARROW_CNT.narrow_addr_int[1]_i_24\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \GEN_NARROW_CNT.narrow_addr_int[1]_i_25\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \GEN_NARROW_CNT.narrow_addr_int[1]_i_27\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \GEN_NARROW_CNT.narrow_addr_int[1]_i_4\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \GEN_NARROW_CNT.narrow_bram_addr_inc_d1_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg[0]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.bram_en_int_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of axi_bvalid_int_i_1 : label is "soft_lutpair72";
attribute SOFT_HLUTNM of axi_bvalid_int_i_2 : label is "soft_lutpair61";
attribute SOFT_HLUTNM of axi_wr_burst_i_2 : label is "soft_lutpair68";
attribute SOFT_HLUTNM of axi_wready_int_mod_i_1 : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \bvalid_cnt[0]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_1 : label is "soft_lutpair73";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_1 : label is "soft_lutpair73";
begin
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[2]_0\(0) <= \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[2]_0\(0);
\GEN_NARROW_CNT.narrow_bram_addr_inc_d1_reg_0\ <= \^gen_narrow_cnt.narrow_bram_addr_inc_d1_reg_0\;
Q(0) <= \^q\(0);
aw_active_d1 <= \^aw_active_d1\;
axi_bvalid_int_reg_0 <= \^axi_bvalid_int_reg_0\;
s_axi_awlen_0_sp_1 <= s_axi_awlen_0_sn_1;
s_axi_awlen_5_sp_1 <= s_axi_awlen_5_sn_1;
s_axi_awsize_0_sp_1 <= s_axi_awsize_0_sn_1;
s_axi_bid(0) <= \^s_axi_bid\(0);
s_axi_wready <= \^s_axi_wready\;
\ADDR_SNG_PORT.bram_addr_int[19]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000100FF"
)
port map (
I0 => narrow_bram_addr_inc_d1,
I1 => narrow_addr_int(0),
I2 => narrow_addr_int(1),
I3 => \ADDR_SNG_PORT.bram_addr_int[19]_i_7_n_0\,
I4 => curr_narrow_burst,
I5 => curr_fixed_burst_reg,
O => \^gen_narrow_cnt.narrow_bram_addr_inc_d1_reg_0\
);
\ADDR_SNG_PORT.bram_addr_int[19]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi_wvalid,
I1 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[1]\,
O => \ADDR_SNG_PORT.bram_addr_int[19]_i_7_n_0\
);
BID_FIFO: entity work.design_1_axi_bram_ctrl_0_1_SRL_FIFO
port map (
Arb2AW_Active => Arb2AW_Active,
Data_Exists_DFF_0 => \^aw_active_d1\,
Data_Exists_DFF_1 => \^axi_bvalid_int_reg_0\,
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[1]\ => BID_FIFO_n_1,
Q(2 downto 0) => AW2Arb_BVALID_Cnt(2 downto 0),
SR(0) => SR(0),
aw_active_re => aw_active_re,
\axi_bid_int_reg[0]\ => BID_FIFO_n_2,
axi_wdata_full_reg => axi_wdata_full_reg,
axi_wr_burst => axi_wr_burst,
bid_gets_fifo_load => bid_gets_fifo_load,
bid_gets_fifo_load_d1 => bid_gets_fifo_load_d1,
bid_gets_fifo_load_d1_reg => axi_bvalid_int_i_2_n_0,
bid_gets_fifo_load_d1_reg_0(1) => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[1]\,
bid_gets_fifo_load_d1_reg_0(0) => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[0]\,
s_axi_aclk => s_axi_aclk,
s_axi_awid(0) => s_axi_awid(0),
s_axi_bid(0) => \^s_axi_bid\(0),
s_axi_bready => s_axi_bready,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid
);
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A202"
)
port map (
I0 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[0]\,
I1 => s_axi_wlast,
I2 => axi_wdata_full_reg,
I3 => axi_wr_burst,
O => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[1]_i_1_n_0\
);
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFEAAA"
)
port map (
I0 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_3_n_0\,
I1 => s_axi_wlast,
I2 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[1]\,
I3 => s_axi_wvalid,
I4 => \^q\(0),
O => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_1_n_0\
);
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFBAAAAA"
)
port map (
I0 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[1]\,
I1 => axi_wr_burst,
I2 => axi_wdata_full_reg,
I3 => s_axi_wlast,
I4 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[0]\,
O => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_2_n_0\
);
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[0]\,
I1 => Arb2AW_Active,
I2 => axi_wdata_full_reg,
I3 => s_axi_wvalid,
O => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_3_n_0\
);
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_1_n_0\,
D => \^q\(0),
Q => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[0]\,
S => SR(0)
);
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_1_n_0\,
D => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[1]_i_1_n_0\,
Q => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[1]\,
R => SR(0)
);
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_1_n_0\,
D => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_2_n_0\,
Q => \^q\(0),
R => SR(0)
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"80FF"
)
port map (
I0 => curr_narrow_burst,
I1 => s_axi_wvalid,
I2 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[1]\,
I3 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_3_n_0\,
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_1_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"332E002E"
)
port map (
I0 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_19_n_0\,
I1 => s_axi_awsize(1),
I2 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_20_n_0\,
I3 => s_axi_awsize(2),
I4 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_21_n_0\,
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_10_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFFFAFFFCFCCAF0F"
)
port map (
I0 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_19_n_0\,
I1 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_21_n_0\,
I2 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_20_n_0\,
I3 => s_axi_awsize(2),
I4 => s_axi_awsize(1),
I5 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_22_n_0\,
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_11_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"5500FC005500FCFC"
)
port map (
I0 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_23_n_0\,
I1 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_24_n_0\,
I2 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_25_n_0\,
I3 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_26_n_0\,
I4 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_17_n_0\,
I5 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_27_n_0\,
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_12_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(2),
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_13_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FA00CC00FA00"
)
port map (
I0 => s_axi_awlen(2),
I1 => s_axi_awlen(3),
I2 => s_axi_awlen(6),
I3 => s_axi_awvalid,
I4 => s_axi_awsize(0),
I5 => s_axi_awlen(7),
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_14_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => s_axi_awlen(3),
I1 => s_axi_awvalid,
I2 => s_axi_awsize(0),
I3 => s_axi_awsize(1),
I4 => s_axi_awsize(2),
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_15_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A8080000"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_awlen(5),
I2 => s_axi_awsize(0),
I3 => s_axi_awlen(4),
I4 => s_axi_awsize(1),
I5 => s_axi_awsize(2),
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_16_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => s_axi_awsize(0),
I1 => s_axi_awsize(1),
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_17_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF05FF33FF05FF"
)
port map (
I0 => s_axi_awlen(0),
I1 => s_axi_awlen(1),
I2 => s_axi_awlen(4),
I3 => s_axi_awvalid,
I4 => s_axi_awsize(0),
I5 => s_axi_awlen(5),
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_18_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"B800"
)
port map (
I0 => s_axi_awlen(4),
I1 => s_axi_awsize(0),
I2 => s_axi_awlen(5),
I3 => s_axi_awvalid,
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_19_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_20\: unisim.vcomponents.LUT4
generic map(
INIT => X"47FF"
)
port map (
I0 => s_axi_awlen(2),
I1 => s_axi_awsize(0),
I2 => s_axi_awlen(3),
I3 => s_axi_awvalid,
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_20_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_21\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => s_axi_awlen(0),
I1 => s_axi_awsize(0),
I2 => s_axi_awvalid,
I3 => s_axi_awlen(1),
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_21_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_22\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => s_axi_awlen(6),
I1 => s_axi_awsize(0),
I2 => s_axi_awvalid,
I3 => s_axi_awlen(7),
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_22_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_23\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => s_axi_awlen(3),
I1 => s_axi_awsize(0),
I2 => s_axi_awvalid,
I3 => s_axi_awlen(2),
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_23_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_24\: unisim.vcomponents.LUT4
generic map(
INIT => X"47FF"
)
port map (
I0 => s_axi_awlen(1),
I1 => s_axi_awsize(0),
I2 => s_axi_awlen(0),
I3 => s_axi_awvalid,
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_24_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_25\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(2),
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_25_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF00003F7700"
)
port map (
I0 => s_axi_awlen(7),
I1 => s_axi_awvalid,
I2 => s_axi_awlen(6),
I3 => s_axi_awsize(0),
I4 => s_axi_awsize(1),
I5 => s_axi_awsize(2),
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_26_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => s_axi_awlen(5),
I1 => s_axi_awsize(0),
I2 => s_axi_awvalid,
I3 => s_axi_awlen(4),
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_27_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000DDDDDFDD"
)
port map (
I0 => Arb2AW_Active,
I1 => \^aw_active_d1\,
I2 => s_axi_awsize(0),
I3 => s_axi_awsize(1),
I4 => s_axi_awsize(2),
I5 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_8_n_0\,
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_3_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => narrow_addr_int(0),
I1 => narrow_addr_int(1),
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_4_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888A88888888"
)
port map (
I0 => s_axi_awburst(1),
I1 => s_axi_awburst(0),
I2 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_9_n_0\,
I3 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_10_n_0\,
I4 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_11_n_0\,
I5 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_12_n_0\,
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_5_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => narrow_bram_addr_inc_d1,
I1 => narrow_addr_int(0),
I2 => narrow_addr_int(1),
I3 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[1]\,
I4 => s_axi_wvalid,
I5 => curr_narrow_burst,
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_8_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int[1]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0FFF8FFFFFFF8"
)
port map (
I0 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_13_n_0\,
I1 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_14_n_0\,
I2 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_15_n_0\,
I3 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_16_n_0\,
I4 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_17_n_0\,
I5 => \GEN_NARROW_CNT.narrow_addr_int[1]_i_18_n_0\,
O => \GEN_NARROW_CNT.narrow_addr_int[1]_i_9_n_0\
);
\GEN_NARROW_CNT.narrow_addr_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_NARROW_CNT.narrow_addr_int[1]_i_1_n_0\,
D => \GEN_UA_NARROW.I_UA_NARROW_n_1\,
Q => narrow_addr_int(0),
R => SR(0)
);
\GEN_NARROW_CNT.narrow_addr_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_NARROW_CNT.narrow_addr_int[1]_i_1_n_0\,
D => \GEN_UA_NARROW.I_UA_NARROW_n_0\,
Q => narrow_addr_int(1),
R => SR(0)
);
\GEN_NARROW_CNT.narrow_bram_addr_inc_d1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => narrow_addr_int(0),
I1 => narrow_addr_int(1),
I2 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[1]\,
I3 => s_axi_wvalid,
I4 => curr_narrow_burst,
O => narrow_bram_addr_inc
);
\GEN_NARROW_CNT.narrow_bram_addr_inc_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => narrow_bram_addr_inc,
Q => narrow_bram_addr_inc_d1,
R => SR(0)
);
\GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF1F0010"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(2),
I2 => Arb2AW_Active,
I3 => \^aw_active_d1\,
I4 => \GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg_n_0_[0]\,
O => narrow_burst_cnt_ld_reg(0)
);
\GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF01FF00000100"
)
port map (
I0 => s_axi_awsize(1),
I1 => s_axi_awsize(2),
I2 => s_axi_awsize(0),
I3 => Arb2AW_Active,
I4 => \^aw_active_d1\,
I5 => \GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg_n_0_[1]\,
O => narrow_burst_cnt_ld_reg(1)
);
\GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => narrow_burst_cnt_ld_reg(0),
Q => \GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg_n_0_[0]\,
R => SR(0)
);
\GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => narrow_burst_cnt_ld_reg(1),
Q => \GEN_NARROW_CNT_LD.narrow_burst_cnt_ld_reg_reg_n_0_[1]\,
R => SR(0)
);
\GEN_NARROW_EN.axi_wlast_d1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_wvalid,
I2 => s_axi_wlast,
O => p_8_in
);
\GEN_NARROW_EN.axi_wlast_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_8_in,
Q => axi_wlast_d1,
R => SR(0)
);
\GEN_NARROW_EN.curr_narrow_burst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0FBB0F0000000000"
)
port map (
I0 => axi_wlast_d1,
I1 => p_8_in,
I2 => s_axi_awsize_0_sn_1,
I3 => curr_narrow_burst_en,
I4 => curr_narrow_burst,
I5 => s_axi_aresetn,
O => \GEN_NARROW_EN.curr_narrow_burst_i_1_n_0\
);
\GEN_NARROW_EN.curr_narrow_burst_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0F0F0E0"
)
port map (
I0 => s_axi_awlen(5),
I1 => s_axi_awlen(4),
I2 => s_axi_awvalid,
I3 => s_axi_awlen(6),
I4 => s_axi_awlen(7),
O => s_axi_awlen_5_sn_1
);
\GEN_NARROW_EN.curr_narrow_burst_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0F0F0E0"
)
port map (
I0 => s_axi_awlen(0),
I1 => s_axi_awlen(3),
I2 => s_axi_awvalid,
I3 => s_axi_awlen(1),
I4 => s_axi_awlen(2),
O => s_axi_awlen_0_sn_1
);
\GEN_NARROW_EN.curr_narrow_burst_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_NARROW_EN.curr_narrow_burst_i_1_n_0\,
Q => curr_narrow_burst,
R => '0'
);
\GEN_UA_NARROW.I_UA_NARROW\: entity work.design_1_axi_bram_ctrl_0_1_ua_narrow
port map (
D(1) => \GEN_UA_NARROW.I_UA_NARROW_n_0\,
D(0) => \GEN_UA_NARROW.I_UA_NARROW_n_1\,
\GEN_NARROW_CNT.narrow_addr_int_reg[0]\ => \GEN_NARROW_CNT.narrow_addr_int[1]_i_3_n_0\,
\GEN_NARROW_CNT.narrow_addr_int_reg[0]_0\ => \GEN_NARROW_CNT.narrow_addr_int[1]_i_5_n_0\,
\GEN_NARROW_CNT.narrow_addr_int_reg[1]\(1 downto 0) => narrow_burst_cnt_ld_reg(1 downto 0),
\GEN_NARROW_CNT.narrow_addr_int_reg[1]_0\ => \GEN_NARROW_CNT.narrow_addr_int_reg[1]_0\,
\GEN_NARROW_CNT.narrow_addr_int_reg[1]_1\ => \GEN_NARROW_CNT.narrow_addr_int[1]_i_4_n_0\,
Q(0) => narrow_addr_int(0),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(1 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0)
);
\GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.axi_wdata_full_reg_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF020F222F020"
)
port map (
I0 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[0]\,
I1 => Arb2AW_Active,
I2 => axi_wdata_full_reg,
I3 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[1]\,
I4 => s_axi_wvalid,
I5 => \^q\(0),
O => axi_wdata_full_cmb
);
\GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.axi_wdata_full_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wdata_full_cmb,
Q => axi_wdata_full_reg,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.bram_en_int_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFC08080"
)
port map (
I0 => axi_wdata_full_reg,
I1 => Arb2AW_Active,
I2 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[0]\,
I3 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[1]\,
I4 => s_axi_wvalid,
O => \GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.bram_en_int_i_1_n_0\
);
\GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.bram_en_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.bram_en_int_i_1_n_0\,
Q => BRAM_En_A_i,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.clr_bram_we_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => BID_FIFO_n_1,
O => bvalid_cnt_inc
);
\GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.clr_bram_we_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bvalid_cnt_inc,
Q => clr_bram_we,
R => SR(0)
);
\GEN_WRDATA[0].bram_wrdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(0),
Q => bram_wrdata_a(0),
R => '0'
);
\GEN_WRDATA[10].bram_wrdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(10),
Q => bram_wrdata_a(10),
R => '0'
);
\GEN_WRDATA[11].bram_wrdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(11),
Q => bram_wrdata_a(11),
R => '0'
);
\GEN_WRDATA[12].bram_wrdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(12),
Q => bram_wrdata_a(12),
R => '0'
);
\GEN_WRDATA[13].bram_wrdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(13),
Q => bram_wrdata_a(13),
R => '0'
);
\GEN_WRDATA[14].bram_wrdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(14),
Q => bram_wrdata_a(14),
R => '0'
);
\GEN_WRDATA[15].bram_wrdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(15),
Q => bram_wrdata_a(15),
R => '0'
);
\GEN_WRDATA[16].bram_wrdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(16),
Q => bram_wrdata_a(16),
R => '0'
);
\GEN_WRDATA[17].bram_wrdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(17),
Q => bram_wrdata_a(17),
R => '0'
);
\GEN_WRDATA[18].bram_wrdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(18),
Q => bram_wrdata_a(18),
R => '0'
);
\GEN_WRDATA[19].bram_wrdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(19),
Q => bram_wrdata_a(19),
R => '0'
);
\GEN_WRDATA[1].bram_wrdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(1),
Q => bram_wrdata_a(1),
R => '0'
);
\GEN_WRDATA[20].bram_wrdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(20),
Q => bram_wrdata_a(20),
R => '0'
);
\GEN_WRDATA[21].bram_wrdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(21),
Q => bram_wrdata_a(21),
R => '0'
);
\GEN_WRDATA[22].bram_wrdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(22),
Q => bram_wrdata_a(22),
R => '0'
);
\GEN_WRDATA[23].bram_wrdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(23),
Q => bram_wrdata_a(23),
R => '0'
);
\GEN_WRDATA[24].bram_wrdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(24),
Q => bram_wrdata_a(24),
R => '0'
);
\GEN_WRDATA[25].bram_wrdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(25),
Q => bram_wrdata_a(25),
R => '0'
);
\GEN_WRDATA[26].bram_wrdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(26),
Q => bram_wrdata_a(26),
R => '0'
);
\GEN_WRDATA[27].bram_wrdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(27),
Q => bram_wrdata_a(27),
R => '0'
);
\GEN_WRDATA[28].bram_wrdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(28),
Q => bram_wrdata_a(28),
R => '0'
);
\GEN_WRDATA[29].bram_wrdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(29),
Q => bram_wrdata_a(29),
R => '0'
);
\GEN_WRDATA[2].bram_wrdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(2),
Q => bram_wrdata_a(2),
R => '0'
);
\GEN_WRDATA[30].bram_wrdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(30),
Q => bram_wrdata_a(30),
R => '0'
);
\GEN_WRDATA[31].bram_wrdata_int[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF40000"
)
port map (
I0 => axi_wdata_full_reg,
I1 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[0]\,
I2 => \^q\(0),
I3 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[1]\,
I4 => s_axi_wvalid,
O => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\
);
\GEN_WRDATA[31].bram_wrdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(31),
Q => bram_wrdata_a(31),
R => '0'
);
\GEN_WRDATA[3].bram_wrdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(3),
Q => bram_wrdata_a(3),
R => '0'
);
\GEN_WRDATA[4].bram_wrdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(4),
Q => bram_wrdata_a(4),
R => '0'
);
\GEN_WRDATA[5].bram_wrdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(5),
Q => bram_wrdata_a(5),
R => '0'
);
\GEN_WRDATA[6].bram_wrdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(6),
Q => bram_wrdata_a(6),
R => '0'
);
\GEN_WRDATA[7].bram_wrdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(7),
Q => bram_wrdata_a(7),
R => '0'
);
\GEN_WRDATA[8].bram_wrdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(8),
Q => bram_wrdata_a(8),
R => '0'
);
\GEN_WRDATA[9].bram_wrdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wdata(9),
Q => bram_wrdata_a(9),
R => '0'
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
I1 => clr_bram_we,
I2 => s_axi_aresetn,
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wstrb(0),
Q => \GEN_WR_NO_ECC.bram_we_int_reg[3]_0\(0),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wstrb(1),
Q => \GEN_WR_NO_ECC.bram_we_int_reg[3]_0\(1),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wstrb(2),
Q => \GEN_WR_NO_ECC.bram_we_int_reg[3]_0\(2),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WRDATA[31].bram_wrdata_int[31]_i_1_n_0\,
D => s_axi_wstrb(3),
Q => \GEN_WR_NO_ECC.bram_we_int_reg[3]_0\(3),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
I_WRAP_BRST: entity work.design_1_axi_bram_ctrl_0_1_wrap_brst
port map (
\ADDR_SNG_PORT.bram_addr_int[8]_i_2\(3 downto 0) => \ADDR_SNG_PORT.bram_addr_int[8]_i_2\(3 downto 0),
\ADDR_SNG_PORT.bram_addr_int_reg[2]\ => \ADDR_SNG_PORT.bram_addr_int_reg[2]\,
\ADDR_SNG_PORT.bram_addr_int_reg[3]\ => \ADDR_SNG_PORT.bram_addr_int_reg[3]\,
\ADDR_SNG_PORT.bram_addr_int_reg[3]_0\ => \ADDR_SNG_PORT.bram_addr_int_reg[3]_0\,
\ADDR_SNG_PORT.bram_addr_int_reg[4]\ => \ADDR_SNG_PORT.bram_addr_int_reg[4]\,
\ADDR_SNG_PORT.bram_addr_int_reg[5]\ => \ADDR_SNG_PORT.bram_addr_int_reg[5]\,
\ADDR_SNG_PORT.bram_addr_int_reg[5]_0\(2 downto 0) => \ADDR_SNG_PORT.bram_addr_int_reg[5]_0\(2 downto 0),
\ADDR_SNG_PORT.bram_addr_int_reg[5]_1\ => \ADDR_SNG_PORT.bram_addr_int_reg[5]_1\,
Arb2AR_Active => Arb2AR_Active,
Arb2AW_Active => Arb2AW_Active,
D(3 downto 0) => D(3 downto 0),
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[1]\ => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[1]_0\,
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[2]\(0) => \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[2]_0\(0),
Q(1) => \^q\(0),
Q(0) => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[1]\,
SR(0) => SR(0),
ar_active_re => ar_active_re,
aw_active_d1_reg => aw_active_d1_reg_0,
aw_active_re => aw_active_re,
curr_fixed_burst_reg_reg => \^aw_active_d1\,
curr_fixed_burst_reg_reg_0 => \^gen_narrow_cnt.narrow_bram_addr_inc_d1_reg_0\,
curr_narrow_burst => curr_narrow_burst,
curr_wrap_burst_reg => curr_wrap_burst_reg,
narrow_bram_addr_inc_d1 => narrow_bram_addr_inc_d1,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr(17 downto 0) => s_axi_awaddr(19 downto 2),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awsize_0_sp_1 => s_axi_awsize_0_sn_1,
s_axi_awvalid => s_axi_awvalid,
s_axi_wvalid => s_axi_wvalid,
\save_init_bram_addr_ld[19]_i_3_0\(1 downto 0) => narrow_addr_int(1 downto 0),
\save_init_bram_addr_ld_reg[19]_0\(13 downto 0) => \save_init_bram_addr_ld_reg[19]\(13 downto 0)
);
aw_active_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => Arb2AW_Active,
Q => \^aw_active_d1\,
R => SR(0)
);
axi_awready_int_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => s_axi_awvalid,
I1 => AW2Arb_BVALID_Cnt(0),
I2 => AW2Arb_BVALID_Cnt(1),
I3 => AW2Arb_BVALID_Cnt(2),
O => s_axi_awvalid_0
);
\axi_bid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => BID_FIFO_n_2,
Q => \^s_axi_bid\(0),
R => SR(0)
);
axi_bvalid_int_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => s_axi_aresetn,
I1 => axi_bvalid_int_i_2_n_0,
I2 => BID_FIFO_n_1,
O => axi_bvalid_int_i_1_n_0
);
axi_bvalid_int_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF70"
)
port map (
I0 => s_axi_bready,
I1 => \^axi_bvalid_int_reg_0\,
I2 => AW2Arb_BVALID_Cnt(0),
I3 => AW2Arb_BVALID_Cnt(1),
I4 => AW2Arb_BVALID_Cnt(2),
O => axi_bvalid_int_i_2_n_0
);
axi_bvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_bvalid_int_i_1_n_0,
Q => \^axi_bvalid_int_reg_0\,
R => '0'
);
axi_wr_burst_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"5754"
)
port map (
I0 => s_axi_wlast,
I1 => axi_wr_burst_i_2_n_0,
I2 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs[2]_i_3_n_0\,
I3 => axi_wr_burst,
O => axi_wr_burst_i_1_n_0
);
axi_wr_burst_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"A0E0"
)
port map (
I0 => \^q\(0),
I1 => \FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg_n_0_[0]\,
I2 => s_axi_wvalid,
I3 => axi_wdata_full_reg,
O => axi_wr_burst_i_2_n_0
);
axi_wr_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wr_burst_i_1_n_0,
Q => axi_wr_burst,
R => SR(0)
);
axi_wready_int_mod_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_aresetn,
I1 => axi_wdata_full_cmb,
O => axi_wready_int_mod_i_1_n_0
);
axi_wready_int_mod_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wready_int_mod_i_1_n_0,
Q => \^s_axi_wready\,
R => '0'
);
bid_gets_fifo_load_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bid_gets_fifo_load,
Q => bid_gets_fifo_load_d1,
R => SR(0)
);
bram_en_a_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => BRAM_En_A_i,
I1 => BRAM_En_B_i,
O => bram_en_a
);
\bvalid_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => AW2Arb_BVALID_Cnt(0),
O => \bvalid_cnt[0]_i_1_n_0\
);
\bvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF8800770077FF80"
)
port map (
I0 => \^axi_bvalid_int_reg_0\,
I1 => s_axi_bready,
I2 => AW2Arb_BVALID_Cnt(2),
I3 => BID_FIFO_n_1,
I4 => AW2Arb_BVALID_Cnt(1),
I5 => AW2Arb_BVALID_Cnt(0),
O => \bvalid_cnt[1]_i_1_n_0\
);
\bvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA9555555555555"
)
port map (
I0 => BID_FIFO_n_1,
I1 => AW2Arb_BVALID_Cnt(2),
I2 => AW2Arb_BVALID_Cnt(1),
I3 => AW2Arb_BVALID_Cnt(0),
I4 => s_axi_bready,
I5 => \^axi_bvalid_int_reg_0\,
O => \bvalid_cnt[2]_i_1_n_0\
);
\bvalid_cnt[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0000F8FF77000"
)
port map (
I0 => \^axi_bvalid_int_reg_0\,
I1 => s_axi_bready,
I2 => AW2Arb_BVALID_Cnt(0),
I3 => AW2Arb_BVALID_Cnt(1),
I4 => AW2Arb_BVALID_Cnt(2),
I5 => BID_FIFO_n_1,
O => \bvalid_cnt[2]_i_2_n_0\
);
\bvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \bvalid_cnt[2]_i_1_n_0\,
D => \bvalid_cnt[0]_i_1_n_0\,
Q => AW2Arb_BVALID_Cnt(0),
R => SR(0)
);
\bvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \bvalid_cnt[2]_i_1_n_0\,
D => \bvalid_cnt[1]_i_1_n_0\,
Q => AW2Arb_BVALID_Cnt(1),
R => SR(0)
);
\bvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \bvalid_cnt[2]_i_1_n_0\,
D => \bvalid_cnt[2]_i_2_n_0\,
Q => AW2Arb_BVALID_Cnt(2),
R => SR(0)
);
curr_fixed_burst_reg_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_awburst(0),
I1 => s_axi_awburst(1),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => curr_fixed_burst,
Q => curr_fixed_burst_reg,
R => \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[2]_0\(0)
);
curr_wrap_burst_reg_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awburst(1),
I1 => s_axi_awburst(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => aw_active_re,
D => curr_wrap_burst,
Q => curr_wrap_burst_reg,
R => \^fsm_onehot_gen_wdata_sm_no_ecc_sng_reg_wready.wr_data_sng_sm_cs_reg[2]_0\(0)
);
last_arb_won_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000007F00"
)
port map (
I0 => AW2Arb_BVALID_Cnt(2),
I1 => AW2Arb_BVALID_Cnt(1),
I2 => AW2Arb_BVALID_Cnt(0),
I3 => s_axi_awvalid,
I4 => last_arb_won_reg(0),
I5 => last_arb_won_reg(1),
O => \bvalid_cnt_reg[2]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_bram_ctrl_0_1_full_axi is
port (
axi_bvalid_int_reg : out STD_LOGIC;
\GEN_NO_RD_CMD_OPT.axi_rlast_int_reg\ : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 17 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
\GEN_NO_RD_CMD_OPT.axi_rvalid_int_reg\ : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_en_a : out STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wlast : in STD_LOGIC
);
end design_1_axi_bram_ctrl_0_1_full_axi;
architecture STRUCTURE of design_1_axi_bram_ctrl_0_1_full_axi is
signal \ADDR_SNG_PORT.bram_addr_int[10]_i_2_n_0\ : STD_LOGIC;
signal \ADDR_SNG_PORT.bram_addr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \ADDR_SNG_PORT.bram_addr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \ADDR_SNG_PORT.bram_addr_int[3]_i_2_n_0\ : STD_LOGIC;
signal \ADDR_SNG_PORT.bram_addr_int[4]_i_2_n_0\ : STD_LOGIC;
signal \ADDR_SNG_PORT.bram_addr_int[5]_i_2_n_0\ : STD_LOGIC;
signal \ADDR_SNG_PORT.bram_addr_int[6]_i_2_n_0\ : STD_LOGIC;
signal \ADDR_SNG_PORT.bram_addr_int[7]_i_2_n_0\ : STD_LOGIC;
signal \ADDR_SNG_PORT.bram_addr_int[8]_i_2_n_0\ : STD_LOGIC;
signal \ADDR_SNG_PORT.bram_addr_int[9]_i_2_n_0\ : STD_LOGIC;
signal AW2Arb_Active_Clr : STD_LOGIC;
signal Arb2AR_Active : STD_LOGIC;
signal Arb2AW_Active : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal BRAM_En_B_i : STD_LOGIC;
signal BRAM_WE_A_i : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \GEN_ARB.I_SNG_PORT_n_12\ : STD_LOGIC;
signal \GEN_ARB.I_SNG_PORT_n_13\ : STD_LOGIC;
signal \GEN_ARB.I_SNG_PORT_n_14\ : STD_LOGIC;
signal \GEN_ARB.I_SNG_PORT_n_15\ : STD_LOGIC;
signal \GEN_ARB.I_SNG_PORT_n_18\ : STD_LOGIC;
signal \GEN_ARB.I_SNG_PORT_n_24\ : STD_LOGIC;
signal \GEN_ARB.I_SNG_PORT_n_7\ : STD_LOGIC;
signal \GEN_ARB.I_SNG_PORT_n_9\ : STD_LOGIC;
signal \^gen_no_rd_cmd_opt.axi_rlast_int_reg\ : STD_LOGIC;
signal I_RD_CHNL_n_38 : STD_LOGIC;
signal I_RD_CHNL_n_53 : STD_LOGIC;
signal I_RD_CHNL_n_58 : STD_LOGIC;
signal I_RD_CHNL_n_59 : STD_LOGIC;
signal I_RD_CHNL_n_60 : STD_LOGIC;
signal I_WR_CHNL_n_1 : STD_LOGIC;
signal I_WR_CHNL_n_37 : STD_LOGIC;
signal I_WR_CHNL_n_38 : STD_LOGIC;
signal I_WR_CHNL_n_40 : STD_LOGIC;
signal I_WR_CHNL_n_41 : STD_LOGIC;
signal I_WR_CHNL_n_42 : STD_LOGIC;
signal I_WR_CHNL_n_61 : STD_LOGIC;
signal I_WR_CHNL_n_62 : STD_LOGIC;
signal I_WR_CHNL_n_63 : STD_LOGIC;
signal I_WR_CHNL_n_64 : STD_LOGIC;
signal RdChnl_BRAM_Addr_Ld : STD_LOGIC_VECTOR ( 5 downto 3 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal WrChnl_BRAM_Addr_Ld : STD_LOGIC_VECTOR ( 19 downto 6 );
signal ar_active_d1 : STD_LOGIC;
signal ar_active_i_1_n_0 : STD_LOGIC;
signal ar_active_re : STD_LOGIC;
signal arb_sm_cs : STD_LOGIC_VECTOR ( 1 downto 0 );
signal arb_sm_ns : STD_LOGIC_VECTOR ( 1 to 1 );
signal aw_active_d1 : STD_LOGIC;
signal aw_active_i_1_n_0 : STD_LOGIC;
signal aw_active_re : STD_LOGIC;
signal axi_arready_cmb : STD_LOGIC;
signal axi_awready_cmb : STD_LOGIC;
signal curr_narrow_burst_en : STD_LOGIC;
signal last_arb_won : STD_LOGIC;
signal last_arb_won_i_1_n_0 : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 17 downto 0 );
signal sng_bram_addr_ld_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[3]_i_2\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[4]_i_2\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[5]_i_2\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[6]_i_2\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[8]_i_2\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \ADDR_SNG_PORT.bram_addr_int[9]_i_2\ : label is "soft_lutpair74";
begin
BRAM_Addr_A(17 downto 0) <= \^bram_addr_a\(17 downto 0);
\GEN_NO_RD_CMD_OPT.axi_rlast_int_reg\ <= \^gen_no_rd_cmd_opt.axi_rlast_int_reg\;
SR(0) <= \^sr\(0);
\ADDR_SNG_PORT.bram_addr_int[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFFFFF08000000"
)
port map (
I0 => \^bram_addr_a\(6),
I1 => \^bram_addr_a\(4),
I2 => I_WR_CHNL_n_41,
I3 => \^bram_addr_a\(5),
I4 => \^bram_addr_a\(7),
I5 => \^bram_addr_a\(8),
O => \ADDR_SNG_PORT.bram_addr_int[10]_i_2_n_0\
);
\ADDR_SNG_PORT.bram_addr_int[11]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAAAA"
)
port map (
I0 => \^bram_addr_a\(9),
I1 => \^bram_addr_a\(6),
I2 => \ADDR_SNG_PORT.bram_addr_int[11]_i_6_n_0\,
I3 => \^bram_addr_a\(7),
I4 => \^bram_addr_a\(8),
O => \ADDR_SNG_PORT.bram_addr_int[11]_i_5_n_0\
);
\ADDR_SNG_PORT.bram_addr_int[11]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^bram_addr_a\(4),
I1 => \^bram_addr_a\(1),
I2 => \^bram_addr_a\(0),
I3 => \^bram_addr_a\(2),
I4 => \^bram_addr_a\(3),
I5 => \^bram_addr_a\(5),
O => \ADDR_SNG_PORT.bram_addr_int[11]_i_6_n_0\
);
\ADDR_SNG_PORT.bram_addr_int[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^bram_addr_a\(1),
I1 => \^bram_addr_a\(0),
O => \ADDR_SNG_PORT.bram_addr_int[3]_i_2_n_0\
);
\ADDR_SNG_PORT.bram_addr_int[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^bram_addr_a\(2),
I1 => \^bram_addr_a\(0),
I2 => \^bram_addr_a\(1),
O => \ADDR_SNG_PORT.bram_addr_int[4]_i_2_n_0\
);
\ADDR_SNG_PORT.bram_addr_int[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9555"
)
port map (
I0 => \^bram_addr_a\(3),
I1 => \^bram_addr_a\(1),
I2 => \^bram_addr_a\(0),
I3 => \^bram_addr_a\(2),
O => \ADDR_SNG_PORT.bram_addr_int[5]_i_2_n_0\
);
\ADDR_SNG_PORT.bram_addr_int[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^bram_addr_a\(4),
I1 => \^bram_addr_a\(1),
I2 => \^bram_addr_a\(0),
I3 => \^bram_addr_a\(2),
I4 => \^bram_addr_a\(3),
O => \ADDR_SNG_PORT.bram_addr_int[6]_i_2_n_0\
);
\ADDR_SNG_PORT.bram_addr_int[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_a\(5),
I1 => \^bram_addr_a\(3),
I2 => \^bram_addr_a\(2),
I3 => \^bram_addr_a\(0),
I4 => \^bram_addr_a\(1),
I5 => \^bram_addr_a\(4),
O => \ADDR_SNG_PORT.bram_addr_int[7]_i_2_n_0\
);
\ADDR_SNG_PORT.bram_addr_int[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^bram_addr_a\(6),
I1 => \^bram_addr_a\(4),
I2 => I_WR_CHNL_n_41,
I3 => \^bram_addr_a\(5),
O => \ADDR_SNG_PORT.bram_addr_int[8]_i_2_n_0\
);
\ADDR_SNG_PORT.bram_addr_int[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAAAA"
)
port map (
I0 => \^bram_addr_a\(7),
I1 => \^bram_addr_a\(5),
I2 => I_WR_CHNL_n_41,
I3 => \^bram_addr_a\(4),
I4 => \^bram_addr_a\(6),
O => \ADDR_SNG_PORT.bram_addr_int[9]_i_2_n_0\
);
\ADDR_SNG_PORT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_RD_CHNL_n_58,
D => p_1_in(8),
Q => \^bram_addr_a\(8),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_RD_CHNL_n_58,
D => p_1_in(9),
Q => \^bram_addr_a\(9),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => sng_bram_addr_ld_en,
D => p_1_in(10),
Q => \^bram_addr_a\(10),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => sng_bram_addr_ld_en,
D => p_1_in(11),
Q => \^bram_addr_a\(11),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => sng_bram_addr_ld_en,
D => p_1_in(12),
Q => \^bram_addr_a\(12),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => sng_bram_addr_ld_en,
D => p_1_in(13),
Q => \^bram_addr_a\(13),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => sng_bram_addr_ld_en,
D => p_1_in(14),
Q => \^bram_addr_a\(14),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => sng_bram_addr_ld_en,
D => p_1_in(15),
Q => \^bram_addr_a\(15),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => sng_bram_addr_ld_en,
D => p_1_in(16),
Q => \^bram_addr_a\(16),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => sng_bram_addr_ld_en,
D => p_1_in(17),
Q => \^bram_addr_a\(17),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_RD_CHNL_n_58,
D => p_1_in(0),
Q => \^bram_addr_a\(0),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_RD_CHNL_n_58,
D => p_1_in(1),
Q => \^bram_addr_a\(1),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_RD_CHNL_n_58,
D => p_1_in(2),
Q => \^bram_addr_a\(2),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_RD_CHNL_n_58,
D => p_1_in(3),
Q => \^bram_addr_a\(3),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_RD_CHNL_n_58,
D => p_1_in(4),
Q => \^bram_addr_a\(4),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_RD_CHNL_n_58,
D => p_1_in(5),
Q => \^bram_addr_a\(5),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_RD_CHNL_n_58,
D => p_1_in(6),
Q => \^bram_addr_a\(6),
R => I_WR_CHNL_n_1
);
\ADDR_SNG_PORT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_RD_CHNL_n_58,
D => p_1_in(7),
Q => \^bram_addr_a\(7),
R => I_WR_CHNL_n_1
);
\GEN_ARB.I_SNG_PORT\: entity work.design_1_axi_bram_ctrl_0_1_sng_port_arb
port map (
Arb2AR_Active => Arb2AR_Active,
Arb2AW_Active => Arb2AW_Active,
D(0) => arb_sm_ns(1),
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[2]\ => \GEN_ARB.I_SNG_PORT_n_15\,
\FSM_sequential_arb_sm_cs_reg[0]_0\(0) => AW2Arb_Active_Clr,
\GEN_NARROW_CNT.narrow_addr_int_reg[1]\ => I_WR_CHNL_n_42,
\GEN_NARROW_EN.curr_narrow_burst_reg\ => I_WR_CHNL_n_61,
\GEN_NARROW_EN.curr_narrow_burst_reg_0\ => I_WR_CHNL_n_62,
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]\ => I_RD_CHNL_n_38,
\GEN_NO_RD_CMD_OPT.act_rd_burst_two_reg\ => I_RD_CHNL_n_59,
\GEN_NO_RD_CMD_OPT.axi_rlast_int_reg\ => \GEN_ARB.I_SNG_PORT_n_14\,
Q(1 downto 0) => arb_sm_cs(1 downto 0),
SR(0) => \^sr\(0),
ar_active_d1 => ar_active_d1,
ar_active_re => ar_active_re,
ar_active_reg_0 => \GEN_ARB.I_SNG_PORT_n_24\,
ar_active_reg_1 => ar_active_i_1_n_0,
aw_active_d1 => aw_active_d1,
aw_active_re => aw_active_re,
aw_active_reg_0 => aw_active_i_1_n_0,
axi_arready_cmb => axi_arready_cmb,
axi_arready_int_reg_0 => \^gen_no_rd_cmd_opt.axi_rlast_int_reg\,
axi_awready_cmb => axi_awready_cmb,
axi_awready_int_reg_0 => I_RD_CHNL_n_60,
axi_awready_int_reg_1 => I_WR_CHNL_n_64,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
\bram_we_a[3]\(3 downto 0) => BRAM_WE_A_i(3 downto 0),
curr_narrow_burst_en => curr_narrow_burst_en,
last_arb_won => last_arb_won,
last_arb_won_reg_0 => \GEN_ARB.I_SNG_PORT_n_18\,
last_arb_won_reg_1 => last_arb_won_i_1_n_0,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_araddr_1_sp_1 => \GEN_ARB.I_SNG_PORT_n_12\,
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
\s_axi_arlen[2]_0\ => \GEN_ARB.I_SNG_PORT_n_13\,
s_axi_arlen_2_sp_1 => \GEN_ARB.I_SNG_PORT_n_7\,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(1 downto 0) => s_axi_awaddr(1 downto 0),
s_axi_awaddr_1_sp_1 => \GEN_ARB.I_SNG_PORT_n_9\,
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_rready => s_axi_rready
);
I_RD_CHNL: entity work.design_1_axi_bram_ctrl_0_1_rd_chnl
port map (
\ADDR_SNG_PORT.bram_addr_int_reg[10]\ => \ADDR_SNG_PORT.bram_addr_int[10]_i_2_n_0\,
\ADDR_SNG_PORT.bram_addr_int_reg[11]\ => I_WR_CHNL_n_37,
\ADDR_SNG_PORT.bram_addr_int_reg[11]_0\ => \ADDR_SNG_PORT.bram_addr_int[11]_i_5_n_0\,
\ADDR_SNG_PORT.bram_addr_int_reg[11]_1\ => I_WR_CHNL_n_38,
\ADDR_SNG_PORT.bram_addr_int_reg[19]\(13 downto 0) => WrChnl_BRAM_Addr_Ld(19 downto 6),
\ADDR_SNG_PORT.bram_addr_int_reg[19]_0\ => I_WR_CHNL_n_40,
\ADDR_SNG_PORT.bram_addr_int_reg[6]\ => \ADDR_SNG_PORT.bram_addr_int[6]_i_2_n_0\,
\ADDR_SNG_PORT.bram_addr_int_reg[7]\ => \ADDR_SNG_PORT.bram_addr_int[7]_i_2_n_0\,
\ADDR_SNG_PORT.bram_addr_int_reg[8]\ => \ADDR_SNG_PORT.bram_addr_int[8]_i_2_n_0\,
\ADDR_SNG_PORT.bram_addr_int_reg[9]\ => \ADDR_SNG_PORT.bram_addr_int[9]_i_2_n_0\,
Arb2AR_Active => Arb2AR_Active,
BRAM_En_B_i => BRAM_En_B_i,
D(13 downto 0) => p_1_in(17 downto 4),
E(1) => sng_bram_addr_ld_en,
E(0) => I_RD_CHNL_n_58,
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_addr_int_reg[1]_0\ => \GEN_ARB.I_SNG_PORT_n_12\,
\GEN_NO_RD_CMD_OPT.GEN_NARROW_CNT.narrow_bram_addr_inc_d1_reg_0\(2 downto 0) => RdChnl_BRAM_Addr_Ld(5 downto 3),
\GEN_NO_RD_CMD_OPT.GEN_NARROW_EN.curr_narrow_burst_reg_0\ => I_RD_CHNL_n_53,
\GEN_NO_RD_CMD_OPT.act_rd_burst_two_reg_0\ => \GEN_ARB.I_SNG_PORT_n_7\,
\GEN_NO_RD_CMD_OPT.axi_rlast_int_reg_0\ => \^gen_no_rd_cmd_opt.axi_rlast_int_reg\,
\GEN_NO_RD_CMD_OPT.axi_rvalid_int_reg_0\ => \GEN_NO_RD_CMD_OPT.axi_rvalid_int_reg\,
\GEN_NO_RD_CMD_OPT.brst_one_reg_0\ => \GEN_ARB.I_SNG_PORT_n_13\,
Q(2 downto 0) => \^bram_addr_a\(2 downto 0),
SR(0) => \^sr\(0),
ar_active_d1 => ar_active_d1,
ar_active_re => ar_active_re,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(18 downto 2) => s_axi_araddr(19 downto 3),
s_axi_araddr(1 downto 0) => s_axi_araddr(1 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlen_6_sp_1 => I_RD_CHNL_n_59,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arsize_0_sp_1 => I_RD_CHNL_n_38,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rready => s_axi_rready,
s_axi_rready_0 => I_RD_CHNL_n_60,
\save_init_bram_addr_ld_reg[11]\ => I_WR_CHNL_n_41
);
I_WR_CHNL: entity work.design_1_axi_bram_ctrl_0_1_wr_chnl
port map (
\ADDR_SNG_PORT.bram_addr_int[8]_i_2\(3 downto 0) => \^bram_addr_a\(3 downto 0),
\ADDR_SNG_PORT.bram_addr_int_reg[2]\ => \GEN_ARB.I_SNG_PORT_n_24\,
\ADDR_SNG_PORT.bram_addr_int_reg[3]\ => I_WR_CHNL_n_41,
\ADDR_SNG_PORT.bram_addr_int_reg[3]_0\ => \ADDR_SNG_PORT.bram_addr_int[3]_i_2_n_0\,
\ADDR_SNG_PORT.bram_addr_int_reg[4]\ => \ADDR_SNG_PORT.bram_addr_int[4]_i_2_n_0\,
\ADDR_SNG_PORT.bram_addr_int_reg[5]\ => I_RD_CHNL_n_53,
\ADDR_SNG_PORT.bram_addr_int_reg[5]_0\(2 downto 0) => RdChnl_BRAM_Addr_Ld(5 downto 3),
\ADDR_SNG_PORT.bram_addr_int_reg[5]_1\ => \ADDR_SNG_PORT.bram_addr_int[5]_i_2_n_0\,
Arb2AR_Active => Arb2AR_Active,
Arb2AW_Active => Arb2AW_Active,
BRAM_En_B_i => BRAM_En_B_i,
D(3 downto 0) => p_1_in(3 downto 0),
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[1]_0\ => I_WR_CHNL_n_37,
\FSM_onehot_GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY.wr_data_sng_sm_cs_reg[2]_0\(0) => I_WR_CHNL_n_1,
\GEN_NARROW_CNT.narrow_addr_int_reg[1]_0\ => \GEN_ARB.I_SNG_PORT_n_9\,
\GEN_NARROW_CNT.narrow_bram_addr_inc_d1_reg_0\ => I_WR_CHNL_n_38,
\GEN_WR_NO_ECC.bram_we_int_reg[3]_0\(3 downto 0) => BRAM_WE_A_i(3 downto 0),
Q(0) => AW2Arb_Active_Clr,
SR(0) => \^sr\(0),
ar_active_re => ar_active_re,
aw_active_d1 => aw_active_d1,
aw_active_d1_reg_0 => I_WR_CHNL_n_40,
aw_active_re => aw_active_re,
axi_bvalid_int_reg_0 => axi_bvalid_int_reg,
bram_en_a => bram_en_a,
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
\bvalid_cnt_reg[2]_0\ => I_WR_CHNL_n_63,
curr_narrow_burst_en => curr_narrow_burst_en,
last_arb_won_reg(1 downto 0) => arb_sm_cs(1 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr(19 downto 0) => s_axi_awaddr(19 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlen_0_sp_1 => I_WR_CHNL_n_62,
s_axi_awlen_5_sp_1 => I_WR_CHNL_n_61,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awsize_0_sp_1 => I_WR_CHNL_n_42,
s_axi_awvalid => s_axi_awvalid,
s_axi_awvalid_0 => I_WR_CHNL_n_64,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
\save_init_bram_addr_ld_reg[19]\(13 downto 0) => WrChnl_BRAM_Addr_Ld(19 downto 6)
);
ar_active_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"ABBBA888"
)
port map (
I0 => arb_sm_ns(1),
I1 => \GEN_ARB.I_SNG_PORT_n_18\,
I2 => \GEN_ARB.I_SNG_PORT_n_15\,
I3 => s_axi_arvalid,
I4 => Arb2AR_Active,
O => ar_active_i_1_n_0
);
aw_active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0ACFFF0A0A0000"
)
port map (
I0 => I_WR_CHNL_n_64,
I1 => arb_sm_cs(1),
I2 => arb_sm_cs(0),
I3 => AW2Arb_Active_Clr,
I4 => axi_awready_cmb,
I5 => Arb2AW_Active,
O => aw_active_i_1_n_0
);
last_arb_won_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAABBBAAAAA888"
)
port map (
I0 => arb_sm_ns(1),
I1 => axi_arready_cmb,
I2 => I_WR_CHNL_n_64,
I3 => \GEN_ARB.I_SNG_PORT_n_14\,
I4 => I_WR_CHNL_n_63,
I5 => last_arb_won,
O => last_arb_won_i_1_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_bram_ctrl_0_1_axi_bram_ctrl_top is
port (
axi_bvalid_int_reg : out STD_LOGIC;
\GEN_NO_RD_CMD_OPT.axi_rlast_int_reg\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 17 downto 0 );
bram_rst_a : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
\GEN_NO_RD_CMD_OPT.axi_rvalid_int_reg\ : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_en_a : out STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wlast : in STD_LOGIC
);
end design_1_axi_bram_ctrl_0_1_axi_bram_ctrl_top;
architecture STRUCTURE of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl_top is
begin
\GEN_AXI4.I_FULL_AXI\: entity work.design_1_axi_bram_ctrl_0_1_full_axi
port map (
BRAM_Addr_A(17 downto 0) => Q(17 downto 0),
\GEN_NO_RD_CMD_OPT.axi_rlast_int_reg\ => \GEN_NO_RD_CMD_OPT.axi_rlast_int_reg\,
\GEN_NO_RD_CMD_OPT.axi_rvalid_int_reg\ => \GEN_NO_RD_CMD_OPT.axi_rvalid_int_reg\,
SR(0) => bram_rst_a,
axi_bvalid_int_reg => axi_bvalid_int_reg,
bram_en_a => bram_en_a,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(19 downto 0) => s_axi_araddr(19 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(19 downto 0) => s_axi_awaddr(19 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rready => s_axi_rready,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_bram_ctrl_0_1_axi_bram_ctrl is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ecc_interrupt : out STD_LOGIC;
ecc_ue : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_ctrl_awvalid : in STD_LOGIC;
s_axi_ctrl_awready : out STD_LOGIC;
s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wvalid : in STD_LOGIC;
s_axi_ctrl_wready : out STD_LOGIC;
s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_bvalid : out STD_LOGIC;
s_axi_ctrl_bready : in STD_LOGIC;
s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_arvalid : in STD_LOGIC;
s_axi_ctrl_arready : out STD_LOGIC;
s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_rvalid : out STD_LOGIC;
s_axi_ctrl_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 19 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 19 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 18;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is "zynquplus";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 262144;
attribute C_RD_CMD_OPTIMIZATION : integer;
attribute C_RD_CMD_OPTIMIZATION of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 0;
attribute C_READ_LATENCY : integer;
attribute C_READ_LATENCY of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 1;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 20;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 1;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is 1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl : entity is "yes";
end design_1_axi_bram_ctrl_0_1_axi_bram_ctrl;
architecture STRUCTURE of design_1_axi_bram_ctrl_0_1_axi_bram_ctrl is
signal \<const0>\ : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 19 downto 2 );
signal \^s_axi_aclk\ : STD_LOGIC;
begin
\^s_axi_aclk\ <= s_axi_aclk;
bram_addr_a(19 downto 2) <= \^bram_addr_a\(19 downto 2);
bram_addr_a(1) <= \<const0>\;
bram_addr_a(0) <= \<const0>\;
bram_addr_b(19) <= \<const0>\;
bram_addr_b(18) <= \<const0>\;
bram_addr_b(17) <= \<const0>\;
bram_addr_b(16) <= \<const0>\;
bram_addr_b(15) <= \<const0>\;
bram_addr_b(14) <= \<const0>\;
bram_addr_b(13) <= \<const0>\;
bram_addr_b(12) <= \<const0>\;
bram_addr_b(11) <= \<const0>\;
bram_addr_b(10) <= \<const0>\;
bram_addr_b(9) <= \<const0>\;
bram_addr_b(8) <= \<const0>\;
bram_addr_b(7) <= \<const0>\;
bram_addr_b(6) <= \<const0>\;
bram_addr_b(5) <= \<const0>\;
bram_addr_b(4) <= \<const0>\;
bram_addr_b(3) <= \<const0>\;
bram_addr_b(2) <= \<const0>\;
bram_addr_b(1) <= \<const0>\;
bram_addr_b(0) <= \<const0>\;
bram_clk_a <= \^s_axi_aclk\;
bram_clk_b <= \<const0>\;
bram_en_b <= \<const0>\;
bram_rst_b <= \<const0>\;
bram_we_b(3) <= \<const0>\;
bram_we_b(2) <= \<const0>\;
bram_we_b(1) <= \<const0>\;
bram_we_b(0) <= \<const0>\;
bram_wrdata_b(31) <= \<const0>\;
bram_wrdata_b(30) <= \<const0>\;
bram_wrdata_b(29) <= \<const0>\;
bram_wrdata_b(28) <= \<const0>\;
bram_wrdata_b(27) <= \<const0>\;
bram_wrdata_b(26) <= \<const0>\;
bram_wrdata_b(25) <= \<const0>\;
bram_wrdata_b(24) <= \<const0>\;
bram_wrdata_b(23) <= \<const0>\;
bram_wrdata_b(22) <= \<const0>\;
bram_wrdata_b(21) <= \<const0>\;
bram_wrdata_b(20) <= \<const0>\;
bram_wrdata_b(19) <= \<const0>\;
bram_wrdata_b(18) <= \<const0>\;
bram_wrdata_b(17) <= \<const0>\;
bram_wrdata_b(16) <= \<const0>\;
bram_wrdata_b(15) <= \<const0>\;
bram_wrdata_b(14) <= \<const0>\;
bram_wrdata_b(13) <= \<const0>\;
bram_wrdata_b(12) <= \<const0>\;
bram_wrdata_b(11) <= \<const0>\;
bram_wrdata_b(10) <= \<const0>\;
bram_wrdata_b(9) <= \<const0>\;
bram_wrdata_b(8) <= \<const0>\;
bram_wrdata_b(7) <= \<const0>\;
bram_wrdata_b(6) <= \<const0>\;
bram_wrdata_b(5) <= \<const0>\;
bram_wrdata_b(4) <= \<const0>\;
bram_wrdata_b(3) <= \<const0>\;
bram_wrdata_b(2) <= \<const0>\;
bram_wrdata_b(1) <= \<const0>\;
bram_wrdata_b(0) <= \<const0>\;
ecc_interrupt <= \<const0>\;
ecc_ue <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_ctrl_arready <= \<const0>\;
s_axi_ctrl_awready <= \<const0>\;
s_axi_ctrl_bresp(1) <= \<const0>\;
s_axi_ctrl_bresp(0) <= \<const0>\;
s_axi_ctrl_bvalid <= \<const0>\;
s_axi_ctrl_rdata(31) <= \<const0>\;
s_axi_ctrl_rdata(30) <= \<const0>\;
s_axi_ctrl_rdata(29) <= \<const0>\;
s_axi_ctrl_rdata(28) <= \<const0>\;
s_axi_ctrl_rdata(27) <= \<const0>\;
s_axi_ctrl_rdata(26) <= \<const0>\;
s_axi_ctrl_rdata(25) <= \<const0>\;
s_axi_ctrl_rdata(24) <= \<const0>\;
s_axi_ctrl_rdata(23) <= \<const0>\;
s_axi_ctrl_rdata(22) <= \<const0>\;
s_axi_ctrl_rdata(21) <= \<const0>\;
s_axi_ctrl_rdata(20) <= \<const0>\;
s_axi_ctrl_rdata(19) <= \<const0>\;
s_axi_ctrl_rdata(18) <= \<const0>\;
s_axi_ctrl_rdata(17) <= \<const0>\;
s_axi_ctrl_rdata(16) <= \<const0>\;
s_axi_ctrl_rdata(15) <= \<const0>\;
s_axi_ctrl_rdata(14) <= \<const0>\;
s_axi_ctrl_rdata(13) <= \<const0>\;
s_axi_ctrl_rdata(12) <= \<const0>\;
s_axi_ctrl_rdata(11) <= \<const0>\;
s_axi_ctrl_rdata(10) <= \<const0>\;
s_axi_ctrl_rdata(9) <= \<const0>\;
s_axi_ctrl_rdata(8) <= \<const0>\;
s_axi_ctrl_rdata(7) <= \<const0>\;
s_axi_ctrl_rdata(6) <= \<const0>\;
s_axi_ctrl_rdata(5) <= \<const0>\;
s_axi_ctrl_rdata(4) <= \<const0>\;
s_axi_ctrl_rdata(3) <= \<const0>\;
s_axi_ctrl_rdata(2) <= \<const0>\;
s_axi_ctrl_rdata(1) <= \<const0>\;
s_axi_ctrl_rdata(0) <= \<const0>\;
s_axi_ctrl_rresp(1) <= \<const0>\;
s_axi_ctrl_rresp(0) <= \<const0>\;
s_axi_ctrl_rvalid <= \<const0>\;
s_axi_ctrl_wready <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gext_inst.abcv4_0_ext_inst\: entity work.design_1_axi_bram_ctrl_0_1_axi_bram_ctrl_top
port map (
\GEN_NO_RD_CMD_OPT.axi_rlast_int_reg\ => s_axi_rlast,
\GEN_NO_RD_CMD_OPT.axi_rvalid_int_reg\ => s_axi_rvalid,
Q(17 downto 0) => \^bram_addr_a\(19 downto 2),
axi_bvalid_int_reg => s_axi_bvalid,
bram_en_a => bram_en_a,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
bram_rst_a => bram_rst_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => \^s_axi_aclk\,
s_axi_araddr(19 downto 0) => s_axi_araddr(19 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(19 downto 0) => s_axi_awaddr(19 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rready => s_axi_rready,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_axi_bram_ctrl_0_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 19 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of design_1_axi_bram_ctrl_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of design_1_axi_bram_ctrl_0_1 : entity is "design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of design_1_axi_bram_ctrl_0_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of design_1_axi_bram_ctrl_0_1 : entity is "axi_bram_ctrl,Vivado 2020.1.1_AR73018";
end design_1_axi_bram_ctrl_0_1;
architecture STRUCTURE of design_1_axi_bram_ctrl_0_1 is
signal NLW_U0_bram_clk_b_UNCONNECTED : STD_LOGIC;
signal NLW_U0_bram_en_b_UNCONNECTED : STD_LOGIC;
signal NLW_U0_bram_rst_b_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ecc_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ecc_ue_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_bram_addr_b_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_bram_we_b_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_bram_wrdata_b_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_ctrl_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ctrl_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_ctrl_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of U0 : label is 18;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of U0 : label is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynquplus";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of U0 : label is 262144;
attribute C_RD_CMD_OPTIMIZATION : integer;
attribute C_RD_CMD_OPTIMIZATION of U0 : label is 0;
attribute C_READ_LATENCY : integer;
attribute C_READ_LATENCY of U0 : label is 1;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of U0 : label is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 20;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of U0 : label is 1;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute x_interface_info : string;
attribute x_interface_info of bram_clk_a : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
attribute x_interface_info of bram_en_a : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
attribute x_interface_info of bram_rst_a : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
attribute x_interface_parameter : string;
attribute x_interface_parameter of bram_rst_a : signal is "XIL_INTERFACENAME BRAM_PORTA, MASTER_TYPE BRAM_CTRL, MEM_SIZE 1048576, MEM_WIDTH 32, MEM_ECC NONE, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1";
attribute x_interface_info of s_axi_aclk : signal is "xilinx.com:signal:clock:1.0 CLKIF CLK";
attribute x_interface_parameter of s_axi_aclk : signal is "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI:S_AXI_CTRL, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk0, INSERT_VIP 0";
attribute x_interface_info of s_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 RSTIF RST";
attribute x_interface_parameter of s_axi_aresetn : signal is "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0";
attribute x_interface_info of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
attribute x_interface_info of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute x_interface_info of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute x_interface_info of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
attribute x_interface_info of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute x_interface_info of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute x_interface_info of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute x_interface_info of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute x_interface_info of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
attribute x_interface_info of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute x_interface_info of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute x_interface_info of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
attribute x_interface_info of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute x_interface_info of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute x_interface_info of bram_addr_a : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
attribute x_interface_info of bram_rddata_a : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
attribute x_interface_info of bram_we_a : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
attribute x_interface_info of bram_wrdata_a : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
attribute x_interface_info of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute x_interface_info of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
attribute x_interface_info of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
attribute x_interface_info of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
attribute x_interface_info of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
attribute x_interface_info of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
attribute x_interface_info of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute x_interface_parameter of s_axi_awaddr : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 20, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_zynq_ultra_ps_e_0_0_pl_clk0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
attribute x_interface_info of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
attribute x_interface_info of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
attribute x_interface_info of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
attribute x_interface_info of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
attribute x_interface_info of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
attribute x_interface_info of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute x_interface_info of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute x_interface_info of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute x_interface_info of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute x_interface_info of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
U0: entity work.design_1_axi_bram_ctrl_0_1_axi_bram_ctrl
port map (
bram_addr_a(19 downto 0) => bram_addr_a(19 downto 0),
bram_addr_b(19 downto 0) => NLW_U0_bram_addr_b_UNCONNECTED(19 downto 0),
bram_clk_a => bram_clk_a,
bram_clk_b => NLW_U0_bram_clk_b_UNCONNECTED,
bram_en_a => bram_en_a,
bram_en_b => NLW_U0_bram_en_b_UNCONNECTED,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
bram_rddata_b(31 downto 0) => B"00000000000000000000000000000000",
bram_rst_a => bram_rst_a,
bram_rst_b => NLW_U0_bram_rst_b_UNCONNECTED,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_we_b(3 downto 0) => NLW_U0_bram_we_b_UNCONNECTED(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
bram_wrdata_b(31 downto 0) => NLW_U0_bram_wrdata_b_UNCONNECTED(31 downto 0),
ecc_interrupt => NLW_U0_ecc_interrupt_UNCONNECTED,
ecc_ue => NLW_U0_ecc_ue_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(19 downto 0) => s_axi_araddr(19 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock => s_axi_arlock,
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(19 downto 0) => s_axi_awaddr(19 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock => s_axi_awlock,
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_ctrl_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_arready => NLW_U0_s_axi_ctrl_arready_UNCONNECTED,
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_awready => NLW_U0_s_axi_ctrl_awready_UNCONNECTED,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_bresp(1 downto 0) => NLW_U0_s_axi_ctrl_bresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_bvalid => NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED,
s_axi_ctrl_rdata(31 downto 0) => NLW_U0_s_axi_ctrl_rdata_UNCONNECTED(31 downto 0),
s_axi_ctrl_rready => '0',
s_axi_ctrl_rresp(1 downto 0) => NLW_U0_s_axi_ctrl_rresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_rvalid => NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED,
s_axi_ctrl_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_wready => NLW_U0_s_axi_ctrl_wready_UNCONNECTED,
s_axi_ctrl_wvalid => '0',
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
--
-- Copyright (c) 2018, UPC
-- All rights reserved.
--
library ieee;
use ieee.std_logic_1164.all;
use work.param_disenyo_pkg.all;
use work.cte_tipos_deco_camino_pkg.all;
use work.retardos_pkg.all;
entity FMTS is
port(instr: in tipo_inst_busq;
inmS: in st_fmtS;
inmediato: out tam_dat_camino);
end FMTS;
architecture compor of FMTS is
begin
selecformatoS: process(instr, inmS)
variable t_inmediato: tam_dat_camino;
begin
case inmS is
when fmtS_J => -- tipo UJ
t_inmediato := (31 downto 20 => instr(31)) & instr(19 downto 12) & instr(20) & instr(30 downto 21) & '0';
when fmtS_I => -- tipo I
t_inmediato := (31 downto 11 => instr(31)) & instr(30 downto 20);
when fmtS_B => -- tipo SB
t_inmediato := (31 downto 12 => instr(31)) & instr(7) & instr(30 downto 25) & instr(11 downto 8) & '0';
when others =>
t_inmediato := (others => '0');
end case;
inmediato <= t_inmediato after retfmtS;
end process;
end;
|
-- quadrature_decoder_testbench - testbench for quadrature decoder
-- Written in 2016 by <<NAME>> <<EMAIL>>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
entity quadrature_decoder_testbench is
end quadrature_decoder_testbench;
architecture behavioral of quadrature_decoder_testbench is
signal clock : std_logic := '0';
signal a, b : std_logic := '0';
signal rotary : std_logic_vector (1 downto 0);
signal direction : std_logic;
signal pulse : std_logic;
signal done : boolean := false;
procedure noise(variable n : inout std_logic_vector(15 downto 0)) is
begin
-- Thanks Maxim on smspower for (reverse engineered?) specs.
-- Generator polynomial for noise channel of SN76489
-- used on the SMS is not irrereducible: X^16 + X^13 + 1
n := (n(0) xor n(3)) & n(15 downto 1);
end procedure;
procedure switch(
signal s : out std_logic;
constant v : std_logic;
variable n : inout std_logic_vector(15 downto 0)) is
begin
s <= v;
wait for 10 us;
for i in 1 to 19 loop
s <= n(0);
noise(n);
wait for 10 us;
end loop;
s <= v;
wait for 800 us;
end procedure;
begin
rotary <= b & a;
quadrature_decoder_inst : entity work.quadrature_decoder
port map (clock, rotary, direction, pulse);
clk_gen : process
begin
if done then
wait;
else
wait for 1 us;
clock <= not clock;
end if;
end process;
stimulus : process
variable n : std_logic_vector(15 downto 0) := (15 => '1', others => '0');
begin
-- start position
a <= '0';
b <= '0';
wait for 2 ms;
for j in 0 to 2 loop
for i in 0 to j loop
-- one step left
switch(a, '1', n);
switch(b, '1', n);
switch(a, '0', n);
switch(b, '0', n);
wait for 1 ms;
end loop;
for i in 0 to j loop
-- one step right
switch(b, '1', n);
switch(a, '1', n);
switch(b, '0', n);
switch(a, '0', n);
wait for 1 ms;
end loop;
end loop;
done <= true;
wait;
end process;
end behavioral;
|
-------------------------------------------------------------------------------
--! @file
--! @brief PWM module
-------------------------------------------------------------------------------
--! Using IEEE library
LIBRARY ieee;
--! Using IEEE standard logic components
USE ieee.std_logic_1164.ALL;
--! Using IEE standard numeric components
USE ieee.numeric_std.ALL;
--! @brief PWM entity
--!
--! @image html pwm_entity.png "PWM Entity"
--!
--! This entity is a configurable PWM generator. The 'count_max' determines
--! how high the PWM will count to before rolling over. The 'pwm_duty' input
--! determines when the PWM will turn off in the cycle.
--!
--! A pwm_duty of '0' causes the pwm to stay low all the time; where-as a
--! pwm_duty of 'count_max + 1' causes the pwm to stay high all the time.
ENTITY pwm IS
GENERIC (
bit_width : natural RANGE 2 TO 32 := 8 --! PWM width
);
PORT (
clk_in : IN std_logic; --! Clock
rst_in : IN std_logic; --! Asynchronous reset
pwm_adv_in : IN std_logic; --! PWM Advance flag
pwm_duty_in : IN std_logic_vector(bit_width - 1 DOWNTO 0); --! PWM duty cycle
pwm_out : OUT std_logic --! PWM output
);
END ENTITY pwm;
--! Architecture rtl of pwm entity
ARCHITECTURE rtl OF pwm IS
--! Maximum PWM count
CONSTANT c_count_max : natural := (2 ** bit_width) - 2;
--! PWM count
SIGNAL count : unsigned(pwm_duty_in'range);
--! PWM state
SIGNAL state : std_logic;
BEGIN
--! @brief Process for PWM generation
pr_pwm : PROCESS (clk_in, rst_in) IS
BEGIN
IF (rst_in = '1') THEN
-- Reset state
count <= (OTHERS => '0');
state <= '0';
ELSIF (rising_edge(clk_in)) THEN
IF (pwm_adv_in = '1') THEN
-- Drive state
IF (count < unsigned(pwm_duty_in)) THEN
state <= '1';
ELSE
state <= '0';
END IF;
-- Increment count
IF (count = c_count_max) THEN
count <= (OTHERS => '0');
ELSE
count <= count + 1;
END IF;
END IF;
END IF;
END PROCESS pr_pwm;
pwm_out <= state;
END ARCHITECTURE rtl;
|
-- Copyright 2018 Delft University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.Streams.all;
use work.StreamSim.all;
entity StreamElementCounter_tb is
generic (
IN_COUNT_WIDTH : positive;
IN_COUNT_MAX : positive;
OUT_COUNT_WIDTH : positive;
OUT_COUNT_MAX : positive;
OUT_COUNT_MAX_CLAMP : natural
);
port (
clk : in std_logic;
reset : in std_logic
);
end StreamElementCounter_tb;
architecture TestBench of StreamElementCounter_tb is
signal data_a : std_logic_vector(IN_COUNT_WIDTH + 1 downto 0);
signal count_a : std_logic_vector(IN_COUNT_WIDTH - 1 downto 0);
signal last_a : std_logic;
signal dvalid_a : std_logic;
signal valid_a : std_logic;
signal ready_a : std_logic;
signal data_b : std_logic_vector(OUT_COUNT_WIDTH downto 0);
signal count_b : std_logic_vector(OUT_COUNT_WIDTH - 1 downto 0);
signal last_b : std_logic;
signal valid_b : std_logic;
signal ready_b : std_logic;
begin
prod_a: StreamTbProd
generic map (
DATA_WIDTH => IN_COUNT_WIDTH + 2,
SEED => 1,
NAME => "a"
)
port map (
clk => clk,
reset => reset,
out_valid => valid_a,
out_ready => ready_a,
out_data => data_a
);
count_a <= data_a(IN_COUNT_WIDTH - 1 downto 0);
dvalid_a <= data_a(IN_COUNT_WIDTH);
last_a <= data_a(IN_COUNT_WIDTH + 1);
uut: StreamElementCounter
generic map (
IN_COUNT_WIDTH => IN_COUNT_WIDTH,
IN_COUNT_MAX => IN_COUNT_MAX,
OUT_COUNT_WIDTH => OUT_COUNT_WIDTH,
OUT_COUNT_MAX => OUT_COUNT_MAX
)
port map (
clk => clk,
reset => reset,
in_valid => valid_a,
in_ready => ready_a,
in_last => last_a,
in_count => count_a,
in_dvalid => dvalid_a,
out_valid => valid_b,
out_ready => ready_b,
out_count => count_b,
out_last => last_b
);
data_b(OUT_COUNT_WIDTH - 1 downto 0) <= count_b;
data_b(OUT_COUNT_WIDTH) <= last_b;
cons_d: StreamTbCons
generic map (
DATA_WIDTH => OUT_COUNT_WIDTH + 1,
SEED => 1,
NAME => "b"
)
port map (
clk => clk,
reset => reset,
in_valid => valid_b,
in_ready => ready_b,
in_data => data_b
);
end TestBench;
|
-- Copyright (c) 2007-2020 <NAME>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--------------------------------------------------
--UART Receiver Datapath
--This entity is used by uart_receive
--------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--For the signal description, see the state machine
entity uart_recv_dp is
generic (
clock_speed : natural := 33000000;
baud_rate : natural := 115200;
cc_size : natural
);
port (
clk : in std_logic;
reset : in std_logic;
rx : in std_logic;
data : out unsigned(7 downto 0);
parity_ok : out std_logic;
rx_data_en : in std_logic;
sc_iseleven : out std_logic;
cc_incr : in std_logic;
cc_reset : in std_logic;
cc_max : in unsigned(cc_size - 1 downto 0);
cc_half : in unsigned(cc_size - 1 downto 0)
);
end uart_recv_dp;
architecture rxdp of uart_recv_dp is
signal sc_incr : std_logic;
signal sc_shift : std_logic;
signal sc_iseleven_i : std_logic;
signal cc_ishalf : std_logic;
signal hold_reg : unsigned(10 downto 0);
signal shift_reg : unsigned(10 downto 0);
signal cc_reg : unsigned(cc_size - 1 downto 0);
signal sc_reg : unsigned(3 downto 0);
signal parity_i : std_logic;
signal parity_ok_hold_reg : std_logic;
begin
sc_iseleven <= sc_iseleven_i;
data <= hold_reg(8 downto 1);
parity_ok <= parity_ok_hold_reg;
--Data hold register
--It copies the received data from the
--shit register when it is received.
process (clk, reset)
begin
if (reset = '1') then
hold_reg <= (others => '0');
elsif (clk'event and clk = '1') then
if (sc_iseleven_i = '1') then
hold_reg <= shift_reg;
end if;
end if;
end process;
--Parity hold register
process (clk, reset)
begin
if (reset = '1') then
parity_ok_hold_reg <= '0';
elsif (clk'event and clk = '1') then
if (sc_iseleven_i = '1') then
parity_ok_hold_reg <= parity_i;
end if;
end if;
end process;
--Parity register
--If a one is received, the parity is
--negated. At the end of the process
--a one in this register signals no error
--in the case of the even parity.
process (clk, reset, cc_reset)
begin
if (reset = '1') then
parity_i <= '0';
elsif (clk'event and clk = '1') then
if (cc_reset = '1') then
parity_i <= '0';
elsif (sc_shift = '1' and rx = '1') then
parity_i <= not parity_i;
end if;
end if;
end process;
--Shift register
--Rx data is shifted into the register at the
--half of the count. We use the half because
--the input signal is stabilized at this stage.
sc_shift <= rx_data_en and cc_ishalf;
process (clk, reset, sc_shift)
begin
if (reset = '1') then
shift_reg <= (others => '0');
elsif (clk'event and clk = '1') then
if (sc_shift = '1') then
shift_reg <= rx & shift_reg(10 downto 1);
end if;
end if;
end process;
--Shift counter
--Counts to 11 because there are 11 bits to receive
process (clk, reset, sc_shift, cc_reset)
begin
if (reset = '1') then
sc_reg <= (others => '0');
elsif (clk'event and clk = '1') then
if (sc_reg = "1011" or (cc_reset = '1')) then
sc_reg <= (others => '0');
elsif (sc_shift = '1') then
sc_reg <= sc_reg + 1;
end if;
end if;
end process;
sc_iseleven_i <= '1' when sc_reg = "1011" else
'0';
--cycle counter
--It determines when the bits are received.
process (clk, reset, cc_incr, cc_reset)
begin
if (reset = '1') then
cc_reg <= (others => '0');
elsif (clk'event and clk = '1') then
if (cc_reset = '1') then
cc_reg <= (others => '0');
elsif (cc_incr = '1') then
if (cc_reg = cc_max)
then
cc_reg <= (others => '0');
else
cc_reg <= cc_reg + 1;
end if;
end if;
end if;
end process;
cc_ishalf <= '1' when cc_reg = cc_half else
'0';
end rxdp;
|
<reponame>s2swdev/ESE-345-Final-Project<filename>cell_lite/src/alu.vhd
-------------------------------------------------------------------------------
--
-- ESE 345 : Computer Architecture
--
-- Module Name: ALU
-- Description: Top level strutural design of ALU
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
entity alu is
Port ( A : in std_logic_vector(63 downto 0);
B : in std_logic_vector(63 downto 0);
ALU_Op : in std_logic_vector(3 downto 0);
Rs2 : in std_logic_vector(3 downto 0);
ALUOut : out std_logic_vector(63 downto 0));
end alu;
architecture Structure of alu is
component alu_logshift is
Port ( A : in std_logic_vector(63 downto 0);
B : in std_logic_vector(63 downto 0);
shftamnt : in std_logic_vector(3 downto 0);
logshift_op : in std_logic_vector(2 downto 0);
R : out std_logic_vector(63 downto 0));
end component;
component alu_arth is
Port ( A : in std_logic_vector(63 downto 0);
B : in std_logic_vector(63 downto 0);
arth_op : in std_logic_vector(3 downto 0);
R : out std_logic_vector(63 downto 0));
end component;
component mux64_2x1_2 is
port( in1 : in std_logic_vector(63 downto 0);
in0 : in std_logic_vector(63 downto 0);
sel : in std_logic_vector (3 downto 0);
y : out std_logic_vector(63 downto 0) );
end component;
signal Arth_Out, LogShift_Out : std_logic_vector(63 downto 0);
begin
u1: alu_logshift port map( A => A,
B => B,
shftamnt => B(3 downto 0),
logshift_op => ALU_Op(2 downto 0),
R => LogShift_Out );
u2: alu_arth port map( A => A,
B => B,
arth_op => ALU_Op,
R => Arth_out );
u3: mux64_2x1_2 port map( in1 => Arth_out,
in0 => Logshift_Out,
sel => ALU_Op(3 downto 0),
y => ALUOut );
end Structure;
|
library ieee;
use ieee.std_logic_1164.all;
package MIPS_pkg is
constant ROM_ADDR_SIZE : positive := 6;
constant RAM_ADDR_SIZE : positive := 6;
end package MIPS_pkg;
package body MIPS_pkg is
end package body MIPS_pkg;
|
<filename>Processor/FU_Logic_ALU.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FU_Logic_ALU is
Port ( RS_Logic_Ready : in STD_LOGIC;
RS_Logic_Data : in STD_LOGIC_VECTOR (72 downto 0);
ALU_Zero : out STD_LOGIC:= '0';
ALU_Cout : out STD_LOGIC:= '0';
ALU_Ovf : out STD_LOGIC:= '0';
ALU_V_Out : out STD_LOGIC_VECTOR (31 downto 0):= "00000000000000000000000000000000";
ALU_Q_Out : out STD_LOGIC_VECTOR (4 downto 0):= "00000");
end FU_Logic_ALU;
architecture Behavioral of FU_Logic_ALU is
signal tempOutput: STD_LOGIC_VECTOR(31 downto 0):= "00000000000000000000000000000000";
begin
process(RS_Logic_Ready, RS_Logic_Data, tempOutput)
begin
if RS_Logic_Ready = '1' then
case RS_Logic_Data(67 downto 64) is
when "0000" => --Or: A||B
tempOutput <= RS_Logic_Data(63 downto 32) or RS_Logic_Data(31 downto 0);
ALU_V_Out <= tempOutput;
ALU_Q_Out <= RS_Logic_Data(72 downto 68);
ALU_Cout <= '0';
ALU_Ovf <= '0';
if tempOutput = "00000000000000000000000000000000" then
ALU_Zero <= '1';
else
ALU_Zero <= '0';
end if;
when "0001" => --And: A && B
tempOutput <= RS_Logic_Data(63 downto 32) and RS_Logic_Data(31 downto 0);
ALU_V_Out <= tempOutput;
ALU_Q_Out <= RS_Logic_Data(72 downto 68);
ALU_Cout <= '0';
ALU_Ovf <= '0';
if tempOutput = "00000000000000000000000000000000" then
ALU_Zero <= '1';
else
ALU_Zero <= '0';
end if;
when "0010" => --Not: !A
tempOutput <= not RS_Logic_Data(63 downto 32);
ALU_V_Out <= tempOutput;
ALU_Q_Out <= RS_Logic_Data(72 downto 68);
ALU_Cout <= '0';
ALU_Ovf <= '0';
if tempOutput = "00000000000000000000000000000000" then
ALU_Zero <= '1';
else
ALU_Zero <= '0';
end if;
when others =>
ALU_V_Out <= "00000000000000000000000000000000";
ALU_Q_Out <= "00000";
ALU_Cout <= '0';
ALU_Ovf <= '0';
ALU_Zero <= '0';
end case;
else
ALU_V_Out <= "00000000000000000000000000000000";
ALU_Q_Out <= "00000";
ALU_Cout <= '0';
ALU_Ovf <= '0';
ALU_Zero <= '0';
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
package constants is
type ctr_array is array(254 downto 0) of std_logic_vector(7 downto 0);
type key_array is array(254 downto 0) of std_logic_vector(79 downto 0);
type l1_array is array(254 downto 0) of std_logic_vector(24 downto 0);
type l2_array is array(254 downto 0) of std_logic_vector(38 downto 0);
end package;
|
<gh_stars>0
library library IEEE;
use IEEE.std_logic_1164.all;
entity and_gate is
port (a,b: in bit;
y: out bit);
end and_gate;
architecture and_gate_arch of and_gate is
begin
y< = a and b;
end and_gate_arch;
|
<reponame>Psomvanshi/Sobel_edge_detection
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|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cpu2j0_components_pack.all;
use work.test_pkg.all;
entity register_tap is
end register_tap;
architecture tb of register_tap is
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal addr_ra, addr_rb, w_addr_wb, w_addr_ex : std_logic_vector(4 downto 0);
signal din_wb, din_ex : std_logic_vector(31 downto 0);
signal dout_a0, dout_b0, dout_00 : std_logic_vector(31 downto 0);
signal dout_a1, dout_b1, dout_01 : std_logic_vector(31 downto 0);
signal we_wb, we_ex : std_logic;
signal slot : std_logic;
shared variable ENDSIM : boolean := false;
begin -- tb
--
--clk <= '0' after 5 ns when clk = '1' else '1' after 5 ns;
clk_gen : process
begin
if ENDSIM = false then
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
else
wait;
end if;
end process;
u_regfile0 : entity work.register_file(flops)
generic map (
ADDR_WIDTH => 5,
NUM_REGS => 22,
REG_WIDTH => 32)
port map(clk => clk, rst => rst, ce => slot,
addr_ra => addr_ra,
dout_a => dout_a0,
addr_rb => addr_rb,
dout_b => dout_b0,
dout_0 => dout_00,
we_wb => we_wb,
w_addr_wb => w_addr_wb,
din_wb => din_wb,
we_ex => we_ex,
w_addr_ex => w_addr_ex,
din_ex => din_ex);
u_regfile1 : entity work.register_file(two_bank)
generic map (
ADDR_WIDTH => 5,
NUM_REGS => 22,
REG_WIDTH => 32)
port map(clk => clk, rst => rst, ce => slot,
addr_ra => addr_ra,
dout_a => dout_a1,
addr_rb => addr_rb,
dout_b => dout_b1,
dout_0 => dout_01,
we_wb => we_wb,
w_addr_wb => w_addr_wb,
din_wb => din_wb,
we_ex => we_ex,
w_addr_ex => w_addr_ex,
din_ex => din_ex);
process
begin
test_plan(22,"register file");
addr_ra <= "00001";
addr_rb <= "00000";
w_addr_wb <= "00000";
din_wb <= x"bbbbbbbb";
w_addr_ex <= "00001";
din_ex <= x"aaaaaaaa";
slot <= '0';
we_wb <= '1';
we_ex <= '0';
wait for 10 ns;
rst <= '0';
slot <= '1';
wait for 5 ns;
addr_ra <= "00000";
din_wb <= x"cccccccc";
wait for 5 ns; -- check out (mid CC)
test_equal(dout_a0, x"cccccccc","test wb_pipe on dout_a0");
test_equal(dout_b0, x"cccccccc","test wb_pipe on dout_b0");
test_equal(dout_00, x"cccccccc","test wb_pipe on dout_00");
test_equal(dout_a1, x"cccccccc","test wb_pipe on dout_a1");
test_equal(dout_b1, x"cccccccc","test wb_pipe on dout_b1");
test_equal(dout_01, x"cccccccc","test wb_pipe on dout_01");
wait for 10 ns;
we_wb <= '0';
din_wb <= x"dddddddd";
wait for 10 ns;
-- addr_ra <= "00001";
wait for 20 ns;
we_ex <= '1';
wait for 5 ns;
addr_ra <= "00001";
wait for 10 ns;
test_equal(dout_a0, x"aaaaaaaa","test ex_pipe[1] on dout_a0");
test_equal(dout_a1, x"aaaaaaaa","test ex_pipe[1] on dout_a1");
we_ex <= '0';
din_ex <= x"55555555";
wait for 10 ns;
addr_ra <= "00000";
wait for 10 ns; --
test_equal(dout_a0, x"cccccccc","test RAM[0] on dout_a0");
test_equal(dout_a1, x"cccccccc","test RAM[0] on dout_a1");
wait for 10 ns; --
w_addr_ex <= "00000";
w_addr_wb <= "00001";
wait for 10 ns;
we_ex <= '1';
--w_addr_ex <= "00010"; -- hmmm
wait for 10 ns; --
-- w_addr_ex <= "00000";
we_ex <= '0';
addr_ra <= "00001";
wait for 5 ns;
test_equal(dout_a0, x"aaaaaaaa","test RAM[1] on dout_a0");
test_equal(dout_b0, x"55555555","test ex_pipe[1] on dout_b0");
test_equal(dout_00, x"55555555","test ex_pipe[1] on dout_00");
test_equal(dout_a1, x"aaaaaaaa","test RAM[1] on dout_a1");
test_equal(dout_b1, x"55555555","test ex_pipe[1] on dout_b1");
test_equal(dout_01, x"55555555","test ex_pipe[1] on dout_01");
wait for 5 ns;
addr_ra <= "00000";
wait for 10 ns;
test_equal(dout_a0, x"55555555","test ex_pipe[2] on dout_a0");
test_equal(dout_a1, x"55555555","test ex_pipe[2] on dout_a1");
wait for 20 ns;
we_wb <= '1';
w_addr_wb <= "00010";
wait for 10 ns;
addr_rb <= "00010";
w_addr_wb <= "00011";
wait for 10 ns;
we_wb <= '0';
test_equal(dout_b0, x"dddddddd","test RAM[2] on dout_b0");
test_equal(dout_b1, x"dddddddd","test RAM[2] on dout_b1");
wait for 10 ns;
we_ex <= '1';
--w_addr_ex <= "00011";
din_ex <= x"ffffffff";
wait for 10 ns;
we_ex <= '0';
wait for 10 ns;
w_addr_ex <= "00100";
din_ex <= x"22222222";
we_ex <= '1';
wait for 10 ns;
we_ex <= '0';
test_equal(dout_00, x"ffffffff","test reg_0 on dout_00");
test_equal(dout_01, x"ffffffff","test reg_0 on dout_01");
test_finished("done");
wait for 40 ns;
ENDSIM := true;
wait;
end process;
end tb ;
|
------------------------------------------------------
--! @file fa_1bit.vhdl
--! @brief
--! @author <NAME> (<EMAIL>)
--! @date 06/2020
-------------------------------------------------------
entity fa_1bit is
port (
A,B : in bit;
CIN : in bit;
SUM : out bit;
COUT : out bit
);
end entity fa_1bit;
architecture sum_minterm of fa_1bit is
begin
SUM <= (not(CIN) and not(A) and B) or
(not(CIN) and A and not(B)) or
(CIN and not(A) and not(B)) or
(CIN and A and B);
COUT <= (not(CIN) and A and B) or
(CIN and not(A) and B) or
(CIN and A and not(B)) or
(CIN and A and B);
end architecture sum_minterm;
|
<reponame>nbhebert/Frequency-comb-DPLL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity fast_arctan_testbench is
end fast_arctan_testbench;
architecture behavior of fast_arctan_testbench is
component fast_arctan is
port (
clk : in std_logic;
ce : in std_logic;
input_x : in std_logic_vector(15 downto 0);
input_y : in std_logic_vector(15 downto 0);
angle : out std_logic_vector(19 downto 0)
);
end component;
-- Inputs
signal clk : std_logic := '0';
signal ce : std_logic := '1';
signal input_x : std_logic_vector(15 downto 0) := (others => '0');
signal input_y : std_logic_vector(15 downto 0) := (others => '0');
-- Outputs
signal angle : std_logic_vector(19 downto 0);
signal randa_num : std_logic_vector(16-1 downto 0) := (others => '0');
signal randb_num : std_logic_vector(16-1 downto 0) := (others => '0');
signal ramp : std_logic_vector(16-1 downto 0) := (others => '0');
signal reg0_input_x : std_logic_vector(15 downto 0) := (others => '0');
signal reg1_input_x : std_logic_vector(15 downto 0) := (others => '0');
signal reg2_input_x : std_logic_vector(15 downto 0) := (others => '0');
signal reg3_input_x : std_logic_vector(15 downto 0) := (others => '0');
signal reg4_input_x : std_logic_vector(15 downto 0) := (others => '0');
signal reg5_input_x : std_logic_vector(15 downto 0) := (others => '0');
signal reg6_input_x : std_logic_vector(15 downto 0) := (others => '0');
signal reg0_input_y : std_logic_vector(15 downto 0) := (others => '0');
signal reg1_input_y : std_logic_vector(15 downto 0) := (others => '0');
signal reg2_input_y : std_logic_vector(15 downto 0) := (others => '0');
signal reg3_input_y : std_logic_vector(15 downto 0) := (others => '0');
signal reg4_input_y : std_logic_vector(15 downto 0) := (others => '0');
signal reg5_input_y : std_logic_vector(15 downto 0) := (others => '0');
signal reg6_input_y : std_logic_vector(15 downto 0) := (others => '0');
signal input_x_real : real := 0.0;
signal input_y_real : real := 0.0;
signal angle_real : real := 0.0;
signal angle_wide : std_logic_vector(31 downto 0) := (others => '0');
signal angle_ref : std_logic_vector(19 downto 0) := (others => '0');
signal angle_error : std_logic_vector(19 downto 0) := (others => '0');
-- Clock period definition
constant clk_period : time := 5 ns;
begin
-- Unit under test
fast_arctan_inst : fast_arctan
port map (
clk => clk,
ce => ce,
input_x => input_x,
input_y => input_y,
angle => angle
);
process (clk) is
variable seed1: positive := 1;
variable seed2: positive := 1;
variable randa: real := 0.0;
variable randb: real := 0.0;
begin
if rising_edge(clk) then
uniform(seed1, seed2, randa);
randa_num <= std_logic_vector(to_signed(integer(randa*32767.0*2.0-32767.0), 16));
uniform(seed1, seed2, randb);
randb_num <= std_logic_vector(to_signed(integer(randb*32767.0*2.0-32767.0), 16));
ramp <= std_logic_vector(signed(ramp) + 1);
end if;
end process;
process (clk) is
begin
if rising_edge(clk) then
reg0_input_x <= input_x;
reg1_input_x <= reg0_input_x;
reg2_input_x <= reg1_input_x;
reg3_input_x <= reg2_input_x;
reg4_input_x <= reg3_input_x;
reg5_input_x <= reg4_input_x;
reg6_input_x <= reg5_input_x;
reg0_input_y <= input_y;
reg1_input_y <= reg0_input_y;
reg2_input_y <= reg1_input_y;
reg3_input_y <= reg2_input_y;
reg4_input_y <= reg3_input_y;
reg5_input_y <= reg4_input_y;
reg6_input_y <= reg5_input_y;
end if;
end process;
input_x_real <= real(to_integer(signed(reg4_input_x)));
input_y_real <= real(to_integer(signed(reg4_input_y)));
angle_real <= ARCTAN(input_y_real, input_x_real);
angle_wide <= std_logic_vector(to_signed(integer(angle_real*1048576.0/6.283185307179586), 32));
angle_ref <= angle_wide(19 downto 0);
angle_error <= std_logic_vector(signed(angle) - signed(angle_ref));
-- Clock process definition for "clk"
process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
--input_y <= randa_num;
--input_x <= randb_num;
input_y <= ramp;
input_x <= std_logic_vector(to_signed(3456, 16));
-- Stimulus process
process
begin
wait for clk_period*10;
wait until rising_edge(clk);
--wait for clk_period*30;
--wait until rising_edge(clk);
--ce <= '0';
--wait for clk_period*30;
--wait until rising_edge(clk);
--ce <= '1';
wait;
end process;
end architecture;
|
<filename>Tutorial/MultifunctionBarrelShifter/MultifunctionBarrelShifter_tb.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MultifunctionBarrelShifter_tb IS
END MultifunctionBarrelShifter_tb;
ARCHITECTURE behavior OF MultifunctionBarrelShifter_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MultifunctionBarrelShifter
PORT(
a : IN std_logic_vector(7 downto 0);
amt : IN std_logic_vector(2 downto 0);
lr : IN std_logic;
y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(7 downto 0) := (others => '0');
signal amt : std_logic_vector(2 downto 0) := (others => '0');
signal lr : std_logic := '0';
--Outputs
signal y : std_logic_vector(7 downto 0);
constant period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MultifunctionBarrelShifter PORT MAP (
a => a,
amt => amt,
lr => lr,
y => y
);
-- Stimulus process
stim_proc: process
begin
a <= "00011000";
-- to the left
lr <= '1';
amt <= "000";
wait for period;
amt <= "001";
wait for period;
amt <= "010";
wait for period;
amt <= "101";
wait for period;
-- to the right
lr <= '0';
amt <= "000";
wait for period;
amt <= "001";
wait for period;
amt <= "010";
wait for period;
amt <= "101";
wait for period;
assert false
report "Simulation complete" severity failure;
end process;
END;
|
<reponame>clnrp/ep4ce6e22c8_vhdl<gh_stars>1-10
-- ep4ce6e22c8 - test microcontroller
-- Author: <NAME>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TristateBuffer is
generic (
size : integer := 8 -- buffer size
);
port (
En : in std_logic; -- enable
A : in std_logic_vector (size-1 downto 0); -- A is input
B : out std_logic_vector (size-1 downto 0) -- B is output
);
end TristateBuffer;
architecture arch of TristateBuffer is
begin
tristate : for i in 0 to size-1 generate
B(i) <= A(i) when En = '1' else 'Z'; -- if En is 1 B <= A, else B get high impedance
end generate tristate;
end arch;
|
<filename>CertificationSystem_M2S090TS/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vhdl/amba_bfm/bfm_ahbl.vhd
-- Actel Corporation Proprietary and Confidential
-- Copyright 2008 Actel Corporation. All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
-- Revision Information:
-- SVN Revision Information:
-- SVN $Revision: 22340 $
-- SVN $Date: 2014-04-11 17:29:35 +0100 (Fri, 11 Apr 2014) $
use STd.tEXTio.all;
library ieee;
use IEEe.STD_logIC_1164.all;
use ieee.nuMERic_sTD.all;
use woRK.bFM_pacKAGe.all;
entity bfm_AHbl is
generic (VECtfilE: sTRIng := "test.vec";
Max_iNSTrucTIOns: inteGER := 16384;
mAX_stacK: INTeger := 1024;
max_MEmteST: INtegeR := 65536;
tpD: inTEGEr range 0 to 1000 := 1;
DEbuglEVEl: INtegeR range -1 to 5 := -1;
arGVAlue0: intEGEr := 0;
ArgvaLUE1: INtegeR := 0;
aRGValue2: INtegeR := 0;
arGVAlue3: IntegER := 0;
arGVAlue4: INTeger := 0;
aRGValue5: INtegER := 0;
ARgvalUE6: iNTEger := 0;
ArgvaLUE7: inteGER := 0;
argvALUe8: iNTEger := 0;
argVALue9: iNTEger := 0;
ARgvalUE10: iNTEger := 0;
aRGValue11: INtegeR := 0;
ARGvaluE12: INtegeR := 0;
ArgvALUe13: intEGEr := 0;
aRGValue14: iNTEger := 0;
ARGvaluE15: intEGEr := 0;
ArgvALUE16: inTEGer := 0;
ARGvaluE17: iNTEger := 0;
ARgvaLUE18: inTEGer := 0;
ARGvalUE19: InteGER := 0;
aRGVAlue20: INtegeR := 0;
arGVAlue21: iNTEger := 0;
arGVAlue22: INtegER := 0;
ArgvaLUE23: INtegER := 0;
ArgvALUe24: INTeger := 0;
ARgvaLUE25: inTEGer := 0;
arGVAlue26: inteGER := 0;
aRGValuE27: IntegER := 0;
ARgvalUE28: IntegER := 0;
aRGValue29: iNTEger := 0;
argVALue30: InteGER := 0;
ARgvalUE31: INtegeR := 0;
aRGValue32: inTEGer := 0;
ARgvalUE33: intEGEr := 0;
arGVAlue34: INtegeR := 0;
ArgvaLUE35: intEGEr := 0;
argvALUe36: inteGER := 0;
arGVAlue37: intEGEr := 0;
ArgvaLUE38: intEGEr := 0;
aRGVAlue39: iNTEger := 0;
aRGVAlue40: IntegER := 0;
ARGvaluE41: intEGEr := 0;
ARgvaLUE42: inTEGer := 0;
arGVAlue43: INTeger := 0;
ARGvalUE44: INtegeR := 0;
arGVAlue45: inTEGEr := 0;
ARGvaluE46: iNTEGer := 0;
aRGValue47: inteGER := 0;
argvALUe48: INtegeR := 0;
ArgvALUE49: inTEGer := 0;
ArgvaLUE50: InteGER := 0;
ArgvaLUE51: IntegER := 0;
ArgvaLUE52: IntegER := 0;
aRGValuE53: iNTEger := 0;
argvALUe54: inTEGer := 0;
ARGvalUE55: INTeger := 0;
ARGvaluE56: InteGER := 0;
argVALue57: INTeger := 0;
aRGValue58: inteGER := 0;
ARGValuE59: INtegeR := 0;
aRGValue60: INTEger := 0;
ARgvalUE61: inteGER := 0;
ARGvalUE62: INTeger := 0;
ARgvaLUE63: IntegER := 0;
argVALue64: IntegER := 0;
ARgvaLUE65: inTEGer := 0;
argvALUe66: iNTEger := 0;
ArgvALUE67: inTEGer := 0;
argvALUe68: INtegeR := 0;
arGVAlue69: INTeger := 0;
ArgvaLUE70: INTeger := 0;
ARgvalUE71: iNTEger := 0;
argvALUe72: INTeger := 0;
ARGvalUE73: intEGEr := 0;
ArgvaLUE74: iNTEger := 0;
argVALue75: intEGEr := 0;
argVALue76: INTeger := 0;
argVALue77: inTEGEr := 0;
ARgvalUE78: iNTEger := 0;
ARgvalUE79: INtegeR := 0;
ARGvalUE80: iNTEger := 0;
ArgvaLUE81: iNTEger := 0;
argVALue82: inteGER := 0;
ARGvalUE83: intEGEr := 0;
argvALUe84: intEGEr := 0;
ArgvaLUE85: INTEger := 0;
ARgvalUE86: INtegeR := 0;
argvALUe87: INtegeR := 0;
aRGValue88: intEGEr := 0;
ArgvALUE89: INTeger := 0;
argvALUe90: intEGEr := 0;
argVALue91: INtegeR := 0;
ARGvalUE92: INtegeR := 0;
argvALUe93: inteGER := 0;
arGVAlue94: inTEGer := 0;
argVALue95: inteGER := 0;
ARGvaluE96: INtegeR := 0;
argvALUe97: INtegeR := 0;
ARGvaluE98: InteGER := 0;
aRGValuE99: inteGER := 0); port (sySCLk: in std_LOgic;
SysrsTN: in sTD_logIC;
Haddr: out stD_logiC_VectOR(31 downto 0);
hCLK: out STD_logIC;
HRESetn: out STD_logIC;
HbursT: out std_LOgic_VEctoR(2 downto 0);
HmastLOCk: out Std_lOGIc;
HProt: out STD_loGIC_veCTOr(3 downto 0);
hsiZE: out STD_loGIC_veCTOr(2 downto 0);
htRANs: out STd_loGIC_veCTOr(1 downto 0);
HWRite: out STD_logIC;
HwdatA: out std_LOGic_VECtor(31 downto 0);
hRDAta: in std_LOgic_VEctoR(31 downto 0);
HReady: in STD_logIC;
hRESp: in Std_lOGIc;
hsel: out Std_LOGic_vECTor(15 downto 0);
InterRUPt: in std_LOgic_VEctoR(255 downto 0);
gP_Out: out STD_logIC_vecTOr(31 downto 0);
gp_IN: in STd_lOGIC_veCTor(31 downto 0);
EXT_wr: out Std_lOGIc;
EXt_rd: out Std_lOGIc;
exT_addr: out STd_loGIC_vecTOr(31 downto 0);
ext_DAta: inout sTD_logIC_vecTOR(31 downto 0);
ext_Wait: in STD_logIC;
FINisheD: out std_LOGic;
FAiled: out stD_LogiC);
end BFm_aHBL;
architecture BFMA1I10i of BFm_ahBL is
signal BFMA1OO1ol: STD_logIC := '0';
signal inSTR_in: Std_lOGIc_veCTOr(31 downto 0) := ( others => '0');
signal con_Addr: Std_lOGIc_vECTor(15 downto 0) := ( others => '0');
signal Con_DATa: stD_LogiC_VectOR(31 downto 0) := ( others => 'Z');
begin
BFMA1LO1ol: BFM_maIN
generic map (opmODE => 0,
cON_spuLSE => 0,
vECTfile => VectfILE,
Max_iNSTructIONs => max_INstrUCTionS,
Tpd => tPD,
max_STack => maX_StacK,
MAX_memTESt => maX_memtEST,
deBUGleveL => DebugLEVEl,
ARGvaluE0 => ArgvaLUE0,
ARGvalUE1 => ArgvaLUE1,
argVALue2 => ArgvaLUE2,
aRGValue3 => ArgvaLUE3,
ARgvaLUE4 => argVALue4,
argvALUe5 => argvALUe5,
arGVAlue6 => argvALUe6,
argVALue7 => ArgvaLUE7,
aRGValue8 => ArgvaLUE8,
ArgvALUe9 => ARgvalUE9,
ArgvaLUE10 => ARGvaluE10,
aRGValue11 => argvALUe11,
aRGValue12 => ArgvaLUE12,
aRGValue13 => ARgvaLUE13,
arGVAlue14 => ARgvalUE14,
arGVAlue15 => aRGValue15,
argVALue16 => ARGvaluE16,
ARgvalUE17 => ARGvaluE17,
arGVAlue18 => argVALue18,
aRGValue19 => ArgvALUe19,
ArgvaLUE20 => ARGvalUE20,
argvALUe21 => ARgvalUE21,
aRGVAlue22 => arGVAlue22,
aRGVAlue23 => ArgvaLUE23,
ArgvaLUE24 => ARGvaluE24,
argVALue25 => arGVAlue25,
aRGValue26 => ArgvaLUE26,
ARgvalUE27 => arGVAlue27,
aRGValue28 => aRGValuE28,
aRGValue29 => ARGValuE29,
ARgvalUE30 => ARgvalUE30,
arGVALue31 => ARGvaluE31,
aRGValue32 => ARgvalUE32,
ARgvaLUE33 => arGVAlue33,
argVALue34 => argvALUe34,
aRGValuE35 => aRGValue35,
ARGvaluE36 => ArgvaLUE36,
argVALue37 => ARGvaluE37,
arGVAlue38 => ArgvaLUE38,
argVALue39 => argVALue39,
argVALue40 => aRGValue40,
arGVAlue41 => ARGvaluE41,
ArgvALUE42 => aRGValuE42,
ArgvaLUE43 => aRGValue43,
ArgvaLUE44 => aRGVAlue44,
arGVAlue45 => argvALUe45,
argVALue46 => arGVAlue46,
argVALue47 => ARGvaluE47,
ARGvalUE48 => aRGValue48,
ARgvalUE49 => argvALUe49,
ARgvalUE50 => arGVAlue50,
arGVAlue51 => ARGvaluE51,
ArgvaLUE52 => aRGValue52,
aRGValue53 => ARgvalUE53,
aRGVAlue54 => arGVAlue54,
arGVAlue55 => arGVAlue55,
argvALUe56 => aRGValue56,
argvALUe57 => arGVALue57,
ARGvaluE58 => aRGValue58,
argvALUe59 => ARgvalUE59,
ARgvalUE60 => ArgvALUe60,
ARgvalUE61 => ArgvaLUE61,
arGVAlue62 => aRGVAlue62,
argVALue63 => ArgvaLUE63,
ArgvaLUE64 => arGVAlue64,
argvALUe65 => ArgvaLUE65,
ARgvalUE66 => argVALue66,
argVALue67 => argvALUe67,
ARGvalUE68 => ArgvaLUE68,
ArgvaLUE69 => ARgvaLUE69,
ARGvaluE70 => aRGVAlue70,
ARGvaluE71 => arGVAlue71,
aRGValue72 => argvALUe72,
ARGvalUE73 => aRGValue73,
aRGValuE74 => arGVAlue74,
ArgvaLUE75 => aRGValue75,
ArgvaLUE76 => aRGVAlue76,
ARGvaluE77 => aRGValue77,
aRGValue78 => argvALUe78,
ArgvaLUE79 => ARgvaLUE79,
argVALue80 => argVALue80,
ARgvalUE81 => ARGvalUE81,
argvALUe82 => ArgvaLUE82,
ArgvaLUE83 => ARgvalUE83,
argVALue84 => arGVAlue84,
ARgvalUE85 => arGVAlue85,
aRGValue86 => ARgvalUE86,
ARgvalUE87 => ARgvaLUE87,
argVALue88 => arGVAlue88,
ArgvaLUE89 => ArgvALUE89,
ArgvaLUE90 => aRGVAlue90,
aRGValue91 => aRGValue91,
arGVAlue92 => argVALue92,
argvALUe93 => argvALUe93,
ARGvalUE94 => argvALUe94,
ARGvaluE95 => ARGValuE95,
argVALue96 => argvALUe96,
argvALUe97 => ARGValuE97,
ArgvALUe98 => ARgvalUE98,
ARgvalUE99 => arGVAlue99)
port map (sYSClk => SYsclk,
SYSrstn => sySRStn,
HAddr => HADDr,
Hclk => Hclk,
PClk => open ,
HresETN => hreSETn,
HBurst => HBurst,
hmasTLOck => HmastLOCk,
hprOT => hproT,
hSIZe => HSIze,
HtranS => htrANS,
hwriTE => hwrITE,
HwdaTA => HWData,
HRdata => HRdata,
hreaDY => HREady,
hreSP => HResp,
hsel => hSEL,
INterRUPT => iNTErrupT,
GP_ouT => GP_out,
GP_in => gp_iN,
EXT_wr => ext_WR,
ext_RD => ext_RD,
Ext_aDDR => EXt_adDR,
ext_Data => EXT_datA,
Ext_wAIT => exT_wait,
con_Addr => COn_adDR,
con_DATa => CON_datA,
COn_rd => BFMA1OO1ol,
con_WR => BFMA1Oo1ol,
Con_BUSy => open ,
iNSTR_ouT => open ,
INStr_iN => iNSTr_iN,
FInishED => fINIshed,
FAiled => failED);
end BFMA1i10I;
|
<filename>Single-Cycle-Processor/DisplayInterface.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01/31/2019 02:20:50 PM
-- Design Name:
-- Module Name: Top_Module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DisplayInterface is
Port (
instruction : in std_logic_vector (31 downto 0);
addr_pm : in std_logic_vector (31 downto 0);
addr_dm : in std_logic_vector (31 downto 0);
data_out : in std_logic_vector (31 downto 0);
data_in : in std_logic_vector (31 downto 0);
slide_display : in std_logic_vector (5 downto 0);
display_reg0 : in std_logic_vector(31 downto 0);
display_reg1 : in std_logic_vector(31 downto 0);
display_reg2 : in std_logic_vector(31 downto 0);
display_reg3 : in std_logic_vector(31 downto 0);
display_reg4 : in std_logic_vector(31 downto 0);
display_reg5 : in std_logic_vector(31 downto 0);
display_reg6 : in std_logic_vector(31 downto 0);
display_reg7 : in std_logic_vector(31 downto 0);
display_reg8 : in std_logic_vector(31 downto 0);
display_reg9 : in std_logic_vector(31 downto 0);
display_reg10 : in std_logic_vector(31 downto 0);
display_reg11 : in std_logic_vector(31 downto 0);
display_reg12 : in std_logic_vector(31 downto 0);
display_reg13 : in std_logic_vector(31 downto 0);
display_reg14 : in std_logic_vector(31 downto 0);
display_reg15 : in std_logic_vector(31 downto 0);
-- Add the States input from the CPU
led_Out : out std_logic_vector (15 downto 0)
);
end DisplayInterface;
architecture Behavioral of DisplayInterface is
signal selected : std_logic_vector(31 downto 0);
begin
selected <= display_reg0 when slide_display(4 downto 0) = "00000" else
display_reg1 when slide_display(4 downto 0) = "00001" else
display_reg2 when slide_display(4 downto 0) = "00010" else
display_reg3 when slide_display(4 downto 0) = "00011" else
display_reg4 when slide_display(4 downto 0) = "00100" else
display_reg5 when slide_display(4 downto 0) = "00101" else
display_reg6 when slide_display(4 downto 0) = "00110" else
display_reg7 when slide_display(4 downto 0) = "00111" else
display_reg8 when slide_display(4 downto 0) = "01000" else
display_reg9 when slide_display(4 downto 0) = "01001" else
display_reg10 when slide_display(4 downto 0) = "01010" else
display_reg11 when slide_display(4 downto 0) = "01011" else
display_reg12 when slide_display(4 downto 0) = "01100" else
display_reg13 when slide_display(4 downto 0) = "01101" else
display_reg14 when slide_display(4 downto 0) = "01110" else
display_reg15 when slide_display(4 downto 0) = "01111" else
data_out when slide_display(4 downto 0) = "10000" else
addr_dm when slide_display(4 downto 0) = "10001" else
addr_pm when slide_display(4 downto 0) = "10010" else
data_in when slide_display(4 downto 0) = "10011" else
instruction when slide_display(4 downto 0) = "11111" else
"11111111111111111111111111111111";
led_Out <= selected(31 downto 16) when slide_display(5) = '1' else --leftmost switch
selected(15 downto 0);
end Behavioral;
|
<reponame>brunoartc/GladOS
-- Elementos de Sistemas
-- by <NAME>
-- FullAdder.vhd
-- Implementa Full Adder
Library ieee;
use ieee.std_logic_1164.all;
entity FullAdder is
port(
a,b,c: in STD_LOGIC; -- entradas
soma,vaium: out STD_LOGIC -- sum e carry
);
end entity;
architecture rtl of FullAdder is
begin
soma <= (a xor b) xor c;
vaium <= ((a xor b) and c) or (a and b);
end architecture;
|
<filename>generic_components/rtl/two_input_size_generic_buffer.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.GENERIC_FUNCTIONS.max;
entity two_input_size_generic_buffer is
generic (
INPUT_1_LENGTH : natural;
INPUT_2_LENGTH : natural;
OUTPUT_LENGTH : natural;
NUM_OF_OUTPUT_ELEMENTS : natural
);
port (
clk : in std_logic;
rst : in std_logic;
i_data_length_selector : in std_logic;
i_rd_en : in std_logic;
i_wr_en : in std_logic;
i_wr_data : in std_logic_vector(max(INPUT_1_LENGTH, INPUT_2_LENGTH)-1 downto 0);
o_full_buffer : out std_logic;
o_empty_buffer : out std_logic;
o_rd_data : out std_logic_vector(OUTPUT_LENGTH-1 downto 0)
);
end two_input_size_generic_buffer;
architecture behavioral of two_input_size_generic_buffer is
begin
end behavioral;
|
<gh_stars>10-100
------------------------------------------------------------------------------
-- Copyright [2014] [Ztachip Technologies Inc]
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
------------------------------------------------------------------------------
-------
-- Description:
-- Implement register file
-- Every write operations are performed on 2 RAM bank.
-- Each read port is assigned to a RAM bank
-- Register file can be accessed by ALU for parameter load/store
-- Register file can also be accessed by DP engine.
-- Register file is divided into 2 independent partitions. Each partition is assigned to a process
-- The data layout of register file is as followed
-- thread0 privateMem word#0
-- thread1 privateMem word#0
-- :
-- thread15 privateMem word#0
-- thread0 privateMem word#1
-- thread1 privateMem word#1
-- :
-- thread15 privateMem word#1
-- :
-- thread0 privateMem word#N
-- thread1 privateMem word#N
-- :
-- thread15 privateMem word#N
-- :
-- :
-- sharedMem word#N
-- SharedMem word#N-1
-- :
-- SharedMem word#0
--
-- Number of private memory words available for each thread is dependent on memory model size of pcore program
------
library std;
use std.standard.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
--library output_files;
use work.hpc_pkg.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY register_bank IS
PORT(
SIGNAL clock_in : IN STD_LOGIC;
SIGNAL reset_in : IN STD_LOGIC;
SIGNAL rd_en_in : IN STD_LOGIC;
SIGNAL rd_en_vm_in : IN STD_LOGIC;
SIGNAL rd_en_out : OUT STD_LOGIC;
SIGNAL rd_x1_vector_in : IN STD_LOGIC;
SIGNAL rd_x1_addr_in : IN STD_LOGIC_VECTOR(register_file_depth_c-1 DOWNTO 0); -- Read address of port 1
SIGNAL rd_x2_vector_in : IN STD_LOGIC;
SIGNAL rd_x2_addr_in : IN STD_LOGIC_VECTOR(register_file_depth_c-1 DOWNTO 0); -- Read address of port 2
SIGNAL rd_x1_data_out : OUT STD_LOGIC_VECTOR(vregister_width_c-1 DOWNTO 0); -- Read value returned to port 1
SIGNAL rd_x2_data_out : OUT STD_LOGIC_VECTOR(vregister_width_c-1 DOWNTO 0); -- Read value returned to port 2
SIGNAL wr_en_in : IN STD_LOGIC; -- Write enable
SIGNAL wr_en_vm_in : IN STD_LOGIC; -- Write enable
SIGNAL wr_vector_in : IN STD_LOGIC;
SIGNAL wr_addr_in : IN STD_LOGIC_VECTOR(register_file_depth_c-1 DOWNTO 0); -- Write address
SIGNAL wr_data_in : IN STD_LOGIC_VECTOR(vregister_width_c-1 DOWNTO 0); -- Write value
SIGNAL wr_lane_in : IN STD_LOGIC_VECTOR(vector_width_c-1 DOWNTO 0);
-- DP interface
SIGNAL dp_rd_vector_in : IN unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_rd_scatter_in : IN scatter_t;
SIGNAL dp_rd_scatter_cnt_in : IN unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_rd_scatter_vector_in : IN unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_rd_gen_valid_in : IN STD_LOGIC;
SIGNAL dp_rd_data_flow_in : IN data_flow_t;
SIGNAL dp_rd_data_type_in : IN dp_data_type_t;
SIGNAL dp_rd_stream_in : IN std_logic;
SIGNAL dp_rd_stream_id_in : stream_id_t;
SIGNAL dp_rd_addr_in : IN STD_LOGIC_VECTOR(bus_width_c-1 DOWNTO 0);
SIGNAL dp_wr_vector_in : IN unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_wr_addr_in : IN STD_LOGIC_VECTOR(bus_width_c-1 DOWNTO 0);
SIGNAL dp_write_in : IN STD_LOGIC;
SIGNAL dp_write_vm_in : IN STD_LOGIC;
SIGNAL dp_read_in : IN STD_LOGIC;
SIGNAL dp_read_vm_in : IN STD_LOGIC;
SIGNAL dp_writedata_in : IN STD_LOGIC_VECTOR(ddrx_data_width_c-1 DOWNTO 0);
SIGNAL dp_readdata_out : OUT STD_LOGIC_VECTOR(ddrx_data_width_c-1 DOWNTO 0);
SIGNAL dp_readdata_vm_out : OUT STD_LOGIC;
SIGNAL dp_readena_out : OUT STD_LOGIC;
SIGNAL dp_read_vector_out : OUT unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_read_vaddr_out : OUT STD_LOGIC_VECTOR(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_read_scatter_out : OUT scatter_t;
SIGNAL dp_read_scatter_cnt_out : OUT unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_read_scatter_vector_out : OUT unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_read_gen_valid_out : OUT STD_LOGIC;
SIGNAL dp_read_data_flow_out : OUT data_flow_t;
SIGNAL dp_read_data_type_out : OUT dp_data_type_t;
SIGNAL dp_read_stream_out : OUT std_logic;
SIGNAL dp_read_stream_id_out : OUT stream_id_t
);
END register_bank;
ARCHITECTURE behavior OF register_bank IS
SIGNAL rd_en_vm1:STD_LOGIC;
SIGNAL rd_en_vm2:STD_LOGIC;
SIGNAL wr_en_vm1:STD_LOGIC; -- Write enable
SIGNAL wr_en_vm2:STD_LOGIC; -- Write enable
SIGNAL dp_read_vm1:STD_LOGIC;
SIGNAL dp_read_vm2:STD_LOGIC;
SIGNAL dp_write_vm1:STD_LOGIC;
SIGNAL dp_write_vm2:STD_LOGIC;
SIGNAL dp_readena_vm1:STD_LOGIC;
SIGNAL dp_readena_vm2:STD_LOGIC;
SIGNAL dp_read_vector_vm1:unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_read_vector_vm2:unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_read_vaddr_vm1:std_logic_vector(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_read_vaddr_vm2:std_logic_vector(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_read_gen_valid_vm1:STD_LOGIC;
SIGNAL dp_read_gen_valid_vm2:STD_LOGIC;
SIGNAL dp_read_data_flow_vm1:data_flow_t;
SIGNAL dp_read_data_flow_vm2:data_flow_t;
SIGNAL dp_read_stream_vm1:std_logic;
SIGNAL dp_read_stream_vm2:std_logic;
SIGNAL dp_read_stream_id_vm1:stream_id_t;
SIGNAL dp_read_stream_id_vm2:stream_id_t;
SIGNAL dp_read_data_type_vm1:dp_data_type_t;
SIGNAL dp_read_data_type_vm2:dp_data_type_t;
SIGNAL dp_encode:STD_LOGIC_VECTOR(register_width_c-1 downto 0);
SIGNAL rd_en1_vm1:STD_LOGIC;
SIGNAL rd_en1_vm2:STD_LOGIC;
SIGNAL dp_readdata_vm:STD_LOGIC_VECTOR(ddrx_data_width_c-1 downto 0);
SIGNAL dp_readdata_vm1:STD_LOGIC_VECTOR(ddrx_data_width_c-1 downto 0);
SIGNAL dp_readdata_vm2:STD_LOGIC_VECTOR(ddrx_data_width_c-1 downto 0);
SIGNAL q1_encode:STD_LOGIC_VECTOR(register_width_c-1 downto 0);
SIGNAL q2_encode:STD_LOGIC_VECTOR(register_width_c-1 downto 0);
SIGNAL rd_x1_data_vm:STD_LOGIC_VECTOR(vregister_width_c-1 downto 0);
SIGNAL rd_x2_data_vm:STD_LOGIC_VECTOR(vregister_width_c-1 downto 0);
SIGNAL rd_x1_data1_vm1:STD_LOGIC_VECTOR(vregister_width_c-1 downto 0);
SIGNAL rd_x2_data1_vm1:STD_LOGIC_VECTOR(vregister_width_c-1 downto 0);
SIGNAL rd_x1_data1_vm2:STD_LOGIC_VECTOR(vregister_width_c-1 downto 0);
SIGNAL rd_x2_data1_vm2:STD_LOGIC_VECTOR(vregister_width_c-1 downto 0);
SIGNAL rd_enable1_vm1:STD_LOGIC;
SIGNAL rd_enable1_vm2:STD_LOGIC;
SIGNAL dp_read_scatter_vm1:scatter_t;
SIGNAL dp_read_scatter_cnt_vm1:unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_read_scatter_vector_vm1:unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_read_scatter_vm2:scatter_t;
SIGNAL dp_read_scatter_cnt_vm2:unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_read_scatter_vector_vm2:unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_rd_data_flow_r:data_flow_t;
SIGNAL dp_rd_data_type_r:dp_data_type_t;
SIGNAL dp_rd_stream_r:std_logic;
SIGNAL dp_rd_stream_id_r:stream_id_t;
SIGNAL dp_rd_gen_valid_r:STD_LOGIC;
SIGNAL dp_rd_scatter_r:scatter_t;
SIGNAL dp_rd_scatter_cnt_r:unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_rd_scatter_vector_r:unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_rd_vaddr_r:STD_LOGIC_VECTOR(vector_depth_c-1 downto 0);
SIGNAL dp_rd_vector_r:unsigned(vector_depth_c-1 downto 0);
SIGNAL dp_rd_data_flow_rr:data_flow_t;
SIGNAL dp_rd_data_type_rr:dp_data_type_t;
SIGNAL dp_rd_stream_rr:std_logic;
SIGNAL dp_rd_stream_id_rr:stream_id_t;
SIGNAL dp_rd_gen_valid_rr:STD_LOGIC;
SIGNAL dp_rd_scatter_rr:scatter_t;
SIGNAL dp_rd_scatter_cnt_rr:unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_rd_scatter_vector_rr:unsigned(ddr_vector_depth_c-1 downto 0);
SIGNAL dp_rd_vaddr_rr:STD_LOGIC_VECTOR(vector_depth_c-1 downto 0);
SIGNAL dp_rd_vector_rr:unsigned(vector_depth_c-1 downto 0);
SIGNAL rd_x1_vector_r:STD_LOGIC;
SIGNAL rd_x1_vector_rr:STD_LOGIC;
SIGNAL rd_x1_vaddr_r:STD_LOGIC_VECTOR(vector_depth_c-1 downto 0);
SIGNAL rd_x1_vaddr_rr:STD_LOGIC_VECTOR(vector_depth_c-1 downto 0);
SIGNAL rd_x2_vector_r:STD_LOGIC;
SIGNAL rd_x2_vector_rr:STD_LOGIC;
SIGNAL rd_x2_vaddr_r:STD_LOGIC_VECTOR(vector_depth_c-1 downto 0);
SIGNAL rd_x2_vaddr_rr:STD_LOGIC_VECTOR(vector_depth_c-1 downto 0);
BEGIN
rd_en_vm1 <= rd_en_in and (not rd_en_vm_in);
rd_en_vm2 <= rd_en_in and (rd_en_vm_in);
wr_en_vm1 <= wr_en_in and (not wr_en_vm_in);
wr_en_vm2 <= wr_en_in and wr_en_vm_in;
dp_read_vm1 <= dp_read_in and (not dp_read_vm_in);
dp_read_vm2 <= dp_read_in and (dp_read_vm_in);
dp_write_vm1 <= dp_write_in and (not dp_write_vm_in);
dp_write_vm2 <= dp_write_in and (dp_write_vm_in);
dp_readdata_out(dp_readdata_out'length-1 downto register_width_c) <= dp_readdata_vm(dp_readdata_out'length-1 downto register_width_c);
dp_readdata_out(register_width_c-1 downto 0) <= dp_encode;
dp_readdata_vm_out <= '0' when dp_readena_vm1='1' else '1';
rd_en_out <= rd_enable1_vm1 or rd_enable1_vm2;
--
-- ALU X1 and X2 read output
---
process(rd_x1_vector_rr,rd_x1_data_vm,q1_encode,rd_x2_vector_rr,rd_x2_data_vm,q2_encode)
begin
if rd_x1_vector_rr/='0' then
rd_x1_data_out <= rd_x1_data_vm; -- This is a vector read
else
rd_x1_data_out <= q1_encode & -- This is a non-vector read
q1_encode &
q1_encode &
q1_encode &
q1_encode &
q1_encode &
q1_encode &
q1_encode;
end if;
if rd_x2_vector_rr/='0' then
rd_x2_data_out <= rd_x2_data_vm; -- This is vector read
else
rd_x2_data_out <= q2_encode & -- This is a non-vector read
q2_encode &
q2_encode &
q2_encode &
q2_encode &
q2_encode &
q2_encode &
q2_encode;
end if;
end process;
dp_readena_out <= dp_readena_vm1 or dp_readena_vm2;
dp_read_vector_out <= dp_rd_vector_rr;
dp_read_vaddr_out <= dp_rd_vaddr_rr;
dp_read_scatter_out <= dp_rd_scatter_rr;
dp_read_scatter_cnt_out <= dp_rd_scatter_cnt_rr;
dp_read_scatter_vector_out <= dp_rd_scatter_vector_rr;
dp_read_gen_valid_out <= dp_rd_gen_valid_rr;
dp_read_data_flow_out <= dp_rd_data_flow_rr;
dp_read_data_type_out <= dp_rd_data_type_rr;
dp_read_stream_out <= dp_rd_stream_rr;
dp_read_stream_id_out <= dp_rd_stream_id_rr;
process(clock_in,reset_in)
begin
if reset_in = '0' then
dp_rd_vaddr_r <= (others=>'0');
dp_rd_vector_r <= (others=>'0');
dp_rd_data_flow_r <= (others=>'0');
dp_rd_data_type_r <= (others=>'0');
dp_rd_stream_r <= '0';
dp_rd_stream_id_r <= (others=>'0');
dp_rd_gen_valid_r <= '0';
dp_rd_scatter_r <= (others=>'0');
dp_rd_scatter_cnt_r <= (others=>'0');
dp_rd_scatter_vector_r <= (others=>'0');
dp_rd_vaddr_rr <= (others=>'0');
dp_rd_vector_rr <= (others=>'0');
dp_rd_data_flow_rr <= (others=>'0');
dp_rd_data_type_rr <= (others=>'0');
dp_rd_stream_rr <= '0';
dp_rd_stream_id_rr <= (others=>'0');
dp_rd_gen_valid_rr <= '0';
dp_rd_scatter_rr <= (others=>'0');
dp_rd_scatter_cnt_rr <= (others=>'0');
dp_rd_scatter_vector_rr <= (others=>'0');
rd_x1_vector_r <= '0';
rd_x1_vector_rr <= '0';
rd_x1_vaddr_r <= (others=>'0');
rd_x1_vaddr_rr <= (others=>'0');
rd_x2_vector_r <= '0';
rd_x2_vector_rr <= '0';
rd_x2_vaddr_r <= (others=>'0');
rd_x2_vaddr_rr <= (others=>'0');
dp_rd_vector_r <= (others=>'0');
dp_rd_vaddr_r <= (others=>'0');
else
if clock_in'event and clock_in='1' then
dp_rd_gen_valid_r <= dp_rd_gen_valid_in;
dp_rd_data_flow_r <= dp_rd_data_flow_in;
dp_rd_data_type_r <= dp_rd_data_type_in;
dp_rd_stream_r <= dp_rd_stream_in;
dp_rd_stream_id_r <= dp_rd_stream_id_in;
dp_rd_scatter_r <= dp_rd_scatter_in;
dp_rd_scatter_cnt_r <= dp_rd_scatter_cnt_in;
dp_rd_scatter_vector_r <= dp_rd_scatter_vector_in;
dp_rd_vaddr_r <= dp_rd_addr_in(vector_depth_c-1 downto 0);
dp_rd_vector_r <= dp_rd_vector_in;
dp_rd_gen_valid_rr <= dp_rd_gen_valid_r;
dp_rd_data_flow_rr <= dp_rd_data_flow_r;
dp_rd_data_type_rr <= dp_rd_data_type_r;
dp_rd_stream_rr <= dp_rd_stream_r;
dp_rd_stream_id_rr <= dp_rd_stream_id_r;
dp_rd_scatter_rr <= dp_rd_scatter_r;
dp_rd_scatter_cnt_rr <= dp_rd_scatter_cnt_r;
dp_rd_scatter_vector_rr <= dp_rd_scatter_vector_r;
dp_rd_vaddr_rr <= dp_rd_vaddr_r;
dp_rd_vector_rr <= dp_rd_vector_r;
rd_x1_vector_r <= rd_x1_vector_in;
rd_x1_vector_rr <= rd_x1_vector_r;
rd_x1_vaddr_r <= rd_x1_addr_in(vector_depth_c-1 downto 0);
rd_x1_vaddr_rr <= rd_x1_vaddr_r;
rd_x2_vector_r <= rd_x2_vector_in;
rd_x2_vector_rr <= rd_x2_vector_r;
rd_x2_vaddr_r <= rd_x2_addr_in(vector_depth_c-1 downto 0);
rd_x2_vaddr_rr <= rd_x2_vaddr_r;
dp_rd_vector_r <= dp_rd_vector_in;
dp_rd_vaddr_r <= dp_rd_addr_in(vector_depth_c-1 downto 0);
end if;
end if;
end process;
dp_readdata_vm <= dp_readdata_vm1 when dp_readena_vm1='1' else dp_readdata_vm2;
--
-- Single (non-vector read) selection for DP (DataProcessor) access
---
process(dp_rd_vector_rr,dp_readdata_vm,dp_rd_vaddr_rr)
variable t:STD_LOGIC_VECTOR(register_width_c-1 downto 0);
begin
case dp_rd_vaddr_rr is
when "000"=>
dp_encode <= dp_readdata_vm(1*register_width_c-1 downto 0*register_width_c);
when "001"=>
dp_encode <= dp_readdata_vm(2*register_width_c-1 downto 1*register_width_c);
when "010"=>
dp_encode <= dp_readdata_vm(3*register_width_c-1 downto 2*register_width_c);
when "011"=>
dp_encode <= dp_readdata_vm(4*register_width_c-1 downto 3*register_width_c);
when "100"=>
dp_encode <= dp_readdata_vm(5*register_width_c-1 downto 4*register_width_c);
when "101"=>
dp_encode <= dp_readdata_vm(6*register_width_c-1 downto 5*register_width_c);
when "110"=>
dp_encode <= dp_readdata_vm(7*register_width_c-1 downto 6*register_width_c);
when others=>
dp_encode <= dp_readdata_vm(8*register_width_c-1 downto 7*register_width_c);
end case;
end process;
rd_x1_data_vm <= rd_x1_data1_vm1 when rd_enable1_vm1='1' else rd_x1_data1_vm2;
--
-- Single (non-vector read) selection for ALU X1 read access
---
process(rd_x1_vector_r,rd_x1_data_vm,rd_x1_vaddr_rr)
variable t:STD_LOGIC_VECTOR(register_width_c-1 downto 0);
begin
case rd_x1_vaddr_rr is
when "000"=>
q1_encode <= rd_x1_data_vm(1*register_width_c-1 downto 0*register_width_c);
when "001"=>
q1_encode <= rd_x1_data_vm(2*register_width_c-1 downto 1*register_width_c);
when "010"=>
q1_encode <= rd_x1_data_vm(3*register_width_c-1 downto 2*register_width_c);
when "011"=>
q1_encode <= rd_x1_data_vm(4*register_width_c-1 downto 3*register_width_c);
when "100"=>
q1_encode <= rd_x1_data_vm(5*register_width_c-1 downto 4*register_width_c);
when "101"=>
q1_encode <= rd_x1_data_vm(6*register_width_c-1 downto 5*register_width_c);
when "110"=>
q1_encode <= rd_x1_data_vm(7*register_width_c-1 downto 6*register_width_c);
when others=>
q1_encode <= rd_x1_data_vm(8*register_width_c-1 downto 7*register_width_c);
end case;
end process;
rd_x2_data_vm <= rd_x2_data1_vm1 when rd_enable1_vm1='1' else rd_x2_data1_vm2;
--
-- Single (non-vector read) selection for ALU X2 read access
---
process(rd_x2_vector_r,rd_x2_data_vm,rd_x2_vaddr_rr)
variable t:STD_LOGIC_VECTOR(register_width_c-1 downto 0);
begin
case rd_x2_vaddr_rr is
when "000"=>
q2_encode <= rd_x2_data_vm(1*register_width_c-1 downto 0*register_width_c);
when "001"=>
q2_encode <= rd_x2_data_vm(2*register_width_c-1 downto 1*register_width_c);
when "010"=>
q2_encode <= rd_x2_data_vm(3*register_width_c-1 downto 2*register_width_c);
when "011"=>
q2_encode <= rd_x2_data_vm(4*register_width_c-1 downto 3*register_width_c);
when "100"=>
q2_encode <= rd_x2_data_vm(5*register_width_c-1 downto 4*register_width_c);
when "101"=>
q2_encode <= rd_x2_data_vm(6*register_width_c-1 downto 5*register_width_c);
when "110"=>
q2_encode <= rd_x2_data_vm(7*register_width_c-1 downto 6*register_width_c);
when others=>
q2_encode <= rd_x2_data_vm(8*register_width_c-1 downto 7*register_width_c);
end case;
end process;
-------
-- Instantiate register file for process#0
-------
register_file_i: register_file port map(
clock_in =>clock_in,
reset_in =>reset_in,
rd_en_in => rd_en_vm1,
rd_en_out => rd_enable1_vm1,
rd_x1_vector_in => rd_x1_vector_in,
rd_x1_addr_in =>rd_x1_addr_in,
rd_x2_vector_in => rd_x2_vector_in,
rd_x2_addr_in =>rd_x2_addr_in,
rd_x1_data_out =>rd_x1_data1_vm1,
rd_x2_data_out =>rd_x2_data1_vm1,
wr_en_in => wr_en_vm1,
wr_vector_in => wr_vector_in,
wr_addr_in => wr_addr_in,
wr_data_in =>wr_data_in,
wr_lane_in => wr_lane_in,
dp_rd_vector_in => dp_rd_vector_in,
dp_rd_scatter_in => dp_rd_scatter_in,
dp_rd_scatter_cnt_in => dp_rd_scatter_cnt_in,
dp_rd_scatter_vector_in => dp_rd_scatter_vector_in,
dp_rd_gen_valid_in => dp_rd_gen_valid_in,
dp_rd_data_flow_in => dp_rd_data_flow_in,
dp_rd_data_type_in => dp_rd_data_type_in,
dp_rd_stream_in => dp_rd_stream_in,
dp_rd_stream_id_in => dp_rd_stream_id_in,
dp_rd_addr_in => dp_rd_addr_in,
dp_wr_vector_in => dp_wr_vector_in,
dp_wr_addr_in => dp_wr_addr_in,
dp_write_in => dp_write_vm1,
dp_read_in => dp_read_vm1,
dp_writedata_in => dp_writedata_in,
dp_readdata_out => dp_readdata_vm1,
dp_readena_out => dp_readena_vm1
);
-------
-- Instantiate register file for process#1
-------
register_file_i2: register_file port map(
clock_in =>clock_in,
reset_in =>reset_in,
rd_en_in => rd_en_vm2,
rd_en_out => rd_enable1_vm2,
rd_x1_vector_in => rd_x1_vector_in,
rd_x1_addr_in =>rd_x1_addr_in,
rd_x2_vector_in => rd_x2_vector_in,
rd_x2_addr_in =>rd_x2_addr_in,
rd_x1_data_out =>rd_x1_data1_vm2,
rd_x2_data_out =>rd_x2_data1_vm2,
wr_en_in => wr_en_vm2,
wr_vector_in => wr_vector_in,
wr_addr_in => wr_addr_in,
wr_data_in =>wr_data_in,
wr_lane_in => wr_lane_in,
dp_rd_vector_in => dp_rd_vector_in,
dp_rd_scatter_in => dp_rd_scatter_in,
dp_rd_scatter_cnt_in => dp_rd_scatter_cnt_in,
dp_rd_scatter_vector_in => dp_rd_scatter_vector_in,
dp_rd_gen_valid_in => dp_rd_gen_valid_in,
dp_rd_data_flow_in => dp_rd_data_flow_in,
dp_rd_data_type_in => dp_rd_data_type_in,
dp_rd_stream_in => dp_rd_stream_in,
dp_rd_stream_id_in => dp_rd_stream_id_in,
dp_rd_addr_in => dp_rd_addr_in,
dp_wr_vector_in => dp_wr_vector_in,
dp_wr_addr_in => dp_wr_addr_in,
dp_write_in => dp_write_vm2,
dp_read_in => dp_read_vm2,
dp_writedata_in => dp_writedata_in,
dp_readdata_out => dp_readdata_vm2,
dp_readena_out => dp_readena_vm2
);
END behavior;
|
library Common;
use Common.CommonLib.all;
architecture RTL of i2cTransceiver is
-- receiver
signal clDelayed : std_uLogic;
signal daDelayed : std_uLogic;
signal clRising : std_uLogic;
signal clFalling : std_uLogic;
signal daRising : std_uLogic;
signal daFalling : std_uLogic;
signal startCondition : std_uLogic;
signal stopCondition : std_uLogic;
signal bitCounter : unsigned(requiredBitNb(dataBitNb)-1 downto 0);
signal inputShiftReg : std_ulogic_vector(dataBitNb-2 downto 0);
signal clRisingDelayed: std_uLogic;
signal endOfWord : std_uLogic;
signal i2cByteValid : std_uLogic;
signal i2cByte : std_ulogic_vector(dataIn'range);
-- ack
signal ackMoment : std_uLogic;
signal sendAck : std_uLogic;
-- decoder
type rxStateType is (idle, readChipAddress, readRegAddress,
incAddress1, incAddress);
signal rxState : rxStateType;
signal chipAddress : unsigned(chipAddr'range);
signal registerAddress: unsigned(registerAddr'range);
signal writeMode : std_uLogic;
signal loadOutShiftReg: std_uLogic;
signal enSdaOut : std_uLogic;
signal outputShiftReg : std_ulogic_vector(dataBitNb-2-1 downto 0);
begin
--============================================================================
-- start, stop and other conditions
delayInputs: process(reset, clock)
begin
if reset = '1' then
clDelayed <= '1';
daDelayed <= '1';
clRisingDelayed <= '0';
elsif rising_edge(clock) then
clDelayed <= sCl;
daDelayed <= sDaIn;
clRisingDelayed <= clRising;
end if;
end process delayInputs;
clRising <= '1' when (sCl = '1') and (clDelayed = '0') else '0';
clFalling <= '1' when (sCl = '0') and (clDelayed = '1') else '0';
daRising <= '1' when (sDaIn = '1') and (daDelayed = '0') else '0';
daFalling <= '1' when (sDaIn = '0') and (daDelayed = '1') else '0';
startCondition <= '1' when (daFalling = '1') and (sCl = '1') else '0';
stopCondition <= '1' when (daRising = '1') and (sCl = '1') else '0';
------------------------------------------------------------------------------
-- bit counter
countBitNb: process(reset, clock)
begin
if reset = '1' then
bitCounter <= (others => '0');
elsif rising_edge(clock) then
if startCondition = '1' then
bitCounter <= (others => '0');
elsif stopCondition = '1' then
bitCounter <= (others => '0');
elsif clFalling = '1' then
if bitCounter < dataBitNb-1 then
bitCounter <= bitCounter + 1;
else
bitCounter <= to_unsigned(1, bitCounter'length);
end if;
end if;
end if;
end process countBitNb;
endOfWord <= '1' when (clRisingDelayed = '1') and (bitCounter = dataBitNb-1)
else '0';
--============================================================================
-- input shift register
shiftInputBits: process(reset, clock)
begin
if reset = '1' then
inputShiftReg <= (others => '0');
elsif rising_edge(clock) then
if clRising = '1' then
inputShiftReg(inputShiftReg'high downto 1) <= inputShiftReg(inputShiftReg'high-1 downto 0);
inputShiftReg(0) <= sDaIn;
end if;
end if;
end process shiftInputBits;
------------------------------------------------------------------------------
-- read byte from shift register
i2cByteValid <= '1' when (bitCounter = i2cByte'length) and (clFalling = '1')
else '0';
i2cByte <= inputShiftReg(i2cByte'range);
storeByte: process(reset, clock)
begin
if reset = '1' then
dataIn <= (others => '0');
elsif rising_edge(clock) then
if i2cByteValid = '1' then
dataIn <= i2cByte;
end if;
end if;
end process storeByte;
--============================================================================
-- address extraction
rxFsm: process(reset, clock)
begin
if reset = '1' then
rxState <= idle;
elsif rising_edge(clock) then
if stopCondition = '1' then
rxState <= idle;
elsif startCondition = '1' then
rxState <= readChipAddress;
elsif endOfWord = '1' then
case rxState is
when readChipAddress =>
if writeMode = '1' then
rxState <= readRegAddress;
else
rxState <= incAddress1;
end if;
when readRegAddress =>
rxState <= incAddress1;
when incAddress1 =>
rxState <= incAddress;
when incAddress =>
if (writeMode = '0') and (sDaIn = '1') then
rxState <= idle;
end if;
when others => null;
end case;
end if;
end if;
end process rxFsm;
dataValid <= endOfWord when (rxState = incAddress1) or (rxState = incAddress)
else '0';
------------------------------------------------------------------------------
-- provide running i2c address
updateAddress: process(reset, clock)
begin
if reset = '1' then
chipAddress <= (others => '0');
registerAddress <= (others => '0');
writeMode <= '0';
elsif rising_edge(clock) then
if i2cByteValid = '1' then
case rxState is
when readChipAddress =>
chipAddress <= resize(
shift_right(unsigned(i2cByte), 1),
chipAddress'length
);
if i2cByte(0) = '0' then -- i2cByte(0)=0 -> master write to slave
writeMode <= '1';
else
writeMode <= '0';
registerAddress <= registerAddress + 1;
end if;
when readRegAddress =>
registerAddress <= resize(unsigned(i2cByte)-1, registerAddress'length);
when incAddress1 | incAddress =>
registerAddress <= registerAddress + 1;
when others => null;
end case;
end if;
end if;
end process updateAddress;
chipAddr <= chipAddress;
registerAddr <= registerAddress;
writeData <= writeMode;
------------------------------------------------------------------------------
-- acknowledge
findAckMoment: process(reset, clock)
begin
if reset = '1' then
ackMoment <= '0';
sendAck <= '0';
elsif rising_edge(clock) then
if (bitCounter = dataBitNb-2) and (clFalling = '1') then
ackMoment <= '1';
elsif clFalling = '1' then
ackMoment <= '0';
end if;
if ackMoment = '0' then
sendAck <= '0';
elsif isSelected = '1' then
if writeMode = '1' then
sendAck <= '1';
elsif rxState = readChipAddress then
sendAck <= '1';
end if;
end if;
end if;
end process findAckMoment;
--============================================================================
-- output controls
controlAnswering: process(reset, clock)
begin
if reset = '1' then
loadOutShiftReg <= '0';
enSdaOut <= '0';
elsif rising_edge(clock) then
if endOfWord = '1' then
loadOutShiftReg <= '1';
elsif clRising = '1' then
loadOutShiftReg <= '0';
end if;
if
(bitCounter = 1) and
( (rxState = incAddress1) or (rxState = incAddress) ) and
(writeMode = '0')
then
if sDaIn /= '0' then -- let master finish ack pulse
enSdaOut <= '1';
end if;
elsif ( (bitCounter = dataBitNb-2) and (clFalling = '1') ) or (rxState = idle) then
enSdaOut <= '0';
end if;
end if;
end process controlAnswering;
------------------------------------------------------------------------------
-- output shift register
shiftOutputBits: process(reset, clock)
begin
if reset = '1' then
outputShiftReg <= (others => '0');
elsif rising_edge(clock) then
if loadOutShiftReg = '1' then
outputShiftReg <= (others => '1');
outputShiftReg(dataOut'range) <= dataOut;
elsif clFalling = '1' then
outputShiftReg(outputShiftReg'high downto 1) <= outputShiftReg(outputShiftReg'high-1 downto 0);
outputShiftReg(0) <= '0';
end if;
end if;
end process shiftOutputBits;
------------------------------------------------------------------------------
-- reply to read request
sDaOut <= '0' when sendAck = '1'
else outputShiftReg(outputShiftReg'high) when enSdaOut = '1'
else '1';
end RTL;
|
<gh_stars>10-100
-- Copyright 2018 Delft University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.TestCase_pkg.all;
-- This package provides a means for universal inter-process communication
-- through (global) shared variables.
package SimDataComms_pkg is
-- Types supported by SimComms; that is, these primitive data types can be
-- transferred, everything else must be serialized to a string.
type variant_enum is (
SCV_NULL, -- No data.
SCV_SENT, -- The first entry in a dictionary list, serving as a sentinel
-- to prevent empty dictionaries. Does not contain data.
SCV_DICT, -- Dictionary type.
SCV_STR, -- Leaf node with raw string data.
SCV_SLV, -- Leaf node with std_logic_vector data encoded as a string.
SCV_STD, -- Leaf node with std_logic data encoded as a string.
SCV_BOOL, -- Leaf node with boolean data encoded as a string.
SCV_INT, -- Leaf node with integer data encoded as a string.
SCV_TIME -- Leaf node with time data encoded as a string.
);
-- This object implements arbitrary communication through a shared variable.
-- Conceptually, the contained data is encapsulated in the form of
-- dictionaries and queues of a number of VHDL data types. Data is indexed
-- using key strings, using . as a hierarchy separator; each entry in the
-- key string indexes the next dictionary.
type sc_data_type is protected
-- Data setters. key is a period-separated hierarchical name. If no data
-- exists yet for the specified key, it is created. If the key maps to a
-- queue, the data is written to the tail of the queue.
procedure set_str (key: string; data: string);
procedure set_slv (key: string; data: std_logic_vector);
procedure set_uns (key: string; data: unsigned);
procedure set_sgn (key: string; data: signed);
procedure set_std (key: string; data: std_logic);
procedure set_bool(key: string; data: boolean);
procedure set_int (key: string; data: integer);
procedure set_time(key: string; data: time);
-- Data getters. key is a period-separated hierarchical name. If no data
-- exists yet for the specified key or the type is wrong, simulation is
-- halted with an error message. If the key maps to a queue, the data is
-- read from the head of the queue.
impure function get_str (key: string) return string;
impure function get_slv (key: string) return std_logic_vector;
impure function get_uns (key: string) return unsigned;
impure function get_sgn (key: string) return signed;
impure function get_std (key: string) return std_logic;
impure function get_bool(key: string) return boolean;
impure function get_int (key: string) return integer;
impure function get_time(key: string) return time;
-- Same as above, with one exception: If no data exists for the given key,
-- the default is returned instead of simulation halting.
impure function get_str (key: string; def: string) return string;
impure function get_slv (key: string; def: std_logic_vector) return std_logic_vector;
impure function get_uns (key: string; def: unsigned) return unsigned;
impure function get_sgn (key: string; def: signed) return signed;
impure function get_std (key: string; def: std_logic) return std_logic;
impure function get_bool(key: string; def: boolean) return boolean;
impure function get_int (key: string; def: integer) return integer;
impure function get_time(key: string; def: time) return time;
-- Type getter. Returns the type of the given key, or SCV_NULL if it does
-- not exist.
impure function get_type(key: string) return variant_enum;
impure function exists (key: string) return boolean;
-- Deletes a mapping. Traverses by moving to the head of queues (like
-- getters). No-op when a key does not exist.
procedure delete (key: string);
-- Copies data from one key to another. This can essentially be used to set
-- entire mappings at once. Destination key traversal works like setters,
-- source key traversal works like getters.
procedure copy (src: string; dest: string);
-- Returns whether the specified key is associated with more than one data
-- entry, making it a queue. Traverses by moving to the head of queues
-- (like getters).
impure function is_queue(key: string) return boolean;
-- Pushes/pops data to/from a queue. When traversing the hierarchy, push
-- moves to the tail of parent queues (like setters) and pop moves to the
-- head (like getters). fwd combines a pop and a push by pushing the popped
-- entry to a different queue instead of deallocating it. pop with a second
-- key is like fwd, but copies the popped entry to dest without pushing
-- (allowing data to be added to it before the push).
procedure push (key: string);
procedure pop (key: string);
procedure pop (src: string; dest: string);
procedure fwd (src: string; dest: string);
-- Dump the contents of the simcomms object to stdout for debugging.
procedure dump;
-- Frees all dynamically allocated memory, checking for memory leaks.
procedure reset;
end protected sc_data_type;
end package SimDataComms_pkg;
package body SimDataComms_pkg is
-- String pointer type.
type string_ptr is access string;
-- Variant type. Variants form the basis of the communication system. They
-- are basically multi-dimensional linked lists; whenever additional data
-- is needed somewhere (like a new queue entry, or a new bit of data
-- associated with a dictionary) it is newly allocated and appended to one
-- of the linked lists.
type variant_type;
type variant_ptr is access variant_type;
type variant_type is record
-- Link to next dictionary entry, or null if end of list.
link : variant_ptr;
-- Link to previous dictionary entry, or the dictionary definition if
-- start of list.
rlink : variant_ptr;
-- Dictionary entry name.
name : string_ptr;
-- Type information for this entry.
typ : variant_enum;
-- Leaf data when typ is SCV_DICT.
dict : variant_ptr;
-- Leaf data when typ is SCV_STR or SCV_SLV.
str : string_ptr;
-- Leaf data when typ is SCV_STD, SCV_BOOL, or SCV_INT.
int : integer;
-- Leaf data when typ is SCV_TIME.
tim : time;
-- Next queue entry. link, rlink, and name are invalid for queue entries,
-- only the values are used. Data setters should iterate to the end of the
-- queue before writing; data getters should not do that. Push and pop
-- add/remove queue entries.
queue : variant_ptr;
end record;
-- This object implements arbitrary communication through a shared variable.
-- Conceptually, the contained data is encapsulated in the form of
-- dictionaries and queues of a number of VHDL data types. Data is indexed
-- using key strings, using . as a hierarchy separator; each entry in the
-- key string indexes the next dictionary.
type sc_data_type is protected body
--#########################################################################
-- Private entries.
--#########################################################################
-- Root node. This always has the SCV_DICT type when initialized.
variable root : variant_ptr := null;
-- Allocation counters for debugging. These are incremented on allocation
-- and decremented on deallocation to allow memory leak checks to be
-- performed.
variable allocs_variant : integer := 0;
variable allocs_string : integer := 0;
-- Forward declaration for clearing/deallocating entries.
procedure clear_leaf(ent: inout variant_ptr);
procedure clear_data(ent: inout variant_ptr);
procedure clear_entry(ent: inout variant_ptr);
-- Traverses into the hierarchy by exactly one level, using ent as the
-- starting point and output. ent is the dictionary definition; so
-- ent.all.dict is the first entry (if there is one). If set is true, the
-- key is created if it does not exist yet, and queues are traversed before
-- entering the next dictionary. If set is false, ent will be null if the
-- key does not exist yet.
procedure traverse_single(keypart: string; set: boolean; ent: inout variant_ptr) is
begin
-- Check input.
tc_check_nw(ent /= null, "Traversing into null variant");
tc_check_nw(ent.all.typ = SCV_SENT, "Traversing into non-dict variant");
-- Loop through the linkedlist representing the dictionary. We start at
-- the sentinel entry, so the first thing we should do is move to the
-- next entry (if there is one).
loop
if ent.all.link /= null then
-- Go to the next entry.
ent := ent.all.link;
-- Check if this is the entry we're looking for.
tc_check_nw(ent.all.name /= null, "Variant has null name");
exit when ent.all.name.all = keypart;
else
-- We're at the end of the linkedlist, so the requested entry doesn't
-- exist.
if set then
-- We're setting; create the new entry.
ent.all.link := new variant_type'(
link => null,
rlink => ent,
name => new string'(keypart),
typ => SCV_NULL,
dict => null,
str => null,
int => 0,
tim => 0 ns,
queue => null
);
allocs_variant := allocs_variant + 1;
allocs_string := allocs_string + 1;
ent := ent.all.link;
exit;
else
-- We're getting; return null.
ent := null;
return;
end if;
end if;
end loop;
-- Self-test: the current entry must always have the requested name.
tc_check_nw(ent.all.name.all = keypart, "Variant has null name");
-- ent now points to the entry we're looking for. But if we're setting,
-- we also need to traverse into the queue to get to the tail.
while set and ent.all.queue /= null loop
ent := ent.all.queue;
end loop;
end procedure;
-- Like traverse, but handles the full key string.
procedure traverse(key: string; set: boolean; result: out variant_ptr) is
variable ent : variant_ptr;
variable first : natural;
variable last : natural;
begin
-- Initialize ourselves if we haven't yet.
if root = null then
root := new variant_type'(
link => null,
rlink => null,
name => new string'("*"),
typ => SCV_DICT,
dict => new variant_type'(
link => null,
rlink => null,
name => null,
typ => SCV_SENT,
dict => null,
str => null,
int => 0,
tim => 0 ns,
queue => null
),
str => null,
int => 0,
tim => 0 ns,
queue => null
);
allocs_variant := allocs_variant + 2;
allocs_string := allocs_string + 1;
end if;
-- Start traversal at the sentinel of the root dictionary.
ent := root.all.dict;
first := key'low;
last := key'low;
while first <= key'high loop
-- Move the last character pointer until last+1 is a period or lies
-- beyond the string.
loop
exit when last = key'high;
exit when key(last+1) = '.';
last := last + 1;
end loop;
-- key(first to last) is now the current section between periods.
traverse_single(key(first to last), set, ent);
-- Return immediately if ent is null; this means the key does not
-- exist. Note that traverse_single should be creating it if set is
-- true.
if ent = null then
result := null;
return;
end if;
-- Move the first/last pointers beyond the period.
first := last + 2;
last := last + 2;
-- If we're not done traversing, the new node should be a dictionary
-- and we should move into it.
if first <= key'high then
-- If the returned entry is not a dictionary, turn it into one.
if ent.all.typ /= SCV_DICT then
clear_data(ent);
ent.all.typ := SCV_DICT;
ent.all.dict := new variant_type'(
link => null,
rlink => null,
name => null,
typ => SCV_SENT,
dict => null,
str => null,
int => 0,
tim => 0 ns,
queue => null
);
allocs_variant := allocs_variant + 1;
end if;
-- Enter the dictionary.
ent := ent.all.dict;
end if;
end loop;
-- Return the node we found.
result := ent;
end procedure;
-- Deletes leaf data (dict and str) contained by the given entry and resets
-- its type to SCV_NULL.
procedure clear_leaf(ent: inout variant_ptr) is
variable ent2 : variant_ptr;
begin
if ent = null then
return;
end if;
-- Delete dict data by removing the first entry until no entries remain.
-- Then remove the sentinel manually.
if ent.all.dict /= null then
while ent.all.dict.all.link /= null loop
ent2 := ent.all.dict.all.link;
clear_entry(ent2);
end loop;
deallocate(ent.all.dict);
allocs_variant := allocs_variant - 1;
ent.all.dict := null;
end if;
-- Delete string data.
if ent.all.str /= null then
deallocate(ent.all.str);
allocs_string := allocs_string - 1;
ent.all.str := null;
end if;
-- Clear static entries.
ent.all.typ := SCV_NULL;
ent.all.int := 0;
ent.all.tim := 0 ns;
end procedure;
-- Deletes all data (dict, str, and queue) contained by the given entry and
-- resets its type to SCV_NULL.
procedure clear_data(ent: inout variant_ptr) is
variable ent2 : variant_ptr;
begin
if ent = null then
return;
end if;
-- Clear leaf data.
clear_leaf(ent);
-- Delete queue data recursively.
if ent.all.queue /= null then
ent2 := ent.all.queue;
clear_entry(ent2);
ent.all.queue := null;
end if;
end procedure;
-- Deletes a variant constituting a map entry (queue entries should NOT be
-- passed to this!).
procedure clear_entry(ent: inout variant_ptr) is
begin
if ent = null then
return;
end if;
clear_data(ent);
if ent.all.rlink /= null then
ent.all.rlink.all.link := ent.all.link;
end if;
if ent.all.link /= null then
ent.all.link.all.rlink := ent.all.rlink;
end if;
if ent.all.name /= null then
deallocate(ent.all.name);
allocs_string := allocs_string - 1;
end if;
deallocate(ent);
allocs_variant := allocs_variant - 1;
end procedure;
procedure dump_str(str: string) is
variable ln : std.textio.line;
begin
ln := new string'(str);
writeline(std.textio.output, ln);
if ln /= null then
deallocate(ln);
end if;
end procedure;
-- Internal dump function; dumps an entry with a specified amount of
-- indentation.
procedure dump_entry(ent: inout variant_ptr; indent: string) is
variable qent : variant_ptr;
variable ment : variant_ptr;
begin
if ent = null then
dump_str(indent & "<NULL!>");
return;
end if;
if ent.all.name = null then
dump_str(indent & " - name: <NULL!>");
else
dump_str(indent & " - name: " & ent.all.name.all);
end if;
qent := ent;
while qent /= null loop
dump_str(indent & " type: " & variant_enum'image(qent.all.typ));
case qent.all.typ is
when SCV_NULL =>
null;
when SCV_SENT =>
null;
when SCV_DICT =>
dump_str(indent & " val:");
ment := qent.all.dict;
tc_check_nw(ment /= null, "Empty dict without sentinel");
tc_check_nw(ment.all.typ = SCV_SENT, "Nonempty dict without sentinel");
while ment.all.link /= null loop
if ment.all.link.all.rlink /= ment then
dump_str(indent & " ### RLINK INCONSISTENT ###");
end if;
ment := ment.all.link;
dump_entry(ment, indent & " ");
end loop;
when SCV_STR | SCV_SLV =>
if qent.all.str = null then
dump_str(indent & " val: <NULL!>");
else
dump_str(indent & " val: """ & qent.all.str.all & """");
end if;
when SCV_STD =>
dump_str(indent & " val: " & std_logic'image(std_logic'val(qent.all.int)));
when SCV_BOOL =>
dump_str(indent & " val: " & boolean'image(boolean'val(qent.all.int)));
when SCV_INT =>
dump_str(indent & " val: " & integer'image(qent.all.int));
when SCV_TIME =>
dump_str(indent & " val: " & time'image(qent.all.tim));
end case;
qent := qent.all.queue;
if qent /= null then
dump_str(indent & " ~~~~~");
end if;
end loop;
end procedure;
--#########################################################################
-- Data setters. key is a period-separated hierarchical name. If no data
-- exists yet for the specified key, it is created. If the key maps to a
-- queue, the data is written to the tail of the queue.
--#########################################################################
procedure set_str(key: string; data: string) is
variable ent : variant_ptr;
begin
traverse(key, true, ent);
clear_data(ent);
ent.all.typ := SCV_STR;
ent.all.str := new string'(data);
allocs_string := allocs_string + 1;
end procedure;
procedure set_slv(key: string; data: std_logic_vector) is
variable ent : variant_ptr;
variable str : string(1 to data'length);
variable si : natural;
begin
si := 1;
for i in data'range loop
case data(i) is
when 'U' => str(si) := 'U';
when 'X' => str(si) := 'X';
when '0' => str(si) := '0';
when '1' => str(si) := '1';
when 'Z' => str(si) := 'Z';
when 'W' => str(si) := 'W';
when 'L' => str(si) := 'L';
when 'H' => str(si) := 'H';
when '-' => str(si) := '-';
end case;
si := si + 1;
end loop;
traverse(key, true, ent);
clear_data(ent);
ent.all.typ := SCV_SLV;
ent.all.str := new string'(str);
allocs_string := allocs_string + 1;
end procedure;
procedure set_uns(key: string; data: unsigned) is
begin
set_slv(key, std_logic_vector(data));
end procedure;
procedure set_sgn(key: string; data: signed) is
begin
set_slv(key, std_logic_vector(data));
end procedure;
procedure set_std(key: string; data: std_logic) is
variable ent : variant_ptr;
begin
traverse(key, true, ent);
clear_data(ent);
ent.all.typ := SCV_STD;
ent.all.int := std_logic'pos(data);
end procedure;
procedure set_bool(key: string; data: boolean) is
variable ent : variant_ptr;
begin
traverse(key, true, ent);
clear_data(ent);
ent.all.typ := SCV_BOOL;
ent.all.int := boolean'pos(data);
end procedure;
procedure set_int(key: string; data: integer) is
variable ent : variant_ptr;
begin
traverse(key, true, ent);
clear_data(ent);
ent.all.typ := SCV_INT;
ent.all.int := data;
end procedure;
procedure set_time(key: string; data: time) is
variable ent : variant_ptr;
begin
traverse(key, true, ent);
clear_data(ent);
ent.all.typ := SCV_TIME;
ent.all.tim := data;
end procedure;
--#########################################################################
-- Data getters. key is a period-separated hierarchical name. If no data
-- exists yet for the specified key or the type is wrong, simulation is
-- halted with an error message. If the key maps to a queue, the data is
-- read from the head of the queue.
--#########################################################################
impure function get_str(key: string) return string is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
tc_check_nw(ent /= null, key & " is not defined");
tc_check_nw(ent.all.typ = SCV_STR, key & " is not a string");
return ent.all.str.all;
end function;
-- Private helper function for get_slv, needed to figure out vector length
-- at function elaboration time.
impure function get_slv_str(key: string) return string is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
tc_check_nw(ent /= null, key & " is not defined");
tc_check_nw(ent.all.typ = SCV_SLV, key & " is not an std_logic_vector-like");
return ent.all.str.all;
end function;
impure function get_slv(key: string) return std_logic_vector is
constant str : string := get_slv_str(key);
variable slv : std_logic_vector(str'length - 1 downto 0);
variable si : natural;
begin
si := 1;
for i in slv'range loop
case str(si) is
when 'U' => slv(i) := 'U';
when 'X' => slv(i) := 'X';
when '0' => slv(i) := '0';
when '1' => slv(i) := '1';
when 'Z' => slv(i) := 'Z';
when 'W' => slv(i) := 'W';
when 'L' => slv(i) := 'L';
when 'H' => slv(i) := 'H';
when '-' => slv(i) := '-';
when others => tc_fail_nw("Invalid character in std_logic_vector string");
end case;
si := si + 1;
end loop;
return slv;
end function;
impure function get_uns(key: string) return unsigned is
begin
return unsigned(get_slv(key));
end function;
impure function get_sgn(key: string) return signed is
begin
return signed(get_slv(key));
end function;
impure function get_std(key: string) return std_logic is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
tc_check_nw(ent /= null, key & " is not defined");
tc_check_nw(ent.all.typ = SCV_STD, key & " is not an std_logic");
return std_logic'val(ent.all.int);
end function;
impure function get_bool(key: string) return boolean is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
tc_check_nw(ent /= null, key & " is not defined");
tc_check_nw(ent.all.typ = SCV_BOOL, key & " is not a boolean");
return boolean'val(ent.all.int);
end function;
impure function get_int(key: string) return integer is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
tc_check_nw(ent /= null, key & " is not defined");
tc_check_nw(ent.all.typ = SCV_INT, key & " is not an integer");
return ent.all.int;
end function;
impure function get_time(key: string) return time is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
tc_check_nw(ent /= null, key & " is not defined");
tc_check_nw(ent.all.typ = SCV_TIME, key & " is not a time");
return ent.all.tim;
end function;
--#########################################################################
-- Same as above, with one exception: If no data exists for the given key,
-- the default is returned instead of simulation halting.
--#########################################################################
impure function get_str(key: string; def: string) return string is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
if ent = null then
return def;
end if;
tc_check_nw(ent.all.typ = SCV_STR, key & " is not a string");
return ent.all.str.all;
end function;
-- Private helper function for get_slv, needed to figure out vector length
-- at function elaboration time.
impure function get_slv_str(key: string; def: string) return string is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
if ent = null then
return def;
end if;
tc_check_nw(ent.all.typ = SCV_SLV, key & " is not an std_logic_vector-like");
return ent.all.str.all;
end function;
impure function get_slv(key: string; def: std_logic_vector) return std_logic_vector is
constant str : string := get_slv_str(key, "null");
variable slv : std_logic_vector(str'length - 1 downto 0);
variable si : natural;
begin
if str = "null" then
return def;
end if;
si := 1;
for i in slv'range loop
case str(si) is
when 'U' => slv(i) := 'U';
when 'X' => slv(i) := 'X';
when '0' => slv(i) := '0';
when '1' => slv(i) := '1';
when 'Z' => slv(i) := 'Z';
when 'W' => slv(i) := 'W';
when 'L' => slv(i) := 'L';
when 'H' => slv(i) := 'H';
when '-' => slv(i) := '-';
when others => tc_fail_nw("Invalid character in std_logic_vector string");
end case;
si := si + 1;
end loop;
return slv;
end function;
impure function get_uns(key: string; def: unsigned) return unsigned is
begin
return unsigned(get_slv(key, std_logic_vector(def)));
end function;
impure function get_sgn(key: string; def: signed) return signed is
begin
return signed(get_slv(key, std_logic_vector(def)));
end function;
impure function get_std(key: string; def: std_logic) return std_logic is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
if ent = null then
return def;
end if;
tc_check_nw(ent.all.typ = SCV_STD, key & " is not an std_logic");
return std_logic'val(ent.all.int);
end function;
impure function get_bool(key: string; def: boolean) return boolean is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
if ent = null then
return def;
end if;
tc_check_nw(ent.all.typ = SCV_BOOL, key & " is not a boolean");
return boolean'val(ent.all.int);
end function;
impure function get_int(key: string; def: integer) return integer is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
if ent = null then
return def;
end if;
tc_check_nw(ent.all.typ = SCV_INT, key & " is not an integer");
return ent.all.int;
end function;
impure function get_time(key: string; def: time) return time is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
if ent = null then
return def;
end if;
tc_check_nw(ent.all.typ = SCV_TIME, key & " is not a time");
return ent.all.tim;
end function;
--#########################################################################
-- Type getter. Returns the type of the given key, or SCV_NULL if it does
-- not exist.
--#########################################################################
impure function get_type(key: string) return variant_enum is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
if ent = null then
return SCV_NULL;
end if;
return ent.all.typ;
end function;
impure function exists(key: string) return boolean is
begin
return get_type(key) /= SCV_NULL;
end function;
--#########################################################################
-- Deletes a mapping. Traverses by moving to the head of queues (like
-- getters). No-op when a key does not exist.
--#########################################################################
procedure delete(key: string) is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
clear_entry(ent);
end procedure;
--#########################################################################
-- Copies data from one key to another. This can essentially be used to set
-- entire mappings at once. Destination key traversal works like setters,
-- source key traversal works like getters.
--#########################################################################
-- Internal function used by copy. Deep-copies the contents of sent (source
-- entry) to dent (destination entry), leaving map entry metadata (link,
-- rlink, and name intact).
procedure copy_entry(sent: inout variant_ptr; dent: inout variant_ptr) is
variable sqent : variant_ptr;
variable dqent : variant_ptr;
variable sment : variant_ptr;
variable dment : variant_ptr;
begin
-- Iterate over queue entries, including the current one.
sqent := sent;
dqent := dent;
while sqent /= null loop
-- Copy static information.
dqent.all.typ := sqent.all.typ;
dqent.all.int := sqent.all.int;
dqent.all.tim := sqent.all.tim;
-- Make a copy of the string data if it exists.
if sqent.all.str /= null then
dqent.all.str := new string'(sqent.all.str.all);
allocs_string := allocs_string + 1;
else
dqent.all.str := null;
end if;
-- Make a copy of the map data if it exists.
if sqent.all.dict /= null then
dqent.all.dict := new variant_type'(
link => null,
rlink => null,
name => null,
typ => SCV_SENT,
dict => null,
str => null,
int => 0,
tim => 0 ns,
queue => null
);
allocs_variant := allocs_variant + 1;
sment := sqent.all.dict;
dment := dqent.all.dict;
while sment.all.link /= null loop
dment.all.link := new variant_type'(
link => null,
rlink => dment,
name => null,
typ => SCV_NULL,
dict => null,
str => null,
int => 0,
tim => 0 ns,
queue => null
);
allocs_variant := allocs_variant + 1;
dment := dment.all.link;
sment := sment.all.link;
if sment.all.name /= null then
dment.all.name := new string'(sment.all.name.all);
allocs_string := allocs_string + 1;
else
dment.all.name := null;
end if;
copy_entry(sment, dment);
end loop;
else
dqent.all.dict := null;
end if;
-- Make a copy of the next queue entry if it exists.
if sqent.all.queue /= null then
dqent.all.queue := new variant_type'(
link => null,
rlink => null,
name => null,
typ => SCV_NULL,
dict => null,
str => null,
int => 0,
tim => 0 ns,
queue => null
);
allocs_variant := allocs_variant + 1;
else
dqent.all.queue := null;
end if;
-- Move to the next queue entry.
sqent := sqent.all.queue;
dqent := dqent.all.queue;
end loop;
end procedure;
procedure copy(src: string; dest: string) is
variable sent : variant_ptr;
variable dent : variant_ptr;
begin
traverse(src, false, sent);
tc_check_nw(sent /= null, src & " is not defined");
traverse(dest, true, dent);
clear_data(dent);
copy_entry(sent, dent);
end procedure;
--#########################################################################
-- Returns whether the specified key is associated with more than one data
-- entry, making it a queue. Traverses by moving to the head of queues
-- (like getters).
--#########################################################################
impure function is_queue(key: string) return boolean is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
if ent = null then
return false;
end if;
return ent.all.queue /= null;
end function;
--#########################################################################
-- Pushes/pops data to/from a queue. When traversing the hierarchy, push
-- moves to the tail of parent queues(like setters) and pop moves to the
-- head(like getters).
--#########################################################################
-- Private procedure that performs the bulk of the pop operation. ent must
-- be the head of a non-empty queue. It is detached from the queue, but not
-- deallocated.
procedure detach(ent : inout variant_ptr) is
begin
-- name
-- ^
-- |
-- .-----------. link .-----. link ............
-- | ent.rlink |------->| ent |------->: ent.link :
-- | |<-------| |<-------: (null?) :
-- '-----------' rlink '-----' rlink ''''''''''''
-- |
-- | queue
-- | name
-- v .---0
-- .-----------.
-- | ent.queue |--0
-- 0--| |
-- '-----------'
-- |
-- | queue
-- v
-- null?
ent.all.rlink.all.link := ent.all.queue;
if ent.all.link /= null then
ent.all.link.all.rlink := ent.all.queue;
end if;
-- name
-- ^
-- |
-- .-----------. .-----. link ............
-- | ent.rlink | | ent |------->: ent.link :
-- | |<-------| | : (null?) :
-- '-----------' rlink '-----' ''''''''''''
-- | | |
-- | | queue |
-- | | name |
-- | v .---0 |
-- | link .-----------. |
-- '--------->| ent.queue |--0 |
-- 0--| |<----------'
-- '-----------' rlink
-- |
-- | queue
-- v
-- null?
ent.all.queue.all.link := ent.all.link;
ent.all.queue.all.rlink := ent.all.rlink;
-- name
-- ^
-- |
-- .-----------. .-----. link ............
-- | ent.rlink | | ent |------->: ent.link :
-- | |<-------| | : (null?) :
-- '-----------' rlink '-----' ''''''''''''
-- ^ | | ^ |
-- | | | queue | |
-- | | | name | |
-- | | v .---0 | |
-- | | link .-----------. link | |
-- | '--------->| ent.queue |---------' |
-- '------------| |<----------'
-- rlink '-----------' rlink
-- |
-- | queue
-- v
-- null?
ent.all.queue.all.name := ent.all.name;
ent.all.name := null;
-- 0
-- ^
-- name |
-- .-----------. .-----. link ............
-- | ent.rlink | | ent |------->: ent.link :
-- | |<-------| | : (null?) :
-- '-----------' rlink '-----' ''''''''''''
-- ^ | | ^ |
-- | | | queue | |
-- | | | | |
-- | | v .-->name | |
-- | | link .-----------. link | |
-- | '--------->| ent.queue |---------' |
-- '------------| |<----------'
-- rlink '-----------' rlink
-- |
-- | queue
-- v
-- null?
ent.all.rlink := null;
ent.all.link := null;
ent.all.queue := null;
ent.all.name := null;
-- 0
-- ^
-- |
-- .-----------. .-----. ............
-- | ent.rlink | | ent |--0 : ent.link :
-- | | 0--| | : (null?) :
-- '-----------' '-----' ''''''''''''
-- ^ | | ^ |
-- | | 0 | |
-- | | name | |
-- | | .-->name | |
-- | | link .-----------. link | |
-- | '--------->| ent.queue |---------' |
-- '------------| |<----------'
-- rlink '-----------' rlink
-- |
-- | queue
-- v
-- null?
end procedure;
procedure push(key: string) is
variable ent : variant_ptr;
begin
traverse(key, true, ent);
assert ent.all.queue = null
report "Setter traversal resulted in entry with non-null queue"
severity failure;
ent.all.queue := new variant_type'(
link => null, -- unused
rlink => null, -- unused
name => null, -- unused
typ => SCV_NULL,
dict => null,
str => null,
int => 0,
tim => 0 ns,
queue => null
);
allocs_variant := allocs_variant + 1;
end procedure;
procedure pop(key: string) is
variable ent : variant_ptr;
begin
traverse(key, false, ent);
tc_check_nw(ent /= null, key & " is not defined");
tc_check_nw(ent.all.rlink /= null, key & " rlink is missing");
tc_check_nw(ent.all.queue /= null, "pop from empty queue " & key);
detach(ent);
clear_entry(ent);
end procedure;
-- Private procedure implementing the common part of pop(s,d) and fwd.
procedure fwd_int(src: string; dest: string; sent: inout variant_ptr; dent: inout variant_ptr) is
begin
-- Prepare source.
traverse(src, false, sent);
tc_check_nw(sent /= null, src & " is not defined");
tc_check_nw(sent.all.rlink /= null, src & " rlink is missing");
tc_check_nw(sent.all.queue /= null, "pop from empty queue " & src);
-- Prepare destination.
traverse(dest, true, dent);
assert dent.all.queue = null
report "Setter traversal resulted in entry with non-null queue"
severity failure;
-- Detach the head of the source queue.
detach(sent);
-- Write source to dest.
clear_data(dent);
dent.all.typ := sent.all.typ;
dent.all.dict := sent.all.dict;
dent.all.str := sent.all.str;
dent.all.int := sent.all.int;
dent.all.tim := sent.all.tim;
end procedure;
procedure pop(src: string; dest: string) is
variable sent : variant_ptr;
variable dent : variant_ptr;
begin
fwd_int(src, dest, sent, dent);
-- We don't need the source entry anymore, so deallocate it.
deallocate(sent);
allocs_variant := allocs_variant - 1;
end procedure;
procedure fwd(src: string; dest: string) is
variable sent : variant_ptr;
variable dent : variant_ptr;
begin
fwd_int(src, dest, sent, dent);
-- Now we need to push dent and deallocate sent. Kill two birds with one
-- stone by reusing sent instead of deallocating it and then allocating a
-- new variant for dent. link, rlink, name, and queue should already be
-- null after detach().
dent.all.queue := sent;
sent.all.typ := SCV_NULL;
sent.all.dict := null;
sent.all.str := null;
sent.all.int := 0;
sent.all.tim := 0 ns;
end procedure;
--#########################################################################
-- Dump the contents of the simcomms object to stdout for debugging.
--#########################################################################
procedure dump is
begin
dump_entry(root, "");
end procedure;
--#########################################################################
-- Frees all dynamically allocated memory, checking for memory leaks.
--#########################################################################
procedure reset is
begin
if root /= null then
clear_entry(root);
root := null;
assert allocs_string = 0 and allocs_variant = 0
report "SimComms object leaked " & integer'image(allocs_string) &
" string(s) and " & integer'image(allocs_variant) & " variant(s)!"
severity failure;
end if;
end procedure;
end protected body sc_data_type;
end package body SimDataComms_pkg;
|
----------------------------------------------------------------------------
--
-- Revision: $Revision: 1506 $
-- Date: $Date: 2009-04-25 23:51:56 -0700 (Sat, 25 Apr 2009) $
--
-- Copyright (c) 2004, 2008, 2009 The SPIRIT Consortium.
--
-- This work forms part of a deliverable of The SPIRIT Consortium.
--
-- Use of these materials are governed by the legal terms and conditions
-- outlined in the disclaimer available from www.spiritconsortium.org.
--
-- This source file is provided on an AS IS basis. The SPIRIT
-- Consortium disclaims any warranty express or implied including
-- any warranty of merchantability and fitness for use for a
-- particular purpose.
--
-- The user of the source file shall indemnify and hold The SPIRIT
-- Consortium and its members harmless from any damages or liability.
-- Users are requested to provide feedback to The SPIRIT Consortium
-- using either mailto:<EMAIL> or the forms at
-- http://www.spiritconsortium.org/about/contact_us/
--
-- This file may be copied, and distributed, with or without
-- modifications; this notice must be included on any copy.
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: ahbstat
-- File: ahbstat.vhd
-- Author: <NAME> - ESA/ESTEC
-- Description: AHB status register. Latches the address and bus
-- parameters when an error is signalled on the AHB bus.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.iface.all;
use work.amba.all;
entity ahbstat is
port (
rst : in std_logic;
clk : in clk_type;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbsto : out ahbstat_out_type
);
end;
architecture rtl of ahbstat is
type memstattype is record
hsize : std_logic_vector(2 downto 0);
hmaster : std_logic_vector(3 downto 0);
address : std_logic_vector(31 downto 0); -- failed address
read : std_logic;
newerr : std_logic;
ahberr : std_logic;
hresp : std_logic_vector(1 downto 0);
end record;
signal r, rin : memstattype;
begin
ctrl : process(rst, ahbmi, ahbsi, apbi, r)
variable v : memstattype;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
begin
v := r;
regsd := (others => '0');
case apbi.paddr(2 downto 2) is
when "1" => regsd := r.address;
when "0" =>
regsd := "00000000000000000000000" & r.newerr & r.read &
r.hmaster & r.hsize ;
when others => regsd := (others => '-');
end case;
apbo.prdata <= regsd;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(2 downto 2) is
when "1" => v.address := apbi.pwdata;
when "0" =>
v.newerr := apbi.pwdata(8);
v.read := apbi.pwdata(7);
v.hmaster := apbi.pwdata(6 downto 3);
v.hsize := apbi.pwdata(2 downto 0);
when others => null;
end case;
end if;
v.hresp := ahbmi.hresp;
if (ahbsi.hready = '1') then
if (r.newerr = '0') then
if (r.hresp = HRESP_ERROR) then v.newerr := '1';
else
v.hmaster := ahbsi.hmaster; v.address := ahbsi.haddr;
v.read := not ahbsi.hwrite; v.hsize := ahbsi.hsize;
end if;
end if;
v.hresp := HRESP_OKAY;
end if;
if rst = '0' then
v.newerr := '0';
v.read := '0';
v.hmaster := "0000";
v.hsize := "000";
v.address := "00000000000000000000000000000000";
v.hresp := HRESP_OKAY;
end if;
v.ahberr := v.newerr and not r.newerr;
rin <= v;
ahbsto.ahberr <= r.ahberr;
end process;
memstatregs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
|
<reponame>vfinotti/cortex-m0-soft-microcontroller
-- MMCM_BASE : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the body of the design code. The instance name
-- declaration : (MMCM_BASE_inst) and/or the port declarations after the
-- code : "=>" declaration maybe changed to properly reference and
-- : connect this function to the design. All inputs and outputs
-- : must be connected.
-- Library : In addition to adding the instance declaration, a use
-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that will be used
-- : for simulation.
-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity sys_pll is
generic(
-- 200 MHz input clock
g_clkin_period : real := 5.000;
g_divclk_divide : integer := 1;
g_clkbout_mult_f : integer := 5;
-- Reference jitter
g_ref_jitter : real := 0.010;
-- 100 MHz output clock
g_clk0_divide_f : integer := 10;
-- 200 MHz output clock
g_clk1_divide : integer := 5;
g_clk2_divide : integer := 6
);
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
clk2_o : out std_logic;
locked_o : out std_logic
);
end sys_pll;
architecture syn of sys_pll is
signal s_mmcm_fbin : std_logic;
signal s_mmcm_fbout : std_logic;
signal s_clk0 : std_logic;
signal s_clk1 : std_logic;
signal s_clk2 : std_logic;
begin
-- Clock PLL
cmp_sys_pll : PLLE2_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => g_clkbout_mult_f, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => g_clkin_period,
CLKIN2_PERIOD => g_clkin_period,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => g_clk0_divide_f,
CLKOUT1_DIVIDE => g_clk1_divide,
CLKOUT2_DIVIDE => g_clk2_divide,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => g_divclk_divide, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => g_ref_jitter,
REF_JITTER2 => g_ref_jitter,
STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => s_clk0, -- 1-bit output: CLKOUT0
CLKOUT1 => s_clk1, -- 1-bit output: CLKOUT1
CLKOUT2 => s_clk2, -- 1-bit output: CLKOUT2
CLKOUT3 => open, -- 1-bit output: CLKOUT3
CLKOUT4 => open, -- 1-bit output: CLKOUT4
CLKOUT5 => open, -- 1-bit output: CLKOUT5
-- DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports
DO => open, -- 16-bit output: DRP data
DRDY => open, -- 1-bit output: DRP ready
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => s_mmcm_fbout, -- 1-bit output: Feedback clock
LOCKED => locked_o, -- 1-bit output: LOCK
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => clk_i, -- 1-bit input: Primary clock
CLKIN2 => '0', -- 1-bit input: Secondary clock
-- Control Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1', -- 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
PWRDWN => '0', -- 1-bit input: Power-down
RST => rst_i, -- 1-bit input: Reset
-- DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports
DADDR => (others => '0'), -- 7-bit input: DRP address
DCLK => '0', -- 1-bit input: DRP clock
DEN => '0', -- 1-bit input: DRP enable
DI => (others => '0'), -- 16-bit input: DRP data
DWE => '0', -- 1-bit input: DRP write enable
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => s_mmcm_fbin -- 1-bit input: Feedback clock
);
-- Global clock buffers for "cmp_mmcm" instance
cmp_clkf_bufg : BUFG
port map(
O => s_mmcm_fbin,
I => s_mmcm_fbout
);
cmp_clkout0_buf : BUFG
port map(
O => clk0_o,
I => s_clk0
);
cmp_clkout1_buf : BUFG
port map(
O => clk1_o,
I => s_clk1
);
cmp_clkout2_buf : BUFG
port map(
O => clk2_o,
I => s_clk2
);
end syn;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_SIN.VHD ***
--*** ***
--*** Function: Single Precision SIN Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take cos(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 7 ***
--*** (1 more than cos) ***
--***************************************************
ENTITY fp_sincos_fused IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout_sin : OUT STD_LOGIC;
exponentout_sin : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout_sin : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
signout_cos : OUT STD_LOGIC;
exponentout_cos : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout_cos : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_sincos_fused;
ARCHITECTURE rtl of fp_sincos_fused IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal input_number : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal input_number_delay : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (9 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign_sin, quadrantsign_cos, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff_sin,signcalcff_cos : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4+cordic_depth DOWNTO 1);
signal fixed_sin : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sinnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sinff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_cos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_cosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_cosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode_sin : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff_sin : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode_sin : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff_sin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode_sin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff_sin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode_sin : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal mantissaoutff_sin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentoutff_sin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal signoutff_sin : STD_LOGIC;
signal countnode_cos : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff_cos : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode_cos : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff_cos : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode_cos : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff_cos : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode_cos : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal mantissaoutff_cos : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentoutff_cos : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal signoutff_cos : STD_LOGIC;
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1_fused
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sin_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1);
cos_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** SIN(X) = X when exponent < 115 ***
input_number <= signin & exponentin & mantissain;
-- level 1 in, level range_depth+cordic_depth+7 out
cdin: fp_del
GENERIC MAP (width=>32,pipes=>range_depth+cordic_depth+6)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>input_number,
cc=>input_number_delay);
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign_sin <= circle(36); -- sin negative in quadrants 3&4
quadrantsign_cos <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- sin (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take cos rather than sin
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff_sin(k) <= '0';
signcalcff_cos(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
END LOOP;
FOR k IN 1 TO range_depth+cordic_depth+5 LOOP
selectoutputff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4+cordic_depth LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff_sin(1) <= quadrantsign_sin XOR signinff(range_depth);
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff_sin(k) <= signcalcff_sin(k-1);
END LOOP;
signcalcff_cos(1) <= quadrantsign_cos;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff_cos(k) <= signcalcff_cos(k-1);
END LOOP;
exponentinff <= exponentin; -- level 1
selectoutputff(1) <= exponentcheck(9); -- level 2 to range_depth+cordic_depth+6
FOR k IN 2 TO range_depth+cordic_depth+5 LOOP
selectoutputff(k) <= selectoutputff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + NOT(quadrant(34)); -- level range_depth+1
-- level range depth+1 to range_depth+4
-- Here is an interesting thing - depending on the quadrant the input is in, computation
-- or a sin or cosine can use sin or cosine result. What this means is that we may have to swap
-- results when they come out of the cordic block.
select_sincosff(1) <= quadrant(34);
FOR k IN 2 TO 4+cordic_depth LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- if exponent < 115, sin = input
exponentcheck <= ('0' & exponentinff) - ('0' & x"73");
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1_fused
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sin_out=>fixed_sin,
cos_out=>fixed_cos);
gfxa: IF (width < 36) GENERATE
fixed_sinnode <= (fixed_sin & zerovec(36-width DOWNTO 1)) when (select_sincosff(4+cordic_depth) = '1') else (fixed_cos & zerovec(36-width DOWNTO 1));
fixed_cosnode <= (fixed_cos & zerovec(36-width DOWNTO 1)) when (select_sincosff(4+cordic_depth) = '1') else (fixed_sin & zerovec(36-width DOWNTO 1));
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sinnode <= fixed_sin when (select_sincosff(4+cordic_depth) = '1') else fixed_cos;
fixed_cosnode <= fixed_cos when (select_sincosff(4+cordic_depth) = '1') else fixed_sin;
END GENERATE;
clz1: fp_clz36
PORT MAP (mantissa=>fixed_sinnode,leading=>countnode_sin);
clz2: fp_clz36
PORT MAP (mantissa=>fixed_cosnode,leading=>countnode_cos);
sft1: fp_lsft36
PORT MAP (inbus=>fixed_sinff,shift=>countff_sin,
outbus=>mantissanormnode_sin);
sft2: fp_lsft36
PORT MAP (inbus=>fixed_cosff,shift=>countff_cos,
outbus=>mantissanormnode_cos);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode_sin <= "10000000" - ("00" & countff_sin);
exponentnormnode_cos <= "10000000" - ("00" & countff_cos);
overflownode_sin(1) <= mantissanormnode_sin(12);
gova1: FOR k IN 2 TO 24 GENERATE
overflownode_sin(k) <= mantissanormnode_sin(k+11) AND overflownode_sin(k-1);
END GENERATE;
overflownode_cos(1) <= mantissanormnode_cos(12);
gova2: FOR k IN 2 TO 24 GENERATE
overflownode_cos(k) <= mantissanormnode_cos(k+11) AND overflownode_cos(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sinff(k) <= '0';
fixed_cosff(k) <= '0';
END LOOP;
countff_sin <= "000000";
countff_cos <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff_sin(k) <= '0';
mantissaoutff_sin(k) <= '0';
mantissanormff_cos(k) <= '0';
mantissaoutff_cos(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff_sin(k) <= '0';
exponentoutff_sin(k) <= '0';
exponentnormff_cos(k) <= '0';
exponentoutff_cos(k) <= '0';
END LOOP;
signoutff_sin <= '0';
signoutff_cos <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sinff <= fixed_sinnode; -- level range_depth+cordic_depth+5
fixed_cosff <= fixed_cosnode; -- level range_depth+cordic_depth+5
countff_sin <= countnode_sin; -- level range_depth+4+cordic_depth+5
countff_cos <= countnode_cos; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff_cos <= mantissanormnode_cos(35 DOWNTO 13) + mantissanormnode_cos(12);
exponentnormff_cos <= exponentnormnode_cos(8 DOWNTO 1) + overflownode_cos(24);
mantissanormff_sin <= mantissanormnode_sin(35 DOWNTO 13) + mantissanormnode_sin(12);
exponentnormff_sin <= exponentnormnode_sin(8 DOWNTO 1) + overflownode_sin(24);
-- level range_depth+cordic_depth+7
FOR k IN 1 TO 23 LOOP
mantissaoutff_sin(k) <= (mantissanormff_sin(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(k) AND selectoutputff(range_depth+cordic_depth+5));
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff_sin(k) <= (exponentnormff_sin(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(k+23) AND selectoutputff(range_depth+cordic_depth+5));
END LOOP;
signoutff_sin <= (signcalcff_sin(cordic_depth+6) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(32) AND selectoutputff(range_depth+cordic_depth+5));
mantissaoutff_cos <= mantissanormff_cos;
exponentoutff_cos <= exponentnormff_cos;
signoutff_cos <= signcalcff_cos(cordic_depth+6);
END IF;
END IF;
END PROCESS;
mantissaout_sin <= mantissaoutff_sin;
exponentout_sin <= exponentoutff_sin;
signout_sin <= signoutff_sin;
mantissaout_cos <= mantissaoutff_cos;
exponentout_cos <= exponentoutff_cos;
signout_cos <= signoutff_cos;
END rtl;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 2020 <NAME>
-- All rights reserved.
--
-------------------------------------------------------------------------------
-- Project Name : FPGA Dev Board Project
-- Author(s) : <NAME>
-- File Name : tb_fifo_sync.vhd
--
-- Testbench for a First-Word Fall-Through (FWFT) synchronous FIFO
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.util_pkg.num_bits;
entity tb_fifo_sync is
end entity tb_fifo_sync;
architecture tb_fifo_sync_rtl of tb_fifo_sync is
-- component generics
constant G_DATA_WIDTH : integer := 8;
constant G_LOG2_DEPTH : integer := 4;
constant G_REGISTER_OUT : boolean := false;
-- RAM styles:
-- Xilinx: "block", "distributed", "registers" or "uram"
-- Altera: "logic", "M512", "M4K", "M9K", "M20K", "M144K", "MLAB", or "M-RAM"
-- Lattice: "registers", "distributed" or "block_ram"
constant G_RAM_STYLE : string := "block";
-- component ports
-- Clock and Reset signals
signal clk : std_logic := '0';
signal rst : std_logic := '0';
-- Write ports
signal i_data : std_logic_vector(G_DATA_WIDTH - 1 downto 0) := (others => '0');
signal i_wr_en : std_logic := '0';
signal o_full : std_logic;
signal o_wr_error : std_logic;
-- Read ports
signal o_empty : std_logic;
signal i_rd_en : std_logic := '0';
signal o_data : std_logic_vector(G_DATA_WIDTH - 1 downto 0);
signal o_dval : std_logic;
signal o_rd_error : std_logic;
signal fifo_rst : std_logic := '0';
-- Stimulus counter
constant C_COUNT_MAX : natural := 126;
signal count : unsigned(num_bits(C_COUNT_MAX - 1) - 1 downto 0) := (others => '0');
signal data : unsigned(num_bits(C_COUNT_MAX - 1) - 1 downto 0) := (others => '0');
-- Self-checking signals
signal first_result : std_logic := '0';
signal last_data : unsigned(G_DATA_WIDTH - 1 downto 0) := (others => '0');
begin -- architecture tb_fifo_sync_rtl
-- component instantiation
DUT : entity work.fifo_sync
generic map (
G_DATA_WIDTH => G_DATA_WIDTH,
G_LOG2_DEPTH => G_LOG2_DEPTH,
G_REGISTER_OUT => G_REGISTER_OUT,
-- RAM styles:
-- Xilinx: "block" or "distributed"
-- Altera: "logic", "M512", "M4K", "M9K", "M20K", "M144K", "MLAB", or "M-RAM"
-- Lattice: "registers", "distributed" or "block_ram"
G_RAM_STYLE => G_RAM_STYLE)
port map (
-- Clock and Reset signals
clk => clk,
rst => fifo_rst,
-- Write ports
i_data => i_data,
i_wr_en => i_wr_en,
o_full => o_full,
o_wr_error => o_wr_error,
-- Read ports
o_empty => o_empty,
i_rd_en => i_rd_en,
o_data => o_data,
o_dval => o_dval,
o_rd_error => o_rd_error);
-------------------------------------------------------------------------------
-- System clock generation
clk_gen : process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process clk_gen;
-----------------------------------------------------------------------------
-- Reset generation
rst_gen : process
begin
rst <= '1';
wait for 30 ns;
rst <= '0';
wait;
end process rst_gen;
fifo_rst <= rst or o_wr_error or o_rd_error;
----------------------------------------------------------------------
-- Counter
-- constant C_COUNT_MAX : natural := 127;
-- signal count : natural range 0 to C_COUNT_MAX;
process (clk)
begin
if (rising_edge(clk)) then
if (rst = '1') then
count <= (others => '0');
else
if (count < C_COUNT_MAX) then
count <= count + 1;
else
count <= (others => '0');
end if;
end if;
end if;
end process;
process (clk)
begin
if (rising_edge(clk)) then
if (rst = '1') then
data <= (others => '0');
else
i_wr_en <= '0';
if ((count(3) xor count(1)) = '1' and o_full = '0') then
i_wr_en <= '1';
if (data < C_COUNT_MAX) then
data <= data + 1;
else
data <= (others => '0');
end if;
end if;
end if;
end if;
end process;
process (clk)
begin
if (rising_edge(clk)) then
if (rst = '1') then
i_data <= (others => '1');
else
i_data <= std_logic_vector(resize(data, i_data'length));
end if;
end if;
end process;
i_rd_en <= (count(2) and not count(6)) when o_empty = '0'
else '0';
-- Check the results
process (clk)
begin
if (rising_edge(clk)) then
if (fifo_rst = '1') then
first_result <= '1';
else
if (o_dval = '1') then
first_result <= '0';
last_data <= unsigned(o_data);
end if;
end if;
end if;
end process;
process (clk)
begin
if (rising_edge(clk)) then
if (first_result = '0') then
if (o_dval = '1') then
if (last_data = C_COUNT_MAX) then
assert unsigned(o_data) = 0
report "Non-sequential data coming out" severity warning;
else
assert unsigned(o_data) = last_data + 1
report "Non-sequential data coming out" severity warning;
end if;
end if;
end if;
end if;
end process;
end architecture tb_fifo_sync_rtl;
-------------------------------------------------------------------------------
configuration tb_fifo_sync_rtl_cfg of tb_fifo_sync is
for tb_fifo_sync_rtl
end for;
end tb_fifo_sync_rtl_cfg;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY keyboard IS
PORT( keyboard_clk, keyboard_data, clock_25Mhz ,
reset, read : IN STD_LOGIC;
scan_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
scan_ready : OUT STD_LOGIC);
END keyboard;
ARCHITECTURE a OF keyboard IS
SIGNAL INCNT : std_logic_vector(3 downto 0);
SIGNAL SHIFTIN : std_logic_vector(8 downto 0);
SIGNAL READ_CHAR : std_logic;
SIGNAL INFLAG, ready_set : std_logic;
SIGNAL keyboard_clk_filtered : std_logic;
SIGNAL filter : std_logic_vector(7 downto 0);
BEGIN
PROCESS (read, ready_set)
BEGIN
IF read = '1' THEN scan_ready <= '0';
ELSIF ready_set'EVENT and ready_set = '1' THEN
scan_ready <= '1';
END IF;
END PROCESS;
--This process filters the raw clock signal coming from the keyboard using a shift register and two AND gates
Clock_filter: PROCESS
BEGIN
WAIT UNTIL clock_25Mhz'EVENT AND clock_25Mhz= '1';
filter (6 DOWNTO 0) <= filter(7 DOWNTO 1) ;
filter(7) <= keyboard_clk;
IF filter = "11111111" THEN keyboard_clk_filtered <= '1';
ELSIF filter= "00000000" THEN keyboard_clk_filtered <= '0';
END IF;
END PROCESS Clock_filter;
--This process reads in serial data coming from the terminal
PROCESS
BEGIN
WAIT UNTIL (KEYBOARD_CLK_filtered'EVENT AND KEYBOARD_CLK_filtered='1');
IF RESET='1' THEN
INCNT <= "0000";
READ_CHAR <= '0';
ELSE
IF KEYBOARD_DATA='0' AND READ_CHAR='0' THEN
READ_CHAR<= '1';
ready_set<= '0';
ELSE
-- Shift in next 8 data bits to assemble a scan code
IF READ_CHAR = '1' THEN
IF INCNT < "1001" THEN
INCNT <= INCNT + 1;
SHIFTIN(7 DOWNTO 0) <= SHIFTIN(8 DOWNTO 1);
SHIFTIN(8) <= KEYBOARD_DATA;
ready_set <= '0';
-- End of scan code character, so set flags and exit loop
ELSE
scan_code <= SHIFTIN(7 DOWNTO 0);
READ_CHAR <='0';
ready_set <= '1';
INCNT <= "0000";
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END a;
|
<gh_stars>10-100
------------------------------------------------------------------------------------------------
-- Copyright (c) 2011 <NAME>
-- All rights reserved.
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of the copyright holder nor the
-- names of its contributors may be used to endorse or promote products
-- derived from this software without specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
-- IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ------------------------------------------------------------------------------------------------
-- ------------------------------------------------------------------------------------------------
-- Shifts the significand of floating-point operand C to the right by the amount as determined by
-- the exponent alignment block, or shift an integer input by the amount as specified at the
-- input. When a floating-point subtraction is performed the aligned significand is also inverted
-- as part of the end-around carry addition technique.
-- ------------------------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use work.alu_pkg_lvl1.all;
use work.alu_pkg_lvl2.all;
entity shiftright_conditionalcomplement is
port(
sign_a_in : in std_logic; -- sign of floating-point operand A
sign_b_in : in std_logic; -- sign of floating-point operand B
sign_c_in : in std_logic; -- sign of floating-point operand C
a_iszero_in : in std_logic; -- floating-point operand A is zero
b_iszero_in : in std_logic; -- floating-point operand B is zero
c_iszero_in : in std_logic; -- floating-point operand C is zero
int_float_in : in std_logic; -- integer or floating-point instruction
shift_int_in : in std_logic; -- shift a two's complement integer number
integer_shiftcount_in : in std_logic_vector(EXPONENTWIDTH-1 downto 0); -- shift-count for integer
float_shiftcount_in : in std_logic_vector(EXPONENTWIDTH-1 downto 0); -- shift-count for floating-point alignment
significand_c_in : in std_logic_vector((HIDDENBIT+SIGNIFICANDWIDTH)-1 downto 0); -- significand of operand C or integer to shift
shifted_out : out std_logic_vector((3*(HIDDENBIT+SIGNIFICANDWIDTH)+GUARDBITS) downto 0) -- shifted (aligned) operand
);
end shiftright_conditionalcomplement;
architecture rtl of shiftright_conditionalcomplement is
begin
combinatorial : process(sign_a_in, sign_b_in, sign_c_in, a_iszero_in, b_iszero_in, c_iszero_in, int_float_in, shift_int_in, integer_shiftcount_in, float_shiftcount_in, significand_c_in)
variable shifted : std_logic_vector((3*(HIDDENBIT+SIGNIFICANDWIDTH)+GUARDBITS) downto 0);
variable sha : integer;
begin
if(shift_int_in = '1') then -- shift integer, so sign extend input
shifted := std_logic_vector(resize(signed(significand_c_in),3*(HIDDENBIT+SIGNIFICANDWIDTH)+GUARDBITS+1));
sha := to_integer(unsigned(integer_shiftcount_in));
else -- align floating-point, so extend with a '0' such that arithmetic shift becomes logic shift
shifted := (others => '0');
shifted(shifted'left-1 downto shifted'left-(HIDDENBIT+SIGNIFICANDWIDTH)) := significand_c_in;
sha := to_integer(unsigned(float_shiftcount_in));
end if;
-- Implement the actual shifter as an arithmetic shift operation. Both the 'unsigned' floating-
-- point and signed integer input can be shifted correctly on an arithmetic shifter if the MSB
-- of the floating-point input is guaranteed to be zero.
shifted := std_logic_vector(shift_right(signed(shifted),sha));
if(int_float_in = '1' and shift_int_in = '1') then -- integer shift-right
shifted_out <= shifted;
elsif(int_float_in = '1' and shift_int_in = '0') then -- integer arithmetic (don't shift)
shifted_out <= std_logic_vector(resize(signed(significand_c_in),3*(HIDDENBIT+SIGNIFICANDWIDTH)+GUARDBITS+1));
else -- floating-point alignment
-- When the floating-point operation is an effective subtraction (i.e., the signs of A*B and C
-- differ), the shifted output is inverted (i.e., one's complement representation). This is the
-- first step needed for end-around carry addition, a technique to perform subtraction on
-- sign-magnitude numbers without having to convert to two's complement representation.
if(((((sign_a_in xor sign_b_in) xor sign_c_in)) and not(a_iszero_in or b_iszero_in or c_iszero_in)) = '1') then
-- The sign-bit is placed before the aligned and complemented significand to cancel
-- erroneous carry-out detection in a later stage of end-around carry addition. In case of
-- effective subtraction this sign will be - ('1'), otherwise it will always be + ('0').
shifted_out <= '1' & not(std_logic_vector(resize(unsigned(shifted(shifted'left-1 downto 0)),3*(HIDDENBIT+SIGNIFICANDWIDTH)+GUARDBITS)));
else
shifted_out <= '0' & std_logic_vector(resize(unsigned(shifted(shifted'left-1 downto 0)),3*(HIDDENBIT+SIGNIFICANDWIDTH)+GUARDBITS));
end if;
end if;
end process;
end rtl;
|
<gh_stars>1-10
-- Standard 74153 TTL multiplexor designed from the behavioral model in the data sheet.
library IEEE;
use IEEE.std_logic_1164.all;
entity TTL74153 is
port(
pin1_n1g: in std_logic;
pin2_b : in std_logic;
pin3_1c3: in std_logic;
pin4_1c2: in std_logic;
pin5_1c1 : in std_logic;
pin6_1c0 : in std_logic;
pin7_1y : out std_logic;
pin9_2y : out std_logic;
pin10_2c0 : in std_logic;
pin11_2c1 : in std_logic;
pin12_2c2 : in std_logic;
pin13_2c3 : in std_logic;
pin14_a : in std_logic;
pin15_n2g : in std_logic);
end TTL74153;
architecture logic of TTL74153 is
begin
pin7_1y <= (pin6_1c0 and not pin2_b and not pin14_a and not pin1_n1g) or
(pin5_1c1 and not pin2_b and pin14_a and not pin1_n1g) or
(pin4_1c2 and pin2_b and not pin14_a and not pin1_n1g) or
(pin3_1c3 and pin2_b and pin14_a and not pin1_n1g);
pin9_2y <= (pin10_2c0 and not pin2_b and not pin14_a and not pin15_n2g) or
(pin11_2c1 and not pin2_b and pin14_a and not pin15_n2g) or
(pin12_2c2 and pin2_b and not pin14_a and not pin15_n2g) or
(pin13_2c3 and pin2_b and pin14_a and not pin15_n2g);
end logic;
|
<gh_stars>1-10
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.01.2020 16:26:41
-- Design Name:
-- Module Name: SHUFFLYBOI - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SHUFFLYBOI is
Generic(
factor : positive
);
Port ( IS0 : in STD_LOGIC_VECTOR (7 downto 0);
IS1 : in STD_LOGIC_VECTOR (7 downto 0);
IS2 : in std_logic_vector(7 downto 0);
IS3 : in std_logic_vector(7 downto 0);
DATA_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end SHUFFLYBOI;
architecture Behavioral of SHUFFLYBOI is
begin
F4: if factor = 4 generate
DATA_OUT(0) <= IS0(0);
DATA_OUT(1) <= IS1(0);
DATA_OUT(2) <= IS2(0);
DATA_OUT(3) <= IS3(0);
DATA_OUT(4) <= IS0(1);
DATA_OUT(5) <= IS1(1);
DATA_OUT(6) <= IS2(1);
DATA_OUT(7) <= IS3(1);
DATA_OUT(8) <= IS0(2);
DATA_OUT(9) <= IS1(2);
DATA_OUT(10) <= IS2(2);
DATA_OUT(11) <= IS3(2);
DATA_OUT(12) <= IS0(3);
DATA_OUT(13) <= IS1(3);
DATA_OUT(14) <= IS2(3);
DATA_OUT(15) <= IS3(3);
DATA_OUT(16) <= IS0(4);
DATA_OUT(17) <= IS1(4);
DATA_OUT(18) <= IS2(4);
DATA_OUT(19) <= IS3(4);
DATA_OUT(20) <= IS0(5);
DATA_OUT(21) <= IS1(5);
DATA_OUT(22) <= IS2(5);
DATA_OUT(23) <= IS3(5);
DATA_OUT(24) <= IS0(6);
DATA_OUT(25) <= IS1(6);
DATA_OUT(26) <= IS2(6);
DATA_OUT(27) <= IS3(6);
DATA_OUT(28) <= IS0(7);
DATA_OUT(29) <= IS1(7);
DATA_OUT(30) <= IS2(7);
DATA_OUT(31) <= IS3(7);
end generate;
F2 : if(factor = 2) generate
DATA_OUT(0) <= IS0(0);
DATA_OUT(1) <= IS1(0);
DATA_OUT(2) <= IS0(1);
DATA_OUT(3) <= IS1(1);
DATA_OUT(4) <= IS0(2);
DATA_OUT(5) <= IS1(2);
DATA_OUT(6) <= IS0(3);
DATA_OUT(7) <= IS1(3);
DATA_OUT(8) <= IS0(4);
DATA_OUT(9) <= IS1(4);
DATA_OUT(10) <= IS0(5);
DATA_OUT(11) <= IS1(5);
DATA_OUT(12) <= IS0(6);
DATA_OUT(13) <= IS1(6);
DATA_OUT(14) <= IS0(7);
DATA_OUT(15) <= IS1(7);
end generate;
end Behavioral;
|
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