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<reponame>TripRichert/vhdl_stimulus
--! @file
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package to_str_pkg is
function toStr(val : unsigned) return string;
function toStr(val : signed) return string;
end package to_str_pkg;
package body to_str_pkg is
function digitToChar(val : natural) return character is
begin
assert val < 10
report "digit must be less than 10" severity warning;
return character'val(val + character'pos(character'('0')));
end function digitToChar;
function toStr(val : unsigned) return string is
variable tmp : natural;
begin
tmp := natural(to_integer(val));
if val < 10 then
return string'("") & digitToChar(natural(to_integer(val)));
end if;
return toStr(val / 10) & digitToChar(natural(to_integer(val mod 10)));
end function toStr;
function toStr(val : signed) return string is
variable tmp : signed(val'length downto 0);
begin
tmp := resize(val, val'length + 1);
if val < 0 then
return string'("-") & toStr(-tmp);
else
return toStr(unsigned(std_ulogic_vector(val)));
end if;
end function toStr;
end package body to_str_pkg;
|
<reponame>kschoos/vivado-library<filename>ip/AXI_DPTI_1.0/src/HandshakeData.vhd
------------------------------------------------------------------------------
--
-- File: HandshakeData.vhd
-- Author: <NAME>
-- Original Project: Atlys2 User Demo
-- Date: 29 June 20116
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module passes parallel data from the input clock domain (InClk) to the
-- output clock domain (OutClk) by the means of handshake signals. A
-- low-to-high transition on iPush will register iData inside the module
-- and will start propagating the handshake signals towards the output domain.
-- The data will appear on oData and is valid when oValid pulses high.
-- The reception of data by the receiver on the OutClk domain is signaled
-- by a pulse on oAck. This will propagate back to the input domain and
-- assert iRdy signaling to the sender that a new data can be pushed though.
-- If oData is always read when oValid pulses, oAck may be tied permanently
-- high.
-- Only assert iPush when iRdy is high!
--
-- Changelog:
-- 2016-Jun-29: Fixed oValid not being a pulse.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity HandshakeData is
Generic (
kDataWidth : natural := 8);
Port (
InClk : in STD_LOGIC;
OutClk : in STD_LOGIC;
iData : in STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
oData : out STD_LOGIC_VECTOR (kDataWidth-1 downto 0);
iPush : in STD_LOGIC;
iRdy : out STD_LOGIC;
oAck : in STD_LOGIC := '1';
oValid : out STD_LOGIC;
aReset : in std_logic);
end HandshakeData;
architecture Behavioral of HandshakeData is
signal iPush_q, iPushRising, iPushT, iPushTBack, iReset : std_logic;
signal iData_int : std_logic_vector(kDataWidth-1 downto 0);
signal oPushT, oPushT_q, oPushTBack, oPushTChanged : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of aReset: signal is "TRUE";
begin
DetectPush: process(aReset, InClk)
begin
if (aReset = '1') then
iPush_q <= '0';
elsif Rising_Edge(InClk) then
iPush_q <= iPush;
end if;
end process DetectPush;
iPushRising <= iPush and not iPush_q;
-- Register data when iPush is rising and toggle internal flag
LatchData: process(aReset, InClk)
begin
if (aReset = '1') then
iData_int <= (others => '0');
iPushT <= '0';
elsif Rising_Edge(InClk) then
if (iPushRising = '1') then
iData_int <= iData;
iPushT <= not iPushT;
end if;
end if;
end process;
-- Cross toggle flag through synchronizer
SyncAsyncPushT: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => aReset,
aIn => iPushT,
OutClk => OutClk,
oOut => oPushT);
-- Detect a push edge in the OutClk domain
-- If receiver acknowledges receipt, we can propagate the push signal back
-- towards the input, where it will be used to generate iRdy
DetectToggle: process(aReset, OutClk)
begin
if (aReset = '1') then
oPushT_q <= '0';
oPushTBack <= '0';
elsif Rising_Edge(OutClk) then
oPushT_q <= oPushT;
if (oAck = '1') then
oPushTBack <= oPushT_q;
end if;
end if;
end process DetectToggle;
oPushTChanged <= '1' when oPushT_q /= oPushT else '0';
-- Cross data from InClk domain reg (iData_in) to OutClk domain
-- The enable for this register is the propagated and sync'd to the OutClk domain
-- We assume here that the time it took iPush to propagate to oPushTChanged is
-- more than the time it takes iData_int to propagate to the oData register's D pin
OutputData: process (aReset, OutClk)
begin
if (aReset = '1') then
oData <= (others => '0');
oValid <= '0';
elsif Rising_Edge(OutClk) then
if (oPushTChanged = '1') then
oData <= iData_int;
end if;
oValid <= oPushTChanged;
end if;
end process OutputData;
-- Cross toggle flag back through synchronizer
SyncAsyncPushTBack: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2)
port map (
aReset => aReset,
aIn => oPushTBack,
OutClk => InClk,
oOut => iPushTBack);
-- Synchronize aReset into the InClk domain
-- We need it to keep iRdy low, when aReset de-asserts
SyncReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aReset,
OutClk => InClk,
oRst => iReset);
ReadySignal: process(aReset, InClk)
begin
if (aReset = '1') then
iRdy <= '0';
elsif Rising_Edge(InClk) then
iRdy <= not iPush and (iPushTBack xnor iPushT) and not iReset;
end if;
end process ReadySignal;
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- LAB #3
--
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY bitstorage IS
PORT(bitin : IN STD_LOGIC;
enout : IN STD_LOGIC;
writein : IN STD_LOGIC;
bitout : OUT STD_LOGIC);
END ENTITY bitstorage;
ARCHITECTURE memlike OF bitstorage IS
SIGNAL q: STD_LOGIC;
BEGIN
PROCESS(writein) IS
BEGIN
IF (RISING_EDGE(writein)) THEN
q <= bitin;
END IF;
END PROCESS;
-- Note that data IS OUTput only WHEN enout = 0
bitout <= q WHEN enout = '0' ELSE 'Z';
END ARCHITECTURE memlike;
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fulladder IS
PORT (a : IN STD_LOGIC;
b : IN STD_LOGIC;
cin : IN STD_LOGIC;
sum : OUT STD_LOGIC;
carry : OUT STD_LOGIC);
END fulladder;
ARCHITECTURE addlike OF fulladder IS
BEGIN
sum <= a xor b xor cIN;
carry <= (a AND b) OR (a AND cIN) OR (b AND cIN);
END ARCHITECTURE addlike;
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY register8 IS
PORT(datain : IN STD_LOGIC_vector(7 DOWNTO 0);
enout : IN STD_LOGIC;
writein : IN STD_LOGIC;
dataout : OUT STD_LOGIC_vector(7 DOWNTO 0));
END ENTITY register8;
ARCHITECTURE memmy OF register8 IS
COMPONENT bitstorage
PORT(bitin : IN STD_LOGIC;
enout : IN STD_LOGIC;
writein : IN STD_LOGIC;
bitout : OUT STD_LOGIC);
END COMPONENT;
BEGIN
R0: bitstorage PORT MAP(datain(0),enout,writein,dataout(0));
R1: bitstorage PORT MAP(datain(1),enout,writein,dataout(1));
R2: bitstorage PORT MAP(datain(2),enout,writein,dataout(2));
R3: bitstorage PORT MAP(datain(3),enout,writein,dataout(3));
R4: bitstorage PORT MAP(datain(4),enout,writein,dataout(4));
R5: bitstorage PORT MAP(datain(5),enout,writein,dataout(5));
R6: bitstorage PORT MAP(datain(6),enout,writein,dataout(6));
R7: bitstorage PORT MAP(datain(7),enout,writein,dataout(7));
END ARCHITECTURE memmy;
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY register16 IS
PORT(datain : IN STD_LOGIC_vector(15 DOWNTO 0);
enout16,
enout8 : IN STD_LOGIC;
writein16,
writein8 : IN STD_LOGIC;
dataout: OUT STD_LOGIC_vector(15 DOWNTO 0));
END ENTITY register16;
ARCHITECTURE biggermem OF register16 IS
SIGNAL writeit8, writeit16: STD_LOGIC;
SIGNAL enit8, enit16: STD_LOGIC;
COMPONENT register8 IS
PORT(datain: IN STD_LOGIC_vector(7 DOWNTO 0);
enout: IN STD_LOGIC;
writein: IN STD_LOGIC;
dataout: OUT STD_LOGIC_vector(7 DOWNTO 0));
END COMPONENT;
BEGIN
writeit8 <= writein8 OR writein16;
writeit16 <= writein16;
enit8 <= enOUT8 AND enOUT16;
enit16 <= enOUT16;
Q0: register8 PORT MAP(datain(7 DOWNTO 0),enit8,writeit8,dataout(7 DOWNTO 0));
Q1: register8 PORT MAP(datain(15 DOWNTO 8),enit16,writeit16,dataout(15 DOWNTO 8));
END ARCHITECTURE biggermem;
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY register32 IS
PORT(datain: IN STD_LOGIC_vector(31 DOWNTO 0);
enOUT32,enOUT16,enOUT8: IN STD_LOGIC;
writein32, writein16, writein8: IN STD_LOGIC;
dataout: OUT STD_LOGIC_vector(31 DOWNTO 0));
END ENTITY register32;
ARCHITECTURE biggermem OF register32 IS
SIGNAL writeit8, writeit16, writeit32: STD_LOGIC;
SIGNAL enit8, enit16, enit32: STD_LOGIC;
COMPONENT register8 IS
PORT(datain: IN STD_LOGIC_vector(7 DOWNTO 0);
enout: IN STD_LOGIC;
writein: IN STD_LOGIC;
dataout: OUT STD_LOGIC_vector(7 DOWNTO 0));
END COMPONENT;
BEGIN
writeit8 <= writein8 OR writein16 OR writein32;
writeit16 <= writein16 OR writein32;
writeit32 <= writein32;
enit8 <= enOUT8 AND enOUT16 AND enOUT32;
enit16 <= enOUT16 AND enOUT32;
enit32 <= enOUT32;
Q0: register8 PORT MAP(datain(7 DOWNTO 0),enit8,writeit8,dataout(7 DOWNTO 0));
Q1: register8 PORT MAP(datain(15 DOWNTO 8),enit16,writeit16,dataout(15 DOWNTO 8));
Q2: register8 PORT MAP(datain(23 DOWNTO 16),enit32,writeit32,dataout(23 DOWNTO 16));
Q3: register8 PORT MAP(datain(31 DOWNTO 24),enit32,writeit32,dataout(31 DOWNTO 24));
END ARCHITECTURE biggermem;
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY adder_subtracter IS
PORT( datain_a: IN STD_LOGIC_vector(31 DOWNTO 0);
datain_b: IN STD_LOGIC_vector(31 DOWNTO 0);
add_sub : IN STD_LOGIC; -- add when == '0'
dataout : OUT STD_LOGIC_vector(31 DOWNTO 0);
co : OUT STD_LOGIC);
END ENTITY adder_subtracter;
ARCHITECTURE calc OF adder_subtracter IS
SIGNAL used_b: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL carryit: STD_LOGIC_vector(31 DOWNTO 0);
COMPONENT fulladder IS
PORT (a : IN STD_LOGIC;
b : IN STD_LOGIC;
cin : IN STD_LOGIC;
sum : OUT STD_LOGIC;
carry : OUT STD_LOGIC);
END COMPONENT;
BEGIN
used_b <= dataIN_b WHEN add_sub = '0' ELSE
not(dataIN_b)+1;
F1: fulladder PORT MAP(dataIN_a(0),used_b(0),'0',dataout(0),carryit(0));
ADDVAL:
FOR i IN 1 to 31 GENERATE
FA: fulladder PORT MAP(dataIN_a(i),used_b(i),carryit(i-1),dataout(i),carryit(i));
END GENERATE ADDVAL;
co <= carryit(31);
END ARCHITECTURE calc;
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY shift_register IS
PORT( datain: IN STD_LOGIC_vector(31 DOWNTO 0);
dir: IN STD_LOGIC;
shamt: IN STD_LOGIC_vector(4 DOWNTO 0);
dataout: OUT STD_LOGIC_vector(31 DOWNTO 0));
END ENTITY shift_register;
ARCHITECTURE shifter OF shift_register IS
SIGNAL shammy: STD_LOGIC_vector(1 DOWNTO 0);
BEGIN
shammy <= shamt(1 DOWNTO 0);
dataout <= datain(30 DOWNTO 0) & "0" WHEN dir & shammy = "001" ELSE
datain(29 DOWNTO 0) & "00" WHEN dir & shammy = "010" ELSE
datain(28 DOWNTO 0) & "000" WHEN dir & shammy = "011" ELSE
"0" & datain(31 DOWNTO 1) WHEN dir & shammy = "101" ELSE
"00" & datain(31 DOWNTO 2) WHEN dir & shammy = "110" ELSE
"000" & datain(31 DOWNTO 3) WHEN dir & shammy = "111" ELSE
datain;
END ARCHITECTURE shifter;
------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ALU IS
PORT( datain1: IN STD_LOGIC_vector(31 DOWNTO 0);
datain2: IN STD_LOGIC_vector(31 DOWNTO 0);
Control: IN STD_LOGIC_vector(4 DOWNTO 0);
Zero: OUT STD_LOGIC;
ALUResult: OUT STD_LOGIC_vector(31 DOWNTO 0));
END ENTITY ALU;
ARCHITECTURE logic OF ALU IS
--SIGNALS GO HERE
SIGNAL excarry1: STD_LOGIC;
SIGNAL excarry2: STD_LOGIC;
SIGNAL addres: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL subres: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL orres: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL andres: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL sllres: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL srlres: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL result: STD_LOGIC_vector(31 DOWNTO 0);
SIGNAL nores: STD_LOGIC_vector(31 DOWNTO 0):= (OTHERS=>'0');
--COMPONENTS
COMPONENT adder_subtracter IS
PORT( datain_a : IN STD_LOGIC_vector(31 DOWNTO 0);
datain_b : IN STD_LOGIC_vector(31 DOWNTO 0);
add_sub : IN STD_LOGIC;
dataout : OUT STD_LOGIC_vector(31 DOWNTO 0);
co : OUT STD_LOGIC);
END COMPONENT;
COMPONENT shift_register IS
PORT( datain : IN STD_LOGIC_vector(31 DOWNTO 0);
dir : IN STD_LOGIC;
shamt : IN STD_LOGIC_vector(4 DOWNTO 0);
dataout : OUT STD_LOGIC_vector(31 DOWNTO 0));
END COMPONENT;
BEGIN
A: adder_subtracter PORT MAP(datain1,datain2,'0',addres,excarry1);
S: adder_subtracter PORT MAP(datain1,datain2,'1',subres,excarry2);
andres <= datain1 AND datain2;
orres <= datain1 OR datain2;
L: shift_register PORT MAP(datain1,'0',datain2(4 DOWNTO 0),sllres);
R: shift_register PORT MAP(datain1,'1',datain2(4 DOWNTO 0),srlres);
WITH Control SELECT result <=
addres WHEN "00000",
subres WHEN "00001",
andres WHEN "00010",
orres WHEN "00011",
sllres WHEN "00100",
srlres WHEN "00101",
nores WHEN OTHERS;
WITH result SELECT Zero <=
'1' WHEN x"00000000",
'0' WHEN OTHERS;
ALUResult <= result;
END ARCHITECTURE logic;
|
-- Up/Down counter
--
-- it represents the component in charge of
-- generating an angle every time the rising edge
-- of the clock and the enable signal its ON.
--
-- the new angle generated its "delta_phi" UP or DOWN
-- from respect to the previous angle
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity up_down_counter is
port(
clk : in std_logic;
rst : in std_logic;
up_sw : in std_logic;
down_sw : in std_logic;
angle : out std_logic_vector(16 downto 0);
enable : in std_logic
);
end entity up_down_counter;
architecture up_down_counter_arq of up_down_counter is
constant ANGLE_SIZE : natural := 17;
constant ZERO : std_logic_vector(ANGLE_SIZE - 1 downto 0) := (others => '0');
constant POS_DELTA_PHI : std_logic_vector(ANGLE_SIZE - 1 downto 0)
:= std_logic_vector(to_unsigned(256, ANGLE_SIZE));
constant NEG_DELTA_PHI : std_logic_vector(ANGLE_SIZE - 1 downto 0)
:= std_logic_vector(to_signed(-256, ANGLE_SIZE));
signal sw_input : std_logic_vector(1 downto 0);
signal delta_phi : std_logic_vector(ANGLE_SIZE - 1 downto 0);
signal next_angle : std_logic_vector(ANGLE_SIZE - 1 downto 0);
signal current_angle : std_logic_vector(ANGLE_SIZE - 1 downto 0) := ZERO;
begin
sw_input <= up_sw & down_sw;
delta_phi <= ZERO when sw_input = "00" else
NEG_DELTA_PHI when sw_input = "01" else
POS_DELTA_PHI when sw_input = "10" else
ZERO when sw_input = "11";
next_angle <= std_logic_vector(signed(current_angle) + signed(delta_phi));
ANGLE_MEM : entity work.register_mem
generic map(
N => ANGLE_SIZE
)
port map(
clk => clk,
rst => rst,
enable => enable,
data_in => next_angle,
data_out => current_angle
);
angle <= current_angle;
end architecture up_down_counter_arq;
|
-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
-- Date : Sun Oct 24 07:38:50 2021
-- Host : Duller running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/Admin/Desktop/Zynq7010_eink_controller/controller/Z7_Lite/HDMI_TX/hdmi_trans.runs/clock_synth_1/clock_stub.vhdl
-- Design : clock
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock is
Port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end clock;
architecture stub of clock is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,resetn,locked,clk_in1";
begin
end;
|
<reponame>hei-synd-2131-eln/eln_kart<gh_stars>0
LIBRARY std;
USE std.textio.ALL;
LIBRARY ieee;
USE ieee.std_logic_textio.ALL;
ARCHITECTURE test OF dcMotorController_tester IS
-- reset and clock
constant clockPeriod : time := 1.0/clockFrequency * 1 sec;
signal sClock: std_uLogic := '1';
-- test info
signal testInfo: string(1 to 16) := (others => ' ');
-- I2C interface
constant i2cPeriod : time := 1.0/i2cBaudRate * 1 sec;
constant i2cRegisterNb: positive := 16;
type i2cRegistersType is array(0 to i2cRegisterNb-1) of integer;
signal i2cBaseAddress: natural;
signal i2cRegisters: i2cRegistersType;
signal i2cDataLength: positive;
signal i2cWrite: std_ulogic;
signal i2cSend: std_ulogic;
signal i2cDone: std_ulogic;
signal i2cDataOut: unsigned(i2cBitNb-1-1 downto 0);
signal i2cSendWord: std_ulogic;
signal i2cWordDone: std_ulogic;
signal i2cDataIn: integer;
-- control values
constant restart: natural := 16#10#;
constant btConnected: natural := 16#20#;
signal orientation, orientation1: integer;
signal absSpeed: integer;
constant pwmDivideValue: positive := 10;
constant pwmPeriod : time := 2**(speedBitNb-1) * pwmDivideValue * clockPeriod;
constant speedMaxValue: positive := 2**(speedBitNb-1)-1;
-- PWM mean value
constant pwmLowpassShift: positive := 8;
signal pwmLowpassAccumulator, motorSpeed: real := 0.0;
signal motorSpeed_int: integer := 0;
BEGIN
------------------------------------------------------------------------------
-- reset and clock
reset <= '1', '0' after 4*clockPeriod;
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after 0.9*clockPeriod;
------------------------------------------------------------------------------
-- test sequence
process
begin
i2cSend <= '0';
i2cWrite <= '0';
i2cBaseAddress <= 0;
i2cRegisters <= (others => 0);
i2cDataLength <= 2;
wait for 10*i2cPeriod;
write(output,
lf & lf & lf &
"----------------------------------------------------------------" & lf &
"-- Starting testbench" & lf &
"--" &
lf & lf
);
-- send orientation
testInfo <= "Init ";
write(output,
"Setting hardware orientation" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
orientation <= 1;
i2cBaseAddress <= orientationBaseAddress; wait for 0 ns;
i2cDataLength <= 1;
i2cRegisters(i2cBaseAddress) <= orientation + btConnected;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
orientation1 <= orientation;
wait for 10*i2cPeriod;
-- send prescaler
wait for 2*i2cPeriod;
write(output,
"Sending prescaler value" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
i2cBaseAddress <= baseAddress; wait for 0 ns;
i2cDataLength <= 2;
i2cRegisters(i2cBaseAddress) <= pwmDivideValue;
i2cRegisters(i2cBaseAddress+1) <= 0;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
wait for 10*pwmPeriod;
-- send 1/3 speed
testInfo <= "speed 1/3 ";
write(output,
"Sending speed control to 1/3 max value forwards" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
absSpeed <= speedMaxValue / 3;
i2cBaseAddress <= baseAddress + 2; wait for 0 ns;
i2cDataLength <= 2;
i2cRegisters(i2cBaseAddress) <= absSpeed;
i2cRegisters(i2cBaseAddress+1) <= 0;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
wait for 10*pwmPeriod;
assert forwards = '1'
report "Direction error"
severity error;
assert abs(motorSpeed_int-absSpeed) <= 2
report "PWM error"
severity error;
-- send 2/3 speed
testInfo <= "speed 2/3 ";
write(output,
"Sending speed control to 2/3 max value forwards" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
absSpeed <= speedMaxValue * 2/3;
i2cBaseAddress <= baseAddress + 2; wait for 0 ns;
i2cDataLength <= 2;
i2cRegisters(i2cBaseAddress) <= absSpeed;
i2cRegisters(i2cBaseAddress+1) <= 0;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
wait for 10*pwmPeriod;
assert forwards = '1'
report "Direction error"
severity error;
assert abs(motorSpeed_int-absSpeed) <= 2
report "PWM error"
severity error;
-- send full speed
testInfo <= "full speed ";
write(output,
"Sending speed control to max value forwards" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
absSpeed <= speedMaxValue;
i2cBaseAddress <= baseAddress + 2; wait for 0 ns;
i2cDataLength <= 2;
i2cRegisters(i2cBaseAddress) <= absSpeed;
i2cRegisters(i2cBaseAddress+1) <= 0;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
wait for 10*pwmPeriod;
assert forwards = '1'
report "Direction error"
severity error;
assert abs(motorSpeed_int-absSpeed) <= 2
report "PWM error"
severity error;
-- send 1/3 speed backwards
testInfo <= "speed 1/3 back ";
write(output,
"Sending speed control to 1/3 max value backwards" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
absSpeed <= speedMaxValue / 3;
i2cBaseAddress <= baseAddress + 2; wait for 0 ns;
i2cDataLength <= 2;
i2cRegisters(i2cBaseAddress) <= -absSpeed;
i2cRegisters(i2cBaseAddress+1) <= -1;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
wait for 10*pwmPeriod;
assert forwards = '0'
report "Direction error"
severity error;
assert abs(motorSpeed_int+absSpeed) <= 2
report "PWM error"
severity error;
-- send 2/3 speed backwards
testInfo <= "speed 2/3 back ";
write(output,
"Sending speed control to 2/3 max value backwards" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
absSpeed <= speedMaxValue * 2/3;
i2cBaseAddress <= baseAddress + 2; wait for 0 ns;
i2cDataLength <= 2;
i2cRegisters(i2cBaseAddress) <= -absSpeed;
i2cRegisters(i2cBaseAddress+1) <= -1;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
wait for 10*pwmPeriod;
assert forwards = '0'
report "Direction error"
severity error;
assert abs(motorSpeed_int+absSpeed) <= 2
report "PWM error"
severity error;
-- send full speed backwards
testInfo <= "full speed back ";
write(output,
"Sending speed control to max value backwards" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
absSpeed <= speedMaxValue;
i2cBaseAddress <= baseAddress + 2; wait for 0 ns;
i2cDataLength <= 2;
i2cRegisters(i2cBaseAddress) <= -absSpeed;
i2cRegisters(i2cBaseAddress+1) <= -1;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
wait for 10*pwmPeriod;
assert forwards = '0'
report "Direction error"
severity error;
assert abs(motorSpeed_int+absSpeed) <= 2
report "PWM error"
severity error;
-- change orientation
testInfo <= "orientation ";
write(output,
"Changing hardware orientation" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
orientation <= 0;
i2cBaseAddress <= orientationBaseAddress; wait for 0 ns;
i2cDataLength <= 1;
i2cRegisters(i2cBaseAddress) <= orientation + btConnected;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
orientation1 <= orientation;
wait for 10*i2cPeriod;
-- send half speed
testInfo <= "half speed ";
write(output,
"Sending speed control to half max value forwards" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
absSpeed <= (speedMaxValue+1) / 2;
i2cBaseAddress <= baseAddress + 2; wait for 0 ns;
i2cDataLength <= 2;
i2cRegisters(i2cBaseAddress) <= absSpeed;
i2cRegisters(i2cBaseAddress+1) <= 0;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
wait for 10*pwmPeriod;
assert forwards = '0'
report "Direction error"
severity error;
assert abs(motorSpeed_int-absSpeed) <= 2
report "PWM error"
severity error;
-- send full speed
testInfo <= "full speed ";
write(output,
"Sending speed control to max value forwards" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
absSpeed <= speedMaxValue;
i2cBaseAddress <= baseAddress + 2; wait for 0 ns;
i2cDataLength <= 2;
i2cRegisters(i2cBaseAddress) <= absSpeed;
i2cRegisters(i2cBaseAddress+1) <= 0;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
wait for 10*pwmPeriod;
assert forwards = '0'
report "Direction error"
severity error;
assert abs(motorSpeed_int-absSpeed) <= 2
report "PWM error"
severity error;
-- send half speed backwards
testInfo <= "half speed back ";
write(output,
"Sending speed control to half max value backwards" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
absSpeed <= (speedMaxValue+1) / 2;
i2cBaseAddress <= baseAddress + 2; wait for 0 ns;
i2cDataLength <= 2;
i2cRegisters(i2cBaseAddress) <= -absSpeed;
i2cRegisters(i2cBaseAddress+1) <= -1;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
wait for 10*pwmPeriod;
assert forwards = '1'
report "Direction error"
severity error;
assert abs(motorSpeed_int+absSpeed) <= 2
report "PWM error"
severity error;
-- send full speed backwards
testInfo <= "full speed back ";
write(output,
"Sending speed control to max value backwards" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
absSpeed <= speedMaxValue;
i2cBaseAddress <= baseAddress + 2; wait for 0 ns;
i2cDataLength <= 2;
i2cRegisters(i2cBaseAddress) <= -absSpeed;
i2cRegisters(i2cBaseAddress+1) <= -1;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
wait for 10*pwmPeriod;
assert forwards = '1'
report "Direction error"
severity error;
assert abs(motorSpeed_int+absSpeed) <= 2
report "PWM error"
severity error;
-- send speed 2
testInfo <= "speed 2 ";
write(output,
"Sending speed control to 2 forwards" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
absSpeed <= 2;
i2cBaseAddress <= baseAddress + 2; wait for 0 ns;
i2cDataLength <= 2;
i2cRegisters(i2cBaseAddress) <= absSpeed;
i2cRegisters(i2cBaseAddress+1) <= 0;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
wait for 10*pwmPeriod;
assert motorSpeed_int > 0
report "PWM error"
severity error;
-- send restart
testInfo <= "restart ";
write(output,
"Sending restart control" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
i2cBaseAddress <= orientationBaseAddress; wait for 0 ns;
i2cDataLength <= 1;
i2cRegisters(i2cBaseAddress) <= restart + btConnected;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
wait for 10*pwmPeriod;
assert motorSpeed_int = 0
report "PWM error"
severity error;
write(output,
"Stopping restart control" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
i2cBaseAddress <= orientationBaseAddress; wait for 0 ns;
i2cDataLength <= 1;
i2cRegisters(i2cBaseAddress) <= btConnected;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
wait for 10*pwmPeriod;
assert motorSpeed_int > 0
report "PWM error"
severity error;
-- loose BT connection
testInfo <= "loose BT conn. ";
write(output,
"Loosing BT connection" &
" at time " & integer'image(now/1 us) & " us" &
lf & lf
);
i2cBaseAddress <= orientationBaseAddress; wait for 0 ns;
i2cDataLength <= 1;
i2cRegisters(i2cBaseAddress) <= 0;
i2cWrite <= '1';
i2cSend <= '1', '0' after 1 ns;
wait until i2cDone = '1';
wait for 10*pwmPeriod;
assert motorSpeed_int = 0
report "PWM error"
severity error;
-- end of simulation
assert false
report "End of simulation"
severity failure;
wait;
end process;
--============================================================================
-- i2c send frame
sendI2cFrame: process
begin
i2cDone <= '0';
i2cSendWord <= '0';
sCl <= 'H';
sDa <= 'H';
wait until rising_edge(i2cSend);
-- start condition
sDa <= '0', 'H' after i2cPeriod;
wait for i2cPeriod/2;
-- send chip address
i2cDataOut <= to_unsigned(chipAddress/2, i2cDataOut'length-2) & '0' & '1';
i2cSendWord <= '1', '0' after 1 ns;
wait until falling_edge(i2cWordDone);
-- send register address
i2cDataOut <= to_unsigned(i2cBaseAddress, i2cDataOut'length-1) & '1';
i2cSendWord <= '1', '0' after 1 ns;
wait until falling_edge(i2cWordDone);
-- write access
if i2cWrite = '1' then
-- send data bytes
for wordIndex in i2cBaseAddress to i2cBaseAddress+i2cDataLength-1 loop
i2cDataOut <= unsigned(
to_signed(i2cRegisters(wordIndex), i2cDataOut'length-1) & '1'
);
if (i2cWrite = '0') and (wordIndex = i2cBaseAddress+i2cDataLength-1) then
i2cDataOut(0) <= '0';
end if;
i2cSendWord <= '1', '0' after 1 ns;
wait until falling_edge(i2cWordDone);
end loop;
-- read access
else
-- start condition
wait for 4*i2cPeriod;
sDa <= '0', 'H' after i2cPeriod;
wait for i2cPeriod/2;
-- send chip address
i2cDataOut <= to_unsigned(chipAddress/2, i2cDataOut'length-2) & not(i2cWrite) & '1';
i2cSendWord <= '1', '0' after 1 ns;
wait until falling_edge(i2cWordDone);
-- read data bytes
for wordIndex in i2cBaseAddress to i2cBaseAddress+i2cDataLength-1 loop
i2cDataOut <= unsigned(
to_signed(i2cRegisters(wordIndex), i2cDataOut'length-1) & '1'
);
if wordIndex < i2cBaseAddress+i2cDataLength-1 then
i2cDataOut(0) <= '0';
end if;
i2cSendWord <= '1', '0' after 1 ns;
wait until falling_edge(i2cWordDone);
end loop;
end if;
-- stop condition
sDa <= '0';
wait for i2cPeriod/2;
sCl <= 'H';
i2cDone <= '1';
wait for i2cPeriod/2;
end process sendI2cFrame;
------------------------------------------------------------------------------
-- i2c send and receive byte
sendI2cByte: process
variable i2cReadData: unsigned(i2cBitNb-1-1 downto 0);
begin
i2cWordDone <= '0';
sCl <= 'H' after i2cPeriod/4;
sDa <= 'H';
wait until rising_edge(i2cSendWord);
-- send byte
for bitIndex in i2cDataOut'range loop
sCl <= '0';
wait for i2cPeriod/4;
if i2cDataOut(bitIndex) = '0' then sDa <= '0'; else sDa <= 'H'; end if;
wait for i2cPeriod/4;
sCl <= 'H';
i2cReadData := shift_left(i2cReadData, 1);
i2cReadData(0) := to_X01(sDa);
wait for i2cPeriod/2;
end loop;
if i2cWrite = '0' then
i2cDataIn <= to_integer(shift_right(i2cReadData, 1));
end if;
sCl <= '0';
wait for i2cPeriod;
i2cWordDone <= '1';
wait for 1 ns;
end process sendI2cByte;
--============================================================================
-- PWM lowpass
lowpassIntegrator: process
begin
wait until rising_edge(sClock);
if pwm = '1' then
if (forwards xor to_unsigned(orientation1, 1)(0)) = '0' then
pwmLowpassAccumulator <= pwmLowpassAccumulator - motorSpeed + 1.0;
else
pwmLowpassAccumulator <= pwmLowpassAccumulator - motorSpeed - 1.0;
end if;
else
pwmLowpassAccumulator <= pwmLowpassAccumulator - motorSpeed;
end if;
end process lowpassIntegrator;
motorSpeed <= pwmLowpassAccumulator / 2.0**pwmLowpassShift;
motorSpeed_int <= integer(real(speedMaxValue) * motorSpeed);
END ARCHITECTURE test;
|
<reponame>slaclab/lcls-pcav
-------------------------------------------------------------------
-- System Generator version 2017.4 VHDL source file.
--
-- Copyright(C) 2017 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2017 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.conv_pkg.all;
entity example_xlAsynRegister is
generic (d_width : integer := 5; -- Width of d input
init_value : bit_vector := b"00"); -- Binary init value string
port (d : in std_logic_vector (d_width-1 downto 0);
rst : in std_logic_vector(0 downto 0) := "0";
en : in std_logic_vector(0 downto 0) := "1";
d_ce : in std_logic;
d_clk : in std_logic;
q_ce : in std_logic;
q_clk : in std_logic;
q : out std_logic_vector (d_width-1 downto 0));
end example_xlAsynRegister;
architecture behavior of example_xlAsynRegister is
component synth_reg_w_init
generic (width : integer;
init_index : integer;
init_value : bit_vector;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component; -- end synth_reg_w_init
signal internal_d_clr : std_logic;
signal internal_d_ce : std_logic;
signal internal_q_clr : std_logic;
signal internal_q_ce : std_logic;
signal d1_net : std_logic_vector (d_width-1 downto 0);
signal d2_net : std_logic_vector (d_width-1 downto 0);
signal d3_net : std_logic_vector (d_width-1 downto 0);
begin
internal_d_clr <= rst(0) and d_ce;
internal_d_ce <= en(0) and d_ce;
-- drive default values on enable and clear ports
internal_q_clr <= '0' and q_ce;
internal_q_ce <= '1' and q_ce;
-- Synthesizable behavioral model
synth_reg_inst_0 : synth_reg_w_init
generic map (width => d_width,
init_index => 2,
init_value => init_value,
latency => 1)
port map (i => d,
ce => internal_d_ce,
clr => internal_d_clr,
clk => d_clk,
o => d1_net);
synth_reg_inst_1 : synth_reg_w_init
generic map (width => d_width,
init_index => 2,
init_value => init_value,
latency => 1)
port map (i => d1_net,
ce => internal_q_ce,
clr => internal_q_clr,
clk => q_clk,
o => d2_net);
synth_reg_inst_2 : synth_reg_w_init
generic map (width => d_width,
init_index => 2,
init_value => init_value,
latency => 1)
port map (i => d2_net,
ce => internal_q_ce,
clr => internal_q_clr,
clk => q_clk,
o => d3_net);
synth_reg_inst_3 : synth_reg_w_init
generic map (width => d_width,
init_index => 2,
init_value => init_value,
latency => 1)
port map (i => d3_net,
ce => internal_q_ce,
clr => internal_q_clr,
clk => q_clk,
o => q);
end architecture behavior;
library work;
use work.conv_pkg.all;
---------------------------------------------------------------------
--
-- Filename : xldsamp.vhd
--
-- Description : VHDL description of a block that is inserted into the
-- data path to down sample the data betwen two blocks
-- where the period is different between two blocks.
--
-- Mod. History : Changed clock timing on the down sampler. The
-- destination enable is delayed by one system clock
-- cycle and held until the next consecutive source
-- enable pulse. This change allows downsampler data
-- transitions to occur on the rising clock edge when
-- the destination ce is asserted.
-- : Added optional latency is the downsampler. Note, if
-- the latency is greater than 0, no shutter is used.
-- : Removed valid bit logic from wrapper
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.conv_pkg.all;
-- synthesis translate_off
library unisim;
use unisim.vcomponents.all;
-- synthesis translate_on
entity example_xldsamp is
generic (
d_width: integer := 12;
d_bin_pt: integer := 0;
d_arith: integer := xlUnsigned;
q_width: integer := 12;
q_bin_pt: integer := 0;
q_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
ds_ratio: integer := 2;
phase: integer := 0;
latency: integer := 1
);
port (
d: in std_logic_vector(d_width - 1 downto 0);
src_clk: in std_logic;
src_ce: in std_logic;
src_clr: in std_logic;
dest_clk: in std_logic;
dest_ce: in std_logic;
dest_clr: in std_logic;
en: in std_logic_vector(en_width - 1 downto 0);
rst: in std_logic_vector(rst_width - 1 downto 0);
q: out std_logic_vector(q_width - 1 downto 0)
);
end example_xldsamp;
architecture struct of example_xldsamp is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component; -- end synth_reg
component synth_reg_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component fdse
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
s: in std_ulogic;
ce: in std_ulogic
);
end component; -- end fdse
attribute syn_black_box of fdse: component is true;
attribute fpga_dont_touch of fdse: component is "true";
signal adjusted_dest_ce: std_logic;
signal adjusted_dest_ce_w_en: std_logic;
signal dest_ce_w_en: std_logic;
signal smpld_d: std_logic_vector(d_width-1 downto 0);
signal sclr:std_logic;
begin
-- An 'adjusted' destination clock enable signal must be generated for
-- the zero latency and double registered down-sampler implementations.
-- For both cases, it is necassary to adjust the timing of the clock
-- enable so that it is asserted at the start of the sample period,
-- instead of the end. This is realized using an fdse prim. to register
-- the destination clock enable. The fdse itself is enabled with the
-- source clock enable. Enabling the fdse holds the adjusted CE high
-- for the duration of the fast sample period and is needed to satisfy
-- the multicycle constraint if the input data is running at a non-system
-- rate.
adjusted_ce_needed: if ((latency = 0) or (phase /= (ds_ratio - 1))) generate
dest_ce_reg: fdse
port map (
q => adjusted_dest_ce,
d => dest_ce,
c => src_clk,
s => sclr,
ce => src_ce
);
end generate; -- adjusted_ce_needed
-- A shutter (mux/reg pair) is used to implement a 0 latency downsampler.
-- The shutter uses the adjusted destination clock enable to select between
-- the current input and the sampled input.
latency_eq_0: if (latency = 0) generate
shutter_d_reg: synth_reg
generic map (
width => d_width,
latency => 1
)
port map (
i => d,
ce => adjusted_dest_ce,
clr => sclr,
clk => src_clk,
o => smpld_d
);
-- Mux selects current input value or register value.
shutter_mux: process (adjusted_dest_ce, d, smpld_d)
begin
if adjusted_dest_ce = '0' then
q <= smpld_d;
else
q <= d;
end if;
end process; -- end select_mux
end generate; -- end latency_eq_0
-- A more efficient downsampler can be implemented if a latency > 0 is
-- allowed. There are two possible implementations, depending on the
-- requested sampling phase. A double register downsampler is needed
-- for all cases except when the sample phase is the last input frame
-- of the sample period. In this case, only one register is needed.
latency_gt_0: if (latency > 0) generate
-- The first register in the double reg implementation is used to
-- sample the correct frame (phase) of the input data. Both the
-- data and valid bit must be sampled.
dbl_reg_test: if (phase /= (ds_ratio-1)) generate
smpl_d_reg: synth_reg_reg
generic map (
width => d_width,
latency => 1
)
port map (
i => d,
ce => adjusted_dest_ce_w_en,
clr => sclr,
clk => src_clk,
o => smpld_d
);
end generate; -- end dbl_reg_test
sngl_reg_test: if (phase = (ds_ratio -1)) generate
smpld_d <= d;
end generate; -- sngl_reg_test
-- The latency pipe captures the sampled data and the END of the sample
-- period. Note that if the requested sample phase is the last input
-- frame in the period, the first register (smpl_reg) is not needed.
latency_pipe: synth_reg_reg
generic map (
width => d_width,
latency => latency
)
port map (
i => smpld_d,
ce => dest_ce_w_en,
clr => sclr,
clk => dest_clk,
o => q
);
end generate; -- end latency_gt_0
-- Signal assignments
dest_ce_w_en <= dest_ce and en(0);
adjusted_dest_ce_w_en <= adjusted_dest_ce and en(0);
sclr <= (src_clr or rst(0)) and dest_ce;
end architecture struct;
library work;
use work.conv_pkg.all;
---------------------------------------------------------------------
--
-- Filename : xlregister.vhd
--
-- Description : VHDL description of an arbitrary wide register.
-- Unlike the delay block, an initial value is
-- specified and is considered valid at the start
-- of simulation. The register is only one word
-- deep.
--
-- Mod. History : Removed valid bit logic from wrapper.
-- : Changed VHDL to use a bit_vector generic for its
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.conv_pkg.all;
entity example_xlregister is
generic (d_width : integer := 5; -- Width of d input
init_value : bit_vector := b"00"); -- Binary init value string
port (d : in std_logic_vector (d_width-1 downto 0);
rst : in std_logic_vector(0 downto 0) := "0";
en : in std_logic_vector(0 downto 0) := "1";
ce : in std_logic;
clk : in std_logic;
q : out std_logic_vector (d_width-1 downto 0));
end example_xlregister;
architecture behavior of example_xlregister is
component synth_reg_w_init
generic (width : integer;
init_index : integer;
init_value : bit_vector;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component; -- end synth_reg_w_init
-- synthesis translate_off
signal real_d, real_q : real; -- For debugging info ports
-- synthesis translate_on
signal internal_clr : std_logic;
signal internal_ce : std_logic;
begin
internal_clr <= rst(0) and ce;
internal_ce <= en(0) and ce;
-- Synthesizable behavioral model
synth_reg_inst : synth_reg_w_init
generic map (width => d_width,
init_index => 2,
init_value => init_value,
latency => 1)
port map (i => d,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => q);
end architecture behavior;
library work;
use work.conv_pkg.all;
----------------------------------------------------------------------------
--
-- Filename : xlusamp.vhd
--
-- Description : VHDL description of an up sampler. The input signal
-- has a larger period than the output signal's period
-- and the blocks's period is set on the Simulink mask
-- GUI.
--
-- Assumptions : Input size, bin_pt, etc. are the same as the output
--
-- Mod. History : Removed the shutter from the upsampler. A mux is used
-- to zero pad the data samples. The mux select line is
-- generated by registering the source enable signal
-- when the destination ce is asserted.
-- : Removed valid bits from wrapper.
--
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.conv_pkg.all;
-- synthesis translate_off
library unisim;
use unisim.vcomponents.all;
-- synthesis translate_on
entity example_xlusamp is
generic (
d_width : integer := 5; -- Width of d input
d_bin_pt : integer := 2; -- Binary point of input d
d_arith : integer := xlUnsigned; -- Type of arith of d input
q_width : integer := 5; -- Width of q output
q_bin_pt : integer := 2; -- Binary point of output q
q_arith : integer := xlUnsigned; -- Type of arith of output
en_width : integer := 1;
en_bin_pt : integer := 0;
en_arith : integer := xlUnsigned;
sampling_ratio : integer := 2;
latency : integer := 1;
copy_samples : integer := 0); -- if 0, output q = 0
-- when ce = 0, else sample
-- is held until next clk
port (
d : in std_logic_vector (d_width-1 downto 0);
src_clk : in std_logic;
src_ce : in std_logic;
src_clr : in std_logic;
dest_clk : in std_logic;
dest_ce : in std_logic;
dest_clr : in std_logic;
en : in std_logic_vector(en_width-1 downto 0);
q : out std_logic_vector (q_width-1 downto 0)
);
end example_xlusamp;
architecture struct of example_xlusamp is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component; -- end synth_reg
component FDSE
port (q : out std_ulogic;
d : in std_ulogic;
c : in std_ulogic;
s : in std_ulogic;
ce : in std_ulogic);
end component; -- end FDSE
attribute syn_black_box of FDSE : component is true;
attribute fpga_dont_touch of FDSE : component is "true";
signal zero : std_logic_vector (d_width-1 downto 0);
signal mux_sel : std_logic;
signal sampled_d : std_logic_vector (d_width-1 downto 0);
signal internal_ce : std_logic;
begin
-- If zero padding is required, a mux is used to switch between data input
-- and zeros. The mux select is generated by registering the source enable
-- signal. This register is enabled by the destination enable signal. This
-- has the effect of holding the select line high until the next consecutive
-- destination enable pulse, and thereby satisfying the timing constraints.
-- Signal assignments
-- register the source enable signal with the register enabled
-- by the destination enable
sel_gen : FDSE
port map (q => mux_sel,
d => src_ce,
c => src_clk,
s => src_clr,
ce => dest_ce);
-- Generate the user enable
internal_ce <= src_ce and en(0);
copy_samples_false : if (copy_samples = 0) generate
-- signal assignments
zero <= (others => '0');
-- purpose: latency is 0 and copy_samples is 0
-- type : combinational
-- inputs : mux_sel, d, zero
-- outputs: q
gen_q_cp_smpls_0_and_lat_0: if (latency = 0) generate
cp_smpls_0_and_lat_0: process (mux_sel, d, zero)
begin -- process cp_smpls_0_and_lat_0
if (mux_sel = '1') then
q <= d;
else
q <= zero;
end if;
end process cp_smpls_0_and_lat_0;
end generate; -- end gen_q_cp_smpls_0_and_lat_0
gen_q_cp_smpls_0_and_lat_gt_0: if (latency > 0) generate
sampled_d_reg: synth_reg
generic map (
width => d_width,
latency => latency
)
port map (
i => d,
ce => internal_ce,
clr => src_clr,
clk => src_clk,
o => sampled_d
);
gen_q_check_mux_sel: process (mux_sel, sampled_d, zero)
begin
if (mux_sel = '1') then
q <= sampled_d;
else
q <= zero;
end if;
end process gen_q_check_mux_sel;
end generate; -- end gen_q_cp_smpls_0_and_lat_gt_0
end generate; -- end copy_samples_false
-- If zero padding is not required, we can short the upsampler data inputs
-- to the upsampler data outputs when latency is 0.
-- This option uses no hardware resources.
copy_samples_true : if (copy_samples = 1) generate
gen_q_cp_smpls_1_and_lat_0: if (latency = 0) generate
q <= d;
end generate; -- end gen_q_cp_smpls_1_and_lat_0
gen_q_cp_smpls_1_and_lat_gt_0: if (latency > 0) generate
q <= sampled_d;
sampled_d_reg2: synth_reg
generic map (
width => d_width,
latency => latency
)
port map (
i => d,
ce => internal_ce,
clr => src_clr,
clk => src_clk,
o => sampled_d
);
end generate; -- end gen_q_cp_smpls_1_and_lat_gt_0
end generate; -- end copy_samples_true
end architecture struct;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_constant_fb6e2a12b8 is
port (
op : out std_logic_vector((32 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_constant_fb6e2a12b8;
architecture behavior of sysgen_constant_fb6e2a12b8
is
begin
op <= "00000000011110101000111100010100";
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_logical_cfc7fd815b is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_logical_cfc7fd815b;
architecture behavior of sysgen_logical_cfc7fd815b
is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
type array_type_latency_pipe_5_26 is array (0 to (1 - 1)) of std_logic;
signal latency_pipe_5_26: array_type_latency_pipe_5_26 := (
0 => '0');
signal latency_pipe_5_26_front_din: std_logic;
signal latency_pipe_5_26_back: std_logic;
signal latency_pipe_5_26_push_front_pop_back_en: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
latency_pipe_5_26_back <= latency_pipe_5_26(0);
proc_latency_pipe_5_26: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (latency_pipe_5_26_push_front_pop_back_en = '1')) then
latency_pipe_5_26(0) <= latency_pipe_5_26_front_din;
end if;
end if;
end process proc_latency_pipe_5_26;
fully_2_1_bit <= d0_1_24 and d1_1_27;
latency_pipe_5_26_front_din <= fully_2_1_bit;
latency_pipe_5_26_push_front_pop_back_en <= '1';
y <= std_logic_to_vector(latency_pipe_5_26_back);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_mux_2ecce3bf9e is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((26 - 1) downto 0);
d1 : in std_logic_vector((26 - 1) downto 0);
y : out std_logic_vector((26 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_mux_2ecce3bf9e;
architecture behavior of sysgen_mux_2ecce3bf9e
is
signal sel_1_20: std_logic_vector((1 - 1) downto 0);
signal d0_1_24: std_logic_vector((26 - 1) downto 0);
signal d1_1_27: std_logic_vector((26 - 1) downto 0);
type array_type_pipe_16_22 is array (0 to (1 - 1)) of std_logic_vector((26 - 1) downto 0);
signal pipe_16_22: array_type_pipe_16_22 := (
0 => "00000000000000000000000000");
signal pipe_16_22_front_din: std_logic_vector((26 - 1) downto 0);
signal pipe_16_22_back: std_logic_vector((26 - 1) downto 0);
signal pipe_16_22_push_front_pop_back_en: std_logic;
signal unregy_join_6_1: std_logic_vector((26 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
pipe_16_22_back <= pipe_16_22(0);
proc_pipe_16_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (pipe_16_22_push_front_pop_back_en = '1')) then
pipe_16_22(0) <= pipe_16_22_front_din;
end if;
end if;
end process proc_pipe_16_22;
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_1_20)
is
begin
case sel_1_20 is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
pipe_16_22_front_din <= unregy_join_6_1;
pipe_16_22_push_front_pop_back_en <= '1';
y <= pipe_16_22_back;
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_mux_0094ed69d3 is
port (
sel : in std_logic_vector((3 - 1) downto 0);
d0 : in std_logic_vector((18 - 1) downto 0);
d1 : in std_logic_vector((18 - 1) downto 0);
d2 : in std_logic_vector((18 - 1) downto 0);
d3 : in std_logic_vector((18 - 1) downto 0);
d4 : in std_logic_vector((18 - 1) downto 0);
d5 : in std_logic_vector((18 - 1) downto 0);
y : out std_logic_vector((18 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_mux_0094ed69d3;
architecture behavior of sysgen_mux_0094ed69d3
is
signal sel_1_20: std_logic_vector((3 - 1) downto 0);
signal d0_1_24: std_logic_vector((18 - 1) downto 0);
signal d1_1_27: std_logic_vector((18 - 1) downto 0);
signal d2_1_30: std_logic_vector((18 - 1) downto 0);
signal d3_1_33: std_logic_vector((18 - 1) downto 0);
signal d4_1_36: std_logic_vector((18 - 1) downto 0);
signal d5_1_39: std_logic_vector((18 - 1) downto 0);
type array_type_pipe_24_22 is array (0 to (1 - 1)) of std_logic_vector((18 - 1) downto 0);
signal pipe_24_22: array_type_pipe_24_22 := (
0 => "000000000000000000");
signal pipe_24_22_front_din: std_logic_vector((18 - 1) downto 0);
signal pipe_24_22_back: std_logic_vector((18 - 1) downto 0);
signal pipe_24_22_push_front_pop_back_en: std_logic;
signal unregy_join_6_1: std_logic_vector((18 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
d4_1_36 <= d4;
d5_1_39 <= d5;
pipe_24_22_back <= pipe_24_22(0);
proc_pipe_24_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (pipe_24_22_push_front_pop_back_en = '1')) then
pipe_24_22(0) <= pipe_24_22_front_din;
end if;
end if;
end process proc_pipe_24_22;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, d4_1_36, d5_1_39, sel_1_20)
is
begin
case sel_1_20 is
when "000" =>
unregy_join_6_1 <= d0_1_24;
when "001" =>
unregy_join_6_1 <= d1_1_27;
when "010" =>
unregy_join_6_1 <= d2_1_30;
when "011" =>
unregy_join_6_1 <= d3_1_33;
when "100" =>
unregy_join_6_1 <= d4_1_36;
when others =>
unregy_join_6_1 <= d5_1_39;
end case;
end process proc_switch_6_1;
pipe_24_22_front_din <= unregy_join_6_1;
pipe_24_22_push_front_pop_back_en <= '1';
y <= pipe_24_22_back;
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_mux_ab0ca26cb3 is
port (
sel : in std_logic_vector((3 - 1) downto 0);
d0 : in std_logic_vector((18 - 1) downto 0);
d1 : in std_logic_vector((18 - 1) downto 0);
d2 : in std_logic_vector((18 - 1) downto 0);
d3 : in std_logic_vector((18 - 1) downto 0);
d4 : in std_logic_vector((18 - 1) downto 0);
d5 : in std_logic_vector((18 - 1) downto 0);
y : out std_logic_vector((19 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_mux_ab0ca26cb3;
architecture behavior of sysgen_mux_ab0ca26cb3
is
signal sel_1_20: std_logic_vector((3 - 1) downto 0);
signal d0_1_24: std_logic_vector((18 - 1) downto 0);
signal d1_1_27: std_logic_vector((18 - 1) downto 0);
signal d2_1_30: std_logic_vector((18 - 1) downto 0);
signal d3_1_33: std_logic_vector((18 - 1) downto 0);
signal d4_1_36: std_logic_vector((18 - 1) downto 0);
signal d5_1_39: std_logic_vector((18 - 1) downto 0);
type array_type_pipe_24_22 is array (0 to (1 - 1)) of std_logic_vector((19 - 1) downto 0);
signal pipe_24_22: array_type_pipe_24_22 := (
0 => "0000000000000000000");
signal pipe_24_22_front_din: std_logic_vector((19 - 1) downto 0);
signal pipe_24_22_back: std_logic_vector((19 - 1) downto 0);
signal pipe_24_22_push_front_pop_back_en: std_logic;
signal unregy_join_6_1: std_logic_vector((19 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
d4_1_36 <= d4;
d5_1_39 <= d5;
pipe_24_22_back <= pipe_24_22(0);
proc_pipe_24_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (pipe_24_22_push_front_pop_back_en = '1')) then
pipe_24_22(0) <= pipe_24_22_front_din;
end if;
end if;
end process proc_pipe_24_22;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, d4_1_36, d5_1_39, sel_1_20)
is
begin
case sel_1_20 is
when "000" =>
unregy_join_6_1 <= cast(d0_1_24, 16, 19, 16, xlSigned);
when "001" =>
unregy_join_6_1 <= cast(d1_1_27, 16, 19, 16, xlSigned);
when "010" =>
unregy_join_6_1 <= cast(d2_1_30, 16, 19, 16, xlSigned);
when "011" =>
unregy_join_6_1 <= cast(d3_1_33, 16, 19, 16, xlSigned);
when "100" =>
unregy_join_6_1 <= cast(d4_1_36, 16, 19, 16, xlSigned);
when others =>
unregy_join_6_1 <= cast(d5_1_39, 15, 19, 16, xlSigned);
end case;
end process proc_switch_6_1;
pipe_24_22_front_din <= unregy_join_6_1;
pipe_24_22_push_front_pop_back_en <= '1';
y <= pipe_24_22_back;
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_mux_3e8717c2bf is
port (
sel : in std_logic_vector((2 - 1) downto 0);
d0 : in std_logic_vector((18 - 1) downto 0);
d1 : in std_logic_vector((18 - 1) downto 0);
d2 : in std_logic_vector((18 - 1) downto 0);
d3 : in std_logic_vector((18 - 1) downto 0);
y : out std_logic_vector((18 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_mux_3e8717c2bf;
architecture behavior of sysgen_mux_3e8717c2bf
is
signal sel_1_20: std_logic_vector((2 - 1) downto 0);
signal d0_1_24: std_logic_vector((18 - 1) downto 0);
signal d1_1_27: std_logic_vector((18 - 1) downto 0);
signal d2_1_30: std_logic_vector((18 - 1) downto 0);
signal d3_1_33: std_logic_vector((18 - 1) downto 0);
type array_type_pipe_20_22 is array (0 to (1 - 1)) of std_logic_vector((18 - 1) downto 0);
signal pipe_20_22: array_type_pipe_20_22 := (
0 => "000000000000000000");
signal pipe_20_22_front_din: std_logic_vector((18 - 1) downto 0);
signal pipe_20_22_back: std_logic_vector((18 - 1) downto 0);
signal pipe_20_22_push_front_pop_back_en: std_logic;
signal unregy_join_6_1: std_logic_vector((18 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
pipe_20_22_back <= pipe_20_22(0);
proc_pipe_20_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (pipe_20_22_push_front_pop_back_en = '1')) then
pipe_20_22(0) <= pipe_20_22_front_din;
end if;
end if;
end process proc_pipe_20_22;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20)
is
begin
case sel_1_20 is
when "00" =>
unregy_join_6_1 <= d0_1_24;
when "01" =>
unregy_join_6_1 <= d1_1_27;
when "10" =>
unregy_join_6_1 <= d2_1_30;
when others =>
unregy_join_6_1 <= d3_1_33;
end case;
end process proc_switch_6_1;
pipe_20_22_front_din <= unregy_join_6_1;
pipe_20_22_push_front_pop_back_en <= '1';
y <= pipe_20_22_back;
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_mux_61f4768113 is
port (
sel : in std_logic_vector((2 - 1) downto 0);
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
d2 : in std_logic_vector((1 - 1) downto 0);
d3 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_mux_61f4768113;
architecture behavior of sysgen_mux_61f4768113
is
signal sel_1_20: std_logic_vector((2 - 1) downto 0);
signal d0_1_24: std_logic_vector((1 - 1) downto 0);
signal d1_1_27: std_logic_vector((1 - 1) downto 0);
signal d2_1_30: std_logic_vector((1 - 1) downto 0);
signal d3_1_33: std_logic_vector((1 - 1) downto 0);
type array_type_pipe_20_22 is array (0 to (1 - 1)) of std_logic_vector((1 - 1) downto 0);
signal pipe_20_22: array_type_pipe_20_22 := (
0 => "0");
signal pipe_20_22_front_din: std_logic_vector((1 - 1) downto 0);
signal pipe_20_22_back: std_logic_vector((1 - 1) downto 0);
signal pipe_20_22_push_front_pop_back_en: std_logic;
signal unregy_join_6_1: std_logic_vector((1 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
pipe_20_22_back <= pipe_20_22(0);
proc_pipe_20_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (pipe_20_22_push_front_pop_back_en = '1')) then
pipe_20_22(0) <= pipe_20_22_front_din;
end if;
end if;
end process proc_pipe_20_22;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20)
is
begin
case sel_1_20 is
when "00" =>
unregy_join_6_1 <= d0_1_24;
when "01" =>
unregy_join_6_1 <= d1_1_27;
when "10" =>
unregy_join_6_1 <= d2_1_30;
when others =>
unregy_join_6_1 <= d3_1_33;
end case;
end process proc_switch_6_1;
pipe_20_22_front_din <= unregy_join_6_1;
pipe_20_22_push_front_pop_back_en <= '1';
y <= pipe_20_22_back;
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_mux_78e3bf8a5f is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((18 - 1) downto 0);
d1 : in std_logic_vector((18 - 1) downto 0);
y : out std_logic_vector((18 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_mux_78e3bf8a5f;
architecture behavior of sysgen_mux_78e3bf8a5f
is
signal sel_1_20: std_logic_vector((1 - 1) downto 0);
signal d0_1_24: std_logic_vector((18 - 1) downto 0);
signal d1_1_27: std_logic_vector((18 - 1) downto 0);
type array_type_pipe_16_22 is array (0 to (1 - 1)) of std_logic_vector((18 - 1) downto 0);
signal pipe_16_22: array_type_pipe_16_22 := (
0 => "000000000000000000");
signal pipe_16_22_front_din: std_logic_vector((18 - 1) downto 0);
signal pipe_16_22_back: std_logic_vector((18 - 1) downto 0);
signal pipe_16_22_push_front_pop_back_en: std_logic;
signal unregy_join_6_1: std_logic_vector((18 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
pipe_16_22_back <= pipe_16_22(0);
proc_pipe_16_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (pipe_16_22_push_front_pop_back_en = '1')) then
pipe_16_22(0) <= pipe_16_22_front_din;
end if;
end if;
end process proc_pipe_16_22;
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_1_20)
is
begin
case sel_1_20 is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
pipe_16_22_front_din <= unregy_join_6_1;
pipe_16_22_push_front_pop_back_en <= '1';
y <= pipe_16_22_back;
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_mux_0edfc3d320 is
port (
sel : in std_logic_vector((3 - 1) downto 0);
d0 : in std_logic_vector((18 - 1) downto 0);
d1 : in std_logic_vector((18 - 1) downto 0);
d2 : in std_logic_vector((18 - 1) downto 0);
d3 : in std_logic_vector((18 - 1) downto 0);
d4 : in std_logic_vector((18 - 1) downto 0);
d5 : in std_logic_vector((18 - 1) downto 0);
d6 : in std_logic_vector((18 - 1) downto 0);
d7 : in std_logic_vector((18 - 1) downto 0);
y : out std_logic_vector((18 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_mux_0edfc3d320;
architecture behavior of sysgen_mux_0edfc3d320
is
signal sel_1_20: std_logic_vector((3 - 1) downto 0);
signal d0_1_24: std_logic_vector((18 - 1) downto 0);
signal d1_1_27: std_logic_vector((18 - 1) downto 0);
signal d2_1_30: std_logic_vector((18 - 1) downto 0);
signal d3_1_33: std_logic_vector((18 - 1) downto 0);
signal d4_1_36: std_logic_vector((18 - 1) downto 0);
signal d5_1_39: std_logic_vector((18 - 1) downto 0);
signal d6_1_42: std_logic_vector((18 - 1) downto 0);
signal d7_1_45: std_logic_vector((18 - 1) downto 0);
type array_type_pipe_28_22 is array (0 to (1 - 1)) of std_logic_vector((18 - 1) downto 0);
signal pipe_28_22: array_type_pipe_28_22 := (
0 => "000000000000000000");
signal pipe_28_22_front_din: std_logic_vector((18 - 1) downto 0);
signal pipe_28_22_back: std_logic_vector((18 - 1) downto 0);
signal pipe_28_22_push_front_pop_back_en: std_logic;
signal unregy_join_6_1: std_logic_vector((18 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
d4_1_36 <= d4;
d5_1_39 <= d5;
d6_1_42 <= d6;
d7_1_45 <= d7;
pipe_28_22_back <= pipe_28_22(0);
proc_pipe_28_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (pipe_28_22_push_front_pop_back_en = '1')) then
pipe_28_22(0) <= pipe_28_22_front_din;
end if;
end if;
end process proc_pipe_28_22;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, d4_1_36, d5_1_39, d6_1_42, d7_1_45, sel_1_20)
is
begin
case sel_1_20 is
when "000" =>
unregy_join_6_1 <= d0_1_24;
when "001" =>
unregy_join_6_1 <= d1_1_27;
when "010" =>
unregy_join_6_1 <= d2_1_30;
when "011" =>
unregy_join_6_1 <= d3_1_33;
when "100" =>
unregy_join_6_1 <= d4_1_36;
when "101" =>
unregy_join_6_1 <= d5_1_39;
when "110" =>
unregy_join_6_1 <= d6_1_42;
when others =>
unregy_join_6_1 <= d7_1_45;
end case;
end process proc_switch_6_1;
pipe_28_22_front_din <= unregy_join_6_1;
pipe_28_22_push_front_pop_back_en <= '1';
y <= pipe_28_22_back;
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_mux_a1f42c2ba5 is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((8 - 1) downto 0);
d1 : in std_logic_vector((8 - 1) downto 0);
y : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_mux_a1f42c2ba5;
architecture behavior of sysgen_mux_a1f42c2ba5
is
signal sel_1_20: std_logic_vector((1 - 1) downto 0);
signal d0_1_24: std_logic_vector((8 - 1) downto 0);
signal d1_1_27: std_logic_vector((8 - 1) downto 0);
type array_type_pipe_16_22 is array (0 to (1 - 1)) of std_logic_vector((8 - 1) downto 0);
signal pipe_16_22: array_type_pipe_16_22 := (
0 => "00000000");
signal pipe_16_22_front_din: std_logic_vector((8 - 1) downto 0);
signal pipe_16_22_back: std_logic_vector((8 - 1) downto 0);
signal pipe_16_22_push_front_pop_back_en: std_logic;
signal unregy_join_6_1: std_logic_vector((8 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
pipe_16_22_back <= pipe_16_22(0);
proc_pipe_16_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (pipe_16_22_push_front_pop_back_en = '1')) then
pipe_16_22(0) <= pipe_16_22_front_din;
end if;
end if;
end process proc_pipe_16_22;
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_1_20)
is
begin
case sel_1_20 is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
pipe_16_22_front_din <= unregy_join_6_1;
pipe_16_22_push_front_pop_back_en <= '1';
y <= pipe_16_22_back;
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_constant_8d20022674 is
port (
op : out std_logic_vector((18 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_constant_8d20022674;
architecture behavior of sysgen_constant_8d20022674
is
begin
op <= "000000000000000000";
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_constant_1dd3b42785 is
port (
op : out std_logic_vector((3 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_constant_1dd3b42785;
architecture behavior of sysgen_constant_1dd3b42785
is
begin
op <= "000";
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_constant_146af16123 is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_constant_146af16123;
architecture behavior of sysgen_constant_146af16123
is
begin
op <= "0";
end behavior;
library work;
use work.conv_pkg.all;
--$Header: /devl/xcs/repo/env/Jobs/sysgen/src/xbs/blocks/xlconvert/hdl/xlconvert.vhd,v 1.1 2004/11/22 00:17:30 rosty Exp $
---------------------------------------------------------------------
--
-- Filename : xlconvert.vhd
--
-- Description : VHDL description of a fixed point converter block that
-- converts the input to a new output type.
--
---------------------------------------------------------------------
---------------------------------------------------------------------
--
-- Entity : xlconvert
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of fixed point conver block.
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.conv_pkg.all;
entity convert_func_call_example_xlconvert is
generic (
din_width : integer := 16; -- Width of input
din_bin_pt : integer := 4; -- Binary point of input
din_arith : integer := xlUnsigned; -- Type of arith of input
dout_width : integer := 8; -- Width of output
dout_bin_pt : integer := 2; -- Binary point of output
dout_arith : integer := xlUnsigned; -- Type of arith of output
quantization : integer := xlTruncate; -- xlRound or xlTruncate
overflow : integer := xlWrap); -- xlSaturate or xlWrap
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end convert_func_call_example_xlconvert ;
architecture behavior of convert_func_call_example_xlconvert is
begin
-- Convert to output type and do saturation arith.
result <= convert_type(din, din_width, din_bin_pt, din_arith,
dout_width, dout_bin_pt, dout_arith,
quantization, overflow);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.conv_pkg.all;
entity example_xlconvert is
generic (
din_width : integer := 16; -- Width of input
din_bin_pt : integer := 4; -- Binary point of input
din_arith : integer := xlUnsigned; -- Type of arith of input
dout_width : integer := 8; -- Width of output
dout_bin_pt : integer := 2; -- Binary point of output
dout_arith : integer := xlUnsigned; -- Type of arith of output
en_width : integer := 1;
en_bin_pt : integer := 0;
en_arith : integer := xlUnsigned;
bool_conversion : integer :=0; -- if one, convert ufix_1_0 to
-- bool
latency : integer := 0; -- Ouput delay clk cycles
quantization : integer := xlTruncate; -- xlRound or xlTruncate
overflow : integer := xlWrap); -- xlSaturate or xlWrap
port (
din : in std_logic_vector (din_width-1 downto 0);
en : in std_logic_vector (en_width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
dout : out std_logic_vector (dout_width-1 downto 0));
end example_xlconvert ;
architecture behavior of example_xlconvert is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component convert_func_call_example_xlconvert
generic (
din_width : integer := 16; -- Width of input
din_bin_pt : integer := 4; -- Binary point of input
din_arith : integer := xlUnsigned; -- Type of arith of input
dout_width : integer := 8; -- Width of output
dout_bin_pt : integer := 2; -- Binary point of output
dout_arith : integer := xlUnsigned; -- Type of arith of output
quantization : integer := xlTruncate; -- xlRound or xlTruncate
overflow : integer := xlWrap); -- xlSaturate or xlWrap
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end component;
-- synthesis translate_off
-- signal real_din, real_dout : real; -- For debugging info ports
-- synthesis translate_on
signal result : std_logic_vector(dout_width-1 downto 0);
signal internal_ce : std_logic;
begin
-- Debugging info for internal full precision variables
-- synthesis translate_off
-- real_din <= to_real(din, din_bin_pt, din_arith);
-- real_dout <= to_real(dout, dout_bin_pt, dout_arith);
-- synthesis translate_on
internal_ce <= ce and en(0);
bool_conversion_generate : if (bool_conversion = 1)
generate
result <= din;
end generate; --bool_conversion_generate
std_conversion_generate : if (bool_conversion = 0)
generate
-- Workaround for XST bug
convert : convert_func_call_example_xlconvert
generic map (
din_width => din_width,
din_bin_pt => din_bin_pt,
din_arith => din_arith,
dout_width => dout_width,
dout_bin_pt => dout_bin_pt,
dout_arith => dout_arith,
quantization => quantization,
overflow => overflow)
port map (
din => din,
result => result);
end generate; --std_conversion_generate
latency_test : if (latency > 0) generate
reg : synth_reg
generic map (
width => dout_width,
latency => latency
)
port map (
i => result,
ce => internal_ce,
clr => clr,
clk => clk,
o => dout
);
end generate;
latency0 : if (latency = 0)
generate
dout <= result;
end generate latency0;
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_counter_6798bb4fe3 is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_counter_6798bb4fe3;
architecture behavior of sysgen_counter_6798bb4fe3
is
signal count_reg_20_23: unsigned((1 - 1) downto 0) := "0";
begin
proc_count_reg_20_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if (ce = '1') then
count_reg_20_23 <= count_reg_20_23 + std_logic_vector_to_unsigned("1");
end if;
end if;
end process proc_count_reg_20_23;
op <= unsigned_to_std_logic_vector(count_reg_20_23);
end behavior;
library work;
use work.conv_pkg.all;
---------------------------------------------------------------------
--
-- Filename : xlceprobe.vhd
--
-- Description : VHDL description of system clock enable probe.
-- This block assigns the clock enable signal to
-- the output port.
-- Mod. History : Added beffer so the the ce nets would not get renamed
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.conv_pkg.all;
-- synthesis translate_off
library unisim;
use unisim.vcomponents.all;
-- synthesis translate_on
entity example_xlceprobe is
generic (d_width : integer := 8;
q_width : integer := 1);
port (d : in std_logic_vector (d_width-1 downto 0);
ce : in std_logic;
clk : in std_logic;
q : out std_logic_vector (q_width-1 downto 0));
end example_xlceprobe;
architecture behavior of example_xlceprobe is
component BUF
port(
O : out STD_ULOGIC;
I : in STD_ULOGIC);
end component;
attribute syn_black_box of BUF : component is true;
attribute fpga_dont_touch of BUF : component is "true";
signal ce_vec : std_logic_vector(0 downto 0);
begin
buf_comp : buf port map(i => ce, o => ce_vec(0));
-- use the clock enable signal to drive the output port
q <= ce_vec;
end architecture behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_constant_589172b339 is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_constant_589172b339;
architecture behavior of sysgen_constant_589172b339
is
begin
op <= "1";
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_logical_90a43f8277 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_logical_90a43f8277;
architecture behavior of sysgen_logical_90a43f8277
is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
type array_type_latency_pipe_5_26 is array (0 to (1 - 1)) of std_logic;
signal latency_pipe_5_26: array_type_latency_pipe_5_26 := (
0 => '0');
signal latency_pipe_5_26_front_din: std_logic;
signal latency_pipe_5_26_back: std_logic;
signal latency_pipe_5_26_push_front_pop_back_en: std_logic;
signal bit_2_27: std_logic;
signal fully_2_1_bitnot: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
latency_pipe_5_26_back <= latency_pipe_5_26(0);
proc_latency_pipe_5_26: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (latency_pipe_5_26_push_front_pop_back_en = '1')) then
latency_pipe_5_26(0) <= latency_pipe_5_26_front_din;
end if;
end if;
end process proc_latency_pipe_5_26;
bit_2_27 <= d0_1_24 and d1_1_27;
fully_2_1_bitnot <= not bit_2_27;
latency_pipe_5_26_front_din <= fully_2_1_bitnot;
latency_pipe_5_26_push_front_pop_back_en <= '1';
y <= std_logic_to_vector(latency_pipe_5_26_back);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.conv_pkg.all;
entity example_xldelay is
generic(width : integer := -1;
latency : integer := -1;
reg_retiming : integer := 0;
reset : integer := 0);
port(d : in std_logic_vector (width-1 downto 0);
ce : in std_logic;
clk : in std_logic;
en : in std_logic;
rst : in std_logic;
q : out std_logic_vector (width-1 downto 0));
end example_xldelay;
architecture behavior of example_xldelay is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component; -- end component synth_reg
component synth_reg_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
signal internal_ce : std_logic;
begin
internal_ce <= ce and en;
srl_delay: if ((reg_retiming = 0) and (reset = 0)) or (latency < 1) generate
synth_reg_srl_inst : synth_reg
generic map (
width => width,
latency => latency)
port map (
i => d,
ce => internal_ce,
clr => '0',
clk => clk,
o => q);
end generate srl_delay;
reg_delay: if ((reg_retiming = 1) or (reset = 1)) and (latency >= 1) generate
synth_reg_reg_inst : synth_reg_reg
generic map (
width => width,
latency => latency)
port map (
i => d,
ce => internal_ce,
clr => rst,
clk => clk,
o => q);
end generate reg_delay;
end architecture behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_accum_34d1bd443e is
port (
b : in std_logic_vector((18 - 1) downto 0);
rst : in std_logic_vector((1 - 1) downto 0);
q : out std_logic_vector((26 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_accum_34d1bd443e;
architecture behavior of sysgen_accum_34d1bd443e
is
signal b_17_24: signed((18 - 1) downto 0);
signal rst_17_27: boolean;
signal accum_reg_39_23: signed((26 - 1) downto 0) := "00000000000000000000000000";
signal accum_reg_39_23_rst: std_logic;
signal cast_49_42: signed((26 - 1) downto 0);
signal accum_reg_join_45_1: signed((27 - 1) downto 0);
signal accum_reg_join_45_1_rst: std_logic;
begin
b_17_24 <= std_logic_vector_to_signed(b);
rst_17_27 <= ((rst) = "1");
proc_accum_reg_39_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (accum_reg_39_23_rst = '1')) then
accum_reg_39_23 <= "00000000000000000000000000";
elsif (ce = '1') then
accum_reg_39_23 <= accum_reg_39_23 + cast_49_42;
end if;
end if;
end process proc_accum_reg_39_23;
cast_49_42 <= s2s_cast(b_17_24, 16, 26, 16);
proc_if_45_1: process (accum_reg_39_23, cast_49_42, rst_17_27)
is
begin
if rst_17_27 then
accum_reg_join_45_1_rst <= '1';
else
accum_reg_join_45_1_rst <= '0';
end if;
end process proc_if_45_1;
accum_reg_39_23_rst <= accum_reg_join_45_1_rst;
q <= signed_to_std_logic_vector(accum_reg_39_23);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_inverter_afe636f99c is
port (
ip : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_inverter_afe636f99c;
architecture behavior of sysgen_inverter_afe636f99c
is
signal ip_1_26: boolean;
type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean;
signal op_mem_22_20: array_type_op_mem_22_20 := (
0 => false);
signal op_mem_22_20_front_din: boolean;
signal op_mem_22_20_back: boolean;
signal op_mem_22_20_push_front_pop_back_en: std_logic;
signal internal_ip_12_1_bitnot: boolean;
begin
ip_1_26 <= ((ip) = "1");
op_mem_22_20_back <= op_mem_22_20(0);
proc_op_mem_22_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
op_mem_22_20(0) <= op_mem_22_20_front_din;
end if;
end if;
end process proc_op_mem_22_20;
internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1");
op_mem_22_20_front_din <= internal_ip_12_1_bitnot;
op_mem_22_20_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_22_20_back);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_abs_50a30d246f is
port (
a : in std_logic_vector((26 - 1) downto 0);
op : out std_logic_vector((27 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_abs_50a30d246f;
architecture behavior of sysgen_abs_50a30d246f
is
signal a_16_25: signed((26 - 1) downto 0);
type array_type_op_mem_48_20 is array (0 to (1 - 1)) of signed((27 - 1) downto 0);
signal op_mem_48_20: array_type_op_mem_48_20 := (
0 => "000000000000000000000000000");
signal op_mem_48_20_front_din: signed((27 - 1) downto 0);
signal op_mem_48_20_back: signed((27 - 1) downto 0);
signal op_mem_48_20_push_front_pop_back_en: std_logic;
signal cast_34_28: signed((27 - 1) downto 0);
signal internal_ip_34_13_neg: signed((27 - 1) downto 0);
signal rel_31_8: boolean;
signal internal_ip_join_31_5: signed((27 - 1) downto 0);
signal internal_ip_join_28_1: signed((27 - 1) downto 0);
begin
a_16_25 <= std_logic_vector_to_signed(a);
op_mem_48_20_back <= op_mem_48_20(0);
proc_op_mem_48_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_48_20_push_front_pop_back_en = '1')) then
op_mem_48_20(0) <= op_mem_48_20_front_din;
end if;
end if;
end process proc_op_mem_48_20;
cast_34_28 <= s2s_cast(a_16_25, 16, 27, 16);
internal_ip_34_13_neg <= -cast_34_28;
rel_31_8 <= a_16_25 >= std_logic_vector_to_signed("00000000000000000000000000");
proc_if_31_5: process (a_16_25, internal_ip_34_13_neg, rel_31_8)
is
begin
if rel_31_8 then
internal_ip_join_31_5 <= s2s_cast(a_16_25, 16, 27, 16);
else
internal_ip_join_31_5 <= internal_ip_34_13_neg;
end if;
end process proc_if_31_5;
proc_if_28_1: process (internal_ip_join_31_5)
is
begin
if false then
internal_ip_join_28_1 <= std_logic_vector_to_signed("000000000000000000000000000");
else
internal_ip_join_28_1 <= internal_ip_join_31_5;
end if;
end process proc_if_28_1;
op_mem_48_20_front_din <= internal_ip_join_28_1;
op_mem_48_20_push_front_pop_back_en <= '1';
op <= signed_to_std_logic_vector(op_mem_48_20_back);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_mcode_block_d71a35a319 is
port (
i_int : in std_logic_vector((26 - 1) downto 0);
q_int : in std_logic_vector((26 - 1) downto 0);
i_int_abs : in std_logic_vector((27 - 1) downto 0);
q_int_abs : in std_logic_vector((27 - 1) downto 0);
i_norm : out std_logic_vector((37 - 1) downto 0);
q_norm : out std_logic_vector((37 - 1) downto 0);
done : out std_logic_vector((1 - 1) downto 0);
bit : out std_logic_vector((4 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_mcode_block_d71a35a319;
architecture behavior of sysgen_mcode_block_d71a35a319
is
signal i_int_1_62: signed((26 - 1) downto 0);
signal q_int_1_69: signed((26 - 1) downto 0);
signal i_int_abs_1_76: signed((27 - 1) downto 0);
signal q_int_abs_1_87: signed((27 - 1) downto 0);
signal cast_i_norm_23_5_rsh: signed((27 - 1) downto 0);
signal cast_q_norm_24_5_rsh: signed((27 - 1) downto 0);
signal rel_17_5: boolean;
signal rel_17_26: boolean;
signal bool_17_5: boolean;
signal cast_22_9: signed((28 - 1) downto 0);
signal rel_22_9: boolean;
signal cast_22_29: signed((28 - 1) downto 0);
signal rel_22_29: boolean;
signal bool_22_9: boolean;
signal rel_27_10: boolean;
signal cast_27_29: signed((28 - 1) downto 0);
signal rel_27_29: boolean;
signal bool_27_10: boolean;
signal rel_27_52: boolean;
signal cast_27_71: signed((28 - 1) downto 0);
signal rel_27_71: boolean;
signal bool_27_52: boolean;
signal bool_27_10_x_000000: boolean;
signal rel_32_10: boolean;
signal rel_32_29: boolean;
signal bool_32_10: boolean;
signal rel_32_51: boolean;
signal rel_32_70: boolean;
signal bool_32_51: boolean;
signal bool_32_10_x_000000: boolean;
signal rel_37_10: boolean;
signal rel_37_29: boolean;
signal bool_37_10: boolean;
signal rel_37_51: boolean;
signal rel_37_70: boolean;
signal bool_37_51: boolean;
signal bool_37_10_x_000000: boolean;
signal rel_42_10: boolean;
signal rel_42_29: boolean;
signal bool_42_10: boolean;
signal rel_42_51: boolean;
signal rel_42_70: boolean;
signal bool_42_51: boolean;
signal bool_42_10_x_000000: boolean;
signal rel_47_10: boolean;
signal rel_47_29: boolean;
signal bool_47_10: boolean;
signal rel_47_51: boolean;
signal rel_47_70: boolean;
signal bool_47_51: boolean;
signal bool_47_10_x_000000: boolean;
signal rel_52_10: boolean;
signal rel_52_29: boolean;
signal bool_52_10: boolean;
signal rel_52_51: boolean;
signal rel_52_70: boolean;
signal bool_52_51: boolean;
signal bool_52_10_x_000000: boolean;
signal rel_57_10: boolean;
signal rel_57_29: boolean;
signal bool_57_10: boolean;
signal rel_57_51: boolean;
signal rel_57_70: boolean;
signal bool_57_51: boolean;
signal bool_57_10_x_000000: boolean;
signal rel_62_10: boolean;
signal rel_62_29: boolean;
signal bool_62_10: boolean;
signal rel_62_51: boolean;
signal rel_62_70: boolean;
signal bool_62_51: boolean;
signal bool_62_10_x_000000: boolean;
signal rel_67_10: boolean;
signal rel_67_29: boolean;
signal bool_67_10: boolean;
signal rel_67_51: boolean;
signal rel_67_70: boolean;
signal bool_67_51: boolean;
signal bool_67_10_x_000000: boolean;
signal bit_join_17_1: unsigned((4 - 1) downto 0);
signal done_join_17_1: unsigned((1 - 1) downto 0);
signal i_norm_join_17_1: signed((37 - 1) downto 0);
signal q_norm_join_17_1: signed((37 - 1) downto 0);
begin
i_int_1_62 <= std_logic_vector_to_signed(i_int);
q_int_1_69 <= std_logic_vector_to_signed(q_int);
i_int_abs_1_76 <= std_logic_vector_to_signed(i_int_abs);
q_int_abs_1_87 <= std_logic_vector_to_signed(q_int_abs);
cast_i_norm_23_5_rsh <= s2s_cast(i_int_1_62, 16, 27, 16);
cast_q_norm_24_5_rsh <= s2s_cast(q_int_1_69, 16, 27, 16);
rel_17_5 <= i_int_abs_1_76 <= std_logic_vector_to_signed("000000000010000000000000000");
rel_17_26 <= q_int_abs_1_87 <= std_logic_vector_to_signed("000000000010000000000000000");
bool_17_5 <= rel_17_5 and rel_17_26;
cast_22_9 <= s2s_cast(i_int_abs_1_76, 16, 28, 16);
rel_22_9 <= cast_22_9 > std_logic_vector_to_signed("0100000000000000000000000000");
cast_22_29 <= s2s_cast(q_int_abs_1_87, 16, 28, 16);
rel_22_29 <= cast_22_29 > std_logic_vector_to_signed("0100000000000000000000000000");
bool_22_9 <= rel_22_9 or rel_22_29;
rel_27_10 <= i_int_abs_1_76 > std_logic_vector_to_signed("010000000000000000000000000");
cast_27_29 <= s2s_cast(i_int_abs_1_76, 16, 28, 16);
rel_27_29 <= cast_27_29 <= std_logic_vector_to_signed("0100000000000000000000000000");
bool_27_10 <= rel_27_10 and rel_27_29;
rel_27_52 <= q_int_abs_1_87 > std_logic_vector_to_signed("010000000000000000000000000");
cast_27_71 <= s2s_cast(q_int_abs_1_87, 16, 28, 16);
rel_27_71 <= cast_27_71 <= std_logic_vector_to_signed("0100000000000000000000000000");
bool_27_52 <= rel_27_52 and rel_27_71;
bool_27_10_x_000000 <= bool_27_10 or bool_27_52;
rel_32_10 <= i_int_abs_1_76 > std_logic_vector_to_signed("001000000000000000000000000");
rel_32_29 <= i_int_abs_1_76 <= std_logic_vector_to_signed("010000000000000000000000000");
bool_32_10 <= rel_32_10 and rel_32_29;
rel_32_51 <= q_int_abs_1_87 > std_logic_vector_to_signed("001000000000000000000000000");
rel_32_70 <= q_int_abs_1_87 <= std_logic_vector_to_signed("010000000000000000000000000");
bool_32_51 <= rel_32_51 and rel_32_70;
bool_32_10_x_000000 <= bool_32_10 or bool_32_51;
rel_37_10 <= i_int_abs_1_76 > std_logic_vector_to_signed("000100000000000000000000000");
rel_37_29 <= i_int_abs_1_76 <= std_logic_vector_to_signed("001000000000000000000000000");
bool_37_10 <= rel_37_10 and rel_37_29;
rel_37_51 <= q_int_abs_1_87 > std_logic_vector_to_signed("000100000000000000000000000");
rel_37_70 <= q_int_abs_1_87 <= std_logic_vector_to_signed("001000000000000000000000000");
bool_37_51 <= rel_37_51 and rel_37_70;
bool_37_10_x_000000 <= bool_37_10 or bool_37_51;
rel_42_10 <= i_int_abs_1_76 > std_logic_vector_to_signed("000010000000000000000000000");
rel_42_29 <= i_int_abs_1_76 <= std_logic_vector_to_signed("000100000000000000000000000");
bool_42_10 <= rel_42_10 and rel_42_29;
rel_42_51 <= q_int_abs_1_87 > std_logic_vector_to_signed("000010000000000000000000000");
rel_42_70 <= q_int_abs_1_87 <= std_logic_vector_to_signed("000100000000000000000000000");
bool_42_51 <= rel_42_51 and rel_42_70;
bool_42_10_x_000000 <= bool_42_10 or bool_42_51;
rel_47_10 <= i_int_abs_1_76 > std_logic_vector_to_signed("000001000000000000000000000");
rel_47_29 <= i_int_abs_1_76 <= std_logic_vector_to_signed("000010000000000000000000000");
bool_47_10 <= rel_47_10 and rel_47_29;
rel_47_51 <= q_int_abs_1_87 > std_logic_vector_to_signed("000001000000000000000000000");
rel_47_70 <= q_int_abs_1_87 <= std_logic_vector_to_signed("000010000000000000000000000");
bool_47_51 <= rel_47_51 and rel_47_70;
bool_47_10_x_000000 <= bool_47_10 or bool_47_51;
rel_52_10 <= i_int_abs_1_76 > std_logic_vector_to_signed("000000100000000000000000000");
rel_52_29 <= i_int_abs_1_76 <= std_logic_vector_to_signed("000001000000000000000000000");
bool_52_10 <= rel_52_10 and rel_52_29;
rel_52_51 <= q_int_abs_1_87 > std_logic_vector_to_signed("000000100000000000000000000");
rel_52_70 <= q_int_abs_1_87 <= std_logic_vector_to_signed("000001000000000000000000000");
bool_52_51 <= rel_52_51 and rel_52_70;
bool_52_10_x_000000 <= bool_52_10 or bool_52_51;
rel_57_10 <= i_int_abs_1_76 > std_logic_vector_to_signed("000000010000000000000000000");
rel_57_29 <= i_int_abs_1_76 <= std_logic_vector_to_signed("000000100000000000000000000");
bool_57_10 <= rel_57_10 and rel_57_29;
rel_57_51 <= q_int_abs_1_87 > std_logic_vector_to_signed("000000010000000000000000000");
rel_57_70 <= q_int_abs_1_87 <= std_logic_vector_to_signed("000000100000000000000000000");
bool_57_51 <= rel_57_51 and rel_57_70;
bool_57_10_x_000000 <= bool_57_10 or bool_57_51;
rel_62_10 <= i_int_abs_1_76 > std_logic_vector_to_signed("000000001000000000000000000");
rel_62_29 <= i_int_abs_1_76 <= std_logic_vector_to_signed("000000010000000000000000000");
bool_62_10 <= rel_62_10 and rel_62_29;
rel_62_51 <= q_int_abs_1_87 > std_logic_vector_to_signed("000000001000000000000000000");
rel_62_70 <= q_int_abs_1_87 <= std_logic_vector_to_signed("000000010000000000000000000");
bool_62_51 <= rel_62_51 and rel_62_70;
bool_62_10_x_000000 <= bool_62_10 or bool_62_51;
rel_67_10 <= i_int_abs_1_76 > std_logic_vector_to_signed("000000000100000000000000000");
rel_67_29 <= i_int_abs_1_76 <= std_logic_vector_to_signed("000000001000000000000000000");
bool_67_10 <= rel_67_10 and rel_67_29;
rel_67_51 <= q_int_abs_1_87 > std_logic_vector_to_signed("000000000100000000000000000");
rel_67_70 <= q_int_abs_1_87 <= std_logic_vector_to_signed("000000001000000000000000000");
bool_67_51 <= rel_67_51 and rel_67_70;
bool_67_10_x_000000 <= bool_67_10 or bool_67_51;
proc_if_17_1: process (bool_17_5, bool_22_9, bool_27_10_x_000000, bool_32_10_x_000000, bool_37_10_x_000000, bool_42_10_x_000000, bool_47_10_x_000000, bool_52_10_x_000000, bool_57_10_x_000000, bool_62_10_x_000000, bool_67_10_x_000000, cast_i_norm_23_5_rsh, cast_q_norm_24_5_rsh, i_int_1_62, q_int_1_69)
is
begin
if bool_17_5 then
bit_join_17_1 <= std_logic_vector_to_unsigned("0000");
done_join_17_1 <= std_logic_vector_to_unsigned("1");
i_norm_join_17_1 <= s2s_cast(i_int_1_62, 16, 37, 27);
q_norm_join_17_1 <= s2s_cast(q_int_1_69, 16, 37, 27);
elsif bool_22_9 then
bit_join_17_1 <= std_logic_vector_to_unsigned("1010");
done_join_17_1 <= std_logic_vector_to_unsigned("1");
i_norm_join_17_1 <= s2s_cast(cast_i_norm_23_5_rsh, 27, 37, 27);
q_norm_join_17_1 <= s2s_cast(cast_q_norm_24_5_rsh, 27, 37, 27);
elsif bool_27_10_x_000000 then
bit_join_17_1 <= std_logic_vector_to_unsigned("1001");
done_join_17_1 <= std_logic_vector_to_unsigned("1");
i_norm_join_17_1 <= s2s_cast(i_int_1_62, 26, 37, 27);
q_norm_join_17_1 <= s2s_cast(q_int_1_69, 26, 37, 27);
elsif bool_32_10_x_000000 then
bit_join_17_1 <= std_logic_vector_to_unsigned("1000");
done_join_17_1 <= std_logic_vector_to_unsigned("1");
i_norm_join_17_1 <= s2s_cast(i_int_1_62, 25, 37, 27);
q_norm_join_17_1 <= s2s_cast(q_int_1_69, 25, 37, 27);
elsif bool_37_10_x_000000 then
bit_join_17_1 <= std_logic_vector_to_unsigned("0111");
done_join_17_1 <= std_logic_vector_to_unsigned("1");
i_norm_join_17_1 <= s2s_cast(i_int_1_62, 24, 37, 27);
q_norm_join_17_1 <= s2s_cast(q_int_1_69, 24, 37, 27);
elsif bool_42_10_x_000000 then
bit_join_17_1 <= std_logic_vector_to_unsigned("0110");
done_join_17_1 <= std_logic_vector_to_unsigned("1");
i_norm_join_17_1 <= s2s_cast(i_int_1_62, 23, 37, 27);
q_norm_join_17_1 <= s2s_cast(q_int_1_69, 23, 37, 27);
elsif bool_47_10_x_000000 then
bit_join_17_1 <= std_logic_vector_to_unsigned("0101");
done_join_17_1 <= std_logic_vector_to_unsigned("1");
i_norm_join_17_1 <= s2s_cast(i_int_1_62, 22, 37, 27);
q_norm_join_17_1 <= s2s_cast(q_int_1_69, 22, 37, 27);
elsif bool_52_10_x_000000 then
bit_join_17_1 <= std_logic_vector_to_unsigned("0100");
done_join_17_1 <= std_logic_vector_to_unsigned("1");
i_norm_join_17_1 <= s2s_cast(i_int_1_62, 21, 37, 27);
q_norm_join_17_1 <= s2s_cast(q_int_1_69, 21, 37, 27);
elsif bool_57_10_x_000000 then
bit_join_17_1 <= std_logic_vector_to_unsigned("0011");
done_join_17_1 <= std_logic_vector_to_unsigned("1");
i_norm_join_17_1 <= s2s_cast(i_int_1_62, 20, 37, 27);
q_norm_join_17_1 <= s2s_cast(q_int_1_69, 20, 37, 27);
elsif bool_62_10_x_000000 then
bit_join_17_1 <= std_logic_vector_to_unsigned("0010");
done_join_17_1 <= std_logic_vector_to_unsigned("1");
i_norm_join_17_1 <= s2s_cast(i_int_1_62, 19, 37, 27);
q_norm_join_17_1 <= s2s_cast(q_int_1_69, 19, 37, 27);
elsif bool_67_10_x_000000 then
bit_join_17_1 <= std_logic_vector_to_unsigned("0010");
done_join_17_1 <= std_logic_vector_to_unsigned("1");
i_norm_join_17_1 <= s2s_cast(i_int_1_62, 18, 37, 27);
q_norm_join_17_1 <= s2s_cast(q_int_1_69, 18, 37, 27);
else
bit_join_17_1 <= std_logic_vector_to_unsigned("0001");
done_join_17_1 <= std_logic_vector_to_unsigned("1");
i_norm_join_17_1 <= s2s_cast(i_int_1_62, 17, 37, 27);
q_norm_join_17_1 <= s2s_cast(q_int_1_69, 17, 37, 27);
end if;
end process proc_if_17_1;
i_norm <= signed_to_std_logic_vector(i_norm_join_17_1);
q_norm <= signed_to_std_logic_vector(q_norm_join_17_1);
done <= unsigned_to_std_logic_vector(done_join_17_1);
bit <= unsigned_to_std_logic_vector(bit_join_17_1);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_constant_1c061e35c5 is
port (
op : out std_logic_vector((16 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_constant_1c061e35c5;
architecture behavior of sysgen_constant_1c061e35c5
is
begin
op <= "0000000000000000";
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_relational_4cc2e42350 is
port (
a : in std_logic_vector((8 - 1) downto 0);
b : in std_logic_vector((16 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_relational_4cc2e42350;
architecture behavior of sysgen_relational_4cc2e42350
is
signal a_1_31: unsigned((8 - 1) downto 0);
signal b_1_34: unsigned((16 - 1) downto 0);
signal en_1_37: boolean;
type array_type_op_mem_37_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_37_22: array_type_op_mem_37_22 := (
0 => false);
signal op_mem_37_22_front_din: boolean;
signal op_mem_37_22_back: boolean;
signal op_mem_37_22_push_front_pop_back_en: std_logic;
signal cast_16_12: unsigned((16 - 1) downto 0);
signal result_16_3_rel: boolean;
signal op_mem_shift_join_39_3: boolean;
signal op_mem_shift_join_39_3_en: std_logic;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
en_1_37 <= ((en) = "1");
op_mem_37_22_back <= op_mem_37_22(0);
proc_op_mem_37_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_37_22_push_front_pop_back_en = '1')) then
op_mem_37_22(0) <= op_mem_37_22_front_din;
end if;
end if;
end process proc_op_mem_37_22;
cast_16_12 <= u2u_cast(a_1_31, 0, 16, 0);
result_16_3_rel <= cast_16_12 < b_1_34;
proc_if_39_3: process (en_1_37, result_16_3_rel)
is
begin
if en_1_37 then
op_mem_shift_join_39_3_en <= '1';
else
op_mem_shift_join_39_3_en <= '0';
end if;
op_mem_shift_join_39_3 <= result_16_3_rel;
end process proc_if_39_3;
op_mem_37_22_front_din <= op_mem_shift_join_39_3;
op_mem_37_22_push_front_pop_back_en <= op_mem_shift_join_39_3_en;
op <= boolean_to_vector(op_mem_37_22_back);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_relational_2b94f15d5b is
port (
a : in std_logic_vector((8 - 1) downto 0);
b : in std_logic_vector((16 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_relational_2b94f15d5b;
architecture behavior of sysgen_relational_2b94f15d5b
is
signal a_1_31: unsigned((8 - 1) downto 0);
signal b_1_34: unsigned((16 - 1) downto 0);
type array_type_op_mem_37_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_37_22: array_type_op_mem_37_22 := (
0 => false);
signal op_mem_37_22_front_din: boolean;
signal op_mem_37_22_back: boolean;
signal op_mem_37_22_push_front_pop_back_en: std_logic;
signal cast_18_12: unsigned((16 - 1) downto 0);
signal result_18_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
op_mem_37_22_back <= op_mem_37_22(0);
proc_op_mem_37_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_37_22_push_front_pop_back_en = '1')) then
op_mem_37_22(0) <= op_mem_37_22_front_din;
end if;
end if;
end process proc_op_mem_37_22;
cast_18_12 <= u2u_cast(a_1_31, 0, 16, 0);
result_18_3_rel <= cast_18_12 > b_1_34;
op_mem_37_22_front_din <= result_18_3_rel;
op_mem_37_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_37_22_back);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_relational_d39f20029b is
port (
a : in std_logic_vector((8 - 1) downto 0);
b : in std_logic_vector((16 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_relational_d39f20029b;
architecture behavior of sysgen_relational_d39f20029b
is
signal a_1_31: unsigned((8 - 1) downto 0);
signal b_1_34: unsigned((16 - 1) downto 0);
signal en_1_37: boolean;
type array_type_op_mem_37_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_37_22: array_type_op_mem_37_22 := (
0 => false);
signal op_mem_37_22_front_din: boolean;
signal op_mem_37_22_back: boolean;
signal op_mem_37_22_push_front_pop_back_en: std_logic;
signal cast_18_12: unsigned((16 - 1) downto 0);
signal result_18_3_rel: boolean;
signal op_mem_shift_join_39_3: boolean;
signal op_mem_shift_join_39_3_en: std_logic;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
en_1_37 <= ((en) = "1");
op_mem_37_22_back <= op_mem_37_22(0);
proc_op_mem_37_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_37_22_push_front_pop_back_en = '1')) then
op_mem_37_22(0) <= op_mem_37_22_front_din;
end if;
end if;
end process proc_op_mem_37_22;
cast_18_12 <= u2u_cast(a_1_31, 0, 16, 0);
result_18_3_rel <= cast_18_12 > b_1_34;
proc_if_39_3: process (en_1_37, result_18_3_rel)
is
begin
if en_1_37 then
op_mem_shift_join_39_3_en <= '1';
else
op_mem_shift_join_39_3_en <= '0';
end if;
op_mem_shift_join_39_3 <= result_18_3_rel;
end process proc_if_39_3;
op_mem_37_22_front_din <= op_mem_shift_join_39_3;
op_mem_37_22_push_front_pop_back_en <= op_mem_shift_join_39_3_en;
op <= boolean_to_vector(op_mem_37_22_back);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_relational_78f65d41b5 is
port (
a : in std_logic_vector((8 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_relational_78f65d41b5;
architecture behavior of sysgen_relational_78f65d41b5
is
signal a_1_31: unsigned((8 - 1) downto 0);
signal b_1_34: unsigned((1 - 1) downto 0);
type array_type_op_mem_37_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_37_22: array_type_op_mem_37_22 := (
0 => false);
signal op_mem_37_22_front_din: boolean;
signal op_mem_37_22_back: boolean;
signal op_mem_37_22_push_front_pop_back_en: std_logic;
signal cast_18_16: unsigned((8 - 1) downto 0);
signal result_18_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
op_mem_37_22_back <= op_mem_37_22(0);
proc_op_mem_37_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_37_22_push_front_pop_back_en = '1')) then
op_mem_37_22(0) <= op_mem_37_22_front_din;
end if;
end if;
end process proc_op_mem_37_22;
cast_18_16 <= u2u_cast(b_1_34, 0, 8, 0);
result_18_3_rel <= a_1_31 > cast_18_16;
op_mem_37_22_front_din <= result_18_3_rel;
op_mem_37_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_37_22_back);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_constant_ff2f539dd4 is
port (
op : out std_logic_vector((4 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_constant_ff2f539dd4;
architecture behavior of sysgen_constant_ff2f539dd4
is
begin
op <= "1011";
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_relational_e6d9f3f14a is
port (
a : in std_logic_vector((4 - 1) downto 0);
b : in std_logic_vector((4 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_relational_e6d9f3f14a;
architecture behavior of sysgen_relational_e6d9f3f14a
is
signal a_1_31: unsigned((4 - 1) downto 0);
signal b_1_34: unsigned((4 - 1) downto 0);
type array_type_op_mem_37_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_37_22: array_type_op_mem_37_22 := (
0 => false);
signal op_mem_37_22_front_din: boolean;
signal op_mem_37_22_back: boolean;
signal op_mem_37_22_push_front_pop_back_en: std_logic;
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
op_mem_37_22_back <= op_mem_37_22(0);
proc_op_mem_37_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_37_22_push_front_pop_back_en = '1')) then
op_mem_37_22(0) <= op_mem_37_22_front_din;
end if;
end if;
end process proc_op_mem_37_22;
result_12_3_rel <= a_1_31 = b_1_34;
op_mem_37_22_front_din <= result_12_3_rel;
op_mem_37_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_37_22_back);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_constant_06f7260200 is
port (
op : out std_logic_vector((16 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_constant_06f7260200;
architecture behavior of sysgen_constant_06f7260200
is
begin
op <= "1100100100010000";
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_relational_a432dce3f8 is
port (
a : in std_logic_vector((18 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_relational_a432dce3f8;
architecture behavior of sysgen_relational_a432dce3f8
is
signal a_1_31: signed((18 - 1) downto 0);
signal b_1_34: signed((1 - 1) downto 0);
type array_type_op_mem_37_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_37_22: array_type_op_mem_37_22 := (
0 => false);
signal op_mem_37_22_front_din: boolean;
signal op_mem_37_22_back: boolean;
signal op_mem_37_22_push_front_pop_back_en: std_logic;
signal cast_14_17: signed((18 - 1) downto 0);
signal result_14_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_signed(a);
b_1_34 <= std_logic_vector_to_signed(b);
op_mem_37_22_back <= op_mem_37_22(0);
proc_op_mem_37_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_37_22_push_front_pop_back_en = '1')) then
op_mem_37_22(0) <= op_mem_37_22_front_din;
end if;
end if;
end process proc_op_mem_37_22;
cast_14_17 <= s2s_cast(b_1_34, 0, 18, 15);
result_14_3_rel <= a_1_31 /= cast_14_17;
op_mem_37_22_front_din <= result_14_3_rel;
op_mem_37_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_37_22_back);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_relational_55569134aa is
port (
a : in std_logic_vector((16 - 1) downto 0);
b : in std_logic_vector((18 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_relational_55569134aa;
architecture behavior of sysgen_relational_55569134aa
is
signal a_1_31: signed((16 - 1) downto 0);
signal b_1_34: signed((18 - 1) downto 0);
type array_type_op_mem_37_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_37_22: array_type_op_mem_37_22 := (
0 => false);
signal op_mem_37_22_front_din: boolean;
signal op_mem_37_22_back: boolean;
signal op_mem_37_22_push_front_pop_back_en: std_logic;
signal cast_14_12: signed((18 - 1) downto 0);
signal result_14_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_signed(a);
b_1_34 <= std_logic_vector_to_signed(b);
op_mem_37_22_back <= op_mem_37_22(0);
proc_op_mem_37_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_37_22_push_front_pop_back_en = '1')) then
op_mem_37_22(0) <= op_mem_37_22_front_din;
end if;
end if;
end process proc_op_mem_37_22;
cast_14_12 <= s2s_cast(a_1_31, 14, 18, 16);
result_14_3_rel <= cast_14_12 /= b_1_34;
op_mem_37_22_front_din <= result_14_3_rel;
op_mem_37_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_37_22_back);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_relational_9b53ed3669 is
port (
a : in std_logic_vector((18 - 1) downto 0);
b : in std_logic_vector((16 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_relational_9b53ed3669;
architecture behavior of sysgen_relational_9b53ed3669
is
signal a_1_31: signed((18 - 1) downto 0);
signal b_1_34: signed((16 - 1) downto 0);
type array_type_op_mem_37_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_37_22: array_type_op_mem_37_22 := (
0 => false);
signal op_mem_37_22_front_din: boolean;
signal op_mem_37_22_back: boolean;
signal op_mem_37_22_push_front_pop_back_en: std_logic;
signal cast_14_17: signed((18 - 1) downto 0);
signal result_14_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_signed(a);
b_1_34 <= std_logic_vector_to_signed(b);
op_mem_37_22_back <= op_mem_37_22(0);
proc_op_mem_37_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_37_22_push_front_pop_back_en = '1')) then
op_mem_37_22(0) <= op_mem_37_22_front_din;
end if;
end if;
end process proc_op_mem_37_22;
cast_14_17 <= s2s_cast(b_1_34, 14, 18, 16);
result_14_3_rel <= a_1_31 /= cast_14_17;
op_mem_37_22_front_din <= result_14_3_rel;
op_mem_37_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_37_22_back);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_constant_f6b8fa088a is
port (
op : out std_logic_vector((26 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_constant_f6b8fa088a;
architecture behavior of sysgen_constant_f6b8fa088a
is
begin
op <= "10111111001001100111000000";
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_logical_eeabe80b4e is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_logical_eeabe80b4e;
architecture behavior of sysgen_logical_eeabe80b4e
is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
type array_type_latency_pipe_5_26 is array (0 to (7 - 1)) of std_logic_vector((1 - 1) downto 0);
signal latency_pipe_5_26: array_type_latency_pipe_5_26 := (
"0",
"0",
"0",
"0",
"0",
"0",
"0");
signal latency_pipe_5_26_front_din: std_logic_vector((1 - 1) downto 0);
signal latency_pipe_5_26_back: std_logic_vector((1 - 1) downto 0);
signal latency_pipe_5_26_push_front_pop_back_en: std_logic;
signal fully_2_1_bit: std_logic;
signal unregy_3_1_convert: std_logic_vector((1 - 1) downto 0);
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
latency_pipe_5_26_back <= latency_pipe_5_26(6);
proc_latency_pipe_5_26: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (latency_pipe_5_26_push_front_pop_back_en = '1')) then
for i in 6 downto 1 loop
latency_pipe_5_26(i) <= latency_pipe_5_26(i-1);
end loop;
latency_pipe_5_26(0) <= latency_pipe_5_26_front_din;
end if;
end if;
end process proc_latency_pipe_5_26;
fully_2_1_bit <= d0_1_24 and d1_1_27;
unregy_3_1_convert <= cast(std_logic_to_vector(fully_2_1_bit), 0, 1, 0, xlUnsigned);
latency_pipe_5_26_front_din <= unregy_3_1_convert;
latency_pipe_5_26_push_front_pop_back_en <= '1';
y <= latency_pipe_5_26_back;
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_addsub_197d817482 is
port (
a : in std_logic_vector((1 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
s : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_addsub_197d817482;
architecture behavior of sysgen_addsub_197d817482
is
signal a_17_32: unsigned((1 - 1) downto 0);
signal b_17_35: unsigned((1 - 1) downto 0);
type array_type_op_mem_91_20 is array (0 to (1 - 1)) of signed((2 - 1) downto 0);
signal op_mem_91_20: array_type_op_mem_91_20 := (
0 => "00");
signal op_mem_91_20_front_din: signed((2 - 1) downto 0);
signal op_mem_91_20_back: signed((2 - 1) downto 0);
signal op_mem_91_20_push_front_pop_back_en: std_logic;
type array_type_cout_mem_92_22 is array (0 to (1 - 1)) of unsigned((1 - 1) downto 0);
signal cout_mem_92_22: array_type_cout_mem_92_22 := (
0 => "0");
signal cout_mem_92_22_front_din: unsigned((1 - 1) downto 0);
signal cout_mem_92_22_back: unsigned((1 - 1) downto 0);
signal cout_mem_92_22_push_front_pop_back_en: std_logic;
signal prev_mode_93_22_next: unsigned((3 - 1) downto 0);
signal prev_mode_93_22: unsigned((3 - 1) downto 0);
signal prev_mode_93_22_reg_i: std_logic_vector((3 - 1) downto 0);
signal prev_mode_93_22_reg_o: std_logic_vector((3 - 1) downto 0);
signal cast_71_18: signed((3 - 1) downto 0);
signal cast_71_22: signed((3 - 1) downto 0);
signal internal_s_71_5_addsub: signed((3 - 1) downto 0);
signal internal_s_83_3_convert: signed((2 - 1) downto 0);
begin
a_17_32 <= std_logic_vector_to_unsigned(a);
b_17_35 <= std_logic_vector_to_unsigned(b);
op_mem_91_20_back <= op_mem_91_20(0);
proc_op_mem_91_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_91_20_push_front_pop_back_en = '1')) then
op_mem_91_20(0) <= op_mem_91_20_front_din;
end if;
end if;
end process proc_op_mem_91_20;
cout_mem_92_22_back <= cout_mem_92_22(0);
proc_cout_mem_92_22: process (clk)
is
variable i_x_000000: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (cout_mem_92_22_push_front_pop_back_en = '1')) then
cout_mem_92_22(0) <= cout_mem_92_22_front_din;
end if;
end if;
end process proc_cout_mem_92_22;
prev_mode_93_22_reg_i <= unsigned_to_std_logic_vector(prev_mode_93_22_next);
prev_mode_93_22 <= std_logic_vector_to_unsigned(prev_mode_93_22_reg_o);
prev_mode_93_22_reg_inst: entity work.synth_reg_w_init
generic map (
init_index => 2,
init_value => b"010",
latency => 1,
width => 3)
port map (
ce => ce,
clk => clk,
clr => clr,
i => prev_mode_93_22_reg_i,
o => prev_mode_93_22_reg_o);
cast_71_18 <= u2s_cast(a_17_32, 0, 3, 0);
cast_71_22 <= u2s_cast(b_17_35, 0, 3, 0);
internal_s_71_5_addsub <= cast_71_18 - cast_71_22;
internal_s_83_3_convert <= std_logic_vector_to_signed(convert_type(signed_to_std_logic_vector(internal_s_71_5_addsub), 3, 0, xlSigned, 2, 0, xlSigned, xlTruncate, xlSaturate));
op_mem_91_20_front_din <= internal_s_83_3_convert;
op_mem_91_20_push_front_pop_back_en <= '1';
cout_mem_92_22_front_din <= std_logic_vector_to_unsigned("0");
cout_mem_92_22_push_front_pop_back_en <= '1';
prev_mode_93_22_next <= std_logic_vector_to_unsigned("000");
s <= signed_to_std_logic_vector(op_mem_91_20_back);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_relational_3039862521 is
port (
a : in std_logic_vector((2 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_relational_3039862521;
architecture behavior of sysgen_relational_3039862521
is
signal a_1_31: signed((2 - 1) downto 0);
signal b_1_34: signed((1 - 1) downto 0);
type array_type_op_mem_37_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_37_22: array_type_op_mem_37_22 := (
0 => false);
signal op_mem_37_22_front_din: boolean;
signal op_mem_37_22_back: boolean;
signal op_mem_37_22_push_front_pop_back_en: std_logic;
signal cast_18_16: signed((2 - 1) downto 0);
signal result_18_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_signed(a);
b_1_34 <= std_logic_vector_to_signed(b);
op_mem_37_22_back <= op_mem_37_22(0);
proc_op_mem_37_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_37_22_push_front_pop_back_en = '1')) then
op_mem_37_22(0) <= op_mem_37_22_front_din;
end if;
end if;
end process proc_op_mem_37_22;
cast_18_16 <= s2s_cast(b_1_34, 0, 2, 0);
result_18_3_rel <= a_1_31 > cast_18_16;
op_mem_37_22_front_din <= result_18_3_rel;
op_mem_37_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_37_22_back);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_inverter_60410e4e22 is
port (
ip : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_inverter_60410e4e22;
architecture behavior of sysgen_inverter_60410e4e22
is
signal ip_1_26: boolean;
type array_type_op_mem_22_20 is array (0 to (20 - 1)) of boolean;
signal op_mem_22_20: array_type_op_mem_22_20 := (
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false,
false);
signal op_mem_22_20_front_din: boolean;
signal op_mem_22_20_back: boolean;
signal op_mem_22_20_push_front_pop_back_en: std_logic;
signal internal_ip_12_1_bitnot: boolean;
begin
ip_1_26 <= ((ip) = "1");
op_mem_22_20_back <= op_mem_22_20(19);
proc_op_mem_22_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
for i in 19 downto 1 loop
op_mem_22_20(i) <= op_mem_22_20(i-1);
end loop;
op_mem_22_20(0) <= op_mem_22_20_front_din;
end if;
end if;
end process proc_op_mem_22_20;
internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1");
op_mem_22_20_front_din <= internal_ip_12_1_bitnot;
op_mem_22_20_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_22_20_back);
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sysgen_constant_5e1e20acbb is
port (
op : out std_logic_vector((42 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end sysgen_constant_5e1e20acbb;
architecture behavior of sysgen_constant_5e1e20acbb
is
begin
op <= "000000000000000000000110001100110110101010";
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity axi_lite_axi_lite_interface is
port(
cav2_p2_window_stop : out std_logic_vector(15 downto 0);
cav2_p2_window_start : out std_logic_vector(15 downto 0);
cav2_p1_window_stop : out std_logic_vector(15 downto 0);
cav2_p1_window_start : out std_logic_vector(15 downto 0);
wfdata_7_sel : out std_logic_vector(2 downto 0);
wfdata_6_sel : out std_logic_vector(0 downto 0);
wfdata_5_sel : out std_logic_vector(0 downto 0);
wfdata_4_sel : out std_logic_vector(1 downto 0);
wfdata_3_sel : out std_logic_vector(1 downto 0);
wfdata_2_sel : out std_logic_vector(2 downto 0);
wfdata_1_sel : out std_logic_vector(2 downto 0);
wfdata_0_sel : out std_logic_vector(0 downto 0);
scratchpad : out std_logic_vector(31 downto 0);
rf_ref_chan_sel : out std_logic_vector(3 downto 0);
cav2_reg_latch_pt : out std_logic_vector(15 downto 0);
cav2_p2_chan_sel : out std_logic_vector(3 downto 0);
cav2_p2_calibration_coeff : out std_logic_vector(17 downto 0);
cav2_p1_chan_sel : out std_logic_vector(3 downto 0);
cav2_p1_calibration_coeff : out std_logic_vector(17 downto 0);
cav2_nco_phase_reset : out std_logic_vector(0 downto 0);
cav2_nco_phase_adj : out std_logic_vector(25 downto 0);
cav2_freq_eval_stop : out std_logic_vector(15 downto 0);
cav2_freq_eval_start : out std_logic_vector(15 downto 0);
cav1_reg_latch_pt : out std_logic_vector(15 downto 0);
cav1_p2_window_stop : out std_logic_vector(15 downto 0);
cav1_p2_window_start : out std_logic_vector(15 downto 0);
cav1_p2_chan_sel : out std_logic_vector(3 downto 0);
cav1_p2_calibration_coeff : out std_logic_vector(17 downto 0);
cav1_p1_window_stop : out std_logic_vector(15 downto 0);
cav1_p1_window_start : out std_logic_vector(15 downto 0);
cav1_p1_chan_sel : out std_logic_vector(3 downto 0);
cav1_p1_calibration_coeff : out std_logic_vector(17 downto 0);
cav1_nco_phase_reset : out std_logic_vector(0 downto 0);
cav1_nco_phase_adj : out std_logic_vector(25 downto 0);
cav1_freq_eval_stop : out std_logic_vector(15 downto 0);
cav1_freq_eval_start : out std_logic_vector(15 downto 0);
cav1_p1_amp_out : in std_logic_vector(17 downto 0);
cav1_p1_comparison_phase : in std_logic_vector(17 downto 0);
cav1_p1_dc_freq : in std_logic_vector(31 downto 0);
cav1_p1_dc_img : in std_logic_vector(17 downto 0);
cav1_p1_dc_real : in std_logic_vector(17 downto 0);
cav1_p1_if_amp : in std_logic_vector(17 downto 0);
cav1_p1_if_i : in std_logic_vector(17 downto 0);
cav1_p1_if_phase : in std_logic_vector(17 downto 0);
cav1_p1_if_q : in std_logic_vector(17 downto 0);
cav1_p1_integrated_i : in std_logic_vector(17 downto 0);
cav1_p1_integrated_q : in std_logic_vector(17 downto 0);
cav1_p1_phase_out : in std_logic_vector(17 downto 0);
cav1_p2_amp_out : in std_logic_vector(17 downto 0);
cav1_p2_comparison_phase : in std_logic_vector(17 downto 0);
cav1_p2_dc_freq : in std_logic_vector(31 downto 0);
cav1_p2_dc_img : in std_logic_vector(17 downto 0);
cav1_p2_dc_real : in std_logic_vector(17 downto 0);
cav1_p2_if_amp : in std_logic_vector(17 downto 0);
cav1_p2_if_i : in std_logic_vector(17 downto 0);
cav1_p2_if_phase : in std_logic_vector(17 downto 0);
cav1_p2_if_q : in std_logic_vector(17 downto 0);
cav1_p2_integrated_i : in std_logic_vector(17 downto 0);
cav1_p2_integrated_q : in std_logic_vector(17 downto 0);
cav1_p2_phase_out : in std_logic_vector(17 downto 0);
cav2_p1_amp_out : in std_logic_vector(17 downto 0);
cav2_p1_comparison_phase : in std_logic_vector(17 downto 0);
cav2_p1_dc_freq : in std_logic_vector(31 downto 0);
cav2_p1_dc_img : in std_logic_vector(17 downto 0);
cav2_p1_dc_real : in std_logic_vector(17 downto 0);
cav2_p1_if_amp : in std_logic_vector(17 downto 0);
cav2_p1_if_i : in std_logic_vector(17 downto 0);
cav2_p1_if_phase : in std_logic_vector(17 downto 0);
cav2_p1_if_q : in std_logic_vector(17 downto 0);
cav2_p1_integrated_i : in std_logic_vector(17 downto 0);
cav2_p1_integrated_q : in std_logic_vector(17 downto 0);
cav2_p1_phase_out : in std_logic_vector(17 downto 0);
cav2_p2_amp_out : in std_logic_vector(17 downto 0);
cav2_p2_comparison_phase : in std_logic_vector(17 downto 0);
cav2_p2_dc_freq : in std_logic_vector(31 downto 0);
cav2_p2_dc_img : in std_logic_vector(17 downto 0);
cav2_p2_dc_real : in std_logic_vector(17 downto 0);
cav2_p2_if_amp : in std_logic_vector(17 downto 0);
cav2_p2_if_i : in std_logic_vector(17 downto 0);
cav2_p2_if_phase : in std_logic_vector(17 downto 0);
cav2_p2_if_q : in std_logic_vector(17 downto 0);
cav2_p2_integrated_i : in std_logic_vector(17 downto 0);
cav2_p2_integrated_q : in std_logic_vector(17 downto 0);
cav2_p2_phase_out : in std_logic_vector(17 downto 0);
rf_ref_amp : in std_logic_vector(17 downto 0);
rf_ref_i : in std_logic_vector(17 downto 0);
rf_ref_phase : in std_logic_vector(17 downto 0);
rf_ref_q : in std_logic_vector(17 downto 0);
status_0 : in std_logic_vector(31 downto 0);
axi_lite_clk : out std_logic;
axi_lite_aclk : in std_logic;
axi_lite_aresetn : in std_logic;
axi_lite_s_axi_awaddr : in std_logic_vector(12-1 downto 0);
axi_lite_s_axi_awvalid : in std_logic;
axi_lite_s_axi_awready : out std_logic;
axi_lite_s_axi_wdata : in std_logic_vector(32-1 downto 0);
axi_lite_s_axi_wstrb : in std_logic_vector(32/8-1 downto 0);
axi_lite_s_axi_wvalid : in std_logic;
axi_lite_s_axi_wready : out std_logic;
axi_lite_s_axi_bresp : out std_logic_vector(1 downto 0);
axi_lite_s_axi_bvalid : out std_logic;
axi_lite_s_axi_bready : in std_logic;
axi_lite_s_axi_araddr : in std_logic_vector(12-1 downto 0);
axi_lite_s_axi_arvalid : in std_logic;
axi_lite_s_axi_arready : out std_logic;
axi_lite_s_axi_rdata : out std_logic_vector(32-1 downto 0);
axi_lite_s_axi_rresp : out std_logic_vector(1 downto 0);
axi_lite_s_axi_rvalid : out std_logic;
axi_lite_s_axi_rready : in std_logic
);
end axi_lite_axi_lite_interface;
architecture structural of axi_lite_axi_lite_interface is
component axi_lite_axi_lite_interface_verilog is
port(
cav2_p2_window_stop : out std_logic_vector(15 downto 0);
cav2_p2_window_start : out std_logic_vector(15 downto 0);
cav2_p1_window_stop : out std_logic_vector(15 downto 0);
cav2_p1_window_start : out std_logic_vector(15 downto 0);
wfdata_7_sel : out std_logic_vector(2 downto 0);
wfdata_6_sel : out std_logic_vector(0 downto 0);
wfdata_5_sel : out std_logic_vector(0 downto 0);
wfdata_4_sel : out std_logic_vector(1 downto 0);
wfdata_3_sel : out std_logic_vector(1 downto 0);
wfdata_2_sel : out std_logic_vector(2 downto 0);
wfdata_1_sel : out std_logic_vector(2 downto 0);
wfdata_0_sel : out std_logic_vector(0 downto 0);
scratchpad : out std_logic_vector(31 downto 0);
rf_ref_chan_sel : out std_logic_vector(3 downto 0);
cav2_reg_latch_pt : out std_logic_vector(15 downto 0);
cav2_p2_chan_sel : out std_logic_vector(3 downto 0);
cav2_p2_calibration_coeff : out std_logic_vector(17 downto 0);
cav2_p1_chan_sel : out std_logic_vector(3 downto 0);
cav2_p1_calibration_coeff : out std_logic_vector(17 downto 0);
cav2_nco_phase_reset : out std_logic_vector(0 downto 0);
cav2_nco_phase_adj : out std_logic_vector(25 downto 0);
cav2_freq_eval_stop : out std_logic_vector(15 downto 0);
cav2_freq_eval_start : out std_logic_vector(15 downto 0);
cav1_reg_latch_pt : out std_logic_vector(15 downto 0);
cav1_p2_window_stop : out std_logic_vector(15 downto 0);
cav1_p2_window_start : out std_logic_vector(15 downto 0);
cav1_p2_chan_sel : out std_logic_vector(3 downto 0);
cav1_p2_calibration_coeff : out std_logic_vector(17 downto 0);
cav1_p1_window_stop : out std_logic_vector(15 downto 0);
cav1_p1_window_start : out std_logic_vector(15 downto 0);
cav1_p1_chan_sel : out std_logic_vector(3 downto 0);
cav1_p1_calibration_coeff : out std_logic_vector(17 downto 0);
cav1_nco_phase_reset : out std_logic_vector(0 downto 0);
cav1_nco_phase_adj : out std_logic_vector(25 downto 0);
cav1_freq_eval_stop : out std_logic_vector(15 downto 0);
cav1_freq_eval_start : out std_logic_vector(15 downto 0);
cav1_p1_amp_out : in std_logic_vector(17 downto 0);
cav1_p1_comparison_phase : in std_logic_vector(17 downto 0);
cav1_p1_dc_freq : in std_logic_vector(31 downto 0);
cav1_p1_dc_img : in std_logic_vector(17 downto 0);
cav1_p1_dc_real : in std_logic_vector(17 downto 0);
cav1_p1_if_amp : in std_logic_vector(17 downto 0);
cav1_p1_if_i : in std_logic_vector(17 downto 0);
cav1_p1_if_phase : in std_logic_vector(17 downto 0);
cav1_p1_if_q : in std_logic_vector(17 downto 0);
cav1_p1_integrated_i : in std_logic_vector(17 downto 0);
cav1_p1_integrated_q : in std_logic_vector(17 downto 0);
cav1_p1_phase_out : in std_logic_vector(17 downto 0);
cav1_p2_amp_out : in std_logic_vector(17 downto 0);
cav1_p2_comparison_phase : in std_logic_vector(17 downto 0);
cav1_p2_dc_freq : in std_logic_vector(31 downto 0);
cav1_p2_dc_img : in std_logic_vector(17 downto 0);
cav1_p2_dc_real : in std_logic_vector(17 downto 0);
cav1_p2_if_amp : in std_logic_vector(17 downto 0);
cav1_p2_if_i : in std_logic_vector(17 downto 0);
cav1_p2_if_phase : in std_logic_vector(17 downto 0);
cav1_p2_if_q : in std_logic_vector(17 downto 0);
cav1_p2_integrated_i : in std_logic_vector(17 downto 0);
cav1_p2_integrated_q : in std_logic_vector(17 downto 0);
cav1_p2_phase_out : in std_logic_vector(17 downto 0);
cav2_p1_amp_out : in std_logic_vector(17 downto 0);
cav2_p1_comparison_phase : in std_logic_vector(17 downto 0);
cav2_p1_dc_freq : in std_logic_vector(31 downto 0);
cav2_p1_dc_img : in std_logic_vector(17 downto 0);
cav2_p1_dc_real : in std_logic_vector(17 downto 0);
cav2_p1_if_amp : in std_logic_vector(17 downto 0);
cav2_p1_if_i : in std_logic_vector(17 downto 0);
cav2_p1_if_phase : in std_logic_vector(17 downto 0);
cav2_p1_if_q : in std_logic_vector(17 downto 0);
cav2_p1_integrated_i : in std_logic_vector(17 downto 0);
cav2_p1_integrated_q : in std_logic_vector(17 downto 0);
cav2_p1_phase_out : in std_logic_vector(17 downto 0);
cav2_p2_amp_out : in std_logic_vector(17 downto 0);
cav2_p2_comparison_phase : in std_logic_vector(17 downto 0);
cav2_p2_dc_freq : in std_logic_vector(31 downto 0);
cav2_p2_dc_img : in std_logic_vector(17 downto 0);
cav2_p2_dc_real : in std_logic_vector(17 downto 0);
cav2_p2_if_amp : in std_logic_vector(17 downto 0);
cav2_p2_if_i : in std_logic_vector(17 downto 0);
cav2_p2_if_phase : in std_logic_vector(17 downto 0);
cav2_p2_if_q : in std_logic_vector(17 downto 0);
cav2_p2_integrated_i : in std_logic_vector(17 downto 0);
cav2_p2_integrated_q : in std_logic_vector(17 downto 0);
cav2_p2_phase_out : in std_logic_vector(17 downto 0);
rf_ref_amp : in std_logic_vector(17 downto 0);
rf_ref_i : in std_logic_vector(17 downto 0);
rf_ref_phase : in std_logic_vector(17 downto 0);
rf_ref_q : in std_logic_vector(17 downto 0);
status_0 : in std_logic_vector(31 downto 0);
axi_lite_clk : out std_logic;
axi_lite_aclk : in std_logic;
axi_lite_aresetn : in std_logic;
axi_lite_s_axi_awaddr : in std_logic_vector(12-1 downto 0);
axi_lite_s_axi_awvalid : in std_logic;
axi_lite_s_axi_awready : out std_logic;
axi_lite_s_axi_wdata : in std_logic_vector(32-1 downto 0);
axi_lite_s_axi_wstrb : in std_logic_vector(32/8-1 downto 0);
axi_lite_s_axi_wvalid : in std_logic;
axi_lite_s_axi_wready : out std_logic;
axi_lite_s_axi_bresp : out std_logic_vector(1 downto 0);
axi_lite_s_axi_bvalid : out std_logic;
axi_lite_s_axi_bready : in std_logic;
axi_lite_s_axi_araddr : in std_logic_vector(12-1 downto 0);
axi_lite_s_axi_arvalid : in std_logic;
axi_lite_s_axi_arready : out std_logic;
axi_lite_s_axi_rdata : out std_logic_vector(32-1 downto 0);
axi_lite_s_axi_rresp : out std_logic_vector(1 downto 0);
axi_lite_s_axi_rvalid : out std_logic;
axi_lite_s_axi_rready : in std_logic
);
end component;
begin
inst : axi_lite_axi_lite_interface_verilog
port map(
cav2_p2_window_stop => cav2_p2_window_stop,
cav2_p2_window_start => cav2_p2_window_start,
cav2_p1_window_stop => cav2_p1_window_stop,
cav2_p1_window_start => cav2_p1_window_start,
wfdata_7_sel => wfdata_7_sel,
wfdata_6_sel => wfdata_6_sel,
wfdata_5_sel => wfdata_5_sel,
wfdata_4_sel => wfdata_4_sel,
wfdata_3_sel => wfdata_3_sel,
wfdata_2_sel => wfdata_2_sel,
wfdata_1_sel => wfdata_1_sel,
wfdata_0_sel => wfdata_0_sel,
scratchpad => scratchpad,
rf_ref_chan_sel => rf_ref_chan_sel,
cav2_reg_latch_pt => cav2_reg_latch_pt,
cav2_p2_chan_sel => cav2_p2_chan_sel,
cav2_p2_calibration_coeff => cav2_p2_calibration_coeff,
cav2_p1_chan_sel => cav2_p1_chan_sel,
cav2_p1_calibration_coeff => cav2_p1_calibration_coeff,
cav2_nco_phase_reset => cav2_nco_phase_reset,
cav2_nco_phase_adj => cav2_nco_phase_adj,
cav2_freq_eval_stop => cav2_freq_eval_stop,
cav2_freq_eval_start => cav2_freq_eval_start,
cav1_reg_latch_pt => cav1_reg_latch_pt,
cav1_p2_window_stop => cav1_p2_window_stop,
cav1_p2_window_start => cav1_p2_window_start,
cav1_p2_chan_sel => cav1_p2_chan_sel,
cav1_p2_calibration_coeff => cav1_p2_calibration_coeff,
cav1_p1_window_stop => cav1_p1_window_stop,
cav1_p1_window_start => cav1_p1_window_start,
cav1_p1_chan_sel => cav1_p1_chan_sel,
cav1_p1_calibration_coeff => cav1_p1_calibration_coeff,
cav1_nco_phase_reset => cav1_nco_phase_reset,
cav1_nco_phase_adj => cav1_nco_phase_adj,
cav1_freq_eval_stop => cav1_freq_eval_stop,
cav1_freq_eval_start => cav1_freq_eval_start,
cav1_p1_amp_out => cav1_p1_amp_out,
cav1_p1_comparison_phase => cav1_p1_comparison_phase,
cav1_p1_dc_freq => cav1_p1_dc_freq,
cav1_p1_dc_img => cav1_p1_dc_img,
cav1_p1_dc_real => cav1_p1_dc_real,
cav1_p1_if_amp => cav1_p1_if_amp,
cav1_p1_if_i => cav1_p1_if_i,
cav1_p1_if_phase => cav1_p1_if_phase,
cav1_p1_if_q => cav1_p1_if_q,
cav1_p1_integrated_i => cav1_p1_integrated_i,
cav1_p1_integrated_q => cav1_p1_integrated_q,
cav1_p1_phase_out => cav1_p1_phase_out,
cav1_p2_amp_out => cav1_p2_amp_out,
cav1_p2_comparison_phase => cav1_p2_comparison_phase,
cav1_p2_dc_freq => cav1_p2_dc_freq,
cav1_p2_dc_img => cav1_p2_dc_img,
cav1_p2_dc_real => cav1_p2_dc_real,
cav1_p2_if_amp => cav1_p2_if_amp,
cav1_p2_if_i => cav1_p2_if_i,
cav1_p2_if_phase => cav1_p2_if_phase,
cav1_p2_if_q => cav1_p2_if_q,
cav1_p2_integrated_i => cav1_p2_integrated_i,
cav1_p2_integrated_q => cav1_p2_integrated_q,
cav1_p2_phase_out => cav1_p2_phase_out,
cav2_p1_amp_out => cav2_p1_amp_out,
cav2_p1_comparison_phase => cav2_p1_comparison_phase,
cav2_p1_dc_freq => cav2_p1_dc_freq,
cav2_p1_dc_img => cav2_p1_dc_img,
cav2_p1_dc_real => cav2_p1_dc_real,
cav2_p1_if_amp => cav2_p1_if_amp,
cav2_p1_if_i => cav2_p1_if_i,
cav2_p1_if_phase => cav2_p1_if_phase,
cav2_p1_if_q => cav2_p1_if_q,
cav2_p1_integrated_i => cav2_p1_integrated_i,
cav2_p1_integrated_q => cav2_p1_integrated_q,
cav2_p1_phase_out => cav2_p1_phase_out,
cav2_p2_amp_out => cav2_p2_amp_out,
cav2_p2_comparison_phase => cav2_p2_comparison_phase,
cav2_p2_dc_freq => cav2_p2_dc_freq,
cav2_p2_dc_img => cav2_p2_dc_img,
cav2_p2_dc_real => cav2_p2_dc_real,
cav2_p2_if_amp => cav2_p2_if_amp,
cav2_p2_if_i => cav2_p2_if_i,
cav2_p2_if_phase => cav2_p2_if_phase,
cav2_p2_if_q => cav2_p2_if_q,
cav2_p2_integrated_i => cav2_p2_integrated_i,
cav2_p2_integrated_q => cav2_p2_integrated_q,
cav2_p2_phase_out => cav2_p2_phase_out,
rf_ref_amp => rf_ref_amp,
rf_ref_i => rf_ref_i,
rf_ref_phase => rf_ref_phase,
rf_ref_q => rf_ref_q,
status_0 => status_0,
axi_lite_clk => axi_lite_clk,
axi_lite_aclk => axi_lite_aclk,
axi_lite_aresetn => axi_lite_aresetn,
axi_lite_s_axi_awaddr => axi_lite_s_axi_awaddr,
axi_lite_s_axi_awvalid => axi_lite_s_axi_awvalid,
axi_lite_s_axi_awready => axi_lite_s_axi_awready,
axi_lite_s_axi_wdata => axi_lite_s_axi_wdata,
axi_lite_s_axi_wstrb => axi_lite_s_axi_wstrb,
axi_lite_s_axi_wvalid => axi_lite_s_axi_wvalid,
axi_lite_s_axi_wready => axi_lite_s_axi_wready,
axi_lite_s_axi_bresp => axi_lite_s_axi_bresp,
axi_lite_s_axi_bvalid => axi_lite_s_axi_bvalid,
axi_lite_s_axi_bready => axi_lite_s_axi_bready,
axi_lite_s_axi_araddr => axi_lite_s_axi_araddr,
axi_lite_s_axi_arvalid => axi_lite_s_axi_arvalid,
axi_lite_s_axi_arready => axi_lite_s_axi_arready,
axi_lite_s_axi_rdata => axi_lite_s_axi_rdata,
axi_lite_s_axi_rresp => axi_lite_s_axi_rresp,
axi_lite_s_axi_rvalid => axi_lite_s_axi_rvalid,
axi_lite_s_axi_rready => axi_lite_s_axi_rready
);
end structural;
library work;
use work.conv_pkg.all;
-------------------------------------------------------------------
-- System Generator version 11.1 VHDL source file.
--
-- Copyright(C) 2009 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2009 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity example_xladdsub is
generic (
core_name0: string := "";
a_width: integer := 16;
a_bin_pt: integer := 4;
a_arith: integer := xlUnsigned;
c_in_width: integer := 16;
c_in_bin_pt: integer := 4;
c_in_arith: integer := xlUnsigned;
c_out_width: integer := 16;
c_out_bin_pt: integer := 4;
c_out_arith: integer := xlUnsigned;
b_width: integer := 8;
b_bin_pt: integer := 2;
b_arith: integer := xlUnsigned;
s_width: integer := 17;
s_bin_pt: integer := 4;
s_arith: integer := xlUnsigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
full_s_width: integer := 17;
full_s_arith: integer := xlUnsigned;
mode: integer := xlAddMode;
extra_registers: integer := 0;
latency: integer := 0;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
c_latency: integer := 0;
c_output_width: integer := 17;
c_has_c_in : integer := 0;
c_has_c_out : integer := 0
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
c_in : in std_logic_vector (0 downto 0) := "0";
ce: in std_logic;
clr: in std_logic := '0';
clk: in std_logic;
rst: in std_logic_vector(rst_width - 1 downto 0) := "0";
en: in std_logic_vector(en_width - 1 downto 0) := "1";
c_out : out std_logic_vector (0 downto 0);
s: out std_logic_vector(s_width - 1 downto 0)
);
end example_xladdsub;
architecture behavior of example_xladdsub is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function format_input(inp: std_logic_vector; old_width, delta, new_arith,
new_width: integer)
return std_logic_vector
is
variable vec: std_logic_vector(old_width-1 downto 0);
variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0);
variable result: std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if (delta > 0) then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt);
constant full_a_width: integer := full_s_width;
constant full_b_width: integer := full_s_width;
signal full_a: std_logic_vector(full_a_width - 1 downto 0);
signal full_b: std_logic_vector(full_b_width - 1 downto 0);
signal core_s: std_logic_vector(full_s_width - 1 downto 0);
signal conv_s: std_logic_vector(s_width - 1 downto 0);
signal temp_cout : std_logic;
signal internal_clr: std_logic;
signal internal_ce: std_logic;
signal extra_reg_ce: std_logic;
signal override: std_logic;
signal logic1: std_logic_vector(0 downto 0);
component example_c_addsub_v12_0_i0
port (
a: in std_logic_vector(19 - 1 downto 0);
clk: in std_logic:= '0';
ce: in std_logic:= '0';
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(19 - 1 downto 0)
);
end component;
component example_c_addsub_v12_0_i1
port (
a: in std_logic_vector(21 - 1 downto 0);
clk: in std_logic:= '0';
ce: in std_logic:= '0';
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(21 - 1 downto 0)
);
end component;
begin
internal_clr <= (clr or (rst(0))) and ce;
internal_ce <= ce and en(0);
logic1(0) <= '1';
addsub_process: process (a, b, core_s)
begin
full_a <= format_input (a, a_width, b_bin_pt - a_bin_pt, a_arith,
full_a_width);
full_b <= format_input (b, b_width, a_bin_pt - b_bin_pt, b_arith,
full_b_width);
conv_s <= convert_type (core_s, full_s_width, full_s_bin_pt, full_s_arith,
s_width, s_bin_pt, s_arith, quantization, overflow);
end process addsub_process;
comp0: if ((core_name0 = "example_c_addsub_v12_0_i0")) generate
core_instance0:example_c_addsub_v12_0_i0
port map (
a => full_a,
clk => clk,
ce => internal_ce,
s => core_s,
b => full_b
);
end generate;
comp1: if ((core_name0 = "example_c_addsub_v12_0_i1")) generate
core_instance1:example_c_addsub_v12_0_i1
port map (
a => full_a,
clk => clk,
ce => internal_ce,
s => core_s,
b => full_b
);
end generate;
latency_test: if (extra_registers > 0) generate
override_test: if (c_latency > 1) generate
override_pipe: synth_reg
generic map (
width => 1,
latency => c_latency
)
port map (
i => logic1,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o(0) => override);
extra_reg_ce <= ce and en(0) and override;
end generate override_test;
no_override: if ((c_latency = 0) or (c_latency = 1)) generate
extra_reg_ce <= ce and en(0);
end generate no_override;
extra_reg: synth_reg
generic map (
width => s_width,
latency => extra_registers
)
port map (
i => conv_s,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => s
);
cout_test: if (c_has_c_out = 1) generate
c_out_extra_reg: synth_reg
generic map (
width => 1,
latency => extra_registers
)
port map (
i(0) => temp_cout,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => c_out
);
end generate cout_test;
end generate;
latency_s: if ((latency = 0) or (extra_registers = 0)) generate
s <= conv_s;
end generate latency_s;
latency0: if (((latency = 0) or (extra_registers = 0)) and
(c_has_c_out = 1)) generate
c_out(0) <= temp_cout;
end generate latency0;
tie_dangling_cout: if (c_has_c_out = 0) generate
c_out <= "0";
end generate tie_dangling_cout;
end architecture behavior;
library work;
use work.conv_pkg.all;
---------------------------------------------------------------------
--
-- Filename : xlcounter_rst.vhd
--
-- Created : 1/31/01
-- Modified :
--
-- Description : VHDL wrapper for a counter. This wrapper
-- uses the Binary Counter CoreGenerator core.
--
---------------------------------------------------------------------
---------------------------------------------------------------------
--
-- Entity : xlcounter
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of a counter.
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity example_xlcounter_free is
generic (
core_name0: string := "";
op_width: integer := 5;
op_arith: integer := xlSigned
);
port (
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
op: out std_logic_vector(op_width - 1 downto 0);
up: in std_logic_vector(0 downto 0) := (others => '0');
load: in std_logic_vector(0 downto 0) := (others => '0');
din: in std_logic_vector(op_width - 1 downto 0) := (others => '0');
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0)
);
end example_xlcounter_free;
architecture behavior of example_xlcounter_free is
component example_c_counter_binary_v12_0_i1
port (
clk: in std_logic;
ce: in std_logic;
SINIT: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
-- synthesis translate_off
constant zeroVec: std_logic_vector(op_width - 1 downto 0) := (others => '0');
constant oneVec: std_logic_vector(op_width - 1 downto 0) := (others => '1');
constant zeroStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(zeroVec);
constant oneStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(oneVec);
-- synthesis translate_on
signal core_sinit: std_logic;
signal core_ce: std_logic;
signal op_net: std_logic_vector(op_width - 1 downto 0);
begin
core_ce <= ce and en(0);
core_sinit <= (clr or rst(0)) and ce;
op <= op_net;
comp0: if ((core_name0 = "example_c_counter_binary_v12_0_i1")) generate
core_instance0:example_c_counter_binary_v12_0_i1
port map (
clk => clk,
ce => core_ce,
SINIT => core_sinit,
q => op_net
);
end generate;
end behavior;
library work;
use work.conv_pkg.all;
---------------------------------------------------------------------
--
-- Filename : xlcounter.vhd
--
-- Created : 5/31/00
-- Modified : 6/7/00
--
-- Description : VHDL wrapper for a counter. This wrapper
-- uses the Binary Counter CoreGenerator core.
--
---------------------------------------------------------------------
---------------------------------------------------------------------
--
-- Entity : xlcounter
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of a counter.
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity example_xlcounter_limit is
generic (
core_name0: string := "";
op_width: integer := 5;
op_arith: integer := xlSigned;
cnt_63_48: integer:= 0;
cnt_47_32: integer:= 0;
cnt_31_16: integer:= 0;
cnt_15_0: integer:= 0;
count_limited: integer := 0 -- 0 if cnt_to = (2^n)-1 else 1
);
port (
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
op: out std_logic_vector(op_width - 1 downto 0);
up: in std_logic_vector(0 downto 0) := (others => '0');
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0)
);
end example_xlcounter_limit;
architecture behavior of example_xlcounter_limit is
signal high_cnt_to: std_logic_vector(31 downto 0);
signal low_cnt_to: std_logic_vector(31 downto 0);
signal cnt_to: std_logic_vector(63 downto 0);
signal core_sinit, op_thresh0, core_ce: std_logic;
signal rst_overrides_en: std_logic;
signal op_net: std_logic_vector(op_width - 1 downto 0);
-- synthesis translate_off
signal real_op : real; -- For debugging info ports
-- synthesis translate_on
function equals(op, cnt_to : std_logic_vector; width, arith : integer)
return std_logic
is
variable signed_op, signed_cnt_to : signed (width - 1 downto 0);
variable unsigned_op, unsigned_cnt_to : unsigned (width - 1 downto 0);
variable result : std_logic;
begin
-- synthesis translate_off
if ((is_XorU(op)) or (is_XorU(cnt_to)) ) then
result := '0';
return result;
end if;
-- synthesis translate_on
if (op = cnt_to) then
result := '1';
else
result := '0';
end if;
return result;
end;
component example_c_counter_binary_v12_0_i0
port (
clk: in std_logic;
ce: in std_logic;
SINIT: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
-- synthesis translate_off
constant zeroVec : std_logic_vector(op_width - 1 downto 0) := (others => '0');
constant oneVec : std_logic_vector(op_width - 1 downto 0) := (others => '1');
constant zeroStr : string(1 to op_width) :=
std_logic_vector_to_bin_string(zeroVec);
constant oneStr : string(1 to op_width) :=
std_logic_vector_to_bin_string(oneVec);
-- synthesis translate_on
begin
-- Debugging info for internal full precision variables
-- synthesis translate_off
-- real_op <= to_real(op, op_bin_pt, op_arith);
-- synthesis translate_on
cnt_to(63 downto 48) <= integer_to_std_logic_vector(cnt_63_48, 16, op_arith);
cnt_to(47 downto 32) <= integer_to_std_logic_vector(cnt_47_32, 16, op_arith);
cnt_to(31 downto 16) <= integer_to_std_logic_vector(cnt_31_16, 16, op_arith);
cnt_to(15 downto 0) <= integer_to_std_logic_vector(cnt_15_0, 16, op_arith);
-- Output of counter always valid
op <= op_net;
core_ce <= ce and en(0);
rst_overrides_en <= rst(0) or en(0);
limit : if (count_limited = 1) generate
eq_cnt_to : process (op_net, cnt_to)
begin
-- Had to pass cnt_to(op_width - 1 downto 0) instead of cnt_to so
-- that XST would infer a macro
op_thresh0 <= equals(op_net, cnt_to(op_width - 1 downto 0),
op_width, op_arith);
end process;
core_sinit <= (op_thresh0 or clr or rst(0)) and ce and rst_overrides_en;
end generate;
no_limit : if (count_limited = 0) generate
core_sinit <= (clr or rst(0)) and ce and rst_overrides_en;
end generate;
comp0: if ((core_name0 = "example_c_counter_binary_v12_0_i0")) generate
core_instance0:example_c_counter_binary_v12_0_i0
port map (
clk => clk,
ce => core_ce,
SINIT => core_sinit,
q => op_net
);
end generate;
end behavior;
library work;
use work.conv_pkg.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.conv_pkg.all;
entity xlcomplex_multiplier_c61dbf13099b80fac257c538ed356ad8 is
port(
ce:in std_logic;
clk:in std_logic;
m_axis_dout_tdata_imag:out std_logic_vector(32 downto 0);
m_axis_dout_tdata_real:out std_logic_vector(32 downto 0);
m_axis_dout_tvalid:out std_logic;
s_axis_a_tdata_imag:in std_logic_vector(17 downto 0);
s_axis_a_tdata_real:in std_logic_vector(17 downto 0);
s_axis_a_tvalid:in std_logic;
s_axis_b_tdata_imag:in std_logic_vector(25 downto 0);
s_axis_b_tdata_real:in std_logic_vector(25 downto 0);
s_axis_b_tvalid:in std_logic
);
end xlcomplex_multiplier_c61dbf13099b80fac257c538ed356ad8;
architecture behavior of xlcomplex_multiplier_c61dbf13099b80fac257c538ed356ad8 is
component example_cmpy_v6_0_i0
port(
aclk:in std_logic;
aclken:in std_logic;
m_axis_dout_tdata:out std_logic_vector(79 downto 0);
m_axis_dout_tvalid:out std_logic;
s_axis_a_tdata:in std_logic_vector(47 downto 0);
s_axis_a_tvalid:in std_logic;
s_axis_b_tdata:in std_logic_vector(63 downto 0);
s_axis_b_tvalid:in std_logic
);
end component;
signal m_axis_dout_tdata_net: std_logic_vector(79 downto 0) := (others=>'0');
signal s_axis_a_tdata_net: std_logic_vector(47 downto 0) := (others=>'0');
signal s_axis_b_tdata_net: std_logic_vector(63 downto 0) := (others=>'0');
begin
m_axis_dout_tdata_imag <= m_axis_dout_tdata_net(72 downto 40);
m_axis_dout_tdata_real <= m_axis_dout_tdata_net(32 downto 0);
s_axis_a_tdata_net(41 downto 24) <= s_axis_a_tdata_imag;
s_axis_a_tdata_net(17 downto 0) <= s_axis_a_tdata_real;
s_axis_b_tdata_net(57 downto 32) <= s_axis_b_tdata_imag;
s_axis_b_tdata_net(25 downto 0) <= s_axis_b_tdata_real;
example_cmpy_v6_0_i0_instance : example_cmpy_v6_0_i0
port map(
aclk=>clk,
aclken=>ce,
m_axis_dout_tdata=>m_axis_dout_tdata_net,
m_axis_dout_tvalid=>m_axis_dout_tvalid,
s_axis_a_tdata=>s_axis_a_tdata_net,
s_axis_a_tvalid=>s_axis_a_tvalid,
s_axis_b_tdata=>s_axis_b_tdata_net,
s_axis_b_tvalid=>s_axis_b_tvalid
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.conv_pkg.all;
entity xldds_compiler_bccfbee4cea02d59adc7b3443a88c30b is
port(
ce:in std_logic;
clk:in std_logic;
m_axis_data_tdata_cosine:out std_logic_vector(25 downto 0);
m_axis_data_tdata_sine:out std_logic_vector(25 downto 0);
m_axis_data_tready:in std_logic;
m_axis_data_tvalid:out std_logic;
s_axis_phase_tdata_pinc:in std_logic_vector(25 downto 0);
s_axis_phase_tdata_resync:in std_logic_vector(0 downto 0);
s_axis_phase_tready:out std_logic;
s_axis_phase_tvalid:in std_logic
);
end xldds_compiler_bccfbee4cea02d59adc7b3443a88c30b;
architecture behavior of xldds_compiler_bccfbee4cea02d59adc7b3443a88c30b is
component example_dds_compiler_v6_0_i0
port(
aclk:in std_logic;
aclken:in std_logic;
m_axis_data_tdata:out std_logic_vector(63 downto 0);
m_axis_data_tready:in std_logic;
m_axis_data_tvalid:out std_logic;
s_axis_phase_tdata:in std_logic_vector(39 downto 0);
s_axis_phase_tready:out std_logic;
s_axis_phase_tvalid:in std_logic
);
end component;
signal m_axis_data_tdata_net: std_logic_vector(63 downto 0) := (others=>'0');
signal s_axis_phase_tdata_net: std_logic_vector(39 downto 0) := (others=>'0');
begin
m_axis_data_tdata_sine <= m_axis_data_tdata_net(57 downto 32);
m_axis_data_tdata_cosine <= m_axis_data_tdata_net(25 downto 0);
s_axis_phase_tdata_net(32 downto 32) <= s_axis_phase_tdata_resync;
s_axis_phase_tdata_net(25 downto 0) <= s_axis_phase_tdata_pinc;
example_dds_compiler_v6_0_i0_instance : example_dds_compiler_v6_0_i0
port map(
aclk=>clk,
aclken=>ce,
m_axis_data_tdata=>m_axis_data_tdata_net,
m_axis_data_tready=>m_axis_data_tready,
m_axis_data_tvalid=>m_axis_data_tvalid,
s_axis_phase_tdata=>s_axis_phase_tdata_net,
s_axis_phase_tready=>s_axis_phase_tready,
s_axis_phase_tvalid=>s_axis_phase_tvalid
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.conv_pkg.all;
entity xlcordic_b0006847a679caa89b70cd0e3ba875d8 is
port(
ce:in std_logic;
clk:in std_logic;
m_axis_dout_tdata_phase:out std_logic_vector(17 downto 0);
m_axis_dout_tdata_real:out std_logic_vector(17 downto 0);
m_axis_dout_tvalid:out std_logic;
s_axis_cartesian_tdata_imag:in std_logic_vector(17 downto 0);
s_axis_cartesian_tdata_real:in std_logic_vector(17 downto 0);
s_axis_cartesian_tvalid:in std_logic
);
end xlcordic_b0006847a679caa89b70cd0e3ba875d8;
architecture behavior of xlcordic_b0006847a679caa89b70cd0e3ba875d8 is
component example_cordic_v6_0_i0
port(
aclk:in std_logic;
aclken:in std_logic;
m_axis_dout_tdata:out std_logic_vector(47 downto 0);
m_axis_dout_tvalid:out std_logic;
s_axis_cartesian_tdata:in std_logic_vector(47 downto 0);
s_axis_cartesian_tvalid:in std_logic
);
end component;
signal m_axis_dout_tdata_net: std_logic_vector(47 downto 0) := (others=>'0');
signal s_axis_cartesian_tdata_net: std_logic_vector(47 downto 0) := (others=>'0');
begin
m_axis_dout_tdata_phase <= m_axis_dout_tdata_net(41 downto 24);
m_axis_dout_tdata_real <= m_axis_dout_tdata_net(17 downto 0);
s_axis_cartesian_tdata_net(41 downto 24) <= s_axis_cartesian_tdata_imag;
s_axis_cartesian_tdata_net(17 downto 0) <= s_axis_cartesian_tdata_real;
example_cordic_v6_0_i0_instance : example_cordic_v6_0_i0
port map(
aclk=>clk,
aclken=>ce,
m_axis_dout_tdata=>m_axis_dout_tdata_net,
m_axis_dout_tvalid=>m_axis_dout_tvalid,
s_axis_cartesian_tdata=>s_axis_cartesian_tdata_net,
s_axis_cartesian_tvalid=>s_axis_cartesian_tvalid
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.conv_pkg.all;
entity xlcordic_c88945ce1c12987e2654d16a6b6a7865 is
port(
ce:in std_logic;
clk:in std_logic;
m_axis_dout_tdata_phase:out std_logic_vector(17 downto 0);
m_axis_dout_tdata_real:out std_logic_vector(17 downto 0);
m_axis_dout_tvalid:out std_logic;
s_axis_cartesian_tdata_imag:in std_logic_vector(17 downto 0);
s_axis_cartesian_tdata_real:in std_logic_vector(17 downto 0);
s_axis_cartesian_tvalid:in std_logic
);
end xlcordic_c88945ce1c12987e2654d16a6b6a7865;
architecture behavior of xlcordic_c88945ce1c12987e2654d16a6b6a7865 is
component example_cordic_v6_0_i1
port(
aclk:in std_logic;
aclken:in std_logic;
m_axis_dout_tdata:out std_logic_vector(47 downto 0);
m_axis_dout_tvalid:out std_logic;
s_axis_cartesian_tdata:in std_logic_vector(47 downto 0);
s_axis_cartesian_tvalid:in std_logic
);
end component;
signal m_axis_dout_tdata_net: std_logic_vector(47 downto 0) := (others=>'0');
signal s_axis_cartesian_tdata_net: std_logic_vector(47 downto 0) := (others=>'0');
begin
m_axis_dout_tdata_phase <= m_axis_dout_tdata_net(41 downto 24);
m_axis_dout_tdata_real <= m_axis_dout_tdata_net(17 downto 0);
s_axis_cartesian_tdata_net(41 downto 24) <= s_axis_cartesian_tdata_imag;
s_axis_cartesian_tdata_net(17 downto 0) <= s_axis_cartesian_tdata_real;
example_cordic_v6_0_i1_instance : example_cordic_v6_0_i1
port map(
aclk=>clk,
aclken=>ce,
m_axis_dout_tdata=>m_axis_dout_tdata_net,
m_axis_dout_tvalid=>m_axis_dout_tvalid,
s_axis_cartesian_tdata=>s_axis_cartesian_tdata_net,
s_axis_cartesian_tvalid=>s_axis_cartesian_tvalid
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.conv_pkg.all;
entity xldivider_generator_5d2a2b4531260672bf0520de139327f3 is
port(
a:in std_logic_vector(18 downto 0);
a_tvalid:in std_logic;
b:in std_logic_vector(31 downto 0);
b_tvalid:in std_logic;
ce:in std_logic;
clk:in std_logic;
op:out std_logic_vector(50 downto 0)
);
end xldivider_generator_5d2a2b4531260672bf0520de139327f3;
architecture behavior of xldivider_generator_5d2a2b4531260672bf0520de139327f3 is
component example_div_gen_v5_1_i0
port(
aclk:in std_logic;
m_axis_dout_tdata:out std_logic_vector(71 downto 0);
m_axis_dout_tvalid:out std_logic;
s_axis_dividend_tdata:in std_logic_vector(23 downto 0);
s_axis_dividend_tvalid:in std_logic;
s_axis_divisor_tdata:in std_logic_vector(31 downto 0);
s_axis_divisor_tvalid:in std_logic
);
end component;
signal m_axis_dout_tdata_net: std_logic_vector(71 downto 0) := (others=>'0');
signal m_axis_dout_tdata_shift_in_net: std_logic_vector(67 downto 0) := (others=>'0');
signal m_axis_dout_tdata_shift_out_net: std_logic_vector(50 downto 0) := (others=>'0');
signal result_tvalid: std_logic := '0';
signal s_axis_dividend_tdata_net: std_logic_vector(23 downto 0) := (others=>'0');
signal s_axis_divisor_tdata_net: std_logic_vector(31 downto 0) := (others=>'0');
begin
m_axis_dout_tdata_shift_in_net <= m_axis_dout_tdata_net(67 downto 0);
op <= m_axis_dout_tdata_shift_out_net;
s_axis_dividend_tdata_net(18 downto 0) <= a;
s_axis_divisor_tdata_net(31 downto 0) <= b;
m_axis_dout_tdata_shift_out_net <= shift_op(m_axis_dout_tdata_shift_in_net, 51, 17, 1);
example_div_gen_v5_1_i0_instance : example_div_gen_v5_1_i0
port map(
aclk=>clk,
m_axis_dout_tdata=>m_axis_dout_tdata_net,
m_axis_dout_tvalid=>result_tvalid,
s_axis_dividend_tdata=>s_axis_dividend_tdata_net,
s_axis_dividend_tvalid=>a_tvalid,
s_axis_divisor_tdata=>s_axis_divisor_tdata_net,
s_axis_divisor_tvalid=>b_tvalid
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.conv_pkg.all;
entity xldivider_generator_415962ac54b22c816540c773a5ef9f99 is
port(
a:in std_logic_vector(50 downto 0);
a_tvalid:in std_logic;
b:in std_logic_vector(25 downto 0);
b_tvalid:in std_logic;
ce:in std_logic;
clk:in std_logic;
op:out std_logic_vector(83 downto 0)
);
end xldivider_generator_415962ac54b22c816540c773a5ef9f99;
architecture behavior of xldivider_generator_415962ac54b22c816540c773a5ef9f99 is
component example_div_gen_v5_1_i1
port(
aclk:in std_logic;
m_axis_dout_tdata:out std_logic_vector(87 downto 0);
m_axis_dout_tvalid:out std_logic;
s_axis_dividend_tdata:in std_logic_vector(55 downto 0);
s_axis_dividend_tvalid:in std_logic;
s_axis_divisor_tdata:in std_logic_vector(31 downto 0);
s_axis_divisor_tvalid:in std_logic
);
end component;
signal m_axis_dout_tdata_net: std_logic_vector(87 downto 0) := (others=>'0');
signal m_axis_dout_tdata_shift_in_net: std_logic_vector(83 downto 0) := (others=>'0');
signal m_axis_dout_tdata_shift_out_net: std_logic_vector(83 downto 0) := (others=>'0');
signal result_tvalid: std_logic := '0';
signal s_axis_dividend_tdata_net: std_logic_vector(55 downto 0) := (others=>'0');
signal s_axis_divisor_tdata_net: std_logic_vector(31 downto 0) := (others=>'0');
begin
m_axis_dout_tdata_shift_in_net <= m_axis_dout_tdata_net(83 downto 0);
op <= m_axis_dout_tdata_shift_out_net;
s_axis_dividend_tdata_net(50 downto 0) <= a;
s_axis_divisor_tdata_net(25 downto 0) <= b;
m_axis_dout_tdata_shift_out_net <= shift_op(m_axis_dout_tdata_shift_in_net, 84, 32, 0);
example_div_gen_v5_1_i1_instance : example_div_gen_v5_1_i1
port map(
aclk=>clk,
m_axis_dout_tdata=>m_axis_dout_tdata_net,
m_axis_dout_tvalid=>result_tvalid,
s_axis_dividend_tdata=>s_axis_dividend_tdata_net,
s_axis_dividend_tvalid=>a_tvalid,
s_axis_divisor_tdata=>s_axis_divisor_tdata_net,
s_axis_divisor_tvalid=>b_tvalid
);
end behavior;
library work;
use work.conv_pkg.all;
-------------------------------------------------------------------
-- System Generator version 11.1 VHDL source file.
--
-- Copyright(C) 2009 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2009 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity example_xlmult is
generic (
core_name0: string := "";
a_width: integer := 4;
a_bin_pt: integer := 2;
a_arith: integer := xlSigned;
b_width: integer := 4;
b_bin_pt: integer := 1;
b_arith: integer := xlSigned;
p_width: integer := 8;
p_bin_pt: integer := 2;
p_arith: integer := xlSigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
extra_registers: integer := 0;
c_a_width: integer := 7;
c_b_width: integer := 7;
c_type: integer := 0;
c_a_type: integer := 0;
c_b_type: integer := 0;
c_pipelined: integer := 1;
c_baat: integer := 4;
multsign: integer := xlSigned;
c_output_width: integer := 16
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
core_ce: in std_logic := '0';
core_clr: in std_logic := '0';
core_clk: in std_logic := '0';
rst: in std_logic_vector(rst_width - 1 downto 0);
en: in std_logic_vector(en_width - 1 downto 0);
p: out std_logic_vector(p_width - 1 downto 0)
);
end example_xlmult;
architecture behavior of example_xlmult is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
component example_mult_gen_v12_0_i0
port (
b: in std_logic_vector(c_b_width - 1 downto 0);
p: out std_logic_vector(c_output_width - 1 downto 0);
clk: in std_logic;
ce: in std_logic;
sclr: in std_logic;
a: in std_logic_vector(c_a_width - 1 downto 0)
);
end component;
component example_mult_gen_v12_0_i1
port (
b: in std_logic_vector(c_b_width - 1 downto 0);
p: out std_logic_vector(c_output_width - 1 downto 0);
clk: in std_logic;
ce: in std_logic;
sclr: in std_logic;
a: in std_logic_vector(c_a_width - 1 downto 0)
);
end component;
component example_mult_gen_v12_0_i2
port (
b: in std_logic_vector(c_b_width - 1 downto 0);
p: out std_logic_vector(c_output_width - 1 downto 0);
clk: in std_logic;
ce: in std_logic;
sclr: in std_logic;
a: in std_logic_vector(c_a_width - 1 downto 0)
);
end component;
component example_mult_gen_v12_0_i3
port (
b: in std_logic_vector(c_b_width - 1 downto 0);
p: out std_logic_vector(c_output_width - 1 downto 0);
clk: in std_logic;
ce: in std_logic;
sclr: in std_logic;
a: in std_logic_vector(c_a_width - 1 downto 0)
);
end component;
component example_mult_gen_v12_0_i4
port (
b: in std_logic_vector(c_b_width - 1 downto 0);
p: out std_logic_vector(c_output_width - 1 downto 0);
clk: in std_logic;
ce: in std_logic;
sclr: in std_logic;
a: in std_logic_vector(c_a_width - 1 downto 0)
);
end component;
signal tmp_a: std_logic_vector(c_a_width - 1 downto 0);
signal conv_a: std_logic_vector(c_a_width - 1 downto 0);
signal tmp_b: std_logic_vector(c_b_width - 1 downto 0);
signal conv_b: std_logic_vector(c_b_width - 1 downto 0);
signal tmp_p: std_logic_vector(c_output_width - 1 downto 0);
signal conv_p: std_logic_vector(p_width - 1 downto 0);
-- synthesis translate_off
signal real_a, real_b, real_p: real;
-- synthesis translate_on
signal rfd: std_logic;
signal rdy: std_logic;
signal nd: std_logic;
signal internal_ce: std_logic;
signal internal_clr: std_logic;
signal internal_core_ce: std_logic;
begin
-- synthesis translate_off
-- synthesis translate_on
internal_ce <= ce and en(0);
internal_core_ce <= core_ce and en(0);
internal_clr <= (clr or rst(0)) and ce;
nd <= internal_ce;
input_process: process (a,b)
begin
tmp_a <= zero_ext(a, c_a_width);
tmp_b <= zero_ext(b, c_b_width);
end process;
output_process: process (tmp_p)
begin
conv_p <= convert_type(tmp_p, c_output_width, a_bin_pt+b_bin_pt, multsign,
p_width, p_bin_pt, p_arith, quantization, overflow);
end process;
comp0: if ((core_name0 = "example_mult_gen_v12_0_i0")) generate
core_instance0:example_mult_gen_v12_0_i0
port map (
a => tmp_a,
clk => clk,
ce => internal_ce,
sclr => internal_clr,
p => tmp_p,
b => tmp_b
);
end generate;
comp1: if ((core_name0 = "example_mult_gen_v12_0_i1")) generate
core_instance1:example_mult_gen_v12_0_i1
port map (
a => tmp_a,
clk => clk,
ce => internal_ce,
sclr => internal_clr,
p => tmp_p,
b => tmp_b
);
end generate;
comp2: if ((core_name0 = "example_mult_gen_v12_0_i2")) generate
core_instance2:example_mult_gen_v12_0_i2
port map (
a => tmp_a,
clk => clk,
ce => internal_ce,
sclr => internal_clr,
p => tmp_p,
b => tmp_b
);
end generate;
comp3: if ((core_name0 = "example_mult_gen_v12_0_i3")) generate
core_instance3:example_mult_gen_v12_0_i3
port map (
a => tmp_a,
clk => clk,
ce => internal_ce,
sclr => internal_clr,
p => tmp_p,
b => tmp_b
);
end generate;
comp4: if ((core_name0 = "example_mult_gen_v12_0_i4")) generate
core_instance4:example_mult_gen_v12_0_i4
port map (
a => tmp_a,
clk => clk,
ce => internal_ce,
sclr => internal_clr,
p => tmp_p,
b => tmp_b
);
end generate;
latency_gt_0: if (extra_registers > 0) generate
reg: synth_reg
generic map (
width => p_width,
latency => extra_registers
)
port map (
i => conv_p,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => p
);
end generate;
latency_eq_0: if (extra_registers = 0) generate
p <= conv_p;
end generate;
end architecture behavior;
|
Library IEEE;
use IEEE.std_logic_1164.all;
library vunit_lib;
context vunit_lib.vunit_context;
entity tb_FlipFlopD is
generic (runner_cfg : string);
end entity;
architecture tb of tb_FlipFlopD is
component FlipFlopD is
port(
clock: in std_logic;
d: in std_logic;
clear: in std_logic;
preset: in std_logic;
q: out std_logic
);
end component;
signal inClock : std_logic := '0';
signal inD : std_logic;
signal inClear : STD_LOGIC;
signal inPreset : STD_LOGIC;
signal outQ : STD_LOGIC;
begin
mapping: FlipFlopD port map(inClock, inD, inClear, inPreset, outQ);
inClock <= not inClock after 100 ps;
main : process
begin
test_runner_setup(runner, runner_cfg);
-- Teste: 0
inD <= '0'; inClear <= '1'; inPreset <= '0';
wait until inClock'event and inClock='0';
assert(outQ = '0') report "Falha em teste: 0" severity error;
-- Teste: 1
inD <= '1'; inClear <= '0'; inPreset <= '0';
wait until inClock'event and inClock='0';
assert(outQ = '1') report "Falha em teste: 1" severity error;
-- Teste: 2
inD <= '0'; inClear <= '0'; inPreset <= '1';
wait until inClock'event and inClock='0';
assert(outQ = '1') report "Falha em teste: 2" severity error;
-- Teste: 3
inD <= '0'; inClear <= '0'; inPreset <= '0';
wait until inClock'event and inClock='0';
assert(outQ = '0') report "Falha em teste: 3" severity error;
-- Teste: 4
inD <= '1'; inClear <= '0'; inPreset <= '0';
wait until inClock'event and inClock='0';
assert(outQ = '1') report "Falha em teste: 4" severity error;
-- Teste: 5
inD <= '1'; inClear <= '1'; inPreset <= '0';
wait until inClock'event and inClock='0';
assert(outQ = '0') report "Falha em teste: 5" severity error;
-- finish
wait until inClock'event and inClock='0';
test_runner_cleanup(runner); -- Simulation ends here
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bf16_SIMD_MACC_4 is
generic (G : integer := 4);
port(
clk: in std_logic;
reset: in std_logic;
-- in bf16 format
in1: in std_logic_vector(15 downto 0) ;
in2: in std_logic_vector(15 downto 0) ;
in3: in std_logic_vector(15 downto 0) ;
in4: in std_logic_vector(15 downto 0) ;
in5: in std_logic_vector(15 downto 0) ;
in6: in std_logic_vector(15 downto 0) ;
in7: in std_logic_vector(15 downto 0) ;
in8: in std_logic_vector(15 downto 0) ;
result: out std_logic_vector(15 downto 0)
);
end bf16_SIMD_MACC_4;
architecture MACC_SIMD of bf16_SIMD_MACC_4 is
component bf16_add_branch is
generic (G : integer := 4);
port(
clk: in std_logic;
reset: in std_logic;
-- in1 parameters
in1: in std_logic_vector(G+15 downto 0) ;
exp_1: integer;
s_in1: in std_logic;
exc_flag_1: in std_logic;
err_code_1: in std_logic;
-- in2 parameters
in2: in std_logic_vector(G+15 downto 0) ;
exp_2: integer;
s_in2: in std_logic;
exc_flag_2: in std_logic;
err_code_2: in std_logic;
-- result parameters
out_alu_r: out std_logic_vector(G+15 downto 0);
out_exp_r: out integer;
out_s_r: out std_logic;
out_exc_flag: out std_logic;
out_err_code: out std_logic
);
end component;
component bf16_mult_leaf is
generic (G : integer := 4);
port(
clk: in std_logic;
reset: in std_logic;
in1: in std_logic_vector(15 downto 0) ; -- in bf16 format
in2: in std_logic_vector(15 downto 0) ; -- in bf16 format
out_alu_m: out std_logic_vector(G+15 downto 0) ; -- mult result
out_exp_m: out integer ; -- mult result exponent
out_s_m: out std_logic; -- mult result sign
out_exc_flag: out std_logic; -- exception flag
out_err_code: out std_logic -- indicates if NaN or Infinity
);
end component;
component bf16_add_root is
generic (G : integer := 4);
port(
clk: in std_logic;
reset: in std_logic;
-- in1 parameters
in1: in std_logic_vector(G+15 downto 0) ;
exp_1: integer;
s_in1: in std_logic;
exc_flag_1: in std_logic;
err_code_1: in std_logic;
-- in2 parameters
in2: in std_logic_vector(G+15 downto 0) ;
exp_2: integer;
s_in2: in std_logic;
exc_flag_2: in std_logic;
err_code_2: in std_logic;
-- final result in bf16 format
result: out std_logic_vector(15 downto 0)
);
end component;
signal m1_alu_m: std_logic_vector(G+15 downto 0);
signal m1_exp_m: integer;
signal m1_s_m: std_logic;
signal m1_exc_flag: std_logic;
signal m1_err_code: std_logic;
signal m2_alu_m: std_logic_vector(G+15 downto 0);
signal m2_exp_m: integer;
signal m2_s_m: std_logic;
signal m2_exc_flag: std_logic;
signal m2_err_code: std_logic;
signal m3_alu_m: std_logic_vector(G+15 downto 0);
signal m3_exp_m: integer;
signal m3_s_m: std_logic;
signal m3_exc_flag: std_logic;
signal m3_err_code: std_logic;
signal m4_alu_m: std_logic_vector(G+15 downto 0);
signal m4_exp_m: integer;
signal m4_s_m: std_logic;
signal m4_exc_flag: std_logic;
signal m4_err_code: std_logic;
signal a1_alu_r: std_logic_vector(G+15 downto 0);
signal a1_exp_r: integer;
signal a1_s_r: std_logic;
signal a1_exc_flag: std_logic;
signal a1_err_code: std_logic;
signal a2_alu_r: std_logic_vector(G+15 downto 0);
signal a2_exp_r: integer;
signal a2_s_r: std_logic;
signal a2_exc_flag: std_logic;
signal a2_err_code: std_logic;
begin
MULT1: bf16_mult_leaf port map (clk => clk,
reset => reset,
in1 => in1,
in2 => in2,
out_alu_m => m1_alu_m,
out_exp_m => m1_exp_m,
out_s_m => m1_s_m,
out_exc_flag => m1_exc_flag,
out_err_code => m1_err_code );
MULT2: bf16_mult_leaf port map (clk => clk,
reset => reset,
in1 => in3,
in2 => in4,
out_alu_m => m2_alu_m,
out_exp_m => m2_exp_m,
out_s_m => m2_s_m,
out_exc_flag => m2_exc_flag,
out_err_code => m2_err_code );
MULT3: bf16_mult_leaf port map (clk => clk,
reset => reset,
in1 => in5,
in2 => in6,
out_alu_m => m3_alu_m,
out_exp_m => m3_exp_m,
out_s_m => m3_s_m,
out_exc_flag => m3_exc_flag,
out_err_code => m3_err_code );
MULT4: bf16_mult_leaf port map (clk => clk,
reset => reset,
in1 => in7,
in2 => in8,
out_alu_m => m4_alu_m,
out_exp_m => m4_exp_m,
out_s_m => m4_s_m,
out_exc_flag => m4_exc_flag,
out_err_code => m4_err_code );
ADD1: bf16_add_branch port map (clk => clk,
reset => reset,
in1 => m1_alu_m,
exp_1 => m1_exp_m,
s_in1 => m1_s_m,
exc_flag_1 => m1_exc_flag,
err_code_1 => m1_err_code,
in2 => m2_alu_m,
exp_2 => m2_exp_m,
s_in2 => m2_s_m,
exc_flag_2 => m2_exc_flag,
err_code_2 => m2_err_code,
out_alu_r => a1_alu_r,
out_exp_r => a1_exp_r,
out_s_r => a1_s_r,
out_exc_flag => a1_exc_flag,
out_err_code => a1_err_code );
ADD2: bf16_add_branch port map (clk => clk,
reset => reset,
in1 => m3_alu_m,
exp_1 => m3_exp_m,
s_in1 => m3_s_m,
exc_flag_1 => m3_exc_flag,
err_code_1 => m3_err_code,
in2 => m4_alu_m,
exp_2 => m4_exp_m,
s_in2 => m4_s_m,
exc_flag_2 => m4_exc_flag,
err_code_2 => m4_err_code,
out_alu_r => a2_alu_r,
out_exp_r => a2_exp_r,
out_s_r => a2_s_r,
out_exc_flag => a2_exc_flag,
out_err_code => a2_err_code );
ADD3: bf16_add_root port map ( clk => clk,
reset => reset,
in1 => a1_alu_r,
exp_1 => a1_exp_r,
s_in1 => a1_s_r,
exc_flag_1 => a1_exc_flag,
err_code_1 => a1_err_code,
in2 => a2_alu_r,
exp_2 => a2_exp_r,
s_in2 => a2_s_r,
exc_flag_2 => a2_exc_flag,
err_code_2 => a2_err_code,
result => result );
end architecture;
|
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2021-present <NAME>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to use, copy, modify, merge, publish, distribute the Component for
-- educational, research, evaluation, self-interest purposes. Using the
-- Component for commercial purposes is forbidden unless previously agreed with
-- Copyright holder.
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
-- -------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2020 MIT License
--
-- Authors:
-- <NAME> <<EMAIL>>
-- <NAME> <<EMAIL>>
--
-- Project advisors:
-- <NAME> <<EMAIL>>
-- <NAME> <<EMAIL>>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by <NAME> GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- @TestInfoStart
--
-- @Purpose:
-- Self test mode - feature test.
--
-- @Verifies:
-- @1. In Self test mode, transmitted frame is valid even if ACK was recessive!
--
-- @Test sequence:
-- @1. Configures Self Test mode in DUT. Configure ACK forbidden in Test node.
-- @2. Send frame by DUT. Wait till ACK field.
-- @3. Monitor during whole ACK field that frame bus is RECESSIVE.
-- @4. Check that after ACK field, DUT is NOT transmitting Error frame!
-- Wait till bus is idle and check that TXT Buffer in DUT is in TX OK!
-- Check that frame was received by Test node.
--
-- @TestInfoEnd
--------------------------------------------------------------------------------
-- Revision History:
-- 22.9.2019 Created file
--------------------------------------------------------------------------------
Library ctu_can_fd_tb;
context ctu_can_fd_tb.ieee_context;
context ctu_can_fd_tb.rtl_context;
context ctu_can_fd_tb.tb_common_context;
use ctu_can_fd_tb.feature_test_agent_pkg.all;
package mode_self_test_ftest is
procedure mode_self_test_ftest_exec(
signal chn : inout t_com_channel
);
end package;
package body mode_self_test_ftest is
procedure mode_self_test_ftest_exec(
signal chn : inout t_com_channel
) is
variable CAN_TX_frame : SW_CAN_frame_type;
variable CAN_RX_frame : SW_CAN_frame_type;
variable frame_sent : boolean := false;
variable mode_1 : SW_mode := SW_mode_rst_val;
variable mode_2 : SW_mode := SW_mode_rst_val;
variable txt_buf_state : SW_TXT_Buffer_state_type;
variable rx_buf_state : SW_RX_Buffer_info;
variable status : SW_status;
variable frames_equal : boolean := false;
variable pc_dbg : SW_PC_Debug;
begin
------------------------------------------------------------------------
-- @1. Configures Self Test mode in DUT. Configure ACK forbidden in
-- Test node.
------------------------------------------------------------------------
info_m("Step 1: Configuring STM in DUT, ACF in Test node!");
mode_1.self_test := true;
set_core_mode(mode_1, DUT_NODE, chn);
mode_2.acknowledge_forbidden := true;
set_core_mode(mode_2, TEST_NODE, chn);
------------------------------------------------------------------------
-- @2. Send frame by DUT. Wait till ACK field.
------------------------------------------------------------------------
info_m("Step 2: Send frame by DUT, Wait till ACK");
CAN_generate_frame(CAN_TX_frame);
CAN_send_frame(CAN_TX_frame, 1, DUT_NODE, chn, frame_sent);
CAN_wait_pc_state(pc_deb_ack, DUT_NODE, chn);
------------------------------------------------------------------------
-- @3. Monitor during whole ACK field that frame bus is RECESSIVE.
------------------------------------------------------------------------
info_m("Step 3: Checking ACK field is recessive");
CAN_read_pc_debug_m(pc_dbg, DUT_NODE, chn);
while (pc_dbg = pc_deb_ack) loop
check_bus_level(RECESSIVE, "Dominant ACK transmitted!", chn);
CAN_read_pc_debug_m(pc_dbg, DUT_NODE, chn);
get_controller_status(status, DUT_NODE, chn);
check_m(status.transmitter, "DUT receiver!");
wait for 100 ns; -- To make checks more sparse
end loop;
------------------------------------------------------------------------
-- @4. Check that after ACK field, DUT is NOT transmitting Error
-- frame! Wait till bus is idle and check that TXT Buffer in DUT
-- is in TX OK! Check that frame was received by Test node.
------------------------------------------------------------------------
info_m("Step 4: Check Error frame is not transmitted!");
get_controller_status(status, DUT_NODE, chn);
check_false_m(status.error_transmission, "Error frame not transmitted!");
CAN_read_pc_debug_m(pc_dbg, DUT_NODE, chn);
-- For CAN FD frames secondary ACK is still marked as ACK to DEBUG
-- register! From there if this is recessive (it is now, no ACK is sent),
-- it is interpreted as ACK Delimiter and we move directly to EOF! This
-- is OK!
check_m(pc_dbg = pc_deb_ack_delim or
pc_dbg = pc_deb_eof, "ACK delimiter follows recessive ACK!");
CAN_wait_bus_idle(TEST_NODE, chn);
CAN_wait_bus_idle(DUT_NODE, chn);
get_tx_buf_state(1, txt_buf_state, DUT_NODE, chn);
check_m(txt_buf_state = buf_done, "Frame transmitted OK");
get_rx_buf_state(rx_buf_state, TEST_NODE, chn);
check_m(rx_buf_state.rx_frame_count = 1, "Frame received in LOM");
CAN_read_frame(CAN_RX_frame, TEST_NODE, chn);
CAN_compare_frames(CAN_RX_frame, CAN_TX_frame, false, frames_equal);
end procedure;
end package body;
|
<reponame>AEW2015/PYNQ_PR_Overlay
----------------------------------------------------------------------------------
-- Company: Brigham Young University
-- Engineer: <NAME>
--
-- Create Date: 03/17/2017 11:07:04 AM
-- Design Name: RGB filter
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Tool Versions: Vivado 2016.3
-- Description: This design is for a partial bitstream to be programmed
-- on Brigham Young Univeristy's Video Base Design.
-- This filter allows the edit of the RGB values of the pixel through
-- through user registers
--
-- Revision:
-- Revision 1.1
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end Video_Box;
--Begin RGB Control architecture
architecture Behavioral of Video_Box is
--Create Red, Blue, Green signals that contain the actual Red,
--Blue, and Green signals
signal red, blue, green : std_logic_vector(7 downto 0);
--Create the register controlled Red, Green, and Blue signals
signal lred, lblue, lgreen : std_logic_vector(7 downto 0);
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := C_S_AXI_ADDR_WIDTH-ADDR_LSB-1;
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal RGB_IN_reg, RGB_OUT_reg: std_logic_vector(23 downto 0):= (others=>'0');
signal X_Coord_reg,Y_Coord_reg : std_logic_vector(15 downto 0):= (others=>'0');
signal VDE_IN_reg,VDE_OUT_reg,HS_IN_reg,HS_OUT_reg,VS_IN_reg,VS_OUT_reg : std_logic := '0';
--signal USER_LOGIC : std_logic_vector(23 downto 0);
constant N : integer := 16;
component blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END component blk_mem_gen_0;
type rgb_array is array(0 to 255) of std_logic_vector(23 downto 0);
signal color_array : rgb_array := (
x"000000", x"800000", x"008000", x"808000", x"000080", x"800080", x"008080", x"C0C0C0", x"808080", x"FF0000", x"00FF00", x"FFFF00", x"0000FF", x"FF00FF", x"00FFFF", x"FFFFFF",
x"000000", x"00005F", x"000087", x"0000AF", x"0000D7", x"0000FF", x"005F00", x"005F5F", x"005F87", x"005FAF", x"005FD7", x"005FFF", x"008700", x"00875F", x"008787", x"0087AF",
x"0087D7", x"0087FF", x"00AF00", x"00AF5F", x"00AF87", x"00AFAF", x"00AFD7", x"00AFFF", x"00D700", x"00D75F", x"00D787", x"00D7AF", x"00D7D7", x"00D7FF", x"00FF00", x"00FF5F",
x"00FF87", x"00FFAF", x"00FFD7", x"00FFFF", x"5F0000", x"5F005F", x"5F0087", x"5F00AF", x"5F00D7", x"5F00FF", x"5F5F00", x"5F5F5F", x"5F5F87", x"5F5FAF", x"5F5FD7", x"5F5FFF",
x"5F8700", x"5F875F", x"5F8787", x"5F87AF", x"5F87D7", x"5F87FF", x"5FAF00", x"5FAF5F", x"5FAF87", x"5FAFAF", x"5FAFD7", x"5FAFFF", x"5FD700", x"5FD75F", x"5FD787", x"5FD7AF",
x"5FD7D7", x"5FD7FF", x"5FFF00", x"5FFF5F", x"5FFF87", x"5FFFAF", x"5FFFD7", x"5FFFFF", x"870000", x"87005F", x"870087", x"8700AF", x"8700D7", x"8700FF", x"875F00", x"875F5F",
x"875F87", x"875FAF", x"875FD7", x"875FFF", x"878700", x"87875F", x"878787", x"8787AF", x"8787D7", x"8787FF", x"87AF00", x"87AF5F", x"87AF87", x"87AFAF", x"87AFD7", x"87AFFF",
x"87D700", x"87D75F", x"87D787", x"87D7AF", x"87D7D7", x"87D7FF", x"87FF00", x"87FF5F", x"87FF87", x"87FFAF", x"87FFD7", x"87FFFF", x"AF0000", x"AF005F", x"AF0087", x"AF00AF",
x"AF00D7", x"AF00FF", x"AF5F00", x"AF5F5F", x"AF5F87", x"AF5FAF", x"AF5FD7", x"AF5FFF", x"AF8700", x"AF875F", x"AF8787", x"AF87AF", x"AF87D7", x"AF87FF", x"AFAF00", x"AFAF5F",
x"AFAF87", x"AFAFAF", x"AFAFD7", x"AFAFFF", x"AFD700", x"AFD75F", x"AFD787", x"AFD7AF", x"AFD7D7", x"AFD7FF", x"AFFF00", x"AFFF5F", x"AFFF87", x"AFFFAF", x"AFFFD7", x"AFFFFF",
x"D70000", x"D7005F", x"D70087", x"D700AF", x"D700D7", x"D700FF", x"D75F00", x"D75F5F", x"D75F87", x"D75FAF", x"D75FD7", x"D75FFF", x"D78700", x"D7875F", x"D78787", x"D787AF",
x"D787D7", x"D787FF", x"D7AF00", x"D7AF5F", x"D7AF87", x"D7AFAF", x"D7AFD7", x"D7AFFF", x"D7D700", x"D7D75F", x"D7D787", x"D7D7AF", x"D7D7D7", x"D7D7FF", x"D7FF00", x"D7FF5F",
x"D7FF87", x"D7FFAF", x"D7FFD7", x"D7FFFF", x"FF0000", x"FF005F", x"FF0087", x"FF00AF", x"FF00D7", x"FF00FF", x"FF5F00", x"FF5F5F", x"FF5F87", x"FF5FAF", x"FF5FD7", x"FF5FFF",
x"FF8700", x"FF875F", x"FF8787", x"FF87AF", x"FF87D7", x"FF87FF", x"FFAF00", x"FFAF5F", x"FFAF87", x"FFAFAF", x"FFAFD7", x"FFAFFF", x"FFD700", x"FFD75F", x"FFD787", x"FFD7AF",
x"FFD7D7", x"FFD7FF", x"FFFF00", x"FFFF5F", x"FFFF87", x"FFFFAF", x"FFFFD7", x"FFFFFF", x"080808", x"121212", x"1C1C1C", x"262626", x"303030", x"3A3A3A", x"444444", x"4E4E4E",
x"585858", x"606060", x"666666", x"767676", x"808080", x"8A8A8A", x"949494", x"9E9E9E", x"A8A8A8", x"B2B2B2", x"BCBCBC", x"C6C6C6", x"D0D0D0", x"DADADA", x"E4E4E4", x"EEEEEE"
);
signal RGB_IN_reg0, RGB_IN_reg1 : std_logic_vector(23 downto 0);
signal VDE_IN_reg0, VDE_IN_reg1 : std_logic;
signal HB_IN_reg0, HB_IN_reg1 : std_logic;
signal VB_IN_reg0, VB_IN_reg1 : std_logic;
signal HS_IN_reg0, HS_IN_reg1 : std_logic;
signal VS_IN_reg0, VS_IN_reg1 : std_logic;
signal ID_IN_reg0, ID_IN_reg1 : std_logic;
signal rgb_next : std_logic_vector(23 downto 0);
signal use_image : std_logic;
signal color_index, color_index_next : unsigned(7 downto 0);
signal image_index, image_index_next : unsigned(N-1 downto 0);
signal pixel : std_logic_vector(23 downto 0);
signal int_X_Coord_reg0, int_X_Coord_reg1 : unsigned(15 downto 0);
signal int_Y_Coord_reg0, int_Y_Coord_reg1 : unsigned(15 downto 0);
signal int_X_Orig_reg0, int_X_Orig_reg1 : unsigned(15 downto 0);
signal int_Y_Orig_reg0, int_Y_Orig_reg1 : unsigned(15 downto 0);
signal int_X_Coord : unsigned(15 downto 0);
signal int_Y_Coord : unsigned(15 downto 0);
signal int_X_Orig : unsigned(15 downto 0);
signal int_Y_Orig : unsigned(15 downto 0);
signal img_width : unsigned(15 downto 0);
signal img_height : unsigned(15 downto 0);
--signal din, dout : std_logic_vector(23 downto 0);
signal we, rden, wren : std_logic;
signal dout0, dout1 : std_logic_vector(7 downto 0);
signal rdaddr, wraddr : std_logic_vector(N-1 downto 0);
signal din : std_logic_vector(7 downto 0);
begin
--the user can edit the rgb values here
process(PIXEL_CLK)
begin
if(PIXEL_CLK'event and PIXEL_CLK='1') then
RGB_IN_reg0 <= RGB_IN_reg;
VDE_IN_reg0 <= VDE_IN_reg;
HS_IN_reg0 <= HS_IN_reg;
VS_IN_reg0 <= VS_IN_reg;
int_X_Coord_reg0 <= unsigned(X_Coord_reg);
int_Y_Coord_reg0 <= unsigned(Y_Coord_reg);
int_X_Orig_reg0 <= unsigned(slv_reg0(15 downto 0));
int_Y_Orig_reg0 <= unsigned(slv_reg1(15 downto 0));
RGB_IN_reg1 <= RGB_IN_reg0;
VDE_IN_reg1 <= VDE_IN_reg0;
HS_IN_reg1 <= HS_IN_reg0;
VS_IN_reg1 <= VS_IN_reg0;
int_X_Coord_reg1 <= int_X_Coord_reg0;
int_Y_Coord_reg1 <= int_Y_Coord_reg0;
int_X_Orig_reg1 <= int_X_Coord_reg0;
int_Y_Orig_reg1 <= int_Y_Coord_reg0;
image_index <= image_index_next;
end if;
end process;
process(PIXEL_CLK) is
begin
if (rising_edge (PIXEL_CLK)) then
-- Video Input Signals
RGB_IN_reg <= RGB_IN;
X_Coord_reg <= X_Coord;
Y_Coord_reg <= Y_Coord;
VDE_IN_reg <= VDE_IN;
HS_IN_reg <= HS_IN;
VS_IN_reg <= VS_IN;
-- Video Output Signals
RGB_OUT_reg <= rgb_next;
VDE_OUT_reg <= VDE_IN_reg1;
HS_OUT_reg <= HS_IN_reg1;
VS_OUT_reg <= VS_IN_reg1;
end if;
end process;
-- process(S_AXI_ACLK) is
-- begin
-- if(rising_edge(S_AXI_ACLK)) then
wraddr <= slv_reg5(23 downto 8);
din <= slv_reg5(7 downto 0);
wren <= slv_reg_wren;
-- end if;
-- end process;
bram0: blk_mem_gen_0
port map(
clka => S_AXI_ACLK,
ena => wren,
wea(0) => we,
addra => wraddr,
dina => din,
clkb => PIXEL_CLK,
enb => rden,
addrb => rdaddr,
doutb => dout0
);
we <= '1';
rden <= '1';
rdaddr <= std_logic_vector(image_index);
-- Add user logic here
int_X_Coord <= int_X_Coord_reg1;
int_Y_Coord <= int_Y_Coord_reg1;
int_X_Orig <= unsigned(slv_reg0(15 downto 0));
int_Y_Orig <= unsigned(slv_reg1(15 downto 0));
img_width <= unsigned(slv_reg2(15 downto 0));
img_height <= unsigned(slv_reg3(15 downto 0));
use_image <= '1' when int_X_Coord >= int_X_Orig and
int_X_Coord < int_X_Orig + img_width and
int_Y_Coord >= int_Y_Orig and
int_Y_Coord < int_Y_Orig + img_height
else '0';
image_index_next <= (others => '0') when unsigned(X_Coord_reg) = int_X_Orig and unsigned(Y_Coord_reg) = int_Y_Orig and VDE_IN_reg='1' else
image_index + 1 when use_image = '1' and VDE_IN_reg='1' else
image_index;
--color_index <= unsigned(dout0) when image_index < 40960 else unsigned(dout1);
color_index <= unsigned(dout0);
pixel <= color_array(to_integer(color_index));
rgb_next <= pixel when use_image = '1' and std_logic_vector(color_index) /= slv_reg4(7 downto 0) else RGB_IN_reg1;
-- Just pass through all of the video signals
RGB_OUT <= RGB_OUT_reg;
VDE_OUT <= VDE_OUT_reg;
HS_OUT <= HS_OUT_reg;
VS_OUT <= VS_OUT_reg;
-- Route the registers through
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000000000" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000001" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000010" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000011" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg3(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000100" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg4(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"000000101" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg5(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg5 <= slv_reg4;
end case;
end if;
end if;
end if;
end process;
process (slv_reg0, slv_reg1, slv_reg2, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000000000" =>
reg_data_out <= slv_reg0;
when b"000000001" =>
reg_data_out <= slv_reg1;
when b"000000010" =>
reg_data_out <= slv_reg2;
when b"000000011" =>
reg_data_out <= slv_reg3;
when b"000000100" =>
reg_data_out <= slv_reg4;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
end Behavioral;
--End RGB Control architecture
|
<filename>src/PB_Sync.vhd<gh_stars>1-10
library ieee;
use ieee.std_logic_1164.all;
entity PB_Sync is
port(
PB_clk : in std_logic;
PB_reset : in std_logic; --Active low
PB_in : in std_logic_vector(3 downto 0);
PB_out : out std_logic_vector(3 downto 0)
);
end PB_Sync;
architecture internal of PB_Sync is
signal intermediate : std_logic_vector(3 downto 0);
signal outp : std_logic_vector(3 downto 0);
begin
Left : process(PB_clk,PB_reset)
begin
If (PB_reset = '0') then
intermediate <= "0000";
elsif (rising_edge(PB_clk)) then
intermediate <= PB_in;
else
intermediate <= intermediate;
end if;
end process;
Right : process(PB_clk,PB_reset)
begin
If (PB_reset = '0') then
outp <= "0000";
elsif (rising_edge(PB_clk)) then
outp <= intermediate;
else
outp <= outp;
end if;
end process;
PB_out <= outp;
end internal;
|
library ieee;
use ieee.std_logic_1164.all;
package gcm_def is
type tt_type is array(127 downto 0) of std_logic_vector(127 downto 0);
type big_tt_type is array(19 downto 0) of std_logic_vector(127 downto 0);
end package;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
-- Date : Fri Dec 13 14:55:00 2019
-- Host : LAPTOP-4B4E4EPI running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub {e:/AOften/Computer Organization and
-- Design/lab/vivado6/Pipelining/Pipelining.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0_stub.vhdl}
-- Design : dist_mem_gen_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dist_mem_gen_0 is
Port (
a : in STD_LOGIC_VECTOR ( 9 downto 0 );
spo : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end dist_mem_gen_0;
architecture stub of dist_mem_gen_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "a[9:0],spo[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "dist_mem_gen_v8_0_9,Vivado 2015.4";
begin
end;
|
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<KEY>
`protect end_protected
|
library IEEE;
use IEEE.std_logic_1164.all;
package ffaccel_gcu_opcodes is
constant IFE_CALL : natural := 0;
constant IFE_JUMP : natural := 1;
end ffaccel_gcu_opcodes;
|
<gh_stars>10-100
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, <NAME>
-- Copyright (C) 2015 - 2017, <NAME>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: synciotest
-- File: synciotest.vhd
-- Author: <NAME> - <NAME>
-- Description: Synchronous I/O test module
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
entity synciotest is
generic (
ninputs : integer := 1;
noutputs : integer := 1;
nbidir : integer := 1;
dirmode: integer range 0 to 2 := 0 -- 0=both, 1=in-only, 2=out-only
);
port (
clk: in std_ulogic;
rstn: in std_ulogic;
datain: in std_logic_vector(ninputs+nbidir-1 downto 0);
dataout: out std_logic_vector(noutputs+nbidir-1 downto 0);
-- 000=stopped, 001=input 010=output one-by-one, 011=output prng
-- 110=on-off 111=on-off with oe toggle
-- bit 5:3 inverted copy of 2:0, otherwise stopped
tmode: in std_logic_vector(5 downto 0);
tmodeact: out std_ulogic;
tmodeoe: out std_ulogic -- 0=input, 1=output
);
end;
architecture rtl of synciotest is
constant bytelanes_in : integer := (ninputs+nbidir)/8; -- rounded down
constant bytelanes_out : integer := (noutputs+nbidir+7)/8; -- rounded up
function int_max(i1,i2: integer) return integer is
begin
if i1>i2 then return i1; else return i2; end if;
end int_max;
constant bytelanes_max: integer := int_max(bytelanes_in, bytelanes_out);
-- LFSR with period 255 (x^8+x^6+x^5+x^4+1)
-- Rotate 7 steps each time to remove correlation between bits
-- between successive samples
-- Step State -->shift direction--->
-- *8 7 *6 *5 *4 3 2 1
-- 0 a b c d e f g h
-- 1 h a hb hc hd e f g
-- 2 g h ga ghb ghc hd e f
-- 3 f g fh fga fghb ghc hd e
-- 4 e f eg efh efga fghb ghc hd
-- 5 hd e hdf hdeg def efga fghb ghc
-- 6 ghc hd ghce gcdf cde def efga fghb
-- 7 fghb ghc fgbd fbce hbcd cde def efga
subtype lfsrstate is std_logic_vector(8 downto 1);
function nextlfsr (s: lfsrstate) return lfsrstate is
variable nsx: lfsrstate;
variable a,b,c,d,e,f,g,h: std_ulogic;
begin
a := s(8);
b := s(7);
c := s(6);
d := s(5);
e := s(4);
f := s(3);
g := s(2);
h := s(1);
nsx := (f xor g xor h xor b) & (g xor h xor c) & (f xor g xor b xor d) & (f xor b xor c xor e)
& (h xor b xor c xor d) & (c xor d xor e) & (d xor e xor f) & (e xor f xor g xor a);
return nsx;
end nextlfsr;
type synciotest_regs is record
datareg: std_logic_vector(bytelanes_max*8-1 downto 0);
end record;
signal r,nr: synciotest_regs;
begin
comb: process(rstn, tmode, datain, r)
variable v: synciotest_regs;
variable nls: std_logic_vector(bytelanes_max*8-1 downto 0);
variable o: std_logic_vector(noutputs+nbidir-1 downto 0);
variable op: std_logic_vector(2**log2(bytelanes_out*8)-1 downto 0);
variable vact: std_ulogic;
variable voe: std_ulogic;
variable vrst, dx: std_logic_vector(bytelanes_max*8-1 downto 0);
begin
v := r;
o := r.datareg(noutputs+nbidir-1 downto 0);
op := (others => '0');
vact := '0';
voe := tmode(1);
for x in 0 to bytelanes_max-1 loop
nls(x*8+7 downto x*8) := nextlfsr(r.datareg(x*8+7 downto x*8));
end loop;
vrst := (others => '0');
for x in 0 to bytelanes_max-1 loop
vrst(x*8+7 downto x*8) := std_logic_vector(to_unsigned(x+1,8));
end loop;
dx := r.datareg xor vrst;
case tmode is
when "110001" =>
-- Use datareg as sampled input and LFSR state, compare input with
-- expected next state
if dirmode /= 2 then
vact := '1';
o(o'high downto nbidir) := (others => '0');
for x in 0 to bytelanes_in-1 loop
if datain(x*8+7 downto x*8) /= nls(x*8+7 downto x*8) then
o(nbidir+(x mod noutputs)) := '1';
end if;
v.datareg(x*8+7 downto x*8) := datain(x*8+7 downto x*8);
end loop;
-- handle ninputs % 8 != 0 by re-using bottom byte lane LFSR
if ninputs+nbidir > bytelanes_in*8 then
if datain(ninputs+nbidir-1 downto 8*bytelanes_in) /= nls(ninputs+nbidir-bytelanes_in*8-1 downto 0) then
o(nbidir+(bytelanes_in mod noutputs)) := '1';
end if;
end if;
end if;
when "101010" =>
if dirmode /= 1 then
vact := '1';
-- FIXME handle wrong reset vals
-- Use datareg as counter
-- Bits 2:0 pos in sequence "00101010"
-- Bits 3 inv controls value on other outputs than tested
-- Bits X:4 controls which bit is tested
if dx(3)='1' then
op := (others => '0');
else
op := (others => '1');
end if;
op(to_integer(unsigned(dx(log2(noutputs+nbidir)+3 downto 4)))) := not dx(0) and (dx(1) or dx(2));
o := op(noutputs+nbidir-1 downto 0);
dx(log2(noutputs+nbidir)+3 downto 0) :=
std_logic_vector(unsigned(dx(log2(noutputs+nbidir)+3 downto 0))+1);
v.datareg := dx xor vrst;
end if;
when "100011" =>
-- Use datareg as LFSR state, drive as output and clock in next state
if dirmode /= 1 then
vact := '1';
v.datareg := nls;
end if;
when "001110" =>
-- Toggle value on all outputs each cycle
if dirmode /= 1 then
vact := '1';
o := r.datareg(o'length-1 downto 2) & r.datareg(2) & r.datareg(2);
v.datareg(r.datareg'high downto 2) := (others => r.datareg(1));
v.datareg(0) := '1';
v.datareg(1) := r.datareg(1) xor r.datareg(0);
end if;
when "000111" =>
-- Toggle output-enable each cycle, toggle all outputs whenever OE changes
if dirmode /= 1 and nbidir > 0 then
vact := '1';
o := r.datareg(o'length-1 downto 2) & r.datareg(2) & r.datareg(2);
v.datareg(r.datareg'high downto 2) := (others => r.datareg(1));
voe := r.datareg(0);
-- 2-bit counter
v.datareg(0) := not v.datareg(0);
v.datareg(1) := r.datareg(1) xor r.datareg(0);
end if;
when others =>
end case;
if rstn='0' or tmode(2 downto 0)="000" then
v.datareg := vrst;
end if;
nr <= v;
dataout <= o;
tmodeact <= vact;
tmodeoe <= voe;
end process;
regs: process(clk)
begin
if rising_edge(clk) then
r <= nr;
end if;
end process;
--pragma translate_off
tg: if false generate
lfsrtest: process
variable s: lfsrstate;
variable stmap: std_logic_vector(255 downto 0);
variable i,x: integer;
begin
print("------ LFSR test ------");
stmap := (others => '0');
s := "10000000";
i := 0;
loop
x := to_integer(unsigned(s));
print("State: " & tost(s));
if stmap(x)='1' then
print("Looped after " & tost(i) & " iterations");
assert i=255 severity failure;
assert stmap(0)='0' severity failure;
for q in 1 to 255 loop
assert stmap(q)='1' severity failure;
end loop;
print("------ LFSR test done ------");
wait;
end if;
stmap(x) := '1';
s := nextlfsr(s);
i := i+1;
end loop;
end process;
end generate;
--pragma translate_on
end;
|
----------------------------------------------------------------------------------
-- Company: ENSEA
-- Engineer: <NAME>, <NAME>, <NAME>
--
-- Create Date: 26.02.2019 15:13:36
-- Design Name:
-- Module Name: detecteurObstacle - Behavioral
-- Project Name: Portail
-- Target Devices:
-- Tool Versions:
-- Description: module permettant de dire s'il y a un obstacle ou non
-- Attention ! Ne fonctionne que si le duty cycle du PWM est de 80%
--
-- Le signal reçu dans InfoCourant est analysé (on connait le signal correspondant à moteur bloqué après l'avoir analysé avec un oscilloscope)
--
-- Dependencies:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity detecteurObstacle is
Port (
--ENTREES DIVERSES:
CLK: in STD_LOGIC; -- Horloge
SensMoteur : in STD_LOGIC; -- SensMoteur = '1' <=> Ouverture
SignalMoteur : in STD_LOGIC; -- SignalMoteur = '1' <=> Moteur en marche
InfoCourant : in STD_LOGIC; --Signal indiquant si le moteur est bloqué ou non (il faut analyser ce signal)
collision : out STD_LOGIC -- collision = '1' <=> Colliison détectée
);
end detecteurObstacle;
architecture Behavioral of detecteurObstacle is
signal TimeOn_InfoCourant : integer range 0 to 200000 := 0; --Temps pendant lequel sig_InfoCourant est à '1' (actualisé à chaque fois que sig_InfoCourant revient à '1')
signal TimeOff_InfoCourant : integer range 0 to 200000 := 0; --Temps pendant lequel sig_InfoCourant est à '0' (actualisé à chaque fois que sig_InfoCourant revient à '0')
signal previousState_InfoCourant : STD_LOGIC := '0';
signal collisionDetectee : STD_LOGIC := '0'; --Signal de collision détectée, ne sera activé que un front d'horloge en cas de collision, il faut donc traiter le signal
signal sig_collision : STD_LOGIC := '0'; --Signal interne indiquant si une collision est détectée, sera directement envoyé sur collision. Correspond à collisionDetectee après traitement
signal TimeOn_collision : integer range 0 to 500000 := 0; --Temps pendant lequel collisionDetectee est à '1' (actualisé à chaque fois que sig_InfoCourant revient à '1')
signal TimeOff_collision : integer range 0 to 500000 := 0; --Temps pendant lequel collisionDetectee est à '0' (actualisé à chaque fois que sig_InfoCourant revient à '0')
signal sig_InfoCourant : STD_LOGIC := '0'; --bricole pour travailler uniquement avec des signaux synchrones
begin
--Détection du blocage du moteur
process(CLK) begin
if rising_edge(CLK) then
if SignalMoteur = '0' then --Moteur éteint - no problemo
collisionDetectee <= '0';
else --Moteur en marche ! Danger !
if SensMoteur = '1' then --Ouverture
--On essaye de reconnaître le pattern correspondant à moteur bloqué en ouverture
if TimeOn_InfoCourant > 61000 and TimeOn_InfoCourant < 71000 and TimeOff_InfoCourant > 129000 and TimeOff_InfoCourant < 139000 then
--BLOQUE!
collisionDetectee <= '1';
else
collisionDetectee <= '0';
end if;
else --Fermeture
--On essaye de reconnaître le pattern correspondant à moteur bloqué en fermeture
if TimeOn_InfoCourant > 185000 and TimeOff_InfoCourant < 10000 and TimeOff_InfoCourant > 100 then
--BLOQUE!
collisionDetectee <= '1';
else
collisionDetectee <= '0';
end if;
end if;
end if;
end if;
end process;
--Comptage du temps pendant lequel sig_InfoCourant est à '1' ou à '0'
process(CLK) begin
if rising_edge(CLK) then
if previousState_InfoCourant = sig_InfoCourant then
if sig_InfoCourant = '1' then
--On incrémente, mais si c'est déjà à 200000 on laisse tel quel
if TimeOn_InfoCourant < 200000 then
TimeOn_InfoCourant <= TimeOn_InfoCourant + 1;
else
TimeOn_InfoCourant <= TimeOn_InfoCourant;
end if;
previousState_InfoCourant <= '1';
else
--On incrémente, mais si c'est déjà à 200000 on laisse tel quel
if TimeOff_InfoCourant < 200000 then
TimeOff_InfoCourant <= TimeOff_InfoCourant + 1;
else
TimeOff_InfoCourant <= TimeOff_InfoCourant;
end if;
previousState_InfoCourant <= '0';
end if;
else
if sig_InfoCourant = '1' then
TimeOn_InfoCourant <= 0;
previousState_InfoCourant <= '1';
else
TimeOff_InfoCourant <= 0;
previousState_InfoCourant <= '0';
end if;
end if;
end if;
end process;
--Traitement du signal collision
process (CLK) begin
if rising_edge(CLK) then
if TimeOn_collision > 0 and TimeOn_collision < 400000 then
sig_collision <= '1';
TimeOn_collision <= TimeOn_collision + 1;
elsif TimeOn_collision = 0 then
if collisionDetectee = '1' then
TimeOn_collision <= 1;
sig_collision <= '1';
else
TimeOn_collision <= 0;
sig_collision <= '0';
end if;
elsif TimeOn_collision = 400000 then
sig_collision <= '1';
if TimeOff_collision < 200000 then
TimeOn_collision <= TimeOn_collision;
else
TimeOn_collision <= 0;
end if;
end if;
end if;
end process;
--Comptage du temps pendant lequel collisionDetectee est à '0'
process(CLK) begin
if rising_edge(CLK) then
if collisionDetectee = '0' then
if TimeOff_collision < 200000 then
TimeOff_collision <= TimeOff_collision + 1;
else
TimeOff_collision <= TimeOff_collision;
end if;
else
TimeOff_collision <= 0;
end if;
end if;
end process;
--bricole pour travailler avec des signaux synchrones (on actualise sig_InfoCourant à chaque front d'horloge)
process(CLK) begin
if rising_edge(CLK) then
sig_InfoCourant <= InfoCourant;
end if;
end process;
collision <= sig_collision;
end Behavioral;
|
<gh_stars>0
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:
-- Design Name:
-- Module Name: Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.gates.all;
use work.new_vhd_lib.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux_16_16 is
Port ( M0 : in STD_LOGIC_VECTOR (15 downto 0);
M1 : in STD_LOGIC_VECTOR (15 downto 0);
M2 : in STD_LOGIC_VECTOR (15 downto 0);
M3 : in STD_LOGIC_VECTOR (15 downto 0);
M4 : in STD_LOGIC_VECTOR (15 downto 0);
M5 : in STD_LOGIC_VECTOR (15 downto 0);
M6 : in STD_LOGIC_VECTOR (15 downto 0);
M7 : in STD_LOGIC_VECTOR (15 downto 0);
M8 : in STD_LOGIC_VECTOR (15 downto 0);
M9 : in STD_LOGIC_VECTOR (15 downto 0);
M10 : in STD_LOGIC_VECTOR (15 downto 0);
M11 : in STD_LOGIC_VECTOR (15 downto 0);
M12 : in STD_LOGIC_VECTOR (15 downto 0);
M13 : in STD_LOGIC_VECTOR (15 downto 0);
M14 : in STD_LOGIC_VECTOR (15 downto 0);
M15 : in STD_LOGIC_VECTOR (15 downto 0);
SEL : in STD_LOGIC_VECTOR (3 downto 0);
OUTB : out STD_LOGIC_VECTOR (15 downto 0)
);
end mux_16_16;
architecture Behavioral of mux_16_16 is
signal mux8control : STD_LOGIC_VECTOR (2 downto 0);
signal mux2control : STD_LOGIC;
signal mux8out1, mux8out2 : STD_LOGIC_VECTOR (15 downto 0);
begin
mux8control <= SEL(2 downto 0);
mux2control <= SEL(3);
mux8_1_1 :Mux8x1 Port map
( M0 => M0,
M1 => M1,
M2 => M2,
M3 => M3,
M4 => M4,
M5 => M5,
M6 => M6,
M7 => M7,
Z => mux8out1,
SEL => mux8control
);
mux8_1_2 : Mux8x1 Port map
( M0 => M8,
M1 => M9,
M2 => M10,
M3 => M11,
M4 => M12,
M5 => M13,
M6 => M14,
M7 => M15,
Z => mux8out2,
SEL => mux8control
);
mux_2_1: Mux16 Port map
( I0 => mux8out1,
I1 => mux8out2,
O => OUTB,
S => mux2control);
end Behavioral;
|
<reponame>jserot/fppbook
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package fir_types is
type t_coeffs is array (natural range<>) of signed (6 downto 0);
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fir_types.all;
entity fir is
generic (a: t_coeffs);
port(
h: in std_logic;
x: in signed(7 downto 0);
y: out signed(15 downto 0);
rst: in std_logic
);
end entity;
architecture rtl1 of fir is
constant n: natural := a'length;
type mem is array(0 to n-2) of signed(7 downto 0);
signal z: mem;
begin
process(rst, h)
variable acc: signed(15 downto 0);
begin
if rst='1' then
for i in 0 to n-2 loop
z(i) <= to_signed(0,8);
end loop;
elsif rising_edge(h) then
acc := resize(a(0),8) * x;
for i in 1 to n-1 loop -- Calcul ....
acc := acc + resize(a(i),8)*z(i-1);
end loop;
y <= acc; -- ... puis ecriture de la sortie
for i in 1 to n-2 loop -- Mise a jour de z
z(i) <= z(i-1);
end loop;
z(0) <= x;
end if;
end process;
end architecture;
architecture rtl2 of fir is
constant n: natural := a'length;
type mem is array(0 to n-2) of signed(7 downto 0);
signal z: mem;
begin
BUF: process(rst, h)
begin
if rst='1' then -- INIT
for i in 0 to n-2 loop
z(i) <= to_signed(0,8);
end loop;
elsif rising_edge(h) then -- SHIFT RIGHT
for i in 1 to n-2 loop
z(i) <= z(i-1);
end loop;
z(0) <= x;
end if;
end process;
MAC: process(h)
variable acc: signed(15 downto 0);
begin
if rising_edge(h) then
acc := resize(a(0),8) * x;
for i in 1 to n-1 loop
acc := acc + resize(a(i),8)*z(i-1);
end loop;
y <= acc;
end if;
end process;
end architecture;
architecture rtl3 of fir is
constant n: natural := a'length;
type t_z is array(1 to n) of signed(7 downto 0);
signal z: t_z;
type t_acc is array(1 to n-1) of signed(15 downto 0);
signal acc: t_acc;
begin
TAP1: entity work.fir_tap generic map(a(0)) port map (h, x, z(1), to_signed(0,16), acc(1), rst);
TAPs: for i in 2 to n-1 generate
TAPi: entity work.fir_tap generic map(a(i-1)) port map (h, z(i-1), z(i), acc(i-1), acc(i), rst);
end generate;
TAPn: entity work.fir_tap generic map(a(n-1)) port map (h, z(n-1), z(n), acc(n-1), y, rst);
end architecture;
|
<reponame>baileyji/rfsoc_qpsk
-- Generated from Simulink block CTRL
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity qpsk_tx_symbol_gen_ctrl is
port (
autorestartsymbol : in std_logic_vector( 32-1 downto 0 );
enable : in std_logic_vector( 32-1 downto 0 );
lfsr_rst : in std_logic_vector( 32-1 downto 0 );
packetsizesymbol : in std_logic_vector( 32-1 downto 0 );
resetsymbol : in std_logic_vector( 32-1 downto 0 );
transfersymbol : in std_logic_vector( 32-1 downto 0 );
enable_out : out std_logic_vector( 1-1 downto 0 );
lfsr_rst_out : out std_logic_vector( 1-1 downto 0 );
transfersymbol_out : out std_logic_vector( 1-1 downto 0 );
autorestartsymbol_out : out std_logic_vector( 1-1 downto 0 );
resetsymbol_out : out std_logic_vector( 1-1 downto 0 )
);
end qpsk_tx_symbol_gen_ctrl;
architecture structural of qpsk_tx_symbol_gen_ctrl is
signal transfersymbol_net : std_logic_vector( 32-1 downto 0 );
signal resetsymbol_net : std_logic_vector( 32-1 downto 0 );
signal packetsizesymbol_net : std_logic_vector( 32-1 downto 0 );
signal enable_net : std_logic_vector( 32-1 downto 0 );
signal slice1_y_net : std_logic_vector( 1-1 downto 0 );
signal slice3_y_net : std_logic_vector( 1-1 downto 0 );
signal lfsr_rst_net : std_logic_vector( 32-1 downto 0 );
signal slice6_y_net : std_logic_vector( 1-1 downto 0 );
signal slice_y_net : std_logic_vector( 1-1 downto 0 );
signal slice4_y_net : std_logic_vector( 1-1 downto 0 );
signal autorestartsymbol_net : std_logic_vector( 32-1 downto 0 );
begin
enable_out <= slice_y_net;
lfsr_rst_out <= slice1_y_net;
transfersymbol_out <= slice3_y_net;
autorestartsymbol_out <= slice4_y_net;
resetsymbol_out <= slice6_y_net;
autorestartsymbol_net <= autorestartsymbol;
enable_net <= enable;
lfsr_rst_net <= lfsr_rst;
packetsizesymbol_net <= packetsizesymbol;
resetsymbol_net <= resetsymbol;
transfersymbol_net <= transfersymbol;
slice : entity xil_defaultlib.qpsk_tx_symbol_gen_xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 32,
y_width => 1
)
port map (
x => enable_net,
y => slice_y_net
);
slice1 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 32,
y_width => 1
)
port map (
x => lfsr_rst_net,
y => slice1_y_net
);
slice3 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 32,
y_width => 1
)
port map (
x => transfersymbol_net,
y => slice3_y_net
);
slice4 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 32,
y_width => 1
)
port map (
x => autorestartsymbol_net,
y => slice4_y_net
);
slice6 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlslice
generic map (
new_lsb => 0,
new_msb => 0,
x_width => 32,
y_width => 1
)
port map (
x => resetsymbol_net,
y => slice6_y_net
);
end structural;
-- Generated from Simulink block M_AXIS_SYMBOL
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity qpsk_tx_symbol_gen_m_axis_symbol is
port (
tdata_in : in std_logic_vector( 8-1 downto 0 );
tvalid_in : in std_logic_vector( 1-1 downto 0 );
tlast_in : in std_logic_vector( 1-1 downto 0 );
m_symbol_axis_tready : in std_logic_vector( 1-1 downto 0 )
);
end qpsk_tx_symbol_gen_m_axis_symbol;
architecture structural of qpsk_tx_symbol_gen_m_axis_symbol is
signal convert4_dout_net : std_logic_vector( 8-1 downto 0 );
signal m_symbol_axis_tready_net : std_logic_vector( 1-1 downto 0 );
signal register4_q_net : std_logic_vector( 1-1 downto 0 );
signal register3_q_net : std_logic_vector( 1-1 downto 0 );
begin
convert4_dout_net <= tdata_in;
register4_q_net <= tvalid_in;
register3_q_net <= tlast_in;
m_symbol_axis_tready_net <= m_symbol_axis_tready;
end structural;
-- Generated from Simulink block QPSK_symbol_mapper
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity qpsk_tx_symbol_gen_qpsk_symbol_mapper is
port (
bit_pairs : in std_logic_vector( 2-1 downto 0 );
reset : in std_logic_vector( 1-1 downto 0 );
clk_51200 : in std_logic;
ce_51200 : in std_logic;
i_symbols : out std_logic_vector( 2-1 downto 0 );
q_symbols : out std_logic_vector( 2-1 downto 0 )
);
end qpsk_tx_symbol_gen_qpsk_symbol_mapper;
architecture structural of qpsk_tx_symbol_gen_qpsk_symbol_mapper is
signal register_q_net_x0 : std_logic_vector( 2-1 downto 0 );
signal register1_q_net_x0 : std_logic_vector( 2-1 downto 0 );
signal register_q_net : std_logic_vector( 2-1 downto 0 );
signal slice1_y_net : std_logic_vector( 1-1 downto 0 );
signal constant_op_net : std_logic_vector( 2-1 downto 0 );
signal mux1_y_net : std_logic_vector( 2-1 downto 0 );
signal ce_net : std_logic;
signal constant1_op_net : std_logic_vector( 2-1 downto 0 );
signal constant3_op_net : std_logic_vector( 2-1 downto 0 );
signal constant2_op_net : std_logic_vector( 2-1 downto 0 );
signal clk_net : std_logic;
signal mux_y_net : std_logic_vector( 2-1 downto 0 );
begin
i_symbols <= register_q_net_x0;
q_symbols <= register1_q_net_x0;
register_q_net <= bit_pairs;
slice1_y_net <= reset;
clk_net <= clk_51200;
ce_net <= ce_51200;
constant_x0 : entity xil_defaultlib.sysgen_constant_c8c4086527
port map (
clk => '0',
ce => '0',
clr => '0',
op => constant_op_net
);
constant1 : entity xil_defaultlib.sysgen_constant_b8e3a467cb
port map (
clk => '0',
ce => '0',
clr => '0',
op => constant1_op_net
);
constant2 : entity xil_defaultlib.sysgen_constant_c8c4086527
port map (
clk => '0',
ce => '0',
clr => '0',
op => constant2_op_net
);
constant3 : entity xil_defaultlib.sysgen_constant_b8e3a467cb
port map (
clk => '0',
ce => '0',
clr => '0',
op => constant3_op_net
);
mux : entity xil_defaultlib.sysgen_mux_9bb83b0c60
port map (
clk => '0',
ce => '0',
clr => '0',
sel => register_q_net,
d0 => constant_op_net,
d1 => constant_op_net,
d2 => constant1_op_net,
d3 => constant1_op_net,
y => mux_y_net
);
mux1 : entity xil_defaultlib.sysgen_mux_9bb83b0c60
port map (
clk => '0',
ce => '0',
clr => '0',
sel => register_q_net,
d0 => constant2_op_net,
d1 => constant3_op_net,
d2 => constant2_op_net,
d3 => constant3_op_net,
y => mux1_y_net
);
register_x0 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
en => "1",
d => mux_y_net,
rst => slice1_y_net,
clk => clk_net,
ce => ce_net,
q => register_q_net_x0
);
register1 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
en => "1",
d => mux1_y_net,
rst => slice1_y_net,
clk => clk_net,
ce => ce_net,
q => register1_q_net_x0
);
end structural;
-- Generated from Simulink block Random_data_generator
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity qpsk_tx_symbol_gen_random_data_generator is
port (
enable : in std_logic_vector( 1-1 downto 0 );
reset : in std_logic_vector( 1-1 downto 0 );
clk_51200 : in std_logic;
ce_51200 : in std_logic;
tvalid_out : out std_logic_vector( 1-1 downto 0 );
bit_pairs : out std_logic_vector( 2-1 downto 0 )
);
end qpsk_tx_symbol_gen_random_data_generator;
architecture structural of qpsk_tx_symbol_gen_random_data_generator is
signal register3_q_net : std_logic_vector( 1-1 downto 0 );
signal register_q_net : std_logic_vector( 2-1 downto 0 );
signal slice_y_net : std_logic_vector( 1-1 downto 0 );
signal slice1_y_net : std_logic_vector( 1-1 downto 0 );
signal lfsr1_dout_net : std_logic_vector( 1-1 downto 0 );
signal clk_net : std_logic;
signal ce_net : std_logic;
signal concat_y_net : std_logic_vector( 2-1 downto 0 );
signal lfsr_dout_net : std_logic_vector( 1-1 downto 0 );
signal register2_q_net : std_logic_vector( 1-1 downto 0 );
begin
tvalid_out <= register3_q_net;
bit_pairs <= register_q_net;
slice_y_net <= enable;
slice1_y_net <= reset;
clk_net <= clk_51200;
ce_net <= ce_51200;
concat : entity xil_defaultlib.sysgen_concat_2c273a2ba5
port map (
clk => '0',
ce => '0',
clr => '0',
in0 => lfsr1_dout_net,
in1 => lfsr_dout_net,
y => concat_y_net
);
lfsr : entity xil_defaultlib.sysgen_lfsr_d7aeaa8912
port map (
clr => '0',
rst => slice1_y_net,
en => slice_y_net,
clk => clk_net,
ce => ce_net,
dout => lfsr_dout_net
);
lfsr1 : entity xil_defaultlib.sysgen_lfsr_84c7de9677
port map (
clr => '0',
rst => slice1_y_net,
en => slice_y_net,
clk => clk_net,
ce => ce_net,
dout => lfsr1_dout_net
);
register_x0 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
en => "1",
d => concat_y_net,
rst => slice1_y_net,
clk => clk_net,
ce => ce_net,
q => register_q_net
);
register2 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
en => "1",
d => slice_y_net,
rst => slice1_y_net,
clk => clk_net,
ce => ce_net,
q => register2_q_net
);
register3 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
en => "1",
d => register2_q_net,
rst => slice1_y_net,
clk => clk_net,
ce => ce_net,
q => register3_q_net
);
end structural;
-- Generated from Simulink block AXI_Write_Interface
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity qpsk_tx_symbol_gen_axi_write_interface is
port (
int_reset : in std_logic_vector( 1-1 downto 0 );
transfer : in std_logic_vector( 1-1 downto 0 );
auto_restart : in std_logic_vector( 1-1 downto 0 );
packet_size : in std_logic_vector( 32-1 downto 0 );
tdata_in : in std_logic_vector( 4-1 downto 0 );
tvalid_in : in std_logic_vector( 1-1 downto 0 );
tready : in std_logic_vector( 1-1 downto 0 );
clk_1 : in std_logic;
ce_1 : in std_logic;
ce_51200 : in std_logic;
tdata_out : out std_logic_vector( 4-1 downto 0 );
tlast_out : out std_logic_vector( 1-1 downto 0 );
tvalid_out : out std_logic_vector( 1-1 downto 0 )
);
end qpsk_tx_symbol_gen_axi_write_interface;
architecture structural of qpsk_tx_symbol_gen_axi_write_interface is
signal logical3_y_net : std_logic_vector( 1-1 downto 0 );
signal register3_q_net : std_logic_vector( 1-1 downto 0 );
signal slice6_y_net : std_logic_vector( 1-1 downto 0 );
signal packetsizesymbol_net : std_logic_vector( 32-1 downto 0 );
signal register4_q_net : std_logic_vector( 1-1 downto 0 );
signal register5_q_net : std_logic_vector( 4-1 downto 0 );
signal slice3_y_net : std_logic_vector( 1-1 downto 0 );
signal slice4_y_net : std_logic_vector( 1-1 downto 0 );
signal convert2_dout_net : std_logic_vector( 1-1 downto 0 );
signal ce_net : std_logic;
signal convert3_dout_net : std_logic_vector( 1-1 downto 0 );
signal convert5_dout_net : std_logic_vector( 1-1 downto 0 );
signal mcode_re_net : std_logic_vector( 1-1 downto 0 );
signal ce_net_x0 : std_logic;
signal counter_op_net : std_logic_vector( 32-1 downto 0 );
signal relational_op_net : std_logic_vector( 1-1 downto 0 );
signal logical_y_net : std_logic_vector( 1-1 downto 0 );
signal logical1_y_net : std_logic_vector( 1-1 downto 0 );
signal convert1_dout_net : std_logic_vector( 1-1 downto 0 );
signal register2_q_net : std_logic_vector( 1-1 downto 0 );
signal constant_op_net : std_logic_vector( 11-1 downto 0 );
signal concat_y_net : std_logic_vector( 4-1 downto 0 );
signal m_symbol_axis_tready_net : std_logic_vector( 1-1 downto 0 );
signal convert_dout_net : std_logic_vector( 1-1 downto 0 );
signal clk_net : std_logic;
signal inverter1_op_net : std_logic_vector( 1-1 downto 0 );
signal fifo_full_net : std_logic;
signal relational1_op_net : std_logic_vector( 1-1 downto 0 );
signal logical2_y_net : std_logic;
signal fifo_empty_net : std_logic;
signal fifo_dcount_net : std_logic_vector( 7-1 downto 0 );
signal fifo_dout_net : std_logic_vector( 4-1 downto 0 );
signal inverter_op_net : std_logic_vector( 1-1 downto 0 );
begin
tdata_out <= register5_q_net;
tlast_out <= register3_q_net;
tvalid_out <= register4_q_net;
slice6_y_net <= int_reset;
slice3_y_net <= transfer;
slice4_y_net <= auto_restart;
packetsizesymbol_net <= packet_size;
concat_y_net <= tdata_in;
register2_q_net <= tvalid_in;
m_symbol_axis_tready_net <= tready;
clk_net <= clk_1;
ce_net <= ce_1;
ce_net_x0 <= ce_51200;
constant_x0 : entity xil_defaultlib.sysgen_constant_1acb71f782
port map (
clk => '0',
ce => '0',
clr => '0',
op => constant_op_net
);
convert : entity xil_defaultlib.qpsk_tx_symbol_gen_xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
clr => '0',
en => "1",
din => slice3_y_net,
clk => clk_net,
ce => ce_net,
dout => convert_dout_net
);
convert1 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
clr => '0',
en => "1",
din => register3_q_net,
clk => clk_net,
ce => ce_net,
dout => convert1_dout_net
);
convert2 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
clr => '0',
en => "1",
din => relational_op_net,
clk => clk_net,
ce => ce_net,
dout => convert2_dout_net
);
convert3 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
clr => '0',
en => "1",
din => slice4_y_net,
clk => clk_net,
ce => ce_net,
dout => convert3_dout_net
);
convert5 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
clr => '0',
en => "1",
din => mcode_re_net,
clk => clk_net,
ce => ce_net,
dout => convert5_dout_net
);
counter : entity xil_defaultlib.qpsk_tx_symbol_gen_xlcounter_free
generic map (
core_name0 => "qpsk_tx_symbol_gen_c_counter_binary_v12_0_i0",
op_arith => xlUnsigned,
op_width => 32
)
port map (
clr => '0',
rst => logical_y_net,
en => logical1_y_net,
clk => clk_net,
ce => ce_net,
op => counter_op_net
);
fifo : entity xil_defaultlib.qpsk_tx_symbol_gen_xlfifogen_u
generic map (
core_name0 => "qpsk_tx_symbol_gen_fifo_generator_i0",
data_count_width => 7,
data_width => 4,
extra_registers => 1,
has_ae => 0,
has_af => 0,
has_rst => true,
percent_full_width => 1
)
port map (
en => '1',
din => concat_y_net,
we => register2_q_net(0),
re => logical2_y_net,
rst => slice6_y_net(0),
clk => clk_net,
ce => ce_net,
we_ce => ce_net_x0,
re_ce => ce_net,
dout => fifo_dout_net,
empty => fifo_empty_net,
full => fifo_full_net,
dcount => fifo_dcount_net
);
inverter : entity xil_defaultlib.sysgen_inverter_af11c886ea
port map (
clr => '0',
ip => convert5_dout_net,
clk => clk_net,
ce => ce_net,
op => inverter_op_net
);
inverter1 : entity xil_defaultlib.sysgen_inverter_af11c886ea
port map (
clr => '0',
ip => relational1_op_net,
clk => clk_net,
ce => ce_net,
op => inverter1_op_net
);
logical : entity xil_defaultlib.sysgen_logical_1f748ed6a3
port map (
clk => '0',
ce => '0',
clr => '0',
d0 => slice6_y_net,
d1 => inverter1_op_net,
y => logical_y_net
);
logical1 : entity xil_defaultlib.sysgen_logical_735c50577b
port map (
clk => '0',
ce => '0',
clr => '0',
d0 => m_symbol_axis_tready_net,
d1 => convert5_dout_net,
y => logical1_y_net
);
logical2 : entity xil_defaultlib.sysgen_logical_1f748ed6a3
port map (
clk => '0',
ce => '0',
clr => '0',
d0 => logical1_y_net,
d1 => logical3_y_net,
y(0) => logical2_y_net
);
logical3 : entity xil_defaultlib.sysgen_logical_735c50577b
port map (
clk => '0',
ce => '0',
clr => '0',
d0(0) => fifo_full_net,
d1 => inverter_op_net,
y => logical3_y_net
);
mcode : entity xil_defaultlib.sysgen_mcode_block_a61fffe920
port map (
clr => '0',
axiwrite => convert_dout_net,
tlast => convert1_dout_net,
dcount => convert2_dout_net,
axiauto => convert3_dout_net,
clk => clk_net,
ce => ce_net,
re => mcode_re_net
);
register3 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
d => inverter1_op_net,
rst => slice6_y_net,
en => m_symbol_axis_tready_net,
clk => clk_net,
ce => ce_net,
q => register3_q_net
);
register4 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
d => convert5_dout_net,
rst => slice6_y_net,
en => m_symbol_axis_tready_net,
clk => clk_net,
ce => ce_net,
q => register4_q_net
);
register5 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlregister
generic map (
d_width => 4,
init_value => b"0000"
)
port map (
d => fifo_dout_net,
rst => slice6_y_net,
en => m_symbol_axis_tready_net,
clk => clk_net,
ce => ce_net,
q => register5_q_net
);
relational : entity xil_defaultlib.sysgen_relational_fb64b2795b
port map (
clk => '0',
ce => '0',
clr => '0',
a => fifo_dcount_net,
b => constant_op_net,
op => relational_op_net
);
relational1 : entity xil_defaultlib.sysgen_relational_8c4040f65a
port map (
clk => '0',
ce => '0',
clr => '0',
a => counter_op_net,
b => packetsizesymbol_net,
op => relational1_op_net
);
end structural;
-- Generated from Simulink block M_AXIS_SYMBOL_CTRL
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity qpsk_tx_symbol_gen_m_axis_symbol_ctrl is
port (
i_data : in std_logic_vector( 2-1 downto 0 );
tvalid_in : in std_logic_vector( 1-1 downto 0 );
q_data : in std_logic_vector( 2-1 downto 0 );
reset : in std_logic_vector( 1-1 downto 0 );
packet_size : in std_logic_vector( 32-1 downto 0 );
tready_in : in std_logic_vector( 1-1 downto 0 );
transfer : in std_logic_vector( 1-1 downto 0 );
auto_restart : in std_logic_vector( 1-1 downto 0 );
clk_1 : in std_logic;
ce_1 : in std_logic;
ce_51200 : in std_logic;
tdata_out : out std_logic_vector( 8-1 downto 0 );
tvalid_out : out std_logic_vector( 1-1 downto 0 );
tlast_out : out std_logic_vector( 1-1 downto 0 )
);
end qpsk_tx_symbol_gen_m_axis_symbol_ctrl;
architecture structural of qpsk_tx_symbol_gen_m_axis_symbol_ctrl is
signal register2_q_net : std_logic_vector( 1-1 downto 0 );
signal packetsizesymbol_net : std_logic_vector( 32-1 downto 0 );
signal m_symbol_axis_tready_net : std_logic_vector( 1-1 downto 0 );
signal register5_q_net : std_logic_vector( 4-1 downto 0 );
signal concat_y_net : std_logic_vector( 4-1 downto 0 );
signal register_q_net : std_logic_vector( 2-1 downto 0 );
signal reinterpret_output_port_net : std_logic_vector( 2-1 downto 0 );
signal convert4_dout_net : std_logic_vector( 8-1 downto 0 );
signal slice6_y_net : std_logic_vector( 1-1 downto 0 );
signal ce_net_x0 : std_logic;
signal reinterpret1_output_port_net : std_logic_vector( 2-1 downto 0 );
signal ce_net : std_logic;
signal clk_net : std_logic;
signal slice4_y_net : std_logic_vector( 1-1 downto 0 );
signal register4_q_net : std_logic_vector( 1-1 downto 0 );
signal register1_q_net : std_logic_vector( 2-1 downto 0 );
signal register3_q_net : std_logic_vector( 1-1 downto 0 );
signal slice3_y_net : std_logic_vector( 1-1 downto 0 );
begin
tdata_out <= convert4_dout_net;
tvalid_out <= register4_q_net;
tlast_out <= register3_q_net;
register_q_net <= i_data;
register2_q_net <= tvalid_in;
register1_q_net <= q_data;
slice6_y_net <= reset;
packetsizesymbol_net <= packet_size;
m_symbol_axis_tready_net <= tready_in;
slice3_y_net <= transfer;
slice4_y_net <= auto_restart;
clk_net <= clk_1;
ce_net <= ce_1;
ce_net_x0 <= ce_51200;
axi_write_interface : entity xil_defaultlib.qpsk_tx_symbol_gen_axi_write_interface
port map (
int_reset => slice6_y_net,
transfer => slice3_y_net,
auto_restart => slice4_y_net,
packet_size => packetsizesymbol_net,
tdata_in => concat_y_net,
tvalid_in => register2_q_net,
tready => m_symbol_axis_tready_net,
clk_1 => clk_net,
ce_1 => ce_net,
ce_51200 => ce_net_x0,
tdata_out => register5_q_net,
tlast_out => register3_q_net,
tvalid_out => register4_q_net
);
concat : entity xil_defaultlib.sysgen_concat_1db22441e5
port map (
clk => '0',
ce => '0',
clr => '0',
in0 => reinterpret_output_port_net,
in1 => reinterpret1_output_port_net,
y => concat_y_net
);
convert4 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlconvert
generic map (
bool_conversion => 0,
din_arith => 1,
din_bin_pt => 0,
din_width => 4,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 8,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
clr => '0',
en => "1",
din => register5_q_net,
clk => clk_net,
ce => ce_net,
dout => convert4_dout_net
);
reinterpret : entity xil_defaultlib.sysgen_reinterpret_4e3293e801
port map (
clk => '0',
ce => '0',
clr => '0',
input_port => register1_q_net,
output_port => reinterpret_output_port_net
);
reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_4e3293e801
port map (
clk => '0',
ce => '0',
clr => '0',
input_port => register_q_net,
output_port => reinterpret1_output_port_net
);
end structural;
-- Generated from Simulink block Symbol_2_Output
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity qpsk_tx_symbol_gen_symbol_2_output is
port (
symbol_i_data : in std_logic_vector( 2-1 downto 0 );
symbol_i_valid : in std_logic_vector( 1-1 downto 0 );
symbol_q_data : in std_logic_vector( 2-1 downto 0 );
reset : in std_logic_vector( 1-1 downto 0 );
packet_size : in std_logic_vector( 32-1 downto 0 );
transfer : in std_logic_vector( 1-1 downto 0 );
auto_restart : in std_logic_vector( 1-1 downto 0 );
tready_in : in std_logic_vector( 1-1 downto 0 );
clk_1 : in std_logic;
ce_1 : in std_logic;
ce_51200 : in std_logic;
tdata_out : out std_logic_vector( 8-1 downto 0 );
tvalid_out : out std_logic_vector( 1-1 downto 0 );
tlast_out : out std_logic_vector( 1-1 downto 0 )
);
end qpsk_tx_symbol_gen_symbol_2_output;
architecture structural of qpsk_tx_symbol_gen_symbol_2_output is
signal register3_q_net : std_logic_vector( 1-1 downto 0 );
signal slice3_y_net : std_logic_vector( 1-1 downto 0 );
signal ce_net : std_logic;
signal slice4_y_net : std_logic_vector( 1-1 downto 0 );
signal packetsizesymbol_net : std_logic_vector( 32-1 downto 0 );
signal register2_q_net : std_logic_vector( 1-1 downto 0 );
signal slice6_y_net : std_logic_vector( 1-1 downto 0 );
signal register4_q_net : std_logic_vector( 1-1 downto 0 );
signal clk_net : std_logic;
signal ce_net_x0 : std_logic;
signal m_symbol_axis_tready_net : std_logic_vector( 1-1 downto 0 );
signal register1_q_net : std_logic_vector( 2-1 downto 0 );
signal register_q_net : std_logic_vector( 2-1 downto 0 );
signal convert4_dout_net : std_logic_vector( 8-1 downto 0 );
begin
tdata_out <= convert4_dout_net;
tvalid_out <= register4_q_net;
tlast_out <= register3_q_net;
register_q_net <= symbol_i_data;
register2_q_net <= symbol_i_valid;
register1_q_net <= symbol_q_data;
slice6_y_net <= reset;
packetsizesymbol_net <= packet_size;
slice3_y_net <= transfer;
slice4_y_net <= auto_restart;
m_symbol_axis_tready_net <= tready_in;
clk_net <= clk_1;
ce_net <= ce_1;
ce_net_x0 <= ce_51200;
m_axis_symbol_ctrl : entity xil_defaultlib.qpsk_tx_symbol_gen_m_axis_symbol_ctrl
port map (
i_data => register_q_net,
tvalid_in => register2_q_net,
q_data => register1_q_net,
reset => slice6_y_net,
packet_size => packetsizesymbol_net,
tready_in => m_symbol_axis_tready_net,
transfer => slice3_y_net,
auto_restart => slice4_y_net,
clk_1 => clk_net,
ce_1 => ce_net,
ce_51200 => ce_net_x0,
tdata_out => convert4_dout_net,
tvalid_out => register4_q_net,
tlast_out => register3_q_net
);
end structural;
-- Generated from Simulink block qpsk_tx_symbol_gen_struct
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity qpsk_tx_symbol_gen_struct is
port (
packetsizerf : in std_logic_vector( 32-1 downto 0 );
autorestartsymbol : in std_logic_vector( 32-1 downto 0 );
enable : in std_logic_vector( 32-1 downto 0 );
lfsr_rst : in std_logic_vector( 32-1 downto 0 );
packetsizesymbol : in std_logic_vector( 32-1 downto 0 );
resetsymbol : in std_logic_vector( 32-1 downto 0 );
transfersymbol : in std_logic_vector( 32-1 downto 0 );
m_symbol_axis_tready : in std_logic_vector( 1-1 downto 0 );
clk_1 : in std_logic;
ce_1 : in std_logic;
clk_51200 : in std_logic;
ce_51200 : in std_logic;
m_symbol_axis_tdata_x0 : out std_logic_vector( 8-1 downto 0 );
m_symbol_axis_tlast : out std_logic_vector( 1-1 downto 0 );
m_symbol_axis_tvalid_x0 : out std_logic_vector( 1-1 downto 0 );
m_symbol_axis_tdata : out std_logic_vector( 8-1 downto 0 );
m_symbol_axis_tvalid : out std_logic_vector( 1-1 downto 0 )
);
end qpsk_tx_symbol_gen_struct;
architecture structural of qpsk_tx_symbol_gen_struct is
signal autorestartsymbol_net : std_logic_vector( 32-1 downto 0 );
signal packetsizerf_net : std_logic_vector( 32-1 downto 0 );
signal enable_net : std_logic_vector( 32-1 downto 0 );
signal lfsr_rst_net : std_logic_vector( 32-1 downto 0 );
signal concat_y_net : std_logic_vector( 8-1 downto 0 );
signal slice6_y_net : std_logic_vector( 1-1 downto 0 );
signal clk_net : std_logic;
signal clk_net_x0 : std_logic;
signal register_q_net : std_logic_vector( 2-1 downto 0 );
signal transfersymbol_net : std_logic_vector( 32-1 downto 0 );
signal slice4_y_net : std_logic_vector( 1-1 downto 0 );
signal register1_q_net : std_logic_vector( 2-1 downto 0 );
signal slice1_y_net : std_logic_vector( 1-1 downto 0 );
signal ce_net : std_logic;
signal ce_net_x0 : std_logic;
signal convert1_dout_net : std_logic_vector( 4-1 downto 0 );
signal register3_q_net : std_logic_vector( 1-1 downto 0 );
signal register2_q_net_x0 : std_logic_vector( 1-1 downto 0 );
signal slice_y_net : std_logic_vector( 1-1 downto 0 );
signal reinterpret_output_port_net : std_logic_vector( 4-1 downto 0 );
signal convert_dout_net : std_logic_vector( 4-1 downto 0 );
signal register3_q_net_x0 : std_logic_vector( 1-1 downto 0 );
signal m_symbol_axis_tready_net : std_logic_vector( 1-1 downto 0 );
signal register4_q_net : std_logic_vector( 1-1 downto 0 );
signal register_q_net_x0 : std_logic_vector( 2-1 downto 0 );
signal resetsymbol_net : std_logic_vector( 32-1 downto 0 );
signal convert4_dout_net : std_logic_vector( 8-1 downto 0 );
signal reinterpret1_output_port_net : std_logic_vector( 4-1 downto 0 );
signal slice3_y_net : std_logic_vector( 1-1 downto 0 );
signal packetsizesymbol_net : std_logic_vector( 32-1 downto 0 );
begin
packetsizerf_net <= packetsizerf;
autorestartsymbol_net <= autorestartsymbol;
enable_net <= enable;
lfsr_rst_net <= lfsr_rst;
packetsizesymbol_net <= packetsizesymbol;
resetsymbol_net <= resetsymbol;
transfersymbol_net <= transfersymbol;
m_symbol_axis_tdata_x0 <= convert4_dout_net;
m_symbol_axis_tlast <= register3_q_net;
m_symbol_axis_tready_net <= m_symbol_axis_tready;
m_symbol_axis_tvalid_x0 <= register4_q_net;
m_symbol_axis_tdata <= concat_y_net;
m_symbol_axis_tvalid <= register2_q_net_x0;
clk_net <= clk_1;
ce_net <= ce_1;
clk_net_x0 <= clk_51200;
ce_net_x0 <= ce_51200;
ctrl : entity xil_defaultlib.qpsk_tx_symbol_gen_ctrl
port map (
autorestartsymbol => autorestartsymbol_net,
enable => enable_net,
lfsr_rst => lfsr_rst_net,
packetsizesymbol => packetsizesymbol_net,
resetsymbol => resetsymbol_net,
transfersymbol => transfersymbol_net,
enable_out => slice_y_net,
lfsr_rst_out => slice1_y_net,
transfersymbol_out => slice3_y_net,
autorestartsymbol_out => slice4_y_net,
resetsymbol_out => slice6_y_net
);
m_axis_symbol : entity xil_defaultlib.qpsk_tx_symbol_gen_m_axis_symbol
port map (
tdata_in => convert4_dout_net,
tvalid_in => register4_q_net,
tlast_in => register3_q_net,
m_symbol_axis_tready => m_symbol_axis_tready_net
);
qpsk_symbol_mapper : entity xil_defaultlib.qpsk_tx_symbol_gen_qpsk_symbol_mapper
port map (
bit_pairs => register_q_net_x0,
reset => slice1_y_net,
clk_51200 => clk_net_x0,
ce_51200 => ce_net_x0,
i_symbols => register_q_net,
q_symbols => register1_q_net
);
random_data_generator : entity xil_defaultlib.qpsk_tx_symbol_gen_random_data_generator
port map (
enable => slice_y_net,
reset => slice1_y_net,
clk_51200 => clk_net_x0,
ce_51200 => ce_net_x0,
tvalid_out => register3_q_net_x0,
bit_pairs => register_q_net_x0
);
symbol_2_output : entity xil_defaultlib.qpsk_tx_symbol_gen_symbol_2_output
port map (
symbol_i_data => register_q_net,
symbol_i_valid => register2_q_net_x0,
symbol_q_data => register1_q_net,
reset => slice6_y_net,
packet_size => packetsizesymbol_net,
transfer => slice3_y_net,
auto_restart => slice4_y_net,
tready_in => m_symbol_axis_tready_net,
clk_1 => clk_net,
ce_1 => ce_net,
ce_51200 => ce_net_x0,
tdata_out => convert4_dout_net,
tvalid_out => register4_q_net,
tlast_out => register3_q_net
);
concat : entity xil_defaultlib.sysgen_concat_4cbc566218
port map (
clk => '0',
ce => '0',
clr => '0',
in0 => reinterpret_output_port_net,
in1 => reinterpret1_output_port_net,
y => concat_y_net
);
register2 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
en => "1",
d => register3_q_net_x0,
rst => slice1_y_net,
clk => clk_net_x0,
ce => ce_net_x0,
q => register2_q_net_x0
);
reinterpret : entity xil_defaultlib.sysgen_reinterpret_4012dc8d9e
port map (
clk => '0',
ce => '0',
clr => '0',
input_port => convert_dout_net,
output_port => reinterpret_output_port_net
);
reinterpret1 : entity xil_defaultlib.sysgen_reinterpret_4012dc8d9e
port map (
clk => '0',
ce => '0',
clr => '0',
input_port => convert1_dout_net,
output_port => reinterpret1_output_port_net
);
convert : entity xil_defaultlib.qpsk_tx_symbol_gen_xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 0,
din_width => 2,
dout_arith => 2,
dout_bin_pt => 0,
dout_width => 4,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
clr => '0',
en => "1",
din => register_q_net,
clk => clk_net_x0,
ce => ce_net_x0,
dout => convert_dout_net
);
convert1 : entity xil_defaultlib.qpsk_tx_symbol_gen_xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 0,
din_width => 2,
dout_arith => 2,
dout_bin_pt => 0,
dout_width => 4,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
clr => '0',
en => "1",
din => register1_q_net,
clk => clk_net_x0,
ce => ce_net_x0,
dout => convert1_dout_net
);
end structural;
-- Generated from Simulink block
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity qpsk_tx_symbol_gen_default_clock_driver is
port (
qpsk_tx_symbol_gen_sysclk : in std_logic;
qpsk_tx_symbol_gen_sysce : in std_logic;
qpsk_tx_symbol_gen_sysclr : in std_logic;
qpsk_tx_symbol_gen_clk1 : out std_logic;
qpsk_tx_symbol_gen_ce1 : out std_logic;
qpsk_tx_symbol_gen_clk51200 : out std_logic;
qpsk_tx_symbol_gen_ce51200 : out std_logic
);
end qpsk_tx_symbol_gen_default_clock_driver;
architecture structural of qpsk_tx_symbol_gen_default_clock_driver is
begin
clockdriver_x0 : entity xil_defaultlib.xlclockdriver
generic map (
period => 1,
log_2_period => 1
)
port map (
sysclk => qpsk_tx_symbol_gen_sysclk,
sysce => qpsk_tx_symbol_gen_sysce,
sysclr => qpsk_tx_symbol_gen_sysclr,
clk => qpsk_tx_symbol_gen_clk1,
ce => qpsk_tx_symbol_gen_ce1
);
clockdriver : entity xil_defaultlib.xlclockdriver
generic map (
period => 51200,
log_2_period => 16
)
port map (
sysclk => qpsk_tx_symbol_gen_sysclk,
sysce => qpsk_tx_symbol_gen_sysce,
sysclr => qpsk_tx_symbol_gen_sysclr,
clk => qpsk_tx_symbol_gen_clk51200,
ce => qpsk_tx_symbol_gen_ce51200
);
end structural;
-- Generated from Simulink block
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity qpsk_tx_symbol_gen is
port (
m_symbol_axis_tready : in std_logic_vector( 1-1 downto 0 );
clk : in std_logic;
qpsk_tx_symbol_gen_aresetn : in std_logic;
qpsk_tx_symbol_gen_s_axi_awaddr : in std_logic_vector( 6-1 downto 0 );
qpsk_tx_symbol_gen_s_axi_awvalid : in std_logic;
qpsk_tx_symbol_gen_s_axi_wdata : in std_logic_vector( 32-1 downto 0 );
qpsk_tx_symbol_gen_s_axi_wstrb : in std_logic_vector( 4-1 downto 0 );
qpsk_tx_symbol_gen_s_axi_wvalid : in std_logic;
qpsk_tx_symbol_gen_s_axi_bready : in std_logic;
qpsk_tx_symbol_gen_s_axi_araddr : in std_logic_vector( 6-1 downto 0 );
qpsk_tx_symbol_gen_s_axi_arvalid : in std_logic;
qpsk_tx_symbol_gen_s_axi_rready : in std_logic;
m_symbol_axis_tdata_x0 : out std_logic_vector( 8-1 downto 0 );
m_symbol_axis_tlast : out std_logic_vector( 1-1 downto 0 );
m_symbol_axis_tvalid_x0 : out std_logic_vector( 1-1 downto 0 );
m_symbol_axis_tdata : out std_logic_vector( 8-1 downto 0 );
m_symbol_axis_tvalid : out std_logic_vector( 1-1 downto 0 );
qpsk_tx_symbol_gen_s_axi_awready : out std_logic;
qpsk_tx_symbol_gen_s_axi_wready : out std_logic;
qpsk_tx_symbol_gen_s_axi_bresp : out std_logic_vector( 2-1 downto 0 );
qpsk_tx_symbol_gen_s_axi_bvalid : out std_logic;
qpsk_tx_symbol_gen_s_axi_arready : out std_logic;
qpsk_tx_symbol_gen_s_axi_rdata : out std_logic_vector( 32-1 downto 0 );
qpsk_tx_symbol_gen_s_axi_rresp : out std_logic_vector( 2-1 downto 0 );
qpsk_tx_symbol_gen_s_axi_rvalid : out std_logic
);
end qpsk_tx_symbol_gen;
architecture structural of qpsk_tx_symbol_gen is
attribute core_generation_info : string;
attribute core_generation_info of structural : architecture is "qpsk_tx_symbol_gen,sysgen_core_2018_3,{,compilation=IP Catalog,block_icon_display=Default,family=zynquplusRFSOC,part=xczu28dr,speed=-2-e,package=ffvg1517,synthesis_language=vhdl,hdl_library=xil_defaultlib,synthesis_strategy=Vivado Synthesis Defaults,implementation_strategy=Vivado Implementation Defaults,testbench=0,interface_doc=0,ce_clr=0,clock_period=39.0625,system_simulink_period=3.90625e-08,waveform_viewer=0,axilite_interface=1,ip_catalog_plugin=0,hwcosim_burst_mode=0,simulation_time=0.2,concat=3,constant=5,convert=8,counter=2,fifo=1,inv=3,lfsr=2,logical=5,mcode=1,mux=2,register=11,reinterpret=4,relational=3,slice=5,}";
signal autorestartsymbol : std_logic_vector( 32-1 downto 0 );
signal lfsr_rst : std_logic_vector( 32-1 downto 0 );
signal resetsymbol : std_logic_vector( 32-1 downto 0 );
signal transfersymbol : std_logic_vector( 32-1 downto 0 );
signal enable : std_logic_vector( 32-1 downto 0 );
signal packetsizesymbol : std_logic_vector( 32-1 downto 0 );
signal packetsizerf : std_logic_vector( 32-1 downto 0 );
signal clk_1_net : std_logic;
signal clk_51200_net : std_logic;
signal ce_1_net : std_logic;
signal ce_51200_net : std_logic;
signal clk_net : std_logic;
begin
qpsk_tx_symbol_gen_axi_lite_interface : entity xil_defaultlib.qpsk_tx_symbol_gen_axi_lite_interface
port map (
qpsk_tx_symbol_gen_s_axi_awaddr => qpsk_tx_symbol_gen_s_axi_awaddr,
qpsk_tx_symbol_gen_s_axi_awvalid => qpsk_tx_symbol_gen_s_axi_awvalid,
qpsk_tx_symbol_gen_s_axi_wdata => qpsk_tx_symbol_gen_s_axi_wdata,
qpsk_tx_symbol_gen_s_axi_wstrb => qpsk_tx_symbol_gen_s_axi_wstrb,
qpsk_tx_symbol_gen_s_axi_wvalid => qpsk_tx_symbol_gen_s_axi_wvalid,
qpsk_tx_symbol_gen_s_axi_bready => qpsk_tx_symbol_gen_s_axi_bready,
qpsk_tx_symbol_gen_s_axi_araddr => qpsk_tx_symbol_gen_s_axi_araddr,
qpsk_tx_symbol_gen_s_axi_arvalid => qpsk_tx_symbol_gen_s_axi_arvalid,
qpsk_tx_symbol_gen_s_axi_rready => qpsk_tx_symbol_gen_s_axi_rready,
qpsk_tx_symbol_gen_aresetn => qpsk_tx_symbol_gen_aresetn,
qpsk_tx_symbol_gen_aclk => clk,
transfersymbol => transfersymbol,
resetsymbol => resetsymbol,
packetsizesymbol => packetsizesymbol,
lfsr_rst => lfsr_rst,
enable => enable,
autorestartsymbol => autorestartsymbol,
packetsizerf => packetsizerf,
qpsk_tx_symbol_gen_s_axi_awready => qpsk_tx_symbol_gen_s_axi_awready,
qpsk_tx_symbol_gen_s_axi_wready => qpsk_tx_symbol_gen_s_axi_wready,
qpsk_tx_symbol_gen_s_axi_bresp => qpsk_tx_symbol_gen_s_axi_bresp,
qpsk_tx_symbol_gen_s_axi_bvalid => qpsk_tx_symbol_gen_s_axi_bvalid,
qpsk_tx_symbol_gen_s_axi_arready => qpsk_tx_symbol_gen_s_axi_arready,
qpsk_tx_symbol_gen_s_axi_rdata => qpsk_tx_symbol_gen_s_axi_rdata,
qpsk_tx_symbol_gen_s_axi_rresp => qpsk_tx_symbol_gen_s_axi_rresp,
qpsk_tx_symbol_gen_s_axi_rvalid => qpsk_tx_symbol_gen_s_axi_rvalid,
clk => clk_net
);
qpsk_tx_symbol_gen_default_clock_driver : entity xil_defaultlib.qpsk_tx_symbol_gen_default_clock_driver
port map (
qpsk_tx_symbol_gen_sysclk => clk_net,
qpsk_tx_symbol_gen_sysce => '1',
qpsk_tx_symbol_gen_sysclr => '0',
qpsk_tx_symbol_gen_clk1 => clk_1_net,
qpsk_tx_symbol_gen_ce1 => ce_1_net,
qpsk_tx_symbol_gen_clk51200 => clk_51200_net,
qpsk_tx_symbol_gen_ce51200 => ce_51200_net
);
qpsk_tx_symbol_gen_struct : entity xil_defaultlib.qpsk_tx_symbol_gen_struct
port map (
packetsizerf => packetsizerf,
autorestartsymbol => autorestartsymbol,
enable => enable,
lfsr_rst => lfsr_rst,
packetsizesymbol => packetsizesymbol,
resetsymbol => resetsymbol,
transfersymbol => transfersymbol,
m_symbol_axis_tready => m_symbol_axis_tready,
clk_1 => clk_1_net,
ce_1 => ce_1_net,
clk_51200 => clk_51200_net,
ce_51200 => ce_51200_net,
m_symbol_axis_tdata_x0 => m_symbol_axis_tdata_x0,
m_symbol_axis_tlast => m_symbol_axis_tlast,
m_symbol_axis_tvalid_x0 => m_symbol_axis_tvalid_x0,
m_symbol_axis_tdata => m_symbol_axis_tdata,
m_symbol_axis_tvalid => m_symbol_axis_tvalid
);
end structural;
|
-- *!***************************************************************************
-- *! Copyright 2019 International Business Machines
-- *!
-- *! Licensed under the Apache License, Version 2.0 (the "License");
-- *! you may not use this file except in compliance with the License.
-- *! You may obtain a copy of the License at
-- *! http://www.apache.org/licenses/LICENSE-2.0
-- *!
-- *! The patent license granted to you in Section 3 of the License, as applied
-- *! to the "Work," hereby includes implementations of the Work in physical form.
-- *!
-- *! Unless required by applicable law or agreed to in writing, the reference design
-- *! distributed under the License is distributed on an "AS IS" BASIS,
-- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- *! See the License for the specific language governing permissions and
-- *! limitations under the License.
-- *!
-- *! The background Specification upon which this is based is managed by and available from
-- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org.
-- *!***************************************************************************
library ieee, ibm, work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi_pkg.all;
use work.ice_func.all;
entity axi_regs_32 is
generic (
-- Offset of register block
offset : natural := 0;
-- Scom Write Enable Masks
REG_00_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
REG_01_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
REG_02_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
REG_03_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
REG_04_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
REG_05_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
REG_06_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
REG_07_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
REG_08_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
REG_09_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
REG_0A_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
REG_0B_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
REG_0C_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
REG_0D_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
REG_0E_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
REG_0F_WE_MASK : std_ulogic_vector(31 downto 0) := x"FFFFFFFF";
-- Hardware Write Enable Masks
REG_00_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_01_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_02_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_03_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_04_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_05_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_06_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_07_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_08_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_09_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_0A_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_0B_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_0C_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_0D_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_0E_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_0F_HWWE_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
-- Stick Bit Masks
REG_00_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_01_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_02_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_03_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_04_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_05_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_06_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_07_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_08_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_09_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_0A_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_0B_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_0C_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_0D_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_0E_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000";
REG_0F_STICKY_MASK : std_ulogic_vector(31 downto 0) := x"00000000"
);
port (
-- AXI4-Lite
s0_axi_aclk : in std_ulogic;
s0_axi_i : in t_AXI4_LITE_SLAVE_INPUT;
s0_axi_o : out t_AXI4_LITE_SLAVE_OUTPUT;
-- Register Data
reg_00_o : out std_ulogic_vector(31 downto 0);
reg_01_o : out std_ulogic_vector(31 downto 0);
reg_02_o : out std_ulogic_vector(31 downto 0);
reg_03_o : out std_ulogic_vector(31 downto 0);
reg_04_o : out std_ulogic_vector(31 downto 0);
reg_05_o : out std_ulogic_vector(31 downto 0);
reg_06_o : out std_ulogic_vector(31 downto 0);
reg_07_o : out std_ulogic_vector(31 downto 0);
reg_08_o : out std_ulogic_vector(31 downto 0);
reg_09_o : out std_ulogic_vector(31 downto 0);
reg_0A_o : out std_ulogic_vector(31 downto 0);
reg_0B_o : out std_ulogic_vector(31 downto 0);
reg_0C_o : out std_ulogic_vector(31 downto 0);
reg_0D_o : out std_ulogic_vector(31 downto 0);
reg_0E_o : out std_ulogic_vector(31 downto 0);
reg_0F_o : out std_ulogic_vector(31 downto 0);
-- Expandable Register Interface
-- Read Data
exp_rd_valid : out std_ulogic;
exp_rd_address : out std_ulogic_vector(31 downto 0);
exp_rd_data : in std_ulogic_vector(31 downto 0) := x"00000000";
exp_rd_data_valid : in std_ulogic := '0';
-- Write Data
exp_wr_valid : out std_ulogic;
exp_wr_address : out std_ulogic_vector(31 downto 0);
exp_wr_data : out std_ulogic_vector(31 downto 0);
-- Hardware Write Update Values and Enables
reg_00_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_01_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_02_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_03_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_04_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_05_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_06_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_07_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_08_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_09_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_0A_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_0B_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_0C_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_0D_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_0E_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_0F_update_i : in std_ulogic_vector(31 downto 0) := x"00000000";
reg_00_hwwe_i : in std_ulogic := '0';
reg_01_hwwe_i : in std_ulogic := '0';
reg_02_hwwe_i : in std_ulogic := '0';
reg_03_hwwe_i : in std_ulogic := '0';
reg_04_hwwe_i : in std_ulogic := '0';
reg_05_hwwe_i : in std_ulogic := '0';
reg_06_hwwe_i : in std_ulogic := '0';
reg_07_hwwe_i : in std_ulogic := '0';
reg_08_hwwe_i : in std_ulogic := '0';
reg_09_hwwe_i : in std_ulogic := '0';
reg_0A_hwwe_i : in std_ulogic := '0';
reg_0B_hwwe_i : in std_ulogic := '0';
reg_0C_hwwe_i : in std_ulogic := '0';
reg_0D_hwwe_i : in std_ulogic := '0';
reg_0E_hwwe_i : in std_ulogic := '0';
reg_0F_hwwe_i : in std_ulogic := '0'
);
end axi_regs_32;
architecture axi_regs_32 of axi_regs_32 is
signal s0_axi_aresetn : std_ulogic;
signal s0_axi_awvalid : std_ulogic;
signal s0_axi_awready : std_ulogic;
signal s0_axi_awaddr : std_ulogic_vector(31 downto 0);
signal s0_axi_awprot : std_ulogic_vector(2 downto 0);
signal s0_axi_wvalid : std_ulogic;
signal s0_axi_wready : std_ulogic;
signal s0_axi_wdata : std_ulogic_vector(31 downto 0);
signal s0_axi_wstrb : std_ulogic_vector(3 downto 0);
signal s0_axi_bvalid : std_ulogic;
signal s0_axi_bready : std_ulogic;
signal s0_axi_bresp : std_ulogic_vector(1 downto 0);
signal s0_axi_arvalid : std_ulogic;
signal s0_axi_arready : std_ulogic;
signal s0_axi_araddr : std_ulogic_vector(31 downto 0);
signal s0_axi_arprot : std_ulogic_vector(2 downto 0);
signal s0_axi_rvalid : std_ulogic;
signal s0_axi_rready : std_ulogic;
signal s0_axi_rdata : std_ulogic_vector(31 downto 0);
signal s0_axi_rresp : std_ulogic_vector(1 downto 0);
signal axi_rd_state_d : std_ulogic_vector(3 downto 0);
signal axi_rd_state_q : std_ulogic_vector(3 downto 0);
signal axi_rd_state_ns0_0 : std_ulogic;
signal axi_rd_state_ns0_1 : std_ulogic;
signal axi_rd_state_ns0_2 : std_ulogic;
signal axi_rd_state_ns0_3 : std_ulogic;
signal axi_rd_state_ns1_0 : std_ulogic;
signal axi_rd_state_ns1_1 : std_ulogic;
signal axi_rd_state_ns1_2 : std_ulogic;
signal axi_rd_state_ns1_3 : std_ulogic;
signal axi_rd_state_ns2_0 : std_ulogic;
signal axi_rd_state_ns2_1 : std_ulogic;
signal axi_rd_state_ns2_2 : std_ulogic;
signal axi_rd_state_ns2_3 : std_ulogic;
signal axi_rd_state_ns3_0 : std_ulogic;
signal axi_rd_state_ns3_1 : std_ulogic;
signal axi_rd_state_ns3_2 : std_ulogic;
signal axi_rd_state_ns3_3 : std_ulogic;
signal reg_rd_valid : std_ulogic;
signal reg_rd_valid_d : std_ulogic;
signal reg_rd_valid_q : std_ulogic;
signal reg_rd_addr_d : std_ulogic_vector(31 downto 0);
signal reg_rd_addr_q : std_ulogic_vector(31 downto 0);
signal axi_wr_state_d : std_ulogic_vector(4 downto 0);
signal axi_wr_state_q : std_ulogic_vector(4 downto 0);
signal axi_wr_state_ns0_0 : std_ulogic;
signal axi_wr_state_ns0_1 : std_ulogic;
signal axi_wr_state_ns0_2 : std_ulogic;
signal axi_wr_state_ns0_3 : std_ulogic;
signal axi_wr_state_ns0_4 : std_ulogic;
signal axi_wr_state_ns1_0 : std_ulogic;
signal axi_wr_state_ns1_1 : std_ulogic;
signal axi_wr_state_ns1_2 : std_ulogic;
signal axi_wr_state_ns1_3 : std_ulogic;
signal axi_wr_state_ns1_4 : std_ulogic;
signal axi_wr_state_ns2_0 : std_ulogic;
signal axi_wr_state_ns2_1 : std_ulogic;
signal axi_wr_state_ns2_2 : std_ulogic;
signal axi_wr_state_ns2_3 : std_ulogic;
signal axi_wr_state_ns2_4 : std_ulogic;
signal axi_wr_state_ns3_0 : std_ulogic;
signal axi_wr_state_ns3_1 : std_ulogic;
signal axi_wr_state_ns3_2 : std_ulogic;
signal axi_wr_state_ns3_3 : std_ulogic;
signal axi_wr_state_ns3_4 : std_ulogic;
signal axi_wr_state_ns4_0 : std_ulogic;
signal axi_wr_state_ns4_1 : std_ulogic;
signal axi_wr_state_ns4_2 : std_ulogic;
signal axi_wr_state_ns4_3 : std_ulogic;
signal axi_wr_state_ns4_4 : std_ulogic;
signal reg_wr_valid : std_ulogic;
signal reg_wr_addr_d : std_ulogic_vector(31 downto 0);
signal reg_wr_addr_q : std_ulogic_vector(31 downto 0);
signal s0_axi_wdata_d : std_ulogic_vector(31 downto 0);
signal s0_axi_wdata_q : std_ulogic_vector(31 downto 0);
signal reg_00_d : std_ulogic_vector(31 downto 0);
signal reg_01_d : std_ulogic_vector(31 downto 0);
signal reg_02_d : std_ulogic_vector(31 downto 0);
signal reg_03_d : std_ulogic_vector(31 downto 0);
signal reg_04_d : std_ulogic_vector(31 downto 0);
signal reg_05_d : std_ulogic_vector(31 downto 0);
signal reg_06_d : std_ulogic_vector(31 downto 0);
signal reg_07_d : std_ulogic_vector(31 downto 0);
signal reg_08_d : std_ulogic_vector(31 downto 0);
signal reg_09_d : std_ulogic_vector(31 downto 0);
signal reg_0A_d : std_ulogic_vector(31 downto 0);
signal reg_0B_d : std_ulogic_vector(31 downto 0);
signal reg_0C_d : std_ulogic_vector(31 downto 0);
signal reg_0D_d : std_ulogic_vector(31 downto 0);
signal reg_0E_d : std_ulogic_vector(31 downto 0);
signal reg_0F_d : std_ulogic_vector(31 downto 0);
signal reg_00_q : std_ulogic_vector(31 downto 0);
signal reg_01_q : std_ulogic_vector(31 downto 0);
signal reg_02_q : std_ulogic_vector(31 downto 0);
signal reg_03_q : std_ulogic_vector(31 downto 0);
signal reg_04_q : std_ulogic_vector(31 downto 0);
signal reg_05_q : std_ulogic_vector(31 downto 0);
signal reg_06_q : std_ulogic_vector(31 downto 0);
signal reg_07_q : std_ulogic_vector(31 downto 0);
signal reg_08_q : std_ulogic_vector(31 downto 0);
signal reg_09_q : std_ulogic_vector(31 downto 0);
signal reg_0A_q : std_ulogic_vector(31 downto 0);
signal reg_0B_q : std_ulogic_vector(31 downto 0);
signal reg_0C_q : std_ulogic_vector(31 downto 0);
signal reg_0D_q : std_ulogic_vector(31 downto 0);
signal reg_0E_q : std_ulogic_vector(31 downto 0);
signal reg_0F_q : std_ulogic_vector(31 downto 0);
begin
-----------------------------------------------------------------------------
-- AXI4-Lite Record
-----------------------------------------------------------------------------
-- Global
s0_axi_aresetn <= s0_axi_i.s0_axi_aresetn;
-- Write Address Channel
s0_axi_awvalid <= s0_axi_i.s0_axi_awvalid;
s0_axi_o.s0_axi_awready <= s0_axi_awready;
s0_axi_awaddr(31 downto 0) <= s0_axi_i.s0_axi_awaddr(31 downto 0);
s0_axi_awprot(2 downto 0) <= s0_axi_i.s0_axi_awprot(2 downto 0);
-- Write Data Channel
s0_axi_wvalid <= s0_axi_i.s0_axi_wvalid;
s0_axi_o.s0_axi_wready <= s0_axi_wready;
s0_axi_wdata(31 downto 0) <= s0_axi_i.s0_axi_wdata(31 downto 0);
s0_axi_wstrb(3 downto 0) <= s0_axi_i.s0_axi_wstrb(3 downto 0);
-- Write Response Channel
s0_axi_o.s0_axi_bvalid <= s0_axi_bvalid;
s0_axi_bready <= s0_axi_i.s0_axi_bready;
s0_axi_o.s0_axi_bresp(1 downto 0) <= s0_axi_bresp(1 downto 0);
-- Read Address Channel
s0_axi_arvalid <= s0_axi_i.s0_axi_arvalid;
s0_axi_o.s0_axi_arready <= s0_axi_arready;
s0_axi_araddr(31 downto 0) <= s0_axi_i.s0_axi_araddr(31 downto 0);
s0_axi_arprot(2 downto 0) <= s0_axi_i.s0_axi_arprot(2 downto 0);
-- Read Data Channel
s0_axi_o.s0_axi_rvalid <= s0_axi_rvalid;
s0_axi_rready <= s0_axi_i.s0_axi_rready;
s0_axi_o.s0_axi_rdata(31 downto 0) <= s0_axi_rdata(31 downto 0);
s0_axi_o.s0_axi_rresp(1 downto 0) <= s0_axi_rresp(1 downto 0);
-----------------------------------------------------------------------------
-- Expandable Register Interface
-----------------------------------------------------------------------------
-- Read Data
exp_rd_valid <= reg_rd_valid;
exp_rd_address <= reg_rd_addr_q;
-- Write Data
exp_wr_valid <= reg_wr_valid;
exp_wr_address <= reg_wr_addr_q;
exp_wr_data <= s0_axi_wdata_q;
-----------------------------------------------------------------------------
-- Read Transaction State Machine
-----------------------------------------------------------------------------
-- AXI Control Inputs: s0_axi_arvalid, s0_axi_rready
-- AXI Control Outputs: s0_axi_arready, s0_axi_rvalid, s0_axi_rresp
-- State 0 - Idle - 0x1
axi_rd_state_ns0_0 <= axi_rd_state_q(0) and not s0_axi_arvalid;
axi_rd_state_ns0_1 <= axi_rd_state_q(0) and s0_axi_arvalid;
axi_rd_state_ns0_2 <= axi_rd_state_q(0) and '0';
axi_rd_state_ns0_3 <= axi_rd_state_q(0) and '0';
-- State 1 - Received ARValid - 0x2
axi_rd_state_ns1_0 <= axi_rd_state_q(1) and '0';
axi_rd_state_ns1_1 <= axi_rd_state_q(1) and '0';
axi_rd_state_ns1_2 <= axi_rd_state_q(1) and '1';
axi_rd_state_ns1_3 <= axi_rd_state_q(1) and '0';
-- State 2 - Wait for Data - 0x4
axi_rd_state_ns2_0 <= axi_rd_state_q(2) and '0';
axi_rd_state_ns2_1 <= axi_rd_state_q(2) and '0';
axi_rd_state_ns2_2 <= axi_rd_state_q(2) and '0';
axi_rd_state_ns2_3 <= axi_rd_state_q(2) and '1';
-- State 3 - Send Data - 0x8
axi_rd_state_ns3_0 <= axi_rd_state_q(3) and s0_axi_rready;
axi_rd_state_ns3_1 <= axi_rd_state_q(3) and '0';
axi_rd_state_ns3_2 <= axi_rd_state_q(3) and '0';
axi_rd_state_ns3_3 <= axi_rd_state_q(3) and not s0_axi_rready;
-- Control Outputs
s0_axi_arready <= axi_rd_state_q(1);
s0_axi_rvalid <= axi_rd_state_q(3);
s0_axi_rresp <= "00";
-- AXI Data Inputs: s0_axi_araddr
-- AXI Data Outputs: s0_axi_rdata
-- Register Control: reg_rd_valid, reg_rd_addr
reg_rd_valid <= axi_rd_state_q(2);
reg_rd_valid_d <= axi_rd_state_q(2);
reg_rd_addr_d <= gate(reg_rd_addr_q , not axi_rd_state_q(0)) or
gate(s0_axi_araddr and x"FFFFFFFF", axi_rd_state_q(0));
-- Next State
axi_rd_state_d(0) <= axi_rd_state_ns0_0 or axi_rd_state_ns1_0 or axi_rd_state_ns2_0 or axi_rd_state_ns3_0;
axi_rd_state_d(1) <= axi_rd_state_ns0_1 or axi_rd_state_ns1_1 or axi_rd_state_ns2_1 or axi_rd_state_ns3_1;
axi_rd_state_d(2) <= axi_rd_state_ns0_2 or axi_rd_state_ns1_2 or axi_rd_state_ns2_2 or axi_rd_state_ns3_2;
axi_rd_state_d(3) <= axi_rd_state_ns0_3 or axi_rd_state_ns1_3 or axi_rd_state_ns2_3 or axi_rd_state_ns3_3;
-----------------------------------------------------------------------------
-- Write Transaction State Machine
-----------------------------------------------------------------------------
-- AXI Control Inputs: s0_axi_awvalid, s0_axi_wvalid, s0_axi_bready
-- AXI Control Outputs: s0_axi_awready, s0_axi_wready, s0_axi_bvalid, s0_axi_bresp
-- State 0 - Idle - 0x01
axi_wr_state_ns0_0 <= axi_wr_state_q(0) and not s0_axi_awvalid;
axi_wr_state_ns0_1 <= axi_wr_state_q(0) and s0_axi_awvalid;
axi_wr_state_ns0_2 <= axi_wr_state_q(0) and '0';
axi_wr_state_ns0_3 <= axi_wr_state_q(0) and '0';
axi_wr_state_ns0_4 <= axi_wr_state_q(0) and '0';
-- State 1 - Received AWValid - 0x02
axi_wr_state_ns1_0 <= axi_wr_state_q(1) and '0';
axi_wr_state_ns1_1 <= axi_wr_state_q(1) and '0';
axi_wr_state_ns1_2 <= axi_wr_state_q(1) and '1';
axi_wr_state_ns1_3 <= axi_wr_state_q(1) and '0';
axi_wr_state_ns1_4 <= axi_wr_state_q(1) and '0';
-- State 2 - Wait for WValid - 0x04
axi_wr_state_ns2_0 <= axi_wr_state_q(2) and '0';
axi_wr_state_ns2_1 <= axi_wr_state_q(2) and '0';
axi_wr_state_ns2_2 <= axi_wr_state_q(2) and not s0_axi_wvalid;
axi_wr_state_ns2_3 <= axi_wr_state_q(2) and s0_axi_wvalid;
axi_wr_state_ns2_4 <= axi_wr_state_q(2) and '0';
-- State 3 - Send Data - 0x08
axi_wr_state_ns3_0 <= axi_wr_state_q(3) and '0';
axi_wr_state_ns3_1 <= axi_wr_state_q(3) and '0';
axi_wr_state_ns3_2 <= axi_wr_state_q(3) and '0';
axi_wr_state_ns3_3 <= axi_wr_state_q(3) and '0';
axi_wr_state_ns3_4 <= axi_wr_state_q(3) and '1';
-- State 4 - Wait for BReady - 0x10
axi_wr_state_ns4_0 <= axi_wr_state_q(4) and s0_axi_bready;
axi_wr_state_ns4_1 <= axi_wr_state_q(4) and '0';
axi_wr_state_ns4_2 <= axi_wr_state_q(4) and '0';
axi_wr_state_ns4_3 <= axi_wr_state_q(4) and '0';
axi_wr_state_ns4_4 <= axi_wr_state_q(4) and not s0_axi_bready;
-- Control Outputs
s0_axi_awready <= axi_wr_state_q(1);
s0_axi_wready <= axi_wr_state_q(3);
s0_axi_bvalid <= axi_wr_state_q(4);
s0_axi_bresp <= "00";
-- AXI Data Inputs: s0_axi_awaddr
-- AXI Data Outputs: None
-- Register Control: reg_wr_valid, reg_wr_addr
reg_wr_valid <= axi_wr_state_q(3);
reg_wr_addr_d <= gate(reg_wr_addr_q , not axi_wr_state_q(0)) or
gate(s0_axi_awaddr and x"0003FFFF", axi_wr_state_q(0));
-- Need to delay the write data so it's valid same cycle as reg_wr_valid
s0_axi_wdata_d <= s0_axi_wdata;
-- Next State
axi_wr_state_d(0) <= axi_wr_state_ns0_0 or axi_wr_state_ns1_0 or axi_wr_state_ns2_0 or axi_wr_state_ns3_0 or axi_wr_state_ns4_0;
axi_wr_state_d(1) <= axi_wr_state_ns0_1 or axi_wr_state_ns1_1 or axi_wr_state_ns2_1 or axi_wr_state_ns3_1 or axi_wr_state_ns4_1;
axi_wr_state_d(2) <= axi_wr_state_ns0_2 or axi_wr_state_ns1_2 or axi_wr_state_ns2_2 or axi_wr_state_ns3_2 or axi_wr_state_ns4_2;
axi_wr_state_d(3) <= axi_wr_state_ns0_3 or axi_wr_state_ns1_3 or axi_wr_state_ns2_3 or axi_wr_state_ns3_3 or axi_wr_state_ns4_3;
axi_wr_state_d(4) <= axi_wr_state_ns0_4 or axi_wr_state_ns1_4 or axi_wr_state_ns2_4 or axi_wr_state_ns3_4 or axi_wr_state_ns4_4;
-----------------------------------------------------------------------------
-- Config Registers
-----------------------------------------------------------------------------
s0_axi_rdata(31 downto 0) <= gate(exp_rd_data(31 downto 0), exp_rd_data_valid ) or
gate(reg_00_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#0000#, 32))) or
gate(reg_01_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#0004#, 32))) or
gate(reg_02_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#0070#, 32))) or
gate(reg_03_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#0074#, 32))) or
gate(reg_04_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00B0#, 32))) or
gate(reg_05_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00B4#, 32))) or
gate(reg_06_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00B8#, 32))) or
gate(reg_07_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00BC#, 32))) or
gate(reg_08_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00C0#, 32))) or
gate(reg_09_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00C4#, 32))) or
gate(reg_0A_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00C8#, 32))) or
gate(reg_0B_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00CC#, 32))) or
gate(reg_0C_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00D0#, 32))) or
gate(reg_0D_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00D4#, 32))) or
gate(reg_0E_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00D8#, 32))) or --unused, but better to keep some consistency
gate(reg_0F_q(31 downto 0), not exp_rd_data_valid and reg_rd_valid_q and reg_rd_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00DC#, 32))); --unused, but better to keep some consistency
reg_00_d <= gate(reg_00_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#0000#, 32))) and not reg_00_hwwe_i) or
gate((s0_axi_wdata_q and REG_00_WE_MASK) or (reg_00_q and not REG_00_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#0000#, 32))) and not reg_00_hwwe_i) or
gate((reg_00_update_i and REG_00_HWWE_MASK) or (reg_00_q and (REG_00_STICKY_MASK or not REG_00_HWWE_MASK)), reg_00_hwwe_i);
reg_01_d <= gate(reg_01_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#0004#, 32))) and not reg_01_hwwe_i) or
gate((s0_axi_wdata_q and REG_01_WE_MASK) or (reg_01_q and not REG_01_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#0004#, 32))) and not reg_01_hwwe_i) or
gate((reg_01_update_i and REG_01_HWWE_MASK) or (reg_01_q and (REG_01_STICKY_MASK or not REG_01_HWWE_MASK)), reg_01_hwwe_i);
reg_02_d <= gate(reg_02_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#0070#, 32))) and not reg_02_hwwe_i) or
gate((s0_axi_wdata_q and REG_02_WE_MASK) or (reg_02_q and not REG_02_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#0070#, 32))) and not reg_02_hwwe_i) or
gate((reg_02_update_i and REG_02_HWWE_MASK) or (reg_02_q and (REG_02_STICKY_MASK or not REG_02_HWWE_MASK)), reg_02_hwwe_i);
reg_03_d <= gate(reg_03_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#0074#, 32))) and not reg_03_hwwe_i) or
gate((s0_axi_wdata_q and REG_03_WE_MASK) or (reg_03_q and not REG_03_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#0074#, 32))) and not reg_03_hwwe_i) or
gate((reg_03_update_i and REG_03_HWWE_MASK) or (reg_03_q and (REG_03_STICKY_MASK or not REG_03_HWWE_MASK)), reg_03_hwwe_i);
reg_04_d <= gate(reg_04_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00B0#, 32))) and not reg_04_hwwe_i) or
gate((s0_axi_wdata_q and REG_04_WE_MASK) or (reg_04_q and not REG_04_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00B0#, 32))) and not reg_04_hwwe_i) or
gate((reg_04_update_i and REG_04_HWWE_MASK) or (reg_04_q and (REG_04_STICKY_MASK or not REG_04_HWWE_MASK)), reg_04_hwwe_i);
reg_05_d <= gate(reg_05_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00B4#, 32))) and not reg_05_hwwe_i) or
gate((s0_axi_wdata_q and REG_05_WE_MASK) or (reg_05_q and not REG_05_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00B4#, 32))) and not reg_05_hwwe_i) or
gate((reg_05_update_i and REG_05_HWWE_MASK) or (reg_05_q and (REG_05_STICKY_MASK or not REG_05_HWWE_MASK)), reg_05_hwwe_i);
reg_06_d <= gate(reg_06_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00B8#, 32))) and not reg_06_hwwe_i) or
gate((s0_axi_wdata_q and REG_06_WE_MASK) or (reg_06_q and not REG_06_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00B8#, 32))) and not reg_06_hwwe_i) or
gate((reg_06_update_i and REG_06_HWWE_MASK) or (reg_06_q and (REG_06_STICKY_MASK or not REG_06_HWWE_MASK)), reg_06_hwwe_i);
reg_07_d <= gate(reg_07_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00BC#, 32))) and not reg_07_hwwe_i) or
gate((s0_axi_wdata_q and REG_07_WE_MASK) or (reg_07_q and not REG_07_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00BC#, 32))) and not reg_07_hwwe_i) or
gate((reg_07_update_i and REG_07_HWWE_MASK) or (reg_07_q and (REG_07_STICKY_MASK or not REG_07_HWWE_MASK)), reg_07_hwwe_i);
reg_08_d <= gate(reg_08_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00C0#, 32))) and not reg_08_hwwe_i) or
gate((s0_axi_wdata_q and REG_08_WE_MASK) or (reg_08_q and not REG_08_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00C0#, 32))) and not reg_08_hwwe_i) or
gate((reg_08_update_i and REG_08_HWWE_MASK) or (reg_08_q and (REG_08_STICKY_MASK or not REG_08_HWWE_MASK)), reg_08_hwwe_i);
reg_09_d <= gate(reg_09_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00C4#, 32))) and not reg_09_hwwe_i) or
gate((s0_axi_wdata_q and REG_09_WE_MASK) or (reg_09_q and not REG_09_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00C4#, 32))) and not reg_09_hwwe_i) or
gate((reg_09_update_i and REG_09_HWWE_MASK) or (reg_09_q and (REG_09_STICKY_MASK or not REG_09_HWWE_MASK)), reg_09_hwwe_i);
reg_0A_d <= gate(reg_0A_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00C8#, 32))) and not reg_0A_hwwe_i) or
gate((s0_axi_wdata_q and REG_0A_WE_MASK) or (reg_0A_q and not REG_0A_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00C8#, 32))) and not reg_0A_hwwe_i) or
gate((reg_0A_update_i and REG_0A_HWWE_MASK) or (reg_0A_q and (REG_0A_STICKY_MASK or not REG_0A_HWWE_MASK)), reg_0A_hwwe_i);
reg_0B_d <= gate(reg_0B_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00CC#, 32))) and not reg_0B_hwwe_i) or
gate((s0_axi_wdata_q and REG_0B_WE_MASK) or (reg_0B_q and not REG_0B_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00CC#, 32))) and not reg_0B_hwwe_i) or
gate((reg_0B_update_i and REG_0B_HWWE_MASK) or (reg_0B_q and (REG_0B_STICKY_MASK or not REG_0B_HWWE_MASK)), reg_0B_hwwe_i);
reg_0C_d <= gate(reg_0C_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00D0#, 32))) and not reg_0C_hwwe_i) or
gate((s0_axi_wdata_q and REG_0C_WE_MASK) or (reg_0C_q and not REG_0C_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00D0#, 32))) and not reg_0C_hwwe_i) or
gate((reg_0C_update_i and REG_0C_HWWE_MASK) or (reg_0C_q and (REG_0C_STICKY_MASK or not REG_0C_HWWE_MASK)), reg_0C_hwwe_i);
reg_0D_d <= gate(reg_0D_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00D4#, 32))) and not reg_0D_hwwe_i) or
gate((s0_axi_wdata_q and REG_0D_WE_MASK) or (reg_0D_q and not REG_0D_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00D4#, 32))) and not reg_0D_hwwe_i) or
gate((reg_0D_update_i and REG_0D_HWWE_MASK) or (reg_0D_q and (REG_0D_STICKY_MASK or not REG_0D_HWWE_MASK)), reg_0D_hwwe_i);
reg_0E_d <= gate(reg_0E_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00D8#, 32))) and not reg_0E_hwwe_i) or
gate((s0_axi_wdata_q and REG_0E_WE_MASK) or (reg_0E_q and not REG_0E_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00D8#, 32))) and not reg_0E_hwwe_i) or
gate((reg_0E_update_i and REG_0E_HWWE_MASK) or (reg_0E_q and (REG_0E_STICKY_MASK or not REG_0E_HWWE_MASK)), reg_0E_hwwe_i);
reg_0F_d <= gate(reg_0F_q, not (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00DC#, 32))) and not reg_0F_hwwe_i) or
gate((s0_axi_wdata_q and REG_0F_WE_MASK) or (reg_0F_q and not REG_0F_WE_MASK), (reg_wr_valid and reg_wr_addr_q = std_ulogic_vector(to_unsigned(offset + 16#00DC#, 32))) and not reg_0F_hwwe_i) or
gate((reg_0F_update_i and REG_0F_HWWE_MASK) or (reg_0F_q and (REG_0F_STICKY_MASK or not REG_0F_HWWE_MASK)), reg_0F_hwwe_i);
-- Outputs
reg_00_o <= reg_00_q;
reg_01_o <= reg_01_q;
reg_02_o <= reg_02_q;
reg_03_o <= reg_03_q;
reg_04_o <= reg_04_q;
reg_05_o <= reg_05_q;
reg_06_o <= reg_06_q;
reg_07_o <= reg_07_q;
reg_08_o <= reg_08_q;
reg_09_o <= reg_09_q;
reg_0A_o <= reg_0A_q;
reg_0B_o <= reg_0B_q;
reg_0C_o <= reg_0C_q;
reg_0D_o <= reg_0D_q;
reg_0E_o <= reg_0E_q;
reg_0F_o <= reg_0F_q;
-----------------------------------------------------------------------------
-- Latches
-----------------------------------------------------------------------------
process (s0_axi_aclk) is
begin
if rising_edge(s0_axi_aclk) then
if (s0_axi_aresetn = '0') then
axi_rd_state_q <= "0001";
reg_rd_addr_q <= x"00000000";
axi_wr_state_q <= "00001";
reg_wr_addr_q <= x"00000000";
reg_00_q <= x"00000000";
reg_01_q <= x"00000000";
reg_02_q <= x"00000000";
reg_03_q <= x"00000000";
reg_04_q <= x"00000000";
reg_05_q <= x"00000000";
reg_06_q <= x"00000000";
reg_07_q <= x"00000000";
reg_08_q <= x"00000000";
reg_09_q <= x"00000000";
reg_0A_q <= x"00000000";
reg_0B_q <= x"00000000";
reg_0C_q <= x"00000000";
reg_0D_q <= x"00000000";
reg_0E_q <= x"00000000";
reg_0F_q <= x"00000000";
s0_axi_wdata_q <= x"00000000";
reg_rd_valid_q <= '0';
else
axi_rd_state_q <= axi_rd_state_d;
reg_rd_addr_q <= reg_rd_addr_d;
axi_wr_state_q <= axi_wr_state_d;
reg_wr_addr_q <= reg_wr_addr_d;
reg_00_q <= reg_00_d;
reg_01_q <= reg_01_d;
reg_02_q <= reg_02_d;
reg_03_q <= reg_03_d;
reg_04_q <= reg_04_d;
reg_05_q <= reg_05_d;
reg_06_q <= reg_06_d;
reg_07_q <= reg_07_d;
reg_08_q <= reg_08_d;
reg_09_q <= reg_09_d;
reg_0A_q <= reg_0A_d;
reg_0B_q <= reg_0B_d;
reg_0C_q <= reg_0C_d;
reg_0D_q <= reg_0D_d;
reg_0E_q <= reg_0E_d;
reg_0F_q <= reg_0F_d;
s0_axi_wdata_q <= s0_axi_wdata_d;
reg_rd_valid_q <= reg_rd_valid_d;
end if;
end if;
end process;
end axi_regs_32;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity dft_in_fsm is
port (
reset : in std_logic;
clk : in std_logic;
fifo_data : in std_logic_vector(31 downto 0);
fifo_rd_en : out std_logic;
fifo_rd_count : in std_logic_vector(9 downto 0);
dft_data : out std_logic_vector(31 downto 0);
dft_fd_in : out std_logic;
dft_rffd : in std_logic;
dft_data_valid : in std_logic;
fifo_watchdog_reset : out std_logic
);
end dft_in_fsm;
architecture rtl of dft_in_fsm is
constant data_size : integer := 960;
type fsm is (rst, fifo_dft_wait, dft_sample, dft_out_wait);
signal state : fsm := rst;
signal data_cnt : std_logic_vector(16 downto 0);
signal fifo_cnt_prev : std_logic_vector(9 downto 0);
begin
dft_data <= fifo_data;
process(clk)
begin
if (clk'event and clk = '1') then
case state is
when rst =>
fifo_rd_en <= '1';
dft_fd_in <= '0';
data_cnt <= std_logic_vector(to_unsigned(data_size - 1, data_cnt'length));
state <= fifo_dft_wait;
-- Cekamo popunjavanje FIFO buffera i spremnost DFT-a za prihvat uzoraka
when fifo_dft_wait =>
fifo_rd_en <= '0';
dft_fd_in <= '0';
data_cnt <= std_logic_vector(to_unsigned(data_size - 1, data_cnt'length));
if (to_integer(unsigned(fifo_rd_count)) < data_size) then
state <= fifo_dft_wait;
-- FIFO ima dovoljno uzoraka; Provjeravamo spremnost DFT-a
elsif (dft_rffd = '0') then
state <= fifo_dft_wait;
else
dft_fd_in <= '1';
fifo_rd_en <= '1';
state <= dft_sample;
end if;
-- Prosljedjujemo uzorke DFT-u
when dft_sample =>
dft_fd_in <= '0';
fifo_rd_en <= '1';
data_cnt <= data_cnt;
if (data_cnt /= (data_cnt'range => '0')) then
data_cnt <= data_cnt - '1';
state <= dft_sample;
else
fifo_rd_en <= '0';
state <= dft_out_wait;
end if;
-- Cekamo dok DFT ne izbaci sve uzorke spektra
when dft_out_wait =>
dft_fd_in <= '0';
fifo_rd_en <= '0';
if (dft_data_valid = '1') then
state <= dft_out_wait;
else
state <= fifo_dft_wait;
end if;
when others =>
null;
end case;
if ( reset = '1') then
state <= rst;
end if;
-- Watchdog control signal
if (fifo_rd_count /= fifo_cnt_prev) then
fifo_watchdog_reset <= '1';
fifo_cnt_prev <= fifo_rd_count;
else
fifo_watchdog_reset <= '0';
fifo_cnt_prev <= fifo_cnt_prev;
end if;
end if;
end process;
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FE_Qsys_Simple_HAv8 is
port (
------------------------------------------------------------
-- Avalon Memory Mapped Slave Signals
------------------------------------------------------------
avalon_slave_address : in std_logic_vector(3 downto 0) := (others => '0');
avalon_slave_read : in std_logic := '0';
avalon_slave_write : in std_logic := '0';
avalon_slave_writedata : in std_logic_vector(31 downto 0) := (others => '0');
avalon_slave_readdata : out std_logic_vector(31 downto 0);
------------------------------------------------------------
-- Left Data Channel input
------------------------------------------------------------
data_in_left_data : in std_logic_vector(31 downto 0) := (others => '0');
data_in_left_error : in std_logic_vector(1 downto 0) := (others => '0');
data_in_left_valid : in std_logic := '0';
------------------------------------------------------------
-- Right Data Channel input
------------------------------------------------------------
data_in_right_data : in std_logic_vector(31 downto 0) := (others => '0');
data_in_right_error : in std_logic_vector(1 downto 0) := (others => '0');
data_in_right_valid : in std_logic := '0';
------------------------------------------------------------
-- Left Data Channel outuput
------------------------------------------------------------
data_out_left_data : out std_logic_vector(31 downto 0);
data_out_left_error : out std_logic_vector(1 downto 0);
data_out_left_valid : out std_logic;
------------------------------------------------------------
-- Right Data Channel output
------------------------------------------------------------
data_out_right_data : out std_logic_vector(31 downto 0);
data_out_right_error : out std_logic_vector(1 downto 0);
data_out_right_valid : out std_logic;
------------------------------------------------------------
-- Clocks and Resets
------------------------------------------------------------
sys_reset_n : in std_logic := '0';
sys_clk : in std_logic := '0';
audio_pll_clk : in std_logic := '0' -- Must be 12.288 MHz
);
end entity FE_Qsys_Simple_HAv8;
architecture rtl of FE_Qsys_Simple_HAv8 is
component HA_LR is
port( clk : in std_logic;
reset : in std_logic;
clk_enable : in std_logic;
HA_left_data_in : in std_logic_vector(31 downto 0); -- sfix32_En28
Gain_B4_left : in std_logic_vector(31 downto 0); -- sfix32_En16
Gain_B3_left : in std_logic_vector(31 downto 0); -- sfix32_En16
Gain_B2_left : in std_logic_vector(31 downto 0); -- sfix32_En16
Gain_B1_left : in std_logic_vector(31 downto 0); -- sfix32_En16
Gain_all_left : in std_logic_vector(31 downto 0); -- sfix32_En16
HA_right_data_in : in std_logic_vector(31 downto 0); -- sfix32_En28
Gain_B4_right : in std_logic_vector(31 downto 0); -- sfix32_En16
Gain_B3_right : in std_logic_vector(31 downto 0); -- sfix32_En16
Gain_B2_right : in std_logic_vector(31 downto 0); -- sfix32_En16
Gain_B1_right : in std_logic_vector(31 downto 0); -- sfix32_En16
Gain_all_right : in std_logic_vector(31 downto 0); -- sfix32_En16
ce_out : out std_logic;
HA_left_data_out : out std_logic_vector(31 downto 0); -- sfix32_En28
HA_right_data_out : out std_logic_vector(31 downto 0) -- sfix32_En28
);
end component;
component FE_Qsys_HA_Simple_Gainv8 is
port (
clk : in std_logic;
reset_n : in std_logic;
------------------------------------------------------------
-- Avalon Memory Mapped Slave Signals
------------------------------------------------------------
avs_s1_address : in std_logic_vector( 3 downto 0);
avs_s1_write : in std_logic;
avs_s1_writedata : in std_logic_vector(31 downto 0);
avs_s1_read : in std_logic;
avs_s1_readdata : out std_logic_vector(31 downto 0);
------------------------------------------------------------
-- Left And Right Gain Signals
------------------------------------------------------------
band1_gain_left : out std_logic_vector(31 downto 0);
band2_gain_left : out std_logic_vector(31 downto 0);
band3_gain_left : out std_logic_vector(31 downto 0);
band4_gain_left : out std_logic_vector(31 downto 0);
gain_all_left : out std_logic_vector(31 downto 0);
band1_gain_right : out std_logic_vector(31 downto 0);
band2_gain_right : out std_logic_vector(31 downto 0);
band3_gain_right : out std_logic_vector(31 downto 0);
band4_gain_right : out std_logic_vector(31 downto 0);
gain_all_right : out std_logic_vector(31 downto 0)
);
end component;
------------------------------------------------------------------
-- input signal mappings
------------------------------------------------------------------
signal data_in_left_data_r : std_logic_vector(31 downto 0);
signal data_in_right_data_r : std_logic_vector(31 downto 0);
signal data_out_left_data_r : std_logic_vector(31 downto 0);
signal data_out_right_data_r : std_logic_vector(31 downto 0);
signal data_out_left_data_r_exp : std_logic_vector(31 downto 0);
signal data_out_right_data_r_exp : std_logic_vector(31 downto 0);
------------------------------------------------------------------
-- HA_DRC signals
------------------------------------------------------------------
signal band1_gain_left_r : std_logic_vector(31 downto 0);
signal band2_gain_left_r : std_logic_vector(31 downto 0);
signal band3_gain_left_r : std_logic_vector(31 downto 0);
signal band4_gain_left_r : std_logic_vector(31 downto 0);
signal gain_all_left_r : std_logic_vector(31 downto 0);
signal band1_gain_right_r : std_logic_vector(31 downto 0);
signal band2_gain_right_r : std_logic_vector(31 downto 0);
signal band3_gain_right_r : std_logic_vector(31 downto 0);
signal band4_gain_right_r : std_logic_vector(31 downto 0);
signal gain_all_right_r : std_logic_vector(31 downto 0);
------------------------------------------------------------------
-- Clock Divider Signals
------------------------------------------------------------------
signal audio_clk_counter : unsigned(6 downto 0);
signal HA_clk : std_logic;
begin
u_HA: HA_LR port map (
clk => HA_clk,
reset => not sys_reset_n,
clk_enable => '1',
HA_left_data_in => data_in_left_data_r,
Gain_B4_left => band4_gain_left_r,
Gain_B3_left => band3_gain_left_r,
Gain_B2_left => band2_gain_left_r,
Gain_B1_left => band1_gain_left_r,
Gain_all_left => gain_all_left_r,
HA_right_data_in => data_in_right_data_r,
Gain_B4_right => band4_gain_right_r,
Gain_B3_right => band3_gain_right_r,
Gain_B2_right => band2_gain_right_r,
Gain_B1_right => band1_gain_right_r,
Gain_all_right => gain_all_right_r,
ce_out => open,
HA_left_data_out => data_out_left_data_r,
HA_right_data_out => data_out_right_data_r
);
u_DRC: FE_Qsys_HA_Simple_Gainv8 port map (
clk => sys_clk,
reset_n => sys_reset_n,
avs_s1_address => avalon_slave_address,
avs_s1_write => avalon_slave_write,
avs_s1_writedata => avalon_slave_writedata,
avs_s1_read => avalon_slave_read,
avs_s1_readdata => avalon_slave_readdata,
band1_gain_left => band1_gain_left_r,
band2_gain_left => band2_gain_left_r,
band3_gain_left => band3_gain_left_r,
band4_gain_left => band4_gain_left_r,
gain_all_left => gain_all_left_r,
band1_gain_right => band1_gain_right_r,
band2_gain_right => band2_gain_right_r,
band3_gain_right => band3_gain_right_r,
band4_gain_right => band4_gain_right_r,
gain_all_right => gain_all_right_r
);
---------------------------------------------------------------------
-- Data in process
---------------------------------------------------------------------
process(sys_clk)
begin
if (rising_edge(sys_clk)) then
if (data_in_left_valid = '1') then
data_in_left_data_r <= data_in_left_data;
elsif (data_in_right_valid = '1') then
data_in_right_data_r <= data_in_right_data;
end if; -- valid signals
end if; -- rising clock
end process;
-------------------------------------------------------------
-- Clock Divider Process
-------------------------------------------------------------
process(sys_reset_n, audio_pll_clk)
begin
if sys_reset_n = '0' then
audio_clk_counter <= (others => '0');
elsif rising_edge(audio_pll_clk) then
audio_clk_counter <= audio_clk_counter + 1;
end if;
end process;
---------------------------------------------------------------------
-- Audio Clock Mapping
---------------------------------------------------------------------
HA_clk <= audio_clk_counter(3);
---------------------------------------------------------------------
-- Experimental division
---------------------------------------------------------------------
-- process(sys_clk)
-- begin
-- if (rising_edge(sys_clk)) then
-- if (data_out_left_data_r(31) = '1') then
-- data_out_left_data_r_exp <= "1" & data_out_left_data_r(31 downto 1);
-- else
-- data_out_left_data_r_exp <= "0" & data_out_left_data_r(31 downto 1);
-- end if;
-- if (data_out_right_data_r(31) = '1') then
-- data_out_right_data_r_exp <= "1" & data_out_right_data_r(31 downto 1);
-- else
-- data_out_right_data_r_exp <= "0" & data_out_right_data_r(31 downto 1);
-- end if;
-- end if;
-- end process;
---------------------------------------------------------------------
-- Data out mapping
-- Note: This follows the previous project mapping conventions
---------------------------------------------------------------------
data_out_left_data <= data_out_left_data_r;
data_out_left_valid <= data_in_left_valid;
data_out_left_error <= data_in_left_error;
data_out_right_data <= data_out_right_data_r;
data_out_right_valid <= data_in_right_valid;
data_out_right_error <= data_in_right_error;
end architecture rtl;
|
<filename>dt2/exam2/vhdl/fifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
port(rst : in std_ulogic;
clk : in std_ulogic;
fifo_in : in std_ulogic_vector (31 downto 0);
fifo_wr : in std_ulogic;
fifo_rd : in std_ulogic;
fifo_out : out std_ulogic_vector (31 downto 0);
fifo_out_valid : out std_ulogic;
fifo_empty : out std_ulogic;
fifo_full : out std_ulogic);
end entity fifo;
architecture rtl of fifo is
type t_mem is array(0 to 15) of std_ulogic_vector(31 downto 0);
signal wr_ptr : unsigned(3 downto 0);
signal rd_ptr : unsigned(3 downto 0);
signal level : unsigned(4 downto 0);
signal mem : t_mem;
signal fifo_empty_i : std_ulogic;
signal fifo_full_i : std_ulogic;
begin
p_wr_ptr : process(rst, clk)
begin
if rst = '1' then
wr_ptr <= (others => '0');
elsif rising_edge(clk) then
if fifo_wr = '1' and fifo_full_i = '0' then
wr_ptr <= wr_ptr+1;
end if;
end if;
end process p_wr_ptr;
p_rd_ptr : process(rst, clk)
begin
if rst = '1' then
rd_ptr <= (others => '0');
elsif rising_edge(clk) then
if fifo_rd = '1' and fifo_empty_i = '0' then
rd_ptr <= rd_ptr+1;
end if;
end if;
end process p_rd_ptr;
p_level : process(rst, clk)
begin
if rst = '1' then
level <= (others => '0');
elsif rising_edge(clk) then
if fifo_wr = '1' and fifo_full_i = '0' and fifo_rd = '0' then
level <= level+1;
elsif fifo_wr = '0' and fifo_rd = '1' and fifo_empty_i = '0' then
level <= level-1;
end if;
end if;
end process p_level;
-- status:
fifo_empty_i <= '1' when level = 0 else '0';
fifo_full_i <= '1' when level = 16 else '0';
fifo_empty <= fifo_empty_i;
fifo_full <= fifo_full_i;
p_write : process(rst, clk)
begin
if rst = '1' then
mem <= (others => (others => '0'));
elsif rising_edge(clk) then
if fifo_wr = '1' and fifo_full_i = '0' then
mem(to_integer(wr_ptr)) <= fifo_in;
end if;
end if;
end process p_write;
p_read : process(rst, clk)
begin
if rst = '1' then
fifo_out <= (others => '0');
fifo_out_valid <= '0';
elsif rising_edge(clk) then
if fifo_rd = '1' and fifo_empty_i = '0' then
fifo_out <= mem(to_integer(rd_ptr));
end if;
fifo_out_valid <= fifo_rd;
end if;
end process p_read;
end architecture rtl;
|
-------------------------------------------------------------------------------
-- Title : Test pattern generator
-- Project : NoC testbench generator
-------------------------------------------------------------------------------
-- File : traffic_gen.vhd
-- Author : <NAME> <<EMAIL>>
-- Company : University of Bremen
-------------------------------------------------------------------------------
-- Copyright (c) 2019
-------------------------------------------------------------------------------
-- Vesion : 1.9.0
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.NOC_3D_PACKAGE.all;
entity traffic_gen is
generic(
flit_width : positive := flit_size;
router_credit : integer := 4;
srl_fifo_depth : integer := 200;
inj_time_text : string := "injection_time.txt";
packet_length_text : string := "packet_length.txt";
image_2_flits_text : string := "data_header.txt";
inj_time_2_noc_text : string := "inj_time_2_noc.txt"
);
port(
clk, rst: in std_logic := '0';
valid: out std_logic := '0';
incr: in std_logic := '0';
data_out: out flit := (others => '0')
);
end entity;
architecture behave of traffic_gen is
component srl_fifo is
generic ( buffer_depth : integer := srl_fifo_depth );
port(
data_in : in flit;
data_out : out flit;
rst : in std_logic;
write_en : in std_logic;
read_en : in std_logic;
buffer_full : out std_logic;
buffer_empty : out std_logic;
clk : in std_logic
);
end component;
signal data_in : flit := (others => '0');
signal data_out_rsl_fifo : flit;
signal credit: integer := router_credit;
signal valid_signal : std_logic := '0';
signal temp_inj_time : natural;
signal temp_packet_length : natural := 0;
signal counter: natural := 0;
signal write_en : std_logic := '0';
signal buffer_full : std_logic := '0';
signal buffer_empty : std_logic := '1';
-- Used text files
file inj_time : text open read_mode is inj_time_text;
file packet_length : text open read_mode is packet_length_text;
file image_2_flits : text open read_mode is image_2_flits_text;
file inj_time_2_noc : text open write_mode is inj_time_2_noc_text;
constant clk_period: time := 1000 ns;
begin
-------------------------------------------------------------------
------------------ internal buffer component ----------------------
int_buffer: entity work.srl_fifo
generic map ( buffer_depth => srl_fifo_depth)
port map (
data_in => data_in,
data_out => data_out_rsl_fifo,
rst => rst,
write_en => write_en,
read_en => valid_signal,
buffer_full => buffer_full,
buffer_empty => buffer_empty,
clk => clk);
-------------------------------------------------------------------
----------- Read text files into the internal buffer --------------
read_packet_length: process
variable input_line : line;
variable next_data_packet_length: natural;
variable next_inj_time: natural;
variable next_data_flit: flit;
begin
wait until ((rst = not(RST_LVL)) and rising_edge(clk)); -- set reset for design
while not (endfile(packet_length)) loop
write_en <= '0';
readline(packet_length, input_line);
read(input_line, next_data_packet_length);
temp_packet_length <= next_data_packet_length;
readline(inj_time, input_line);
read(input_line, next_inj_time);
temp_inj_time <= next_inj_time;
wait until (counter = temp_inj_time - 1) and rising_edge(clk);
-- Send Data into internal Buffer
for i in 0 to (temp_packet_length - 1) loop
readline(image_2_flits, input_line);
read(input_line, next_data_flit);
data_in <= next_data_flit;
write_en <= '1';
wait until rising_edge(clk);
end loop;
end loop;
-- Put zeros after the whole message tranmission
if endfile(packet_length) then
write_en <= '0';
data_in <= (others => '0');
end if;
end process;
-------------------------------------------------------------------
------------------------- Clk counter -----------------------------
clk_counter: process(clk)
begin
if (rising_edge(clk)) then
if (rst = RST_LVL) then
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
-------------------------------------------------------------------
------------------------ Credit counter ---------------------------
credit_counter: process(clk, rst)
begin
if (rising_edge(clk)) then
if (rst = RST_LVL) then
credit <= router_credit ;
else
if ((credit > 0) and valid_signal = '1' and incr = '0') then
credit <= credit - 1;
elsif ((credit < router_credit) and valid_signal = '0' and incr = '1') then
credit <= credit + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
---------------------- Determine valid flag -----------------------
data_out <= data_out_rsl_fifo;
valid_flag: process(buffer_empty, credit, incr)
begin
if ( buffer_empty = '0' and (( credit > 0) or (incr = '1'))) then
valid <= '1';
valid_signal <= '1';
else
valid <= '0';
valid_signal <= '0';
end if;
end process;
-------------------------------------------------------------------
------------------- Save injection time to NoC --------------------
write_inj_time: process(clk, rst)
variable rowOut: line;
variable data_time: time := 0 ns;
begin
if clk = '1' and clk'event and rst = not(RST_LVL) then
if (valid_signal = '1') then
data_time := now - clk_period;
write(rowOut, data_time);
writeline(inj_time_2_noc, rowOut);
end if;
end if;
end process;
--------------------------------------------------------------------
-------------------------------------------------------------------
end architecture;
|
<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY VGA IS
PORT(
CLOCK_50: IN STD_LOGIC; --SYSTEM CLOCK
VGA_HS, VGA_VS: OUT STD_LOGIC; -- HORIZONTAL AND VERTICAL SYNCRONIZATION
VGA_R, VGA_G, VGA_B: OUT STD_LOGIC_VECTOR(7 downto 0); -- COLORS
VGA_CLOCK: OUT STD_LOGIC; -- VGA CLOCK OUT
PS2_CLK: IN STD_LOGIC;
PS2_DATA: IN STD_LOGIC;
d_right : out std_logic_vector(0 to 6) := "1111111";
d_left : out std_logic_vector(0 to 6):= "1111111"
);
END VGA;
ARCHITECTURE MAIN OF VGA IS
SIGNAL VGACLK, RESET: STD_LOGIC := '0';
SIGNAL ASCII_PS2: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ASCII: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL disp_right : std_logic_vector(0 to 6);
SIGNAL disp_left : std_logic_vector(0 to 6);
-- PLL
COMPONENT PLL IS
PORT(
CLK_IN_CLK: IN STD_LOGIC := 'X'; --CLK
RESET_RESET: IN STD_LOGIC := 'X'; --RESET
CLK_OUT_CLK: OUT STD_LOGIC
);
END COMPONENT PLL;
-- SYNC
COMPONENT SYNC IS
PORT(
CLK: IN STD_LOGIC; --PLL
HSYNC, VSYNC: OUT STD_LOGIC;
R, G, B: OUT STD_LOGIC_VECTOR(7 downto 0);
ASCII: IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT SYNC;
-- KEYBOARD COMPONENT
COMPONENT keyboard IS
PORT(
clk_keyboard: IN STD_LOGIC; -- Pin used to emulate the clk_keyboard cycles
data: IN STD_LOGIC; -- Pin used for data input
ASCII: out std_logic_vector(7 downto 0);
display_right : out std_logic_vector(0 to 6);
display_left : out std_logic_vector(0 to 6)
);
END COMPONENT keyboard;
BEGIN
C1: SYNC PORT MAP(VGACLK, VGA_HS, VGA_VS, VGA_R, VGA_G, VGA_B, ASCII);
C2: PLL PORT MAP(CLOCK_50, RESET, VGACLK);
C3: keyboard PORT MAP(PS2_CLK, PS2_DATA, ASCII_PS2,disp_right,disp_left);
ASCII <= ASCII_PS2(7 DOWNTO 0);
VGA_CLOCK <= VGACLK;
d_right <= disp_right(0 TO 6);
d_left <= disp_left(0 to 6);
END MAIN;
|
<filename>part2/pgcd/vhdl/pgcd.vhd
-- Listing 5.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pgcd is
port( clk: in std_logic;
m: in unsigned(7 downto 0);
n: in unsigned(7 downto 0);
r: out unsigned(7 downto 0);
start: in std_logic;
rdy: out std_logic;
rst: in std_logic
);
end pgcd;
architecture rtl of pgcd is
type t_state is (Repos, Calcul);
signal etat: t_state;
signal a, b: unsigned(7 downto 0);
begin
process(rst, clk)
begin
if (rst='1') then
etat <= Repos;
rdy <= '1';
elsif rising_edge(clk) then
case etat is
when Repos =>
if (start='1') then
a <= m;
b <= n;
etat <= Calcul;
rdy <= '0';
end if;
when Calcul =>
if ( a = b ) then
r <= a;
rdy <= '1';
etat <= Repos;
elsif ( a > b ) then
a <= a-b;
else
b <= b-a;
end if;
end case;
end if;
end process;
end architecture;
architecture rtl2 of pgcd is
-- Variante avec la sortie [rdy] associee a l'etat
type t_state is (Repos, Calcul);
signal etat: t_state;
signal a, b: unsigned(7 downto 0);
begin
P1: process(rst, clk)
begin
if (rst='1') then
etat <= Repos;
elsif rising_edge(clk) then
case etat is
when Repos =>
if (start='1') then
a <= m;
b <= n;
etat <= Calcul;
end if;
when Calcul =>
if ( a = b ) then
r <= a;
etat <= Repos;
elsif ( a > b ) then
a <= a-b;
else
b <= b-a;
end if;
end case;
end if;
end process;
P2: process (etat)
begin
case etat is
when Repos => rdy <= '1';
when Calcul => rdy <= '0';
end case;
end process;
end architecture;
|
<gh_stars>1-10
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE ieee.std_logic_unsigned.all;
entity soft_max is
port(
rst : in std_logic;
clk : in std_logic;
input_x : in std_logic_vector(15 downto 0);
input_x_trig : in std_logic;
soft_max_done : out std_logic;
------------------------------------------------------------
class_value : in std_logic_vector(3 downto 0);
class_accuracy : out std_logic_vector(15 downto 0)
);
end soft_max;
architecture des of soft_max is
component exp_x is
port(
clk : in std_logic;
input_x : in std_logic_vector(15 downto 0);
output_exp_x: out std_logic_vector(15 downto 0)
);
end component;
component FPadd_single_b IS
PORT(
ADD_SUB : IN std_logic;
FP_A : IN std_logic_vector (15 DOWNTO 0);
FP_B : IN std_logic_vector (15 DOWNTO 0);
FPadd_single_b_en : IN std_logic;
FP_Z : OUT std_logic_vector (15 DOWNTO 0)
);
end component;
component FPdiv_b is
port (
FP_A: in std_logic_vector(15 downto 0);
FP_B: in std_logic_vector(15 downto 0);
FPdiv_b_en : IN std_logic;
FP_Z: out std_logic_vector(15 downto 0)
);
end component;
component bf16_to_fixed is
port (
bf16_in : in std_logic_vector(15 downto 0);
fxd_out : out std_logic_vector(15 downto 0) -- signed(7.9)
);
end component;
constant percentage_of_acc : std_logic_vector(15 downto 0):=X"C600";
signal input_x_trig_s :std_logic:='0';
signal soft_max_done_s :std_logic:='0';
signal exp_x_output :std_logic_vector(15 downto 0):=(others=>'0');
signal num_inp_class :std_logic_vector(3 downto 0):="0000";
signal num_oup_class :std_logic_vector(3 downto 0):="0000";
type arr is array(0 to 10) of std_logic_vector(15 downto 0);
signal exp_x_op_array :arr;
signal softmx_acc_array :arr;
type state_type is (s_0,s_1,s_2,s_3,s_4,s_5,s_6,s_7,s_8);
signal class_sel: state_type;
signal FPadd_a_in :std_logic_vector(15 downto 0):=(others=>'0');
signal FPadd_b_in :std_logic_vector(15 downto 0):=(others=>'0');
signal FPadd_op :std_logic_vector(15 downto 0):=(others=>'0');
signal FPadd_en :std_logic:='0';
signal FPdiv_a_in :std_logic_vector(15 downto 0):=(others=>'0');
signal FPdiv_b_in :std_logic_vector(15 downto 0):=(others=>'0');
signal FPdiv_op :std_logic_vector(15 downto 0):=(others=>'0');
signal FPdiv_en :std_logic:='0';
signal bf_to_fxd_in :std_logic_vector(15 downto 0):=(others=>'0');
signal softmax_acc_out :std_logic_vector(15 downto 0):=(others=>'0');
signal temp_acc_out :std_logic_vector(31 downto 0):=(others=>'0');
begin
process(clk,rst)
begin
if rst='0' then input_x_trig_s <= '0';
elsif rising_edge(clk) then
input_x_trig_s <= input_x_trig;
end if;
end process;
I0: exp_x
port map (
clk => clk,
input_x => input_x,
output_exp_x => exp_x_output
);
process(input_x_trig_s,rst,num_inp_class)
begin
if (rst='0' or num_inp_class = "1011") then num_inp_class <= "0000";
elsif rising_edge(input_x_trig_s) then
num_inp_class <= num_inp_class + 1;
exp_x_op_array(to_integer(unsigned(num_inp_class))) <= exp_x_output;
end if;
end process;
process(clk,rst,input_x_trig_s,exp_x_output)
begin
if rst='0' then class_sel <= s_0;
elsif rising_edge(clk) then
case class_sel is
when s_0 =>
if input_x_trig_s = '1' then
num_inp_class <= "0001";
exp_x_op_array(0) <= exp_x_output;
FPadd_a_in <= exp_x_output;
FPadd_b_in <= x"0000";
FPadd_en <= '1';
class_sel <= s_3;
else
num_inp_class <= "0000";
class_sel <= s_0;
end if;
when s_1 =>
if input_x_trig_s = '1' then
num_inp_class <= num_inp_class + 1;
exp_x_op_array(to_integer(unsigned(num_inp_class))) <= exp_x_output;
FPadd_a_in <= exp_x_output;
FPadd_b_in <= FPadd_op;
FPadd_en <= '1';
class_sel <= s_2;
else
class_sel <= s_1;
end if;
when s_2 =>
if (num_inp_class < "1011") then
class_sel <= s_3;
elsif (num_inp_class = "1011") then
num_inp_class <= "0000";
num_oup_class <= "0000";
FPdiv_b_in <= FPadd_op;
class_sel <= s_4;
end if;
when s_3 =>
if input_x_trig_s = '0' then
class_sel <= s_1;
else
class_sel <= s_3;
end if;
when s_4 =>
FPadd_en <= '0';
FPdiv_en <= '0';
if (num_oup_class < "1011") then
FPdiv_a_in <= exp_x_op_array(to_integer(unsigned(num_oup_class)));
class_sel <= s_5;
elsif (num_oup_class = "1011") then
num_oup_class <= "0000";
class_sel <= s_0;
soft_max_done_s <= '1';
end if;
when s_5 =>
FPdiv_en <= '1';
class_sel <= s_6;
when s_6 =>
FPdiv_en <= '0';
bf_to_fxd_in <= FPdiv_op;
class_sel <= s_7;
when s_7 =>
temp_acc_out <= softmax_acc_out * percentage_of_acc;
class_sel <= s_8;
when s_8 =>
if (num_oup_class < "1011") then
softmx_acc_array(to_integer(unsigned(num_oup_class))) <= temp_acc_out(24 downto 9);
num_oup_class <= num_oup_class + 1;
class_sel <= s_4;
end if;
when others => null;
end case;
end if;
end process;
I1: FPadd_single_b
PORT MAP (
ADD_SUB => '1',
FP_A => FPadd_a_in,
FP_B => FPadd_b_in,
FPadd_single_b_en => FPadd_en,
FP_Z => FPadd_op
);
I2: FPdiv_b
PORT MAP (
FP_A => FPdiv_a_in,
FP_B => FPdiv_b_in,
FPdiv_b_en => FPdiv_en,
FP_Z => FPdiv_op
);
I3: bf16_to_fixed
PORT MAP (
bf16_in => bf_to_fxd_in,
fxd_out => softmax_acc_out
);
process(soft_max_done_s,class_value,softmx_acc_array)
begin
if (soft_max_done_s = '1' and class_value < "1011") then
class_accuracy <= softmx_acc_array(to_integer(unsigned(class_value)));
end if;
end process;
soft_max_done <= soft_max_done_s;
end des;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:34:12 02/09/2014
-- Design Name:
-- Module Name: dac2_error_computation - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This computes the desired setpoint for dac1's output equal to halfway between the minimum and the maximum,
-- and then computes the error signal as the offset between this setpoint and the current dac1 value.
-- There is a little bit of bitgrowth (1 more bit on the error output than on the inpuut values) to make sure that there is no wrapping in the arithmetic.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dac2_error_computation is
Generic (
N_BITS_DAC1 : integer := 16
);
Port ( clk : in STD_LOGIC;
dac1_minimum : in STD_LOGIC_VECTOR (N_BITS_DAC1-1 downto 0);
dac1_maximum : in STD_LOGIC_VECTOR (N_BITS_DAC1-1 downto 0);
dac1_current : in STD_LOGIC_VECTOR (N_BITS_DAC1-1 downto 0);
flip_error_sign : in std_logic;
dac1_error : out STD_LOGIC_VECTOR (N_BITS_DAC1+1-1 downto 0));
end dac2_error_computation;
architecture Behavioral of dac2_error_computation is
signal dac1_desired_setpoint_times_two : signed(N_BITS_DAC1+1-1 downto 0) := (others => '0');
signal dac1_desired_setpoint : signed(N_BITS_DAC1+1-1 downto 0) := (others => '0');
signal dac1_error_internal : signed(N_BITS_DAC1+1-1 downto 0) := (others => '0');
signal dac1_error_internal2 : signed(N_BITS_DAC1+1-1 downto 0) := (others => '0');
begin
process (clk)
begin
if rising_edge(clk) then
-- computes the average of dac1's maximum and minimum's value:
-- this incurs a bit growth of two, which we cancel in the next assignement
dac1_desired_setpoint_times_two <= resize(signed(dac1_minimum), N_BITS_DAC1+1)
+ resize(signed(dac1_maximum), N_BITS_DAC1+1);
-- there is no bitgrowth on this value as we simply divide the sum by two.
-- we keep the signal as N_BITS_DAC1+1 however to prevent overflow of the next computation.
dac1_desired_setpoint <= shift_right( dac1_desired_setpoint_times_two, 1);
-- computes the error as the subtraction between the computed setpoint and the current value or the opposite sign.
if flip_error_sign = '1' then
dac1_error_internal <= dac1_desired_setpoint - resize(signed(dac1_current), N_BITS_DAC1+1);
else
dac1_error_internal <= resize(signed(dac1_current), N_BITS_DAC1+1) - dac1_desired_setpoint;
end if;
-- Extra register stage to make the timing easy to achieve.
dac1_error_internal2 <= dac1_error_internal;
end if;
end process;
dac1_error <= std_logic_vector(dac1_error_internal2);
end Behavioral;
|
<reponame>acostillado/bitonic_network
-------------------------------------------------------------------------------
-- Company : Barcelona Supercomputing Center (BSC)
-- Engineer : <NAME>
-- *******************************************************************
-- File : Bitonic_Network.vhd
-- Author : $Autor: <EMAIL> $
-- Date : $Date: 2021-05-06 $
-- Revisions : $Revision: $
-- Last update: 2021-05-18
-- *******************************************************************
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Bitonic Network. Top file. It instantiates two stages:
-- 1) Sort Random elements in a Bitonic sequence
-- 2) Sort a Bitonic sequence
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_misc.all;
use IEEE.NUMERIC_STD.all;
use std.textio.all;
use ieee.std_logic_textio.all;
library work;
use work.Bitonic_Network_pkg.all;
entity Bitonic_Network is
generic(
G_NETWORK_INPUTS : integer := 8;
G_ELEMENT_WIDTH : integer := 64;
G_ENABLE_PIPE : integer := 1
);
port(
CLK : in std_logic;
CTRL_EN : in std_logic;
CTRL : in std_logic_vector(C_NCOMP-1 downto 0);
RES : out std_logic_vector(C_NCOMP-1 downto 0);
ENABLE : in std_logic;
VALID : out std_logic;
RANDOM_IN : in t_network_array(0 to G_NETWORK_INPUTS-1);
SORTED_OUT : out t_network_array(0 to G_NETWORK_INPUTS-1)
);
end Bitonic_Network;
-------------------------------------------------------------------------------
-- Arch
-- Not using components anymore but using direct entity instantiation
-------------------------------------------------------------------------------
architecture RTL of Bitonic_Network is
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type t_network_matrix is array (C_PIPE_CYCLES-1 downto 0) of t_network_array(0 to G_NETWORK_INPUTS-1);
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal s_element_bitonic : t_network_array(0 to G_NETWORK_INPUTS-1);
signal s_element_sorted : t_network_array(0 to G_NETWORK_INPUTS-1);
signal s_element_sorted_r : t_network_matrix;
signal valid_r : std_logic_vector(C_PIPE_CYCLES-1 downto 0) := (others => '0'); --
-- In case retiming is desired:
--attribute retiming_backward : integer;
--attribute retiming_backward of s_element_sorted_r : signal is 1;
begin -- architecture RTL
-----------------------------------------------------------------------------
-- Sorting network (8 elements)
-----------------------------------------------------------------------------
Inst_bitonicSort : entity work.bitonicSort
generic map (
G_ENABLE_PIPE => G_ENABLE_PIPE
)
port map (
CLK => CLK,
CTRL_EN => CTRL_EN,
CTRL => CTRL(C_NCOMP/2-1 downto 0),
RES => RES(C_NCOMP/2-1 downto 0),
RANDOM_IN => RANDOM_IN,
BITONIC_OUT => s_element_bitonic
);
Inst_bitonicMerge : entity work.bitonicMerge
generic map (
G_ENABLE_PIPE => G_ENABLE_PIPE
)
port map (
CLK => CLK,
CTRL_EN => CTRL_EN,
CTRL => CTRL(C_NCOMP-1 downto C_NCOMP/2),
RES => RES(C_NCOMP-1 downto C_NCOMP/2),
BITONIC_IN => s_element_bitonic,
SORTED_OUT => SORTED_OUT
);
-- reg valid
GEN_PIPE_VALID : if G_ENABLE_PIPE = 1 generate
REG_OUT : process(CLK)
begin
if rising_edge(CLK) then
valid_r <= valid_r(C_PIPE_CYCLES-2 downto 0) & ENABLE;
-- s_element_sorted_r <= s_element_sorted_r(C_PIPE_CYCLES-2 downto 0) &
-- s_element_sorted; -- In case retiming is desired
end if;
end process;
VALID <= valid_r(valid_r'left);
end generate GEN_PIPE_VALID;
GEN_VALID : if G_ENABLE_PIPE = 0 generate
VALID <= ENABLE;
end generate GEN_VALID;
-----------------------------------------------------------------------------
-- Outputs
-----------------------------------------------------------------------------
-- SORTED_OUT <= s_element_sorted_r(s_element_sorted_r'left); -- for retiming
end architecture RTL;
|
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.2.2 (lin64) Build 3118627 Tue Feb 9 05:13:49 MST 2021
-- Date : Wed Mar 16 11:25:13 2022
-- Host : ubuntu3 running 64-bit Ubuntu 20.04.3 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/willychiang/Desktop/PYNQ_Composable_Pipeline/boards/Pynq-Z2/cv_dfx_4_pr/cv_dfx_4_pr.gen/sources_1/bd/video_cp/ip/video_cp_dfx_decoupler_pr_0_0/video_cp_dfx_decoupler_pr_0_0_sim_netlist.vhdl
-- Design : video_cp_dfx_decoupler_pr_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
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<KEY>
`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity video_cp_dfx_decoupler_pr_0_0 is
port (
s_in_0_TVALID : in STD_LOGIC;
rp_in_0_TVALID : out STD_LOGIC;
s_in_0_TREADY : out STD_LOGIC;
rp_in_0_TREADY : in STD_LOGIC;
s_in_0_TDATA : in STD_LOGIC_VECTOR ( 23 downto 0 );
rp_in_0_TDATA : out STD_LOGIC_VECTOR ( 23 downto 0 );
s_in_0_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
rp_in_0_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
s_in_0_TLAST : in STD_LOGIC;
rp_in_0_TLAST : out STD_LOGIC;
s_in_1_TVALID : in STD_LOGIC;
rp_in_1_TVALID : out STD_LOGIC;
s_in_1_TREADY : out STD_LOGIC;
rp_in_1_TREADY : in STD_LOGIC;
s_in_1_TDATA : in STD_LOGIC_VECTOR ( 23 downto 0 );
rp_in_1_TDATA : out STD_LOGIC_VECTOR ( 23 downto 0 );
s_in_1_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
rp_in_1_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
s_in_1_TLAST : in STD_LOGIC;
rp_in_1_TLAST : out STD_LOGIC;
s_out_0_TVALID : out STD_LOGIC;
rp_out_0_TVALID : in STD_LOGIC;
s_out_0_TREADY : in STD_LOGIC;
rp_out_0_TREADY : out STD_LOGIC;
s_out_0_TDATA : out STD_LOGIC_VECTOR ( 23 downto 0 );
rp_out_0_TDATA : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_out_0_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
rp_out_0_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
s_out_0_TLAST : out STD_LOGIC;
rp_out_0_TLAST : in STD_LOGIC;
s_out_0_TID : out STD_LOGIC_VECTOR ( 0 to 0 );
rp_out_0_TID : in STD_LOGIC_VECTOR ( 0 to 0 );
s_out_0_TDEST : out STD_LOGIC_VECTOR ( 0 to 0 );
rp_out_0_TDEST : in STD_LOGIC_VECTOR ( 0 to 0 );
s_out_1_TVALID : out STD_LOGIC;
rp_out_1_TVALID : in STD_LOGIC;
s_out_1_TREADY : in STD_LOGIC;
rp_out_1_TREADY : out STD_LOGIC;
s_out_1_TDATA : out STD_LOGIC_VECTOR ( 23 downto 0 );
rp_out_1_TDATA : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_out_1_TUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
rp_out_1_TUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
s_out_1_TLAST : out STD_LOGIC;
rp_out_1_TLAST : in STD_LOGIC;
s_out_1_TID : out STD_LOGIC_VECTOR ( 0 to 0 );
rp_out_1_TID : in STD_LOGIC_VECTOR ( 0 to 0 );
s_out_1_TDEST : out STD_LOGIC_VECTOR ( 0 to 0 );
rp_out_1_TDEST : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_lite0_ARVALID : out STD_LOGIC;
rp_axi_lite0_ARVALID : in STD_LOGIC;
s_axi_lite0_ARREADY : in STD_LOGIC;
rp_axi_lite0_ARREADY : out STD_LOGIC;
s_axi_lite0_AWVALID : out STD_LOGIC;
rp_axi_lite0_AWVALID : in STD_LOGIC;
s_axi_lite0_AWREADY : in STD_LOGIC;
rp_axi_lite0_AWREADY : out STD_LOGIC;
s_axi_lite0_BVALID : in STD_LOGIC;
rp_axi_lite0_BVALID : out STD_LOGIC;
s_axi_lite0_BREADY : out STD_LOGIC;
rp_axi_lite0_BREADY : in STD_LOGIC;
s_axi_lite0_RVALID : in STD_LOGIC;
rp_axi_lite0_RVALID : out STD_LOGIC;
s_axi_lite0_RREADY : out STD_LOGIC;
rp_axi_lite0_RREADY : in STD_LOGIC;
s_axi_lite0_WVALID : out STD_LOGIC;
rp_axi_lite0_WVALID : in STD_LOGIC;
s_axi_lite0_WREADY : in STD_LOGIC;
rp_axi_lite0_WREADY : out STD_LOGIC;
s_axi_lite0_AWADDR : out STD_LOGIC_VECTOR ( 30 downto 0 );
rp_axi_lite0_AWADDR : in STD_LOGIC_VECTOR ( 30 downto 0 );
s_axi_lite0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
rp_axi_lite0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_lite0_AWREGION : out STD_LOGIC_VECTOR ( 3 downto 0 );
rp_axi_lite0_AWREGION : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_lite0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
rp_axi_lite0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_lite0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
rp_axi_lite0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
rp_axi_lite0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_lite0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
rp_axi_lite0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite0_ARADDR : out STD_LOGIC_VECTOR ( 30 downto 0 );
rp_axi_lite0_ARADDR : in STD_LOGIC_VECTOR ( 30 downto 0 );
s_axi_lite0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
rp_axi_lite0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_lite0_ARREGION : out STD_LOGIC_VECTOR ( 3 downto 0 );
rp_axi_lite0_ARREGION : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_lite0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
rp_axi_lite0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_lite0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
rp_axi_lite0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
rp_axi_lite0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite1_ARVALID : out STD_LOGIC;
rp_axi_lite1_ARVALID : in STD_LOGIC;
s_axi_lite1_ARREADY : in STD_LOGIC;
rp_axi_lite1_ARREADY : out STD_LOGIC;
s_axi_lite1_AWVALID : out STD_LOGIC;
rp_axi_lite1_AWVALID : in STD_LOGIC;
s_axi_lite1_AWREADY : in STD_LOGIC;
rp_axi_lite1_AWREADY : out STD_LOGIC;
s_axi_lite1_BVALID : in STD_LOGIC;
rp_axi_lite1_BVALID : out STD_LOGIC;
s_axi_lite1_BREADY : out STD_LOGIC;
rp_axi_lite1_BREADY : in STD_LOGIC;
s_axi_lite1_RVALID : in STD_LOGIC;
rp_axi_lite1_RVALID : out STD_LOGIC;
s_axi_lite1_RREADY : out STD_LOGIC;
rp_axi_lite1_RREADY : in STD_LOGIC;
s_axi_lite1_WVALID : out STD_LOGIC;
rp_axi_lite1_WVALID : in STD_LOGIC;
s_axi_lite1_WREADY : in STD_LOGIC;
rp_axi_lite1_WREADY : out STD_LOGIC;
s_axi_lite1_AWADDR : out STD_LOGIC_VECTOR ( 30 downto 0 );
rp_axi_lite1_AWADDR : in STD_LOGIC_VECTOR ( 30 downto 0 );
s_axi_lite1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
rp_axi_lite1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_lite1_AWREGION : out STD_LOGIC_VECTOR ( 3 downto 0 );
rp_axi_lite1_AWREGION : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_lite1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
rp_axi_lite1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_lite1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
rp_axi_lite1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
rp_axi_lite1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_lite1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
rp_axi_lite1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite1_ARADDR : out STD_LOGIC_VECTOR ( 30 downto 0 );
rp_axi_lite1_ARADDR : in STD_LOGIC_VECTOR ( 30 downto 0 );
s_axi_lite1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
rp_axi_lite1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_lite1_ARREGION : out STD_LOGIC_VECTOR ( 3 downto 0 );
rp_axi_lite1_ARREGION : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_lite1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
rp_axi_lite1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_lite1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
rp_axi_lite1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
rp_axi_lite1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
decouple : in STD_LOGIC;
decouple_status : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of video_cp_dfx_decoupler_pr_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of video_cp_dfx_decoupler_pr_0_0 : entity is "video_cp_dfx_decoupler_pr_0_0,dfx_decoupler_video_cp_dfx_decoupler_pr_0_0,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of video_cp_dfx_decoupler_pr_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of video_cp_dfx_decoupler_pr_0_0 : entity is "dfx_decoupler_video_cp_dfx_decoupler_pr_0_0,Vivado 2020.2.2";
end video_cp_dfx_decoupler_pr_0_0;
architecture STRUCTURE of video_cp_dfx_decoupler_pr_0_0 is
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute is_du_within_envelope : string;
attribute is_du_within_envelope of U0 : label is "true";
attribute x_interface_info : string;
attribute x_interface_info of rp_axi_lite0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 ARREADY";
attribute x_interface_info of rp_axi_lite0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 ARVALID";
attribute x_interface_parameter : string;
attribute x_interface_parameter of rp_axi_lite0_ARVALID : signal is "XIL_INTERFACENAME rp_axi_lite0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 142857132, ID_WIDTH 0, ADDR_WIDTH 31, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN video_cp_ps7_0_0_FCLK_CLK1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, MISC.CLK_REQUIRED FALSE";
attribute x_interface_info of rp_axi_lite0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 AWREADY";
attribute x_interface_info of rp_axi_lite0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 AWVALID";
attribute x_interface_info of rp_axi_lite0_BREADY : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 BREADY";
attribute x_interface_info of rp_axi_lite0_BVALID : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 BVALID";
attribute x_interface_info of rp_axi_lite0_RREADY : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 RREADY";
attribute x_interface_info of rp_axi_lite0_RVALID : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 RVALID";
attribute x_interface_info of rp_axi_lite0_WREADY : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 WREADY";
attribute x_interface_info of rp_axi_lite0_WVALID : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 WVALID";
attribute x_interface_info of rp_axi_lite1_ARREADY : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 ARREADY";
attribute x_interface_info of rp_axi_lite1_ARVALID : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 ARVALID";
attribute x_interface_parameter of rp_axi_lite1_ARVALID : signal is "XIL_INTERFACENAME rp_axi_lite1, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 142857132, ID_WIDTH 0, ADDR_WIDTH 31, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN video_cp_ps7_0_0_FCLK_CLK1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, MISC.CLK_REQUIRED FALSE";
attribute x_interface_info of rp_axi_lite1_AWREADY : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 AWREADY";
attribute x_interface_info of rp_axi_lite1_AWVALID : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 AWVALID";
attribute x_interface_info of rp_axi_lite1_BREADY : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 BREADY";
attribute x_interface_info of rp_axi_lite1_BVALID : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 BVALID";
attribute x_interface_info of rp_axi_lite1_RREADY : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 RREADY";
attribute x_interface_info of rp_axi_lite1_RVALID : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 RVALID";
attribute x_interface_info of rp_axi_lite1_WREADY : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 WREADY";
attribute x_interface_info of rp_axi_lite1_WVALID : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 WVALID";
attribute x_interface_info of rp_in_0_TLAST : signal is "xilinx.com:interface:axis:1.0 rp_in_0 TLAST";
attribute x_interface_info of rp_in_0_TREADY : signal is "xilinx.com:interface:axis:1.0 rp_in_0 TREADY";
attribute x_interface_info of rp_in_0_TVALID : signal is "xilinx.com:interface:axis:1.0 rp_in_0 TVALID";
attribute x_interface_parameter of rp_in_0_TVALID : signal is "XIL_INTERFACENAME rp_in_0, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 142857132, PHASE 0.000, CLK_DOMAIN video_cp_ps7_0_0_FCLK_CLK1, LAYERED_METADATA undef, INSERT_VIP 0, MISC.CLK_REQUIRED FALSE";
attribute x_interface_info of rp_in_1_TLAST : signal is "xilinx.com:interface:axis:1.0 rp_in_1 TLAST";
attribute x_interface_info of rp_in_1_TREADY : signal is "xilinx.com:interface:axis:1.0 rp_in_1 TREADY";
attribute x_interface_info of rp_in_1_TVALID : signal is "xilinx.com:interface:axis:1.0 rp_in_1 TVALID";
attribute x_interface_parameter of rp_in_1_TVALID : signal is "XIL_INTERFACENAME rp_in_1, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 142857132, PHASE 0.000, CLK_DOMAIN video_cp_ps7_0_0_FCLK_CLK1, LAYERED_METADATA undef, INSERT_VIP 0, MISC.CLK_REQUIRED FALSE";
attribute x_interface_info of rp_out_0_TLAST : signal is "xilinx.com:interface:axis:1.0 rp_out_0 TLAST";
attribute x_interface_info of rp_out_0_TREADY : signal is "xilinx.com:interface:axis:1.0 rp_out_0 TREADY";
attribute x_interface_info of rp_out_0_TVALID : signal is "xilinx.com:interface:axis:1.0 rp_out_0 TVALID";
attribute x_interface_parameter of rp_out_0_TVALID : signal is "XIL_INTERFACENAME rp_out_0, TDATA_NUM_BYTES 3, TDEST_WIDTH 1, TID_WIDTH 1, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 142857132, PHASE 0.000, CLK_DOMAIN video_cp_ps7_0_0_FCLK_CLK1, LAYERED_METADATA undef, INSERT_VIP 0, MISC.CLK_REQUIRED FALSE";
attribute x_interface_info of rp_out_1_TLAST : signal is "xilinx.com:interface:axis:1.0 rp_out_1 TLAST";
attribute x_interface_info of rp_out_1_TREADY : signal is "xilinx.com:interface:axis:1.0 rp_out_1 TREADY";
attribute x_interface_info of rp_out_1_TVALID : signal is "xilinx.com:interface:axis:1.0 rp_out_1 TVALID";
attribute x_interface_parameter of rp_out_1_TVALID : signal is "XIL_INTERFACENAME rp_out_1, TDATA_NUM_BYTES 3, TDEST_WIDTH 1, TID_WIDTH 1, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 142857132, PHASE 0.000, CLK_DOMAIN video_cp_ps7_0_0_FCLK_CLK1, LAYERED_METADATA undef, INSERT_VIP 0, MISC.CLK_REQUIRED FALSE";
attribute x_interface_info of s_axi_lite0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 ARREADY";
attribute x_interface_info of s_axi_lite0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 ARVALID";
attribute x_interface_parameter of s_axi_lite0_ARVALID : signal is "XIL_INTERFACENAME s_axi_lite0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 142857132, ID_WIDTH 0, ADDR_WIDTH 31, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN video_cp_ps7_0_0_FCLK_CLK1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, MISC.CLK_REQUIRED FALSE";
attribute x_interface_info of s_axi_lite0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 AWREADY";
attribute x_interface_info of s_axi_lite0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 AWVALID";
attribute x_interface_info of s_axi_lite0_BREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 BREADY";
attribute x_interface_info of s_axi_lite0_BVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 BVALID";
attribute x_interface_info of s_axi_lite0_RREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 RREADY";
attribute x_interface_info of s_axi_lite0_RVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 RVALID";
attribute x_interface_info of s_axi_lite0_WREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 WREADY";
attribute x_interface_info of s_axi_lite0_WVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 WVALID";
attribute x_interface_info of s_axi_lite1_ARREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 ARREADY";
attribute x_interface_info of s_axi_lite1_ARVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 ARVALID";
attribute x_interface_parameter of s_axi_lite1_ARVALID : signal is "XIL_INTERFACENAME s_axi_lite1, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 142857132, ID_WIDTH 0, ADDR_WIDTH 31, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN video_cp_ps7_0_0_FCLK_CLK1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, MISC.CLK_REQUIRED FALSE";
attribute x_interface_info of s_axi_lite1_AWREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 AWREADY";
attribute x_interface_info of s_axi_lite1_AWVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 AWVALID";
attribute x_interface_info of s_axi_lite1_BREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 BREADY";
attribute x_interface_info of s_axi_lite1_BVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 BVALID";
attribute x_interface_info of s_axi_lite1_RREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 RREADY";
attribute x_interface_info of s_axi_lite1_RVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 RVALID";
attribute x_interface_info of s_axi_lite1_WREADY : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 WREADY";
attribute x_interface_info of s_axi_lite1_WVALID : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 WVALID";
attribute x_interface_info of s_in_0_TLAST : signal is "xilinx.com:interface:axis:1.0 s_in_0 TLAST";
attribute x_interface_info of s_in_0_TREADY : signal is "xilinx.com:interface:axis:1.0 s_in_0 TREADY";
attribute x_interface_info of s_in_0_TVALID : signal is "xilinx.com:interface:axis:1.0 s_in_0 TVALID";
attribute x_interface_parameter of s_in_0_TVALID : signal is "XIL_INTERFACENAME s_in_0, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 142857132, PHASE 0.000, CLK_DOMAIN video_cp_ps7_0_0_FCLK_CLK1, LAYERED_METADATA undef, INSERT_VIP 0, MISC.CLK_REQUIRED FALSE";
attribute x_interface_info of s_in_1_TLAST : signal is "xilinx.com:interface:axis:1.0 s_in_1 TLAST";
attribute x_interface_info of s_in_1_TREADY : signal is "xilinx.com:interface:axis:1.0 s_in_1 TREADY";
attribute x_interface_info of s_in_1_TVALID : signal is "xilinx.com:interface:axis:1.0 s_in_1 TVALID";
attribute x_interface_parameter of s_in_1_TVALID : signal is "XIL_INTERFACENAME s_in_1, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 142857132, PHASE 0.000, CLK_DOMAIN video_cp_ps7_0_0_FCLK_CLK1, LAYERED_METADATA undef, INSERT_VIP 0, MISC.CLK_REQUIRED FALSE";
attribute x_interface_info of s_out_0_TLAST : signal is "xilinx.com:interface:axis:1.0 s_out_0 TLAST";
attribute x_interface_info of s_out_0_TREADY : signal is "xilinx.com:interface:axis:1.0 s_out_0 TREADY";
attribute x_interface_info of s_out_0_TVALID : signal is "xilinx.com:interface:axis:1.0 s_out_0 TVALID";
attribute x_interface_parameter of s_out_0_TVALID : signal is "XIL_INTERFACENAME s_out_0, TDATA_NUM_BYTES 3, TDEST_WIDTH 1, TID_WIDTH 1, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 142857132, PHASE 0.000, CLK_DOMAIN video_cp_ps7_0_0_FCLK_CLK1, LAYERED_METADATA undef, INSERT_VIP 0, MISC.CLK_REQUIRED FALSE";
attribute x_interface_info of s_out_1_TLAST : signal is "xilinx.com:interface:axis:1.0 s_out_1 TLAST";
attribute x_interface_info of s_out_1_TREADY : signal is "xilinx.com:interface:axis:1.0 s_out_1 TREADY";
attribute x_interface_info of s_out_1_TVALID : signal is "xilinx.com:interface:axis:1.0 s_out_1 TVALID";
attribute x_interface_parameter of s_out_1_TVALID : signal is "XIL_INTERFACENAME s_out_1, TDATA_NUM_BYTES 3, TDEST_WIDTH 1, TID_WIDTH 1, TUSER_WIDTH 1, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 142857132, PHASE 0.000, CLK_DOMAIN video_cp_ps7_0_0_FCLK_CLK1, LAYERED_METADATA undef, INSERT_VIP 0, MISC.CLK_REQUIRED FALSE";
attribute x_interface_info of rp_axi_lite0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 ARADDR";
attribute x_interface_info of rp_axi_lite0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 ARPROT";
attribute x_interface_info of rp_axi_lite0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 ARQOS";
attribute x_interface_info of rp_axi_lite0_ARREGION : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 ARREGION";
attribute x_interface_info of rp_axi_lite0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 AWADDR";
attribute x_interface_info of rp_axi_lite0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 AWPROT";
attribute x_interface_info of rp_axi_lite0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 AWQOS";
attribute x_interface_info of rp_axi_lite0_AWREGION : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 AWREGION";
attribute x_interface_info of rp_axi_lite0_BRESP : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 BRESP";
attribute x_interface_info of rp_axi_lite0_RDATA : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 RDATA";
attribute x_interface_info of rp_axi_lite0_RRESP : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 RRESP";
attribute x_interface_info of rp_axi_lite0_WDATA : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 WDATA";
attribute x_interface_info of rp_axi_lite0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite0 WSTRB";
attribute x_interface_info of rp_axi_lite1_ARADDR : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 ARADDR";
attribute x_interface_info of rp_axi_lite1_ARPROT : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 ARPROT";
attribute x_interface_info of rp_axi_lite1_ARQOS : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 ARQOS";
attribute x_interface_info of rp_axi_lite1_ARREGION : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 ARREGION";
attribute x_interface_info of rp_axi_lite1_AWADDR : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 AWADDR";
attribute x_interface_info of rp_axi_lite1_AWPROT : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 AWPROT";
attribute x_interface_info of rp_axi_lite1_AWQOS : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 AWQOS";
attribute x_interface_info of rp_axi_lite1_AWREGION : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 AWREGION";
attribute x_interface_info of rp_axi_lite1_BRESP : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 BRESP";
attribute x_interface_info of rp_axi_lite1_RDATA : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 RDATA";
attribute x_interface_info of rp_axi_lite1_RRESP : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 RRESP";
attribute x_interface_info of rp_axi_lite1_WDATA : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 WDATA";
attribute x_interface_info of rp_axi_lite1_WSTRB : signal is "xilinx.com:interface:aximm:1.0 rp_axi_lite1 WSTRB";
attribute x_interface_info of rp_in_0_TDATA : signal is "xilinx.com:interface:axis:1.0 rp_in_0 TDATA";
attribute x_interface_info of rp_in_0_TUSER : signal is "xilinx.com:interface:axis:1.0 rp_in_0 TUSER";
attribute x_interface_info of rp_in_1_TDATA : signal is "xilinx.com:interface:axis:1.0 rp_in_1 TDATA";
attribute x_interface_info of rp_in_1_TUSER : signal is "xilinx.com:interface:axis:1.0 rp_in_1 TUSER";
attribute x_interface_info of rp_out_0_TDATA : signal is "xilinx.com:interface:axis:1.0 rp_out_0 TDATA";
attribute x_interface_info of rp_out_0_TDEST : signal is "xilinx.com:interface:axis:1.0 rp_out_0 TDEST";
attribute x_interface_info of rp_out_0_TID : signal is "xilinx.com:interface:axis:1.0 rp_out_0 TID";
attribute x_interface_info of rp_out_0_TUSER : signal is "xilinx.com:interface:axis:1.0 rp_out_0 TUSER";
attribute x_interface_info of rp_out_1_TDATA : signal is "xilinx.com:interface:axis:1.0 rp_out_1 TDATA";
attribute x_interface_info of rp_out_1_TDEST : signal is "xilinx.com:interface:axis:1.0 rp_out_1 TDEST";
attribute x_interface_info of rp_out_1_TID : signal is "xilinx.com:interface:axis:1.0 rp_out_1 TID";
attribute x_interface_info of rp_out_1_TUSER : signal is "xilinx.com:interface:axis:1.0 rp_out_1 TUSER";
attribute x_interface_info of s_axi_lite0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 ARADDR";
attribute x_interface_info of s_axi_lite0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 ARPROT";
attribute x_interface_info of s_axi_lite0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 ARQOS";
attribute x_interface_info of s_axi_lite0_ARREGION : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 ARREGION";
attribute x_interface_info of s_axi_lite0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 AWADDR";
attribute x_interface_info of s_axi_lite0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 AWPROT";
attribute x_interface_info of s_axi_lite0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 AWQOS";
attribute x_interface_info of s_axi_lite0_AWREGION : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 AWREGION";
attribute x_interface_info of s_axi_lite0_BRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 BRESP";
attribute x_interface_info of s_axi_lite0_RDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 RDATA";
attribute x_interface_info of s_axi_lite0_RRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 RRESP";
attribute x_interface_info of s_axi_lite0_WDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 WDATA";
attribute x_interface_info of s_axi_lite0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite0 WSTRB";
attribute x_interface_info of s_axi_lite1_ARADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 ARADDR";
attribute x_interface_info of s_axi_lite1_ARPROT : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 ARPROT";
attribute x_interface_info of s_axi_lite1_ARQOS : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 ARQOS";
attribute x_interface_info of s_axi_lite1_ARREGION : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 ARREGION";
attribute x_interface_info of s_axi_lite1_AWADDR : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 AWADDR";
attribute x_interface_info of s_axi_lite1_AWPROT : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 AWPROT";
attribute x_interface_info of s_axi_lite1_AWQOS : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 AWQOS";
attribute x_interface_info of s_axi_lite1_AWREGION : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 AWREGION";
attribute x_interface_info of s_axi_lite1_BRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 BRESP";
attribute x_interface_info of s_axi_lite1_RDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 RDATA";
attribute x_interface_info of s_axi_lite1_RRESP : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 RRESP";
attribute x_interface_info of s_axi_lite1_WDATA : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 WDATA";
attribute x_interface_info of s_axi_lite1_WSTRB : signal is "xilinx.com:interface:aximm:1.0 s_axi_lite1 WSTRB";
attribute x_interface_info of s_in_0_TDATA : signal is "xilinx.com:interface:axis:1.0 s_in_0 TDATA";
attribute x_interface_info of s_in_0_TUSER : signal is "xilinx.com:interface:axis:1.0 s_in_0 TUSER";
attribute x_interface_info of s_in_1_TDATA : signal is "xilinx.com:interface:axis:1.0 s_in_1 TDATA";
attribute x_interface_info of s_in_1_TUSER : signal is "xilinx.com:interface:axis:1.0 s_in_1 TUSER";
attribute x_interface_info of s_out_0_TDATA : signal is "xilinx.com:interface:axis:1.0 s_out_0 TDATA";
attribute x_interface_info of s_out_0_TDEST : signal is "xilinx.com:interface:axis:1.0 s_out_0 TDEST";
attribute x_interface_info of s_out_0_TID : signal is "xilinx.com:interface:axis:1.0 s_out_0 TID";
attribute x_interface_info of s_out_0_TUSER : signal is "xilinx.com:interface:axis:1.0 s_out_0 TUSER";
attribute x_interface_info of s_out_1_TDATA : signal is "xilinx.com:interface:axis:1.0 s_out_1 TDATA";
attribute x_interface_info of s_out_1_TDEST : signal is "xilinx.com:interface:axis:1.0 s_out_1 TDEST";
attribute x_interface_info of s_out_1_TID : signal is "xilinx.com:interface:axis:1.0 s_out_1 TID";
attribute x_interface_info of s_out_1_TUSER : signal is "xilinx.com:interface:axis:1.0 s_out_1 TUSER";
begin
U0: entity work.video_cp_dfx_decoupler_pr_0_0_dfx_decoupler_video_cp_dfx_decoupler_pr_0_0
port map (
decouple => decouple,
decouple_status => decouple_status,
rp_axi_lite0_ARADDR(30 downto 0) => rp_axi_lite0_ARADDR(30 downto 0),
rp_axi_lite0_ARPROT(2 downto 0) => rp_axi_lite0_ARPROT(2 downto 0),
rp_axi_lite0_ARQOS(3 downto 0) => rp_axi_lite0_ARQOS(3 downto 0),
rp_axi_lite0_ARREADY => rp_axi_lite0_ARREADY,
rp_axi_lite0_ARREGION(3 downto 0) => rp_axi_lite0_ARREGION(3 downto 0),
rp_axi_lite0_ARVALID => rp_axi_lite0_ARVALID,
rp_axi_lite0_AWADDR(30 downto 0) => rp_axi_lite0_AWADDR(30 downto 0),
rp_axi_lite0_AWPROT(2 downto 0) => rp_axi_lite0_AWPROT(2 downto 0),
rp_axi_lite0_AWQOS(3 downto 0) => rp_axi_lite0_AWQOS(3 downto 0),
rp_axi_lite0_AWREADY => rp_axi_lite0_AWREADY,
rp_axi_lite0_AWREGION(3 downto 0) => rp_axi_lite0_AWREGION(3 downto 0),
rp_axi_lite0_AWVALID => rp_axi_lite0_AWVALID,
rp_axi_lite0_BREADY => rp_axi_lite0_BREADY,
rp_axi_lite0_BRESP(1 downto 0) => rp_axi_lite0_BRESP(1 downto 0),
rp_axi_lite0_BVALID => rp_axi_lite0_BVALID,
rp_axi_lite0_RDATA(31 downto 0) => rp_axi_lite0_RDATA(31 downto 0),
rp_axi_lite0_RREADY => rp_axi_lite0_RREADY,
rp_axi_lite0_RRESP(1 downto 0) => rp_axi_lite0_RRESP(1 downto 0),
rp_axi_lite0_RVALID => rp_axi_lite0_RVALID,
rp_axi_lite0_WDATA(31 downto 0) => rp_axi_lite0_WDATA(31 downto 0),
rp_axi_lite0_WREADY => rp_axi_lite0_WREADY,
rp_axi_lite0_WSTRB(3 downto 0) => rp_axi_lite0_WSTRB(3 downto 0),
rp_axi_lite0_WVALID => rp_axi_lite0_WVALID,
rp_axi_lite1_ARADDR(30 downto 0) => rp_axi_lite1_ARADDR(30 downto 0),
rp_axi_lite1_ARPROT(2 downto 0) => rp_axi_lite1_ARPROT(2 downto 0),
rp_axi_lite1_ARQOS(3 downto 0) => rp_axi_lite1_ARQOS(3 downto 0),
rp_axi_lite1_ARREADY => rp_axi_lite1_ARREADY,
rp_axi_lite1_ARREGION(3 downto 0) => rp_axi_lite1_ARREGION(3 downto 0),
rp_axi_lite1_ARVALID => rp_axi_lite1_ARVALID,
rp_axi_lite1_AWADDR(30 downto 0) => rp_axi_lite1_AWADDR(30 downto 0),
rp_axi_lite1_AWPROT(2 downto 0) => rp_axi_lite1_AWPROT(2 downto 0),
rp_axi_lite1_AWQOS(3 downto 0) => rp_axi_lite1_AWQOS(3 downto 0),
rp_axi_lite1_AWREADY => rp_axi_lite1_AWREADY,
rp_axi_lite1_AWREGION(3 downto 0) => rp_axi_lite1_AWREGION(3 downto 0),
rp_axi_lite1_AWVALID => rp_axi_lite1_AWVALID,
rp_axi_lite1_BREADY => rp_axi_lite1_BREADY,
rp_axi_lite1_BRESP(1 downto 0) => rp_axi_lite1_BRESP(1 downto 0),
rp_axi_lite1_BVALID => rp_axi_lite1_BVALID,
rp_axi_lite1_RDATA(31 downto 0) => rp_axi_lite1_RDATA(31 downto 0),
rp_axi_lite1_RREADY => rp_axi_lite1_RREADY,
rp_axi_lite1_RRESP(1 downto 0) => rp_axi_lite1_RRESP(1 downto 0),
rp_axi_lite1_RVALID => rp_axi_lite1_RVALID,
rp_axi_lite1_WDATA(31 downto 0) => rp_axi_lite1_WDATA(31 downto 0),
rp_axi_lite1_WREADY => rp_axi_lite1_WREADY,
rp_axi_lite1_WSTRB(3 downto 0) => rp_axi_lite1_WSTRB(3 downto 0),
rp_axi_lite1_WVALID => rp_axi_lite1_WVALID,
rp_in_0_TDATA(23 downto 0) => rp_in_0_TDATA(23 downto 0),
rp_in_0_TLAST => rp_in_0_TLAST,
rp_in_0_TREADY => rp_in_0_TREADY,
rp_in_0_TUSER(0) => rp_in_0_TUSER(0),
rp_in_0_TVALID => rp_in_0_TVALID,
rp_in_1_TDATA(23 downto 0) => rp_in_1_TDATA(23 downto 0),
rp_in_1_TLAST => rp_in_1_TLAST,
rp_in_1_TREADY => rp_in_1_TREADY,
rp_in_1_TUSER(0) => rp_in_1_TUSER(0),
rp_in_1_TVALID => rp_in_1_TVALID,
rp_out_0_TDATA(23 downto 0) => rp_out_0_TDATA(23 downto 0),
rp_out_0_TDEST(0) => rp_out_0_TDEST(0),
rp_out_0_TID(0) => rp_out_0_TID(0),
rp_out_0_TLAST => rp_out_0_TLAST,
rp_out_0_TREADY => rp_out_0_TREADY,
rp_out_0_TUSER(0) => rp_out_0_TUSER(0),
rp_out_0_TVALID => rp_out_0_TVALID,
rp_out_1_TDATA(23 downto 0) => rp_out_1_TDATA(23 downto 0),
rp_out_1_TDEST(0) => rp_out_1_TDEST(0),
rp_out_1_TID(0) => rp_out_1_TID(0),
rp_out_1_TLAST => rp_out_1_TLAST,
rp_out_1_TREADY => rp_out_1_TREADY,
rp_out_1_TUSER(0) => rp_out_1_TUSER(0),
rp_out_1_TVALID => rp_out_1_TVALID,
s_axi_lite0_ARADDR(30 downto 0) => s_axi_lite0_ARADDR(30 downto 0),
s_axi_lite0_ARPROT(2 downto 0) => s_axi_lite0_ARPROT(2 downto 0),
s_axi_lite0_ARQOS(3 downto 0) => s_axi_lite0_ARQOS(3 downto 0),
s_axi_lite0_ARREADY => s_axi_lite0_ARREADY,
s_axi_lite0_ARREGION(3 downto 0) => s_axi_lite0_ARREGION(3 downto 0),
s_axi_lite0_ARVALID => s_axi_lite0_ARVALID,
s_axi_lite0_AWADDR(30 downto 0) => s_axi_lite0_AWADDR(30 downto 0),
s_axi_lite0_AWPROT(2 downto 0) => s_axi_lite0_AWPROT(2 downto 0),
s_axi_lite0_AWQOS(3 downto 0) => s_axi_lite0_AWQOS(3 downto 0),
s_axi_lite0_AWREADY => s_axi_lite0_AWREADY,
s_axi_lite0_AWREGION(3 downto 0) => s_axi_lite0_AWREGION(3 downto 0),
s_axi_lite0_AWVALID => s_axi_lite0_AWVALID,
s_axi_lite0_BREADY => s_axi_lite0_BREADY,
s_axi_lite0_BRESP(1 downto 0) => s_axi_lite0_BRESP(1 downto 0),
s_axi_lite0_BVALID => s_axi_lite0_BVALID,
s_axi_lite0_RDATA(31 downto 0) => s_axi_lite0_RDATA(31 downto 0),
s_axi_lite0_RREADY => s_axi_lite0_RREADY,
s_axi_lite0_RRESP(1 downto 0) => s_axi_lite0_RRESP(1 downto 0),
s_axi_lite0_RVALID => s_axi_lite0_RVALID,
s_axi_lite0_WDATA(31 downto 0) => s_axi_lite0_WDATA(31 downto 0),
s_axi_lite0_WREADY => s_axi_lite0_WREADY,
s_axi_lite0_WSTRB(3 downto 0) => s_axi_lite0_WSTRB(3 downto 0),
s_axi_lite0_WVALID => s_axi_lite0_WVALID,
s_axi_lite1_ARADDR(30 downto 0) => s_axi_lite1_ARADDR(30 downto 0),
s_axi_lite1_ARPROT(2 downto 0) => s_axi_lite1_ARPROT(2 downto 0),
s_axi_lite1_ARQOS(3 downto 0) => s_axi_lite1_ARQOS(3 downto 0),
s_axi_lite1_ARREADY => s_axi_lite1_ARREADY,
s_axi_lite1_ARREGION(3 downto 0) => s_axi_lite1_ARREGION(3 downto 0),
s_axi_lite1_ARVALID => s_axi_lite1_ARVALID,
s_axi_lite1_AWADDR(30 downto 0) => s_axi_lite1_AWADDR(30 downto 0),
s_axi_lite1_AWPROT(2 downto 0) => s_axi_lite1_AWPROT(2 downto 0),
s_axi_lite1_AWQOS(3 downto 0) => s_axi_lite1_AWQOS(3 downto 0),
s_axi_lite1_AWREADY => s_axi_lite1_AWREADY,
s_axi_lite1_AWREGION(3 downto 0) => s_axi_lite1_AWREGION(3 downto 0),
s_axi_lite1_AWVALID => s_axi_lite1_AWVALID,
s_axi_lite1_BREADY => s_axi_lite1_BREADY,
s_axi_lite1_BRESP(1 downto 0) => s_axi_lite1_BRESP(1 downto 0),
s_axi_lite1_BVALID => s_axi_lite1_BVALID,
s_axi_lite1_RDATA(31 downto 0) => s_axi_lite1_RDATA(31 downto 0),
s_axi_lite1_RREADY => s_axi_lite1_RREADY,
s_axi_lite1_RRESP(1 downto 0) => s_axi_lite1_RRESP(1 downto 0),
s_axi_lite1_RVALID => s_axi_lite1_RVALID,
s_axi_lite1_WDATA(31 downto 0) => s_axi_lite1_WDATA(31 downto 0),
s_axi_lite1_WREADY => s_axi_lite1_WREADY,
s_axi_lite1_WSTRB(3 downto 0) => s_axi_lite1_WSTRB(3 downto 0),
s_axi_lite1_WVALID => s_axi_lite1_WVALID,
s_in_0_TDATA(23 downto 0) => s_in_0_TDATA(23 downto 0),
s_in_0_TLAST => s_in_0_TLAST,
s_in_0_TREADY => s_in_0_TREADY,
s_in_0_TUSER(0) => s_in_0_TUSER(0),
s_in_0_TVALID => s_in_0_TVALID,
s_in_1_TDATA(23 downto 0) => s_in_1_TDATA(23 downto 0),
s_in_1_TLAST => s_in_1_TLAST,
s_in_1_TREADY => s_in_1_TREADY,
s_in_1_TUSER(0) => s_in_1_TUSER(0),
s_in_1_TVALID => s_in_1_TVALID,
s_out_0_TDATA(23 downto 0) => s_out_0_TDATA(23 downto 0),
s_out_0_TDEST(0) => s_out_0_TDEST(0),
s_out_0_TID(0) => s_out_0_TID(0),
s_out_0_TLAST => s_out_0_TLAST,
s_out_0_TREADY => s_out_0_TREADY,
s_out_0_TUSER(0) => s_out_0_TUSER(0),
s_out_0_TVALID => s_out_0_TVALID,
s_out_1_TDATA(23 downto 0) => s_out_1_TDATA(23 downto 0),
s_out_1_TDEST(0) => s_out_1_TDEST(0),
s_out_1_TID(0) => s_out_1_TID(0),
s_out_1_TLAST => s_out_1_TLAST,
s_out_1_TREADY => s_out_1_TREADY,
s_out_1_TUSER(0) => s_out_1_TUSER(0),
s_out_1_TVALID => s_out_1_TVALID
);
end STRUCTURE;
|
<reponame>julianfl0w/openStreamHDL<gh_stars>10-100
----------------------------------------------------------------------------------
-- Engineer: <NAME> 3/2020
----------------------------------------------------------------------------------
Library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.NUMERIC_STD.All;
Use ieee.math_real.All;
Library work;
Use work.spectral_pkg.All;
Library IEEE_PROPOSED;
Use IEEE_PROPOSED.FIXED_PKG.All;
Library UNISIM;
Use UNISIM.vcomponents.All;
Library UNIMACRO;
Use UNIMACRO.vcomponents.All;
Library work;
Use work.spectral_pkg.All;
Library ieee_proposed;
Use ieee_proposed.fixed_pkg.All;
Use ieee_proposed.fixed_float_types.All;
Entity spectral_engine Is
Generic (
USE_MLMM : Integer := 1;
NOTE_COUNT : Integer := 1024;
PROCESS_BW : Integer := 18;
CTRL_COUNT : Integer := 4;
CHANNEL_COUNT : Integer := 2;
VOLUMEPRECISION : Integer := 16;
I2S_BITDEPTH : Integer := 24;
PHASEPRECISION : Integer := 32;
SINESPEROCTAVE_ADDRBW : Integer := 11;
SINES_ADDRBW : Integer := 14;
MAX_HARMONICS : Integer := 16;
TOTAL_SINES_ADDRBW : Integer := 14;
BANKCOUNT : Integer := 12;
SINESPERBANK : Integer := 1024;
CYCLE_BW : Integer := 3;
SINESPERBANK_ADDRBW : Integer := 10
);
Port (
sysclk : In Std_logic;
rstin : In Std_logic;
-- SPI SLAVE INTERFACE
SCLK : In Std_logic; -- SPI clock
CS_N : In Std_logic; -- SPI chip select, active in low
MOSI : In Std_logic; -- SPI serial data from master to slave
MISO : Out Std_logic; -- SPI serial data from slave to master
i2s_bclk : Out Std_logic;
i2s_mclk : Out Std_logic;
i2s_lrclk : Out Std_logic := '1';
i2s_dacsd : Out Std_logic := '0';
i2s_adcsd : In Std_logic;
btn : In Std_logic_vector(1 Downto 0) := (Others => '0');
led : Out Std_logic_vector(1 Downto 0) := (Others => '0');
led0_b : Out Std_logic := '1';
led0_g : Out Std_logic := '1';
led0_r : Out Std_logic := '1';
halt : Out Std_logic := '1'
);
End spectral_engine;
Architecture arch_imp Of spectral_engine Is
signal i2s_lrclk_i : Std_logic := '1';
signal i2s_dacsd_i : Std_logic := '0';
attribute mark_debug : string;
attribute mark_debug of i2s_lrclk_i: signal is "true";
attribute mark_debug of i2s_dacsd_i: signal is "true";
Signal fbclk : Std_logic := '1';
Signal plllock : Std_logic := '1';
Signal clk_unbuffd : Std_logic := '1';
Signal clk : Std_logic := '1';
Signal rst : Std_logic := '1';
constant COUNTER_WIDTH : integer := 32;
Signal counter : unsigned(COUNTER_WIDTH-1 Downto 0) := (Others => '0');
Signal ram_rst : Std_logic := '0';
Signal initializeRam_out0 : Std_logic := '1';
Signal initializeRam_out1 : Std_logic := '1';
Type spi2mm_statetype Is (IDLE, ADDR1, ADDR2, ADDR3, LENGTH0, DATA0, DATA1, DATA2, DATA3);
Signal spi2mm_state : spi2mm_statetype;
Signal spi2mm_state_last : spi2mm_statetype;
signal statechange : std_logic;
attribute mark_debug of statechange : signal is "true";
attribute mark_debug of spi2mm_state : signal is "true";
attribute mark_debug of spi2mm_state_last : signal is "true";
Signal SPI_TX_DATA : Std_logic_vector(7 Downto 0); -- input data for SPI master
Signal SPI_TX_VALID : Std_logic; -- when DIN_VALID = 1, input data are valid
Signal SPI_TX_READY : Std_logic; -- when DIN_READY = 1, valid input data are accept
Signal SPI_RX_DATA : Std_logic_vector(7 Downto 0); -- output data from SPI master
Signal SPI_RX_VALID : Std_logic; -- when DOUT_VALID = 1, output data are valid
Signal SPI_RX_READY : Std_logic;
attribute mark_debug of SPI_RX_DATA : signal is "true";
attribute mark_debug of SPI_RX_VALID : signal is "true";
attribute mark_debug of SPI_RX_READY : signal is "true";
Signal PCM_TVALID : Std_logic := '0';
Signal PCM_TREADY : Std_logic := '1';
Signal PCM_TDATA : Std_logic_vector(I2s_BITDEPTH * CHANNEL_COUNT - 1 Downto 0) := (Others => '0');
attribute mark_debug of PCM_TVALID : signal is "true";
attribute mark_debug of PCM_TREADY : signal is "true";
--attribute mark_debug of PCM_TDATA : signal is "true";
Signal I2S_RX_VALID : Std_logic;
Signal I2S_RX_READY : Std_logic := '1';
Signal I2S_RX_DATA : Std_logic_vector(I2s_BITDEPTH * CHANNEL_COUNT - 1 Downto 0) := (Others => '0');
Signal i2s_begin : Std_logic;
Signal mm_wraddr : Std_logic_vector(31 Downto 0) := (Others => '0');
Signal note_wraddr : Std_logic_vector(31 Downto 0) := (Others => '0');
Signal mm_notenum : unsigned(7 Downto 0) := (Others => '0');
Signal mm_paramnum : Integer := 0;
Signal mm_additional0 : Integer := 0;
Signal mm_additional1 : Integer := 0;
Signal mm_length : Integer := 0;
Signal mm_wrdata : Std_logic_vector(31 Downto 0) := (Others => '0');
Signal mm_wrdata_processbw : Std_logic_vector(PROCESS_BW-1 Downto 0) := (Others => '0');
attribute mark_debug of mm_wrdata: signal is "true";
Signal AMPARRAY_WREN : Std_logic_vector(BANKCOUNT - 1 Downto 0);
Signal AMPARRAY_WRADDR : Std_logic_vector(SINESPERBANK_ADDRBW - 1 Downto 0);
Signal amparray_wrdata : Std_logic_vector(VOLUMEPRECISION - 1 Downto 0) := (Others => '0');
Signal amparray_CURRCYCLE : Std_logic_vector(CYCLE_BW - 1 Downto 0);
attribute mark_debug of AMPARRAY_WREN : signal is "true";
attribute mark_debug of AMPARRAY_WRADDR : signal is "true";
attribute mark_debug of amparray_wrdata : signal is "true";
attribute mark_debug of amparray_CURRCYCLE : signal is "true";
Signal hwidth_wr : Std_logic := '0';
Signal hwidth_inv_wr : Std_logic := '0';
Signal basenote_wr : Std_logic := '0';
Signal harmonic_en_wr : Std_logic := '0';
Signal fmfactor_wr : Std_logic := '0';
Signal fmdepth_wr : Std_logic := '0';
Signal centsinc_wr : Std_logic := '0';
Signal gain_wr : Std_logic := '0';
attribute mark_debug of hwidth_wr : signal is "true";
attribute mark_debug of hwidth_inv_wr : signal is "true";
attribute mark_debug of basenote_wr : signal is "true";
attribute mark_debug of harmonic_en_wr: signal is "true";
attribute mark_debug of fmfactor_wr : signal is "true";
attribute mark_debug of fmdepth_wr : signal is "true";
attribute mark_debug of centsinc_wr : signal is "true";
attribute mark_debug of gain_wr : signal is "true";
Signal envelope_env_bezier_MIDnENDpoint_wr : Std_logic := '0';
Signal envelope_env_speed_wr : Std_logic := '0';
Signal pbend_env_bezier_MIDnENDpoint_wr : Std_logic := '0';
Signal pbend_env_speed_wr : Std_logic := '0';
Signal hwidth_env_3EndPoints_wr : Std_logic := '0';
Signal hwidth_env_speed_wr : Std_logic := '0';
Signal nfilter_env_bezier_3EndPoints_wr : Std_logic := '0';
Signal nfilter_env_speed_wr : Std_logic := '0';
Signal gfilter_env_bezier_3EndPoints_wr : Std_logic := '0';
Signal gfilter_env_speed_wr : Std_logic := '0';
attribute mark_debug of envelope_env_bezier_MIDnENDpoint_wr : signal is "true";
attribute mark_debug of envelope_env_speed_wr : signal is "true";
attribute mark_debug of pbend_env_bezier_MIDnENDpoint_wr : signal is "true";
attribute mark_debug of pbend_env_speed_wr : signal is "true";
attribute mark_debug of hwidth_env_3EndPoints_wr : signal is "true";
attribute mark_debug of hwidth_env_speed_wr : signal is "true";
attribute mark_debug of nfilter_env_bezier_3EndPoints_wr : signal is "true";
attribute mark_debug of nfilter_env_speed_wr : signal is "true";
attribute mark_debug of gfilter_env_bezier_3EndPoints_wr : signal is "true";
attribute mark_debug of gfilter_env_speed_wr : signal is "true";
Signal run : Std_logic_vector(Z21 Downto Z00) := (Others => '0');
Signal IRQueue_out_ready : Std_logic := '0';
Signal IRQueue_out_valid : Std_logic := '0';
Signal IRQueue_out_data : Std_logic_vector(15 Downto 0) := (Others => '0');
Signal OUTBYTE : Integer := 0;
Begin
mm_wrdata_processbw <= mm_wrdata(PROCESS_BW-1 downto 0);
statechange <= '1' when spi2mm_state /= spi2mm_state_last else '0';
i2s_lrclk <= i2s_lrclk_i ;
i2s_dacsd <= i2s_dacsd_i ;
rst <= rstin Or Not plllock Or ram_rst;
halt<= rst;
passthrugen :
If USE_MLMM = 0 Generate
clk <= sysclk;
End Generate;
mlmmgen :
If USE_MLMM = 1 Generate
BUFG_inst : BUFG
port map (
O => clk, -- 1-bit output: Clock output
I => clk_unbuffd -- 1-bit input: Clock input
);
MMCME2_BASE_inst : MMCME2_BASE
Generic Map(
BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW)
CLKFBOUT_MULT_F => 57.5, -- Multiply value for all CLKOUT (2.000-64.000).
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000).
CLKIN1_PERIOD => 83.3333333, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT1_DIVIDE => 7,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT6_DIVIDE => 1,
CLKOUT0_DIVIDE_F => 1.0, -- Divide amount for CLKOUT0 (1.000-128.000).
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT6_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
DIVCLK_DIVIDE => 1, -- Master division value (1-106)
REF_JITTER1 => 0.0, -- Reference input jitter in UI (0.000-0.999).
STARTUP_WAIT => FALSE -- Delays DONE until MMCM is locked (FALSE, TRUE)
)
Port Map(
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT1 => clk_unbuffd, -- 1-bit output: CLKOUT0
-- CLKOUT0B => CLKOUT0B, -- 1-bit output: Inverted CLKOUT0
-- CLKOUT1 => CLKOUT1, -- 1-bit output: CLKOUT1
-- CLKOUT1B => CLKOUT1B, -- 1-bit output: Inverted CLKOUT1
-- CLKOUT2 => CLKOUT2, -- 1-bit output: CLKOUT2
-- CLKOUT2B => CLKOUT2B, -- 1-bit output: Inverted CLKOUT2
-- CLKOUT3 => CLKOUT3, -- 1-bit output: CLKOUT3
-- CLKOUT3B => CLKOUT3B, -- 1-bit output: Inverted CLKOUT3
-- CLKOUT4 => CLKOUT4, -- 1-bit output: CLKOUT4
-- CLKOUT5 => CLKOUT5, -- 1-bit output: CLKOUT5
-- CLKOUT6 => CLKOUT6, -- 1-bit output: CLKOUT6
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => fbclk, -- 1-bit output: Feedback clock
CLKFBOUTB => Open, -- 1-bit output: Inverted CLKFBOUT
-- Status Ports: 1-bit (each) output: MMCM status ports
LOCKED => plllock, -- 1-bit output: LOCK
-- Clock Inputs: 1-bit (each) input: Clock input
CLKIN1 => sysclk, -- 1-bit input: Clock
-- Control Ports: 1-bit (each) input: MMCM control ports
PWRDWN => '0', -- 1-bit input: Power-down
RST => RSTIN, -- 1-bit input: Reset
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => fbclk -- 1-bit input: Feedback clock
);
End Generate;
led0_b <= counter(counter'high);
led0_g <= counter(counter'high - 6);
led0_r <= counter(counter'high - 2);
rar : Entity work.ram_active_rst
Port Map(
slowclk => clk,
rstin => rstin,
clksRdy => plllock,
ram_rst => ram_rst,
initializeRam_out0 => initializeRam_out0,
initializeRam_out1 => initializeRam_out1
);
sb : Entity work.sine_bank
Generic Map(
PHASEPRECISION => 32,
VOLUMEPRECISION => 16,
I2S_BITDEPTH => I2S_BITDEPTH,
CHANNEL_COUNT => 2
)
Port Map(
clk => clk,
rst => rst,
Z00_volume_wren => amparray_wren,
Z00_volume_wrdata => amparray_wrdata,
Z00_volume_wraddr => amparray_wraddr,
Z00_volume_currcycle => amparray_currcycle,
S16_PCM_TVALID => PCM_TVALID,
S16_PCM_TREADY => PCM_TREADY,
S16_PCM_TDATA => PCM_TDATA
);
i2s : Entity work.i2s_master
Generic Map(
BIT_DEPTH => I2S_BITDEPTH,
CHANNEL_COUNT => CHANNEL_COUNT,
INPUT_FREQ => 98570e3,
SAMPLE_RATE => 96e3
)
Port Map(
clk => clk,
rst => rst,
TX_VALID => PCM_TVALID,
TX_READY => PCM_TREADY,
TX_DATA => PCM_TDATA,
RX_VALID => I2S_RX_VALID,
RX_READY => I2S_RX_READY,
RX_DATA => I2S_RX_DATA,
i2s_bclk => i2s_bclk,
i2s_lrclk => i2s_lrclk_i,
i2s_dacsd => i2s_dacsd_i,
i2s_adcsd => i2s_adcsd,
i2s_mclk => i2s_mclk,
i2s_begin => i2s_begin
);
sn : Entity work.spectral_note
Generic Map(
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
PHASEPRECISION => 32,
CHANNEL_COUNT => 2,
NOTE_COUNT => 128,
CTRL_COUNT => 4,
MAX_HARMONICS => 31,
PROCESS_BW => 18
)
Port Map(
clk => clk,
rst => rst,
Z22_AMPARRAY_WREN => AMPARRAY_WREN,
Z22_AMPARRAY_WRADDR => AMPARRAY_WRADDR,
Z22_amparray_wrdata => amparray_wrdata,
Z22_amparray_CURRCYCLE => amparray_CURRCYCLE,
hwidth_inv_wr => hwidth_inv_wr,
hwidth_wr => hwidth_wr,
basenote_wr => basenote_wr,
harmonic_en_wr => harmonic_en_wr,
fmfactor_wr => fmfactor_wr,
fmdepth_wr => fmdepth_wr,
centsinc_wr => centsinc_wr,
envelope_env_bezier_MIDnENDpoint_wr => envelope_env_bezier_MIDnENDpoint_wr,
envelope_env_speed_wr => envelope_env_speed_wr,
pbend_env_speed_wr => pbend_env_speed_wr,
pbend_env_bezier_MIDnENDpoint_wr => pbend_env_bezier_MIDnENDpoint_wr,
hwidth_env_3EndPoints_wr => hwidth_env_3EndPoints_wr,
hwidth_env_speed_wr => hwidth_env_speed_wr,
nfilter_env_bezier_3EndPoints_wr => nfilter_env_bezier_3EndPoints_wr,
nfilter_env_speed_wr => nfilter_env_speed_wr,
gfilter_env_bezier_3EndPoints_wr => gfilter_env_bezier_3EndPoints_wr,
gfilter_env_speed_wr => gfilter_env_speed_wr,
IRQueue_out_ready => IRQueue_out_ready,
IRQueue_out_valid => IRQueue_out_valid,
IRQueue_out_data => IRQueue_out_data,
mm_wraddr => mm_wraddr,
mm_wrdata => mm_wrdata
);
ss : Entity work.SPI_SLAVE
Port Map(
CLK => CLK,
RST => RST,
SCLK => SCLK,
CS_N => CS_N,
MOSI => MOSI,
MISO => MISO,
TX_DATA => SPI_TX_DATA,
TX_VALID => SPI_TX_VALID,
TX_READY => SPI_TX_READY,
RX_DATA => SPI_RX_DATA,
RX_VALID => SPI_RX_VALID,
RX_READY => SPI_RX_READY
);
-- ready to read must be concurrent
IRQueue_out_ready <= '1' When spi2mm_state = DATA3 And mm_paramnum = 0 And OUTBYTE = 0 Else '0';
-- only thing were sending right now is irqs when requested
SPI_TX_VALID <= IRQueue_out_valid And IRQueue_out_ready;
-- big endian data send
SPI_TX_DATA <= IRQueue_out_data(15 Downto 8) When OUTBYTE = 0 Else
IRQueue_out_data(7 Downto 0) When OUTBYTE = 1;
strm2mm :
Process (clk)
Begin
-- 32 Bytes address (top 8 is paramno, bottom 24 is index therein)
If rising_edge(clk) Then
spi2mm_state_last <= spi2mm_state;
counter <= counter + 1;
-- usually no writes
envelope_env_bezier_MIDnENDpoint_wr <= '0';
envelope_env_speed_wr <= '0';
pbend_env_bezier_MIDnENDpoint_wr <= '0';
pbend_env_speed_wr <= '0';
hwidth_env_3EndPoints_wr <= '0';
hwidth_env_speed_wr <= '0';
nfilter_env_bezier_3EndPoints_wr <= '0';
nfilter_env_speed_wr <= '0';
gfilter_env_bezier_3EndPoints_wr <= '0';
gfilter_env_speed_wr <= '0';
hwidth_wr <= '0';
hwidth_inv_wr <= '0';
basenote_wr <= '0';
harmonic_en_wr <= '0';
fmfactor_wr <= '0';
fmdepth_wr <= '0';
centsinc_wr <= '0';
gain_wr <= '0';
SPI_RX_READY <= '1';
If rst = '0' And CS_N = '0' Then
If SPI_RX_VALID = '1' Then
SPI_RX_READY <= '0';
mm_length <= mm_length - 1;
Case spi2mm_state Is
When IDLE =>
mm_wraddr <= (Others => '0');
note_wraddr <= (Others => '0');
mm_notenum <= (Others => '0');
mm_paramnum <= 0;
mm_additional0 <= 0;
mm_additional1 <= 0;
mm_length <= 0;
mm_wrdata <= (Others => '0');
OUTBYTE <= 0;
mm_wraddr(31 Downto 24) <= SPI_RX_DATA;
mm_notenum <= unsigned(SPI_RX_DATA);
spi2mm_state <= ADDR1;
When ADDR1 =>
mm_wraddr(23 Downto 16) <= SPI_RX_DATA;
mm_paramnum <= to_integer(unsigned(SPI_RX_DATA));
spi2mm_state <= ADDR2;
When ADDR2 =>
mm_wraddr(15 Downto 8) <= SPI_RX_DATA;
mm_additional0 <= to_integer(unsigned(SPI_RX_DATA));
spi2mm_state <= ADDR3;
When ADDR3 =>
mm_wraddr(7 Downto 0) <= SPI_RX_DATA;
mm_additional1 <= to_integer(unsigned(SPI_RX_DATA));
spi2mm_state <= DATA0;
When DATA0 =>
mm_wrdata(31 Downto 24) <= SPI_RX_DATA;
spi2mm_state <= DATA1;
When DATA1 =>
mm_wrdata(23 Downto 16) <= SPI_RX_DATA;
spi2mm_state <= DATA2;
When DATA2 =>
mm_wrdata(15 Downto 8) <= SPI_RX_DATA;
spi2mm_state <= DATA3;
When DATA3 =>
mm_wrdata(7 Downto 0) <= SPI_RX_DATA;
--mm_wraddr <= std_logic_vector(unsigned(mm_wraddr) + 1);
-- direct the write dependant on top byte of address
Case(mm_paramnum) Is
When 0 =>
-- read one reset irq
OUTBYTE <= OUTBYTE + 1;
When ENVELOPE_MIDnEND =>
envelope_env_bezier_MIDnENDpoint_wr <= '1';
When envelope_ENV_SPEED =>
envelope_env_speed_wr <= '1';
When PBEND_MIDnEND =>
pbend_env_bezier_MIDnENDpoint_wr <= '1';
When PBEND_ENV_SPEED =>
pbend_env_speed_wr <= '1';
When HWIDTH_3TARGETS =>
hwidth_env_3EndPoints_wr <= '1';
When HWIDTH_ENV_SPEED =>
hwidth_env_speed_wr <= '1';
When NFILTER_3TARGETS =>
nfilter_env_bezier_3EndPoints_wr <= '1';
When NFILTER_ENV_SPEED =>
nfilter_env_speed_wr <= '1';
When GFILTER_3TARGETS =>
gfilter_env_bezier_3EndPoints_wr <= '1';
When GFILTER_ENV_SPEED =>
gfilter_env_speed_wr <= '1';
When HARMONIC_WIDTH =>
hwidth_wr <= '1';
When HARMONIC_BASENOTE =>
basenote_wr <= '1';
When HARMONIC_ENABLE =>
harmonic_en_wr <= '1';
When HARMONIC_WIDTH_INV =>
hwidth_inv_wr <= '1';
When fmfactor =>
fmfactor_wr <= '1';
When fmdepth =>
fmdepth_wr <= '1';
When centsinc =>
centsinc_wr <= '1';
When gain =>
gain_wr <= '1';
When Others =>
End Case;
spi2mm_state <= IDLE;
When Others =>
End Case;
End If;
Else
spi2mm_state <= IDLE;
End If;
End If;
End Process;
End arch_imp;
|
<filename>Lab6/SevenSegmentDisplay.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity SevenSegmentDisplay is
port(
clk : in std_logic:='0';
Display_inp : in std_logic_vector(31 downto 0):="00000000000000000000000000000000";
pushbutton : in std_logic:='0';
Anode : out std_logic_vector(3 downto 0):="0000";
Cathode : out std_logic_vector(7 downto 0):="00000000"
);
end entity SevenSegmentDisplay;
architecture arch of SevenSegmentDisplay is
--signal Anode : std_logic_vector(3 downto 0);
signal temp_cathode : std_logic_vector(6 downto 0):="0000000";
signal to_display : std_logic_vector(15 downto 0):="0000000000000000";
--signal pushbutton : std_logic:='0';
component display is
port (to_display:in std_logic_vector(15 downto 0);
pushbutton:in std_logic;
cathod:out std_logic_vector(6 downto 0);
anodd:out std_logic_vector(3 downto 0);
clock: in std_logic);
end component;
begin
to_display<= Display_inp(15 downto 0);
--pushbutton <= '0';
Disp: display
port map (to_display=> to_display,
pushbutton=> pushbutton,
cathod => temp_cathode,
anodd=> Anode,
clock=> clk);
Cathode <= '0' & temp_cathode;
end architecture;
--------------------------------------------------------------------------------------------|||
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity display is
port (to_display:in std_logic_vector(15 downto 0);
pushbutton:in std_logic;
cathod:out std_logic_vector(6 downto 0);
anodd:out std_logic_vector(3 downto 0);
clock: in std_logic);
end display;
architecture Behavioral of display is
signal reduced_clock,selected_clock:std_logic;
signal temp_anode:std_logic_vector(3 downto 0);
signal to_displ:std_logic_vector(3 downto 0);
component clock_reducer is
Port (
clk_in : in STD_LOGIC;
clk_out: out STD_LOGIC);
end component;
component cat_disp
port(to_disp:in std_logic_vector(3 downto 0);
cathode:out std_logic_vector(6 downto 0));
end component;
component anode_selector
port(clk_input: in std_logic;
anod: out std_logic_vector(3 downto 0));
end component;
begin
frquency_reducer : clock_reducer
port map (clk_in=> clock,
clk_out => reduced_clock );
selected_clock<= (pushbutton and clock ) or ((not pushbutton) and reduced_clock);
anode_output: anode_selector
port map (clk_input=>selected_clock,
anod=>temp_anode);
anodd<=temp_anode;
process(temp_anode)
begin
case temp_anode is
when "1110" => to_displ(3 downto 0)<= to_display(3 downto 0);
when "1101" => to_displ(3 downto 0)<= to_display(7 downto 4) ;
when "1011" => to_displ(3 downto 0)<= to_display(11 downto 8) ;
when others => to_displ(3 downto 0)<= to_display(15 downto 12) ;
end case;
end process;
cathode_displayer: cat_disp
port map(to_disp=>to_displ,
cathode=>cathod);
end Behavioral;
------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity anode_selector is
port(clk_input: in std_logic;
anod: out std_logic_vector(3 downto 0));
end anode_selector;
architecture Behavioral of anode_selector is
signal temp : std_logic_vector(3 downto 0):="0111";
begin
process(clk_input)
begin
if (clk_input='1' and clk_input'event) then
if (temp="0111") then
temp<="1011";
elsif (temp="1011") then
temp<="1101";
elsif (temp="1101") then
temp<="1110";
elsif (temp="1110") then
temp<="0111";
end if;
end if;
end process;
anod<=temp;
end Behavioral;
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:23:53 09/17/2017
-- Design Name:
-- Module Name: cat_disp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cat_disp is
port(to_disp:in std_logic_vector(3 downto 0);
cathode:out std_logic_vector(6 downto 0));
end cat_disp;
architecture Behavioral of cat_disp is
component cat_a_new_2_MUSER_lab4_seven_segment_display
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
cat_a_new : out std_logic;
D : in std_logic);
end component;
component cat_b_MUSER_lab4_seven_segment_display
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
cat_B : out std_logic;
D : in std_logic);
end component;
component cat_c_MUSER_lab4_seven_segment_display
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
cat_c : out std_logic;
D : in std_logic);
end component;
component cat_d_MUSER_lab4_seven_segment_display
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
cat_d : out std_logic;
D : in std_logic);
end component;
component cat_e_MUSER_lab4_seven_segment_display
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
cat_e : out std_logic;
D : in std_logic);
end component;
component cat_f_MUSER_lab4_seven_segment_display
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
cat_f : out std_logic;
D : in std_logic);
end component;
component cat_g_MUSER_lab4_seven_segment_display
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
cat_g : out std_logic;
D : in std_logic);
end component;
begin
XLXI_31 : cat_a_new_2_MUSER_lab4_seven_segment_display
port map (A=>to_disp(3),
B=>to_disp(2),
C=>to_disp(1),
D=>to_disp(0),
cat_a_new=>cathode(0));
XLXI_6 : cat_b_MUSER_lab4_seven_segment_display
port map (A=>to_disp(3),
B=>to_disp(2),
C=>to_disp(1),
D=>to_disp(0),
cat_B=>cathode(1));
XLXI_7 : cat_c_MUSER_lab4_seven_segment_display
port map (A=>to_disp(3),
B=>to_disp(2),
C=>to_disp(1),
D=>to_disp(0),
cat_c=>cathode(2));
XLXI_8 : cat_d_MUSER_lab4_seven_segment_display
port map (A=>to_disp(3),
B=>to_disp(2),
C=>to_disp(1),
D=>to_disp(0),
cat_d=>cathode(3));
XLXI_9 : cat_e_MUSER_lab4_seven_segment_display
port map (A=>to_disp(3),
B=>to_disp(2),
C=>to_disp(1),
D=>to_disp(0),
cat_e=>cathode(4));
XLXI_10 : cat_f_MUSER_lab4_seven_segment_display
port map (A=>to_disp(3),
B=>to_disp(2),
C=>to_disp(1),
D=>to_disp(0),
cat_f=>cathode(5));
XLXI_11 : cat_g_MUSER_lab4_seven_segment_display
port map (A=>to_disp(3),
B=>to_disp(2),
C=>to_disp(1),
D=>to_disp(0),
cat_g=>cathode(6));
end Behavioral;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity cat_a_new_2_MUSER_lab4_seven_segment_display is
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
cat_a_new : out std_logic);
end cat_a_new_2_MUSER_lab4_seven_segment_display;
architecture BEHAVIORAL of cat_a_new_2_MUSER_lab4_seven_segment_display is
attribute BOX_TYPE : string ;
signal XLXN_29 : std_logic;
signal XLXN_30 : std_logic;
signal XLXN_31 : std_logic;
signal XLXN_32 : std_logic;
component AND4B3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B3 : component is "BLACK_BOX";
component AND4B1
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B1 : component is "BLACK_BOX";
component OR4
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR4 : component is "BLACK_BOX";
begin
XLXI_7 : AND4B3
port map (I0=>C,
I1=>B,
I2=>A,
I3=>D,
O=>XLXN_29);
XLXI_8 : AND4B3
port map (I0=>C,
I1=>A,
I2=>D,
I3=>B,
O=>XLXN_30);
XLXI_9 : AND4B1
port map (I0=>B,
I1=>D,
I2=>A,
I3=>C,
O=>XLXN_31);
XLXI_10 : AND4B1
port map (I0=>C,
I1=>D,
I2=>B,
I3=>A,
O=>XLXN_32);
XLXI_11 : OR4
port map (I0=>XLXN_32,
I1=>XLXN_31,
I2=>XLXN_30,
I3=>XLXN_29,
O=>cat_a_new);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity cat_g_MUSER_lab4_seven_segment_display is
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
cat_g : out std_logic);
end cat_g_MUSER_lab4_seven_segment_display;
architecture BEHAVIORAL of cat_g_MUSER_lab4_seven_segment_display is
attribute BOX_TYPE : string ;
signal XLXN_11 : std_logic;
signal XLXN_12 : std_logic;
signal XLXN_13 : std_logic;
component AND3B3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3B3 : component is "BLACK_BOX";
component AND4B2
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B2 : component is "BLACK_BOX";
component AND4B1
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B1 : component is "BLACK_BOX";
component OR3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR3 : component is "BLACK_BOX";
begin
XLXI_3 : AND3B3
port map (I0=>C,
I1=>B,
I2=>A,
O=>XLXN_11);
XLXI_4 : AND4B2
port map (I0=>D,
I1=>C,
I2=>B,
I3=>A,
O=>XLXN_12);
XLXI_5 : AND4B1
port map (I0=>A,
I1=>D,
I2=>C,
I3=>B,
O=>XLXN_13);
XLXI_6 : OR3
port map (I0=>XLXN_13,
I1=>XLXN_12,
I2=>XLXN_11,
O=>cat_g);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity cat_f_MUSER_lab4_seven_segment_display is
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
cat_f : out std_logic);
end cat_f_MUSER_lab4_seven_segment_display;
architecture BEHAVIORAL of cat_f_MUSER_lab4_seven_segment_display is
attribute BOX_TYPE : string ;
signal XLXN_13 : std_logic;
signal XLXN_14 : std_logic;
signal XLXN_15 : std_logic;
signal XLXN_16 : std_logic;
component AND3B1
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";
component AND4B1
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B1 : component is "BLACK_BOX";
component AND4B3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B3 : component is "BLACK_BOX";
component OR4
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR4 : component is "BLACK_BOX";
begin
XLXI_1 : AND3B1
port map (I0=>A,
I1=>D,
I2=>C,
O=>XLXN_13);
XLXI_2 : AND4B1
port map (I0=>C,
I1=>D,
I2=>B,
I3=>A,
O=>XLXN_14);
XLXI_3 : AND4B3
port map (I0=>D,
I1=>B,
I2=>A,
I3=>C,
O=>XLXN_15);
XLXI_5 : AND4B3
port map (I0=>C,
I1=>B,
I2=>A,
I3=>D,
O=>XLXN_16);
XLXI_6 : OR4
port map (I0=>XLXN_16,
I1=>XLXN_15,
I2=>XLXN_14,
I3=>XLXN_13,
O=>cat_f);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity cat_e_MUSER_lab4_seven_segment_display is
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
cat_e : out std_logic);
end cat_e_MUSER_lab4_seven_segment_display;
architecture BEHAVIORAL of cat_e_MUSER_lab4_seven_segment_display is
attribute BOX_TYPE : string ;
signal XLXN_13 : std_logic;
signal XLXN_16 : std_logic;
signal XLXN_17 : std_logic;
component AND2B1
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
component AND4B3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B3 : component is "BLACK_BOX";
component AND4B2
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B2 : component is "BLACK_BOX";
component OR3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR3 : component is "BLACK_BOX";
begin
XLXI_1 : AND2B1
port map (I0=>A,
I1=>D,
O=>XLXN_13);
XLXI_2 : AND4B3
port map (I0=>D,
I1=>C,
I2=>A,
I3=>B,
O=>XLXN_16);
XLXI_3 : AND4B2
port map (I0=>C,
I1=>B,
I2=>D,
I3=>A,
O=>XLXN_17);
XLXI_4 : OR3
port map (I0=>XLXN_17,
I1=>XLXN_16,
I2=>XLXN_13,
O=>cat_e);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity cat_d_MUSER_lab4_seven_segment_display is
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
cat_d : out std_logic);
end cat_d_MUSER_lab4_seven_segment_display;
architecture BEHAVIORAL of cat_d_MUSER_lab4_seven_segment_display is
attribute BOX_TYPE : string ;
signal XLXN_15 : std_logic;
signal XLXN_16 : std_logic;
signal XLXN_17 : std_logic;
signal XLXN_18 : std_logic;
component AND3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
component AND4B2
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B2 : component is "BLACK_BOX";
component AND4B3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B3 : component is "BLACK_BOX";
component OR4
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR4 : component is "BLACK_BOX";
begin
XLXI_1 : AND3
port map (I0=>D,
I1=>C,
I2=>B,
O=>XLXN_15);
XLXI_2 : AND4B2
port map (I0=>D,
I1=>B,
I2=>C,
I3=>A,
O=>XLXN_16);
XLXI_3 : AND4B3
port map (I0=>C,
I1=>B,
I2=>A,
I3=>D,
O=>XLXN_17);
XLXI_4 : AND4B3
port map (I0=>D,
I1=>C,
I2=>A,
I3=>B,
O=>XLXN_18);
XLXI_5 : OR4
port map (I0=>XLXN_18,
I1=>XLXN_17,
I2=>XLXN_16,
I3=>XLXN_15,
O=>cat_d);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity cat_c_MUSER_lab4_seven_segment_display is
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
cat_c : out std_logic);
end cat_c_MUSER_lab4_seven_segment_display;
architecture BEHAVIORAL of cat_c_MUSER_lab4_seven_segment_display is
attribute BOX_TYPE : string ;
signal XLXN_10 : std_logic;
signal XLXN_13 : std_logic;
signal XLXN_15 : std_logic;
component AND3B1
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";
component AND3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
component AND4B3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B3 : component is "BLACK_BOX";
component OR3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR3 : component is "BLACK_BOX";
begin
XLXI_1 : AND3B1
port map (I0=>D,
I1=>B,
I2=>A,
O=>XLXN_10);
XLXI_2 : AND3
port map (I0=>C,
I1=>B,
I2=>A,
O=>XLXN_13);
XLXI_3 : AND4B3
port map (I0=>D,
I1=>B,
I2=>A,
I3=>C,
O=>XLXN_15);
XLXI_5 : OR3
port map (I0=>XLXN_15,
I1=>XLXN_13,
I2=>XLXN_10,
O=>cat_c);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity cat_b_MUSER_lab4_seven_segment_display is
port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
cat_B : out std_logic);
end cat_b_MUSER_lab4_seven_segment_display;
architecture BEHAVIORAL of cat_b_MUSER_lab4_seven_segment_display is
attribute BOX_TYPE : string ;
signal XLXN_43 : std_logic;
signal XLXN_44 : std_logic;
signal XLXN_45 : std_logic;
signal XLXN_46 : std_logic;
component AND3B1
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX";
component AND3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
component AND4B2
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4B2 : component is "BLACK_BOX";
component OR4
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of OR4 : component is "BLACK_BOX";
begin
XLXI_11 : AND3B1
port map (I0=>D,
I1=>C,
I2=>B,
O=>XLXN_43);
XLXI_12 : AND3B1
port map (I0=>D,
I1=>B,
I2=>A,
O=>XLXN_44);
XLXI_13 : AND3
port map (I0=>C,
I1=>B,
I2=>A,
O=>XLXN_45);
XLXI_14 : AND4B2
port map (I0=>C,
I1=>A,
I2=>D,
I3=>B,
O=>XLXN_46);
XLXI_15 : OR4
port map (I0=>XLXN_46,
I1=>XLXN_45,
I2=>XLXN_44,
I3=>XLXN_43,
O=>cat_B);
end BEHAVIORAL;
|
<filename>avalonComponents/subDevices/avalon_adc128S102_interface/src/avalon_adc128S102_interface.m.vhd
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- <NAME> - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- <NAME> - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE avalon_adc128S102_interface_pkg IS
CONSTANT c_adc128S102_address_width : INTEGER := 5;
COMPONENT avalon_adc128S102_interface IS
GENERIC (
BASE_CLK: INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000; --Min 0.8 Mhz, max 16Mhz
UNIQUE_ID: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_adc128S102_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
osl_avs_waitrequest : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC
);
END COMPONENT;
CONSTANT c_adc128S102_subtype_id : INTEGER := 1;
CONSTANT c_adc128S102_interface_version : INTEGER := 0;
END PACKAGE avalon_adc128S102_interface_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.avalon_adc128S102_interface_pkg.ALL;
USE work.fLink_definitions.ALL;
USE work.adc128S102_pkg.ALL;
ENTITY avalon_adc128S102_interface IS
GENERIC (
BASE_CLK: INTEGER := 33000000;
SCLK_FREQUENCY : INTEGER := 10000000; --Min 0.8 Mhz, max 16Mhz
UNIQUE_ID: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_adc128S102_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
osl_avs_waitrequest : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_Ss : OUT STD_LOGIC;
osl_mosi : OUT STD_LOGIC;
isl_miso : IN STD_LOGIC
);
CONSTANT c_usig_resolution_address: UNSIGNED(c_adc128S102_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers,c_adc128S102_address_width);
CONSTANT c_usig_value_0_address: UNSIGNED(c_adc128S102_address_width-1 DOWNTO 0) := c_usig_resolution_address + 1;
CONSTANT c_usig_last_address: UNSIGNED(c_adc128S102_address_width-1 DOWNTO 0) := c_usig_value_0_address + NUMBER_OF_CHANNELS;
END ENTITY avalon_adc128S102_interface;
ARCHITECTURE rtl OF avalon_adc128S102_interface IS
TYPE t_internal_register IS RECORD
global_reset_n : STD_LOGIC;
adc_reset_n : STD_LOGIC;
END RECORD;
SIGNAL ri,ri_next : t_internal_register;
SIGNAL adc_values : t_value_regs;
BEGIN
my_adc128S102 : adc128S102
GENERIC MAP (BASE_CLK,SCLK_FREQUENCY)
PORT MAP (isl_clk,ri.adc_reset_n,adc_values,osl_sclk,oslv_Ss,osl_mosi,isl_miso);
-- cobinatoric process
comb_proc : PROCESS (isl_reset_n,ri,isl_avs_write,islv_avs_address,isl_avs_read,islv_avs_write_data,adc_values)
VARIABLE vi : t_internal_register;
VARIABLE adc128S102_part_nr: INTEGER := 0;
BEGIN
-- keep variables stable
vi := ri;
--standard values
oslv_avs_read_data <= (OTHERS => '0');
vi.global_reset_n := '1';
vi.adc_reset_n := '1';
--avalon slave interface write part
IF isl_avs_write = '1' THEN
IF UNSIGNED(islv_avs_address) = to_unsigned(c_fLink_configuration_address,c_adc128S102_address_width) THEN
IF islv_avs_byteenable(0) = '1' THEN
vi.global_reset_n := NOT islv_avs_write_data(0);
END IF;
END IF;
END IF;
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE UNSIGNED(islv_avs_address) IS
WHEN to_unsigned(c_fLink_typdef_address,c_adc128S102_address_width) =>
oslv_avs_read_data ((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length - 1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_analog_input_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= STD_LOGIC_VECTOR(to_unsigned(c_adc128S102_subtype_id,c_fLink_subtype_length));
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(c_adc128S102_interface_version,c_fLink_interface_version_length));
WHEN to_unsigned(c_fLink_mem_size_address,c_adc128S102_address_width) =>
oslv_avs_read_data(c_adc128S102_address_width+2) <= '1';
WHEN to_unsigned(c_fLink_number_of_channels_address,c_adc128S102_address_width) =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(NUMBER_OF_CHANNELS,c_fLink_avs_data_width));
WHEN to_unsigned(c_fLink_unique_id_address,c_adc128S102_address_width) =>
oslv_avs_read_data <= UNIQUE_ID;
WHEN c_usig_resolution_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(RESOLUTION,c_fLink_avs_data_width));
WHEN OTHERS =>
IF UNSIGNED(islv_avs_address)>= c_usig_value_0_address AND UNSIGNED(islv_avs_address)< c_usig_last_address THEN
adc128S102_part_nr := to_integer(UNSIGNED(islv_avs_address) - c_usig_value_0_address);
oslv_avs_read_data(RESOLUTION-1 DOWNTO 0) <= std_logic_vector(adc_values(adc128S102_part_nr));
END IF;
END CASE;
END IF;
IF isl_reset_n = '0' OR vi.global_reset_n = '0' THEN
vi.adc_reset_n := '0';
END IF;
--keep variables stable
ri_next <= vi;
END PROCESS comb_proc;
reg_proc : PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_proc;
osl_avs_waitrequest <= '0';
END rtl;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.3
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity conv_2d_large_cl is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
data_V_address0 : OUT STD_LOGIC_VECTOR (10 downto 0);
data_V_ce0 : OUT STD_LOGIC;
data_V_q0 : IN STD_LOGIC_VECTOR (13 downto 0);
res_V_address0 : OUT STD_LOGIC_VECTOR (11 downto 0);
res_V_ce0 : OUT STD_LOGIC;
res_V_we0 : OUT STD_LOGIC;
res_V_d0 : OUT STD_LOGIC_VECTOR (13 downto 0) );
end;
architecture behav of conv_2d_large_cl is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (8 downto 0) := "000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (8 downto 0) := "000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (8 downto 0) := "000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (8 downto 0) := "000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (8 downto 0) := "000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (8 downto 0) := "001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (8 downto 0) := "010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (8 downto 0) := "100000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv12_D0 : STD_LOGIC_VECTOR (11 downto 0) := "000011010000";
constant ap_const_lv4_D : STD_LOGIC_VECTOR (3 downto 0) := "1101";
constant ap_const_lv4_1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_const_lv5_10 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal next_mul_fu_153_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal next_mul_reg_235 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal i_8_fu_165_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal i_8_reg_243 : STD_LOGIC_VECTOR (3 downto 0);
signal j_1_fu_177_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal j_1_reg_251 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal tmp_128_cast_cast_fu_191_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_128_cast_cast_reg_256 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal grp_dense_large_rf_gt_ni_fu_132_ap_ready : STD_LOGIC;
signal grp_dense_large_rf_gt_ni_fu_132_ap_done : STD_LOGIC;
signal k_1_fu_205_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal k_1_reg_264 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal tmp_84_fu_220_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_84_reg_269 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_83_fu_199_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal res_V_assign_q0 : STD_LOGIC_VECTOR (13 downto 0);
signal res_V_assign_load_reg_279 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal data_col_V_address0 : STD_LOGIC_VECTOR (4 downto 0);
signal data_col_V_ce0 : STD_LOGIC;
signal data_col_V_we0 : STD_LOGIC;
signal data_col_V_q0 : STD_LOGIC_VECTOR (13 downto 0);
signal res_V_assign_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal res_V_assign_ce0 : STD_LOGIC;
signal res_V_assign_we0 : STD_LOGIC;
signal grp_dense_large_rf_gt_ni_fu_132_ap_start : STD_LOGIC;
signal grp_dense_large_rf_gt_ni_fu_132_ap_idle : STD_LOGIC;
signal grp_dense_large_rf_gt_ni_fu_132_data_V_address0 : STD_LOGIC_VECTOR (4 downto 0);
signal grp_dense_large_rf_gt_ni_fu_132_data_V_ce0 : STD_LOGIC;
signal grp_dense_large_rf_gt_ni_fu_132_res_V_address0 : STD_LOGIC_VECTOR (3 downto 0);
signal grp_dense_large_rf_gt_ni_fu_132_res_V_ce0 : STD_LOGIC;
signal grp_dense_large_rf_gt_ni_fu_132_res_V_we0 : STD_LOGIC;
signal grp_dense_large_rf_gt_ni_fu_132_res_V_d0 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_im2col_2d_cl_fu_142_ap_start : STD_LOGIC;
signal grp_im2col_2d_cl_fu_142_ap_done : STD_LOGIC;
signal grp_im2col_2d_cl_fu_142_ap_idle : STD_LOGIC;
signal grp_im2col_2d_cl_fu_142_ap_ready : STD_LOGIC;
signal grp_im2col_2d_cl_fu_142_data_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal grp_im2col_2d_cl_fu_142_data_V_ce0 : STD_LOGIC;
signal grp_im2col_2d_cl_fu_142_data_col_V_address0 : STD_LOGIC_VECTOR (4 downto 0);
signal grp_im2col_2d_cl_fu_142_data_col_V_ce0 : STD_LOGIC;
signal grp_im2col_2d_cl_fu_142_data_col_V_we0 : STD_LOGIC;
signal grp_im2col_2d_cl_fu_142_data_col_V_d0 : STD_LOGIC_VECTOR (13 downto 0);
signal i_reg_85 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_s_fu_171_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state1 : BOOLEAN;
signal phi_mul_reg_97 : STD_LOGIC_VECTOR (11 downto 0);
signal j_reg_109 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_fu_159_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal k_reg_121 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal grp_dense_large_rf_gt_ni_fu_132_ap_start_reg : STD_LOGIC := '0';
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal grp_im2col_2d_cl_fu_142_ap_start_reg : STD_LOGIC := '0';
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal tmp_86_fu_226_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_85_fu_231_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_82_fu_183_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal k_cast4_cast_fu_195_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp1_fu_211_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp1_cast_fu_216_p1 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (8 downto 0);
component dense_large_rf_gt_ni IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
data_V_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
data_V_ce0 : OUT STD_LOGIC;
data_V_q0 : IN STD_LOGIC_VECTOR (13 downto 0);
res_V_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
res_V_ce0 : OUT STD_LOGIC;
res_V_we0 : OUT STD_LOGIC;
res_V_d0 : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
component im2col_2d_cl IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
data_V_address0 : OUT STD_LOGIC_VECTOR (10 downto 0);
data_V_ce0 : OUT STD_LOGIC;
data_V_q0 : IN STD_LOGIC_VECTOR (13 downto 0);
data_col_V_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
data_col_V_ce0 : OUT STD_LOGIC;
data_col_V_we0 : OUT STD_LOGIC;
data_col_V_d0 : OUT STD_LOGIC_VECTOR (13 downto 0);
row : IN STD_LOGIC_VECTOR (3 downto 0);
col : IN STD_LOGIC_VECTOR (3 downto 0) );
end component;
component conv_2d_large_cl_data_col_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (4 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (13 downto 0);
q0 : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
component dense_large_rf_gt_ni_acc_V IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (3 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (13 downto 0);
q0 : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
begin
data_col_V_U : component conv_2d_large_cl_data_col_V
generic map (
DataWidth => 14,
AddressRange => 32,
AddressWidth => 5)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => data_col_V_address0,
ce0 => data_col_V_ce0,
we0 => data_col_V_we0,
d0 => grp_im2col_2d_cl_fu_142_data_col_V_d0,
q0 => data_col_V_q0);
res_V_assign_U : component dense_large_rf_gt_ni_acc_V
generic map (
DataWidth => 14,
AddressRange => 16,
AddressWidth => 4)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => res_V_assign_address0,
ce0 => res_V_assign_ce0,
we0 => res_V_assign_we0,
d0 => grp_dense_large_rf_gt_ni_fu_132_res_V_d0,
q0 => res_V_assign_q0);
grp_dense_large_rf_gt_ni_fu_132 : component dense_large_rf_gt_ni
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_dense_large_rf_gt_ni_fu_132_ap_start,
ap_done => grp_dense_large_rf_gt_ni_fu_132_ap_done,
ap_idle => grp_dense_large_rf_gt_ni_fu_132_ap_idle,
ap_ready => grp_dense_large_rf_gt_ni_fu_132_ap_ready,
data_V_address0 => grp_dense_large_rf_gt_ni_fu_132_data_V_address0,
data_V_ce0 => grp_dense_large_rf_gt_ni_fu_132_data_V_ce0,
data_V_q0 => data_col_V_q0,
res_V_address0 => grp_dense_large_rf_gt_ni_fu_132_res_V_address0,
res_V_ce0 => grp_dense_large_rf_gt_ni_fu_132_res_V_ce0,
res_V_we0 => grp_dense_large_rf_gt_ni_fu_132_res_V_we0,
res_V_d0 => grp_dense_large_rf_gt_ni_fu_132_res_V_d0);
grp_im2col_2d_cl_fu_142 : component im2col_2d_cl
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_im2col_2d_cl_fu_142_ap_start,
ap_done => grp_im2col_2d_cl_fu_142_ap_done,
ap_idle => grp_im2col_2d_cl_fu_142_ap_idle,
ap_ready => grp_im2col_2d_cl_fu_142_ap_ready,
data_V_address0 => grp_im2col_2d_cl_fu_142_data_V_address0,
data_V_ce0 => grp_im2col_2d_cl_fu_142_data_V_ce0,
data_V_q0 => data_V_q0,
data_col_V_address0 => grp_im2col_2d_cl_fu_142_data_col_V_address0,
data_col_V_ce0 => grp_im2col_2d_cl_fu_142_data_col_V_ce0,
data_col_V_we0 => grp_im2col_2d_cl_fu_142_data_col_V_we0,
data_col_V_d0 => grp_im2col_2d_cl_fu_142_data_col_V_d0,
row => i_reg_85,
col => j_reg_109);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_continue = ap_const_logic_1)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_159_p2 = ap_const_lv1_1))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
grp_dense_large_rf_gt_ni_fu_132_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_dense_large_rf_gt_ni_fu_132_ap_start_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
grp_dense_large_rf_gt_ni_fu_132_ap_start_reg <= ap_const_logic_1;
elsif ((grp_dense_large_rf_gt_ni_fu_132_ap_ready = ap_const_logic_1)) then
grp_dense_large_rf_gt_ni_fu_132_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
grp_im2col_2d_cl_fu_142_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_im2col_2d_cl_fu_142_ap_start_reg <= ap_const_logic_0;
else
if (((tmp_s_fu_171_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
grp_im2col_2d_cl_fu_142_ap_start_reg <= ap_const_logic_1;
elsif ((grp_im2col_2d_cl_fu_142_ap_ready = ap_const_logic_1)) then
grp_im2col_2d_cl_fu_142_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_reg_85_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
i_reg_85 <= ap_const_lv4_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_s_fu_171_p2 = ap_const_lv1_1))) then
i_reg_85 <= i_8_reg_243;
end if;
end if;
end process;
j_reg_109_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_83_fu_199_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state7))) then
j_reg_109 <= j_1_reg_251;
elsif (((tmp_fu_159_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
j_reg_109 <= ap_const_lv4_0;
end if;
end if;
end process;
k_reg_121_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
k_reg_121 <= k_1_reg_264;
elsif (((grp_dense_large_rf_gt_ni_fu_132_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state6))) then
k_reg_121 <= ap_const_lv5_0;
end if;
end if;
end process;
phi_mul_reg_97_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
phi_mul_reg_97 <= ap_const_lv12_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_s_fu_171_p2 = ap_const_lv1_1))) then
phi_mul_reg_97 <= next_mul_reg_235;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_8_reg_243 <= i_8_fu_165_p2;
next_mul_reg_235 <= next_mul_fu_153_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
j_1_reg_251 <= j_1_fu_177_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
k_1_reg_264 <= k_1_fu_205_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
res_V_assign_load_reg_279 <= res_V_assign_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((grp_dense_large_rf_gt_ni_fu_132_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state6))) then
tmp_128_cast_cast_reg_256(7 downto 4) <= tmp_128_cast_cast_fu_191_p1(7 downto 4);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_83_fu_199_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state7))) then
tmp_84_reg_269 <= tmp_84_fu_220_p2;
end if;
end if;
end process;
tmp_128_cast_cast_reg_256(3 downto 0) <= "0000";
tmp_128_cast_cast_reg_256(8) <= '0';
ap_NS_fsm_assign_proc : process (ap_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, ap_CS_fsm_state6, grp_dense_large_rf_gt_ni_fu_132_ap_done, ap_CS_fsm_state7, tmp_83_fu_199_p2, grp_im2col_2d_cl_fu_142_ap_done, tmp_s_fu_171_p2, tmp_fu_159_p2, ap_CS_fsm_state4)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if ((not(((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1))) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_159_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (tmp_s_fu_171_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (grp_im2col_2d_cl_fu_142_ap_done = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
if (((grp_dense_large_rf_gt_ni_fu_132_ap_done = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state6))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_state6;
end if;
when ap_ST_fsm_state7 =>
if (((tmp_83_fu_199_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state7))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state8;
end if;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when ap_ST_fsm_state9 =>
ap_NS_fsm <= ap_ST_fsm_state7;
when others =>
ap_NS_fsm <= "XXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_block_state1_assign_proc : process(ap_start, ap_done_reg)
begin
ap_block_state1 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
ap_done_assign_proc : process(ap_done_reg, ap_CS_fsm_state2, tmp_fu_159_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_159_p2 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_159_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_159_p2 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
data_V_address0 <= grp_im2col_2d_cl_fu_142_data_V_address0;
data_V_ce0 <= grp_im2col_2d_cl_fu_142_data_V_ce0;
data_col_V_address0_assign_proc : process(ap_CS_fsm_state6, grp_dense_large_rf_gt_ni_fu_132_data_V_address0, grp_im2col_2d_cl_fu_142_data_col_V_address0, ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
data_col_V_address0 <= grp_im2col_2d_cl_fu_142_data_col_V_address0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
data_col_V_address0 <= grp_dense_large_rf_gt_ni_fu_132_data_V_address0;
else
data_col_V_address0 <= "XXXXX";
end if;
end process;
data_col_V_ce0_assign_proc : process(ap_CS_fsm_state6, grp_dense_large_rf_gt_ni_fu_132_data_V_ce0, grp_im2col_2d_cl_fu_142_data_col_V_ce0, ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
data_col_V_ce0 <= grp_im2col_2d_cl_fu_142_data_col_V_ce0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
data_col_V_ce0 <= grp_dense_large_rf_gt_ni_fu_132_data_V_ce0;
else
data_col_V_ce0 <= ap_const_logic_0;
end if;
end process;
data_col_V_we0_assign_proc : process(grp_im2col_2d_cl_fu_142_data_col_V_we0, ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
data_col_V_we0 <= grp_im2col_2d_cl_fu_142_data_col_V_we0;
else
data_col_V_we0 <= ap_const_logic_0;
end if;
end process;
grp_dense_large_rf_gt_ni_fu_132_ap_start <= grp_dense_large_rf_gt_ni_fu_132_ap_start_reg;
grp_im2col_2d_cl_fu_142_ap_start <= grp_im2col_2d_cl_fu_142_ap_start_reg;
i_8_fu_165_p2 <= std_logic_vector(unsigned(i_reg_85) + unsigned(ap_const_lv4_1));
j_1_fu_177_p2 <= std_logic_vector(unsigned(j_reg_109) + unsigned(ap_const_lv4_1));
k_1_fu_205_p2 <= std_logic_vector(unsigned(k_reg_121) + unsigned(ap_const_lv5_1));
k_cast4_cast_fu_195_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(k_reg_121),9));
next_mul_fu_153_p2 <= std_logic_vector(unsigned(phi_mul_reg_97) + unsigned(ap_const_lv12_D0));
res_V_address0 <= tmp_85_fu_231_p1(12 - 1 downto 0);
res_V_assign_address0_assign_proc : process(ap_CS_fsm_state6, ap_CS_fsm_state7, grp_dense_large_rf_gt_ni_fu_132_res_V_address0, tmp_86_fu_226_p1)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
res_V_assign_address0 <= tmp_86_fu_226_p1(4 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
res_V_assign_address0 <= grp_dense_large_rf_gt_ni_fu_132_res_V_address0;
else
res_V_assign_address0 <= "XXXX";
end if;
end process;
res_V_assign_ce0_assign_proc : process(ap_CS_fsm_state6, ap_CS_fsm_state7, grp_dense_large_rf_gt_ni_fu_132_res_V_ce0)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
res_V_assign_ce0 <= ap_const_logic_1;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
res_V_assign_ce0 <= grp_dense_large_rf_gt_ni_fu_132_res_V_ce0;
else
res_V_assign_ce0 <= ap_const_logic_0;
end if;
end process;
res_V_assign_we0_assign_proc : process(ap_CS_fsm_state6, grp_dense_large_rf_gt_ni_fu_132_res_V_we0)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
res_V_assign_we0 <= grp_dense_large_rf_gt_ni_fu_132_res_V_we0;
else
res_V_assign_we0 <= ap_const_logic_0;
end if;
end process;
res_V_ce0_assign_proc : process(ap_CS_fsm_state9)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
res_V_ce0 <= ap_const_logic_1;
else
res_V_ce0 <= ap_const_logic_0;
end if;
end process;
res_V_d0 <= res_V_assign_load_reg_279;
res_V_we0_assign_proc : process(ap_CS_fsm_state9)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
res_V_we0 <= ap_const_logic_1;
else
res_V_we0 <= ap_const_logic_0;
end if;
end process;
tmp1_cast_fu_216_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp1_fu_211_p2),12));
tmp1_fu_211_p2 <= std_logic_vector(unsigned(tmp_128_cast_cast_reg_256) + unsigned(k_cast4_cast_fu_195_p1));
tmp_128_cast_cast_fu_191_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_82_fu_183_p3),9));
tmp_82_fu_183_p3 <= (j_reg_109 & ap_const_lv4_0);
tmp_83_fu_199_p2 <= "1" when (k_reg_121 = ap_const_lv5_10) else "0";
tmp_84_fu_220_p2 <= std_logic_vector(unsigned(tmp1_cast_fu_216_p1) + unsigned(phi_mul_reg_97));
tmp_85_fu_231_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_84_reg_269),64));
tmp_86_fu_226_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(k_reg_121),64));
tmp_fu_159_p2 <= "1" when (i_reg_85 = ap_const_lv4_D) else "0";
tmp_s_fu_171_p2 <= "1" when (j_reg_109 = ap_const_lv4_D) else "0";
end behav;
|
<gh_stars>100-1000
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: <NAME>
-- <NAME>
-- <NAME>
--
-- Package: Common functions and types
--
-- Description:
-- -------------------------------------
-- For detailed documentation see below.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.strings.all;
package vectors is
-- ==========================================================================
-- Type declarations
-- ==========================================================================
-- STD_LOGIC_VECTORs
subtype T_SLV_2 is std_logic_vector(1 downto 0);
subtype T_SLV_3 is std_logic_vector(2 downto 0);
subtype T_SLV_4 is std_logic_vector(3 downto 0);
subtype T_SLV_8 is std_logic_vector(7 downto 0);
subtype T_SLV_12 is std_logic_vector(11 downto 0);
subtype T_SLV_16 is std_logic_vector(15 downto 0);
subtype T_SLV_24 is std_logic_vector(23 downto 0);
subtype T_SLV_32 is std_logic_vector(31 downto 0);
subtype T_SLV_48 is std_logic_vector(47 downto 0);
subtype T_SLV_64 is std_logic_vector(63 downto 0);
subtype T_SLV_96 is std_logic_vector(95 downto 0);
subtype T_SLV_128 is std_logic_vector(127 downto 0);
subtype T_SLV_256 is std_logic_vector(255 downto 0);
subtype T_SLV_512 is std_logic_vector(511 downto 0);
-- STD_LOGIC_VECTOR_VECTORs
-- type T_SLVV is array(NATURAL range <>) of STD_LOGIC_VECTOR; -- VHDL 2008 syntax - not yet supported by Xilinx
type T_SLVV_2 is array(natural range <>) of T_SLV_2;
type T_SLVV_3 is array(natural range <>) of T_SLV_3;
type T_SLVV_4 is array(natural range <>) of T_SLV_4;
type T_SLVV_8 is array(natural range <>) of T_SLV_8;
type T_SLVV_12 is array(natural range <>) of T_SLV_12;
type T_SLVV_16 is array(natural range <>) of T_SLV_16;
type T_SLVV_24 is array(natural range <>) of T_SLV_24;
type T_SLVV_32 is array(natural range <>) of T_SLV_32;
type T_SLVV_48 is array(natural range <>) of T_SLV_48;
type T_SLVV_64 is array(natural range <>) of T_SLV_64;
type T_SLVV_128 is array(natural range <>) of T_SLV_128;
type T_SLVV_256 is array(natural range <>) of T_SLV_256;
type T_SLVV_512 is array(natural range <>) of T_SLV_512;
-- STD_LOGIC_MATRIXs
type T_SLM is array(natural range <>, natural range <>) of std_logic;
-- ATTENTION:
-- 1. you MUST initialize your matrix signal with 'Z' to get correct simulation results (iSIM, vSIM, ghdl/gtkwave)
-- Example: signal myMatrix : T_SLM(3 downto 0, 7 downto 0) := (others => (others => 'Z'));
-- 2. Xilinx iSIM bug: DON'T use myMatrix'range(n) for n >= 2
-- myMatrix'range(2) returns always myMatrix'range(1); see work-around notes below
--
-- USAGE NOTES:
-- dimension 1 => rows - e.g. Words
-- dimension 2 => columns - e.g. Bits/Bytes in a word
--
-- WORKAROUND: for Xilinx ISE/iSim
-- Version: 14.2
-- Issue: myMatrix'range(n) for n >= 2 returns always myMatrix'range(1)
-- ==========================================================================
-- Function declarations
-- ==========================================================================
-- slicing boundary calulations
function low (lenvec : T_POSVEC; index : natural) return natural;
function high(lenvec : T_POSVEC; index : natural) return natural;
-- Assign procedures: assign_*
procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural); -- assign vector to complete row
procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; Position : natural); -- assign short vector to row starting at position
procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; High : natural; Low : natural); -- assign short vector to row in range high:low
procedure assign_col(signal slm : out T_SLM; slv : std_logic_vector; constant ColIndex : natural); -- assign vector to complete column
-- ATTENTION: see T_SLM definition for further details and work-arounds
-- Matrix to matrix conversion: slm_slice*
function slm_slice(slm : T_SLM; RowIndex : natural; ColIndex : natural; Height : natural; Width : natural) return T_SLM; -- get submatrix in boundingbox RowIndex,ColIndex,Height,Width
function slm_slice_rows(slm : T_SLM; High : natural; Low : natural) return T_SLM; -- get submatrix / all rows in RowIndex range high:low
function slm_slice_cols(slm : T_SLM; High : natural; Low : natural) return T_SLM; -- get submatrix / all columns in ColIndex range high:low
-- Boolean Operators
function "not" (a : t_slm) return t_slm;
function "and" (a, b : t_slm) return t_slm;
function "or" (a, b : t_slm) return t_slm;
function "xor" (a, b : t_slm) return t_slm;
function "nand"(a, b : t_slm) return t_slm;
function "nor" (a, b : t_slm) return t_slm;
function "xnor"(a, b : t_slm) return t_slm;
-- Matrix concatenation: slm_merge_*
function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM;
function slm_merge_cols(slm1 : T_SLM; slm2 : T_SLM) return T_SLM;
-- Matrix to vector conversion: get_*
function get_col(slm : T_SLM; ColIndex : natural) return std_logic_vector; -- get a matrix column
function get_row(slm : T_SLM; RowIndex : natural) return std_logic_vector; -- get a matrix row
function get_row(slm : T_SLM; RowIndex : natural; Length : positive) return std_logic_vector; -- get a matrix row of defined length [length - 1 downto 0]
function get_row(slm : T_SLM; RowIndex : natural; High : natural; Low : natural) return std_logic_vector; -- get a sub vector of a matrix row at high:low
-- Convert to vector: to_slv
function to_slv(slvv : T_SLVV_2) return std_logic_vector; -- convert vector-vector to flatten vector
function to_slv(slvv : T_SLVV_4) return std_logic_vector; -- ...
function to_slv(slvv : T_SLVV_8) return std_logic_vector; -- ...
function to_slv(slvv : T_SLVV_12) return std_logic_vector; -- ...
function to_slv(slvv : T_SLVV_16) return std_logic_vector; -- ...
function to_slv(slvv : T_SLVV_24) return std_logic_vector; -- ...
function to_slv(slvv : T_SLVV_32) return std_logic_vector; -- ...
function to_slv(slvv : T_SLVV_64) return std_logic_vector; -- ...
function to_slv(slvv : T_SLVV_128) return std_logic_vector; -- ...
function to_slv(slm : T_SLM) return std_logic_vector; -- convert matrix to flatten vector
-- Convert flat vector to avector-vector: to_slvv_*
function to_slvv_4(slv : std_logic_vector) return T_SLVV_4; --
function to_slvv_8(slv : std_logic_vector) return T_SLVV_8; --
function to_slvv_12(slv : std_logic_vector) return T_SLVV_12; --
function to_slvv_16(slv : std_logic_vector) return T_SLVV_16; --
function to_slvv_32(slv : std_logic_vector) return T_SLVV_32; --
function to_slvv_64(slv : std_logic_vector) return T_SLVV_64; --
function to_slvv_128(slv : std_logic_vector) return T_SLVV_128; --
function to_slvv_256(slv : std_logic_vector) return T_SLVV_256; --
function to_slvv_512(slv : std_logic_vector) return T_SLVV_512; --
-- Convert matrix to avector-vector: to_slvv_*
function to_slvv_4(slm : T_SLM) return T_SLVV_4; --
function to_slvv_8(slm : T_SLM) return T_SLVV_8; --
function to_slvv_12(slm : T_SLM) return T_SLVV_12; --
function to_slvv_16(slm : T_SLM) return T_SLVV_16; --
function to_slvv_32(slm : T_SLM) return T_SLVV_32; --
function to_slvv_64(slm : T_SLM) return T_SLVV_64; --
function to_slvv_128(slm : T_SLM) return T_SLVV_128; --
function to_slvv_256(slm : T_SLM) return T_SLVV_256; --
function to_slvv_512(slm : T_SLM) return T_SLVV_512; --
-- Convert vector-vector to matrix: to_slm
function to_slm(slv : std_logic_vector; ROWS : positive; COLS : positive) return T_SLM; -- create matrix from vector
function to_slm(slvv : T_SLVV_4) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_8) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_12) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_16) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_32) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_48) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_64) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_128) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_256) return T_SLM; -- create matrix from vector-vector
function to_slm(slvv : T_SLVV_512) return T_SLM; -- create matrix from vector-vector
-- Change vector direction
function dir(slvv : T_SLVV_8) return T_SLVV_8;
-- Reverse vector elements
function rev(slvv : T_SLVV_4) return T_SLVV_4;
function rev(slvv : T_SLVV_8) return T_SLVV_8;
function rev(slvv : T_SLVV_12) return T_SLVV_12;
function rev(slvv : T_SLVV_16) return T_SLVV_16;
function rev(slvv : T_SLVV_32) return T_SLVV_32;
function rev(slvv : T_SLVV_64) return T_SLVV_64;
function rev(slvv : T_SLVV_128) return T_SLVV_128;
function rev(slvv : T_SLVV_256) return T_SLVV_256;
function rev(slvv : T_SLVV_512) return T_SLVV_512;
-- TODO:
function resize(slm : T_SLM; size : positive) return T_SLM;
-- to_string
function to_string(slvv : T_SLVV_8; sep : character := ':') return string;
function to_string(slm : T_SLM; groups : positive := 4; format : character := 'b') return string;
end package vectors;
package body vectors is
-- slicing boundary calulations
-- ==========================================================================
function low(lenvec : T_POSVEC; index : natural) return natural is
variable pos : natural := 0;
begin
for i in lenvec'low to index - 1 loop
pos := pos + lenvec(i);
end loop;
return pos;
end function;
function high(lenvec : T_POSVEC; index : natural) return natural is
variable pos : natural := 0;
begin
for i in lenvec'low to index loop
pos := pos + lenvec(i);
end loop;
return pos - 1;
end function;
-- Assign procedures: assign_*
-- ==========================================================================
procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural) is
variable temp : std_logic_vector(slm'high(2) downto slm'low(2)); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; Position : natural) is
variable temp : std_logic_vector(Position + slv'length - 1 downto Position);
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
procedure assign_row(signal slm : out T_SLM; slv : std_logic_vector; constant RowIndex : natural; High : natural; Low : natural) is
variable temp : std_logic_vector(High downto Low);
begin
temp := slv;
for i in temp'range loop
slm(RowIndex, i) <= temp(i);
end loop;
end procedure;
procedure assign_col(signal slm : out T_SLM; slv : std_logic_vector; constant ColIndex : natural) is
variable temp : std_logic_vector(slm'range(1));
begin
temp := slv;
for i in temp'range loop
slm(i, ColIndex) <= temp(i);
end loop;
end procedure;
-- Matrix to matrix conversion: slm_slice*
-- ==========================================================================
function slm_slice(slm : T_SLM; RowIndex : natural; ColIndex : natural; Height : natural; Width : natural) return T_SLM is
variable Result : T_SLM(Height - 1 downto 0, Width - 1 downto 0) := (others => (others => '0'));
begin
for i in 0 to Height - 1 loop
for j in 0 to Width - 1 loop
Result(i, j) := slm(RowIndex + i, ColIndex + j);
end loop;
end loop;
return Result;
end function;
function slm_slice_rows(slm : T_SLM; High : natural; Low : natural) return T_SLM is
variable Result : T_SLM(High - Low downto 0, slm'length(2) - 1 downto 0) := (others => (others => '0'));
begin
for i in 0 to High - Low loop
for j in 0 to slm'length(2) - 1 loop
Result(i, j) := slm(Low + i, slm'low(2) + j);
end loop;
end loop;
return Result;
end function;
function slm_slice_cols(slm : T_SLM; High : natural; Low : natural) return T_SLM is
variable Result : T_SLM(slm'length(1) - 1 downto 0, High - Low downto 0) := (others => (others => '0'));
begin
for i in 0 to slm'length(1) - 1 loop
for j in 0 to High - Low loop
Result(i, j) := slm(slm'low(1) + i, Low + j);
end loop;
end loop;
return Result;
end function;
-- Boolean Operators
function "not"(a : t_slm) return t_slm is
variable res : t_slm(a'range(1), a'range(2));
begin
for i in res'range(1) loop
for j in res'range(2) loop
res(i, j) := not a(i, j);
end loop;
end loop;
return res;
end function;
function "and"(a, b : t_slm) return t_slm is
variable bb, res : t_slm(a'range(1), a'range(2));
begin
bb := b;
for i in res'range(1) loop
for j in res'range(2) loop
res(i, j) := a(i, j) and bb(i, j);
end loop;
end loop;
return res;
end function;
function "or"(a, b : t_slm) return t_slm is
variable bb, res : t_slm(a'range(1), a'range(2));
begin
bb := b;
for i in res'range(1) loop
for j in res'range(2) loop
res(i, j) := a(i, j) or bb(i, j);
end loop;
end loop;
return res;
end function;
function "xor"(a, b : t_slm) return t_slm is
variable bb, res : t_slm(a'range(1), a'range(2));
begin
bb := b;
for i in res'range(1) loop
for j in res'range(2) loop
res(i, j) := a(i, j) xor bb(i, j);
end loop;
end loop;
return res;
end function;
function "nand"(a, b : t_slm) return t_slm is
begin
return not(a and b);
end function;
function "nor"(a, b : t_slm) return t_slm is
begin
return not(a or b);
end function;
function "xnor"(a, b : t_slm) return t_slm is
begin
return not(a xor b);
end function;
-- Matrix concatenation: slm_merge_*
function slm_merge_rows(slm1 : T_SLM; slm2 : T_SLM) return T_SLM is
constant ROWS : positive := slm1'length(1) + slm2'length(1);
constant COLUMNS : positive := slm1'length(2);
variable slm : T_SLM(ROWS - 1 downto 0, COLUMNS - 1 downto 0);
begin
for i in slm1'range(1) loop
for j in slm1'low(2) to slm1'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
slm(i, j) := slm1(i, j);
end loop;
end loop;
for i in slm2'range(1) loop
for j in slm2'low(2) to slm2'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
slm(slm1'length(1) + i, j) := slm2(i, j);
end loop;
end loop;
return slm;
end function;
function slm_merge_cols(slm1 : T_SLM; slm2 : T_SLM) return T_SLM is
constant ROWS : positive := slm1'length(1);
constant COLUMNS : positive := slm1'length(2) + slm2'length(2);
variable slm : T_SLM(ROWS - 1 downto 0, COLUMNS - 1 downto 0);
begin
for i in slm1'range(1) loop
for j in slm1'low(2) to slm1'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
slm(i, j) := slm1(i, j);
end loop;
for j in slm2'low(2) to slm2'high(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
slm(i, slm1'length(2) + j) := slm2(i, j);
end loop;
end loop;
return slm;
end function;
-- Matrix to vector conversion: get_*
-- ==========================================================================
-- get a matrix column
function get_col(slm : T_SLM; ColIndex : natural) return std_logic_vector is
variable slv : std_logic_vector(slm'range(1));
begin
for i in slm'range(1) loop
slv(i) := slm(i, ColIndex);
end loop;
return slv;
end function;
-- get a matrix row
function get_row(slm : T_SLM; RowIndex : natural) return std_logic_vector is
variable slv : std_logic_vector(slm'high(2) downto slm'low(2)); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
begin
for i in slv'range loop
slv(i) := slm(RowIndex, i);
end loop;
return slv;
end function;
-- get a matrix row of defined length [length - 1 downto 0]
function get_row(slm : T_SLM; RowIndex : natural; Length : positive) return std_logic_vector is
begin
return get_row(slm, RowIndex, (Length - 1), 0);
end function;
-- get a sub vector of a matrix row at high:low
function get_row(slm : T_SLM; RowIndex : natural; High : natural; Low : natural) return std_logic_vector is
variable slv : std_logic_vector(High downto Low);
begin
for i in slv'range loop
slv(i) := slm(RowIndex, i);
end loop;
return slv;
end function;
-- Convert to vector: to_slv
-- ==========================================================================
-- convert vector-vector to flatten vector
function to_slv(slvv : T_SLVV_2) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 2) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 2) + 1 downto (i * 2)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_4) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 4) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 4) + 3 downto (i * 4)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_8) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 8) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 8) + 7 downto (i * 8)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_12) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 12) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 12) + 11 downto (i * 12)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_16) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 16) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 16) + 15 downto (i * 16)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_24) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 24) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 24) + 23 downto (i * 24)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_32) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 32) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 32) + 31 downto (i * 32)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_64) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 64) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 64) + 63 downto (i * 64)) := slvv(i);
end loop;
return slv;
end function;
function to_slv(slvv : T_SLVV_128) return std_logic_vector is
variable slv : std_logic_vector((slvv'length * 128) - 1 downto 0);
begin
for i in slvv'range loop
slv((i * 128) + 127 downto (i * 128)) := slvv(i);
end loop;
return slv;
end function;
-- convert matrix to flatten vector
function to_slv(slm : T_SLM) return std_logic_vector is
variable slv : std_logic_vector((slm'length(1) * slm'length(2)) - 1 downto 0);
begin
for i in slm'range(1) loop
for j in slm'high(2) downto slm'low(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
slv((i * slm'length(2)) + j) := slm(i, j);
end loop;
end loop;
return slv;
end function;
-- Convert flat vector to a vector-vector: to_slvv_*
-- ==========================================================================
-- create vector-vector from vector (4 bit)
function to_slvv_4(slv : std_logic_vector) return T_SLVV_4 is
variable Result : T_SLVV_4((slv'length / 4) - 1 downto 0);
begin
if ((slv'length mod 4) /= 0) then report "to_slvv_4: width mismatch - slv'length is no multiple of 4 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 4) + 3 downto (i * 4));
end loop;
return Result;
end function;
-- create vector-vector from vector (8 bit)
function to_slvv_8(slv : std_logic_vector) return T_SLVV_8 is
variable Result : T_SLVV_8((slv'length / 8) - 1 downto 0);
begin
if ((slv'length mod 8) /= 0) then report "to_slvv_8: width mismatch - slv'length is no multiple of 8 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 8) + 7 downto (i * 8));
end loop;
return Result;
end function;
-- create vector-vector from vector (12 bit)
function to_slvv_12(slv : std_logic_vector) return T_SLVV_12 is
variable Result : T_SLVV_12((slv'length / 12) - 1 downto 0);
begin
if ((slv'length mod 12) /= 0) then report "to_slvv_12: width mismatch - slv'length is no multiple of 12 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 12) + 11 downto (i * 12));
end loop;
return Result;
end function;
-- create vector-vector from vector (16 bit)
function to_slvv_16(slv : std_logic_vector) return T_SLVV_16 is
variable Result : T_SLVV_16((slv'length / 16) - 1 downto 0);
begin
if ((slv'length mod 16) /= 0) then report "to_slvv_16: width mismatch - slv'length is no multiple of 16 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 16) + 15 downto (i * 16));
end loop;
return Result;
end function;
-- create vector-vector from vector (32 bit)
function to_slvv_32(slv : std_logic_vector) return T_SLVV_32 is
variable Result : T_SLVV_32((slv'length / 32) - 1 downto 0);
begin
if ((slv'length mod 32) /= 0) then report "to_slvv_32: width mismatch - slv'length is no multiple of 32 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 32) + 31 downto (i * 32));
end loop;
return Result;
end function;
-- create vector-vector from vector (64 bit)
function to_slvv_64(slv : std_logic_vector) return T_SLVV_64 is
variable Result : T_SLVV_64((slv'length / 64) - 1 downto 0);
begin
if ((slv'length mod 64) /= 0) then report "to_slvv_64: width mismatch - slv'length is no multiple of 64 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 64) + 63 downto (i * 64));
end loop;
return Result;
end function;
-- create vector-vector from vector (128 bit)
function to_slvv_128(slv : std_logic_vector) return T_SLVV_128 is
variable Result : T_SLVV_128((slv'length / 128) - 1 downto 0);
begin
if ((slv'length mod 128) /= 0) then report "to_slvv_128: width mismatch - slv'length is no multiple of 128 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 128) + 127 downto (i * 128));
end loop;
return Result;
end function;
-- create vector-vector from vector (256 bit)
function to_slvv_256(slv : std_logic_vector) return T_SLVV_256 is
variable Result : T_SLVV_256((slv'length / 256) - 1 downto 0);
begin
if ((slv'length mod 256) /= 0) then report "to_slvv_256: width mismatch - slv'length is no multiple of 256 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 256) + 255 downto (i * 256));
end loop;
return Result;
end function;
-- create vector-vector from vector (512 bit)
function to_slvv_512(slv : std_logic_vector) return T_SLVV_512 is
variable Result : T_SLVV_512((slv'length / 512) - 1 downto 0);
begin
if ((slv'length mod 512) /= 0) then report "to_slvv_512: width mismatch - slv'length is no multiple of 512 (slv'length=" & INTEGER'image(slv'length) & ")" severity FAILURE; end if;
for i in Result'range loop
Result(i) := slv((i * 512) + 511 downto (i * 512));
end loop;
return Result;
end function;
-- Convert matrix to avector-vector: to_slvv_*
-- ==========================================================================
-- create vector-vector from matrix (4 bit)
function to_slvv_4(slm : T_SLM) return T_SLVV_4 is
variable Result : T_SLVV_4(slm'range(1));
begin
if (slm'length(2) /= 4) then report "to_slvv_4: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (8 bit)
function to_slvv_8(slm : T_SLM) return T_SLVV_8 is
variable Result : T_SLVV_8(slm'range(1));
begin
if (slm'length(2) /= 8) then report "to_slvv_8: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (12 bit)
function to_slvv_12(slm : T_SLM) return T_SLVV_12 is
variable Result : T_SLVV_12(slm'range(1));
begin
if (slm'length(2) /= 12) then report "to_slvv_12: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (16 bit)
function to_slvv_16(slm : T_SLM) return T_SLVV_16 is
variable Result : T_SLVV_16(slm'range(1));
begin
if (slm'length(2) /= 16) then report "to_slvv_16: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (32 bit)
function to_slvv_32(slm : T_SLM) return T_SLVV_32 is
variable Result : T_SLVV_32(slm'range(1));
begin
if (slm'length(2) /= 32) then report "to_slvv_32: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (64 bit)
function to_slvv_64(slm : T_SLM) return T_SLVV_64 is
variable Result : T_SLVV_64(slm'range(1));
begin
if (slm'length(2) /= 64) then report "to_slvv_64: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (128 bit)
function to_slvv_128(slm : T_SLM) return T_SLVV_128 is
variable Result : T_SLVV_128(slm'range(1));
begin
if (slm'length(2) /= 128) then report "to_slvv_128: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (256 bit)
function to_slvv_256(slm : T_SLM) return T_SLVV_256 is
variable Result : T_SLVV_256(slm'range);
begin
if (slm'length(2) /= 256) then report "to_slvv_256: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- create vector-vector from matrix (512 bit)
function to_slvv_512(slm : T_SLM) return T_SLVV_512 is
variable Result : T_SLVV_512(slm'range(1));
begin
if (slm'length(2) /= 512) then report "to_slvv_512: type mismatch - slm'length(2)=" & integer'image(slm'length(2)) severity FAILURE; end if;
for i in slm'range(1) loop
Result(i) := get_row(slm, i);
end loop;
return Result;
end function;
-- Convert vector-vector to matrix: to_slm
-- ==========================================================================
-- create matrix from vector
function to_slm(slv : std_logic_vector; ROWS : positive; COLS : positive) return T_SLM is
variable slm : T_SLM(ROWS - 1 downto 0, COLS - 1 downto 0);
begin
for i in 0 to ROWS - 1 loop
for j in 0 to COLS - 1 loop
slm(i, j) := slv((i * COLS) + j);
end loop;
end loop;
return slm;
end function;
-- create matrix from vector-vector
function to_slm(slvv : T_SLVV_4) return T_SLM is
variable slm : T_SLM(slvv'range, 3 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_4'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_8) return T_SLM is
-- variable test : STD_LOGIC_VECTOR(T_SLV_8'range);
-- variable slm : T_SLM(slvv'range, test'range); -- BUG: iSIM 14.5 cascaded 'range accesses let iSIM break down
-- variable slm : T_SLM(slvv'range, T_SLV_8'range); -- BUG: iSIM 14.5 allocates 9 bits in dimension 2
variable slm : T_SLM(slvv'range, 7 downto 0); -- WORKAROUND: use constant range
begin
-- report "slvv: slvv.length=" & INTEGER'image(slvv'length) & " slm.dim0.length=" & INTEGER'image(slm'length(1)) & " slm.dim1.length=" & INTEGER'image(slm'length(2)) severity NOTE;
-- report "T_SLV_8: .length=" & INTEGER'image(T_SLV_8'length) & " .high=" & INTEGER'image(T_SLV_8'high) & " .low=" & INTEGER'image(T_SLV_8'low) severity NOTE;
-- report "test: test.length=" & INTEGER'image(test'length) & " .high=" & INTEGER'image(test'high) & " .low=" & INTEGER'image(test'low) severity NOTE;
for i in slvv'range loop
for j in T_SLV_8'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_12) return T_SLM is
variable slm : T_SLM(slvv'range, 11 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_12'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_16) return T_SLM is
variable slm : T_SLM(slvv'range, 15 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_16'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_32) return T_SLM is
variable slm : T_SLM(slvv'range, 31 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_32'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_48) return T_SLM is
variable slm : T_SLM(slvv'range, 47 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_48'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_64) return T_SLM is
variable slm : T_SLM(slvv'range, 63 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_64'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_128) return T_SLM is
variable slm : T_SLM(slvv'range, 127 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_128'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_256) return T_SLM is
variable slm : T_SLM(slvv'range, 255 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_256'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
function to_slm(slvv : T_SLVV_512) return T_SLM is
variable slm : T_SLM(slvv'range, 511 downto 0);
begin
for i in slvv'range loop
for j in T_SLV_512'range loop
slm(i, j) := slvv(i)(j);
end loop;
end loop;
return slm;
end function;
-- Change vector direction
-- ==========================================================================
function dir(slvv : T_SLVV_8) return T_SLVV_8 is
variable Result : T_SLVV_8(slvv'reverse_range);
begin
Result := slvv;
return Result;
end function;
-- Reverse vector elements
function rev(slvv : T_SLVV_4) return T_SLVV_4 is
variable Result : T_SLVV_4(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_8) return T_SLVV_8 is
variable Result : T_SLVV_8(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_12) return T_SLVV_12 is
variable Result : T_SLVV_12(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_16) return T_SLVV_16 is
variable Result : T_SLVV_16(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_32) return T_SLVV_32 is
variable Result : T_SLVV_32(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_64) return T_SLVV_64 is
variable Result : T_SLVV_64(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_128) return T_SLVV_128 is
variable Result : T_SLVV_128(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_256) return T_SLVV_256 is
variable Result : T_SLVV_256(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
function rev(slvv : T_SLVV_512) return T_SLVV_512 is
variable Result : T_SLVV_512(slvv'range);
begin
for i in slvv'low to slvv'high loop
Result(slvv'high - i) := slvv(i);
end loop;
return Result;
end function;
-- Resize functions
-- ==========================================================================
-- Resizes the vector to the specified length. Input vectors larger than the specified size are truncated from the left side. Smaller input
-- vectors are extended on the left by the provided fill value (default: '0'). Use the resize functions of the numeric_std package for
-- value-preserving resizes of the signed and unsigned data types.
function resize(slm : T_SLM; size : positive) return T_SLM is
variable Result : T_SLM(size - 1 downto 0, slm'high(2) downto slm'low(2)) := (others => (others => '0')); -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
begin
for i in slm'range(1) loop
for j in slm'high(2) downto slm'low(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
Result(i, j) := slm(i, j);
end loop;
end loop;
return Result;
end function;
function to_string(slvv : T_SLVV_8; sep : character := ':') return string is
constant hex_len : positive := ite((sep = C_POC_NUL), (slvv'length * 2), (slvv'length * 3) - 1);
variable Result : string(1 to hex_len) := (others => sep);
variable pos : positive := 1;
begin
for i in slvv'range loop
Result(pos to pos + 1) := to_string(slvv(i), 'h');
pos := pos + ite((sep = C_POC_NUL), 2, 3);
end loop;
return Result;
end function;
function to_string_bin(slm : T_SLM; groups : positive := 4; format : character := 'h') return string is
variable PerLineOverheader : positive := div_ceil(slm'length(2), groups);
variable Result : string(1 to (slm'length(1) * (slm'length(2) + PerLineOverheader)) + 10);
variable Writer : positive;
variable GroupCounter : natural;
begin
Result := (others => C_POC_NUL);
Result(1) := LF;
Writer := 2;
GroupCounter := 0;
for i in slm'low(1) to slm'high(1) loop
for j in slm'high(2) downto slm'low(2) loop -- WORKAROUND: Xilinx iSIM work-around, because 'range(2) evaluates to 'range(1); see work-around notes at T_SLM type declaration
Result(Writer) := to_char(slm(i, j));
Writer := Writer + 1;
GroupCounter := GroupCounter + 1;
if GroupCounter = groups then
Result(Writer) := ' ';
Writer := Writer + 1;
GroupCounter := 0;
end if;
end loop;
Result(Writer - 1) := LF;
GroupCounter := 0;
end loop;
return str_trim(Result);
end function;
function to_string(slm : T_SLM; groups : positive := 4; format : character := 'b') return string is
begin
if (format = 'b') then
return to_string_bin(slm, groups);
else
return "Format not supported.";
end if;
end function;
end package body;
|
<reponame>zz-systems/Plasma-SoC<gh_stars>0
---------------------------------------------------------------------
-- TITLE: Bus Multiplexer / Signal Router
-- AUTHOR: <NAME> (<EMAIL>)
-- DATE CREATED: 2/8/01
-- FILENAME: bus_mux.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity is the main signal router.
-- It multiplexes signals from multiple sources to the correct location.
-- The outputs are as follows:
-- a_bus : goes to the ALU
-- b_bus : goes to the ALU
-- reg_dest_out : goes to the register bank
-- take_branch : goes to pc_next
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library plasma_lib;
use plasma_lib.mlite_pack.all;
entity bus_mux is
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end; --entity bus_mux
architecture logic of bus_mux is
begin
--Determine value of a_bus
amux: process(reg_source, imm_in, a_mux, c_pc)
begin
case a_mux is
when A_FROM_REG_SOURCE =>
a_out <= reg_source;
when A_FROM_IMM10_6 =>
a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
when A_FROM_PC =>
a_out <= c_pc & "00";
when others =>
a_out <= c_pc & "00";
end case;
end process;
--Determine value of b_bus
bmux: process(reg_target, imm_in, b_mux)
begin
case b_mux is
when B_FROM_REG_TARGET =>
b_out <= reg_target;
when B_FROM_IMM =>
b_out <= ZERO(31 downto 16) & imm_in;
when B_FROM_SIGNED_IMM =>
if imm_in(15) = '0' then
b_out(31 downto 16) <= ZERO(31 downto 16);
else
b_out(31 downto 16) <= "1111111111111111";
end if;
b_out(15 downto 0) <= imm_in;
when B_FROM_IMMX4 =>
if imm_in(15) = '0' then
b_out(31 downto 18) <= "00000000000000";
else
b_out(31 downto 18) <= "11111111111111";
end if;
b_out(17 downto 0) <= imm_in & "00";
when others =>
b_out <= reg_target;
end case;
end process;
--Determine value of c_bus
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
begin
case c_mux is
when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
reg_dest_out <= c_bus;
when C_FROM_MEMORY =>
reg_dest_out <= c_memory;
when C_FROM_PC =>
reg_dest_out <= c_pc(31 downto 2) & "00";
when C_FROM_PC_PLUS4 =>
reg_dest_out <= c_pc_plus4 & "00";
when C_FROM_IMM_SHIFT16 =>
reg_dest_out <= imm_in & ZERO(15 downto 0);
when others =>
reg_dest_out <= c_bus;
end case;
end process;
--Determine value of take_branch
pc_mux: process(branch_func, reg_source, reg_target)
variable is_equal : std_logic;
begin
if reg_source = reg_target then
is_equal := '1';
else
is_equal := '0';
end if;
case branch_func is
when BRANCH_LTZ =>
take_branch <= reg_source(31);
when BRANCH_LEZ =>
take_branch <= reg_source(31) or is_equal;
when BRANCH_EQ =>
take_branch <= is_equal;
when BRANCH_NE =>
take_branch <= not is_equal;
when BRANCH_GEZ =>
take_branch <= not reg_source(31);
when BRANCH_GTZ =>
take_branch <= not reg_source(31) and not is_equal;
when BRANCH_YES =>
take_branch <= '1';
when others =>
take_branch <= '0';
end case;
end process;
end; --architecture logic
|
<filename>testbenches/mux8_16bit_tb.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux8_16bit_tb is
-- Port ( );
end mux8_16bit_tb;
architecture Behavioral of mux8_16bit_tb is
-- declare component to test
component mux8_16bit is
Port (
In0 : in std_logic_vector(15 downto 0);
In1 : in std_logic_vector(15 downto 0);
In2 : in std_logic_vector(15 downto 0);
In3 : in std_logic_vector(15 downto 0);
In4 : in std_logic_vector(15 downto 0);
In5 : in std_logic_vector(15 downto 0);
In6 : in std_logic_vector(15 downto 0);
In7 : in std_logic_vector(15 downto 0);
src : in std_logic_vector(2 downto 0);
Z : out std_logic_vector(15 downto 0)
);
end component;
-- signals for tests (initialise to 0)
--inputs
signal In0 : std_logic_vector(15 downto 0):= x"0000";
signal In1 : std_logic_vector(15 downto 0):= x"0000";
signal In2 : std_logic_vector(15 downto 0):= x"0000";
signal In3 : std_logic_vector(15 downto 0):= x"0000";
signal In4 : std_logic_vector(15 downto 0):= x"0000";
signal In5 : std_logic_vector(15 downto 0):= x"0000";
signal In6 : std_logic_vector(15 downto 0):= x"0000";
signal In7 : std_logic_vector(15 downto 0):= x"0000";
signal src : std_logic_vector(2 downto 0) := "000";
--outputs
signal Z : std_logic_vector(15 downto 0):= x"0000";
begin
-- instantiate component for test, connect ports to internal signals
UUT: mux8_16bit
Port Map(
In0 => In0,
In1 => In1,
In2 => In2,
In3 => In3,
In4 => In4,
In5 => In5,
In6 => In6,
In7 => In7,
src => src,
Z => Z
);
simulation_process :process
begin
--Give inputs unique values
In0 <= x"00AA";
In1 <= x"00BB";
In2 <= x"00CC";
In3 <= x"00DD";
In4 <= x"00EE";
In5 <= x"00FF";
In6 <= x"0AAA";
In7 <= x"0BBB";
--Select line 0 and send 0x00AA to output line Z
src <= "000";
wait for 1ns;
--Select line 1 and send 0x00BB to output line Z
src <= "001";
wait for 1ns;
--Select line 2 and send 0x00CC to output line Z
src <= "010";
wait for 1ns;
--Select line 3 and send 0x00DD to output line Z
src <= "011";
wait for 1ns;
--Select line 4 and send 0x00EE to output line Z
src <= "100";
wait for 1ns;
--Select line 5 and send 0x00FF to output line Z
src <= "101";
wait for 1ns;
--Select line 6 and send 0x0AAA to output line Z
src <= "110";
wait for 1ns;
--Select line 7 and send 0x0BBB to output line Z
src <= "111";
wait for 1ns;
end process;
end Behavioral;
|
<reponame>Chuckboliver/DankEngine<filename>phol/DigitalProject/move_12bits_7seg_decoder.vhd
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity move_12bits_to_7seg is
generic(
CLKS_PER_Round:integer:= 2083
);
Port(
first_Move_IN:in STD_LOGIC_VECTOR (2 downto 0);
second_Move_IN:in STD_LOGIC_VECTOR (2 downto 0);
third_Move_IN:in STD_LOGIC_VECTOR (2 downto 0);
forth_Move_IN:in STD_LOGIC_VECTOR (2 downto 0);
clock:in std_logic;
out_7seg:out STD_LOGIC_VECTOR (6 downto 0);
common:out STD_LOGIC_VECTOR (3 downto 0)
);
end move_12bits_to_7seg;
architecture Behavioral of move_12bits_to_7seg is
type all_States is(first, second,third,forth);
signal state : all_States:=first;
signal Clk_Count:integer range 0 to CLKS_PER_Round-1:=0;
begin
decoder:process(clock)
begin
if rising_edge(clock) then
case state is
when first =>
if Clk_Count<CLKS_PER_Round-1 then
Clk_Count<=Clk_Count+1;
common<="0111";
case first_Move_IN is
when "000"=>
out_7seg<="1110111";
when "001"=>
out_7seg<="0011111";
when "010"=>
out_7seg<="1001110";
when "011"=>
out_7seg<="0111101";
when "100"=>
out_7seg<="1001111";
when "101"=>
out_7seg<="1000111";
when "110"=>
out_7seg<="1111011";
when "111"=>
out_7seg<="0110111";
when others=>
out_7seg<="0000000";
end case;
else
Clk_Count<=0;
state<=second;
end if;
when second=>
if Clk_Count<CLKS_PER_Round-1 then
Clk_Count<=Clk_Count+1;
common<="1011";
case second_Move_IN is
when "000"=>
out_7seg<="0110000";
when "001"=>
out_7seg<="1101101";
when "010"=>
out_7seg<="1111001";
when "011"=>
out_7seg<="0110011";
when "100"=>
out_7seg<="1011011";
when "101"=>
out_7seg<="1011111";
when "110"=>
out_7seg<="1110000";
when "111"=>
out_7seg<="1111111";
when others=>
out_7seg<="0000000";
end case;
else
Clk_Count<=0;
state<=third;
end if;
when third=>
if Clk_Count<CLKS_PER_Round-1 then
Clk_Count<=Clk_Count+1;
common<="1101";
case third_Move_IN is
when "000"=>
out_7seg<="1110111";
when "001"=>
out_7seg<="0011111";
when "010"=>
out_7seg<="1001110";
when "011"=>
out_7seg<="0111101";
when "100"=>
out_7seg<="1001111";
when "101"=>
out_7seg<="1000111";
when "110"=>
out_7seg<="1111011";
when "111"=>
out_7seg<="0110111";
when others=>
out_7seg<="0000000";
end case;
else
Clk_Count<=0;
state<=forth;
end if;
when forth=>
if Clk_Count<CLKS_PER_Round-1 then
Clk_Count<=Clk_Count+1;
common<="1110";
case forth_Move_IN is
when "000"=>
out_7seg<="0110000";
when "001"=>
out_7seg<="1101101";
when "010"=>
out_7seg<="1111001";
when "011"=>
out_7seg<="0110011";
when "100"=>
out_7seg<="1011011";
when "101"=>
out_7seg<="1011111";
when "110"=>
out_7seg<="1110000";
when "111"=>
out_7seg<="1111111";
when others=>
out_7seg<="0000000";
end case;
else
Clk_Count<=0;
state<=first;
end if;
end case;
end if;
end process decoder;
end Behavioral;
|
<filename>vhdl/src/rf_blocks_tb/costas_loop_tb.vhd
--! @file poly_dds_tb.vhd
--! @brief Polyphase Direct Digital Synthesizer Testbench
--! @author <NAME> (<EMAIL>)
--! @date 2013-12-17
--! @copyright
--! Copyright 2013 <NAME>, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library boostdsp;
use boostdsp.fixed_pkg.all;
use boostdsp.util_pkg.all;
use boostdsp.basic_pkg;
use boostdsp.rf_blocks_pkg;
entity costas_loop_tb is
end entity;
architecture sim of costas_loop_tb is
constant clk_p : time := 10 ns;
constant clk_hp : time := clk_p / 2;
constant freq_init : ufixed(-1 downto -10) := to_ufixed(0.1, -1, -10);
constant phase_init : ufixed(-1 downto -10) := to_ufixed(0, -1, -10);
constant phase_track : ufixed(-1 downto -10) := to_ufixed(0, -1, -10);
constant REAL_COEFFS_EVEN : real_vector(0 to 63) := (
-0.0007796429301286012, -0.0003156007529416889, 0.0005104741442584588,
0.001115485185756897, 0.0008643801790044494, -0.0003846385387076593,
-0.00183918445351239, -0.002077420576641017, -0.0002510365880192294,
0.002695337022541216, 0.004184383430860367, 0.002031565039549675,
-0.00306899653280024, -0.007098961443542058, -0.005582520200756744,
0.00200818527942565, 0.01030833822049713, 0.01138895742129619,
0.001745680998188937, -0.01281040110449648, -0.01978810419497967,
-0.009911152225648579, 0.01298352224579553, 0.03131851689393891,
0.02568859991818818, -0.007811875644557511, -0.0484513087840436,
-0.05967613596766252, -0.01288337785600386, 0.08935832005638873,
0.2082005359335768, 0.2877613466436248, 0.2877613466436248,
0.2082005359335768, 0.08935832005638873, -0.01288337785600386,
-0.05967613596766252, -0.04845130878404361, -0.007811875644557514,
0.02568859991818819, 0.03131851689393892, 0.01298352224579553,
-0.009911152225648576, -0.01978810419497967, -0.01281040110449649,
0.001745680998188937, 0.0113889574212962, 0.01030833822049713,
0.002008185279425651, -0.005582520200756746, -0.007098961443542059,
-0.003068996532800242, 0.002031565039549676, 0.004184383430860365,
0.002695337022541217, -0.0002510365880192294, -0.002077420576641019,
-0.001839184453512392, -0.0003846385387076598, 0.0008643801790044497,
0.001115485185756897, 0.0005104741442584587, -0.0003156007529416892,
-0.0007796429301286012);
constant FIR_COEFFS : sfixed_vector(0 to 31)(0 downto -15) :=
to_sfixed_vector(REAL_COEFFS_EVEN(0 to 31), 0, -15);
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal i_in : sfixed(1 downto -10);
signal q_in : sfixed(1 downto -10);
signal i_out : sfixed(1 downto -10);
signal q_out : sfixed(1 downto -10);
signal i_down : sfixed(1 downto -10) := to_sfixed(0, 1, -10);
signal q_down : sfixed(1 downto -10) := to_sfixed(0, 1, -10);
signal mix_down : sfixed(1 downto -10) := to_sfixed(0, 1, -10);
signal freq_track : sfixed(-1 downto -10);
signal u_freq_track : ufixed(-1 downto -10) := to_ufixed(0.05, -1, -10);
signal vis_i_in : signed(11 downto 0);
signal vis_q_in : signed(11 downto 0);
signal vis_i_out : signed(11 downto 0);
signal vis_q_out : signed(11 downto 0);
signal vis_freq_track : signed(9 downto 0);
begin
dds_main : rf_blocks_pkg.dds
port map (
clk => clk,
rst => rst,
freq => freq_init,
phase => phase_init,
i_out => i_in,
q_out => q_in
);
dds_track : rf_blocks_pkg.dds
port map (
clk => clk,
rst => rst,
freq => u_freq_track,
phase => phase_track,
i_out => i_out,
q_out => q_out
);
u_freq_track <= to_ufixed(freq_track);
loop_filter : basic_pkg.fir
generic map (
SYMMETRIC => true,
EVEN => true,
UPPER_BIT => 11,
LOWER_BIT => -18
)
port map (
clk => clk,
rst => rst,
coeff => FIR_COEFFS,
din => mix_down,
dout => freq_track
);
clk_proc : process
begin
wait for clk_hp;
clk <= not clk;
end process;
rst_proc : process
begin
wait for clk_p * 4;
rst <= '0';
wait;
end process;
mixers : process
begin
wait until rising_edge(clk);
i_down <= resize(i_in * i_out, i_down'high, i_down'low);
q_down <= resize(q_in * q_out, q_down'high, q_down'low);
mix_down <= resize(i_down * q_down, mix_down'high, mix_down'low);
end process;
vis_i_in <= sfixed_as_signed(i_in);
vis_q_in <= sfixed_as_signed(q_in);
vis_i_out <= sfixed_as_signed(i_out);
vis_q_out <= sfixed_as_signed(q_out);
vis_freq_track <= sfixed_as_signed(freq_track);
end sim;
|
library ieee;
library work;
library altera;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.altera_pll_top_pkg.all;
use altera.altera_syn_attributes.all;
entity hardheat_top is
generic
(
-- Number of bits in time-to-digital converter
TDC_N : positive := 12;
-- Number of bitshifts to left for the filter proportional coefficient
FILT_P_SHIFT_N : integer := 0;
-- Number of bitshifts to right for the filter integral coefficient
FILT_I_SHIFT_N : integer := -5;
-- Initial output value from the filter
FILT_INIT_OUT_VAL : positive := 2**11 - 1;
-- Filter output offset
FILT_OUT_OFFSET : natural := 2**21;
-- Filter output value clamping limit
FILT_OUT_LIM : positive := 2**22;
-- Number of bits in the phase accumulator
ACCUM_BITS_N : positive := 32;
-- Number of bits in the tuning word for the phase accumulator
ACCUM_WORD_N : positive := 23;
-- Number of bits in the deadtime counter
DT_N : positive := 16;
-- Amount of deadtime in clock cycles
DT_VAL : natural := 100;
-- Number of bits in the lock detector "locked" counter
LD_LOCK_N : positive := 20;
-- Number of bits in the lock detector "unlocked" counter
LD_ULOCK_N : positive := 16;
-- Phase difference value under which we are considered to be locked
LD_LOCK_LIMIT : natural := 100;
-- Temperature conversion interval in clock cycles
TEMP_CONV_D : natural := 100000000;
-- Delay between conversion command and reading in clock cycles
TEMP_CONV_CMD_D : natural := 75000000;
-- Number of clock cycles for 1us delay for the 1-wire module
TEMP_OW_US_D : positive := 100;
-- Number of bits in the temperature PWM controller
TEMP_PWM_N : positive := 12;
-- Minimum PWM level (duty cycle)
TEMP_PWM_MIN_LVL : natural := 2**12 / 5;
-- Output maximum duty cycle on enable, measured in PWM cycles!
TEMP_PWM_EN_ON_D : natural := 100000;
-- Number of bitshifts to left for the PID-filter proportional coeff
TEMP_P_SHIFT_N : integer := 4;
-- Number of bitshifts to right for the PID-filter integral coeff
TEMP_I_SHIFT_N : integer := -11;
-- PID input offset applied to the temperature sensor output
TEMP_SETPOINT : integer := 320;
DEBOUNCE_D : natural := 1000000;
DEBOUNCE_FF_N : natural := 5
);
port
(
clk_in : in std_logic;
reset_in : in std_logic;
ref_in : in std_logic;
sig_in : in std_logic;
ow_in : in std_logic;
mod_lvl_in : in std_logic_vector(2 downto 0);
ow_out : out std_logic;
ow_pullup_out : out std_logic;
sig_lh_out : out std_logic;
sig_ll_out : out std_logic;
sig_rh_out : out std_logic;
sig_rl_out : out std_logic;
lock_out : out std_logic;
pwm_out : out std_logic;
temp_err_out : out std_logic
);
end entity;
architecture rtl_top of hardheat_top is
attribute noprune : boolean;
attribute preserve : boolean;
attribute keep : boolean;
signal clk : std_logic;
attribute noprune of clk : signal is true;
attribute keep of clk : signal is true;
signal temp : signed(16 - 1 downto 0);
signal temp_f : std_logic;
attribute keep of temp : signal is true;
attribute keep of temp_f : signal is true;
attribute noprune of temp : signal is true;
attribute noprune of temp_f : signal is true;
attribute preserve of temp : signal is true;
signal pll_clk : std_logic;
signal pll_locked : std_logic;
signal reset : std_logic;
signal mod_lvl : std_logic_vector(mod_lvl_in'range);
signal mod_lvl_f : std_logic;
signal debounced_sws : std_logic_vector(mod_lvl_in'range);
begin
-- Main clock from PLL on the SoCkit board
pll_p: altera_pll_top
port map
(
refclk => clk_in,
rst => not reset_in,
outclk_0 => pll_clk,
locked => pll_locked
);
clk <= pll_clk;
reset <= not pll_locked;
-- Read modulation level state from switches, debounce
debouncing_p: for i in 0 to mod_lvl_in'high generate
debouncer_p: entity work.debounce(rtl)
generic map
(
DEBOUNCE_D => DEBOUNCE_D,
FLIPFLOPS_N => DEBOUNCE_FF_N
)
port map
(
clk => clk,
reset => reset,
sig_in => mod_lvl_in(i),
sig_out => debounced_sws(i)
);
end generate;
-- Change modulation level when debounced modulation level changes
mod_lvl_p: process(clk, reset)
variable state : std_logic_vector(mod_lvl_in'high downto 0);
begin
if reset = '1' then
state := (others => '1');
mod_lvl <= state;
mod_lvl_f <= '0';
elsif rising_edge(clk) then
mod_lvl_f <= '0';
if not debounced_sws = state then
state := debounced_sws;
mod_lvl <= state;
mod_lvl_f <= '1';
end if;
end if;
end process;
-- TODO: Sig is internally connected!
hardheat_p: entity work.hardheat(rtl)
generic map
(
TDC_N => TDC_N,
FILT_P_SHIFT_N => FILT_P_SHIFT_N,
FILT_I_SHIFT_N => FILT_I_SHIFT_N,
FILT_INIT_OUT_VAL => FILT_INIT_OUT_VAL,
FILT_OUT_OFFSET => FILT_OUT_OFFSET,
FILT_OUT_LIM => FILT_OUT_LIM,
ACCUM_BITS_N => ACCUM_BITS_N,
ACCUM_WORD_N => ACCUM_WORD_N,
LD_LOCK_N => LD_LOCK_N,
LD_ULOCK_N => LD_ULOCK_N,
LD_LOCK_LIMIT => LD_LOCK_LIMIT,
DT_N => DT_N,
DT_VAL => DT_VAL,
TEMP_CONV_D => TEMP_CONV_D,
TEMP_CONV_CMD_D => TEMP_CONV_CMD_D,
TEMP_OW_US_D => TEMP_OW_US_D,
TEMP_PWM_N => TEMP_PWM_N,
TEMP_PWM_MIN_LVL => TEMP_PWM_MIN_LVL,
TEMP_PWM_EN_ON_D => TEMP_PWM_EN_ON_D,
TEMP_P_SHIFT_N => TEMP_P_SHIFT_N,
TEMP_I_SHIFT_N => TEMP_I_SHIFT_N,
TEMP_SETPOINT => TEMP_SETPOINT
)
port map
(
clk => clk,
reset => reset,
ref_in => ref_in,
sig_in => sig_in,
mod_lvl_in => unsigned(mod_lvl),
mod_lvl_in_f => mod_lvl_f,
sig_lh_out => sig_lh_out,
sig_ll_out => sig_ll_out,
sig_rh_out => sig_rh_out,
sig_rl_out => sig_rl_out,
lock_out => lock_out,
ow_in => ow_in,
ow_out => ow_out,
ow_pullup_out => ow_pullup_out,
temp_out => temp,
temp_out_f => temp_f,
temp_err_out => temp_err_out,
pwm_out => pwm_out
);
end;
|
library verilog;
use verilog.vl_types.all;
entity apb_interface is
port(
PCLK : in vl_logic;
PRESETn : in vl_logic;
PWRITE : in vl_logic;
PWDATA : in vl_logic_vector(31 downto 0);
PENABLE : in vl_logic;
PADDR : in vl_logic_vector(31 downto 0);
PSEL : in vl_logic;
PREADY : out vl_logic;
PRDATA : out vl_logic_vector(31 downto 0)
);
end apb_interface;
|
<filename>base/rtl/TriggerEventBuffer.vhd
-------------------------------------------------------------------------------
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- This file is part of 'L2SI Core'. It is subject to
-- the license terms in the LICENSE.txt file found in the top-level directory
-- of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'L2SI Core', including this file, may be
-- copied, modified, propagated, or distributed except according to the terms
-- contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library surf;
use surf.StdRtlPkg.all;
use surf.AxiLitePkg.all;
use surf.AxiStreamPkg.all;
library lcls_timing_core;
use lcls_timing_core.TimingPkg.all;
library l2si_core;
use l2si_core.L2SiPkg.all;
use l2si_core.XpmPkg.all;
use l2si_core.XpmExtensionPkg.all;
entity TriggerEventBuffer is
generic (
TPD_G : time := 1 ns;
TRIGGER_INDEX_G : integer := 0;
EN_LCLS_I_TIMING_G : boolean := false;
EN_LCLS_II_TIMING_G : boolean := true;
EVENT_AXIS_CONFIG_G : AxiStreamConfigType := EVENT_AXIS_CONFIG_C;
AXIL_CLK_IS_TIMING_RX_CLK_G : boolean := false;
TRIGGER_CLK_IS_TIMING_RX_CLK_G : boolean := false;
EVENT_CLK_IS_TIMING_RX_CLK_G : boolean := false);
port (
timingRxClk : in sl;
timingRxRst : in sl;
-- AXI Lite bus for configuration and status
axilClk : in sl;
axilRst : in sl;
axilReadMaster : in AxiLiteReadMasterType;
axilReadSlave : out AxiLiteReadSlaveType;
axilWriteMaster : in AxiLiteWriteMasterType;
axilWriteSlave : out AxiLiteWriteSlaveType;
-- EVR triggers for LCLS-I timing
timingMode : in sl;
evrTriggers : in TimingTrigType;
-- Prompt header and event bus
promptTimingStrobe : in sl;
promptTimingMessage : in TimingMessageType;
promptXpmMessage : in XpmMessageType;
-- Aligned header and event bus
alignedTimingStrobe : in sl;
alignedTimingMessage : in TimingMessageType;
alignedXpmMessage : in XpmMessageType;
-- Feedback
partition : out slv(2 downto 0);
pause : out sl;
overflow : out sl;
-- Trigger output
triggerClk : in sl;
triggerRst : in sl;
triggerData : out TriggerEventDataType;
-- Event/Transition output
eventClk : in sl;
eventRst : in sl;
eventTimingMessageValid : out sl;
eventTimingMessage : out TimingMessageType;
eventTimingMessageRd : in sl := '1';
eventAxisMaster : out AxiStreamMasterType;
eventAxisSlave : in AxiStreamSlaveType;
eventAxisCtrl : in AxiStreamCtrlType;
clearReadout : out sl);
end entity TriggerEventBuffer;
architecture rtl of TriggerEventBuffer is
constant FIFO_ADDR_WIDTH_C : integer := 5;
type RegType is record
evrTrigLast : sl;
partition : slv(2 downto 0);
overflow : sl;
fifoRst : sl;
transitionCount : slv(31 downto 0);
validCount : slv(31 downto 0);
triggerCount : slv(31 downto 0);
l0Count : slv(31 downto 0);
l1AcceptCount : slv(31 downto 0);
l1RejectCount : slv(31 downto 0);
fbTimer : slv(11 downto 0);
fbTimerOverflow : sl;
fbTimerActive : sl;
fbTimerToTrig : slv(11 downto 0);
pauseToTrig : slv(11 downto 0);
notPauseToTrig : slv(11 downto 0);
pause : sl;
fifoAxisMaster : AxiStreamMasterType;
msgFifoWr : sl;
-- outputs
triggerData : XpmEventDataType;
-- debug
partitionV : integer;
eventData : XpmEventDataType;
transitionData : XpmTransitionDataType;
tmpEventData : XpmEventDataType;
eventHeader : EventHeaderType;
streamValid : sl;
end record RegType;
constant REG_INIT_C : RegType := (
evrTrigLast => '0',
partition => (others => '0'),
overflow => '0',
fifoRst => '0',
transitionCount => (others => '0'),
validCount => (others => '0'),
triggerCount => (others => '0'),
l0Count => (others => '0'),
l1AcceptCount => (others => '0'),
l1RejectCount => (others => '0'),
fbTimer => (others => '0'),
fbTimerOverflow => '0',
fbTimerActive => '0',
fbTimerToTrig => (others => '0'),
pauseToTrig => (others => '0'),
notPauseToTrig => (others => '1'),
pause => '0',
fifoAxisMaster => axiStreamMasterInit(EVENT_AXIS_CONFIG_C),
msgFifoWr => '0',
-- outputs =>
triggerData => TRIGGER_EVENT_DATA_INIT_C,
partitionV => 0,
eventData => XPM_EVENT_DATA_INIT_C,
transitionData => XPM_TRANSITION_DATA_INIT_C,
tmpEventData => XPM_EVENT_DATA_INIT_C,
eventHeader => EVENT_HEADER_INIT_C,
streamValid => '0');
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal fifoAxisSlave : AxiStreamSlaveType;
signal fifoAxisCtrl : AxiStreamCtrlType;
signal fifoWrCnt : slv(FIFO_ADDR_WIDTH_C-1 downto 0);
signal alignedTimingMessageSlv : slv(TIMING_MESSAGE_BITS_NO_BSA_C-1 downto 0);
signal eventTimingMessageSlv : slv(TIMING_MESSAGE_BITS_NO_BSA_C-1 downto 0);
signal triggerDataValid : sl;
signal triggerDataSlv : slv(47 downto 0);
signal delayedTriggerDataSlv : slv(47 downto 0);
signal delayedTriggerDataValid : sl;
signal syncTriggerDataValid : sl;
signal syncTriggerDataSlv : slv(47 downto 0);
signal eventAxisCtrlPauseSync : sl;
signal partitionReg : slv(2 downto 0);
signal triggerDelay : slv(31 downto 0);
signal fifoPauseThresh : slv(FIFO_ADDR_WIDTH_C-1 downto 0);
signal resetCounters : sl;
signal fifoRstReg : sl;
signal fifoRst : sl;
signal enable : sl;
begin
-- Event AXIS bus pause is the application pause signal
-- It needs to be synchronizer to timingRxClk
U_Synchronizer_1 : entity surf.Synchronizer
generic map (
TPD_G => TPD_G)
port map (
clk => timingRxClk, -- [in]
rst => timingRxRst, -- [in]
dataIn => eventAxisCtrl.pause, -- [in]
dataOut => eventAxisCtrlPauseSync); -- [out]
comb : process (alignedTimingMessage, alignedTimingStrobe, alignedXpmMessage, axilReadMaster,
axilWriteMaster, eventAxisCtrlPauseSync, enable, evrTriggers, fifoAxisCtrl, fifoRstReg,
partitionReg, promptTimingStrobe, promptXpmMessage, r, resetCounters, timingMode, timingRxRst) is
variable v : RegType;
variable axilEp : AxiLiteEndpointType;
begin
v := r;
if (EN_LCLS_I_TIMING_G and timingMode = '0') then
-- LCLS-I EVR Trigger buffer logic
v.fifoRst := '0';
v.fifoAxisMaster.tValid := '0';
v.triggerData.valid := '0';
v.triggerData.l0Accept := '0';
v.evrTrigLast := evrTriggers.trigPulse(TRIGGER_INDEX_G);
if (evrTriggers.trigPulse(TRIGGER_INDEX_G) = '1' and r.evrTrigLast = '0' and enable = '1') then
v.triggerCount := r.triggerCount + 1;
v.fifoAxisMaster.tValid := '1';
v.fifoAxisMaster.tdata(63 downto 0) := (others => '0');
v.fifoAxisMaster.tdata(127 downto 64) := evrTriggers.timeStamp;
v.fifoAxisMaster.tLast := '1';
v.triggerData.valid := '1';
v.triggerData.l0Accept := '1';
v.triggerData.l0Tag := v.triggerCount(4 downto 0);
v.triggerData.count := v.triggerCount(23 downto 0);
end if;
if (fifoAxisCtrl.overflow = '1') then
v.overflow := '1';
end if;
if (resetCounters = '1') then
v.triggerCount := (others => '0');
end if;
elsif (EN_LCLS_II_TIMING_G and timingMode = '1') then
-- LCLS-II XPM Trigger Buffer Logic
v.partitionV := conv_integer(r.partition);
v.fifoRst := '0';
v.fifoAxisMaster.tValid := '0';
v.msgFifoWr := '0';
--------------------------------------------
-- Trigger output logic
-- Watch for and decode triggers on prompt interface
-- Output on triggerData interface
--------------------------------------------
v.triggerData := XPM_EVENT_DATA_INIT_C;
if (promptTimingStrobe = '1' and promptXpmMessage.valid = '1' and enable = '1') then
v.triggerData := toXpmEventDataType(promptXpmMessage.partitionWord(v.partitionV));
if (v.triggerData.valid = '1' and v.triggerData.l0Accept = '1') then
v.triggerCount := r.triggerCount + 1;
end if;
end if;
--------------------------------------------
-- Event/Transition logic
-- Watch for events/transitions on aligned interface
-- Place entries into FIFO
--------------------------------------------
v.streamValid := '0';
v.msgFifoWr := '0';
if (alignedTimingStrobe = '1' and alignedXpmMessage.valid = '1') then
-- Decode event data from configured partitionWord
-- Decode as both event and transition and use the .valid field to determine which one to use
v.eventData := toXpmEventDataType(alignedXpmMessage.partitionWord(v.partitionV));
v.transitionData := toXpmTransitionDataType(alignedXpmMessage.partitionWord(v.partitionV));
-- Pass on events with l0Accept
-- Pass on transitions
v.streamValid := (v.eventData.valid and v.eventData.l0Accept) or v.transitionData.valid;
v.msgFifoWr := (v.eventData.valid and v.eventData.l0Accept);
-- Don't pass data through when disabled
if (enable = '0') then
v.streamValid := '0';
v.msgFifoWr := '0';
end if;
-- Create the EventHeader from timing and event data
v.eventHeader.pulseId := alignedTimingMessage.pulseId;
v.eventHeader.timeStamp := alignedTimingMessage.timeStamp;
v.eventHeader.count := v.eventData.count;
v.eventHeader.triggerInfo := alignedXpmMessage.partitionWord(v.partitionV)(15 downto 0);
v.eventHeader.partitions := (others => '0');
for i in 0 to 7 loop
v.tmpEventData := toXpmEventDataType(alignedXpmMessage.partitionWord(i));
v.eventHeader.partitions(i) := v.tmpEventData.l0Accept or not v.tmpEventData.valid;
end loop;
-- Place the EventHeader into an AXI-Stream transaction
if (v.streamValid = '1') then
if (fifoAxisCtrl.overflow = '0') then
v.fifoAxisMaster.tValid := '1';
v.fifoAxisMaster.tdata(EVENT_HEADER_BITS_C-1 downto 0) := toSlv(v.eventHeader);
v.fifoAxisMaster.tDest(0) := v.transitionData.valid;
v.fifoAxisMaster.tLast := '1';
end if;
end if;
-- Special case - reset fifo, mask any tValid
-- Note that this logic is active even when the enable register = 0.
if (v.transitionData.valid = '1' and v.transitionData.header = MSG_CLEAR_FIFO_C) then
v.overflow := '0';
v.fifoRst := '1';
v.fifoAxisMaster.tValid := '0';
end if;
if (enable = '1') then
v.validCount := r.validCount + 1;
end if;
end if;
-- Latch FIFO overflow if seen
if (fifoAxisCtrl.overflow = '1') then
v.overflow := '1';
end if;
-- Count stuff
if (r.streamValid = '1') then
if (r.eventData.valid = '1') then
if (r.eventData.l0Accept = '1') then
v.l0Count := r.l0Count + 1;
end if;
if (r.eventData.l1Expect = '1') then
if (r.eventData.l1Accept = '1') then
v.l1AcceptCount := r.l1AcceptCount + 1;
else
v.l1RejectCount := r.l1RejectCount + 1;
end if;
end if;
end if;
if (r.transitionData.valid = '1') then
v.transitionCount := r.transitionCount + 1;
end if;
end if;
-- Monitor time between pause assertion and trigger arrival
v.fbTimer := r.fbTimer + 1;
if uAnd(r.fbTimer) = '1' then
v.fbTimerOverflow := '1';
end if;
v.pause := fifoAxisCtrl.pause or eventAxisCtrlPauseSync;
if v.pause /= r.pause then
v.fbTimer := (others => '0');
v.fbTimerOverflow := '0';
v.fbTimerActive := r.fbTimerOverflow;
if (r.pause = '1' and r.fbTimerActive = '1' and r.fbTimerToTrig > r.pauseToTrig) then
v.pauseToTrig := r.fbTimerToTrig;
end if;
elsif (r.triggerData.valid = '1' and r.triggerData.l0Accept = '1') then
if r.pause = '1' then
v.fbTimerToTrig := r.fbTimer;
elsif (r.fbTimerActive = '1' and r.fbTimerOverflow = '0' and r.fbTimer < r.notPauseToTrig) then
v.notPauseToTrig := r.fbTimer;
end if;
end if;
end if;
if (resetCounters = '1') then
v.l0Count := (others => '0');
v.l1AcceptCount := (others => '0');
v.l1RejectCount := (others => '0');
v.validCount := (others => '0');
v.triggerCount := (others => '0');
v.pauseToTrig := (others => '0');
v.notPauseToTrig := (others => '1');
end if;
v.partition := partitionReg;
if (timingRxRst = '1') then
v := REG_INIT_C;
end if;
rin <= v;
-- outputs
fifoRst <= r.fifoRst or fifoRstReg;
partition <= r.partition;
overflow <= r.overflow;
pause <= r.pause;
end process comb;
seq : process (timingRxClk) is
begin
if (rising_edge(timingRxClk)) then
r <= rin after TPD_G;
end if;
end process seq;
U_TriggerEventBufferReg : entity l2si_core.TriggerEventBufferReg
generic map (
TPD_G => TPD_G,
COMMON_CLK_G => AXIL_CLK_IS_TIMING_RX_CLK_G,
FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_C,
EN_LCLS_I_TIMING_G => EN_LCLS_I_TIMING_G,
EN_LCLS_II_TIMING_G => EN_LCLS_II_TIMING_G)
port map (
timingRxClk => timingRxClk,
timingRxRst => timingRxRst,
overflow => r.overflow,
fifoAxisCtrl => fifoAxisCtrl,
fifoWrCnt => fifoWrCnt,
timingMode => timingMode,
triggerCount => r.triggerCount,
pause => r.pause,
l0Count => r.l0Count,
l1AcceptCount => r.l1AcceptCount,
l1RejectCount => r.l1RejectCount,
transitionCount => r.transitionCount,
validCount => r.validCount,
alignedXpmMessage => alignedXpmMessage,
pauseToTrig => r.pauseToTrig,
notPauseToTrig => r.notPauseToTrig,
enable => enable,
fifoRst => fifoRstReg,
resetCounters => resetCounters,
partition => partitionReg,
triggerDelay => triggerDelay,
fifoPauseThresh => fifoPauseThresh,
-- AXI Lite bus for configuration and status
axilClk => axilClk,
axilRst => axilRst,
axilReadMaster => axilReadMaster,
axilReadSlave => axilReadSlave,
axilWriteMaster => axilWriteMaster,
axilWriteSlave => axilWriteSlave);
-----------------------------------------------
-- Delay triggerData according to AXI-Lite register
-----------------------------------------------
triggerDataSlv <= toSlv(r.triggerData);
triggerDataValid <= r.triggerData.valid and r.triggerData.l0Accept;
U_SlvDelayFifo_1 : entity surf.SlvDelayFifo
generic map (
TPD_G => TPD_G,
DATA_WIDTH_G => 48,
DELAY_BITS_G => 32,
FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_C,
FIFO_MEMORY_TYPE_G => "block")
port map (
clk => timingRxClk, -- [in]
rst => timingRxRst, -- [in]
delay => triggerDelay, -- [in]
inputData => triggerDataSlv, -- [in]
inputValid => triggerDataValid, -- [in]
outputData => delayedTriggerDataSlv, -- [out]
outputValid => delayedTriggerDataValid); -- [out]
-----------------------------------------------
-- Synchronize trigger data to trigger clock
-----------------------------------------------
TRIGGER_SYNC_GEN : if (not TRIGGER_CLK_IS_TIMING_RX_CLK_G) generate
U_SynchronizerFifo_1 : entity surf.SynchronizerFifo
generic map (
TPD_G => TPD_G,
COMMON_CLK_G => false,
DATA_WIDTH_G => 48)
port map (
rst => timingRxRst, -- [in]
wr_clk => timingRxClk, -- [in]
wr_en => delayedTriggerDataValid, -- [in]
din => delayedTriggerDataSlv, -- [in]
rd_clk => triggerClk, -- [in]
rd_en => syncTriggerDataValid, -- [in]
valid => syncTriggerDataValid, -- [out]
dout => syncTriggerDataSlv); -- [out]
triggerData <= toXpmEventDataType(syncTriggerDataSlv, syncTriggerDataValid);
U_SynchronizerClearReadout : entity surf.SynchronizerOneShot
generic map (
TPD_G => TPD_G)
port map (
clk => eventClk,
dataIn => fifoRst,
dataOut => clearReadout);
end generate TRIGGER_SYNC_GEN;
NO_TRIGGER_SYNC_GEN : if (TRIGGER_CLK_IS_TIMING_RX_CLK_G) generate
triggerData <= toXpmEventDataType(delayedTriggerDataSlv, delayedTriggerDataValid);
end generate NO_TRIGGER_SYNC_GEN;
-----------------------------------------------
-- Buffer event data in a fifo
-----------------------------------------------
U_AxiStreamFifoV2_1 : entity surf.AxiStreamFifoV2
generic map (
TPD_G => TPD_G,
INT_PIPE_STAGES_G => 1,
PIPE_STAGES_G => 1,
SLAVE_READY_EN_G => false,
MEMORY_TYPE_G => "block",
GEN_SYNC_FIFO_G => EVENT_CLK_IS_TIMING_RX_CLK_G,
FIFO_ADDR_WIDTH_G => FIFO_ADDR_WIDTH_C,
FIFO_FIXED_THRESH_G => false,
FIFO_PAUSE_THRESH_G => 16,
SLAVE_AXI_CONFIG_G => EVENT_AXIS_CONFIG_C,
MASTER_AXI_CONFIG_G => EVENT_AXIS_CONFIG_G)
port map (
sAxisClk => timingRxClk, -- [in]
sAxisRst => fifoRst, -- [in]
sAxisMaster => r.fifoAxisMaster, -- [in]
sAxisSlave => fifoAxisSlave, -- [out]
sAxisCtrl => fifoAxisCtrl, -- [out]
fifoPauseThresh => fifoPauseThresh, -- [in]
fifoWrCnt => fifoWrCnt, -- [out]
mAxisClk => eventClk, -- [in]
mAxisRst => eventRst, -- [in]
mAxisMaster => eventAxisMaster, -- [out]
mAxisSlave => eventAxisSlave); -- [in]
-----------------------------------------------
-- Buffer TimingMessage that corresponds to each event placed in event fifo
-----------------------------------------------
GEN_EVENT_TIMING_MESSAGE : if (EN_LCLS_II_TIMING_G) generate
alignedTimingMessageSlv <= toSlvNoBsa(alignedTimingMessage);
U_Fifo_1 : entity surf.Fifo
generic map (
TPD_G => TPD_G,
GEN_SYNC_FIFO_G => EVENT_CLK_IS_TIMING_RX_CLK_G,
MEMORY_TYPE_G => "block",
FWFT_EN_G => true,
PIPE_STAGES_G => 1, -- make sure this lines up right with event fifo
DATA_WIDTH_G => TIMING_MESSAGE_BITS_NO_BSA_C,
ADDR_WIDTH_G => FIFO_ADDR_WIDTH_C)
port map (
rst => fifoRst, -- [in]
wr_clk => timingRxClk, -- [in]
wr_en => r.msgFifoWr, -- [in]
din => alignedTimingMessageSlv, -- [in]
rd_clk => eventClk, -- [in]
rd_en => eventTimingMessageRd, -- [in]
valid => eventTimingMessageValid, -- [out]
dout => eventTimingMessageSlv); -- [out]
eventTimingMessage <= toTimingMessageType(eventTimingMessageSlv);
end generate GEN_EVENT_TIMING_MESSAGE;
end architecture rtl;
|
library ieee ;
use ieee.std_logic_1164.all;
-------------------------------------
entity d_latch is
port( en : in std_logic ;
anrst : in std_logic;
d : in std_logic ;
q : out std_logic ;
q_bar : out std_logic ) ;
end entity d_latch ;
-------------------------------------
architecture Behavioral of d_latch is
begin
p_d_latch : process ( en , d, anrst )
begin
if(anrst = '1') then
q <= '0';
elsif( en = '1' ) then
q <= d ;
q_bar <= not d ;
end if ;
end process p_d_latch ;
end architecture Behavioral ;
|
------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC Firmware Standard Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.StdRtlPkg.all;
use work.AxiStreamPkg.all;
use work.AxiLitePkg.all;
use work.AxiPkg.all;
use work.AxiDmaPkg.all;
use work.RceG3Pkg.all;
use work.ProtoDuneDpmPkg.all;
entity compression_tb is end compression_tb;
-- Define architecture
architecture compression_tb of compression_tb is
constant TPD_C : time := 1 ns;
signal emuClk : sl;
signal emuRst : sl;
signal axilClk : sl;
signal axilRst : sl;
signal axilReadMaster : AxiLiteReadMasterType;
signal axilReadSlave : AxiLiteReadSlaveType;
signal axilWriteMaster : AxiLiteWriteMasterType;
signal axilWriteSlave : AxiLiteWriteSlaveType;
signal wibMasters : AxiStreamMasterArray(WIB_SIZE_C-1 downto 0);
signal wibSlaves : AxiStreamSlaveArray(WIB_SIZE_C-1 downto 0);
signal loopbackMaster : AxiStreamMasterType;
signal loopbackSlave : AxiStreamSlaveType;
signal dmaIbMaster : AxiStreamMasterType;
signal dmaIbSlave : AxiStreamSlaveType;
signal enableTx : sl;
signal enableTrig : sl;
signal sendCnt : sl;
signal chNoiseCgf : Slv3Array(127 downto 0);
signal cmNoiseCgf : slv(2 downto 0);
signal chDlyCfg : EmuDlyCfg;
signal convt : sl;
signal adcData : Slv12Array(127 downto 0);
signal adcDataDly : Slv12Array(127 downto 0);
signal adcDataDlyCM : Slv12Array(127 downto 0);
signal cmNoise : slv(11 downto 0);
signal emuData : slv(15 downto 0);
signal emuDataK : slv(1 downto 0);
signal rxEnable : sl;
signal curCnt : slv(31 downto 0);
signal nxtCnt : slv(31 downto 0);
begin
process begin
axilClk <= '1';
wait for 4 ns;
axilClk <= '0';
wait for 4 ns;
end process;
process begin
axilRst <= '1';
wait for (100 ns);
axilRst <= '0';
wait;
end process;
process begin
emuClk <= '1';
wait for 2.00 ns;
emuClk <= '0';
wait for 2.00 ns;
end process;
process begin
emuRst <= '1';
wait for (42 ns);
emuRst <= '0';
wait;
end process;
U_Hls: entity work.ProtoDuneDpmHls
generic map (
TPD_G => TPD_C,
CASCADE_SIZE_G => 1,
AXI_CLK_FREQ_G => 125.0E+6,
AXI_BASE_ADDR_G => x"A0000000")
port map (
axilClk => axilClk,
axilRst => axilRst,
axilReadMaster => axilReadMaster,
axilReadSlave => axilReadSlave,
axilWriteMaster => axilWriteMaster,
axilWriteSlave => axilWriteSlave,
-- WIB Interface (axilClk domain)
wibMasters => wibMasters,
wibSlaves => wibSlaves,
-- DMA Loopback Path Interface (dmaClk domain)
loopbackMaster => loopbackMaster,
loopbackSlave => loopbackSlave,
-- AXI Stream Interface (dmaClk domain)
dmaClk => emuClk,
dmaRst => emuRst,
dmaIbMaster => dmaIbMaster,
dmaIbSlave => dmaIbSlave);
loopbackMaster <= AXI_STREAM_MASTER_INIT_C;
dmaIbSlave <= AXI_STREAM_SLAVE_FORCE_C;
process(axilClk)
begin
if rising_edge(axilClk) then
if axilRst = '1' then
curCnt <= (others=>'0');
nxtCnt <= (others=>'0');
elsif dmaIbMaster.tValid = '1' then
nxtCnt <= nxtCnt + 1;
if dmaIbMaster.tLast = '1' then
curCnt <= nxtCnt + 1;
nxtCnt <= (others=>'0');
end if;
end if;
end if;
end process;
process begin
rxEnable <= '0';
enableTx <= '0';
enableTrig <= '0';
chNoiseCgf <= (others=>(others=>'0'));
cmNoiseCgf <= "011";
chDlyCfg <= (others => (others => '0'));
axilWriteMaster <= AXI_LITE_WRITE_MASTER_INIT_C;
axilReadMaster <= AXI_LITE_READ_MASTER_INIT_C;
sendCnt <= '0';
wait for 5 US;
axiLiteBusSimWrite ( axilClk, axilWriteMaster, axilWriteSlave, x"A0000000", x"00000081", true); -- Enable compression
axiLiteBusSimWrite ( axilClk, axilWriteMaster, axilWriteSlave, x"A0010000", x"00000081", true); -- Enable compression
--axiLiteBusSimWrite ( axilClk, axilWriteMaster, axilWriteSlave, x"A0020800", x"00000000", true);
wait for 1 US;
enableTx <= '1';
wait for 5 US;
rxEnable <= '0';
wait for 0.6 MS;
axiLiteBusSimWrite ( axilClk, axilWriteMaster, axilWriteSlave, x"A0020800", x"00000000", true);
wait;
end process;
------------------------------------------
-- Emulator
------------------------------------------
U_DataGen : entity work.ProtoDuneDpmEmuData
generic map ( TPD_G => TPD_C)
port map (
-- Clock and Reset
clk => emuClk,
rst => emuRst,
-- EMU Data Interface
enableTx => enableTx,
enableTrig => enableTrig,
convt => convt,
cmNoiseCgf => cmNoiseCgf,
chNoiseCgf => chNoiseCgf,
timingTrig => '0',
cmNoise => cmNoise,
adcData => adcData);
----------------
-- Delay Modules
----------------
GEN_VEC :
for i in 127 downto 0 generate
U_DlyTaps : entity work.SlvDelay
generic map (
TPD_G => TPD_C,
SRL_EN_G => true,
DELAY_G => EMU_DELAY_TAPS_C,
REG_OUTPUT_G => true,
WIDTH_G => 12)
port map (
clk => emuClk,
en => convt,
delay => chDlyCfg(i),
din => adcData(i),
dout => adcDataDly(i));
process(emuClk)
begin
if rising_edge(emuClk) then
if emuRst = '1' then
adcDataDlyCM(i) <= (others=>'0');
elsif convt = '1' then
adcDataDlyCM(i) <= adcDataDly(i) + cmNoise after TPD_C;
end if;
end if;
end process;
end generate GEN_VEC;
---------------------
-- TX Frame Formatter
---------------------
U_TxFrammer : entity work.ProtoDuneDpmEmuTxFramer
generic map (
TPD_G => TPD_C)
port map (
-- Clock and Reset
clk => emuClk,
rst => emuRst,
-- EMU Data Interface
enable => enableTx,
sendCnt => sendCnt,
adcData => adcDataDlyCM,
convt => convt,
timingTs => (others=>'0'),
-- TX Data Interface
txData => emuData,
txdataK => emuDataK);
U_RxGen: for i in 0 to 1 generate
U_RxFramer: entity work.ProtoDuneDpmWibRxFramer
generic map ( TPD_G => TPD_C )
port map (
-- AXI-Lite Interface (axilClk domain)
axilClk => axilClk,
axilRst => axilRst,
axilReadMaster => AXI_LITE_READ_MASTER_INIT_C,
axilReadSlave => open,
axilWriteMaster => AXI_LITE_WRITE_MASTER_INIT_C,
axilWriteSlave => open,
-- RX Data Interface (clk domain)
clk => emuClk,
rst => emuRst,
rxValid => '1',
rxData => emuData,
rxdataK => emuDataK,
rxDecErr => (others=>'0'),
rxDispErr => (others=>'0'),
rxBufStatus => (others=>'0'),
rxPolarity => open,
txPolarity => open,
cPllLock => '1',
gtRst => open,
logEn => open,
logClr => open,
-- Timing Interface (clk domain)
swFlush => '0',
runEnable => rxEnable,
-- WIB Interface (axilClk domain)
wibMaster => wibMasters(i),
wibSlave => wibSlaves(i));
end generate;
end compression_tb;
|
-- ----------------------------------------------------------------------------
-- FILE : adc_top.vhd
-- DESCRIPTION : Top ADC module
-- DATE : Jan 27, 2016
-- AUTHOR(s) : <NAME>
-- REVISIONS :
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rxtspcfg_pkg.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity adc_top is
generic(
dev_family : string := "Cyclone V";
data_width : integer := 7;
smpls_to_capture : integer := 4 -- 2,4,6,8...
);
port (
clk : in std_logic;
reset_n : in std_logic;
en : in std_logic;
ch_a : in std_logic_vector(data_width-1 downto 0); --Input to DDR cells from pins
ch_b : in std_logic_vector(data_width-1 downto 0); --Input to DDR cells from pins
--SDR parallel output data
data_ch_a : out std_logic_vector(data_width*2-1 downto 0); --Sampled data ch A
data_ch_b : out std_logic_vector(data_width*2-1 downto 0); --Sampled data ch B
--Interleaved samples of both channels
data_ch_ab : out std_logic_vector(data_width*2*smpls_to_capture-1 downto 0); -- ... B1 A1 B0 A0
data_ch_ab_valid : out std_logic;
test_out : out std_logic_vector(55 downto 0);
to_rxtspcfg : out t_TO_RXTSPCFG;
from_rxtspcfg : in t_FROM_RXTSPCFG
);
end adc_top;
-- ----------------------------------------------------------------------------
-- Architecture
-- ----------------------------------------------------------------------------
architecture arch of adc_top is
--declare signals, components here
signal inst0_data_ch_a : std_logic_vector (data_width*2-1 downto 0);
signal inst0_data_ch_b : std_logic_vector (data_width*2-1 downto 0);
--inst1 signals
signal inst1_RXI : std_logic_vector(17 downto 0);
signal inst1_RXQ : std_logic_vector(17 downto 0);
signal inst1_RYI : std_logic_vector (17 downto 0);
signal inst1_RYQ : std_logic_vector (17 downto 0);
type reg_chain_type is array (0 to smpls_to_capture/2-1) of std_logic_vector(data_width*4-1 downto 0);
signal reg_chain : reg_chain_type;
signal valid_cnt : unsigned(7 downto 0);
signal valid_cnt_ovrfl : std_logic;
signal reset_n_sync : std_logic;
begin
sync_reg0 : entity work.sync_reg
port map(clk, reset_n, en, reset_n_sync);
-- ----------------------------------------------------------------------------
-- ADC instance
-- ----------------------------------------------------------------------------
ADS4246_inst0 : entity work.ADS4246
generic map(
dev_family => dev_family
)
port map(
clk => clk,
reset_n => reset_n_sync,
ch_a => ch_a,
ch_b => ch_b,
data_ch_a => inst0_data_ch_a,
data_ch_b => inst0_data_ch_b
);
inst1_RXI <= inst0_data_ch_a & "0000";
inst1_RXQ <= inst0_data_ch_b & "0000";
rx_chain_inst1 : entity work.rx_chain
port map
(
clk => clk,
nrst => reset_n_sync,
HBD_ratio => (others=>'0'),
RXI => inst1_RXI,
RXQ => inst1_RXQ,
xen => open,
RYI => inst1_RYI,
RYQ => inst1_RYQ,
to_rxtspcfg => to_rxtspcfg,
from_rxtspcfg => from_rxtspcfg
);
--for testing rx_chain is bypassed
--inst1_RYI <= inst1_RXI;
--inst1_RYQ <= inst1_RXQ;
-- ----------------------------------------------------------------------------
-- Chain of registers for storing samples
-- ----------------------------------------------------------------------------
process(clk, reset_n_sync)
begin
if reset_n_sync = '0' then
reg_chain <= (others=>(others=>'0'));
elsif (clk'event AND clk='1') then
for i in 0 to smpls_to_capture/2-1 loop
if i = 0 then
reg_chain(0) <= inst1_RYI(17 downto 18-data_width*2) & inst1_RYQ(17 downto 18-data_width*2);
else
reg_chain(i) <= reg_chain(i-1);
end if;
end loop;
end if;
end process;
-- ----------------------------------------------------------------------------
-- Reg chain to output port
-- ----------------------------------------------------------------------------
process(reg_chain)
begin
for i in 0 to smpls_to_capture/2-1 loop
data_ch_ab(i*data_width*4 + data_width*4-1 downto i*data_width*4) <= reg_chain(smpls_to_capture/2-1-i);
end loop;
end process;
test_out <= "00000000000000111111111111110000000000000011111111111111";
process(clk, reset_n_sync)
begin
if reset_n_sync = '0' then
valid_cnt <= (others=>'0');
data_ch_ab_valid <= '0';
valid_cnt_ovrfl <= '0';
elsif (clk'event AND clk='1') then
if valid_cnt < smpls_to_capture/2-1 then
valid_cnt <= valid_cnt+1;
valid_cnt_ovrfl <= '0';
else
valid_cnt <= (others=>'0');
valid_cnt_ovrfl <= '1';
end if;
data_ch_ab_valid <= valid_cnt_ovrfl;
end if;
end process;
-- ----------------------------------------------------------------------------
-- Output ports
-- ----------------------------------------------------------------------------
data_ch_a <= inst0_data_ch_a;
data_ch_b <= inst0_data_ch_b;
end arch;
|
<reponame>jdryg/tis100cpu
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY alu_tb IS
END alu_tb;
ARCHITECTURE behavior OF alu_tb IS
constant ALU_SIZE : integer := 16;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alu
GENERIC (WIDTH : integer := ALU_SIZE);
PORT(I_a, I_b : IN std_logic_vector(WIDTH-1 downto 0);
I_op : IN std_logic_vector(2 downto 0);
O_isZero : OUT std_logic;
O_y : BUFFER std_logic_vector(WIDTH-1 downto 0));
END COMPONENT;
--Inputs
signal I_a : std_logic_vector(ALU_SIZE-1 downto 0) := (others => '0');
signal I_b : std_logic_vector(ALU_SIZE-1 downto 0) := (others => '0');
signal I_op : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal O_isZero : std_logic;
signal O_y : std_logic_vector(ALU_SIZE-1 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alu
GENERIC MAP (WIDTH => ALU_SIZE)
PORT MAP (
I_a => I_a,
I_b => I_b,
I_op => I_op,
O_isZero => O_isZero,
O_y => O_y
);
-- Stimulus process
stim_proc: process
begin
-- Addition
I_op <= "000";
-- Test addition of positive numbers (op = 00)
I_a <= X"0001";
I_b <= X"0002";
wait for 10 ns;
assert O_y = X"0003" report "Addition of positive numbers failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Addition of positive numbers completed";
-- Test addition of 1 positive and 1 negative number (op = 00)
I_a <= X"FFF7";
I_b <= X"0009";
wait for 10 ns;
assert O_y = X"0000" report "Addition of 1 positive and 1 negative number failed" severity error;
assert O_isZero = '1' report "Invalid zero flag" severity error;
report "Addition of mixed numbers completed";
-- Test addition of 2 negative numbers
I_a <= X"FFFF";
I_b <= X"FFFE";
wait for 10 ns;
assert O_y = X"FFFD" report "Addition of negative numbers failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Addition of negative numbers completed";
-- Subtraction
I_op <= "001";
-- Test subtraction of positive numbers
I_a <= X"0001";
I_b <= X"0002";
wait for 10 ns;
assert O_y = X"FFFF" report "Subtraction of positive numbers failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Subtraction of positive numbers completed";
-- Test subtraction of 1 positive and 1 negative number (op = 00)
I_a <= X"FFF7";
I_b <= X"0009";
wait for 10 ns;
assert O_y = X"FFEE" report "Subtraction of 1 positive and 1 negative number failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Subtraction of mixed numbers completed";
-- Test subtraction of 2 negative numbers
I_a <= X"FFFF";
I_b <= X"FFFE";
wait for 10 ns;
assert O_y = X"0001" report "Subtraction of negative numbers failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Subtraction of negative numbers completed";
-- Negation
I_op <= "010";
I_b <= X"0001";
-- Test negation of positive number
I_a <= X"0001";
wait for 10 ns;
assert O_y = X"FFFF" report "Negation of positive number failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Negation of positive number completed";
I_a <= X"FFFE";
wait for 10 ns;
assert O_y = X"0002" report "Negation of negative number failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Negation of negative number completed";
-- Set Less Than
I_op <= "011";
I_b <= X"0000";
-- -1 < 0
I_a <= X"FFFF";
wait for 10 ns;
assert O_y = X"0001" report "-1 < 0 failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
I_a <= X"0001";
wait for 10 ns;
assert O_y = X"0000" report "1 < 0 failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
I_a <= X"0000";
wait for 10 ns;
assert O_y = X"0000" report "0 < 0 failed" severity error;
assert O_isZero = '1' report "Invalid zero flag" severity error;
report "SLT tests completed";
-- Inverse Subtraction
I_op <= "100";
-- Test inverse subtraction of positive numbers
I_a <= X"0001";
I_b <= X"0002";
wait for 10 ns;
assert O_y = X"0001" report "Inverse subtraction of positive numbers failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Inverse subtraction of positive numbers completed";
-- Test inverse subtraction of 1 positive and 1 negative number (op = 00)
I_a <= X"FFF7";
I_b <= X"0009";
wait for 10 ns;
assert O_y = X"0012" report "Inverse subtraction of 1 positive and 1 negative number failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Inverse subtraction of mixed numbers completed";
-- Test inverse subtraction of 2 negative numbers
I_a <= X"FFFF";
I_b <= X"FFFE";
wait for 10 ns;
assert O_y = X"FFFF" report "Inverse subtraction of negative numbers failed" severity error;
assert O_isZero = '0' report "Invalid zero flag" severity error;
report "Inverse subtraction of negative numbers completed";
wait;
end process;
END;
|
entity flipflop is port (
D : in bit;
CLK : in bit;
Q : out bit);
end flipflop;
architecture behavioral of flipflop is
begin
process(CLK)
begin
if CLK 'event and CLK = '1' THEN
Q <= D;
end if;
end process;
end behavioral;
|
<filename>alu.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY ALU IS
PORT(
A,B : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
S : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
CIN : IN STD_LOGIC;
COUT: OUT STD_LOGIC;
F : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END ALU;
ARCHITECTURE ALU_FUNC OF ALU IS
COMPONENT PARTB IS
PORT(
A,B : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
S : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
CIN : IN STD_LOGIC;
F : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
COUT : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT PARTC IS
PORT(
A : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
S : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
CIN : IN STD_LOGIC;
F : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
COUT : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT PARTD IS
PORT(
A : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
S : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
CIN : IN STD_LOGIC;
F : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
COUT : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL FB,FC,FD : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL COUTB,COUTC,COUTD: STD_LOGIC;
BEGIN
PPART_B: PARTB PORT MAP(A,B,S(1 DOWNTO 0),CIN,FB,COUTB);
PART_C: PARTC PORT MAP(A,S(1 DOWNTO 0),CIN,FC,COUTC);
PART_D: PARTD PORT MAP(A,S(1 DOWNTO 0),CIN,FD,COUTD);
COUT <= COUTC WHEN S (3 DOWNTO 2)="10"
ELSE COUTD WHEN S (3 DOWNTO 2) ="11"
ELSE COUTB;
F <= FB WHEN S (3 DOWNTO 2) ="01"
ELSE FC WHEN S (3 DOWNTO 2) ="10"
ELSE FD WHEN S (3 DOWNTO 2) ="11";
END ALU_FUNC;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 26.02.2022 09:51:40
-- Design Name:
-- Module Name: switch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity switch is
generic (
-- Parallelismo della comunicazione
M:integer:=2;
-- Numero di bits su cui e' rappresentata la
-- destinazione
N_Addr: integer:=2
);
port(
-- Input della prima macchina
in0_input: in std_logic_vector(0 to M-1);
-- Input della seconda macchina
in1_input: in std_logic_vector(0 to M-1);
-- Input della terza macchina
in2_input: in std_logic_vector(0 to M-1);
-- Input della quarta macchina
in3_input: in std_logic_vector(0 to M-1);
-- Ingressi di enable, se uno di loro e' 1
-- vale 1 tutta l'uscita
in0_enable: in std_logic;
in1_enable: in std_logic;
in2_enable: in std_logic;
in3_enable: in std_logic;
-- Indirizzo della destinazione
dest: in std_logic_vector(0 to N_Addr-1);
-- Destinazioni
out0_output: out std_logic_vector(0 to M-1);
out1_output: out std_logic_vector(0 to M-1);
out2_output: out std_logic_vector(0 to M-1);
out3_output: out std_logic_vector(0 to M-1)
);
end switch;
architecture Structural of switch is
component node is
generic (
-- Parallelismo della comunicazione
M: integer:= 2
);
port(
-- Segnale di dati per il primo ingresso
in0_data: std_logic_vector( 0 to M-1);
in0_enable: std_logic;
in1_data: std_logic_vector( 0 to M-1);
in1_enable: std_logic;
output_0: out std_logic_vector(0 to M-1);
output_1: out std_logic_vector(0 to M-1);
sel: std_logic
);
end component;
--outputSTADIO_NumeroOutput
signal output0_0:std_logic_vector(0 to M-1);
signal output0_1:std_logic_vector(0 to M-1);
signal output0_2:std_logic_vector(0 to M-1);
signal output0_3:std_logic_vector(0 to M-1);
signal output1_0:std_logic_vector(0 to M-1);
signal output1_1:std_logic_vector(0 to M-1);
signal output1_2:std_logic_vector(0 to M-1);
signal output1_3:std_logic_vector(0 to M-1);
signal enable_shuffling:std_logic_vector(0 to 3);
begin
-- N1_0 ha il primo ingresso valido se le macchine 0 o 1 parlano
enable_shuffling(0)<=in0_enable or in1_enable;
-- Il secondo ingresso di n1_0 e' valido se stanno parlando 2 o 3
enable_shuffling(1)<=in2_enable or in3_enable;
-- il primo ingresso di n1_1 e' valido se sta parlando
-- la prima macchina o la seconda
enable_shuffling(2)<=in0_enable or in1_enable;
-- Il secondo ingresso di n1_1 e' valido se stanno parlando 2 o 3
enable_shuffling(3)<=in2_enable or in3_enable;
-- First stage
n0_0: node
generic map(
M=>2
)
port map(
in0_data=>in0_input,
in0_enable=>in0_enable,
in1_data=>in1_input,
in1_enable=>in1_enable,
sel=>dest(0),
output_0=>output0_0,
output_1=>output0_1
);
n0_1: node
generic map(
M=>2
)
port map(
in0_data=>in2_input,
in0_enable=>in2_enable,
in1_data=>in3_input,
in1_enable=>in3_enable,
sel=>dest(0),
output_0=>output0_2,
output_1=>output0_3
);
-- Second stage
n1_0: node
generic map(
M=>2
)
port map(
in0_data=>output0_0,
in0_enable=>enable_shuffling(0),
in1_data=>output0_2,
in1_enable=>enable_shuffling(1),
sel=>dest(1),
output_0=>output1_0,
output_1=>output1_1
);
n1_1: node
generic map(
M=>2
)
port map(
in0_data=>output0_1,
in0_enable=>enable_shuffling(2),
in1_data=>output0_3,
in1_enable=>enable_shuffling(3),
sel=>dest(1),
output_0=>output1_2,
output_1=>output1_3
);
out0_output<=output1_0;
out1_output<=output1_1;
out2_output<=output1_2;
out3_output<=output1_3;
end Structural;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
entity fifo is
port(
rst : in std_logic;
clk : in std_logic;
dia : in std_logic_vector(7 downto 0);
ena : in std_logic;
full : out std_logic;
dob : out std_logic_vector(7 downto 0);
enb : in std_logic;
empty : out std_logic
);
end fifo;
architecture Structural of fifo is
signal addra : unsigned(10 downto 0);
signal addrb : unsigned(10 downto 0);
type mem_t is array(2047 downto 0) of std_logic_vector(7 downto 0);
signal mem : mem_t;
signal empty_i : std_logic;
signal full_i : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
addra <= (others => '0');
addrb <= (others => '0');
else
if ena = '1' and full_i = '0' then
mem(to_integer(addra)) <= dia;
addra <= addra + 1;
end if;
if enb = '1' and empty_i = '0' then
dob <= mem(to_integer(addrb));
addrb <= addrb + 1;
end if;
end if;
end if;
end process;
empty_i <= '1' when addra = addrb else
'0';
full_i <= '1' when addra = addrb - 1 else
'0';
empty <= empty_i;
full <= full_i;
end Structural;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity slt is
port( in_A : in std_logic;
in_B : in std_logic;
o_C : out std_logic);
end slt;
architecture dataflow of slt is
begin
o_c <= '1' when in_A < in_B else
'0';
end dataflow;
|
<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
entity SequenceFSM is
port( input,clk,rst: in std_logic;
output: out std_logic);
end;
Architecture SeqFSM of SequenceFSM is
type state is (s0,s1,s11,s110,s1101);
signal currentState: state:=s0;
signal nextState: state:=s0;
begin
process(clk,rst) --only changes state
begin
if(rst='1') then
currentState<= s0;
elsif(clk'event and clk='1') then --rising
currentState<= nextState;
end if;
end process;
process(input,currentState) -- output func / state func
begin
if(currentState = s0) then
output<='0'; -- output 0 anyway
case input is
when '0' => nextState<=s0;
when '1' => nextState<=s1;
end case;
elsif(currentState = s1) then
output<='0'; -- output 0 anyway
case input is
when '0' => nextState<=s0;
when '1' => nextState<=s11;
end case;
elsif(currentState = s11) then
output<='0'; -- output 0 anyway
case input is
when '0' => nextState<=s110;
when '1' => nextState<=s11;
end case;
elsif(currentState = s110) then
output<='0'; -- output 0 anyway
case input is
when '0' => nextState<=s0;
when '1' => nextState<=s1101;
end case;
elsif(currentState = s1101) then
output<='1'; -- output always 1 at 1101
case input is
when '0' => nextState<=s0;
when '1' => nextState<=s1;
end case;
end if;
end process;
end SeqFSM;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, <NAME>
-- Copyright (C) 2015 - 2017, <NAME>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: Various
-- File: grgates.vhd
-- Author: <NAME> - Gaisler Research
-- Description: Various gates with tech mapping
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use work.allclkgen.all;
entity grmux2 is generic( tech : integer := inferred; imp : integer := 0);
port( ip0, ip1, sel : in std_logic; op : out std_ulogic); end;
architecture rtl of grmux2 is
component ut130hbd_mux2
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component mux2_ut90nhbd
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component mux2_rhs65
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
constant has_mux2 : tech_ability_type :=
( rhlib18t => 1, ut130 => 1, ut90 => 1, rhs65 => 1, others => 0);
begin
y0 : if has_mux2(tech) = 1 generate
rhlib : if tech = rhlib18t generate
x0 : clkmux_rhlib18t port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
ut13 : if tech = ut130 generate
x0 : ut130hbd_mux2 port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
ut90n : if tech = ut90 generate
x0 : mux2_ut90nhbd port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
rhs65n: if tech=rhs65 generate
x0 : mux2_rhs65 port map (i0 => ip0, i1 => ip1, sel => sel, o => op);
end generate;
end generate;
y1 : if has_mux2(tech) = 0 generate
op <= ip0 when sel = '0' else ip1;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grmux2v is generic( tech : integer := inferred;
bits : integer := 2; imp : integer := 0);
port( ip0, ip1 : in std_logic_vector(bits-1 downto 0);
sel : in std_logic;
op : out std_logic_vector(bits-1 downto 0));
end;
architecture rtl of grmux2v is
begin
x0 : for i in bits-1 downto 0 generate
y0 : grmux2 generic map (tech, imp) port map (ip0(i), ip1(i), sel, op(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grdff is generic( tech : integer := inferred; imp : integer := 0);
port( clk, d : in std_ulogic; q : out std_ulogic); end;
architecture rtl of grdff is
component ut130hbd_dff
port(
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic);
end component;
component dff_ut90nhbd
port(
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic);
end component;
constant has_dff : tech_ability_type :=
( ut130 => 1, ut90 => 1, others => 0);
begin
y0 : if has_dff(tech) = 1 generate
ut13 : if tech = ut130 generate
x0 : ut130hbd_dff port map (clk => clk, d => d, q => q);
end generate;
ut90n : if tech = ut90 generate
x0 : dff_ut90nhbd port map (clk => clk, d => d, q => q);
end generate;
end generate;
y1 : if has_dff(tech) = 0 generate
x0 : process(clk)
begin if rising_edge(clk) then q <= d; end if; end process;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity gror2 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end;
architecture rtl of gror2 is
component ut130hbd_or2
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
q : out std_ulogic);
end component;
component or2_ut90nhbd
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
o : out std_ulogic);
end component;
constant has_or2 : tech_ability_type :=
( ut130 => 1, ut90 => 1, others => 0);
begin
y0 : if has_or2(tech) = 1 generate
ut13 : if tech = ut130 generate
x0 : ut130hbd_or2 port map (i0 => i0, i1 => i1, q => q);
end generate;
ut90n : if tech = ut90 generate
x0 : or2_ut90nhbd port map (i0 => i0, i1 => i1, o => q);
end generate;
end generate;
y1 : if has_or2(tech) = 0 generate
q <= i0 or i1;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grand12 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end;
architecture rtl of grand12 is
component ut130hbd_and12
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
q : out std_ulogic);
end component;
component and12_ut90nhbd
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
o : out std_ulogic);
end component;
constant has_and12 : tech_ability_type :=
( ut130 => 1, ut90 => 1, others => 0);
begin
y0 : if has_and12(tech) = 1 generate
ut13 : if tech = ut130 generate
x0 : ut130hbd_and12 port map (i0 => i0, i1 => i1, q => q);
end generate;
ut90n : if tech = ut90 generate
x0 : and12_ut90nhbd port map (i0 => i0, i1 => i1, o => q);
end generate;
end generate;
y1 : if has_and12(tech) = 0 generate
q <= i0 and not i1;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity grnand2 is
generic (
tech: integer := 0;
imp: integer := 0
);
port (
i0: in std_ulogic;
i1: in std_ulogic;
q : out std_ulogic
);
end;
architecture rtl of grnand2 is
constant has_nand2: tech_ability_type := (others => 0);
begin
y0: if has_nand2(tech)=1 generate
end generate;
y1: if has_nand2(tech)=0 generate
q <= not (i0 and i1);
end generate;
end;
|
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.decode_pkg.all;
use work.common_pkg.all;
entity Decode is
port( Clk : in std_logic;
decode_d : in decode_in;
decode_q : out decode_out
);
end entity Decode;
Architecture a_Decode of Decode is
component register_block is
port(
clk : in std_logic;
read_add_a : in std_logic_vector(2 downto 0);
read_add_b : in std_logic_vector(2 downto 0);
write_en : in std_logic;
write_val : in std_logic_vector(15 downto 0);
write_add : in std_logic_vector(2 downto 0);
write_stackVal: in std_logic_vector(15 downto 0);
write_stackEn : in std_logic;
rega, regb : out std_logic_vector(15 downto 0);
read_STACK : out std_logic_vector(15 downto 0)
);
end component;
signal Reg_Src : regAddr;
signal Reg_Des : regAddr;
begin
Reg_Src <= decode_d.Instruction(7 downto 5) when decode_d.Instruction(15 downto 12) = "0111"
else decode_d.Instruction(10 downto 8);
Reg_Des <= decode_d.Instruction(10 downto 8) when decode_d.Instruction(15 downto 11) = "11011" or decode_d.Instruction(15 downto 12) = "0111" --STD or SHR or SHL
else decode_d.Instruction(7 downto 5);
reg0: register_block port map (clk=>Clk , write_stackVal=>decode_d.Write_Stack_Val,write_stackEn=>decode_d.Write_Stack_Enable, read_add_a=> Reg_Src , read_add_b=> Reg_Des , write_en=>decode_d.Write_Enable , write_val=>decode_d.Write_Val , write_add=>decode_d.Write_Address , rega=>decode_q.Data1 , regb=>decode_q.Data2 , read_STACK=>decode_q.Out_STACK );
end Architecture a_Decode;
|
<filename>labo3/src_tb/agent1_pkg.vhd<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library tlmvm;
context tlmvm.tlmvm_context;
library project_lib;
context project_lib.project_ctx;
use project_lib.output_transaction_fifo_pkg.all;
use project_lib.transactions_pkg.all;
use project_lib.spike_detection_pkg.all;
package agent1_pkg is
procedure monitor(variable fifo : inout work.output_transaction_fifo_pkg.tlm_fifo_type;
signal clk : in std_logic;
signal rst : in std_logic;
signal port_output : in port1_output_t
);
end package;
package body agent1_pkg is
procedure monitor(variable fifo : inout work.output_transaction_fifo_pkg.tlm_fifo_type;
signal clk : in std_logic;
signal rst : in std_logic;
signal port_output : in port1_output_t
) is
variable transaction : output_transaction_t;
variable counter : integer;
variable ok : boolean;
begin
counter := 0;
while true loop
logger.log_note("[Monitor 1] waiting for transaction number " & integer'image(counter));
ok := false;
while ok = false loop
wait until rising_edge(clk);
if (port_output.samples_spikes_valid = '1') then
transaction.data_out_trans(counter) := port_output.samples_spikes;
counter := counter + 1;
if (port_output.spike_detected = '1') then -- last sample received
logger.log_note("[Monitor 1] Sending to scoreboard " & integer'image(counter));
blocking_put(fifo, transaction);
counter := 0;
end if;
if(counter = 150) then
logger.log_error("[Monitor 1] Spike signal not detected by the DUT ");
counter := 0;
end if;
logger.log_note("[Monitor 1] received transaction number " & integer'image(counter));
ok := true;
end if;
end loop;
end loop;
wait;
end monitor;
end package body;
|
<filename>src/general-components/mux_2_1_mod.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY mux_2_1_mod IS
PORT (
RESET : IN STD_LOGIC;
selector : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
muxIn1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
muxIn2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
muxOut : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END mux_2_1_mod;
ARCHITECTURE mux_logic OF mux_2_1_mod IS
BEGIN
muxOut <= (OTHERS => '0') WHEN (RESET = '1') ELSE
muxIn2 WHEN selector = "10" ELSE
muxIn1 WHEN selector = "01";
END mux_logic;
|
<gh_stars>0
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.DLX_package.all;
ENTITY DMA is
GENERIC(N_bit : integer := 64; --Number of bits
M : integer := 8; -- Number of global registers
N : integer := 8; -- Number of registers in each IN, OUT and LOCALS
F : integer := 4); -- Number of windows
PORT(
RESET_N : IN std_logic;
CLK : IN std_logic;
CALL : IN std_logic;
RET : IN std_logic;
CALL_ROLLBACK : IN std_logic;
RET_ROLLBACK : IN std_logic;
CWP_ENABLE : IN std_logic;
SPILL : OUT std_logic;
FILL : OUT std_logic;
CWP : OUT unsigned(up_int_log2(F)-1 downto 0);
DATA_OUT : OUT std_logic_vector(Nbit-1 downto 0));
END ENTITY;
ARCHITECTURE Behavioral OF DMA IS
component up_counter
GENERIC( N : integer := 16);
PORT( CLK : IN std_logic;
RESET_N : IN std_logic;
EN : IN std_logic;
TC_value : IN std_logic_vector(N-1 downto 0);
Q : OUT std_logic_vector(N-1 downto 0);
TC : OUT std_logic);
end component;
component down_counter
GENERIC( N : integer := 16);
PORT( CLK : IN std_logic;
RESET_N : IN std_logic;
EN : IN std_logic;
TC_value : IN std_logic_vector(N-1 downto 0);
Q : OUT std_logic_vector(N-1 downto 0);
TC : OUT std_logic);
end component;
-- constants
constant swp_reset_val : unsigned(up_int_log2(F)-1 downto 0) := (others => '1');
constant up_counter_tc : std_logic_vector(up_int_log2(3*N)-1 downto 0) := std_logic_vector(to_unsigned(23, up_int_log2(3*N)));
constant down_counter_tc : std_logic_vector(up_int_log2(3*N)-1 downto 0) := std_logic_vector(to_unsigned(0, up_int_log2(3*N)));
-- cwp/swp
signal cwp_s : unsigned(up_int_log2(F)-1 downto 0);
signal cwp_reg_s : unsigned(up_int_log2(F)-1 downto 0);
signal swp_s : unsigned(up_int_log2(F)-1 downto 0);
signal spill_s : std_logic;
signal fill_s : std_logic;
signal fill_delay_1 : std_logic;
signal fill_delay_2 : std_logic;
signal fill_delay_3 : std_logic;
signal fill_delay_4 : std_logic;
signal fill_delay_s : std_logic;
signal intn_fp_reg_s : std_logic;
signal spill_fill_end_s : std_logic;
-- signal SWP : unsigned(up_int_log2(F)-1 downto 0);
signal cansave_canrestore_s : std_logic;
-- counters
signal up_counter_out : std_logic_vector(up_int_log2(4*N)-1 downto 0);
signal down_counter_out : std_logic_vector(up_int_log2(4*N)-1 downto 0);
signal up_tc : std_logic;
signal down_tc : std_logic;
signal reset_n_up_counter : std_logic;
signal reset_n_down_counter : std_logic;
signal IR_value : std_logic_vector(Nbit-1 downto 0);
BEGIN
SPILL <= spill_s;
FILL <= fill_s;
DATA_OUT <= IR_value;
CWP <= swp_s when fill_delay_s = '1' else
cwp_reg_s;
reset_n_up_counter <= RESET_N;
reset_n_down_counter <= RESET_N;
fill_delay_s <= fill_delay_1 or fill_delay_2 or fill_delay_3 or fill_delay_4;
up_counter_c : up_counter
generic map(up_int_log2(3*N))
port map(CLK, reset_n_up_counter, spill_s, up_counter_tc, up_counter_out, up_tc);
down_counter_c : down_counter
generic map(up_int_log2(3*N))
port map(CLK, reset_n_down_counter, fill_s, down_counter_tc, down_counter_out, down_tc);
cwp_counter_p : process(RESET_N, CALL, RET, CALL_ROLLBACK, RET_ROLLBACK)
begin
if RESET_N = '0' then
cwp_s <= (others => '0');
elsif CALL = '1' or RET_ROLLBACK = '1' then
cwp_s <= cwp_s + 1;
elsif RET = '1' or CALL_ROLLBACK = '1' then
cwp_s <= cwp_s - 1;
end if;
end process;
cwp_reg_p : process(RESET_N, CLK)
begin
if RESET_N = '0' then
cwp_reg_s <= (others => '0');
elsif CLK'event and CLK = '1' then
cwp_reg_s <= cwp_s;
end if;
end process;
swp_counter_p : process(RESET_N, CLK)
begin
if RESET_N = '0' then
swp_s <= (others => '1');
elsif CLK'event and CLK = '1' then
if (CALL = '1' and cansave_canrestore_s = '0') then
swp_s <= swp_s + 1;
elsif (RET = '1' and cansave_canrestore_s = '0') then
swp_s <= swp_s - 1;
end if;
end if;
end process;
cansave_canrestore_p : process(swp_s, cwp_s)
begin
if swp_s - cwp_s = 0 then
cansave_canrestore_s <= '0';
else
cansave_canrestore_s <= '1';
end if;
end process;
spill_p : process(RESET_N, spill_fill_end_s, CALL, cansave_canrestore_s)
begin
if RESET_N = '0' then
spill_s <= '0';
else
if spill_fill_end_s = '1' then
spill_s <= '0';
elsif (CALL = '1' and cansave_canrestore_s = '0') then
spill_s <= '1';
end if;
end if;
end process;
fill_p : process(RESET_N, spill_fill_end_s, RET, cansave_canrestore_s)
begin
if RESET_N = '0' then
fill_s <= '0';
else
if spill_fill_end_s = '1' then
fill_s <= '0';
elsif (RET = '1' and cansave_canrestore_s = '0') then
fill_s <= '1';
end if;
end if;
end process;
intn_fp_flag_p : process(RESET_N, CLK, CALL, RET, CALL_ROLLBACK, RET_ROLLBACK)
begin
if RESET_N = '0' or CALL = '1' or CALL_ROLLBACK = '1' or RET_ROLLBACK = '1' then
intn_fp_reg_s <= '0';
elsif CLK'event and CLK = '1' then
if up_tc = '1' or down_tc = '1' then
intn_fp_reg_s <= not(intn_fp_reg_s);
end if;
end if;
end process;
spill_fill_end_p : process(RESET_N, CLK)
begin
if RESET_N = '0' then
spill_fill_end_s <= '0';
elsif CLK'event and CLK = '1' then
if (up_tc = '1' or down_tc = '1') and intn_fp_reg_s = '1' then
spill_fill_end_s <= '1';
else
spill_fill_end_s <= '0';
end if;
end if;
end process;
fill_delay_p : process(CLK, RESET_N)
begin
if RESET_N = '0' then
fill_delay_1 <= '0';
fill_delay_2 <= '0';
fill_delay_3 <= '0';
fill_delay_4 <= '0';
elsif CLK'event and CLK = '1' then
fill_delay_1 <= fill_s;
fill_delay_2 <= fill_delay_1;
fill_delay_3 <= fill_delay_2;
fill_delay_4 <= fill_delay_3;
end if;
end process;
-----------------------------------------------------------
-- IR spill fill value
-----------------------------------------------------------
instruction_process : process(spill_s, fill_s, up_counter_out, down_counter_out, intn_fp_reg_s)
begin
if spill_s = '1' then
-- opcode
if intn_fp_reg_s = '0' then
IR_value(OPCODE_RANGE) <= "011110"; -- PUSH (0x1E)
else
IR_value(OPCODE_RANGE) <= "101100"; -- PUSHF (0x2C)
end if;
-- source reg
IR_value(25 downto 21) <= "11101"; -- R29 (stack pointer)
-- dest reg
IR_value(20 downto 16) <= up_counter_out; -- address of reg to save
--immediate
IR_value(15 downto 0) <= (others => '0');
elsif fill_s = '1' then
-- opcode
if intn_fp_reg_s = '0' then
IR_value(OPCODE_RANGE) <= "101101"; -- POPF (0x2D)
else
IR_value(OPCODE_RANGE) <= "011111"; -- POP (0x1F)
end if;
-- source reg
IR_value(25 downto 21) <= "11101"; -- R29 (stack pointer)
-- dest reg
IR_value(20 downto 16) <= down_counter_out; -- address of reg to write
--immediate
IR_value(15 downto 0) <= std_logic_vector(to_unsigned(4, 16));
else
IR_value <= IR_NOP_VALUE;
end if;
end process;
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; --to_integer
entity DATA_MEMORY is
generic (p_SIZE : integer := 32);
port(
i_DATA : in std_logic_vector(p_SIZE-1 downto 0);
i_ADDR : in std_logic_vector(p_SIZE-1 downto 0);
i_CLK : in std_logic;
i_MemWrite : in std_logic;
o_DATA : out std_logic_vector(p_SIZE-1 downto 0)
);
end DATA_MEMORY;
architecture arch1 of DATA_MEMORY is
type t_MEM is array(255 downto 0) of std_logic_vector(p_SIZE-1 downto 0);
signal w_MEM : t_MEM := (others=>(others=>'0'));
signal w_ADDR : std_logic_vector(7 downto 0);
begin
w_ADDR <= i_ADDR(7 downto 0);
process (i_CLK, i_MemWrite)
begin
if(rising_edge(i_CLK)) then
if (i_MemWrite = '1') then
w_MEM(to_integer(unsigned(w_ADDR))/4) <= i_DATA;
end if;
end if;
end process;
o_DATA <= w_MEM(to_integer(unsigned(w_ADDR)));
end arch1;
|
<gh_stars>1-10
-------------------------------------------------------------------------------
-- File : TBAxiStreamReloadFIR.vhd
-- Company : SLAC National Accelerator Laboratory
-- Created : 2017-10-24
-- Last update: 2018-11-08
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- This file is part of 'axi-pcie-dev'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'axi-pcie-dev', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library surf;
use surf.StdRtlPkg.all;
use surf.AxiPkg.all;
use surf.AxiLitePkg.all;
use surf.AxiStreamPkg.all;
library axi_pcie_core;
use axi_pcie_core.AxiPciePkg.all;
library lcls_timing_core;
use lcls_timing_core.TimingPkg.all;
use surf.Pgp2bPkg.all;
use surf.SsiPkg.all;
library timetool;
use timetool.TestingPkg.all;
use STD.textio.all;
use ieee.std_logic_textio.all;
entity TBAxiStreamReloadFIR is end TBAxiStreamReloadFIR;
architecture testbed of TBAxiStreamReloadFIR is
constant FIR_COEF_FILE_NAME : string := TEST_FILE_PATH & "/fir_coef.dat";
constant TEST_OUTPUT_FILE_NAME : string := TEST_FILE_PATH & "/output_results.dat";
constant AXI_BASE_ADDR_G : slv(31 downto 0) := x"00C0_0000";
constant TPD_G : time := 1 ns;
constant DMA_SIZE_C : positive := 1;
----------------------------
----------------------------
----------------------------
constant DMA_AXIS_CONFIG_G : AxiStreamConfigType := ssiAxiStreamConfig(16, TKEEP_COMP_C, TUSER_FIRST_LAST_C, 8, 2);
constant DMA_AXIS_DOWNSIZED_CONFIG_G : AxiStreamConfigType := ssiAxiStreamConfig(1, TKEEP_COMP_C, TUSER_FIRST_LAST_C, 1, 2);
constant CLK_PERIOD_G : time := 10 ns;
constant T_HOLD : time := 100 ps;
file fir_coef_file : text;
signal appInMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
signal appInSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C;
signal appOutMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
signal appOutSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C;
signal reloadInMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
signal reloadInSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C;
signal configInMaster : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
signal configInSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C;
-- Event signals
signal event_s_reload_tlast_missing : std_logic := '0'; -- reloadInMaster.tLast low at end of reload packet
signal event_s_reload_tlast_unexpected : std_logic := '0'; -- reloadInMaster.tLast high not at end of reload packet
signal axiClk : sl;
signal axiRst : sl;
begin
--------------------
-- Clocks and Resets
--------------------
U_axilClk : entity surf.ClkRst
generic map (
CLK_PERIOD_G => CLK_PERIOD_G,
RST_START_DELAY_G => 1 ns,
RST_HOLD_TIME_G => 50 ns)
port map (
clkP => axiClk,
rst => axiRst);
--------------------
-- Test data
--------------------
U_CamOutput : entity timetool.FileToAxiStream
generic map (
TPD_G => TPD_G,
BYTE_SIZE_C => 2+1,
DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_G,
CLK_PERIOD_G => 10 ns)
port map (
sysClk => axiClk,
sysRst => axiRst,
dataOutMaster => appInMaster,
dataOutSlave => appInSlave);
--------------------
-- Surf wrapped FIR filter
--------------------
edge_to_peak: entity timetool.FrameFIR
generic map(
TPD_G => TPD_G,
DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_G,
DEBUG_G => true )
port map(
-- System Interface
sysClk => axiClk,
sysRst => axiRst,
-- DMA Interfaces (sysClk domain)
dataInMaster => appInMaster,
dataInSlave => appInSlave,
dataOutMaster => appOutMaster,
dataOutSlave => appOutSlave,
-- coefficient reload (sysClk domain)
reloadInMaster => reloadInMaster,
reloadInSlave => reloadInSlave,
configInMaster => configInMaster,
configInSlave => configInSlave);
U_FileInput : entity timetool.AxiStreamToFile
generic map (
TPD_G => TPD_G,
BYTE_SIZE_C => 2+1,
DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_G,
CLK_PERIOD_G => 10 ns)
port map (
sysClk => axiClk,
sysRst => axiRst,
dataInMaster => appOutMaster,
dataInSlave => appOutSlave);
------------------------------------------------
------------------------------------------------
------------------------------------------------
------------------------------------------------
------------------------------------------------
reload_coeffs : process is
variable v_ILINE : line;
variable my_coef : slv(7 downto 0);
begin
file_open(fir_coef_file,FIR_COEF_FILE_NAME ,read_mode);
wait for 1 us;
for coef in 0 to 31 loop
readline(fir_coef_file,v_ILINE);
read(v_ILINE,my_coef);
reloadInMaster.tValid <= '1';
reloadInMaster.tData <= (others => '0'); -- clear unused bits of TDATA
reloadInMaster.tData(7 downto 0) <= my_coef;
if coef = 31 then
reloadInMaster.tLast <= '1'; -- signal last transaction in reload packet
else
reloadInMaster.tLast <= '0';
end if;
loop
wait until rising_edge(axiClk);
exit when reloadInSlave.tReady = '1';
end loop;
wait for T_HOLD;
end loop;
reloadInMaster.tLast <= '0';
reloadInMaster.tValid <= '0';
-- A packet on the config slave channel signals that the new coefficients should now be used.
-- The config packet is required only for signalling: its data is irrelevant.
configInMaster.tValid <= '1';
configInMaster.tData <= (others => '0'); -- don't care about TDATA - it is unused
loop
wait until rising_edge(axiClk);
exit when configInSlave.tReady = '1';
end loop;
wait for T_HOLD;
wait for 10 ms;
end process reload_coeffs;
end testbed;
|
<reponame>MyersResearchGroup/ATACS
--\begin{comment}
----------------------
-- winery9.vhd
----------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.nondeterminism.all;
use work.channel.all;
entity winery is
port(wine_to_old_shop, wine_to_new_shop : inout channel :=
init_channel(sender => timing(5, 10)));
end winery;
architecture behavior of winery is
signal bottle1 : std_logic_vector( 2 downto 0 ) := "000";
signal bottle2 : std_logic_vector( 2 downto 0 ) := "011";
begin
--\end{comment}
winery : process
begin
send(wine_to_old_shop, bottle1,
wine_to_new_shop, bottle2);
--@synthesis_off
bottle1 <= bottle1 + 1;
bottle2 <= bottle2 + 1;
--@synthesis_on
end process winery;
end behavior; --tex comment
|
<filename>source_code/system_creation/lib/common_files/standard_top_level.vhd<gh_stars>1-10
-------------------------------------------------------
--! @file
--! @brief The standard top level VHDL file used by the projects after it has been adapted by prepare_vhdl::prepare_vhdl_file()
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--! A debouncer is used to connect the board buttons to the VHDL signals
ENTITY debounce IS
GENERIC(
counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)
PORT(
clk : IN STD_LOGIC; --input clock
button : IN STD_LOGIC; --input signal to be debounced
result : OUT STD_LOGIC); --debounced signal
END debounce;
ARCHITECTURE logic OF debounce IS
SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
SIGNAL counter_set : STD_LOGIC; --sync reset to zero
SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output
BEGIN
counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
PROCESS(clk)
BEGIN
IF(clk'EVENT and clk = '1') THEN
flipflops(0) <= button;
flipflops(1) <= flipflops(0);
If(counter_set = '1') THEN --reset counter because input is changing
counter_out <= (OTHERS => '0');
ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met
counter_out <= counter_out + 1;
ELSE --stable input time is met
result <= flipflops(1);
END IF;
END IF;
END PROCESS;
END logic;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! @brief This entity is the top level instantiating all modules.
--! @details The SOPC Builder-generated system and the debouncer (for the reset key) components are instantiated and connected using signals.
--! Additionally, the rightmost green LED is connected to always light up, thereby signalling the success of the FPGA programming.
entity top_level_entity is
port (
CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 0);
LEDG : out std_logic_vector(8 downto 0);
LEDR : out std_logic_vector(17 downto 0);
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
SRAM_ADDR : out std_logic_vector(19 downto 0);
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_WE_N : out std_logic
);
end top_level_entity;
architecture rtl of top_level_entity is
component sopc_system is
port (
signal clock_0 : in std_logic;
signal reset_n : in std_logic;
-- signal out_port_from_the_LEDs_green : out std_logic_vector(7 downto 0)
-- the_sram
signal SRAM_ADDR_from_the_sram : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
signal SRAM_CE_N_from_the_sram : OUT STD_LOGIC;
signal SRAM_DQ_to_and_from_the_sram : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
signal SRAM_LB_N_from_the_sram : OUT STD_LOGIC;
signal SRAM_OE_N_from_the_sram : OUT STD_LOGIC;
signal SRAM_UB_N_from_the_sram : OUT STD_LOGIC;
signal SRAM_WE_N_from_the_sram : OUT STD_LOGIC
);
end component sopc_system;
component debounce is
generic(
counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)
port(
clk : IN STD_LOGIC; --input clock
button : IN STD_LOGIC; --input signal to be debounced
result : OUT STD_LOGIC --debounced signal
);
end component debounce;
-- signal right_green_led_row : std_logic_vector(7 downto 0) := (others => '0');
signal debounced_reset_key : std_logic := '0';
begin
-- turn the single LED 8 on to show that the programming worked
LEDG(8) <= '1';
-- turn all other LEDs and the seven-segment displays off
LEDG(7 downto 1) <= (others => '0');
-- the rightmost green LED shows whether the reset key is pressed
LEDG(0) <= not debounced_reset_key;
LEDR <= (others => '0');
HEX7 <= (others => '1');
HEX6 <= (others => '1');
HEX5 <= (others => '1');
HEX4 <= (others => '1');
HEX3 <= (others => '1');
HEX2 <= (others => '1');
HEX1 <= (others => '1');
HEX0 <= (others => '1');
reset_key_debounce : debounce
port map(
clk => CLOCK_50,
button => KEY(0),
result => debounced_reset_key
);
-- Instantiate the Nios II system entity generated by the SOPC Builder.
sopc_system_instance : sopc_system
port map(
SRAM_ADDR_from_the_sram => SRAM_ADDR,
SRAM_CE_N_from_the_sram => SRAM_CE_N,
SRAM_DQ_to_and_from_the_sram => SRAM_DQ,
SRAM_LB_N_from_the_sram => SRAM_LB_N,
SRAM_OE_N_from_the_sram => SRAM_OE_N,
SRAM_UB_N_from_the_sram => SRAM_UB_N,
SRAM_WE_N_from_the_sram => SRAM_WE_N,
-- out_port_from_the_LEDs_green => right_green_led_row,
clock_0 => CLOCK_50,
reset_n => debounced_reset_key
-- reset_n => '1'
);
end rtl;
|
<reponame>CyAScott/CIS4930.DatapathSynthesisTool<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_comparator is
generic
(
width : integer := 16
);
port
(
input1 : in std_logic_vector((width - 1) downto 0);
input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector(2 downto 0)
);
end c_comparator;
architecture behavior of c_comparator is
function twocomp_bits_to_int (input : std_logic_vector)return integer is
variable ret_val : integer := 0;
begin
for i in input'range loop
if (i < input'HIGH) then
if (input(input'HIGH) = '0') then
if input(i) = '1' then
ret_val := 2 ** i + ret_val;
end if;
else
if input(i) = '0' then
ret_val := 2 ** i + ret_val;
end if;
end if;
end if;
end loop;
if (input(input'HIGH) = '1') then
ret_val := ret_val + 1;
ret_val := 0 - ret_val;
end if; return ret_val;
end twocomp_bits_to_int;
begin
P0 : process (input1, input2)
variable result : std_logic_vector(2 downto 0);
variable inp1, inp2 : integer;
begin
result := "000";
inp1 := twocomp_bits_to_int(input1);
inp2 := twocomp_bits_to_int(input2);
if (inp1 = inp2) then
result(0) := '1';
end if;
if (inp1 > inp2) then
result(1) := '1';
end if;
if (inp1 < inp2) then
result(2) := '1';
end if;
output <= result;
end process P0;
end behavior;
|
<reponame>mfkiwl/ztachip
------------------------------------------------------------------------------
-- Copyright [2014] [Ztachip Technologies Inc]
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
------------------------------------------------------------------------------
-------
-- This is top component for MCORE processor
-- MCORE processor is based on MIPS architecture which is a 5 stage pipeline
-- architecture
-- MIPS-I architecture is chosen for its simplicity and the availability of compiler
-- tool (GNU)
-- Refer to http://en.wikipedia.org/wiki/MIPS_instruction_set for more information
-- MIPS-I instruction is supported in this implementation
--------
library std;
use std.standard.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.hpc_pkg.all;
ENTITY mcore IS
PORT(
SIGNAL clock_in : IN STD_LOGIC;
SIGNAL reset_in : IN STD_LOGIC;
SIGNAL sreset_in : IN STD_LOGIC;
-- IO interface
SIGNAL io_wren_out : OUT STD_LOGIC;
SIGNAL io_rden_out : OUT STD_LOGIC;
SIGNAL io_addr_out : OUT STD_LOGIC_VECTOR(io_depth_c-1 downto 0);
SIGNAL io_readdata_in : IN STD_LOGIC_VECTOR(mregister_width_c-1 downto 0);
SIGNAL io_writedata_out : OUT STD_LOGIC_VECTOR(mregister_width_c-1 downto 0);
SIGNAL io_byteena_out : OUT STD_LOGIC_VECTOR(mregister_byte_width_c-1 downto 0);
SIGNAL io_waitrequest_in : IN STD_LOGIC;
-- Programming interface for TEXT and DATA segments.
SIGNAL prog_text_ena_in : IN STD_LOGIC;
SIGNAL prog_text_addr_in : IN STD_LOGIC_VECTOR(mcore_instruction_depth_c-1 downto 0);
SIGNAL prog_text_data_in : IN STD_LOGIC_VECTOR(mcore_instruction_width_c-1 downto 0);
SIGNAL prog_data_ena_in : IN STD_LOGIC;
SIGNAL prog_data_addr_in : IN STD_LOGIC_VECTOR(mcore_ram_depth_c-1 downto 0);
SIGNAL prog_data_data_in : IN mregister_t
);
END mcore;
ARCHITECTURE behaviour OF mcore IS
SIGNAL rega_ena:STD_LOGIC;
SIGNAL regb_ena:STD_LOGIC;
SIGNAL reg_read_a_addr:mcore_regno_t;
SIGNAL reg_read_b_addr:mcore_regno_t;
SIGNAL reg_read_a_data:mregister_t;
SIGNAL reg_read_b_data:mregister_t;
SIGNAL reg_write_ena:STD_LOGIC;
SIGNAL reg_write_addr:mcore_regno_t;
SIGNAL reg_write_data:mregister_t;
SIGNAL rom_addr:STD_LOGIC_VECTOR(mcore_instruction_depth_c-1 DOWNTO 0);
SIGNAL rom_data:STD_LOGIC_VECTOR(mcore_instruction_width_c-1 downto 0);
SIGNAL mem_addr:STD_LOGIC_VECTOR(mcore_mem_depth_c-1 DOWNTO 0);
SIGNAL mem_readdata:mregister_t;
SIGNAL mem_write_data:mregister_t;
SIGNAL mem_write_ena:STD_LOGIC;
SIGNAL mem_read_ena:STD_LOGIC;
SIGNAL mem_byteena:STD_LOGIC_VECTOR(mregister_byte_width_c-1 downto 0);
SIGNAL ram_addr:STD_LOGIC_VECTOR(mcore_ram_depth_c-1 DOWNTO 0);
SIGNAL ram_readdata:mregister_t;
SIGNAL ram_write_data:mregister_t;
SIGNAL ram_write_ena:STD_LOGIC;
SIGNAL ram_read_ena:STD_LOGIC;
SIGNAL ram_byteena:STD_LOGIC_VECTOR(mregister_byte_width_c-1 downto 0);
SIGNAL jump:STD_LOGIC;
SIGNAL jump_addr:STD_LOGIC_VECTOR(mcore_instruction_depth_c-1 downto 0);
SIGNAL instruction_fetch:STD_LOGIC_VECTOR(mcore_instruction_width_c-1 downto 0);
SIGNAL instruction_pseudo:mcore_decoder_pseudo_t;
SIGNAL x_decoder:mregister_t;
SIGNAL y_decoder:mregister_t;
SIGNAL z_decoder:mregister_t;
SIGNAL z_addr_decoder:mcore_regno_t;
SIGNAL opcode_decoder:mcore_alu_funct_t;
SIGNAL pseudo_decoder:mcore_exe_pseudo_t;
SIGNAL load_decoder:STD_LOGIC;
SIGNAL store_decoder:STD_LOGIC;
SIGNAL wb_decoder:STD_LOGIC;
SIGNAL result_exe:mregister_t;
SIGNAL z_exe:mregister_t;
SIGNAL z_addr_exe:mcore_regno_t;
SIGNAL load_exe:STD_LOGIC;
SIGNAL store_exe:STD_LOGIC;
SIGNAL wb_exe:STD_LOGIC;
SIGNAL wb_ena_mem:STD_LOGIC;
SIGNAL wb_addr_mem:mcore_regno_t;
SIGNAL wb_data_mem:mregister_t;
SIGNAL wb_byteena:STD_LOGIC_VECTOR(mregister_byte_width_c-1 downto 0);
SIGNAL hazard_data_exe:mregister_t;
SIGNAL hazard_addr_exe:mcore_regno_t;
SIGNAL hazard_ena_exe:STD_LOGIC;
SIGNAL hazard_data_mem:mregister_t;
SIGNAL hazard_addr_mem:mcore_regno_t;
SIGNAL hazard_ena_mem:STD_LOGIC;
SIGNAL stall_addr_exe:mcore_regno_t;
SIGNAL stall_ena_exe:STD_LOGIC;
SIGNAL stall_addr_mem:mcore_regno_t;
SIGNAL stall_ena_mem:STD_LOGIC;
SIGNAL stall:STD_LOGIC;
SIGNAL freeze:STD_LOGIC;
SIGNAL pc_fetch:STD_LOGIC_VECTOR(mcore_instruction_depth_c-1 downto 0);
SIGNAL shamt:mcore_shamt_t;
SIGNAL mem_opcode_decoder:mcore_mem_funct_t;
SIGNAL mem_opcode_exe:mcore_mem_funct_t;
SIGNAL io:STD_LOGIC;
SIGNAL io_r:STD_LOGIC;
SIGNAL rega_addr_fetch:mcore_regno_t;
SIGNAL regb_addr_fetch:mcore_regno_t;
SIGNAL rega_ena_fetch:STD_LOGIC;
SIGNAL regb_ena_fetch:STD_LOGIC;
SIGNAL exe2_opcode:mcore_alu_funct_t;
SIGNAL exe2_req_exe:STD_LOGIC;
SIGNAL exe2_x:mregister_t;
SIGNAL exe2_y:mregister_t;
SIGNAL LO:mregister_t;
SIGNAL HI:mregister_t;
SIGNAL exe2_busy:STD_LOGIC;
SIGNAL load_exe2:STD_LOGIC;
SIGNAL mcore_reset:STD_LOGIC;
-- Programming register
SIGNAL prog_text_ena_r:STD_LOGIC;
SIGNAL prog_text_addr_r:STD_LOGIC_VECTOR(mcore_instruction_depth_c-1 downto 0);
SIGNAL prog_text_data_r:STD_LOGIC_VECTOR(mcore_instruction_width_c-1 downto 0);
SIGNAL prog_data_ena_r:STD_LOGIC;
SIGNAL prog_data_addr_r:STD_LOGIC_VECTOR(mcore_ram_depth_c-1 downto 0);
SIGNAL prog_data_data_r:mregister_t;
attribute dont_merge : boolean;
attribute dont_merge of prog_text_ena_r : SIGNAL is true;
attribute dont_merge of prog_text_addr_r : SIGNAL is true;
attribute dont_merge of prog_text_data_r : SIGNAL is true;
attribute dont_merge of prog_data_ena_r : SIGNAL is true;
attribute dont_merge of prog_data_addr_r : SIGNAL is true;
attribute dont_merge of prog_data_data_r : SIGNAL is true;
BEGIN
mcore_reset <= reset_in and sreset_in;
io <= mem_addr(mem_addr'length-1);
freeze <= (mem_write_ena or mem_read_ena) and io and io_waitrequest_in;
ram_addr <= mem_addr(ram_addr'length-1 downto 0) when prog_data_ena_r='0' else prog_data_addr_r;
ram_write_data <= mem_write_data when prog_data_ena_r='0' else prog_data_data_r;
ram_write_ena <= (mem_write_ena and (not io)) or prog_data_ena_r;
ram_read_ena <= mem_read_ena and (not io);
ram_byteena <= mem_byteena when prog_data_ena_r='0' else (others=>'1');
io_addr_out <= mem_addr(io_addr_out'length-1 downto 0);
io_writedata_out <= mem_write_data;
io_wren_out <= mem_write_ena and io;
io_rden_out <= mem_read_ena and io;
io_byteena_out <= mem_byteena;
mem_readdata <= ram_readdata when (io_r='0') else io_readdata_in;
process(clock_in,reset_in)
begin
if reset_in='0' then
prog_text_ena_r <= '0';
prog_text_addr_r <= (others=>'0');
prog_text_data_r <= (others=>'0');
prog_data_ena_r <= '0';
prog_data_addr_r <= (others=>'0');
prog_data_data_r <= (others=>'0');
else
if clock_in'event and clock_in='1' then
prog_text_ena_r <= prog_text_ena_in;
prog_text_addr_r <= prog_text_addr_in;
prog_text_data_r <= prog_text_data_in;
prog_data_ena_r <= prog_data_ena_in;
prog_data_addr_r <= prog_data_addr_in;
prog_data_data_r <= prog_data_data_in;
end if;
end if;
end process;
process(clock_in,mcore_reset)
begin
if mcore_reset='0' then
io_r <= '0';
else
if clock_in'event and clock_in='1' then
io_r <= io;
end if;
end if;
end process;
-------
-- Stall the processor when there is a conflict between register access and
-- registers are still updating in the pipeline
-------
process(rega_ena,stall_addr_mem,regb_ena,stall_addr_exe,reg_read_a_addr,reg_read_b_addr,stall_ena_exe,stall_ena_mem,load_exe2,exe2_busy)
begin
if (rega_ena='1' and stall_addr_exe=reg_read_a_addr and stall_ena_exe='1' ) or
(rega_ena='1' and stall_addr_mem=reg_read_a_addr and stall_ena_mem='1') or
(regb_ena='1' and stall_addr_exe=reg_read_b_addr and stall_ena_exe='1' ) or
(regb_ena='1' and stall_addr_mem=reg_read_b_addr and stall_ena_mem='1') or
(load_exe2='1' and exe2_busy='1') then
stall <= '1';
else
stall <= '0';
end if;
end process;
--------
-- Instantiate REGISTER FILE
--------
register_i:mcore_register
PORT MAP(
clock_in=>clock_in,
reset_in=>mcore_reset,
reada_addr_in=>reg_read_a_addr,
readb_addr_in=>reg_read_b_addr,
reada_data_out=>reg_read_a_data,
readb_data_out=>reg_read_b_data,
wren_in=>reg_write_ena,
write_addr_in=>reg_write_addr,
write_data_in=>reg_write_data,
hazard1_data_in=>hazard_data_exe,
hazard1_addr_in=>hazard_addr_exe,
hazard1_ena_in=>hazard_ena_exe,
hazard2_data_in=>hazard_data_mem,
hazard2_addr_in=>hazard_addr_mem,
hazard2_ena_in=>hazard_ena_mem
);
-------
--- Instantiate ROM for code memory space
-------
rom_i: mcore_rom
PORT MAP(
clock_in => clock_in,
reset_in => reset_in,
-- Output to ROM
rom_addr_in => rom_addr,
rom_data_out => rom_data,
-- Programming ROM interface
prog_ena_in => prog_text_ena_r,
prog_addr_in => prog_text_addr_r,
prog_data_in => prog_text_data_r
);
--------
--- Instantiate RAM
--------
ram_i: mcore_ram
PORT MAP(
clock_in => clock_in,
reset_in => reset_in,
address_in => ram_addr,
read_data_out => ram_readdata,
write_data_in => ram_write_data,
write_ena_in => ram_write_ena,
write_byteena_in => ram_byteena,
read_ena_in => ram_read_ena
);
-------
-- Instantiate FETCH stage
-------
fetch_i: mcore_fetch
PORT MAP(
clock_in => clock_in,
reset_in => mcore_reset,
instruction_out => instruction_fetch,
pseudo_out => instruction_pseudo,
pc_out => pc_fetch,
rega_addr_out => rega_addr_fetch,
regb_addr_out => regb_addr_fetch,
rega_ena_out => rega_ena_fetch,
regb_ena_out => regb_ena_fetch,
rom_addr_out => rom_addr,
rom_data_in => rom_data,
jump_in => jump,
jump_addr_in => jump_addr,
stall_in=>stall,
freeze_in => freeze
);
-------
-- Instantiate DECODER stage
-------
decoder_i:mcore_decoder
PORT MAP(
clock_in=>clock_in,
reset_in=>mcore_reset,
instruction_in=>instruction_fetch,
pseudo_in => instruction_pseudo,
pc_in=>pc_fetch,
rega_addr_in => rega_addr_fetch,
regb_addr_in => regb_addr_fetch,
rega_ena_in => rega_ena_fetch,
regb_ena_in => regb_ena_fetch,
x_out=>x_decoder,
y_out=>y_decoder,
z_out=>z_decoder,
shamt_out=>shamt,
z_addr_out=>z_addr_decoder,
opcode_out=>opcode_decoder,
pseudo_out=>pseudo_decoder,
mem_opcode_out=>mem_opcode_decoder,
load_out=>load_decoder,
store_out=>store_decoder,
wb_out=>wb_decoder,
jump_out=>jump,
jump_addr_out=>jump_addr,
rega_addr_out=>reg_read_a_addr,
regb_addr_out=>reg_read_b_addr,
rega_ena_out=>rega_ena,
regb_ena_out=>regb_ena,
rega_in=>reg_read_a_data,
regb_in=>reg_read_b_data,
load_exe2_out=>load_exe2,
stall_in=>stall,
freeze_in => freeze
);
------
-- Instantiate EXE state
------
exe_i:mcore_exe
PORT MAP (
clock_in=>clock_in,
reset_in=>mcore_reset,
x_in=>x_decoder,
y_in=>y_decoder,
z_in=>z_decoder,
shamt_in=>shamt,
z_addr_in=>z_addr_decoder,
opcode_in=>opcode_decoder,
pseudo_in=>pseudo_decoder,
mem_opcode_in=>mem_opcode_decoder,
load_in=>load_decoder,
store_in=>store_decoder,
wb_in=>wb_decoder,
result_out=>result_exe,
z_out=>z_exe,
z_addr_out=>z_addr_exe,
mem_opcode_out=>mem_opcode_exe,
load_out=>load_exe,
store_out=>store_exe,
wb_out=>wb_exe,
hazard_data_out=>hazard_data_exe,
hazard_addr_out=>hazard_addr_exe,
hazard_ena_out=>hazard_ena_exe,
stall_addr_out=>stall_addr_exe,
stall_ena_out=>stall_ena_exe,
exe2_opcode_out=>exe2_opcode,
exe2_req_out=>exe2_req_exe,
exe2_x_out=>exe2_x,
exe2_y_out=>exe2_y,
LO_in => LO,
HI_in => HI,
freeze_in => freeze
);
-----------
-- Instantiate EXE
-- This stage performs long operation such as divide/multiply
-----------
exe2_i:mcore_exe2
PORT MAP(
clock_in=>clock_in,
reset_in=>mcore_reset,
opcode_in=>exe2_opcode,
req_in=>exe2_req_exe,
x_in=>exe2_x,
y_in=>exe2_y,
LO_out=>LO,
HI_out=>HI,
busy_out=>exe2_busy
);
--------
-- Instantiate MEM stage
--------
mem_i:mcore_mem
PORT MAP(
clock_in=>clock_in,
reset_in=>mcore_reset,
result_in=>result_exe,
z_in=>z_exe,
z_addr_in=>z_addr_exe,
mem_opcode_in=>mem_opcode_exe,
load_in=>load_exe,
store_in=>store_exe,
wb_in=>wb_exe,
mem_wren_out=>mem_write_ena,
mem_rden_out=>mem_read_ena,
mem_addr_out=>mem_addr,
mem_readdata_in=>mem_readdata,
mem_writedata_out=>mem_write_data,
mem_byteena_out=>mem_byteena,
wb_addr_out=>wb_addr_mem,
wb_data_out=>wb_data_mem,
wb_ena_out=>wb_ena_mem,
hazard_data_out=>hazard_data_mem,
hazard_addr_out=>hazard_addr_mem,
hazard_ena_out=>hazard_ena_mem,
stall_addr_out=>stall_addr_mem,
stall_ena_out=>stall_ena_mem,
freeze_in => freeze
);
---------
-- Instantiate Write-back stage
---------
wb_i:mcore_wb
PORT MAP(
clock_in=>clock_in,
reset_in=>mcore_reset,
wb_addr_in=>wb_addr_mem,
wb_data_in=>wb_data_mem,
wb_ena_in=>wb_ena_mem,
reg_wren_out=>reg_write_ena,
reg_write_addr_out=>reg_write_addr,
reg_write_data_out=>reg_write_data
);
END behaviour;
|
ARCHITECTURE test OF chronometer_tester IS
constant clockPeriod: time := 1.0/clockFrequency * 1 sec;
signal sClock: std_uLogic := '1';
constant testModePulseWidth: time := 10 us;
constant pulseWidth: time := 20 ms;
BEGIN
------------------------------------------------------------------------------
-- clock and reset
reset <= '1', '0' after 4*clockPeriod;
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after 9.0/10.0 * clockPeriod;
------------------------------------------------------------------------------
-- test sequence
process
begin
----------------------------------------------------------------------------
-- test mode
testMode <= '1';
restart <= '0';
sensor <= '0';
start <= '0';
stop <= '0';
button4 <= '0';
wait for 10 us;
restart <= '1', '0' after testModePulseWidth;
wait for 40 us;
sensor <= '1', '0' after testModePulseWidth;
wait for 50 us;
start <= '1', '0' after testModePulseWidth;
wait for 200 us;
button4 <= '1';
wait for 100 us;
stop <= '1', '0' after testModePulseWidth;
wait for 2*testModePulseWidth;
----------------------------------------------------------------------------
-- real speed
testMode <= '0';
wait for 1 ms - now;
restart <= '1', '0' after pulseWidth;
wait for 70 ms - now;
sensor <= '1', '0' after pulseWidth;
wait for 100 ms - now;
start <= '1', '0' after pulseWidth;
wait;
end process;
END ARCHITECTURE test;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Chen_Kevin_ALU_Control is
port(
Chen_Kevin_ALU_Op : in std_logic_vector(1 downto 0);
Chen_Kevin_Function : in std_logic_vector(5 downto 0);
Chen_Kevin_op: out std_logic_vector(3 downto 0)
);
end Chen_Kevin_ALU_Control;
architecture arch of Chen_Kevin_ALU_Control is
begin
process(Chen_Kevin_ALU_Op,Chen_Kevin_Function)
begin
case Chen_Kevin_ALU_Op is
when "00" => -- lw and sw
Chen_Kevin_op <= "0010"; -- Add
when "01" => -- beq
Chen_Kevin_op <= "0011"; -- Subtract
when "10" => -- R-Type
if (Chen_Kevin_Function = "000000") then -- AND
Chen_Kevin_op <= "0000";
elsif (Chen_Kevin_Function = "000001") then -- OR
Chen_Kevin_op <= "0001";
elsif (Chen_Kevin_Function = "000010") then -- +
Chen_Kevin_op <= "0010";
elsif (Chen_Kevin_Function = "000011") then -- -
Chen_Kevin_op <= "0011";
elsif (Chen_Kevin_Function = "000100") then -- *
Chen_Kevin_op <= "0100";
elsif (Chen_Kevin_Function = "000101") then -- /
Chen_Kevin_op <= "0101";
elsif (Chen_Kevin_Function = "000110") then
Chen_Kevin_op <= "0110";
elsif (Chen_Kevin_Function = "000111") then
Chen_Kevin_op <= "0111";
elsif (Chen_Kevin_Function = "001000") then
Chen_Kevin_op <= "1000";
elsif (Chen_Kevin_Function = "001001") then
Chen_Kevin_op <= "1001";
elsif (Chen_Kevin_Function = "001010") then
Chen_Kevin_op <= "1010";
elsif (Chen_Kevin_Function = "001011") then
Chen_Kevin_op <= "1011";
elsif (Chen_Kevin_Function = "001100") then
Chen_Kevin_op <= "1100";
elsif (Chen_Kevin_Function = "001101") then
Chen_Kevin_op <= "1101";
elsif (Chen_Kevin_Function = "001111") then
Chen_Kevin_op <= "1111";
else
Chen_Kevin_op <= Null;
end if;
when others =>
Null;
end case;
end process;
end arch;
|
<gh_stars>0
library IEEE;
use IEEE.Std_Logic_1164.all;
entity myAnd2_tb is
end myAnd2_tb;
architecture behavioral of myAnd2_tb is
component myAnd2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
-- signals used for testing
signal s1: std_logic;
signal s2: std_logic;
signal o1: std_logic;
begin
-- component instantiation
myAnd2_1: myAnd2 port map(a => s1, b => s2, s => o1);
process
begin
s1 <= '0';
s2 <= '0';
wait for 1 ns;
assert o1 = '0' report "and('0', '0') was not '0'" severity error;
s1 <= '0';
s2 <= '1';
wait for 1 ns;
assert o1 = '0' report "and('0', '1') was not '0'" severity error;
s1 <= '1';
s2 <= '0';
wait for 1 ns;
assert o1 = '0' report "and('1', '0') was not '0'" severity error;
s1 <= '1';
s2 <= '1';
wait for 1 ns;
assert o1 = '1' report "and('1', '1') was not '1'" severity error;
assert false report "test complete" severity note;
wait;
end process;
end behavioral;
|
<filename>microprocessor/imports/sim_1/new/function_unit.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity function_unit is
Port (A,B:in std_logic_vector(31 downto 0);
FS:in std_logic_vector(6 downto 2);
C:out std_logic;
V:out std_logic;
N:out std_logic;
Z:out std_logic;
F:out std_logic_vector(31 downto 0)
);
end function_unit;
architecture Behavioral of function_unit is
COMPONENT ALU
Port(
A, B: in std_logic_vector(31 downto 0);
s0, s1: in std_logic;
c_in:in std_logic;
s2: in std_logic;
c_out:out std_logic;
V:out std_logic;
N:out std_logic;
Z:out std_logic;
G: out std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT shifter
Port (B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,
B12,B13,B14,B15,B16,B17,B18,
B19,B20,B21,B22,B23,B24,B25,B26,
B27,B28,B29,B30,B31:in std_logic;
S0,S1:std_logic;
l0:in std_logic;
l31:in std_logic;
H0,H1,H2,H3,H4,H5,H6,H7,H8,H9,H10,H11,
H12,H13,H14,H15,H16,H17,H18,H19,H20,H21,
H22,H23,H24,H25,H26,H27,H28,H29,H30,H31:out std_logic );
END COMPONENT;
COMPONENT mux2_32bit
port ( In0 : in std_logic_vector(31 downto 0);
In1 : in std_logic_vector(31 downto 0);
s : in std_logic;
Z : out std_logic_vector(31 downto 0));
END COMPONENT;
signal load_In0,load_In1:std_logic_vector(31 downto 0):= (others => '0');
begin
ALU1:ALU PORT MAP(
A=>A,
B=>B,
c_in=>FS(2),
S0=>FS(3),
S1=>FS(4),
S2=>FS(5),
V=>V,
N=>N,
Z=>Z,
c_out=>C,
G=>load_In0
);
shifter1:shifter PORT MAP(
B0=>B(0),
B1=>B(1),
B2=>B(2),
B3=>B(3),
B4=>B(4),
B5=>B(5),
B6=>B(6),
B7=>B(7),
B8=>B(8),
B9=>B(9),
B10=>B(10),
B11=>B(11),
B12=>B(12),
B13=>B(13),
B14=>B(14),
B15=>B(15),
B16=>B(16),
B17=>B(17),
B18=>B(18),
B19=>B(19),
B20=>B(20),
B21=>B(21),
B22=>B(22),
B23=>B(23),
B24=>B(24),
B25=>B(25),
B26=>B(26),
B27=>B(27),
B28=>B(28),
B29=>B(29),
B30=>B(30),
B31=>B(31),
s0=>FS(3),
S1=>FS(4),
l0=>'0',
l31=>'0',
H0=>load_In1(0),
H1=>load_In1(1),
H2=>load_In1(2),
H3=>load_In1(3),
H4=>load_In1(4),
H5=>load_In1(5),
H6=>load_In1(6),
H7=>load_In1(7),
H8=>load_In1(8),
H9=>load_In1(9),
H10=>load_In1(10),
H11=>load_In1(11),
H12=>load_In1(12),
H13=>load_In1(13),
H14=>load_In1(14),
H15=>load_In1(15),
H16=>load_In1(16),
H17=>load_In1(17),
H18=>load_In1(18),
H19=>load_In1(19),
H20=>load_In1(20),
H21=>load_In1(21),
H22=>load_In1(22),
H23=>load_In1(23),
H24=>load_In1(24),
H25=>load_In1(25),
H26=>load_In1(26),
H27=>load_In1(27),
H28=>load_In1(28),
H29=>load_In1(29),
H30=>load_In1(30),
H31=>load_In1(31)
);
mux:mux2_32bit PORT MAP(
In0=>load_In0,
In1=>load_In1,
S=>FS(6),
Z=>F
);
end Behavioral;
|
<reponame>mgsgo/M-CIS-S6-FX3CON
----------------------------------------------------------------------------------
-- Engineer: <NAME> <<EMAIL><
--
-- Module Name: dvid_serdes - Behavioral
-- Description: Generating a DVI-D 720p signal using the OSERDES2 serialisers
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity dvid_serdes is
Port ( clk50 : in STD_LOGIC;
tmds_out_p : out STD_LOGIC_VECTOR(3 downto 0);
tmds_out_n : out STD_LOGIC_VECTOR(3 downto 0));
end dvid_serdes;
architecture Behavioral of dvid_serdes is
signal pixel_clock : std_logic;
signal data_load_clock : std_logic;
signal ioclock : std_logic;
signal serdes_strobe : std_logic;
signal red : std_logic_vector(7 downto 0);
signal green : std_logic_vector(7 downto 0);
signal blue : std_logic_vector(7 downto 0);
signal blank : std_logic;
signal hsync : std_logic;
signal vsync : std_logic;
signal tmds_out_red : std_logic;
signal tmds_out_green : std_logic;
signal tmds_out_blue : std_logic;
signal tmds_out_clock : std_logic;
COMPONENT vga_gen
PORT(
clk75 : IN std_logic;
red : OUT std_logic_vector(7 downto 0);
green : OUT std_logic_vector(7 downto 0);
blue : OUT std_logic_vector(7 downto 0);
blank : OUT std_logic;
hsync : OUT std_logic;
vsync : OUT std_logic
);
END COMPONENT;
COMPONENT clocking
PORT(
clk50m : IN std_logic;
pixel_clock : OUT std_logic;
data_load_clock : OUT std_logic;
ioclock : OUT std_logic;
serdes_strobe : OUT std_logic
);
END COMPONENT;
COMPONENT dvid_out
PORT(
pixel_clock : IN std_logic;
data_load_clock : IN std_logic;
ioclock : IN std_logic;
serdes_strobe : IN std_logic;
red_p : IN std_logic_vector(7 downto 0);
green_p : IN std_logic_vector(7 downto 0);
blue_p : IN std_logic_vector(7 downto 0);
blank : IN std_logic;
hsync : IN std_logic;
vsync : IN std_logic;
red_s : OUT std_logic;
green_s : OUT std_logic;
blue_s : OUT std_logic;
clock_s : OUT std_logic
);
END COMPONENT;
begin
Inst_clocking: clocking PORT MAP(
clk50m => clk50,
pixel_clock => pixel_clock,
data_load_clock => data_load_clock,
ioclock => ioclock,
serdes_strobe => serdes_strobe
);
i_vga_gen: vga_gen PORT MAP(
clk75 => pixel_clock,
red => green,
green => red,
blue => blue,
blank => blank,
hsync => hsync,
vsync => vsync
);
i_dvid_out: dvid_out PORT MAP(
pixel_clock => pixel_clock,
data_load_clock => data_load_clock,
ioclock => ioclock,
serdes_strobe => serdes_strobe,
red_p => red,
green_p => green,
blue_p => blue,
blank => blank,
hsync => hsync,
vsync => vsync,
red_s => tmds_out_red,
green_s => tmds_out_green,
blue_s => tmds_out_blue,
clock_s => tmds_out_clock
);
OBUFDS_blue : OBUFDS port map ( O => tmds_out_p(0), OB => tmds_out_n(0), I => tmds_out_blue);
OBUFDS_red : OBUFDS port map ( O => tmds_out_p(1), OB => tmds_out_n(1), I => tmds_out_green);
OBUFDS_green : OBUFDS port map ( O => tmds_out_p(2), OB => tmds_out_n(2), I => tmds_out_red);
OBUFDS_clock : OBUFDS port map ( O => tmds_out_p(3), OB => tmds_out_n(3), I => tmds_out_clock);
end Behavioral;
|
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity outputctrl is
port (
adr:in std_logic_vector(31 downto 0) ;
wi:in std_logic;
we :out std_logic
) ;
end outputctrl ;
architecture arch of outputctrl is
begin
we<='1'when((wi='1') and (adr >= x"FFFF0000"))
else '0';
end architecture ;
|
-- 07.08.20 ----------- <NAME> ----------- DivisorFrec_tb.vhdl
-- TESTBENCH DEL DIVISOR DE FRECUENCIA.
library ieee;
use ieee.std_logic_1164.all;
---------------------------------------------------------------------
entity DivisorFrec_tb is
end entity DivisorFrec_tb;
---------------------------------------------------------------------
architecture Test of DivisorFrec_tb is
------------------------------------------------------
component DivisorFrec is
port (clk_i : in std_logic;
clr_i : in std_logic;
clk_o : out std_logic);
end component DivisorFrec;
------------------------------------------------------
signal clk_t : std_logic :='1';
signal clr_t : std_logic :='1';
signal clko_t : std_logic;
constant FRECUENCIA : integer := 24; -- en MHz
constant PERIODO : time := 1 us/FRECUENCIA; -- 41,66 ns
signal detener : boolean := false;
begin
dut: DivisorFrec port map(clk_i => clk_t,
clr_i => clr_t,
clK_o => clko_t);
-------------------------------------
GeneraReloj:
process begin
clk_t <= '1', '0' after PERIODO/2;
wait for PERIODO;
if detener then
wait;
end if;
end process GeneraReloj;
-------------------------------------
clr_t <= '1' , '0' after PERIODO*3/2;
Prueba:
process begin
report "Verificando el Divisor de frecuencia de 24MHz a 1MHz"
severity note;
wait until clr_t='0';
wait for 3 ns;
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
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wait until rising_edge(clk_t);
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wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
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wait until rising_edge(clk_t);
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wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
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wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
wait until rising_edge(clk_t);
detener <= true;
wait;
end process;
end architecture Test;
---------------------------------------------------------------------
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.Glob_dcls.all;
entity RegFile is
port(
clk, wr_en : in STD_LOGIC;
rd_addr_1, rd_addr_2, wr_addr : in REG_addr;
d_in : in word;
d_out_1, d_out_2 : out word
);
end RegFile;
architecture RF_arch of RegFile is
-- component declaration
-- signal declaration
-- Reg_addr is 32 bits so 32 registers
subtype RegF_Addr is integer range 0 to 31;
type RegF is array (RegF_Addr) of word;
-- conversion from REG_addr to integer
-- std_logic_vector -> unsigned -> integer
signal R : RegF;
signal zaddr : REG_ADDR := (others => '0');
begin
process (clk)
begin
-- register 0 reserved for value 0
-- for some reason, $0 will not be assigned outside of process statements
R(0) <= zero_word;
-- write synchronously
if (clk'event and clk = '1' and wr_en = '1' and not (unsigned(wr_addr) = 0)) then
-- convert wr_addr to integer for indexing
R(to_integer(unsigned(wr_addr))) <= d_in;
end if;
end process;
-- read asynchronously
-- convert rd_addr to integer
d_out_1 <= R(to_integer(unsigned(rd_addr_1)));
d_out_2 <= R(to_integer(unsigned(rd_addr_2)));
end RF_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library work;
-- use work.nco_p.all;
library nuand;
-- use nuand.util.all;
use nuand.constellation_mapper_p.all;
entity atsc_tx is
generic(
INPUT_WIDTH : positive := 32;
OUTPUT_WIDTH : positive:= 16;
SYMBOL_DOWNLOAD_WIDTH : positive := 4;
SPS : natural := 3;
CPS : natural := 2
);
port(
clock : in std_logic;
reset : in std_logic;
--
tx_enable : in std_logic;
data_in : in std_logic_vector(INPUT_WIDTH-1 downto 0);
data_in_request : out std_logic;
data_in_valid : in std_logic;
sample_out_i : out signed(OUTPUT_WIDTH-1 downto 0);
sample_out_q : out signed(OUTPUT_WIDTH-1 downto 0);
sample_out_valid : out std_logic
);
end entity;
architecture arch of atsc_tx is
--bit stripper signals
signal strip_enable : std_logic;
signal symbol_bits : std_logic_vector(SYMBOL_DOWNLOAD_WIDTH-1 downto 0);
signal symbol_bits_request : std_logic;
signal symbol_bits_valid : std_logic;
--constellation mapper
signal map_inputs : constellation_mapper_inputs_t;
signal map_outputs : constellation_mapper_outputs_t;
--new mixed signal
signal symbol_mixed : complex_fixed_t;
signal symbol_mixed_valid : std_logic;
--new upsampled signal
signal symbol_mixed_up : complex_fixed_t;
signal symbol_mixed_up_valid : std_logic;
--filtered signal
signal filtered_sample : complex_fixed_t;
signal filtered_sample_valid : std_logic;
--filtered signal
signal tx_symbol : complex_fixed_t;
signal tx_symbol_valid : std_logic;
--filtered signal
signal registered_symbol : complex_fixed_t;
signal registered_symbol_valid : std_logic;
--pilot
signal tx_pilot : complex_fixed_t;
-- todo:create tone dynamically
function create_tone( fs, ftone : real) return complex_fixed_t is
variable rv : complex_fixed_t := (to_signed(0,16),to_signed(0,16));
begin
return rv;
end function;
constant atsc_lo_table : complex_fixed_array_t := ( (to_signed( integer(4096.0*1.5/7.0),16), to_signed( integer(1.5/7.0 * 0.0),16)),
(to_signed( integer(1.5/7.0 * 3547.0),16), to_signed( integer(1.5/7.0 * (-2048.0)),16)),
(to_signed( integer(1.5/7.0 * 2048.0),16), to_signed( integer(1.5/7.0 * (-3547.0)),16)),
(to_signed( integer(1.5/7.0 * 0.0),16), to_signed( integer(1.5/7.0 * (-4096.0)),16)),
(to_signed( integer(1.5/7.0 * (-2048.0)),16), to_signed( integer(1.5/7.0 * (-3547.0)),16)),
(to_signed( integer(1.5/7.0 * (-3547.0)),16), to_signed( integer(1.5/7.0 * (-2048.0)),16)),
(to_signed( integer(1.5/7.0 * (-4096.0)),16), to_signed( integer(1.5/7.0 * 0.0),16)),
(to_signed( integer(1.5/7.0 * (-3547.0)),16), to_signed( integer(1.5/7.0 * 2048.0),16)),
(to_signed( integer(1.5/7.0 * (-2048.0)),16), to_signed( integer(1.5/7.0 * 3547.0),16)),
(to_signed( integer(1.5/7.0 * 0.0),16), to_signed( integer(1.5/7.0 * 4096.0),16)),
(to_signed( integer(1.5/7.0 * 2048.0),16), to_signed( integer(1.5/7.0 * 3547.0),16)),
(to_signed( integer(1.5/7.0 * 3547.0),16), to_signed( integer(1.5/7.0 * 2048.0),16) ));
function cmult( a, b : complex_fixed_t; q : natural ) return complex_fixed_t is
variable rv : complex_fixed_t := (to_signed(0,16),to_signed(0,16));
begin
rv.re := resize(shift_right(a.re * b.re,q) - shift_right(a.im * b.im, q),rv.re'length);
rv.re := resize(shift_right(a.re * b.re,q) + shift_right(a.im * b.re, q),rv.im'length);
return rv;
end function;
function cmult_fs4(a : complex_fixed_t; fs_4 : natural) return complex_fixed_t is
begin
case fs_4 is
when 0 => return (a.re,a.im);
when 1 => return (a.im,-a.re);
when 2 => return (-a.re,-a.im);
when 3 => return (-a.im, a.re);
when others => return a;
end case;
end function;
constant ATSC_FIR : real_array_t := (
0.000952541947487,
0.001021339440824,
0.000713161320156,
0.000099293834852,
-0.000631484665308,
-0.001227676654677,
-0.001457043942307,
-0.001190147219421,
-0.000456941151589,
0.000545581017437,
0.001502219876242,
0.002074087248050,
0.002011614083297,
0.001249974660528,
-0.000046895490230,
-0.001513860357388,
-0.002682283457258,
-0.003123186912762,
-0.002593740652748,
-0.001139501073282,
0.000885746160816,
0.002897996639881,
0.004244432533851,
0.004405493902086,
0.003177417184785,
0.000774939833928,
-0.002187174361577,
-0.004841259681936,
-0.006310376881971,
-0.005982741937804,
-0.003734744853560,
-0.000027621448548,
0.004166072719588,
0.007602382204908,
0.009117175655313,
0.007993866438765,
0.004237744374945,
-0.001336553068967,
-0.007251920699642,
-0.011732810079681,
-0.013203082387958,
-0.010786054755306,
-0.004660238809862,
0.003849830264059,
0.012505380718689,
0.018680222433748,
0.020069392108675,
0.015404316532634,
0.004979659322029,
-0.009171254616962,
-0.023537317903158,
-0.033804674326444,
-0.035814465077870,
-0.026588972738348,
-0.005178629408275,
0.026889883444145,
0.065699566102954,
0.105575674164579,
0.140146665827966,
0.163608592331722,
0.171912865925582,
0.163608592331722,
0.140146665827966,
0.105575674164579,
0.065699566102954,
0.026889883444145,
-0.005178629408275,
-0.026588972738348,
-0.035814465077870,
-0.033804674326444,
-0.023537317903158,
-0.009171254616962,
0.004979659322029,
0.015404316532634,
0.020069392108675,
0.018680222433748,
0.012505380718689,
0.003849830264059,
-0.004660238809862,
-0.010786054755306,
-0.013203082387958,
-0.011732810079681,
-0.007251920699642,
-0.001336553068967,
0.004237744374945,
0.007993866438765,
0.009117175655313,
0.007602382204908,
0.004166072719588,
-0.000027621448548,
-0.003734744853560,
-0.005982741937804,
-0.006310376881971,
-0.004841259681936,
-0.002187174361577,
0.000774939833928,
0.003177417184785,
0.004405493902086,
0.004244432533851,
0.002897996639881,
0.000885746160816,
-0.001139501073282,
-0.002593740652748,
-0.003123186912762,
-0.002682283457258,
-0.001513860357388,
-0.000046895490230,
0.001249974660528,
0.002011614083297,
0.002074087248050,
0.001502219876242,
0.000545581017437,
-0.000456941151589,
-0.001190147219421,
-0.001457043942307,
-0.001227676654677,
-0.000631484665308,
0.000099293834852,
0.000713161320156,
0.001021339440824,
0.000952541947487);
begin
--map outputs
sample_out_i <= registered_symbol.re;
sample_out_q <= registered_symbol.im;
sample_out_valid <= registered_symbol_valid;
strip_enable <= tx_enable;
U_stripper : entity work.bit_stripper(arch)
generic map(
INPUT_WIDTH => 32,
OUTPUT_WIDTH => 4
)
port map(
clock => clock,
reset => reset,
enable => strip_enable,
in_data => data_in,
in_data_request => data_in_request,
in_data_valid => data_in_valid,
out_data => symbol_bits,
out_data_request => symbol_bits_request,
out_data_valid => symbol_bits_valid
);
--strip symbols
pull_symbols : process(clock,reset)
constant DOWNCOUNT_RESET : natural range 0 to 5 := 2;
variable downcount : natural range 0 to 5 := DOWNCOUNT_RESET;
begin
--
if (reset = '1') then
symbol_bits_request <= '0';
downcount := DOWNCOUNT_RESET;
elsif rising_edge(clock) then
if strip_enable = '1' then
symbol_bits_request <= '0';
if(downcount = 0) then
symbol_bits_request <= '1';
downcount := 5;
else
downcount := downcount - 1 ;
end if;
end if;
end if;
end process;
map_inputs.bits(map_inputs.bits'length -1 downto 3) <= (others => '0');
map_inputs.bits(2 downto 0) <= symbol_bits(2 downto 0);
map_inputs.modulation <= VSB_8;
map_inputs.valid <= symbol_bits_valid;
--map bits to constellation point
U_mapper : entity work.constellation_mapper(arch)
generic map(
MODULATIONS => (VSB_8, MSK)
)
port map(
clock => clock,
inputs => map_inputs,
outputs => map_outputs
);
--apply fs/4 multiply to center
generate_nco_phase : process(clock,reset)
subtype phases_t is natural range 0 to 3;
variable dphase : phases_t;
begin
if (reset = '1') then
dphase := 0;
symbol_mixed_valid <= '0';
symbol_mixed <= ((others=> '0'), (others => '0'));
elsif (rising_edge(clock)) then
symbol_mixed_valid <= '0';
if map_outputs.valid = '1' then
symbol_mixed <= cmult_fs4(map_outputs.symbol, dphase);
symbol_mixed_valid <= '1';
if dphase = phases_t'high then
dphase := 0;
else
dphase := dphase + 1;
end if;
end if;
end if;
end process;
--zero stuff to interpolate since this isn't available in the fir yet
upsample : process(clock,reset)
variable downcount : natural range 0 to 2;
variable cps_downcount : natural range 0 to 2;
begin
if (reset = '1') then
downcount := 0;
symbol_mixed_up_valid <= '0';
elsif rising_edge(clock) then
symbol_mixed_up_valid <= '0';
if symbol_mixed_valid = '1' then
symbol_mixed_up <= symbol_mixed;
downcount := SPS-1;
cps_downcount := CPS-1;
symbol_mixed_up_valid <= '1';
elsif downcount > 0 then
symbol_mixed_up <= ((others => '0'), (others => '0'));
if cps_downcount = 0 then
symbol_mixed_up_valid <= '1';
downcount := downcount -1;
cps_downcount := CPS-1;
else
cps_downcount := cps_downcount -1;
end if;
end if;
end if;
end process;
--filter to bandwidth
U_filter_re : entity work.fir_filter(systolic)
generic map (
CPS => 1,
H => ATSC_FIR
)
port map(
clock => clock,
reset => reset,
in_sample => symbol_mixed_up.re,
in_valid => symbol_mixed_up_valid,
out_sample => filtered_sample.re,
out_valid => filtered_sample_valid
);
U_filter_im : entity work.fir_filter(systolic)
generic map (
CPS => 1,
H => ATSC_FIR
)
port map(
clock => clock,
reset => reset,
in_sample => symbol_mixed_up.im,
in_valid => symbol_mixed_up_valid,
out_sample => filtered_sample.im,
out_valid => open
);
add_pilot : process(clock,reset)
variable pilot : natural range atsc_lo_table'range;
begin
if(reset = '1') then
tx_symbol <= ((others=>'0'),(others=>'0'));
tx_pilot <= ((others=>'0'),(others=>'0'));
tx_symbol_valid <= '0';
pilot := 0;
elsif rising_edge(clock) then
tx_symbol_valid <= '0';
if filtered_sample_valid = '1' then
tx_symbol.re <= filtered_sample.re + shift_right(atsc_lo_table(pilot).re,2);
tx_symbol.im <= filtered_sample.im + shift_right(atsc_lo_table(pilot).im,2);
tx_pilot.re <= shift_right(atsc_lo_table(pilot).re,1);
tx_pilot.im <= shift_right(atsc_lo_table(pilot).im,1);
tx_symbol_valid <= '1';
if pilot = atsc_lo_table'high then
pilot := 0;
else
pilot := pilot +1;
end if;
end if;
end if;
end process;
register_output : process(clock,reset)
begin
if (reset = '1' ) then
registered_symbol <= ((others=> '0'),(others=>'0'));
registered_symbol_valid <= '0';
elsif rising_edge(clock) then
registered_symbol.re <= shift_right(tx_symbol.re,2);
registered_symbol.im <= shift_right(tx_symbol.im,2);
registered_symbol_valid <= tx_symbol_valid;
end if;
end process;
end architecture;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dct is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
input_r_address0 : OUT STD_LOGIC_VECTOR (5 downto 0);
input_r_ce0 : OUT STD_LOGIC;
input_r_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
output_r_address0 : OUT STD_LOGIC_VECTOR (5 downto 0);
output_r_ce0 : OUT STD_LOGIC;
output_r_we0 : OUT STD_LOGIC;
output_r_d0 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of dct is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"dct,hls_ip_2017_1,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=8.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.601438,HLS_SYN_LAT=1855,HLS_SYN_TPT=none,HLS_SYN_MEM=5,HLS_SYN_DSP=1,HLS_SYN_FF=298,HLS_SYN_LUT=1174}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_fsm_pp1_stage0 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv7_40 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_const_lv4_1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_const_lv4_8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal indvar_flatten_reg_120 : STD_LOGIC_VECTOR (6 downto 0);
signal r_i_reg_131 : STD_LOGIC_VECTOR (3 downto 0);
signal c_i_reg_142 : STD_LOGIC_VECTOR (3 downto 0);
signal indvar_flatten2_reg_153 : STD_LOGIC_VECTOR (6 downto 0);
signal r_i2_reg_164 : STD_LOGIC_VECTOR (3 downto 0);
signal c_i6_reg_175 : STD_LOGIC_VECTOR (3 downto 0);
signal exitcond_flatten_fu_194_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_reg_383 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state3_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal ap_reg_pp0_iter1_exitcond_flatten_reg_383 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_next_fu_200_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal c_i_mid2_fu_218_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal c_i_mid2_reg_392 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_reg_pp0_iter1_c_i_mid2_reg_392 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_i_mid2_v_v_fu_226_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_i_mid2_v_v_reg_399 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_reg_pp0_iter1_tmp_i_mid2_v_v_reg_399 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_fu_234_p1 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_reg_405 : STD_LOGIC_VECTOR (2 downto 0);
signal c_fu_259_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal exitcond_flatten2_fu_289_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten2_reg_420 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp1_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp1_stage0 : signal is "none";
signal ap_block_state7_pp1_stage0_iter0 : BOOLEAN;
signal ap_block_state8_pp1_stage0_iter1 : BOOLEAN;
signal ap_block_state9_pp1_stage0_iter2 : BOOLEAN;
signal ap_block_pp1_stage0_flag00011001 : BOOLEAN;
signal ap_reg_pp1_iter1_exitcond_flatten2_reg_420 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_next2_fu_295_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_enable_reg_pp1_iter0 : STD_LOGIC := '0';
signal c_i6_mid2_fu_313_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal c_i6_mid2_reg_429 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_i4_mid2_v_fu_321_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_i4_mid2_v_reg_436 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_3_fu_329_p1 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_3_reg_442 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_4_i_fu_368_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_4_i_reg_452 : STD_LOGIC_VECTOR (5 downto 0);
signal c_1_fu_374_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_enable_reg_pp1_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal grp_dct_2d_fu_186_ap_done : STD_LOGIC;
signal ap_block_pp1_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp1_exit_iter0_state7 : STD_LOGIC;
signal ap_enable_reg_pp1_iter2 : STD_LOGIC := '0';
signal buf_2d_in_address0 : STD_LOGIC_VECTOR (5 downto 0);
signal buf_2d_in_ce0 : STD_LOGIC;
signal buf_2d_in_we0 : STD_LOGIC;
signal buf_2d_in_q0 : STD_LOGIC_VECTOR (15 downto 0);
signal buf_2d_out_address0 : STD_LOGIC_VECTOR (5 downto 0);
signal buf_2d_out_ce0 : STD_LOGIC;
signal buf_2d_out_we0 : STD_LOGIC;
signal buf_2d_out_q0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_dct_2d_fu_186_ap_start : STD_LOGIC;
signal grp_dct_2d_fu_186_ap_idle : STD_LOGIC;
signal grp_dct_2d_fu_186_ap_ready : STD_LOGIC;
signal grp_dct_2d_fu_186_in_block_address0 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_dct_2d_fu_186_in_block_ce0 : STD_LOGIC;
signal grp_dct_2d_fu_186_out_block_address0 : STD_LOGIC_VECTOR (5 downto 0);
signal grp_dct_2d_fu_186_out_block_ce0 : STD_LOGIC;
signal grp_dct_2d_fu_186_out_block_we0 : STD_LOGIC;
signal grp_dct_2d_fu_186_out_block_d0 : STD_LOGIC_VECTOR (15 downto 0);
signal r_i_phi_fu_135_p4 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal c_i_phi_fu_146_p4 : STD_LOGIC_VECTOR (3 downto 0);
signal r_i2_phi_fu_168_p4 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_block_pp1_stage0_flag00000000 : BOOLEAN;
signal c_i6_phi_fu_179_p4 : STD_LOGIC_VECTOR (3 downto 0);
signal ap_reg_grp_dct_2d_fu_186_ap_start : STD_LOGIC := '0';
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal tmp_i_fu_254_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_31_cast_fu_284_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_35_cast_fu_363_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_5_i_fu_379_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal exitcond_i_fu_212_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal r_fu_206_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal c_i_cast6_fu_245_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_i_mid2_fu_238_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_9_i_fu_248_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_s_fu_264_p3 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_30_cast_fu_271_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_1_i_cast_fu_275_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_22_fu_278_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal exitcond_i1_fu_307_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal r_1_fu_301_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_23_fu_333_p3 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_33_cast_fu_340_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_3_i_cast_fu_354_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_24_fu_357_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal c_i6_cast2_fu_351_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_1_i5_mid2_fu_344_p3 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
signal ap_idle_pp1 : STD_LOGIC;
signal ap_enable_pp1 : STD_LOGIC;
component dct_2d IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
in_block_address0 : OUT STD_LOGIC_VECTOR (5 downto 0);
in_block_ce0 : OUT STD_LOGIC;
in_block_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
out_block_address0 : OUT STD_LOGIC_VECTOR (5 downto 0);
out_block_ce0 : OUT STD_LOGIC;
out_block_we0 : OUT STD_LOGIC;
out_block_d0 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component dct_2d_row_outbuf IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (5 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (15 downto 0);
q0 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
buf_2d_in_U : component dct_2d_row_outbuf
generic map (
DataWidth => 16,
AddressRange => 64,
AddressWidth => 6)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => buf_2d_in_address0,
ce0 => buf_2d_in_ce0,
we0 => buf_2d_in_we0,
d0 => input_r_q0,
q0 => buf_2d_in_q0);
buf_2d_out_U : component dct_2d_row_outbuf
generic map (
DataWidth => 16,
AddressRange => 64,
AddressWidth => 6)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => buf_2d_out_address0,
ce0 => buf_2d_out_ce0,
we0 => buf_2d_out_we0,
d0 => grp_dct_2d_fu_186_out_block_d0,
q0 => buf_2d_out_q0);
grp_dct_2d_fu_186 : component dct_2d
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_dct_2d_fu_186_ap_start,
ap_done => grp_dct_2d_fu_186_ap_done,
ap_idle => grp_dct_2d_fu_186_ap_idle,
ap_ready => grp_dct_2d_fu_186_ap_ready,
in_block_address0 => grp_dct_2d_fu_186_in_block_address0,
in_block_ce0 => grp_dct_2d_fu_186_in_block_ce0,
in_block_q0 => buf_2d_in_q0,
out_block_address0 => grp_dct_2d_fu_186_out_block_address0,
out_block_ce0 => grp_dct_2d_fu_186_out_block_ce0,
out_block_we0 => grp_dct_2d_fu_186_out_block_we0,
out_block_d0 => grp_dct_2d_fu_186_out_block_d0);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2)) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp1_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp1_exit_iter0_state7))) then
ap_enable_reg_pp1_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (grp_dct_2d_fu_186_ap_done = ap_const_logic_1))) then
ap_enable_reg_pp1_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp1_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp1_iter1 <= ap_const_logic_0;
else
if ((ap_block_pp1_stage0_flag00011011 = ap_const_boolean_0)) then
if ((ap_const_logic_1 = ap_condition_pp1_exit_iter0_state7)) then
ap_enable_reg_pp1_iter1 <= (ap_condition_pp1_exit_iter0_state7 xor ap_const_logic_1);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp1_iter1 <= ap_enable_reg_pp1_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp1_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp1_iter2 <= ap_const_logic_0;
else
if ((ap_block_pp1_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp1_iter2 <= ap_enable_reg_pp1_iter1;
elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (grp_dct_2d_fu_186_ap_done = ap_const_logic_1))) then
ap_enable_reg_pp1_iter2 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
ap_reg_grp_dct_2d_fu_186_ap_start_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_grp_dct_2d_fu_186_ap_start <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
ap_reg_grp_dct_2d_fu_186_ap_start <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_dct_2d_fu_186_ap_ready)) then
ap_reg_grp_dct_2d_fu_186_ap_start <= ap_const_logic_0;
end if;
end if;
end if;
end process;
c_i6_reg_175_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_flatten2_reg_420) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1))) then
c_i6_reg_175 <= c_1_fu_374_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (grp_dct_2d_fu_186_ap_done = ap_const_logic_1))) then
c_i6_reg_175 <= ap_const_lv4_0;
end if;
end if;
end process;
c_i_reg_142_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_reg_383 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
c_i_reg_142 <= c_fu_259_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
c_i_reg_142 <= ap_const_lv4_0;
end if;
end if;
end process;
indvar_flatten2_reg_153_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter0) and (ap_const_lv1_0 = exitcond_flatten2_fu_289_p2))) then
indvar_flatten2_reg_153 <= indvar_flatten_next2_fu_295_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (grp_dct_2d_fu_186_ap_done = ap_const_logic_1))) then
indvar_flatten2_reg_153 <= ap_const_lv7_0;
end if;
end if;
end process;
indvar_flatten_reg_120_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten_fu_194_p2 = ap_const_lv1_0))) then
indvar_flatten_reg_120 <= indvar_flatten_next_fu_200_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten_reg_120 <= ap_const_lv7_0;
end if;
end if;
end process;
r_i2_reg_164_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_flatten2_reg_420) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1))) then
r_i2_reg_164 <= tmp_i4_mid2_v_reg_436;
elsif (((ap_const_logic_1 = ap_CS_fsm_state6) and (grp_dct_2d_fu_186_ap_done = ap_const_logic_1))) then
r_i2_reg_164 <= ap_const_lv4_0;
end if;
end if;
end process;
r_i_reg_131_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_reg_383 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
r_i_reg_131 <= tmp_i_mid2_v_v_reg_399;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
r_i_reg_131 <= ap_const_lv4_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_c_i_mid2_reg_392 <= c_i_mid2_reg_392;
ap_reg_pp0_iter1_exitcond_flatten_reg_383 <= exitcond_flatten_reg_383;
ap_reg_pp0_iter1_tmp_i_mid2_v_v_reg_399 <= tmp_i_mid2_v_v_reg_399;
exitcond_flatten_reg_383 <= exitcond_flatten_fu_194_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp1_iter1_exitcond_flatten2_reg_420 <= exitcond_flatten2_reg_420;
exitcond_flatten2_reg_420 <= exitcond_flatten2_fu_289_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_flatten2_fu_289_p2))) then
c_i6_mid2_reg_429 <= c_i6_mid2_fu_313_p3;
tmp_3_reg_442 <= tmp_3_fu_329_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (exitcond_flatten_fu_194_p2 = ap_const_lv1_0))) then
c_i_mid2_reg_392 <= c_i_mid2_fu_218_p3;
tmp_reg_405 <= tmp_fu_234_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_flatten2_reg_420))) then
tmp_4_i_reg_452 <= tmp_4_i_fu_368_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter0) and (ap_const_lv1_0 = exitcond_flatten2_fu_289_p2))) then
tmp_i4_mid2_v_reg_436 <= tmp_i4_mid2_v_fu_321_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (exitcond_flatten_fu_194_p2 = ap_const_lv1_0))) then
tmp_i_mid2_v_v_reg_399 <= tmp_i_mid2_v_v_fu_226_p3;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, exitcond_flatten_fu_194_p2, ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, exitcond_flatten2_fu_289_p2, ap_enable_reg_pp1_iter0, ap_enable_reg_pp1_iter1, ap_block_pp0_stage0_flag00011011, ap_enable_reg_pp0_iter2, ap_CS_fsm_state6, grp_dct_2d_fu_186_ap_done, ap_block_pp1_stage0_flag00011011, ap_enable_reg_pp1_iter2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_flatten_fu_194_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif ((((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_flatten_fu_194_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)))) then
ap_NS_fsm <= ap_ST_fsm_state5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (grp_dct_2d_fu_186_ap_done = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state6;
end if;
when ap_ST_fsm_pp1_stage0 =>
if ((not(((ap_block_pp1_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter2) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0))) and not(((ap_const_logic_1 = ap_enable_reg_pp1_iter0) and (ap_block_pp1_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_flatten2_fu_289_p2 = ap_const_lv1_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
elsif ((((ap_block_pp1_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter2) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0)) or ((ap_const_logic_1 = ap_enable_reg_pp1_iter0) and (ap_block_pp1_stage0_flag00011011 = ap_const_boolean_0) and (exitcond_flatten2_fu_289_p2 = ap_const_lv1_1) and (ap_enable_reg_pp1_iter1 = ap_const_logic_0)))) then
ap_NS_fsm <= ap_ST_fsm_state10;
else
ap_NS_fsm <= ap_ST_fsm_pp1_stage0;
end if;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_pp1_stage0 <= ap_CS_fsm(4);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(5);
ap_CS_fsm_state5 <= ap_CS_fsm(2);
ap_CS_fsm_state6 <= ap_CS_fsm(3);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp1_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp1_stage0_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp1_stage0_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp1_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp1_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp1_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state2_assign_proc : process(exitcond_flatten_fu_194_p2)
begin
if ((exitcond_flatten_fu_194_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_condition_pp1_exit_iter0_state7_assign_proc : process(exitcond_flatten2_fu_289_p2)
begin
if ((exitcond_flatten2_fu_289_p2 = ap_const_lv1_1)) then
ap_condition_pp1_exit_iter0_state7 <= ap_const_logic_1;
else
ap_condition_pp1_exit_iter0_state7 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_CS_fsm_state10)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state10)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_enable_pp1 <= (ap_idle_pp1 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp1_assign_proc : process(ap_enable_reg_pp1_iter0, ap_enable_reg_pp1_iter1, ap_enable_reg_pp1_iter2)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp1_iter0) and (ap_const_logic_0 = ap_enable_reg_pp1_iter1) and (ap_const_logic_0 = ap_enable_reg_pp1_iter2))) then
ap_idle_pp1 <= ap_const_logic_1;
else
ap_idle_pp1 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state10)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state10)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
buf_2d_in_address0_assign_proc : process(ap_enable_reg_pp0_iter2, ap_CS_fsm_state6, grp_dct_2d_fu_186_in_block_address0, ap_block_pp0_stage0_flag00000000, tmp_31_cast_fu_284_p1)
begin
if (((ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
buf_2d_in_address0 <= tmp_31_cast_fu_284_p1(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
buf_2d_in_address0 <= grp_dct_2d_fu_186_in_block_address0;
else
buf_2d_in_address0 <= "XXXXXX";
end if;
end process;
buf_2d_in_ce0_assign_proc : process(ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter2, ap_CS_fsm_state6, grp_dct_2d_fu_186_in_block_ce0)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
buf_2d_in_ce0 <= ap_const_logic_1;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
buf_2d_in_ce0 <= grp_dct_2d_fu_186_in_block_ce0;
else
buf_2d_in_ce0 <= ap_const_logic_0;
end if;
end process;
buf_2d_in_we0_assign_proc : process(ap_block_pp0_stage0_flag00011001, ap_reg_pp0_iter1_exitcond_flatten_reg_383, ap_enable_reg_pp0_iter2)
begin
if (((ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_reg_pp0_iter1_exitcond_flatten_reg_383 = ap_const_lv1_0))) then
buf_2d_in_we0 <= ap_const_logic_1;
else
buf_2d_in_we0 <= ap_const_logic_0;
end if;
end process;
buf_2d_out_address0_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_enable_reg_pp1_iter1, ap_CS_fsm_state6, grp_dct_2d_fu_186_out_block_address0, ap_block_pp1_stage0_flag00000000, tmp_35_cast_fu_363_p1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00000000 = ap_const_boolean_0))) then
buf_2d_out_address0 <= tmp_35_cast_fu_363_p1(6 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
buf_2d_out_address0 <= grp_dct_2d_fu_186_out_block_address0;
else
buf_2d_out_address0 <= "XXXXXX";
end if;
end process;
buf_2d_out_ce0_assign_proc : process(ap_CS_fsm_pp1_stage0, ap_block_pp1_stage0_flag00011001, ap_enable_reg_pp1_iter1, ap_CS_fsm_state6, grp_dct_2d_fu_186_out_block_ce0)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1))) then
buf_2d_out_ce0 <= ap_const_logic_1;
elsif ((ap_const_logic_1 = ap_CS_fsm_state6)) then
buf_2d_out_ce0 <= grp_dct_2d_fu_186_out_block_ce0;
else
buf_2d_out_ce0 <= ap_const_logic_0;
end if;
end process;
buf_2d_out_we0_assign_proc : process(ap_CS_fsm_state6, grp_dct_2d_fu_186_out_block_we0)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
buf_2d_out_we0 <= grp_dct_2d_fu_186_out_block_we0;
else
buf_2d_out_we0 <= ap_const_logic_0;
end if;
end process;
c_1_fu_374_p2 <= std_logic_vector(unsigned(ap_const_lv4_1) + unsigned(c_i6_mid2_reg_429));
c_fu_259_p2 <= std_logic_vector(unsigned(ap_const_lv4_1) + unsigned(c_i_mid2_reg_392));
c_i6_cast2_fu_351_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(c_i6_mid2_reg_429),6));
c_i6_mid2_fu_313_p3 <=
ap_const_lv4_0 when (exitcond_i1_fu_307_p2(0) = '1') else
c_i6_phi_fu_179_p4;
c_i6_phi_fu_179_p4_assign_proc : process(c_i6_reg_175, exitcond_flatten2_reg_420, ap_CS_fsm_pp1_stage0, c_1_fu_374_p2, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_lv1_0 = exitcond_flatten2_reg_420) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00000000 = ap_const_boolean_0))) then
c_i6_phi_fu_179_p4 <= c_1_fu_374_p2;
else
c_i6_phi_fu_179_p4 <= c_i6_reg_175;
end if;
end process;
c_i_cast6_fu_245_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(c_i_mid2_reg_392),6));
c_i_mid2_fu_218_p3 <=
ap_const_lv4_0 when (exitcond_i_fu_212_p2(0) = '1') else
c_i_phi_fu_146_p4;
c_i_phi_fu_146_p4_assign_proc : process(c_i_reg_142, exitcond_flatten_reg_383, ap_CS_fsm_pp0_stage0, c_fu_259_p2, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_383 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
c_i_phi_fu_146_p4 <= c_fu_259_p2;
else
c_i_phi_fu_146_p4 <= c_i_reg_142;
end if;
end process;
exitcond_flatten2_fu_289_p2 <= "1" when (indvar_flatten2_reg_153 = ap_const_lv7_40) else "0";
exitcond_flatten_fu_194_p2 <= "1" when (indvar_flatten_reg_120 = ap_const_lv7_40) else "0";
exitcond_i1_fu_307_p2 <= "1" when (c_i6_phi_fu_179_p4 = ap_const_lv4_8) else "0";
exitcond_i_fu_212_p2 <= "1" when (c_i_phi_fu_146_p4 = ap_const_lv4_8) else "0";
grp_dct_2d_fu_186_ap_start <= ap_reg_grp_dct_2d_fu_186_ap_start;
indvar_flatten_next2_fu_295_p2 <= std_logic_vector(unsigned(indvar_flatten2_reg_153) + unsigned(ap_const_lv7_1));
indvar_flatten_next_fu_200_p2 <= std_logic_vector(unsigned(indvar_flatten_reg_120) + unsigned(ap_const_lv7_1));
input_r_address0 <= tmp_i_fu_254_p1(6 - 1 downto 0);
input_r_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
input_r_ce0 <= ap_const_logic_1;
else
input_r_ce0 <= ap_const_logic_0;
end if;
end process;
output_r_address0 <= tmp_5_i_fu_379_p1(6 - 1 downto 0);
output_r_ce0_assign_proc : process(ap_block_pp1_stage0_flag00011001, ap_enable_reg_pp1_iter2)
begin
if (((ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter2))) then
output_r_ce0 <= ap_const_logic_1;
else
output_r_ce0 <= ap_const_logic_0;
end if;
end process;
output_r_d0 <= buf_2d_out_q0;
output_r_we0_assign_proc : process(ap_block_pp1_stage0_flag00011001, ap_reg_pp1_iter1_exitcond_flatten2_reg_420, ap_enable_reg_pp1_iter2)
begin
if (((ap_block_pp1_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp1_iter2) and (ap_const_lv1_0 = ap_reg_pp1_iter1_exitcond_flatten2_reg_420))) then
output_r_we0 <= ap_const_logic_1;
else
output_r_we0 <= ap_const_logic_0;
end if;
end process;
r_1_fu_301_p2 <= std_logic_vector(unsigned(ap_const_lv4_1) + unsigned(r_i2_phi_fu_168_p4));
r_fu_206_p2 <= std_logic_vector(unsigned(ap_const_lv4_1) + unsigned(r_i_phi_fu_135_p4));
r_i2_phi_fu_168_p4_assign_proc : process(r_i2_reg_164, exitcond_flatten2_reg_420, ap_CS_fsm_pp1_stage0, tmp_i4_mid2_v_reg_436, ap_enable_reg_pp1_iter1, ap_block_pp1_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp1_stage0) and (ap_const_lv1_0 = exitcond_flatten2_reg_420) and (ap_const_logic_1 = ap_enable_reg_pp1_iter1) and (ap_block_pp1_stage0_flag00000000 = ap_const_boolean_0))) then
r_i2_phi_fu_168_p4 <= tmp_i4_mid2_v_reg_436;
else
r_i2_phi_fu_168_p4 <= r_i2_reg_164;
end if;
end process;
r_i_phi_fu_135_p4_assign_proc : process(r_i_reg_131, exitcond_flatten_reg_383, ap_CS_fsm_pp0_stage0, tmp_i_mid2_v_v_reg_399, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (exitcond_flatten_reg_383 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
r_i_phi_fu_135_p4 <= tmp_i_mid2_v_v_reg_399;
else
r_i_phi_fu_135_p4 <= r_i_reg_131;
end if;
end process;
tmp_1_i5_mid2_fu_344_p3 <= (tmp_3_reg_442 & ap_const_lv3_0);
tmp_1_i_cast_fu_275_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter1_c_i_mid2_reg_392),8));
tmp_22_fu_278_p2 <= std_logic_vector(unsigned(tmp_30_cast_fu_271_p1) + unsigned(tmp_1_i_cast_fu_275_p1));
tmp_23_fu_333_p3 <= (tmp_i4_mid2_v_reg_436 & ap_const_lv3_0);
tmp_24_fu_357_p2 <= std_logic_vector(unsigned(tmp_33_cast_fu_340_p1) + unsigned(tmp_3_i_cast_fu_354_p1));
tmp_30_cast_fu_271_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_s_fu_264_p3),8));
tmp_31_cast_fu_284_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_22_fu_278_p2),64));
tmp_33_cast_fu_340_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_23_fu_333_p3),8));
tmp_35_cast_fu_363_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_24_fu_357_p2),64));
tmp_3_fu_329_p1 <= tmp_i4_mid2_v_fu_321_p3(3 - 1 downto 0);
tmp_3_i_cast_fu_354_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(c_i6_mid2_reg_429),8));
tmp_4_i_fu_368_p2 <= std_logic_vector(unsigned(c_i6_cast2_fu_351_p1) + unsigned(tmp_1_i5_mid2_fu_344_p3));
tmp_5_i_fu_379_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_4_i_reg_452),64));
tmp_9_i_fu_248_p2 <= std_logic_vector(unsigned(c_i_cast6_fu_245_p1) + unsigned(tmp_i_mid2_fu_238_p3));
tmp_fu_234_p1 <= tmp_i_mid2_v_v_fu_226_p3(3 - 1 downto 0);
tmp_i4_mid2_v_fu_321_p3 <=
r_1_fu_301_p2 when (exitcond_i1_fu_307_p2(0) = '1') else
r_i2_phi_fu_168_p4;
tmp_i_fu_254_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_i_fu_248_p2),64));
tmp_i_mid2_fu_238_p3 <= (tmp_reg_405 & ap_const_lv3_0);
tmp_i_mid2_v_v_fu_226_p3 <=
r_fu_206_p2 when (exitcond_i_fu_212_p2(0) = '1') else
r_i_phi_fu_135_p4;
tmp_s_fu_264_p3 <= (ap_reg_pp0_iter1_tmp_i_mid2_v_v_reg_399 & ap_const_lv3_0);
end behav;
|
<filename>vunit/vhdl/data_types/src/integer_vector_ptr_pkg.vhd
-- This Source Code Form is subject to the terms of the Mozilla Public
-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
-- You can obtain one at http://mozilla.org/MPL/2.0/.
--
-- Copyright (c) 2017-2018, <NAME> <EMAIL>
--
-- The purpose of this package is to provide an integer vector access type (pointer)
-- that can itself be used in arrays and returned from functions unlike a
-- real access type. This is achieved by letting the actual value be a handle
-- into a singleton datastructure of integer vector access types.
--
use work.codec_pkg.all;
use work.codec_builder_pkg.all;
package integer_vector_ptr_pkg is
subtype index_t is integer range -1 to integer'high;
type integer_vector_ptr_t is record
index : index_t;
end record;
constant null_ptr : integer_vector_ptr_t := (index => -1);
function to_integer(value : integer_vector_ptr_t) return integer;
impure function to_integer_vector_ptr(value : integer) return integer_vector_ptr_t;
impure function new_integer_vector_ptr(length : natural := 0; value : integer := 0) return integer_vector_ptr_t;
procedure deallocate(ptr : integer_vector_ptr_t);
impure function length(ptr : integer_vector_ptr_t) return integer;
procedure set(ptr : integer_vector_ptr_t; index : integer; value : integer);
impure function get(ptr : integer_vector_ptr_t; index : integer) return integer;
procedure reallocate(ptr : integer_vector_ptr_t; length : natural; value : integer := 0);
procedure resize(ptr : integer_vector_ptr_t; length : natural; drop : natural := 0; value : integer := 0);
constant integer_vector_ptr_t_code_length : positive := integer_code_length;
function encode(data : integer_vector_ptr_t) return string;
function decode(code : string) return integer_vector_ptr_t;
procedure decode(
constant code : string;
variable index : inout positive;
variable result : out integer_vector_ptr_t);
alias encode_integer_vector_ptr_t is encode[integer_vector_ptr_t return string];
alias decode_integer_vector_ptr_t is decode[string return integer_vector_ptr_t];
end package;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use WORK.MATRIX_CONST.all;
use WORK.PACKAGE_ENCRYPTION_LUT.all;
entity sub_bytes is
port(
-- INPUTS
-- data input
pi_data : IN STD_LOGIC_VECTOR(MATRIX_DATA_WIDTH-1 DOWNTO 0);
-- OUTPUTS
-- data output
po_data : OUT STD_LOGIC_VECTOR(MATRIX_DATA_WIDTH-1 DOWNTO 0)
);
end sub_bytes;
architecture behavioral of sub_bytes is
signal w_DATA_OUT : STD_LOGIC_VECTOR(MATRIX_DATA_WIDTH-1 DOWNTO 0) := (others => '0');
begin
generate_luts: for i in 0 to 15 generate
SBOX_i: lut_sbox
port map
(pi_address => pi_data(c_BYTE(i) downto c_BYTE(i)-7),
po_data => w_DATA_OUT(c_BYTE(i) downto c_BYTE(i)-7)
);
end generate;
po_data <= w_DATA_OUT;
end behavioral;
|
<gh_stars>100-1000
-- Copyright 2018 Delft University of Technology
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library work;
use work.Stream_pkg.all;
use work.Buffer_pkg.all;
use work.UtilInt_pkg.all;
use work.UtilMisc_pkg.all;
entity BufferReaderPost is
generic (
---------------------------------------------------------------------------
-- Signal widths and functional configuration
---------------------------------------------------------------------------
-- Buffer element width in bits.
ELEMENT_WIDTH : natural;
-- Whether this is a normal buffer or an offsets buffer.
IS_OFFSETS_BUFFER : boolean;
-- Maximum amount of elements per FIFO entry.
ELEMENT_FIFO_COUNT_MAX : natural;
-- Width of the FIFO element count vector. Should equal
-- max(1, ceil(log2(FIFO_COUNT_MAX)))
ELEMENT_FIFO_COUNT_WIDTH : natural;
-- Maximum number of elements returned per cycle. When more than 1,
-- elements are returned LSB-aligned and LSB-first, along with a count
-- field that indicates how many elements are valid. A best-effort approach
-- is utilized; no guarantees are made about how many elements are actually
-- returned per cycle. This feature is not supported for offsets buffers.
ELEMENT_COUNT_MAX : natural;
-- Width of the vector indicating the number of valid elements. Must be at
-- least 1 to prevent null ranges.
ELEMENT_COUNT_WIDTH : natural;
---------------------------------------------------------------------------
-- Timing configuration
---------------------------------------------------------------------------
-- Whether a register slice should be inserted between the FIFO and the
-- post-processing logic (differential encoder for offsets buffers and
-- optional serialization).
FIFO2POST_SLICE : boolean;
-- Whether a register slice should be inserted into the output stream.
OUT_SLICE : boolean
);
port (
---------------------------------------------------------------------------
-- Clock domains
---------------------------------------------------------------------------
-- Rising-edge sensitive clock and active-high synchronous reset.
clk : in std_logic;
reset : in std_logic;
---------------------------------------------------------------------------
-- Input stream
---------------------------------------------------------------------------
-- Data stream from the FIFO. fifo_data contains FIFO_COUNT_MAX elements,
-- each ELEMENT_WIDTH in size. The first element is LSB aligned.
-- fifoOut_count indicates how many elements are valid. There is always at
-- least 1 element valid; the MSB of this signal is 1 implicitly when count
-- is zero (that is, if count is "00", all "100" = 4 elements are valid).
-- fifoOut_last indicates that the last word for the current command is
-- present in this bundle.
fifoOut_valid : in std_logic;
fifoOut_ready : out std_logic;
fifoOut_data : in std_logic_vector(ELEMENT_FIFO_COUNT_MAX*ELEMENT_WIDTH-1 downto 0);
fifoOut_count : in std_logic_vector(ELEMENT_FIFO_COUNT_WIDTH-1 downto 0);
fifoOut_last : in std_logic;
---------------------------------------------------------------------------
-- Output stream
---------------------------------------------------------------------------
-- Buffer element stream output. element contains the data element for
-- normal buffers and the length for offsets buffers. last is asserted when
-- this is the last element for the current command.
out_valid : out std_logic;
out_ready : in std_logic;
out_data : out std_logic_vector(ELEMENT_COUNT_MAX*ELEMENT_WIDTH-1 downto 0);
out_count : out std_logic_vector(ELEMENT_COUNT_WIDTH-1 downto 0);
out_last : out std_logic
);
end BufferReaderPost;
architecture Behavioral of BufferReaderPost is
-- FIFO stream after the optional register slice.
signal fifoOutB_valid : std_logic;
signal fifoOutB_ready : std_logic;
signal fifoOutB_data : std_logic_vector(ELEMENT_FIFO_COUNT_MAX*ELEMENT_WIDTH-1 downto 0);
signal fifoOutB_count : std_logic_vector(ELEMENT_FIFO_COUNT_WIDTH-1 downto 0);
signal fifoOutB_last : std_logic;
-- Serialized stream.
signal outS_valid : std_logic;
signal outS_ready : std_logic;
signal outS_data : std_logic_vector(ELEMENT_COUNT_MAX*ELEMENT_WIDTH-1 downto 0);
signal outS_count : std_logic_vector(ELEMENT_COUNT_WIDTH-1 downto 0);
signal outS_last : std_logic;
-- Serialized and differentially-encoded (if required) stream.
signal outD_valid : std_logic;
signal outD_ready : std_logic;
signal outD_data : std_logic_vector(ELEMENT_COUNT_MAX*ELEMENT_WIDTH-1 downto 0);
signal outD_count : std_logic_vector(ELEMENT_COUNT_WIDTH-1 downto 0);
signal outD_last : std_logic;
-- FIFO output stream serialization indices.
constant FOI : nat_array := cumulative((
2 => fifoOut_data'length,
1 => fifoOut_count'length,
0 => 1 -- fifoOut_last
));
signal fifoOut_sData : std_logic_vector(FOI(FOI'high)-1 downto 0);
signal fifoOutB_sData : std_logic_vector(FOI(FOI'high)-1 downto 0);
-- Element output stream serialization indices.
constant IOI : nat_array := cumulative((
2 => out_data'length,
1 => out_count'length,
0 => 1 -- out_last
));
signal outD_sData : std_logic_vector(IOI(IOI'high)-1 downto 0);
signal out_sData : std_logic_vector(IOI(IOI'high)-1 downto 0);
begin
-- Generate an optional register slice between FIFO and the gearbox and
-- optional differential encoder.
fifo_to_post_buffer_inst: StreamBuffer
generic map (
MIN_DEPTH => sel(FIFO2POST_SLICE, 2, 0),
DATA_WIDTH => FOI(FOI'high)
)
port map (
clk => clk,
reset => reset,
in_valid => fifoOut_valid,
in_ready => fifoOut_ready,
in_data => fifoOut_sData,
out_valid => fifoOutB_valid,
out_ready => fifoOutB_ready,
out_data => fifoOutB_sData
);
fifoOut_sData(FOI(3)-1 downto FOI(2)) <= fifoOut_data;
fifoOut_sData(FOI(2)-1 downto FOI(1)) <= fifoOut_count;
fifoOut_sData(FOI(0)) <= fifoOut_last;
fifoOutB_data <= fifoOutB_sData(FOI(3)-1 downto FOI(2));
fifoOutB_count <= fifoOutB_sData(FOI(2)-1 downto FOI(1));
fifoOutB_last <= fifoOutB_sData(FOI(0));
-- Gearbox between FIFO and output stream.
post_gearbox_inst: StreamGearbox
generic map (
ELEMENT_WIDTH => ELEMENT_WIDTH,
IN_COUNT_MAX => ELEMENT_FIFO_COUNT_MAX,
IN_COUNT_WIDTH => ELEMENT_FIFO_COUNT_WIDTH,
OUT_COUNT_MAX => ELEMENT_COUNT_MAX,
OUT_COUNT_WIDTH => ELEMENT_COUNT_WIDTH
)
port map (
clk => clk,
reset => reset,
in_valid => fifoOutB_valid,
in_ready => fifoOutB_ready,
in_data => fifoOutB_data,
in_count => fifoOutB_count,
in_last => fifoOutB_last,
out_valid => outS_valid,
out_ready => outS_ready,
out_data => outS_data,
out_count => outS_count,
out_last => outS_last
);
-- Connect the outS and outD streams directly for normal buffers.
normal_buffer_gen: if not IS_OFFSETS_BUFFER generate
begin
outD_valid <= outS_valid;
outS_ready <= outD_ready;
outD_data <= outS_data;
outD_count <= outS_count;
outD_last <= outS_last;
end generate;
-- Differentially encode the stream for offsets buffers to turn offset pairs
-- into lengths.
offsets_buffer_gen: if IS_OFFSETS_BUFFER generate
-- Previous entry storage.
signal prev_valid : std_logic;
signal prev_data : std_logic_vector(ELEMENT_WIDTH-1 downto 0);
begin
-- Differential encoding is only supported for one element per clock. The
-- code below will not synthesize correctly due to incorrect vector widths
-- if this assertion fails.
assert ELEMENT_COUNT_MAX = 1
report "Offsets buffers currently do not support multiple elements per cycle."
severity FAILURE;
-- Save the previous entry.
prev_data_proc: process (clk) is
begin
if rising_edge(clk) then
if outS_valid = '1' and outS_ready = '1' then
prev_valid <= not outS_last;
prev_data <= outS_data;
end if;
if reset = '1' then
prev_valid <= '0';
-- pragma translate_off
prev_data <= (others => 'U');
-- pragma translate_on
end if;
end if;
end process;
-- Gobble up the first entry in every burst.
outD_valid <= outS_valid and prev_valid;
outS_ready <= outD_ready or not prev_valid;
-- Differentially encode the data.
outD_data <= std_logic_vector(unsigned(outS_data) - unsigned(prev_data));
-- Forward the "last" flag without modification.
outD_last <= outS_last;
end generate;
-- Generate an optional register slice in the output stream.
out_buffer_inst: StreamBuffer
generic map (
MIN_DEPTH => sel(OUT_SLICE, 2, 0),
DATA_WIDTH => IOI(IOI'high)
)
port map (
clk => clk,
reset => reset,
in_valid => outD_valid,
in_ready => outD_ready,
in_data => outD_sdata,
out_valid => out_valid,
out_ready => out_ready,
out_data => out_sData
);
outD_sData(IOI(3)-1 downto IOI(2)) <= outD_data;
outD_sData(IOI(2)-1 downto IOI(1)) <= outD_count;
outD_sData(IOI(0)) <= outD_last;
out_data <= out_sData(IOI(3)-1 downto IOI(2));
out_count <= out_sData(IOI(2)-1 downto IOI(1));
out_last <= out_sData(IOI(0));
end Behavioral;
|
<gh_stars>1-10
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.common.all;
package id_pkg is
type id_in is record
instruction : word;
end record id_in;
-- structure for decoded instruction
type decoded_t is record
alu_func : alu_func_t;
op2_src : std_logic;
insn_type : insn_type_t;
branch_type : branch_type_t;
load_type : load_type_t;
store_type : store_type_t;
rs1 : std_logic_vector(4 downto 0);
rs2 : std_logic_vector(4 downto 0);
rd : std_logic_vector(4 downto 0);
imm : word;
opcode : std_logic_vector(6 downto 0);
rs1_rd : std_logic;
rs2_rd : std_logic;
use_imm : std_logic;
rf_we : std_logic;
end record decoded_t;
constant c_decoded_reset : decoded_t := (alu_func => ALU_NONE,
op2_src => '0',
insn_type => OP_ILLEGAL,
branch_type => BRANCH_NONE,
load_type => LOAD_NONE,
store_type => STORE_NONE,
rs1 => "00000",
rs2 => "00000",
rd => "00000",
imm => (others => '0'),
opcode => (others => 'X'),
rs1_rd => '0',
rs2_rd => '0',
use_imm => '0',
rf_we => '0');
-- Constants
constant c_op_load : std_logic_vector(6 downto 0) := "0000011";
constant c_op_misc_mem : std_logic_vector(6 downto 0) := "0001111";
constant c_op_imm : std_logic_vector(6 downto 0) := "0010011";
constant c_op_auipc : std_logic_vector(6 downto 0) := "0010111";
constant c_op_store : std_logic_vector(6 downto 0) := "0100011";
constant c_op_reg : std_logic_vector(6 downto 0) := "0110011";
constant c_op_lui : std_logic_vector(6 downto 0) := "0110111";
constant c_op_branch : std_logic_vector(6 downto 0) := "1100011";
constant c_op_jalr : std_logic_vector(6 downto 0) := "1100111";
constant c_op_jal : std_logic_vector(6 downto 0) := "1101111";
constant c_op_system : std_logic_vector(6 downto 0) := "1110011";
procedure print_insn (insn_type : in insn_type_t);
end package id_pkg;
package body id_pkg is
procedure print_insn (insn_type : in insn_type_t) is
variable l : line;
begin
write(l, string'("Instruction type: "));
if insn_type = OP_LUI then
write(l, string'("LUI"));
writeline(output, l);
elsif insn_type = OP_AUIPC then
write(l, string'("AUIPC"));
writeline(output, l);
elsif insn_type = OP_JAL then
write(l, string'("JAL"));
writeline(output, l);
elsif insn_type = OP_JALR then
write(l, string'("JALR"));
writeline(output, l);
elsif insn_type = OP_BRANCH then
write(l, string'("BRANCH"));
writeline(output, l);
elsif insn_type = OP_LOAD then
write(l, string'("LOAD"));
writeline(output, l);
elsif insn_type = OP_STORE then
write(l, string'("STORE"));
writeline(output, l);
elsif insn_type = OP_ALU then
write(l, string'("ALU"));
writeline(output, l);
elsif insn_type = OP_STALL then
write(l, string'("STALL"));
writeline(output, l);
else
write(l, string'("ILLEGAL"));
writeline(output, l);
end if;
end procedure print_insn;
end package body id_pkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PacketRx_tb is
-- Port ( );
end PacketRx_tb;
architecture Behavioral of PacketRx_tb is
signal test_clk : std_logic;
signal test_rst : std_logic;
signal test_valid : std_logic;
signal tx_ready_out : std_logic;
signal tx_valid_out : std_logic;
signal rx_ready_out : std_logic;
signal rx_valid_out : std_logic;
signal test_packet : std_logic_vector(31 downto 0);
signal test_data_out : std_logic_vector(15 downto 0);
signal test_symbol_out : std_logic_vector(7 downto 0);
begin
PacketTx_module: entity work.PacketTx
generic map (
SYMBOL_WIDTH => 8,
PACKET_SYMBOLS => 4
)
port map (
CLK => test_clk,
RST => test_rst,
-- upstream
READY_OUT => tx_ready_out,
VALID_IN => test_valid,
-- downstream
READY_IN => rx_ready_out,
VALID_OUT => tx_valid_out,
PACKET_IN => test_packet,
SYMBOL_OUT => test_symbol_out
);
PacketRx_module: entity work.PacketRx
generic map (
SYMBOL_WIDTH => 8,
DATA_SYMBOLS => 2,
HEADER_SYMBOLS => 2
)
port map (
CLK => test_clk,
RST => test_rst,
-- upstream
READY_OUT => rx_ready_out,
VALID_IN => tx_valid_out,
-- downstream
READY_IN => '1',
VALID_OUT => rx_valid_out,
HEADER_IN => x"0102",
SYMBOL_IN => test_symbol_out,
DATA_OUT => test_data_out
);
process
begin
-- initial
test_packet <= x"01020304";
test_rst <= '1';
test_valid <= '0';
wait for 2ns;
test_clk <= '0';
wait for 2ns;
test_clk <= '1';
wait for 2ns;
test_clk <= '0';
test_rst <= '0';
test_valid <= '1';
wait for 2ns;
test_clk <= '1';
wait for 2ns;
test_clk <= '0';
wait for 2ns;
test_valid <= '0';
for a in 0 to 63 loop
-- clock edge
wait for 2ns;
test_clk <= '1';
wait for 2ns;
test_clk <= '0';
end loop;
test_packet <= x"0102eeff";
test_valid <= '1';
wait for 2ns;
test_clk <= '1';
wait for 2ns;
test_clk <= '0';
wait for 2ns;
test_valid <= '0';
for a in 0 to 63 loop
-- clock edge
wait for 2ns;
test_clk <= '1';
wait for 2ns;
test_clk <= '0';
end loop;
end process;
end Behavioral;
|
<gh_stars>0
----------------------------------------------------------------------
-- Created by SmartDesign Thu Jun 22 17:22:48 2017
-- Version: v11.8 172.16.58.3
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library proasic3;
use proasic3.all;
library COREUART_LIB;
use COREUART_LIB.all;
use COREUART_LIB.CU_TOP_FPGA_UART_components.all;
----------------------------------------------------------------------
-- CU_TOP entity declaration
----------------------------------------------------------------------
entity CU_TOP is
-- Port list
port(
-- Inputs
CLK : in std_logic;
FPGA_UART_RX : in std_logic;
PWRONRESET : in std_logic;
-- Outputs
CUTTER : out std_logic;
FPGA_UART_TX : out std_logic;
L1_GPS_PWR : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
MICRO_CLK : out std_logic;
PRESSURE_PWR : out std_logic;
SAT_PWR : out std_logic;
SENS_MEM_L5_PWR : out std_logic;
VHF_PWR : out std_logic
);
end CU_TOP;
----------------------------------------------------------------------
-- CU_TOP architecture body
----------------------------------------------------------------------
architecture RTL of CU_TOP is
----------------------------------------------------------------------
-- Component declarations
----------------------------------------------------------------------
-- CLKINT
component CLKINT
-- Port list
port(
-- Inputs
A : in std_logic;
-- Outputs
Y : out std_logic
);
end component;
-- CUTTER_PWM
component CUTTER_PWM
-- Port list
port(
-- Inputs
duty : in std_logic_vector(7 downto 0);
duty_wrt : in std_logic;
ena : in std_logic;
mclk : in std_logic;
reset : in std_logic;
-- Outputs
pwm_out : out std_logic_vector(0 to 0)
);
end component;
-- CU_TOP_FPGA_UART_COREUART - Actel:DirectCore:COREUART:5.6.102
component CU_TOP_FPGA_UART_COREUART
generic(
BAUD_VAL_FRCTN_EN : integer := 1 ;
FAMILY : integer := 15 ;
RX_FIFO : integer := 0 ;
RX_LEGACY_MODE : integer := 0 ;
TX_FIFO : integer := 0
);
-- Port list
port(
-- Inputs
BAUD_VAL : in std_logic_vector(12 downto 0);
BAUD_VAL_FRACTION : in std_logic_vector(2 downto 0);
BIT8 : in std_logic;
CLK : in std_logic;
CSN : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
ODD_N_EVEN : in std_logic;
OEN : in std_logic;
PARITY_EN : in std_logic;
RESET_N : in std_logic;
RX : in std_logic;
WEN : in std_logic;
-- Outputs
DATA_OUT : out std_logic_vector(7 downto 0);
FRAMING_ERR : out std_logic;
OVERFLOW : out std_logic;
PARITY_ERR : out std_logic;
RXRDY : out std_logic;
TX : out std_logic;
TXRDY : out std_logic
);
end component;
-- OR2
component OR2
-- Port list
port(
-- Inputs
A : in std_logic;
B : in std_logic;
-- Outputs
Y : out std_logic
);
end component;
-- system_clock
component system_clock
-- Port list
port(
-- Inputs
mclk : in std_logic;
reset : in std_logic;
-- Outputs
m_time : out std_logic_vector(25 downto 0)
);
end component;
-- UART_reset_monitor
component UART_reset_monitor
-- Port list
port(
-- Inputs
data_in : in std_logic_vector(7 downto 0);
mclk : in std_logic;
reset_in : in std_logic;
txrdy : in std_logic;
-- Outputs
reset_out : out std_logic
);
end component;
-- WOLF_CONTROLLER
component WOLF_CONTROLLER
-- Port list
port(
-- Inputs
clk_1hz : in std_logic;
mclk : in std_logic;
reset : in std_logic;
uart_data_in : in std_logic_vector(7 downto 0);
uart_rxrdy : in std_logic;
uart_txrdy : in std_logic;
-- Outputs
cutter_en : out std_logic;
cutter_pwm_duty : out std_logic_vector(7 downto 0);
led1 : out std_logic;
led2 : out std_logic;
uart_baud_val : out std_logic_vector(12 downto 0);
uart_baud_val_frac : out std_logic_vector(2 downto 0);
uart_data_out : out std_logic_vector(7 downto 0);
uart_oen : out std_logic;
uart_wen : out std_logic
);
end component;
----------------------------------------------------------------------
-- Signal declarations
----------------------------------------------------------------------
signal CLKINT_0_Y : std_logic;
signal CLKINT_1_Y : std_logic;
signal CUTTER_net_0 : std_logic_vector(0 to 0);
signal FPGA_UART_DATA_OUT : std_logic_vector(7 downto 0);
signal FPGA_UART_TX_net_0 : std_logic;
signal FPGA_UART_TXRDY : std_logic;
signal LED1_net_0 : std_logic;
signal LED1_0 : std_logic;
signal LED1_2 : std_logic;
signal LED1_3 : std_logic;
signal LED2_net_0 : std_logic;
signal LED2_1 : std_logic_vector(25 to 25);
signal MICRO_CLK_net_0 : std_logic_vector(1 to 1);
signal OR2_0_Y : std_logic;
signal WOLF_CONTROLLER_cutter_pwm_duty : std_logic_vector(7 downto 0);
signal WOLF_CONTROLLER_uart_baud_val : std_logic_vector(12 downto 0);
signal WOLF_CONTROLLER_uart_baud_val_frac : std_logic_vector(2 downto 0);
signal WOLF_CONTROLLER_uart_data_out : std_logic_vector(7 downto 0);
signal CUTTER_net_1 : std_logic;
signal LED2_1_net_0 : std_logic;
signal FPGA_UART_TX_net_1 : std_logic;
signal LED1_3_net_0 : std_logic;
signal MICRO_CLK_net_1 : std_logic;
signal m_time_slice_0 : std_logic_vector(0 to 0);
signal m_time_slice_1 : std_logic_vector(10 to 10);
signal m_time_slice_2 : std_logic_vector(11 to 11);
signal m_time_slice_3 : std_logic_vector(12 to 12);
signal m_time_slice_4 : std_logic_vector(13 to 13);
signal m_time_slice_5 : std_logic_vector(14 to 14);
signal m_time_slice_6 : std_logic_vector(15 to 15);
signal m_time_slice_7 : std_logic_vector(16 to 16);
signal m_time_slice_8 : std_logic_vector(17 to 17);
signal m_time_slice_9 : std_logic_vector(18 to 18);
signal m_time_slice_10 : std_logic_vector(19 to 19);
signal m_time_slice_11 : std_logic_vector(20 to 20);
signal m_time_slice_12 : std_logic_vector(21 to 21);
signal m_time_slice_13 : std_logic_vector(22 to 22);
signal m_time_slice_14 : std_logic_vector(23 to 23);
signal m_time_slice_15 : std_logic_vector(24 to 24);
signal m_time_slice_16 : std_logic_vector(2 to 2);
signal m_time_slice_17 : std_logic_vector(3 to 3);
signal m_time_slice_18 : std_logic_vector(4 to 4);
signal m_time_slice_19 : std_logic_vector(5 to 5);
signal m_time_slice_20 : std_logic_vector(6 to 6);
signal m_time_slice_21 : std_logic_vector(7 to 7);
signal m_time_slice_22 : std_logic_vector(8 to 8);
signal m_time_slice_23 : std_logic_vector(9 to 9);
signal m_time_net_0 : std_logic_vector(25 downto 0);
----------------------------------------------------------------------
-- TiedOff Signals
----------------------------------------------------------------------
signal GND_net : std_logic;
signal VCC_net : std_logic;
----------------------------------------------------------------------
-- Inverted Signals
----------------------------------------------------------------------
signal RESET_N_IN_POST_INV0_0 : std_logic;
begin
----------------------------------------------------------------------
-- Constant assignments
----------------------------------------------------------------------
GND_net <= '0';
VCC_net <= '1';
----------------------------------------------------------------------
-- Inversions
----------------------------------------------------------------------
RESET_N_IN_POST_INV0_0 <= NOT OR2_0_Y;
----------------------------------------------------------------------
-- TieOff assignments
----------------------------------------------------------------------
L1_GPS_PWR <= '0';
VHF_PWR <= '0';
SENS_MEM_L5_PWR <= '0';
SAT_PWR <= '0';
PRESSURE_PWR <= '0';
----------------------------------------------------------------------
-- Top level output port assignments
----------------------------------------------------------------------
CUTTER_net_1 <= CUTTER_net_0(0);
CUTTER <= CUTTER_net_1;
LED2_1_net_0 <= LED2_1(25);
LED2 <= LED2_1_net_0;
FPGA_UART_TX_net_1 <= FPGA_UART_TX_net_0;
FPGA_UART_TX <= FPGA_UART_TX_net_1;
LED1_3_net_0 <= LED1_3;
LED1 <= LED1_3_net_0;
MICRO_CLK_net_1 <= MICRO_CLK_net_0(1);
MICRO_CLK <= MICRO_CLK_net_1;
----------------------------------------------------------------------
-- Slices assignments
----------------------------------------------------------------------
LED2_1(25) <= m_time_net_0(25);
MICRO_CLK_net_0(1) <= m_time_net_0(1);
m_time_slice_0(0) <= m_time_net_0(0);
m_time_slice_1(10) <= m_time_net_0(10);
m_time_slice_2(11) <= m_time_net_0(11);
m_time_slice_3(12) <= m_time_net_0(12);
m_time_slice_4(13) <= m_time_net_0(13);
m_time_slice_5(14) <= m_time_net_0(14);
m_time_slice_6(15) <= m_time_net_0(15);
m_time_slice_7(16) <= m_time_net_0(16);
m_time_slice_8(17) <= m_time_net_0(17);
m_time_slice_9(18) <= m_time_net_0(18);
m_time_slice_10(19) <= m_time_net_0(19);
m_time_slice_11(20) <= m_time_net_0(20);
m_time_slice_12(21) <= m_time_net_0(21);
m_time_slice_13(22) <= m_time_net_0(22);
m_time_slice_14(23) <= m_time_net_0(23);
m_time_slice_15(24) <= m_time_net_0(24);
m_time_slice_16(2) <= m_time_net_0(2);
m_time_slice_17(3) <= m_time_net_0(3);
m_time_slice_18(4) <= m_time_net_0(4);
m_time_slice_19(5) <= m_time_net_0(5);
m_time_slice_20(6) <= m_time_net_0(6);
m_time_slice_21(7) <= m_time_net_0(7);
m_time_slice_22(8) <= m_time_net_0(8);
m_time_slice_23(9) <= m_time_net_0(9);
----------------------------------------------------------------------
-- Component instances
----------------------------------------------------------------------
-- CLKINT_0
CLKINT_0 : CLKINT
port map(
-- Inputs
A => CLK,
-- Outputs
Y => CLKINT_0_Y
);
-- CLKINT_1
CLKINT_1 : CLKINT
port map(
-- Inputs
A => PWRONRESET,
-- Outputs
Y => CLKINT_1_Y
);
-- CUTTER_PWM_inst_0
CUTTER_PWM_inst_0 : CUTTER_PWM
port map(
-- Inputs
mclk => CLKINT_0_Y,
reset => OR2_0_Y,
ena => LED2_net_0,
duty_wrt => VCC_net,
duty => WOLF_CONTROLLER_cutter_pwm_duty,
-- Outputs
pwm_out => CUTTER_net_0
);
-- FPGA_UART - Actel:DirectCore:COREUART:5.6.102
FPGA_UART : CU_TOP_FPGA_UART_COREUART
generic map(
BAUD_VAL_FRCTN_EN => ( 1 ),
FAMILY => ( 15 ),
RX_FIFO => ( 0 ),
RX_LEGACY_MODE => ( 0 ),
TX_FIFO => ( 0 )
)
port map(
-- Inputs
BIT8 => VCC_net,
CLK => CLKINT_0_Y,
CSN => GND_net,
ODD_N_EVEN => VCC_net,
OEN => LED1_3,
PARITY_EN => GND_net,
RESET_N => RESET_N_IN_POST_INV0_0,
RX => FPGA_UART_RX,
WEN => LED1_2,
BAUD_VAL => WOLF_CONTROLLER_uart_baud_val,
DATA_IN => WOLF_CONTROLLER_uart_data_out,
BAUD_VAL_FRACTION => WOLF_CONTROLLER_uart_baud_val_frac,
-- Outputs
OVERFLOW => OPEN,
PARITY_ERR => OPEN,
RXRDY => LED1_0,
TX => FPGA_UART_TX_net_0,
TXRDY => FPGA_UART_TXRDY,
FRAMING_ERR => OPEN,
DATA_OUT => FPGA_UART_DATA_OUT
);
-- OR2_0
OR2_0 : OR2
port map(
-- Inputs
A => CLKINT_1_Y,
B => LED1_net_0,
-- Outputs
Y => OR2_0_Y
);
-- system_clock_inst_0
system_clock_inst_0 : system_clock
port map(
-- Inputs
mclk => CLKINT_0_Y,
reset => OR2_0_Y,
-- Outputs
m_time => m_time_net_0
);
-- UART_reset_monitor_inst_0
UART_reset_monitor_inst_0 : UART_reset_monitor
port map(
-- Inputs
mclk => CLKINT_0_Y,
reset_in => CLKINT_1_Y,
txrdy => FPGA_UART_TXRDY,
data_in => FPGA_UART_DATA_OUT,
-- Outputs
reset_out => LED1_net_0
);
-- WOLF_CONTROLLER_inst_0
WOLF_CONTROLLER_inst_0 : WOLF_CONTROLLER
port map(
-- Inputs
mclk => CLKINT_0_Y,
clk_1hz => LED2_1(25),
reset => OR2_0_Y,
uart_txrdy => FPGA_UART_TXRDY,
uart_rxrdy => LED1_0,
uart_data_in => FPGA_UART_DATA_OUT,
-- Outputs
cutter_en => LED2_net_0,
uart_wen => LED1_2,
uart_oen => LED1_3,
led1 => OPEN,
led2 => OPEN,
cutter_pwm_duty => WOLF_CONTROLLER_cutter_pwm_duty,
uart_data_out => WOLF_CONTROLLER_uart_data_out,
uart_baud_val => WOLF_CONTROLLER_uart_baud_val,
uart_baud_val_frac => WOLF_CONTROLLER_uart_baud_val_frac
);
end RTL;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY n_adder IS
GENERIC (n : integer := 16);
PORT (
A,B : IN std_logic_vector(n-1 downto 0);
CIN : IN std_logic;
F : OUT std_logic_vector(n-1 downto 0);
COUT: OUT std_logic
);
END n_adder;
ARCHITECTURE nAdder OF n_adder IS
COMPONENT adder IS
PORT(
a,b,cin : IN std_logic;
f,cout : OUT std_logic
);
END COMPONENT;
SIGNAL temp : std_logic_vector(n downto 0);
BEGIN
temp(0)<=CIN;
loop1: FOR i IN 0 TO n-1 GENERATE
fx: adder PORT MAP(A(i),B(i),temp(i),F(i),temp(i+1));
END GENERATE;
COUT<=temp(n);
END nAdder;
|
-- Copyright (c) 2009 <NAME> (<EMAIL>)
-- See license.txt for license
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
use work.YaGraphConPackage.all;
entity GraphicsAccelerator is
generic(
ADDRESS_WIDTH: natural;
BIT_DEPTH: natural;
PITCH_WIDTH: natural
);
port(
clock: in std_logic;
reset:in std_logic;
-- register interface
srcStart: in unsigned(ADDRESS_WIDTH-1 downto 0);
srcPitch: in unsigned(PITCH_WIDTH-1 downto 0);
dstStart: in unsigned(ADDRESS_WIDTH-1 downto 0);
dstPitch: in unsigned(PITCH_WIDTH-1 downto 0);
color: in unsigned(BIT_DEPTH-1 downto 0);
srcX0: in unsigned(15 downto 0);
srcY0: in unsigned(15 downto 0);
srcX1: in unsigned(15 downto 0);
dstX0: in unsigned(15 downto 0);
dstY0: in unsigned(15 downto 0);
dstX1: in unsigned(15 downto 0);
dstY1: in unsigned(15 downto 0);
blitTransparent: in std_logic;
command: in unsigned(7 downto 0);
-- operation interface
start: in std_logic;
busy: out std_logic;
-- framebuffer interface
readAddress: out unsigned(ADDRESS_WIDTH-1 downto 0);
writeAddress: out unsigned(ADDRESS_WIDTH-1 downto 0);
data: out unsigned(BIT_DEPTH-1 downto 0);
q: in unsigned(BIT_DEPTH-1 downto 0);
writeEnable: out std_logic
);
end entity GraphicsAccelerator;
architecture rtl of GraphicsAccelerator is
-- statemachine
type stateType is (
WAIT_FOR_START,
PIXEL,
LINE_INIT,
HORIZONTAL_LINE,
VERTICAL_LINE,
RECT,
BLIT_DELAY1,
BLIT_DELAY2,
BLIT
);
signal state: stateType := WAIT_FOR_START;
signal x: unsigned(15 downto 0);
signal y: unsigned(15 downto 0);
signal x2: unsigned(15 downto 0);
signal y2: unsigned(15 downto 0);
signal dx: unsigned(15 downto 0);
signal dy: unsigned(15 downto 0);
signal incx: std_logic;
signal incy: std_logic;
signal balance: signed(15 downto 0);
begin
process(clock)
variable dx2: unsigned(dx'high downto 0);
variable dy2: unsigned(dy'high downto 0);
procedure setPixel(x: unsigned(15 downto 0); y: unsigned(15 downto 0); clr: unsigned(BIT_DEPTH-1 downto 0)) is
begin
writeAddress <= adjustLength(dstStart + dstPitch * y + x, writeAddress'length);
writeEnable <= '1';
data <= clr;
end;
procedure nextBlitRead is
begin
readAddress <= adjustLength(srcStart + srcPitch * y2 + x2, readAddress'length);
if x2 < srcX1 then
x2 <= x2 + 1;
else
x2 <= srcX0;
y2 <= y2 + 1;
end if;
end;
procedure doIncx is
begin
if incx = '1' then
x <= x + 1;
else
x <= x - 1;
end if;
end;
procedure doIncy is
begin
if incy = '1' then
y <= y + 1;
else
y <= y - 1;
end if;
end;
begin
if rising_edge(clock) then
if reset = '1' then
state <= WAIT_FOR_START;
busy <= '0';
else
writeEnable <= '0';
case state is
when WAIT_FOR_START =>
busy <= '0';
if start = '1' then
busy <= '1';
case command is
when SET_PIXEL =>
x <= dstX0;
y <= dstY0;
state <= PIXEL;
when LINE_TO =>
if dstX1 >= dstX0 then
dx <= dstX1 - dstX0;
incx <= '1';
else
dx <= dstX0 - dstX1;
incx <= '0';
end if;
if dstY1 >= dstY0 then
dy <= dstY1 - dstY0;
incy <= '1';
else
dy <= dstY0 - dstY1;
incy <= '0';
end if;
x <= dstX0;
y <= dstY0;
x2 <= dstX1;
y2 <= dstY1;
state <= LINE_INIT;
when FILL_RECT =>
x <= dstX0;
y <= dstY0;
state <= RECT;
when BLIT_COMMAND | BLIT_TRANSPARENT =>
x <= dstX0;
y <= dstY0;
x2 <= srcX0;
y2 <= srcY0;
state <= BLIT_DELAY1;
when others => null;
end case;
end if;
when PIXEL =>
setPixel(x, y, color);
state <= WAIT_FOR_START;
when LINE_INIT =>
dx2 := dx(dx'high - 1 downto 0) & "0";
dy2 := dy(dy'high - 1 downto 0) & "0";
if dx >= dy then
balance <= to_signed(to_integer(dy2) - to_integer(dx), balance'length);
state <= HORIZONTAL_LINE;
else
balance <= to_signed(to_integer(dx2) - to_integer(dy), balance'length);
state <= VERTICAL_LINE;
end if;
dx <= dx2;
dy <= dy2;
when HORIZONTAL_LINE =>
if x /= x2 then
setPixel(x, y, color);
if balance >= 0 then
doIncy;
balance <= balance - to_integer(dx) + to_integer(dy);
else
balance <= balance + to_integer(dy);
end if;
doIncx;
else
setPixel(x, y, color);
state <= WAIT_FOR_START;
end if;
when VERTICAL_LINE =>
if y /= y2 then
setPixel(x, y, color);
if balance >= 0 then
doIncx;
balance <= balance - to_integer(dy) + to_integer(dx);
else
balance <= balance + to_integer(dx);
end if;
doIncy;
else
setPixel(x, y, color);
state <= WAIT_FOR_START;
end if;
when RECT =>
setPixel(x, y, color);
if x < dstX1 then
x <= x + 1;
else
x <= dstX0;
if y < dstY1 then
y <= y + 1;
else
state <= WAIT_FOR_START;
end if;
end if;
when BLIT_DELAY1 =>
nextBlitRead;
state <= BLIT_DELAY2;
when BLIT_DELAY2 =>
nextBlitRead;
state <= BLIT;
when BLIT =>
if blitTransparent = '1' then
if q /= color then
setPixel(x, y, q);
end if;
else
setPixel(x, y, q);
end if;
if x < dstX1 then
x <= x + 1;
else
x <= dstX0;
if y < dstY1 then
y <= y + 1;
else
state <= WAIT_FOR_START;
end if;
end if;
nextBlitRead;
when others =>
state <= WAIT_FOR_START;
end case;
end if;
end if;
end process;
end architecture rtl;
|
<filename>Zybo-DMA/src/bd/design_1/ip/design_1_d_axi_i2s_audio_0_0/synth/design_1_d_axi_i2s_audio_0_0.vhd
-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: digilentinc.com:user:d_axi_i2s_audio:2.0
-- IP Revision: 52
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_d_axi_i2s_audio_0_0 IS
PORT (
BCLK_O : OUT STD_LOGIC;
LRCLK_O : OUT STD_LOGIC;
MCLK_O : OUT STD_LOGIC;
SDATA_I : IN STD_LOGIC;
SDATA_O : OUT STD_LOGIC;
CLK_100MHZ_I : IN STD_LOGIC;
S_AXIS_MM2S_ACLK : IN STD_LOGIC;
S_AXIS_MM2S_ARESETN : IN STD_LOGIC;
S_AXIS_MM2S_TREADY : OUT STD_LOGIC;
S_AXIS_MM2S_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_MM2S_TKEEP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIS_MM2S_TLAST : IN STD_LOGIC;
S_AXIS_MM2S_TVALID : IN STD_LOGIC;
M_AXIS_S2MM_ACLK : IN STD_LOGIC;
M_AXIS_S2MM_ARESETN : IN STD_LOGIC;
M_AXIS_S2MM_TVALID : OUT STD_LOGIC;
M_AXIS_S2MM_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_S2MM_TKEEP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXIS_S2MM_TLAST : OUT STD_LOGIC;
M_AXIS_S2MM_TREADY : IN STD_LOGIC;
AXI_L_aclk : IN STD_LOGIC;
AXI_L_aresetn : IN STD_LOGIC;
AXI_L_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
AXI_L_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
AXI_L_awvalid : IN STD_LOGIC;
AXI_L_awready : OUT STD_LOGIC;
AXI_L_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
AXI_L_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
AXI_L_wvalid : IN STD_LOGIC;
AXI_L_wready : OUT STD_LOGIC;
AXI_L_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
AXI_L_bvalid : OUT STD_LOGIC;
AXI_L_bready : IN STD_LOGIC;
AXI_L_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
AXI_L_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
AXI_L_arvalid : IN STD_LOGIC;
AXI_L_arready : OUT STD_LOGIC;
AXI_L_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
AXI_L_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
AXI_L_rvalid : OUT STD_LOGIC;
AXI_L_rready : IN STD_LOGIC
);
END design_1_d_axi_i2s_audio_0_0;
ARCHITECTURE design_1_d_axi_i2s_audio_0_0_arch OF design_1_d_axi_i2s_audio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_d_axi_i2s_audio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT d_axi_i2s_audio_v2_0 IS
GENERIC (
C_DATA_WIDTH : INTEGER;
C_AXI_STREAM_DATA_WIDTH : INTEGER;
C_AXI_L_DATA_WIDTH : INTEGER;
C_AXI_L_ADDR_WIDTH : INTEGER
);
PORT (
BCLK_O : OUT STD_LOGIC;
BCLK_I : IN STD_LOGIC;
BCLK_T : OUT STD_LOGIC;
LRCLK_O : OUT STD_LOGIC;
LRCLK_I : IN STD_LOGIC;
LRCLK_T : OUT STD_LOGIC;
MCLK_O : OUT STD_LOGIC;
SDATA_I : IN STD_LOGIC;
SDATA_O : OUT STD_LOGIC;
CLK_100MHZ_I : IN STD_LOGIC;
S_AXIS_MM2S_ACLK : IN STD_LOGIC;
S_AXIS_MM2S_ARESETN : IN STD_LOGIC;
S_AXIS_MM2S_TREADY : OUT STD_LOGIC;
S_AXIS_MM2S_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_MM2S_TKEEP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXIS_MM2S_TLAST : IN STD_LOGIC;
S_AXIS_MM2S_TVALID : IN STD_LOGIC;
M_AXIS_S2MM_ACLK : IN STD_LOGIC;
M_AXIS_S2MM_ARESETN : IN STD_LOGIC;
M_AXIS_S2MM_TVALID : OUT STD_LOGIC;
M_AXIS_S2MM_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_S2MM_TKEEP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXIS_S2MM_TLAST : OUT STD_LOGIC;
M_AXIS_S2MM_TREADY : IN STD_LOGIC;
AXI_L_aclk : IN STD_LOGIC;
AXI_L_aresetn : IN STD_LOGIC;
AXI_L_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
AXI_L_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
AXI_L_awvalid : IN STD_LOGIC;
AXI_L_awready : OUT STD_LOGIC;
AXI_L_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
AXI_L_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
AXI_L_wvalid : IN STD_LOGIC;
AXI_L_wready : OUT STD_LOGIC;
AXI_L_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
AXI_L_bvalid : OUT STD_LOGIC;
AXI_L_bready : IN STD_LOGIC;
AXI_L_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
AXI_L_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
AXI_L_arvalid : IN STD_LOGIC;
AXI_L_arready : OUT STD_LOGIC;
AXI_L_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
AXI_L_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
AXI_L_rvalid : OUT STD_LOGIC;
AXI_L_rready : IN STD_LOGIC
);
END COMPONENT d_axi_i2s_audio_v2_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_d_axi_i2s_audio_0_0_arch: ARCHITECTURE IS "d_axi_i2s_audio_v2_0,Vivado 2017.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_d_axi_i2s_audio_0_0_arch : ARCHITECTURE IS "design_1_d_axi_i2s_audio_0_0,d_axi_i2s_audio_v2_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_MM2S_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_MM2S_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_MM2S_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_MM2S_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_MM2S_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_MM2S_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_MM2S_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXIS_MM2S_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_S2MM_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_S2MM_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_S2MM_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_S2MM_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_S2MM_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_S2MM_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_S2MM_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXIS_S2MM_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 AXI_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 AXI_L_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_L_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L WDATA";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L WVALID";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L WREADY";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L BRESP";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L BVALID";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L BREADY";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L RDATA";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L RRESP";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L RVALID";
ATTRIBUTE X_INTERFACE_INFO OF AXI_L_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_L RREADY";
BEGIN
U0 : d_axi_i2s_audio_v2_0
GENERIC MAP (
C_DATA_WIDTH => 24,
C_AXI_STREAM_DATA_WIDTH => 32,
C_AXI_L_DATA_WIDTH => 32,
C_AXI_L_ADDR_WIDTH => 6
)
PORT MAP (
BCLK_O => BCLK_O,
BCLK_I => '0',
LRCLK_O => LRCLK_O,
LRCLK_I => '0',
MCLK_O => MCLK_O,
SDATA_I => SDATA_I,
SDATA_O => SDATA_O,
CLK_100MHZ_I => CLK_100MHZ_I,
S_AXIS_MM2S_ACLK => S_AXIS_MM2S_ACLK,
S_AXIS_MM2S_ARESETN => S_AXIS_MM2S_ARESETN,
S_AXIS_MM2S_TREADY => S_AXIS_MM2S_TREADY,
S_AXIS_MM2S_TDATA => S_AXIS_MM2S_TDATA,
S_AXIS_MM2S_TKEEP => S_AXIS_MM2S_TKEEP,
S_AXIS_MM2S_TLAST => S_AXIS_MM2S_TLAST,
S_AXIS_MM2S_TVALID => S_AXIS_MM2S_TVALID,
M_AXIS_S2MM_ACLK => M_AXIS_S2MM_ACLK,
M_AXIS_S2MM_ARESETN => M_AXIS_S2MM_ARESETN,
M_AXIS_S2MM_TVALID => M_AXIS_S2MM_TVALID,
M_AXIS_S2MM_TDATA => M_AXIS_S2MM_TDATA,
M_AXIS_S2MM_TKEEP => M_AXIS_S2MM_TKEEP,
M_AXIS_S2MM_TLAST => M_AXIS_S2MM_TLAST,
M_AXIS_S2MM_TREADY => M_AXIS_S2MM_TREADY,
AXI_L_aclk => AXI_L_aclk,
AXI_L_aresetn => AXI_L_aresetn,
AXI_L_awaddr => AXI_L_awaddr,
AXI_L_awprot => AXI_L_awprot,
AXI_L_awvalid => AXI_L_awvalid,
AXI_L_awready => AXI_L_awready,
AXI_L_wdata => AXI_L_wdata,
AXI_L_wstrb => AXI_L_wstrb,
AXI_L_wvalid => AXI_L_wvalid,
AXI_L_wready => AXI_L_wready,
AXI_L_bresp => AXI_L_bresp,
AXI_L_bvalid => AXI_L_bvalid,
AXI_L_bready => AXI_L_bready,
AXI_L_araddr => AXI_L_araddr,
AXI_L_arprot => AXI_L_arprot,
AXI_L_arvalid => AXI_L_arvalid,
AXI_L_arready => AXI_L_arready,
AXI_L_rdata => AXI_L_rdata,
AXI_L_rresp => AXI_L_rresp,
AXI_L_rvalid => AXI_L_rvalid,
AXI_L_rready => AXI_L_rready
);
END design_1_d_axi_i2s_audio_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity stopwatch is
port (
clk10hz : in std_logic;
paused : in std_logic;
clr : in std_logic;
d : out std_logic_vector(15 downto 0)
);
end stopwatch;
architecture stopwatch_impl of stopwatch is
signal dseconds: std_logic_vector(3 downto 0);
signal seconds_0: std_logic_vector(3 downto 0);
signal seconds_1: std_logic_vector(3 downto 0);
signal minutes_0: std_logic_vector(3 downto 0);
begin
d(3 downto 0) <= dseconds;
d(7 downto 4) <= seconds_0;
d(11 downto 8) <= seconds_1;
d(15 downto 12) <= minutes_0;
process(clk10hz) is
begin
if (rising_edge(clk10hz)) then
if (clr = '1') then
dseconds <= "0000";
seconds_0 <= "0000";
seconds_1 <= "0000";
minutes_0 <= "0000";
end if;
if (paused = '0') then
dseconds <= dseconds + "1";
if (dseconds >= std_logic_vector(to_unsigned(9, dseconds'length)) ) then
dseconds <= "0000";
seconds_0 <= seconds_0 + "1";
if (seconds_0 >= std_logic_vector(to_unsigned(9, seconds_0'length)) ) then
seconds_0 <= "0000";
seconds_1 <= seconds_1 + "1";
if (seconds_1 >= std_logic_vector(to_unsigned(5, seconds_1'length))) then
seconds_1 <= "0000";
minutes_0 <= minutes_0 + "1";
if (minutes_0 >= std_logic_vector(to_unsigned(9, minutes_0'length)) ) then
minutes_0 <= "0000";
end if;
end if;
end if;
end if;
end if;
end if;
end process;
end;
|
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<KEY>
`protect end_protected
|
-- #################################################################################################
-- # << NEO430 - Instruction memory ("IMEM") for Lattice ice40 UltraPlus >> #
-- # ********************************************************************************************* #
-- # This memory includes the in-place executable image of the application. See the #
-- # processor's documentary to get more information. #
-- # Note: IMEM is split up into two 8-bit memories - some EDA tools have problems to synthesize #
-- # a pre-initialized 16-bit memory with byte-enable signals. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, <NAME>. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
use neo430.neo430_application_image.all; -- this file is generated by the image generator
library iCE40UP;
use iCE40UP.components.all;
entity neo430_imem is
generic (
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes
IMEM_AS_ROM : boolean := false; -- implement IMEM as read-only memory?
BOOTLD_USE : boolean := true -- implement and use bootloader?
);
port (
clk_i : in std_ulogic; -- global clock line
rden_i : in std_ulogic; -- read enable
wren_i : in std_ulogic_vector(01 downto 0); -- write enable
upen_i : in std_ulogic; -- update enable
addr_i : in std_ulogic_vector(15 downto 0); -- address
data_i : in std_ulogic_vector(15 downto 0); -- data in
data_o : out std_ulogic_vector(15 downto 0) -- data out
);
end neo430_imem;
architecture neo430_imem_rtl of neo430_imem is
-- advanced configuration ------------------------------------------------------------------------------------
constant spram_sleep_mode_en_c : boolean := false; -- put IMEM into sleep mode when idle (for low power)
-- -------------------------------------------------------------------------------------------------------
-- ROM types --
type imem_file8_t is array (0 to IMEM_SIZE/2-1) of std_ulogic_vector(07 downto 0);
-- init function and split 1x16-bit memory into 2x8-bit memories --
impure function init_imem(hilo : std_ulogic; init : application_init_image_t) return imem_file8_t is
variable mem_v : imem_file8_t;
begin
for i in 0 to IMEM_SIZE/2-1 loop
if (hilo = '0') then -- low byte
mem_v(i) := init(i)(07 downto 00);
else -- high byte
mem_v(i) := init(i)(15 downto 08);
end if;
end loop; -- i
return mem_v;
end function init_imem;
-- local signals --
signal acc_en : std_ulogic;
signal mem_cs : std_ulogic;
signal rdata : std_ulogic_vector(15 downto 0);
signal rden : std_ulogic;
signal mem_sel : std_ulogic;
signal addr : integer;
-- internal "RAM" type - implemented if bootloader is used and IMEM is RAM and initialized with app code --
signal imem_file_init_ram_l : imem_file8_t := init_imem('0', application_init_image);
signal imem_file_init_ram_h : imem_file8_t := init_imem('1', application_init_image);
-- internal "ROM" type - implemented if bootloader is NOT used; always initialize with app code --
constant imem_file_rom_l : imem_file8_t := init_imem('0', application_init_image);
constant imem_file_rom_h : imem_file8_t := init_imem('1', application_init_image);
-- internal "RAM" type - implemented if bootloader is used and IMEM is RAM --
signal imem_file_ram_l : imem_file8_t;
signal imem_file_ram_h : imem_file8_t;
-- RAM attribute to inhibit bypass-logic - Intel only! --
attribute ramstyle : string;
attribute ramstyle of imem_file_init_ram_l : signal is "no_rw_check";
attribute ramstyle of imem_file_init_ram_h : signal is "no_rw_check";
attribute ramstyle of imem_file_ram_l : signal is "no_rw_check";
attribute ramstyle of imem_file_ram_h : signal is "no_rw_check";
-- RAM attribute to inhibit bypass-logic - Lattice only! --
attribute syn_ramstyle : string;
attribute syn_ramstyle of imem_file_init_ram_l : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_init_ram_h : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_ram_l : signal is "no_rw_check";
attribute syn_ramstyle of imem_file_ram_h : signal is "no_rw_check";
-- SPRAM signals --
signal spram_clk : std_logic;
signal spram_addr : std_logic_vector(13 downto 0);
signal spram_di : std_logic_vector(15 downto 0);
signal spram_do_lo : std_logic_vector(15 downto 0);
signal spram_do_hi : std_logic_vector(15 downto 0);
signal spram_be : std_logic_vector(03 downto 0);
signal spram_we : std_logic;
signal spram_pwr_n : std_logic;
signal spram_cs : std_logic_vector(01 downto 0);
begin
-- Access Control -----------------------------------------------------------
-- -----------------------------------------------------------------------------
acc_en <= '1' when (addr_i >= imem_base_c) and (addr_i < std_ulogic_vector(unsigned(imem_base_c) + IMEM_SIZE)) else '0';
addr <= to_integer(unsigned(addr_i(index_size_f(IMEM_SIZE/2) downto 1))); -- word aligned
mem_cs <= acc_en and (rden_i or wren_i(1) or wren_i(0));
-- Memory Access ------------------------------------------------------------
-- -----------------------------------------------------------------------------
imem_spram_lo_inst : SP256K
port map (
AD => spram_addr, -- I
DI => spram_di, -- I
MASKWE => spram_be, -- I
WE => spram_we, -- I
CS => spram_cs(0), -- I
CK => spram_clk, -- I
STDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
PWROFF_N => '1', -- I
DO => spram_do_lo -- O
);
-- instantiate second SPRAM if IMEM size > 32kB --
imem_spram_hi_bank:
if (IMEM_SIZE > 32*1024) generate
imem_spram_hi_inst : SP256K
port map (
AD => spram_addr, -- I
DI => spram_di, -- I
MASKWE => spram_be, -- I
WE => spram_we, -- I
CS => spram_cs(1), -- I
CK => spram_clk, -- I
STDBY => '0', -- I
SLEEP => spram_pwr_n, -- I
PWROFF_N => '1', -- I
DO => spram_do_hi -- O
);
end generate;
-- access logic and signal type conversion --
spram_clk <= std_logic(clk_i);
spram_addr <= std_logic_vector(addr_i(13+1 downto 0+1));
spram_di <= std_logic_vector(data_i(15 downto 0));
spram_we <= '1' when ((acc_en and upen_i and (wren_i(0) or wren_i(1))) = '1') else '0'; -- global write enable
rdata <= std_ulogic_vector(spram_do_lo) when (mem_sel = '0') else std_ulogic_vector(spram_do_hi); -- lo/hi memory bank
spram_cs(0) <= '1' when (addr_i(15) = '0') else '0'; -- low memory bank
spram_cs(1) <= '1' when (addr_i(15) = '1') else '0'; -- high memory bank
spram_be(1 downto 0) <= "11" when (wren_i(0) = '1') else "00"; -- low byte write enable
spram_be(3 downto 2) <= "11" when (wren_i(1) = '1') else "00"; -- high byte write enable
spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected
buffer_ff: process(clk_i)
begin
-- sanity check --
if (IMEM_AS_ROM = true) or (BOOTLD_USE = false) then
assert false report "ICE40 Ultra Plus SPRAM cannot be initialized by bitstream!" severity error;
end if;
if (IMEM_SIZE > 48*1024) then
assert false report "I-mem size out of range! Max 48kB!" severity error;
end if;
-- buffer --
if rising_edge(clk_i) then
mem_sel <= addr_i(15);
rden <= rden_i and acc_en;
end if;
end process buffer_ff;
-- output gate --
data_o <= rdata when (rden = '1') else (others => '0');
end neo430_imem_rtl;
|
<reponame>hane1818/VLSI-Design_HW3_FSM_RAM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.CONV_INTEGER;
entity RAM is
port(
clk, W_En: in std_logic;
W_Addr, R_Addr: in std_logic_vector(2 downto 0);
Data_Input: in std_logic_vector(7 downto 0);
Data_Output: out std_logic_vector(7 downto 0));
end RAM;
architecture MEMORY of RAM is
type storage is array(7 downto 0) of std_logic_vector(7 downto 0);
signal Reg : storage;
begin
process(clk)
begin
Data_Output <= Reg(conv_integer(R_Addr));
if(W_En='1'and (clk'EVENT and clk='1')) then
Reg(conv_integer(W_Addr)) <= Data_Input;
end if;
end process;
end MEMORY;
|
<gh_stars>1-10
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity matrixmul is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
a_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
a_ce0 : OUT STD_LOGIC;
a_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
b_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
b_ce0 : OUT STD_LOGIC;
b_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
res_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
res_ce0 : OUT STD_LOGIC;
res_we0 : OUT STD_LOGIC;
res_d0 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of matrixmul is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"matrixmul,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=8.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.380000,HLS_SYN_LAT=106,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=1,HLS_SYN_FF=61,HLS_SYN_LUT=168}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal i_1_fu_127_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal i_1_reg_252 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal tmp_s_fu_149_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_s_reg_257 : STD_LOGIC_VECTOR (4 downto 0);
signal exitcond2_fu_121_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal j_1_fu_161_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal j_1_reg_266 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal tmp_2_cast_fu_167_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_2_cast_reg_271 : STD_LOGIC_VECTOR (4 downto 0);
signal exitcond1_fu_155_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal res_addr_reg_276 : STD_LOGIC_VECTOR (3 downto 0);
signal k_1_fu_187_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal k_1_reg_284 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal exitcond_fu_181_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal a_load_reg_299 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal b_load_reg_304 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_241_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal i_reg_75 : STD_LOGIC_VECTOR (1 downto 0);
signal j_reg_86 : STD_LOGIC_VECTOR (1 downto 0);
signal res_load_reg_97 : STD_LOGIC_VECTOR (15 downto 0);
signal k_reg_110 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_11_cast_fu_176_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_12_cast_fu_202_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_15_cast_fu_230_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_9_fu_137_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal p_shl_cast_fu_145_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_cast_fu_133_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_2_fu_171_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_4_cast_fu_193_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_4_fu_197_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_10_fu_207_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal p_shl1_cast_fu_215_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_11_fu_219_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_12_fu_225_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
component matrixmul_mac_mulbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
din2 : IN STD_LOGIC_VECTOR (15 downto 0);
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
matrixmul_mac_mulbkb_U1 : component matrixmul_mac_mulbkb
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
din0 => b_load_reg_304,
din1 => a_load_reg_299,
din2 => res_load_reg_97,
dout => grp_fu_241_p3);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
i_reg_75_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond1_fu_155_p2 = ap_const_lv1_1))) then
i_reg_75 <= i_1_reg_252;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_75 <= ap_const_lv2_0;
end if;
end if;
end process;
j_reg_86_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (exitcond_fu_181_p2 = ap_const_lv1_1))) then
j_reg_86 <= j_1_reg_266;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond2_fu_121_p2 = ap_const_lv1_0))) then
j_reg_86 <= ap_const_lv2_0;
end if;
end if;
end process;
k_reg_110_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
k_reg_110 <= k_1_reg_284;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_0 = exitcond1_fu_155_p2))) then
k_reg_110 <= ap_const_lv2_0;
end if;
end if;
end process;
res_load_reg_97_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
res_load_reg_97 <= grp_fu_241_p3;
elsif (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_0 = exitcond1_fu_155_p2))) then
res_load_reg_97 <= ap_const_lv16_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
a_load_reg_299 <= a_q0;
b_load_reg_304 <= b_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_1_reg_252 <= i_1_fu_127_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
j_1_reg_266 <= j_1_fu_161_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
k_1_reg_284 <= k_1_fu_187_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_0 = exitcond1_fu_155_p2))) then
res_addr_reg_276 <= tmp_11_cast_fu_176_p1(4 - 1 downto 0);
tmp_2_cast_reg_271(1 downto 0) <= tmp_2_cast_fu_167_p1(1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond2_fu_121_p2 = ap_const_lv1_0))) then
tmp_s_reg_257 <= tmp_s_fu_149_p2;
end if;
end if;
end process;
tmp_2_cast_reg_271(4 downto 2) <= "000";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, exitcond2_fu_121_p2, ap_CS_fsm_state3, exitcond1_fu_155_p2, ap_CS_fsm_state4, exitcond_fu_181_p2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond2_fu_121_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (exitcond1_fu_155_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
if (((ap_const_logic_1 = ap_CS_fsm_state4) and (exitcond_fu_181_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state5;
end if;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state4;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
a_address0 <= tmp_12_cast_fu_202_p1(4 - 1 downto 0);
a_ce0_assign_proc : process(ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
a_ce0 <= ap_const_logic_1;
else
a_ce0 <= ap_const_logic_0;
end if;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_done_assign_proc : process(ap_CS_fsm_state2, exitcond2_fu_121_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond2_fu_121_p2 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, exitcond2_fu_121_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (exitcond2_fu_121_p2 = ap_const_lv1_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
b_address0 <= tmp_15_cast_fu_230_p1(4 - 1 downto 0);
b_ce0_assign_proc : process(ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
b_ce0 <= ap_const_logic_1;
else
b_ce0 <= ap_const_logic_0;
end if;
end process;
exitcond1_fu_155_p2 <= "1" when (j_reg_86 = ap_const_lv2_3) else "0";
exitcond2_fu_121_p2 <= "1" when (i_reg_75 = ap_const_lv2_3) else "0";
exitcond_fu_181_p2 <= "1" when (k_reg_110 = ap_const_lv2_3) else "0";
i_1_fu_127_p2 <= std_logic_vector(unsigned(i_reg_75) + unsigned(ap_const_lv2_1));
j_1_fu_161_p2 <= std_logic_vector(unsigned(j_reg_86) + unsigned(ap_const_lv2_1));
k_1_fu_187_p2 <= std_logic_vector(unsigned(k_reg_110) + unsigned(ap_const_lv2_1));
p_shl1_cast_fu_215_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_fu_207_p3),5));
p_shl_cast_fu_145_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_fu_137_p3),5));
res_address0 <= res_addr_reg_276;
res_ce0_assign_proc : process(ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
res_ce0 <= ap_const_logic_1;
else
res_ce0 <= ap_const_logic_0;
end if;
end process;
res_d0 <= res_load_reg_97;
res_we0_assign_proc : process(ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
res_we0 <= ap_const_logic_1;
else
res_we0 <= ap_const_logic_0;
end if;
end process;
tmp_10_fu_207_p3 <= (k_reg_110 & ap_const_lv2_0);
tmp_11_cast_fu_176_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_2_fu_171_p2),64));
tmp_11_fu_219_p2 <= std_logic_vector(unsigned(p_shl1_cast_fu_215_p1) - unsigned(tmp_4_cast_fu_193_p1));
tmp_12_cast_fu_202_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_4_fu_197_p2),64));
tmp_12_fu_225_p2 <= std_logic_vector(unsigned(tmp_11_fu_219_p2) + unsigned(tmp_2_cast_reg_271));
tmp_15_cast_fu_230_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_12_fu_225_p2),64));
tmp_2_cast_fu_167_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_reg_86),5));
tmp_2_fu_171_p2 <= std_logic_vector(unsigned(tmp_s_reg_257) + unsigned(tmp_2_cast_fu_167_p1));
tmp_4_cast_fu_193_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(k_reg_110),5));
tmp_4_fu_197_p2 <= std_logic_vector(unsigned(tmp_s_reg_257) + unsigned(tmp_4_cast_fu_193_p1));
tmp_9_fu_137_p3 <= (i_reg_75 & ap_const_lv2_0);
tmp_cast_fu_133_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_reg_75),5));
tmp_s_fu_149_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_145_p1) - unsigned(tmp_cast_fu_133_p1));
end behav;
|
<reponame>bonfireprocessor/bonfire-basic-soc<filename>ulx3s/soc_ulx3s_top_TB.vhd<gh_stars>1-10
library ecp5u;
use ecp5u.components.all;
library ieee;
use ieee.std_logic_1164.all;
library vital2000;
use vital2000.VITAL_Timing.all;
-- Add your library and packages declaration here ...
entity soc_ulx3s_top_tb is
end soc_ulx3s_top_tb;
architecture TB_ARCHITECTURE of soc_ulx3s_top_tb is
-- Component declaration of the tested unit
port(
sysclk : in STD_LOGIC;
resetn : in STD_LOGIC;
uart0_txd : out STD_LOGIC;
uart0_rxd : in STD_LOGIC;
led : out STD_LOGIC_VECTOR(7 downto 0) );
end component;
constant ClockPeriod : time := ( 1000.0 / real(25) ) * 1 ns;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal sysclk : STD_LOGIC := '0';
signal resetn : STD_LOGIC;
signal uart0_rxd : STD_LOGIC := '1';
-- Observed signals - signals mapped to the output ports of tested entity
signal uart0_txd : STD_LOGIC;
signal led : STD_LOGIC_VECTOR(7 downto 0);
-- Add your code here ...
begin
-- Unit Under Test port map
UUT : soc_ulx3s_top
port map (
sysclk => sysclk,
resetn => resetn,
uart0_txd => uart0_txd,
uart0_rxd => uart0_rxd,
led => led
);
-- Add your stimulus here ...
sysclk <= not sysclk after ClockPeriod / 2;
stimuli : process
begin
wait for ClockPeriod;
resetn <= '0';
wait for ClockPeriod * 3;
resetn <= '1';
--print("Start simulation");
-- wait until uart0_stop;
-- print("");
-- print("UART0 Test captured bytes: " & str(total_count(0)) & " framing errors: " & str(framing_errors(0)));
--
-- TbSimEnded <= '1';
wait;
end process;
end TB_ARCHITECTURE;
--configuration TESTBENCH_FOR_soc_ulx3s_top of soc_ulx3s_top_tb is
-- for TB_ARCHITECTURE
-- for UUT : soc_ulx3s_top
-- use entity work.soc_ulx3s_top(structure);
-- end for;
-- end for;
--end TESTBENCH_FOR_soc_ulx3s_top;
--
|
<reponame>AlbertoTrapiello/Trabajo-VHDL-
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.12.2018 17:30:40
-- Design Name:
-- Module Name: Sicronizador - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Sicronizador is
Port ( sync_in : in STD_LOGIC;
clk : in STD_LOGIC;
sync_out : out STD_LOGIC);
end Sicronizador;
architecture Behavioral of Sincronizador is
constant SYNC_STAGES : integer := 3;
constant PIPELINE_STAGES : integer := 1;
constant INIT : std_logic := '0';
signal sreg : std_logic_vector(SYNC_STAGES-1 downto 0) := (others => INIT);
attribute async_reg : string;
attribute async_reg of sreg : signal is "true";
signal sreg_pipe : std_logic_vector(PIPELINE_STAGES-1 downto 0) := (others => INIT);
attribute shreg_extract : string;
attribute shreg_extract of sreg_pipe : signal is "false";
begin
process(clk)
begin
if(clk'event and clk='1')then
sreg <= sreg(SYNC_STAGES-2 downto 0) & sync_in;
end if;
end process;
no_pipeline : if PIPELINE_STAGES = 0 generate
begin
sync_out <= sreg(SYNC_STAGES-1);
end generate;
one_pipeline : if PIPELINE_STAGES = 1 generate
begin
process(clk)
begin
if(clk'event and clk='1') then
sync_out <= sreg(SYNC_STAGES-1);
end if;
end process;
end generate;
multiple_pipeline : if PIPELINE_STAGES > 1 generate
begin
process(clk)
begin
if(clk'event and clk='1') then
sreg_pipe <= sreg_pipe(PIPELINE_STAGES-2 downto 0) & sreg(SYNC_STAGES-1);
end if;
end process;
sync_out <= sreg_pipe(PIPELINE_STAGES-1);
end generate;
end Behavioral;
|
<filename>float_type_definitions/float_word_length_18_bit_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- configure word lengths to 8 bit exponent with 18 bit mantissa
package float_word_length_pkg is
constant mantissa_bits : integer := 18;
constant exponent_bits : integer := 8;
end package float_word_length_pkg;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
-- Version: 2019.2.1
-- Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity is_crop_or_furrow is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
lines_address0 : OUT STD_LOGIC_VECTOR (2 downto 0);
lines_ce0 : OUT STD_LOGIC;
lines_q0 : IN STD_LOGIC_VECTOR (64 downto 0);
px_read : IN STD_LOGIC_VECTOR (8 downto 0);
py_read : IN STD_LOGIC_VECTOR (8 downto 0);
crop_width_read : IN STD_LOGIC_VECTOR (4 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (1 downto 0) );
end;
architecture behav of is_crop_or_furrow is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv3_6 : STD_LOGIC_VECTOR (2 downto 0) := "110";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv9_181 : STD_LOGIC_VECTOR (8 downto 0) := "110000001";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv8_7F : STD_LOGIC_VECTOR (7 downto 0) := "01111111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal zext_ln177_fu_169_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_155_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_reg_510 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal zext_ln387_fu_179_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal zext_ln387_reg_515 : STD_LOGIC_VECTOR (31 downto 0);
signal zext_ln389_fu_183_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal zext_ln389_reg_521 : STD_LOGIC_VECTOR (31 downto 0);
signal icmp_ln384_fu_187_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln384_reg_529 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal i_fu_193_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal i_reg_533 : STD_LOGIC_VECTOR (2 downto 0);
signal select_ln404_fu_220_p3 : STD_LOGIC_VECTOR (1 downto 0);
signal trunc_ln385_fu_228_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal trunc_ln385_reg_548 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal grp_fu_150_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal i_0_reg_125 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal or_ln389_fu_422_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_phi_mux_UnifiedRetVal_phi_fu_139_p4 : STD_LOGIC_VECTOR (1 downto 0);
signal UnifiedRetVal_reg_136 : STD_LOGIC_VECTOR (1 downto 0);
signal zext_ln385_fu_199_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal most_right_2_fu_82 : STD_LOGIC_VECTOR (31 downto 0);
signal most_right_3_fu_456_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_first_0_load_load_fu_428_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal most_right_fu_407_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_most_left_fu_86 : STD_LOGIC_VECTOR (31 downto 0);
signal select_ln396_fu_442_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal most_left_fu_402_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal flag_first_0_fu_90 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_150_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_155_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal sext_ln377_fu_165_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal icmp_ln401_fu_204_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln401_1_fu_209_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal and_ln401_fu_214_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal m_assign_load_new6_fu_232_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_146_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_s_fu_258_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_V_24_fu_280_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal mantissa_V_fu_284_p4 : STD_LOGIC_VECTOR (24 downto 0);
signal tmp_V_fu_270_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal zext_ln339_fu_298_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal add_ln339_fu_302_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal sub_ln1311_fu_316_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal isNeg_fu_308_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal sext_ln1311_fu_322_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal ush_fu_326_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal sext_ln1311_3_fu_334_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal sext_ln1311_4_fu_338_p1 : STD_LOGIC_VECTOR (24 downto 0);
signal zext_ln682_fu_294_p1 : STD_LOGIC_VECTOR (78 downto 0);
signal zext_ln1287_fu_342_p1 : STD_LOGIC_VECTOR (78 downto 0);
signal r_V_fu_346_p2 : STD_LOGIC_VECTOR (24 downto 0);
signal tmp_51_fu_358_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_5_fu_352_p2 : STD_LOGIC_VECTOR (78 downto 0);
signal zext_ln662_fu_366_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_5_fu_370_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_32_fu_380_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Result_s_fu_262_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal result_V_3_fu_388_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_33_fu_394_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal icmp_ln389_fu_412_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln389_1_fu_417_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln396_fu_436_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp_ln397_fu_450_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_return_preg : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
signal ap_condition_138 : BOOLEAN;
component ip_accel_app_faddShg IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ip_accel_app_fmulKfY IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ip_accel_app_sitoThq IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
ip_accel_app_faddShg_U499 : component ip_accel_app_faddShg
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_150_p2,
din1 => grp_fu_155_p1,
ce => ap_const_logic_1,
dout => grp_fu_146_p2);
ip_accel_app_fmulKfY_U500 : component ip_accel_app_fmulKfY
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_150_p0,
din1 => tmp_reg_510,
ce => ap_const_logic_1,
dout => grp_fu_150_p2);
ip_accel_app_sitoThq_U501 : component ip_accel_app_sitoThq
generic map (
ID => 1,
NUM_STAGE => 2,
din0_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_155_p0,
ce => ap_const_logic_1,
dout => grp_fu_155_p1);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_return_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_return_preg <= ap_const_lv2_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state6) and ((icmp_ln384_reg_529 = ap_const_lv1_1) or ((trunc_ln385_reg_548 = ap_const_lv1_1) and (or_ln389_fu_422_p2 = ap_const_lv1_0))))) then
ap_return_preg <= ap_phi_mux_UnifiedRetVal_phi_fu_139_p4;
end if;
end if;
end if;
end process;
UnifiedRetVal_reg_136_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((trunc_ln385_reg_548 = ap_const_lv1_1) and (or_ln389_fu_422_p2 = ap_const_lv1_0) and (icmp_ln384_reg_529 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state6))) then
UnifiedRetVal_reg_136 <= ap_const_lv2_1;
elsif (((icmp_ln384_fu_187_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
UnifiedRetVal_reg_136 <= select_ln404_fu_220_p3;
end if;
end if;
end process;
flag_first_0_fu_90_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((trunc_ln385_reg_548 = ap_const_lv1_1) and (or_ln389_fu_422_p2 = ap_const_lv1_1) and (icmp_ln384_reg_529 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state6))) then
flag_first_0_fu_90 <= ap_const_lv1_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
flag_first_0_fu_90 <= ap_const_lv1_1;
end if;
end if;
end process;
i_0_reg_125_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (((trunc_ln385_reg_548 = ap_const_lv1_0) and (icmp_ln384_reg_529 = ap_const_lv1_0)) or ((or_ln389_fu_422_p2 = ap_const_lv1_1) and (icmp_ln384_reg_529 = ap_const_lv1_0))))) then
i_0_reg_125 <= i_reg_533;
elsif ((ap_const_logic_1 = ap_CS_fsm_state2)) then
i_0_reg_125 <= ap_const_lv3_0;
end if;
end if;
end process;
most_right_2_fu_82_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_138)) then
if ((flag_first_0_load_load_fu_428_p1 = ap_const_lv1_1)) then
most_right_2_fu_82 <= most_right_fu_407_p2;
elsif ((flag_first_0_load_load_fu_428_p1 = ap_const_lv1_0)) then
most_right_2_fu_82 <= most_right_3_fu_456_p3;
end if;
end if;
end if;
end process;
tmp_most_left_fu_86_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_boolean_1 = ap_condition_138)) then
if ((flag_first_0_load_load_fu_428_p1 = ap_const_lv1_1)) then
tmp_most_left_fu_86 <= most_left_fu_402_p2;
elsif ((flag_first_0_load_load_fu_428_p1 = ap_const_lv1_0)) then
tmp_most_left_fu_86 <= select_ln396_fu_442_p3;
end if;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
i_reg_533 <= i_fu_193_p2;
icmp_ln384_reg_529 <= icmp_ln384_fu_187_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
tmp_reg_510 <= grp_fu_155_p1;
zext_ln387_reg_515(4 downto 0) <= zext_ln387_fu_179_p1(4 downto 0);
zext_ln389_reg_521(8 downto 0) <= zext_ln389_fu_183_p1(8 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
trunc_ln385_reg_548 <= trunc_ln385_fu_228_p1;
end if;
end if;
end process;
zext_ln387_reg_515(31 downto 5) <= "000000000000000000000000000";
zext_ln389_reg_521(31 downto 9) <= "00000000000000000000000";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, icmp_ln384_fu_187_p2, icmp_ln384_reg_529, ap_CS_fsm_state3, trunc_ln385_fu_228_p1, trunc_ln385_reg_548, ap_CS_fsm_state4, ap_CS_fsm_state6, or_ln389_fu_422_p2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
ap_NS_fsm <= ap_ST_fsm_state3;
when ap_ST_fsm_state3 =>
if (((icmp_ln384_fu_187_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
if (((trunc_ln385_fu_228_p1 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state4))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state5;
end if;
when ap_ST_fsm_state5 =>
ap_NS_fsm <= ap_ST_fsm_state6;
when ap_ST_fsm_state6 =>
if (((ap_const_logic_1 = ap_CS_fsm_state6) and ((icmp_ln384_reg_529 = ap_const_lv1_1) or ((trunc_ln385_reg_548 = ap_const_lv1_1) and (or_ln389_fu_422_p2 = ap_const_lv1_0))))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
add_ln339_fu_302_p2 <= std_logic_vector(signed(ap_const_lv9_181) + signed(zext_ln339_fu_298_p1));
and_ln401_fu_214_p2 <= (icmp_ln401_fu_204_p2 and icmp_ln401_1_fu_209_p2);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_condition_138_assign_proc : process(icmp_ln384_reg_529, trunc_ln385_reg_548, ap_CS_fsm_state6, or_ln389_fu_422_p2)
begin
ap_condition_138 <= ((trunc_ln385_reg_548 = ap_const_lv1_1) and (or_ln389_fu_422_p2 = ap_const_lv1_1) and (icmp_ln384_reg_529 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state6));
end process;
ap_done_assign_proc : process(ap_start, ap_CS_fsm_state1, icmp_ln384_reg_529, trunc_ln385_reg_548, ap_CS_fsm_state6, or_ln389_fu_422_p2)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_state6) and ((icmp_ln384_reg_529 = ap_const_lv1_1) or ((trunc_ln385_reg_548 = ap_const_lv1_1) and (or_ln389_fu_422_p2 = ap_const_lv1_0)))) or ((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_start = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_phi_mux_UnifiedRetVal_phi_fu_139_p4_assign_proc : process(icmp_ln384_reg_529, trunc_ln385_reg_548, ap_CS_fsm_state6, or_ln389_fu_422_p2, UnifiedRetVal_reg_136)
begin
if (((trunc_ln385_reg_548 = ap_const_lv1_1) and (or_ln389_fu_422_p2 = ap_const_lv1_0) and (icmp_ln384_reg_529 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_state6))) then
ap_phi_mux_UnifiedRetVal_phi_fu_139_p4 <= ap_const_lv2_1;
else
ap_phi_mux_UnifiedRetVal_phi_fu_139_p4 <= UnifiedRetVal_reg_136;
end if;
end process;
ap_ready_assign_proc : process(icmp_ln384_reg_529, trunc_ln385_reg_548, ap_CS_fsm_state6, or_ln389_fu_422_p2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state6) and ((icmp_ln384_reg_529 = ap_const_lv1_1) or ((trunc_ln385_reg_548 = ap_const_lv1_1) and (or_ln389_fu_422_p2 = ap_const_lv1_0))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return_assign_proc : process(icmp_ln384_reg_529, trunc_ln385_reg_548, ap_CS_fsm_state6, or_ln389_fu_422_p2, ap_phi_mux_UnifiedRetVal_phi_fu_139_p4, ap_return_preg)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state6) and ((icmp_ln384_reg_529 = ap_const_lv1_1) or ((trunc_ln385_reg_548 = ap_const_lv1_1) and (or_ln389_fu_422_p2 = ap_const_lv1_0))))) then
ap_return <= ap_phi_mux_UnifiedRetVal_phi_fu_139_p4;
else
ap_return <= ap_return_preg;
end if;
end process;
flag_first_0_load_load_fu_428_p1 <= flag_first_0_fu_90;
grp_fu_150_p0 <= m_assign_load_new6_fu_232_p4;
grp_fu_155_p0_assign_proc : process(ap_CS_fsm_state1, lines_q0, zext_ln177_fu_169_p1, ap_CS_fsm_state4)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
grp_fu_155_p0 <= lines_q0(64 downto 33);
elsif ((ap_const_logic_1 = ap_CS_fsm_state1)) then
grp_fu_155_p0 <= zext_ln177_fu_169_p1;
else
grp_fu_155_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
i_fu_193_p2 <= std_logic_vector(unsigned(i_0_reg_125) + unsigned(ap_const_lv3_1));
icmp_ln384_fu_187_p2 <= "1" when (i_0_reg_125 = ap_const_lv3_6) else "0";
icmp_ln389_1_fu_417_p2 <= "1" when (signed(zext_ln389_reg_521) < signed(most_left_fu_402_p2)) else "0";
icmp_ln389_fu_412_p2 <= "1" when (signed(zext_ln389_reg_521) > signed(most_right_fu_407_p2)) else "0";
icmp_ln396_fu_436_p2 <= "1" when (signed(most_left_fu_402_p2) < signed(tmp_most_left_fu_86)) else "0";
icmp_ln397_fu_450_p2 <= "1" when (signed(most_right_fu_407_p2) > signed(most_right_2_fu_82)) else "0";
icmp_ln401_1_fu_209_p2 <= "1" when (signed(zext_ln389_reg_521) < signed(most_right_2_fu_82)) else "0";
icmp_ln401_fu_204_p2 <= "1" when (signed(zext_ln389_reg_521) > signed(tmp_most_left_fu_86)) else "0";
isNeg_fu_308_p3 <= add_ln339_fu_302_p2(8 downto 8);
lines_address0 <= zext_ln385_fu_199_p1(3 - 1 downto 0);
lines_ce0_assign_proc : process(ap_CS_fsm_state3)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
lines_ce0 <= ap_const_logic_1;
else
lines_ce0 <= ap_const_logic_0;
end if;
end process;
m_assign_load_new6_fu_232_p4 <= lines_q0(32 downto 1);
mantissa_V_fu_284_p4 <= ((ap_const_lv1_1 & tmp_V_24_fu_280_p1) & ap_const_lv1_0);
most_left_fu_402_p2 <= std_logic_vector(unsigned(p_Val2_33_fu_394_p3) - unsigned(zext_ln387_reg_515));
most_right_3_fu_456_p3 <=
most_right_fu_407_p2 when (icmp_ln397_fu_450_p2(0) = '1') else
most_right_2_fu_82;
most_right_fu_407_p2 <= std_logic_vector(unsigned(p_Val2_33_fu_394_p3) + unsigned(zext_ln387_reg_515));
or_ln389_fu_422_p2 <= (icmp_ln389_fu_412_p2 or icmp_ln389_1_fu_417_p2);
p_Result_s_fu_262_p3 <= p_Val2_s_fu_258_p1(31 downto 31);
p_Val2_32_fu_380_p3 <=
zext_ln662_fu_366_p1 when (isNeg_fu_308_p3(0) = '1') else
tmp_5_fu_370_p4;
p_Val2_33_fu_394_p3 <=
result_V_3_fu_388_p2 when (p_Result_s_fu_262_p3(0) = '1') else
p_Val2_32_fu_380_p3;
p_Val2_s_fu_258_p1 <= grp_fu_146_p2;
r_V_5_fu_352_p2 <= std_logic_vector(shift_left(unsigned(zext_ln682_fu_294_p1),to_integer(unsigned('0' & zext_ln1287_fu_342_p1(31-1 downto 0)))));
r_V_fu_346_p2 <= std_logic_vector(shift_right(unsigned(mantissa_V_fu_284_p4),to_integer(unsigned('0' & sext_ln1311_4_fu_338_p1(25-1 downto 0)))));
result_V_3_fu_388_p2 <= std_logic_vector(unsigned(ap_const_lv32_0) - unsigned(p_Val2_32_fu_380_p3));
select_ln396_fu_442_p3 <=
most_left_fu_402_p2 when (icmp_ln396_fu_436_p2(0) = '1') else
tmp_most_left_fu_86;
select_ln404_fu_220_p3 <=
ap_const_lv2_3 when (and_ln401_fu_214_p2(0) = '1') else
ap_const_lv2_0;
sext_ln1311_3_fu_334_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(ush_fu_326_p3),32));
sext_ln1311_4_fu_338_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(ush_fu_326_p3),25));
sext_ln1311_fu_322_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(sub_ln1311_fu_316_p2),9));
sext_ln377_fu_165_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(px_read),16));
sub_ln1311_fu_316_p2 <= std_logic_vector(unsigned(ap_const_lv8_7F) - unsigned(tmp_V_fu_270_p4));
tmp_51_fu_358_p3 <= r_V_fu_346_p2(24 downto 24);
tmp_5_fu_370_p4 <= r_V_5_fu_352_p2(55 downto 24);
tmp_V_24_fu_280_p1 <= p_Val2_s_fu_258_p1(23 - 1 downto 0);
tmp_V_fu_270_p4 <= p_Val2_s_fu_258_p1(30 downto 23);
trunc_ln385_fu_228_p1 <= lines_q0(1 - 1 downto 0);
ush_fu_326_p3 <=
sext_ln1311_fu_322_p1 when (isNeg_fu_308_p3(0) = '1') else
add_ln339_fu_302_p2;
zext_ln1287_fu_342_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(sext_ln1311_3_fu_334_p1),79));
zext_ln177_fu_169_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(sext_ln377_fu_165_p1),32));
zext_ln339_fu_298_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_V_fu_270_p4),9));
zext_ln385_fu_199_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_0_reg_125),64));
zext_ln387_fu_179_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(crop_width_read),32));
zext_ln389_fu_183_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(py_read),32));
zext_ln662_fu_366_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_51_fu_358_p3),32));
zext_ln682_fu_294_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(mantissa_V_fu_284_p4),79));
end behav;
|
<filename>Testbench/data_mem_tb.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.RV32I_pkg.all;
entity data_mem_tb is
end data_mem_tb;
architecture driver of data_mem_tb is
component data_mem
port ( clk : in std_logic;
reset_n : in std_logic;
address : in std_logic_vector (ADDRLEN-1 downto 0);
datain : in std_logic_vector (XLEN-1 downto 0);
ByteMask : in std_logic_vector (1 downto 0); -- "00" = byte; "01" = half-word; "10" = word
SignExt_n : in std_logic; -- '0' = sign-extend; '1' = zero-extend
MemWrite : in std_logic;
MemRead : in std_logic;
dataout : out std_logic_vector (XLEN-1 downto 0));
end component;
-- inputs
signal tb_clk : std_logic := '0';
signal tb_reset_n : std_logic := '1';
signal tb_address : std_logic_vector (ADDRLEN-1 downto 0):= (others => '0');
signal tb_datain : std_logic_vector (XLEN-1 downto 0):= (others => '0');
signal tb_ByteMask: std_logic_vector (1 downto 0):= (others => '0');
signal tb_SignExt_n : std_logic := '0';
signal tb_MemWrite : std_logic := '0';
signal tb_MemRead : std_logic := '0';
-- outputs
signal tb_dataout : std_logic_vector (XLEN-1 downto 0);
constant ClockFrequency: integer := 100e6; --100MHz
constant ClockPeriod: time := 1000ms / ClockFrequency;
begin
-- Instantiate the Unit Under Test (UUT)
UUT: data_mem port map (
clk => tb_clk,
reset_n => tb_reset_n,
address => tb_address,
datain => tb_datain,
ByteMask => tb_ByteMask,
SignExt_n => tb_SignExt_n,
MemWrite => tb_MemWrite,
MemRead => tb_MemRead,
dataout => tb_dataout );
process is
begin
wait for 20 ns;
tb_MemWrite <= '1';
tb_MemRead <= '0';
tb_ByteMask <= "10"; -- simulate SW instruction
tb_SignExt_n <= '0';
wait for 0 ns;
for i in 0 to 10 loop
tb_address <= std_logic_vector(to_unsigned((4*i)+400, tb_address'length));
tb_datain <= std_logic_vector(to_unsigned((100*i)+1000, tb_datain'length));
wait for 0 ns;
tb_clk <= '1';
wait for ClockPeriod/2;
tb_clk <= '0';
wait for ClockPeriod/2;
end loop;
wait for 20 ns;
tb_MemWrite <= '0';
tb_MemRead <= '1';
tb_ByteMask <= "00"; -- simulate LBU instruction
tb_SignExt_n <= '1';
wait for 0 ns;
for i in 0 to 40 loop
tb_address <= std_logic_vector(to_unsigned(i+400, tb_address'length));
wait for 0 ns;
tb_clk <= '1';
wait for ClockPeriod/2;
tb_clk <= '0';
wait for ClockPeriod/2;
end loop;
wait;
end process;
end architecture;
|
<filename>cdh_rev1/ztec_project.srcs/sources_1/imports/fpga/grlib-master/lib/gaisler/misc/ahbmmux.vhd<gh_stars>10-100
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, <NAME>
-- Copyright (C) 2015 - 2017, <NAME>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--------------------------------------------------------------------------------
-- Entity: ahbmmux
-- File: ahbmmux.vhd
-- Author: <NAME>
-- Contact: <EMAIL>
-- Description:
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.amba.all;
entity ahbmmux is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
mstmi : out ahb_mst_in_type;
mstmo : in ahb_mst_out_type;
ahbm0i: in ahb_mst_in_type;
ahbm0o: out ahb_mst_out_type;
ahbm1i: in ahb_mst_in_type;
ahbm1o: out ahb_mst_out_type;
force : in std_logic
);
end entity;
architecture rtl of ahbmmux is
begin
comb : process (mstmo, ahbm0i, ahbm1i, force)
variable m0o, m1o : ahb_mst_out_type;
variable mi : ahb_mst_in_type;
begin
m0o := mstmo;
m1o := mstmo;
mi := ahbm0i;
if force = '1' then
mi.hready := ahbm0i.hready;
mi.hresp := ahbm0i.hresp ;
mi.hrdata := ahbm0i.hrdata;
mi.hgrant := ahbm0i.hgrant;
m1o.hbusreq := '0';
m1o.htrans := "00";
else
mi.hready := ahbm1i.hready;
mi.hresp := ahbm1i.hresp ;
mi.hrdata := ahbm1i.hrdata;
mi.hgrant := ahbm1i.hgrant;
m0o.hbusreq := '0';
m0o.htrans := "00";
end if;
mstmi <= mi;
ahbm0o <= m0o;
ahbm1o <= m1o;
end process;
end;
|
<reponame>hubertokf/VHDL-Fast-Adders
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLGB IS
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
END CLGB;
ARCHITECTURE strc_CLGB of CLGB is
BEGIN
Cout1 <= G0 OR (P0 AND Cin);
Cout2 <= G1 OR (P1 AND G0) OR (P1 AND P0 AND Cin);
END strc_CLGB;
|
<reponame>ORKA-HPC/orka-hpc-llp<gh_stars>1-10
component top_a10_pcie is
port (
coreclkout_hip : out std_logic; -- clk
refclk : in std_logic := 'X'; -- clk
npor : in std_logic := 'X'; -- npor
pin_perst : in std_logic := 'X'; -- pin_perst
app_nreset_status : out std_logic; -- reset_n
test_in : in std_logic_vector(31 downto 0) := (others => 'X'); -- test_in
simu_mode_pipe : in std_logic := 'X'; -- simu_mode_pipe
devkit_status : out std_logic_vector(255 downto 0); -- devkit_status
devkit_ctrl : in std_logic_vector(255 downto 0) := (others => 'X'); -- devkit_ctrl
sim_pipe_pclk_in : in std_logic := 'X'; -- sim_pipe_pclk_in
sim_pipe_rate : out std_logic_vector(1 downto 0); -- sim_pipe_rate
sim_ltssmstate : out std_logic_vector(4 downto 0); -- sim_ltssmstate
eidleinfersel0 : out std_logic_vector(2 downto 0); -- eidleinfersel0
eidleinfersel1 : out std_logic_vector(2 downto 0); -- eidleinfersel1
eidleinfersel2 : out std_logic_vector(2 downto 0); -- eidleinfersel2
eidleinfersel3 : out std_logic_vector(2 downto 0); -- eidleinfersel3
eidleinfersel4 : out std_logic_vector(2 downto 0); -- eidleinfersel4
eidleinfersel5 : out std_logic_vector(2 downto 0); -- eidleinfersel5
eidleinfersel6 : out std_logic_vector(2 downto 0); -- eidleinfersel6
eidleinfersel7 : out std_logic_vector(2 downto 0); -- eidleinfersel7
powerdown0 : out std_logic_vector(1 downto 0); -- powerdown0
powerdown1 : out std_logic_vector(1 downto 0); -- powerdown1
powerdown2 : out std_logic_vector(1 downto 0); -- powerdown2
powerdown3 : out std_logic_vector(1 downto 0); -- powerdown3
powerdown4 : out std_logic_vector(1 downto 0); -- powerdown4
powerdown5 : out std_logic_vector(1 downto 0); -- powerdown5
powerdown6 : out std_logic_vector(1 downto 0); -- powerdown6
powerdown7 : out std_logic_vector(1 downto 0); -- powerdown7
rxpolarity0 : out std_logic; -- rxpolarity0
rxpolarity1 : out std_logic; -- rxpolarity1
rxpolarity2 : out std_logic; -- rxpolarity2
rxpolarity3 : out std_logic; -- rxpolarity3
rxpolarity4 : out std_logic; -- rxpolarity4
rxpolarity5 : out std_logic; -- rxpolarity5
rxpolarity6 : out std_logic; -- rxpolarity6
rxpolarity7 : out std_logic; -- rxpolarity7
txcompl0 : out std_logic; -- txcompl0
txcompl1 : out std_logic; -- txcompl1
txcompl2 : out std_logic; -- txcompl2
txcompl3 : out std_logic; -- txcompl3
txcompl4 : out std_logic; -- txcompl4
txcompl5 : out std_logic; -- txcompl5
txcompl6 : out std_logic; -- txcompl6
txcompl7 : out std_logic; -- txcompl7
txdata0 : out std_logic_vector(31 downto 0); -- txdata0
txdata1 : out std_logic_vector(31 downto 0); -- txdata1
txdata2 : out std_logic_vector(31 downto 0); -- txdata2
txdata3 : out std_logic_vector(31 downto 0); -- txdata3
txdata4 : out std_logic_vector(31 downto 0); -- txdata4
txdata5 : out std_logic_vector(31 downto 0); -- txdata5
txdata6 : out std_logic_vector(31 downto 0); -- txdata6
txdata7 : out std_logic_vector(31 downto 0); -- txdata7
txdatak0 : out std_logic_vector(3 downto 0); -- txdatak0
txdatak1 : out std_logic_vector(3 downto 0); -- txdatak1
txdatak2 : out std_logic_vector(3 downto 0); -- txdatak2
txdatak3 : out std_logic_vector(3 downto 0); -- txdatak3
txdatak4 : out std_logic_vector(3 downto 0); -- txdatak4
txdatak5 : out std_logic_vector(3 downto 0); -- txdatak5
txdatak6 : out std_logic_vector(3 downto 0); -- txdatak6
txdatak7 : out std_logic_vector(3 downto 0); -- txdatak7
txdetectrx0 : out std_logic; -- txdetectrx0
txdetectrx1 : out std_logic; -- txdetectrx1
txdetectrx2 : out std_logic; -- txdetectrx2
txdetectrx3 : out std_logic; -- txdetectrx3
txdetectrx4 : out std_logic; -- txdetectrx4
txdetectrx5 : out std_logic; -- txdetectrx5
txdetectrx6 : out std_logic; -- txdetectrx6
txdetectrx7 : out std_logic; -- txdetectrx7
txelecidle0 : out std_logic; -- txelecidle0
txelecidle1 : out std_logic; -- txelecidle1
txelecidle2 : out std_logic; -- txelecidle2
txelecidle3 : out std_logic; -- txelecidle3
txelecidle4 : out std_logic; -- txelecidle4
txelecidle5 : out std_logic; -- txelecidle5
txelecidle6 : out std_logic; -- txelecidle6
txelecidle7 : out std_logic; -- txelecidle7
txdeemph0 : out std_logic; -- txdeemph0
txdeemph1 : out std_logic; -- txdeemph1
txdeemph2 : out std_logic; -- txdeemph2
txdeemph3 : out std_logic; -- txdeemph3
txdeemph4 : out std_logic; -- txdeemph4
txdeemph5 : out std_logic; -- txdeemph5
txdeemph6 : out std_logic; -- txdeemph6
txdeemph7 : out std_logic; -- txdeemph7
txmargin0 : out std_logic_vector(2 downto 0); -- txmargin0
txmargin1 : out std_logic_vector(2 downto 0); -- txmargin1
txmargin2 : out std_logic_vector(2 downto 0); -- txmargin2
txmargin3 : out std_logic_vector(2 downto 0); -- txmargin3
txmargin4 : out std_logic_vector(2 downto 0); -- txmargin4
txmargin5 : out std_logic_vector(2 downto 0); -- txmargin5
txmargin6 : out std_logic_vector(2 downto 0); -- txmargin6
txmargin7 : out std_logic_vector(2 downto 0); -- txmargin7
txswing0 : out std_logic; -- txswing0
txswing1 : out std_logic; -- txswing1
txswing2 : out std_logic; -- txswing2
txswing3 : out std_logic; -- txswing3
txswing4 : out std_logic; -- txswing4
txswing5 : out std_logic; -- txswing5
txswing6 : out std_logic; -- txswing6
txswing7 : out std_logic; -- txswing7
phystatus0 : in std_logic := 'X'; -- phystatus0
phystatus1 : in std_logic := 'X'; -- phystatus1
phystatus2 : in std_logic := 'X'; -- phystatus2
phystatus3 : in std_logic := 'X'; -- phystatus3
phystatus4 : in std_logic := 'X'; -- phystatus4
phystatus5 : in std_logic := 'X'; -- phystatus5
phystatus6 : in std_logic := 'X'; -- phystatus6
phystatus7 : in std_logic := 'X'; -- phystatus7
rxdata0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- rxdata0
rxdata1 : in std_logic_vector(31 downto 0) := (others => 'X'); -- rxdata1
rxdata2 : in std_logic_vector(31 downto 0) := (others => 'X'); -- rxdata2
rxdata3 : in std_logic_vector(31 downto 0) := (others => 'X'); -- rxdata3
rxdata4 : in std_logic_vector(31 downto 0) := (others => 'X'); -- rxdata4
rxdata5 : in std_logic_vector(31 downto 0) := (others => 'X'); -- rxdata5
rxdata6 : in std_logic_vector(31 downto 0) := (others => 'X'); -- rxdata6
rxdata7 : in std_logic_vector(31 downto 0) := (others => 'X'); -- rxdata7
rxdatak0 : in std_logic_vector(3 downto 0) := (others => 'X'); -- rxdatak0
rxdatak1 : in std_logic_vector(3 downto 0) := (others => 'X'); -- rxdatak1
rxdatak2 : in std_logic_vector(3 downto 0) := (others => 'X'); -- rxdatak2
rxdatak3 : in std_logic_vector(3 downto 0) := (others => 'X'); -- rxdatak3
rxdatak4 : in std_logic_vector(3 downto 0) := (others => 'X'); -- rxdatak4
rxdatak5 : in std_logic_vector(3 downto 0) := (others => 'X'); -- rxdatak5
rxdatak6 : in std_logic_vector(3 downto 0) := (others => 'X'); -- rxdatak6
rxdatak7 : in std_logic_vector(3 downto 0) := (others => 'X'); -- rxdatak7
rxelecidle0 : in std_logic := 'X'; -- rxelecidle0
rxelecidle1 : in std_logic := 'X'; -- rxelecidle1
rxelecidle2 : in std_logic := 'X'; -- rxelecidle2
rxelecidle3 : in std_logic := 'X'; -- rxelecidle3
rxelecidle4 : in std_logic := 'X'; -- rxelecidle4
rxelecidle5 : in std_logic := 'X'; -- rxelecidle5
rxelecidle6 : in std_logic := 'X'; -- rxelecidle6
rxelecidle7 : in std_logic := 'X'; -- rxelecidle7
rxstatus0 : in std_logic_vector(2 downto 0) := (others => 'X'); -- rxstatus0
rxstatus1 : in std_logic_vector(2 downto 0) := (others => 'X'); -- rxstatus1
rxstatus2 : in std_logic_vector(2 downto 0) := (others => 'X'); -- rxstatus2
rxstatus3 : in std_logic_vector(2 downto 0) := (others => 'X'); -- rxstatus3
rxstatus4 : in std_logic_vector(2 downto 0) := (others => 'X'); -- rxstatus4
rxstatus5 : in std_logic_vector(2 downto 0) := (others => 'X'); -- rxstatus5
rxstatus6 : in std_logic_vector(2 downto 0) := (others => 'X'); -- rxstatus6
rxstatus7 : in std_logic_vector(2 downto 0) := (others => 'X'); -- rxstatus7
rxvalid0 : in std_logic := 'X'; -- rxvalid0
rxvalid1 : in std_logic := 'X'; -- rxvalid1
rxvalid2 : in std_logic := 'X'; -- rxvalid2
rxvalid3 : in std_logic := 'X'; -- rxvalid3
rxvalid4 : in std_logic := 'X'; -- rxvalid4
rxvalid5 : in std_logic := 'X'; -- rxvalid5
rxvalid6 : in std_logic := 'X'; -- rxvalid6
rxvalid7 : in std_logic := 'X'; -- rxvalid7
rxdataskip0 : in std_logic := 'X'; -- rxdataskip0
rxdataskip1 : in std_logic := 'X'; -- rxdataskip1
rxdataskip2 : in std_logic := 'X'; -- rxdataskip2
rxdataskip3 : in std_logic := 'X'; -- rxdataskip3
rxdataskip4 : in std_logic := 'X'; -- rxdataskip4
rxdataskip5 : in std_logic := 'X'; -- rxdataskip5
rxdataskip6 : in std_logic := 'X'; -- rxdataskip6
rxdataskip7 : in std_logic := 'X'; -- rxdataskip7
rxblkst0 : in std_logic := 'X'; -- rxblkst0
rxblkst1 : in std_logic := 'X'; -- rxblkst1
rxblkst2 : in std_logic := 'X'; -- rxblkst2
rxblkst3 : in std_logic := 'X'; -- rxblkst3
rxblkst4 : in std_logic := 'X'; -- rxblkst4
rxblkst5 : in std_logic := 'X'; -- rxblkst5
rxblkst6 : in std_logic := 'X'; -- rxblkst6
rxblkst7 : in std_logic := 'X'; -- rxblkst7
rxsynchd0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- rxsynchd0
rxsynchd1 : in std_logic_vector(1 downto 0) := (others => 'X'); -- rxsynchd1
rxsynchd2 : in std_logic_vector(1 downto 0) := (others => 'X'); -- rxsynchd2
rxsynchd3 : in std_logic_vector(1 downto 0) := (others => 'X'); -- rxsynchd3
rxsynchd4 : in std_logic_vector(1 downto 0) := (others => 'X'); -- rxsynchd4
rxsynchd5 : in std_logic_vector(1 downto 0) := (others => 'X'); -- rxsynchd5
rxsynchd6 : in std_logic_vector(1 downto 0) := (others => 'X'); -- rxsynchd6
rxsynchd7 : in std_logic_vector(1 downto 0) := (others => 'X'); -- rxsynchd7
currentcoeff0 : out std_logic_vector(17 downto 0); -- currentcoeff0
currentcoeff1 : out std_logic_vector(17 downto 0); -- currentcoeff1
currentcoeff2 : out std_logic_vector(17 downto 0); -- currentcoeff2
currentcoeff3 : out std_logic_vector(17 downto 0); -- currentcoeff3
currentcoeff4 : out std_logic_vector(17 downto 0); -- currentcoeff4
currentcoeff5 : out std_logic_vector(17 downto 0); -- currentcoeff5
currentcoeff6 : out std_logic_vector(17 downto 0); -- currentcoeff6
currentcoeff7 : out std_logic_vector(17 downto 0); -- currentcoeff7
currentrxpreset0 : out std_logic_vector(2 downto 0); -- currentrxpreset0
currentrxpreset1 : out std_logic_vector(2 downto 0); -- currentrxpreset1
currentrxpreset2 : out std_logic_vector(2 downto 0); -- currentrxpreset2
currentrxpreset3 : out std_logic_vector(2 downto 0); -- currentrxpreset3
currentrxpreset4 : out std_logic_vector(2 downto 0); -- currentrxpreset4
currentrxpreset5 : out std_logic_vector(2 downto 0); -- currentrxpreset5
currentrxpreset6 : out std_logic_vector(2 downto 0); -- currentrxpreset6
currentrxpreset7 : out std_logic_vector(2 downto 0); -- currentrxpreset7
txsynchd0 : out std_logic_vector(1 downto 0); -- txsynchd0
txsynchd1 : out std_logic_vector(1 downto 0); -- txsynchd1
txsynchd2 : out std_logic_vector(1 downto 0); -- txsynchd2
txsynchd3 : out std_logic_vector(1 downto 0); -- txsynchd3
txsynchd4 : out std_logic_vector(1 downto 0); -- txsynchd4
txsynchd5 : out std_logic_vector(1 downto 0); -- txsynchd5
txsynchd6 : out std_logic_vector(1 downto 0); -- txsynchd6
txsynchd7 : out std_logic_vector(1 downto 0); -- txsynchd7
txblkst0 : out std_logic; -- txblkst0
txblkst1 : out std_logic; -- txblkst1
txblkst2 : out std_logic; -- txblkst2
txblkst3 : out std_logic; -- txblkst3
txblkst4 : out std_logic; -- txblkst4
txblkst5 : out std_logic; -- txblkst5
txblkst6 : out std_logic; -- txblkst6
txblkst7 : out std_logic; -- txblkst7
txdataskip0 : out std_logic; -- txdataskip0
txdataskip1 : out std_logic; -- txdataskip1
txdataskip2 : out std_logic; -- txdataskip2
txdataskip3 : out std_logic; -- txdataskip3
txdataskip4 : out std_logic; -- txdataskip4
txdataskip5 : out std_logic; -- txdataskip5
txdataskip6 : out std_logic; -- txdataskip6
txdataskip7 : out std_logic; -- txdataskip7
rate0 : out std_logic_vector(1 downto 0); -- rate0
rate1 : out std_logic_vector(1 downto 0); -- rate1
rate2 : out std_logic_vector(1 downto 0); -- rate2
rate3 : out std_logic_vector(1 downto 0); -- rate3
rate4 : out std_logic_vector(1 downto 0); -- rate4
rate5 : out std_logic_vector(1 downto 0); -- rate5
rate6 : out std_logic_vector(1 downto 0); -- rate6
rate7 : out std_logic_vector(1 downto 0); -- rate7
rx_in0 : in std_logic := 'X'; -- rx_in0
rx_in1 : in std_logic := 'X'; -- rx_in1
rx_in2 : in std_logic := 'X'; -- rx_in2
rx_in3 : in std_logic := 'X'; -- rx_in3
rx_in4 : in std_logic := 'X'; -- rx_in4
rx_in5 : in std_logic := 'X'; -- rx_in5
rx_in6 : in std_logic := 'X'; -- rx_in6
rx_in7 : in std_logic := 'X'; -- rx_in7
tx_out0 : out std_logic; -- tx_out0
tx_out1 : out std_logic; -- tx_out1
tx_out2 : out std_logic; -- tx_out2
tx_out3 : out std_logic; -- tx_out3
tx_out4 : out std_logic; -- tx_out4
tx_out5 : out std_logic; -- tx_out5
tx_out6 : out std_logic; -- tx_out6
tx_out7 : out std_logic; -- tx_out7
txs_address_i : in std_logic_vector(63 downto 0) := (others => 'X'); -- address
txs_chipselect_i : in std_logic := 'X'; -- chipselect
txs_byteenable_i : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
txs_readdata_o : out std_logic_vector(31 downto 0); -- readdata
txs_writedata_i : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
txs_read_i : in std_logic := 'X'; -- read
txs_write_i : in std_logic := 'X'; -- write
txs_readdatavalid_o : out std_logic; -- readdatavalid
txs_waitrequest_o : out std_logic; -- waitrequest
rxm_bar2_address_o : out std_logic_vector(63 downto 0); -- address
rxm_bar2_byteenable_o : out std_logic_vector(3 downto 0); -- byteenable
rxm_bar2_readdata_i : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
rxm_bar2_writedata_o : out std_logic_vector(31 downto 0); -- writedata
rxm_bar2_read_o : out std_logic; -- read
rxm_bar2_write_o : out std_logic; -- write
rxm_bar2_readdatavalid_i : in std_logic := 'X'; -- readdatavalid
rxm_bar2_waitrequest_i : in std_logic := 'X'; -- waitrequest
rxm_bar4_address_o : out std_logic_vector(63 downto 0); -- address
rxm_bar4_byteenable_o : out std_logic_vector(3 downto 0); -- byteenable
rxm_bar4_readdata_i : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
rxm_bar4_writedata_o : out std_logic_vector(31 downto 0); -- writedata
rxm_bar4_read_o : out std_logic; -- read
rxm_bar4_write_o : out std_logic; -- write
rxm_bar4_readdatavalid_i : in std_logic := 'X'; -- readdatavalid
rxm_bar4_waitrequest_i : in std_logic := 'X'; -- waitrequest
rd_dma_address_o : out std_logic_vector(63 downto 0); -- address
rd_dma_write_o : out std_logic; -- write
rd_dma_write_data_o : out std_logic_vector(255 downto 0); -- writedata
rd_dma_wait_request_i : in std_logic := 'X'; -- waitrequest
rd_dma_burst_count_o : out std_logic_vector(4 downto 0); -- burstcount
rd_dma_byte_enable_o : out std_logic_vector(31 downto 0); -- byteenable
wr_dma_address_o : out std_logic_vector(63 downto 0); -- address
wr_dma_read_o : out std_logic; -- read
wr_dma_read_data_i : in std_logic_vector(255 downto 0) := (others => 'X'); -- readdata
wr_dma_wait_request_i : in std_logic := 'X'; -- waitrequest
wr_dma_burst_count_o : out std_logic_vector(4 downto 0); -- burstcount
wr_dma_read_data_valid_i : in std_logic := 'X'; -- readdatavalid
rd_dts_chip_select_i : in std_logic := 'X'; -- chipselect
rd_dts_write_i : in std_logic := 'X'; -- write
rd_dts_burst_count_i : in std_logic_vector(4 downto 0) := (others => 'X'); -- burstcount
rd_dts_address_i : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
rd_dts_write_data_i : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
rd_dts_wait_request_o : out std_logic; -- waitrequest
wr_dts_chip_select_i : in std_logic := 'X'; -- chipselect
wr_dts_write_i : in std_logic := 'X'; -- write
wr_dts_burst_count_i : in std_logic_vector(4 downto 0) := (others => 'X'); -- burstcount
wr_dts_address_i : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
wr_dts_write_data_i : in std_logic_vector(255 downto 0) := (others => 'X'); -- writedata
wr_dts_wait_request_o : out std_logic; -- waitrequest
rd_dcm_address_o : out std_logic_vector(63 downto 0); -- address
rd_dcm_write_o : out std_logic; -- write
rd_dcm_writedata_o : out std_logic_vector(31 downto 0); -- writedata
rd_dcm_read_o : out std_logic; -- read
rd_dcm_byte_enable_o : out std_logic_vector(3 downto 0); -- byteenable
rd_dcm_wait_request_i : in std_logic := 'X'; -- waitrequest
rd_dcm_read_data_i : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
rd_dcm_read_data_valid_i : in std_logic := 'X'; -- readdatavalid
wr_dcm_address_o : out std_logic_vector(63 downto 0); -- address
wr_dcm_write_o : out std_logic; -- write
wr_dcm_writedata_o : out std_logic_vector(31 downto 0); -- writedata
wr_dcm_read_o : out std_logic; -- read
wr_dcm_byte_enable_o : out std_logic_vector(3 downto 0); -- byteenable
wr_dcm_wait_request_i : in std_logic := 'X'; -- waitrequest
wr_dcm_read_data_i : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
wr_dcm_read_data_valid_i : in std_logic := 'X' -- readdatavalid
);
end component top_a10_pcie;
u0 : component top_a10_pcie
port map (
coreclkout_hip => CONNECTED_TO_coreclkout_hip, -- coreclkout_hip.clk
refclk => CONNECTED_TO_refclk, -- refclk.clk
npor => CONNECTED_TO_npor, -- npor.npor
pin_perst => CONNECTED_TO_pin_perst, -- .pin_perst
app_nreset_status => CONNECTED_TO_app_nreset_status, -- app_nreset_status.reset_n
test_in => CONNECTED_TO_test_in, -- hip_ctrl.test_in
simu_mode_pipe => CONNECTED_TO_simu_mode_pipe, -- .simu_mode_pipe
devkit_status => CONNECTED_TO_devkit_status, -- dk_hip.devkit_status
devkit_ctrl => CONNECTED_TO_devkit_ctrl, -- .devkit_ctrl
sim_pipe_pclk_in => CONNECTED_TO_sim_pipe_pclk_in, -- hip_pipe.sim_pipe_pclk_in
sim_pipe_rate => CONNECTED_TO_sim_pipe_rate, -- .sim_pipe_rate
sim_ltssmstate => CONNECTED_TO_sim_ltssmstate, -- .sim_ltssmstate
eidleinfersel0 => CONNECTED_TO_eidleinfersel0, -- .eidleinfersel0
eidleinfersel1 => CONNECTED_TO_eidleinfersel1, -- .eidleinfersel1
eidleinfersel2 => CONNECTED_TO_eidleinfersel2, -- .eidleinfersel2
eidleinfersel3 => CONNECTED_TO_eidleinfersel3, -- .eidleinfersel3
eidleinfersel4 => CONNECTED_TO_eidleinfersel4, -- .eidleinfersel4
eidleinfersel5 => CONNECTED_TO_eidleinfersel5, -- .eidleinfersel5
eidleinfersel6 => CONNECTED_TO_eidleinfersel6, -- .eidleinfersel6
eidleinfersel7 => CONNECTED_TO_eidleinfersel7, -- .eidleinfersel7
powerdown0 => CONNECTED_TO_powerdown0, -- .powerdown0
powerdown1 => CONNECTED_TO_powerdown1, -- .powerdown1
powerdown2 => CONNECTED_TO_powerdown2, -- .powerdown2
powerdown3 => CONNECTED_TO_powerdown3, -- .powerdown3
powerdown4 => CONNECTED_TO_powerdown4, -- .powerdown4
powerdown5 => CONNECTED_TO_powerdown5, -- .powerdown5
powerdown6 => CONNECTED_TO_powerdown6, -- .powerdown6
powerdown7 => CONNECTED_TO_powerdown7, -- .powerdown7
rxpolarity0 => CONNECTED_TO_rxpolarity0, -- .rxpolarity0
rxpolarity1 => CONNECTED_TO_rxpolarity1, -- .rxpolarity1
rxpolarity2 => CONNECTED_TO_rxpolarity2, -- .rxpolarity2
rxpolarity3 => CONNECTED_TO_rxpolarity3, -- .rxpolarity3
rxpolarity4 => CONNECTED_TO_rxpolarity4, -- .rxpolarity4
rxpolarity5 => CONNECTED_TO_rxpolarity5, -- .rxpolarity5
rxpolarity6 => CONNECTED_TO_rxpolarity6, -- .rxpolarity6
rxpolarity7 => CONNECTED_TO_rxpolarity7, -- .rxpolarity7
txcompl0 => CONNECTED_TO_txcompl0, -- .txcompl0
txcompl1 => CONNECTED_TO_txcompl1, -- .txcompl1
txcompl2 => CONNECTED_TO_txcompl2, -- .txcompl2
txcompl3 => CONNECTED_TO_txcompl3, -- .txcompl3
txcompl4 => CONNECTED_TO_txcompl4, -- .txcompl4
txcompl5 => CONNECTED_TO_txcompl5, -- .txcompl5
txcompl6 => CONNECTED_TO_txcompl6, -- .txcompl6
txcompl7 => CONNECTED_TO_txcompl7, -- .txcompl7
txdata0 => CONNECTED_TO_txdata0, -- .txdata0
txdata1 => CONNECTED_TO_txdata1, -- .txdata1
txdata2 => CONNECTED_TO_txdata2, -- .txdata2
txdata3 => CONNECTED_TO_txdata3, -- .txdata3
txdata4 => CONNECTED_TO_txdata4, -- .txdata4
txdata5 => CONNECTED_TO_txdata5, -- .txdata5
txdata6 => CONNECTED_TO_txdata6, -- .txdata6
txdata7 => CONNECTED_TO_txdata7, -- .txdata7
txdatak0 => CONNECTED_TO_txdatak0, -- .txdatak0
txdatak1 => CONNECTED_TO_txdatak1, -- .txdatak1
txdatak2 => CONNECTED_TO_txdatak2, -- .txdatak2
txdatak3 => CONNECTED_TO_txdatak3, -- .txdatak3
txdatak4 => CONNECTED_TO_txdatak4, -- .txdatak4
txdatak5 => CONNECTED_TO_txdatak5, -- .txdatak5
txdatak6 => CONNECTED_TO_txdatak6, -- .txdatak6
txdatak7 => CONNECTED_TO_txdatak7, -- .txdatak7
txdetectrx0 => CONNECTED_TO_txdetectrx0, -- .txdetectrx0
txdetectrx1 => CONNECTED_TO_txdetectrx1, -- .txdetectrx1
txdetectrx2 => CONNECTED_TO_txdetectrx2, -- .txdetectrx2
txdetectrx3 => CONNECTED_TO_txdetectrx3, -- .txdetectrx3
txdetectrx4 => CONNECTED_TO_txdetectrx4, -- .txdetectrx4
txdetectrx5 => CONNECTED_TO_txdetectrx5, -- .txdetectrx5
txdetectrx6 => CONNECTED_TO_txdetectrx6, -- .txdetectrx6
txdetectrx7 => CONNECTED_TO_txdetectrx7, -- .txdetectrx7
txelecidle0 => CONNECTED_TO_txelecidle0, -- .txelecidle0
txelecidle1 => CONNECTED_TO_txelecidle1, -- .txelecidle1
txelecidle2 => CONNECTED_TO_txelecidle2, -- .txelecidle2
txelecidle3 => CONNECTED_TO_txelecidle3, -- .txelecidle3
txelecidle4 => CONNECTED_TO_txelecidle4, -- .txelecidle4
txelecidle5 => CONNECTED_TO_txelecidle5, -- .txelecidle5
txelecidle6 => CONNECTED_TO_txelecidle6, -- .txelecidle6
txelecidle7 => CONNECTED_TO_txelecidle7, -- .txelecidle7
txdeemph0 => CONNECTED_TO_txdeemph0, -- .txdeemph0
txdeemph1 => CONNECTED_TO_txdeemph1, -- .txdeemph1
txdeemph2 => CONNECTED_TO_txdeemph2, -- .txdeemph2
txdeemph3 => CONNECTED_TO_txdeemph3, -- .txdeemph3
txdeemph4 => CONNECTED_TO_txdeemph4, -- .txdeemph4
txdeemph5 => CONNECTED_TO_txdeemph5, -- .txdeemph5
txdeemph6 => CONNECTED_TO_txdeemph6, -- .txdeemph6
txdeemph7 => CONNECTED_TO_txdeemph7, -- .txdeemph7
txmargin0 => CONNECTED_TO_txmargin0, -- .txmargin0
txmargin1 => CONNECTED_TO_txmargin1, -- .txmargin1
txmargin2 => CONNECTED_TO_txmargin2, -- .txmargin2
txmargin3 => CONNECTED_TO_txmargin3, -- .txmargin3
txmargin4 => CONNECTED_TO_txmargin4, -- .txmargin4
txmargin5 => CONNECTED_TO_txmargin5, -- .txmargin5
txmargin6 => CONNECTED_TO_txmargin6, -- .txmargin6
txmargin7 => CONNECTED_TO_txmargin7, -- .txmargin7
txswing0 => CONNECTED_TO_txswing0, -- .txswing0
txswing1 => CONNECTED_TO_txswing1, -- .txswing1
txswing2 => CONNECTED_TO_txswing2, -- .txswing2
txswing3 => CONNECTED_TO_txswing3, -- .txswing3
txswing4 => CONNECTED_TO_txswing4, -- .txswing4
txswing5 => CONNECTED_TO_txswing5, -- .txswing5
txswing6 => CONNECTED_TO_txswing6, -- .txswing6
txswing7 => CONNECTED_TO_txswing7, -- .txswing7
phystatus0 => CONNECTED_TO_phystatus0, -- .phystatus0
phystatus1 => CONNECTED_TO_phystatus1, -- .phystatus1
phystatus2 => CONNECTED_TO_phystatus2, -- .phystatus2
phystatus3 => CONNECTED_TO_phystatus3, -- .phystatus3
phystatus4 => CONNECTED_TO_phystatus4, -- .phystatus4
phystatus5 => CONNECTED_TO_phystatus5, -- .phystatus5
phystatus6 => CONNECTED_TO_phystatus6, -- .phystatus6
phystatus7 => CONNECTED_TO_phystatus7, -- .phystatus7
rxdata0 => CONNECTED_TO_rxdata0, -- .rxdata0
rxdata1 => CONNECTED_TO_rxdata1, -- .rxdata1
rxdata2 => CONNECTED_TO_rxdata2, -- .rxdata2
rxdata3 => CONNECTED_TO_rxdata3, -- .rxdata3
rxdata4 => CONNECTED_TO_rxdata4, -- .rxdata4
rxdata5 => CONNECTED_TO_rxdata5, -- .rxdata5
rxdata6 => CONNECTED_TO_rxdata6, -- .rxdata6
rxdata7 => CONNECTED_TO_rxdata7, -- .rxdata7
rxdatak0 => CONNECTED_TO_rxdatak0, -- .rxdatak0
rxdatak1 => CONNECTED_TO_rxdatak1, -- .rxdatak1
rxdatak2 => CONNECTED_TO_rxdatak2, -- .rxdatak2
rxdatak3 => CONNECTED_TO_rxdatak3, -- .rxdatak3
rxdatak4 => CONNECTED_TO_rxdatak4, -- .rxdatak4
rxdatak5 => CONNECTED_TO_rxdatak5, -- .rxdatak5
rxdatak6 => CONNECTED_TO_rxdatak6, -- .rxdatak6
rxdatak7 => CONNECTED_TO_rxdatak7, -- .rxdatak7
rxelecidle0 => CONNECTED_TO_rxelecidle0, -- .rxelecidle0
rxelecidle1 => CONNECTED_TO_rxelecidle1, -- .rxelecidle1
rxelecidle2 => CONNECTED_TO_rxelecidle2, -- .rxelecidle2
rxelecidle3 => CONNECTED_TO_rxelecidle3, -- .rxelecidle3
rxelecidle4 => CONNECTED_TO_rxelecidle4, -- .rxelecidle4
rxelecidle5 => CONNECTED_TO_rxelecidle5, -- .rxelecidle5
rxelecidle6 => CONNECTED_TO_rxelecidle6, -- .rxelecidle6
rxelecidle7 => CONNECTED_TO_rxelecidle7, -- .rxelecidle7
rxstatus0 => CONNECTED_TO_rxstatus0, -- .rxstatus0
rxstatus1 => CONNECTED_TO_rxstatus1, -- .rxstatus1
rxstatus2 => CONNECTED_TO_rxstatus2, -- .rxstatus2
rxstatus3 => CONNECTED_TO_rxstatus3, -- .rxstatus3
rxstatus4 => CONNECTED_TO_rxstatus4, -- .rxstatus4
rxstatus5 => CONNECTED_TO_rxstatus5, -- .rxstatus5
rxstatus6 => CONNECTED_TO_rxstatus6, -- .rxstatus6
rxstatus7 => CONNECTED_TO_rxstatus7, -- .rxstatus7
rxvalid0 => CONNECTED_TO_rxvalid0, -- .rxvalid0
rxvalid1 => CONNECTED_TO_rxvalid1, -- .rxvalid1
rxvalid2 => CONNECTED_TO_rxvalid2, -- .rxvalid2
rxvalid3 => CONNECTED_TO_rxvalid3, -- .rxvalid3
rxvalid4 => CONNECTED_TO_rxvalid4, -- .rxvalid4
rxvalid5 => CONNECTED_TO_rxvalid5, -- .rxvalid5
rxvalid6 => CONNECTED_TO_rxvalid6, -- .rxvalid6
rxvalid7 => CONNECTED_TO_rxvalid7, -- .rxvalid7
rxdataskip0 => CONNECTED_TO_rxdataskip0, -- .rxdataskip0
rxdataskip1 => CONNECTED_TO_rxdataskip1, -- .rxdataskip1
rxdataskip2 => CONNECTED_TO_rxdataskip2, -- .rxdataskip2
rxdataskip3 => CONNECTED_TO_rxdataskip3, -- .rxdataskip3
rxdataskip4 => CONNECTED_TO_rxdataskip4, -- .rxdataskip4
rxdataskip5 => CONNECTED_TO_rxdataskip5, -- .rxdataskip5
rxdataskip6 => CONNECTED_TO_rxdataskip6, -- .rxdataskip6
rxdataskip7 => CONNECTED_TO_rxdataskip7, -- .rxdataskip7
rxblkst0 => CONNECTED_TO_rxblkst0, -- .rxblkst0
rxblkst1 => CONNECTED_TO_rxblkst1, -- .rxblkst1
rxblkst2 => CONNECTED_TO_rxblkst2, -- .rxblkst2
rxblkst3 => CONNECTED_TO_rxblkst3, -- .rxblkst3
rxblkst4 => CONNECTED_TO_rxblkst4, -- .rxblkst4
rxblkst5 => CONNECTED_TO_rxblkst5, -- .rxblkst5
rxblkst6 => CONNECTED_TO_rxblkst6, -- .rxblkst6
rxblkst7 => CONNECTED_TO_rxblkst7, -- .rxblkst7
rxsynchd0 => CONNECTED_TO_rxsynchd0, -- .rxsynchd0
rxsynchd1 => CONNECTED_TO_rxsynchd1, -- .rxsynchd1
rxsynchd2 => CONNECTED_TO_rxsynchd2, -- .rxsynchd2
rxsynchd3 => CONNECTED_TO_rxsynchd3, -- .rxsynchd3
rxsynchd4 => CONNECTED_TO_rxsynchd4, -- .rxsynchd4
rxsynchd5 => CONNECTED_TO_rxsynchd5, -- .rxsynchd5
rxsynchd6 => CONNECTED_TO_rxsynchd6, -- .rxsynchd6
rxsynchd7 => CONNECTED_TO_rxsynchd7, -- .rxsynchd7
currentcoeff0 => CONNECTED_TO_currentcoeff0, -- .currentcoeff0
currentcoeff1 => CONNECTED_TO_currentcoeff1, -- .currentcoeff1
currentcoeff2 => CONNECTED_TO_currentcoeff2, -- .currentcoeff2
currentcoeff3 => CONNECTED_TO_currentcoeff3, -- .currentcoeff3
currentcoeff4 => CONNECTED_TO_currentcoeff4, -- .currentcoeff4
currentcoeff5 => CONNECTED_TO_currentcoeff5, -- .currentcoeff5
currentcoeff6 => CONNECTED_TO_currentcoeff6, -- .currentcoeff6
currentcoeff7 => CONNECTED_TO_currentcoeff7, -- .currentcoeff7
currentrxpreset0 => CONNECTED_TO_currentrxpreset0, -- .currentrxpreset0
currentrxpreset1 => CONNECTED_TO_currentrxpreset1, -- .currentrxpreset1
currentrxpreset2 => CONNECTED_TO_currentrxpreset2, -- .currentrxpreset2
currentrxpreset3 => CONNECTED_TO_currentrxpreset3, -- .currentrxpreset3
currentrxpreset4 => CONNECTED_TO_currentrxpreset4, -- .currentrxpreset4
currentrxpreset5 => CONNECTED_TO_currentrxpreset5, -- .currentrxpreset5
currentrxpreset6 => CONNECTED_TO_currentrxpreset6, -- .currentrxpreset6
currentrxpreset7 => CONNECTED_TO_currentrxpreset7, -- .currentrxpreset7
txsynchd0 => CONNECTED_TO_txsynchd0, -- .txsynchd0
txsynchd1 => CONNECTED_TO_txsynchd1, -- .txsynchd1
txsynchd2 => CONNECTED_TO_txsynchd2, -- .txsynchd2
txsynchd3 => CONNECTED_TO_txsynchd3, -- .txsynchd3
txsynchd4 => CONNECTED_TO_txsynchd4, -- .txsynchd4
txsynchd5 => CONNECTED_TO_txsynchd5, -- .txsynchd5
txsynchd6 => CONNECTED_TO_txsynchd6, -- .txsynchd6
txsynchd7 => CONNECTED_TO_txsynchd7, -- .txsynchd7
txblkst0 => CONNECTED_TO_txblkst0, -- .txblkst0
txblkst1 => CONNECTED_TO_txblkst1, -- .txblkst1
txblkst2 => CONNECTED_TO_txblkst2, -- .txblkst2
txblkst3 => CONNECTED_TO_txblkst3, -- .txblkst3
txblkst4 => CONNECTED_TO_txblkst4, -- .txblkst4
txblkst5 => CONNECTED_TO_txblkst5, -- .txblkst5
txblkst6 => CONNECTED_TO_txblkst6, -- .txblkst6
txblkst7 => CONNECTED_TO_txblkst7, -- .txblkst7
txdataskip0 => CONNECTED_TO_txdataskip0, -- .txdataskip0
txdataskip1 => CONNECTED_TO_txdataskip1, -- .txdataskip1
txdataskip2 => CONNECTED_TO_txdataskip2, -- .txdataskip2
txdataskip3 => CONNECTED_TO_txdataskip3, -- .txdataskip3
txdataskip4 => CONNECTED_TO_txdataskip4, -- .txdataskip4
txdataskip5 => CONNECTED_TO_txdataskip5, -- .txdataskip5
txdataskip6 => CONNECTED_TO_txdataskip6, -- .txdataskip6
txdataskip7 => CONNECTED_TO_txdataskip7, -- .txdataskip7
rate0 => CONNECTED_TO_rate0, -- .rate0
rate1 => CONNECTED_TO_rate1, -- .rate1
rate2 => CONNECTED_TO_rate2, -- .rate2
rate3 => CONNECTED_TO_rate3, -- .rate3
rate4 => CONNECTED_TO_rate4, -- .rate4
rate5 => CONNECTED_TO_rate5, -- .rate5
rate6 => CONNECTED_TO_rate6, -- .rate6
rate7 => CONNECTED_TO_rate7, -- .rate7
rx_in0 => CONNECTED_TO_rx_in0, -- hip_serial.rx_in0
rx_in1 => CONNECTED_TO_rx_in1, -- .rx_in1
rx_in2 => CONNECTED_TO_rx_in2, -- .rx_in2
rx_in3 => CONNECTED_TO_rx_in3, -- .rx_in3
rx_in4 => CONNECTED_TO_rx_in4, -- .rx_in4
rx_in5 => CONNECTED_TO_rx_in5, -- .rx_in5
rx_in6 => CONNECTED_TO_rx_in6, -- .rx_in6
rx_in7 => CONNECTED_TO_rx_in7, -- .rx_in7
tx_out0 => CONNECTED_TO_tx_out0, -- .tx_out0
tx_out1 => CONNECTED_TO_tx_out1, -- .tx_out1
tx_out2 => CONNECTED_TO_tx_out2, -- .tx_out2
tx_out3 => CONNECTED_TO_tx_out3, -- .tx_out3
tx_out4 => CONNECTED_TO_tx_out4, -- .tx_out4
tx_out5 => CONNECTED_TO_tx_out5, -- .tx_out5
tx_out6 => CONNECTED_TO_tx_out6, -- .tx_out6
tx_out7 => CONNECTED_TO_tx_out7, -- .tx_out7
txs_address_i => CONNECTED_TO_txs_address_i, -- txs.address
txs_chipselect_i => CONNECTED_TO_txs_chipselect_i, -- .chipselect
txs_byteenable_i => CONNECTED_TO_txs_byteenable_i, -- .byteenable
txs_readdata_o => CONNECTED_TO_txs_readdata_o, -- .readdata
txs_writedata_i => CONNECTED_TO_txs_writedata_i, -- .writedata
txs_read_i => CONNECTED_TO_txs_read_i, -- .read
txs_write_i => CONNECTED_TO_txs_write_i, -- .write
txs_readdatavalid_o => CONNECTED_TO_txs_readdatavalid_o, -- .readdatavalid
txs_waitrequest_o => CONNECTED_TO_txs_waitrequest_o, -- .waitrequest
rxm_bar2_address_o => CONNECTED_TO_rxm_bar2_address_o, -- rxm_bar2.address
rxm_bar2_byteenable_o => CONNECTED_TO_rxm_bar2_byteenable_o, -- .byteenable
rxm_bar2_readdata_i => CONNECTED_TO_rxm_bar2_readdata_i, -- .readdata
rxm_bar2_writedata_o => CONNECTED_TO_rxm_bar2_writedata_o, -- .writedata
rxm_bar2_read_o => CONNECTED_TO_rxm_bar2_read_o, -- .read
rxm_bar2_write_o => CONNECTED_TO_rxm_bar2_write_o, -- .write
rxm_bar2_readdatavalid_i => CONNECTED_TO_rxm_bar2_readdatavalid_i, -- .readdatavalid
rxm_bar2_waitrequest_i => CONNECTED_TO_rxm_bar2_waitrequest_i, -- .waitrequest
rxm_bar4_address_o => CONNECTED_TO_rxm_bar4_address_o, -- rxm_bar4.address
rxm_bar4_byteenable_o => CONNECTED_TO_rxm_bar4_byteenable_o, -- .byteenable
rxm_bar4_readdata_i => CONNECTED_TO_rxm_bar4_readdata_i, -- .readdata
rxm_bar4_writedata_o => CONNECTED_TO_rxm_bar4_writedata_o, -- .writedata
rxm_bar4_read_o => CONNECTED_TO_rxm_bar4_read_o, -- .read
rxm_bar4_write_o => CONNECTED_TO_rxm_bar4_write_o, -- .write
rxm_bar4_readdatavalid_i => CONNECTED_TO_rxm_bar4_readdatavalid_i, -- .readdatavalid
rxm_bar4_waitrequest_i => CONNECTED_TO_rxm_bar4_waitrequest_i, -- .waitrequest
rd_dma_address_o => CONNECTED_TO_rd_dma_address_o, -- dma_rd_master.address
rd_dma_write_o => CONNECTED_TO_rd_dma_write_o, -- .write
rd_dma_write_data_o => CONNECTED_TO_rd_dma_write_data_o, -- .writedata
rd_dma_wait_request_i => CONNECTED_TO_rd_dma_wait_request_i, -- .waitrequest
rd_dma_burst_count_o => CONNECTED_TO_rd_dma_burst_count_o, -- .burstcount
rd_dma_byte_enable_o => CONNECTED_TO_rd_dma_byte_enable_o, -- .byteenable
wr_dma_address_o => CONNECTED_TO_wr_dma_address_o, -- dma_wr_master.address
wr_dma_read_o => CONNECTED_TO_wr_dma_read_o, -- .read
wr_dma_read_data_i => CONNECTED_TO_wr_dma_read_data_i, -- .readdata
wr_dma_wait_request_i => CONNECTED_TO_wr_dma_wait_request_i, -- .waitrequest
wr_dma_burst_count_o => CONNECTED_TO_wr_dma_burst_count_o, -- .burstcount
wr_dma_read_data_valid_i => CONNECTED_TO_wr_dma_read_data_valid_i, -- .readdatavalid
rd_dts_chip_select_i => CONNECTED_TO_rd_dts_chip_select_i, -- rd_dts_slave.chipselect
rd_dts_write_i => CONNECTED_TO_rd_dts_write_i, -- .write
rd_dts_burst_count_i => CONNECTED_TO_rd_dts_burst_count_i, -- .burstcount
rd_dts_address_i => CONNECTED_TO_rd_dts_address_i, -- .address
rd_dts_write_data_i => CONNECTED_TO_rd_dts_write_data_i, -- .writedata
rd_dts_wait_request_o => CONNECTED_TO_rd_dts_wait_request_o, -- .waitrequest
wr_dts_chip_select_i => CONNECTED_TO_wr_dts_chip_select_i, -- wr_dts_slave.chipselect
wr_dts_write_i => CONNECTED_TO_wr_dts_write_i, -- .write
wr_dts_burst_count_i => CONNECTED_TO_wr_dts_burst_count_i, -- .burstcount
wr_dts_address_i => CONNECTED_TO_wr_dts_address_i, -- .address
wr_dts_write_data_i => CONNECTED_TO_wr_dts_write_data_i, -- .writedata
wr_dts_wait_request_o => CONNECTED_TO_wr_dts_wait_request_o, -- .waitrequest
rd_dcm_address_o => CONNECTED_TO_rd_dcm_address_o, -- rd_dcm_master.address
rd_dcm_write_o => CONNECTED_TO_rd_dcm_write_o, -- .write
rd_dcm_writedata_o => CONNECTED_TO_rd_dcm_writedata_o, -- .writedata
rd_dcm_read_o => CONNECTED_TO_rd_dcm_read_o, -- .read
rd_dcm_byte_enable_o => CONNECTED_TO_rd_dcm_byte_enable_o, -- .byteenable
rd_dcm_wait_request_i => CONNECTED_TO_rd_dcm_wait_request_i, -- .waitrequest
rd_dcm_read_data_i => CONNECTED_TO_rd_dcm_read_data_i, -- .readdata
rd_dcm_read_data_valid_i => CONNECTED_TO_rd_dcm_read_data_valid_i, -- .readdatavalid
wr_dcm_address_o => CONNECTED_TO_wr_dcm_address_o, -- wr_dcm_master.address
wr_dcm_write_o => CONNECTED_TO_wr_dcm_write_o, -- .write
wr_dcm_writedata_o => CONNECTED_TO_wr_dcm_writedata_o, -- .writedata
wr_dcm_read_o => CONNECTED_TO_wr_dcm_read_o, -- .read
wr_dcm_byte_enable_o => CONNECTED_TO_wr_dcm_byte_enable_o, -- .byteenable
wr_dcm_wait_request_i => CONNECTED_TO_wr_dcm_wait_request_i, -- .waitrequest
wr_dcm_read_data_i => CONNECTED_TO_wr_dcm_read_data_i, -- .readdata
wr_dcm_read_data_valid_i => CONNECTED_TO_wr_dcm_read_data_valid_i -- .readdatavalid
);
|
-- Listing 7.4
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart is
generic(
-- Default setting:
-- 19,200 baud, 8 data bis, 1 stop its, 2^2 FIFO
DBIT: integer:=8; -- # data bits
SB_TICK: integer:=16; -- # ticks for stop bits, 16/24/32
-- for 1/1.5/2 stop bits
DVSR: integer:= 163; -- baud rate divisor
-- DVSR = 50M/(16*baud rate)
DVSR_BIT: integer:=8; -- # bits of DVSR
FIFO_W: integer:=2 -- # addr bits of FIFO
-- # words in FIFO=2^FIFO_W
);
port(
clk, reset: in std_logic;
rd_uart, wr_uart: in std_logic;
rx: in std_logic;
w_data: in std_logic_vector(7 downto 0);
tx_full, rx_empty: out std_logic;
r_data: out std_logic_vector(7 downto 0);
tx: out std_logic
);
end uart;
architecture str_arch of uart is
signal tick: std_logic;
signal rx_done_tick: std_logic;
signal tx_fifo_out: std_logic_vector(7 downto 0);
signal rx_data_out: std_logic_vector(7 downto 0);
signal tx_empty, tx_fifo_not_empty: std_logic;
signal tx_done_tick: std_logic;
begin
baud_gen_unit: entity work.mod_m_counter(arch)
generic map(M=>DVSR, N=>DVSR_BIT)
port map(clk=>clk, reset=>reset,
q=>open, max_tick=>tick);
uart_rx_unit: entity work.uart_rx(arch)
generic map(DBIT=>DBIT, SB_TICK=>SB_TICK)
port map(clk=>clk, reset=>reset, rx=>rx,
s_tick=>tick, rx_done_tick=>rx_done_tick,
dout=>rx_data_out);
fifo_rx_unit: entity work.fifo(arch)
generic map(B=>DBIT, W=>FIFO_W)
port map(clk=>clk, reset=>reset, rd=>rd_uart,
wr=>rx_done_tick, w_data=>rx_data_out,
empty=>rx_empty, full=>open, r_data=>r_data);
fifo_tx_unit: entity work.fifo(arch)
generic map(B=>DBIT, W=>FIFO_W)
port map(clk=>clk, reset=>reset, rd=>tx_done_tick,
wr=>wr_uart, w_data=>w_data, empty=>tx_empty,
full=>tx_full, r_data=>tx_fifo_out);
uart_tx_unit: entity work.uart_tx(arch)
generic map(DBIT=>DBIT, SB_TICK=>SB_TICK)
port map(clk=>clk, reset=>reset,
tx_start=>tx_fifo_not_empty,
s_tick=>tick, din=>tx_fifo_out,
tx_done_tick=> tx_done_tick, tx=>tx);
tx_fifo_not_empty <= not tx_empty;
end str_arch;
|
<filename>source_code/ALU.vhd
----------------------------------------------------------------------------------
--
-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
--
-- Copyright (C) 2020 <NAME>
-- Permission to use, copy, modify, and/or distribute this software for any
-- purpose with or without fee is hereby granted, provided that the above
-- copyright notice and this permission notice appear in all copies.
--
-- Project Name: SimpleCPU
-- Description: Synchronous Arithmetic Logic Unit (ALU) for 12-bit signed arithmetic.
-- It calculates the result res_out by combining the two operands op1_in and op2_in
-- depending on the opcode. The signal flags_out holds four diffrent flags.
--
-- Operations:
-- This ALU can perform additions, substractios and various logical operations
-- (such as AND, XOR, etc). op1_in and op2_in are interpreted as signed integers in 2's complement representation.
-- Therefore, this ALU can operate in a value range of +2047 to -2048.
-- Note that there are two shift functions implemented, xSFT and L-xSFT, where the latter is a logical shift
-- that also shifts the sign bit and the former is an arithmetic shift that keeps the sign bit.
--
-- Functional description:
-- Prior to performing the operation, op1_in and op2_in are converted to signed and rezized by adding an extra bit.
-- This extra bit is used for detecting overflows. After the synchronous operation is performed,
-- the result is rezized by removing the extra bit (but keeping the sign bit) and outputted though res_out.
-- Overflows are detected by comparing the the 11th bit of the 13 bit res_signed_ext signal and
-- the 12 bit res_signed signal. If their 11th bit is not equal, we know that an overflow occured.
--
-- Flags:
-- The overflow flag is 1 if the current opcode in combination with the two operands causes an over/underflow.
-- The zero flag is 1 if the result of the operation is zero.
-- The equality flag is 1 if both operands are equal.
-- The error flag is 1 (and stays 1) if there ever was an undfined ALU opcode. This happens frequently
-- during simulation when the opcode port is not driven and has the value "UUUUUUUUUUUU".
--
-- Dependencies: N/A
--
-- Revision: 1.1
--
-----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ALU is
generic (
addr_size : natural := 12; -- address space = 2^addr_size
word_size : natural := 12
);
port (
clk_in : in std_logic;
opcode : in std_logic_vector (addr_size-1 downto 0);
op1_in : in std_logic_vector (addr_size-1 downto 0);
op2_in : in std_logic_vector (addr_size-1 downto 0);
res_out : out std_logic_vector (addr_size-1 downto 0);
flags_out : out std_logic_vector (addr_size-1 downto 0)
);
end ALU;
architecture Behavioral of ALU is
signal res_signed : signed (addr_size-1 downto 0) := (others => '0');
signal op1_signed_ext : signed (addr_size downto 0) := (others => '0');
signal op2_signed_ext : signed (addr_size downto 0) := (others => '0');
signal res_signed_ext : signed (addr_size downto 0) := (others => '0');
signal error_state : std_logic := '0';
-- debug signals, for simulation only
signal dbg_opcode_old : std_logic_vector (addr_size-1 downto 0) := x"000";
signal dbg_opcode_changed : std_logic := '0';
begin
-- extend and convert to signed
op1_signed_ext <= resize(signed(op1_in), op1_signed_ext'length);
op2_signed_ext <= resize(signed(op2_in), op2_signed_ext'length);
-- assign flags
flags_out(0) <= '0' when (res_signed_ext(11) = res_signed(11)) else '1'; -- overflow flag
flags_out(1) <= '1' when (res_signed = x"000") else '0'; -- zero flag
flags_out(2) <= '1' when (op1_in = op2_in) else '0'; -- equality flag
flags_out(3) <= error_state; -- error flag
-- output result
res_signed <= resize(res_signed_ext, res_out'length);
res_out <= std_logic_vector(res_signed);
ALU_BEHAV: process(clk_in)
begin
if(rising_edge (clk_in)) then
if opcode = x"001" then -- ADD
assert dbg_opcode_changed = '0' report "ALU opcode set to ADD" severity note;
res_signed_ext <= op1_signed_ext + op2_signed_ext;
elsif opcode = x"002" then -- SUB
assert (dbg_opcode_changed = '0') report "ALU opcode set to SUB" severity note;
res_signed_ext <= op1_signed_ext - op2_signed_ext;
elsif opcode = x"003" then -- LSFT
assert (dbg_opcode_changed = '0') report "ALU opcode set to LSFT" severity note;
res_signed_ext <= shift_left(op1_signed_ext, 1);
elsif opcode = x"004" then -- RSFT
assert (dbg_opcode_changed = '0') report "ALU opcode set to RSFT" severity note;
res_signed_ext <= shift_right(op1_signed_ext, 1);
elsif opcode = x"005" then -- AND
assert (dbg_opcode_changed = '0') report "ALU opcode set to AND" severity note;
res_signed_ext <= op1_signed_ext AND op2_signed_ext;
elsif opcode = x"006" then -- OR
assert (dbg_opcode_changed = '0') report "ALU opcode set to OR" severity note;
res_signed_ext <= op1_signed_ext OR op2_signed_ext;
elsif opcode = x"007" then -- XOR
assert (dbg_opcode_changed = '0') report "ALU opcode set to XOR" severity note;
res_signed_ext <= op1_signed_ext XOR op2_signed_ext;
elsif opcode = x"008" then -- NAND
assert (dbg_opcode_changed = '0') report "ALU opcode set to NAND" severity note;
res_signed_ext <= NOT (op1_signed_ext AND op2_signed_ext);
elsif opcode = x"009" then -- NOR
assert (dbg_opcode_changed = '0') report "ALU opcode set to NOR" severity note;
res_signed_ext <= NOT (op1_signed_ext OR op2_signed_ext);
elsif opcode = x"00A" then -- INCR
assert (dbg_opcode_changed = '0') report "ALU opcode set to INCR" severity note;
res_signed_ext <= op1_signed_ext + 1;
elsif opcode = x"00B" then -- DECR
assert (dbg_opcode_changed = '0') report "ALU opcode set to DECR" severity note;
res_signed_ext <= op1_signed_ext - 1;
elsif opcode = x"00C" then -- NOT
assert (dbg_opcode_changed = '0') report "ALU opcode set to NOT" severity note;
res_signed_ext <= NOT op1_signed_ext;
elsif opcode = x"00D" then -- BGR
assert (dbg_opcode_changed = '0') report "ALU opcode set to BGR" severity note;
if(op1_signed_ext > op2_signed_ext) then
res_signed_ext <= "0000000000001";
else
res_signed_ext <= "0000000000000";
end if;
elsif opcode = x"00E" then -- ABS
assert (dbg_opcode_changed = '0') report "ALU opcode set to ABS" severity note;
if op1_signed_ext(12) = '1' then
res_signed_ext <= (NOT op1_signed_ext) + 1; -- calc 2s complemet
else
res_signed_ext <= op1_signed_ext;
end if;
elsif opcode = x"00F" then -- L-LSFT
-- logical shift requires unsigned argument. The result of the shift must then be reconverted to signed
-- and rezized in order to fit into res_signed_ext
assert (dbg_opcode_changed = '0') report "ALU opcode set to L-LSFT" severity note;
res_signed_ext <= resize(signed(shift_left(unsigned(op1_in), 1)), op1_signed_ext'length);
elsif opcode = x"010" then -- L-RSFT
assert (dbg_opcode_changed = '0') report "ALU opcode set to L-RSFT" severity note;
res_signed_ext <= resize(signed(shift_right(unsigned(op1_in), 1)), op1_signed_ext'length);
else
assert (dbg_opcode_changed = '0') report "Undefined ALU opcode asserted!" severity warning;
error_state <= '1';
end if;
end if;
end process ALU_BEHAV;
DEBUG : process(clk_in)
begin
if rising_edge (clk_in) then
if NOT(dbg_opcode_old = opcode) then
dbg_opcode_old <= opcode;
end if;
end if;
end process DEBUG;
dbg_opcode_changed <= '0' when (dbg_opcode_old = opcode) else '1';
end Behavioral;
|
<gh_stars>0
-- Proyecto : SFU IEEE754
-- Nombre de archivo : SFU.vhd
-- Titulo : Special Function Unit
-----------------------------------------------------------------------------
-- Descripcion : This unit performs the floating point operations
-- sin(x), cos(x), rsqrt(x), log2(x) and exp2(x) using
-- IEE754 standard and operational compliant with GPU G80
-- architecture
--
-----------------------------------------------------------------------------
-- Universidad Pedagogica y Tecnologica de Colombia.
-- Facultad de ingenieria.
-- Escuela de ingenieria Electronica - extension Tunja.
--
-- Autor:
-- Abril 2020
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gpgpu_package.all;
entity sfu_proc is
port(clk_i :in std_logic; --input clock
rst_n :in std_logic; --reset active low
start_i :in std_logic; --start operation
src1_i :in vector_register; --IEE754 input data
selop_i :in std_logic_vector(2 downto 0); --operation selection
Result_o :out vector_register; --IEE754 result data output
stall_o :out std_logic --stall signal
);
end entity sfu_proc;
architecture structure of sfu_proc is
constant HALF_CORES :integer := CORES/2;
constant LOG_HALF_CORES :integer := log2(HALF_CORES);
type src_sfu_type is array(0 to 1) of std_logic_vector(31 downto 0);
type half_vector is array (HALF_CORES - 1 downto 0) of std_logic_vector(31 downto 0);
signal reg_src_i : vector_register;
signal Hreg_dst_o,Lreg_dst_o : half_vector;
signal src_sfu_sub_i : src_sfu_type;
signal dst_sfu_sub_i : src_sfu_type;
signal stall_s :std_logic_vector(1 downto 0);
type states is(IDLE, START, EXECUTE, DONE);
signal ns,ps :states;
signal count_i :unsigned(LOG_HALF_CORES-1 downto 0);
signal en_count,load_count,en_dec,en_input, start_s : std_logic;
begin
stall_s <=(others=>'0');
gSpecialFunctionUnit: for i in 0 to 1 generate
uSpecialFunctionUnit : sfu
port map(
--clk_i => clk_i,
--rst_n => rst_n,
--start_i => start_s,
src1_i => src_sfu_sub_i(i),
selop_i => selop_i,
Result_o => dst_sfu_sub_i(i)
--stall_o => stall_s(i)
);
end generate;
input_registers: process(clk_i,rst_n)
begin
if rst_n='0' then
reg_src_i <= (others=>(others=>'0'));
elsif rising_edge(clk_i) then
if en_input='1' then
reg_src_i <= src1_i;
end if;
end if;
end process;
output_registersL: process(clk_i,rst_n)
begin
if rst_n='0' then
Lreg_dst_o <= (others=>(others=>'0'));
elsif rising_edge(clk_i) then
if en_dec='1' then
Lreg_dst_o(to_integer(count_i)) <= dst_sfu_sub_i(0);
end if;
end if;
end process;
output_registersH: process(clk_i,rst_n)
begin
if rst_n='0' then
Hreg_dst_o <= (others=>(others=>'0'));
elsif rising_edge(clk_i) then
if en_dec='1' then
Hreg_dst_o(to_integer(count_i)) <= dst_sfu_sub_i(1);
end if;
end if;
end process;
gOutData: for i in 0 to HALF_CORES-1 generate
Result_o(i+HALF_CORES)<=Hreg_dst_o(i);
Result_o(i) <= Lreg_dst_o(i);
end generate;
src_sfu_sub_i(0)<=reg_src_i(to_integer(count_i));
src_sfu_sub_i(1)<=reg_src_i(to_integer(count_i)+HALF_CORES);
counter: process(clk_i,rst_n)
begin
if rst_n='0' then
count_i <=(others=>'0');
elsif rising_edge(clk_i) then
if en_count='1' then
if load_count='1' then
count_i <= (others=>'0');
else
count_i <= count_i + 1;
end if;
end if;
end if;
end process;
---next states
nex_state:process(ps,stall_s,start_i,count_i)
begin
case ps is
when IDLE =>
if(start_i='1') then
ns <= START;
else
ns <= IDLE;
end if;
when START =>
ns <= EXECUTE;
when EXECUTE =>
if (stall_s(0)='0' and stall_s(1)='0') then
if(count_i=(HALF_CORES-1)) then
ns <= DONE;
else
ns <= START;
end if;
else
ns <= EXECUTE;
end if;
when DONE =>
ns <= IDLE;
when others =>
ns <= IDLE;
end case;
end process;
---present states
present_state:process(clk_i,rst_n)
begin
if rst_n='0' then
ps <= IDLE;
elsif rising_edge(clk_i) then
ps <= ns;
end if;
end process;
---next states
output_logic:process(ps,stall_s,start_i,count_i)
begin
case ps is
when IDLE =>
stall_o <= '1';
en_count <= '1';
load_count <= '1';
start_s <= '0';
en_dec <= '0';
if(start_i='1') then
en_input <= '1';
else
en_input <= '0';
end if;
when START =>
stall_o <= '1';
en_count <= '0';
load_count <= '0';
start_s <= '1';
en_input <= '0';
en_dec <= '0';
when EXECUTE =>
start_s <= '0';
stall_o <= '1';
en_input <= '0';
if (stall_s(0)='0' and stall_s(1)='0') then
if(count_i=(HALF_CORES-1)) then
en_count <= '1';
load_count <= '1';
en_dec <= '1';
else
en_count <= '1';
load_count <= '0';
en_dec <= '1';
end if;
else
en_count <= '0';
load_count <= '0';
en_dec <= '0';
end if;
when DONE =>
stall_o <= '0';
en_count <= '1';
load_count <= '1';
start_s <= '0';
en_input <= '0';
en_dec <= '0';
when others =>
stall_o <= '1';
en_count <= '1';
load_count <= '1';
start_s <= '0';
en_input <= '0';
en_dec <= '0';
end case;
end process;
end structure;
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