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------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, <NAME>
-- Copyright (C) 2015 - 2017, <NAME>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: ddrpkg
-- File: ddrpkg.vhd
-- Author: <NAME> - <NAME>
-- Description: Components and types for DDR SDRAM controllers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
package ddrpkg is
type ddrctrl_in_type is record
-- Data signals
data : std_logic_vector (127 downto 0);-- data in
cb : std_logic_vector(63 downto 0); -- checkbits in
-- Bus/timing control signals
datavalid : std_logic; -- Data-valid signal (DDR2,LPDDR2,LPDDR3)
writereq : std_logic; -- Write-data request (LPDDR2,LPDDR3)
-- Calibration and configuration
regrdata : std_logic_vector(63 downto 0); -- PHY-specific reg in (DDR2)
end record;
constant ddrctrl_in_none : ddrctrl_in_type :=
((others => '0'), (others => '0'), '0', '0', (others => '0'));
type ddrctrl_out_type is record
-- Control signals to memory
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en (DDR1,DDR2,LPDDR1)
rasn : std_ulogic; -- row addr stb (DDR1,DDR2,LPDDR1)
casn : std_ulogic; -- col addr stb (DDR1,DDR2,LPDDR1)
address : std_logic_vector(14 downto 0); -- address out (DDR1,DDR2,LPDDR1)
ba : std_logic_vector (2 downto 0); -- bank address (DDR1,DDR2,LPDDR1)
odt : std_logic_vector(1 downto 0); -- On Die Termination (DDR2,LPDDR3)
ca : std_logic_vector(19 downto 0); -- Ctrl/Addr bus (LPDDR2,LPDDR3)
-- Data signals
data : std_logic_vector(127 downto 0); -- data out
dqm : std_logic_vector(15 downto 0); -- data i/o mask
cb : std_logic_vector(63 downto 0); -- checkbits
cbdqm : std_logic_vector(7 downto 0); -- checkbits data mask
-- Bus/timing control signals
bdrive : std_ulogic; -- bus drive (DDR1,DDR2,LPDDR1)
qdrive : std_ulogic; -- bus drive (DDR1,DDR2,LPDDR1)
nbdrive : std_ulogic; -- bdrive 1 cycle early (DDR2)
sdck : std_logic_vector(2 downto 0); -- Clock enable (DDR1,LPDDR1,LPDDR2,LPDDR3)
moben : std_logic; -- Mobile DDR mode (DDR1/LPDDR1)
oct : std_logic; -- On Chip Termination (DDR2)
dqs_gate : std_logic; -- DQS gate control (DDR2)
read_pend : std_logic_vector(7 downto 0); -- Read pending within 7...0
-- cycles (not including phy
-- delays) (DDR2,LPDDR2,LPDDR3)
wrpend : std_logic_vector(7 downto 0); -- Write pending (LPDDR2,LPDDR3)
boot : std_ulogic; -- Boot clock selection (LPDDR2,LPDDR3)
-- Calibration and configuration
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration (DDR2)
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay (DDR2)
cal_pll : std_logic_vector(1 downto 0); -- (enable,inc/dec) pll phase (DDR2)
cal_rst : std_logic; -- calibration reset (DDR2)
conf : std_logic_vector(63 downto 0); -- Conf. interface (DDR1,LPDDR1)
cbcal_en : std_logic_vector(3 downto 0); -- CB enable delay calib (DDR2)
cbcal_inc : std_logic_vector(3 downto 0); -- CB inc/dec delay (DDR2)
regwdata : std_logic_vector(63 downto 0); -- Reg Write data (DDR2)
regwrite : std_logic_vector(1 downto 0); -- Reg write strobe (DDR2)
-- Status outputs to front-end
ce : std_ulogic; -- Error corrected
end record;
constant ddrctrl_out_none : ddrctrl_out_type :=
((others => '0'), (others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'), '0', '0', '0', (others => '0'),
'0', '0', '0', (others => '0'), (others => '0'), '0', (others => '0'),
(others => '0'), (others => '0'), '0', (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0' );
-----------------------------------------------------------------------------
-- DDR2SPA types and components
-----------------------------------------------------------------------------
-- DDR2 controller without PHY
component ddr2spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
TRFC : integer := 130;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer range 0 to 1 := 0; -- Set to 1 if 8 banks instead of 4
dqsse : integer range 0 to 1 := 0; -- single ended DQS
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
hwidthen : integer range 0 to 1 := 0;
rstdel : integer := 200;
scantest : integer := 0;
cke_rst : integer := 0;
pipe_ctrl : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
hwidth : in std_ulogic
);
end component;
-- DDR2 controller with PHY
component ddr2spa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
TRFC : integer := 130;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
readdly : integer := 1;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1 : integer := 0;
cbdelayb2 : integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
octen : integer := 0;
dqsgating : integer := 0;
nosync : integer := 0;
eightbanks : integer := 0;
dqsse : integer range 0 to 1 := 0;
burstlen : integer range 4 to 128 := 8;
ahbbits : integer := ahbdw;
ft : integer range 0 to 1 := 0;
ftbits : integer := 0;
bigmem : integer range 0 to 1 := 0;
raspipe : integer range 0 to 1 := 0;
nclk : integer range 1 to 3 := 3;
scantest : integer := 0;
ncs : integer := 2;
cke_rst : integer := 0;
pipe_ctrl : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkref200 : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((ddrbits+ftbits)/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits+ftbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
ce : out std_logic;
oct_rdn : in std_logic := '0';
oct_rup : in std_logic := '0'
);
end component;
-- DDR2 PHY with just data or checkbits+data on same bus, including pads
component ddr2phy_wrap_cbd is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2 ;
clk_div : integer := 2;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1 : integer := 0;
cbdelayb2 : integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
ctrl2en : integer := 0;
resync : integer := 0;
custombits : integer := 8;
extraio : integer := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+(dbits+padbits+chkbits)/8-1 downto 0);-- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic;
oct_rdn : in std_logic := '0';
oct_rup : in std_logic := '0'
);
end component;
-- DDR2 PHY with just data or checkbits+data on same bus, not including pads
component ddr2phy_wrap_cbd_wo_pads is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2 ;
clk_div : integer := 2;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1: integer := 0;
cbdelayb2: integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0;
rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
resync : integer := 0;
custombits : integer := 8;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
-- DDR2 PHY with separate checkbit and data buses, including pads
component ddr2phy_wrap
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2;
clk_div : integer := 2;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
cbdelayb0 : integer := 0;
cbdelayb1 : integer := 0;
cbdelayb2 : integer := 0;
cbdelayb3 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
cben : integer := 0;
chkbits : integer := 8;
ctrl2en : integer := 0;
resync : integer := 0;
custombits : integer := 8;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector ((dbits+padbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
ddr_cbdm : out std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqs : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdqsn : inout std_logic_vector(chkbits/8-1 downto 0);
ddr_cbdq : inout std_logic_vector(chkbits-1 downto 0);
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
-----------------------------------------------------------------------------
-- DDRSPA types and components
-----------------------------------------------------------------------------
-- DDR/LPDDR controller, without PHY
component ddr1spax is
generic (
memtech : integer := 0;
phytech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
ahbbits : integer := ahbdw;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
regoutput : integer := 0;
ft : integer := 0;
ddr400 : integer := 1;
rstdel : integer := 200;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
ahb_rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type
);
end component;
-- DDR/LPDDR controller with PHY
component ddrspa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
regoutput : integer range 0 to 1 := 0;
ddr400 : integer := 1;
scantest : integer := 0;
phyiconf : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0) -- ddr data
);
end component;
-- DDR/LPDDR PHY, including pads
component ddrphy_wrap
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0;
mobile : integer := 0;
scantest : integer := 0;
phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic;
clkread : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0);-- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
-- DDR/LPDDR PHY with data and checkbits on same bus, including pads
component ddrphy_wrap_cbd is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
chkbits : integer := 0;
padbits : integer := 0;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0;
mobile : integer := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
scantest : integer := 0;
phyiconf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
-- DDR/LPDDR PHY with data and checkbits on same bus, without pads
component ddrphy_wrap_cbd_wo_pads is
generic (
tech : integer := virtex2;
MHz : integer := 100;
rstdelay : integer := 200;
dbits : integer := 16;
padbits : integer := 0;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0;
mobile : integer := 0;
abits : integer := 14;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
scantest : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic
);
end component;
component lpddr2phy_wrap_cbd_wo_pads is
generic (
tech : integer := virtex2;
dbits : integer := 16;
nclk : integer := 3;
ncs : integer := 2;
chkbits : integer := 0;
padbits : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic; -- input clock
clkin2 : in std_ulogic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkout2 : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0); -- ddr cmd/addr
ddr_dm : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector ((dbits+padbits+chkbits)/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits+padbits+chkbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits+padbits+chkbits-1 downto 0);
sdi : out ddrctrl_in_type;
sdo : in ddrctrl_out_type;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
-----------------------------------------------------------------------------
-- Other components using DDRxSPA sub-components
-----------------------------------------------------------------------------
type ddravl_slv_in_type is record
burstbegin : std_ulogic;
addr : std_logic_vector(31 downto 0);
wdata : std_logic_vector(256 downto 0);
be : std_logic_vector(32 downto 0);
read_req : std_ulogic;
write_req : std_ulogic;
size : std_logic_vector(3 downto 0);
end record;
type ddravl_slv_out_type is record
ready : std_ulogic;
rdata_valid : std_ulogic;
rdata : std_logic_vector(256 downto 0);
end record;
constant ddravl_slv_in_none: ddravl_slv_in_type :=
('0',(others => '0'),(others => '0'),(others => '0'),'0','0',(others => '0'));
component ahb2avl_async is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
avldbits : integer := 32;
avlabits : integer := 20
);
port (
rst_ahb : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
rst_avl : in std_ulogic;
clk_avl : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type
);
end component;
-----------------------------------------------------------------------------
-- MIG wrappers / bridges
-----------------------------------------------------------------------------
component ahb2mig_7series_ddr2_dq16_ad13_ba3
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false);
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_reset_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_i : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic);
end component ;
component ahb2mig_7series_ddr3_dq16_ad14_ba3
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
maxwriteburst : integer := 8;
maxreadburst : integer := 8;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(15 downto 0);
ddr3_dqs_p : inout std_logic_vector(1 downto 0);
ddr3_dqs_n : inout std_logic_vector(1 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(1 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_i : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end component ;
component ahb2mig_7series_ddr3_dq16_ad15_ba3
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
maxwriteburst : integer := 8;
maxreadburst : integer := 8;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(15 downto 0);
ddr3_dqs_p : inout std_logic_vector(1 downto 0);
ddr3_dqs_n : inout std_logic_vector(1 downto 0);
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(1 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_i : in std_logic;
-- clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end component ;
component ahb2mig_7series_ddr3_dq16
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
maxwriteburst : integer := 8;
maxreadburst : integer := 8;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
chipabits : integer := 14; -- number of address bits on the memory
abits : integer := 28; -- number of bits needed to address all RAM memory
banksbits : integer := 3; -- number of bank address bits
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(15 downto 0);
ddr3_dqs_p : inout std_logic_vector(1 downto 0);
ddr3_dqs_n : inout std_logic_vector(1 downto 0);
ddr3_addr : out std_logic_vector(chipabits-1 downto 0);
ddr3_ba : out std_logic_vector(banksbits-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(1 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_i : in std_logic;
-- clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end component;
end package;
|
<gh_stars>10-100
entity test is
file foo : bar open qux is "baz";
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:44:25 09/21/2011
-- Design Name:
-- Module Name: MUXforcmpaddress - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUXforcmpaddress is
port(clk,NRMsignalint:in std_logic;
ap,Qaddressval,ap1,Qaddressval1,ap2,Qaddressval2,ap3,Qaddressval3:in std_logic_vector(8 downto 0);
addrsstomin1,addrsstomin2,addrsstomin3,addrsstomin4:out std_logic_vector(8 downto 0));
end MUXforcmpaddress;
architecture Behavioral of MUXforcmpaddress is
begin
process(clk,NRMsignalint)
begin
if clk'event and clk='1' then
if NRMsignalint='0' then
addrsstomin1<=Qaddressval;
addrsstomin2<=Qaddressval1;
addrsstomin3<=Qaddressval2;
addrsstomin4<=Qaddressval3;
else
addrsstomin1<=ap;
addrsstomin2<=ap1;
addrsstomin3<=ap2;
addrsstomin4<=ap3;
end if;
end if;
end process;
end Behavioral;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNRND.VHD ***
--*** ***
--*** Function: FP LOG Output Block - Rounded ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_lnrnd;
ARCHITECTURE rtl OF fp_lnrnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
|
<filename>src/debouncer.vhd
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity debouncer is
generic(
counter_size : integer := 19);
port(
clk, button : in std_logic;
result : out STD_LOGIC);
end debouncer;
architecture debouncer_arch of debouncer is
signal flipflops : std_logic_vector(1 downto 0);
signal counter_set : std_logic;
signal counter_out : std_logic_vector(counter_size downto 0) := (others => '0');
begin
counter_set <= flipflops(0) xor flipflops(1);
process(clk)
begin
if(clk'event and clk = '1') then
flipflops(0) <= button;
flipflops(1) <= flipflops(0);
if(counter_set = '1') then
counter_out <= (others => '0');
elsif(counter_out(counter_size) = '0') then
counter_out <= counter_out + 1;
else
result <= flipflops(1);
end if;
end if;
end process;
end debouncer_arch;
|
-------------------------------------------------------------------------------
-- microblaze_0_bram_block_elaborate.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity microblaze_0_bram_block_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
attribute keep_hierarchy : STRING;
attribute keep_hierarchy of microblaze_0_bram_block_elaborate : entity is "yes";
end microblaze_0_bram_block_elaborate;
architecture STRUCTURE of microblaze_0_bram_block_elaborate is
component RAMB16BWER is
generic (
INIT_FILE : string;
DATA_WIDTH_A : integer;
DATA_WIDTH_B : integer
);
port (
ADDRA : in std_logic_vector(13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DOA : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
ENA : in std_logic;
REGCEA : in std_logic;
RSTA : in std_logic;
WEA : in std_logic_vector(3 downto 0);
ADDRB : in std_logic_vector(13 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector(31 downto 0);
DIPB : in std_logic_vector(3 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ENB : in std_logic;
REGCEB : in std_logic;
RSTB : in std_logic;
WEB : in std_logic_vector(3 downto 0)
);
end component;
attribute BMM_INFO : STRING;
attribute BMM_INFO of ramb16bwer_0: label is " ";
attribute BMM_INFO of ramb16bwer_1: label is " ";
attribute BMM_INFO of ramb16bwer_2: label is " ";
attribute BMM_INFO of ramb16bwer_3: label is " ";
attribute BMM_INFO of ramb16bwer_4: label is " ";
attribute BMM_INFO of ramb16bwer_5: label is " ";
attribute BMM_INFO of ramb16bwer_6: label is " ";
attribute BMM_INFO of ramb16bwer_7: label is " ";
attribute BMM_INFO of ramb16bwer_8: label is " ";
attribute BMM_INFO of ramb16bwer_9: label is " ";
attribute BMM_INFO of ramb16bwer_10: label is " ";
attribute BMM_INFO of ramb16bwer_11: label is " ";
attribute BMM_INFO of ramb16bwer_12: label is " ";
attribute BMM_INFO of ramb16bwer_13: label is " ";
attribute BMM_INFO of ramb16bwer_14: label is " ";
attribute BMM_INFO of ramb16bwer_15: label is " ";
-- Internal signals
signal net_gnd0 : std_logic;
signal net_gnd4 : std_logic_vector(3 downto 0);
signal pgassign1 : std_logic_vector(0 to 0);
signal pgassign2 : std_logic_vector(0 to 29);
signal pgassign3 : std_logic_vector(13 downto 0);
signal pgassign4 : std_logic_vector(31 downto 0);
signal pgassign5 : std_logic_vector(31 downto 0);
signal pgassign6 : std_logic_vector(3 downto 0);
signal pgassign7 : std_logic_vector(13 downto 0);
signal pgassign8 : std_logic_vector(31 downto 0);
signal pgassign9 : std_logic_vector(31 downto 0);
signal pgassign10 : std_logic_vector(3 downto 0);
signal pgassign11 : std_logic_vector(13 downto 0);
signal pgassign12 : std_logic_vector(31 downto 0);
signal pgassign13 : std_logic_vector(31 downto 0);
signal pgassign14 : std_logic_vector(3 downto 0);
signal pgassign15 : std_logic_vector(13 downto 0);
signal pgassign16 : std_logic_vector(31 downto 0);
signal pgassign17 : std_logic_vector(31 downto 0);
signal pgassign18 : std_logic_vector(3 downto 0);
signal pgassign19 : std_logic_vector(13 downto 0);
signal pgassign20 : std_logic_vector(31 downto 0);
signal pgassign21 : std_logic_vector(31 downto 0);
signal pgassign22 : std_logic_vector(3 downto 0);
signal pgassign23 : std_logic_vector(13 downto 0);
signal pgassign24 : std_logic_vector(31 downto 0);
signal pgassign25 : std_logic_vector(31 downto 0);
signal pgassign26 : std_logic_vector(3 downto 0);
signal pgassign27 : std_logic_vector(13 downto 0);
signal pgassign28 : std_logic_vector(31 downto 0);
signal pgassign29 : std_logic_vector(31 downto 0);
signal pgassign30 : std_logic_vector(3 downto 0);
signal pgassign31 : std_logic_vector(13 downto 0);
signal pgassign32 : std_logic_vector(31 downto 0);
signal pgassign33 : std_logic_vector(31 downto 0);
signal pgassign34 : std_logic_vector(3 downto 0);
signal pgassign35 : std_logic_vector(13 downto 0);
signal pgassign36 : std_logic_vector(31 downto 0);
signal pgassign37 : std_logic_vector(31 downto 0);
signal pgassign38 : std_logic_vector(3 downto 0);
signal pgassign39 : std_logic_vector(13 downto 0);
signal pgassign40 : std_logic_vector(31 downto 0);
signal pgassign41 : std_logic_vector(31 downto 0);
signal pgassign42 : std_logic_vector(3 downto 0);
signal pgassign43 : std_logic_vector(13 downto 0);
signal pgassign44 : std_logic_vector(31 downto 0);
signal pgassign45 : std_logic_vector(31 downto 0);
signal pgassign46 : std_logic_vector(3 downto 0);
signal pgassign47 : std_logic_vector(13 downto 0);
signal pgassign48 : std_logic_vector(31 downto 0);
signal pgassign49 : std_logic_vector(31 downto 0);
signal pgassign50 : std_logic_vector(3 downto 0);
signal pgassign51 : std_logic_vector(13 downto 0);
signal pgassign52 : std_logic_vector(31 downto 0);
signal pgassign53 : std_logic_vector(31 downto 0);
signal pgassign54 : std_logic_vector(3 downto 0);
signal pgassign55 : std_logic_vector(13 downto 0);
signal pgassign56 : std_logic_vector(31 downto 0);
signal pgassign57 : std_logic_vector(31 downto 0);
signal pgassign58 : std_logic_vector(3 downto 0);
signal pgassign59 : std_logic_vector(13 downto 0);
signal pgassign60 : std_logic_vector(31 downto 0);
signal pgassign61 : std_logic_vector(31 downto 0);
signal pgassign62 : std_logic_vector(3 downto 0);
signal pgassign63 : std_logic_vector(13 downto 0);
signal pgassign64 : std_logic_vector(31 downto 0);
signal pgassign65 : std_logic_vector(31 downto 0);
signal pgassign66 : std_logic_vector(3 downto 0);
signal pgassign67 : std_logic_vector(13 downto 0);
signal pgassign68 : std_logic_vector(31 downto 0);
signal pgassign69 : std_logic_vector(31 downto 0);
signal pgassign70 : std_logic_vector(3 downto 0);
signal pgassign71 : std_logic_vector(13 downto 0);
signal pgassign72 : std_logic_vector(31 downto 0);
signal pgassign73 : std_logic_vector(31 downto 0);
signal pgassign74 : std_logic_vector(3 downto 0);
signal pgassign75 : std_logic_vector(13 downto 0);
signal pgassign76 : std_logic_vector(31 downto 0);
signal pgassign77 : std_logic_vector(31 downto 0);
signal pgassign78 : std_logic_vector(3 downto 0);
signal pgassign79 : std_logic_vector(13 downto 0);
signal pgassign80 : std_logic_vector(31 downto 0);
signal pgassign81 : std_logic_vector(31 downto 0);
signal pgassign82 : std_logic_vector(3 downto 0);
signal pgassign83 : std_logic_vector(13 downto 0);
signal pgassign84 : std_logic_vector(31 downto 0);
signal pgassign85 : std_logic_vector(31 downto 0);
signal pgassign86 : std_logic_vector(3 downto 0);
signal pgassign87 : std_logic_vector(13 downto 0);
signal pgassign88 : std_logic_vector(31 downto 0);
signal pgassign89 : std_logic_vector(31 downto 0);
signal pgassign90 : std_logic_vector(3 downto 0);
signal pgassign91 : std_logic_vector(13 downto 0);
signal pgassign92 : std_logic_vector(31 downto 0);
signal pgassign93 : std_logic_vector(31 downto 0);
signal pgassign94 : std_logic_vector(3 downto 0);
signal pgassign95 : std_logic_vector(13 downto 0);
signal pgassign96 : std_logic_vector(31 downto 0);
signal pgassign97 : std_logic_vector(31 downto 0);
signal pgassign98 : std_logic_vector(3 downto 0);
signal pgassign99 : std_logic_vector(13 downto 0);
signal pgassign100 : std_logic_vector(31 downto 0);
signal pgassign101 : std_logic_vector(31 downto 0);
signal pgassign102 : std_logic_vector(3 downto 0);
signal pgassign103 : std_logic_vector(13 downto 0);
signal pgassign104 : std_logic_vector(31 downto 0);
signal pgassign105 : std_logic_vector(31 downto 0);
signal pgassign106 : std_logic_vector(3 downto 0);
signal pgassign107 : std_logic_vector(13 downto 0);
signal pgassign108 : std_logic_vector(31 downto 0);
signal pgassign109 : std_logic_vector(31 downto 0);
signal pgassign110 : std_logic_vector(3 downto 0);
signal pgassign111 : std_logic_vector(13 downto 0);
signal pgassign112 : std_logic_vector(31 downto 0);
signal pgassign113 : std_logic_vector(31 downto 0);
signal pgassign114 : std_logic_vector(3 downto 0);
signal pgassign115 : std_logic_vector(13 downto 0);
signal pgassign116 : std_logic_vector(31 downto 0);
signal pgassign117 : std_logic_vector(31 downto 0);
signal pgassign118 : std_logic_vector(3 downto 0);
signal pgassign119 : std_logic_vector(13 downto 0);
signal pgassign120 : std_logic_vector(31 downto 0);
signal pgassign121 : std_logic_vector(31 downto 0);
signal pgassign122 : std_logic_vector(3 downto 0);
signal pgassign123 : std_logic_vector(13 downto 0);
signal pgassign124 : std_logic_vector(31 downto 0);
signal pgassign125 : std_logic_vector(31 downto 0);
signal pgassign126 : std_logic_vector(3 downto 0);
signal pgassign127 : std_logic_vector(13 downto 0);
signal pgassign128 : std_logic_vector(31 downto 0);
signal pgassign129 : std_logic_vector(31 downto 0);
signal pgassign130 : std_logic_vector(3 downto 0);
begin
-- Internal assignments
pgassign1(0 to 0) <= B"0";
pgassign2(0 to 29) <= B"000000000000000000000000000000";
pgassign3(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign3(0 downto 0) <= B"0";
pgassign4(31 downto 2) <= B"000000000000000000000000000000";
pgassign4(1 downto 0) <= BRAM_Dout_A(0 to 1);
BRAM_Din_A(0 to 1) <= pgassign5(1 downto 0);
pgassign6(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign6(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign6(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign6(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign7(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign7(0 downto 0) <= B"0";
pgassign8(31 downto 2) <= B"000000000000000000000000000000";
pgassign8(1 downto 0) <= BRAM_Dout_B(0 to 1);
BRAM_Din_B(0 to 1) <= pgassign9(1 downto 0);
pgassign10(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign10(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign10(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign10(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign11(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign11(0 downto 0) <= B"0";
pgassign12(31 downto 2) <= B"000000000000000000000000000000";
pgassign12(1 downto 0) <= BRAM_Dout_A(2 to 3);
BRAM_Din_A(2 to 3) <= pgassign13(1 downto 0);
pgassign14(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign14(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign14(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign14(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign15(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign15(0 downto 0) <= B"0";
pgassign16(31 downto 2) <= B"000000000000000000000000000000";
pgassign16(1 downto 0) <= BRAM_Dout_B(2 to 3);
BRAM_Din_B(2 to 3) <= pgassign17(1 downto 0);
pgassign18(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign18(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign18(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign18(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign19(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign19(0 downto 0) <= B"0";
pgassign20(31 downto 2) <= B"000000000000000000000000000000";
pgassign20(1 downto 0) <= BRAM_Dout_A(4 to 5);
BRAM_Din_A(4 to 5) <= pgassign21(1 downto 0);
pgassign22(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign22(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign22(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign22(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign23(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign23(0 downto 0) <= B"0";
pgassign24(31 downto 2) <= B"000000000000000000000000000000";
pgassign24(1 downto 0) <= BRAM_Dout_B(4 to 5);
BRAM_Din_B(4 to 5) <= pgassign25(1 downto 0);
pgassign26(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign26(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign26(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign26(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign27(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign27(0 downto 0) <= B"0";
pgassign28(31 downto 2) <= B"000000000000000000000000000000";
pgassign28(1 downto 0) <= BRAM_Dout_A(6 to 7);
BRAM_Din_A(6 to 7) <= pgassign29(1 downto 0);
pgassign30(3 downto 3) <= BRAM_WEN_A(0 to 0);
pgassign30(2 downto 2) <= BRAM_WEN_A(0 to 0);
pgassign30(1 downto 1) <= BRAM_WEN_A(0 to 0);
pgassign30(0 downto 0) <= BRAM_WEN_A(0 to 0);
pgassign31(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign31(0 downto 0) <= B"0";
pgassign32(31 downto 2) <= B"000000000000000000000000000000";
pgassign32(1 downto 0) <= BRAM_Dout_B(6 to 7);
BRAM_Din_B(6 to 7) <= pgassign33(1 downto 0);
pgassign34(3 downto 3) <= BRAM_WEN_B(0 to 0);
pgassign34(2 downto 2) <= BRAM_WEN_B(0 to 0);
pgassign34(1 downto 1) <= BRAM_WEN_B(0 to 0);
pgassign34(0 downto 0) <= BRAM_WEN_B(0 to 0);
pgassign35(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign35(0 downto 0) <= B"0";
pgassign36(31 downto 2) <= B"000000000000000000000000000000";
pgassign36(1 downto 0) <= BRAM_Dout_A(8 to 9);
BRAM_Din_A(8 to 9) <= pgassign37(1 downto 0);
pgassign38(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign38(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign38(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign38(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign39(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign39(0 downto 0) <= B"0";
pgassign40(31 downto 2) <= B"000000000000000000000000000000";
pgassign40(1 downto 0) <= BRAM_Dout_B(8 to 9);
BRAM_Din_B(8 to 9) <= pgassign41(1 downto 0);
pgassign42(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign42(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign42(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign42(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign43(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign43(0 downto 0) <= B"0";
pgassign44(31 downto 2) <= B"000000000000000000000000000000";
pgassign44(1 downto 0) <= BRAM_Dout_A(10 to 11);
BRAM_Din_A(10 to 11) <= pgassign45(1 downto 0);
pgassign46(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign46(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign46(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign46(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign47(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign47(0 downto 0) <= B"0";
pgassign48(31 downto 2) <= B"000000000000000000000000000000";
pgassign48(1 downto 0) <= BRAM_Dout_B(10 to 11);
BRAM_Din_B(10 to 11) <= pgassign49(1 downto 0);
pgassign50(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign50(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign50(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign50(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign51(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign51(0 downto 0) <= B"0";
pgassign52(31 downto 2) <= B"000000000000000000000000000000";
pgassign52(1 downto 0) <= BRAM_Dout_A(12 to 13);
BRAM_Din_A(12 to 13) <= pgassign53(1 downto 0);
pgassign54(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign54(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign54(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign54(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign55(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign55(0 downto 0) <= B"0";
pgassign56(31 downto 2) <= B"000000000000000000000000000000";
pgassign56(1 downto 0) <= BRAM_Dout_B(12 to 13);
BRAM_Din_B(12 to 13) <= pgassign57(1 downto 0);
pgassign58(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign58(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign58(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign58(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign59(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign59(0 downto 0) <= B"0";
pgassign60(31 downto 2) <= B"000000000000000000000000000000";
pgassign60(1 downto 0) <= BRAM_Dout_A(14 to 15);
BRAM_Din_A(14 to 15) <= pgassign61(1 downto 0);
pgassign62(3 downto 3) <= BRAM_WEN_A(1 to 1);
pgassign62(2 downto 2) <= BRAM_WEN_A(1 to 1);
pgassign62(1 downto 1) <= BRAM_WEN_A(1 to 1);
pgassign62(0 downto 0) <= BRAM_WEN_A(1 to 1);
pgassign63(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign63(0 downto 0) <= B"0";
pgassign64(31 downto 2) <= B"000000000000000000000000000000";
pgassign64(1 downto 0) <= BRAM_Dout_B(14 to 15);
BRAM_Din_B(14 to 15) <= pgassign65(1 downto 0);
pgassign66(3 downto 3) <= BRAM_WEN_B(1 to 1);
pgassign66(2 downto 2) <= BRAM_WEN_B(1 to 1);
pgassign66(1 downto 1) <= BRAM_WEN_B(1 to 1);
pgassign66(0 downto 0) <= BRAM_WEN_B(1 to 1);
pgassign67(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign67(0 downto 0) <= B"0";
pgassign68(31 downto 2) <= B"000000000000000000000000000000";
pgassign68(1 downto 0) <= BRAM_Dout_A(16 to 17);
BRAM_Din_A(16 to 17) <= pgassign69(1 downto 0);
pgassign70(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign70(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign70(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign70(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign71(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign71(0 downto 0) <= B"0";
pgassign72(31 downto 2) <= B"000000000000000000000000000000";
pgassign72(1 downto 0) <= BRAM_Dout_B(16 to 17);
BRAM_Din_B(16 to 17) <= pgassign73(1 downto 0);
pgassign74(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign74(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign74(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign74(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign75(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign75(0 downto 0) <= B"0";
pgassign76(31 downto 2) <= B"000000000000000000000000000000";
pgassign76(1 downto 0) <= BRAM_Dout_A(18 to 19);
BRAM_Din_A(18 to 19) <= pgassign77(1 downto 0);
pgassign78(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign78(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign78(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign78(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign79(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign79(0 downto 0) <= B"0";
pgassign80(31 downto 2) <= B"000000000000000000000000000000";
pgassign80(1 downto 0) <= BRAM_Dout_B(18 to 19);
BRAM_Din_B(18 to 19) <= pgassign81(1 downto 0);
pgassign82(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign82(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign82(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign82(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign83(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign83(0 downto 0) <= B"0";
pgassign84(31 downto 2) <= B"000000000000000000000000000000";
pgassign84(1 downto 0) <= BRAM_Dout_A(20 to 21);
BRAM_Din_A(20 to 21) <= pgassign85(1 downto 0);
pgassign86(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign86(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign86(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign86(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign87(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign87(0 downto 0) <= B"0";
pgassign88(31 downto 2) <= B"000000000000000000000000000000";
pgassign88(1 downto 0) <= BRAM_Dout_B(20 to 21);
BRAM_Din_B(20 to 21) <= pgassign89(1 downto 0);
pgassign90(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign90(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign90(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign90(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign91(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign91(0 downto 0) <= B"0";
pgassign92(31 downto 2) <= B"000000000000000000000000000000";
pgassign92(1 downto 0) <= BRAM_Dout_A(22 to 23);
BRAM_Din_A(22 to 23) <= pgassign93(1 downto 0);
pgassign94(3 downto 3) <= BRAM_WEN_A(2 to 2);
pgassign94(2 downto 2) <= BRAM_WEN_A(2 to 2);
pgassign94(1 downto 1) <= BRAM_WEN_A(2 to 2);
pgassign94(0 downto 0) <= BRAM_WEN_A(2 to 2);
pgassign95(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign95(0 downto 0) <= B"0";
pgassign96(31 downto 2) <= B"000000000000000000000000000000";
pgassign96(1 downto 0) <= BRAM_Dout_B(22 to 23);
BRAM_Din_B(22 to 23) <= pgassign97(1 downto 0);
pgassign98(3 downto 3) <= BRAM_WEN_B(2 to 2);
pgassign98(2 downto 2) <= BRAM_WEN_B(2 to 2);
pgassign98(1 downto 1) <= BRAM_WEN_B(2 to 2);
pgassign98(0 downto 0) <= BRAM_WEN_B(2 to 2);
pgassign99(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign99(0 downto 0) <= B"0";
pgassign100(31 downto 2) <= B"000000000000000000000000000000";
pgassign100(1 downto 0) <= BRAM_Dout_A(24 to 25);
BRAM_Din_A(24 to 25) <= pgassign101(1 downto 0);
pgassign102(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign102(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign102(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign102(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign103(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign103(0 downto 0) <= B"0";
pgassign104(31 downto 2) <= B"000000000000000000000000000000";
pgassign104(1 downto 0) <= BRAM_Dout_B(24 to 25);
BRAM_Din_B(24 to 25) <= pgassign105(1 downto 0);
pgassign106(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign106(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign106(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign106(0 downto 0) <= BRAM_WEN_B(3 to 3);
pgassign107(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign107(0 downto 0) <= B"0";
pgassign108(31 downto 2) <= B"000000000000000000000000000000";
pgassign108(1 downto 0) <= BRAM_Dout_A(26 to 27);
BRAM_Din_A(26 to 27) <= pgassign109(1 downto 0);
pgassign110(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign110(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign110(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign110(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign111(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign111(0 downto 0) <= B"0";
pgassign112(31 downto 2) <= B"000000000000000000000000000000";
pgassign112(1 downto 0) <= BRAM_Dout_B(26 to 27);
BRAM_Din_B(26 to 27) <= pgassign113(1 downto 0);
pgassign114(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign114(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign114(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign114(0 downto 0) <= BRAM_WEN_B(3 to 3);
pgassign115(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign115(0 downto 0) <= B"0";
pgassign116(31 downto 2) <= B"000000000000000000000000000000";
pgassign116(1 downto 0) <= BRAM_Dout_A(28 to 29);
BRAM_Din_A(28 to 29) <= pgassign117(1 downto 0);
pgassign118(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign118(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign118(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign118(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign119(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign119(0 downto 0) <= B"0";
pgassign120(31 downto 2) <= B"000000000000000000000000000000";
pgassign120(1 downto 0) <= BRAM_Dout_B(28 to 29);
BRAM_Din_B(28 to 29) <= pgassign121(1 downto 0);
pgassign122(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign122(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign122(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign122(0 downto 0) <= BRAM_WEN_B(3 to 3);
pgassign123(13 downto 1) <= BRAM_Addr_A(17 to 29);
pgassign123(0 downto 0) <= B"0";
pgassign124(31 downto 2) <= B"000000000000000000000000000000";
pgassign124(1 downto 0) <= BRAM_Dout_A(30 to 31);
BRAM_Din_A(30 to 31) <= pgassign125(1 downto 0);
pgassign126(3 downto 3) <= BRAM_WEN_A(3 to 3);
pgassign126(2 downto 2) <= BRAM_WEN_A(3 to 3);
pgassign126(1 downto 1) <= BRAM_WEN_A(3 to 3);
pgassign126(0 downto 0) <= BRAM_WEN_A(3 to 3);
pgassign127(13 downto 1) <= BRAM_Addr_B(17 to 29);
pgassign127(0 downto 0) <= B"0";
pgassign128(31 downto 2) <= B"000000000000000000000000000000";
pgassign128(1 downto 0) <= BRAM_Dout_B(30 to 31);
BRAM_Din_B(30 to 31) <= pgassign129(1 downto 0);
pgassign130(3 downto 3) <= BRAM_WEN_B(3 to 3);
pgassign130(2 downto 2) <= BRAM_WEN_B(3 to 3);
pgassign130(1 downto 1) <= BRAM_WEN_B(3 to 3);
pgassign130(0 downto 0) <= BRAM_WEN_B(3 to 3);
net_gnd0 <= '0';
net_gnd4(3 downto 0) <= B"0000";
ramb16bwer_0 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_0.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign3,
CLKA => BRAM_Clk_A,
DIA => pgassign4,
DIPA => net_gnd4,
DOA => pgassign5,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign6,
ADDRB => pgassign7,
CLKB => BRAM_Clk_B,
DIB => pgassign8,
DIPB => net_gnd4,
DOB => pgassign9,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign10
);
ramb16bwer_1 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_1.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign11,
CLKA => BRAM_Clk_A,
DIA => pgassign12,
DIPA => net_gnd4,
DOA => pgassign13,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign14,
ADDRB => pgassign15,
CLKB => BRAM_Clk_B,
DIB => pgassign16,
DIPB => net_gnd4,
DOB => pgassign17,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign18
);
ramb16bwer_2 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_2.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign19,
CLKA => BRAM_Clk_A,
DIA => pgassign20,
DIPA => net_gnd4,
DOA => pgassign21,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign22,
ADDRB => pgassign23,
CLKB => BRAM_Clk_B,
DIB => pgassign24,
DIPB => net_gnd4,
DOB => pgassign25,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign26
);
ramb16bwer_3 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_3.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign27,
CLKA => BRAM_Clk_A,
DIA => pgassign28,
DIPA => net_gnd4,
DOA => pgassign29,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign30,
ADDRB => pgassign31,
CLKB => BRAM_Clk_B,
DIB => pgassign32,
DIPB => net_gnd4,
DOB => pgassign33,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign34
);
ramb16bwer_4 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_4.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign35,
CLKA => BRAM_Clk_A,
DIA => pgassign36,
DIPA => net_gnd4,
DOA => pgassign37,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign38,
ADDRB => pgassign39,
CLKB => BRAM_Clk_B,
DIB => pgassign40,
DIPB => net_gnd4,
DOB => pgassign41,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign42
);
ramb16bwer_5 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_5.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign43,
CLKA => BRAM_Clk_A,
DIA => pgassign44,
DIPA => net_gnd4,
DOA => pgassign45,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign46,
ADDRB => pgassign47,
CLKB => BRAM_Clk_B,
DIB => pgassign48,
DIPB => net_gnd4,
DOB => pgassign49,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign50
);
ramb16bwer_6 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_6.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign51,
CLKA => BRAM_Clk_A,
DIA => pgassign52,
DIPA => net_gnd4,
DOA => pgassign53,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign54,
ADDRB => pgassign55,
CLKB => BRAM_Clk_B,
DIB => pgassign56,
DIPB => net_gnd4,
DOB => pgassign57,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign58
);
ramb16bwer_7 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_7.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign59,
CLKA => BRAM_Clk_A,
DIA => pgassign60,
DIPA => net_gnd4,
DOA => pgassign61,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign62,
ADDRB => pgassign63,
CLKB => BRAM_Clk_B,
DIB => pgassign64,
DIPB => net_gnd4,
DOB => pgassign65,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign66
);
ramb16bwer_8 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_8.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign67,
CLKA => BRAM_Clk_A,
DIA => pgassign68,
DIPA => net_gnd4,
DOA => pgassign69,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign70,
ADDRB => pgassign71,
CLKB => BRAM_Clk_B,
DIB => pgassign72,
DIPB => net_gnd4,
DOB => pgassign73,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign74
);
ramb16bwer_9 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_9.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign75,
CLKA => BRAM_Clk_A,
DIA => pgassign76,
DIPA => net_gnd4,
DOA => pgassign77,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign78,
ADDRB => pgassign79,
CLKB => BRAM_Clk_B,
DIB => pgassign80,
DIPB => net_gnd4,
DOB => pgassign81,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign82
);
ramb16bwer_10 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_10.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign83,
CLKA => BRAM_Clk_A,
DIA => pgassign84,
DIPA => net_gnd4,
DOA => pgassign85,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign86,
ADDRB => pgassign87,
CLKB => BRAM_Clk_B,
DIB => pgassign88,
DIPB => net_gnd4,
DOB => pgassign89,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign90
);
ramb16bwer_11 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_11.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign91,
CLKA => BRAM_Clk_A,
DIA => pgassign92,
DIPA => net_gnd4,
DOA => pgassign93,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign94,
ADDRB => pgassign95,
CLKB => BRAM_Clk_B,
DIB => pgassign96,
DIPB => net_gnd4,
DOB => pgassign97,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign98
);
ramb16bwer_12 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_12.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign99,
CLKA => BRAM_Clk_A,
DIA => pgassign100,
DIPA => net_gnd4,
DOA => pgassign101,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign102,
ADDRB => pgassign103,
CLKB => BRAM_Clk_B,
DIB => pgassign104,
DIPB => net_gnd4,
DOB => pgassign105,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign106
);
ramb16bwer_13 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_13.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign107,
CLKA => BRAM_Clk_A,
DIA => pgassign108,
DIPA => net_gnd4,
DOA => pgassign109,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign110,
ADDRB => pgassign111,
CLKB => BRAM_Clk_B,
DIB => pgassign112,
DIPB => net_gnd4,
DOB => pgassign113,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign114
);
ramb16bwer_14 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_14.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign115,
CLKA => BRAM_Clk_A,
DIA => pgassign116,
DIPA => net_gnd4,
DOA => pgassign117,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign118,
ADDRB => pgassign119,
CLKB => BRAM_Clk_B,
DIB => pgassign120,
DIPB => net_gnd4,
DOB => pgassign121,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign122
);
ramb16bwer_15 : RAMB16BWER
generic map (
INIT_FILE => "microblaze_0_bram_block_combined_15.mem",
DATA_WIDTH_A => 2,
DATA_WIDTH_B => 2
)
port map (
ADDRA => pgassign123,
CLKA => BRAM_Clk_A,
DIA => pgassign124,
DIPA => net_gnd4,
DOA => pgassign125,
DOPA => open,
ENA => BRAM_EN_A,
REGCEA => net_gnd0,
RSTA => BRAM_Rst_A,
WEA => pgassign126,
ADDRB => pgassign127,
CLKB => BRAM_Clk_B,
DIB => pgassign128,
DIPB => net_gnd4,
DOB => pgassign129,
DOPB => open,
ENB => BRAM_EN_B,
REGCEB => net_gnd0,
RSTB => BRAM_Rst_B,
WEB => pgassign130
);
end architecture STRUCTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use ieee.numeric_std.all;
entity Multiplier is
port (
Op1 : in std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
Op2 : in std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
Result : out std_logic_vector(31 downto 0));
end Multiplier;
architecture struc of Multiplier is
begin
Result <= std_logic_vector(to_unsigned(to_integer(signed(Op1)) * to_integer(signed(Op2)), 32));
-- Result <= Op1 * Op2;
end struc;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: tech_atc18
-- File: tech_atc18.vhd
-- Author: <NAME> - Gaisler Research
-- Description: Contains Atmel ATC18 specific pads and ram generators
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
package tech_atc18 is
-- sync ram generator
component atc18_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address : in std_logic_vector(abits -1 downto 0);
clk : in clk_type;
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic);
end component;
-- IU regfile generator
component atc18_regfile_iu
generic (rftype : integer := 1; abits : integer := 8; dbits : integer := 32; words : integer := 136);
port (
rst : in std_logic;
clk : in clk_type;
clkn : in clk_type;
rfi : in rf_in_type;
rfo : out rf_out_type);
end component;
component atc18_regfile_cp
generic (
abits : integer := 4;
dbits : integer := 32;
words : integer := 16
);
port (
rst : in std_logic;
clk : in clk_type;
rfi : in rf_cp_in_type;
rfo : out rf_cp_out_type);
end component;
component atc18_dpram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address1 : in std_logic_vector((abits -1) downto 0);
clk1 : in clk_type;
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_logic;
write1 : in std_logic;
address2 : in std_logic_vector((abits -1) downto 0);
clk2 : in clk_type;
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_logic;
write2 : in std_logic
);
end component;
-- input pads, all others pads are taken from the atc25 package
component atc18_inpad
port (pad : in std_logic; q : out std_logic);
end component;
component atc18_smpad
port (pad : in std_logic; q : out std_logic);
end component;
end;
------------------------------------------------------------------
-- behavioural pad models --------------------------------------------
------------------------------------------------------------------
-- Only needed for simulation, not synthesis.
-- pragma translate_off
-- input pad
library IEEE;
use IEEE.std_logic_1164.all;
entity pc33d00 is port (pad : in std_logic; cin : out std_logic); end;
architecture rtl of pc33d00 is begin cin <= to_x01(pad) after 1 ns; end;
-- input schmitt pad
library IEEE;
use IEEE.std_logic_1164.all;
entity pc33d20 is port (pad : in std_logic; cin : out std_logic); end;
architecture rtl of pc33d20 is begin cin <= to_x01(pad) after 1 ns; end;
------------------------------------------------------------------
-- behavioural ram models ----------------------------------------
------------------------------------------------------------------
-- synchronous 1-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity atc18_syncram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end;
architecture behavioral of atc18_syncram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clk, oe, me)
variable memarr : mem;
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clk) and (me = '1') and not is_x(addr) then
if (we = '1') then memarr(conv_integer(unsigned(addr))) := di; end if;
doint := memarr(conv_integer(unsigned(addr)));
end if;
if (me and oe) = '1' then do <= doint;
else do <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous 2-port ram
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity atc18_2pram_sim is
generic (
abits : integer := 10;
dbits : integer := 8;
words : integer := 1024
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end;
architecture behavioral of atc18_2pram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (words-1)) of word;
begin
main : process(clka, clkb, oeb, mea, meb, wea)
variable memarr : mem;
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(conv_integer(unsigned(addra)) mod words) := dia; end if;
end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
doint := memarr(conv_integer(unsigned(addrb)) mod words);
end if;
if oeb = '1' then dob <= doint;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous dual-port ram
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity atc18_dpram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end;
architecture behavioral of atc18_dpram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clka, oea, mea, clkb, oeb, meb)
variable memarr : mem;
variable dointa, dointb : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(conv_integer(unsigned(addra))) := dia; end if;
dointa := memarr(conv_integer(unsigned(addra)));
end if;
if (mea and oea) = '1' then doa <= dointa;
else doa <= (others => 'Z'); end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
if (web = '1') then memarr(conv_integer(unsigned(addrb))) := dib; end if;
dointb := memarr(conv_integer(unsigned(addrb)));
end if;
if oeb = '1' then dob <= dointb;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
-- package with common ram simulation models
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.iface.all;
package tech_atc18_sim is
component atc18_syncram_sim
generic ( abits : integer := 10; dbits : integer := 8 );
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end component;
-- synchronous 2-port ram
component atc18_2pram_sim
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end component;
component atc18_dpram_sim
generic (
abits : integer := 8;
dbits : integer := 32
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end component;
end;
-- 1-port syncronous ram
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_atc18_sim.all;
entity hdss1_128x32cm4sw0 is
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_128x32cm4sw0 is
begin
syncram0 : atc18_syncram_sim
generic map ( abits => 7, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_atc18_sim.all;
entity hdss1_256x32cm4sw0 is
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_256x32cm4sw0 is
begin
syncram0 : atc18_syncram_sim
generic map ( abits => 8, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_atc18_sim.all;
entity hdss1_512x32cm4sw0 is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x32cm4sw0 is
begin
syncram0 : atc18_syncram_sim
generic map ( abits => 9, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_atc18_sim.all;
entity hdss1_1024x32cm4sw0 is
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_1024x32cm4sw0 is
begin
syncram0 : atc18_syncram_sim
generic map ( abits => 10, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_atc18_sim.all;
entity hdss1_2048x32cm8sw0 is
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_2048x32cm8sw0 is
begin
syncram0 : atc18_syncram_sim
generic map ( abits => 11, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
-- 2-port syncronous ram
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_atc18_sim.all;
entity rfss2_136x32cm2sw0 is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x32cm2sw0 is
begin
syncram0 : atc18_2pram_sim
generic map ( abits => 8, dbits => 32, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_atc18_sim.all;
entity rfss2_168x32cm2sw0 is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_168x32cm2sw0 is
begin
syncram0 : atc18_2pram_sim
generic map ( abits => 8, dbits => 32, words => 168)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
-- dual-port syncronous ram
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.tech_atc18_sim.all;
entity hdss2_64x32cm4sw0 is
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_64x32cm4sw0 is
begin
syncram0 : atc18_dpram_sim
generic map ( abits => 6, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_atc18_sim.all;
entity hdss2_128x32cm4sw0 is
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_128x32cm4sw0 is
begin
syncram0 : atc18_dpram_sim
generic map ( abits => 7, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_atc18_sim.all;
entity hdss2_256x32cm4sw0 is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_256x32cm4sw0 is
begin
syncram0 : atc18_dpram_sim
generic map ( abits => 8, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use IEEE.std_logic_1164.all;
use work.tech_atc18_sim.all;
entity hdss2_512x32cm4sw0 is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x32cm4sw0 is
begin
syncram0 : atc18_dpram_sim
generic map ( abits => 9, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
-- pragma translate_on
-- component declarations from true tech library
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package tech_atc18_syn is
component hdss1_128x32cm4sw0
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_256x32cm4sw0
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_512x32cm4sw0
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_1024x32cm4sw0
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component hdss1_2048x32cm8sw0
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end component;
component rfss2_136x32cm2sw0
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end component;
component rfss2_168x32cm2sw0
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_64x32cm4sw0
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_128x32cm4sw0
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_256x32cm4sw0
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
component hdss2_512x32cm4sw0
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end component;
-- input pad
component pc33d00 port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad
component pc33d20 port (pad : in std_logic; cin : out std_logic); end component;
end;
------------------------------------------------------------------
-- sync ram generator --------------------------------------------
------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_atc18_syn.all;
use work.iface.all;
entity atc18_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address : in std_logic_vector(abits -1 downto 0);
clk : in clk_type;
datain : in std_logic_vector(dbits -1 downto 0);
dataout : out std_logic_vector(dbits -1 downto 0);
enable : in std_logic;
write : in std_logic
);
end;
architecture rtl of atc18_syncram is
signal d, q, gnd : std_logic_vector(35 downto 0);
signal a : std_logic_vector(17 downto 0);
signal vcc : std_logic;
constant synopsys_bug : std_logic_vector(37 downto 0) := (others => '0');
begin
gnd <= (others => '0'); vcc <= '1';
a(abits -1 downto 0) <= address;
d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
a(17 downto abits) <= synopsys_bug(17 downto abits);
d(35 downto dbits) <= synopsys_bug(35 downto dbits);
dataout <= q(dbits -1 downto 0);
q(35 downto dbits) <= synopsys_bug(35 downto dbits);
a7d32 : if (abits <= 7) and (dbits <= 32) generate
id0 : hdss1_128x32cm4sw0
port map (a(6 downto 0), gnd(6 downto 0), clk ,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a8d32 : if (abits = 8) and (dbits <= 32) generate
id0 : hdss1_256x32cm4sw0
port map (a(7 downto 0), gnd(7 downto 0), clk ,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d32 : if (abits = 9) and (dbits <= 32) generate
id0 : hdss1_512x32cm4sw0
port map (address(8 downto 0), gnd(8 downto 0), clk ,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a10d32 : if (abits = 10) and (dbits <= 32) generate
id0 : hdss1_1024x32cm4sw0
port map (address(9 downto 0), gnd(9 downto 0), clk ,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a11d32 : if (abits = 11) and (dbits <= 32) generate
id0 : hdss1_2048x32cm8sw0
port map (address(10 downto 0), gnd(10 downto 0), clk ,
d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
end rtl;
------------------------------------------------------------------
-- sync dpram generator --------------------------------------------
------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.tech_atc18_syn.all;
use work.iface.all;
entity atc18_dpram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
address1 : in std_logic_vector((abits -1) downto 0);
clk1 : in clk_type;
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_logic;
write1 : in std_logic;
address2 : in std_logic_vector((abits -1) downto 0);
clk2 : in clk_type;
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_logic;
write2 : in std_logic
);
end;
architecture rtl of atc18_dpram is
signal vcc : std_logic;
signal d1, d2, a1, a2, q1, q2, gnd : std_logic_vector(35 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
d1(dbits-1 downto 0) <= datain1; d1(35 downto dbits) <= (others => '0');
d2(dbits-1 downto 0) <= datain2; d2(35 downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= address1; a1(35 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= address2; a2(35 downto abits) <= (others => '0');
dataout1 <= q1(dbits-1 downto 0); dataout2 <= q2(dbits-1 downto 0);
a6d32 : if (abits <= 6) and (dbits <= 32) generate
id0 : hdss2_64x32cm4sw0
port map (a1(5 downto 0), gnd(5 downto 0), a2(5 downto 0),
gnd(5 downto 0), clk1 , clk2 ,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a7d32 : if (abits = 7) and (dbits <= 32) generate
id0 : hdss2_128x32cm4sw0
port map (a1(6 downto 0), gnd(6 downto 0), a2(6 downto 0),
gnd(6 downto 0), clk1 , clk2 ,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a8d32 : if (abits = 8) and (dbits <= 32) generate
id0 : hdss2_256x32cm4sw0
port map (a1(7 downto 0), gnd(7 downto 0), a2(7 downto 0),
gnd(7 downto 0), clk1 , clk2 ,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
a9d32 : if (abits = 9) and (dbits <= 32) generate
id0 : hdss2_512x32cm4sw0
port map (a1(8 downto 0), gnd(8 downto 0), a2(8 downto 0),
gnd(8 downto 0), clk1 , clk2 ,
d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
q1(31 downto 0), q2(31 downto 0),
enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
end generate;
end;
------------------------------------------------------------------
-- regfile generator --------------------------------------------
------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.tech_generic.all;
use work.tech_atc18_syn.all;
use work.iface.all;
use work.config.all;
entity atc18_regfile_iu is
generic (
rftype : integer := 1;
abits : integer := 8;
dbits : integer := 32;
words : integer := 136
);
port (
rst : in std_logic;
clk : in clk_type;
clkn : in clk_type;
rfi : in rf_in_type;
rfo : out rf_out_type);
end;
architecture rtl of atc18_regfile_iu is
signal din1, din2, qq1, qq2, gnd : std_logic_vector(39 downto 0);
signal vcc : std_logic;
signal ra1, ra2, wa : std_logic_vector(14 downto 0);
begin
vcc <= '1'; gnd <= (others => '0');
ra1(abits-1 downto 0) <= rfi.rd1addr;
ra2(abits-1 downto 0) <= rfi.rd2addr;
wa(abits-1 downto 0) <= rfi.wraddr;
din1(dbits-1 downto 0) <= rfi.wrdata;
din2(dbits-1 downto 0) <= rfi.wrdata;
wa(14 downto abits) <= gnd(14 downto abits);
ra1(14 downto abits) <= gnd(14 downto abits);
ra2(14 downto abits) <= gnd(14 downto abits);
din1(39 downto dbits) <= (others => '0');
din2(39 downto dbits) <= (others => '0');
rf136x32 : if (words <= 136) and (dbits = 32) generate
id0 : rfss2_136x32cm2sw0 port map (
wa(7 downto 0), gnd(7 downto 0), ra1(7 downto 0), gnd(7 downto 0),
clk , clkn , din1(31 downto 0), gnd(31 downto 0), qq1(31 downto 0), vcc,
rfi.wren, gnd(0), gnd(0), gnd(0), vcc, vcc, gnd(0), gnd(0),gnd(0), gnd(0));
id1 : rfss2_136x32cm2sw0 port map (
wa(7 downto 0), gnd(7 downto 0), ra2(7 downto 0), gnd(7 downto 0),
clk , clkn , din2(31 downto 0), gnd(31 downto 0), qq2(31 downto 0), vcc,
rfi.wren, gnd(0), gnd(0), gnd(0), vcc, vcc, gnd(0), gnd(0),gnd(0), gnd(0));
end generate;
rf168x32 : if (words <= 168) and (words > 136) and (dbits = 32) generate
id0 : rfss2_168x32cm2sw0 port map (
wa(7 downto 0), gnd(7 downto 0), ra1(7 downto 0), gnd(7 downto 0),
clk , clkn , din1(31 downto 0), gnd(31 downto 0), qq1(31 downto 0), vcc,
rfi.wren, gnd(0), gnd(0), gnd(0), vcc, vcc, gnd(0), gnd(0),gnd(0), gnd(0));
id1 : rfss2_168x32cm2sw0 port map (
wa(7 downto 0), gnd(7 downto 0), ra2(7 downto 0), gnd(7 downto 0),
clk , clkn , din2(31 downto 0), gnd(31 downto 0), qq2(31 downto 0), vcc,
rfi.wren, gnd(0), gnd(0), gnd(0), vcc, vcc, gnd(0), gnd(0),gnd(0), gnd(0));
end generate;
rfo.data1(dbits-1 downto 0) <= qq1(dbits-1 downto 0);
rfo.data2(dbits-1 downto 0) <= qq2(dbits-1 downto 0);
end;
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.tech_generic.all;
use work.tech_atc18_syn.all;
use work.iface.all;
entity atc18_regfile_cp is
generic (
abits : integer := 4;
dbits : integer := 32;
words : integer := 16
);
port (
rst : in std_logic;
clk : in clk_type;
rfi : in rf_cp_in_type;
rfo : out rf_cp_out_type);
end;
architecture rtl of atc18_regfile_cp is
signal din1, qq1, qq2 : std_logic_vector(39 downto 0);
signal wa : std_logic_vector(abits-1 downto 0);
signal vcc, gnd, wen : std_logic;
begin
vcc <= '1'; gnd <= '0';
rfo.data1(dbits-1 downto 0) <= qq1(dbits-1 downto 0);
rfo.data2(dbits-1 downto 0) <= qq2(dbits-1 downto 0);
end;
------------------------------------------------------------------
-- mapping generic pads on tech pads ---------------------------------
------------------------------------------------------------------
-- input pad
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc18_syn.all;
entity atc18_inpad is port (pad : in std_logic; q : out std_logic); end;
architecture syn of atc18_inpad is begin
i0 : pc33d00 port map (pad => pad, cin => q);
end;
-- input schmitt pad
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc18_syn.all;
entity atc18_smpad is port (pad : in std_logic; q : out std_logic); end;
architecture syn of atc18_smpad is begin
i0 : pc33d20 port map (pad => pad, cin => q);
end;
|
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`protect end_protected
|
-- args: --std=08 --ieee=synopsys
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.configure.all;
use work.constants.all;
use work.functions.all;
use work.dwire.all;
entity ddata is
generic(
cache_sets : integer;
cache_ways : integer;
cache_words : integer
);
port(
reset : in std_logic;
clock : in std_logic;
data_i : in ddata_in_type;
data_o : out ddata_out_type
);
end ddata;
architecture behavior of ddata is
type data_type is array (0 to 2**cache_sets-1) of std_logic_vector((2**cache_words)*64-1 downto 0);
signal data_array : data_type := (others => (others => '0'));
signal rdata : std_logic_vector((2**cache_words)*64-1 downto 0) := (others => '0');
begin
data_o.rdata <= rdata;
process(clock)
begin
if rising_edge(clock) then
if data_i.wen = '1' then
data_array(data_i.waddr) <= data_i.wdata;
end if;
rdata <= data_array(data_i.raddr);
end if;
end process;
end architecture;
|
-- Testbench for 74151 TTL multiplexor
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
-- empty
end testbench;
architecture tb of testbench is
-- DUT component
component TTL74151 is
port(
pin1_d3: in std_logic;
pin2_d2 : in std_logic;
pin3_d1: in std_logic;
pin4_d0: in std_logic;
pin5_y : out std_logic;
pin6_w : out std_logic;
pin7_ng : in std_logic;
pin9_c : in std_logic;
pin10_b : in std_logic;
pin11_a : in std_logic;
pin12_d7 : in std_logic;
pin13_d6 : in std_logic;
pin14_d5 : in std_logic;
pin15_d4 : in std_logic);
end component;
signal d3,d2,d1,d0,y,w,ng, c,b,a,d7,d6,d5,d4: std_logic;
begin
-- Connect DUT
DUT: TTL74151 port map(d3,d2,d1,d0,y,w,ng,c,b,a,d7,d6,d5,d4);
process
begin
d3 <= 'X';
d2 <= 'X';
d1 <= 'X';
d0 <= 'X';
c <= 'X';
b <= 'X';
a <= 'X';
ng <= '1';
d7 <= 'X';
d6 <= 'X';
d5 <= 'X';
d4 <= 'X';
wait for 100 ns;
assert (y = '0') report "Fail qA not cleared" severity error;
assert (w = '1') report "Fail qB not cleared" severity error;
d3 <= 'X';
d2 <= 'X';
d1 <= 'X';
d0 <= '0';
c <= '0';
b <= '0';
a <= '0';
ng <= '0';
d7 <= 'X';
d6 <= 'X';
d5 <= 'X';
d4 <= 'X';
wait for 100 ns;
assert (y = '0') report "Fail Y not cleared" severity error;
assert (w = '1') report "Fail W not set" severity error;
d3 <= 'X';
d2 <= 'X';
d1 <= 'X';
d0 <= '1';
c <= '0';
b <= '0';
a <= '0';
ng <= '0';
d7 <= 'X';
d6 <= 'X';
d5 <= 'X';
d4 <= 'X';
wait for 100 ns;
assert (y = '1') report "Fail Y not cleared" severity error;
assert (w = '0') report "Fail W not set" severity error;
d3 <= 'X';
d2 <= 'X';
d1 <= '0';
d0 <= 'X';
c <= '0';
b <= '0';
a <= '1';
ng <= '0';
d7 <= 'X';
d6 <= 'X';
d5 <= 'X';
d4 <= 'X';
wait for 100 ns;
assert (y = '0') report "Fail Y not cleared" severity error;
assert (w = '1') report "Fail W not set" severity error;
d3 <= 'X';
d2 <= 'X';
d1 <= '1';
d0 <= 'X';
c <= '0';
b <= '0';
a <= '1';
ng <= '0';
d7 <= 'X';
d6 <= 'X';
d5 <= 'X';
d4 <= 'X';
wait for 100 ns;
assert (y = '1') report "Fail Y not cleared" severity error;
assert (w = '0') report "Fail W not set" severity error;
d3 <= 'X';
d2 <= '0';
d1 <= 'X';
d0 <= 'X';
c <= '0';
b <= '1';
a <= '0';
ng <= '0';
d7 <= 'X';
d6 <= 'X';
d5 <= 'X';
d4 <= 'X';
wait for 100 ns;
assert (y = '0') report "Fail Y not cleared" severity error;
assert (w = '1') report "Fail W not set" severity error;
d3 <= 'X';
d2 <= '1';
d1 <= 'X';
d0 <= 'X';
c <= '0';
b <= '1';
a <= '0';
ng <= '0';
d7 <= 'X';
d6 <= 'X';
d5 <= 'X';
d4 <= 'X';
wait for 100 ns;
assert (y = '1') report "Fail Y not cleared" severity error;
assert (w = '0') report "Fail W not set" severity error;
d3 <= '0';
d2 <= 'X';
d1 <= 'X';
d0 <= 'X';
c <= '0';
b <= '1';
a <= '1';
ng <= '0';
d7 <= 'X';
d6 <= 'X';
d5 <= 'X';
d4 <= 'X';
wait for 100 ns;
assert (y = '0') report "Fail Y not cleared" severity error;
assert (w = '1') report "Fail W not set" severity error;
d3 <= '1';
d2 <= 'X';
d1 <= 'X';
d0 <= 'X';
c <= '0';
b <= '1';
a <= '1';
ng <= '0';
d7 <= 'X';
d6 <= 'X';
d5 <= 'X';
d4 <= 'X';
wait for 100 ns;
assert (y = '1') report "Fail Y not cleared" severity error;
assert (w = '0') report "Fail W not set" severity error;
d3 <= 'X';
d2 <= 'X';
d1 <= 'X';
d0 <= 'X';
c <= '1';
b <= '0';
a <= '0';
ng <= '0';
d7 <= 'X';
d6 <= 'X';
d5 <= 'X';
d4 <= '0';
wait for 100 ns;
assert (y = '0') report "Fail Y not cleared" severity error;
assert (w = '1') report "Fail W not set" severity error;
d3 <= 'X';
d2 <= 'X';
d1 <= 'X';
d0 <= 'X';
c <= '1';
b <= '0';
a <= '0';
ng <= '0';
d7 <= 'X';
d6 <= 'X';
d5 <= 'X';
d4 <= '1';
wait for 100 ns;
assert (y = '1') report "Fail Y not cleared" severity error;
assert (w = '0') report "Fail W not set" severity error;
d3 <= 'X';
d2 <= 'X';
d1 <= 'X';
d0 <= 'X';
c <= '1';
b <= '0';
a <= '1';
ng <= '0';
d7 <= 'X';
d6 <= 'X';
d5 <= '0';
d4 <= 'X';
wait for 100 ns;
assert (y = '0') report "Fail Y not cleared" severity error;
assert (w = '1') report "Fail W not set" severity error;
d3 <= 'X';
d2 <= 'X';
d1 <= 'X';
d0 <= 'X';
c <= '1';
b <= '0';
a <= '1';
ng <= '0';
d7 <= 'X';
d6 <= 'X';
d5 <= '1';
d4 <= 'X';
wait for 100 ns;
assert (y = '1') report "Fail Y not cleared" severity error;
assert (w = '0') report "Fail W not set" severity error;
d3 <= 'X';
d2 <= 'X';
d1 <= 'X';
d0 <= 'X';
c <= '1';
b <= '1';
a <= '0';
ng <= '0';
d7 <= 'X';
d6 <= '0';
d5 <= 'X';
d4 <= 'X';
wait for 100 ns;
assert (y = '0') report "Fail Y not cleared" severity error;
assert (w = '1') report "Fail W not set" severity error;
d3 <= 'X';
d2 <= 'X';
d1 <= 'X';
d0 <= 'X';
c <= '1';
b <= '1';
a <= '0';
ng <= '0';
d7 <= 'X';
d6 <= '1';
d5 <= 'X';
d4 <= 'X';
wait for 100 ns;
assert (y = '1') report "Fail Y not cleared" severity error;
assert (w = '0') report "Fail W not set" severity error;
d3 <= 'X';
d2 <= 'X';
d1 <= 'X';
d0 <= 'X';
c <= '1';
b <= '1';
a <= '1';
ng <= '0';
d7 <= '0';
d6 <= 'X';
d5 <= 'X';
d4 <= 'X';
wait for 100 ns;
assert (y = '0') report "Fail Y not cleared" severity error;
assert (w = '1') report "Fail W not set" severity error;
d3 <= 'X';
d2 <= 'X';
d1 <= 'X';
d0 <= 'X';
c <= '1';
b <= '1';
a <= '1';
ng <= '0';
d7 <= '1';
d6 <= 'X';
d5 <= 'X';
d4 <= 'X';
wait for 100 ns;
assert (y = '1') report "Fail Y not cleared" severity error;
assert (w = '0') report "Fail W not set" severity error;
assert false report "Test done." severity note;
wait;
end process;
end tb;
|
<filename>src/dp_ram.vhd<gh_stars>1-10
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--------------------------------------------------------------------------------
-- Dual port RAM
--------------------------------------------------------------------------------
entity dp_ram is
generic (
ELEMENTS : integer := 21760;
ELEMENT_SIZE : integer := 16;
RAM_TYPE : string := "block"
);
port (
clk : in std_logic;
aresetn : in std_logic;
wr : in std_logic;
wraddr : in integer range 0 to ELEMENTS-1;
wrdata : in std_logic_vector(ELEMENT_SIZE-1 downto 0);
rd : in std_logic;
rdaddr : in integer range 0 to ELEMENTS-1;
rddata : out std_logic_vector(ELEMENT_SIZE-1 downto 0)
);
end dp_ram;
architecture rtl of dp_ram is
type ram_t is array (0 to ELEMENTS-1) of std_logic_vector(ELEMENT_SIZE-1 downto 0);
signal ram : ram_t := (others => (others => '0'));
attribute ram_style : string;
attribute ram_style of ram : signal is RAM_TYPE;
begin
process (clk)
begin
if (rising_edge(clk)) then
if (rd = '1') then
rddata <= ram(rdaddr);
end if;
end if;
end process;
process (clk)
begin
if (rising_edge(clk)) then
if (wr = '1') then
ram(wraddr) <= wrdata;
end if;
end if;
end process;
end rtl;
|
-- How this works:
-- The process is used whenever a particular signal changes.
--
-- A signal could change when a new result is computed, and/or the ALU
-- opcode changes.
--
-- The circuit basically works with all the inputs connected to each math unit
-- When the multiplexer matches an opcode, that channel is opened, and the result
-- from whatever math unit is moved into the output line.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
entity al_unit is
port (
A, B : in std_logic_vector(7 downto 0);
OP : in std_logic_vector(3 downto 0);
F : out std_logic_vector(7 downto 0)
);
end al_unit;
architecture behavioral of al_unit is
-- The adder
component adder
port (
vec1, vec2 : in std_logic_vector(7 downto 0);
out_vec : out std_logic_vector(7 downto 0);
co : out std_logic
);
end component;
-- The subtractor
component subtractor
port (
A, B : in std_logic_vector(7 downto 0);
F : out std_logic_vector(7 downto 0)
);
end component;
-- The left-shifter
component lshift
port (
A, B : in std_logic_vector(7 downto 0);
F : out std_logic_vector(7 downto 0)
);
end component;
-- The right-shifter
component rshift
port (
A, B : in std_logic_vector(7 downto 0);
F : out std_logic_vector(7 downto 0)
);
end component;
-- The 8-bit AND
component and8
port (
A, B : in std_logic_vector(7 downto 0);
F : out std_logic_vector(7 downto 0)
);
end component;
-- The 8-bit OR
component or8
port (
A, B : in std_logic_vector(7 downto 0);
F : out std_logic_vector(7 downto 0)
);
end component;
-- The 8-bit XOR
component xor8
port (
A, B : in std_logic_vector(7 downto 0);
F : out std_logic_vector(7 downto 0)
);
end component;
-- The 8-bit NOT
component not8
port (
A : in std_logic_vector(7 downto 0);
F : out std_logic_vector(7 downto 0)
);
end component;
-- The negate (2's complement) unit
component negate
port (
A : in std_logic_vector(7 downto 0);
F : out std_logic_vector(7 downto 0)
);
end component;
-- The signals
signal add_out : std_logic_vector(7 downto 0);
signal subtract_out : std_logic_vector(7 downto 0);
signal lshift_out : std_logic_vector(7 downto 0);
signal rshift_out : std_logic_vector(7 downto 0);
signal and_out : std_logic_vector(7 downto 0);
signal or_out : std_logic_vector(7 downto 0);
signal xor_out : std_logic_vector(7 downto 0);
signal not_out : std_logic_vector(7 downto 0);
signal negate_out : std_logic_vector(7 downto 0);
signal inc_out : std_logic_vector(7 downto 0);
signal dec_out : std_logic_vector(7 downto 0);
-- Constants
constant one : std_logic_vector(7 downto 0) := "00000001";
begin
add : adder port map(vec1 => A, vec2 => B, out_vec => add_out, co => open);
sub : subtractor port map(A => A, B => B, F => subtract_out);
lsh : lshift port map(A => A, B => B, F => lshift_out);
rsh : rshift port map(A => A, B => B, F => rshift_out);
and8_0 : and8 port map(A => A, B => B, F => and_out);
or8_0 : or8 port map(A => A, B => B, F => or_out);
xor8_0 : xor8 port map(A => A, B => B, F => xor_out);
not8_0 : not8 port map(A => A, F => not_out);
neg : negate port map(A => A, F => negate_out);
inc : adder port map(vec1 => A, vec2 => one, out_vec => inc_out, co => open);
dec : subtractor port map(A => A, B => one, F => dec_out);
process (add_out, subtract_out,
lshift_out, rshift_out,
and_out, or_out, xor_out, not_out,
negate_out,
inc_out, dec_out,
OP) is
begin
case OP is
when "0000" => F <= add_out; -- Add
when "0001" => F <= subtract_out; -- Subtract
when "0010" => F <= rshift_out; -- Right-shift
when "0011" => F <= lshift_out; -- Left-shift
when "0100" => F <= and_out; -- And
when "0101" => F <= or_out; -- Or
when "0110" => F <= xor_out; -- Xor
when "0111" => F <= not_out; -- Not
when "1000" => F <= negate_out; -- 2's complement
when "1001" => F <= inc_out; -- Increment
when "1010" => F <= dec_out; -- Decrement
when others => F <= (others => 'X');
end case;
end process;
end behavioral;
|
<filename>src/subbytes.vhd<gh_stars>1-10
library project
use project.aes.all;
library ieee;
use ieee.std_logic_1164.all;
entity subbytes is
port(
inMat : in Matrix;
outMat : out Matrix
);
end entity subbytes;
architecture behaviour of subbytes is
component sbox is
port(
inByte : in Byte;
outByte : out Byte
);
end component sbox;
begin:
sbox_00: sbox port map(
inByte => inMat(0)(0);
outByte => outMat(0)(0);
);
sbox_01: sbox port map(
inByte => inMat(0)(1);
outByte => outMat(0)(1);
);
sbox_02: sbox port map(
inByte => inMat(0)(2);
outByte => outMat(0)(2);
);
sbox_03: sbox port map(
inByte => inMat(0)(3);
outByte => outMat(0)(3);
);
sbox_10: sbox port map(
inByte => inMat(1)(0);
outByte => outMat(1)(0);
);
sbox_11: sbox port map(
inByte => inMat(1)(1);
outByte => outMat(1)(1);
);
sbox_12: sbox port map(
inByte => inMat(1)(2);
outByte => outMat(1)(2);
);
sbox_13: sbox port map(
inByte => inMat(1)(3);
outByte => outMat(1)(3);
);
sbox_20: sbox port map(
inByte => inMat(2)(0);
outByte => outMat(2)(0);
);
sbox_21: sbox port map(
inByte => inMat(2)(1);
outByte => outMat(2)(1);
);
sbox_22: sbox port map(
inByte => inMat(2)(2);
outByte => outMat(2)(2);
);
sbox_23: sbox port map(
inByte => inMat(2)(3);
outByte => outMat(2)(3);
);
sbox_30: sbox port map(
inByte => inMat(3)(0);
outByte => outMat(3)(0);
);
sbox_31: sbox port map(
inByte => inMat(3)(1);
outByte => outMat(3)(1);
);
sbox_32: sbox port map(
inByte => inMat(3)(2);
outByte => outMat(3)(2);
);
sbox_33: sbox port map(
inByte => inMat(3)(3);
outByte => outMat(3)(3);
);
end behaviour;
|
-------------------------------------------------------------------------------
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description: SLV array to AXI-Lite Master Bridge
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC Firmware Standard Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library surf;
use surf.StdRtlPkg.all;
use surf.AxiLitePkg.all;
entity SlvArraytoAxiLite is
generic (
TPD_G : time := 1 ns;
COMMON_CLK_G : boolean := false; -- Set true if axilClk = clk
SIZE_G : positive := 1;
ADDR_G : Slv32Array := (0 => x"00000000"));
port (
-- SLV Array Interface
clk : in sl;
rst : in sl;
input : in Slv32Array(SIZE_G-1 downto 0);
-- AXI-Lite Master Interface
axilClk : in sl;
axilRst : in sl;
axilReadMaster : out AxiLiteReadMasterType;
axilReadSlave : in AxiLiteReadSlaveType;
axilWriteMaster : out AxiLiteWriteMasterType;
axilWriteSlave : in AxiLiteWriteSlaveType);
end entity SlvArraytoAxiLite;
architecture rtl of SlvArraytoAxiLite is
type StateType is (
IDLE_S,
WAIT_S);
type RegType is record
cnt : natural range 0 to SIZE_G-1;
valid : slv(SIZE_G-1 downto 0);
inSlv : Slv32Array(SIZE_G-1 downto 0);
req : AxiLiteReqType;
state : StateType;
end record;
constant REG_INIT_C : RegType := (
cnt => 0,
valid => (others => '0'),
inSlv => (others => (others => '0')),
req => AXI_LITE_REQ_INIT_C,
state => IDLE_S);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal inSlv : Slv32Array(SIZE_G-1 downto 0);
signal ack : AxiLiteAckType;
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
begin
GEN_VEC :
for i in (SIZE_G-1) downto 0 generate
SyncFifo : entity surf.SynchronizerFifo
generic map (
TPD_G => TPD_G,
COMMON_CLK_G => COMMON_CLK_G,
DATA_WIDTH_G => 32)
port map (
-- Write Ports (wr_clk domain)
wr_clk => clk,
din => input(i),
-- Read Ports (rd_clk domain)
rd_clk => axilClk,
dout => inSlv(i));
end generate GEN_VEC;
U_AxiLiteMaster : entity surf.AxiLiteMaster
generic map (
TPD_G => TPD_G)
port map (
req => r.req,
ack => ack,
axilClk => axilClk,
axilRst => axilRst,
axilWriteMaster => axilWriteMaster,
axilWriteSlave => axilWriteSlave,
axilReadMaster => axilReadMaster,
axilReadSlave => axilReadSlave);
comb : process (ack, axilRst, inSlv, r) is
variable v : RegType;
variable i : natural;
begin
-- Latch the current value
v := r;
-- Loop through the SLV array
for i in (SIZE_G-1) downto 0 loop
-- Check for changes in the bus
if inSlv(i) /= r.inSlv(i) then
-- Set the flag
v.valid(i) := '1';
end if;
end loop;
-- Update the registered value
v.inSlv := inSlv;
-- State Machine
case (r.state) is
----------------------------------------------------------------------
when IDLE_S =>
-- Check if transaction completed
if (ack.done = '0') then
-- Increment the counter
if r.cnt = (SIZE_G-1) then
v.cnt := 0;
else
v.cnt := r.cnt + 1;
end if;
-- Check the valid flag and transaction completed
if (r.valid(r.cnt) = '1') then
-- Reset the flag
v.valid(r.cnt) := '0';
-- Setup the AXI-Lite Master request
v.req.request := '1';
v.req.rnw := '0'; -- Write operation
v.req.address := ADDR_G(r.cnt);
v.req.wrData := r.inSlv(r.cnt);
-- Next state
v.state := WAIT_S;
end if;
end if;
----------------------------------------------------------------------
when WAIT_S =>
-- Wait for DONE to set
if ack.done = '1' then
-- Reset the flag
v.req.request := '0';
-- Next state
v.state := IDLE_S;
end if;
----------------------------------------------------------------------
end case;
-- Synchronous Reset
if (axilRst = '1') then
v := REG_INIT_C;
end if;
-- Register the variable for next clock cycle
rin <= v;
end process comb;
seq : process (axilClk) is
begin
if (rising_edge(axilClk)) then
r <= rin after TPD_G;
end if;
end process seq;
end architecture rtl;
|
<reponame>vhdlf/cpu_basic
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pkg_bits.all;
package pkg_cpu is
-- registers
type cpu_registers is array (15 downto 0) of word;
-- states
type cpu_state is (
st_halted,
st_fetch0,
st_fetch1,
st_fetch2,
st_fetch3,
st_load0,
st_load1,
st_execute,
st_store0,
st_store1
);
-- opcodes
constant OP_HALT: bits8 := x"00";
constant OP_LOAD: bits8 := x"10";
constant OP_STORE: bits8 := x"11";
constant OP_MOVI: bits8 := x"12";
constant OP_MOV: bits8 := x"13";
constant OP_CMP: bits8 := x"20";
constant OP_JMP: bits8 := x"21";
constant OP_JZ: bits8 := x"22";
constant OP_JNZ: bits8 := x"23";
constant OP_JB: bits8 := x"24";
constant OP_JBE: bits8 := x"25";
constant OP_JG: bits8 := x"26";
constant OP_JGE: bits8 := x"27";
constant OP_ADD: bits8 := x"30";
constant OP_ADC: bits8 := x"31";
constant OP_SUB: bits8 := x"32";
constant OP_SBB: bits8 := x"33";
constant OP_MUL: bits8 := x"34";
constant OP_IMUL: bits8 := x"35";
constant OP_DIV: bits8 := x"36";
constant OP_IDIV: bits8 := x"37";
constant OP_INC: bits8 := x"38";
constant OP_DEC: bits8 := x"39";
constant OP_AND: bits8 := x"40";
constant OP_OR: bits8 := x"41";
constant OP_NOT: bits8 := x"42";
constant OP_XOR: bits8 := x"43";
constant OP_SHL: bits8 := x"44";
constant OP_SHR: bits8 := x"45";
constant OP_ROL: bits8 := x"46";
constant OP_ROR: bits8 := x"47";
-- flags
constant FL_CARRY: integer := 0;
constant FL_ZERO: integer := 1;
constant FL_SIGN: integer := 2;
constant FL_OVERFLOW: integer := 3;
-- output
type cpu_output is record
-- status
state: bits4;
ip: bits8;
-- instruction
op: bits8;
rd: bits4;
rs: bits4;
end record cpu_output;
-- internal
type cpu_internal is record
-- status
state: cpu_state;
regs: cpu_registers;
flags: bits4;
ip: word;
-- instruction
op: bits8;
rd: bits4;
rs: bits4;
imm: word;
-- memory
addr: bits16;
data: bits16;
buff: word;
wr: std_logic;
end record cpu_internal;
function flags_word(v: word1) return bits4;
function flags_dword(v: dword1) return bits4;
end package pkg_cpu;
package body pkg_cpu is
function flags_word(v: word1) return bits4 is
variable f: bits4 := (others => '0');
begin
f(FL_CARRY) := v(32);
f(FL_SIGN) := v(31);
if v(31 downto 0) = 0 then f(FL_ZERO) := '1'; end if;
return f;
end function flags_word;
function flags_dword(v: dword1) return bits4 is
variable f: bits4 := (others => '0');
begin
f(FL_CARRY) := v(64);
f(FL_SIGN) := v(63);
if v(63 downto 0) = 0 then f(FL_ZERO) := '1'; end if;
return f;
end function flags_dword;
end package body pkg_cpu;
|
<filename>xtea-cripto-core/rtl/pipeline_version/xtea_pipeline.vhd
--! @file enc_xtea_pipeline.vhd
--! @brief
--! @author <NAME>, <EMAIL>
--! @date 2016-08-10
-------------------------------------------------------------------------------
-- Libraries
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
entity xtea_pipeline is
generic (
ROUNDS : integer := 32
);
port (
rst : in std_logic;
clk : in std_logic;
key_i : in std_logic_vector(127 downto 0);
start_i : in std_logic;
done_o : out std_logic;
mode_i : in std_logic;
mode_o : out std_logic;
data_i : in std_logic_vector(63 downto 0);
data_o : out std_logic_vector(63 downto 0)
);
end xtea_pipeline;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture xtea_pipeline of xtea_pipeline is
-----------------------------------
-- Types
-----------------------------------
type matrix_32 is array (0 to ROUNDS - 1) of std_logic_vector (31 downto 0);
type matrix_64 is array (0 to ROUNDS - 1) of std_logic_vector (63 downto 0);
-----------------------------------
-- Constants
-----------------------------------
constant DELTA_C : std_logic_vector(31 downto 0) := x"9e3779b9";
constant SUM_C : std_logic_vector(63 downto 0) := conv_std_logic_vector((conv_integer(DELTA_C)*ROUNDS),64);
-----------------------------------
-- Signal Declarations
-----------------------------------
signal sum_pipe : matrix_32;
signal sum_kernel : matrix_32;
signal data_pipe : matrix_64;
signal data_kernel : matrix_64;
signal mode_pipe : std_logic_vector(ROUNDS - 1 downto 0);
signal mode_kernel : std_logic_vector(ROUNDS - 1 downto 0);
signal start_pipe : std_logic_vector(ROUNDS - 1 downto 0);
signal start_kernel : std_logic_vector(ROUNDS - 1 downto 0);
signal sum_reg : std_logic_vector (31 downto 0);
signal xtea_input : std_logic_vector (63 downto 0);
signal xtea_output : std_logic_vector (63 downto 0);
signal mode_output : std_logic;
begin
-----------------------------------
-- Port Mappings
-----------------------------------
dec_stages_gen : for i in 0 to ROUNDS generate
first_stages : if i = 0 generate
dec_stage_i: entity work.pipeline_stage
port map(
clk => clk,
rst => rst,
start_i => start_i,
start_o => start_pipe(i),
sum_i => sum_reg,
sum_o => sum_pipe(i),
mode_i => mode_i,
mode_o => mode_pipe(i),
data_i => xtea_input,
data_o => data_pipe(i)
);
end generate first_stages;
last_stages : if i = ROUNDS generate
dec_stage_i: entity work.pipeline_stage
port map(
clk => clk,
rst => rst,
start_i => start_kernel(i-1),
start_o => done_o,
sum_i => sum_kernel(i-1),
sum_o => open,
mode_i => mode_kernel(i-1),
mode_o => mode_output,
data_i => data_kernel(i-1),
data_o => xtea_output
);
end generate last_stages;
other_stages : if i > 0 and i < ROUNDS generate
dec_stage_i: entity work.pipeline_stage
port map(
clk => clk,
rst => rst,
start_i => start_kernel(i-1),
start_o => start_pipe(i),
sum_i => sum_kernel(i-1),
sum_o => sum_pipe(i),
mode_i => mode_kernel(i-1),
mode_o => mode_pipe(i),
data_i => data_kernel(i-1),
data_o => data_pipe(i)
);
end generate other_stages;
end generate dec_stages_gen;
dec_xtea_gen : for i in 0 to ROUNDS-1 generate
dec_kernel_i: entity work.kernel_round
port map(
clk => clk,
rst => rst,
delta_i => DELTA_C,
key_i => key_i,
start_i => start_pipe(i),
start_o => start_kernel(i),
sum_i => sum_pipe(i),
sum_o => sum_kernel(i),
mode_i => mode_pipe(i),
mode_o => mode_kernel(i),
data_i => data_pipe(i),
data_o => data_kernel(i)
);
end generate dec_xtea_gen;
-----------------------------------
-- Asynchronous Assignments
-----------------------------------
mode_o <= mode_output;
xtea_input <= data_i when mode_i = '0' else data_i(31 downto 0) & data_i(63 downto 32);
data_o <= xtea_output when mode_output = '0' else xtea_output(31 downto 0) & xtea_output(63 downto 32);
sum_reg <= SUM_C(31 downto 0) when mode_i = '1' else (others=>'0');
-----------------------------------
-- Processes
-----------------------------------
end xtea_pipeline;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.token.all;
entity tb is
end tb;
architecture struct of tb is
signal rst, clk: std_logic;
signal rx_rdy, tx_rdy: std_logic;
signal tx_wr, rx_rd: std_logic;
signal rx_data, tx_data: character;
constant test_1: string := "12^34+2*"; -- => 46 92
constant test_2: string := "12^34^2*+"; -- => 68 80
constant test_3: string := "2^10*5^1-+"; -- => 20 4 24
constant test_4: string := "2^2-"; -- => 0
constant test_5: string := "12^2/"; -- => 6
begin
uart: entity work.uart
generic map(test_3)
port map(tx_wr, tx_data, rx_rd, rx_data, tx_rdy, rx_rdy);
calc: entity work.calc
generic map(false)
port map(clk, rst, tx_wr, tx_data, rx_rd, rx_data, tx_rdy, rx_rdy, open, open);
CLOCK: process
begin
clk<='1'; wait for 5 ns;
clk<='0'; wait for 5 ns;
end process;
RESET: process
begin
rst <= '0'; wait for 1 ns;
rst <= '1'; wait;
end process;
end architecture;
|
<filename>hw/perf_counter_v1_00_a/hdl/vhdl/perf_counter.vhd
-- Performance Counter for MicroBlaze
-- Author: <NAME> <<EMAIL>>
-- Copyrights (c) 2010 by Universiteit Leiden
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity perf_counter is
generic
(
C_NUM_OF_COUNTERS : integer := 4;
C_LOG2_NUM_OF_COUNTERS : integer := 2;
C_EXT_RESET_HIGH : integer := 1
);
port
(
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : out std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : out std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
);
end perf_counter;
architecture rtl of perf_counter is
constant MSB_OP : integer := 31;
constant LSB_OP : integer := 29;
constant MSB_ID : integer := 28;
constant LSB_ID : integer := 28-C_LOG2_NUM_OF_COUNTERS+1;
constant RST_ALL : std_logic_vector(0 to 2) := "000";
constant RST_ID : std_logic_vector(0 to 2) := "001";
constant START_ID : std_logic_vector(0 to 2) := "010";
constant STOP_ID : std_logic_vector(0 to 2) := "011";
constant READ_ID : std_logic_vector(0 to 2) := "100";
-- 64-bit counter @ 100MHz = > 5800 years
-- This eliminates the need for handling overflows
type counter_t is array(1 to C_NUM_OF_COUNTERS) of std_logic_vector(0 to 63);
signal counter : counter_t;
type op_t is (idle, running, reset, rd);
type op_array_t is array(1 to C_NUM_OF_COUNTERS) of op_t;
signal op_r : op_array_t;
signal op_i : op_array_t;
subtype id_int_t is integer range 0 to C_NUM_OF_COUNTERS;
signal rd_id_r : id_int_t;
signal rd_id_i : id_int_t;
signal rst : std_logic;
begin
rst <= FSL_Rst when (C_EXT_RESET_HIGH = 1) else not FSL_Rst;
FSL_M_Control <= '0';
FSL_M_Clk <= FSL_Clk;
FSL_S_Clk <= FSL_Clk;
registers: process(FSL_Clk)
begin
if rising_edge(FSL_Clk) then
if (rst = '1') then
counter <= (others => (others => '0'));
op_r <= (others => idle);
rd_id_r <= 0;
else
op_r <= op_i;
rd_id_r <= rd_id_i;
for i in 1 to C_NUM_OF_COUNTERS loop
case (op_i(i)) is
when idle =>
counter(i) <= counter(i);
when running =>
counter(i) <= std_logic_vector(unsigned(counter(i))+1);
when reset =>
counter(i) <= (others => '0');
when rd =>
counter(i) <= counter(i);
when others =>
null;
end case;
end loop;
end if;
end if;
end process;
fsm: process(FSL_S_Exists, FSL_S_Data, op_r, counter, rd_id_r)
variable id : integer;
begin
-- Default assignments
id := 0;
op_i <= op_r;
FSL_M_Data <= (others => '0');
FSL_M_Write <= '0';
FSL_S_Read <= '0';
rd_id_i <= 0;
if (FSL_S_Exists = '1' and rd_id_r = 0) then
id := to_integer(unsigned(FSL_S_Data(LSB_ID to MSB_ID))) + 1;
case(FSL_S_Data(LSB_OP to MSB_OP)) is
when RST_ALL =>
op_i <= (others => reset);
FSL_S_Read <= '1';
when RST_ID =>
op_i(id) <= reset;
FSL_S_Read <= '1';
when STOP_ID =>
op_i(id) <= idle;
FSL_S_Read <= '1';
when START_ID =>
op_i(id) <= running;
FSL_S_Read <= '1';
when READ_ID =>
op_i(id) <= rd;
rd_id_i <= id;
FSL_S_Read <= '1';
FSL_M_Data <= counter(id)(32 to 63);
FSL_M_Write <= '1';
when others =>
null;
end case;
end if;
if (rd_id_r /= 0) then
op_i(rd_id_r) <= running;
FSL_S_Read <= '0';
FSL_M_Data <= counter(rd_id_r)(0 to 31);
FSL_M_Write <= '1';
rd_id_i <= 0;
end if;
end process;
end architecture rtl;
|
<reponame>xivisi/MachineLearning
-- (C) 2001-2018 Intel Corporation. All rights reserved.
-- This simulation model contains highly confidential and
-- proprietary information of Intel and is being provided
-- in accordance with and subject to the protections of the
-- applicable Intel Program License Subscription Agreement
-- which governs its use and disclosure. Your use of Intel
-- Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions,
-- and any output files from any of the foregoing (including device
-- programming or simulation files), and any associated
-- documentation or information are expressly subject to the
-- terms and conditions of the Intel Program License Subscription
-- Agreement, Intel FPGA IP License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of simulating designs
-- for use exclusively in logic devices manufactured by Intel and sold
-- by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details. Intel products and
-- services are protected under numerous U.S. and foreign patents,
-- maskwork rights, copyrights and other intellectual property laws.
-- Intel assumes no responsibility or liability arising out of the
-- application or use of this simulation model.
-- ACDS 18.1
`protect begin_protected
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KhtUtgB1lN38qozP9K3VGw8QqB6+iH93lzsugEh26LVldQWNo4G8sbl3/YE19Bc7rWoABBRk0a32
KKZcD9+X1vXHL/sAK8ZJimIW6mAvgO+jBgF6SD/rjYP/RIzUC0TcdmD0fPEyOwhfBKhn3r/hhlY6
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sbntkRDzRqKXscL/x0npoSih88IijR0H2GmTdHMom/b7kPIoKi2yGoZraVaa9wJoMXp7pyIQazV0
u12Ph8JAUASbz8JRfmi8j9HpjpsT3zSfOQQVr9kzaBx0VLjAn7vzwVmqM5WOxfU/odqF8h63FM/S
Bq+lTXYyq8Nch9JxNLPqhSybNc0InlrRnxxDvF3Wr7ItOiQxBQ3gltrnxnqnzAmce2usZ+MhzkcA
y7LzMjZ62SSziff7Mgh/XXktLejsH684C+leCFya63c0OWPnnKgltw89k1bGD/yWmmEt6io=
`protect end_protected
|
<reponame>shufps/troika_ice40
component pow_pll1 is
port(outglobal_o: out std_logic;
latch_i: in std_logic;
outcore_o: out std_logic;
ref_clk_i: in std_logic;
rst_n_i: in std_logic);
end component;
__: pow_pll1 port map(outglobal_o=> , latch_i=> , outcore_o=> , ref_clk_i=> ,
rst_n_i=> );
|
<filename>hw_des/des/src/Key_Generator/REG56.vhd
-------------------------------------------------------------------------------
-- Title : REG56
-- Design : des
-- Author : KDG
-- Company : AUTS - NTU KhPI
-- File : REG56.vhd
-- Generated : Wed Dec 15 17:54:37 2021
-------------------------------------------------------------------------------
-- Description : 56-bit register for cipher key schedule
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity REG56 is
port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
WE : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR(55 downto 0);
DO : out STD_LOGIC_VECTOR(55 downto 0)
);
end entity;
architecture REG56_arch of REG56 is
signal reg_state : STD_LOGIC_VECTOR(55 downto 0) := (others => '0');
begin
p1: process(CLK, RST)
begin
if RST = '1' then
reg_state <= (others => '0');
elsif CLK'event and CLK = '1' then
if WE = '1' then
reg_state <= DI;
end if;
end if;
end process;
DO <= reg_state;
end architecture;
|
<gh_stars>0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PruebaGenericDecoder is
generic(word_bits:integer:=5);
-- Port ( );
end PruebaGenericDecoder;
architecture Test of PruebaGenericDecoder is
signal sa: std_logic_vector(3-1 downto 0):= (others => '0');
signal soutput: std_logic_vector(2**3-1 downto 0);
begin
decoder: entity work.GenericDecoder(Base)
generic map(word_bits => 3)
port map(
a => sa,
output => soutput
);
test: process
begin
sa <= "000";
wait for 20 ns;
sa <= "001";
wait for 20 ns;
sa <= "100";
wait for 20 ns;
sa <= "011";
wait for 20 ns;
sa <= "101";
wait for 20 ns;
sa <= "111";
wait for 20 ns;
end process;
end Test;
|
<reponame>stark-dev/dlx-processor<filename>vhd/a.b.c.b-shifter.vhd<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
ENTITY Shifter IS
generic(N : integer := 32);
port( R : IN std_logic_vector(N-1 downto 0);
arith_logicaln : IN std_logic;
right_leftn : IN std_logic;
count : IN std_logic_vector(4 downto 0);
R_OUT : OUT std_logic_vector(N-1 downto 0));
END ENTITY;
ARCHITECTURE Structural OF Shifter IS
type mask_array is array(3 downto 0) of std_logic_vector(N-1+7 downto 0);
signal mask : mask_array;
signal shifted_data : std_logic_vector(N-1+7 downto 0);
signal count_sel : std_logic_vector(2 downto 0);
signal right_leftn_ext : std_logic_vector(2 downto 0);
component Mux2to1
generic (N:integer := 16);
Port (
A: In std_logic_vector (N-1 downto 0);
B: In std_logic_vector (N-1 downto 0);
S: In std_logic;
Y: Out std_logic_vector (N-1 downto 0));
end component;
component Mux8to1
generic (N:integer := 16);
Port (
In1: In std_logic_vector (N-1 downto 0);
IN2: In std_logic_vector (N-1 downto 0);
IN3: In std_logic_vector (N-1 downto 0);
IN4: In std_logic_vector (N-1 downto 0);
In5: In std_logic_vector (N-1 downto 0);
IN6: In std_logic_vector (N-1 downto 0);
IN7: In std_logic_vector (N-1 downto 0);
IN8: In std_logic_vector (N-1 downto 0);
S: In std_logic_vector(2 downto 0);
Y: Out std_logic_vector (N-1 downto 0));
end component;
component Mux4to1
generic (N:integer := 16);
Port (
In1: In std_logic_vector (N-1 downto 0);
IN2: In std_logic_vector (N-1 downto 0);
IN3: In std_logic_vector (N-1 downto 0);
IN4: In std_logic_vector (N-1 downto 0);
S: In std_logic_vector(1 downto 0);
Y: Out std_logic_vector (N-1 downto 0));
end component;
BEGIN
level1 : for i in 0 to 3 generate
signal sh_left, sh_right : std_logic_vector(N-1+7 downto 0);
begin
sh_left(8*(i+1)-2 downto 0)<= (others => '0');
sh_left(N-1+7 downto 8*(i+1)-1) <= R(N-1-(8*i) downto 0);
sh_right(N-1+7 downto N-(8*i)) <= (others => arith_logicaln and R(N-1));
sh_right(N-1-(8*i) downto 0) <= R(N-1 downto 8*i);
mux : mux2to1
generic map(N+7)
port map(sh_left, sh_right, right_leftn, mask(i));
end generate;
level2 : mux4to1
generic map(N+7)
port map(mask(0), mask(1), mask(2), mask(3), count(4 downto 3), shifted_data);
right_leftn_ext <= (others => right_leftn);
count_sel <= count(2 downto 0) xnor right_leftn_ext;
level3 : mux8to1
generic map(N)
port map(shifted_data(N-1 downto 0), shifted_data(N downto 1), shifted_data(N+1 downto 2), shifted_data(N+2 downto 3),
shifted_data(N+3 downto 4), shifted_data(N+4 downto 5), shifted_data(N+5 downto 6), shifted_data(N+6 downto 7),
count_sel, R_OUT);
END ARCHITECTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity shift_8 is
port (
inp : in std_logic_vector(31 downto 0);
shift_type : in std_logic_vector(1 downto 0);
c_out : out std_logic;
slct : in std_logic;
oup : out std_logic_vector(31 downto 0));
end entity shift_8;
architecture arch_1 of shift_8 is
signal t_i : std_logic_vector(7 downto 0);
begin
with slct select oup <=
t_i & inp(31 downto 8) when '1',
inp(31 downto 0) when others;
with shift_type select t_i <=
"00000000" when "00",
"00000000" when "01",
inp(31)&inp(31)&inp(31)&inp(31)&inp(31)&inp(31)&inp(31)&inp(31) when "10",
inp (7)&inp(6)&inp (5)&inp(4)&inp (3)&inp(2)&inp (1)&inp(0) when others;
--c_out<=inp(7);
with slct select c_out <=
inp(7) when '1',
-- c_in when others;
'0' when others;
end architecture arch_1;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.aes_package.BYTE;
-- multiply.vhd
-- Contains multiplication look up tables that are used in mixColumns
-- Tables take in one byte at a time, and produce one byte at the output
-- Tables include multiply by 2, 3, 9, B, D, and E
-- Look up tables can be found at https://en.wikipedia.org/wiki/Rijndael_MixColumns
entity multiply_2 is
port (i : in BYTE;
o : out BYTE
);
end multiply_2;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.aes_package.BYTE;
entity multiply_3 is
port (i : in BYTE;
o : out BYTE
);
end multiply_3;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.aes_package.BYTE;
entity multiply_9 is
port (i : in BYTE;
o : out BYTE
);
end multiply_9;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.aes_package.BYTE;
entity multiply_b is
port (i : in BYTE;
o : out BYTE
);
end multiply_b;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.aes_package.BYTE;
entity multiply_d is
port (i : in BYTE;
o : out BYTE
);
end multiply_d;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.aes_package.BYTE;
entity multiply_e is
port (i : in std_logic_vector (7 downto 0); --BYTE
o : out std_logic_vector (7 downto 0) -- BYTE
);
end multiply_e;
architecture Behavioral of multiply_2 is
begin
with i select o <=
x"00" when x"00",
x"02" when x"01",
x"04" when x"02",
x"06" when x"03",
x"08" when x"04",
x"0A" when x"05",
x"0C" when x"06",
x"0E" when x"07",
x"10" when x"08",
x"12" when x"09",
x"14" when x"0A",
x"16" when x"0B",
x"18" when x"0C",
x"1A" when x"0D",
x"1C" when x"0E",
x"1E" when x"0F",
x"20" when x"10",
x"22" when x"11",
x"24" when x"12",
x"26" when x"13",
x"28" when x"14",
x"2A" when x"15",
x"2C" when x"16",
x"2E" when x"17",
x"30" when x"18",
x"32" when x"19",
x"34" when x"1A",
x"36" when x"1B",
x"38" when x"1C",
x"3A" when x"1D",
x"3C" when x"1E",
x"3E" when x"1F",
x"40" when x"20",
x"42" when x"21",
x"44" when x"22",
x"46" when x"23",
x"48" when x"24",
x"4A" when x"25",
x"4C" when x"26",
x"4E" when x"27",
x"50" when x"28",
x"52" when x"29",
x"54" when x"2A",
x"56" when x"2B",
x"58" when x"2C",
x"5A" when x"2D",
x"5C" when x"2E",
x"5E" when x"2F",
x"60" when x"30",
x"62" when x"31",
x"64" when x"32",
x"66" when x"33",
x"68" when x"34",
x"6A" when x"35",
x"6C" when x"36",
x"6E" when x"37",
x"70" when x"38",
x"72" when x"39",
x"74" when x"3A",
x"76" when x"3B",
x"78" when x"3C",
x"7A" when x"3D",
x"7C" when x"3E",
x"7E" when x"3F",
x"80" when x"40",
x"82" when x"41",
x"84" when x"42",
x"86" when x"43",
x"88" when x"44",
x"8A" when x"45",
x"8C" when x"46",
x"8E" when x"47",
x"90" when x"48",
x"92" when x"49",
x"94" when x"4A",
x"96" when x"4B",
x"98" when x"4C",
x"9A" when x"4D",
x"9C" when x"4E",
x"9E" when x"4F",
x"A0" when x"50",
x"A2" when x"51",
x"A4" when x"52",
x"A6" when x"53",
x"A8" when x"54",
x"AA" when x"55",
x"AC" when x"56",
x"AE" when x"57",
x"B0" when x"58",
x"B2" when x"59",
x"B4" when x"5A",
x"B6" when x"5B",
x"B8" when x"5C",
x"BA" when x"5D",
x"BC" when x"5E",
x"BE" when x"5F",
x"C0" when x"60",
x"C2" when x"61",
x"C4" when x"62",
x"C6" when x"63",
x"C8" when x"64",
x"CA" when x"65",
x"CC" when x"66",
x"CE" when x"67",
x"D0" when x"68",
x"D2" when x"69",
x"D4" when x"6A",
x"D6" when x"6B",
x"D8" when x"6C",
x"DA" when x"6D",
x"DC" when x"6E",
x"DE" when x"6F",
x"E0" when x"70",
x"E2" when x"71",
x"E4" when x"72",
x"E6" when x"73",
x"E8" when x"74",
x"EA" when x"75",
x"EC" when x"76",
x"EE" when x"77",
x"F0" when x"78",
x"F2" when x"79",
x"F4" when x"7A",
x"F6" when x"7B",
x"F8" when x"7C",
x"FA" when x"7D",
x"FC" when x"7E",
x"FE" when x"7F",
x"1B" when x"80",
x"19" when x"81",
x"1F" when x"82",
x"1D" when x"83",
x"13" when x"84",
x"11" when x"85",
x"17" when x"86",
x"15" when x"87",
x"0B" when x"88",
x"09" when x"89",
x"0F" when x"8A",
x"0D" when x"8B",
x"03" when x"8C",
x"01" when x"8D",
x"07" when x"8E",
x"05" when x"8F",
x"3B" when x"90",
x"39" when x"91",
x"3F" when x"92",
x"3D" when x"93",
x"33" when x"94",
x"31" when x"95",
x"37" when x"96",
x"35" when x"97",
x"2B" when x"98",
x"29" when x"99",
x"2F" when x"9A",
x"2D" when x"9B",
x"23" when x"9C",
x"21" when x"9D",
x"27" when x"9E",
x"25" when x"9F",
x"5B" when x"A0",
x"59" when x"A1",
x"5F" when x"A2",
x"5D" when x"A3",
x"53" when x"A4",
x"51" when x"A5",
x"57" when x"A6",
x"55" when x"A7",
x"4B" when x"A8",
x"49" when x"A9",
x"4F" when x"AA",
x"4D" when x"AB",
x"43" when x"AC",
x"41" when x"AD",
x"47" when x"AE",
x"45" when x"AF",
x"7B" when x"B0",
x"79" when x"B1",
x"7F" when x"B2",
x"7D" when x"B3",
x"73" when x"B4",
x"71" when x"B5",
x"77" when x"B6",
x"75" when x"B7",
x"6B" when x"B8",
x"69" when x"B9",
x"6F" when x"BA",
x"6D" when x"BB",
x"63" when x"BC",
x"61" when x"BD",
x"67" when x"BE",
x"65" when x"BF",
x"9B" when x"C0",
x"99" when x"C1",
x"9F" when x"C2",
x"9D" when x"C3",
x"93" when x"C4",
x"91" when x"C5",
x"97" when x"C6",
x"95" when x"C7",
x"8B" when x"C8",
x"89" when x"C9",
x"8F" when x"CA",
x"8D" when x"CB",
x"83" when x"CC",
x"81" when x"CD",
x"87" when x"CE",
x"85" when x"CF",
x"BB" when x"D0",
x"B9" when x"D1",
x"BF" when x"D2",
x"BD" when x"D3",
x"B3" when x"D4",
x"B1" when x"D5",
x"B7" when x"D6",
x"B5" when x"D7",
x"AB" when x"D8",
x"A9" when x"D9",
x"AF" when x"DA",
x"AD" when x"DB",
x"A3" when x"DC",
x"A1" when x"DD",
x"A7" when x"DE",
x"A5" when x"DF",
x"DB" when x"E0",
x"D9" when x"E1",
x"DF" when x"E2",
x"DD" when x"E3",
x"D3" when x"E4",
x"D1" when x"E5",
x"D7" when x"E6",
x"D5" when x"E7",
x"CB" when x"E8",
x"C9" when x"E9",
x"CF" when x"EA",
x"CD" when x"EB",
x"C3" when x"EC",
x"C1" when x"ED",
x"C7" when x"EE",
x"C5" when x"EF",
x"FB" when x"F0",
x"F9" when x"F1",
x"FF" when x"F2",
x"FD" when x"F3",
x"F3" when x"F4",
x"F1" when x"F5",
x"F7" when x"F6",
x"F5" when x"F7",
x"EB" when x"F8",
x"E9" when x"F9",
x"EF" when x"FA",
x"ED" when x"FB",
x"E3" when x"FC",
x"E1" when x"FD",
x"E7" when x"FE",
x"E5" when x"FF",
x"00" when others;
end Behavioral;
architecture Behavioral of multiply_3 is
begin
with i select o <=
x"00" when x"00",
x"03" when x"01",
x"06" when x"02",
x"05" when x"03",
x"0C" when x"04",
x"0F" when x"05",
x"0A" when x"06",
x"09" when x"07",
x"18" when x"08",
x"1B" when x"09",
x"1E" when x"0A",
x"1D" when x"0B",
x"14" when x"0C",
x"17" when x"0D",
x"12" when x"0E",
x"11" when x"0F",
x"30" when x"10",
x"33" when x"11",
x"36" when x"12",
x"35" when x"13",
x"3C" when x"14",
x"3F" when x"15",
x"3A" when x"16",
x"39" when x"17",
x"28" when x"18",
x"2B" when x"19",
x"2E" when x"1A",
x"2D" when x"1B",
x"24" when x"1C",
x"27" when x"1D",
x"22" when x"1E",
x"21" when x"1F",
x"60" when x"20",
x"63" when x"21",
x"66" when x"22",
x"65" when x"23",
x"6C" when x"24",
x"6F" when x"25",
x"6A" when x"26",
x"69" when x"27",
x"78" when x"28",
x"7B" when x"29",
x"7E" when x"2A",
x"7D" when x"2B",
x"74" when x"2C",
x"77" when x"2D",
x"72" when x"2E",
x"71" when x"2F",
x"50" when x"30",
x"53" when x"31",
x"56" when x"32",
x"55" when x"33",
x"5C" when x"34",
x"5F" when x"35",
x"5A" when x"36",
x"59" when x"37",
x"48" when x"38",
x"4B" when x"39",
x"4E" when x"3A",
x"4D" when x"3B",
x"44" when x"3C",
x"47" when x"3D",
x"42" when x"3E",
x"41" when x"3F",
x"C0" when x"40",
x"C3" when x"41",
x"C6" when x"42",
x"C5" when x"43",
x"CC" when x"44",
x"CF" when x"45",
x"CA" when x"46",
x"C9" when x"47",
x"D8" when x"48",
x"DB" when x"49",
x"DE" when x"4A",
x"DD" when x"4B",
x"D4" when x"4C",
x"D7" when x"4D",
x"D2" when x"4E",
x"D1" when x"4F",
x"F0" when x"50",
x"F3" when x"51",
x"F6" when x"52",
x"F5" when x"53",
x"FC" when x"54",
x"FF" when x"55",
x"FA" when x"56",
x"F9" when x"57",
x"E8" when x"58",
x"EB" when x"59",
x"EE" when x"5A",
x"ED" when x"5B",
x"E4" when x"5C",
x"E7" when x"5D",
x"E2" when x"5E",
x"E1" when x"5F",
x"A0" when x"60",
x"A3" when x"61",
x"A6" when x"62",
x"A5" when x"63",
x"AC" when x"64",
x"AF" when x"65",
x"AA" when x"66",
x"A9" when x"67",
x"B8" when x"68",
x"BB" when x"69",
x"BE" when x"6A",
x"BD" when x"6B",
x"B4" when x"6C",
x"B7" when x"6D",
x"B2" when x"6E",
x"B1" when x"6F",
x"90" when x"70",
x"93" when x"71",
x"96" when x"72",
x"95" when x"73",
x"9C" when x"74",
x"9F" when x"75",
x"9A" when x"76",
x"99" when x"77",
x"88" when x"78",
x"8B" when x"79",
x"8E" when x"7A",
x"8D" when x"7B",
x"84" when x"7C",
x"87" when x"7D",
x"82" when x"7E",
x"81" when x"7F",
x"9B" when x"80",
x"98" when x"81",
x"9D" when x"82",
x"9E" when x"83",
x"97" when x"84",
x"94" when x"85",
x"91" when x"86",
x"92" when x"87",
x"83" when x"88",
x"80" when x"89",
x"85" when x"8A",
x"86" when x"8B",
x"8F" when x"8C",
x"8C" when x"8D",
x"89" when x"8E",
x"8A" when x"8F",
x"AB" when x"90",
x"A8" when x"91",
x"AD" when x"92",
x"AE" when x"93",
x"A7" when x"94",
x"A4" when x"95",
x"A1" when x"96",
x"A2" when x"97",
x"B3" when x"98",
x"B0" when x"99",
x"B5" when x"9A",
x"B6" when x"9B",
x"BF" when x"9C",
x"BC" when x"9D",
x"B9" when x"9E",
x"BA" when x"9F",
x"FB" when x"A0",
x"F8" when x"A1",
x"FD" when x"A2",
x"FE" when x"A3",
x"F7" when x"A4",
x"F4" when x"A5",
x"F1" when x"A6",
x"F2" when x"A7",
x"E3" when x"A8",
x"E0" when x"A9",
x"E5" when x"AA",
x"E6" when x"AB",
x"EF" when x"AC",
x"EC" when x"AD",
x"E9" when x"AE",
x"EA" when x"AF",
x"CB" when x"B0",
x"C8" when x"B1",
x"CD" when x"B2",
x"CE" when x"B3",
x"C7" when x"B4",
x"C4" when x"B5",
x"C1" when x"B6",
x"C2" when x"B7",
x"D3" when x"B8",
x"D0" when x"B9",
x"D5" when x"BA",
x"D6" when x"BB",
x"DF" when x"BC",
x"DC" when x"BD",
x"D9" when x"BE",
x"DA" when x"BF",
x"5B" when x"C0",
x"58" when x"C1",
x"5D" when x"C2",
x"5E" when x"C3",
x"57" when x"C4",
x"54" when x"C5",
x"51" when x"C6",
x"52" when x"C7",
x"43" when x"C8",
x"40" when x"C9",
x"45" when x"CA",
x"46" when x"CB",
x"4F" when x"CC",
x"4C" when x"CD",
x"49" when x"CE",
x"4A" when x"CF",
x"6B" when x"D0",
x"68" when x"D1",
x"6D" when x"D2",
x"6E" when x"D3",
x"67" when x"D4",
x"64" when x"D5",
x"61" when x"D6",
x"62" when x"D7",
x"73" when x"D8",
x"70" when x"D9",
x"75" when x"DA",
x"76" when x"DB",
x"7F" when x"DC",
x"7C" when x"DD",
x"79" when x"DE",
x"7A" when x"DF",
x"3B" when x"E0",
x"38" when x"E1",
x"3D" when x"E2",
x"3E" when x"E3",
x"37" when x"E4",
x"34" when x"E5",
x"31" when x"E6",
x"32" when x"E7",
x"23" when x"E8",
x"20" when x"E9",
x"25" when x"EA",
x"26" when x"EB",
x"2F" when x"EC",
x"2C" when x"ED",
x"29" when x"EE",
x"2A" when x"EF",
x"0B" when x"F0",
x"08" when x"F1",
x"0D" when x"F2",
x"0E" when x"F3",
x"07" when x"F4",
x"04" when x"F5",
x"01" when x"F6",
x"02" when x"F7",
x"13" when x"F8",
x"10" when x"F9",
x"15" when x"FA",
x"16" when x"FB",
x"1F" when x"FC",
x"1C" when x"FD",
x"19" when x"FE",
x"1A" when x"FF",
x"00" when others;
end Behavioral;
architecture Behavioral of multiply_9 is
begin
with i select o <=
x"00" when x"00",
x"09" when x"01",
x"12" when x"02",
x"1B" when x"03",
x"24" when x"04",
x"2D" when x"05",
x"36" when x"06",
x"3F" when x"07",
x"48" when x"08",
x"41" when x"09",
x"5A" when x"0A",
x"53" when x"0B",
x"6C" when x"0C",
x"65" when x"0D",
x"7E" when x"0E",
x"77" when x"0F",
x"90" when x"10",
x"99" when x"11",
x"82" when x"12",
x"8B" when x"13",
x"B4" when x"14",
x"BD" when x"15",
x"A6" when x"16",
x"AF" when x"17",
x"D8" when x"18",
x"D1" when x"19",
x"CA" when x"1A",
x"C3" when x"1B",
x"FC" when x"1C",
x"F5" when x"1D",
x"EE" when x"1E",
x"E7" when x"1F",
x"3B" when x"20",
x"32" when x"21",
x"29" when x"22",
x"20" when x"23",
x"1F" when x"24",
x"16" when x"25",
x"0D" when x"26",
x"04" when x"27",
x"73" when x"28",
x"7A" when x"29",
x"61" when x"2A",
x"68" when x"2B",
x"57" when x"2C",
x"5E" when x"2D",
x"45" when x"2E",
x"4C" when x"2F",
x"AB" when x"30",
x"A2" when x"31",
x"B9" when x"32",
x"B0" when x"33",
x"8F" when x"34",
x"86" when x"35",
x"9D" when x"36",
x"94" when x"37",
x"E3" when x"38",
x"EA" when x"39",
x"F1" when x"3A",
x"F8" when x"3B",
x"C7" when x"3C",
x"CE" when x"3D",
x"D5" when x"3E",
x"DC" when x"3F",
x"76" when x"40",
x"7F" when x"41",
x"64" when x"42",
x"6D" when x"43",
x"52" when x"44",
x"5B" when x"45",
x"40" when x"46",
x"49" when x"47",
x"3E" when x"48",
x"37" when x"49",
x"2C" when x"4A",
x"25" when x"4B",
x"1A" when x"4C",
x"13" when x"4D",
x"08" when x"4E",
x"01" when x"4F",
x"E6" when x"50",
x"EF" when x"51",
x"F4" when x"52",
x"FD" when x"53",
x"C2" when x"54",
x"CB" when x"55",
x"D0" when x"56",
x"D9" when x"57",
x"AE" when x"58",
x"A7" when x"59",
x"BC" when x"5A",
x"B5" when x"5B",
x"8A" when x"5C",
x"83" when x"5D",
x"98" when x"5E",
x"91" when x"5F",
x"4D" when x"60",
x"44" when x"61",
x"5F" when x"62",
x"56" when x"63",
x"69" when x"64",
x"60" when x"65",
x"7B" when x"66",
x"72" when x"67",
x"05" when x"68",
x"0C" when x"69",
x"17" when x"6A",
x"1E" when x"6B",
x"21" when x"6C",
x"28" when x"6D",
x"33" when x"6E",
x"3A" when x"6F",
x"DD" when x"70",
x"D4" when x"71",
x"CF" when x"72",
x"C6" when x"73",
x"F9" when x"74",
x"F0" when x"75",
x"EB" when x"76",
x"E2" when x"77",
x"95" when x"78",
x"9C" when x"79",
x"87" when x"7A",
x"8E" when x"7B",
x"B1" when x"7C",
x"B8" when x"7D",
x"A3" when x"7E",
x"AA" when x"7F",
x"EC" when x"80",
x"E5" when x"81",
x"FE" when x"82",
x"F7" when x"83",
x"C8" when x"84",
x"C1" when x"85",
x"DA" when x"86",
x"D3" when x"87",
x"A4" when x"88",
x"AD" when x"89",
x"B6" when x"8A",
x"BF" when x"8B",
x"80" when x"8C",
x"89" when x"8D",
x"92" when x"8E",
x"9B" when x"8F",
x"7C" when x"90",
x"75" when x"91",
x"6E" when x"92",
x"67" when x"93",
x"58" when x"94",
x"51" when x"95",
x"4A" when x"96",
x"43" when x"97",
x"34" when x"98",
x"3D" when x"99",
x"26" when x"9A",
x"2F" when x"9B",
x"10" when x"9C",
x"19" when x"9D",
x"02" when x"9E",
x"0B" when x"9F",
x"D7" when x"A0",
x"DE" when x"A1",
x"C5" when x"A2",
x"CC" when x"A3",
x"F3" when x"A4",
x"FA" when x"A5",
x"E1" when x"A6",
x"E8" when x"A7",
x"9F" when x"A8",
x"96" when x"A9",
x"8D" when x"AA",
x"84" when x"AB",
x"BB" when x"AC",
x"B2" when x"AD",
x"A9" when x"AE",
x"A0" when x"AF",
x"47" when x"B0",
x"4E" when x"B1",
x"55" when x"B2",
x"5C" when x"B3",
x"63" when x"B4",
x"6A" when x"B5",
x"71" when x"B6",
x"78" when x"B7",
x"0F" when x"B8",
x"06" when x"B9",
x"1D" when x"BA",
x"14" when x"BB",
x"2B" when x"BC",
x"22" when x"BD",
x"39" when x"BE",
x"30" when x"BF",
x"9A" when x"C0",
x"93" when x"C1",
x"88" when x"C2",
x"81" when x"C3",
x"BE" when x"C4",
x"B7" when x"C5",
x"AC" when x"C6",
x"A5" when x"C7",
x"D2" when x"C8",
x"DB" when x"C9",
x"C0" when x"CA",
x"C9" when x"CB",
x"F6" when x"CC",
x"FF" when x"CD",
x"E4" when x"CE",
x"ED" when x"CF",
x"0A" when x"D0",
x"03" when x"D1",
x"18" when x"D2",
x"11" when x"D3",
x"2E" when x"D4",
x"27" when x"D5",
x"3C" when x"D6",
x"35" when x"D7",
x"42" when x"D8",
x"4B" when x"D9",
x"50" when x"DA",
x"59" when x"DB",
x"66" when x"DC",
x"6F" when x"DD",
x"74" when x"DE",
x"7D" when x"DF",
x"A1" when x"E0",
x"A8" when x"E1",
x"B3" when x"E2",
x"BA" when x"E3",
x"85" when x"E4",
x"8C" when x"E5",
x"97" when x"E6",
x"9E" when x"E7",
x"E9" when x"E8",
x"E0" when x"E9",
x"FB" when x"EA",
x"F2" when x"EB",
x"CD" when x"EC",
x"C4" when x"ED",
x"DF" when x"EE",
x"D6" when x"EF",
x"31" when x"F0",
x"38" when x"F1",
x"23" when x"F2",
x"2A" when x"F3",
x"15" when x"F4",
x"1C" when x"F5",
x"07" when x"F6",
x"0E" when x"F7",
x"79" when x"F8",
x"70" when x"F9",
x"6B" when x"FA",
x"62" when x"FB",
x"5D" when x"FC",
x"54" when x"FD",
x"4F" when x"FE",
x"46" when x"FF",
x"00" when others;
end Behavioral;
architecture Behavioral of multiply_b is
begin
with i select o <=
x"00" when x"00",
x"0B" when x"01",
x"16" when x"02",
x"1D" when x"03",
x"2C" when x"04",
x"27" when x"05",
x"3A" when x"06",
x"31" when x"07",
x"58" when x"08",
x"53" when x"09",
x"4E" when x"0A",
x"45" when x"0B",
x"74" when x"0C",
x"7F" when x"0D",
x"62" when x"0E",
x"69" when x"0F",
x"B0" when x"10",
x"BB" when x"11",
x"A6" when x"12",
x"AD" when x"13",
x"9C" when x"14",
x"97" when x"15",
x"8A" when x"16",
x"81" when x"17",
x"E8" when x"18",
x"E3" when x"19",
x"FE" when x"1A",
x"F5" when x"1B",
x"C4" when x"1C",
x"CF" when x"1D",
x"D2" when x"1E",
x"D9" when x"1F",
x"7B" when x"20",
x"70" when x"21",
x"6D" when x"22",
x"66" when x"23",
x"57" when x"24",
x"5C" when x"25",
x"41" when x"26",
x"4A" when x"27",
x"23" when x"28",
x"28" when x"29",
x"35" when x"2A",
x"3E" when x"2B",
x"0F" when x"2C",
x"04" when x"2D",
x"19" when x"2E",
x"12" when x"2F",
x"CB" when x"30",
x"C0" when x"31",
x"DD" when x"32",
x"D6" when x"33",
x"E7" when x"34",
x"EC" when x"35",
x"F1" when x"36",
x"FA" when x"37",
x"93" when x"38",
x"98" when x"39",
x"85" when x"3A",
x"8E" when x"3B",
x"BF" when x"3C",
x"B4" when x"3D",
x"A9" when x"3E",
x"A2" when x"3F",
x"F6" when x"40",
x"FD" when x"41",
x"E0" when x"42",
x"EB" when x"43",
x"DA" when x"44",
x"D1" when x"45",
x"CC" when x"46",
x"C7" when x"47",
x"AE" when x"48",
x"A5" when x"49",
x"B8" when x"4A",
x"B3" when x"4B",
x"82" when x"4C",
x"89" when x"4D",
x"94" when x"4E",
x"9F" when x"4F",
x"46" when x"50",
x"4D" when x"51",
x"50" when x"52",
x"5B" when x"53",
x"6A" when x"54",
x"61" when x"55",
x"7C" when x"56",
x"77" when x"57",
x"1E" when x"58",
x"15" when x"59",
x"08" when x"5A",
x"03" when x"5B",
x"32" when x"5C",
x"39" when x"5D",
x"24" when x"5E",
x"2F" when x"5F",
x"8D" when x"60",
x"86" when x"61",
x"9B" when x"62",
x"90" when x"63",
x"A1" when x"64",
x"AA" when x"65",
x"B7" when x"66",
x"BC" when x"67",
x"D5" when x"68",
x"DE" when x"69",
x"C3" when x"6A",
x"C8" when x"6B",
x"F9" when x"6C",
x"F2" when x"6D",
x"EF" when x"6E",
x"E4" when x"6F",
x"3D" when x"70",
x"36" when x"71",
x"2B" when x"72",
x"20" when x"73",
x"11" when x"74",
x"1A" when x"75",
x"07" when x"76",
x"0C" when x"77",
x"65" when x"78",
x"6E" when x"79",
x"73" when x"7A",
x"78" when x"7B",
x"49" when x"7C",
x"42" when x"7D",
x"5F" when x"7E",
x"54" when x"7F",
x"F7" when x"80",
x"FC" when x"81",
x"E1" when x"82",
x"EA" when x"83",
x"DB" when x"84",
x"D0" when x"85",
x"CD" when x"86",
x"C6" when x"87",
x"AF" when x"88",
x"A4" when x"89",
x"B9" when x"8A",
x"B2" when x"8B",
x"83" when x"8C",
x"88" when x"8D",
x"95" when x"8E",
x"9E" when x"8F",
x"47" when x"90",
x"4C" when x"91",
x"51" when x"92",
x"5A" when x"93",
x"6B" when x"94",
x"60" when x"95",
x"7D" when x"96",
x"76" when x"97",
x"1F" when x"98",
x"14" when x"99",
x"09" when x"9A",
x"02" when x"9B",
x"33" when x"9C",
x"38" when x"9D",
x"25" when x"9E",
x"2E" when x"9F",
x"8C" when x"A0",
x"87" when x"A1",
x"9A" when x"A2",
x"91" when x"A3",
x"A0" when x"A4",
x"AB" when x"A5",
x"B6" when x"A6",
x"BD" when x"A7",
x"D4" when x"A8",
x"DF" when x"A9",
x"C2" when x"AA",
x"C9" when x"AB",
x"F8" when x"AC",
x"F3" when x"AD",
x"EE" when x"AE",
x"E5" when x"AF",
x"3C" when x"B0",
x"37" when x"B1",
x"2A" when x"B2",
x"21" when x"B3",
x"10" when x"B4",
x"1B" when x"B5",
x"06" when x"B6",
x"0D" when x"B7",
x"64" when x"B8",
x"6F" when x"B9",
x"72" when x"BA",
x"79" when x"BB",
x"48" when x"BC",
x"43" when x"BD",
x"5E" when x"BE",
x"55" when x"BF",
x"01" when x"C0",
x"0A" when x"C1",
x"17" when x"C2",
x"1C" when x"C3",
x"2D" when x"C4",
x"26" when x"C5",
x"3B" when x"C6",
x"30" when x"C7",
x"59" when x"C8",
x"52" when x"C9",
x"4F" when x"CA",
x"44" when x"CB",
x"75" when x"CC",
x"7E" when x"CD",
x"63" when x"CE",
x"68" when x"CF",
x"B1" when x"D0",
x"BA" when x"D1",
x"A7" when x"D2",
x"AC" when x"D3",
x"9D" when x"D4",
x"96" when x"D5",
x"8B" when x"D6",
x"80" when x"D7",
x"E9" when x"D8",
x"E2" when x"D9",
x"FF" when x"DA",
x"F4" when x"DB",
x"C5" when x"DC",
x"CE" when x"DD",
x"D3" when x"DE",
x"D8" when x"DF",
x"7A" when x"E0",
x"71" when x"E1",
x"6C" when x"E2",
x"67" when x"E3",
x"56" when x"E4",
x"5D" when x"E5",
x"40" when x"E6",
x"4B" when x"E7",
x"22" when x"E8",
x"29" when x"E9",
x"34" when x"EA",
x"3F" when x"EB",
x"0E" when x"EC",
x"05" when x"ED",
x"18" when x"EE",
x"13" when x"EF",
x"CA" when x"F0",
x"C1" when x"F1",
x"DC" when x"F2",
x"D7" when x"F3",
x"E6" when x"F4",
x"ED" when x"F5",
x"F0" when x"F6",
x"FB" when x"F7",
x"92" when x"F8",
x"99" when x"F9",
x"84" when x"FA",
x"8F" when x"FB",
x"BE" when x"FC",
x"B5" when x"FD",
x"A8" when x"FE",
x"A3" when x"FF",
x"00" when others;
end Behavioral;
architecture Behavioral of multiply_d is
begin
with i select o <=
x"00" when x"00",
x"0D" when x"01",
x"1A" when x"02",
x"17" when x"03",
x"34" when x"04",
x"39" when x"05",
x"2E" when x"06",
x"23" when x"07",
x"68" when x"08",
x"65" when x"09",
x"72" when x"0A",
x"7F" when x"0B",
x"5C" when x"0C",
x"51" when x"0D",
x"46" when x"0E",
x"4B" when x"0F",
x"D0" when x"10",
x"DD" when x"11",
x"CA" when x"12",
x"C7" when x"13",
x"E4" when x"14",
x"E9" when x"15",
x"FE" when x"16",
x"F3" when x"17",
x"B8" when x"18",
x"B5" when x"19",
x"A2" when x"1A",
x"AF" when x"1B",
x"8C" when x"1C",
x"81" when x"1D",
x"96" when x"1E",
x"9B" when x"1F",
x"BB" when x"20",
x"B6" when x"21",
x"A1" when x"22",
x"AC" when x"23",
x"8F" when x"24",
x"82" when x"25",
x"95" when x"26",
x"98" when x"27",
x"D3" when x"28",
x"DE" when x"29",
x"C9" when x"2A",
x"C4" when x"2B",
x"E7" when x"2C",
x"EA" when x"2D",
x"FD" when x"2E",
x"F0" when x"2F",
x"6B" when x"30",
x"66" when x"31",
x"71" when x"32",
x"7C" when x"33",
x"5F" when x"34",
x"52" when x"35",
x"45" when x"36",
x"48" when x"37",
x"03" when x"38",
x"0E" when x"39",
x"19" when x"3A",
x"14" when x"3B",
x"37" when x"3C",
x"3A" when x"3D",
x"2D" when x"3E",
x"20" when x"3F",
x"6D" when x"40",
x"60" when x"41",
x"77" when x"42",
x"7A" when x"43",
x"59" when x"44",
x"54" when x"45",
x"43" when x"46",
x"4E" when x"47",
x"05" when x"48",
x"08" when x"49",
x"1F" when x"4A",
x"12" when x"4B",
x"31" when x"4C",
x"3C" when x"4D",
x"2B" when x"4E",
x"26" when x"4F",
x"BD" when x"50",
x"B0" when x"51",
x"A7" when x"52",
x"AA" when x"53",
x"89" when x"54",
x"84" when x"55",
x"93" when x"56",
x"9E" when x"57",
x"D5" when x"58",
x"D8" when x"59",
x"CF" when x"5A",
x"C2" when x"5B",
x"E1" when x"5C",
x"EC" when x"5D",
x"FB" when x"5E",
x"F6" when x"5F",
x"D6" when x"60",
x"DB" when x"61",
x"CC" when x"62",
x"C1" when x"63",
x"E2" when x"64",
x"EF" when x"65",
x"F8" when x"66",
x"F5" when x"67",
x"BE" when x"68",
x"B3" when x"69",
x"A4" when x"6A",
x"A9" when x"6B",
x"8A" when x"6C",
x"87" when x"6D",
x"90" when x"6E",
x"9D" when x"6F",
x"06" when x"70",
x"0B" when x"71",
x"1C" when x"72",
x"11" when x"73",
x"32" when x"74",
x"3F" when x"75",
x"28" when x"76",
x"25" when x"77",
x"6E" when x"78",
x"63" when x"79",
x"74" when x"7A",
x"79" when x"7B",
x"5A" when x"7C",
x"57" when x"7D",
x"40" when x"7E",
x"4D" when x"7F",
x"DA" when x"80",
x"D7" when x"81",
x"C0" when x"82",
x"CD" when x"83",
x"EE" when x"84",
x"E3" when x"85",
x"F4" when x"86",
x"F9" when x"87",
x"B2" when x"88",
x"BF" when x"89",
x"A8" when x"8A",
x"A5" when x"8B",
x"86" when x"8C",
x"8B" when x"8D",
x"9C" when x"8E",
x"91" when x"8F",
x"0A" when x"90",
x"07" when x"91",
x"10" when x"92",
x"1D" when x"93",
x"3E" when x"94",
x"33" when x"95",
x"24" when x"96",
x"29" when x"97",
x"62" when x"98",
x"6F" when x"99",
x"78" when x"9A",
x"75" when x"9B",
x"56" when x"9C",
x"5B" when x"9D",
x"4C" when x"9E",
x"41" when x"9F",
x"61" when x"A0",
x"6C" when x"A1",
x"7B" when x"A2",
x"76" when x"A3",
x"55" when x"A4",
x"58" when x"A5",
x"4F" when x"A6",
x"42" when x"A7",
x"09" when x"A8",
x"04" when x"A9",
x"13" when x"AA",
x"1E" when x"AB",
x"3D" when x"AC",
x"30" when x"AD",
x"27" when x"AE",
x"2A" when x"AF",
x"B1" when x"B0",
x"BC" when x"B1",
x"AB" when x"B2",
x"A6" when x"B3",
x"85" when x"B4",
x"88" when x"B5",
x"9F" when x"B6",
x"92" when x"B7",
x"D9" when x"B8",
x"D4" when x"B9",
x"C3" when x"BA",
x"CE" when x"BB",
x"ED" when x"BC",
x"E0" when x"BD",
x"F7" when x"BE",
x"FA" when x"BF",
x"B7" when x"C0",
x"BA" when x"C1",
x"AD" when x"C2",
x"A0" when x"C3",
x"83" when x"C4",
x"8E" when x"C5",
x"99" when x"C6",
x"94" when x"C7",
x"DF" when x"C8",
x"D2" when x"C9",
x"C5" when x"CA",
x"C8" when x"CB",
x"EB" when x"CC",
x"E6" when x"CD",
x"F1" when x"CE",
x"FC" when x"CF",
x"67" when x"D0",
x"6A" when x"D1",
x"7D" when x"D2",
x"70" when x"D3",
x"53" when x"D4",
x"5E" when x"D5",
x"49" when x"D6",
x"44" when x"D7",
x"0F" when x"D8",
x"02" when x"D9",
x"15" when x"DA",
x"18" when x"DB",
x"3B" when x"DC",
x"36" when x"DD",
x"21" when x"DE",
x"2C" when x"DF",
x"0C" when x"E0",
x"01" when x"E1",
x"16" when x"E2",
x"1B" when x"E3",
x"38" when x"E4",
x"35" when x"E5",
x"22" when x"E6",
x"2F" when x"E7",
x"64" when x"E8",
x"69" when x"E9",
x"7E" when x"EA",
x"73" when x"EB",
x"50" when x"EC",
x"5D" when x"ED",
x"4A" when x"EE",
x"47" when x"EF",
x"DC" when x"F0",
x"D1" when x"F1",
x"C6" when x"F2",
x"CB" when x"F3",
x"E8" when x"F4",
x"E5" when x"F5",
x"F2" when x"F6",
x"FF" when x"F7",
x"B4" when x"F8",
x"B9" when x"F9",
x"AE" when x"FA",
x"A3" when x"FB",
x"80" when x"FC",
x"8D" when x"FD",
x"9A" when x"FE",
x"97" when x"FF",
x"00" when others;
end Behavioral;
architecture Behavioral of multiply_e is
begin
with i select o <=
x"00" when x"00",
x"0E" when x"01",
x"1C" when x"02",
x"12" when x"03",
x"38" when x"04",
x"36" when x"05",
x"24" when x"06",
x"2A" when x"07",
x"70" when x"08",
x"7E" when x"09",
x"6C" when x"0A",
x"62" when x"0B",
x"48" when x"0C",
x"46" when x"0D",
x"54" when x"0E",
x"5A" when x"0F",
x"E0" when x"10",
x"EE" when x"11",
x"FC" when x"12",
x"F2" when x"13",
x"D8" when x"14",
x"D6" when x"15",
x"C4" when x"16",
x"CA" when x"17",
x"90" when x"18",
x"9E" when x"19",
x"8C" when x"1A",
x"82" when x"1B",
x"A8" when x"1C",
x"A6" when x"1D",
x"B4" when x"1E",
x"BA" when x"1F",
x"DB" when x"20",
x"D5" when x"21",
x"C7" when x"22",
x"C9" when x"23",
x"E3" when x"24",
x"ED" when x"25",
x"FF" when x"26",
x"F1" when x"27",
x"AB" when x"28",
x"A5" when x"29",
x"B7" when x"2A",
x"B9" when x"2B",
x"93" when x"2C",
x"9D" when x"2D",
x"8F" when x"2E",
x"81" when x"2F",
x"3B" when x"30",
x"35" when x"31",
x"27" when x"32",
x"29" when x"33",
x"03" when x"34",
x"0D" when x"35",
x"1F" when x"36",
x"11" when x"37",
x"4B" when x"38",
x"45" when x"39",
x"57" when x"3A",
x"59" when x"3B",
x"73" when x"3C",
x"7D" when x"3D",
x"6F" when x"3E",
x"61" when x"3F",
x"AD" when x"40",
x"A3" when x"41",
x"B1" when x"42",
x"BF" when x"43",
x"95" when x"44",
x"9B" when x"45",
x"89" when x"46",
x"87" when x"47",
x"DD" when x"48",
x"D3" when x"49",
x"C1" when x"4A",
x"CF" when x"4B",
x"E5" when x"4C",
x"EB" when x"4D",
x"F9" when x"4E",
x"F7" when x"4F",
x"4D" when x"50",
x"43" when x"51",
x"51" when x"52",
x"5F" when x"53",
x"75" when x"54",
x"7B" when x"55",
x"69" when x"56",
x"67" when x"57",
x"3D" when x"58",
x"33" when x"59",
x"21" when x"5A",
x"2F" when x"5B",
x"05" when x"5C",
x"0B" when x"5D",
x"19" when x"5E",
x"17" when x"5F",
x"76" when x"60",
x"78" when x"61",
x"6A" when x"62",
x"64" when x"63",
x"4E" when x"64",
x"40" when x"65",
x"52" when x"66",
x"5C" when x"67",
x"06" when x"68",
x"08" when x"69",
x"1A" when x"6A",
x"14" when x"6B",
x"3E" when x"6C",
x"30" when x"6D",
x"22" when x"6E",
x"2C" when x"6F",
x"96" when x"70",
x"98" when x"71",
x"8A" when x"72",
x"84" when x"73",
x"AE" when x"74",
x"A0" when x"75",
x"B2" when x"76",
x"BC" when x"77",
x"E6" when x"78",
x"E8" when x"79",
x"FA" when x"7A",
x"F4" when x"7B",
x"DE" when x"7C",
x"D0" when x"7D",
x"C2" when x"7E",
x"CC" when x"7F",
x"41" when x"80",
x"4F" when x"81",
x"5D" when x"82",
x"53" when x"83",
x"79" when x"84",
x"77" when x"85",
x"65" when x"86",
x"6B" when x"87",
x"31" when x"88",
x"3F" when x"89",
x"2D" when x"8A",
x"23" when x"8B",
x"09" when x"8C",
x"07" when x"8D",
x"15" when x"8E",
x"1B" when x"8F",
x"A1" when x"90",
x"AF" when x"91",
x"BD" when x"92",
x"B3" when x"93",
x"99" when x"94",
x"97" when x"95",
x"85" when x"96",
x"8B" when x"97",
x"D1" when x"98",
x"DF" when x"99",
x"CD" when x"9A",
x"C3" when x"9B",
x"E9" when x"9C",
x"E7" when x"9D",
x"F5" when x"9E",
x"FB" when x"9F",
x"9A" when x"A0",
x"94" when x"A1",
x"86" when x"A2",
x"88" when x"A3",
x"A2" when x"A4",
x"AC" when x"A5",
x"BE" when x"A6",
x"B0" when x"A7",
x"EA" when x"A8",
x"E4" when x"A9",
x"F6" when x"AA",
x"F8" when x"AB",
x"D2" when x"AC",
x"DC" when x"AD",
x"CE" when x"AE",
x"C0" when x"AF",
x"7A" when x"B0",
x"74" when x"B1",
x"66" when x"B2",
x"68" when x"B3",
x"42" when x"B4",
x"4C" when x"B5",
x"5E" when x"B6",
x"50" when x"B7",
x"0A" when x"B8",
x"04" when x"B9",
x"16" when x"BA",
x"18" when x"BB",
x"32" when x"BC",
x"3C" when x"BD",
x"2E" when x"BE",
x"20" when x"BF",
x"EC" when x"C0",
x"E2" when x"C1",
x"F0" when x"C2",
x"FE" when x"C3",
x"D4" when x"C4",
x"DA" when x"C5",
x"C8" when x"C6",
x"C6" when x"C7",
x"9C" when x"C8",
x"92" when x"C9",
x"80" when x"CA",
x"8E" when x"CB",
x"A4" when x"CC",
x"AA" when x"CD",
x"B8" when x"CE",
x"B6" when x"CF",
x"0C" when x"D0",
x"02" when x"D1",
x"10" when x"D2",
x"1E" when x"D3",
x"34" when x"D4",
x"3A" when x"D5",
x"28" when x"D6",
x"26" when x"D7",
x"7C" when x"D8",
x"72" when x"D9",
x"60" when x"DA",
x"6E" when x"DB",
x"44" when x"DC",
x"4A" when x"DD",
x"58" when x"DE",
x"56" when x"DF",
x"37" when x"E0",
x"39" when x"E1",
x"2B" when x"E2",
x"25" when x"E3",
x"0F" when x"E4",
x"01" when x"E5",
x"13" when x"E6",
x"1D" when x"E7",
x"47" when x"E8",
x"49" when x"E9",
x"5B" when x"EA",
x"55" when x"EB",
x"7F" when x"EC",
x"71" when x"ED",
x"63" when x"EE",
x"6D" when x"EF",
x"D7" when x"F0",
x"D9" when x"F1",
x"CB" when x"F2",
x"C5" when x"F3",
x"EF" when x"F4",
x"E1" when x"F5",
x"F3" when x"F6",
x"FD" when x"F7",
x"A7" when x"F8",
x"A9" when x"F9",
x"BB" when x"FA",
x"B5" when x"FB",
x"9F" when x"FC",
x"91" when x"FD",
x"83" when x"FE",
x"8D" when x"FF",
x"00" when others;
end Behavioral;
|
<reponame>nallen01/phd-thesis-benchmarks
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.config.all;
use work.lib.all;
-- Entity
entity TimeIndependentPotassiumCurrent is
generic(
g_k1_max : signed(31 downto 0) := CREATE_FP(0.0075)
);
port (
clk : in std_logic;
-- Declare Inputs
time_in : in signed(31 downto 0);
v_in : in signed(31 downto 0);
ko_in : in signed(31 downto 0);
ki_in : in signed(31 downto 0);
r_in : in signed(31 downto 0);
t_in : in signed(31 downto 0);
f_in : in signed(31 downto 0);
k1_infinity_private_in : in signed(31 downto 0);
-- Declare Outputs
i_k1_out : out signed(31 downto 0);
e_k1_out : out signed(31 downto 0);
time_private_out : out signed(31 downto 0);
v_private_out : out signed(31 downto 0)
);
end;
-- Architecture
architecture behavior of TimeIndependentPotassiumCurrent is
-- Declare Outputs
signal i_k1 : signed(31 downto 0) := CREATE_FP(0.0);
signal e_k1 : signed(31 downto 0) := CREATE_FP(0.0);
signal time_private : signed(31 downto 0) := CREATE_FP(0.0);
signal v_private : signed(31 downto 0) := CREATE_FP(0.0);
-- Declare Internal Variables
signal g_k1 : signed(31 downto 0) := CREATE_FP(0.0);
signal k1_infinity : signed(31 downto 0) := CREATE_FP(0.0);
begin
process(clk)
-- Outputs
variable i_k1_update : signed(31 downto 0) := CREATE_FP(0.0);
variable e_k1_update : signed(31 downto 0) := CREATE_FP(0.0);
variable time_private_update : signed(31 downto 0) := CREATE_FP(0.0);
variable v_private_update : signed(31 downto 0) := CREATE_FP(0.0);
-- Internal Variables
variable g_k1_update : signed(31 downto 0) := CREATE_FP(0.0);
variable k1_infinity_update : signed(31 downto 0) := CREATE_FP(0.0);
begin
if clk'event and clk = '1' then
-- Perform Update Operations
g_k1_update := FP_MULT(g_k1_max, FP_SQRT((FP_DIV(ko_in, CREATE_FP(5.4)))));
e_k1_update := FP_MULT(FP_MULT((FP_DIV((FP_MULT(r_in, t_in)), f_in)), FP_LOG((FP_DIV(ko_in, ki_in)))), CREATE_FP(0.9999999999999998));
i_k1_update := FP_MULT(FP_MULT(g_k1, k1_infinity), (v_in - e_k1));
time_private_update := time_in;
v_private_update := v_in;
k1_infinity_update := k1_infinity_private_in;
-- Map Outputs
i_k1_out <= i_k1_update;
i_k1 <= i_k1_update;
e_k1_out <= e_k1_update;
e_k1 <= e_k1_update;
time_private_out <= time_private_update;
time_private <= time_private_update;
v_private_out <= v_private_update;
v_private <= v_private_update;
-- Map Internal Variables
g_k1 <= g_k1_update;
k1_infinity <= k1_infinity_update;
end if;
end process;
end architecture;
|
<reponame>trintinwibul/simulink_models
-- -------------------------------------------------------------
--
-- File Name: C:\Users\conno\Documents\NIH-GitHub\simulink_models\models\fft_filters\hdlsrc\fft_filters\fft_filters_DualRateDualPortRAM_generic.vhd
--
-- Generated by MATLAB 9.9 and HDL Coder 3.17
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: fft_filters_DualRateDualPortRAM_generic
-- Source Path: fft_filters/dataplane/FFT_Analysis_Synthesis_Left/Analysis/FFT Frame Buffering/DualRateDualPortRAM_generic
-- Hierarchy Level: 4
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY fft_filters_DualRateDualPortRAM_generic IS
GENERIC( AddrWidth : integer := 1;
DataWidth : integer := 1
);
PORT( clk : IN std_logic;
enb_1_16_0 : IN std_logic;
enb_1_2048_0 : IN std_logic;
din_A : IN std_logic_vector(DataWidth - 1 DOWNTO 0); -- generic width
addr_A : IN std_logic_vector(AddrWidth - 1 DOWNTO 0); -- generic width
we_A : IN std_logic; -- ufix1
din_B : IN std_logic_vector(DataWidth - 1 DOWNTO 0); -- generic width
addr_B : IN std_logic_vector(AddrWidth - 1 DOWNTO 0); -- generic width
we_B : IN std_logic; -- ufix1
doutA : OUT std_logic_vector(DataWidth - 1 DOWNTO 0); -- generic width
doutB : OUT std_logic_vector(DataWidth - 1 DOWNTO 0) -- generic width
);
END fft_filters_DualRateDualPortRAM_generic;
ARCHITECTURE rtl OF fft_filters_DualRateDualPortRAM_generic IS
-- Local Type Definitions
TYPE ram_type IS ARRAY (2**AddrWidth - 1 DOWNTO 0) of std_logic_vector(DataWidth - 1 DOWNTO 0);
-- Signals
SHARED VARIABLE ram : ram_type := (OTHERS => (OTHERS => '0'));
SIGNAL dout_a : std_logic_vector(DataWidth - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL dout_b : std_logic_vector(DataWidth - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL addr_A_unsigned : unsigned(AddrWidth - 1 DOWNTO 0); -- generic width
SIGNAL addr_B_unsigned : unsigned(AddrWidth - 1 DOWNTO 0); -- generic width
BEGIN
addr_A_unsigned <= unsigned(addr_A);
addr_B_unsigned <= unsigned(addr_B);
DualRateDualPortRAM_generic_processA: PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF enb_1_2048_0 = '1' THEN
IF we_A = '1' THEN
ram(to_integer(addr_A_unsigned)) := din_A;
dout_a <= din_A;
ELSE
dout_a <= ram(to_integer(addr_A_unsigned));
END IF;
END IF;
END IF;
END PROCESS DualRateDualPortRAM_generic_processA;
DualRateDualPortRAM_generic_processB: PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF enb_1_16_0 = '1' THEN
IF we_B = '1' THEN
ram(to_integer(addr_B_unsigned)) := din_B;
dout_b <= din_B;
ELSE
dout_b <= ram(to_integer(addr_B_unsigned));
END IF;
END IF;
END IF;
END PROCESS DualRateDualPortRAM_generic_processB;
doutA <= dout_a;
doutB <= dout_b;
END rtl;
|
<reponame>zerodois-bcc/SEL0632-2019
----------------------------
--<NAME>
--10724239
--
--Exercício 4.9.9
----------------------------
library ieee;
use ieee.std_logic_1164.all;
ENTITY deslocador IS
PORT (V : IN BIT_VECTOR (3 DOWNTO 0);
d0, d1 : IN BIT;
S : OUT BIT_VECTOR (3 DOWNTO 0));
END ENTITY deslocador;
ARCHITECTURE ifelse1 OF deslocador IS
abc: PROCESS (V, d0, d1)
BEGIN
IF d0 & d1 = "00" THEN S <= V(3) & V(2) & V(1) & V(0)
ELSIF d0 & d1 = "01" THEN S <= V(2) & V(1) & V(0) & V(3)
ELSIF d0 & d1 = "10" THEN S <= V(1) & V(0) & V(3) & V(2)
ELSE S <= V(0) & V(3) & V(2) & V(1);
END IF;
END PROCESS abc;
END ifelse1;
ARCHITECTURE casewhen1 OF deslocador IS
SIGNAL cat : std_logic_vector (1 DOWNTO 0);
abc: PROCESS (V, d0, d1)
BEGIN
cat <= d0 & d1;
CASE cat IS
WHEN "00" => S <= V(3) & V(2) & V(1) & V(0);
WHEN "01" => S <= V(2) & V(1) & V(0) & V(3);
WHEN "10" => S <= V(1) & V(0) & V(3) & V(2);
WHEN OTHERS => S <= V(0) & V(3) & V(2) & V(1);
END CASE;
END PROCESS abc;
END casewhen1;
ARCHITECTURE ifelse2 OF deslocador IS
abc: PROCESS (V, d0, d1)
BEGIN
IF d0 = '0' THEN
IF d1 = '0' THEN S <= V(3) & V(2) & V(1) & V(0);
ELSE S <= V(2) & V(1) & V(0) & V(3);
ELSIF d1 = '0' THEN S <= V(1) & V(0) & V(3) & V(2);
ELSE S <= V(0) & V(3) & V(2) & V(1);
END IF;
END PROCESS abc;
END ifelse2;
ARCHITECTURE casewhen2 OF deslocador IS
abc: PROCESS (V, d0, d1)
BEGIN
CASE d0 IS
WHEN '0' =>
CASE d1 IS
WHEN '0' => S <= V(3) & V(2) & V(1) & V(0);
WHEN OTHERS => S <= V(2) & V(1) & V(0) & V(3);
END CASE;
WHEN OTHERS =>
CASE d1 IS
WHEN '0' => S <= V(1) & V(0) & V(3) & V(2);
WHEN OTHERS => S <= V(0) & V(3) & V(2) & V(1);
END CASE;
END CASE;
END PROCESS abc;
END casewhen2;
|
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity control_system is
port ( quantity feedback, target : in voltage;
quantity output : out voltage );
end entity control_system;
----------------------------------------------------------------
architecture simple_feedback of control_system is
constant gain : real := 2.0;
begin
output == gain * ( target - feedback );
end architecture simple_feedback;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Control_Path is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
play : in STD_LOGIC;
uart_data : in STD_LOGIC_VECTOR(7 downto 0);
rx_done_tick : in STD_LOGIC;
clr : out STD_LOGIC;
inc : out STD_LOGIC;
timer_done : in STD_LOGIC;
ram_data : in STD_LOGIC_VECTOR(7 downto 0);
timer_on : out STD_LOGIC;
wr : out STD_LOGIC;
mute : out STD_LOGIC);
end Control_Path;
architecture Behavioral of Control_Path is
type state is (Initial, PlayState, MuteState, CheckForMuteAndPlay, WriteToRAM);
signal state_reg, state_nxt : state;
begin
process (rst, clk)
begin
if (rst = '1') then
state_reg <= Initial;
elsif (rising_edge(clk)) then
state_reg <= state_nxt;
end if;
end process;
process (state_reg, play, uart_data, rx_done_tick, timer_done, ram_data)
begin
state_nxt <= state_reg;
wr <= '0';
mute <= '0';
timer_on <= '0';
clr <= '0';
inc <= '0';
case state_reg is
when Initial =>
clr <= '1';
mute <= '1';
if (rx_done_tick = '1' and
(uart_data = "01100001" or uart_data = "01110011" or uart_data = "01100100" or -- a s d
uart_data = "01100110" or uart_data = "01100111" or uart_data = "01101000" -- f g h
or uart_data = "01101010" or uart_data = "01110001" or uart_data = "01110111" -- j q w
or uart_data = "01100101" or uart_data = "01110010" or uart_data = "01110100" -- e r t
or uart_data = "01111001" or uart_data = "01110101" or uart_data = "00001101")) then -- y u CR
state_nxt <= WriteToRAM;
else
state_nxt <= Initial;
end if;
when WriteToRAM =>
wr <= '1';
state_nxt <= CheckForMuteAndPlay;
when CheckForMuteAndPlay =>
if (play = '1') then
clr <= '1';
state_nxt <= PlayState;
elsif (uart_data = "00010000") then
state_nxt <= MuteState;
elsif (rx_done_tick = '1' and
(uart_data = "01100001" or uart_data = "01110011" or uart_data = "01100100" -- a s d
or uart_data = "01100110" or uart_data = "01100111" or uart_data = "01101000" -- f g h
or uart_data = "01101010" or uart_data = "01110001" or uart_data = "01110111" -- j q w
or uart_data = "01100101" or uart_data = "01110010" or uart_data = "01110100" -- e r t
or uart_data = "01111001" or uart_data = "01110101")) then -- y u
inc <= '1';
state_nxt <= WriteToRAM;
else
state_nxt <= CheckForMuteAndPlay;
end if;
when MuteState =>
mute <= '1';
if (rx_done_tick = '1' and
(uart_data = "01100001" or uart_data = "01110011" or uart_data = "01100100" -- a s d
or uart_data = "01100110" or uart_data = "01100111" or uart_data = "01101000" -- f g h
or uart_data = "01101010" or uart_data = "01110001" or uart_data = "01110111" -- j q w
or uart_data = "01100101" or uart_data = "01110010" or uart_data = "01110100" -- e r t
or uart_data = "01111001" or uart_data = "01110101")) then -- y u
inc <= '1';
state_nxt <= WriteToRAM;
else
state_nxt <= MuteState;
end if;
when PlayState =>
timer_on <= '1';
if (rx_done_tick = '1' and
(uart_data = "01100001" or uart_data = "01110011" or uart_data = "01100100" -- a s d
or uart_data = "01100110" or uart_data = "01100111" or uart_data = "01101000" -- f g h
or uart_data = "01101010" or uart_data = "01110001" or uart_data = "01110111" -- j q w
or uart_data = "01100101" or uart_data = "01110010" or uart_data = "01110100" -- e r t
or uart_data = "01111001" or uart_data = "01110101")) then -- y u
inc <= '1';
state_nxt <= WriteToRAM;
elsif (play = '0') then
state_nxt <= CheckForMuteAndPlay;
elsif (not (ram_data = "01100001" or ram_data = "01110011" or ram_data = "01100100" -- a s d
or ram_data = "01100110" or ram_data = "01100111" or ram_data = "01101000" -- f g h
or ram_data = "01101010" or ram_data = "01110001" or ram_data = "01110111" -- j q w
or ram_data = "01100101" or ram_data = "01110010" or ram_data = "01110100" -- e r t
or ram_data = "01111001" or ram_data = "01110101")) then -- y u
clr <= '1';
state_nxt <= CheckForMuteAndPlay;
elsif (timer_done = '1') then
inc <= '1';
state_nxt <= PlayState;
else
state_nxt <= PlayState;
end if;
end case;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- File Name: /home/cb54103/Documents/fpga-open-speech-tools/simulink_models/models/Dynamic_Compression_Model/hdlsrc/sm_DynamicCompression/sm_DynamicCompression_Addr_Splitter.vhd
--
-- Generated by MATLAB 9.7 and HDL Coder 3.15
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: sm_DynamicCompression_Addr_Splitter
-- Source Path: sm_DynamicCompression/dataplane/Avalon Data Processing/Left Channel Processing/recalculate/Nchan_FbankAGC_AID/Addr_Splitter
-- Hierarchy Level: 5
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY sm_DynamicCompression_Addr_Splitter IS
PORT( Register_Addr : IN std_logic_vector(31 DOWNTO 0); -- sfix32_En28
Addr : OUT std_logic_vector(8 DOWNTO 0); -- ufix9
Sel : OUT std_logic_vector(2 DOWNTO 0) -- ufix3
);
END sm_DynamicCompression_Addr_Splitter;
ARCHITECTURE rtl OF sm_DynamicCompression_Addr_Splitter IS
-- Signals
SIGNAL Register_Addr_signed : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL Data_Type_Conversion_out1 : unsigned(11 DOWNTO 0); -- ufix12
SIGNAL Bit_Slice_out1 : unsigned(8 DOWNTO 0); -- ufix9
SIGNAL Constant1_out1 : std_logic;
SIGNAL Constant_out1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL top3Bits : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Switch_out1 : unsigned(2 DOWNTO 0); -- ufix3
BEGIN
-- Figure out where 7+ comes from
--
-- Addr line contains the local address bits: 0-2^(3+M_bits) -1
--
-- Select Line is 000 to 100, if 101 or greater, don't write to any of these blocks
Register_Addr_signed <= signed(Register_Addr);
Data_Type_Conversion_out1 <= unsigned(resize(Register_Addr_signed(31 DOWNTO 28), 12));
--
Bit_Slice_out1 <= Data_Type_Conversion_out1(8 DOWNTO 0);
Addr <= std_logic_vector(Bit_Slice_out1);
Constant1_out1 <= '0';
Constant_out1 <= to_unsigned(16#5#, 3);
--
top3Bits <= Data_Type_Conversion_out1(11 DOWNTO 9);
Switch_out1 <= Constant_out1 WHEN Constant1_out1 = '0' ELSE
top3Bits;
Sel <= std_logic_vector(Switch_out1);
END rtl;
|
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|
<gh_stars>0
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 18.1 (Release Build #625)
--
-- Legal Notice: Copyright 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from i_sfc_logic_c2_for_body14_conv2d1x1_c2_enter_conv2d1x176
-- VHDL created on Sat Mar 12 13:30:05 2022
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY altera_lnsim;
USE altera_lnsim.altera_lnsim_components.altera_syncram;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity i_sfc_logic_c2_for_body14_conv2d1x1_c2_enter_conv2d1x176 is
port (
in_c2_eni5_0 : in std_logic_vector(0 downto 0); -- ufix1
in_c2_eni5_1 : in std_logic_vector(31 downto 0); -- float32_m23
in_c2_eni5_2 : in std_logic_vector(31 downto 0); -- float32_m23
in_c2_eni5_3 : in std_logic_vector(31 downto 0); -- float32_m23
in_c2_eni5_4 : in std_logic_vector(31 downto 0); -- ufix32
in_c2_eni5_5 : in std_logic_vector(31 downto 0); -- float32_m23
in_c2_eni5_6 : in std_logic_vector(31 downto 0); -- float32_m23
in_c2_eni5_7 : in std_logic_vector(31 downto 0); -- float32_m23
in_c2_eni5_8 : in std_logic_vector(31 downto 0); -- float32_m23
in_i_valid : in std_logic_vector(0 downto 0); -- ufix1
out_c2_exi3_0 : out std_logic_vector(0 downto 0); -- ufix1
out_c2_exi3_1 : out std_logic_vector(31 downto 0); -- float32_m23
out_c2_exi3_2 : out std_logic_vector(31 downto 0); -- float32_m23
out_c2_exi3_3 : out std_logic_vector(31 downto 0); -- float32_m23
out_o_valid : out std_logic_vector(0 downto 0); -- ufix1
clock : in std_logic;
resetn : in std_logic
);
end i_sfc_logic_c2_for_body14_conv2d1x1_c2_enter_conv2d1x176;
architecture normal of i_sfc_logic_c2_for_body14_conv2d1x1_c2_enter_conv2d1x176 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
component floatComponent_i_sfc_logic_c2_for_body14_conv2d1x1_c2_enter_conv2d1x176_addBlockA0Z3d06o00rf00d06of5q0u is
port (
in_0 : in std_logic_vector(31 downto 0); -- Floating Point
in_1 : in std_logic_vector(31 downto 0); -- Floating Point
out_primWireOut : out std_logic_vector(31 downto 0); -- Floating Point
clock : in std_logic;
resetn : in std_logic
);
end component;
component floatComponent_i_sfc_logic_c2_for_body14_conv2d1x1_c2_enter_conv2d1x176_multBlocA0Zp06o303d06o00rf01pzc is
port (
in_0 : in std_logic_vector(31 downto 0); -- Floating Point
in_1 : in std_logic_vector(31 downto 0); -- Floating Point
out_primWireOut : out std_logic_vector(31 downto 0); -- Floating Point
clock : in std_logic;
resetn : in std_logic
);
end component;
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal i_add24_1_conv2d1x1_out_primWireOut : STD_LOGIC_VECTOR (31 downto 0);
signal i_add24_2_conv2d1x1_out_primWireOut : STD_LOGIC_VECTOR (31 downto 0);
signal i_add24_conv2d1x1_out_primWireOut : STD_LOGIC_VECTOR (31 downto 0);
signal i_mul23_1_conv2d1x1_out_primWireOut : STD_LOGIC_VECTOR (31 downto 0);
signal i_mul23_2_conv2d1x1_out_primWireOut : STD_LOGIC_VECTOR (31 downto 0);
signal i_mul23_conv2d1x1_out_primWireOut : STD_LOGIC_VECTOR (31 downto 0);
signal redist0_i_mul23_conv2d1x1_out_primWireOut_1_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist3_i_add24_conv2d1x1_out_primWireOut_1_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist5_i_add24_1_conv2d1x1_out_primWireOut_1_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist8_sync_in_aunroll_x_in_i_valid_52_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_inputreg_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_outputreg_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_reset0 : std_logic;
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_ia : STD_LOGIC_VECTOR (31 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_aa : STD_LOGIC_VECTOR (4 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_ab : STD_LOGIC_VECTOR (4 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_iq : STD_LOGIC_VECTOR (31 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_q : STD_LOGIC_VECTOR (4 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_i : UNSIGNED (4 downto 0);
attribute preserve : boolean;
attribute preserve of redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_i : signal is true;
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_eq : std_logic;
attribute preserve of redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_eq : signal is true;
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_wraddr_q : STD_LOGIC_VECTOR (4 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_last_q : STD_LOGIC_VECTOR (5 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_cmp_b : STD_LOGIC_VECTOR (5 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_cmp_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_cmpReg_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_notEnable_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_nor_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_sticky_ena_q : STD_LOGIC_VECTOR (0 downto 0);
attribute dont_merge : boolean;
attribute dont_merge of redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_sticky_ena_q : signal is true;
signal redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_enaAnd_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_inputreg_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_outputreg_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_reset0 : std_logic;
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_ia : STD_LOGIC_VECTOR (31 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_aa : STD_LOGIC_VECTOR (3 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_ab : STD_LOGIC_VECTOR (3 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_iq : STD_LOGIC_VECTOR (31 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_q : STD_LOGIC_VECTOR (3 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_i : UNSIGNED (3 downto 0);
attribute preserve of redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_i : signal is true;
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_eq : std_logic;
attribute preserve of redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_eq : signal is true;
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_wraddr_q : STD_LOGIC_VECTOR (3 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_last_q : STD_LOGIC_VECTOR (4 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_cmp_b : STD_LOGIC_VECTOR (4 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_cmp_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_cmpReg_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_notEnable_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_nor_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_sticky_ena_q : STD_LOGIC_VECTOR (0 downto 0);
attribute dont_merge of redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_sticky_ena_q : signal is true;
signal redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_enaAnd_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_inputreg_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_outputreg_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_reset0 : std_logic;
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_ia : STD_LOGIC_VECTOR (31 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_aa : STD_LOGIC_VECTOR (4 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_ab : STD_LOGIC_VECTOR (4 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_iq : STD_LOGIC_VECTOR (31 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_q : STD_LOGIC_VECTOR (4 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_i : UNSIGNED (4 downto 0);
attribute preserve of redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_i : signal is true;
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_eq : std_logic;
attribute preserve of redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_eq : signal is true;
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_wraddr_q : STD_LOGIC_VECTOR (4 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_last_q : STD_LOGIC_VECTOR (5 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_cmp_b : STD_LOGIC_VECTOR (5 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_cmp_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_cmpReg_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_notEnable_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_nor_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_sticky_ena_q : STD_LOGIC_VECTOR (0 downto 0);
attribute dont_merge of redist4_i_add24_conv2d1x1_out_primWireOut_30_sticky_ena_q : signal is true;
signal redist4_i_add24_conv2d1x1_out_primWireOut_30_enaAnd_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_inputreg_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_outputreg_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_reset0 : std_logic;
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_ia : STD_LOGIC_VECTOR (31 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_aa : STD_LOGIC_VECTOR (3 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_ab : STD_LOGIC_VECTOR (3 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_iq : STD_LOGIC_VECTOR (31 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_q : STD_LOGIC_VECTOR (3 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_i : UNSIGNED (3 downto 0);
attribute preserve of redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_i : signal is true;
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_eq : std_logic;
attribute preserve of redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_eq : signal is true;
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_wraddr_q : STD_LOGIC_VECTOR (3 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_last_q : STD_LOGIC_VECTOR (4 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_cmp_b : STD_LOGIC_VECTOR (4 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_cmp_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_cmpReg_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_notEnable_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_nor_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_sticky_ena_q : STD_LOGIC_VECTOR (0 downto 0);
attribute dont_merge of redist6_i_add24_1_conv2d1x1_out_primWireOut_15_sticky_ena_q : signal is true;
signal redist6_i_add24_1_conv2d1x1_out_primWireOut_15_enaAnd_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_outputreg_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_reset0 : std_logic;
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_ia : STD_LOGIC_VECTOR (31 downto 0);
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_aa : STD_LOGIC_VECTOR (2 downto 0);
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_ab : STD_LOGIC_VECTOR (2 downto 0);
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_iq : STD_LOGIC_VECTOR (31 downto 0);
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_q : STD_LOGIC_VECTOR (31 downto 0);
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_q : STD_LOGIC_VECTOR (2 downto 0);
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_i : UNSIGNED (2 downto 0);
attribute preserve of redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_i : signal is true;
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_eq : std_logic;
attribute preserve of redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_eq : signal is true;
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_wraddr_q : STD_LOGIC_VECTOR (2 downto 0);
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_last_q : STD_LOGIC_VECTOR (3 downto 0);
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_cmp_b : STD_LOGIC_VECTOR (3 downto 0);
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_cmp_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_cmpReg_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_notEnable_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_nor_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_sticky_ena_q : STD_LOGIC_VECTOR (0 downto 0);
attribute dont_merge of redist7_sync_in_aunroll_x_in_c2_eni5_6_8_sticky_ena_q : signal is true;
signal redist7_sync_in_aunroll_x_in_c2_eni5_6_8_enaAnd_q : STD_LOGIC_VECTOR (0 downto 0);
begin
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- redist8_sync_in_aunroll_x_in_i_valid_52(DELAY,19)
redist8_sync_in_aunroll_x_in_i_valid_52 : dspba_delay
GENERIC MAP ( width => 1, depth => 52, reset_kind => "ASYNC", reset_high => '0' )
PORT MAP ( xin => in_i_valid, xout => redist8_sync_in_aunroll_x_in_i_valid_52_q, clk => clock, aclr => resetn );
-- redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_notEnable(LOGICAL,28)
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_notEnable_q <= STD_LOGIC_VECTOR(not (VCC_q));
-- redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_nor(LOGICAL,29)
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_nor_q <= not (redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_notEnable_q or redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_sticky_ena_q);
-- redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_last(CONSTANT,25)
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_last_q <= "011010";
-- redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_cmp(LOGICAL,26)
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_cmp_b <= STD_LOGIC_VECTOR("0" & redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_q);
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_cmp_q <= "1" WHEN redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_last_q = redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_cmp_b ELSE "0";
-- redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_cmpReg(REG,27)
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_cmpReg_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_cmpReg_q <= "0";
ELSIF (clock'EVENT AND clock = '1') THEN
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_cmpReg_q <= STD_LOGIC_VECTOR(redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_cmp_q);
END IF;
END PROCESS;
-- redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_sticky_ena(REG,30)
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_sticky_ena_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_sticky_ena_q <= "0";
ELSIF (clock'EVENT AND clock = '1') THEN
IF (redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_nor_q = "1") THEN
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_sticky_ena_q <= STD_LOGIC_VECTOR(redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_cmpReg_q);
END IF;
END IF;
END PROCESS;
-- redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_enaAnd(LOGICAL,31)
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_enaAnd_q <= redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_sticky_ena_q and VCC_q;
-- redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt(COUNTER,23)
-- low=0, high=27, step=1, init=0
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_i <= TO_UNSIGNED(0, 5);
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_eq <= '0';
ELSIF (clock'EVENT AND clock = '1') THEN
IF (redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_i = TO_UNSIGNED(26, 5)) THEN
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_eq <= '1';
ELSE
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_eq <= '0';
END IF;
IF (redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_eq = '1') THEN
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_i <= redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_i + 5;
ELSE
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_i <= redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_i, 5)));
-- i_mul23_2_conv2d1x1(BLACKBOX,9)@141
-- out out_primWireOut@148
thei_mul23_2_conv2d1x1 : floatComponent_i_sfc_logic_c2_for_body14_conv2d1x1_c2_enter_conv2d1x176_multBlocA0Zp06o303d06o00rf01pzc
PORT MAP (
in_0 => in_c2_eni5_8,
in_1 => in_c2_eni5_3,
out_primWireOut => i_mul23_2_conv2d1x1_out_primWireOut,
clock => clock,
resetn => resetn
);
-- redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_inputreg(DELAY,20)
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC", reset_high => '0' )
PORT MAP ( xin => i_mul23_2_conv2d1x1_out_primWireOut, xout => redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_inputreg_q, clk => clock, aclr => resetn );
-- redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_wraddr(REG,24)
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_wraddr_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_wraddr_q <= "11011";
ELSIF (clock'EVENT AND clock = '1') THEN
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_wraddr_q <= STD_LOGIC_VECTOR(redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_q);
END IF;
END PROCESS;
-- redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem(DUALMEM,22)
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_ia <= STD_LOGIC_VECTOR(redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_inputreg_q);
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_aa <= redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_wraddr_q;
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_ab <= redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_rdcnt_q;
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_reset0 <= not (resetn);
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_dmem : altera_syncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 5,
numwords_a => 28,
width_b => 32,
widthad_b => 5,
numwords_b => 28,
lpm_type => "altera_syncram",
width_byteena_a => 1,
address_reg_b => "CLOCK0",
indata_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "TRUE",
intended_device_family => "Cyclone V"
)
PORT MAP (
clocken1 => redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_enaAnd_q(0),
clocken0 => VCC_q(0),
clock0 => clock,
aclr1 => redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_reset0,
clock1 => clock,
address_a => redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_aa,
data_a => redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_ia,
wren_a => VCC_q(0),
address_b => redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_ab,
q_b => redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_iq
);
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_q <= redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_iq(31 downto 0);
-- redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_outputreg(DELAY,21)
redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_outputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC", reset_high => '0' )
PORT MAP ( xin => redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_mem_q, xout => redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_outputreg_q, clk => clock, aclr => resetn );
-- redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_notEnable(LOGICAL,40)
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_notEnable_q <= STD_LOGIC_VECTOR(not (VCC_q));
-- redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_nor(LOGICAL,41)
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_nor_q <= not (redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_notEnable_q or redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_sticky_ena_q);
-- redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_last(CONSTANT,37)
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_last_q <= "01011";
-- redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_cmp(LOGICAL,38)
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_cmp_b <= STD_LOGIC_VECTOR("0" & redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_q);
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_cmp_q <= "1" WHEN redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_last_q = redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_cmp_b ELSE "0";
-- redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_cmpReg(REG,39)
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_cmpReg_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_cmpReg_q <= "0";
ELSIF (clock'EVENT AND clock = '1') THEN
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_cmpReg_q <= STD_LOGIC_VECTOR(redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_cmp_q);
END IF;
END PROCESS;
-- redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_sticky_ena(REG,42)
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_sticky_ena_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_sticky_ena_q <= "0";
ELSIF (clock'EVENT AND clock = '1') THEN
IF (redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_nor_q = "1") THEN
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_sticky_ena_q <= STD_LOGIC_VECTOR(redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_cmpReg_q);
END IF;
END IF;
END PROCESS;
-- redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_enaAnd(LOGICAL,43)
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_enaAnd_q <= redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_sticky_ena_q and VCC_q;
-- redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt(COUNTER,35)
-- low=0, high=12, step=1, init=0
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_i <= TO_UNSIGNED(0, 4);
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_eq <= '0';
ELSIF (clock'EVENT AND clock = '1') THEN
IF (redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_i = TO_UNSIGNED(11, 4)) THEN
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_eq <= '1';
ELSE
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_eq <= '0';
END IF;
IF (redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_eq = '1') THEN
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_i <= redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_i + 4;
ELSE
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_i <= redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_i, 4)));
-- i_mul23_1_conv2d1x1(BLACKBOX,8)@141
-- out out_primWireOut@148
thei_mul23_1_conv2d1x1 : floatComponent_i_sfc_logic_c2_for_body14_conv2d1x1_c2_enter_conv2d1x176_multBlocA0Zp06o303d06o00rf01pzc
PORT MAP (
in_0 => in_c2_eni5_7,
in_1 => in_c2_eni5_2,
out_primWireOut => i_mul23_1_conv2d1x1_out_primWireOut,
clock => clock,
resetn => resetn
);
-- redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_inputreg(DELAY,32)
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC", reset_high => '0' )
PORT MAP ( xin => i_mul23_1_conv2d1x1_out_primWireOut, xout => redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_inputreg_q, clk => clock, aclr => resetn );
-- redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_wraddr(REG,36)
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_wraddr_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_wraddr_q <= "1100";
ELSIF (clock'EVENT AND clock = '1') THEN
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_wraddr_q <= STD_LOGIC_VECTOR(redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_q);
END IF;
END PROCESS;
-- redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem(DUALMEM,34)
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_ia <= STD_LOGIC_VECTOR(redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_inputreg_q);
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_aa <= redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_wraddr_q;
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_ab <= redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_rdcnt_q;
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_reset0 <= not (resetn);
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_dmem : altera_syncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 13,
width_b => 32,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altera_syncram",
width_byteena_a => 1,
address_reg_b => "CLOCK0",
indata_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "TRUE",
intended_device_family => "Cyclone V"
)
PORT MAP (
clocken1 => redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_enaAnd_q(0),
clocken0 => VCC_q(0),
clock0 => clock,
aclr1 => redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_reset0,
clock1 => clock,
address_a => redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_aa,
data_a => redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_ia,
wren_a => VCC_q(0),
address_b => redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_ab,
q_b => redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_iq
);
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_q <= redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_iq(31 downto 0);
-- redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_outputreg(DELAY,33)
redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_outputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC", reset_high => '0' )
PORT MAP ( xin => redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_mem_q, xout => redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_outputreg_q, clk => clock, aclr => resetn );
-- i_mul23_conv2d1x1(BLACKBOX,10)@141
-- out out_primWireOut@148
thei_mul23_conv2d1x1 : floatComponent_i_sfc_logic_c2_for_body14_conv2d1x1_c2_enter_conv2d1x176_multBlocA0Zp06o303d06o00rf01pzc
PORT MAP (
in_0 => in_c2_eni5_5,
in_1 => in_c2_eni5_1,
out_primWireOut => i_mul23_conv2d1x1_out_primWireOut,
clock => clock,
resetn => resetn
);
-- redist0_i_mul23_conv2d1x1_out_primWireOut_1(DELAY,11)
redist0_i_mul23_conv2d1x1_out_primWireOut_1 : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC", reset_high => '0' )
PORT MAP ( xin => i_mul23_conv2d1x1_out_primWireOut, xout => redist0_i_mul23_conv2d1x1_out_primWireOut_1_q, clk => clock, aclr => resetn );
-- redist7_sync_in_aunroll_x_in_c2_eni5_6_8_notEnable(LOGICAL,75)
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_notEnable_q <= STD_LOGIC_VECTOR(not (VCC_q));
-- redist7_sync_in_aunroll_x_in_c2_eni5_6_8_nor(LOGICAL,76)
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_nor_q <= not (redist7_sync_in_aunroll_x_in_c2_eni5_6_8_notEnable_q or redist7_sync_in_aunroll_x_in_c2_eni5_6_8_sticky_ena_q);
-- redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_last(CONSTANT,72)
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_last_q <= "0100";
-- redist7_sync_in_aunroll_x_in_c2_eni5_6_8_cmp(LOGICAL,73)
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_cmp_b <= STD_LOGIC_VECTOR("0" & redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_q);
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_cmp_q <= "1" WHEN redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_last_q = redist7_sync_in_aunroll_x_in_c2_eni5_6_8_cmp_b ELSE "0";
-- redist7_sync_in_aunroll_x_in_c2_eni5_6_8_cmpReg(REG,74)
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_cmpReg_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_cmpReg_q <= "0";
ELSIF (clock'EVENT AND clock = '1') THEN
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_cmpReg_q <= STD_LOGIC_VECTOR(redist7_sync_in_aunroll_x_in_c2_eni5_6_8_cmp_q);
END IF;
END PROCESS;
-- redist7_sync_in_aunroll_x_in_c2_eni5_6_8_sticky_ena(REG,77)
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_sticky_ena_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_sticky_ena_q <= "0";
ELSIF (clock'EVENT AND clock = '1') THEN
IF (redist7_sync_in_aunroll_x_in_c2_eni5_6_8_nor_q = "1") THEN
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_sticky_ena_q <= STD_LOGIC_VECTOR(redist7_sync_in_aunroll_x_in_c2_eni5_6_8_cmpReg_q);
END IF;
END IF;
END PROCESS;
-- redist7_sync_in_aunroll_x_in_c2_eni5_6_8_enaAnd(LOGICAL,78)
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_enaAnd_q <= redist7_sync_in_aunroll_x_in_c2_eni5_6_8_sticky_ena_q and VCC_q;
-- redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt(COUNTER,70)
-- low=0, high=5, step=1, init=0
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_i <= TO_UNSIGNED(0, 3);
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_eq <= '0';
ELSIF (clock'EVENT AND clock = '1') THEN
IF (redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_i = TO_UNSIGNED(4, 3)) THEN
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_eq <= '1';
ELSE
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_eq <= '0';
END IF;
IF (redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_eq = '1') THEN
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_i <= redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_i + 3;
ELSE
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_i <= redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_i, 3)));
-- redist7_sync_in_aunroll_x_in_c2_eni5_6_8_wraddr(REG,71)
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_wraddr_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_wraddr_q <= "101";
ELSIF (clock'EVENT AND clock = '1') THEN
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_wraddr_q <= STD_LOGIC_VECTOR(redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_q);
END IF;
END PROCESS;
-- redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem(DUALMEM,69)
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_ia <= STD_LOGIC_VECTOR(in_c2_eni5_6);
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_aa <= redist7_sync_in_aunroll_x_in_c2_eni5_6_8_wraddr_q;
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_ab <= redist7_sync_in_aunroll_x_in_c2_eni5_6_8_rdcnt_q;
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_reset0 <= not (resetn);
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_dmem : altera_syncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 3,
numwords_a => 6,
width_b => 32,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altera_syncram",
width_byteena_a => 1,
address_reg_b => "CLOCK0",
indata_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "TRUE",
intended_device_family => "Cyclone V"
)
PORT MAP (
clocken1 => redist7_sync_in_aunroll_x_in_c2_eni5_6_8_enaAnd_q(0),
clocken0 => VCC_q(0),
clock0 => clock,
aclr1 => redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_reset0,
clock1 => clock,
address_a => redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_aa,
data_a => redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_ia,
wren_a => VCC_q(0),
address_b => redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_ab,
q_b => redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_iq
);
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_q <= redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_iq(31 downto 0);
-- redist7_sync_in_aunroll_x_in_c2_eni5_6_8_outputreg(DELAY,68)
redist7_sync_in_aunroll_x_in_c2_eni5_6_8_outputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC", reset_high => '0' )
PORT MAP ( xin => redist7_sync_in_aunroll_x_in_c2_eni5_6_8_mem_q, xout => redist7_sync_in_aunroll_x_in_c2_eni5_6_8_outputreg_q, clk => clock, aclr => resetn );
-- i_add24_conv2d1x1(BLACKBOX,7)@149
-- out out_primWireOut@163
thei_add24_conv2d1x1 : floatComponent_i_sfc_logic_c2_for_body14_conv2d1x1_c2_enter_conv2d1x176_addBlockA0Z3d06o00rf00d06of5q0u
PORT MAP (
in_0 => redist7_sync_in_aunroll_x_in_c2_eni5_6_8_outputreg_q,
in_1 => redist0_i_mul23_conv2d1x1_out_primWireOut_1_q,
out_primWireOut => i_add24_conv2d1x1_out_primWireOut,
clock => clock,
resetn => resetn
);
-- redist3_i_add24_conv2d1x1_out_primWireOut_1(DELAY,14)
redist3_i_add24_conv2d1x1_out_primWireOut_1 : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC", reset_high => '0' )
PORT MAP ( xin => i_add24_conv2d1x1_out_primWireOut, xout => redist3_i_add24_conv2d1x1_out_primWireOut_1_q, clk => clock, aclr => resetn );
-- i_add24_1_conv2d1x1(BLACKBOX,5)@164
-- out out_primWireOut@178
thei_add24_1_conv2d1x1 : floatComponent_i_sfc_logic_c2_for_body14_conv2d1x1_c2_enter_conv2d1x176_addBlockA0Z3d06o00rf00d06of5q0u
PORT MAP (
in_0 => redist3_i_add24_conv2d1x1_out_primWireOut_1_q,
in_1 => redist2_i_mul23_1_conv2d1x1_out_primWireOut_16_outputreg_q,
out_primWireOut => i_add24_1_conv2d1x1_out_primWireOut,
clock => clock,
resetn => resetn
);
-- redist5_i_add24_1_conv2d1x1_out_primWireOut_1(DELAY,16)
redist5_i_add24_1_conv2d1x1_out_primWireOut_1 : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC", reset_high => '0' )
PORT MAP ( xin => i_add24_1_conv2d1x1_out_primWireOut, xout => redist5_i_add24_1_conv2d1x1_out_primWireOut_1_q, clk => clock, aclr => resetn );
-- i_add24_2_conv2d1x1(BLACKBOX,6)@179
-- out out_primWireOut@193
thei_add24_2_conv2d1x1 : floatComponent_i_sfc_logic_c2_for_body14_conv2d1x1_c2_enter_conv2d1x176_addBlockA0Z3d06o00rf00d06of5q0u
PORT MAP (
in_0 => redist5_i_add24_1_conv2d1x1_out_primWireOut_1_q,
in_1 => redist1_i_mul23_2_conv2d1x1_out_primWireOut_31_outputreg_q,
out_primWireOut => i_add24_2_conv2d1x1_out_primWireOut,
clock => clock,
resetn => resetn
);
-- redist6_i_add24_1_conv2d1x1_out_primWireOut_15_notEnable(LOGICAL,64)
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_notEnable_q <= STD_LOGIC_VECTOR(not (VCC_q));
-- redist6_i_add24_1_conv2d1x1_out_primWireOut_15_nor(LOGICAL,65)
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_nor_q <= not (redist6_i_add24_1_conv2d1x1_out_primWireOut_15_notEnable_q or redist6_i_add24_1_conv2d1x1_out_primWireOut_15_sticky_ena_q);
-- redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_last(CONSTANT,61)
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_last_q <= "01001";
-- redist6_i_add24_1_conv2d1x1_out_primWireOut_15_cmp(LOGICAL,62)
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_cmp_b <= STD_LOGIC_VECTOR("0" & redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_q);
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_cmp_q <= "1" WHEN redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_last_q = redist6_i_add24_1_conv2d1x1_out_primWireOut_15_cmp_b ELSE "0";
-- redist6_i_add24_1_conv2d1x1_out_primWireOut_15_cmpReg(REG,63)
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_cmpReg_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_cmpReg_q <= "0";
ELSIF (clock'EVENT AND clock = '1') THEN
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_cmpReg_q <= STD_LOGIC_VECTOR(redist6_i_add24_1_conv2d1x1_out_primWireOut_15_cmp_q);
END IF;
END PROCESS;
-- redist6_i_add24_1_conv2d1x1_out_primWireOut_15_sticky_ena(REG,66)
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_sticky_ena_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_sticky_ena_q <= "0";
ELSIF (clock'EVENT AND clock = '1') THEN
IF (redist6_i_add24_1_conv2d1x1_out_primWireOut_15_nor_q = "1") THEN
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_sticky_ena_q <= STD_LOGIC_VECTOR(redist6_i_add24_1_conv2d1x1_out_primWireOut_15_cmpReg_q);
END IF;
END IF;
END PROCESS;
-- redist6_i_add24_1_conv2d1x1_out_primWireOut_15_enaAnd(LOGICAL,67)
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_enaAnd_q <= redist6_i_add24_1_conv2d1x1_out_primWireOut_15_sticky_ena_q and VCC_q;
-- redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt(COUNTER,59)
-- low=0, high=10, step=1, init=0
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_i <= TO_UNSIGNED(0, 4);
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_eq <= '0';
ELSIF (clock'EVENT AND clock = '1') THEN
IF (redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_i = TO_UNSIGNED(9, 4)) THEN
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_eq <= '1';
ELSE
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_eq <= '0';
END IF;
IF (redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_eq = '1') THEN
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_i <= redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_i + 6;
ELSE
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_i <= redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_i, 4)));
-- redist6_i_add24_1_conv2d1x1_out_primWireOut_15_inputreg(DELAY,56)
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC", reset_high => '0' )
PORT MAP ( xin => redist5_i_add24_1_conv2d1x1_out_primWireOut_1_q, xout => redist6_i_add24_1_conv2d1x1_out_primWireOut_15_inputreg_q, clk => clock, aclr => resetn );
-- redist6_i_add24_1_conv2d1x1_out_primWireOut_15_wraddr(REG,60)
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_wraddr_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_wraddr_q <= "1010";
ELSIF (clock'EVENT AND clock = '1') THEN
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_wraddr_q <= STD_LOGIC_VECTOR(redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_q);
END IF;
END PROCESS;
-- redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem(DUALMEM,58)
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_ia <= STD_LOGIC_VECTOR(redist6_i_add24_1_conv2d1x1_out_primWireOut_15_inputreg_q);
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_aa <= redist6_i_add24_1_conv2d1x1_out_primWireOut_15_wraddr_q;
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_ab <= redist6_i_add24_1_conv2d1x1_out_primWireOut_15_rdcnt_q;
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_reset0 <= not (resetn);
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_dmem : altera_syncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 11,
width_b => 32,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altera_syncram",
width_byteena_a => 1,
address_reg_b => "CLOCK0",
indata_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "TRUE",
intended_device_family => "Cyclone V"
)
PORT MAP (
clocken1 => redist6_i_add24_1_conv2d1x1_out_primWireOut_15_enaAnd_q(0),
clocken0 => VCC_q(0),
clock0 => clock,
aclr1 => redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_reset0,
clock1 => clock,
address_a => redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_aa,
data_a => redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_ia,
wren_a => VCC_q(0),
address_b => redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_ab,
q_b => redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_iq
);
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_q <= redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_iq(31 downto 0);
-- redist6_i_add24_1_conv2d1x1_out_primWireOut_15_outputreg(DELAY,57)
redist6_i_add24_1_conv2d1x1_out_primWireOut_15_outputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC", reset_high => '0' )
PORT MAP ( xin => redist6_i_add24_1_conv2d1x1_out_primWireOut_15_mem_q, xout => redist6_i_add24_1_conv2d1x1_out_primWireOut_15_outputreg_q, clk => clock, aclr => resetn );
-- redist4_i_add24_conv2d1x1_out_primWireOut_30_notEnable(LOGICAL,52)
redist4_i_add24_conv2d1x1_out_primWireOut_30_notEnable_q <= STD_LOGIC_VECTOR(not (VCC_q));
-- redist4_i_add24_conv2d1x1_out_primWireOut_30_nor(LOGICAL,53)
redist4_i_add24_conv2d1x1_out_primWireOut_30_nor_q <= not (redist4_i_add24_conv2d1x1_out_primWireOut_30_notEnable_q or redist4_i_add24_conv2d1x1_out_primWireOut_30_sticky_ena_q);
-- redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_last(CONSTANT,49)
redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_last_q <= "011000";
-- redist4_i_add24_conv2d1x1_out_primWireOut_30_cmp(LOGICAL,50)
redist4_i_add24_conv2d1x1_out_primWireOut_30_cmp_b <= STD_LOGIC_VECTOR("0" & redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_q);
redist4_i_add24_conv2d1x1_out_primWireOut_30_cmp_q <= "1" WHEN redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_last_q = redist4_i_add24_conv2d1x1_out_primWireOut_30_cmp_b ELSE "0";
-- redist4_i_add24_conv2d1x1_out_primWireOut_30_cmpReg(REG,51)
redist4_i_add24_conv2d1x1_out_primWireOut_30_cmpReg_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist4_i_add24_conv2d1x1_out_primWireOut_30_cmpReg_q <= "0";
ELSIF (clock'EVENT AND clock = '1') THEN
redist4_i_add24_conv2d1x1_out_primWireOut_30_cmpReg_q <= STD_LOGIC_VECTOR(redist4_i_add24_conv2d1x1_out_primWireOut_30_cmp_q);
END IF;
END PROCESS;
-- redist4_i_add24_conv2d1x1_out_primWireOut_30_sticky_ena(REG,54)
redist4_i_add24_conv2d1x1_out_primWireOut_30_sticky_ena_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist4_i_add24_conv2d1x1_out_primWireOut_30_sticky_ena_q <= "0";
ELSIF (clock'EVENT AND clock = '1') THEN
IF (redist4_i_add24_conv2d1x1_out_primWireOut_30_nor_q = "1") THEN
redist4_i_add24_conv2d1x1_out_primWireOut_30_sticky_ena_q <= STD_LOGIC_VECTOR(redist4_i_add24_conv2d1x1_out_primWireOut_30_cmpReg_q);
END IF;
END IF;
END PROCESS;
-- redist4_i_add24_conv2d1x1_out_primWireOut_30_enaAnd(LOGICAL,55)
redist4_i_add24_conv2d1x1_out_primWireOut_30_enaAnd_q <= redist4_i_add24_conv2d1x1_out_primWireOut_30_sticky_ena_q and VCC_q;
-- redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt(COUNTER,47)
-- low=0, high=25, step=1, init=0
redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_i <= TO_UNSIGNED(0, 5);
redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_eq <= '0';
ELSIF (clock'EVENT AND clock = '1') THEN
IF (redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_i = TO_UNSIGNED(24, 5)) THEN
redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_eq <= '1';
ELSE
redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_eq <= '0';
END IF;
IF (redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_eq = '1') THEN
redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_i <= redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_i + 7;
ELSE
redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_i <= redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_q <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR(RESIZE(redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_i, 5)));
-- redist4_i_add24_conv2d1x1_out_primWireOut_30_inputreg(DELAY,44)
redist4_i_add24_conv2d1x1_out_primWireOut_30_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC", reset_high => '0' )
PORT MAP ( xin => redist3_i_add24_conv2d1x1_out_primWireOut_1_q, xout => redist4_i_add24_conv2d1x1_out_primWireOut_30_inputreg_q, clk => clock, aclr => resetn );
-- redist4_i_add24_conv2d1x1_out_primWireOut_30_wraddr(REG,48)
redist4_i_add24_conv2d1x1_out_primWireOut_30_wraddr_clkproc: PROCESS (clock, resetn)
BEGIN
IF (resetn = '0') THEN
redist4_i_add24_conv2d1x1_out_primWireOut_30_wraddr_q <= "11001";
ELSIF (clock'EVENT AND clock = '1') THEN
redist4_i_add24_conv2d1x1_out_primWireOut_30_wraddr_q <= STD_LOGIC_VECTOR(redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_q);
END IF;
END PROCESS;
-- redist4_i_add24_conv2d1x1_out_primWireOut_30_mem(DUALMEM,46)
redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_ia <= STD_LOGIC_VECTOR(redist4_i_add24_conv2d1x1_out_primWireOut_30_inputreg_q);
redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_aa <= redist4_i_add24_conv2d1x1_out_primWireOut_30_wraddr_q;
redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_ab <= redist4_i_add24_conv2d1x1_out_primWireOut_30_rdcnt_q;
redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_reset0 <= not (resetn);
redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_dmem : altera_syncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 5,
numwords_a => 26,
width_b => 32,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altera_syncram",
width_byteena_a => 1,
address_reg_b => "CLOCK0",
indata_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "TRUE",
intended_device_family => "Cyclone V"
)
PORT MAP (
clocken1 => redist4_i_add24_conv2d1x1_out_primWireOut_30_enaAnd_q(0),
clocken0 => VCC_q(0),
clock0 => clock,
aclr1 => redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_reset0,
clock1 => clock,
address_a => redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_aa,
data_a => redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_ia,
wren_a => VCC_q(0),
address_b => redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_ab,
q_b => redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_iq
);
redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_q <= redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_iq(31 downto 0);
-- redist4_i_add24_conv2d1x1_out_primWireOut_30_outputreg(DELAY,45)
redist4_i_add24_conv2d1x1_out_primWireOut_30_outputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1, reset_kind => "ASYNC", reset_high => '0' )
PORT MAP ( xin => redist4_i_add24_conv2d1x1_out_primWireOut_30_mem_q, xout => redist4_i_add24_conv2d1x1_out_primWireOut_30_outputreg_q, clk => clock, aclr => resetn );
-- GND(CONSTANT,0)
GND_q <= "0";
-- sync_out_aunroll_x(GPOUT,3)@193
out_c2_exi3_0 <= GND_q;
out_c2_exi3_1 <= redist4_i_add24_conv2d1x1_out_primWireOut_30_outputreg_q;
out_c2_exi3_2 <= redist6_i_add24_1_conv2d1x1_out_primWireOut_15_outputreg_q;
out_c2_exi3_3 <= i_add24_2_conv2d1x1_out_primWireOut;
out_o_valid <= redist8_sync_in_aunroll_x_in_i_valid_52_q;
END normal;
|
library verilog;
use verilog.vl_types.all;
entity Datapath_vlg_sample_tst is
port(
A_SEL : in vl_logic_vector(1 downto 0);
B_SEL : in vl_logic_vector(1 downto 0);
Cin : in vl_logic;
CLK : in vl_logic;
D_SEL : in vl_logic_vector(1 downto 0);
DATA_MEM_OUT : in vl_logic_vector(15 downto 0);
DATA_MEM_SEL : in vl_logic;
INS_TYPE_MUX_SEL: in vl_logic;
INST_MEM_OUT : in vl_logic_vector(15 downto 0);
LDA : in vl_logic;
LDQ : in vl_logic;
MULT_EN : in vl_logic;
MULT_SEL : in vl_logic;
OAP : in vl_logic_vector(2 downto 0);
PC_EN : in vl_logic;
PC_MUX_SEL : in vl_logic_vector(1 downto 0);
PLUS1_SEL : in vl_logic;
RF_EN : in vl_logic;
RST : in vl_logic;
SL : in vl_logic;
SR : in vl_logic;
SR_SEL : in vl_logic;
UL_SEL : in vl_logic;
WB_SEL : in vl_logic;
sampler_tx : out vl_logic
);
end Datapath_vlg_sample_tst;
|
-- args: --std=08 --ieee=synopsys
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.configure.all;
use work.wire.all;
entity uart is
generic(
clks_per_bit : integer := clks_per_bit
);
port(
reset : in std_logic;
clock : in std_logic;
uart_valid : in std_logic;
uart_ready : out std_logic;
uart_instr : in std_logic;
uart_addr : in std_logic_vector(63 downto 0);
uart_wdata : in std_logic_vector(63 downto 0);
uart_wstrb : in std_logic_vector(7 downto 0);
uart_rdata : out std_logic_vector(63 downto 0);
uart_rx : in std_logic;
uart_tx : out std_logic
);
end uart;
architecture behavior of uart is
type register_tx_type is record
state_tx : unsigned(3 downto 0);
data_tx : std_logic_vector(9 downto 0);
counter_tx : unsigned(31 downto 0);
ready_tx : std_logic;
end record;
type register_rx_type is record
state_re : std_logic;
state_rx : unsigned(3 downto 0);
data_re : std_logic_vector(7 downto 0);
data_rx : std_logic_vector(8 downto 0);
counter_rx : unsigned(31 downto 0);
ready_re : std_logic;
ready_rx : std_logic;
end record;
constant init_register_tx : register_tx_type := (
state_tx => (others => '0'),
data_tx => (others => '1'),
counter_tx => (others => '0'),
ready_tx => '0'
);
constant init_register_rx : register_rx_type := (
state_re => '0',
state_rx => (others => '0'),
data_re => (others => '0'),
data_rx => (others => '1'),
counter_rx => (others => '0'),
ready_re => '0',
ready_rx => '0'
);
signal r_tx,rin_tx : register_tx_type := init_register_tx;
signal r_rx,rin_rx : register_rx_type := init_register_rx;
begin
process(r_tx,uart_valid,uart_instr,uart_addr,uart_wdata,uart_wstrb)
variable v : register_tx_type;
begin
v := r_tx;
v.counter_tx := v.counter_tx + 1;
v.ready_tx := '0';
if (uart_valid = '1' and or_reduce(uart_wstrb) = '1' and r_tx.state_tx = x"0") then
v.data_tx := "1" & uart_wdata(7 downto 0) & "0";
v.state_tx := x"1";
end if;
case r_tx.state_tx is
when x"0" =>
v.counter_tx := (others => '0');
when x"A" =>
if (r_tx.counter_tx > clks_per_bit) then
v.state_tx := (others => '0');
v.counter_tx := (others => '0');
v.ready_tx := '1';
end if;
when others =>
if (r_tx.counter_tx > clks_per_bit) then
v.data_tx := "1" & v.data_tx(9 downto 1);
v.state_tx := v.state_tx + 1;
v.counter_tx := (others => '0');
end if;
end case;
rin_tx <= v;
uart_tx <= r_tx.data_tx(0);
end process;
process(r_rx,uart_valid,uart_instr,uart_addr,uart_wdata,uart_wstrb,uart_rx)
variable v : register_rx_type;
begin
v := r_rx;
v.counter_rx := v.counter_rx + 1;
v.ready_re := '0';
v.ready_rx := '0';
if (uart_valid = '1' and or_reduce(uart_wstrb) = '0' and r_rx.state_rx = x"0") then
v.state_re := '1';
end if;
case r_rx.state_rx is
when x"0" =>
if (uart_rx = '0') then
v.state_rx := x"1";
end if;
v.counter_rx := (others => '0');
when x"9" =>
if (r_rx.counter_rx > clks_per_bit) then
v.state_rx := (others => '0');
v.counter_rx := (others => '0');
v.ready_rx := '1';
end if;
when others =>
if (r_rx.counter_rx > clks_per_bit) then
v.data_rx := uart_rx & v.data_rx(8 downto 1);
v.state_rx := v.state_rx + 1;
v.counter_rx := (others => '0');
end if;
end case;
if (r_rx.state_re = '1' and r_rx.ready_rx = '1') then
v.state_re := '0';
v.ready_re := '1';
v.data_re := r_rx.data_rx(7 downto 0);
end if;
rin_rx <= v;
end process;
uart_rdata <= x"00000000000000" & r_rx.data_re;
uart_ready <= r_tx.ready_tx or r_rx.ready_re;
process(clock)
begin
if (rising_edge(clock)) then
if (reset = '0') then
r_tx <= init_register_tx;
r_rx <= init_register_rx;
else
r_tx <= rin_tx;
r_rx <= rin_rx;
end if;
end if;
end process;
end architecture;
|
ARCHITECTURE studentVersion OF lowpass IS
BEGIN
lowpassOut <= (others => '0');
END ARCHITECTURE studentVersion;
|
-- megafunction wizard: %ALTFP_MULT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTFP_MULT
-- ============================================================
-- File Name: kn_kalman_mult.vhd
-- Megafunction Name(s):
-- ALTFP_MULT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_mult CBX_AUTO_BLACKBOX="ALL" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" EXCEPTION_HANDLING="NO" PIPELINE=11 REDUCED_FUNCTIONALITY="NO" ROUNDING="TO_NEAREST" WIDTH_EXP=8 WIDTH_MAN=23 clock dataa datab result
--VERSION_BEGIN 11.1SP2 cbx_alt_ded_mult_y 2012:01:25:21:13:53:SJ cbx_altbarrel_shift 2012:01:25:21:13:53:SJ cbx_altera_mult_add 2012:01:25:21:13:53:SJ cbx_altfp_mult 2012:01:25:21:13:53:SJ cbx_altmult_add 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_mult 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_padd 2012:01:25:21:13:53:SJ cbx_parallel_add 2012:01:25:21:13:53:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 4 lpm_mult 1 reg 293
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_mult_altfp_mult_oon IS
PORT
(
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END kn_kalman_mult_altfp_mult_oon;
ARCHITECTURE RTL OF kn_kalman_mult_altfp_mult_oon IS
SIGNAL dataa_exp_all_one_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_dataa_exp_all_one_ff_p1_w_lg_q296w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dataa_exp_all_one_ff_p1_w_lg_q291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL dataa_exp_not_zero_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dataa_man_not_zero_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_dataa_man_not_zero_ff_p1_w_lg_w_lg_q290w295w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_dataa_man_not_zero_ff_p1_w_lg_q290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL dataa_man_not_zero_ff_p2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_exp_all_one_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_datab_exp_all_one_ff_p1_w_lg_q294w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_datab_exp_all_one_ff_p1_w_lg_q289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL datab_exp_not_zero_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_man_not_zero_ff_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_datab_man_not_zero_ff_p1_w_lg_w_lg_q288w293w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_datab_man_not_zero_ff_p1_w_lg_q288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL datab_man_not_zero_ff_p2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL delay_exp2_bias : STD_LOGIC_VECTOR(9 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL delay_exp3_bias : STD_LOGIC_VECTOR(9 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL delay_exp_bias : STD_LOGIC_VECTOR(9 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL delay_man_product_msb : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL delay_man_product_msb2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_delay_man_product_msb2_w_lg_q393w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_delay_man_product_msb2_w_lg_q395w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL delay_man_product_msb_p0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL delay_man_product_msb_p1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL delay_round : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_delay_round_w485w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_lg_w_lg_w_lg_w_q_range480w481w482w483w484w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_lg_w_lg_w_lg_w_q_range470w471w472w473w474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_lg_w_lg_w_q_range480w481w482w483w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_lg_w_lg_w_q_range470w471w472w473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_lg_w_q_range480w481w482w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_lg_w_q_range470w471w472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_q_range480w481w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w_q_range470w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_delay_round_w475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_delay_round_w_lg_w475w476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_delay_round_w_q_range480w : STD_LOGIC_VECTOR (21 DOWNTO 0);
SIGNAL wire_delay_round_w_q_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL exp_add_p1 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_exp_add_p1_w_q_range63w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adj_p1 : STD_LOGIC_VECTOR(9 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_adj_p2 : STD_LOGIC_VECTOR(9 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_exp_adj_p2_w_lg_w_lg_w_q_range459w460w461w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_lg_w_q_range459w460w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_lg_w_q_range432w457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range410w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range413w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range459w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_adj_p2_w_q_range432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL exp_bias_p1 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_bias_p2 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_bias_p3 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_result_ff : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL input_is_infinity_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_dffe_3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_ff1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_ff2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_ff3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_ff4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_ff5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_input_is_infinity_ff5_w_lg_q467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_input_is_infinity_ff5_w_lg_q469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL input_is_nan_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe_3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_ff1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_ff2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_ff3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_ff4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_ff5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_input_is_nan_ff5_w_lg_q479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL input_not_zero_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_dffe_3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_ff1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_ff2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_ff3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_ff4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_not_zero_ff5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_input_not_zero_ff5_w_lg_q466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL lsb_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_result_ff : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_round_carry : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_round_carry_p0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_round_p : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_round_p0 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_round_p1 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_round_p2 : STD_LOGIC_VECTOR(24 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_man_round_p2_w_lg_w_q_range404w405w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_round_p2_w_lg_w_q_range401w402w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_round_p2_w_lg_w_q_range391w403w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_round_p2_w_lg_w_lg_w_q_range404w405w406w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_round_p2_w_q_range404w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_round_p2_w_q_range401w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_round_p2_w_q_range391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL round_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_node_ff10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_dffe : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_exp_add_adder_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_add_adder_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_add_adder_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_adj_adder_datab : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_exp_adj_adder_result : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_exp_bias_subtr_dataa : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_exp_bias_subtr_datab : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_exp_bias_subtr_result : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL wire_man_round_adder_dataa : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_round_adder_datab : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_round_adder_result : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_lg_w_result_range302w303w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_lg_w_result_range299w300w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_lg_w_result_range298w373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_lg_w_result_range298w301w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_dataa : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_product2_mult_datab : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_man_product2_mult_result : STD_LOGIC_VECTOR (47 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range335w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range341w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range344w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range347w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range350w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range353w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range356w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range359w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range362w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range308w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range365w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range368w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range371w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range311w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range314w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range302w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range299w : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range298w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range317w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range320w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range323w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range326w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range329w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_product2_mult_w_result_range332w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_inf_num464w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range81w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range91w98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range101w108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range121w128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range131w138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range84w90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range94w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range104w110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range124w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range134w140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range408w412w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range411w415w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range414w418w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range417w421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range420w424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range423w427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_all_one_range426w430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_is_inf468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_is_zero458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range454w456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_inf_num464w465w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_is_inf462w463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_is_inf462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range211w213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range221w223w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range227w229w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range233w235w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range239w241w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range245w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range251w253w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range257w259w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range263w265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range157w159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range269w271w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range275w277w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range281w283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range81w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range91w93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range101w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range121w123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range131w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range163w165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range169w171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range175w177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range181w183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range187w189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range193w195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range199w201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range205w207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range214w216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range224w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range230w232w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range236w238w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range242w244w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range248w250w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range254w256w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range260w262w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range266w268w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range160w162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range272w274w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range278w280w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range284w286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range84w86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range94w96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range104w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range124w126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range134w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range166w168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range172w174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range178w180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range184w186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range190w192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range196w198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range202w204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range208w210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range438w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range440w443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range442w445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range444w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range446w449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range448w451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range450w453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_result_exp_not_zero_range452w455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range306w310w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range336w340w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range339w343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range342w346w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range345w349w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range348w352w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range351w355w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range354w358w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range357w361w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range360w364w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range363w367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range309w313w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range366w370w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range369w374w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range312w316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range315w319w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range318w322w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range321w325w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range324w328w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range327w331w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range330w334w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_sticky_bit_range333w337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL aclr : STD_LOGIC;
SIGNAL bias : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL clk_en : STD_LOGIC;
SIGNAL dataa_exp_all_one : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_exp_not_zero : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_man_not_zero : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL datab_exp_all_one : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL datab_exp_not_zero : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL datab_man_not_zero : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL exp_is_inf : STD_LOGIC;
SIGNAL exp_is_zero : STD_LOGIC;
SIGNAL expmod : STD_LOGIC_VECTOR (9 DOWNTO 0);
SIGNAL inf_num : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL lsb_bit : STD_LOGIC;
SIGNAL man_shift_full : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL result_exp_all_one : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL result_exp_not_zero : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL round_bit : STD_LOGIC;
SIGNAL round_carry : STD_LOGIC;
SIGNAL sticky_bit : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_dataa_range211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range221w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range227w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range239w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range251w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range257w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range263w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range269w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range281w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_all_one_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_exp_not_zero_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range222w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range228w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range234w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range240w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range258w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range270w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_man_not_zero_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range224w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range230w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range236w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range242w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range254w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range260w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range272w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range278w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range284w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_all_one_range139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_exp_not_zero_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range231w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range237w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range243w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range249w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range255w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range261w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range273w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range279w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_man_not_zero_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_shift_full_range379w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range408w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range411w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range414w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_all_one_range426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_result_exp_not_zero_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range306w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range339w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range345w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range348w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range351w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range357w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range360w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range363w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range309w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range366w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range369w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range312w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range315w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range318w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range321w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range324w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range327w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range330w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bit_range333w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_mult
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTHA : NATURAL;
LPM_WIDTHB : NATURAL;
LPM_WIDTHP : NATURAL;
LPM_WIDTHS : NATURAL := 1;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_mult"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTHA-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR(LPM_WIDTHB-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(LPM_WIDTHP-1 DOWNTO 0);
sum : IN STD_LOGIC_VECTOR(LPM_WIDTHS-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
loop0 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_inf_num464w(i) <= inf_num(i) AND wire_w_lg_w_lg_exp_is_inf462w463w(0);
END GENERATE loop0;
wire_w_lg_w_dataa_range81w88w(0) <= wire_w_dataa_range81w(0) AND wire_w_dataa_exp_all_one_range77w(0);
wire_w_lg_w_dataa_range91w98w(0) <= wire_w_dataa_range91w(0) AND wire_w_dataa_exp_all_one_range87w(0);
wire_w_lg_w_dataa_range101w108w(0) <= wire_w_dataa_range101w(0) AND wire_w_dataa_exp_all_one_range97w(0);
wire_w_lg_w_dataa_range111w118w(0) <= wire_w_dataa_range111w(0) AND wire_w_dataa_exp_all_one_range107w(0);
wire_w_lg_w_dataa_range121w128w(0) <= wire_w_dataa_range121w(0) AND wire_w_dataa_exp_all_one_range117w(0);
wire_w_lg_w_dataa_range131w138w(0) <= wire_w_dataa_range131w(0) AND wire_w_dataa_exp_all_one_range127w(0);
wire_w_lg_w_dataa_range141w148w(0) <= wire_w_dataa_range141w(0) AND wire_w_dataa_exp_all_one_range137w(0);
wire_w_lg_w_datab_range84w90w(0) <= wire_w_datab_range84w(0) AND wire_w_datab_exp_all_one_range79w(0);
wire_w_lg_w_datab_range94w100w(0) <= wire_w_datab_range94w(0) AND wire_w_datab_exp_all_one_range89w(0);
wire_w_lg_w_datab_range104w110w(0) <= wire_w_datab_range104w(0) AND wire_w_datab_exp_all_one_range99w(0);
wire_w_lg_w_datab_range114w120w(0) <= wire_w_datab_range114w(0) AND wire_w_datab_exp_all_one_range109w(0);
wire_w_lg_w_datab_range124w130w(0) <= wire_w_datab_range124w(0) AND wire_w_datab_exp_all_one_range119w(0);
wire_w_lg_w_datab_range134w140w(0) <= wire_w_datab_range134w(0) AND wire_w_datab_exp_all_one_range129w(0);
wire_w_lg_w_datab_range144w150w(0) <= wire_w_datab_range144w(0) AND wire_w_datab_exp_all_one_range139w(0);
wire_w_lg_w_result_exp_all_one_range408w412w(0) <= wire_w_result_exp_all_one_range408w(0) AND wire_exp_adj_p2_w_q_range410w(0);
wire_w_lg_w_result_exp_all_one_range411w415w(0) <= wire_w_result_exp_all_one_range411w(0) AND wire_exp_adj_p2_w_q_range413w(0);
wire_w_lg_w_result_exp_all_one_range414w418w(0) <= wire_w_result_exp_all_one_range414w(0) AND wire_exp_adj_p2_w_q_range416w(0);
wire_w_lg_w_result_exp_all_one_range417w421w(0) <= wire_w_result_exp_all_one_range417w(0) AND wire_exp_adj_p2_w_q_range419w(0);
wire_w_lg_w_result_exp_all_one_range420w424w(0) <= wire_w_result_exp_all_one_range420w(0) AND wire_exp_adj_p2_w_q_range422w(0);
wire_w_lg_w_result_exp_all_one_range423w427w(0) <= wire_w_result_exp_all_one_range423w(0) AND wire_exp_adj_p2_w_q_range425w(0);
wire_w_lg_w_result_exp_all_one_range426w430w(0) <= wire_w_result_exp_all_one_range426w(0) AND wire_exp_adj_p2_w_q_range428w(0);
wire_w_lg_exp_is_inf468w(0) <= NOT exp_is_inf;
wire_w_lg_exp_is_zero458w(0) <= NOT exp_is_zero;
wire_w_lg_w_result_exp_not_zero_range454w456w(0) <= NOT wire_w_result_exp_not_zero_range454w(0);
loop1 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_inf_num464w465w(i) <= wire_w_lg_inf_num464w(i) OR wire_exp_adj_p2_w_lg_w_lg_w_q_range459w460w461w(i);
END GENERATE loop1;
wire_w_lg_w_lg_exp_is_inf462w463w(0) <= wire_w_lg_exp_is_inf462w(0) OR input_is_nan_ff5;
wire_w_lg_exp_is_inf462w(0) <= exp_is_inf OR input_is_infinity_ff5;
wire_w_lg_w_dataa_range211w213w(0) <= wire_w_dataa_range211w(0) OR wire_w_dataa_man_not_zero_range206w(0);
wire_w_lg_w_dataa_range221w223w(0) <= wire_w_dataa_range221w(0) OR wire_w_dataa_man_not_zero_range218w(0);
wire_w_lg_w_dataa_range227w229w(0) <= wire_w_dataa_range227w(0) OR wire_w_dataa_man_not_zero_range222w(0);
wire_w_lg_w_dataa_range233w235w(0) <= wire_w_dataa_range233w(0) OR wire_w_dataa_man_not_zero_range228w(0);
wire_w_lg_w_dataa_range239w241w(0) <= wire_w_dataa_range239w(0) OR wire_w_dataa_man_not_zero_range234w(0);
wire_w_lg_w_dataa_range245w247w(0) <= wire_w_dataa_range245w(0) OR wire_w_dataa_man_not_zero_range240w(0);
wire_w_lg_w_dataa_range251w253w(0) <= wire_w_dataa_range251w(0) OR wire_w_dataa_man_not_zero_range246w(0);
wire_w_lg_w_dataa_range257w259w(0) <= wire_w_dataa_range257w(0) OR wire_w_dataa_man_not_zero_range252w(0);
wire_w_lg_w_dataa_range263w265w(0) <= wire_w_dataa_range263w(0) OR wire_w_dataa_man_not_zero_range258w(0);
wire_w_lg_w_dataa_range157w159w(0) <= wire_w_dataa_range157w(0) OR wire_w_dataa_man_not_zero_range152w(0);
wire_w_lg_w_dataa_range269w271w(0) <= wire_w_dataa_range269w(0) OR wire_w_dataa_man_not_zero_range264w(0);
wire_w_lg_w_dataa_range275w277w(0) <= wire_w_dataa_range275w(0) OR wire_w_dataa_man_not_zero_range270w(0);
wire_w_lg_w_dataa_range281w283w(0) <= wire_w_dataa_range281w(0) OR wire_w_dataa_man_not_zero_range276w(0);
wire_w_lg_w_dataa_range81w83w(0) <= wire_w_dataa_range81w(0) OR wire_w_dataa_exp_not_zero_range72w(0);
wire_w_lg_w_dataa_range91w93w(0) <= wire_w_dataa_range91w(0) OR wire_w_dataa_exp_not_zero_range82w(0);
wire_w_lg_w_dataa_range101w103w(0) <= wire_w_dataa_range101w(0) OR wire_w_dataa_exp_not_zero_range92w(0);
wire_w_lg_w_dataa_range111w113w(0) <= wire_w_dataa_range111w(0) OR wire_w_dataa_exp_not_zero_range102w(0);
wire_w_lg_w_dataa_range121w123w(0) <= wire_w_dataa_range121w(0) OR wire_w_dataa_exp_not_zero_range112w(0);
wire_w_lg_w_dataa_range131w133w(0) <= wire_w_dataa_range131w(0) OR wire_w_dataa_exp_not_zero_range122w(0);
wire_w_lg_w_dataa_range163w165w(0) <= wire_w_dataa_range163w(0) OR wire_w_dataa_man_not_zero_range158w(0);
wire_w_lg_w_dataa_range141w143w(0) <= wire_w_dataa_range141w(0) OR wire_w_dataa_exp_not_zero_range132w(0);
wire_w_lg_w_dataa_range169w171w(0) <= wire_w_dataa_range169w(0) OR wire_w_dataa_man_not_zero_range164w(0);
wire_w_lg_w_dataa_range175w177w(0) <= wire_w_dataa_range175w(0) OR wire_w_dataa_man_not_zero_range170w(0);
wire_w_lg_w_dataa_range181w183w(0) <= wire_w_dataa_range181w(0) OR wire_w_dataa_man_not_zero_range176w(0);
wire_w_lg_w_dataa_range187w189w(0) <= wire_w_dataa_range187w(0) OR wire_w_dataa_man_not_zero_range182w(0);
wire_w_lg_w_dataa_range193w195w(0) <= wire_w_dataa_range193w(0) OR wire_w_dataa_man_not_zero_range188w(0);
wire_w_lg_w_dataa_range199w201w(0) <= wire_w_dataa_range199w(0) OR wire_w_dataa_man_not_zero_range194w(0);
wire_w_lg_w_dataa_range205w207w(0) <= wire_w_dataa_range205w(0) OR wire_w_dataa_man_not_zero_range200w(0);
wire_w_lg_w_datab_range214w216w(0) <= wire_w_datab_range214w(0) OR wire_w_datab_man_not_zero_range209w(0);
wire_w_lg_w_datab_range224w226w(0) <= wire_w_datab_range224w(0) OR wire_w_datab_man_not_zero_range220w(0);
wire_w_lg_w_datab_range230w232w(0) <= wire_w_datab_range230w(0) OR wire_w_datab_man_not_zero_range225w(0);
wire_w_lg_w_datab_range236w238w(0) <= wire_w_datab_range236w(0) OR wire_w_datab_man_not_zero_range231w(0);
wire_w_lg_w_datab_range242w244w(0) <= wire_w_datab_range242w(0) OR wire_w_datab_man_not_zero_range237w(0);
wire_w_lg_w_datab_range248w250w(0) <= wire_w_datab_range248w(0) OR wire_w_datab_man_not_zero_range243w(0);
wire_w_lg_w_datab_range254w256w(0) <= wire_w_datab_range254w(0) OR wire_w_datab_man_not_zero_range249w(0);
wire_w_lg_w_datab_range260w262w(0) <= wire_w_datab_range260w(0) OR wire_w_datab_man_not_zero_range255w(0);
wire_w_lg_w_datab_range266w268w(0) <= wire_w_datab_range266w(0) OR wire_w_datab_man_not_zero_range261w(0);
wire_w_lg_w_datab_range160w162w(0) <= wire_w_datab_range160w(0) OR wire_w_datab_man_not_zero_range155w(0);
wire_w_lg_w_datab_range272w274w(0) <= wire_w_datab_range272w(0) OR wire_w_datab_man_not_zero_range267w(0);
wire_w_lg_w_datab_range278w280w(0) <= wire_w_datab_range278w(0) OR wire_w_datab_man_not_zero_range273w(0);
wire_w_lg_w_datab_range284w286w(0) <= wire_w_datab_range284w(0) OR wire_w_datab_man_not_zero_range279w(0);
wire_w_lg_w_datab_range84w86w(0) <= wire_w_datab_range84w(0) OR wire_w_datab_exp_not_zero_range75w(0);
wire_w_lg_w_datab_range94w96w(0) <= wire_w_datab_range94w(0) OR wire_w_datab_exp_not_zero_range85w(0);
wire_w_lg_w_datab_range104w106w(0) <= wire_w_datab_range104w(0) OR wire_w_datab_exp_not_zero_range95w(0);
wire_w_lg_w_datab_range114w116w(0) <= wire_w_datab_range114w(0) OR wire_w_datab_exp_not_zero_range105w(0);
wire_w_lg_w_datab_range124w126w(0) <= wire_w_datab_range124w(0) OR wire_w_datab_exp_not_zero_range115w(0);
wire_w_lg_w_datab_range134w136w(0) <= wire_w_datab_range134w(0) OR wire_w_datab_exp_not_zero_range125w(0);
wire_w_lg_w_datab_range166w168w(0) <= wire_w_datab_range166w(0) OR wire_w_datab_man_not_zero_range161w(0);
wire_w_lg_w_datab_range144w146w(0) <= wire_w_datab_range144w(0) OR wire_w_datab_exp_not_zero_range135w(0);
wire_w_lg_w_datab_range172w174w(0) <= wire_w_datab_range172w(0) OR wire_w_datab_man_not_zero_range167w(0);
wire_w_lg_w_datab_range178w180w(0) <= wire_w_datab_range178w(0) OR wire_w_datab_man_not_zero_range173w(0);
wire_w_lg_w_datab_range184w186w(0) <= wire_w_datab_range184w(0) OR wire_w_datab_man_not_zero_range179w(0);
wire_w_lg_w_datab_range190w192w(0) <= wire_w_datab_range190w(0) OR wire_w_datab_man_not_zero_range185w(0);
wire_w_lg_w_datab_range196w198w(0) <= wire_w_datab_range196w(0) OR wire_w_datab_man_not_zero_range191w(0);
wire_w_lg_w_datab_range202w204w(0) <= wire_w_datab_range202w(0) OR wire_w_datab_man_not_zero_range197w(0);
wire_w_lg_w_datab_range208w210w(0) <= wire_w_datab_range208w(0) OR wire_w_datab_man_not_zero_range203w(0);
wire_w_lg_w_result_exp_not_zero_range438w441w(0) <= wire_w_result_exp_not_zero_range438w(0) OR wire_exp_adj_p2_w_q_range410w(0);
wire_w_lg_w_result_exp_not_zero_range440w443w(0) <= wire_w_result_exp_not_zero_range440w(0) OR wire_exp_adj_p2_w_q_range413w(0);
wire_w_lg_w_result_exp_not_zero_range442w445w(0) <= wire_w_result_exp_not_zero_range442w(0) OR wire_exp_adj_p2_w_q_range416w(0);
wire_w_lg_w_result_exp_not_zero_range444w447w(0) <= wire_w_result_exp_not_zero_range444w(0) OR wire_exp_adj_p2_w_q_range419w(0);
wire_w_lg_w_result_exp_not_zero_range446w449w(0) <= wire_w_result_exp_not_zero_range446w(0) OR wire_exp_adj_p2_w_q_range422w(0);
wire_w_lg_w_result_exp_not_zero_range448w451w(0) <= wire_w_result_exp_not_zero_range448w(0) OR wire_exp_adj_p2_w_q_range425w(0);
wire_w_lg_w_result_exp_not_zero_range450w453w(0) <= wire_w_result_exp_not_zero_range450w(0) OR wire_exp_adj_p2_w_q_range428w(0);
wire_w_lg_w_result_exp_not_zero_range452w455w(0) <= wire_w_result_exp_not_zero_range452w(0) OR wire_exp_adj_p2_w_q_range431w(0);
wire_w_lg_w_sticky_bit_range306w310w(0) <= wire_w_sticky_bit_range306w(0) OR wire_man_product2_mult_w_result_range308w(0);
wire_w_lg_w_sticky_bit_range336w340w(0) <= wire_w_sticky_bit_range336w(0) OR wire_man_product2_mult_w_result_range338w(0);
wire_w_lg_w_sticky_bit_range339w343w(0) <= wire_w_sticky_bit_range339w(0) OR wire_man_product2_mult_w_result_range341w(0);
wire_w_lg_w_sticky_bit_range342w346w(0) <= wire_w_sticky_bit_range342w(0) OR wire_man_product2_mult_w_result_range344w(0);
wire_w_lg_w_sticky_bit_range345w349w(0) <= wire_w_sticky_bit_range345w(0) OR wire_man_product2_mult_w_result_range347w(0);
wire_w_lg_w_sticky_bit_range348w352w(0) <= wire_w_sticky_bit_range348w(0) OR wire_man_product2_mult_w_result_range350w(0);
wire_w_lg_w_sticky_bit_range351w355w(0) <= wire_w_sticky_bit_range351w(0) OR wire_man_product2_mult_w_result_range353w(0);
wire_w_lg_w_sticky_bit_range354w358w(0) <= wire_w_sticky_bit_range354w(0) OR wire_man_product2_mult_w_result_range356w(0);
wire_w_lg_w_sticky_bit_range357w361w(0) <= wire_w_sticky_bit_range357w(0) OR wire_man_product2_mult_w_result_range359w(0);
wire_w_lg_w_sticky_bit_range360w364w(0) <= wire_w_sticky_bit_range360w(0) OR wire_man_product2_mult_w_result_range362w(0);
wire_w_lg_w_sticky_bit_range363w367w(0) <= wire_w_sticky_bit_range363w(0) OR wire_man_product2_mult_w_result_range365w(0);
wire_w_lg_w_sticky_bit_range309w313w(0) <= wire_w_sticky_bit_range309w(0) OR wire_man_product2_mult_w_result_range311w(0);
wire_w_lg_w_sticky_bit_range366w370w(0) <= wire_w_sticky_bit_range366w(0) OR wire_man_product2_mult_w_result_range368w(0);
wire_w_lg_w_sticky_bit_range369w374w(0) <= wire_w_sticky_bit_range369w(0) OR wire_man_product2_mult_w_lg_w_result_range298w373w(0);
wire_w_lg_w_sticky_bit_range312w316w(0) <= wire_w_sticky_bit_range312w(0) OR wire_man_product2_mult_w_result_range314w(0);
wire_w_lg_w_sticky_bit_range315w319w(0) <= wire_w_sticky_bit_range315w(0) OR wire_man_product2_mult_w_result_range317w(0);
wire_w_lg_w_sticky_bit_range318w322w(0) <= wire_w_sticky_bit_range318w(0) OR wire_man_product2_mult_w_result_range320w(0);
wire_w_lg_w_sticky_bit_range321w325w(0) <= wire_w_sticky_bit_range321w(0) OR wire_man_product2_mult_w_result_range323w(0);
wire_w_lg_w_sticky_bit_range324w328w(0) <= wire_w_sticky_bit_range324w(0) OR wire_man_product2_mult_w_result_range326w(0);
wire_w_lg_w_sticky_bit_range327w331w(0) <= wire_w_sticky_bit_range327w(0) OR wire_man_product2_mult_w_result_range329w(0);
wire_w_lg_w_sticky_bit_range330w334w(0) <= wire_w_sticky_bit_range330w(0) OR wire_man_product2_mult_w_result_range332w(0);
wire_w_lg_w_sticky_bit_range333w337w(0) <= wire_w_sticky_bit_range333w(0) OR wire_man_product2_mult_w_result_range335w(0);
aclr <= '0';
bias <= ( "0" & "0" & "0" & "1" & "1" & "1" & "1" & "1" & "1" & "1");
clk_en <= '1';
dataa_exp_all_one <= ( wire_w_lg_w_dataa_range141w148w & wire_w_lg_w_dataa_range131w138w & wire_w_lg_w_dataa_range121w128w & wire_w_lg_w_dataa_range111w118w & wire_w_lg_w_dataa_range101w108w & wire_w_lg_w_dataa_range91w98w & wire_w_lg_w_dataa_range81w88w & dataa(23));
dataa_exp_not_zero <= ( wire_w_lg_w_dataa_range141w143w & wire_w_lg_w_dataa_range131w133w & wire_w_lg_w_dataa_range121w123w & wire_w_lg_w_dataa_range111w113w & wire_w_lg_w_dataa_range101w103w & wire_w_lg_w_dataa_range91w93w & wire_w_lg_w_dataa_range81w83w & dataa(23));
dataa_man_not_zero <= ( wire_w_lg_w_dataa_range281w283w & wire_w_lg_w_dataa_range275w277w & wire_w_lg_w_dataa_range269w271w & wire_w_lg_w_dataa_range263w265w & wire_w_lg_w_dataa_range257w259w & wire_w_lg_w_dataa_range251w253w & wire_w_lg_w_dataa_range245w247w & wire_w_lg_w_dataa_range239w241w & wire_w_lg_w_dataa_range233w235w & wire_w_lg_w_dataa_range227w229w & wire_w_lg_w_dataa_range221w223w & dataa(11) & wire_w_lg_w_dataa_range211w213w & wire_w_lg_w_dataa_range205w207w & wire_w_lg_w_dataa_range199w201w & wire_w_lg_w_dataa_range193w195w & wire_w_lg_w_dataa_range187w189w & wire_w_lg_w_dataa_range181w183w & wire_w_lg_w_dataa_range175w177w & wire_w_lg_w_dataa_range169w171w & wire_w_lg_w_dataa_range163w165w & wire_w_lg_w_dataa_range157w159w & dataa(0));
datab_exp_all_one <= ( wire_w_lg_w_datab_range144w150w & wire_w_lg_w_datab_range134w140w & wire_w_lg_w_datab_range124w130w & wire_w_lg_w_datab_range114w120w & wire_w_lg_w_datab_range104w110w & wire_w_lg_w_datab_range94w100w & wire_w_lg_w_datab_range84w90w & datab(23));
datab_exp_not_zero <= ( wire_w_lg_w_datab_range144w146w & wire_w_lg_w_datab_range134w136w & wire_w_lg_w_datab_range124w126w & wire_w_lg_w_datab_range114w116w & wire_w_lg_w_datab_range104w106w & wire_w_lg_w_datab_range94w96w & wire_w_lg_w_datab_range84w86w & datab(23));
datab_man_not_zero <= ( wire_w_lg_w_datab_range284w286w & wire_w_lg_w_datab_range278w280w & wire_w_lg_w_datab_range272w274w & wire_w_lg_w_datab_range266w268w & wire_w_lg_w_datab_range260w262w & wire_w_lg_w_datab_range254w256w & wire_w_lg_w_datab_range248w250w & wire_w_lg_w_datab_range242w244w & wire_w_lg_w_datab_range236w238w & wire_w_lg_w_datab_range230w232w & wire_w_lg_w_datab_range224w226w & datab(11) & wire_w_lg_w_datab_range214w216w & wire_w_lg_w_datab_range208w210w & wire_w_lg_w_datab_range202w204w & wire_w_lg_w_datab_range196w198w & wire_w_lg_w_datab_range190w192w & wire_w_lg_w_datab_range184w186w & wire_w_lg_w_datab_range178w180w & wire_w_lg_w_datab_range172w174w & wire_w_lg_w_datab_range166w168w & wire_w_lg_w_datab_range160w162w & datab(0));
exp_is_inf <= (((NOT exp_adj_p2(9)) AND exp_adj_p2(8)) OR ((NOT exp_adj_p2(8)) AND result_exp_all_one(7)));
exp_is_zero <= wire_exp_adj_p2_w_lg_w_q_range432w457w(0);
expmod <= ( "00000000" & wire_delay_man_product_msb2_w_lg_q393w & wire_delay_man_product_msb2_w_lg_q395w);
inf_num <= ( "1" & "1" & "1" & "1" & "1" & "1" & "1" & "1");
lsb_bit <= man_shift_full(1);
man_shift_full <= (wire_man_product2_mult_w_lg_w_result_range302w303w OR wire_man_product2_mult_w_lg_w_result_range299w300w);
result <= ( sign_node_ff10 & exp_result_ff(7 DOWNTO 0) & man_result_ff(22 DOWNTO 0));
result_exp_all_one <= ( wire_w_lg_w_result_exp_all_one_range426w430w & wire_w_lg_w_result_exp_all_one_range423w427w & wire_w_lg_w_result_exp_all_one_range420w424w & wire_w_lg_w_result_exp_all_one_range417w421w & wire_w_lg_w_result_exp_all_one_range414w418w & wire_w_lg_w_result_exp_all_one_range411w415w & wire_w_lg_w_result_exp_all_one_range408w412w & exp_adj_p2(0));
result_exp_not_zero <= ( wire_w_lg_w_result_exp_not_zero_range452w455w & wire_w_lg_w_result_exp_not_zero_range450w453w & wire_w_lg_w_result_exp_not_zero_range448w451w & wire_w_lg_w_result_exp_not_zero_range446w449w & wire_w_lg_w_result_exp_not_zero_range444w447w & wire_w_lg_w_result_exp_not_zero_range442w445w & wire_w_lg_w_result_exp_not_zero_range440w443w & wire_w_lg_w_result_exp_not_zero_range438w441w & exp_adj_p2(0));
round_bit <= man_shift_full(0);
round_carry <= (round_dffe AND (lsb_dffe OR sticky_dffe));
sticky_bit <= ( wire_w_lg_w_sticky_bit_range369w374w & wire_w_lg_w_sticky_bit_range366w370w & wire_w_lg_w_sticky_bit_range363w367w & wire_w_lg_w_sticky_bit_range360w364w & wire_w_lg_w_sticky_bit_range357w361w & wire_w_lg_w_sticky_bit_range354w358w & wire_w_lg_w_sticky_bit_range351w355w & wire_w_lg_w_sticky_bit_range348w352w & wire_w_lg_w_sticky_bit_range345w349w & wire_w_lg_w_sticky_bit_range342w346w & wire_w_lg_w_sticky_bit_range339w343w & wire_w_lg_w_sticky_bit_range336w340w & wire_w_lg_w_sticky_bit_range333w337w & wire_w_lg_w_sticky_bit_range330w334w & wire_w_lg_w_sticky_bit_range327w331w & wire_w_lg_w_sticky_bit_range324w328w & wire_w_lg_w_sticky_bit_range321w325w & wire_w_lg_w_sticky_bit_range318w322w & wire_w_lg_w_sticky_bit_range315w319w & wire_w_lg_w_sticky_bit_range312w316w & wire_w_lg_w_sticky_bit_range309w313w & wire_w_lg_w_sticky_bit_range306w310w & wire_man_product2_mult_result(0));
wire_w_dataa_range211w(0) <= dataa(10);
wire_w_dataa_range221w(0) <= dataa(12);
wire_w_dataa_range227w(0) <= dataa(13);
wire_w_dataa_range233w(0) <= dataa(14);
wire_w_dataa_range239w(0) <= dataa(15);
wire_w_dataa_range245w(0) <= dataa(16);
wire_w_dataa_range251w(0) <= dataa(17);
wire_w_dataa_range257w(0) <= dataa(18);
wire_w_dataa_range263w(0) <= dataa(19);
wire_w_dataa_range157w(0) <= dataa(1);
wire_w_dataa_range269w(0) <= dataa(20);
wire_w_dataa_range275w(0) <= dataa(21);
wire_w_dataa_range281w(0) <= dataa(22);
wire_w_dataa_range81w(0) <= dataa(24);
wire_w_dataa_range91w(0) <= dataa(25);
wire_w_dataa_range101w(0) <= dataa(26);
wire_w_dataa_range111w(0) <= dataa(27);
wire_w_dataa_range121w(0) <= dataa(28);
wire_w_dataa_range131w(0) <= dataa(29);
wire_w_dataa_range163w(0) <= dataa(2);
wire_w_dataa_range141w(0) <= dataa(30);
wire_w_dataa_range169w(0) <= dataa(3);
wire_w_dataa_range175w(0) <= dataa(4);
wire_w_dataa_range181w(0) <= dataa(5);
wire_w_dataa_range187w(0) <= dataa(6);
wire_w_dataa_range193w(0) <= dataa(7);
wire_w_dataa_range199w(0) <= dataa(8);
wire_w_dataa_range205w(0) <= dataa(9);
wire_w_dataa_exp_all_one_range77w(0) <= dataa_exp_all_one(0);
wire_w_dataa_exp_all_one_range87w(0) <= dataa_exp_all_one(1);
wire_w_dataa_exp_all_one_range97w(0) <= dataa_exp_all_one(2);
wire_w_dataa_exp_all_one_range107w(0) <= dataa_exp_all_one(3);
wire_w_dataa_exp_all_one_range117w(0) <= dataa_exp_all_one(4);
wire_w_dataa_exp_all_one_range127w(0) <= dataa_exp_all_one(5);
wire_w_dataa_exp_all_one_range137w(0) <= dataa_exp_all_one(6);
wire_w_dataa_exp_not_zero_range72w(0) <= dataa_exp_not_zero(0);
wire_w_dataa_exp_not_zero_range82w(0) <= dataa_exp_not_zero(1);
wire_w_dataa_exp_not_zero_range92w(0) <= dataa_exp_not_zero(2);
wire_w_dataa_exp_not_zero_range102w(0) <= dataa_exp_not_zero(3);
wire_w_dataa_exp_not_zero_range112w(0) <= dataa_exp_not_zero(4);
wire_w_dataa_exp_not_zero_range122w(0) <= dataa_exp_not_zero(5);
wire_w_dataa_exp_not_zero_range132w(0) <= dataa_exp_not_zero(6);
wire_w_dataa_man_not_zero_range152w(0) <= dataa_man_not_zero(0);
wire_w_dataa_man_not_zero_range218w(0) <= dataa_man_not_zero(11);
wire_w_dataa_man_not_zero_range222w(0) <= dataa_man_not_zero(12);
wire_w_dataa_man_not_zero_range228w(0) <= dataa_man_not_zero(13);
wire_w_dataa_man_not_zero_range234w(0) <= dataa_man_not_zero(14);
wire_w_dataa_man_not_zero_range240w(0) <= dataa_man_not_zero(15);
wire_w_dataa_man_not_zero_range246w(0) <= dataa_man_not_zero(16);
wire_w_dataa_man_not_zero_range252w(0) <= dataa_man_not_zero(17);
wire_w_dataa_man_not_zero_range258w(0) <= dataa_man_not_zero(18);
wire_w_dataa_man_not_zero_range264w(0) <= dataa_man_not_zero(19);
wire_w_dataa_man_not_zero_range158w(0) <= dataa_man_not_zero(1);
wire_w_dataa_man_not_zero_range270w(0) <= dataa_man_not_zero(20);
wire_w_dataa_man_not_zero_range276w(0) <= dataa_man_not_zero(21);
wire_w_dataa_man_not_zero_range164w(0) <= dataa_man_not_zero(2);
wire_w_dataa_man_not_zero_range170w(0) <= dataa_man_not_zero(3);
wire_w_dataa_man_not_zero_range176w(0) <= dataa_man_not_zero(4);
wire_w_dataa_man_not_zero_range182w(0) <= dataa_man_not_zero(5);
wire_w_dataa_man_not_zero_range188w(0) <= dataa_man_not_zero(6);
wire_w_dataa_man_not_zero_range194w(0) <= dataa_man_not_zero(7);
wire_w_dataa_man_not_zero_range200w(0) <= dataa_man_not_zero(8);
wire_w_dataa_man_not_zero_range206w(0) <= dataa_man_not_zero(9);
wire_w_datab_range214w(0) <= datab(10);
wire_w_datab_range224w(0) <= datab(12);
wire_w_datab_range230w(0) <= datab(13);
wire_w_datab_range236w(0) <= datab(14);
wire_w_datab_range242w(0) <= datab(15);
wire_w_datab_range248w(0) <= datab(16);
wire_w_datab_range254w(0) <= datab(17);
wire_w_datab_range260w(0) <= datab(18);
wire_w_datab_range266w(0) <= datab(19);
wire_w_datab_range160w(0) <= datab(1);
wire_w_datab_range272w(0) <= datab(20);
wire_w_datab_range278w(0) <= datab(21);
wire_w_datab_range284w(0) <= datab(22);
wire_w_datab_range84w(0) <= datab(24);
wire_w_datab_range94w(0) <= datab(25);
wire_w_datab_range104w(0) <= datab(26);
wire_w_datab_range114w(0) <= datab(27);
wire_w_datab_range124w(0) <= datab(28);
wire_w_datab_range134w(0) <= datab(29);
wire_w_datab_range166w(0) <= datab(2);
wire_w_datab_range144w(0) <= datab(30);
wire_w_datab_range172w(0) <= datab(3);
wire_w_datab_range178w(0) <= datab(4);
wire_w_datab_range184w(0) <= datab(5);
wire_w_datab_range190w(0) <= datab(6);
wire_w_datab_range196w(0) <= datab(7);
wire_w_datab_range202w(0) <= datab(8);
wire_w_datab_range208w(0) <= datab(9);
wire_w_datab_exp_all_one_range79w(0) <= datab_exp_all_one(0);
wire_w_datab_exp_all_one_range89w(0) <= datab_exp_all_one(1);
wire_w_datab_exp_all_one_range99w(0) <= datab_exp_all_one(2);
wire_w_datab_exp_all_one_range109w(0) <= datab_exp_all_one(3);
wire_w_datab_exp_all_one_range119w(0) <= datab_exp_all_one(4);
wire_w_datab_exp_all_one_range129w(0) <= datab_exp_all_one(5);
wire_w_datab_exp_all_one_range139w(0) <= datab_exp_all_one(6);
wire_w_datab_exp_not_zero_range75w(0) <= datab_exp_not_zero(0);
wire_w_datab_exp_not_zero_range85w(0) <= datab_exp_not_zero(1);
wire_w_datab_exp_not_zero_range95w(0) <= datab_exp_not_zero(2);
wire_w_datab_exp_not_zero_range105w(0) <= datab_exp_not_zero(3);
wire_w_datab_exp_not_zero_range115w(0) <= datab_exp_not_zero(4);
wire_w_datab_exp_not_zero_range125w(0) <= datab_exp_not_zero(5);
wire_w_datab_exp_not_zero_range135w(0) <= datab_exp_not_zero(6);
wire_w_datab_man_not_zero_range155w(0) <= datab_man_not_zero(0);
wire_w_datab_man_not_zero_range220w(0) <= datab_man_not_zero(11);
wire_w_datab_man_not_zero_range225w(0) <= datab_man_not_zero(12);
wire_w_datab_man_not_zero_range231w(0) <= datab_man_not_zero(13);
wire_w_datab_man_not_zero_range237w(0) <= datab_man_not_zero(14);
wire_w_datab_man_not_zero_range243w(0) <= datab_man_not_zero(15);
wire_w_datab_man_not_zero_range249w(0) <= datab_man_not_zero(16);
wire_w_datab_man_not_zero_range255w(0) <= datab_man_not_zero(17);
wire_w_datab_man_not_zero_range261w(0) <= datab_man_not_zero(18);
wire_w_datab_man_not_zero_range267w(0) <= datab_man_not_zero(19);
wire_w_datab_man_not_zero_range161w(0) <= datab_man_not_zero(1);
wire_w_datab_man_not_zero_range273w(0) <= datab_man_not_zero(20);
wire_w_datab_man_not_zero_range279w(0) <= datab_man_not_zero(21);
wire_w_datab_man_not_zero_range167w(0) <= datab_man_not_zero(2);
wire_w_datab_man_not_zero_range173w(0) <= datab_man_not_zero(3);
wire_w_datab_man_not_zero_range179w(0) <= datab_man_not_zero(4);
wire_w_datab_man_not_zero_range185w(0) <= datab_man_not_zero(5);
wire_w_datab_man_not_zero_range191w(0) <= datab_man_not_zero(6);
wire_w_datab_man_not_zero_range197w(0) <= datab_man_not_zero(7);
wire_w_datab_man_not_zero_range203w(0) <= datab_man_not_zero(8);
wire_w_datab_man_not_zero_range209w(0) <= datab_man_not_zero(9);
wire_w_man_shift_full_range379w <= man_shift_full(24 DOWNTO 1);
wire_w_result_exp_all_one_range408w(0) <= result_exp_all_one(0);
wire_w_result_exp_all_one_range411w(0) <= result_exp_all_one(1);
wire_w_result_exp_all_one_range414w(0) <= result_exp_all_one(2);
wire_w_result_exp_all_one_range417w(0) <= result_exp_all_one(3);
wire_w_result_exp_all_one_range420w(0) <= result_exp_all_one(4);
wire_w_result_exp_all_one_range423w(0) <= result_exp_all_one(5);
wire_w_result_exp_all_one_range426w(0) <= result_exp_all_one(6);
wire_w_result_exp_not_zero_range438w(0) <= result_exp_not_zero(0);
wire_w_result_exp_not_zero_range440w(0) <= result_exp_not_zero(1);
wire_w_result_exp_not_zero_range442w(0) <= result_exp_not_zero(2);
wire_w_result_exp_not_zero_range444w(0) <= result_exp_not_zero(3);
wire_w_result_exp_not_zero_range446w(0) <= result_exp_not_zero(4);
wire_w_result_exp_not_zero_range448w(0) <= result_exp_not_zero(5);
wire_w_result_exp_not_zero_range450w(0) <= result_exp_not_zero(6);
wire_w_result_exp_not_zero_range452w(0) <= result_exp_not_zero(7);
wire_w_result_exp_not_zero_range454w(0) <= result_exp_not_zero(8);
wire_w_sticky_bit_range306w(0) <= sticky_bit(0);
wire_w_sticky_bit_range336w(0) <= sticky_bit(10);
wire_w_sticky_bit_range339w(0) <= sticky_bit(11);
wire_w_sticky_bit_range342w(0) <= sticky_bit(12);
wire_w_sticky_bit_range345w(0) <= sticky_bit(13);
wire_w_sticky_bit_range348w(0) <= sticky_bit(14);
wire_w_sticky_bit_range351w(0) <= sticky_bit(15);
wire_w_sticky_bit_range354w(0) <= sticky_bit(16);
wire_w_sticky_bit_range357w(0) <= sticky_bit(17);
wire_w_sticky_bit_range360w(0) <= sticky_bit(18);
wire_w_sticky_bit_range363w(0) <= sticky_bit(19);
wire_w_sticky_bit_range309w(0) <= sticky_bit(1);
wire_w_sticky_bit_range366w(0) <= sticky_bit(20);
wire_w_sticky_bit_range369w(0) <= sticky_bit(21);
wire_w_sticky_bit_range312w(0) <= sticky_bit(2);
wire_w_sticky_bit_range315w(0) <= sticky_bit(3);
wire_w_sticky_bit_range318w(0) <= sticky_bit(4);
wire_w_sticky_bit_range321w(0) <= sticky_bit(5);
wire_w_sticky_bit_range324w(0) <= sticky_bit(6);
wire_w_sticky_bit_range327w(0) <= sticky_bit(7);
wire_w_sticky_bit_range330w(0) <= sticky_bit(8);
wire_w_sticky_bit_range333w(0) <= sticky_bit(9);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_exp_all_one_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_exp_all_one_ff_p1 <= dataa_exp_all_one(7);
END IF;
END IF;
END PROCESS;
wire_dataa_exp_all_one_ff_p1_w_lg_q296w(0) <= dataa_exp_all_one_ff_p1 AND wire_dataa_man_not_zero_ff_p1_w_lg_w_lg_q290w295w(0);
wire_dataa_exp_all_one_ff_p1_w_lg_q291w(0) <= dataa_exp_all_one_ff_p1 AND wire_dataa_man_not_zero_ff_p1_w_lg_q290w(0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_exp_not_zero_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_exp_not_zero_ff_p1 <= dataa_exp_not_zero(7);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_not_zero_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_not_zero_ff_p1 <= dataa_man_not_zero(10);
END IF;
END IF;
END PROCESS;
wire_dataa_man_not_zero_ff_p1_w_lg_w_lg_q290w295w(0) <= NOT wire_dataa_man_not_zero_ff_p1_w_lg_q290w(0);
wire_dataa_man_not_zero_ff_p1_w_lg_q290w(0) <= dataa_man_not_zero_ff_p1 OR dataa_man_not_zero_ff_p2;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_not_zero_ff_p2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_not_zero_ff_p2 <= dataa_man_not_zero(22);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_exp_all_one_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_exp_all_one_ff_p1 <= datab_exp_all_one(7);
END IF;
END IF;
END PROCESS;
wire_datab_exp_all_one_ff_p1_w_lg_q294w(0) <= datab_exp_all_one_ff_p1 AND wire_datab_man_not_zero_ff_p1_w_lg_w_lg_q288w293w(0);
wire_datab_exp_all_one_ff_p1_w_lg_q289w(0) <= datab_exp_all_one_ff_p1 AND wire_datab_man_not_zero_ff_p1_w_lg_q288w(0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_exp_not_zero_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_exp_not_zero_ff_p1 <= datab_exp_not_zero(7);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_not_zero_ff_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_not_zero_ff_p1 <= datab_man_not_zero(10);
END IF;
END IF;
END PROCESS;
wire_datab_man_not_zero_ff_p1_w_lg_w_lg_q288w293w(0) <= NOT wire_datab_man_not_zero_ff_p1_w_lg_q288w(0);
wire_datab_man_not_zero_ff_p1_w_lg_q288w(0) <= datab_man_not_zero_ff_p1 OR datab_man_not_zero_ff_p2;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_not_zero_ff_p2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_not_zero_ff_p2 <= datab_man_not_zero(22);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_exp2_bias <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_exp2_bias <= delay_exp_bias;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_exp3_bias <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_exp3_bias <= delay_exp2_bias;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_exp_bias <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_exp_bias <= wire_exp_bias_subtr_result;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_man_product_msb <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_man_product_msb <= delay_man_product_msb_p1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_man_product_msb2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_man_product_msb2 <= delay_man_product_msb;
END IF;
END IF;
END PROCESS;
wire_delay_man_product_msb2_w_lg_q393w(0) <= delay_man_product_msb2 AND wire_man_round_p2_w_q_range391w(0);
wire_delay_man_product_msb2_w_lg_q395w(0) <= delay_man_product_msb2 XOR wire_man_round_p2_w_q_range391w(0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_man_product_msb_p0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_man_product_msb_p0 <= wire_man_product2_mult_w_result_range298w(0);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_man_product_msb_p1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_man_product_msb_p1 <= delay_man_product_msb_p0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN delay_round <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN delay_round <= wire_man_round_p2_w_lg_w_lg_w_q_range404w405w406w;
END IF;
END IF;
END PROCESS;
loop2 : FOR i IN 0 TO 21 GENERATE
wire_delay_round_w485w(i) <= wire_delay_round_w_lg_w_lg_w_lg_w_lg_w_q_range480w481w482w483w484w(i) AND wire_input_is_nan_ff5_w_lg_q479w(0);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 21 GENERATE
wire_delay_round_w_lg_w_lg_w_lg_w_lg_w_q_range480w481w482w483w484w(i) <= wire_delay_round_w_lg_w_lg_w_lg_w_q_range480w481w482w483w(i) AND wire_w_lg_exp_is_zero458w(0);
END GENERATE loop3;
wire_delay_round_w_lg_w_lg_w_lg_w_lg_w_q_range470w471w472w473w474w(0) <= wire_delay_round_w_lg_w_lg_w_lg_w_q_range470w471w472w473w(0) AND wire_w_lg_exp_is_zero458w(0);
loop4 : FOR i IN 0 TO 21 GENERATE
wire_delay_round_w_lg_w_lg_w_lg_w_q_range480w481w482w483w(i) <= wire_delay_round_w_lg_w_lg_w_q_range480w481w482w(i) AND wire_w_lg_exp_is_inf468w(0);
END GENERATE loop4;
wire_delay_round_w_lg_w_lg_w_lg_w_q_range470w471w472w473w(0) <= wire_delay_round_w_lg_w_lg_w_q_range470w471w472w(0) AND wire_w_lg_exp_is_inf468w(0);
loop5 : FOR i IN 0 TO 21 GENERATE
wire_delay_round_w_lg_w_lg_w_q_range480w481w482w(i) <= wire_delay_round_w_lg_w_q_range480w481w(i) AND wire_input_is_infinity_ff5_w_lg_q469w(0);
END GENERATE loop5;
wire_delay_round_w_lg_w_lg_w_q_range470w471w472w(0) <= wire_delay_round_w_lg_w_q_range470w471w(0) AND wire_input_is_infinity_ff5_w_lg_q469w(0);
loop6 : FOR i IN 0 TO 21 GENERATE
wire_delay_round_w_lg_w_q_range480w481w(i) <= wire_delay_round_w_q_range480w(i) AND input_not_zero_ff5;
END GENERATE loop6;
wire_delay_round_w_lg_w_q_range470w471w(0) <= wire_delay_round_w_q_range470w(0) AND input_not_zero_ff5;
wire_delay_round_w475w(0) <= wire_delay_round_w_lg_w_lg_w_lg_w_lg_w_q_range470w471w472w473w474w(0) OR wire_input_is_infinity_ff5_w_lg_q467w(0);
wire_delay_round_w_lg_w475w476w(0) <= wire_delay_round_w475w(0) OR input_is_nan_ff5;
wire_delay_round_w_q_range480w <= delay_round(21 DOWNTO 0);
wire_delay_round_w_q_range470w(0) <= delay_round(22);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_add_p1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_add_p1 <= wire_exp_add_adder_result;
END IF;
END IF;
END PROCESS;
wire_exp_add_p1_w_q_range63w <= exp_add_p1(8 DOWNTO 0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_p1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_p1 <= delay_exp3_bias;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_p2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_p2 <= wire_exp_adj_adder_result;
END IF;
END IF;
END PROCESS;
loop7 : FOR i IN 0 TO 7 GENERATE
wire_exp_adj_p2_w_lg_w_lg_w_q_range459w460w461w(i) <= wire_exp_adj_p2_w_lg_w_q_range459w460w(i) AND input_not_zero_ff5;
END GENERATE loop7;
loop8 : FOR i IN 0 TO 7 GENERATE
wire_exp_adj_p2_w_lg_w_q_range459w460w(i) <= wire_exp_adj_p2_w_q_range459w(i) AND wire_w_lg_exp_is_zero458w(0);
END GENERATE loop8;
wire_exp_adj_p2_w_lg_w_q_range432w457w(0) <= wire_exp_adj_p2_w_q_range432w(0) OR wire_w_lg_w_result_exp_not_zero_range454w456w(0);
wire_exp_adj_p2_w_q_range410w(0) <= exp_adj_p2(1);
wire_exp_adj_p2_w_q_range413w(0) <= exp_adj_p2(2);
wire_exp_adj_p2_w_q_range416w(0) <= exp_adj_p2(3);
wire_exp_adj_p2_w_q_range419w(0) <= exp_adj_p2(4);
wire_exp_adj_p2_w_q_range422w(0) <= exp_adj_p2(5);
wire_exp_adj_p2_w_q_range425w(0) <= exp_adj_p2(6);
wire_exp_adj_p2_w_q_range459w <= exp_adj_p2(7 DOWNTO 0);
wire_exp_adj_p2_w_q_range428w(0) <= exp_adj_p2(7);
wire_exp_adj_p2_w_q_range431w(0) <= exp_adj_p2(8);
wire_exp_adj_p2_w_q_range432w(0) <= exp_adj_p2(9);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_bias_p1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_bias_p1 <= wire_exp_add_p1_w_q_range63w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_bias_p2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_bias_p2 <= exp_bias_p1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_bias_p3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_bias_p3 <= exp_bias_p2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_result_ff <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_result_ff <= wire_w_lg_w_lg_inf_num464w465w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_dffe_0 <= (wire_dataa_exp_all_one_ff_p1_w_lg_q296w(0) OR wire_datab_exp_all_one_ff_p1_w_lg_q294w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_dffe_1 <= input_is_infinity_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_dffe_2 <= input_is_infinity_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_dffe_3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_dffe_3 <= input_is_infinity_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_ff1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_ff1 <= input_is_infinity_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_ff2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_ff2 <= input_is_infinity_ff1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_ff3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_ff3 <= input_is_infinity_ff2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_ff4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_ff4 <= input_is_infinity_ff3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_ff5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_ff5 <= input_is_infinity_ff4;
END IF;
END IF;
END PROCESS;
wire_input_is_infinity_ff5_w_lg_q467w(0) <= input_is_infinity_ff5 AND wire_input_not_zero_ff5_w_lg_q466w(0);
wire_input_is_infinity_ff5_w_lg_q469w(0) <= NOT input_is_infinity_ff5;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe_0 <= (wire_dataa_exp_all_one_ff_p1_w_lg_q291w(0) OR wire_datab_exp_all_one_ff_p1_w_lg_q289w(0));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe_1 <= input_is_nan_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe_2 <= input_is_nan_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe_3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe_3 <= input_is_nan_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_ff1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_ff1 <= input_is_nan_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_ff2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_ff2 <= input_is_nan_ff1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_ff3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_ff3 <= input_is_nan_ff2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_ff4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_ff4 <= input_is_nan_ff3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_ff5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_ff5 <= input_is_nan_ff4;
END IF;
END IF;
END PROCESS;
wire_input_is_nan_ff5_w_lg_q479w(0) <= NOT input_is_nan_ff5;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_dffe_0 <= (dataa_exp_not_zero_ff_p1 AND datab_exp_not_zero_ff_p1);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_dffe_1 <= input_not_zero_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_dffe_2 <= input_not_zero_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_dffe_3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_dffe_3 <= input_not_zero_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_ff1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_ff1 <= input_not_zero_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_ff2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_ff2 <= input_not_zero_ff1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_ff3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_ff3 <= input_not_zero_ff2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_ff4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_ff4 <= input_not_zero_ff3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_not_zero_ff5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_not_zero_ff5 <= input_not_zero_ff4;
END IF;
END IF;
END PROCESS;
wire_input_not_zero_ff5_w_lg_q466w(0) <= NOT input_not_zero_ff5;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN lsb_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN lsb_dffe <= lsb_bit;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_result_ff <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_result_ff <= ( wire_delay_round_w_lg_w475w476w & wire_delay_round_w485w);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_carry <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_carry <= man_round_carry_p0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_carry_p0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_carry_p0 <= round_carry;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_p <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_p <= wire_w_man_shift_full_range379w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_p0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_p0 <= man_round_p;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_p1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_p1 <= man_round_p0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_p2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_p2 <= wire_man_round_adder_result;
END IF;
END IF;
END PROCESS;
loop9 : FOR i IN 0 TO 23 GENERATE
wire_man_round_p2_w_lg_w_q_range404w405w(i) <= wire_man_round_p2_w_q_range404w(i) AND wire_man_round_p2_w_lg_w_q_range391w403w(0);
END GENERATE loop9;
loop10 : FOR i IN 0 TO 23 GENERATE
wire_man_round_p2_w_lg_w_q_range401w402w(i) <= wire_man_round_p2_w_q_range401w(i) AND wire_man_round_p2_w_q_range391w(0);
END GENERATE loop10;
wire_man_round_p2_w_lg_w_q_range391w403w(0) <= NOT wire_man_round_p2_w_q_range391w(0);
loop11 : FOR i IN 0 TO 23 GENERATE
wire_man_round_p2_w_lg_w_lg_w_q_range404w405w406w(i) <= wire_man_round_p2_w_lg_w_q_range404w405w(i) OR wire_man_round_p2_w_lg_w_q_range401w402w(i);
END GENERATE loop11;
wire_man_round_p2_w_q_range404w <= man_round_p2(23 DOWNTO 0);
wire_man_round_p2_w_q_range401w <= man_round_p2(24 DOWNTO 1);
wire_man_round_p2_w_q_range391w(0) <= man_round_p2(24);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_dffe <= round_bit;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff0 <= (dataa(31) XOR datab(31));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff1 <= sign_node_ff0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff2 <= sign_node_ff1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff3 <= sign_node_ff2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff4 <= sign_node_ff3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff5 <= sign_node_ff4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff6 <= sign_node_ff5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff7 <= sign_node_ff6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff8 <= sign_node_ff7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff9 <= sign_node_ff8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_node_ff10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_node_ff10 <= sign_node_ff9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_dffe <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_dffe <= sticky_bit(22);
END IF;
END IF;
END PROCESS;
wire_exp_add_adder_dataa <= ( "0" & dataa(30 DOWNTO 23));
wire_exp_add_adder_datab <= ( "0" & datab(30 DOWNTO 23));
exp_add_adder : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => wire_exp_add_adder_dataa,
datab => wire_exp_add_adder_datab,
result => wire_exp_add_adder_result
);
wire_exp_adj_adder_datab <= ( expmod(9 DOWNTO 0));
exp_adj_adder : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 0,
LPM_WIDTH => 10
)
PORT MAP (
cin => wire_gnd,
dataa => exp_adj_p1,
datab => wire_exp_adj_adder_datab,
result => wire_exp_adj_adder_result
);
wire_exp_bias_subtr_dataa <= ( "0" & exp_bias_p3);
wire_exp_bias_subtr_datab <= ( bias(9 DOWNTO 0));
exp_bias_subtr : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 0,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 10
)
PORT MAP (
dataa => wire_exp_bias_subtr_dataa,
datab => wire_exp_bias_subtr_datab,
result => wire_exp_bias_subtr_result
);
wire_man_round_adder_dataa <= ( "0" & man_round_p1);
wire_man_round_adder_datab <= ( "000000000000000000000000" & man_round_carry);
man_round_adder : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 0,
LPM_WIDTH => 25
)
PORT MAP (
dataa => wire_man_round_adder_dataa,
datab => wire_man_round_adder_datab,
result => wire_man_round_adder_result
);
loop12 : FOR i IN 0 TO 24 GENERATE
wire_man_product2_mult_w_lg_w_result_range302w303w(i) <= wire_man_product2_mult_w_result_range302w(i) AND wire_man_product2_mult_w_lg_w_result_range298w301w(0);
END GENERATE loop12;
loop13 : FOR i IN 0 TO 24 GENERATE
wire_man_product2_mult_w_lg_w_result_range299w300w(i) <= wire_man_product2_mult_w_result_range299w(i) AND wire_man_product2_mult_w_result_range298w(0);
END GENERATE loop13;
wire_man_product2_mult_w_lg_w_result_range298w373w(0) <= wire_man_product2_mult_w_result_range298w(0) AND wire_man_product2_mult_w_result_range371w(0);
wire_man_product2_mult_w_lg_w_result_range298w301w(0) <= NOT wire_man_product2_mult_w_result_range298w(0);
wire_man_product2_mult_dataa <= ( "1" & dataa(22 DOWNTO 0));
wire_man_product2_mult_datab <= ( "1" & datab(22 DOWNTO 0));
wire_man_product2_mult_w_result_range335w(0) <= wire_man_product2_mult_result(10);
wire_man_product2_mult_w_result_range338w(0) <= wire_man_product2_mult_result(11);
wire_man_product2_mult_w_result_range341w(0) <= wire_man_product2_mult_result(12);
wire_man_product2_mult_w_result_range344w(0) <= wire_man_product2_mult_result(13);
wire_man_product2_mult_w_result_range347w(0) <= wire_man_product2_mult_result(14);
wire_man_product2_mult_w_result_range350w(0) <= wire_man_product2_mult_result(15);
wire_man_product2_mult_w_result_range353w(0) <= wire_man_product2_mult_result(16);
wire_man_product2_mult_w_result_range356w(0) <= wire_man_product2_mult_result(17);
wire_man_product2_mult_w_result_range359w(0) <= wire_man_product2_mult_result(18);
wire_man_product2_mult_w_result_range362w(0) <= wire_man_product2_mult_result(19);
wire_man_product2_mult_w_result_range308w(0) <= wire_man_product2_mult_result(1);
wire_man_product2_mult_w_result_range365w(0) <= wire_man_product2_mult_result(20);
wire_man_product2_mult_w_result_range368w(0) <= wire_man_product2_mult_result(21);
wire_man_product2_mult_w_result_range371w(0) <= wire_man_product2_mult_result(22);
wire_man_product2_mult_w_result_range311w(0) <= wire_man_product2_mult_result(2);
wire_man_product2_mult_w_result_range314w(0) <= wire_man_product2_mult_result(3);
wire_man_product2_mult_w_result_range302w <= wire_man_product2_mult_result(46 DOWNTO 22);
wire_man_product2_mult_w_result_range299w <= wire_man_product2_mult_result(47 DOWNTO 23);
wire_man_product2_mult_w_result_range298w(0) <= wire_man_product2_mult_result(47);
wire_man_product2_mult_w_result_range317w(0) <= wire_man_product2_mult_result(4);
wire_man_product2_mult_w_result_range320w(0) <= wire_man_product2_mult_result(5);
wire_man_product2_mult_w_result_range323w(0) <= wire_man_product2_mult_result(6);
wire_man_product2_mult_w_result_range326w(0) <= wire_man_product2_mult_result(7);
wire_man_product2_mult_w_result_range329w(0) <= wire_man_product2_mult_result(8);
wire_man_product2_mult_w_result_range332w(0) <= wire_man_product2_mult_result(9);
man_product2_mult : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 5,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 24,
LPM_WIDTHB => 24,
LPM_WIDTHP => 48,
LPM_WIDTHS => 1,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_man_product2_mult_dataa,
datab => wire_man_product2_mult_datab,
result => wire_man_product2_mult_result
);
END RTL; --kn_kalman_mult_altfp_mult_oon
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END kn_kalman_mult;
ARCHITECTURE RTL OF kn_kalman_mult IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT kn_kalman_mult_altfp_mult_oon
PORT (
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
kn_kalman_mult_altfp_mult_oon_component : kn_kalman_mult_altfp_mult_oon
PORT MAP (
clock => clock,
dataa => dataa,
datab => datab,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: FPM_FORMAT STRING "Single"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES"
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: EXCEPTION_HANDLING STRING "NO"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_mult"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "11"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_mult.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_mult.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_mult.bsf TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_mult_inst.vhd TRUE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_mult.inc FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_mult.cmp TRUE TRUE
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX NUMERIC "1"
-- Retrieval info: LIB_FILE: lpm
|
<reponame>edoomm/arquitectura
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/21/2021 02:17:01 PM
-- Design Name:
-- Module Name: TB_ARCH_REGISTROS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY STD;
USE STD.TEXTIO.ALL;
USE ieee.std_logic_TEXTIO.ALL; --PERMITE USAR STD_LOGIC
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_UNSIGNED.ALL;
USE ieee.std_logic_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_ARCH_REGISTROS IS
END TB_ARCH_REGISTROS;
architecture behavior of TB_ARCH_REGISTROS is
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fileReg
PORT(
writeReg : in STD_LOGIC_VECTOR (3 downto 0);
writeData : in STD_LOGIC_VECTOR (15 downto 0);
readReg1 : in STD_LOGIC_VECTOR (3 downto 0);
readReg2 : in STD_LOGIC_VECTOR (3 downto 0);
shamt : in STD_LOGIC_VECTOR (3 downto 0);
clk, clr, wr, she, dir : in STD_LOGIC;
readData1 : out STD_LOGIC_VECTOR (15 downto 0);
readData2 : out STD_LOGIC_VECTOR (15 downto 0)
);
END COMPONENT;
-- Inputs
signal writeReg : std_logic_vector(3 downto 0) := (others => '0');
signal writeData : std_logic_vector(15 downto 0) := (others => '0');
signal readReg1 : std_logic_vector(3 downto 0) := (others => '0');
signal readReg2 : std_logic_vector(3 downto 0) := (others => '0');
signal shamt : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal clr : std_logic := '0';
signal wr : std_logic := '0';
signal she : std_logic := '0';
signal dir : std_logic := '0';
-- Outputs
signal readData1 : STD_LOGIC_VECTOR (15 downto 0);
signal readData2 : STD_LOGIC_VECTOR (15 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: fileReg PORT MAP (
writeReg => writeReg,
writeData => writeData,
readReg1 => readReg1,
readReg2 => readReg2,
shamt => shamt,
clk => clk,
clr => clr,
wr => wr,
she => she,
dir => dir,
readData1 => readData1,
readData2 => readData2
);
-- Clock process definitions
CLK_process :process
begin
clk <= '0';
wait for CLK_period/2;
clk <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
file ARCH_RES : TEXT;
variable LINEA_RES : line;
VARIABLE VAR_readData1 : STD_LOGIC_VECTOR (15 downto 0);
VARIABLE VAR_readData2 : STD_LOGIC_VECTOR (15 downto 0);
file ARCH_VEC : TEXT;
variable LINEA_VEC : line;
VARIABLE VAR_writeReg : std_logic_vector(3 downto 0);
VARIABLE VAR_writeData : std_logic_vector(15 downto 0);
VARIABLE VAR_readReg1 : std_logic_vector(3 downto 0);
VARIABLE VAR_readReg2 : std_logic_vector(3 downto 0);
VARIABLE VAR_shamt : std_logic_vector(3 downto 0);
VARIABLE VAR_clr : std_logic;
VARIABLE VAR_wr : std_logic;
VARIABLE VAR_she : std_logic;
VARIABLE VAR_dir : std_logic;
VARIABLE CADENA : STRING(1 TO 4); -- !!!AC�? CHANCE SE TIENE QUE CAMBIAR A (1 TO 5) PARA PODER ESCRIBIR "SHAMT"
begin
file_open(ARCH_VEC, "D:\Documents\PracticasArqui\arquitectura\P5\Archivo\VECTORES.TXT", READ_MODE); -- !!!AC�? IGUAL PIENSO QUE SE LE DEBE CAMBIAR POR LA RUTA DE NUESTRAS COMPUTADORAS DONDE TENEMOS ESOS ARCHIVOS DE TEXTO
file_open(ARCH_RES, "D:\Documents\PracticasArqui\arquitectura\P5\Archivo\RESULTADO.TXT", WRITE_MODE); -- !!!AC�? IGUAL PIENSO QUE SE LE DEBE CAMBIAR POR LA RUTA DE NUESTRAS COMPUTADORAS DONDE TENEMOS ESOS ARCHIVOS DE TEXTO
CADENA := "RR1 ";
write(LINEA_RES, CADENA, right, CADENA'LENGTH+1); --ESCRIBE LA CADENA "RR1"
CADENA := " RR2";
write(LINEA_RES, CADENA, right, CADENA'LENGTH+1); --ESCRIBE LA CADENA " RR2"
CADENA := " SHA";
write(LINEA_RES, CADENA, right, CADENA'LENGTH+1); --ESCRIBE LA CADENA " SHAM"
CADENA := " WRG";
write(LINEA_RES, CADENA, right, CADENA'LENGTH+1); --ESCRIBE LA CADENA " WREG"
CADENA := " WD";
write(LINEA_RES, CADENA, right, CADENA'LENGTH+1); --ESCRIBE LA CADENA " WD"
CADENA := " WR";
write(LINEA_RES, CADENA, right, CADENA'LENGTH+1); --ESCRIBE LA CADENA " WR"
CADENA := " SHE";
write(LINEA_RES, CADENA, right, CADENA'LENGTH+1); --ESCRIBE LA CADENA " SHE"
CADENA := " DIR";
write(LINEA_RES, CADENA, right, CADENA'LENGTH+1); --ESCRIBE LA CADENA " DIR"
CADENA := " RD1";
write(LINEA_RES, CADENA, right, CADENA'LENGTH+1); --ESCRIBE LA CADENA " RD1"
CADENA := " RD2";
write(LINEA_RES, CADENA, right, CADENA'LENGTH+1); --ESCRIBE LA CADENA " RD2"
writeline(ARCH_RES,LINEA_RES);-- escribe la linea en el archivo
WAIT FOR 100 NS;
FOR I IN 0 TO 11 LOOP
readline(ARCH_VEC,LINEA_VEC); -- lee una linea completa
-- Hread es pa leer hexadecimales
Hread(LINEA_VEC, VAR_readReg1);
readReg1 <= VAR_readReg1;
Hread(LINEA_VEC, VAR_readReg2);
readReg2 <= VAR_readReg2;
Hread(LINEA_VEC, VAR_shamt);
shamt <= VAR_shamt;
Hread(LINEA_VEC, VAR_writeReg);
writeReg <= VAR_writeReg;
Hread(LINEA_VEC, VAR_writeData);
writeData <= VAR_writeData;
read(LINEA_VEC, VAR_wr);
wr <= VAR_wr;
read(LINEA_VEC, VAR_she);
she <= VAR_she;
read(LINEA_VEC, VAR_dir);
dir <= VAR_dir;
read(LINEA_VEC, VAR_clr); -- !!! En el archivo VECTORES.txt la última columna debe ser 'clr'
clr <= VAR_clr;
WAIT UNTIL RISING_EDGE(CLK); --ESPERO AL FLANCO DE SUBIDA
VAR_readData1 := readData1;
VAR_readData2 := readData2;
Hwrite(LINEA_RES, VAR_readReg1, right, 5); --ESCRIBE EL CAMPO RR1
Hwrite(LINEA_RES, VAR_readReg2, right, 5); --ESCRIBE EL CAMPO RR2
Hwrite(LINEA_RES, VAR_shamt, right, 5); --ESCRIBE EL CAMPO SHAM
Hwrite(LINEA_RES, VAR_writeReg, right, 5); --ESCRIBE EL CAMPO WREG
Hwrite(LINEA_RES, VAR_writeData, right, 5); --ESCRIBE EL CAMPO WD
write(LINEA_RES, VAR_wr, right, 5); --ESCRIBE EL CAMPO WR
write(LINEA_RES, VAR_she, right, 5); --ESCRIBE EL CAMPO SHE
write(LINEA_RES, VAR_dir, right, 5); --ESCRIBE EL CAMPO DIR
Hwrite(LINEA_RES, VAR_readData1, right, 5); --ESCRIBE EL CAMPO RD1
Hwrite(LINEA_RES, VAR_readData2, right, 5); --ESCRIBE EL CAMPO RD2
writeline(ARCH_RES,LINEA_RES);-- escribe la linea en el archivo
end loop;
file_close(ARCH_VEC); -- cierra el archivo
file_close(ARCH_RES); -- cierra el archivo
wait;
end process;
end;
|
<reponame>artic92/digital_systems
--------------------------------------------------------------------------------
-- Company:
-- Engineer: <NAME>
--
-- Create Date: 18:20:44 11/06/2015
-- Design Name:
-- Module Name: tb_flip_flop_d_behavioral.vhd
-- Project Name: latch_flip_flop_d
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: flip_flop_d_behavioral
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_flip_flop_d_behavioral IS
END tb_flip_flop_d_behavioral;
ARCHITECTURE behavior OF tb_flip_flop_d_behavioral IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT flip_flop_d_behavioral
PORT(
data_in : IN std_logic;
reset_n : IN std_logic;
clock : IN std_logic;
data_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal data_in : std_logic := '0';
signal reset_n : std_logic := '0';
signal clock : std_logic := '0';
--Outputs
signal data_out : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: flip_flop_d_behavioral PORT MAP (
data_in => data_in,
reset_n => reset_n,
clock => clock,
data_out => data_out
);
-- Clock process definitions
clk_process :process
begin
clock <= '0';
wait for clk_period/2;
clock <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 50 ns.
wait for 50 ns;
-- insert stimulus here
-- Output 0
data_in <= '1';
reset_n <= '0';
wait for 20 ns;
-- Output 1
reset_n <= '1';
wait for 20 ns;
-- Output 0
data_in <= '0';
wait for 20 ns;
wait;
end process;
END;
|
<filename>bitvis_vip_axilite/tb/maintenance_tb/axilite_vvc_simple_tb.vhd
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
library bitvis_vip_axilite;
context bitvis_vip_axilite.vvc_context;
--hdlunit:tb
-- Test case entity
entity axilite_vvc_simple_tb is
generic (
GC_TESTCASE : string := "UVVM"
);
end entity;
-- Test case architecture
architecture func of axilite_vvc_simple_tb is
constant C_CLK_PERIOD : time := 10 ns;
constant C_ADDR_WIDTH_1 : natural := 32;
constant C_DATA_WIDTH_1 : natural := 32;
constant C_ADDR_WIDTH_2 : natural := 32;
constant C_DATA_WIDTH_2 : natural := 64;
signal clk : std_logic := '0';
signal areset : std_logic := '0';
signal clock_ena : boolean := false;
-- signals
-- The axilite interface is gathered in one record, so procedures that use the
-- axilite interface have less arguments
signal axilite_if_1 : t_axilite_if( write_address_channel( awaddr( C_ADDR_WIDTH_1 -1 downto 0)),
write_data_channel( wdata( C_DATA_WIDTH_1 -1 downto 0),
wstrb(( C_DATA_WIDTH_1/8) -1 downto 0)),
read_address_channel( araddr( C_ADDR_WIDTH_1 -1 downto 0)),
read_data_channel( rdata( C_DATA_WIDTH_1 -1 downto 0)));
signal axilite_if_2 : t_axilite_if( write_address_channel( awaddr( C_ADDR_WIDTH_2 -1 downto 0)),
write_data_channel( wdata( C_DATA_WIDTH_2 -1 downto 0),
wstrb(( C_DATA_WIDTH_2/8) -1 downto 0)),
read_address_channel( araddr( C_ADDR_WIDTH_2 -1 downto 0)),
read_data_channel( rdata( C_DATA_WIDTH_2 -1 downto 0)));
signal read_data_interface_1 : std_logic_vector(C_DATA_WIDTH_1-1 downto 0);
signal read_data_interface_2 : std_logic_vector(C_DATA_WIDTH_2-1 downto 0);
begin
-----------------------------
-- Instantiate Testharness
-----------------------------
i_axilite_test_harness : entity bitvis_vip_axilite.test_harness(struct_vvc)
generic map(
C_DATA_WIDTH_1 => C_DATA_WIDTH_1,
C_ADDR_WIDTH_1 => C_ADDR_WIDTH_1,
C_DATA_WIDTH_2 => C_DATA_WIDTH_2,
C_ADDR_WIDTH_2 => C_ADDR_WIDTH_2
)
port map(
clk => clk,
areset => areset,
axilite_if_1 => axilite_if_1,
axilite_if_2 => axilite_if_2
);
i_ti_uvvm_engine : entity uvvm_vvc_framework.ti_uvvm_engine;
-- Set up clock generator
p_clock: clock_generator(clk, clock_ena, C_CLK_PERIOD, "Axilite CLK");
------------------------------------------------
-- PROCESS: p_main
------------------------------------------------
p_main: process
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
variable v_irq_mask : std_logic_vector(7 downto 0);
variable v_irq_mask_inv : std_logic_vector(7 downto 0);
variable i : integer;
variable v_timestamp : time;
variable v_measured_time : time;
variable v_cmd_idx : natural;
variable v_is_ok : boolean;
variable v_data : work.vvc_cmd_pkg.t_vvc_result;
begin
-- To avoid that log files from different test cases (run in separate
-- simulations) overwrite each other.
set_log_file_name(GC_TESTCASE & "_Log.txt");
set_alert_file_name(GC_TESTCASE & "_Alert.txt");
await_uvvm_initialization(VOID);
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
disable_log_msg(ALL_MESSAGES);
enable_log_msg(ID_LOG_HDR);
enable_log_msg(ID_SEQUENCER);
disable_log_msg(AXILITE_VVCT,1, ALL_MESSAGES);
disable_log_msg(AXILITE_VVCT,2, ALL_MESSAGES);
enable_log_msg(AXILITE_VVCT, 1, ID_BFM);
enable_log_msg(AXILITE_VVCT, 2, ID_BFM);
enable_log_msg(AXILITE_VVCT, 1, ID_IMMEDIATE_CMD);
enable_log_msg(AXILITE_VVCT, 2, ID_IMMEDIATE_CMD);
shared_axilite_vvc_config(1).bfm_config.clock_period := C_CLK_PERIOD;
shared_axilite_vvc_config(2).bfm_config.clock_period := C_CLK_PERIOD;
log(ID_LOG_HDR, "Start Simulation of AXI-Lite", C_SCOPE);
------------------------------------------------------------
clock_ena <= true; -- the axilite_reset routine assumes the clock is running
gen_pulse(areset, 10*C_CLK_PERIOD, "Pulsing reset for 10 clock periods");
log("Do some axilite writes", C_SCOPE);
-- write some data; the current axislave isn't very implemented - doesn't
-- have FIFO, and just has one RW slave register at addr_valueess 0x6000
-- Write to VVC 1
axilite_write(AXILITE_VVCT,1, x"0000", x"5555", "Test of axilite write");
axilite_write(AXILITE_VVCT,1, x"1000", x"befbeef","Write"); -- op0
axilite_write(AXILITE_VVCT,1, x"2000", x"efbeef","Write"); -- op1
axilite_write(AXILITE_VVCT,1, x"3000", x"beef","Write"); -- op2
axilite_write(AXILITE_VVCT,1, x"6000", x"54321","Write"); -- rw reg
await_completion(AXILITE_VVCT, 1, 1000 ns);
-- Read from VVC 1
axilite_read(AXILITE_VVCT, 1, x"3000", ""); -- just do a read
axilite_read(AXILITE_VVCT, 1, x"6000", ""); -- do another read - should see this data
-- verify read data on interface 1
v_cmd_idx := get_last_received_cmd_idx(AXILITE_VVCT, 1);
await_completion(AXILITE_VVCT, 1, 1 us, "waiting for axilite_read() to finish");
fetch_result(AXILITE_VVCT, 1, v_cmd_idx, v_data, v_is_ok, "Fetching read-result.");
check_value(v_is_ok, ERROR, "Readback OK via fetch_result()");
check_value(v_data(C_DATA_WIDTH_1-1 downto 0), x"54321", error, "verifying read data on interface 1.");
-- Write to VVC 2
axilite_write(AXILITE_VVCT,2, x"0000", x"5555", to_string("Test of axilite write"));
axilite_write(AXILITE_VVCT,2, x"0010", x"befbeef","Write"); -- op0
axilite_write(AXILITE_VVCT,2, x"0020", x"efbeef","Write"); -- op1
axilite_write(AXILITE_VVCT,2, x"0030", x"beef","Write"); -- op2
axilite_write(AXILITE_VVCT,2, x"0040", x"54321","Write"); -- op3
axilite_write(AXILITE_VVCT,2, x"0060", x"f00b0","Write"); -- rw reg
await_completion(AXILITE_VVCT, 2, 1000 ns);
-- Read from VVC 2
axilite_read(AXILITE_VVCT, 2, x"0040", ""); -- just do a read
axilite_read(AXILITE_VVCT, 2, x"0040", ""); -- do another read
axilite_read(AXILITE_VVCT, 2, x"0060", ""); -- do another read - should see this data
-- verify read data on interface 2
v_cmd_idx := get_last_received_cmd_idx(AXILITE_VVCT, 2);
await_completion(AXILITE_VVCT, 2, 1 us, "waiting for axilite_read() to finish");
fetch_result(AXILITE_VVCT, 2, v_cmd_idx, v_data, v_is_ok, "Fetching read-result.");
check_value(v_is_ok, ERROR, "Readback OK via fetch_result()");
check_value(v_data(C_DATA_WIDTH_2-1 downto 0), x"f00b0", error, "verifying read data on interface 2.");
-- check that is was correctly written on VVC 1
axilite_check(AXILITE_VVCT,1, x"0006000", x"54321","Check");
axilite_write(AXILITE_VVCT,1, x"0006000", x"abba1972","Write");
await_completion(AXILITE_VVCT, 1, 1000 ns);
axilite_check(AXILITE_VVCT,1, x"0006000", x"abba1972","Check");
-- check that is was correctly written on VVC 2
axilite_check(AXILITE_VVCT,2, x"0000", x"5555","Check");
axilite_check(AXILITE_VVCT,2, x"0010", x"befbeef","Check");
axilite_check(AXILITE_VVCT,2, x"0020", x"efbeef","Check");
axilite_check(AXILITE_VVCT,2, x"0030", x"beef","Check");
axilite_check(AXILITE_VVCT,2, x"0040", x"54321","Check");
await_completion(AXILITE_VVCT, 2, 1000 ns);
axilite_write(AXILITE_VVCT,2, x"0000040", x"abba1972","Write");
await_completion(AXILITE_VVCT, 2, 1000 ns);
axilite_check(AXILITE_VVCT,2, x"0000040", x"abba1972","Check");
-- Await completion on both VVCs
await_completion(AXILITE_VVCT, 1, 1000 ns);
await_completion(AXILITE_VVCT, 2, 1000 ns);
log(ID_LOG_HDR, "Test scoreboard", C_SCOPE);
-- Write to VVC 1
axilite_write(AXILITE_VVCT,1, x"0000", x"5555", "Test of axilite write");
axilite_write(AXILITE_VVCT,1, x"1000", x"befbeef","Write"); -- op0
axilite_write(AXILITE_VVCT,1, x"2000", x"efbeef","Write"); -- op1
axilite_write(AXILITE_VVCT,1, x"3000", x"beef","Write"); -- op2
axilite_write(AXILITE_VVCT,1, x"6000", x"54321","Write"); -- rw reg
AXILITE_VVC_SB.add_expected(1, pad_axilite_sb(x"54321"));
await_completion(AXILITE_VVCT, 1, 1000 ns);
-- Read from VVC 1
axilite_read(AXILITE_VVCT, 1, x"3000", ""); -- just do a read
axilite_read(AXILITE_VVCT, 1, x"6000", TO_SB, "Read data and send to SB"); -- do another read - should see this data
await_completion(AXILITE_VVCT, 1, 1000 ns);
-- Write to VVC 2
axilite_write(AXILITE_VVCT,2, x"0000", x"5555", to_string("Test of axilite write"));
axilite_write(AXILITE_VVCT,2, x"0010", x"befbeef","Write"); -- op0
axilite_write(AXILITE_VVCT,2, x"0020", x"efbeef","Write"); -- op1
axilite_write(AXILITE_VVCT,2, x"0030", x"beef","Write"); -- op2
axilite_write(AXILITE_VVCT,2, x"0040", x"54321","Write"); -- op3
axilite_write(AXILITE_VVCT,2, x"0060", x"f00b0","Write"); -- rw reg
AXILITE_VVC_SB.add_expected(2, pad_axilite_sb(x"f00b0"));
-- Read from VVC 2
axilite_read(AXILITE_VVCT, 2, x"0040", ""); -- just do a read
axilite_read(AXILITE_VVCT, 2, x"0040", ""); -- do another read
axilite_read(AXILITE_VVCT, 2, x"0060", TO_SB, "Read data and send to SB"); -- do another read - should see this data
await_completion(AXILITE_VVCT, 2, 1000 ns);
AXILITE_VVC_SB.report_counters(ALL_INSTANCES);
log(ID_LOG_HDR, "Test of timeout of check", C_SCOPE);
-- verify that a warning arises if the data is not what is expected
increment_expected_alerts(WARNING, 1);
axilite_check(AXILITE_VVCT,1, x"0006000", x"00000000", "Write", WARNING);
await_completion(AXILITE_VVCT, 1, 1000 ns);
-- verify that a warning arises if the data is not what is expected
increment_expected_alerts(WARNING, 1);
axilite_check(AXILITE_VVCT,2, x"0000040", x"00000000", "Check", WARNING);
await_completion(AXILITE_VVCT, 2, 1000 ns);
log(ID_LOG_HDR, "Test with byte enable", C_SCOPE);
axilite_write(AXILITE_VVCT,1, x"0006000", x"0","Clearing register");
axilite_write(AXILITE_VVCT,1, x"0006000", x"dada1960", std_logic_vector'("0011"), "Write to only byte 0 and 1");
await_completion(AXILITE_VVCT, 1, 1000 ns);
axilite_check(AXILITE_VVCT,1, x"0006000", x"00001960","Checking that only byte 0 and 1 were set");
axilite_write(AXILITE_VVCT,1, x"0006000", x"0","Clearing register");
axilite_write(AXILITE_VVCT,1, x"0006000", x"dada1960", std_logic_vector'("1100"), "Write to only byte 2 and 3");
await_completion(AXILITE_VVCT, 1, 1000 ns);
axilite_check(AXILITE_VVCT,1, x"0006000", x"dada0000","Checking that only byte 2 and 3 were set");
axilite_write(AXILITE_VVCT,2, x"0000040", x"0","Clearing register");
axilite_write(AXILITE_VVCT,2, x"0000040", x"abba1972", std_logic_vector'("00000011"), "Write to only byte 0 and 1");
await_completion(AXILITE_VVCT, 2, 1000 ns);
axilite_check(AXILITE_VVCT,2, x"0000040", x"00001972","Checking that only byte 0 and 1 were set");
axilite_write(AXILITE_VVCT,2, x"0000040", x"0","Clearing register");
axilite_write(AXILITE_VVCT,2, x"0000040", x"abba1972", std_logic_vector'("00001100"), "Write to only byte 2 and 3");
await_completion(AXILITE_VVCT, 2, 1000 ns);
axilite_check(AXILITE_VVCT,2, x"0000040", x"abba0000","Checking that only byte 2 and 3 were set");
-- Await completion on both VVCs
await_completion(AXILITE_VVCT, 1, 1000 ns);
await_completion(AXILITE_VVCT, 2, 1000 ns);
log(ID_LOG_HDR, "Testing inter-bfm delay", C_SCOPE);
log("\rChecking TIME_START2START", C_SCOPE);
wait for C_CLK_PERIOD * 51;
wait until rising_edge(clk);
shared_axilite_vvc_config(1).inter_bfm_delay.delay_type := TIME_START2START;
shared_axilite_vvc_config(1).inter_bfm_delay.delay_in_time := C_CLK_PERIOD * 50;
axilite_write(AXILITE_VVCT,1, x"0000", x"1111", "First inter-bfm delay axilite write");
await_completion(AXILITE_VVCT, 1, (56 * C_CLK_PERIOD));
v_timestamp := now;
axilite_write(AXILITE_VVCT,1, x"0000", x"a1a1", "Second inter-bfm delay axilite write");
await_completion(AXILITE_VVCT, 1, (56 * C_CLK_PERIOD));
check_value(now - v_timestamp, C_CLK_PERIOD*50, ERROR, "Checking that inter-bfm delay was upheld");
log("\rChecking that insert_delay does not affect inter-BFM delay", C_SCOPE);
wait for C_CLK_PERIOD * 51;
wait until rising_edge(clk);
axilite_write(AXILITE_VVCT,1, x"0000", x"ffff", "Third inter-bfm delay axilite write");
await_completion(AXILITE_VVCT, 1, (56 * C_CLK_PERIOD));
v_timestamp := now;
insert_delay(AXILITE_VVCT,1, C_CLK_PERIOD);
insert_delay(AXILITE_VVCT,1, C_CLK_PERIOD);
insert_delay(AXILITE_VVCT,1, C_CLK_PERIOD);
insert_delay(AXILITE_VVCT,1, C_CLK_PERIOD);
axilite_write(AXILITE_VVCT,1, x"0000", x"abcd", "Fourth inter-bfm delay axilite write");
await_completion(AXILITE_VVCT, 1, (56 * C_CLK_PERIOD));
check_value(now - v_timestamp, C_CLK_PERIOD*54, ERROR, "Checking that inter-bfm delay was upheld");
log("\rChecking TIME_START2START and provoking inter-bfm delay violation", C_SCOPE);
wait for C_CLK_PERIOD * 10;
shared_axilite_vvc_config(1).inter_bfm_delay.inter_bfm_delay_violation_severity := TB_WARNING;
shared_axilite_vvc_config(1).inter_bfm_delay.delay_type := TIME_START2START;
shared_axilite_vvc_config(1).inter_bfm_delay.delay_in_time := C_CLK_PERIOD;
axilite_write(AXILITE_VVCT,1, x"0000", x"0001", "First inter-bfm delay axilite write");
axilite_write(AXILITE_VVCT,1, x"0000", x"1000", "Second inter-bfm delay axilite write");
await_completion(AXILITE_VVCT, 1, 111 * C_CLK_PERIOD);
log("Setting delay back to initial value", C_SCOPE);
shared_axilite_vvc_config(1).inter_bfm_delay.delay_type := NO_DELAY;
shared_axilite_vvc_config(1).inter_bfm_delay.delay_in_time := 0 ns;
shared_axilite_vvc_config(1).bfm_config.bfm_sync := SYNC_WITH_SETUP_AND_HOLD;
shared_axilite_vvc_config(2).bfm_config.bfm_sync := SYNC_WITH_SETUP_AND_HOLD;
shared_axilite_vvc_config(1).bfm_config.setup_time := 2 ns;
shared_axilite_vvc_config(2).bfm_config.setup_time := 2 ns;
shared_axilite_vvc_config(1).bfm_config.hold_time := 3 ns;
shared_axilite_vvc_config(2).bfm_config.hold_time := 3 ns;
log(ID_LOG_HDR, "Simulation of AXI-Lite with bfm_sync = SYNC_WITH_SETUP_AND_HOLD, setup_time = 2 ns and hold_time = 3 ns;", C_SCOPE);
------------------------------------------------------------
-- Write to VVC 1
axilite_write(AXILITE_VVCT,1, x"0000", x"5555", "Test of axilite write");
axilite_write(AXILITE_VVCT,1, x"1000", x"befbeef","Write"); -- op0
axilite_write(AXILITE_VVCT,1, x"2000", x"efbeef","Write"); -- op1
axilite_write(AXILITE_VVCT,1, x"3000", x"beef","Write"); -- op2
axilite_write(AXILITE_VVCT,1, x"6000", x"54321","Write"); -- rw reg
await_completion(AXILITE_VVCT, 1, 1000 ns);
-- Read from VVC 1
axilite_read(AXILITE_VVCT, 1, x"3000", ""); -- just do a read
axilite_read(AXILITE_VVCT, 1, x"6000", ""); -- do another read - should see this data
-- verify read data on interface 1
v_cmd_idx := get_last_received_cmd_idx(AXILITE_VVCT, 1);
await_completion(AXILITE_VVCT, 1, 1 us, "waiting for axilite_read() to finish");
fetch_result(AXILITE_VVCT, 1, v_cmd_idx, v_data, v_is_ok, "Fetching read-result.");
check_value(v_is_ok, ERROR, "Readback OK via fetch_result()");
check_value(v_data(C_DATA_WIDTH_1-1 downto 0), x"54321", error, "verifying read data on interface 1.");
-- Write to VVC 2
axilite_write(AXILITE_VVCT,2, x"0000", x"5555", to_string("Test of axilite write"));
axilite_write(AXILITE_VVCT,2, x"0010", x"befbeef","Write"); -- op0
axilite_write(AXILITE_VVCT,2, x"0020", x"efbeef","Write"); -- op1
axilite_write(AXILITE_VVCT,2, x"0030", x"beef","Write"); -- op2
axilite_write(AXILITE_VVCT,2, x"0040", x"54321","Write"); -- op3
axilite_write(AXILITE_VVCT,2, x"0060", x"f00b0","Write"); -- rw reg
await_completion(AXILITE_VVCT, 2, 1000 ns);
-- Read from VVC 2
axilite_read(AXILITE_VVCT, 2, x"0040", ""); -- just do a read
axilite_read(AXILITE_VVCT, 2, x"0040", ""); -- do another read
axilite_read(AXILITE_VVCT, 2, x"0060", ""); -- do another read - should see this data
-- verify read data on interface 2
v_cmd_idx := get_last_received_cmd_idx(AXILITE_VVCT, 2);
await_completion(AXILITE_VVCT, 2, 1 us, "waiting for axilite_read() to finish");
fetch_result(AXILITE_VVCT, 2, v_cmd_idx, v_data, v_is_ok, "Fetching read-result.");
check_value(v_is_ok, ERROR, "Readback OK via fetch_result()");
check_value(v_data(C_DATA_WIDTH_2-1 downto 0), x"f00b0", error, "verifying read data on interface 2.");
-- check that is was correctly written on VVC 1
axilite_check(AXILITE_VVCT,1, x"0006000", x"54321","Check");
axilite_write(AXILITE_VVCT,1, x"0006000", x"abba1972","Write");
await_completion(AXILITE_VVCT, 1, 1000 ns);
axilite_check(AXILITE_VVCT,1, x"0006000", x"abba1972","Check");
-- check that is was correctly written on VVC 2
axilite_check(AXILITE_VVCT,2, x"0000", x"5555","Check");
axilite_check(AXILITE_VVCT,2, x"0010", x"befbeef","Check");
axilite_check(AXILITE_VVCT,2, x"0020", x"efbeef","Check");
axilite_check(AXILITE_VVCT,2, x"0030", x"beef","Check");
axilite_check(AXILITE_VVCT,2, x"0040", x"54321","Check");
await_completion(AXILITE_VVCT, 2, 1000 ns);
axilite_write(AXILITE_VVCT,2, x"0000040", x"abba1972","Write");
await_completion(AXILITE_VVCT, 2, 1000 ns);
axilite_check(AXILITE_VVCT,2, x"0000040", x"abba1972","Check");
-- Await completion on both VVCs
await_completion(AXILITE_VVCT, 1, 1000 ns);
await_completion(AXILITE_VVCT, 2, 1000 ns);
log(ID_LOG_HDR, "Test of timeout of check", C_SCOPE);
-- verify that a warning arises if the data is not what is expected
increment_expected_alerts(WARNING, 1);
axilite_check(AXILITE_VVCT,1, x"0006000", x"00000000", "Write", WARNING);
await_completion(AXILITE_VVCT, 1, 1000 ns);
-- verify that a warning arises if the data is not what is expected
increment_expected_alerts(WARNING, 1);
axilite_check(AXILITE_VVCT,2, x"0000040", x"00000000", "Check", WARNING);
await_completion(AXILITE_VVCT, 2, 1000 ns);
--------------------------------------------------------------------------------------------------------------------
-- Testing to force single pending transactions
--------------------------------------------------------------------------------------------------------------------
log(ID_LOG_HDR, "Testing to force single pending transactions");
-- First we measure the time it takes to perform a read and write simultaneously
v_timestamp := now;
axilite_write(AXILITE_VVCT, 2, x"0000", x"5555", "Test of axilite write");
axilite_read(AXILITE_VVCT, 2, x"0040", "Test of axilite read");
await_completion(AXILITE_VVCT, 2, 100 us, "Waiting for commands to finish");
v_measured_time := now - v_timestamp;
-- Then, we turn on the force_single_penging_transaction setting, and see that it takes about twice as long
shared_axilite_vvc_config(2).force_single_pending_transaction := true;
v_timestamp := now;
axilite_write(AXILITE_VVCT, 2, x"0000", x"5555", "Test of axilite write");
axilite_read(AXILITE_VVCT, 2, x"0040", "Test of axilite read");
await_completion(AXILITE_VVCT, 2, 100 us, "Waiting for commands to finish");
-- Checking that it takes twice as long (+- 20 %)
check_value_in_range(now - v_timestamp, v_measured_time*1.8, v_measured_time*2.2, ERROR, "Checking that it takes longer time to force a single pending transaction");
-----------------------------------------------------------------------------
-- Ending the simulation
-----------------------------------------------------------------------------
wait for 100 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- Finish the simulation
std.env.stop;
wait; -- to stop completely
end process p_main;
end func;
|
<reponame>HaraldBlab/vhdl-projects<filename>ring_of_fire/src/reset.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reset is
port (
clk : in std_logic;
rst_n : in std_logic; -- Pullup
rst : out std_logic
);
end reset;
architecture rtl of reset is
signal sreg : std_logic_vector(3 downto 0);
begin
SREG_PROC : process(clk)
begin
if rising_edge(clk) then
sreg <= sreg(sreg'high - 1 downto 0) & rst_n;
end if;
end process;
RESET_PROC : process(sreg)
constant all_ones : std_logic_vector(sreg'range) := (others => '1');
begin
if sreg = all_ones then
rst <= '0';
else
rst <= '1';
end if;
end process;
end architecture;
|
<reponame>ShruKin/Computer-Organization-and-Architecture-Software-Lab<gh_stars>0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY encoder42_df IS
PORT (
Y3, Y2, Y1, Y0 : IN BIT;
A1, A0 : OUT BIT
);
END encoder42_df;
ARCHITECTURE dataflow OF encoder42_df IS
BEGIN
A1 <= Y3 OR Y2;
A0 <= Y1 OR Y3;
END dataflow;
|
-- Code by www.jk-quantized.com
-- Redistribution and use of this code in source and binary forms
-- must retain the above attribution notice and this condition.
library ieee;
use ieee.std_logic_1164.all;
entity mux2to1 is
port (
d1, d0 : in std_logic;
s : in std_logic;
q : out std_logic
);
end entity;
architecture ac of mux2to1 is
begin
q <= ( s and d1 ) or ( ( not s ) and d0 );
end architecture;
--
|
library ieee;
use ieee.std_logic_1164.all;
library proclib;
use proclib.types.all;
entity mux is
port (SEL: in std_logic;
BYTEIN_0, BYTEIN_1: in ByteT;
BYTEOUT: out ByteT);
end entity;
architecture rtl of mux is
begin
BYTEOUT <= BYTEIN_1 when SEL = '1' else BYTEIN_0;
end architecture;
|
<reponame>pfasante/high-speed_bcrypt
-------------------------------------------------------------------------------
-- Title : password generation Topmodule
-- Project : bcrypt bruteforce
-- ----------------------------------------------------------------------------
-- File : pwd_gen.vhd
-- Author : <NAME> <<EMAIL>>
-- Company : Ruhr-University Bochum
-- Created : 2014-04-09
-- Last update: 2014-04-19
-- Platform : Xilinx Toolchain
-- Standard : VHDL'93/02/08
-- ----------------------------------------------------------------------------
-- Description:
-- generates passwords for bcrypt cores
-- ----------------------------------------------------------------------------
-- Copyright (c) 2011-2014 Ruhr-University Bochum
-- ----------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-04-09 1.0 fwi Created
-- 2014-04-19 1.01 fwi Changed to BRAM-password storage
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_bcrypt.all;
use work.rzi_helper.all;
entity pwd_gen is
generic (
INIT : std_logic_vector (PWD_LENGTH*getBitSize(CHARSET_LEN+1)-1 downto 0)
:= const_slv(0,PWD_LENGTH*getBitSize(CHARSET_LEN+1));
LENGTH : integer := 1
);
port (
clk : in std_logic;
rst : in std_logic;
continue: in std_logic; -- generate next pwd
done : out std_logic; -- indicates, that new pwd was generated
weA : out std_logic;
addrA : out std_logic_vector ( 4 downto 0);
dinA : out std_logic_vector (31 downto 0);
weB : out std_logic;
addrB : out std_logic_vector ( 4 downto 0);
dinB : out std_logic_vector (31 downto 0)
);
end pwd_gen;
architecture Behavioral of pwd_gen is
-- --------------------------------------------------------------------- --
-- Types
-- --------------------------------------------------------------------- --
type states_t is (
RESET,
--DELAY_A,
COUNTER_UPDATE,
DELAY,
LOAD_SHIFTREG,
WRITE_TO_BRAM,
IDLE
);
type pwd_cnt_ary_t is array (integer range <>) of
std_logic_vector(getBitSize(CHARSET_LEN+1)-1 downto 0);
-- --------------------------------------------------------------------- --
-- Signals
-- --------------------------------------------------------------------- --
-- FSM
signal current_state: states_t;
signal next_state : states_t;
-- Signals for generating password byte counter states
signal pwd_cnt_ceA : std_logic_vector(PWD_LENGTH-1 downto 0);
signal pwd_cnt_srA : std_logic_vector(PWD_LENGTH-1 downto 0);
signal pwd_cnt_srA_d: std_logic_vector(PWD_LENGTH-1 downto 0);
signal pwd_cnt_srA_d_rst: std_logic;
signal pwd_cnt_doutA: pwd_cnt_ary_t(PWD_LENGTH downto 0);
signal pwd_cnt_ceB : std_logic_vector(PWD_LENGTH-1 downto 0);
signal pwd_cnt_doutB: pwd_cnt_ary_t(PWD_LENGTH downto 0);
signal snd_iter_ce : std_logic;
signal snd_iter_sr : std_logic;
signal second_iteration : std_logic;
signal overflow : std_logic_vector(PWD_LENGTH-1 downto 0);
signal prev_overflow: std_logic_vector(PWD_LENGTH-1 downto 0);
signal is_actual_ce : std_logic;
signal is_actual_sr : std_logic;
signal is_actual_dout : std_logic_vector(PWD_LENGTH-1 downto 0);
signal actual_len_cntA_sr : std_logic;
signal actual_len_cntA_ce : std_logic;
signal actual_len_cntA_dout : std_logic_vector(PWD_BITLEN-1 downto 0);
signal actual_len_cntB_ce : std_logic;
signal actual_len_cntB_dout : std_logic_vector(PWD_BITLEN-1 downto 0);
-- Signals for generate password from counter state and output
signal int2asc_dinA : std_logic_vector(CHARSET_BIT-1 downto 0);
signal int2asc_doutA: std_logic_vector(7 downto 0);
signal int2asc_dinB : std_logic_vector(CHARSET_BIT-1 downto 0);
signal int2asc_doutB: std_logic_vector(7 downto 0);
signal mux_cntA_ce : std_logic;
signal mux_cntA_sr : std_logic;
signal mux_cntA_dout : std_logic_vector(PWD_BITLEN-1 downto 0);
signal mux_cntB_ce : std_logic;
signal mux_cntB_sr : std_logic;
signal mux_cntB_dout : std_logic_vector(PWD_BITLEN-1 downto 0);
signal pwd_reg_ceA : std_logic;
signal pwd_reg_srA : std_logic;
signal pwd_reg_doutA: std_logic_vector(31 downto 0);
signal pwd_reg_ceB : std_logic;
signal pwd_reg_srB : std_logic;
signal pwd_reg_doutB: std_logic_vector(31 downto 0);
-- Counter for State-Machine Transitions
signal updated_cnt_ce : std_logic;
signal updated_cnt_sr : std_logic;
signal updated_cnt_dout : std_logic_vector(PWD_BITLEN-1 downto 0);
signal loaded_bytes_cnt_ce : std_logic;
signal loaded_bytes_cnt_sr : std_logic;
signal loaded_bytes_cnt_dout: std_logic_vector(1 downto 0);
signal written_words_cnt_ce : std_logic;
signal written_words_cnt_sr : std_logic;
signal written_words_cnt_dout : std_logic_vector(4 downto 0);
begin
-- --------------------------------------------------------------------- --
-- --------------------------------------------------------------------- --
-- Logic for updating counter
-- --------------------------------------------------------------------- --
-- --------------------------------------------------------------------- --
-- Instantiation counter for password-bytes
-- --------------------------------------------------------------------- --
pwd_cnter : for i in 0 to PWD_LENGTH-1 generate
pwd_byte_cntA : entity work.nBitCounter
generic map (
BIT_WIDTH => getBitSize(CHARSET_LEN+1)
)
port map (
clk => clk,
ce => pwd_cnt_ceA(i),
sr => pwd_cnt_srA(i),
srinit => INIT(getBitSize(CHARSET_LEN+1)*(i+1)-1 downto getBitSize(CHARSET_LEN+1)*i),
count_up => '1',
dout => pwd_cnt_doutA(i+1)
);
pwd_byte_cntB : entity work.nBitReg
generic map (
BIT_WIDTH => getBitSize(CHARSET_LEN+1)
)
port map (
clk => clk,
ce => pwd_cnt_ceB(i),
sr => '0',
srinit => const_slv(0,getBitSize(CHARSET_LEN+1)),
din => pwd_cnt_doutA(i+1),
dout => pwd_cnt_doutB(i+1)
);
overflow(i) <= '1' when pwd_cnt_doutA(i+1)
= const_slv(CHARSET_LEN, getBitSize(CHARSET_LEN+1))
-- std_logic_vector(
-- to_unsigned(CHARSET_LEN-1,CHARSET_BIT))
else
'0';
end generate pwd_cnter;
pwd_byte_rst_delay : entity work.nBitReg
generic map (
BIT_WIDTH => PWD_LENGTH
)
port map (
clk => clk,
ce => '1',
sr => pwd_cnt_srA_d_rst,
srinit => const_slv(0, PWD_LENGTH),
din => pwd_cnt_srA,
dout => pwd_cnt_srA_d
);
pwd_cnt_doutA(0)<= (others => '0');
pwd_cnt_doutB(0)<= (others => '0');
-- prev_overflow <= overflow(PWD_LENGTH-2 downto 0) & '1';
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
prev_overflow(PWD_LENGTH-1 downto 1) <= (others => '0');
else
prev_overflow(PWD_LENGTH-1 downto 1) <= overflow(PWD_LENGTH-2 downto 0);
end if;
end if;
end process;
prev_overflow(0) <= is_actual_dout(0);
snd_iter : entity work.dff
generic map (
ASYNC => false
)
port map (
clk => clk,
ce => snd_iter_ce,
sr => snd_iter_sr,
srinit => '0',
D => '1',
Q => second_iteration
);
-- --------------------------------------------------------------------- --
-- Instantiation is_actual shift register
-- marks every active counter
-- delayed register is used for snd count up
-- and pwd_B load
-- --------------------------------------------------------------------- --
is_actual_shiftreg : entity work.nxmBitShiftReg
generic map (
N => PWD_LENGTH,
M => 1
)
port map (
clk => clk,
ce => is_actual_ce,
sr => is_actual_sr,
srinit => const_slv(1, PWD_LENGTH),
opmode => "11", -- [Rot?, Left?] -- [rotate,left]
din => "0",
dout => open,
dout_f => is_actual_dout
);
-- --------------------------------------------------------------------- --
-- Instantiation counts the actual password length
-- --------------------------------------------------------------------- --
actual_len_cntA : entity work.nBitCounter
generic map (
BIT_WIDTH => PWD_BITLEN)
port map (
clk => clk,
ce => actual_len_cntA_ce,
sr => actual_len_cntA_sr,
srinit => const_slv(LENGTH,PWD_BITLEN),
count_up => '1',
dout => actual_len_cntA_dout
);
actual_len_cntB : entity work.nBitReg
generic map (
BIT_WIDTH => PWD_BITLEN)
port map (
clk => clk,
ce => actual_len_cntB_ce,
sr => '0',
srinit => const_slv(0,PWD_BITLEN),
din => actual_len_cntA_dout,
dout => actual_len_cntB_dout
);
-- --------------------------------------------------------------------- --
-- Instantiation counts updated counter
-- e.g. from 0 to PWD_LENGTH-1
-- --------------------------------------------------------------------- --
updated_cnt : entity work.nBitCounter
generic map (
BIT_WIDTH => PWD_BITLEN)
port map (
clk => clk,
sr => updated_cnt_sr,
ce => updated_cnt_ce,
srinit => const_slv(0, PWD_BITLEN),
count_up => '1',
dout => updated_cnt_dout
);
-- --------------------------------------------------------------------- --
-- --------------------------------------------------------------------- --
-- Logic for mapping password counter to ascii values
-- --------------------------------------------------------------------- --
-- --------------------------------------------------------------------- --
-- Instantiation counter for the active pwd byte counter
-- (used to mux the password counter)
-- counts from highest active pwd-byte-counter down to 0
-- --------------------------------------------------------------------- --
mux_cntA : entity work.nBitCounter
generic map (
BIT_WIDTH => PWD_BITLEN)
port map (
clk => clk,
ce => mux_cntA_ce,
sr => mux_cntA_sr,
srinit => actual_len_cntA_dout,
count_up => '0',
dout => mux_cntA_dout
);
mux_cntB : entity work.nBitCounter
generic map (
BIT_WIDTH => PWD_BITLEN)
port map (
clk => clk,
ce => mux_cntB_ce,
sr => mux_cntB_sr,
srinit => actual_len_cntB_dout,
count_up => '0',
dout => mux_cntB_dout
);
-- --------------------------------------------------------------------- --
-- Instantiation int2asc mapper
-- --------------------------------------------------------------------- --
int2asc_mapA : entity work.int2asc
port map (
din => int2asc_dinA,
dout => int2asc_doutA
);
int2asc_mapB : entity work.int2asc
port map (
din => int2asc_dinB,
dout => int2asc_doutB
);
int2asc_dinA <= pwd_cnt_doutA(to_integer(unsigned(mux_cntA_dout)))(CHARSET_BIT-1 downto 0);
int2asc_dinB <= pwd_cnt_doutB(to_integer(unsigned(mux_cntB_dout)))(CHARSET_BIT-1 downto 0);
-- --------------------------------------------------------------------- --
-- --------------------------------------------------------------------- --
-- Logic for writing password
-- --------------------------------------------------------------------- --
-- --------------------------------------------------------------------- --
-- Instantiation password shiftregs
-- holds one of the 18 password-words
-- --------------------------------------------------------------------- --
pwd_regA : entity work.nxmBitShiftReg
generic map (
N => 4,
M => 8
)
port map (
clk => clk,
ce => pwd_reg_ceA,
sr => pwd_reg_srA,
srinit => const_slv(0, 32),
opmode => "01", -- [Rot?, Left?] -- [shift,right]
din => int2asc_doutA,
dout => open,
dout_f => pwd_reg_doutA
);
pwd_regB : entity work.nxmBitShiftReg
generic map (
N => 4,
M => 8
)
port map (
clk => clk,
ce => pwd_reg_ceB,
sr => pwd_reg_srB,
srinit => const_slv(0, 32),
opmode => "01", -- [Rot?, Left?] -- [shift,right]
din => int2asc_doutB,
dout => open,
dout_f => pwd_reg_doutB
);
-- --------------------------------------------------------------------- --
-- Instantiation counts loaded bytes for 32bit shiftreg
-- e.g. from 0 to 3
-- --------------------------------------------------------------------- --
loaded_bytes_cnt : entity work.nBitCounter
generic map (
BIT_WIDTH => 2)
port map (
clk => clk,
sr => loaded_bytes_cnt_sr,
ce => loaded_bytes_cnt_ce,
srinit => const_slv(0, 2),
count_up => '1',
dout => loaded_bytes_cnt_dout
);
-- --------------------------------------------------------------------- --
-- Instantiation counts written words to BRAM
-- e.g. from 0 to 17
-- --------------------------------------------------------------------- --
written_words_cnt : entity work.nBitCounter
generic map (
BIT_WIDTH => 5)
port map (
clk => clk,
sr => written_words_cnt_sr,
ce => written_words_cnt_ce,
srinit => const_slv(0, 5),
count_up => '1',
dout => written_words_cnt_dout
);
addrA <= written_words_cnt_dout;
addrB <= written_words_cnt_dout;
dinA <= pwd_reg_doutA;
dinB <= pwd_reg_doutB;
-- --------------------------------------------------------------------- --
-- --------------------------------------------------------------------- --
-- FSM
-- --------------------------------------------------------------------- --
-- --------------------------------------------------------------------- --
-- FSM: state change
fsm_state : process(clk, rst)
begin
if rising_edge(clk) then
if rst = '1' then
current_state <= RESET;
else
current_state <= next_state;
end if; -- rst
end if; -- clk
end process fsm_state;
-- FSM: control logic
fsm_ctrl : process (
current_state, continue, rst, second_iteration,
overflow, is_actual_dout, prev_overflow,
updated_cnt_dout, actual_len_cntA_dout, mux_cntA_dout, mux_cntB_dout,
loaded_bytes_cnt_dout, written_words_cnt_dout, pwd_cnt_srA_d)
begin
-- default values
-- counter and control signals
pwd_cnt_ceA <= (others => '0');
pwd_cnt_srA <= (others => '0');
pwd_cnt_ceB <= (others => '0');
pwd_cnt_srA_d_rst <= '1';
snd_iter_ce <= '0';
snd_iter_sr <= '0';
is_actual_ce <= '0';
is_actual_sr <= '0';
-- load password control signals
mux_cntA_ce <= '1';
mux_cntA_sr <= '1';
mux_cntB_ce <= '1';
mux_cntB_sr <= '1';
actual_len_cntA_ce <= '0';
actual_len_cntA_sr <= '0';
actual_len_cntB_ce <= '0';
updated_cnt_ce <= '1';
updated_cnt_sr <= '1';
loaded_bytes_cnt_ce <= '1';
loaded_bytes_cnt_sr <= '1';
pwd_reg_ceA <= '0';
pwd_reg_srA <= '0';
pwd_reg_ceB <= '0';
pwd_reg_srB <= '0';
-- write password control signals
written_words_cnt_ce <= '0';
written_words_cnt_sr <= '0';
weA <= '0';
weB <= '0';
done <= '0';
next_state <= current_state;
-- FSM states
case current_state is
-- startup
when RESET =>
is_actual_sr <= '1';
pwd_cnt_srA <= (others => '1');
pwd_cnt_ceB <= (others => '1');
snd_iter_sr <= '1';
--implicitly reset mux counter
actual_len_cntA_sr <= '1';
actual_len_cntB_ce <= '1';
pwd_reg_srA <= '1';
pwd_reg_srB <= '1';
written_words_cnt_sr <= '1';
-- TODO: check whats better: DELAY state or IF?
-- next_state <= DELAY_A;
-- when DELAY_A =>
if rst = '0' then
next_state <= COUNTER_UPDATE;
end if;
when COUNTER_UPDATE =>
is_actual_ce <= '1';
pwd_cnt_srA_d_rst <= '0';
pwd_cnt_ceA <= prev_overflow or pwd_cnt_srA_d;
pwd_cnt_srA <= overflow;
updated_cnt_sr <= '0';
-- if hightest active counter overflowed,
-- count up password length
if overflow(to_integer(unsigned(actual_len_cntA_dout))-1)
= '1'
then
actual_len_cntA_ce <= '1';
end if;
if updated_cnt_dout
= std_logic_vector(to_unsigned(PWD_LENGTH-1,PWD_BITLEN))
then
if second_iteration = '1' then
next_state <= DELAY;
else
pwd_cnt_ceB <= (others => '1');
is_actual_sr <= '1';
updated_cnt_sr <= '1';
actual_len_cntB_ce <= '1';
snd_iter_ce <= '1';
end if;
end if;
when DELAY =>
-- we have to delay the mux counter reset,
-- because the password length could have increased
-- implicitly reset password muxer
-- mux_cntA_sr <= '1';
-- mux_cntB_sr <= '1';
next_state <= LOAD_SHIFTREG;
when LOAD_SHIFTREG =>
-- mux next byte counter
if mux_cntA_dout = const_slv(0,PWD_BITLEN) then
mux_cntA_sr <= '1';
else
mux_cntA_sr <= '0';
end if;
-- mux next byte counter
if mux_cntB_dout = const_slv(0,PWD_BITLEN) then
mux_cntB_sr <= '1';
else
mux_cntB_sr <= '0';
end if;
-- count up number of loaded bytes
loaded_bytes_cnt_sr <= '0';
-- load byte to shiftregs
pwd_reg_ceA <= '1';
pwd_reg_ceB <= '1';
if loaded_bytes_cnt_dout = "11" then
next_state <= WRITE_TO_BRAM;
end if;
when WRITE_TO_BRAM =>
mux_cntA_sr <= '0';
mux_cntA_ce <= '0';
mux_cntB_sr <= '0';
mux_cntB_ce <= '0';
weA <= '1';
weB <= '1';
written_words_cnt_ce <= '1';
if written_words_cnt_dout = "10001" then
next_state <= IDLE;
else
next_state <= LOAD_SHIFTREG;
end if;
when IDLE =>
done <= '1';
snd_iter_sr <= '1';
is_actual_sr <= '1';
actual_len_cntB_ce <= '1';
pwd_reg_srA <= '1';
pwd_reg_ceB <= '1';
written_words_cnt_sr <= '1';
if continue = '1' then
next_state <= COUNTER_UPDATE;
end if;
end case; -- state
end process fsm_ctrl;
end Behavioral;
|
----------------------------------------------------------------------------------
-- -- -- Create Date: 4/10/2018
-- -- -- Module Name: sbox
-- -- -- Designer Name: <NAME>
-- -- --
-- -- ----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all; -- to unsigned and to integer
library work;
use work.constants.all;
entity shiftrows is
port(state_in : in STATE;
state_out : out STATE
);
end entity shiftrows;
architecture shiftrows_logic of shiftrows is
begin
-- first column
state_out(0) <= state_in(0);
state_out(1) <= state_in(5);
state_out(2) <= state_in(10);
state_out(3) <= state_in(15);
-- second column
state_out(4) <= state_in(4);
state_out(5) <= state_in(9);
state_out(6) <= state_in(14);
state_out(7) <= state_in(3);
-- third column
state_out(8) <= state_in(8);
state_out(9) <= state_in(13);
state_out(10) <= state_in(2);
state_out(11) <= state_in(7);
-- fourth column
state_out(12) <= state_in(12);
state_out(13) <= state_in(1);
state_out(14) <= state_in(6);
state_out(15) <= state_in(11);
end architecture shiftrows_logic;
|
<reponame>SeaRise/scutie2015-digimon
library ieee;
use ieee.std_logic_1164.ALL;
entity second is
port(Clk : in std_logic;
q : out std_logic);
end second;
architecture behav of second is
begin
process(Clk)
variable time:integer range 0 to 50000000;
begin
if rising_edge(Clk) then
time:=time+1;
if time<=25000000 then
q<='1';
else
if time<50000000 then
q<='0';
else
time:=0;
end if;
end if;
end if;
end process;
END behav;
|
<reponame>LukJA/ModularBlocks
/* maths_signed .vhd */
/* signed maths functions */
/* designed for modular general use under the K1 standard */
/* (c) <NAME> 2017 */
/* All software is written under the MIT license and available on Github */
/* this package contains signed maths of all types */
--------------------------------
/* signed add */
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use work.global.all;
entity M_signed_add is
generic (
word_width : integer := 16
);
port(
Q1 : in vector_t(word_width-1 downto 0) := (others=>'0');
Q2 : in vector_t(word_width-1 downto 0) := (others=>'0');
OV : out bit_t := '0';
output: out vector_t(word_width-1 downto 0) := (others=>'0')
);
end M_signed_add;
architecture logical of M_signed_add is
-- create locale signals with suffix '_s' for signed with one xtrea bit
signal Q1_s : SIGNED(word_width downto 0);
signal Q2_s : SIGNED(word_width downto 0);
signal output_s : SIGNED(word_width downto 0);
signal temp : std_logic_vector(2 downto 0);
begin
-- convert type and perform a sign-extension
Q1_s <= resize(signed(Q1), Q1_s'length);
Q2_s <= resize(signed(Q2), Q2_s'length);
-- addition of two 1 larger bit values
output_s <= Q1_s + Q2_s;
-- resize to require size and type conversion
output <= std_logic_vector(resize(output_s, output'length));
-- concat the three relevant sign-bits from a,b and sum to one vector
temp <= Q1_s(Q1_s'high) & Q2_s(Q2_s'high) & output_s(output_s'high);
process(all) begin
case temp is
when "001" => OV <= '1';
when "110" => OV <= '1';
when others => OV <= '0';
end case;
end process;
end logical;
--------------------------------
/* signed sub */
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use work.global.all;
entity M_signed_sub is
generic (
word_width : integer := 16
);
port(
Q1 : in vector_t(word_width-1 downto 0) := (others=>'0');
Q2 : in vector_t(word_width-1 downto 0) := (others=>'0');
OV : out bit_t := '0';
output: out vector_t(word_width-1 downto 0) := (others=>'0')
);
end M_signed_sub;
architecture logical of M_signed_sub is
-- create locale signals with suffix '_s' for signed with one xtrea bit
signal Q1_s : SIGNED(word_width downto 0);
signal Q2_s : SIGNED(word_width downto 0);
signal output_s : SIGNED(word_width downto 0);
signal temp : std_logic_vector(2 downto 0);
begin
-- convert type and perform a sign-extension
Q1_s <= resize(signed(Q1), Q1_s'length);
Q2_s <= resize(signed(Q2), Q2_s'length);
-- addition of two 1 larger bit values
output_s <= Q1_s - Q2_s;
-- resize to require size and type conversion
output <= std_logic_vector(resize(output_s, output'length));
-- concat the three relevant sign-bits from a,b and sum to one vector
temp <= Q1_s(Q1_s'high) & Q2_s(Q2_s'high) & output_s(output_s'high);
process(all) begin
case temp is
when "001" => OV <= '1';
when "110" => OV <= '1';
when others => OV <= '0';
end case;
end process;
end logical;
--------------------------------
/* signed multi */
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use work.global.all;
entity M_signed_multi is
generic (
word_width : integer := 16
);
port(
Q1 : in vector_t(word_width-1 downto 0) := (others=>'0');
Q2 : in vector_t(word_width-1 downto 0) := (others=>'0');
output: out vector_t(2*(word_width)-1 downto 0) := (others=>'0')
);
end M_signed_multi;
architecture logical of M_signed_multi is
signal temp : vector_t(word_width downto 0);
begin
temp <= std_logic_vector(unsigned(Q1) * unsigned(Q2));
output <= temp;
end logical;
|
<reponame>corywalker/vhdl_fft<gh_stars>1-10
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:26:21 10/22/2014
-- Design Name:
-- Module Name: C:/Users/John/Code/vhdl_fft/ft_controller_tb.vhd
-- Project Name: fft
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ft_controller
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ft_controller_tb IS
END ft_controller_tb;
ARCHITECTURE behavior OF ft_controller_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ft_controller
generic (
SIZE : positive;
SIZELOG : positive;
DELAY : positive;
INT_EXT_SEL: std_logic;
SPI_2X_CLK_DIV: positive;
DA_RESET_DELAY: positive
);
PORT(
CLK1 : IN std_logic;
rst : IN std_logic;
adc_miso : IN std_logic;
start_i : IN std_logic;
busy_o : OUT std_logic;
sck_i : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK1 : std_logic := '0';
signal rst : std_logic := '0';
signal start : std_logic := '0';
signal busy : std_logic;
signal sck : std_logic := '0';
-- Clock period definitions
constant CLK1_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ft_controller
generic map (
SIZE => 512,
SIZELOG => 9,
DELAY => 300,
INT_EXT_SEL => '0',
SPI_2X_CLK_DIV => 2,
DA_RESET_DELAY => 200
)
PORT MAP (
CLK1 => CLK1,
rst => rst,
start_i => start,
busy_o => busy,
sck_i => sck,
adc_miso => '0'
);
-- Clock process definitions
CLK1_process :process
begin
CLK1 <= '0';
wait for CLK1_period/2;
CLK1 <= '1';
wait for CLK1_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
loop
start <= '1';
wait for 30 ns;
start <= '0';
wait for CLK1_period*10;
wait until busy = '0';
wait for 1us;
for I in 0 to 512*16 loop
sck <= '1';
wait for 30 ns;
sck <= '0';
wait for 30 ns;
end loop;
wait for 10us;
end loop;
wait;
end process;
END;
|
<filename>vhdl/check/test/tb_check_next.vhd
-- This test suite verifies the check_next checker.
--
-- This Source Code Form is subject to the terms of the Mozilla Public
-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
-- You can obtain one at http://mozilla.org/MPL/2.0/.
--
-- Copyright (c) 2014, <NAME> <EMAIL>
library ieee;
use ieee.std_logic_1164.all;
library vunit_lib;
use vunit_lib.run_types_pkg.all;
use vunit_lib.run_base_pkg.all;
use vunit_lib.run_pkg.all;
use vunit_lib.log_types_pkg.all;
use vunit_lib.check_types_pkg.all;
use vunit_lib.check_special_types_pkg.all;
use vunit_lib.check_pkg.all;
use work.test_support.all;
use work.test_count.all;
entity tb_check_next is
generic (
runner_cfg : runner_cfg_t := runner_cfg_default);
end entity tb_check_next;
architecture test_fixture of tb_check_next is
signal clk : std_logic := '0';
signal one : std_logic := '1';
signal zero : std_logic := '0';
signal check_next_in_1, check_next_in_2, check_next_in_3, check_next_in_4, check_next_in_5 : std_logic_vector(1 to 3) := "001";
alias check_next_start_event_1 : std_logic is check_next_in_1(1);
alias check_next_expr_1 : std_logic is check_next_in_1(2);
alias check_next_en_1 : std_logic is check_next_in_1(3);
alias check_next_start_event_2 : std_logic is check_next_in_2(1);
alias check_next_expr_2 : std_logic is check_next_in_2(2);
alias check_next_en_2 : std_logic is check_next_in_2(3);
alias check_next_start_event_3 : std_logic is check_next_in_3(1);
alias check_next_expr_3 : std_logic is check_next_in_3(2);
alias check_next_en_3 : std_logic is check_next_in_3(3);
alias check_next_start_event_4 : std_logic is check_next_in_4(1);
alias check_next_expr_4 : std_logic is check_next_in_4(2);
alias check_next_en_4 : std_logic is check_next_in_4(3);
alias check_next_start_event_5 : std_logic is check_next_in_5(1);
alias check_next_expr_5 : std_logic is check_next_in_5(2);
alias check_next_en_5 : std_logic is check_next_in_5(3);
shared variable check_next_checker2, check_next_checker3, check_next_checker4, check_next_checker5 : checker_t;
begin
clock: process is
begin
while runner.phase < test_runner_exit loop
clk <= '1', '0' after 5 ns;
wait for 10 ns;
end loop;
wait;
end process clock;
check_next_1 : check_next(clk,
check_next_en_1,
check_next_start_event_1,
check_next_expr_1,
num_cks => 4);
check_next_2 : check_next(check_next_checker2,
clk,
check_next_en_2,
check_next_start_event_2,
check_next_expr_2,
active_clock_edge => falling_edge,
num_cks => 4);
check_next_3 : check_next(check_next_checker3,
clk,
check_next_en_3,
check_next_start_event_3,
check_next_expr_3,
num_cks => 4);
check_next_4 : check_next(check_next_checker4,
clk,
check_next_en_4,
check_next_start_event_4,
check_next_expr_4,
num_cks => 4,
allow_overlapping => false);
check_next_5 : check_next(check_next_checker5,
clk,
check_next_en_5,
check_next_start_event_5,
check_next_expr_5,
num_cks => 4,
allow_missing_start => false);
check_next_runner : process
variable pass : boolean;
variable stat : checker_stat_t;
procedure test_concurrent_check (
signal clk : in std_logic;
signal check_input : out std_logic_vector;
variable checker : inout checker_t;
constant level : in log_level_t := error;
constant active_rising_clock_edge : in boolean := true) is
begin
if running_test_case = "Test should pass when expr is true num cks enabled cycles after start event" then
get_checker_stat(checker, stat);
apply_sequence("001;101;001;001;000;001;011;001", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
verify_passed_checks(checker, stat, 1);
elsif running_test_case = "Test should fail when expr is false num cks enabled cycles after start event" then
apply_sequence("001;111;011;011;010;011;001;011;001", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
verify_log_call(inc_count, expected_level => level);
elsif running_test_case = "Test should handle a mix of passing and failing overlapping checks when allowed" then
get_checker_stat(checker, stat);
apply_sequence("001;101;001;101;101;000;011;001", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
verify_passed_checks(checker, stat, 1);
verify_failed_checks(checker, stat, 0);
apply_sequence("001;011;001", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
verify_passed_checks(checker, stat, 2);
verify_failed_checks(checker, stat, 0);
apply_sequence("001;001", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
verify_log_call(inc_count, expected_level => level);
elsif running_test_case = "Test should pass a true expr without start event if missing start is allowed" then
get_checker_stat(checker, stat);
apply_sequence("001;001;001;011;001", clk, check_input, active_rising_clock_edge);
wait for 1 ns;
verify_passed_checks(checker, stat, 1);
verify_failed_checks(checker, stat, 0);
end if;
end procedure test_concurrent_check;
begin
custom_checker_init_from_scratch(check_next_checker3, default_level => info);
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("Test should pass when expr is true num cks enabled cycles after start event") or
run("Test should fail when expr is false num cks enabled cycles after start event") or
run("Test should handle a mix of passing and failing overlapping checks when allowed") or
run("Test should pass a true expr without start event if missing start is allowed") then
test_concurrent_check(clk, check_next_in_1, default_checker);
test_concurrent_check(clk, check_next_in_2, check_next_checker2, error, false);
test_concurrent_check(clk, check_next_in_3, check_next_checker3, level => info);
elsif run("Test should fail when an overlapping check is initiated when not allowed") then
get_checker_stat(check_next_checker4, stat);
apply_sequence("001;101;001;101;001;011;001;011;001", clk, check_next_in_4);
wait for 1 ns;
verify_passed_checks(check_next_checker4, stat, 2);
verify_log_call(inc_count, "Overlapping not allowed.");
get_checker_stat(check_next_checker4, stat);
apply_sequence("001;101;001;001;001;111;001;001;001;011;001", clk, check_next_in_4);
wait for 1 ns;
verify_passed_checks(check_next_checker4, stat, 2);
verify_failed_checks(check_next_checker4, stat, 0);
elsif run("Test should fail a true expr without start event if missing start is not allowed") then
get_checker_stat(check_next_checker5, stat);
apply_sequence("001;001;001;011;001", clk, check_next_in_5);
wait for 1 ns;
verify_passed_checks(check_next_checker5, stat, 0);
verify_log_call(inc_count, "Missing start event for true expression.");
elsif run("Test should handle meta values") then
get_checker_stat(check_next_checker5, stat);
apply_sequence("00H;10H;00H;00H;00L;00H;01H;00H;00H", clk, check_next_in_5);
wait for 1 ns;
verify_passed_checks(check_next_checker5, stat, 1);
verify_failed_checks(check_next_checker5, stat, 0);
get_checker_stat(check_next_checker5, stat);
apply_sequence("0LH;1LH;0LH;0LH;0LL;0LH;0HH;0LH;0LH", clk, check_next_in_5);
wait for 1 ns;
verify_passed_checks(check_next_checker5, stat, 1);
verify_failed_checks(check_next_checker5, stat, 0);
get_checker_stat(check_next_checker5, stat);
apply_sequence("LLH;HLH;LLH;LLH;LLL;LLH;LHH;LLH;LLH", clk, check_next_in_5);
wait for 1 ns;
verify_passed_checks(check_next_checker5, stat, 1);
verify_failed_checks(check_next_checker5, stat, 0);
get_checker_stat(check_next_checker5, stat);
apply_sequence("XLH;HLH;LLH;LLH;LXX;LLH;LHH;LLH;LLH", clk, check_next_in_5);
wait for 1 ns;
verify_passed_checks(check_next_checker5, stat, 1);
verify_failed_checks(check_next_checker5, stat, 1);
end if;
end loop;
get_and_print_test_result(stat);
test_runner_cleanup(runner, stat);
wait;
end process;
test_runner_watchdog(runner, 2 us);
end test_fixture;
-- vunit_pragma run_all_in_same_sim
|
<gh_stars>0
-- Copyright (c) 2018 <NAME> <<EMAIL>>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
library work;
use work.cpu8080_types.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------------------------
-- Register File
--
-- 0: b 1:c
-- 2: d 3:e
-- 4: h 5:l
-- 6: m 7:a
-- 8: w 9:z
-- 10: act 11:tmp
-- 12: sph 13:spl => stack pointer
-- 14: pch 15:pcl => program counter
------------------------------------------------------------
entity cpu8080_regfile is
port (clk_i : in std_logic;
reset_i : in std_logic;
cmd_i : in regfile_cmd_t;
sel_a_i : in reg_t;
sel_b_i : in reg_t;
sel_rp_i : in reg_pair_t;
data_i : in unsigned(7 downto 0);
reg_a_o : out unsigned(7 downto 0);
reg_b_o : out unsigned(7 downto 0);
reg_pc_o : out unsigned(15 downto 0);
reg_rp_o : out unsigned(15 downto 0)
);
end cpu8080_regfile;
architecture rtl of cpu8080_regfile is
constant REGI_B : integer := to_integer(REG_B);
constant REGI_C : integer := to_integer(REG_C);
constant REGI_D : integer := to_integer(REG_D);
constant REGI_E : integer := to_integer(REG_E);
constant REGI_H : integer := to_integer(REG_H);
constant REGI_L : integer := to_integer(REG_L);
constant REGI_A : integer := to_integer(REG_A);
constant REGI_W : integer := to_integer(REG_W);
constant REGI_Z : integer := to_integer(REG_Z);
constant REGI_SPH : integer := to_integer(REG_SPH);
constant REGI_SPL : integer := to_integer(REG_SPL);
constant REGI_PCH : integer := to_integer(REG_PCH);
constant REGI_PCL : integer := to_integer(REG_PCL);
constant nr_regs : integer := 16;
type regfile_t is array(0 to nr_regs-1) of unsigned(7 downto 0);
signal regfile : regfile_t;
-- debug signals
signal regb_s : unsigned(7 downto 0);
signal regc_s : unsigned(7 downto 0);
signal regd_s : unsigned(7 downto 0);
signal rege_s : unsigned(7 downto 0);
signal regh_s : unsigned(7 downto 0);
signal regl_s : unsigned(7 downto 0);
signal rega_s : unsigned(7 downto 0);
signal regsph_s : unsigned(7 downto 0);
signal regspl_s : unsigned(7 downto 0);
signal regpch_s : unsigned(7 downto 0);
signal regpcl_s : unsigned(7 downto 0);
begin
control: process(clk_i,reset_i)
variable cmd_reg_a : integer range 0 to nr_regs-1;
variable cmd_reg_b : integer range 0 to nr_regs-1;
variable inc_val : unsigned(15 downto 0);
variable inc_b : unsigned(15 downto 0);
begin
if reset_i = '1' then
regfile <= (others=> (others=>'0'));
elsif clk_i'event and clk_i = '1' then
cmd_reg_a := to_integer(cmd_i.reg_a);
cmd_reg_b := to_integer(cmd_i.reg_b);
-- write
if cmd_i.wr = '1' then
regfile(cmd_reg_a) <= data_i;
-- mov
elsif cmd_i.mov = '1' then
regfile(cmd_reg_a) <= regfile(cmd_reg_b);
-- XCHG
elsif cmd_i.xchg = '1' then
regfile(REGI_D) <= regfile(REGI_H);
regfile(REGI_E) <= regfile(REGI_L);
regfile(REGI_H) <= regfile(REGI_D);
regfile(REGI_L) <= regfile(REGI_E);
end if;
-- inc/dec
if cmd_i.decrp = '1' then
inc_b := x"ffff";
else
inc_b := x"0001";
end if;
if cmd_i.incpc = '1' then
inc_val := ((regfile(REGI_PCH) & regfile(REGI_PCL)) + inc_b);
regfile(REGI_PCH) <= inc_val(15 downto 8);
regfile(REGI_PCL) <= inc_val(7 downto 0);
elsif cmd_i.incrp = '1' or cmd_i.decrp = '1' then
inc_val := ((regfile(cmd_reg_a) & regfile(cmd_reg_b)) + inc_b);
regfile(cmd_reg_a) <= inc_val(15 downto 8);
regfile(cmd_reg_b) <= inc_val(7 downto 0);
end if;
end if;
end process;
-- portA, portB output
reg_a_o <= regfile(to_integer(sel_a_i));
reg_b_o <= regfile(to_integer(sel_b_i));
-- PC output
reg_pc_o <= (regfile(REGI_PCH) & regfile(REGI_PCL));
-- PC,SP,BC,DE,HL output
with sel_rp_i select reg_rp_o <=
(regfile(REGI_PCH) & regfile(REGI_PCL)) when REG_PC,
(regfile(REGI_SPH) & regfile(REGI_SPL)) when REG_SP,
(regfile(REGI_B) & regfile(REGI_C)) when REG_BC,
(regfile(REGI_D) & regfile(REGI_E)) when REG_DE,
(regfile(REGI_H) & regfile(REGI_L)) when REG_HL,
(regfile(REGI_W) & regfile(REGI_Z)) when REG_WZ,
(regfile(REGI_H) & regfile(REGI_L)) when others;
-- debug signals
regb_s <= regfile(REGI_B);
regc_s <= regfile(REGI_C);
regd_s <= regfile(REGI_D);
rege_s <= regfile(REGI_E);
regh_s <= regfile(REGI_H);
regl_s <= regfile(REGI_L);
rega_s <= regfile(REGI_A);
regsph_s <= regfile(REGI_SPH);
regspl_s <= regfile(REGI_SPL);
regpch_s <= regfile(REGI_PCH);
regpcl_s <= regfile(REGI_PCL);
end rtl;
|
<filename>VHDL/Filter_Bank/reconstruction.vhd
--------------------------------------------------------------------------------------------------
-- Signal Reconstruction
--------------------------------------------------------------------------------------------------
-- <NAME> - <EMAIL>
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package reconstruction_pkg is
--FIR filter component declaration
component reconstruction is
generic( low_pass : coefficient_array;
high_pass : coefficient_array);
port( clk_low : in std_logic;
clk_high : in std_logic;
rst : in std_logic;
x_low : in sig;
x_high : in sig;
y : out sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.interpolator_pkg.all;
entity reconstruction is
generic( low_pass : coefficient_array;
high_pass : coefficient_array);
port( clk_low : in std_logic;
clk_high : in std_logic;
rst : in std_logic;
x_low : in sig;
x_high : in sig;
y : out sig);
end reconstruction;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of reconstruction is
signal y_low : sig := (others => '0');
signal y_high : sig := (others => '0');
begin
--Decimate the signal using a low pass filter
low_filter_bank : interpolator
generic map(h => low_pass)
port map( clk_high => clk_high,
clk_low => clk_low,
rst => rst,
sig_low => x_low,
sig_high => y_low);
--Decimate the signal using a high pass filter
high_filter_bank : interpolator
generic map(h => high_pass)
port map( clk_high => clk_high,
clk_low => clk_low,
rst => rst,
sig_low => x_high,
sig_high => y_high);
--Sum the 2 banks together
update_sum : process(clk_high)
begin
if(rising_edge(clk_high)) then
if(rst = '1') then
y <= (others => '0');
else
y <= signed(y_low) + signed(y_high);
end if;
end if;
end process;
end behave;
|
<reponame>najibarbaoui/academic_project3
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: analog.com:user:axi_i2s_adi:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_axi_i2s_adi_0 IS
PORT (
DATA_CLK_I : IN STD_LOGIC;
BCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
LRCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
DMA_REQ_TX_ACLK : IN STD_LOGIC;
DMA_REQ_TX_RSTN : IN STD_LOGIC;
DMA_REQ_TX_DAVALID : IN STD_LOGIC;
DMA_REQ_TX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DAREADY : OUT STD_LOGIC;
DMA_REQ_TX_DRVALID : OUT STD_LOGIC;
DMA_REQ_TX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DRLAST : OUT STD_LOGIC;
DMA_REQ_TX_DRREADY : IN STD_LOGIC;
DMA_REQ_RX_ACLK : IN STD_LOGIC;
DMA_REQ_RX_RSTN : IN STD_LOGIC;
DMA_REQ_RX_DAVALID : IN STD_LOGIC;
DMA_REQ_RX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DAREADY : OUT STD_LOGIC;
DMA_REQ_RX_DRVALID : OUT STD_LOGIC;
DMA_REQ_RX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DRLAST : OUT STD_LOGIC;
DMA_REQ_RX_DRREADY : IN STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC
);
END system_axi_i2s_adi_0;
ARCHITECTURE system_axi_i2s_adi_0_arch OF system_axi_i2s_adi_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_axi_i2s_adi_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_i2s_adi IS
GENERIC (
C_SLOT_WIDTH : INTEGER;
C_LRCLK_POL : INTEGER;
C_BCLK_POL : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_MIN_SIZE : STD_LOGIC_VECTOR;
C_FAMILY : STRING;
C_DMA_TYPE : INTEGER;
C_NUM_CH : INTEGER;
C_HAS_TX : INTEGER;
C_HAS_RX : INTEGER
);
PORT (
DATA_CLK_I : IN STD_LOGIC;
BCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
LRCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXIS_ACLK : IN STD_LOGIC;
S_AXIS_ARESETN : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
M_AXIS_ACLK : IN STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DMA_REQ_TX_ACLK : IN STD_LOGIC;
DMA_REQ_TX_RSTN : IN STD_LOGIC;
DMA_REQ_TX_DAVALID : IN STD_LOGIC;
DMA_REQ_TX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DAREADY : OUT STD_LOGIC;
DMA_REQ_TX_DRVALID : OUT STD_LOGIC;
DMA_REQ_TX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DRLAST : OUT STD_LOGIC;
DMA_REQ_TX_DRREADY : IN STD_LOGIC;
DMA_REQ_RX_ACLK : IN STD_LOGIC;
DMA_REQ_RX_RSTN : IN STD_LOGIC;
DMA_REQ_RX_DAVALID : IN STD_LOGIC;
DMA_REQ_RX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DAREADY : OUT STD_LOGIC;
DMA_REQ_RX_DRVALID : OUT STD_LOGIC;
DMA_REQ_RX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DRLAST : OUT STD_LOGIC;
DMA_REQ_RX_DRREADY : IN STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC
);
END COMPONENT axi_i2s_adi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_axi_i2s_adi_0_arch: ARCHITECTURE IS "axi_i2s_adi,Vivado 2015.2.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_axi_i2s_adi_0_arch : ARCHITECTURE IS "system_axi_i2s_adi_0,axi_i2s_adi,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 DMA_REQ_TX_ACLK CLK, xilinx.com:signal:clock:1.0 DMA_REQ_TX_DMA_ACK_TX_signal_clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_RSTN: SIGNAL IS "xilinx.com:signal:reset:1.0 DMA_REQ_TX_DMA_ACK_TX_signal_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DAVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_ACK_TX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DATYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_ACK_TX TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DAREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_ACK_TX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_REQ_TX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRTYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_REQ_TX TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_REQ_TX TLAST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_REQ_TX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 DMA_REQ_RX_ACLK CLK, xilinx.com:signal:clock:1.0 DMA_REQ_RX_DMA_ACK_RX_signal_clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_RSTN: SIGNAL IS "xilinx.com:signal:reset:1.0 DMA_REQ_RX_DMA_ACK_RX_signal_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DAVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_ACK_RX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DATYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_ACK_RX TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DAREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_ACK_RX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_REQ_RX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRTYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_REQ_RX TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_REQ_RX TLAST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_REQ_RX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
BEGIN
U0 : axi_i2s_adi
GENERIC MAP (
C_SLOT_WIDTH => 24,
C_LRCLK_POL => 0,
C_BCLK_POL => 0,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 16,
C_S_AXI_MIN_SIZE => X"000001FF",
C_FAMILY => "zynq",
C_DMA_TYPE => 1,
C_NUM_CH => 1,
C_HAS_TX => 1,
C_HAS_RX => 1
)
PORT MAP (
DATA_CLK_I => DATA_CLK_I,
BCLK_O => BCLK_O,
LRCLK_O => LRCLK_O,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
S_AXIS_ACLK => '0',
S_AXIS_ARESETN => '0',
S_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXIS_TLAST => '0',
S_AXIS_TVALID => '0',
M_AXIS_ACLK => '0',
M_AXIS_TREADY => '0',
DMA_REQ_TX_ACLK => DMA_REQ_TX_ACLK,
DMA_REQ_TX_RSTN => DMA_REQ_TX_RSTN,
DMA_REQ_TX_DAVALID => DMA_REQ_TX_DAVALID,
DMA_REQ_TX_DATYPE => DMA_REQ_TX_DATYPE,
DMA_REQ_TX_DAREADY => DMA_REQ_TX_DAREADY,
DMA_REQ_TX_DRVALID => DMA_REQ_TX_DRVALID,
DMA_REQ_TX_DRTYPE => DMA_REQ_TX_DRTYPE,
DMA_REQ_TX_DRLAST => DMA_REQ_TX_DRLAST,
DMA_REQ_TX_DRREADY => DMA_REQ_TX_DRREADY,
DMA_REQ_RX_ACLK => DMA_REQ_RX_ACLK,
DMA_REQ_RX_RSTN => DMA_REQ_RX_RSTN,
DMA_REQ_RX_DAVALID => DMA_REQ_RX_DAVALID,
DMA_REQ_RX_DATYPE => DMA_REQ_RX_DATYPE,
DMA_REQ_RX_DAREADY => DMA_REQ_RX_DAREADY,
DMA_REQ_RX_DRVALID => DMA_REQ_RX_DRVALID,
DMA_REQ_RX_DRTYPE => DMA_REQ_RX_DRTYPE,
DMA_REQ_RX_DRLAST => DMA_REQ_RX_DRLAST,
DMA_REQ_RX_DRREADY => DMA_REQ_RX_DRREADY,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY
);
END system_axi_i2s_adi_0_arch;
|
<gh_stars>10-100
------------------------------------------------------------------------------
--
-- SHA-256 Systolic Hashing Engine
-- little_sigma_0.vhd
--
-- This file contains a clock-less combinational logic implementation of the
-- small sigma_0^{256}(x) function defined in FIPS 180-2 section 4.1.2 as:
-- sigma_0^{256}(x) = ROTR^7(x) xor ROTR^18(x) xor SHR^3(x)
--
-- Copyright 2011 <NAME>. All rights reserved.
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.shatypes.all;
entity little_sigma_0 is
port (
x : in word;
q : out word
);
end little_sigma_0;
architecture rtl of little_sigma_0 is
begin
q <= (x( 6 downto 0) & x(31 downto 7)) xor
(x(17 downto 0) & x(31 downto 18)) xor
("000" & x(31 downto 3));
end rtl;
|
<filename>VHDL/src/CheckPattern/divider.vhd<gh_stars>0
--Engineer : <NAME>
--Date : 11/22/2017
--Name of file : divider.vhd
--Description : divides two intervals to give the ratio result
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity divider is
generic (
R_int : positive; -- resolution of interval
R_ctr : positive; -- resolution divider counter
N_dec : positive -- number of fixed point decimal places
);
port (
-- inputs --
clk, reset : in std_logic;
start : in std_logic;
numerator : in unsigned(R_int-1 downto 0);
denominator : in unsigned(R_int-1 downto 0);
-- outputs --
done : out std_logic;
result : out unsigned(R_int-1 downto 0)
);
end divider;
architecture divider_arch of divider is
-- constant definitions
-- signal definitions
signal N : unsigned(R_int+N_dec-1 downto 0); --adjusted numerator
signal D : unsigned(R_int-1 downto 0); -- adjusted denominator
signal done_buf, prev_done_buf : std_logic;
-- debug signals
-- signal counter : unsigned(R_ctr-1 downto 0);
-- signal quotient : unsigned(R_int+N_dec-1 downto 0);
-- signal remainder : unsigned(R_int-1 downto 0);
begin
process ( clk, reset, start )
variable idx : unsigned(R_ctr-1 downto 0);
variable Q : unsigned(R_int+N_dec-1 downto 0); -- quotient
variable R : unsigned(R_int-1 downto 0); -- remainder
begin
if ( reset='1' or start='1' ) then
done_buf <= '0';
idx := to_unsigned(R_int+N_dec-1,R_ctr);
Q := (others=>'0');
R := (others=>'0');
result <= (others=>'0');
elsif ( rising_edge(clk) ) then
-- output to debug signals --
-- counter <= idx;
-- quotient <= Q;
-- remainder <= R;
N <= numerator & to_unsigned(0,N_dec);
D <= denominator;
prev_done_buf <= done_buf;
if ( D>0 ) then
if (idx > 0) then
R := R(R_int-2 downto 0) & N(to_integer(idx));
if ( R >= D ) then
R := R - D;
Q(to_integer(idx)) := '1';
end if;
-- decrement idx and check if done
idx := idx - 1;
if( not(idx>0) ) then
done_buf <= '1';
result <= Q(R_int-1 downto 0); -- assign Q to result
end if;
end if;
else
done_buf <= '1';
result <= (others=>'0');
end if;
end if;
end process;
-- manage done signal
process ( clk, reset ) begin
if ( reset='1' ) then
done <= '0';
elsif ( rising_edge(clk) ) then
if ( prev_done_buf='0' and done_buf='1' ) then
done <= '1';
else
done <= '0';
end if;
end if;
end process;
end divider_arch;
|
library ieee;
library std;
use ieee.std_logic_1164.all;
use std.textio.all;
entity UART is
port(
TX: out std_logic := '1';
RX: in std_logic;
clk: in std_logic;
tx_begin: in std_logic;
tx_data: in std_logic_vector(7 downto 0) := (others => '0');
tx_done: out std_logic := '1';
rx_data: out std_logic_vector(7 downto 0) := (others => '0');
rx_flag: out std_logic := '0'
);
end UART;
architecture RTL of UART is
-- Fosc / baud
-- 25 M / 115200 = 217
constant ticks: integer := 217;
type tx_state_t is (TX_IDLE, TX_START, TX_SEND, TX_STOP);
signal tx_state: tx_state_t := TX_IDLE;
type rx_state_t is (RX_IDLE, RX_START, RX_RECV, RX_STOP);
signal rx_state: rx_state_t := RX_IDLE;
begin
handle_tx: process (clk) is
variable tick_count: integer := 0;
variable bit_index: integer := 0;
variable l: line;
begin
if rising_edge(clk) then
tick_count := tick_count + 1;
case tx_state is
when TX_IDLE =>
TX <= '1';
tx_done <= '1';
if tx_begin = '1' then
tx_state <= TX_START;
tx_done <= '0';
write(l, String'("Start"));
writeline(output, l);
end if;
when TX_START =>
tick_count := 0;
TX <= '0';
tx_state <= TX_SEND;
write(l, String'("Send"));
writeline(output, l);
when TX_SEND =>
if tick_count >= ticks then
if bit_index < 8 then
TX <= tx_data(bit_index);
bit_index := bit_index + 1;
else
bit_index := 0;
tx_state <= TX_STOP;
write(l, String'("Stop"));
writeline(output, l);
end if;
tick_count := 0;
end if;
when TX_STOP =>
TX <= '1';
if tick_count >= ticks then
tx_state <= TX_IDLE;
write(l, String'("Idle"));
writeline(output, l);
tick_count := 0;
end if;
when others =>
tx_state <= TX_IDLE;
write(l, String'("Idle"));
writeline(output, l);
end case;
end if;
end process;
handle_rx: process(clk) is
variable bit_index: integer := 0;
variable tick_count: integer := 0;
begin
if rising_edge(clk) then
tick_count := tick_count + 1;
case rx_state is
when RX_IDLE =>
rx_flag <= '0';
if RX = '0' then
rx_state <= RX_START;
tick_count := 0;
end if;
when RX_START =>
-- Align the sampling with the middle of the bit_indexes
if tick_count >= ticks / 2 then
tick_count := 0;
rx_state <= RX_RECV;
end if;
when RX_RECV =>
if tick_count >= ticks then
if bit_index < 8 then
rx_data(bit_index) <= RX;
bit_index := bit_index + 1;
else
bit_index := 0;
rx_state <= RX_STOP;
end if;
tick_count := 0;
end if;
when RX_STOP =>
if ticks >= tick_count then
rx_flag <= '1';
rx_state <= RX_IDLE;
tick_count := 0;
end if;
when others =>
rx_state <= RX_IDLE;
end case;
end if;
end process;
end RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.ram.all;
entity Dcache is
port(
-- Dcache outterface
mem_adr : in Std_Logic_Vector(31 downto 0);
mem_stw : in Std_Logic;
mem_stb : in Std_Logic;
mem_load : in Std_Logic;
mem_data : in Std_Logic_Vector(31 downto 0);
dc_data : out Std_Logic_Vector(31 downto 0);
dc_stall : out Std_Logic;
ck : in Std_logic);
end Dcache;
----------------------------------------------------------------------
architecture Behavior OF Dcache is
begin
-- Gestion du PC
process (mem_adr, mem_load)
variable adr : signed(31 downto 0);
variable data : signed(31 downto 0);
begin
if (mem_load = '1') then
adr := signed(mem_adr);
data := TO_SIGNED(mem_lw(TO_INTEGER(adr)), 32);
dc_data <= std_logic_vector(data);
end if;
end process;
process (ck)
variable adr : signed(31 downto 0);
variable data : signed(31 downto 0);
variable res : integer;
begin
if rising_edge(ck) then
adr := signed(mem_adr);
data := signed(mem_data);
if mem_stw = '1' then
res := mem_sw(TO_INTEGER(adr), TO_INTEGER(data));
elsif mem_stb='1' then
res := mem_sb(TO_INTEGER(adr), TO_INTEGER(data));
end if;
end if;
end process;
dc_stall <= '0';
end Behavior;
|
<reponame>Dmitriy0111/nanoFOX_VHDL
--
-- File : nf_settings.vhd
-- Autor : <NAME>.
-- Data : 2019.04.20
-- Language : VHDL
-- Description : This is file with common settings
-- Copyright(c) : 2019 <NAME>.
--
library ieee;
use ieee.std_logic_1164.all;
package nf_settings is
constant PROG_START : integer := 0;
-- depth of ram module
constant ADDR_D_W : integer := 20;
constant MEM_D_DEPTH : integer := 2 ** ADDR_D_W;
-- depth of instruction memory module
constant ADDR_I_W : integer := 20;
constant MEM_I_DEPTH : integer := 2 ** ADDR_I_W;
-- number of slave device's
constant SLAVE_COUNT : integer := 3;
--
-- memory map for devices
--
-- 0x0000_0000\
-- \
-- RAM
-- /
-- 0x0000_ffff/
-- 0x0001_0000\
-- \
-- UART
-- /
-- 0x0001_ffff/
-- 0x0002_0000\
-- \
-- AHB2APB_BRIDGE
-- /
-- 0x0002_ffff/
-- 0x0004_0000\
-- \
-- Unused
-- /
-- 0xffff_ffff/
--
-- constant's for gpio module
constant NF_GPIO_WIDTH : integer := 8;
constant NF_GPIO_GPI : std_logic_vector(3 downto 0) := 4X"0";
constant NF_GPIO_GPO : std_logic_vector(3 downto 0) := 4X"4";
constant NF_GPIO_DIR : std_logic_vector(3 downto 0) := 4X"8";
constant NF_GPIO_EN : std_logic_vector(3 downto 0) := 4X"C";
-- constant's for uart module
constant NF_UART_CR : std_logic_vector(3 downto 0) := 4X"0";
constant NF_UART_TX : std_logic_vector(3 downto 0) := 4X"4";
constant NF_UART_RX : std_logic_vector(3 downto 0) := 4X"8";
constant NF_UART_DR : std_logic_vector(3 downto 0) := 4X"C";
--
type logic_array is array(natural range <>) of std_logic;
type logic_v_array is array(natural range <>) of std_logic_vector;
function slv_2_la(slv : std_logic_vector) return logic_array;
constant NF_RAM_ADDR_MATCH : std_logic_vector(31 downto 0) := 32X"0000----";
constant NF_UART_ADDR_MATCH : std_logic_vector(31 downto 0) := 32X"0001----";
constant NF_AHB_APB_MATCH : std_logic_vector(31 downto 0) := 32X"0002----";
constant NF_APB_GPIO_0_ADDR : std_logic_vector(7 downto 0) := 8X"0-";
constant NF_APB_PWM_0_ADDR : std_logic_vector(7 downto 0) := 8X"2-";
constant ahb_vector : logic_v_array(SLAVE_COUNT-1 downto 0)(31 downto 0) :=
(
NF_RAM_ADDR_MATCH,
NF_UART_ADDR_MATCH,
NF_AHB_APB_MATCH
);
end package nf_settings;
package body nf_settings is
function slv_2_la(slv : std_logic_vector)
return logic_array is
variable result_l_a : logic_array(slv'range);
begin
for i in 0 to slv'length-1 loop
result_l_a(i) := slv(i);
end loop;
return result_l_a;
end function;
end package body nf_settings;
|
entity c is
end c;
architecture behav of c is
begin
end behav;
|
<gh_stars>1-10
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity comp_2p2z is
generic ( gain : real := 100.0; -- high DC gain for good load regulation
fp1 : real := 7.5e3; -- pole location to achieve crossover frequency
fp2 : real := 531.0e3; -- pole location to cancel effect of ESR
fz1 : real := 403.0; -- zero locations to cancel L-C filter poles
fz2 : real := 403.0 );
port ( terminal input, output, ref : electrical );
end entity comp_2p2z;
----------------------------------------------------------------
architecture ltf of comp_2p2z is
quantity vin across input to ref;
quantity vout across iout through output to ref;
constant wp1 : real := math_2_pi * fp1; -- Pole freq (in radians)
constant wp2 : real := math_2_pi * fp2;
constant wz1 : real := math_2_pi * fz1; -- Zero freq (in radians)
constant wz2 : real := math_2_pi * fz2;
constant num : real_vector := ( 1.0,
(wz1 + wz2) / (wz1 * wz2),
1.0 / (wz1 * wz2) );
constant den : real_vector := ( 1.0e-9, 1.0,
(wp1 + wp2) / (wp1 * wp2),
1.0 / (wp1 * wp2) );
begin
vout == -1.0 * gain * vin'ltf(num, den);
end architecture ltf;
|
<reponame>IslamZangin/ArchitecturePorject
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity MUX_Fetch is
port (
Sel: in std_logic_vector (1 downto 0);--input from control unit
--at reset control unit send zeroes to pcs
--PC1: in std_logic_vector(15 downto 0 ); --
PC2: in std_logic_vector(15 downto 0 ); --address to jump to from BRANCH
PC3: in std_logic_vector(15 downto 0 ); --address from memory[0]
PC4: in std_logic_vector(15 downto 0 ); --address from memory[1]
CLK: in std_logic;
Out_instruction: out std_logic_vector(15 downto 0 );
InPort: in std_logic_vector(15 downto 0);
OutPort: out std_logic_vector(15 downto 0);
RESET: in std_logic
);
end entity MUX_Fetch;
architecture MUX_Fetch_Arch of MUX_Fetch is
Component syncram is
generic ( n : integer := 16);
port (
clk : in std_logic;
we : in std_logic;
address : in std_logic_vector(n-1 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto 0)
);
end component;
--***********************************************************************************
Component PC is
port (
counter: in std_logic_vector(15 downto 0 );
new_counter: out std_logic_vector(15 downto 0 );
CLK: in std_logic;
RESET: in std_logic
);
end component;
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Component Ext_Mem_Buffer is
Generic ( n : integer := 16);
port (
Clk : in std_logic;
Rst : in std_logic;
--enable : in std_logic;
inport_en_input : in std_logic_vector(15 downto 0); --??????????????
instruction_input :in std_logic_vector(15 downto 0);
inport_en_output : out std_logic_vector(15 downto 0); --??????????????
instruction_output :out std_logic_vector(15 downto 0);
OPcode: out std_logic_vector(4 downto 0 );
R1: out std_logic_vector(2 downto 0 ); --addres of reg1
R2: out std_logic_vector(2 downto 0 ); --addres of reg2
Rout: out std_logic_vector(2 downto 0 ) --for write back
--LDD_Memory: out std_logic_vector(9 downto 0 ); --load value from memory to register
--LDM_immediate: out std_logic_vector(15 downto 0 ); --load immediate value from user to register
--input_port : in std_logic_vector(15 downto 0 )
);
end component;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
signal MY_PC_SIGNAL: std_logic_vector(15 downto 0);
--signal new_count: std_logic_vector(15 downto 0);
signal PC1: std_logic_vector(15 downto 0);
signal copied_data: std_logic_vector(15 downto 0);
-----------------------BUFFER SIGNALS--------------------------
signal inport_en_output_signal: std_logic_vector(15 downto 0); --??????????????
signal instruction_output_signal : std_logic_vector(15 downto 0);
signal OPcode_signal: std_logic_vector(4 downto 0 );
signal R1_signal: std_logic_vector(2 downto 0 ); --addres of reg1
signal R2_signal: std_logic_vector(2 downto 0 ); --addres of reg2
signal Rout_signal: std_logic_vector(2 downto 0 ); --for write back
---------------------------------------------
begin
--inport data
--regesiter to store data of inport
OutPort<=InPort;
--send zero to pc when reset
MY_PC_SIGNAL <= PC1 when Sel = "00" and RESET='0' else
PC2 when Sel = "01" and RESET='0' else
PC3 when Sel = "10" and RESET='0' else
PC4 when Sel = "11" and RESET='0'else
(others => '0') when RESET='1' else
(others => '0');
--------------------------------------
set0: syncram generic map (n =>16) port map (CLK,'0',MY_PC_SIGNAL,"0000000000000000",copied_data); --clk,enable,(address to WRITE in),data to write, outputdata from selected address
My_PC: PC port map (MY_PC_SIGNAL,PC1,CLK,RESET);
--PC1<=MY_PC_SIGNAL;
Out_instruction<=copied_data;
--Out_PC<=MY_PC_SIGNAL;
end architecture MUX_Fetch_Arch;
|
<reponame>slaclab/lcls-timing-core
-------------------------------------------------------------------------------
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- This file is part of 'LCLS Timing Core'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'LCLS Timing Core', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.NUMERIC_STD.all;
library surf;
use surf.StdRtlPkg.all;
use surf.AxiStreamPkg.all;
--use work.SsiPciePkg.all;
library lcls_timing_core;
use lcls_timing_core.TimingPkg.all;
use lcls_timing_core.EvrV2Pkg.all;
--use work.PciPkg.all;
use surf.SsiPkg.all;
use lcls_timing_core.TPGPkg.all;
entity EvrV2_tb is
end EvrV2_tb;
architecture mapping of EvrV2_tb is
constant TPD_G : time := 1 ns;
signal evrClk : sl;
signal evrRst : sl;
signal evrBus : TimingBusType;
signal exptBus : ExptBusType := EXPT_BUS_INIT_C;
signal txPhyClk : sl;
signal txPhyRst : sl;
-- Trigger and Sync Port
signal trigOut : slv(11 downto 0);
-- Misc.
signal cardRst : sl;
signal ledRedL : sl;
signal ledGreenL : sl;
signal ledBlueL : sl;
constant STROBE_INTERVAL_C : integer := 10;
constant MY_CHANNEL_CONFIG_INIT_C : EvrV2ChannelConfig := (
enabled => '1', rateSel => "00" & "0000000" & x"0", destSel => "010" & x"0000",
bsaEnabled => '0', bsaActiveSetup => (others=>'0'), bsaActiveDelay => (others=>'0'), bsaActiveWidth => (others=>'0'),
dmaEnabled => '1' );
constant MY_TRIGGER_CONFIG_INIT_C : EvrV2TriggerConfigType := (
enabled => '1', polarity => '1', delay => x"0007590", width => x"0000080", channel => (others=>'0') );
signal channelConfig : EvrV2ChannelConfigArray(ReadoutChannels-1 downto 0) := (others=>MY_CHANNEL_CONFIG_INIT_C);
signal channelConfigS : EvrV2ChannelConfigArray(ReadoutChannels-1 downto 0) := (others=>MY_CHANNEL_CONFIG_INIT_C);
signal triggerConfig : EvrV2TriggerConfigArray(TriggerOutputs-1 downto 0) := (others=>MY_TRIGGER_CONFIG_INIT_C);
signal triggerConfigS : EvrV2TriggerConfigArray(TriggerOutputs-1 downto 0) := (others=>MY_TRIGGER_CONFIG_INIT_C);
signal rStrobe : slv(ReadoutChannels*STROBE_INTERVAL_C downto 0) := (others=>'0');
signal timingMsg : TimingMessageType := TIMING_MESSAGE_INIT_C;
signal eventSel : slv(ReadoutChannels-1 downto 0) := (others=>'0');
signal dmaControl : EvrV2DmaControlArray(ReadoutChannels+1 downto 0) := (others=>EVRV2_DMA_CONTROL_INIT_C);
signal dmaData : EvrV2DmaDataArray(ReadoutChannels+1 downto 0);
constant SAXIS_MASTER_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(4);
signal dmaMaster : AxiStreamMasterType;
signal dmaSlave : AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C;
signal bsaEnabled : slv(ReadoutChannels-1 downto 0);
signal anyBsaEnabled : sl;
signal dmaFullThr : Slv24Array (0 downto 0) := (others=>x"000000");
signal dmaFullThrS : Slv24Array (0 downto 0) := (others=>x"000000");
begin -- rtl
txPhyClk <= evrClk;
txPhyRst <= evrRst;
cardRst <= '0';
process is
begin
evrClk <= '1';
wait for 2.7 ns;
evrClk <= '0';
wait for 2.7 ns;
end process;
process is
begin
evrRst <= '1';
wait for 20 ns;
evrRst <= '0';
wait for 300 us;
for i in 0 to ReadoutChannels-1 loop
channelConfig(i).enabled <= '0';
wait for 3 us;
end loop;
wait;
end process;
xpm : block
type RegType is record
advance : sl;
count : slv( 7 downto 0);
addrStrobe : slv( 1 downto 0);
partStrobe : slv(15 downto 0);
partIndex : slv( 3 downto 0);
tbus : TimingBusType;
shift : slv(TIMING_MESSAGE_BITS_C-1 downto 0);
end record;
constant REG_INIT_C : RegType := (
advance => '0',
count => (others=>'0'),
addrStrobe => "00",
partStrobe => (others=>'0'),
partIndex => (others=>'0'),
tbus => TIMING_BUS_INIT_C,
shift => (others=>'0') );
signal recTimingClk : sl;
signal recTimingRst : sl;
signal tpgConfig : TPGConfigType := TPG_CONFIG_INIT_C;
signal xData : TimingRxType := TIMING_RX_INIT_C;
signal fiducial : sl;
signal streams : TimingSerialArray(0 downto 0);
signal streamIds : Slv4Array (0 downto 0) := (others=>TIMING_STREAM_ID);
signal advance : slv (0 downto 0);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal data : TimingRxType := TIMING_RX_INIT_C;
begin
evrBus <= r.tbus;
recTimingClk <= evrClk;
recTimingRst <= evrRst;
U_TPG : entity lcls_timing_core.TPGMini
port map ( txClk => recTimingClk,
txRst => recTimingRst,
txRdy => '1',
txData => data.data,
txDataK => data.dataK,
statusO => open,
configI => tpgConfig );
TimingDeserializer_1 : entity lcls_timing_core.TimingDeserializer
generic map ( STREAMS_C => 1 )
port map ( clk => recTimingClk,
rst => recTimingRst,
fiducial => fiducial,
streams => streams,
streamIds => streamIds,
advance => advance,
data => data );
-- This is the serial to parallel part
comb: process (r, advance, streams, fiducial) is
variable v : RegType;
begin
v := r;
v.advance := advance(0);
v.tbus.strobe := '0';
if advance(0)='1' then
v.shift := streams(0).data & r.shift(r.shift'left downto 16);
end if;
if (fiducial='1') then
v.tbus.strobe := '1';
v.tbus.valid := streams(0).ready;
v.tbus.message := toTimingMessageType(r.shift(TIMING_MESSAGE_BITS_C-1 downto 0));
end if;
rin <= v;
end process comb;
seq: process (recTimingClk) is
begin
if rising_edge(recTimingClk) then
r <= rin;
end if;
end process seq;
end block;
-- Undefined signals
ledRedL <= '1';
ledGreenL <= '1';
ledBlueL <= '1';
U_Dma : entity work.EvrV2Dma
generic map ( CHANNELS_C => ReadoutChannels+2,
AXIS_CONFIG_C => SAXIS_MASTER_CONFIG_C )
port map ( clk => evrClk,
dmaCntl => dmaControl,
dmaData => dmaData,
dmaMaster => dmaMaster,
dmaSlave => dmaSlave );
U_BsaControl : entity work.EvrV2BsaControl
generic map ( TPD_G => TPD_G )
port map ( evrClk => evrClk,
evrRst => evrRst,
enable => anyBsaEnabled,
strobeIn => evrBus.strobe,
dataIn => evrBus.message,
dmaCntl => dmaControl (ReadoutChannels),
dmaData => dmaData (ReadoutChannels) );
Loop_BsaCh: for i in 0 to ReadoutChannels-1 generate
U_EventSel : entity lcls_timing_core.EvrV2EventSelect
generic map ( TPD_G => TPD_G )
port map ( clk => evrClk,
rst => evrRst,
config => channelConfigS(i),
strobeIn => rStrobe(i*STROBE_INTERVAL_C),
dataIn => timingMsg,
exptIn => exptBus,
selectOut => eventSel(i) );
U_BsaChannel : entity work.EvrV2BsaChannel
generic map ( TPD_G => TPD_G )
port map ( evrClk => evrClk,
evrRst => evrRst,
channelConfig => channelConfigS(i),
evtSelect => eventSel(i),
strobeIn => rStrobe(i*STROBE_INTERVAL_C+1),
dataIn => timingMsg,
dmaCntl => dmaControl(i),
dmaData => dmaData(i) );
end generate; -- i
U_EventDma : entity work.EvrV2EventDma
generic map ( TPD_G => TPD_G,
CHANNELS_C => ReadoutChannels )
port map ( clk => evrClk,
rst => evrBus.strobe,
strobe => rStrobe(ReadoutChannels*STROBE_INTERVAL_C),
eventSel => eventSel,
eventData => timingMsg,
dmaCntl => dmaControl(ReadoutChannels+1),
dmaData => dmaData (ReadoutChannels+1) );
process (evrClk)
begin -- process
if rising_edge(evrClk) then
rStrobe <= rStrobe(rStrobe'left-1 downto 0) & evrBus.strobe;
if evrBus.strobe='1' then
timingMsg <= evrBus.message;
end if;
end if;
end process;
Out_Trigger: for i in 0 to TriggerOutputs-1 generate
U_Trig : entity lcls_timing_core.EvrV2Trigger
generic map ( TPD_G => TPD_G,
CHANNELS_C => ReadoutChannels,
--DEBUG_C => (i<1) )
DEBUG_C => false )
port map ( clk => evrClk,
rst => evrRst,
config => triggerConfigS(i),
arm => eventSel,
fire => evrBus.strobe,
trigstate=> trigOut(i) );
end generate Out_Trigger;
anyBsaEnabled <= uOr(bsaEnabled);
-- Synchronize configurations to evrClk
Sync_Channel: for i in 0 to ReadoutChannels-1 generate
U_SyncRate : entity surf.SynchronizerVector
generic map ( TPD_G => TPD_G,
WIDTH_G => channelConfig (i).rateSel'length)
port map ( clk => evrClk,
rst => evrRst,
dataIn => channelConfig (i).rateSel,
dataOut => channelConfigS(i).rateSel );
U_SyncDest : entity surf.SynchronizerVector
generic map ( TPD_G => TPD_G,
WIDTH_G => channelConfig (i).destSel'length)
port map ( clk => evrClk,
rst => evrRst,
dataIn => channelConfig (i).destSel,
dataOut => channelConfigS(i).destSel );
Sync_Enable : entity surf.Synchronizer
generic map ( TPD_G => TPD_G )
port map ( clk => evrClk,
rst => evrRst,
dataIn => channelConfig (i).enabled,
dataOut => channelConfigS(i).enabled );
Sync_dmaEnable : entity surf.Synchronizer
generic map ( TPD_G => TPD_G )
port map ( clk => evrClk,
rst => evrRst,
dataIn => channelConfig (i).dmaEnabled,
dataOut => channelConfigS(i).dmaEnabled );
Sync_bsaEnable : entity surf.Synchronizer
generic map ( TPD_G => TPD_G )
port map ( clk => evrClk,
rst => evrRst,
dataIn => channelConfig (i).bsaEnabled,
dataOut => bsaEnabled(i) );
channelConfigS(i).bsaEnabled <= bsaEnabled(i);
Sync_Setup : entity surf.SynchronizerVector
generic map ( TPD_G => TPD_G,
WIDTH_G => channelConfig (i).bsaActiveSetup'length)
port map ( clk => evrClk,
rst => evrRst,
dataIn => channelConfig (i).bsaActiveSetup,
dataOut => channelConfigS(i).bsaActiveSetup );
Sync_Delay : entity surf.SynchronizerVector
generic map ( TPD_G => TPD_G,
WIDTH_G => channelConfig (i).bsaActiveDelay'length)
port map ( clk => evrClk,
rst => evrRst,
dataIn => channelConfig (i).bsaActiveDelay,
dataOut => channelConfigS(i).bsaActiveDelay );
Sync_Width : entity surf.SynchronizerVector
generic map ( TPD_G => TPD_G,
WIDTH_G => channelConfig (i).bsaActiveWidth'length)
port map ( clk => evrClk,
rst => evrRst,
dataIn => channelConfig (i).bsaActiveWidth,
dataOut => channelConfigS(i).bsaActiveWidth );
end generate Sync_Channel;
Sync_Trigger: for i in 0 to TriggerOutputs-1 generate
Sync_Enable : entity surf.Synchronizer
generic map ( TPD_G => TPD_G )
port map ( clk => evrClk,
rst => evrRst,
dataIn => triggerConfig (i).enabled,
dataOut => triggerConfigS(i).enabled );
Sync_Polarity : entity surf.Synchronizer
generic map ( TPD_G => TPD_G )
port map ( clk => evrClk,
rst => evrRst,
dataIn => triggerConfig (i).polarity,
dataOut => triggerConfigS(i).polarity );
Sync_Channel : entity surf.SynchronizerVector
generic map ( TPD_G => TPD_G,
WIDTH_G => triggerConfig (i).channel'length)
port map ( clk => evrClk,
rst => evrRst,
dataIn => triggerConfig (i).channel,
dataOut => triggerConfigS(i).channel );
U_SyncDelay : entity surf.SynchronizerVector
generic map ( TPD_G => TPD_G,
WIDTH_G => triggerConfig (i).delay'length)
port map ( clk => evrClk,
rst => evrRst,
dataIn => triggerConfig (i).delay,
dataOut => triggerConfigS(i).delay );
U_SyncWidth : entity surf.SynchronizerVector
generic map ( TPD_G => TPD_G,
WIDTH_G => triggerConfig (i).width'length)
port map ( clk => evrClk,
rst => evrRst,
dataIn => triggerConfig (i).width,
dataOut => triggerConfigS(i).width );
end generate Sync_Trigger;
Sync_dmaFullThr : entity surf.SynchronizerVector
generic map ( TPD_G => TPD_G,
WIDTH_G => 24 )
port map ( clk => evrClk,
rst => evrRst,
dataIn => dmaFullThr (0),
dataOut => dmaFullThrS(0) );
end mapping;
|
<gh_stars>100-1000
-- The Potato Processor - A simple processor for FPGAs
-- (c) <NAME> 2014 - 2015 <<EMAIL>>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_soc_memory is
end entity tb_soc_memory;
architecture testbench of tb_soc_memory is
-- Clock signal:
signal clk : std_logic;
constant clk_period : time := 10 ns;
-- Reset signal:
signal reset : std_logic := '1';
-- Wishbone signals:
signal wb_adr_in : std_logic_vector(31 downto 0);
signal wb_dat_in : std_logic_vector(31 downto 0);
signal wb_dat_out : std_logic_vector(31 downto 0);
signal wb_cyc_in : std_logic := '0';
signal wb_stb_in : std_logic := '0';
signal wb_sel_in : std_logic_vector(3 downto 0) := (others => '1');
signal wb_we_in : std_logic := '0';
signal wb_ack_out : std_logic;
begin
uut: entity work.pp_soc_memory
port map(
clk => clk,
reset => reset,
wb_adr_in => wb_adr_in,
wb_dat_in => wb_dat_in,
wb_dat_out => wb_dat_out,
wb_cyc_in => wb_cyc_in,
wb_stb_in => wb_stb_in,
wb_sel_in => wb_sel_in,
wb_we_in => wb_we_in,
wb_ack_out => wb_ack_out
);
clock: process
begin
clk <= '1';
wait for clk_period / 2;
clk <= '0';
wait for clk_period / 2;
end process clock;
stimulus: process
begin
wait for clk_period;
reset <= '0';
-- Write 32 bit of data to address 0:
wb_adr_in <= x"00000000";
wb_dat_in <= x"deadbeef";
wb_cyc_in <= '1';
wb_stb_in <= '1';
wb_we_in <= '1';
wait for clk_period;
wb_stb_in <= '0';
wb_cyc_in <= '0';
wait for clk_period;
-- Write a block write of two 32-bit words at address 0 and 1:
wb_adr_in <= x"00000000";
wb_dat_in <= x"feedbeef";
wb_cyc_in <= '1';
wb_stb_in <= '1';
wait for clk_period;
wb_stb_in <= '0';
wb_adr_in <= x"00000004";
wb_dat_in <= x"f00dd00d";
wait for clk_period;
wb_stb_in <= '1';
wait for clk_period;
wb_stb_in <= '0';
wb_cyc_in <= '0';
-- Read address 4:
wait for clk_period;
wb_we_in <= '0';
wb_adr_in <= x"00000000";
wb_cyc_in <= '1';
wb_stb_in <= '1';
wait for clk_period;
-- TODO: Make this testbench automatic.
wait;
end process stimulus;
end architecture testbench;
|
library verilog;
use verilog.vl_types.all;
entity test_vlg_vec_tst is
end test_vlg_vec_tst;
|
<reponame>rubinektomas/Digital-electronics-1
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17.03.2021 10:51:11
-- Design Name:
-- Module Name: tb_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_top is
-- Port ( );
end tb_top;
architecture Behavioral of tb_top is
constant c_CLK_100MHZ_PERIOD : time := 10 ns;
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_data0 : std_logic_vector(4 - 1 downto 0);
signal s_data1 : std_logic_vector(4 - 1 downto 0);
signal s_data2 : std_logic_vector(4 - 1 downto 0);
signal s_data3 : std_logic_vector(4 - 1 downto 0);
signal s_dpi : std_logic_vector(4 - 1 downto 0);
signal s_seg : std_logic_vector(7 - 1 downto 0);
signal s_digo : std_logic_vector(4 - 1 downto 0);
signal s_dpo : std_logic;
begin
uut_top : entity work.top
port map(
CLK100MHZ => s_clk,
BTNC => s_reset,
SW(4-1 downto 0) => s_data0,
SW(8-1 downto 4) => s_data1,
SW(12-1 downto 8) => s_data2,
SW(16-1 downto 12) => s_data3,
CA => s_seg(0),
CB => s_seg(1),
CC => s_seg(2),
CD => s_seg(3),
CE => s_seg(4),
CF => s_seg(5),
CG => s_seg(6),
DP => s_dpo,
AN => s_digo
);
p_clk_gen : process
begin
while now < 750 ns loop -- 75 periods of 100MHz clock
s_clk <= '0';
wait for c_CLK_100MHZ_PERIOD / 2;
s_clk <= '1';
wait for c_CLK_100MHZ_PERIOD / 2;
end loop;
wait;
end process p_clk_gen;
end Behavioral;
|
<filename>project_8_randomsequenceVHDL/project_8_randomsequenceVHDL.srcs/sources_1/imports/mcc-simulator/multiplexer.vhd
----------------------------------------------------------------------------------
-- Company: CERN
-- Engineer: <NAME>, <NAME>
--
-- Create Date: 17:31:33 09/17/2007
-- Design Name:
-- Module Name: multiplexer - Behavioral
-- Project Name: ATLAS Pixel Simulator
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplexer is
port (
enable : in STD_LOGIC; -- simulation enabled(1) or disabled(0)
formatter_mode : in STD_LOGIC_VECTOR (1 downto 0); -- fowmatter mode 40 Mbit/s(00/11), 80 Mbit/s(01) or 160 Mbit/s(10)
multi_simulators : in STD_LOGIC; -- multi simulator use enabled(1) or disabled(0)
inlink_0 : in STD_LOGIC_VECTOR (3 downto 0); -- inputs, not simulated/real data, from BOC
inlink_1 : in STD_LOGIC_VECTOR (3 downto 0); -- inputs, simulated, from simulator 1
inlink_2 : in STD_LOGIC_VECTOR (3 downto 0); -- inputs, simulated, from simulator 2, not used in 160 Mbit/s mode
inlink_3 : in STD_LOGIC_VECTOR (3 downto 0); -- inputs, simulated, from simulator 3, not used in 80 & 160 Mbit/s modes
inlink_4 : in STD_LOGIC_VECTOR (3 downto 0); -- inputs, simulated, from simulator 4, not used in 80 & 160 Mbit/s modes
outlink : out STD_LOGIC_VECTOR (3 downto 0) -- outputs, to formatter
);
end multiplexer;
architecture Behavioral of multiplexer is
begin
output_mux : process (
enable,
formatter_mode,
multi_simulators,
inlink_0,
inlink_1,
inlink_2,
inlink_3,
inlink_4
)
begin
if (enable = '0') then -- real data case
outlink <= inlink_0;
else
case formatter_mode is
when "01" => -- 80 Mbit/s simulated case
if (multi_simulators = '0') then -- single simulator case
outlink(0) <= inlink_1(0);
outlink(1) <= inlink_1(1);
outlink(2) <= inlink_1(0);
outlink(3) <= inlink_1(1);
else -- multiple simulators case
outlink(0) <= inlink_1(0);
outlink(1) <= inlink_1(1);
outlink(2) <= inlink_2(0);
outlink(3) <= inlink_2(1);
end if;
when "10" => -- 160 Mbit/s simulated case, only one simulator possible
outlink(0) <= inlink_1(0);
outlink(1) <= inlink_1(1);
outlink(2) <= inlink_1(2);
outlink(3) <= inlink_1(3);
when others => -- 40 Mbit/s simulated case
if (multi_simulators = '0') then -- single simulator case
outlink(0) <= inlink_1(0);
outlink(1) <= inlink_1(0);
outlink(2) <= inlink_1(0);
outlink(3) <= inlink_1(0);
else -- multiple simulators case
outlink(0) <= inlink_1(0);
outlink(1) <= inlink_2(0);
outlink(2) <= inlink_3(0);
outlink(3) <= inlink_4(0);
end if;
end case;
end if;
end process;
end Behavioral;
|
<filename>PROCESSOR_6_BITS_FINAL/TB_2.vhd
-- Vhdl test bench created from schematic C:\Users\<NAME>\Documents\FINAL LAB RESOUSES\New folder (3)\PROCESSOR_6_BITS_FINAL\AU_6BITS.sch - Fri Dec 09 23:09:14 2016
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY AU_6BITS_AU_6BITS_sch_tb IS
END AU_6BITS_AU_6BITS_sch_tb;
ARCHITECTURE behavioral OF AU_6BITS_AU_6BITS_sch_tb IS
COMPONENT AU_6BITS
PORT( ADD_SUB : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
Z_OUT : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
C_OUT : OUT STD_LOGIC);
END COMPONENT;
SIGNAL ADD_SUB : STD_LOGIC;
SIGNAL A : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL S : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL B : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL Z_OUT : STD_LOGIC;
SIGNAL OVERFLOW : STD_LOGIC;
SIGNAL C_OUT : STD_LOGIC;
BEGIN
UUT: AU_6BITS PORT MAP(
ADD_SUB => ADD_SUB,
A => A,
S => S,
B => B,
Z_OUT => Z_OUT,
OVERFLOW => OVERFLOW,
C_OUT => C_OUT
);
-- *** Test Bench - User Defined Section ***
tb : PROCESS
BEGIN
A(0)<='0';
A(1)<='0';
A(2)<='0';
A(3)<='0';
A(4)<='1';
A(5)<='0';
B(0)<='0';
B(1)<='0';
B(2)<='0';
B(3)<='0';
B(4)<='1';
B(5)<='0';
ADD_SUB<='0';
WAIT FOR 2 NS;
ADD_SUB<='1';
WAIT FOR 2 NS;
WAIT; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;
|
<reponame>jake-billings/PYNQ-DL<filename>darius/ip/cnn_dataflow_2.0/datamover/lib_fifo_v1_0_rfs.vhd
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`protect end_protected
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all ;
entity down_count is
generic ( modulus : integer ); -- for example 11
port (
Clock : in std_logic;
EC : in std_logic;
LC : in std_logic;
Count : out integer
);
end down_count;
architecture Behavioral of down_count is
signal count_signal : integer ;
begin
process(clock, EC)
begin
if EC = '0' then
count_signal <= modulus - 1;
elsif rising_edge(clock) then
-- if LC = '1' then
-- count_signal <= modulus - 1;
if LC = '1' then -- EC = '0' reset!
count_signal <= modulus - 1;
else
count_signal <= count_signal - 1;
end if;
end if;
end process;
count <= count_signal;
end Behavioral;
|
<filename>hdl/can/sim/can_wb_tb.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity can_wb_tb is
end can_wb_tb;
architecture behavior of can_wb_tb is
signal test_running : std_logic := '1';
signal clk : std_logic;
signal can0_phy_tx : std_logic;
signal can0_phy_tx_en : std_logic;
signal can0_phy_rx : std_logic;
constant clk_period : time := 10 ns;
signal wishbone_in : std_logic_vector (100 downto 0) := (others => '0');
signal wishbone_out : std_logic_vector (100 downto 0) := (others => '0');
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(31 downto 0); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing. - Don't touch.
wishbone_in(61) <= wb_clk_i; -- clock
wishbone_in(60) <= wb_rst_i; -- reset signal
wishbone_in(59 downto 28) <= wb_dat_i ;-- the date the master wishes to write
wishbone_in(27 downto 3) <= wb_adr_i(24 downto 0); -- contains the address of the request
wishbone_in(2) <= wb_we_i; -- true for any write requests
wishbone_in(1) <= wb_cyc_i; -- is true any time a wishbone transaction is taking place
wishbone_in(0) <= wb_stb_i; -- is true for any bus transaction request.
wb_dat_o <= wishbone_out(33 downto 2);
wb_ack_o <= wishbone_out(1);
wb_inta_o <= wishbone_out(0);
-- End unpacking Wishbone signals
-- Unpack the wishbone array into signals so the modules code is not confusing. - Don't touch.
-- End unpacking Wishbone signals
uut0: entity work.can_wb port map(
wishbone_in => wishbone_in,
wishbone_out => wishbone_out,
tx => can0_phy_tx,
tx_en => can0_phy_tx_en,
rx => can0_phy_rx
);
clk_process : process
begin
clk <= '0';
wb_clk_i <= '0';
wait for clk_period/2;
clk <= '1';
wb_clk_i <= '1';
wait for clk_period/2;
if test_running = '0' then
wait;
end if;
end process;
can0_test : process
begin
wait for clk_period * 40;
wait until rising_edge(clk);
wait until falling_edge(clk);
-- try to get the version
wb_cyc_i <= '1';
wb_stb_i <= '1';
wb_we_i <= '0';
wb_adr_i <= (31 downto 8 =>'0' ) & x"00";
wait until rising_edge(clk);
wait until falling_edge(clk);
wb_cyc_i <= '0';
--can0_version
assert wb_dat_o = x"13371337" report "DATA unexpected version " & to_hstring(wb_dat_o) severity failure;
-- try to get the initial config
wb_adr_i <= (31 downto 8 =>'0' ) & x"02";
wb_cyc_i <= '1';
wb_stb_i <= '1';
wb_we_i <= '0';
wait until rising_edge(clk);
wait until falling_edge(clk);
wb_cyc_i <= '0';
assert wb_dat_o = x"00000000" report "Config test expected empty but got " & to_hstring(wb_dat_o) severity failure;
wait until rising_edge(clk);
wait until falling_edge(clk);
-- write config
wb_adr_i <= (31 downto 8 =>'0' ) & x"02";
wb_dat_i <= x"00000001";
wb_cyc_i <= '1';
wb_stb_i <= '1';
wb_we_i <= '1';
wait until rising_edge(clk);
wait until falling_edge(clk);
wb_cyc_i <= '0';
-- read back now (and expect 1 as value)
wb_adr_i <= (31 downto 8 =>'0' ) & x"02";
wb_cyc_i <= '1';
wb_stb_i <= '1';
wb_we_i <= '0';
wait until rising_edge(clk);
wait until falling_edge(clk);
wb_cyc_i <= '0';
assert wb_dat_o = x"00000001" report "Config test expected 1 but got " & to_hstring(wb_dat_o) severity failure;
-- try to get the version
wb_adr_i <= (31 downto 8 =>'0' ) & x"00";
wb_cyc_i <= '1';
wb_stb_i <= '1';
wb_we_i <= '0';
wait until rising_edge(clk);
wait until falling_edge(clk);
wb_cyc_i <= '0';
--can0_version
assert wb_dat_o = x"13371337" report "DATA unexpected version " & to_hstring(wb_dat_o) severity failure;
test_running <= '0';
report "DONE";
wait;
--set sample rate
end process;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_Binarization_example is
end entity;
architecture rtl of tb_Binarization_example is
component tb_Binarization
end component;
begin
tb_Binarization_instance :
component tb_Binarization
port map();
end architecture rtl;
|
<reponame>Muhanad23/PDP-11-processor
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE ieee.numeric_std.ALL;
ENTITY M_INS_DEC IS
PORT(IR,FR: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
FLAG_OUT: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
CLK,RESET:IN STD_LOGIC;
OUTPUT: INOUT STD_LOGIC_VECTOR(28 DOWNTO 0));
END ENTITY;
ARCHITECTURE M_INS OF M_INS_DEC IS
COMPONENT CONTROL_UNIT IS
PORT(IR,FR: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
FLAG_OUT: OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
CLK,RESET:IN STD_LOGIC;
MICRO_IR:INOUT STD_LOGIC_VECTOR(17 DOWNTO 0);
M_AR_IN,M_AR_OUT: OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
END COMPONENT;
COMPONENT TRANSPARENT_REG IS
GENERIC (N : INTEGER := 5);
PORT (D: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
RST,CLK: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0));
END COMPONENT;
COMPONENT DECODER IS
GENERIC(N: INTEGER := 3);
PORT (S: IN INTEGER RANGE 0 TO 2**N-1;
O: OUT STD_LOGIC_VECTOR(2**N-1 DOWNTO 0));
END COMPONENT;
SIGNAL MIR_IN,MIR_OUT: STD_LOGIC_VECTOR(17 DOWNTO 0);
SIGNAL F1,F2,F3,F4,F5: INTEGER range 0 to 31;
SIGNAL MICRO_AR_IN,MICRO_AR_OUT: STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
F1<=TO_INTEGER(UNSIGNED(MIR_OUT(12 DOWNTO 10)));
F2<=TO_INTEGER(UNSIGNED(MIR_OUT(9 DOWNTO 8)));
F3<=TO_INTEGER(UNSIGNED(MIR_OUT(7 DOWNTO 6)));
F4<=TO_INTEGER(UNSIGNED(MIR_OUT(5 DOWNTO 3)));
F5<=TO_INTEGER(UNSIGNED(MIR_OUT(2 DOWNTO 1)));
U0: CONTROL_UNIT PORT MAP(IR,FR,FLAG_OUT,CLK,RESET,MIR_IN,MICRO_AR_IN,MICRO_AR_OUT);
U2: TRANSPARENT_REG GENERIC MAP(18)
PORT MAP(MIR_IN,RESET,CLK,MIR_OUT);
FF1: DECODER GENERIC MAP(3)
PORT MAP(F1,OUTPUT(28 DOWNTO 21));
FF2: DECODER GENERIC MAP(2)
PORT MAP(F2,OUTPUT(20 DOWNTO 17));
FF3: DECODER GENERIC MAP(2)
PORT MAP(F3,OUTPUT(16 DOWNTO 13));
FF4: DECODER GENERIC MAP(3)
PORT MAP(F4,OUTPUT(12 DOWNTO 5));
FF5: DECODER GENERIC MAP(2)
PORT MAP(F5,OUTPUT(4 DOWNTO 1));
FF6: OUTPUT(0)<=MIR_OUT(0);
END ARCHITECTURE;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity rotator_3d_tb is
end entity rotator_3d_tb;
architecture rotator_3d_tb_arq of rotator_3d_tb is
constant N_TB : natural := 16;
signal clk_aux : std_logic := '0';
signal rst_aux : std_logic := '1';
signal start_aux : std_logic := '1';
signal done_aux : std_logic;
-- x: 1
signal x_in_aux : std_logic_vector(N_TB - 1 downto 0) := std_logic_vector(to_unsigned(16384, N_TB));
-- y: 0
signal y_in_aux : std_logic_vector(N_TB - 1 downto 0) := std_logic_vector(to_unsigned(0, N_TB));
-- z: 0
signal z_in_aux : std_logic_vector(N_TB - 1 downto 0) := std_logic_vector(to_unsigned(0, N_TB));
-- ang: 10
signal alpha_aux : std_logic_vector(N_TB downto 0) := std_logic_vector(to_unsigned(3641, N_TB + 1));
-- ang: 10
signal beta_aux : std_logic_vector(N_TB downto 0) := std_logic_vector(to_unsigned(3641, N_TB + 1));
-- ang: 10
signal gamma_aux : std_logic_vector(N_TB downto 0) := std_logic_vector(to_unsigned(3641, N_TB + 1));
signal x_out_aux : std_logic_vector(N_TB - 1 downto 0);
signal y_out_aux : std_logic_vector(N_TB - 1 downto 0);
signal z_out_aux : std_logic_vector(N_TB - 1 downto 0);
begin
rst_aux <= '0' after 10 ns;
start_aux <= '0' after 40 ns;
clk_aux <= not clk_aux after 20 ns;
DUT: entity work.rotator_3d
port map (
clk => clk_aux,
rst => rst_aux,
start => start_aux,
x_in => x_in_aux,
y_in => y_in_aux,
z_in => z_in_aux,
alpha => alpha_aux,
beta => beta_aux,
gamma => gamma_aux,
x_out => x_out_aux,
y_out => y_out_aux,
z_out => z_out_aux,
done => done_aux
);
end architecture rotator_3d_tb_arq;
|
<gh_stars>1-10
-- This Source Code Form is subject to the terms of the Mozilla Public
-- License, v. 2.0. If a copy of the MPL was not distributed with this file,
-- You can obtain one at http://mozilla.org/MPL/2.0/.
--
-- Copyright (c) 2014-2015, <NAME> <EMAIL>
library vunit_lib;
use vunit_lib.run_pkg.all;
use vunit_lib.run_base_pkg.all;
use vunit_lib.run_types_pkg.all;
use vunit_lib.check_pkg.all;
use vunit_lib.log_types_pkg.all;
use vunit_lib.path.all;
entity tb_path is
generic (
runner_cfg : runner_cfg_t := runner_cfg_default);
end entity tb_path;
architecture test_fixture of tb_path is
begin
test_runner: process is
procedure check_equal (
constant got : in string;
constant expected : in string) is
begin
check(got = expected, "Expected """ & expected & """ but got """ & got & """.");
end procedure check_equal;
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("Verify that joining a single path returns that path") then
check_equal(join("some_path"), "some_path");
elsif run("Verify that joining an empty path with a second path returns the second path") then
check_equal(join("", "some_path"), "some_path");
elsif run("Verify the joining of two paths") then
check_equal(join("foo", "bar"), "foo/bar");
elsif run("Verify that a separator ending the first path is ignored") then
check_equal(join("foo/", "bar"), "foo/bar");
end if;
end loop;
test_runner_cleanup(runner);
end process test_runner;
test_runner_watchdog(runner, 1 us);
end test_fixture;
|
-------------------------------------------------------------------------------
-- Company : SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
-- Description: Wrapper for Xilinx XPM FIFO module
-------------------------------------------------------------------------------
-- This file is part of 'SLAC Firmware Standard Library'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC Firmware Standard Library', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library surf;
use surf.StdRtlPkg.all;
library altera_mf;
use altera_mf_altera_mf_components.all;
entity FifoAlteraMf is
generic (
TPD_G : time := 1 ns;
RST_POLARITY_G : sl := '1'; -- '1' for active high rst, '0' for active low
FWFT_EN_G : boolean := false;
GEN_SYNC_FIFO_G : boolean := false;
MEMORY_TYPE_G : string := "auto";
SYNC_STAGES_G : positive := 3;
PIPE_STAGES_G : natural := 0;
DATA_WIDTH_G : positive := 18;
ADDR_WIDTH_G : positive := 10;
FULL_THRES_G : positive := 16;
EMPTY_THRES_G : positive := 16);
port (
-- Asynchronous Reset
rst : in sl;
-- Write Ports (wr_clk domain)
wr_clk : in sl;
wr_en : in sl;
din : in slv(DATA_WIDTH_G-1 downto 0);
wr_data_count : out slv(ADDR_WIDTH_G-1 downto 0);
wr_ack : out sl;
overflow : out sl;
prog_full : out sl;
almost_full : out sl;
full : out sl;
not_full : out sl;
-- Read Ports (rd_clk domain)
rd_clk : in sl;
rd_en : in sl;
dout : out slv(DATA_WIDTH_G-1 downto 0);
rd_data_count : out slv(ADDR_WIDTH_G-1 downto 0);
valid : out sl;
underflow : out sl;
prog_empty : out sl;
almost_empty : out sl;
empty : out sl);
end FifoAlteraMf;
architecture mapping of FifoAlteraMf is
constant FWFT_EN_C : string := ite(FWFT_EN_G, "ON", "OFF");
signal reset : sl;
signal sRdEn : sl;
signal sValid : sl;
signal dataOut : slv(DATA_WIDTH_G-1 downto 0);
signal fifoFull : sl;
signal fifoEmpty : sl;
signal wrCount : slv(ADDR_WIDTH_G-1 downto 0);
signal rdCount : slv(ADDR_WIDTH_G-1 downto 0);
begin
GEN_ASYNC : if (GEN_SYNC_FIFO_G = false) generate
U_dcfifo : dcfifo
generic map (
ram_block_type => MEMORY_TYPE_G,
lpm_numwords => (2**ADDR_WIDTH_G),
lpm_showahead => FWFT_EN_C,
lpm_type => "dcfifo",
lpm_width => DATA_WIDTH_G,
lpm_widthu => ADDR_WIDTH_G,
overflow_checking => "ON",
underflow_checking => "ON")
port map (
aclr => reset,
-- Write Ports
wrclk => wr_clk,
wrreq => wr_en,
data => din,
wrfull => fifoFull,
wrusedw => wrCount,
-- Read Ports
rdclk => rd_clk,
rdreq => sRdEn,
q => dout,
rdempty => fifoEmpty,
rdusedw => rdCount);
end generate;
GEN_SYNC : if (GEN_SYNC_FIFO_G = true) generate
U_scfifo : scfifo
generic map (
ram_block_type => MEMORY_TYPE_G,
lpm_numwords => (2**ADDR_WIDTH_G),
lpm_showahead => FWFT_EN_C,
lpm_type => "scfifo",
lpm_width => DATA_WIDTH_G,
lpm_widthu => ADDR_WIDTH_G,
overflow_checking => "ON",
underflow_checking => "ON")
port map (
sclr => reset,
aclr => '0',
clock => wr_clk,
-- Write Ports
wrreq => wr_en,
data => din,
full => fifoFull,
usedw => wrCount,
-- Read Ports
rdreq => sRdEn,
q => dout,
empty => fifoEmpty);
rdCount <= wrCount;
end generate;
reset <= rst when(RST_POLARITY_G = '1') else not(rst);
full <= fifoFull;
not_full <= not(fifoFull);
wr_ack <= wr_en and not fifoFull;
overflow <= wr_en and fifoFull;
wr_data_count <= wrCount;
rd_data_count <= rdCount;
process(fifoEmpty, fifoFull, rdCount, wrCount)
begin
--------------------------------------------
if fifoFull = '1' then
prog_full <= '1';
almost_full <= '1';
else
if wrCount >= FULL_THRES_G then
prog_full <= '1';
else
prog_full <= '0';
end if;
if wrCount >= ((2**ADDR_WIDTH_G)-2) then
almost_full <= '1';
else
almost_full <= '0';
end if;
end if;
--------------------------------------------
if fifoEmpty = '1' then
prog_empty <= '1';
almost_empty <= '1';
else
if rdCount <= EMPTY_THRES_G then
prog_empty <= '1';
else
prog_empty <= '0';
end if;
if rdCount <= 1 then
almost_empty <= '1';
else
almost_empty <= '0';
end if;
end if;
--------------------------------------------
end process;
empty <= fifoEmpty;
underflow <= sRdEn and fifoEmpty;
sValid <= not(fifoEmpty);
BYPASS_PIPE : if ((FWFT_EN_G = false) or (PIPE_STAGES_G = 0)) generate
sRdEn <= rd_en;
valid <= sValid;
dout <= dataOut;
end generate;
GEN_PIPE : if ((FWFT_EN_G = true) and (PIPE_STAGES_G /= 0)) generate
U_Pipeline : entity surf.FifoOutputPipeline
generic map (
TPD_G => TPD_G,
RST_POLARITY_G => RST_POLARITY_G,
RST_ASYNC_G => false,
DATA_WIDTH_G => DATA_WIDTH_G,
PIPE_STAGES_G => PIPE_STAGES_G)
port map (
-- Slave Port
sData => dataOut,
sValid => sValid,
sRdEn => sRdEn,
-- Master Port
mData => dout,
mValid => valid,
mRdEn => rd_en,
-- Clock and Reset
clk => rd_clk,
rst => rst);
end generate;
end mapping;
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Tue Oct 13 21:06:43 2020
-- Host : MACBOOK-CRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mult_gen_0_sim_netlist.vhdl
-- Design : mult_gen_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mult_gen_0,mult_gen_v12_0_16,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mult_gen_v12_0_16,Vivado 2019.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal \<const0>\ : STD_LOGIC;
signal \^a\ : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute x_interface_info : string;
attribute x_interface_info of A : signal is "xilinx.com:signal:data:1.0 a_intf DATA";
attribute x_interface_parameter : string;
attribute x_interface_parameter of A : signal is "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef";
attribute x_interface_info of P : signal is "xilinx.com:signal:data:1.0 p_intf DATA";
attribute x_interface_parameter of P : signal is "XIL_INTERFACENAME p_intf, LAYERED_METADATA undef";
begin
P(15 downto 2) <= \^a\(13 downto 0);
P(1) <= \<const0>\;
P(0) <= \<const0>\;
\^a\(13 downto 0) <= A(13 downto 0);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
end STRUCTURE;
|
-- Main file for running the CORDIC implementation optimised for hardware usage
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
-- All computations are handled in 2's complement fixed point using 1 sign bit, 1 integer bit and 14 fractional bits
-- A scaling factor of 2^14 is therefore used between the actual values and the internally handled values
entity cordic_area is
GENERIC(
ADDR_LENGTH : natural := 4;
DATA_WIDTH : natural := 16);
Port (
i_x : IN STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0):= (others => '0'); -- Input x
i_y : IN STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0):= (others => '0'); -- Input y
o_z : OUT STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0):= (others => '0'); -- Output z
i_enable_cordic : IN STD_LOGIC := '0';
o_done : OUT STD_LOGIC := '0' ;
clk_in : IN STD_LOGIC := '0';
state_LED : OUT STD_LOGIC_VECTOR(3 downto 0):=(others => '0');
LUT_TEST : OUT STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0):= (others => '0')
);
end cordic_area;
architecture behave of cordic_area is
------------- Control signals ----------
signal var_done : STD_LOGIC:= '0';
signal var_zero : STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0 ):= (others => '0');
signal var_debounce : STD_LOGIC:='0';
------------- \Control signals ----------
------------- Intermediate signales -------
signal r_xn : STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0):= (others => '0');
signal r_yn : STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0):= (others => '0');
signal r_zn : STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0):= (others => '0');
signal r_zd : STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0):= (others => '0');
------------- \Intermediate signales -------
-----------bit_shift signals--------
signal i_bitshift : STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0):= (others => '0');
signal o_bitshift : STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0);
signal c_shiftlength : STD_LOGIC_VECTOR((ADDR_LENGTH-1) downto 0):= (others => '0');
-----------/bit_shift signals--------
-----------sign_inverter signals--------
signal i_SI : STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0):= (others => '0');
signal o_SI : STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0);
signal i_SI_control : STD_LOGIC_VECTOR(1 downto 0) := "00";
-----------/sign_inverter signals--------
-----------LUT signals--------
signal i_LUT_addr : STD_LOGIC_VECTOR((ADDR_LENGTH-1) downto 0):= (others => '0');
signal i_mem_enable : STD_LOGIC:= '0';
signal o_LUT : STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0);
signal i_LUT_addr_X : STD_LOGIC_VECTOR((ADDR_LENGTH-1) downto 0):= (others => '0');
signal i_mem_enable_X : STD_LOGIC:= '0';
signal o_LUT_X : STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0);
signal i_LUT_addr_Y : STD_LOGIC_VECTOR((ADDR_LENGTH-1) downto 0):= (others => '0');
signal i_mem_enable_Y : STD_LOGIC:= '0';
signal o_LUT_Y : STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0);
signal LUT_COUNTER : integer:=0;
-----------/LUT signals--------
-----------signed_adder signals--------
signal i_adder_a : STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0):= (others => '0');
signal i_adder_b : STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0):= (others => '0');
signal o_adder : STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0);
-----------/signed_adder signals--------
--------Signals for iteration_counter---
signal clk : std_logic := '0';
signal o_iteration_count : integer range 0 to DATA_WIDTH-1 := 0;
signal i_reset : std_logic := '0';
signal i_enable : std_logic := '0';
-------/Signals for iteration_counter---
-------Signals for clock divider---
--Inputs
--signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal clock_out : std_logic;
-------/Signals for clock divider---
-------States---------
type state_type is (K1, K2, K3, K4, K5, idle, done);
signal state : state_type := idle;
-------/States---------
--------- Components-----------
COMPONENT Clock_Divider is
PORT(
clk : IN std_logic;
reset : IN std_logic;
clock_out : OUT std_logic
);
END COMPONENT Clock_Divider;
component bit_shift is
generic( DATA_WIDTH : natural;
ADDR_LENGTH : natural
);
Port ( i_bitshift : IN std_logic_vector((DATA_WIDTH-1) downto 0);
o_bitshift : OUT std_logic_vector((DATA_WIDTH-1) downto 0);
c_shiftlength : IN STD_LOGIC_VECTOR((ADDR_LENGTH-1) downto 0) -- 2^4 = 16, så man har mulighed for at bifshifte up til 16 gange
);
end component bit_shift;
component sign_inverter is
generic( DATA_WIDTH : natural
);
Port ( i_SI : IN STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0);
o_SI : OUT STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0);
i_SI_control : IN STD_LOGIC_VECTOR(1 downto 0)
);
end component sign_inverter;
component LUT_16 is
Port ( i_LUT_addr : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
i_mem_enable : IN STD_LOGIC;
o_LUT : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component LUT_16;
component LUT_X is
Port ( i_LUT_addr_X : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
i_mem_enable_X : IN STD_LOGIC;
o_LUT_X : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component LUT_X;
component LUT_Y is
Port ( i_LUT_addr_Y : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
i_mem_enable_Y : IN STD_LOGIC;
o_LUT_Y : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component LUT_Y;
component signed_adder is
generic( DATA_WIDTH : natural
);
port( i_adder_a : in STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0);
i_adder_b : in STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0);
o_adder : out STD_LOGIC_VECTOR((DATA_WIDTH-1) downto 0)
);
end component signed_adder;
component iteration_counter is
Port (
clk : in std_logic;
i_reset : in std_logic;
i_enable : in std_logic;
o_iteration_count : out integer range 0 to 31
);
end component iteration_counter;
component Debounce is
Port (
DATA : in std_logic;
CLK : in std_logic;
OP_DATA : out std_logic
);
end component Debounce;
--------- /Components----------
begin
----------- Map----------
-----------clock divider--------
clock_divider_x : Clock_Divider
port map (
clk => clk,
reset => reset,
clock_out => clock_out
);
-----------/clock divider--------
-----------bit_shift signals--------
bit_shift_INST : bit_shift
generic map (DATA_WIDTH => DATA_WIDTH,
ADDR_LENGTH => ADDR_LENGTH)
port map (
i_bitshift => i_bitshift,
o_bitshift => o_bitshift,
c_shiftlength => c_shiftlength
);
-----------/bit_shift signals--------
-----------sign_inverter signals--------
sign_inverter_INST : sign_inverter
generic map (DATA_WIDTH => DATA_WIDTH)
port map (
i_SI => i_SI,
o_SI => o_SI,
i_SI_control => i_SI_control
);
-----------/sign_inverter signals--------
-----------LUT signals--------
LUT_16_INST : LUT_16
port map (
i_LUT_addr => i_LUT_addr,
i_mem_enable => i_mem_enable,
o_LUT => o_LUT
);
LUT_X_INST : LUT_X
port map (
i_LUT_addr_X => i_LUT_addr_X,
i_mem_enable_X => i_mem_enable_X,
o_LUT_X => o_LUT_X
);
LUT_Y_INST : LUT_Y
port map (
i_LUT_addr_Y => i_LUT_addr_Y,
i_mem_enable_Y => i_mem_enable_Y,
o_LUT_Y => o_LUT_Y
);
-----------/LUT signals--------
-----------signed_adder signals--------
Adder_INST : signed_adder
generic map (DATA_WIDTH => DATA_WIDTH)
port map (
i_adder_a => i_adder_a,
i_adder_b => i_adder_b,
o_adder => o_adder
);
-----------/signed_adder signals--------
-----------Iteration counter--------
iteration_counter_INST : iteration_counter
port map (
clk => clock_out,
i_reset => i_reset,
i_enable => i_enable,
o_iteration_count => o_iteration_count
);
-----------\Iteration counter--------
----------- Debounce -----------
Debounce_INST : Debounce
port map (
DATA => i_enable_cordic,
CLK => clk,
OP_DATA => var_debounce);
----------- \Debounce ----------
-----------/Map----------
-- Process for calculating arctangent using CORDIC
process(clock_out) is
begin
if(rising_edge(clock_out)) then
case state is
when idle => -- This case is responsible for initializing the signals used
-------- SHOW STATES --------
state_LED(0) <= '1';
state_LED(1) <= '0';
state_LED(2) <= '0';
state_LED(3) <= '0';
-------- \SHOW STATES --------
------- LUT inputs ------
i_mem_enable_X <= '1'; -- Reads the current input from LUT X and Y
i_mem_enable_Y <= '1';
------- \LUT inputs ----------
---- Done ----
var_done <= '0'; -- Tells that the computation is not finished
---- \Done ----
----- Counter -----
i_reset <= '1'; -- Once this signal goes high, the iteration count is reset
----- \Counter -----
------ Next State -----
if var_debounce = '0' then -- Once this signal goes high, the CORDIC algorithm starts
state <= K1;
end if;
------ \Next State -----
------------ Assign --------
r_yn <= O_LUT_Y;
r_xn <= O_LUT_X;
r_zn <= var_zero;
------------ \Assign --------
when K1 =>
-------- SHOW STATES --------
state_LED(0) <= '0';
state_LED(1) <= '1';
state_LED(2) <= '0';
state_LED(3) <= '0';
-------- \SHOW STATES --------
----- LUT Output -----
LUT_TEST <= O_LUT_Y; -- Sends the current output of the LUT_Y to the LED's on the FPGA board
----- \LUT output -----
------- LUT inputs ------
i_mem_enable_X <= '0'; -- Reads the current input from LUT X and Y
i_mem_enable_Y <= '0';
------- \LUT inputs ----------
----- Counter -----
i_reset <= '0'; -- Set reset low so it can begin counting
----- \Counter -----
----- Next State ----
state <= K2; -- Next state
----- \Next State ----
------------ Bitshift --------
i_bitshift <= r_xn;
------------ \Bitshift --------
if o_iteration_count > 0 then
r_zn <= o_adder;
end if;
------------ -sign ------------
if r_yn = var_zero then
i_SI_control(1) <= '1'; -- If input is zero
else
i_SI_control(1) <= '0'; -- If input is not zero
end if;
i_SI_control(0) <= not r_yn(DATA_WIDTH-1); -- equal to the inverted sign bit.
------------ \-sign ------------
when K2 =>
----- Next State ----
state <= K3; -- Next state
----- \Next State ----
------------ Bitshift --------
i_bitshift <= r_yn;
------------ \Bitshift --------
------------ Simple Multiplier --------
i_SI <= o_bitshift; -- xb
----------- \Simple Multiplier --------
when K3 =>
----- Counter -----
i_enable <= '1'; -- Set high to count one up
----- \Counter -----
---- LUT -----
i_mem_enable <= '1'; -- Set high to get new values
---- \LUT ----
----- Next State ----
state <= K4; -- Next state
----- \Next State ----
------------ Adder -----------
i_adder_a <= r_yn;
i_adder_b <= o_SI; -- xb
------------ \Adder ----------
------------ Simple Multiplier --------
i_SI <= o_bitshift; -- yb
----------- \Simple Multiplier --------
when K4 =>
-------- SHOW STATES --------
state_LED(0) <= '0';
state_LED(1) <= '0';
state_LED(2) <= '0';
state_LED(3) <= '1';
-------- \SHOW STATES --------
----- Counter -----
i_enable <= '0'; -- Set low to be ready for next count.
----- \Counter -----
---- LUT -----
i_mem_enable <= '0'; -- Set low to be ready for next value
---- \LUT ----
----- Next State ----
state <= K5; -- Next state
----- \Next State ----
------------ Adder -----------
i_adder_a <= r_xn;
i_adder_b <= std_logic_vector(-signed(o_SI)); -- yb
r_yn <= o_adder;
------------ \Adder ----------
------------ Simple Multiplier --------
i_SI <= o_LUT;
----------- \Simple Multiplier --------
when K5 =>
----- Next State ----
if o_iteration_count = DATA_WIDTH - 1 then
state <= done; -- Next state done
else
state <= K1; -- Run another iteration
end if;
----- \Next State ----
------------ Adder -----------
i_adder_a <= r_zn;
i_adder_b <= std_logic_vector(-signed(o_SI)); -- zb
r_xn <= o_adder;
------------ \Adder ----------
when done => -- Go back to the setup state and wait for a new input
----- LUT Counter for inputs ----
if LUT_COUNTER > 15 then -- Make sure the LUT-address do not overflow
LUT_COUNTER <= 0;
else
LUT_COUNTER <= LUT_COUNTER+1;
end if;
----- \LUT Counter for inputs ----
----- Done ----
var_done <= '1'; -- Outputs a signal showing that the computations has finished
-- Also sets the final values to the output ports
----- \Done ----
----- Counter ----
i_reset <= '1'; -- Once this signal goes high, the iteration count is reset
----- \Coutner ----
------------ Assign --------
r_zd <= o_adder;
------------ \Assign -------
-------- SHOW STATES --------
state_LED(0) <= '0';
state_LED(1) <= '0';
state_LED(2) <= '1';
state_LED(3) <= '0';
-------- \SHOW STATES --------
---- Next State -----
state <= idle;
---- \Next State -----
when others => state <= idle;
end case;
end if;
end process;
------------ Bitshift --------
c_shiftlength <= std_logic_vector(to_unsigned(o_iteration_count,ADDR_LENGTH));
------------ \Bitshift -------
----- LUT ADDR -----
i_LUT_addr <= std_logic_vector(to_unsigned(o_iteration_count,ADDR_LENGTH));
----- \LUT ADDR ----
----------- INPUT LUTS -------
i_LUT_addr_X <= std_logic_vector(to_unsigned(LUT_COUNTER,ADDR_LENGTH));
i_LUT_addr_Y <= std_logic_vector(to_unsigned(LUT_COUNTER,ADDR_LENGTH));
----------- \INPUT LUTS -------
------------ Set the output ---------
o_z <= r_zd;
o_done <= var_done;
------------ \Set the output ---------
------------ Set the clock ---------
clk <= clk_in;
------------ \Set the clock ---------
end behave;
|
<reponame>kaircx/phoenix-firmware<filename>FPGA/App/controller/synthesis/submodules/FPSqrt/FPSqrt_safe_path.vhd
-- (C) 2001-2020 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files from any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License Subscription
-- Agreement, Intel FPGA IP License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Intel and sold by
-- Intel or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-- safe_path for FPSqrt given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE FPSqrt_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END FPSqrt_safe_path;
PACKAGE body FPSqrt_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END FPSqrt_safe_path;
|
-----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package user_types is
type slv_array is array (natural range <>) of std_logic_vector;
end package;
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: <NAME> A01203712
--
-- Create Date: 14:11:49 09/08/2015
-- Design Name:
-- Module Name: Priority_Encoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Priority Decoder using when
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Priority_Encoder is
Port ( input : in STD_LOGIC_VECTOR (6 downto 0);
output : out STD_LOGIC_VECTOR (2 downto 0));
end Priority_Encoder;
architecture Behavioral of Priority_Encoder is
begin
output <= "111" when input(6)='1' else
"110" when input(5)='1' else
"101" when input(4)='1' else
"100" when input(3)='1' else
"011" when input(2)='1' else
"010" when input(1)='1' else
"001" when input(0)='1' else
"000";
end Behavioral;
|
<reponame>oshears/Designing-a-Custom-AXI-Slave-Peripheral<filename>axi_rc_servo_controller_v2_00_a/axi_rc_servo_controller_v2_00_a.srcs/sim_1/imports/testbench_files/AXI_WRITE_DATA_CHANNEL_model.vhd<gh_stars>10-100
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AXI_WRITE_DATA_CHANNEL_model is
PORT
(
-- User signals
clk : in STD_LOGIC;
resetn : in STD_LOGIC;
data : in STD_LOGIC_VECTOR(31 downto 0);
go : in STD_LOGIC;
done : out STD_LOGIC;
-- AXI write data channel signals
WDATA : out STD_LOGIC_VECTOR(31 downto 0);
WSTRB : out STD_LOGIC_VECTOR(3 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC
);
end AXI_WRITE_DATA_CHANNEL_model;
architecture Behavioral of AXI_WRITE_DATA_CHANNEL_model is
type main_fsm_type is (reset, idle, running, complete);
signal current_state, next_state : main_fsm_type := reset;
signal output_data : std_logic;
begin
state_machine_update : process (clk)
begin
if clk'event and clk = '1' then
if resetn = '0' then
current_state <= reset;
else
current_state <= next_state;
end if;
end if;
end process;
WDATA <= data when output_data = '1' else X"00000000";
state_machine_decisions : process (current_state, WREADY, go)
begin
WSTRB <= "0000";
WVALID <= '0';
output_data <= '0';
done <= '0';
case current_state is
when reset =>
next_state <= idle;
when idle =>
next_state <= idle;
if go = '1' then
next_state <= running;
end if;
when running =>
output_data <= '1';
WSTRB <= "1111";
WVALID <= '1';
if WREADY = '1' then
next_state <= complete;
else
next_state <= running;
end if;
when complete =>
done <= '1';
if go = '0' then
next_state <= idle;
else
next_state <= complete;
end if;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity decode is
port (
clk: in std_logic;
rst: in std_logic;
-- Input for previous stages
fui: in fetch_output_type;
-- Output for next stages
duo: out decode_output_type;
busy: out std_logic;
freeze: in std_logic;
flush: in std_logic;
jump: in std_logic;
dual: out std_logic;
jumpmsb: in std_logic
);
end entity decode;
architecture behave of decode is
signal dr: decode_regs_type;
signal dec: opdec_type;
signal opcode_high: std_logic_vector(15 downto 0);
signal opcode_low: std_logic_vector(15 downto 0);
-- signal pc_lsb: boolean;
begin
opcode_high <= fui.opcode(31 downto 16) when fui.inverted='0' else fui.opcode(15 downto 0);
opcode_low <= fui.opcode(15 downto 0) when fui.inverted='0' else fui.opcode(31 downto 16);
duo.r <= dr;
opdecoder: entity work.opdec
port map (
opcode_high => opcode_high,
opcode_low => opcode_low,
priv => fui.r.priv,
dec => dec
);
process(fui, dr, clk, rst, dec, freeze, jump, jumpmsb, flush, opcode_high,opcode_low)
variable dw: decode_regs_type;
--variable op: decoded_opcode_type;
variable opc1,opc2: std_logic_vector(15 downto 0);
variable rd1,rd2: std_logic;
variable ra1,ra2: regaddress_type;
--variable src: sourcedest_type;
variable dreg0, dreg1: regaddress_type;
variable alu_op: alu_op_type;
variable imm16: std_logic_vector(15 downto 0);
variable imm8: std_logic_vector(7 downto 0);
variable imm_fill: std_logic_vector(31 downto 0);
variable sr: std_logic_vector(2 downto 0);
variable opcdelta: std_logic_vector(2 downto 0);
variable can_issue_both: boolean;
--variable is_pc_lsb: boolean;
variable reg_source0, reg_source1: reg_source_type;
variable regwe :std_logic;
variable sprwe: std_logic;
variable prepost: std_logic;
variable macc: memory_access_type;
variable memory_access: std_logic;
variable memory_write: std_logic;
variable modify_flags: boolean;
--variable compositeloadimm: compositeloadimmtype;
variable jump: std_logic_vector(1 downto 0);
variable condition_clause: condition_type;
variable alu2_imreg: std_logic;
variable alu2_samereg: std_logic;
--variable no_reg_conflict: boolean;
--variable flags_source: flagssource_type;
variable pc: word_type;
variable imflag: std_logic;
variable invert_alu: boolean;
variable except_return: boolean;
variable blocks1: std_logic;
variable blocks2: std_logic;
variable is_jump: boolean;
begin
dw := dr;
busy <= '0';
dual <= '0';
rd1 := '0';
rd2 := '0';
--can_issue_both := false;
modify_flags:=false;
jump := (others => 'X');
--jump_clause := JUMP_NONE;
--no_reg_conflict := true;
imflag := '0';
-- TODO: save power, only enable RB that need..
rd1 := dec.rd1;
rd2 := dec.rd2;
ra1 := dec.sreg1;
ra2 := dec.sreg2; -- Preload DREG for some insns
imm16 := dec.imm8h & dec.imm8l;
imm8 := dec.imm8l;
pc := fui.r.pc;
sr := dec.sr;
jump := dec.jump;
--condition_clause := dec.condition;
except_return:=dec.except_return;
dw.cop_id := dec.cop_id;
dw.cop_reg := dec.cop_reg;
alu_op := dec.alu_op;
reg_source0 := dec.reg_source;
reg_source1 := dec.reg_source;
dreg0 := dec.dreg;
dreg1 := dec.dreg;
blocks1 := dec.blocks;
blocks2 := dec.blocks;
macc := dec.macc;
memory_access := dec.memory_access;
memory_write := dec.memory_write;
modify_flags := dec.modify_flags;
if dec.modify_gpr then
regwe:='1';
else
regwe:='0';
end if;
if dec.modify_spr then
sprwe :='1';
else
sprwe :='0';
end if;
imflag := dec.imflag;
if freeze='0' then
dw.valid := fui.valid;
end if;
if fui.valid='1' and freeze='0' then
dw.rd1 := rd1;
dw.rd2 := rd2;
dw.sra1 := ra1;
dw.sra2 := ra2;
dw.sprwe := sprwe;
dw.pc := pc;
dw.npc := fui.npc;
dw.fpc := fui.npc + 2;
if dr.imflag='0' then
dw.imreg := (others => '0');
dw.tpc := pc;
end if;
case dec.loadimm is
when LOAD8 =>
if dr.imflag='1' then
-- Shift.
dw.imreg(31 downto 8) := dr.imreg(23 downto 0);
dw.imreg(7 downto 0) := unsigned(imm8);
else
dw.imreg(31 downto 8) := (others => imm8(7));
dw.imreg(7 downto 0) := unsigned(imm8);
end if;
when LOAD16 =>
if dr.imflag='0' then
dw.imreg(31 downto 15) := (others => imm16(15));
dw.imreg(14 downto 0) := unsigned(imm16(14 downto 0));
else
dw.imreg(31 downto 16) := dr.imreg(15 downto 0);
dw.imreg(15 downto 0) := unsigned(imm16(15 downto 0));
end if;
when LOAD24 =>
dw.imreg(31 downto 24) := (others => dec.imm24(23));
dw.imreg(23 downto 0) := unsigned(dec.imm24);
when LOAD0 =>
-- Keep imm
when others =>
--dw.imreg := (others => '0');
end case;
dw.imflag := imflag;
dw.enable_alu := dec.enable_alu;
dw.ismult := dec.ismult;
dw.alu_op := alu_op;
dw.alu_source := dec.alu_source;
dw.wb_is_data_address := '0';
dw.cop_en := dec.cop_en;
dw.cop_wr := dec.cop_wr;
dw.macc := macc;
dw.sr := sr;
dw.memory_access := memory_access;
dw.memory_write := memory_write;
dw.modify_flags := modify_flags;
dw.blocks := blocks1 or blocks2;
dw.dreg := dreg0;
dw.reg_source := reg_source0;
dw.regwe := regwe;
dw.priv := dec.priv;
dw.jump := jump;
dw.except_return:= except_return;
dw.use_carry := dec.use_carry;
-- Preserve condition from E24 extension (imm)
if dr.imflag='0' then
dw.condition_clause := dec.condition;
end if;
dw.opcode := opcode_high;
dw.opcode_low := opcode_low;
dw.dual := dec.extended;
dw.decoded := dec.op;
dw.is_jump := dec.is_jump;
else
busy <= freeze;
end if;
if rst='1' or flush='1' then
dw.valid := '0';
--dw.delay_slot := false;
dw.imflag := '0';
dw.regwe := '0';
dw.rd1 := '0';
dw.rd2 := '0';
dw.ismult:= '0';
dw.blocks := '0';
dw.cop_en := '0';
dw.cop_wr := '0';
dw.priv := '0';
dw.sprwe := '0';
dw.is_jump := false;
dw.memory_access := '0';
dw.memory_write := '0';
dw.enable_alu := '0';
dw.use_carry := '0';
dw.modify_flags := false;
end if;
if dec.extended then
dual <= '1';
end if;
-- fast-forward register access
duo.rd1 <= rd1;
duo.rd2 <= rd2;
duo.sra1 <= ra1;
duo.sra2 <= ra2;
if rising_edge(clk) then
dr <= dw;
end if;
-- synthesis translate_off
--dbg_can_issue_both <= can_issue_both;
--dbg_compositeloadimm <= compositeloadimm;
-- synthesis translate_on
end process;
end behave;
|
library verilog;
use verilog.vl_types.all;
entity alt3pram is
generic(
width : integer := 1;
widthad : integer := 1;
numwords : integer := 0;
lpm_file : string := "UNUSED";
lpm_hint : string := "USE_EAB=ON";
indata_reg : string := "UNREGISTERED";
indata_aclr : string := "ON";
write_reg : string := "UNREGISTERED";
write_aclr : string := "ON";
rdaddress_reg_a : string := "UNREGISTERED";
rdaddress_aclr_a: string := "ON";
rdcontrol_reg_a : string := "UNREGISTERED";
rdcontrol_aclr_a: string := "ON";
rdaddress_reg_b : string := "UNREGISTERED";
rdaddress_aclr_b: string := "ON";
rdcontrol_reg_b : string := "UNREGISTERED";
rdcontrol_aclr_b: string := "ON";
outdata_reg_a : string := "UNREGISTERED";
outdata_aclr_a : string := "ON";
outdata_reg_b : string := "UNREGISTERED";
outdata_aclr_b : string := "ON";
intended_device_family: string := "Stratix";
ram_block_type : string := "AUTO";
maximum_depth : integer := 0;
lpm_type : string := "alt3pram"
);
port(
wren : in vl_logic;
data : in vl_logic_vector;
wraddress : in vl_logic_vector;
inclock : in vl_logic;
inclocken : in vl_logic;
rden_a : in vl_logic;
rden_b : in vl_logic;
rdaddress_a : in vl_logic_vector;
rdaddress_b : in vl_logic_vector;
outclock : in vl_logic;
outclocken : in vl_logic;
aclr : in vl_logic;
qa : out vl_logic_vector;
qb : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width : constant is 1;
attribute mti_svvh_generic_type of widthad : constant is 1;
attribute mti_svvh_generic_type of numwords : constant is 1;
attribute mti_svvh_generic_type of lpm_file : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of indata_reg : constant is 1;
attribute mti_svvh_generic_type of indata_aclr : constant is 1;
attribute mti_svvh_generic_type of write_reg : constant is 1;
attribute mti_svvh_generic_type of write_aclr : constant is 1;
attribute mti_svvh_generic_type of rdaddress_reg_a : constant is 1;
attribute mti_svvh_generic_type of rdaddress_aclr_a : constant is 1;
attribute mti_svvh_generic_type of rdcontrol_reg_a : constant is 1;
attribute mti_svvh_generic_type of rdcontrol_aclr_a : constant is 1;
attribute mti_svvh_generic_type of rdaddress_reg_b : constant is 1;
attribute mti_svvh_generic_type of rdaddress_aclr_b : constant is 1;
attribute mti_svvh_generic_type of rdcontrol_reg_b : constant is 1;
attribute mti_svvh_generic_type of rdcontrol_aclr_b : constant is 1;
attribute mti_svvh_generic_type of outdata_reg_a : constant is 1;
attribute mti_svvh_generic_type of outdata_aclr_a : constant is 1;
attribute mti_svvh_generic_type of outdata_reg_b : constant is 1;
attribute mti_svvh_generic_type of outdata_aclr_b : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of maximum_depth : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
end alt3pram;
|
<filename>bps/SymbolSubQuad364QAM.vhd
-------------------------------------------------------------------
-- Authors: <NAME> @ 2019 --
-------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
use ieee.math_real.all;
library work;
USE work.constDef_pkg.all;
---------------------------------------------------------
ENTITY SymbolSubQuad364QAM IS
GENERIC(
Input_int : integer := 2;
Input_frac : integer := 16;
QuadNbits : integer := 3;
AdrrWidth : integer := 3
);
PORT(
clk : IN std_logic;
clk_en : IN std_logic;
Input_I : IN std_logic_vector ((Input_int+Input_frac)-1 DOWNTO 0);
Input_R : IN std_logic_vector ((Input_int+Input_frac)-1 DOWNTO 0);
QuadNumber : IN std_logic_vector (QuadNbits-1 DOWNTO 0);
SymbolAdrr : OUT std_logic_vector (AdrrWidth-1 DOWNTO 0)
);
END SymbolSubQuad364QAM;
ARCHITECTURE Struct OF SymbolSubQuad364QAM IS
signal aux : std_logic_vector(AdrrWidth-1 downto 0) := (others=>'0');
BEGIN
process(QuadNumber,Input_I,Input_R)
begin
C0: case QuadNumber is
when "00" =>
if (Input_I < dcI10) and (Input_R < dcR00) then
aux <= "110110";
elsif (Input_I < dcI10) and (Input_R > dcR00) then
aux <= "110111";
elsif (Input_I > dcI10) and (Input_R < dcR00) then
aux <= "110010";
else
aux <= "110011";
end if;
when "01" =>
if (Input_I < dcI10) and (Input_R < dcR01) then
aux <= "110101";
elsif (Input_I < dcI10) and (Input_R > dcR01) then
aux <= "110100";
elsif (Input_I > dcI10) and (Input_R < dcR01) then
aux <= "110001";
else
aux <= "110000";
end if;
when "10" =>
if (Input_I < dcI11) and (Input_R < dcR00) then
aux <= "111010";
elsif (Input_I < dcI11) and (Input_R > dcR00) then
aux <= "111011";
elsif (Input_I > dcI11) and (Input_R < dcR00) then
aux <= "111110";
else
aux <= "111111";
end if;
when "11" =>
if (Input_I < dcI11) and (Input_R < dcR01) then
aux <= "111001";
elsif (Input_I < dcI11) and (Input_R > dcR01) then
aux <= "111000";
elsif (Input_I > dcI11) and (Input_R < dcR01) then
aux <= "111101";
else
aux <= "111100";
end if;
WHEN OTHERS =>
aux <= "000000";
end case C0;
end process;
SymbolAdrr <= aux;
END Struct;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Use ieee.std_logic_unsigned.all;
entity diviseur_programmable is
Generic(Nbits : integer := 32);
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
division : in STD_LOGIC_VECTOR(Nbits-1 downto 0);
tc : out STD_LOGIC);
end diviseur_programmable;
architecture architecture_diviseur of diviseur_programmable is
signal cpt : std_logic_vector(Nbits-1 downto 0);
begin
-- compteur 0 a division
comptage: process(clk,rst,division)
begin
if rst = '1' then
cpt <= (others => '0');
elsif rising_edge(clk) then
if cpt < division then
cpt <= cpt + 1;
else
cpt <= (others => '0');
end if;
end if;
end process comptage;
-- impulsion de sortie a division
retenue: process(cpt,division)
begin
if cpt=division then
tc <= '1';
else
tc <= '0';
end if;
end process retenue;
end architecture_diviseur;
|
--
-- Virtual board example
--
-- SoC for Virtual simple board
--
-- Only tested for these configurations:
--
-- agneta
--
-- 4/2015 <NAME> <<EMAIL>>
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- For some MACHXO2 specific entities:
library work;
use work.stdtap.all;
use work.global_config.all;
entity virtual_top is
generic ( SIMULATION : boolean := true );
port (
mclk : in std_logic;
pclk : in std_logic;
global_reset : in std_logic;
--clk_xtal_in : in std_logic;
spi_clk : out std_logic;
spi_miso : in std_logic;
spi_mosi : out std_logic;
spi_cs : out std_logic;
i2c_sda : inout std_logic;
i2c_scl : inout std_logic;
uart_rx : in std_logic;
uart_tx : out std_logic;
reset_n : in std_logic
);
end entity virtual_top;
architecture behaviour of virtual_top is
attribute NOM_FREQ : string;
-- attribute NOM_FREQ of osc_inst : label is "22.17";
signal tap2core : tap_out_rec;
signal core2tap : tap_in_rec;
signal irq_in : std_logic := '0';
signal osc_clk : std_logic;
signal osc_stdby : std_logic := '0';
-- signal count : unsigned(23 downto 0) := x"aaaaaa";
signal reset_counter : unsigned(15 downto 0) := x"00ff";
signal nreset : std_logic;
signal cpu_reset : std_logic := '0';
-- signal glob_rst : std_logic := '1';
-- GPIOs:
-- Set to defined state for simulation:
signal gpio : unsigned(31 downto 0);
signal pwm : std_logic_vector(7 downto 0);
-- Debugging:
signal uart_loopback : std_logic;
begin
nreset <= reset_n;
----------------------------------------------------------------------------
-- SoC CPU
maybe_swtap:
if SIMULATION generate
swtap: VirtualTAP_DIRECT
generic map ( IDCODE => CONFIG_TAP_ID, TCLK_PERIOD => CONFIG_TAPCLK_PERIOD,
INS_NOP => x"00000013" )
port map (
-- Core <-> TAP signals:
tin => core2tap,
tout => tap2core
);
end generate;
cpu_reset <= tap2core.core_reset or not nreset;
soc: entity work.SoC
port map (
clk => mclk,
nmi_i => '0',
irq0 => irq_in,
perio_rst => '0',
-- gpio => gpio,
-- pwm => pwm(CONFIG_NUM_TMR-1 downto 0),
-- Emulation pins:
tin => tap2core,
tout => core2tap,
tap_reset => global_reset,
-- Requires CONFIG_UART and CONFIG_SPI enabled:
uart_tx => uart_tx,
uart_rx => uart_rx,
spi_sclk => spi_clk,
spi_cs => spi_cs,
spi_mosi => spi_mosi,
spi_miso => spi_miso,
reset => cpu_reset
);
rev_simulation:
if SIMULATION generate
gpio(15 downto 0) <= "HLLLLHLLLLHLLLLH";
end generate;
end behaviour;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.2
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dct_dct_1d is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
src_address0 : OUT STD_LOGIC_VECTOR (2 downto 0);
src_ce0 : OUT STD_LOGIC;
src_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
src1_address0 : OUT STD_LOGIC_VECTOR (2 downto 0);
src1_ce0 : OUT STD_LOGIC;
src1_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
src2_address0 : OUT STD_LOGIC_VECTOR (2 downto 0);
src2_ce0 : OUT STD_LOGIC;
src2_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
src3_address0 : OUT STD_LOGIC_VECTOR (2 downto 0);
src3_ce0 : OUT STD_LOGIC;
src3_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
src4_address0 : OUT STD_LOGIC_VECTOR (2 downto 0);
src4_ce0 : OUT STD_LOGIC;
src4_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
src5_address0 : OUT STD_LOGIC_VECTOR (2 downto 0);
src5_ce0 : OUT STD_LOGIC;
src5_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
src6_address0 : OUT STD_LOGIC_VECTOR (2 downto 0);
src6_ce0 : OUT STD_LOGIC;
src6_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
src7_address0 : OUT STD_LOGIC_VECTOR (2 downto 0);
src7_ce0 : OUT STD_LOGIC;
src7_q0 : IN STD_LOGIC_VECTOR (15 downto 0);
tmp_1 : IN STD_LOGIC_VECTOR (3 downto 0);
dst_address0 : OUT STD_LOGIC_VECTOR (5 downto 0);
dst_ce0 : OUT STD_LOGIC;
dst_we0 : OUT STD_LOGIC;
dst_d0 : OUT STD_LOGIC_VECTOR (15 downto 0);
tmp_11 : IN STD_LOGIC_VECTOR (3 downto 0) );
end;
architecture behav of dct_dct_1d is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_ST_pp0_stg0_fsm_1 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_ST_st7_fsm_2 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_true : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv4_8 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv4_1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv29_1000 : STD_LOGIC_VECTOR (28 downto 0) := "00000000000000001000000000000";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
signal ap_CS_fsm : STD_LOGIC_VECTOR (2 downto 0) := "001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_21 : BOOLEAN;
signal dct_coeff_table_0_address0 : STD_LOGIC_VECTOR (2 downto 0);
signal dct_coeff_table_0_ce0 : STD_LOGIC;
signal dct_coeff_table_0_q0 : STD_LOGIC_VECTOR (13 downto 0);
signal dct_coeff_table_1_address0 : STD_LOGIC_VECTOR (2 downto 0);
signal dct_coeff_table_1_ce0 : STD_LOGIC;
signal dct_coeff_table_1_q0 : STD_LOGIC_VECTOR (14 downto 0);
signal dct_coeff_table_2_address0 : STD_LOGIC_VECTOR (2 downto 0);
signal dct_coeff_table_2_ce0 : STD_LOGIC;
signal dct_coeff_table_2_q0 : STD_LOGIC_VECTOR (14 downto 0);
signal dct_coeff_table_3_address0 : STD_LOGIC_VECTOR (2 downto 0);
signal dct_coeff_table_3_ce0 : STD_LOGIC;
signal dct_coeff_table_3_q0 : STD_LOGIC_VECTOR (14 downto 0);
signal dct_coeff_table_4_address0 : STD_LOGIC_VECTOR (2 downto 0);
signal dct_coeff_table_4_ce0 : STD_LOGIC;
signal dct_coeff_table_4_q0 : STD_LOGIC_VECTOR (14 downto 0);
signal dct_coeff_table_5_address0 : STD_LOGIC_VECTOR (2 downto 0);
signal dct_coeff_table_5_ce0 : STD_LOGIC;
signal dct_coeff_table_5_q0 : STD_LOGIC_VECTOR (14 downto 0);
signal dct_coeff_table_6_address0 : STD_LOGIC_VECTOR (2 downto 0);
signal dct_coeff_table_6_ce0 : STD_LOGIC;
signal dct_coeff_table_6_q0 : STD_LOGIC_VECTOR (14 downto 0);
signal dct_coeff_table_7_address0 : STD_LOGIC_VECTOR (2 downto 0);
signal dct_coeff_table_7_ce0 : STD_LOGIC;
signal dct_coeff_table_7_q0 : STD_LOGIC_VECTOR (14 downto 0);
signal k_reg_288 : STD_LOGIC_VECTOR (3 downto 0);
signal src_addr_reg_490 : STD_LOGIC_VECTOR (2 downto 0);
signal src1_addr_reg_495 : STD_LOGIC_VECTOR (2 downto 0);
signal src2_addr_reg_500 : STD_LOGIC_VECTOR (2 downto 0);
signal src3_addr_reg_505 : STD_LOGIC_VECTOR (2 downto 0);
signal src4_addr_reg_510 : STD_LOGIC_VECTOR (2 downto 0);
signal src5_addr_reg_515 : STD_LOGIC_VECTOR (2 downto 0);
signal src6_addr_reg_520 : STD_LOGIC_VECTOR (2 downto 0);
signal src7_addr_reg_525 : STD_LOGIC_VECTOR (2 downto 0);
signal p_addr_cast_fu_319_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal p_addr_cast_reg_530 : STD_LOGIC_VECTOR (7 downto 0);
signal exitcond1_fu_323_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond1_reg_535 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_pp0_stg0_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_169 : BOOLEAN;
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppstg_exitcond1_reg_535_pp0_it1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond1_reg_535_pp0_it2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_ppstg_exitcond1_reg_535_pp0_it3 : STD_LOGIC_VECTOR (0 downto 0);
signal k_1_fu_329_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal p_addr1_fu_351_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal p_addr1_reg_584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_p_addr1_reg_584_pp0_it1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_p_addr1_reg_584_pp0_it2 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_ppstg_p_addr1_reg_584_pp0_it3 : STD_LOGIC_VECTOR (7 downto 0);
signal dct_coeff_table_0_load_reg_589 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_reg_ppstg_dct_coeff_table_0_load_reg_589_pp0_it2 : STD_LOGIC_VECTOR (13 downto 0);
signal dct_coeff_table_1_load_reg_594 : STD_LOGIC_VECTOR (14 downto 0);
signal src1_load_reg_599 : STD_LOGIC_VECTOR (15 downto 0);
signal dct_coeff_table_2_load_reg_604 : STD_LOGIC_VECTOR (14 downto 0);
signal ap_reg_ppstg_dct_coeff_table_2_load_reg_604_pp0_it2 : STD_LOGIC_VECTOR (14 downto 0);
signal dct_coeff_table_3_load_reg_609 : STD_LOGIC_VECTOR (14 downto 0);
signal src3_load_reg_614 : STD_LOGIC_VECTOR (15 downto 0);
signal dct_coeff_table_4_load_reg_619 : STD_LOGIC_VECTOR (14 downto 0);
signal ap_reg_ppstg_dct_coeff_table_4_load_reg_619_pp0_it2 : STD_LOGIC_VECTOR (14 downto 0);
signal dct_coeff_table_5_load_reg_624 : STD_LOGIC_VECTOR (14 downto 0);
signal src5_load_reg_629 : STD_LOGIC_VECTOR (15 downto 0);
signal dct_coeff_table_6_load_reg_634 : STD_LOGIC_VECTOR (14 downto 0);
signal src6_load_reg_639 : STD_LOGIC_VECTOR (15 downto 0);
signal dct_coeff_table_7_load_reg_644 : STD_LOGIC_VECTOR (14 downto 0);
signal src7_load_reg_649 : STD_LOGIC_VECTOR (15 downto 0);
signal src_load_reg_654 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_1_fu_362_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal tmp_8_1_reg_659 : STD_LOGIC_VECTOR (28 downto 0);
signal src2_load_reg_664 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_3_fu_374_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal tmp_8_3_reg_669 : STD_LOGIC_VECTOR (28 downto 0);
signal src4_load_reg_674 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_5_fu_386_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal tmp_8_5_reg_679 : STD_LOGIC_VECTOR (28 downto 0);
signal grp_fu_466_p3 : STD_LOGIC_VECTOR (28 downto 0);
signal tmp6_reg_684 : STD_LOGIC_VECTOR (28 downto 0);
signal tmp_4_reg_689 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_cast_fu_299_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_fu_335_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_5_fu_446_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_3_fu_311_p3 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_trn_cast_fu_347_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_8_1_fu_362_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_1_fu_362_p1 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_8_3_fu_374_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_3_fu_374_p1 : STD_LOGIC_VECTOR (14 downto 0);
signal tmp_8_5_fu_386_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_8_5_fu_386_p1 : STD_LOGIC_VECTOR (14 downto 0);
signal grp_fu_482_p3 : STD_LOGIC_VECTOR (28 downto 0);
signal grp_fu_474_p3 : STD_LOGIC_VECTOR (28 downto 0);
signal grp_fu_450_p3 : STD_LOGIC_VECTOR (28 downto 0);
signal tmp1_fu_422_p2 : STD_LOGIC_VECTOR (28 downto 0);
attribute use_dsp48 : string;
attribute use_dsp48 of tmp1_fu_422_p2 : signal is "no";
signal tmp4_fu_426_p2 : STD_LOGIC_VECTOR (28 downto 0);
attribute use_dsp48 of tmp4_fu_426_p2 : signal is "no";
signal tmp_2_fu_430_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal grp_fu_450_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_450_p1 : STD_LOGIC_VECTOR (14 downto 0);
signal grp_fu_450_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal grp_fu_458_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_458_p1 : STD_LOGIC_VECTOR (14 downto 0);
signal grp_fu_458_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_466_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_466_p1 : STD_LOGIC_VECTOR (14 downto 0);
signal grp_fu_466_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal grp_fu_458_p3 : STD_LOGIC_VECTOR (28 downto 0);
signal grp_fu_474_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_474_p1 : STD_LOGIC_VECTOR (14 downto 0);
signal grp_fu_474_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal grp_fu_482_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_482_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal grp_fu_482_p2 : STD_LOGIC_VECTOR (28 downto 0);
signal ap_sig_cseq_ST_st7_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_402 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (2 downto 0);
signal grp_fu_482_p10 : STD_LOGIC_VECTOR (28 downto 0);
component dct_mac_muladd_16s_15s_29s_29_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (14 downto 0);
din2 : IN STD_LOGIC_VECTOR (28 downto 0);
dout : OUT STD_LOGIC_VECTOR (28 downto 0) );
end component;
component dct_mac_muladd_16s_15s_14ns_29_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (14 downto 0);
din2 : IN STD_LOGIC_VECTOR (13 downto 0);
dout : OUT STD_LOGIC_VECTOR (28 downto 0) );
end component;
component dct_mac_muladd_16s_14ns_29s_29_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (13 downto 0);
din2 : IN STD_LOGIC_VECTOR (28 downto 0);
dout : OUT STD_LOGIC_VECTOR (28 downto 0) );
end component;
component dct_dct_1d_dct_coeff_table_0 IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (2 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
component dct_dct_1d_dct_coeff_table_1 IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (2 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (14 downto 0) );
end component;
component dct_dct_1d_dct_coeff_table_2 IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (2 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (14 downto 0) );
end component;
component dct_dct_1d_dct_coeff_table_3 IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (2 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (14 downto 0) );
end component;
component dct_dct_1d_dct_coeff_table_4 IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (2 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (14 downto 0) );
end component;
component dct_dct_1d_dct_coeff_table_5 IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (2 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (14 downto 0) );
end component;
component dct_dct_1d_dct_coeff_table_6 IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (2 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (14 downto 0) );
end component;
component dct_dct_1d_dct_coeff_table_7 IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (2 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (14 downto 0) );
end component;
begin
dct_coeff_table_0_U : component dct_dct_1d_dct_coeff_table_0
generic map (
DataWidth => 14,
AddressRange => 8,
AddressWidth => 3)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => dct_coeff_table_0_address0,
ce0 => dct_coeff_table_0_ce0,
q0 => dct_coeff_table_0_q0);
dct_coeff_table_1_U : component dct_dct_1d_dct_coeff_table_1
generic map (
DataWidth => 15,
AddressRange => 8,
AddressWidth => 3)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => dct_coeff_table_1_address0,
ce0 => dct_coeff_table_1_ce0,
q0 => dct_coeff_table_1_q0);
dct_coeff_table_2_U : component dct_dct_1d_dct_coeff_table_2
generic map (
DataWidth => 15,
AddressRange => 8,
AddressWidth => 3)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => dct_coeff_table_2_address0,
ce0 => dct_coeff_table_2_ce0,
q0 => dct_coeff_table_2_q0);
dct_coeff_table_3_U : component dct_dct_1d_dct_coeff_table_3
generic map (
DataWidth => 15,
AddressRange => 8,
AddressWidth => 3)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => dct_coeff_table_3_address0,
ce0 => dct_coeff_table_3_ce0,
q0 => dct_coeff_table_3_q0);
dct_coeff_table_4_U : component dct_dct_1d_dct_coeff_table_4
generic map (
DataWidth => 15,
AddressRange => 8,
AddressWidth => 3)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => dct_coeff_table_4_address0,
ce0 => dct_coeff_table_4_ce0,
q0 => dct_coeff_table_4_q0);
dct_coeff_table_5_U : component dct_dct_1d_dct_coeff_table_5
generic map (
DataWidth => 15,
AddressRange => 8,
AddressWidth => 3)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => dct_coeff_table_5_address0,
ce0 => dct_coeff_table_5_ce0,
q0 => dct_coeff_table_5_q0);
dct_coeff_table_6_U : component dct_dct_1d_dct_coeff_table_6
generic map (
DataWidth => 15,
AddressRange => 8,
AddressWidth => 3)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => dct_coeff_table_6_address0,
ce0 => dct_coeff_table_6_ce0,
q0 => dct_coeff_table_6_q0);
dct_coeff_table_7_U : component dct_dct_1d_dct_coeff_table_7
generic map (
DataWidth => 15,
AddressRange => 8,
AddressWidth => 3)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => dct_coeff_table_7_address0,
ce0 => dct_coeff_table_7_ce0,
q0 => dct_coeff_table_7_q0);
dct_mac_muladd_16s_15s_29s_29_1_U9 : component dct_mac_muladd_16s_15s_29s_29_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 16,
din1_WIDTH => 15,
din2_WIDTH => 29,
dout_WIDTH => 29)
port map (
din0 => grp_fu_450_p0,
din1 => grp_fu_450_p1,
din2 => grp_fu_450_p2,
dout => grp_fu_450_p3);
dct_mac_muladd_16s_15s_14ns_29_1_U10 : component dct_mac_muladd_16s_15s_14ns_29_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 16,
din1_WIDTH => 15,
din2_WIDTH => 14,
dout_WIDTH => 29)
port map (
din0 => grp_fu_458_p0,
din1 => grp_fu_458_p1,
din2 => grp_fu_458_p2,
dout => grp_fu_458_p3);
dct_mac_muladd_16s_15s_29s_29_1_U11 : component dct_mac_muladd_16s_15s_29s_29_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 16,
din1_WIDTH => 15,
din2_WIDTH => 29,
dout_WIDTH => 29)
port map (
din0 => grp_fu_466_p0,
din1 => grp_fu_466_p1,
din2 => grp_fu_466_p2,
dout => grp_fu_466_p3);
dct_mac_muladd_16s_15s_29s_29_1_U12 : component dct_mac_muladd_16s_15s_29s_29_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 16,
din1_WIDTH => 15,
din2_WIDTH => 29,
dout_WIDTH => 29)
port map (
din0 => grp_fu_474_p0,
din1 => grp_fu_474_p1,
din2 => grp_fu_474_p2,
dout => grp_fu_474_p3);
dct_mac_muladd_16s_14ns_29s_29_1_U13 : component dct_mac_muladd_16s_14ns_29s_29_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 16,
din1_WIDTH => 14,
din2_WIDTH => 29,
dout_WIDTH => 29)
port map (
din0 => grp_fu_482_p0,
din1 => grp_fu_482_p1,
din2 => grp_fu_482_p2,
dout => grp_fu_482_p3);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it0 assign process. --
ap_reg_ppiten_pp0_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and not((exitcond1_fu_323_p2 = ap_const_lv1_0)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (exitcond1_fu_323_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and not((exitcond1_fu_323_p2 = ap_const_lv1_0))))) then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end process;
-- k_reg_288 assign process. --
k_reg_288_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (exitcond1_fu_323_p2 = ap_const_lv1_0))) then
k_reg_288 <= k_1_fu_329_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
k_reg_288 <= ap_const_lv4_0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_true = ap_true)) then
ap_reg_ppstg_dct_coeff_table_0_load_reg_589_pp0_it2 <= dct_coeff_table_0_load_reg_589;
ap_reg_ppstg_dct_coeff_table_2_load_reg_604_pp0_it2 <= dct_coeff_table_2_load_reg_604;
ap_reg_ppstg_dct_coeff_table_4_load_reg_619_pp0_it2 <= dct_coeff_table_4_load_reg_619;
ap_reg_ppstg_exitcond1_reg_535_pp0_it2 <= ap_reg_ppstg_exitcond1_reg_535_pp0_it1;
ap_reg_ppstg_exitcond1_reg_535_pp0_it3 <= ap_reg_ppstg_exitcond1_reg_535_pp0_it2;
ap_reg_ppstg_p_addr1_reg_584_pp0_it2 <= ap_reg_ppstg_p_addr1_reg_584_pp0_it1;
ap_reg_ppstg_p_addr1_reg_584_pp0_it3 <= ap_reg_ppstg_p_addr1_reg_584_pp0_it2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1)) then
ap_reg_ppstg_exitcond1_reg_535_pp0_it1 <= exitcond1_reg_535;
ap_reg_ppstg_p_addr1_reg_584_pp0_it1 <= p_addr1_reg_584;
exitcond1_reg_535 <= exitcond1_fu_323_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (exitcond1_reg_535 = ap_const_lv1_0))) then
dct_coeff_table_0_load_reg_589 <= dct_coeff_table_0_q0;
dct_coeff_table_1_load_reg_594 <= dct_coeff_table_1_q0;
dct_coeff_table_2_load_reg_604 <= dct_coeff_table_2_q0;
dct_coeff_table_3_load_reg_609 <= dct_coeff_table_3_q0;
dct_coeff_table_4_load_reg_619 <= dct_coeff_table_4_q0;
dct_coeff_table_5_load_reg_624 <= dct_coeff_table_5_q0;
dct_coeff_table_6_load_reg_634 <= dct_coeff_table_6_q0;
dct_coeff_table_7_load_reg_644 <= dct_coeff_table_7_q0;
src1_load_reg_599 <= src1_q0;
src3_load_reg_614 <= src3_q0;
src5_load_reg_629 <= src5_q0;
src6_load_reg_639 <= src6_q0;
src7_load_reg_649 <= src7_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (exitcond1_fu_323_p2 = ap_const_lv1_0))) then
p_addr1_reg_584 <= p_addr1_fu_351_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
p_addr_cast_reg_530(6 downto 3) <= p_addr_cast_fu_319_p1(6 downto 3);
src1_addr_reg_495 <= tmp_1_cast_fu_299_p1(3 - 1 downto 0);
src2_addr_reg_500 <= tmp_1_cast_fu_299_p1(3 - 1 downto 0);
src3_addr_reg_505 <= tmp_1_cast_fu_299_p1(3 - 1 downto 0);
src4_addr_reg_510 <= tmp_1_cast_fu_299_p1(3 - 1 downto 0);
src5_addr_reg_515 <= tmp_1_cast_fu_299_p1(3 - 1 downto 0);
src6_addr_reg_520 <= tmp_1_cast_fu_299_p1(3 - 1 downto 0);
src7_addr_reg_525 <= tmp_1_cast_fu_299_p1(3 - 1 downto 0);
src_addr_reg_490 <= tmp_1_cast_fu_299_p1(3 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond1_reg_535_pp0_it1 = ap_const_lv1_0)) then
src2_load_reg_664 <= src2_q0;
src4_load_reg_674 <= src4_q0;
src_load_reg_654 <= src_q0;
tmp6_reg_684 <= grp_fu_466_p3;
tmp_8_1_reg_659 <= tmp_8_1_fu_362_p2;
tmp_8_3_reg_669 <= tmp_8_3_fu_374_p2;
tmp_8_5_reg_679 <= tmp_8_5_fu_386_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_reg_ppstg_exitcond1_reg_535_pp0_it2 = ap_const_lv1_0)) then
tmp_4_reg_689 <= tmp_2_fu_430_p2(28 downto 13);
end if;
end if;
end process;
p_addr_cast_reg_530(2 downto 0) <= "000";
p_addr_cast_reg_530(7) <= '0';
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, exitcond1_fu_323_p2, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_pp0_stg0_fsm_1 =>
if ((not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it4) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it3)))) and not(((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((exitcond1_fu_323_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))))) then
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_1;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((exitcond1_fu_323_p2 = ap_const_lv1_0)) and not((ap_const_logic_1 = ap_reg_ppiten_pp0_it1)))) then
ap_NS_fsm <= ap_ST_st7_fsm_2;
else
ap_NS_fsm <= ap_ST_st7_fsm_2;
end if;
when ap_ST_st7_fsm_2 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st7_fsm_2)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) or (ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_2))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st7_fsm_2)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_2)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_169 assign process. --
ap_sig_bdd_169_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_169 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_21 assign process. --
ap_sig_bdd_21_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_21 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_402 assign process. --
ap_sig_bdd_402_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_402 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_cseq_ST_pp0_stg0_fsm_1 assign process. --
ap_sig_cseq_ST_pp0_stg0_fsm_1_assign_proc : process(ap_sig_bdd_169)
begin
if (ap_sig_bdd_169) then
ap_sig_cseq_ST_pp0_stg0_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp0_stg0_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_21)
begin
if (ap_sig_bdd_21) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_2 assign process. --
ap_sig_cseq_ST_st7_fsm_2_assign_proc : process(ap_sig_bdd_402)
begin
if (ap_sig_bdd_402) then
ap_sig_cseq_ST_st7_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_2 <= ap_const_logic_0;
end if;
end process;
dct_coeff_table_0_address0 <= tmp_fu_335_p1(3 - 1 downto 0);
-- dct_coeff_table_0_ce0 assign process. --
dct_coeff_table_0_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
dct_coeff_table_0_ce0 <= ap_const_logic_1;
else
dct_coeff_table_0_ce0 <= ap_const_logic_0;
end if;
end process;
dct_coeff_table_1_address0 <= tmp_fu_335_p1(3 - 1 downto 0);
-- dct_coeff_table_1_ce0 assign process. --
dct_coeff_table_1_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
dct_coeff_table_1_ce0 <= ap_const_logic_1;
else
dct_coeff_table_1_ce0 <= ap_const_logic_0;
end if;
end process;
dct_coeff_table_2_address0 <= tmp_fu_335_p1(3 - 1 downto 0);
-- dct_coeff_table_2_ce0 assign process. --
dct_coeff_table_2_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
dct_coeff_table_2_ce0 <= ap_const_logic_1;
else
dct_coeff_table_2_ce0 <= ap_const_logic_0;
end if;
end process;
dct_coeff_table_3_address0 <= tmp_fu_335_p1(3 - 1 downto 0);
-- dct_coeff_table_3_ce0 assign process. --
dct_coeff_table_3_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
dct_coeff_table_3_ce0 <= ap_const_logic_1;
else
dct_coeff_table_3_ce0 <= ap_const_logic_0;
end if;
end process;
dct_coeff_table_4_address0 <= tmp_fu_335_p1(3 - 1 downto 0);
-- dct_coeff_table_4_ce0 assign process. --
dct_coeff_table_4_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
dct_coeff_table_4_ce0 <= ap_const_logic_1;
else
dct_coeff_table_4_ce0 <= ap_const_logic_0;
end if;
end process;
dct_coeff_table_5_address0 <= tmp_fu_335_p1(3 - 1 downto 0);
-- dct_coeff_table_5_ce0 assign process. --
dct_coeff_table_5_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
dct_coeff_table_5_ce0 <= ap_const_logic_1;
else
dct_coeff_table_5_ce0 <= ap_const_logic_0;
end if;
end process;
dct_coeff_table_6_address0 <= tmp_fu_335_p1(3 - 1 downto 0);
-- dct_coeff_table_6_ce0 assign process. --
dct_coeff_table_6_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
dct_coeff_table_6_ce0 <= ap_const_logic_1;
else
dct_coeff_table_6_ce0 <= ap_const_logic_0;
end if;
end process;
dct_coeff_table_7_address0 <= tmp_fu_335_p1(3 - 1 downto 0);
-- dct_coeff_table_7_ce0 assign process. --
dct_coeff_table_7_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
dct_coeff_table_7_ce0 <= ap_const_logic_1;
else
dct_coeff_table_7_ce0 <= ap_const_logic_0;
end if;
end process;
dst_address0 <= tmp_5_fu_446_p1(6 - 1 downto 0);
-- dst_ce0 assign process. --
dst_ce0_assign_proc : process(ap_reg_ppiten_pp0_it4)
begin
if ((ap_const_logic_1 = ap_reg_ppiten_pp0_it4)) then
dst_ce0 <= ap_const_logic_1;
else
dst_ce0 <= ap_const_logic_0;
end if;
end process;
dst_d0 <= tmp_4_reg_689;
-- dst_we0 assign process. --
dst_we0_assign_proc : process(ap_reg_ppiten_pp0_it4, ap_reg_ppstg_exitcond1_reg_535_pp0_it3)
begin
if ((((ap_const_logic_1 = ap_reg_ppiten_pp0_it4) and (ap_reg_ppstg_exitcond1_reg_535_pp0_it3 = ap_const_lv1_0)))) then
dst_we0 <= ap_const_logic_1;
else
dst_we0 <= ap_const_logic_0;
end if;
end process;
exitcond1_fu_323_p2 <= "1" when (k_reg_288 = ap_const_lv4_8) else "0";
grp_fu_450_p0 <= src4_load_reg_674;
grp_fu_450_p1 <= ap_reg_ppstg_dct_coeff_table_4_load_reg_619_pp0_it2;
grp_fu_450_p2 <= tmp_8_5_reg_679;
grp_fu_458_p0 <= src7_load_reg_649;
grp_fu_458_p1 <= dct_coeff_table_7_load_reg_644;
grp_fu_458_p2 <= ap_const_lv29_1000(14 - 1 downto 0);
grp_fu_466_p0 <= src6_load_reg_639;
grp_fu_466_p1 <= dct_coeff_table_6_load_reg_634;
grp_fu_466_p2 <= grp_fu_458_p3;
grp_fu_474_p0 <= src2_load_reg_664;
grp_fu_474_p1 <= ap_reg_ppstg_dct_coeff_table_2_load_reg_604_pp0_it2;
grp_fu_474_p2 <= tmp_8_3_reg_669;
grp_fu_482_p0 <= src_load_reg_654;
grp_fu_482_p1 <= grp_fu_482_p10(14 - 1 downto 0);
grp_fu_482_p10 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_dct_coeff_table_0_load_reg_589_pp0_it2),29));
grp_fu_482_p2 <= tmp_8_1_reg_659;
k_1_fu_329_p2 <= std_logic_vector(unsigned(k_reg_288) + unsigned(ap_const_lv4_1));
p_addr1_fu_351_p2 <= std_logic_vector(unsigned(p_addr_cast_reg_530) + unsigned(tmp_trn_cast_fu_347_p1));
p_addr_cast_fu_319_p1 <= std_logic_vector(resize(unsigned(tmp_3_fu_311_p3),8));
src1_address0 <= src1_addr_reg_495;
-- src1_ce0 assign process. --
src1_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
src1_ce0 <= ap_const_logic_1;
else
src1_ce0 <= ap_const_logic_0;
end if;
end process;
src2_address0 <= src2_addr_reg_500;
-- src2_ce0 assign process. --
src2_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) then
src2_ce0 <= ap_const_logic_1;
else
src2_ce0 <= ap_const_logic_0;
end if;
end process;
src3_address0 <= src3_addr_reg_505;
-- src3_ce0 assign process. --
src3_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
src3_ce0 <= ap_const_logic_1;
else
src3_ce0 <= ap_const_logic_0;
end if;
end process;
src4_address0 <= src4_addr_reg_510;
-- src4_ce0 assign process. --
src4_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) then
src4_ce0 <= ap_const_logic_1;
else
src4_ce0 <= ap_const_logic_0;
end if;
end process;
src5_address0 <= src5_addr_reg_515;
-- src5_ce0 assign process. --
src5_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
src5_ce0 <= ap_const_logic_1;
else
src5_ce0 <= ap_const_logic_0;
end if;
end process;
src6_address0 <= src6_addr_reg_520;
-- src6_ce0 assign process. --
src6_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
src6_ce0 <= ap_const_logic_1;
else
src6_ce0 <= ap_const_logic_0;
end if;
end process;
src7_address0 <= src7_addr_reg_525;
-- src7_ce0 assign process. --
src7_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it0)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0))) then
src7_ce0 <= ap_const_logic_1;
else
src7_ce0 <= ap_const_logic_0;
end if;
end process;
src_address0 <= src_addr_reg_490;
-- src_ce0 assign process. --
src_ce0_assign_proc : process(ap_sig_cseq_ST_pp0_stg0_fsm_1, ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp0_stg0_fsm_1) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it1))) then
src_ce0 <= ap_const_logic_1;
else
src_ce0 <= ap_const_logic_0;
end if;
end process;
tmp1_fu_422_p2 <= std_logic_vector(signed(grp_fu_482_p3) + signed(grp_fu_474_p3));
tmp4_fu_426_p2 <= std_logic_vector(signed(grp_fu_450_p3) + signed(tmp6_reg_684));
tmp_1_cast_fu_299_p1 <= std_logic_vector(resize(unsigned(tmp_1),64));
tmp_2_fu_430_p2 <= std_logic_vector(signed(tmp1_fu_422_p2) + signed(tmp4_fu_426_p2));
tmp_3_fu_311_p3 <= (tmp_11 & ap_const_lv3_0);
tmp_5_fu_446_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_p_addr1_reg_584_pp0_it3),64));
tmp_8_1_fu_362_p0 <= src1_load_reg_599;
tmp_8_1_fu_362_p1 <= dct_coeff_table_1_load_reg_594;
tmp_8_1_fu_362_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(tmp_8_1_fu_362_p0) * signed(tmp_8_1_fu_362_p1))), 29));
tmp_8_3_fu_374_p0 <= src3_load_reg_614;
tmp_8_3_fu_374_p1 <= dct_coeff_table_3_load_reg_609;
tmp_8_3_fu_374_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(tmp_8_3_fu_374_p0) * signed(tmp_8_3_fu_374_p1))), 29));
tmp_8_5_fu_386_p0 <= src5_load_reg_629;
tmp_8_5_fu_386_p1 <= dct_coeff_table_5_load_reg_624;
tmp_8_5_fu_386_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed(tmp_8_5_fu_386_p0) * signed(tmp_8_5_fu_386_p1))), 29));
tmp_fu_335_p1 <= std_logic_vector(resize(unsigned(k_reg_288),64));
tmp_trn_cast_fu_347_p1 <= std_logic_vector(resize(unsigned(k_reg_288),8));
end behav;
|
<filename>boards/ip/iprepo/SpectrumAnalyser_v1_1/hdl/vhdl/SpectrumAnalyser_reset_hold.vhd
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\spectrum_analyser\SpectrumAnalyser_reset_hold.vhd
-- Created: 2021-03-09 14:01:03
--
-- Generated by MATLAB 9.8 and HDL Coder 3.16
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: SpectrumAnalyser_reset_hold
-- Source Path: SpectrumAnalyser/SpectrumAnalyser_axi_lite/SpectrumAnalyser_axi_lite_module/SpectrumAnalyser_reset_hold
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY SpectrumAnalyser_reset_hold IS
PORT( clk : IN std_logic;
reset : IN std_logic;
reset_in : IN std_logic; -- ufix1
in_burst : IN std_logic; -- ufix1
reset_out : OUT std_logic; -- ufix1
reset_pending : OUT std_logic -- ufix1
);
END SpectrumAnalyser_reset_hold;
ARCHITECTURE rtl OF SpectrumAnalyser_reset_hold IS
-- Signals
SIGNAL enb : std_logic;
SIGNAL const_1 : std_logic; -- ufix1
SIGNAL reset_hold_module_hstate : unsigned(7 DOWNTO 0); -- uint8
SIGNAL reset_hold_module_reset_out_reg : std_logic;
SIGNAL reset_hold_module_reset_pending_reg : std_logic;
SIGNAL reset_hold_module_hstate_next : unsigned(7 DOWNTO 0); -- uint8
SIGNAL reset_hold_module_reset_out_reg_next : std_logic;
SIGNAL reset_hold_module_reset_pending_reg_next : std_logic;
BEGIN
const_1 <= '1';
enb <= const_1;
reset_hold_module_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
reset_hold_module_hstate <= to_unsigned(16#00#, 8);
reset_hold_module_reset_out_reg <= '0';
reset_hold_module_reset_pending_reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
reset_hold_module_hstate <= reset_hold_module_hstate_next;
reset_hold_module_reset_out_reg <= reset_hold_module_reset_out_reg_next;
reset_hold_module_reset_pending_reg <= reset_hold_module_reset_pending_reg_next;
END IF;
END IF;
END PROCESS reset_hold_module_process;
reset_hold_module_output : PROCESS (in_burst, reset_hold_module_hstate, reset_hold_module_reset_out_reg,
reset_hold_module_reset_pending_reg, reset_in)
VARIABLE reset_in1 : std_logic;
VARIABLE in_burst1 : std_logic;
BEGIN
reset_hold_module_hstate_next <= reset_hold_module_hstate;
reset_hold_module_reset_out_reg_next <= reset_hold_module_reset_out_reg;
reset_hold_module_reset_pending_reg_next <= reset_hold_module_reset_pending_reg;
IF reset_in /= '0' THEN
reset_in1 := '1';
ELSE
reset_in1 := '0';
END IF;
IF in_burst /= '0' THEN
in_burst1 := '1';
ELSE
in_burst1 := '0';
END IF;
CASE reset_hold_module_hstate IS
WHEN "00000000" =>
IF in_burst1 = '1' THEN
reset_hold_module_reset_out_reg_next <= '0';
IF reset_in1 = '1' THEN
reset_hold_module_reset_pending_reg_next <= '1';
reset_hold_module_hstate_next <= to_unsigned(16#02#, 8);
ELSE
reset_hold_module_reset_pending_reg_next <= '0';
reset_hold_module_hstate_next <= to_unsigned(16#01#, 8);
END IF;
ELSE
reset_hold_module_reset_out_reg_next <= reset_in1;
reset_hold_module_reset_pending_reg_next <= '0';
END IF;
WHEN "00000001" =>
IF ( NOT in_burst1) = '1' THEN
reset_hold_module_reset_out_reg_next <= reset_in1;
reset_hold_module_reset_pending_reg_next <= '0';
reset_hold_module_hstate_next <= to_unsigned(16#00#, 8);
ELSIF reset_in1 = '1' THEN
reset_hold_module_reset_out_reg_next <= '0';
reset_hold_module_reset_pending_reg_next <= '1';
reset_hold_module_hstate_next <= to_unsigned(16#02#, 8);
ELSE
reset_hold_module_reset_out_reg_next <= '0';
reset_hold_module_reset_pending_reg_next <= '0';
END IF;
WHEN "00000010" =>
reset_hold_module_reset_out_reg_next <= '0';
reset_hold_module_reset_pending_reg_next <= '1';
IF ( NOT in_burst1) = '1' THEN
reset_hold_module_hstate_next <= to_unsigned(16#03#, 8);
END IF;
WHEN "00000011" =>
reset_hold_module_reset_out_reg_next <= '1';
reset_hold_module_reset_pending_reg_next <= '1';
reset_hold_module_hstate_next <= to_unsigned(16#00#, 8);
WHEN OTHERS =>
reset_hold_module_hstate_next <= to_unsigned(16#00#, 8);
END CASE;
reset_out <= reset_hold_module_reset_out_reg;
reset_pending <= reset_hold_module_reset_pending_reg;
END PROCESS reset_hold_module_output;
END rtl;
|
library verilog;
use verilog.vl_types.all;
entity axis2fib_rxctrl is
generic(
DATA_WIDTH : integer := 64;
BCNT_WIDTH : integer := 32;
AR_IDLE : integer := 1;
AR_WAIT : integer := 2;
AR_READCNT : integer := 4;
AR_RDDATA : integer := 8;
AR_DONE : integer := 22
);
port(
rx_mac_aclk : in vl_logic;
\reset_\ : in vl_logic;
rden_rf : out vl_logic;
rden_rcf : out vl_logic;
rdempty_rf : in vl_logic;
rdempty_rcf : in vl_logic;
dataout_rf : in vl_logic_vector;
dataout_rcf : in vl_logic_vector;
rx_axis_mac_tdata: out vl_logic_vector;
rx_axis_mac_tvalid: out vl_logic;
rx_axis_mac_tlast: out vl_logic;
rx_axis_mac_tuser: out vl_logic;
rx_axis_filter_tuser: out vl_logic;
rx_axis_mac_tstrb: out vl_logic_vector(7 downto 0);
rx_statistics_vector: out vl_logic_vector(27 downto 0);
rx_statistics_valid: out vl_logic;
rx_axis_mac_tready: in vl_logic;
rx_axis_compatible_mode: in vl_logic;
test : out vl_logic
);
end axis2fib_rxctrl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
/*
* button 0: press for reset (during reset button press, one sample is shown, so press a few times to see the stability ADC samples)
* button 1: increase
* button 2: decrease
* button 3: control mode selection - cycle through:
* ACTUAL_V (default, return after some seconds)
* FREQUENCY (trigger level should be set OK)
* TIME_PER_DIV (can use button 1&2)
* CONTROL_MODE_TRIGGER_LEVEL (can use button 1&2 to change trigger level, but only reset can undo user set to default
* (default= avg sensed V since last reset: (min+max)/2 ). indicated by 3 horizontal lines
* When set typ the user, only a minus sign is given
* MIN V
* MAX V
*
* switch 0: trigger on level rising
* switch 1: trigger level enabled
*
* led 0: =switch 0 - on means to trigger on rising signal
* led 1: on=trigger level enabled
* led 2: on=waiting for trigger to occur
* led 3: on=could trigger now
*
* input for ADC:
* + top left = ground
* + bottom right = VDD
* + bottom left = ADC input signal
*/
entity DE1_oscilloscope is
port(
/* ADC */
ADC_CONVST: out std_logic;
ADC_DIN: out std_logic;
ADC_DOUT: in std_logic;
ADC_SCLK: out std_logic;
/* CLOCK */
CLOCK2_50: in std_logic;
CLOCK3_50: in std_logic;
CLOCK4_50: in std_logic;
CLOCK_50: in std_logic;
/* SEG7 */
HEX0: out std_logic_vector(6 downto 0);
HEX1: out std_logic_vector(6 downto 0);
HEX2: out std_logic_vector(6 downto 0);
HEX3: out std_logic_vector(6 downto 0);
HEX4: out std_logic_vector(6 downto 0);
HEX5: out std_logic_vector(6 downto 0);
/* KEY */
KEY: in std_logic_vector(3 downto 0);
/* LED */
LEDR: out std_logic_vector(9 downto 0);
/* SW */
SW: in std_logic_vector(9 downto 0);
/* VGA */
VGA_BLANK_N: out std_logic;
VGA_B: out std_logic_vector(7 downto 0);
VGA_CLK: out std_logic;
VGA_G: out std_logic_vector(7 downto 0);
VGA_HS: out std_logic;
VGA_R: out std_logic_vector(7 downto 0);
VGA_SYNC_N: out std_logic;
VGA_VS: out std_logic;
/* GPIO_0, GPIO_0 connect to GPIO Default */
GPIO_0: inout std_logic_vector(35 downto 0);
/* GPIO_1, GPIO_1 connect to GPIO Default */
GPIO_1: inout std_logic_vector(35 downto 0) );
end DE1_oscilloscope;
architecture structure of DE1_oscilloscope is
component calc_bin_to_6x7seg is
port(
binaryNumber : in std_logic_vector(19 downto 0); -- 2^20 > 999.999 (max on 6 segments)
HEX0: out std_logic_vector(6 downto 0);
HEX1: out std_logic_vector(6 downto 0);
HEX2: out std_logic_vector(6 downto 0);
HEX3: out std_logic_vector(6 downto 0);
HEX4: out std_logic_vector(6 downto 0);
HEX5: out std_logic_vector(6 downto 0)
-- TODO: add enumeration for display mode
-- type display_6x7seg_mode_type is {FULL, ACTUAL_VOLTAGE, ...};
-- put this in a separate package to make it available to other modules
);
end component;
component read_ADC
port(
clk_50MHz : in std_logic; -- 50 MHz clock
reset : in std_logic; -- should be active at least 2 50Mhz cycles, so it is not missed by 25MHz process
/* signals to/from the LTC2308 ADC */
ADC_CONVST: out std_logic;
ADC_DIN: out std_logic;
ADC_DOUT: in std_logic;
ADC_SCLK: out std_logic;
/* 12-bit data as read from ADC */
data : out std_logic_vector(11 downto 0); -- data from measurement of previous start signal
data_available_now : out std_logic -- active high for 1 clock to indicate new data has arrived
);
end component read_ADC;
component display_via_memory
port(
clk_50MHz : in std_logic; -- clock for pixel input
reset : in std_logic;
pixel_X : in std_logic_vector(10 downto 0);
pixel_Y : in std_logic_vector(9 downto 0);
pixel_value_R : in std_logic_vector(7 downto 0);
pixel_value_G : in std_logic_vector(7 downto 0);
pixel_value_B : in std_logic_vector(7 downto 0);
pixel_valid : in std_logic; -- set to 1 means X,Y and pixel_value_[RGB] are valid
/* --- VGA output --- */
VGA_BLANK_N: out std_logic;
VGA_B: out std_logic_vector(7 downto 0);
VGA_CLK: out std_logic;
VGA_G: out std_logic_vector(7 downto 0);
VGA_HS: out std_logic;
VGA_R: out std_logic_vector(7 downto 0);
VGA_SYNC_N: out std_logic;
VGA_VS: out std_logic
);
end component display_via_memory;
component key_detection is
port(
clk : in std_logic;
rst : in std_logic;
KEY: in std_logic_vector(3 downto 1);
button_plus_pressed_once : out std_logic;
button_minus_pressed_once : out std_logic;
button_control_mode_pressed_once : out std_logic;
any_button_being_pressed : out std_logic
);
end component key_detection;
component measure_frequency is
port(
clk : in std_logic;
rst : in std_logic;
one_cycle_reset : in std_logic;
trigger_detected : in std_logic;
measured_frequency: out integer range 0 to 64e3 -- ADC does <500 [KS/s], and need time (14 samples) to measure (hi&how)
);
end component measure_frequency;
component signal_generator is
port(
clk : in std_logic;
signals : out std_logic_vector(5 downto 0)
);
end component signal_generator;
signal overall_reset : std_logic;
signal number2convert : std_logic_vector(19 downto 0);
signal pixel_X : std_logic_vector(10 downto 0);
signal pixel_Y : std_logic_vector(9 downto 0);
signal pixel_value_R : std_logic_vector(7 downto 0);
signal pixel_value_G : std_logic_vector(7 downto 0);
signal pixel_value_B : std_logic_vector(7 downto 0);
signal pixel_valid : std_logic;
signal pixel_X_for_measurement : integer range 0 to 1440-1;
signal pixel_Y_for_measurement : integer range 0 to 900-1;
signal pixel_X_countdown : integer range 0 to 1000000-1;
signal pixel_X_countdown_initial_value : integer range 0 to 1000000-1 := 50000-1; -- 50K is 0.1[s]/div of 100 pixels
/* pixel_X_countdown_initial_value
* 12 1e6 - 2[s]/div (screen 14.4 div = 28.8[s]
* 11 500e3 - 1[s]/div
* 10 250e3 - 500[ms]/div
* 9 100e3 - 200[ms]/div (default) up to 50 Hz (10 X samples/period) >64
* 8 50e3 - 100[ms]/div 100 Hz >128
* 7 25e3 - 50[ms]/div 200 Hz >256
* 6 10e3 - 20[ms]/div 500 Hz >512
* 5 5e3 - 10[ms]/div 1000 Hz >1024
* 4 2.5e3- 5[ms]/div 2000 Hz
* 3 1e3 - 2[ms]/div 5000 Hz
* 2 500 - 1[ms]/div (screen 14.4 div = 14.4[ms]
* 1 250 - 500[us]/div (screen 14.4 div = 7.2[ms], but <1 measurement per pixel)
* 0 100 - 200[us]/div (screen 14.4 div = [ms], but <1 measurement per pixel)
*/
-- type time_per_div_setting_type is (S2, S1, MS500, MS250, MS100, MS50, MS25, MS10, MS5, MS2, MS1);
-- signal time_per_div_setting : time_per_div_setting_type := S1;
signal time_per_div_setting : integer range 0 to 12 := 8;
signal button_plus_pressed_once : std_logic;
signal button_minus_pressed_once : std_logic;
signal button_control_mode_pressed_once : std_logic;
signal any_button_pressed : std_logic;
signal reset_button_was_pressed_prev_clock_cycle : std_logic;
signal reset_button_pressed_once : std_logic;
-- control model to define context for keys and 7 segmented display
type control_mode_type is (CONTROL_MODE_ACTUAL_V, CONTROL_MODE_FREQUENCY, CONTROL_MODE_TIME_PER_DIV, CONTROL_MODE_TRIGGER_LEVEL, CONTROL_MODE_MAX_ADC, CONTROL_MODE_MIN_ADC);
signal control_mode : control_mode_type;
signal control_keep_mode_countdown : integer range 0 to 200e6; -- (4[s] @ 50MHz)
signal measured_frequency : integer range 0 to 64e3; -- ADC does <500 [KS/s], and need time (14 samples) to measure (hi&how)
signal adc_data : std_logic_vector(11 downto 0);
signal adc_data_available_now : std_logic;
signal adc_data_sample_when_reset_just_pressed : std_logic_vector(11 downto 0);
signal max_adc_data : std_logic_vector(11 downto 0);
signal min_adc_data : std_logic_vector(11 downto 0);
signal avg_adc_value : std_logic_vector(11 downto 0);
signal trigger_level_set_by_user : std_logic := '0';
signal trigger_level_enabled : std_logic := '0';
signal trigger_level : std_logic_vector(11 downto 0);
signal trigger_level_rising : std_logic;
signal trigger_now : std_logic; -- 1 cycle active when trigger has been detected
signal sample_level_counter : integer range 0 to 7 := 0;
signal level_other_side_done : std_logic; -- if trigger level rising, then this indicates signal was long enough below trigger level (if trigger level falling, then above trigger level)
signal currentYisADCdata : std_logic := '0';
-- calc_HEX_X is output as calculated from a number
signal calc_HEX_0 : std_logic_vector(6 downto 0);
signal calc_HEX_1 : std_logic_vector(6 downto 0);
signal calc_HEX_2 : std_logic_vector(6 downto 0);
signal calc_HEX_3 : std_logic_vector(6 downto 0);
signal calc_HEX_4 : std_logic_vector(6 downto 0);
signal calc_HEX_5 : std_logic_vector(6 downto 0);
-- calc_HEX_X is output as calculated from a number
signal time_per_div_HEX_0 : std_logic_vector(6 downto 0);
signal time_per_div_HEX_1 : std_logic_vector(6 downto 0);
signal time_per_div_HEX_2 : std_logic_vector(6 downto 0);
signal time_per_div_HEX_3 : std_logic_vector(6 downto 0);
signal time_per_div_HEX_4 : std_logic_vector(6 downto 0);
signal time_per_div_HEX_5 : std_logic_vector(6 downto 0);
begin
overall_reset <= not KEY(0);
trigger_level_rising <= SW(0);
LEDR(0) <= SW(0);
LEDR(1) <= trigger_level_enabled;
LEDR(3) <= trigger_now;
LEDR(9 downto 4) <= b"000000";
reset_key_pressed: process(CLOCK_50)
begin
if rising_edge(CLOCK_50) then
reset_button_was_pressed_prev_clock_cycle <= overall_reset;
reset_button_pressed_once <= overall_reset and not reset_button_was_pressed_prev_clock_cycle;
end if;
end process;
-- HEX2 <= (others => '1'); -- off
-- HEX3 <= (others => overall_reset);
-- HEX4 <= (others => overall_reset);
-- GPIO 1 is at right edge of board
-- botton right on GPIO = GPIO_1_D35 = pin 40
-- botton left on GPIO = GPIO_1_D34 = pin 39
-- botton right on board, second pin = GPIO_0_D2 = pin 38
-- botton left on board, second pin = GPIO_0_D3 = pin 37
-- (ground is at 6th pin counting from top on right side = pin12 ...)
-- see data sheet
signal_creation : signal_generator port map(CLOCK_50, GPIO_1(35 downto 30));
GPIO_1(29) <= '1'; -- 3.3 V
disp_via_mem : display_via_memory port map(
clk_50MHz => CLOCK_50,
reset => overall_reset,
-- pixel data to set in memory
pixel_X => pixel_X, pixel_Y => pixel_Y,
pixel_value_R => pixel_value_R, pixel_value_G => pixel_value_G, pixel_value_B => pixel_value_B,
pixel_valid => pixel_valid,
/* --- VGA output --- */
VGA_BLANK_N => VGA_BLANK_N, VGA_SYNC_N => VGA_SYNC_N,
VGA_HS => VGA_HS, VGA_VS => VGA_VS,
VGA_R => VGA_R, VGA_G => VGA_G, VGA_B => VGA_B,
VGA_CLK => VGA_CLK );
input_keys: key_detection port map(
clk => CLOCK_50,
rst => overall_reset,
KEY => KEY(3 downto 1),
button_plus_pressed_once => button_plus_pressed_once,
button_minus_pressed_once => button_minus_pressed_once,
button_control_mode_pressed_once => button_control_mode_pressed_once,
any_button_being_pressed => any_button_pressed
);
frequency_measure_process : measure_frequency
port map(
clk => CLOCK_50,
rst => overall_reset,
one_cycle_reset => reset_button_pressed_once,
trigger_detected => trigger_now,
measured_frequency => measured_frequency
);
readADC : read_ADC port map( clk_50MHz => CLOCK_50, reset => reset_button_pressed_once,
ADC_CONVST => ADC_CONVST, ADC_DIN => ADC_DIN, ADC_DOUT => ADC_DOUT, ADC_SCLK => ADC_SCLK,
data => adc_data, data_available_now => adc_data_available_now );
adc_data_for_reset: process(CLOCK_50)
begin
if rising_edge(CLOCK_50) and (reset_button_pressed_once = '1') then
adc_data_sample_when_reset_just_pressed <= adc_data;
end if;
end process;
number2convert <= (b"00000000" & adc_data) when (control_mode = CONTROL_MODE_ACTUAL_V) and (overall_reset = '0') else
(b"00000000" & adc_data_sample_when_reset_just_pressed) when (control_mode = CONTROL_MODE_ACTUAL_V) else
(b"00000000" & trigger_level) when (control_mode = CONTROL_MODE_TRIGGER_LEVEL) else
std_logic_vector(to_unsigned(measured_frequency, 20)) when (control_mode = CONTROL_MODE_FREQUENCY) else
(b"00000000" & max_adc_data) when (control_mode = CONTROL_MODE_MAX_ADC) else
(b"00000000" & min_adc_data) when (control_mode = CONTROL_MODE_MIN_ADC) else
b"00000000000000000000"; -- don't care since time_per_div will be on display, but put 0's for lower power usage
calc_seg : calc_bin_to_6x7seg port map(
binaryNumber => number2convert,
HEX0 => calc_HEX_0,
HEX1 => calc_HEX_1,
HEX2 => calc_HEX_2,
HEX3 => calc_HEX_3,
HEX4 => calc_HEX_4, -- max value of ADC is 4096, so no need for MSB display (value is 0)
HEX5 => calc_HEX_5
);
-- output_to_7seg_display
HEX0 <= time_per_div_HEX_0 when (control_mode = CONTROL_MODE_TIME_PER_DIV) else
calc_HEX_0 when (control_mode = CONTROL_MODE_FREQUENCY) else
(not "0111110"); -- V for voltage
HEX1 <= time_per_div_HEX_1 when (control_mode = CONTROL_MODE_TIME_PER_DIV) else
calc_HEX_1 when (control_mode = CONTROL_MODE_FREQUENCY) else
(not "0000000") when (control_mode = CONTROL_MODE_ACTUAL_V) else -- empty
(not "0001000") when (control_mode = CONTROL_MODE_MIN_ADC) else -- low _
(not "0000001") when (control_mode = CONTROL_MODE_MAX_ADC) else -- high _
(not "1000000") when (control_mode = CONTROL_MODE_TRIGGER_LEVEL) and (trigger_level_set_by_user = '1') else
(not "1001001"); -- 3 horizontal lines when trigger level determined from min/max
HEX2 <= time_per_div_HEX_2 when (control_mode = CONTROL_MODE_TIME_PER_DIV) else
calc_HEX_2 when (control_mode = CONTROL_MODE_FREQUENCY) else
calc_HEX_0; -- TRIGGER_LEVEL or ACTUAL_VOLTAGE
HEX3 <= time_per_div_HEX_3 when (control_mode = CONTROL_MODE_TIME_PER_DIV) else
calc_HEX_3 when (control_mode = CONTROL_MODE_FREQUENCY) else
calc_HEX_1; -- TRIGGER_LEVEL or ACTUAL_VOLTAGE
HEX4 <= time_per_div_HEX_4 when (control_mode = CONTROL_MODE_TIME_PER_DIV) else
calc_HEX_4 when (control_mode = CONTROL_MODE_FREQUENCY) else
calc_HEX_2; -- TRIGGER_LEVEL or ACTUAL_VOLTAGE
HEX5 <= time_per_div_HEX_5 when (control_mode = CONTROL_MODE_TIME_PER_DIV) else
calc_HEX_5 when (control_mode = CONTROL_MODE_FREQUENCY) else
calc_HEX_3; -- TRIGGER_LEVEL or ACTUAL_VOLTAGE
control_mode_handling: process(CLOCK_50)
variable prev_control_mode_button_pressed : std_logic;
variable latched_control_mode_button_pressed : std_logic; -- coupled to KEY3, note buttons are debounced, but may change during setup time
begin
if rising_edge(CLOCK_50) then
if (overall_reset = '1') then
control_mode <= CONTROL_MODE_ACTUAL_V;
control_keep_mode_countdown <= 0;
else
if button_control_mode_pressed_once then
-- ORDER: CONTROL_MODE_ACTUAL_V, CONTROL_MODE_FREQUENCY, CONTROL_MODE_TIME_PER_DIV, CONTROL_MODE_TRIGGER_LEVEL
if control_mode = CONTROL_MODE_ACTUAL_V then
control_mode <= CONTROL_MODE_FREQUENCY;
elsif control_mode = CONTROL_MODE_FREQUENCY then
control_mode <= CONTROL_MODE_TIME_PER_DIV;
elsif control_mode = CONTROL_MODE_TIME_PER_DIV then
control_mode <= CONTROL_MODE_TRIGGER_LEVEL;
elsif control_mode = CONTROL_MODE_TRIGGER_LEVEL then
control_mode <= CONTROL_MODE_MIN_ADC;
elsif control_mode = CONTROL_MODE_MIN_ADC then
control_mode <= CONTROL_MODE_MAX_ADC;
else
control_mode <= CONTROL_MODE_ACTUAL_V;
end if;
-- Works, but error in Quartus: control_mode <= CONTROL_MODE_TIME_PER_DIV WHEN control_mode = CONTROL_MODE_ACTUAL_V ELSE
-- CONTROL_MODE_TRIGGER_LEVEL WHEN control_mode = CONTROL_MODE_TIME_PER_DIV ELSE
-- CONTROL_MODE_ACTUAL_V;
elsif (button_minus_pressed_once = '1' or button_plus_pressed_once = '1') and (control_mode /= CONTROL_MODE_TRIGGER_LEVEL) then
control_mode <= CONTROL_MODE_TIME_PER_DIV;
end if;
-- after 4[s] of inactivity, return to displaying the actual voltage when busy with +/- buttons
if any_button_pressed then
control_keep_mode_countdown <= 200e6;
elsif (control_keep_mode_countdown > 0) then
control_keep_mode_countdown <= control_keep_mode_countdown - 1;
elsif (control_keep_mode_countdown = 0) and (control_mode /= CONTROL_MODE_FREQUENCY) then
control_mode <= CONTROL_MODE_ACTUAL_V;
end if;
end if;
end if;
end process;
set_trigger_level: process(CLOCK_50)
begin
if rising_edge(CLOCK_50) then
if (reset_button_pressed_once) then
trigger_level_set_by_user <= '0'; -- only reset can undo the setting of trigger level by user
elsif (control_mode = CONTROL_MODE_TRIGGER_LEVEL) then
if not trigger_level_set_by_user then
trigger_level <= avg_adc_value;
end if;
if button_plus_pressed_once then
trigger_level_set_by_user <= '1';
if ( unsigned(trigger_level) < 4092) then
trigger_level <= std_logic_vector(to_unsigned( (to_integer(unsigned(trigger_level)) + 1), trigger_level'length));
end if;
elsif button_minus_pressed_once then
trigger_level_set_by_user <= '1';
if (unsigned(trigger_level) > 4) then
trigger_level <= std_logic_vector(to_unsigned( (to_integer(unsigned(trigger_level)) - 1), trigger_level'length));
end if;
end if;
end if;
end if;
end process;
set_time_in_X: process(CLOCK_50)
begin
if rising_edge(CLOCK_50) then
if (overall_reset = '1') then
-- set display frequency high enough so user will not get an aliasing problem
-- meaning e.g. a horizontal line for signal that is a multiple of the DISPLAYED sample frequency
if measured_frequency >= 16#1000# then
time_per_div_setting <= 0;
elsif measured_frequency >= 16#800# then
time_per_div_setting <= 1;
elsif measured_frequency >= 16#400# then
time_per_div_setting <= 2;
elsif measured_frequency >= 16#200# then
time_per_div_setting <= 3;
elsif measured_frequency >= 16#100# then
time_per_div_setting <= 4;
elsif measured_frequency >= 16#80# then
time_per_div_setting <= 5;
elsif measured_frequency >= 16#40# then
time_per_div_setting <= 6;
elsif measured_frequency >= 16#20# then
time_per_div_setting <= 7;
else
time_per_div_setting <= 8; -- 0.1 [s/div]
end if;
else
if control_mode = CONTROL_MODE_TIME_PER_DIV then
if button_plus_pressed_once then
if (time_per_div_setting < 11) then
time_per_div_setting <= time_per_div_setting + 1;
end if;
elsif button_minus_pressed_once then
if (time_per_div_setting > 0) then
time_per_div_setting <= time_per_div_setting - 1;
end if;
end if;
end if;
end if;
end if;
end process;
-- set pixel_X_countdown_initial_value depending on
set_time_per_div: process(CLOCK_50)
begin
if rising_edge(CLOCK_50) then
-- next lines do not work in Quartus:
-- with time_per_div_setting select
-- pixel_X_countdown_initial_value <= 500 -1 WHEN 0,
-- 1e3-1 WHEN 1,
-- 2e3-1 WHEN 2,
-- 5e3-1 WHEN 3,
-- 10e3-1 WHEN 4,
-- 20e3-1 WHEN 5,
-- 50e3-1 WHEN 6,
-- 100e3-1 WHEN 7,
-- 200e3-1 WHEN 8,
-- 500e3-1 WHEN 9,
-- 1e6-1 WHEN others;
if time_per_div_setting = 0 then
pixel_X_countdown_initial_value <= 100-1;
elsif time_per_div_setting = 1 then
pixel_X_countdown_initial_value <= 250-1;
elsif time_per_div_setting = 2 then
pixel_X_countdown_initial_value <= 500-1;
elsif time_per_div_setting = 3 then
pixel_X_countdown_initial_value <=1000-1;
elsif time_per_div_setting = 4 then
pixel_X_countdown_initial_value <=2500-1;
elsif time_per_div_setting = 5 then
pixel_X_countdown_initial_value <= 5e3-1;
elsif time_per_div_setting = 6 then
pixel_X_countdown_initial_value <= 10e3-1;
elsif time_per_div_setting = 7 then
pixel_X_countdown_initial_value <= 25e3-1;
elsif time_per_div_setting = 8 then
pixel_X_countdown_initial_value <= 50e3-1;
elsif time_per_div_setting = 9 then
pixel_X_countdown_initial_value <= 100e3-1;
elsif time_per_div_setting = 10 then
pixel_X_countdown_initial_value <= 250e3-1;
elsif time_per_div_setting = 11 then
pixel_X_countdown_initial_value <= 500e3-1;
else
pixel_X_countdown_initial_value <= 1e6-1;
end if;
end if;
end process;
calc_hex_from_time_per_div_setting: process(time_per_div_setting)
begin
if (time_per_div_setting = 12) then
time_per_div_HEX_5 <= not "0000000";
time_per_div_HEX_4 <= not "0000000";
time_per_div_HEX_3 <= not "1011011"; -- 2
time_per_div_HEX_2 <= not "1111001"; -- E
time_per_div_HEX_1 <= not "0111111"; -- 0
time_per_div_HEX_0 <= not "0000000";
elsif (time_per_div_setting = 11) then
time_per_div_HEX_5 <= not "0000000";
time_per_div_HEX_4 <= not "0000000";
time_per_div_HEX_3 <= not "0000110"; -- 1
time_per_div_HEX_2 <= not "1111001"; -- E
time_per_div_HEX_1 <= not "0111111"; -- 0
time_per_div_HEX_0 <= not "0000000";
elsif (time_per_div_setting = 10) then
time_per_div_HEX_5 <= not "1101101"; -- 5
time_per_div_HEX_4 <= not "0111111"; -- 0
time_per_div_HEX_3 <= not "0111111"; -- 0
time_per_div_HEX_2 <= not "1111001"; -- E
time_per_div_HEX_1 <= not "1000000"; -- -
time_per_div_HEX_0 <= not "1001111"; -- 3
elsif (time_per_div_setting = 9) then
time_per_div_HEX_5 <= not "1011011"; -- 2
time_per_div_HEX_4 <= not "0111111"; -- 0
time_per_div_HEX_3 <= not "0111111"; -- 0
time_per_div_HEX_2 <= not "1111001"; -- E
time_per_div_HEX_1 <= not "1000000"; -- -
time_per_div_HEX_0 <= not "1001111"; -- 3
elsif (time_per_div_setting = 8) then
time_per_div_HEX_5 <= not "0000110"; -- 1
time_per_div_HEX_4 <= not "0111111"; -- 0
time_per_div_HEX_3 <= not "0111111"; -- 0
time_per_div_HEX_2 <= not "1111001"; -- E
time_per_div_HEX_1 <= not "1000000"; -- -
time_per_div_HEX_0 <= not "1001111"; -- 3
elsif (time_per_div_setting = 7) then
time_per_div_HEX_5 <= not "0000000";
time_per_div_HEX_4 <= not "1101101"; -- 5
time_per_div_HEX_3 <= not "0111111"; -- 0
time_per_div_HEX_2 <= not "1111001"; -- E
time_per_div_HEX_1 <= not "1000000"; -- -
time_per_div_HEX_0 <= not "1001111"; -- 3
elsif (time_per_div_setting = 6) then
time_per_div_HEX_5 <= not "0000000";
time_per_div_HEX_4 <= not "1011011"; -- 2
time_per_div_HEX_3 <= not "0111111"; -- 0
time_per_div_HEX_2 <= not "1111001"; -- E
time_per_div_HEX_1 <= not "1000000"; -- -
time_per_div_HEX_0 <= not "1001111"; -- 3
elsif (time_per_div_setting = 5) then
time_per_div_HEX_5 <= not "0000000";
time_per_div_HEX_4 <= not "0000110"; -- 1
time_per_div_HEX_3 <= not "0111111"; -- 0
time_per_div_HEX_2 <= not "1111001"; -- E
time_per_div_HEX_1 <= not "1000000"; -- -
time_per_div_HEX_0 <= not "1001111"; -- 3
elsif (time_per_div_setting = 4) then
time_per_div_HEX_5 <= not "0000000";
time_per_div_HEX_4 <= not "0000000";
time_per_div_HEX_3 <= not "1101101"; -- 5
time_per_div_HEX_2 <= not "1111001"; -- E
time_per_div_HEX_1 <= not "1000000"; -- -
time_per_div_HEX_0 <= not "1001111"; -- 3
elsif (time_per_div_setting = 3) then
time_per_div_HEX_5 <= not "0000000";
time_per_div_HEX_4 <= not "0000000";
time_per_div_HEX_3 <= not "1011011"; -- 2
time_per_div_HEX_2 <= not "1111001"; -- E
time_per_div_HEX_1 <= not "1000000"; -- -
time_per_div_HEX_0 <= not "1001111"; -- 3
elsif (time_per_div_setting = 2) then
time_per_div_HEX_5 <= not "0000000";
time_per_div_HEX_4 <= not "0000000";
time_per_div_HEX_3 <= not "0000110"; -- 1
time_per_div_HEX_2 <= not "1111001"; -- E
time_per_div_HEX_1 <= not "1000000"; -- -
time_per_div_HEX_0 <= not "1001111"; -- 3
elsif (time_per_div_setting = 1) then
time_per_div_HEX_5 <= not "1101101"; -- 5
time_per_div_HEX_4 <= not "0111111"; -- 0
time_per_div_HEX_3 <= not "0111111"; -- 0
time_per_div_HEX_2 <= not "1111001"; -- E
time_per_div_HEX_1 <= not "1000000"; -- -
time_per_div_HEX_0 <= not "1111101"; -- 6
elsif (time_per_div_setting = 0) then
time_per_div_HEX_5 <= not "1011011"; -- 2
time_per_div_HEX_4 <= not "0111111"; -- 0
time_per_div_HEX_3 <= not "0111111"; -- 0
time_per_div_HEX_2 <= not "1111001"; -- E
time_per_div_HEX_1 <= not "1000000"; -- -
time_per_div_HEX_0 <= not "1111101"; -- 6
else
time_per_div_HEX_5 <= not "1111001"; -- E
time_per_div_HEX_4 <= not "1010000"; -- r
time_per_div_HEX_3 <= not "1010000"; -- r
time_per_div_HEX_2 <= not "1011100"; -- o
time_per_div_HEX_1 <= not "1010000"; -- r
time_per_div_HEX_0 <= not "0000000";
end if;
end process;
determine_avg_adc_value : process(CLOCK_50)
variable count_max_in_a_row : integer range 0 to 7 := 0;
variable count_min_in_a_row : integer range 0 to 7 := 0;
begin
if rising_edge(CLOCK_50) then
if (overall_reset = '1') then
min_adc_data <= 12b"111111111100";
max_adc_data <= 12b"000000000011";
avg_adc_value <= 12b"011111111111";
count_min_in_a_row := 0;
count_max_in_a_row := 0;
else
if adc_data_available_now then
if to_integer(unsigned(adc_data)) > to_integer(unsigned(max_adc_data)) then
if (count_max_in_a_row = 7) then
max_adc_data <= adc_data; -- was: adc_data, but spikes have too much impact
count_max_in_a_row := 0; -- to prevent rising signal with 1 outlier to give wrong value
else
count_max_in_a_row := count_max_in_a_row + 1;
end if;
else
count_max_in_a_row := 0;
end if;
if to_integer(unsigned(adc_data)) < to_integer(unsigned(min_adc_data)) then
if (count_min_in_a_row = 7) then
min_adc_data <= adc_data; -- was: adc_data, but spikes have too much impact
count_min_in_a_row := 0; -- to prevent rising signal with 1 outlier to give wrong value
else
count_min_in_a_row := count_min_in_a_row + 1;
end if;
else
count_min_in_a_row := 0;
end if;
end if;
avg_adc_value <= std_logic_vector( to_unsigned( ( to_integer(unsigned(min_adc_data)) +
to_integer(unsigned(max_adc_data)) )/2, adc_data'length) );
end if;
end if;
end process;
manage_trigger_level : process(CLOCK_50)
variable sum_min_max : integer range 0 to 4095*2;
begin
if rising_edge(CLOCK_50) then
if reset_button_pressed_once then -- so signal trigger_now is available during reset button press (for freq. for default timescale)
trigger_now <= '0';
trigger_level_enabled <= '0';
sample_level_counter <= 0;
level_other_side_done <= '0';
else
trigger_level_enabled <= SW(1);
-- set min/max adc value since reset, and determine trigger level from that.
-- note that trigger_now is active for only 1 clock cycle.
trigger_now <= '0';
if adc_data_available_now then
sample_level_counter <= 0; -- value may toggle between X and X+1. If X or X+1 is trigger level, reset counter
if ( to_integer(unsigned(adc_data)) > to_integer(unsigned(trigger_level))+1 ) then
if trigger_level_rising and level_other_side_done then
if sample_level_counter = 1 then
trigger_now <= '1';
level_other_side_done <= '0';
sample_level_counter <= 0;
else
sample_level_counter <= sample_level_counter + 1;
end if;
elsif trigger_level_rising and not level_other_side_done then
sample_level_counter <= 0;
elsif (not trigger_level_rising) and level_other_side_done then
sample_level_counter <= 0;
else -- (not trigger_level_rising) and (not level_other_side_done)
if sample_level_counter = 1 then
level_other_side_done <= '1';
sample_level_counter <= 0;
else
sample_level_counter <= sample_level_counter + 1;
end if;
end if;
end if;
if ( to_integer(unsigned(adc_data)) < to_integer(unsigned(trigger_level))-1 ) then
if (not trigger_level_rising) and level_other_side_done then
if sample_level_counter = 1 then
trigger_now <= '1';
level_other_side_done <= '0';
sample_level_counter <= 0;
else
sample_level_counter <= sample_level_counter + 1;
end if;
elsif (not trigger_level_rising) and not level_other_side_done then
sample_level_counter <= 0;
elsif trigger_level_rising and level_other_side_done then
sample_level_counter <= 0;
else -- trigger_level_rising and (not level_other_side_done)
if sample_level_counter = 1 then
level_other_side_done <= '1';
sample_level_counter <= 0;
else
sample_level_counter <= sample_level_counter + 1;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
set_pixels : process(CLOCK_50)
begin
if rising_edge(CLOCK_50) then
pixel_valid <= '0';
if (overall_reset = '1') then
LEDR(2) <= '0';
pixel_X_countdown <= pixel_X_countdown_initial_value;
pixel_X_for_measurement <= 1;
/* elsif pixel_X_countdown = 1 then -- clear 100 pixels ahead
pixel_X <= std_logic_vector(to_unsigned( (pixel_X_for_measurement+100) mod 1440, 11));
pixel_Y <= 10b"1011111111"; -- 1023 means the screen Y position never matches (so not displayed on screen)
pixel_value_R <= "00000000"; -- RGB are not used in display_via_memory now
pixel_value_G <= "00000000";
pixel_value_B <= "00000000";
pixel_valid <= '1';
*/ elsif (pixel_X_countdown = 1) then
if ((trigger_level_enabled = '0') or (trigger_now = '1') or (pixel_X_for_measurement /= 0)) then -- countdown remains 1 when waiting for trigger
-- prepare: first do calculations since 899-ADC/5 may be on critical timing path
if pixel_X_for_measurement < 1440-1 then
pixel_X_for_measurement <= pixel_X_for_measurement + 1;
else
pixel_X_for_measurement <= 0; -- start again from left of the screen
end if;
-- better: while measuring at this X pixel, set all measured values
-- increment array of all possible values, stop measurements at value 255, and then show
-- now: just copy value that happens to be there at the end of the countdown (so 1 measurement per X on screen)
pixel_Y_for_measurement <= (to_integer(unsigned(adc_data))+2)/5; -- so value is 0..819 (=4095/5)
pixel_X_countdown <= 0;
LEDR(2) <= '0'; -- LED1 is off to indicate we are not waiting for a trigger
else
-- countdown remains 1 when waiting for trigger
LEDR(2) <= '1'; -- LED1 is on to indicate we are waiting for a trigger
end if;
elsif pixel_X_countdown = 0 then
pixel_X_countdown <= pixel_X_countdown_initial_value;
pixel_X <= std_logic_vector(to_unsigned(pixel_X_for_measurement, 11));
if (pixel_X_for_measurement /= 0) then
pixel_Y <= std_logic_vector(to_unsigned(pixel_Y_for_measurement, 10));
else
pixel_Y <= std_logic_vector(to_unsigned( (to_integer(unsigned(trigger_level))+2)/5, 10));
end if;
pixel_value_R <= "11111111";
pixel_value_G <= "11111111";
pixel_value_B <= "11111111";
pixel_valid <= '1';
else
pixel_X_countdown <= pixel_X_countdown - 1;
end if;
end if;
end process;
end structure;
/* Original generated system builder code below.
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module DE1_oscilloscope(
//////////// ADC //////////
output ADC_CONVST,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
//////////// CLOCK //////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
//////////// SEG7 //////////
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
//////////// KEY //////////
input [3:0] KEY,
//////////// LED //////////
output [9:0] LEDR,
//////////// SW //////////
input [9:0] SW,
//////////// VGA //////////
output VGA_BLANK_N,
output [7:0] VGA_B,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS,
//////////// GPIO_0, GPIO_0 connect to GPIO Default //////////
inout [35:0] GPIO_0,
//////////// GPIO_1, GPIO_1 connect to GPIO Default //////////
inout [35:0] GPIO_1
);
//=======================================================
// REG/WIRE declarations
//=======================================================
//=======================================================
// Structural coding
//=======================================================
endmodule
*/
|
<reponame>shivankarora/cpu-design-master
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--entity freq_divider is
--Port(
--clk: in std_logic;
--out_clk: out std_logic
--);
--end freq_divider;
--architecture Behavioral of freq_divider is
--signal counter: std_logic_vector(19 downto 0):="00000000000000000000";
--signal temp_clk: std_logic;
--begin
--process(clk)
--begin
--if(counter="00000000000000000000") then temp_clk<='1'
--end if;
--end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Clock_Generator is
Port (
clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end Clock_Generator;
architecture Behavioral of Clock_Generator is
signal count: integer range 0 to 2000000 :=0;
signal temp_clk: STD_LOGIC:='0';
begin
process(clk_in)
begin
if(clk_in='1' and clk_in'EVENT)then
if(count<1000000)then
count<=count+1;
else
count<=0;
temp_clk<=not(temp_clk);
end if;
end if;
end process;
clk_out<=temp_clk;
end Behavioral;
|
--------------------------------------------------------------------------------------------------------------------------
-- Original Authors : <NAME>, <NAME>, <NAME>, <NAME> --
-- Date created: N/A --
-- --
-- Additional Authors : <NAME>, <NAME>, <NAME>, <NAME> --
-- Date edited: March 26, 2018 --
-- --
-- This program takes a value from the synthesizer.vhd file and runs it through the 12-bit ROM to find the --
-- respective sine wave value. --
--------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_SIGNED.all;
use ieee.numeric_std.all; -- Needed for shifts
entity PianoSin_lut is
port (
clk : in std_logic;
en : in std_logic;
--Address input
address_reg : in std_logic_vector(11 downto 0);
--Sine value output
sin_out : out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of PianoSin_lut is
type rom_type is array (0 to 4095) of std_logic_vector (11 downto 0);
constant SIN_ROM : rom_type :=
(
X"000", X"00A", X"015", X"01E", X"029", X"034", X"03E", X"048",
X"052", X"05D", X"068", X"071", X"07C", X"087", X"091", X"09B",
X"0A5", X"0B0", X"0BA", X"0C5", X"0CF", X"0D9", X"0E4", X"0EE",
X"0F8", X"102", X"10D", X"117", X"121", X"12B", X"136", X"140",
X"14B", X"154", X"15F", X"169", X"173", X"17D", X"187", X"191",
X"19C", X"1A5", X"1B0", X"1BA", X"1C4", X"1CD", X"1D8", X"1E2",
X"1EC", X"1F6", X"200", X"20A", X"214", X"21E", X"227", X"231",
X"23B", X"245", X"24F", X"259", X"263", X"26D", X"277", X"280",
X"289", X"293", X"29D", X"2A6", X"2B0", X"2BA", X"2C4", X"2CC",
X"2D6", X"2E0", X"2EA", X"2F2", X"2FC", X"305", X"30F", X"319",
X"321", X"32B", X"334", X"33E", X"346", X"350", X"359", X"362",
X"36B", X"374", X"37D", X"386", X"390", X"398", X"3A1", X"3AA",
X"3B3", X"3BB", X"3C4", X"3CD", X"3D6", X"3DE", X"3E7", X"3F0",
X"3F9", X"401", X"40A", X"412", X"41B", X"424", X"42B", X"434",
X"43C", X"445", X"44D", X"455", X"45D", X"466", X"46D", X"476",
X"47E", X"486", X"48E", X"495", X"49E", X"4A6", X"4AE", X"4B5",
X"4BD", X"4C5", X"4CD", X"4D4", X"4DB", X"4E3", X"4EB", X"4F2",
X"4F9", X"501", X"508", X"510", X"517", X"51E", X"526", X"52D",
X"533", X"53B", X"542", X"549", X"550", X"557", X"55E", X"565",
X"56C", X"572", X"579", X"580", X"586", X"58C", X"593", X"59A",
X"5A0", X"5A6", X"5AD", X"5B3", X"5BA", X"5BF", X"5C6", X"5CC",
X"5D2", X"5D9", X"5DE", X"5E4", X"5EA", X"5F0", X"5F6", X"5FC",
X"602", X"607", X"60D", X"612", X"618", X"61E", X"623", X"628",
X"62E", X"633", X"639", X"63E", X"643", X"648", X"64E", X"652",
X"657", X"65C", X"662", X"666", X"66B", X"670", X"675", X"67A",
X"67E", X"683", X"687", X"68C", X"690", X"695", X"699", X"69E",
X"6A2", X"6A6", X"6AA", X"6AE", X"6B3", X"6B6", X"6BB", X"6BF",
X"6C3", X"6C6", X"6CA", X"6CE", X"6D2", X"6D5", X"6D9", X"6DD",
X"6E0", X"6E4", X"6E7", X"6EB", X"6EE", X"6F1", X"6F5", X"6F8",
X"6FB", X"6FE", X"701", X"704", X"707", X"70A", X"70D", X"710",
X"713", X"716", X"719", X"71B", X"71E", X"721", X"723", X"726",
X"728", X"72B", X"72D", X"72F", X"732", X"734", X"736", X"738",
X"73A", X"73C", X"73F", X"741", X"742", X"744", X"746", X"748",
X"74A", X"74C", X"74D", X"74F", X"750", X"752", X"754", X"755",
X"757", X"758", X"759", X"75B", X"75C", X"75D", X"75E", X"760",
X"761", X"762", X"763", X"764", X"765", X"766", X"767", X"767",
X"768", X"769", X"76A", X"76A", X"76B", X"76C", X"76C", X"76D",
X"76D", X"76E", X"76E", X"76F", X"76F", X"76F", X"76F", X"770",
X"770", X"770", X"770", X"770", X"770", X"770", X"770", X"770",
X"770", X"770", X"770", X"770", X"770", X"76F", X"76F", X"76F",
X"76E", X"76E", X"76E", X"76D", X"76D", X"76C", X"76C", X"76B",
X"76A", X"76A", X"769", X"768", X"768", X"767", X"766", X"765",
X"764", X"764", X"763", X"762", X"761", X"760", X"75F", X"75E",
X"75D", X"75C", X"75A", X"759", X"758", X"757", X"756", X"754",
X"753", X"752", X"750", X"74F", X"74E", X"74C", X"74B", X"749",
X"748", X"746", X"745", X"743", X"742", X"740", X"73E", X"73D",
X"73B", X"739", X"738", X"736", X"734", X"732", X"731", X"72F",
X"72D", X"72B", X"729", X"727", X"726", X"724", X"722", X"720",
X"71E", X"71C", X"71A", X"718", X"716", X"714", X"711", X"70F",
X"70D", X"70B", X"709", X"707", X"705", X"702", X"700", X"6FE",
X"6FC", X"6FA", X"6F7", X"6F5", X"6F3", X"6F1", X"6EE", X"6EC",
X"6E9", X"6E7", X"6E5", X"6E2", X"6E0", X"6DE", X"6DB", X"6D9",
X"6D6", X"6D4", X"6D2", X"6CF", X"6CD", X"6CA", X"6C8", X"6C5",
X"6C3", X"6C0", X"6BE", X"6BB", X"6B9", X"6B6", X"6B3", X"6B1",
X"6AF", X"6AC", X"6A9", X"6A7", X"6A4", X"6A2", X"69F", X"69C",
X"69A", X"697", X"695", X"692", X"690", X"68D", X"68A", X"688",
X"685", X"683", X"680", X"67D", X"67B", X"678", X"675", X"673",
X"670", X"66E", X"66B", X"668", X"666", X"663", X"660", X"65E",
X"65B", X"659", X"656", X"653", X"651", X"64E", X"64B", X"649",
X"646", X"643", X"641", X"63E", X"63C", X"639", X"637", X"634",
X"631", X"62F", X"62C", X"62A", X"627", X"624", X"622", X"61F",
X"61D", X"61A", X"618", X"615", X"613", X"610", X"60E", X"60B",
X"609", X"606", X"604", X"601", X"5FF", X"5FC", X"5FA", X"5F7",
X"5F5", X"5F2", X"5F0", X"5EE", X"5EB", X"5E9", X"5E6", X"5E4",
X"5E2", X"5DF", X"5DD", X"5DA", X"5D8", X"5D6", X"5D4", X"5D1",
X"5CF", X"5CD", X"5CA", X"5C8", X"5C6", X"5C4", X"5C1", X"5BF",
X"5BD", X"5BB", X"5B8", X"5B6", X"5B4", X"5B2", X"5B0", X"5AE",
X"5AB", X"5A9", X"5A7", X"5A5", X"5A3", X"5A1", X"59F", X"59D",
X"59B", X"599", X"597", X"595", X"593", X"591", X"58F", X"58D",
X"58B", X"589", X"587", X"585", X"583", X"581", X"57F", X"57E",
X"57C", X"57A", X"578", X"576", X"575", X"573", X"571", X"56F",
X"56E", X"56C", X"56A", X"568", X"567", X"565", X"563", X"562",
X"560", X"55F", X"55D", X"55B", X"55A", X"558", X"557", X"555",
X"554", X"552", X"551", X"54F", X"54E", X"54C", X"54B", X"549",
X"548", X"547", X"545", X"544", X"543", X"541", X"540", X"53F",
X"53D", X"53C", X"53B", X"539", X"538", X"537", X"536", X"535",
X"533", X"532", X"531", X"530", X"52F", X"52E", X"52C", X"52B",
X"52A", X"529", X"528", X"527", X"526", X"525", X"524", X"523",
X"522", X"521", X"520", X"51F", X"51E", X"51D", X"51C", X"51C",
X"51B", X"51A", X"519", X"518", X"517", X"516", X"516", X"515",
X"514", X"513", X"512", X"512", X"511", X"510", X"510", X"50F",
X"50E", X"50D", X"50D", X"50C", X"50B", X"50B", X"50A", X"509",
X"509", X"508", X"508", X"507", X"507", X"506", X"505", X"505",
X"504", X"504", X"503", X"503", X"502", X"502", X"501", X"501",
X"500", X"500", X"4FF", X"4FF", X"4FF", X"4FE", X"4FE", X"4FD",
X"4FD", X"4FD", X"4FC", X"4FC", X"4FB", X"4FB", X"4FB", X"4FA",
X"4FA", X"4FA", X"4F9", X"4F9", X"4F9", X"4F8", X"4F8", X"4F8",
X"4F7", X"4F7", X"4F7", X"4F7", X"4F6", X"4F6", X"4F6", X"4F6",
X"4F5", X"4F5", X"4F5", X"4F5", X"4F4", X"4F4", X"4F4", X"4F4",
X"4F3", X"4F3", X"4F3", X"4F3", X"4F3", X"4F2", X"4F2", X"4F2",
X"4F2", X"4F2", X"4F1", X"4F1", X"4F1", X"4F1", X"4F1", X"4F0",
X"4F0", X"4F0", X"4F0", X"4F0", X"4F0", X"4EF", X"4EF", X"4EF",
X"4EF", X"4EF", X"4EF", X"4EE", X"4EE", X"4EE", X"4EE", X"4EE",
X"4ED", X"4ED", X"4ED", X"4ED", X"4ED", X"4ED", X"4EC", X"4EC",
X"4EC", X"4EC", X"4EC", X"4EB", X"4EB", X"4EB", X"4EB", X"4EB",
X"4EA", X"4EA", X"4EA", X"4EA", X"4EA", X"4E9", X"4E9", X"4E9",
X"4E9", X"4E8", X"4E8", X"4E8", X"4E8", X"4E7", X"4E7", X"4E7",
X"4E6", X"4E6", X"4E6", X"4E6", X"4E5", X"4E5", X"4E5", X"4E4",
X"4E4", X"4E4", X"4E3", X"4E3", X"4E3", X"4E2", X"4E2", X"4E2",
X"4E1", X"4E1", X"4E0", X"4E0", X"4E0", X"4DF", X"4DF", X"4DE",
X"4DE", X"4DD", X"4DD", X"4DC", X"4DC", X"4DB", X"4DB", X"4DA",
X"4DA", X"4D9", X"4D9", X"4D8", X"4D8", X"4D7", X"4D7", X"4D6",
X"4D5", X"4D5", X"4D4", X"4D4", X"4D3", X"4D2", X"4D2", X"4D1",
X"4D0", X"4D0", X"4CF", X"4CE", X"4CD", X"4CD", X"4CC", X"4CB",
X"4CA", X"4CA", X"4C9", X"4C8", X"4C7", X"4C6", X"4C5", X"4C5",
X"4C4", X"4C3", X"4C2", X"4C1", X"4C0", X"4BF", X"4BE", X"4BD",
X"4BC", X"4BB", X"4BA", X"4B9", X"4B8", X"4B7", X"4B6", X"4B5",
X"4B4", X"4B3", X"4B2", X"4B0", X"4AF", X"4AE", X"4AD", X"4AC",
X"4AB", X"4A9", X"4A8", X"4A7", X"4A6", X"4A4", X"4A3", X"4A2",
X"4A0", X"49F", X"49E", X"49C", X"49B", X"49A", X"498", X"497",
X"495", X"494", X"492", X"491", X"48F", X"48E", X"48C", X"48B",
X"489", X"487", X"486", X"484", X"483", X"481", X"47F", X"47E",
X"47C", X"47A", X"478", X"477", X"475", X"473", X"471", X"46F",
X"46E", X"46C", X"46A", X"468", X"466", X"464", X"462", X"460",
X"45E", X"45C", X"45A", X"458", X"456", X"454", X"452", X"450",
X"44E", X"44C", X"44A", X"447", X"445", X"443", X"441", X"43F",
X"43D", X"43A", X"438", X"436", X"434", X"431", X"42F", X"42C",
X"42A", X"428", X"425", X"423", X"420", X"41E", X"41C", X"419",
X"416", X"414", X"412", X"40F", X"40C", X"40A", X"407", X"405",
X"402", X"3FF", X"3FD", X"3FA", X"3F7", X"3F5", X"3F2", X"3EF",
X"3EC", X"3EA", X"3E7", X"3E4", X"3E1", X"3DE", X"3DB", X"3D9",
X"3D6", X"3D3", X"3D0", X"3CD", X"3CA", X"3C7", X"3C4", X"3C1",
X"3BE", X"3BB", X"3B8", X"3B5", X"3B2", X"3AF", X"3AC", X"3A9",
X"3A6", X"3A3", X"39F", X"39C", X"399", X"396", X"393", X"38F",
X"38C", X"389", X"386", X"382", X"37F", X"37C", X"379", X"375",
X"372", X"36F", X"36B", X"368", X"364", X"361", X"35E", X"35A",
X"357", X"353", X"350", X"34C", X"349", X"345", X"342", X"33E",
X"33B", X"337", X"334", X"330", X"32C", X"329", X"325", X"322",
X"31E", X"31A", X"316", X"313", X"30F", X"30B", X"308", X"304",
X"300", X"2FD", X"2F9", X"2F5", X"2F1", X"2EE", X"2EA", X"2E6",
X"2E2", X"2DE", X"2DA", X"2D7", X"2D3", X"2CF", X"2CB", X"2C7",
X"2C4", X"2C0", X"2BC", X"2B8", X"2B4", X"2B0", X"2AC", X"2A8",
X"2A4", X"2A0", X"29C", X"298", X"294", X"290", X"28C", X"288",
X"284", X"280", X"27C", X"278", X"274", X"270", X"26C", X"268",
X"264", X"260", X"25C", X"258", X"254", X"250", X"24C", X"248",
X"243", X"23F", X"23B", X"237", X"233", X"22F", X"22B", X"227",
X"223", X"21E", X"21A", X"216", X"212", X"20E", X"20A", X"206",
X"202", X"1FD", X"1F9", X"1F5", X"1F1", X"1ED", X"1E8", X"1E4",
X"1E0", X"1DC", X"1D8", X"1D3", X"1D0", X"1CB", X"1C7", X"1C3",
X"1BF", X"1BB", X"1B6", X"1B2", X"1AE", X"1AA", X"1A6", X"1A1",
X"19D", X"199", X"195", X"191", X"18C", X"188", X"184", X"180",
X"17C", X"178", X"173", X"16F", X"16B", X"167", X"163", X"15E",
X"15A", X"156", X"152", X"14E", X"14A", X"145", X"141", X"13D",
X"139", X"135", X"130", X"12D", X"128", X"124", X"120", X"11C",
X"118", X"114", X"110", X"10C", X"108", X"103", X"0FF", X"0FB",
X"0F7", X"0F3", X"0EF", X"0EB", X"0E7", X"0E3", X"0DF", X"0DA",
X"0D7", X"0D3", X"0CE", X"0CA", X"0C7", X"0C3", X"0BE", X"0BA",
X"0B6", X"0B3", X"0AF", X"0AA", X"0A6", X"0A3", X"09F", X"09B",
X"097", X"093", X"08F", X"08B", X"087", X"083", X"07F", X"07C",
X"078", X"074", X"070", X"06C", X"068", X"064", X"061", X"05D",
X"059", X"055", X"052", X"04E", X"04A", X"046", X"042", X"03F",
X"03B", X"037", X"033", X"030", X"02C", X"029", X"025", X"021",
X"01E", X"01A", X"016", X"013", X"00F", X"00C", X"008", X"004",
X"001", X"FFD", X"FFA", X"FF6", X"FF3", X"FEF", X"FEC", X"FE8",
X"FE5", X"FE2", X"FDE", X"FDB", X"FD7", X"FD4", X"FD1", X"FCD",
X"FCA", X"FC7", X"FC3", X"FC0", X"FBD", X"FB9", X"FB6", X"FB3",
X"FAF", X"FAC", X"FA9", X"FA6", X"FA3", X"F9F", X"F9C", X"F99",
X"F96", X"F93", X"F90", X"F8D", X"F8A", X"F87", X"F84", X"F81",
X"F7E", X"F7A", X"F77", X"F75", X"F72", X"F6F", X"F6C", X"F69",
X"F66", X"F63", X"F60", X"F5D", X"F5A", X"F58", X"F55", X"F52",
X"F4F", X"F4C", X"F4A", X"F47", X"F44", X"F42", X"F3F", X"F3C",
X"F3A", X"F37", X"F34", X"F31", X"F2F", X"F2C", X"F2A", X"F27",
X"F25", X"F22", X"F20", X"F1D", X"F1B", X"F18", X"F16", X"F13",
X"F11", X"F0F", X"F0C", X"F0A", X"F07", X"F05", X"F03", X"F01",
X"EFE", X"EFC", X"EFA", X"EF8", X"EF5", X"EF3", X"EF1", X"EEF",
X"EED", X"EEB", X"EE9", X"EE6", X"EE4", X"EE2", X"EE0", X"EDE",
X"EDC", X"EDA", X"ED8", X"ED6", X"ED4", X"ED2", X"ED0", X"ECF",
X"ECD", X"ECB", X"EC9", X"EC7", X"EC5", X"EC4", X"EC2", X"EC0",
X"EBE", X"EBD", X"EBB", X"EB9", X"EB7", X"EB6", X"EB4", X"EB2",
X"EB1", X"EAF", X"EAE", X"EAC", X"EAA", X"EA9", X"EA8", X"EA6",
X"EA4", X"EA3", X"EA2", X"EA0", X"E9F", X"E9D", X"E9C", X"E9B",
X"E99", X"E98", X"E97", X"E95", X"E94", X"E93", X"E92", X"E90",
X"E8F", X"E8E", X"E8D", X"E8C", X"E8A", X"E89", X"E88", X"E87",
X"E86", X"E85", X"E84", X"E83", X"E82", X"E81", X"E80", X"E7F",
X"E7E", X"E7D", X"E7C", X"E7B", X"E7A", X"E79", X"E79", X"E78",
X"E77", X"E76", X"E75", X"E74", X"E74", X"E73", X"E72", X"E72",
X"E71", X"E70", X"E70", X"E6F", X"E6E", X"E6E", X"E6D", X"E6C",
X"E6C", X"E6B", X"E6B", X"E6A", X"E6A", X"E69", X"E69", X"E68",
X"E68", X"E67", X"E67", X"E66", X"E66", X"E66", X"E65", X"E65",
X"E65", X"E64", X"E64", X"E64", X"E63", X"E63", X"E63", X"E63",
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X"E67", X"E68", X"E68", X"E69", X"E69", X"E6A", X"E6A", X"E6A",
X"E6B", X"E6B", X"E6C", X"E6C", X"E6D", X"E6E", X"E6E", X"E6F",
X"E6F", X"E70", X"E70", X"E71", X"E72", X"E72", X"E73", X"E73",
X"E74", X"E75", X"E75", X"E76", X"E77", X"E77", X"E78", X"E79",
X"E7A", X"E7A", X"E7B", X"E7C", X"E7D", X"E7D", X"E7E", X"E7F",
X"E80", X"E81", X"E81", X"E82", X"E83", X"E84", X"E85", X"E86",
X"E86", X"E87", X"E88", X"E89", X"E8A", X"E8B", X"E8C", X"E8D",
X"E8E", X"E8E", X"E8F", X"E90", X"E91", X"E92", X"E93", X"E94",
X"E95", X"E96", X"E97", X"E98", X"E99", X"E9A", X"E9B", X"E9C",
X"E9D", X"E9E", X"E9F", X"EA0", X"EA2", X"EA3", X"EA4", X"EA5",
X"EA6", X"EA7", X"EA8", X"EA9", X"EAA", X"EAB", X"EAD", X"EAE",
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X"EC2", X"EC3", X"EC4", X"EC5", X"EC6", X"EC8", X"EC9", X"ECA",
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X"EF5", X"EF6", X"EF7", X"EF8", X"EFA", X"EFB", X"EFC", X"EFE",
X"EFF", X"F00", X"F02", X"F03", X"F04", X"F06", X"F07", X"F08",
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X"F14", X"F16", X"F17", X"F19", X"F1A", X"F1B", X"F1C", X"F1E",
X"F1F", X"F20", X"F22", X"F23", X"F25", X"F26", X"F27", X"F29",
X"F2A", X"F2B", X"F2C", X"F2E", X"F2F", X"F31", X"F32", X"F33",
X"F34", X"F36", X"F37", X"F38", X"F3A", X"F3B", X"F3C", X"F3E",
X"F3F", X"F40", X"F42", X"F43", X"F44", X"F46", X"F47", X"F48",
X"F49", X"F4B", X"F4C", X"F4D", X"F4F", X"F50", X"F51", X"F52",
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X"F5E", X"F5F", X"F60", X"F62", X"F63", X"F64", X"F65", X"F66",
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X"F71", X"F73", X"F74", X"F75", X"F76", X"F77", X"F79", X"F7A",
X"F7B", X"F7C", X"F7D", X"F7E", X"F80", X"F81", X"F82", X"F83",
X"F84", X"F85", X"F86", X"F88", X"F89", X"F8A", X"F8B", X"F8C",
X"F8D", X"F8E", X"F8F", X"F90", X"F92", X"F93", X"F94", X"F95",
X"F96", X"F97", X"F98", X"F99", X"F9A", X"F9B", X"F9C", X"F9D",
X"F9E", X"F9F", X"FA0", X"FA1", X"FA2", X"FA3", X"FA4", X"FA5",
X"FA6", X"FA7", X"FA8", X"FA9", X"FAA", X"FAB", X"FAC", X"FAD",
X"FAE", X"FAF", X"FB0", X"FB1", X"FB2", X"FB3", X"FB4", X"FB5",
X"FB6", X"FB7", X"FB7", X"FB8", X"FB9", X"FBA", X"FBB", X"FBC",
X"FBD", X"FBE", X"FBF", X"FBF", X"FC0", X"FC1", X"FC2", X"FC3",
X"FC4", X"FC4", X"FC5", X"FC6", X"FC7", X"FC8", X"FC9", X"FC9",
X"FCA", X"FCB", X"FCC", X"FCC", X"FCD", X"FCE", X"FCF", X"FCF",
X"FD0", X"FD1", X"FD2", X"FD2", X"FD3", X"FD4", X"FD4", X"FD5",
X"FD6", X"FD7", X"FD7", X"FD8", X"FD9", X"FD9", X"FDA", X"FDB",
X"FDB", X"FDC", X"FDC", X"FDD", X"FDE", X"FDE", X"FDF", X"FE0",
X"FE0", X"FE1", X"FE1", X"FE2", X"FE3", X"FE3", X"FE4", X"FE4",
X"FE5", X"FE5", X"FE6", X"FE7", X"FE7", X"FE8", X"FE8", X"FE9",
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X"0A1", X"0A2", X"0A4", X"0A5", X"0A6", X"0A7", X"0A9", X"0AA",
X"0AB", X"0AD", X"0AE", X"0AF", X"0B0", X"0B2", X"0B3", X"0B4",
X"0B6", X"0B7", X"0B8", X"0B9", X"0BB", X"0BC", X"0BD", X"0BF",
X"0C0", X"0C1", X"0C3", X"0C4", X"0C5", X"0C7", X"0C8", X"0C9",
X"0CB", X"0CC", X"0CD", X"0CE", X"0D0", X"0D1", X"0D3", X"0D4",
X"0D5", X"0D6", X"0D8", X"0D9", X"0DA", X"0DC", X"0DD", X"0DF",
X"0E0", X"0E1", X"0E3", X"0E4", X"0E5", X"0E6", X"0E8", X"0E9",
X"0EB", X"0EC", X"0ED", X"0EF", X"0F0", X"0F1", X"0F3", X"0F4",
X"0F5", X"0F7", X"0F8", X"0F9", X"0FB", X"0FC", X"0FD", X"0FF",
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X"D9B", X"D97", X"D93", X"D8F", X"D8B", X"D87", X"D83", X"D7F",
X"D7B", X"D77", X"D73", X"D6F", X"D6B", X"D67", X"D63", X"D5F",
X"D5B", X"D57", X"D53", X"D4F", X"D4B", X"D47", X"D43", X"D3F",
X"D3B", X"D38", X"D34", X"D30", X"D2C", X"D28", X"D25", X"D21",
X"D1D", X"D19", X"D15", X"D11", X"D0E", X"D0A", X"D06", X"D02",
X"CFF", X"CFB", X"CF7", X"CF4", X"CF0", X"CEC", X"CE9", X"CE5",
X"CE1", X"CDD", X"CDA", X"CD6", X"CD3", X"CCF", X"CCB", X"CC8",
X"CC4", X"CC1", X"CBD", X"CBA", X"CB6", X"CB3", X"CAF", X"CAC",
X"CA8", X"CA5", X"CA1", X"C9E", X"C9B", X"C97", X"C94", X"C90",
X"C8D", X"C8A", X"C86", X"C83", X"C80", X"C7D", X"C79", X"C76",
X"C73", X"C70", X"C6C", X"C69", X"C66", X"C63", X"C60", X"C5C",
X"C59", X"C56", X"C53", X"C50", X"C4D", X"C4A", X"C47", X"C44",
X"C41", X"C3E", X"C3B", X"C38", X"C35", X"C32", X"C2F", X"C2C",
X"C29", X"C26", X"C24", X"C21", X"C1E", X"C1B", X"C18", X"C15",
X"C13", X"C10", X"C0D", X"C0A", X"C08", X"C05", X"C02", X"C00",
X"BFD", X"BFA", X"BF8", X"BF5", X"BF3", X"BF0", X"BED", X"BEB",
X"BE9", X"BE6", X"BE3", X"BE1", X"BDF", X"BDC", X"BDA", X"BD7",
X"BD5", X"BD3", X"BD0", X"BCE", X"BCB", X"BC9", X"BC7", X"BC5",
X"BC2", X"BC0", X"BBE", X"BBC", X"BBA", X"BB8", X"BB5", X"BB3",
X"BB1", X"BAF", X"BAD", X"BAB", X"BA9", X"BA7", X"BA5", X"BA3",
X"BA1", X"B9F", X"B9D", X"B9B", X"B99", X"B97", X"B95", X"B93",
X"B91", X"B90", X"B8E", X"B8C", X"B8A", X"B88", X"B87", X"B85",
X"B83", X"B81", X"B80", X"B7E", X"B7C", X"B7B", X"B79", X"B78",
X"B76", X"B74", X"B73", X"B71", X"B70", X"B6E", X"B6D", X"B6B",
X"B6A", X"B68", X"B67", X"B65", X"B64", X"B63", X"B61", X"B60",
X"B5F", X"B5D", X"B5C", X"B5B", X"B59", X"B58", X"B57", X"B56",
X"B54", X"B53", X"B52", X"B51", X"B50", X"B4F", X"B4D", X"B4C",
X"B4B", X"B4A", X"B49", X"B48", X"B47", X"B46", X"B45", X"B44",
X"B43", X"B42", X"B41", X"B40", X"B3F", X"B3E", X"B3D", X"B3C",
X"B3B", X"B3A", X"B3A", X"B39", X"B38", X"B37", X"B36", X"B35",
X"B35", X"B34", X"B33", X"B32", X"B32", X"B31", X"B30", X"B2F",
X"B2F", X"B2E", X"B2D", X"B2D", X"B2C", X"B2B", X"B2B", X"B2A",
X"B2A", X"B29", X"B28", X"B28", X"B27", X"B27", X"B26", X"B26",
X"B25", X"B25", X"B24", X"B24", X"B23", X"B23", X"B22", X"B22",
X"B21", X"B21", X"B20", X"B20", X"B1F", X"B1F", X"B1F", X"B1E",
X"B1E", X"B1D", X"B1D", X"B1D", X"B1C", X"B1C", X"B1C", X"B1B",
X"B1B", X"B1B", X"B1A", X"B1A", X"B1A", X"B19", X"B19", X"B19",
X"B19", X"B18", X"B18", X"B18", X"B17", X"B17", X"B17", X"B17",
X"B16", X"B16", X"B16", X"B16", X"B15", X"B15", X"B15", X"B15",
X"B15", X"B14", X"B14", X"B14", X"B14", X"B14", X"B13", X"B13",
X"B13", X"B13", X"B13", X"B12", X"B12", X"B12", X"B12", X"B12",
X"B12", X"B11", X"B11", X"B11", X"B11", X"B11", X"B10", X"B10",
X"B10", X"B10", X"B10", X"B10", X"B0F", X"B0F", X"B0F", X"B0F",
X"B0F", X"B0F", X"B0E", X"B0E", X"B0E", X"B0E", X"B0E", X"B0D",
X"B0D", X"B0D", X"B0D", X"B0D", X"B0C", X"B0C", X"B0C", X"B0C",
X"B0C", X"B0B", X"B0B", X"B0B", X"B0B", X"B0A", X"B0A", X"B0A",
X"B0A", X"B09", X"B09", X"B09", X"B09", X"B08", X"B08", X"B08",
X"B08", X"B07", X"B07", X"B07", X"B06", X"B06", X"B06", X"B05",
X"B05", X"B05", X"B04", X"B04", X"B04", X"B03", X"B03", X"B02",
X"B02", X"B02", X"B01", X"B01", X"B00", X"B00", X"B00", X"AFF",
X"AFF", X"AFE", X"AFE", X"AFD", X"AFD", X"AFC", X"AFC", X"AFB",
X"AFB", X"AFA", X"AFA", X"AF9", X"AF8", X"AF8", X"AF7", X"AF7",
X"AF6", X"AF6", X"AF5", X"AF4", X"AF4", X"AF3", X"AF2", X"AF2",
X"AF1", X"AF0", X"AEF", X"AEF", X"AEE", X"AED", X"AED", X"AEC",
X"AEB", X"AEA", X"AE9", X"AE9", X"AE8", X"AE7", X"AE6", X"AE5",
X"AE4", X"AE3", X"AE3", X"AE2", X"AE1", X"AE0", X"ADF", X"ADE",
X"ADD", X"ADC", X"ADB", X"ADA", X"AD9", X"AD8", X"AD7", X"AD6",
X"AD5", X"AD4", X"AD3", X"AD1", X"AD0", X"ACF", X"ACE", X"ACD",
X"ACC", X"ACA", X"AC9", X"AC8", X"AC7", X"AC6", X"AC4", X"AC3",
X"AC2", X"AC0", X"ABF", X"ABE", X"ABC", X"ABB", X"ABA", X"AB8",
X"AB7", X"AB6", X"AB4", X"AB3", X"AB1", X"AB0", X"AAE", X"AAD",
X"AAB", X"AAA", X"AA8", X"AA7", X"AA5", X"AA4", X"AA2", X"AA0",
X"A9F", X"A9D", X"A9C", X"A9A", X"A98", X"A97", X"A95", X"A93",
X"A91", X"A90", X"A8E", X"A8C", X"A8A", X"A89", X"A87", X"A85",
X"A83", X"A81", X"A80", X"A7E", X"A7C", X"A7A", X"A78", X"A76",
X"A74", X"A72", X"A70", X"A6E", X"A6C", X"A6A", X"A68", X"A66",
X"A64", X"A62", X"A60", X"A5E", X"A5C", X"A5A", X"A58", X"A56",
X"A54", X"A51", X"A4F", X"A4D", X"A4B", X"A49", X"A47", X"A44",
X"A42", X"A40", X"A3E", X"A3B", X"A39", X"A37", X"A35", X"A32",
X"A30", X"A2E", X"A2B", X"A29", X"A27", X"A25", X"A22", X"A20",
X"A1D", X"A1B", X"A19", X"A16", X"A14", X"A11", X"A0F", X"A0D",
X"A0A", X"A08", X"A05", X"A03", X"A00", X"9FE", X"9FB", X"9F9",
X"9F6", X"9F4", X"9F1", X"9EF", X"9EC", X"9EA", X"9E7", X"9E5",
X"9E2", X"9E0", X"9DD", X"9DB", X"9D8", X"9D5", X"9D3", X"9D0",
X"9CE", X"9CB", X"9C8", X"9C6", X"9C3", X"9C1", X"9BE", X"9BC",
X"9B9", X"9B6", X"9B4", X"9B1", X"9AE", X"9AC", X"9A9", X"9A6",
X"9A4", X"9A1", X"99F", X"99C", X"999", X"997", X"994", X"991",
X"98F", X"98C", X"98A", X"987", X"984", X"982", X"97F", X"97C",
X"97A", X"977", X"975", X"972", X"96F", X"96D", X"96A", X"968",
X"965", X"963", X"960", X"95D", X"95B", X"958", X"956", X"953",
X"950", X"94E", X"94C", X"949", X"946", X"944", X"941", X"93F",
X"93C", X"93A", X"937", X"935", X"932", X"930", X"92D", X"92B",
X"929", X"926", X"924", X"921", X"91F", X"91D", X"91A", X"918",
X"916", X"913", X"911", X"90E", X"90C", X"90A", X"908", X"905",
X"903", X"901", X"8FF", X"8FD", X"8FA", X"8F8", X"8F6", X"8F4",
X"8F2", X"8F0", X"8EE", X"8EB", X"8E9", X"8E7", X"8E5", X"8E3",
X"8E1", X"8DF", X"8DD", X"8DB", X"8D9", X"8D8", X"8D6", X"8D4",
X"8D2", X"8D0", X"8CE", X"8CD", X"8CB", X"8C9", X"8C7", X"8C6",
X"8C4", X"8C2", X"8C1", X"8BF", X"8BD", X"8BC", X"8BA", X"8B9",
X"8B7", X"8B6", X"8B4", X"8B3", X"8B1", X"8B0", X"8AF", X"8AD",
X"8AC", X"8AB", X"8A9", X"8A8", X"8A7", X"8A6", X"8A5", X"8A3",
X"8A2", X"8A1", X"8A0", X"89F", X"89E", X"89D", X"89C", X"89B",
X"89B", X"89A", X"899", X"898", X"897", X"897", X"896", X"895",
X"895", X"894", X"893", X"893", X"892", X"892", X"891", X"891",
X"891", X"890", X"890", X"890", X"88F", X"88F", X"88F", X"88F",
X"88F", X"88F", X"88F", X"88F", X"88F", X"88F", X"88F", X"88F",
X"88F", X"88F", X"890", X"890", X"890", X"890", X"891", X"891",
X"892", X"892", X"893", X"893", X"894", X"895", X"895", X"896",
X"897", X"898", X"898", X"899", X"89A", X"89B", X"89C", X"89D",
X"89E", X"89F", X"8A1", X"8A2", X"8A3", X"8A4", X"8A6", X"8A7",
X"8A8", X"8AA", X"8AB", X"8AD", X"8AF", X"8B0", X"8B2", X"8B3",
X"8B5", X"8B7", X"8B9", X"8BB", X"8BD", X"8BE", X"8C0", X"8C3",
X"8C5", X"8C7", X"8C9", X"8CB", X"8CD", X"8D0", X"8D2", X"8D4",
X"8D7", X"8D9", X"8DC", X"8DE", X"8E1", X"8E4", X"8E6", X"8E9",
X"8EC", X"8EF", X"8F2", X"8F5", X"8F8", X"8FB", X"8FE", X"901",
X"904", X"907", X"90A", X"90E", X"911", X"914", X"918", X"91B",
X"91F", X"922", X"926", X"92A", X"92D", X"931", X"935", X"939",
X"93C", X"940", X"944", X"949", X"94C", X"951", X"955", X"959",
X"95D", X"961", X"966", X"96A", X"96F", X"973", X"978", X"97C",
X"981", X"985", X"98A", X"98F", X"994", X"999", X"99D", X"9A3",
X"9A8", X"9AD", X"9B1", X"9B7", X"9BC", X"9C1", X"9C6", X"9CC",
X"9D1", X"9D7", X"9DC", X"9E1", X"9E7", X"9ED", X"9F2", X"9F8",
X"9FD", X"A03", X"A09", X"A0F", X"A15", X"A1B", X"A21", X"A26",
X"A2D", X"A33", X"A39", X"A40", X"A45", X"A4C", X"A52", X"A59",
X"A5F", X"A65", X"A6C", X"A73", X"A79", X"A7F", X"A86", X"A8D",
X"A93", X"A9A", X"AA1", X"AA8", X"AAF", X"AB6", X"ABD", X"AC4",
X"ACC", X"AD2", X"AD9", X"AE1", X"AE8", X"AEF", X"AF7", X"AFE",
X"B06", X"B0D", X"B14", X"B1C", X"B24", X"B2B", X"B32", X"B3A",
X"B42", X"B4A", X"B51", X"B59", X"B61", X"B6A", X"B71", X"B79",
X"B81", X"B89", X"B92", X"B99", X"BA2", X"BAA", X"BB2", X"BBA",
X"BC3", X"BCB", X"BD4", X"BDB", X"BE4", X"BED", X"BF5", X"BFE",
X"C06", X"C0F", X"C18", X"C21", X"C29", X"C32", X"C3B", X"C44",
X"C4C", X"C55", X"C5E", X"C67", X"C6F", X"C79", X"C82", X"C8B",
X"C94", X"C9D", X"CA6", X"CAF", X"CB9", X"CC1", X"CCB", X"CD4",
X"CDE", X"CE6", X"CF0", X"CFA", X"D03", X"D0D", X"D15", X"D1F",
X"D29", X"D33", X"D3B", X"D45", X"D4F", X"D59", X"D62", X"D6C",
X"D76", X"D7F", X"D88", X"D92", X"D9C", X"DA6", X"DB0", X"DBA",
X"DC4", X"DCE", X"DD8", X"DE1", X"DEB", X"DF5", X"DFF", X"E09",
X"E13", X"E1D", X"E27", X"E32", X"E3B", X"E45", X"E4F", X"E5A",
X"E63", X"E6E", X"E78", X"E82", X"E8C", X"E96", X"EA0", X"EAB",
X"EB4", X"EBF", X"EC9", X"ED4", X"EDE", X"EE8", X"EF2", X"EFD",
X"F07", X"F11", X"F1B", X"F26", X"F30", X"F3A", X"F45", X"F4F",
X"F5A", X"F64", X"F6E", X"F78", X"F83", X"F8E", X"F97", X"FA2",
X"FAD", X"FB7", X"FC1", X"FCB", X"FD6", X"FE1", X"FEA", X"FF5"
);
signal data : std_logic_vector(31 downto 0);
signal unsignedIndex : unsigned(11 downto 0) := X"000";
begin
rom_select: process (clk, en)
begin
if (rising_edge(clk)) then
if (en = '1') then
unsignedIndex <= unsigned(address_reg);
data <= (SIN_ROM(to_integer(unsignedIndex)) & x"00000");
sin_out <= std_logic_vector(shift_right(signed(data), 20));
end if;
end if;
end process rom_select;
end rtl;
|
-- file Bcdfreq_v1_0.vhd
-- Bcdfreq_v1_0 module implementation
-- author: <NAME>
-- copyright: (C) 2020 MPSI Technologies GmbH
-- date created: 6 Jan 2020
-- date modified: 4 Feb 2020
-- IP header --- ABOVE
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Bcdfreq_v1_0 is
generic (
fMclk: natural range 1 to 1000000 := 50000
);
port (
reset: in std_logic;
mclk: in std_logic;
high: in std_logic_vector(3 downto 0);
low: in std_logic_vector(3 downto 0);
freq: out std_logic
);
end Bcdfreq_v1_0;
architecture Bcdfreq_v1_0 of Bcdfreq_v1_0 is
------------------------------------------------------------------------
-- signal declarations
------------------------------------------------------------------------
---- main operation (op)
type stateOp_t is (
stateOpInit,
stateOpLoad,
stateOpTen,
stateOpOne
);
signal stateOp: stateOp_t := stateOpInit;
signal freq_sig: std_logic;
begin
------------------------------------------------------------------------
-- implementation: main operation (op)
------------------------------------------------------------------------
freq <= freq_sig;
process (reset, mclk)
constant imax: natural := fMclk/100/2; -- 5us wait for tens
variable i: natural range 0 to imax; -- tens
constant jmax: natural := fMclk/1000/2; -- 500ns wait for ones
variable j: natural range 0 to jmax; -- ones
variable high_lcl, low_lcl: std_logic_vector(3 downto 0);
variable ten: natural range 0 to 15; -- ensure compatibility with (wrong) BCD values A..F
variable one: natural range 0 to 15;
begin
if reset='1' then
stateOp <= stateOpInit;
freq_sig <= '0';
i := 0;
j := 0;
high_lcl := (others => '0');
low_lcl := (others => '0');
ten := 0;
one := 0;
elsif rising_edge(mclk) then
if stateOp=stateOpInit then
freq_sig <= '0';
i := 0;
j := 0;
high_lcl := (others => '0');
low_lcl := (others => '0');
ten := 0;
one := 0;
stateOp <= stateOpLoad;
elsif stateOp=stateOpLoad then
freq_sig <= '0';
high_lcl := high;
low_lcl := low;
if (high_lcl/="0000" or low_lcl/="0000") then
i := 0;
ten := 0;
stateOp <= stateOpTen;
end if;
elsif stateOp=stateOpTen then
if ten >= to_integer(unsigned(high_lcl)) then
j := 0;
one := 0;
stateOp <= stateOpOne;
else
i := i + 1;
if i=imax then
i := 0;
ten := ten + 1;
end if;
end if;
elsif stateOp=stateOpOne then
if one >= to_integer(unsigned(low_lcl)) then
if freq_sig='0' then
freq_sig <= '1';
i := 0;
ten := 0;
stateOp <= stateOpTen;
else
stateOp <= stateOpLoad;
end if;
else
j := j + 1;
if j=jmax then
j := 0;
one := one + 1;
end if;
end if;
end if;
end if;
end process;
end Bcdfreq_v1_0;
|
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
-- Date : Sat Jul 10 22:22:43 2021
-- Host : FCXiaoXin running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ prgrom_sim_netlist.vhdl
-- Design : prgrom
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tfgg484-1
-- --------------------------------------------------------------------------------
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<KEY>
R//<KEY>
`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "prgrom,blk_mem_gen_v8_4_4,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_4_4,Vivado 2021.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "14";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 13.776802 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "prgrom.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "prgrom.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 16384;
attribute C_READ_LATENCY_A : integer;
attribute C_READ_LATENCY_A of U0 : label is 1;
attribute C_READ_LATENCY_B : integer;
attribute C_READ_LATENCY_B of U0 : label is 1;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute is_du_within_envelope : string;
attribute is_du_within_envelope of U0 : label is "true";
attribute x_interface_info : string;
attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_4_4
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => B"00000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => B"00000000000000000000000000000000",
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => NLW_U0_doutb_UNCONNECTED(31 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date : Tue Aug 11 14:15:45 2020
-- Host : DESKTOP-AUBSA4O running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top design_1_c_counter_binary_0_0 -prefix
-- design_1_c_counter_binary_0_0_ design_1_c_counter_binary_0_0_sim_netlist.vhdl
-- Design : design_1_c_counter_binary_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
`protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
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`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
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`protect key_block
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`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Synplicity", key_keyname="<KEY>", key_method="rsa"
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 29056)
`protect data_block
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 is
port (
CLK : in STD_LOGIC;
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
SSET : in STD_LOGIC;
SINIT : in STD_LOGIC;
UP : in STD_LOGIC;
LOAD : in STD_LOGIC;
L : in STD_LOGIC_VECTOR ( 31 downto 0 );
THRESH0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_AINIT_VAL : string;
attribute C_AINIT_VAL of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is "0";
attribute C_CE_OVERRIDES_SYNC : integer;
attribute C_CE_OVERRIDES_SYNC of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 0;
attribute C_COUNT_BY : string;
attribute C_COUNT_BY of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is "1";
attribute C_COUNT_MODE : integer;
attribute C_COUNT_MODE of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 0;
attribute C_COUNT_TO : string;
attribute C_COUNT_TO of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is "1";
attribute C_FB_LATENCY : integer;
attribute C_FB_LATENCY of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 0;
attribute C_HAS_LOAD : integer;
attribute C_HAS_LOAD of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 0;
attribute C_HAS_SINIT : integer;
attribute C_HAS_SINIT of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 0;
attribute C_HAS_SSET : integer;
attribute C_HAS_SSET of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 0;
attribute C_HAS_THRESH0 : integer;
attribute C_HAS_THRESH0 of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 0;
attribute C_IMPLEMENTATION : integer;
attribute C_IMPLEMENTATION of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 1;
attribute C_LOAD_LOW : integer;
attribute C_LOAD_LOW of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 0;
attribute C_RESTRICT_COUNT : integer;
attribute C_RESTRICT_COUNT of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 0;
attribute C_SCLR_OVERRIDES_SSET : integer;
attribute C_SCLR_OVERRIDES_SSET of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 1;
attribute C_SINIT_VAL : string;
attribute C_SINIT_VAL of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is "0";
attribute C_THRESH0_VALUE : string;
attribute C_THRESH0_VALUE of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is "1";
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 0;
attribute C_WIDTH : integer;
attribute C_WIDTH of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 : entity is "yes";
end design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13;
architecture STRUCTURE of design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13 is
signal \<const1>\ : STD_LOGIC;
signal NLW_i_synth_THRESH0_UNCONNECTED : STD_LOGIC;
attribute C_AINIT_VAL of i_synth : label is "0";
attribute C_CE_OVERRIDES_SYNC of i_synth : label is 0;
attribute C_FB_LATENCY of i_synth : label is 0;
attribute C_HAS_CE of i_synth : label is 0;
attribute C_HAS_SCLR of i_synth : label is 0;
attribute C_HAS_SINIT of i_synth : label is 0;
attribute C_HAS_SSET of i_synth : label is 0;
attribute C_IMPLEMENTATION of i_synth : label is 0;
attribute C_SCLR_OVERRIDES_SSET of i_synth : label is 1;
attribute C_SINIT_VAL of i_synth : label is "0";
attribute C_VERBOSITY of i_synth : label is 0;
attribute C_WIDTH of i_synth : label is 32;
attribute C_XDEVICEFAMILY of i_synth : label is "zynq";
attribute c_count_by of i_synth : label is "1";
attribute c_count_mode of i_synth : label is 0;
attribute c_count_to of i_synth : label is "1";
attribute c_has_load of i_synth : label is 0;
attribute c_has_thresh0 of i_synth : label is 0;
attribute c_latency of i_synth : label is 1;
attribute c_load_low of i_synth : label is 0;
attribute c_restrict_count of i_synth : label is 0;
attribute c_thresh0_value of i_synth : label is "1";
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
begin
THRESH0 <= \<const1>\;
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
i_synth: entity work.design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13_viv
port map (
CE => '0',
CLK => CLK,
L(31 downto 0) => B"00000000000000000000000000000000",
LOAD => '0',
Q(31 downto 0) => Q(31 downto 0),
SCLR => '0',
SINIT => '0',
SSET => '0',
THRESH0 => NLW_i_synth_THRESH0_UNCONNECTED,
UP => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_c_counter_binary_0_0 is
port (
CLK : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of design_1_c_counter_binary_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of design_1_c_counter_binary_0_0 : entity is "design_1_c_counter_binary_0_0,c_counter_binary_v12_0_13,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of design_1_c_counter_binary_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of design_1_c_counter_binary_0_0 : entity is "c_counter_binary_v12_0_13,Vivado 2019.1";
end design_1_c_counter_binary_0_0;
architecture STRUCTURE of design_1_c_counter_binary_0_0 is
signal NLW_U0_THRESH0_UNCONNECTED : STD_LOGIC;
attribute C_AINIT_VAL : string;
attribute C_AINIT_VAL of U0 : label is "0";
attribute C_CE_OVERRIDES_SYNC : integer;
attribute C_CE_OVERRIDES_SYNC of U0 : label is 0;
attribute C_FB_LATENCY : integer;
attribute C_FB_LATENCY of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_SINIT : integer;
attribute C_HAS_SINIT of U0 : label is 0;
attribute C_HAS_SSET : integer;
attribute C_HAS_SSET of U0 : label is 0;
attribute C_IMPLEMENTATION : integer;
attribute C_IMPLEMENTATION of U0 : label is 0;
attribute C_SCLR_OVERRIDES_SSET : integer;
attribute C_SCLR_OVERRIDES_SSET of U0 : label is 1;
attribute C_SINIT_VAL : string;
attribute C_SINIT_VAL of U0 : label is "0";
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_WIDTH : integer;
attribute C_WIDTH of U0 : label is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute c_count_by : string;
attribute c_count_by of U0 : label is "1";
attribute c_count_mode : integer;
attribute c_count_mode of U0 : label is 0;
attribute c_count_to : string;
attribute c_count_to of U0 : label is "1";
attribute c_has_load : integer;
attribute c_has_load of U0 : label is 0;
attribute c_has_thresh0 : integer;
attribute c_has_thresh0 of U0 : label is 0;
attribute c_latency : integer;
attribute c_latency of U0 : label is 1;
attribute c_load_low : integer;
attribute c_load_low of U0 : label is 0;
attribute c_restrict_count : integer;
attribute c_restrict_count of U0 : label is 0;
attribute c_thresh0_value : string;
attribute c_thresh0_value of U0 : label is "1";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute x_interface_info : string;
attribute x_interface_info of CLK : signal is "xilinx.com:signal:clock:1.0 clk_intf CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of CLK : signal is "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF q_intf:thresh0_intf:l_intf:load_intf:up_intf:sinit_intf:sset_intf, ASSOCIATED_RESET SCLR, ASSOCIATED_CLKEN CE, FREQ_HZ 125000000, PHASE 0.0, CLK_DOMAIN design_1_clk_wiz_0_0_clk_out1, INSERT_VIP 0";
attribute x_interface_info of Q : signal is "xilinx.com:signal:data:1.0 q_intf DATA";
attribute x_interface_parameter of Q : signal is "XIL_INTERFACENAME q_intf, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value data} bitwidth {attribs {resolve_type generated dependency bitwidth format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} DATA_WIDTH 32}";
begin
U0: entity work.design_1_c_counter_binary_0_0_c_counter_binary_v12_0_13
port map (
CE => '1',
CLK => CLK,
L(31 downto 0) => B"00000000000000000000000000000000",
LOAD => '0',
Q(31 downto 0) => Q(31 downto 0),
SCLR => '0',
SINIT => '0',
SSET => '0',
THRESH0 => NLW_U0_THRESH0_UNCONNECTED,
UP => '1'
);
end STRUCTURE;
|
---------------------------------------------------------------------------------------------------
--! @Author: <NAME> <<EMAIL>>
--
--! @brief i2c master testbench for data acquisition from sensor
--! @details performs all the operatations required for data acquisitionas in the HDC1080
--! @details temperature and humidity sensor
--! @details
--
---------------------------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vunit_lib;
context vunit_lib.vunit_context;
entity i2c_master_data_tb is
generic (runner_cfg : string);
end i2c_master_data_tb;
architecture rtl of i2c_master_data_tb is
---------------------
-- user defined types
---------------------
type sensor_data_t is array (natural range <>) of std_logic_vector(7 downto 0);
------------
-- constants
------------
-- I2C slave address (pmod hygro)
constant C_I2C_SLAVE_ADDR : std_logic_vector(6 downto 0) := "1000000";
-- system clock period
constant C_CLK_SYS : time := 10.0 ns;
-- clock in Hz
constant C_CLK_100MHZ : integer := 10_000_000;
constant C_CLK_100KHZ : integer := 100_000;
-- slave address: 0x40 (TI, HDC1080 temperature/humidity sensor)
constant C_SLAVE_ADDR : std_logic_vector(6 downto 0) := "1000000";
constant C_SLAVE_BAD_ADDR : std_logic_vector(6 downto 0) := "1111010";
-- mode
constant C_MODE_WR : std_logic := '0';
constant C_MODE_RD : std_logic := '1';
-- data
constant C_WRITE_DATA : std_logic_vector(7 downto 0) := "00000000";
constant C_READ_DATA : std_logic_vector(7 downto 0) := "11001100";
constant C_SENSOR_DATA : sensor_data_t := (
X"66", -- temp. MSB
X"1C", -- temp. LSB
X"94", -- hum. MSB
X"07" -- hum. LSB
);
----------
-- signals
----------
-- reset signal, active high
signal s_rst : std_logic := '1';
-- i2c data and control
signal s_clk : std_logic := '0';
signal s_enable : std_logic := '0';
signal s_addr : std_logic_vector(6 downto 0) := (others => '0');
signal s_mode : std_logic := '0';
signal s_data_wr : std_logic_vector(7 downto 0) := (others => '0');
signal s_busy : std_logic;
signal s_data_rd : std_logic_vector(7 downto 0) := (others => '0');
signal s_ack_err : std_logic := '0';
signal s_scl : std_logic;
signal s_sda : std_logic;
-- sensor data
signal s_sensor_data : sensor_data_t(0 to 3) := (X"00", X"00", X"00", X"00");
begin
-----------------------
-- entity instantiation
-----------------------
master_100khz: entity work.i2c_master
generic map(
INPUT_CLK => C_CLK_100MHZ,
BUS_CLK => C_CLK_100KHZ,
DEBUG => TRUE
)
port map(
clk => s_clk,
reset => s_rst,
ena => s_enable,
addr => s_addr,
rw => s_mode,
data_wr => s_data_wr,
busy => s_busy,
data_rd => s_data_rd,
ack_error => s_ack_err,
sda => s_sda,
scl => s_scl
);
--------------------------
-- I2C Slave instantiation
--------------------------
i2c_slv: entity work.i2c_slave
generic map(
SLAVE_ADDRESS => C_I2C_SLAVE_ADDR
)
port map(
i_clk => s_clk,
i_rst => s_rst,
io_scl => s_scl,
io_sda => s_sda
);
------------------------------
-- generate sytem clock signal
------------------------------
clk_sys: process
begin
wait for C_CLK_SYS / 2;
s_clk <= not s_clk;
end process clk_sys;
-------------------------------------------
-- generate stimulus for the driver and dut
-- drivers the I2C Master
-------------------------------------------
stimulus: process
-----------------------
-- setup test case data
-----------------------
procedure setup(
constant address : in std_logic_vector(6 downto 0);
constant wdata : in std_logic_vector(7 downto 0);
constant mode : in std_logic) is
begin
s_enable <= '0';
s_addr <= address;
s_mode <= mode;
s_data_wr <= wdata;
end procedure setup;
--------------------
-- setup for reading
--------------------
procedure setup_read(
constant address : in std_logic_vector(6 downto 0)
) is
begin
s_enable <= '0';
s_addr <= address;
s_mode <= C_MODE_RD;
end procedure setup_read;
-------------
-- enable DUT
-------------
procedure set_enable(en : in std_logic) is
begin
s_enable <= en;
end procedure set_enable;
----------------------------
-- initialise and enable dut
----------------------------
procedure init_dut(clk_ticks : in natural) is
begin
s_rst <= '1';
wait for C_CLK_SYS * clk_ticks;
s_rst <= '0';
wait for C_CLK_SYS * clk_ticks;
s_enable <= '1';
end procedure init_dut;
procedure wait_not_busy is
begin
wait until s_busy = '0' or s_ack_err = '1';
end procedure wait_not_busy;
-------------------------------------------
-- wait until test case finishes
-- clk_ticks: number of clock ticks to wait
-------------------------------------------
procedure wait_done(clk_ticks : in natural) is
begin
wait until s_busy ='1';
wait for C_CLK_SYS * 5 * clk_ticks;
s_enable <= '0';
wait until s_busy = '0' or s_ack_err = '1';
wait for C_CLK_SYS * 20 * clk_ticks;
end procedure wait_done;
begin
test_runner_setup(runner, runner_cfg);
test_cases: while test_suite loop
if run("sensor_data_acquisition") then
info("----------------------------");
info("Test: sensor data acqisition");
info("----------------------------");
------------------
-- write operation
------------------
info("step 1: Request sensor data");
-- initial conditions
setup(C_SLAVE_ADDR, C_WRITE_DATA, C_MODE_WR);
-- initialiase dut
init_dut(5);
-- execute until it is done
wait_done(5);
info("Slave 0x10, Data 0x00 written");
wait for 100 us;
----------------
-- check results
----------------
check_equal(
s_ack_err,
'0',
result("for ACK")
);
-- TODO: check data written on slave
-- check_equal(
-- s_i2c_slave.in_data,
-- C_WRITE_DATA,
-- result("for data received on slave"));
-----------------
-- read operation
-----------------
info("step 2: read sensor data (4 bytes)");
-- setup
setup_read(C_SLAVE_ADDR);
set_enable('1');
for i in 0 to 3 loop
if i = 3 then
set_enable('0');
end if;
wait_not_busy;
info("sensor data read: " & to_hstring(s_data_rd));
s_sensor_data(i) <= s_data_rd;
end loop;
set_enable('0');
wait for 10 us;
--------------------
-- check sensor data
--------------------
for i in 0 to 3 loop
check_equal(
s_sensor_data(i),
C_SENSOR_DATA(i),
result("for sensor data")
);
end loop ;
----------------------
-- check for ACK error
----------------------
check_equal(
s_ack_err,
'0',
result("for ACK")
);
wait for 10 us;
info("------------------------------");
info("----- test case finished -----");
info("------------------------------");
end if;
end loop test_cases;
info("-----------------------------------");
info("End of testbench. All tests passed.");
info("-----------------------------------");
test_runner_cleanup(runner);
end process stimulus;
test_runner_watchdog(runner, 50 ms);
end architecture rtl;
|
----------------------------------------------------------------------------------
--Copyright 2020 <NAME>
--Licensed under the Apache License, Version 2.0 (the "License"); you may not
--use this file except in compliance with the License. You may obtain a copy of
--the License at
-- http://www.apache.org/licenses/LICENSE-2.0
--Unless required by applicable law or agreed to in writing, software distributed
--under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES
--OR CONDITIONS OF ANY KIND, either express or implied. See the License for
--the specific language governing permissions and limitations under the License.
----------------------------------------------------------------------------------
-- altera vhdl_input_version vhdl_2008
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library expert;
use expert.std_logic_gray.all;
library vunit_lib;
context vunit_lib.vunit_context;
entity std_logic_gray_tb is
generic (runner_cfg : string);
end std_logic_gray_tb;
architecture simulation of std_logic_gray_tb is
signal vector_unsigned : unsigned(7 downto 0) := x"55";
signal vector_signed : signed(7 downto 0) := x"f5";
signal vector_integer : integer := 32;
signal vector_svl : std_logic_vector(7 downto 0) := x"f5";
constant ONE_svl : std_logic_vector(7 downto 0) := (0 => '1', others => '0');
constant ZERO_svl : std_logic_vector(7 downto 0) := (others => '0');
constant TOP_svl : std_logic_vector(7 downto 0) := (others => '1');
signal test_tmp : boolean;
constant tmp_slice : std_logic_vector(23 downto 16) := x"05";
begin
main : process
variable tmp_svl1 : std_logic_vector(7 downto 0) := x"04";
variable tmp_svl2 : std_logic_vector(7 downto 0) := x"06";
variable tmp_gv : gray_vector(7 downto 0) := x"06";
variable tmp_int1 : integer := 4;
variable tmp_uns1 : unsigned(7 downto 0) := x"04";
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("Sanity check for system.") then
report "System Sane. Begin tests.";
check_true(true, result("Sanity check for system."));
elsif run("Testing gray_encoder(std_logic_vector)") then
check_equal( gray_encoder(tmp_svl1),tmp_svl2,result("gray_encoder(std_logic_vector)"));
elsif run("Testing gray_decoder(std_logic_vector)") then
check_equal( gray_decoder(tmp_svl2), tmp_svl1,result("gray_encoder(std_logic_vector)"));
elsif run("testing constant creation") then
tmp_gv := create_gray_vector("00000110");
for j in tmp_gv'range loop
check_equal(tmp_gv(j),tmp_svl2(j), result("create_gray_vector(00000110)"));
end loop;
check_equal(translate2svl(tmp_gv),tmp_svl2, result("translate2svl(tmp_gv)"));
elsif run("to_gray_vector(std_logic_vector)") then
info(to_string(tmp_svl1));
info(to_string(translate2svl(to_gray_vector(tmp_svl1))));
check_true(to_gray_vector(tmp_svl1) = tmp_gv,result("to_gray_vector(std_logic_vector)"));
elsif run("to_gray_vector(unsigned)") then
info(to_string(tmp_uns1));
info(to_string(translate2svl(to_gray_vector(tmp_uns1))));
check_true(to_gray_vector(tmp_uns1) = tmp_gv,result("to_gray_vector(unsigned)"));
elsif run("to_gray_vector(integer)") then
info(to_string(tmp_int1));
info(to_string(translate2svl(to_gray_vector(tmp_int1,8))));
check_true(to_gray_vector(tmp_int1,8) = tmp_gv,result("to_gray_vector(integer,integer)"));
elsif run("From gray_vector functions") then
check_true(to_std_logic_vector(tmp_gv) = tmp_svl1,result("to_unsigned(gray_vector)"));
check_true(to_unsigned(tmp_gv) = tmp_uns1,result("to_unsigned(gray_vector)"));
check_true(to_integer(tmp_gv) = tmp_int1,result("to_integer(gray_vector)"));
elsif run("Testing '+'") then
tmp_int1 := to_integer(tmp_gv + tmp_gv);
check_equal(tmp_int1,8,result("gray_vector + gray_vector"));
tmp_int1 := to_integer(tmp_gv + 4);
check_equal(tmp_int1,8,result("gray_vector + integer"));
tmp_int1 := to_integer(tmp_gv + tmp_uns1);
check_equal(tmp_int1,8,result("gray_vector + unsigned"));
tmp_int1 := to_integer(tmp_gv + tmp_svl1);
check_equal(tmp_int1,8,result("gray_vector + std_logic_vector"));
elsif run("Testing '-'") then
tmp_int1 := to_integer(tmp_gv - tmp_gv);
check_equal(tmp_int1,0,result("gray_vector - gray_vector"));
tmp_int1 := to_integer(tmp_gv - 4);
check_equal(tmp_int1,0,result("gray_vector - integer"));
tmp_int1 := to_integer(tmp_gv - tmp_uns1);
check_equal(tmp_int1,0,result("gray_vector - unsigned"));
tmp_int1 := to_integer(tmp_gv - tmp_svl1);
check_equal(tmp_int1,0,result("gray_vector - std_logic_vector"));
elsif run("Testing '*'") then
Info("Operator '*' not implemented for GALOIS_VECTOR");
elsif run("Testing '/'") then
Info("Operator '/' not implemented for GALOIS_VECTOR");
elsif run("Testing 'mod'") then
Info("Operator 'mod' not implemented for GALOIS_VECTOR");
elsif run("Testing 'rem'") then
Info("Operator 'rem' not implemented for GALOIS_VECTOR");
elsif run("Testing '='") then
check_true(tmp_gv = tmp_gv, result("std_logic_vector = integer"));
check_false(tmp_gv = (tmp_gv+1), result("std_logic_vector = integer."));
elsif run("Testing '/='") then
check_true(tmp_gv /= (tmp_gv+1), result("std_logic_vector /= integer"));
check_false(tmp_gv /= tmp_gv, result("std_logic_vector /= integer."));
elsif run("Testing '>'") then
check_true(tmp_gv+1 > tmp_gv, result("std_logic_vector > integer"));
check_false(tmp_gv > tmp_gv, result("std_logic_vector > integer."));
elsif run("Testing '<'") then
check_true(tmp_gv < tmp_gv+1, result("std_logic_vector < integer"));
check_false(tmp_gv < tmp_gv, result("std_logic_vector < integer."));
elsif run("Testing '<='") then
check_true(tmp_gv <= tmp_gv, result("std_logic_vector <= integer"));
check_false(tmp_gv+1 <= tmp_gv, result("std_logic_vector <= integer."));
elsif run("Testing '>='") then
check_true(tmp_gv >= tmp_gv, result("std_logic_vector >= integer"));
check_false(tmp_gv >= tmp_gv+1, result("std_logic_vector >= integer."));
elsif run("Testing 'rol'") then
Info("Operator 'rol' not implemented for GALOIS_VECTOR");
elsif run("Testing 'ror'") then
Info("Operator 'ror' not implemented for GALOIS_VECTOR");
end if;
end loop;
test_runner_cleanup(runner); -- Simulation ends here
end process;
end simulation;
|
<filename>vhdl/src/rf_blocks_tb/poly_dds_tb.vhd
--! @file poly_dds_tb.vhd
--! @brief Polyphase Direct Digital Synthesizer Testbench
--! @author <NAME> (<EMAIL>)
--! @date 2013-12-17
--! @copyright
--! Copyright 2013 <NAME>, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library boostdsp;
use boostdsp.fixed_pkg.all;
use boostdsp.util_pkg.all;
use boostdsp.rf_blocks_pkg;
--! Tests the boostdsp.dds entity.
entity poly_dds_tb is
end entity;
architecture sim of poly_dds_tb is
constant NUM_CHANNELS : positive := 16;
constant CH_MAX : positive := NUM_CHANNELS - 1;
constant clk_p : time := 10 ns;
constant clk_hp : time := clk_p / 2;
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal freq : ufixed(-1 downto -9) := to_ufixed(0.1, -1, -9);
signal phase : ufixed(-1 downto -9) := to_ufixed(0, -1, -9);
signal i_out : sfixed_vector(0 to CH_MAX)(1 downto -6);
signal q_out : sfixed_vector(0 to CH_MAX)(1 downto -6);
signal vis_i_out : signed_vector(0 to CH_MAX)(7 downto 0);
signal vis_q_out : signed_vector(0 to CH_MAX)(7 downto 0);
signal vis_combined_i : signed(7 downto 0);
signal vis_combined_q : signed(7 downto 0);
begin
--! Polyphase DDS Unit Under Test
uut: rf_blocks_pkg.poly_dds
port map(
clk => clk,
rst => rst,
freq => freq,
phase => phase,
i_out => i_out,
q_out => q_out
);
--! Clock generator
clk_proc : process
begin
wait for clk_hp;
clk <= not clk;
end process;
--! Reset generator
rst_proc : process
begin
wait for clk_p * 4;
rst <= '0';
wait;
end process;
--! Test the phase shifting input
phase_test_proc : process
begin
wait for clk_p * 20;
phase <= to_ufixed(0.2, phase);
wait for clk_p * 20;
phase <= to_ufixed(0.5, phase);
wait for clk_p * 20;
phase <= to_ufixed(0, phase);
wait;
end process;
--! Visualize all generated sinusoids
visualize : for i in i_out'range generate
vis_i_out(i) <= sfixed_as_signed(i_out(i));
vis_q_out(i) <= sfixed_as_signed(q_out(i));
end generate;
--! Upconvert and serialize all sinusoids to get high-speed sinusoids
visualize_combined : process
begin
wait until rising_edge(clk);
wait for clk_p / (i_out'length + 2);
while true loop
for i in i_out'range loop
vis_combined_i <= vis_i_out(i);
vis_combined_q <= vis_q_out(i);
wait for clk_p / i_out'length;
end loop;
end loop;
end process;
end sim;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RS_Read_Control is
Port ( Local_Tag : in STD_LOGIC_VECTOR (4 downto 0);
RS_Busy : in STD_LOGIC;
RS_Op : in STD_LOGIC_VECTOR (3 downto 0);
RS_Vj : in STD_LOGIC_VECTOR (31 downto 0);
RS_Qj : in STD_LOGIC_VECTOR (4 downto 0);
RS_Vk : in STD_LOGIC_VECTOR (31 downto 0);
RS_Qk : in STD_LOGIC_VECTOR (4 downto 0);
RS_Ready : out STD_LOGIC:= '0';
RS_Out : out STD_LOGIC_VECTOR (72 downto 0):= "0000000000000000000000000000000000000000000000000000000000000000000000000");
end RS_Read_Control;
architecture Behavioral of RS_Read_Control is
begin
process(RS_Busy, RS_Op, RS_Vj, RS_Qj, RS_Vk, RS_Qk)
begin
if RS_Qj = "00000" and RS_Qk = "00000" and RS_Busy = '1' then
RS_Ready <= '1';
RS_Out(72 downto 68) <= Local_Tag;
RS_Out(67 downto 64) <= RS_Op;
RS_Out(63 downto 32) <= RS_Vj;
RS_Out(31 downto 0) <= RS_Vk;
else
RS_Ready <= '0';
RS_Out <= "0000000000000000000000000000000000000000000000000000000000000000000000000";
end if;
end process;
end Behavioral;
|
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