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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DATAPATH is
generic (DATA_SIZE: integer;
RAM_ADDR_SIZE: integer;
LOCAL_ADDR_SIZE: integer;
RHFSM_MAIN_X_WIDTH: integer;
RHFSM_MAIN_Y_WIDTH: integer;
RHFSM_SEC_X_WIDTH: integer;
RHFSM_SEC_Y_WIDTH: integer);
port (clk, rst: in STD_LOGIC;
XM: out STD_LOGIC_VECTOR (RHFSM_MAIN_X_WIDTH downto 1);
YM: in STD_LOGIC_VECTOR (RHFSM_MAIN_Y_WIDTH downto 1);
XS: out STD_LOGIC_VECTOR (RHFSM_SEC_X_WIDTH downto 1);
YS: in STD_LOGIC_VECTOR (RHFSM_SEC_Y_WIDTH downto 1);
data_in: in STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0);
data_out: out STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0);
dataflow: in STD_LOGIC;
ready: out STD_LOGIC;
new_data, next_data: out STD_LOGIC);
end DATAPATH;
architecture DATAPATH_arch of DATAPATH is
constant ZERO: STD_LOGIC_VECTOR (RAM_ADDR_SIZE-1 downto 0) := (others => '0');
component RAM is
generic (RAM_DATA_SIZE: integer;
RAM_ADDR_SIZE: integer);
port (clk: in STD_LOGIC;
en_A, en_B, W_en_A: in STD_LOGIC;
input: in STD_LOGIC_VECTOR (RAM_DATA_SIZE-1 downto 0);
addr_A, addr_B: in STD_LOGIC_VECTOR (RAM_ADDR_SIZE-1 downto 0);
out_A, out_B: out STD_LOGIC_VECTOR (RAM_DATA_SIZE-1 downto 0));
end component;
subtype RAM_WORD is STD_LOGIC_VECTOR (DATA_SIZE+2*RAM_ADDR_SIZE-1 downto 0);
signal RAM_in, RAM_out_A, RAM_out_B: RAM_WORD;
signal RAM_W_en: STD_LOGIC;
signal RAM_addr_A, RAM_addr_B: STD_LOGIC_VECTOR (RAM_ADDR_SIZE-1 downto 0);
signal RAM_in_data: STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0);
signal RAM_in_la, RAM_in_ra: STD_LOGIC_VECTOR (RAM_ADDR_SIZE-1 downto 0);
signal RAM_out_A_data: STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0);
signal RAM_out_A_la, RAM_out_A_ra: STD_LOGIC_VECTOR (RAM_ADDR_SIZE-1 downto 0);
signal RAM_out_B_data: STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0);
signal RAM_out_B_la, RAM_out_B_ra: STD_LOGIC_VECTOR (RAM_ADDR_SIZE-1 downto 0);
component BR_STACK is
--component STACK is
generic (STACK_ADDR_SIZE: integer;
DATA_SIZE: integer);
port (clk, rst: in STD_LOGIC;
inc, dec: in STD_LOGIC;
data_in: in STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0);
data_out: out STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0);
upper_bound, lower_bound: out STD_LOGIC);
end component;
component BR_STACK_NEG is
generic (STACK_ADDR_SIZE: integer;
DATA_SIZE: integer);
port (clk, rst: in STD_LOGIC;
inc, dec: in STD_LOGIC;
data_in: in STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0);
data_out: out STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0);
upper_bound, lower_bound: out STD_LOGIC);
end component;
signal local_main_out, local_sec_out: STD_LOGIC_VECTOR (RAM_ADDR_SIZE-1 downto 0);
signal temp_data_out: STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0);
signal temp_data_empty: STD_LOGIC;
component RG is
generic (RG_WIDTH: integer);
port (clk, rst: in STD_LOGIC;
RG_en: in STD_LOGIC;
RG_in: in STD_LOGIC_VECTOR (RG_WIDTH-1 downto 0);
RG_out: out STD_LOGIC_VECTOR (RG_WIDTH-1 downto 0));
end component;
signal BUF_L_MAIN_rst, BUF_L_SEC_rst: STD_LOGIC;
signal BUF_L_MAIN_out, BUF_L_SEC_out: STD_LOGIC_VECTOR (RAM_ADDR_SIZE-1 downto 0);
signal BUF_D_out: STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0);
component COUNTER is
generic (COUNTER_WIDTH: integer);
port (clk, rst: in STD_LOGIC;
counter_en: in STD_LOGIC;
full, zero: out STD_LOGIC;
counter_out: out STD_LOGIC_VECTOR (COUNTER_WIDTH-1 downto 0));
end component;
signal RAM_counter_out: STD_LOGIC_VECTOR (RAM_ADDR_SIZE-1 downto 0);
signal RAM_counter_zero: STD_LOGIC;
signal root, same, smaller: STD_LOGIC;
signal left_zero_main, right_zero_main: STD_LOGIC;
signal enable_RAM_A, enable_out, enable_temp_out: STD_LOGIC;
signal write_new_node, write_left_address, write_right_address: STD_LOGIC;
signal write_BUF_L_MAIN, write_BUF_D: STD_LOGIC;
signal sel_address_main, sel_root_main, sel_BUF_main: STD_LOGIC;
signal push_main, pop_main: STD_LOGIC;
signal start_sec, pop_temp: STD_LOGIC;
signal ready_sec: STD_LOGIC;
signal left_zero_sec, right_zero_sec: STD_LOGIC;
signal enable_RAM_B: STD_LOGIC;
signal write_BUF_L_SEC: STD_LOGIC;
signal sel_address_sec, sel_root_sec, sel_BUF_sec: STD_LOGIC;
signal push_sec, pop_sec: STD_LOGIC;
signal push_temp: STD_LOGIC;
signal addr_A_MUX, addr_B_MUX: STD_LOGIC_VECTOR (RAM_ADDR_SIZE-1 downto 0);
begin
-- Mapping of Main Primary Inputs
XM(1) <= dataflow;
XM(2) <= root;
XM(3) <= same;
XM(4) <= smaller;
XM(5) <= left_zero_main;
XM(6) <= right_zero_main;
XM(7) <= ready_sec;
XM(8) <= temp_data_empty;
-- Mapping of Main Primary Outputs
ready <= YM(1);
enable_RAM_A <= YM(2);
write_BUF_L_MAIN <= YM(3);
write_BUF_D <= YM(4);
enable_temp_out <= YM(5);
write_new_node <= YM(6);
write_left_address <= YM(7);
write_right_address <= YM(8);
next_data <= YM(9);
sel_address_main <= YM(10);
sel_root_main <= YM(11);
sel_BUF_main <= YM(12);
enable_out <= YM(13);
push_main <= YM(14);
pop_main <= YM(15);
pop_temp <= YM(16);
start_sec <= YM(17);
-- Mapping of Secondary Primary Inputs
XS(1) <= start_sec;
XS(2) <= left_zero_sec;
XS(3) <= right_zero_sec;
-- Mapping of Secondary Primary Outputs
ready_sec <= YS(1);
enable_RAM_B <= YS(2);
write_BUF_L_sec <= YS(3);
sel_address_sec <= YS(4);
sel_root_sec <= YS(5);
sel_BUF_sec <= YS(6);
push_sec <= YS(7);
pop_sec <= YS(8);
push_temp <= YS(9);
-- Mapping of RAM Inputs
RAM_in(DATA_SIZE+2*RAM_ADDR_SIZE-1 downto 2*RAM_ADDR_SIZE) <= RAM_in_data;
RAM_in(2*RAM_ADDR_SIZE-1 downto RAM_ADDR_SIZE) <= RAM_in_la;
RAM_in(RAM_ADDR_SIZE-1 downto 0) <= RAM_in_ra;
-- Mapping of RAM Outputs
RAM_out_A_data <= RAM_out_A(DATA_SIZE+2*RAM_ADDR_SIZE-1 downto 2*RAM_ADDR_SIZE);
RAM_out_A_la <= RAM_out_A(2*RAM_ADDR_SIZE-1 downto RAM_ADDR_SIZE);
RAM_out_A_ra <= RAM_out_A(RAM_ADDR_SIZE-1 downto 0);
RAM_out_B_data <= RAM_out_B(DATA_SIZE+2*RAM_ADDR_SIZE-1 downto 2*RAM_ADDR_SIZE);
RAM_out_B_la <= RAM_out_B(2*RAM_ADDR_SIZE-1 downto RAM_ADDR_SIZE);
RAM_out_B_ra <= RAM_out_B(RAM_ADDR_SIZE-1 downto 0);
-- Address MUX
addr_A_MUX <= RAM_out_A_ra when sel_address_main = '1' else RAM_out_A_la;
addr_B_MUX <= RAM_out_B_ra when sel_address_sec = '1' else RAM_out_B_la;
-- Data Output
data_out <= RAM_out_A_data when enable_out = '1' else
temp_data_out when enable_temp_out = '1' else
(others => '0');
new_data <= enable_out or enable_temp_out;
-- Conditional Signals
left_zero_main <= '1' when RAM_out_A_la = ZERO else '0';
right_zero_main <= '1' when RAM_out_A_ra = ZERO else '0';
left_zero_sec <= '1' when RAM_out_B_la = ZERO else '0';
right_zero_sec <= '1' when RAM_out_B_ra = ZERO else '0';
root <= RAM_counter_zero;
same <= '1' when BUF_D_out = RAM_out_A_data else '0';
smaller <= '1' when BUF_D_out < RAM_out_A_data else '0';
-- Main Local Stack
LOCAL_MAIN:BR_STACK_NEG
--LOCAL_MAIN:STACK
generic map (LOCAL_ADDR_SIZE, RAM_ADDR_SIZE)
port map (clk, rst, push_main, pop_main, BUF_L_MAIN_out, local_main_out, open, open);
-- Secondary Local Stack
LOCAL_SEC:BR_STACK_NEG
--LOCAL_SEC:STACK
generic map (LOCAL_ADDR_SIZE, RAM_ADDR_SIZE)
port map (clk, rst, push_sec, pop_sec, BUF_L_SEC_out, local_sec_out, open, open);
-- Temp Data Stack
TEMP_DATA:BR_STACK
--TEMP_DATA:STACK
generic map (RAM_ADDR_SIZE, DATA_SIZE)
port map (clk, rst, push_temp, pop_temp, RAM_out_B_data, temp_data_out, open, temp_data_empty);
-- Data RAM
DATA_RAM:RAM
generic map (DATA_SIZE+2*RAM_ADDR_SIZE, RAM_ADDR_SIZE)
port map (clk, enable_RAM_A, enable_RAM_B, RAM_W_en, RAM_in, RAM_addr_A, RAM_addr_B, RAM_out_A, RAM_out_B);
-- RAM Enable/Write Enable
RAM_W_en <= write_new_node or write_left_address or write_right_address;
-- RAM Input
RAM_in_data <= RAM_out_A_data when (write_left_address or write_right_address) = '1'
else BUF_D_out;
RAM_in_la <= ZERO when write_new_node = '1'
else RAM_counter_out when write_left_address = '1'
else RAM_out_A_la;
RAM_in_ra <= ZERO when write_new_node = '1'
else RAM_counter_out when write_right_address = '1'
else RAM_out_A_ra;
-- RAM Address A
RAM_addr_A <= RAM_counter_out when write_new_node = '1'
else BUF_L_MAIN_out when sel_BUF_main = '1'
else local_main_out when pop_main = '1'
else addr_A_MUX;
-- RAM Address B
RAM_addr_B <= BUF_L_SEC_out when sel_BUF_sec = '1'
else local_sec_out when pop_sec = '1'
else addr_B_MUX;
-- Left Buffer Register
BUF_L_MAIN:RG
generic map (RAM_ADDR_SIZE)
port map (clk, BUF_L_MAIN_rst, write_BUF_L_MAIN, addr_A_MUX, BUF_L_MAIN_out);
BUF_L_MAIN_rst <= sel_root_main or rst;
BUF_L_SEC:RG
generic map (RAM_ADDR_SIZE)
port map (clk, BUF_L_SEC_rst, write_BUF_L_SEC, addr_B_MUX, BUF_L_SEC_out);
BUF_L_SEC_rst <= sel_root_sec or rst;
-- Data Buffer Register
BUF_D:RG
generic map (DATA_SIZE)
port map (clk, rst, write_BUF_D, data_in, BUF_D_out);
-- RAM Counter
RAM_COUNTER:COUNTER
generic map (RAM_ADDR_SIZE)
port map (clk, rst, write_new_node, open, RAM_counter_zero, RAM_counter_out);
end DATAPATH_arch;
|
--
-- File: dspl_drv\SRC\dspl_drv.vhd
-- created by <NAME> 05/03/2008 15:30:00
--
--
-- This module implements the interface hardware needed to drive some
-- Digilent boards four digit seven segment display. This
-- display is multiplexed (see the specific board Reference Manual for details)
-- requiring that just one digit be displayed at any moment.
-- Examples boards are D2SB/DIO4, Spartan3 Starter Kit and Nexys
--
-- The inputs of the module are:
-- clock - the 50MHz system board clock
-- reset - the active-high system reset signal
-- di vectors - 4 vectors, each with 6 bits, where:
-- di(0) is the decimal point (active-low)
-- di(4 downto 1) is the binary value of the digit
-- di(5) is the (active-high) enable signal of the digit
-- here, i varies from 4 to 1, 4 corresponds to the rightmost
-- digit of the display and 1 corresponds to the leftmost digit
--
-- The outputs of the module are:
-- an (4 downto 1) - the four wire active-low anode vector.
-- In this circuit, exactly one of these 4 wires is at logic 0
-- at any moment. The wire in 0 lights up one of the 4 7-segment
-- displays. 4 is the rightmost display while 1 is the leftmost.
-- dec_ddp (7 downto 0) - is the decoded value of the digit to show
-- at the current instant. dec_ddp(7 downto 1) corresponds
-- respectively to the segments a b c d e f g, and dec_ddp(0) is
-- the decimal point.
--
-- Functional description: The 50MHz is divided to obtain the
-- 1KHz display refresh clock. Upon reset all displays are turned
-- off. The 1KHz clock feeds a 2-bit counter. This counter
-- generates a signal to select one of the four di vectors. This
-- vector is in turn used to enable or not to show the digit in
-- question (through di(5)) and furnishes the digit value for the
-- single multiplexed 7-segment decoder. All outputs are registered
-- using the 1KHz clock.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity dspl_drv is
port (
clock: in STD_LOGIC;
reset: in STD_LOGIC;
d4: in STD_LOGIC_VECTOR (5 downto 0);
d3: in STD_LOGIC_VECTOR (5 downto 0);
d2: in STD_LOGIC_VECTOR (5 downto 0);
d1: in STD_LOGIC_VECTOR (5 downto 0);
an: out STD_LOGIC_VECTOR (3 downto 0);
dec_ddp: out STD_LOGIC_VECTOR (7 downto 0)
);
end dspl_drv;
--}} End of automatically maintained section
architecture dspl_drv of dspl_drv is
signal ck_1KHz: std_logic;
signal dig_selection: std_logic_vector (1 downto 0);
signal selected_dig: std_logic_vector (4 downto 0);
begin
-- 1KHz clock generation
process (reset, clock)
variable count_25K: integer range 0 to 25000;
begin
if reset='1' then
count_25K := 0;
ck_1KHz <= '0';
elsif (clock'event and clock='1') then
count_25K := count_25K + 1;
if (count_25K = 24999) then
count_25K := 0;
ck_1KHz <= not ck_1KHz;
end if;
end if;
end process;
-- 1KHz counter to select digit and register output
process (reset, ck_1KHz)
begin
if reset='1' then
dig_selection <= (others => '0');
an <= (others => '1'); -- Disable all displays
elsif (ck_1KHz'event and ck_1KHz='1') then
-- a 2-bit Johnson counter
dig_selection <= dig_selection(0) & not dig_selection (1);
if dig_selection="00" then
selected_dig <= d1(4 downto 0);
an <= "111" & (not d1(5));
elsif dig_selection="01" then
selected_dig <= d2(4 downto 0);
an <= "11" & (not d2(5)) & "1";
elsif dig_selection="10" then
selected_dig <= d3(4 downto 0);
an <= "1" & (not d3(5)) & "11";
else
selected_dig <= d4(4 downto 0);
an <= (not d4(5)) & "111";
end if;
end if;
end process;
-- digit 4-to-hex decoder
with selected_dig (4 downto 1) select
dec_ddp(7 downto 1) <=
"0000001" when "0000", --0
"1001111" when "0001", --1
"0010010" when "0010", --2
"0000110" when "0011", --3
"1001100" when "0100", --4
"0100100" when "0101", --5
"0100000" when "0110", --6
"0001111" when "0111", --7
"0000000" when "1000", --8
"0000100" when "1001", --9
"0001000" when "1010", --A
"1100000" when "1011", --b
"0110001" when "1100", --C
"1000010" when "1101", --d
"0110000" when "1110", --E
"0111000" when others; --F
-- and the decimal point
dec_ddp(0) <= selected_dig(0);
end dspl_drv;
|
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
sw : in std_logic_vector (3 downto 0);
seg : out std_logic_vector (6 downto 0);
an : out std_logic_vector (3 downto 0);
dp : out std_logic
);
end top;
architecture behav of top is
begin
hex_to_ss : entity work.hex_to_ss
port map (ss => seg, hex => sw(3 downto 0));
an <= "1110";
dp <= '1';
end behav;
|
<gh_stars>0
-- VHDL netlist for main
-- Date: Wed Jul 10 10:13:31 2013
-- Copyright (c) Lattice Semiconductor Corporation
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGAND5_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGAND5_main;
ARCHITECTURE behav OF PGAND5_main IS
BEGIN
PROCESS (A4, A3, A2, A1,
A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A4 AND A3 AND A2 AND
A1 AND A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGORF72_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGORF72_main;
ARCHITECTURE behav OF PGORF72_main IS
BEGIN
PROCESS (A1, A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A1 OR A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGORF76_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A5 : IN std_logic;
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGORF76_main;
ARCHITECTURE behav OF PGORF76_main IS
BEGIN
PROCESS (A5, A4, A3, A2,
A1, A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A5 OR A4 OR A3 OR
A2 OR A1 OR A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGORF74_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGORF74_main;
ARCHITECTURE behav OF PGORF74_main IS
BEGIN
PROCESS (A3, A2, A1, A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A3 OR A2 OR A1 OR
A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGBUFI_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGBUFI_main;
ARCHITECTURE behav OF PGBUFI_main IS
BEGIN
PROCESS (A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGXOR2_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGXOR2_main;
ARCHITECTURE behav OF PGXOR2_main IS
BEGIN
PROCESS (A1, A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A1 XOR A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGINVI_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A0 : IN std_logic;
ZN0 : OUT std_logic
);
END PGINVI_main;
ARCHITECTURE behav OF PGINVI_main IS
BEGIN
PROCESS (A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := NOT A0;
if ZDF ='1' then
ZN0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
ZN0 <= transport ZDF after TFALL;
else
ZN0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGAND2_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGAND2_main;
ARCHITECTURE behav OF PGAND2_main IS
BEGIN
PROCESS (A1, A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A1 AND A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGDFFR_main IS
GENERIC (
HLCQ : TIME := 1 ns;
LHCQ : TIME := 1 ns;
HLRQ : TIME := 1 ns;
SUD0 : TIME := 0 ns;
SUD1 : TIME := 0 ns;
HOLDD0 : TIME := 0 ns;
HOLDD1 : TIME := 0 ns;
POSC1 : TIME := 0 ns;
POSC0 : TIME := 0 ns;
NEGC1 : TIME := 0 ns;
NEGC0 : TIME := 0 ns;
RECRC : TIME := 0 ns;
HOLDRC : TIME := 0 ns
);
PORT (
RNESET : IN std_logic;
CD : IN std_logic;
CLK : IN std_logic;
D0 : IN std_logic;
Q0 : OUT std_logic
);
END PGDFFR_main;
ARCHITECTURE behav OF PGDFFR_main IS
BEGIN
PROCESS (RNESET, CD, CLK, D0)
variable iQ0 : std_logic;
variable pQ0 : std_logic;
begin
if (CD OR NOT (RNESET)) = '1' then
if NOT (iQ0='0') then
iQ0 := '0';
Q0 <= transport iQ0 after HLRQ;
end if;
elsif (CD OR NOT (RNESET)) = '0' AND CLK= '1' AND CLK'EVENT then
pQ0 := iQ0;
if (D0'EVENT) then
iQ0 := D0'LAST_VALUE;
elsif NOT (D0'EVENT) then
iQ0 := D0;
end if;
if pQ0 = iQ0 then
Q0 <= transport iQ0;
elsif iQ0 = '1' then Q0 <= transport iQ0 after LHCQ;
elsif iQ0 = '0' then Q0 <= transport iQ0 after HLCQ;
else
Q0 <= transport iQ0;
end if;
end if;
END PROCESS;
process(CLK, CD)
begin
if CD'EVENT AND CD='0' AND CLK='1' then
assert (CLK'LAST_EVENT >= HOLDRC)
report("HOLD TIME VIOLAION ON CD (HOLDRC) ")
severity WARNING;
end if;
if CLK'EVENT AND CLK ='1' AND CD ='0' then
assert ( CD'LAST_EVENT >= RECRC)
report("RECOVERY TIME VIOLATION on CD(RECRC) ")
severity WARNING;
end if;
end process;
process(CLK,RNESET)
begin
if RNESET'EVENT AND NOT(RNESET)='0' AND CLK='1' then
assert (CLK'LAST_EVENT >= HOLDRC)
report("HOLD TIME VIOLAION ON RNESET (HOLDRC) ")
severity WARNING;
end if;
if CLK'EVENT AND CLK ='1' AND NOT(RNESET) ='0' then
assert ( RNESET'LAST_EVENT >= RECRC)
report("RECOVERY TIME VIOLATION on RNESET(RECRC) ")
severity WARNING;
end if;
end process;
process(D0, CLK)
variable R_EDGE1 : TIME := 0 ns;
variable R_EDGE0 : TIME := 0 ns;
variable F_EDGE1 : TIME := 0 ns;
variable F_EDGE0 : TIME := 0 ns;
begin
if CLK='1' AND CLK'LAST_VALUE='0' AND NOT(D0'EVENT) then
if D0='1' then
R_EDGE1 := NOW;
assert((R_EDGE1-F_EDGE1) >= NEGC1)
report("NEGATIVE PULSE WIDTH VIOLATION (NEGC1) ON CLK at ")
severity WARNING;
elsif D0='0' then
R_EDGE0 := NOW;
assert((R_EDGE0-F_EDGE0) >= NEGC0)
report("NEGATIVE PULSE WIDTH VIOLATION (NEGC0) ON CLK at ")
severity WARNING;
end if;
end if;
if CLK ='0' AND CLK'LAST_VALUE = '1' AND NOT(D0'EVENT) then
if D0='1' then
F_EDGE1 := NOW;
assert ((F_EDGE1-R_EDGE1) >= POSC1)
report("POSITIVE PULSE WIDTH VIOLATION (POSC1) ON CLK at ")
severity WARNING;
elsif D0='0' then
F_EDGE0 := NOW;
assert ((F_EDGE0-R_EDGE0) >= POSC0)
report("POSITIVE PULSE WIDTH VIOLATION (POSC0) ON CLK at ")
severity WARNING;
end if;
end if;
end process;
process(D0, CLK)
begin
if CLK = '1' AND CLK'EVENT then
if D0='1' then
assert(D0'LAST_EVENT >= SUD1)
report("DATA SET-UP VIOLATION (SUD1) ")
severity WARNING;
elsif D0='0' then
assert(D0'LAST_EVENT >= SUD0)
report("DATA SET-UP VIOLATION (SUD0) ")
severity WARNING;
end if;
end if;
if CLK='1' AND D0'EVENT then
if D0'LAST_VALUE ='1' then
assert(CLK'LAST_EVENT >= HOLDD1)
report("DATA HOLD VIOLATION (HOLDD1) ")
severity WARNING;
elsif D0'LAST_VALUE='0' then
assert(CLK'LAST_EVENT >= HOLDD0)
report("DATA HOLD VIOLATION (HOLDD0) ")
severity WARNING;
end if;
end if;
end process;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGAND6_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A5 : IN std_logic;
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGAND6_main;
ARCHITECTURE behav OF PGAND6_main IS
BEGIN
PROCESS (A5, A4, A3, A2,
A1, A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A5 AND A4 AND A3 AND
A2 AND A1 AND A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGAND3_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGAND3_main;
ARCHITECTURE behav OF PGAND3_main IS
BEGIN
PROCESS (A2, A1, A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A2 AND A1 AND A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGORF73_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGORF73_main;
ARCHITECTURE behav OF PGORF73_main IS
BEGIN
PROCESS (A2, A1, A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A2 OR A1 OR A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGAND4_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGAND4_main;
ARCHITECTURE behav OF PGAND4_main IS
BEGIN
PROCESS (A3, A2, A1, A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A3 AND A2 AND A1 AND
A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGORF77_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A6 : IN std_logic;
A5 : IN std_logic;
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGORF77_main;
ARCHITECTURE behav OF PGORF77_main IS
BEGIN
PROCESS (A6, A5, A4, A3,
A2, A1, A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A6 OR A5 OR A4 OR
A3 OR A2 OR A1 OR A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGAND7_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A6 : IN std_logic;
A5 : IN std_logic;
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGAND7_main;
ARCHITECTURE behav OF PGAND7_main IS
BEGIN
PROCESS (A6, A5, A4, A3,
A2, A1, A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A6 AND A5 AND A4 AND
A3 AND A2 AND A1 AND A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGORF75_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGORF75_main;
ARCHITECTURE behav OF PGORF75_main IS
BEGIN
PROCESS (A4, A3, A2, A1,
A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A4 OR A3 OR A2 OR
A1 OR A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGAND10_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A9 : IN std_logic;
A8 : IN std_logic;
A7 : IN std_logic;
A6 : IN std_logic;
A5 : IN std_logic;
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGAND10_main;
ARCHITECTURE behav OF PGAND10_main IS
BEGIN
PROCESS (A9, A8, A7, A6,
A5, A4, A3, A2,
A1, A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A9 AND A8 AND A7 AND
A6 AND A5 AND A4 AND A3 AND
A2 AND A1 AND A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGAND9_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A8 : IN std_logic;
A7 : IN std_logic;
A6 : IN std_logic;
A5 : IN std_logic;
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGAND9_main;
ARCHITECTURE behav OF PGAND9_main IS
BEGIN
PROCESS (A8, A7, A6, A5,
A4, A3, A2, A1,
A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A8 AND A7 AND A6 AND
A5 AND A4 AND A3 AND A2 AND
A1 AND A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PGAND8_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A7 : IN std_logic;
A6 : IN std_logic;
A5 : IN std_logic;
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END PGAND8_main;
ARCHITECTURE behav OF PGAND8_main IS
BEGIN
PROCESS (A7, A6, A5, A4,
A3, A2, A1, A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A7 AND A6 AND A5 AND
A4 AND A3 AND A2 AND A1 AND
A0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PXIN_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
XI0 : IN std_logic;
Z0 : OUT std_logic
);
END PXIN_main;
ARCHITECTURE behav OF PXIN_main IS
BEGIN
PROCESS (XI0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := XI0;
if ZDF ='1' then
Z0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
Z0 <= transport ZDF after TFALL;
else
Z0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY PXOUT_main IS
GENERIC (
TRISE : TIME := 1 ns;
TFALL : TIME := 1 ns
);
PORT (
A0 : IN std_logic;
XO0 : OUT std_logic
);
END PXOUT_main;
ARCHITECTURE behav OF PXOUT_main IS
BEGIN
PROCESS (A0)
VARIABLE ZDF : std_logic;
BEGIN
ZDF := A0;
if ZDF ='1' then
XO0 <= transport ZDF after TRISE;
elsif ZDF ='0' then
XO0 <= transport ZDF after TFALL;
else
XO0 <= transport ZDF;
end if;
END PROCESS;
END behav;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE work.all;
ENTITY main IS
PORT (
XRESET : IN std_logic;
RE_PRGM : IN std_logic;
RE_CPU : IN std_logic;
PRGM : IN std_logic;
EN : IN std_logic;
DI3 : IN std_logic;
DI2 : IN std_logic;
DI1 : IN std_logic;
DI0 : IN std_logic;
CLK : IN std_logic;
P03 : OUT std_logic;
P02 : OUT std_logic;
P01 : OUT std_logic;
P00 : OUT std_logic
);
END main;
ARCHITECTURE main_STRUCTURE OF main IS
SIGNAL GND : std_logic := '0';
SIGNAL N_41_grpi, D0_N_100_grpi, D0_N_101_grpi, D0_N_102_grpi,
D0_N_104_grpi, D0_N_105_grpi, D0_N_106_grpi, D0_N_113_grpi,
D0_N_127_grpi, D0_N_49_grpi, D0_N_50_grpi, N_37_grpi,
N_38_part2_grpi, N_39_grpi, N_40_grpi, F0_N_7_grpi,
F0_N_6_grpi, D0_N_42_grpi, D0_N_31_grpi, D0_N_18_grpi,
D0_N_7_grpi, D0_N_35_grpi, D0_N_11_grpi, N_40_C_grpi,
P0_N_176_grpi, P0_N_177_grpi, P0_N_178_grpi, P0_N_179_grpi,
P0_N_195_grpi, P0_N_212_grpi, P0_N_214_grpi, AND_1372_grpi,
OR_871_grpi, OR_872_grpi, D0_N_5_grpi, D0_N_37_grpi,
D0_N_13_grpi, D0_N_8_grpi, D0_N_34_grpi, D0_N_10_grpi,
P0_N_218_grpi, P0_N_217_grpi, P0_N_216_grpi, OR_1393_grpi,
OR_1395_grpi, OR_1397_grpi, P0_N_174_grpi, P0_N_175_part2_grpi,
P0_N_180_grpi, P0_N_181_grpi, D0_N_116_C_ck2f, D0_N_2_grpi,
P0_N_175_part1_grpi, OR_1392_grpi, D0_N_3_grpi, D0_N_115_grpi,
D0_N_12_grpi, D0_N_14_grpi, D0_N_15_grpi, D0_N_16_grpi,
D0_N_99_grpi, N_38_part1_grpi, D0_N_3_C_ck1f, P0_N_181_C_grpi,
P0_N_238_grpi, P0_N_239_grpi, P0_N_240_grpi, D0_N_39_grpi,
OR_1394_grpi, D0_N_114_grpi, D0_N_36_grpi, D0_N_38_grpi,
D0_N_40_grpi, D0_N_41_grpi, P0_N_177_C_grpi, OR_1401_grpi,
OR_1400_grpi, OR_1396_grpi, D0_N_116_grpi, D0_N_4_grpi,
D0_N_6_grpi, D0_N_98_grpi, L2L_KEYWD_RESETb, IO51_IBUFO,
IO3_IBUFO, IO18_IBUFO, IO53_IBUFO, IO39_IBUFO,
IO38_IBUFO, IO22_IBUFO, IO15_IBUFO, IO47_IBUFO,
IO16_OBUFI, P03_PIN_iomux, IO20_OBUFI, P02_PIN_iomux,
IO50_OBUFI, P01_PIN_iomux, IO17_OBUFI, P00_PIN_iomux,
N_41, A0_X0O, A0_G3, A0_F5,
A0_F0, A0_P19, A0_IN5, A0_P18,
A0_IN1, A0_P17, A0_IN13, A0_P16,
A0_IN12, A0_P15, A0_IN6, A0_P14,
A0_IN0, A0_IN2, A0_P3, A0_IN7,
A0_P2, A0_IN3, A0_IN9B, A0_P1,
A0_IN4, A0_IN10B, A0_IN11, A0_P0,
A0_IN0B, A0_IN4B, A0_IN9, A0_IN10,
A0_IN14, F0_N_6, F0_N_7, A1_CD,
A1_CLK, A1_CLKP, A1_P13_xa, A1_X0O,
A1_G3, A1_F2, A1_P19, A1_IN3,
A1_P13, A1_P12, A1_IN5, A1_IN11,
A1_P11, A1_IN16, A1_IN17B, F0_N_6_ffb,
F0_N_7_ffb, A1_P10, A1_IN16B, A1_IN17,
D0_N_18, D0_N_31, D0_N_50, D0_N_42,
A2_CD, A2_CLKP, A2_P0_xa, A2_X3O,
A2_P4_xa, A2_X2O, A2_P8_xa, A2_X1O,
A2_P13_xa, A2_X0O, A2_G3, A2_G2,
A2_G1, A2_G0, A2_P19, A2_IN3,
A2_P13, A2_IN13, A2_P12, A2_IN0,
A2_IN1B, A2_IN2, A2_IN4B, A2_IN9,
A2_IN11, A2_P8, A2_IN7, A2_P4,
A2_IN15, A2_P0, A2_IN6, D0_N_35,
D0_N_11, D0_N_105, D0_N_7, A3_CD,
A3_CLKP, A3_P0_xa, A3_X3O, A3_P4_xa,
A3_X2O, A3_P8_xa, A3_X1O, A3_P13_xa,
A3_X0O, A3_G3, A3_G2, A3_G1,
A3_G0, A3_P19, A3_IN3, A3_P13,
A3_IN15, A3_P12, A3_IN0B, A3_IN1,
A3_IN2, A3_IN4B, A3_IN9B, A3_IN11,
A3_P8, A3_IN7, A3_P4, A3_IN6,
A3_P0, A3_IN13, N_37, A4_CD,
A4_CLKP, A4_X0O, A4_G3, A4_F5,
A4_F4, A4_F1, A4_F0, A4_P19,
A4_IN7, A4_P16, A4_P15, A4_P14,
A4_IN11B, A4_IN13B, A4_P12, A4_IN3,
A4_P11, A4_P10, A4_P9, A4_IN5,
A4_P8, A4_IN9, A4_IN10, A4_P7,
A4_IN1, A4_IN2, A4_IN4, A4_IN16B,
A4_P6, A4_IN8, A4_P5, A4_IN6B,
A4_IN13, A4_P4, A4_IN0, A4_IN5B,
A4_IN6, A4_IN8B, A4_IN9B, A4_P3,
A4_IN0B, A4_IN12, A4_IN15, A4_P2,
A4_IN2B, A4_P1, A4_IN1B, N_37_ffb,
A4_P0, A4_IN4B, A4_IN12B, A4_IN16,
D0_N_127, D0_N_13, D0_N_37, D0_N_5,
A5_CD, A5_CLKP, A5_P0_xa, A5_X3O,
A5_P4_xa, A5_X2O, A5_P8_xa, A5_X1O,
A5_P13_xa, A5_X0O, A5_G3, A5_G2,
A5_G1, A5_G0, A5_P19, A5_IN3,
A5_P13, A5_IN15, A5_P12, A5_IN0B,
A5_IN1B, A5_IN2, A5_IN4, A5_IN9B,
A5_IN11, A5_P8, A5_IN13, A5_P4,
A5_IN6, A5_P0, A5_IN7, D0_N_10,
D0_N_106, D0_N_34, D0_N_8, A6_CD,
A6_CLKP, A6_P0_xa, A6_X3O, A6_P4_xa,
A6_X2O, A6_P8_xa, A6_X1O, A6_P13_xa,
A6_X0O, A6_G3, A6_G2, A6_G1,
A6_G0, A6_P19, A6_IN3, A6_P13,
A6_IN15, A6_P12, A6_IN0B, A6_IN1B,
A6_IN2, A6_IN4B, A6_IN9, A6_IN11,
A6_P8, A6_IN13, A6_P4, A6_IN7,
A6_P0, A6_IN6, P0_N_214, P0_N_216,
P0_N_217, P0_N_218, A7_CD, A7_CLKP,
A7_P0_xa, A7_X3O, A7_P4_xa, A7_X2O,
A7_P8_xa, A7_X1O, A7_P13_xa, A7_X0O,
A7_G3, A7_G2, A7_G1, A7_G0,
A7_P19, A7_IN3, A7_P13, A7_IN4,
A7_P12, A7_IN5, A7_IN11, A7_IN14,
A7_IN15B, A7_P8, A7_IN8, A7_P4,
A7_IN12, A7_P0, A7_IN0, D0_N_113,
B0_CD, B0_CLK, B0_P8_xa, B0_X1O,
P03_PIN, B0_X0O, B0_G3, B0_G2,
B0_F5, B0_F4, B0_F1, B0_F0,
B0_P19, B0_P18, B0_P17, B0_P16,
B0_P15, B0_P14, B0_P13, B0_P12,
B0_IN3, B0_P11, B0_P10, B0_P9,
B0_IN4, B0_IN10, B0_P8, B0_IN7,
B0_P7, B0_P6, B0_IN0B, B0_IN13B,
B0_P5, B0_IN9, B0_P4, B0_IN2,
B0_IN5, B0_IN8, B0_P3, B0_P2,
B0_IN13, B0_P1, B0_IN6, B0_IN12B,
B0_P0, B0_IN5B, B0_IN6B, B0_IN9B,
B0_IN12, D0_N_100, D0_N_2, B1_CD,
B1_CLKP, B1_P0_xa, B1_X3O, B1_P8_xa,
B1_X1O, B1_G2, B1_G0, B1_P19,
B1_IN3, B1_P12, B1_IN0B, B1_IN1,
B1_IN2, B1_IN4, B1_IN6, B1_IN11,
B1_P8, B1_IN15, B1_P0, B1_IN7,
OR_872, B2_X3O, OR_871, B2_X2O,
P02_PIN, B2_X0O, B2_G3, B2_G1,
B2_G0, B2_F5, P00_PIN, B2_F1,
B2_F0, B2_P16, B2_P15, B2_P14,
B2_P11, B2_IN10B, B2_P10, B2_IN4B,
B2_P7, B2_P6, B2_P5, B2_P4,
B2_IN4, B2_IN10, B2_P3, B2_IN13,
B2_P2, B2_IN9, OR_872_ffb, B2_P1,
B2_IN5, B2_IN13B, B2_IN17B, B2_P0,
B2_IN0, B2_IN2, B2_IN5B, B2_IN9B,
D0_N_3, B3_CD, B3_CLK, B3_P8_xa,
B3_X1O, OR_1392, B3_X0O, B3_G3,
B3_G2, B3_F5, B3_F0, B3_P19,
B3_IN2, B3_P18, B3_IN8, B3_P17,
B3_IN13, B3_P16, B3_IN6, B3_IN7,
B3_P15, B3_IN11, B3_P14, B3_IN4,
B3_IN14, B3_P12, B3_IN3, B3_P8,
B3_IN15, B3_P3, B3_IN0, B3_P2,
B3_IN10, B3_P1, B3_IN1B, B3_IN5,
B3_IN9B, B3_P0, B3_IN1, B3_IN4B,
B3_IN7B, B3_IN9, B3_IN12, P0_N_180,
B4_CD, B4_CLKP, B4_X2MO, B4_X2O,
P0_N_181_C, B4_X1O, P0_N_212, B4_X0O,
B4_G3, B4_G2, B4_G1, B4_G0,
B4_F5, B4_F4, B4_F1, B4_F0,
B4_P19, B4_IN7, B4_P17, B4_P16,
B4_P15, B4_IN3, B4_IN9, B4_P14,
B4_P13, P0_N_181_C_ffb, B4_P12, B4_IN16,
B4_P11, B4_IN2, B4_P10, B4_IN4B,
B4_IN5, B4_IN11, B4_IN14B, B4_P7,
B4_P6, B4_P3, B4_IN1, B4_IN10,
B4_IN15, B4_P2, B4_IN0B, B4_IN17,
P0_N_180_ffb, B4_P1, B4_IN0, B4_IN1B,
B4_IN2B, B4_IN3B, B4_IN17B, D0_N_39,
B5_CD, B5_CLK, B5_P8_xa, B5_X1O,
B5_G2, B5_P12, B5_IN3, B5_P8,
B5_IN6, D0_N_101, B6_CD, B6_CLK,
OR_1394, B6_X3O, B6_P13_xa, B6_X0O,
B6_G3, B6_G0, B6_F5, B6_F0,
B6_P19, B6_IN14, B6_P18, B6_IN13,
B6_P17, B6_IN5, B6_P16, B6_IN0,
B6_IN15, B6_P15, B6_IN3, B6_P14,
B6_IN4, B6_IN8, B6_P13, B6_IN12,
B6_P12, B6_IN7, B6_P3, B6_IN1,
B6_P2, B6_IN2, B6_IN10B, B6_P1,
B6_IN9B, B6_IN11, B6_P0, B6_IN4B,
B6_IN6, B6_IN9, B6_IN10, B6_IN15B,
P0_N_174, P0_N_176, P0_N_177, B7_CD,
B7_CLKP, B7_X2O, B7_X1O, B7_P13_xa,
B7_X0O, B7_G3, B7_G2, B7_G1,
B7_F5, B7_F4, B7_F1, B7_F0,
B7_P19, B7_IN7, B7_P18, B7_P17,
B7_P16, B7_P15, B7_P14, B7_IN5B,
B7_IN16B, B7_P13, B7_IN12, B7_P12,
B7_IN9, B7_P11, B7_P10, B7_IN2B,
B7_IN3B, B7_P7, B7_IN2, B7_P6,
B7_IN1B, B7_IN3, B7_IN8, B7_P5,
B7_IN15, B7_IN17B, P0_N_174_ffb, B7_P4,
B7_IN1, B7_IN15B, B7_IN17, B7_P3,
B7_IN4B, B7_IN10, B7_P2, B7_IN0,
B7_IN6, B7_IN13, P0_N_176_ffb, B7_P1,
B7_IN16, B7_P0, B7_IN4, B7_IN5,
B7_IN11B, B7_IN13B, D0_N_41, D0_N_49,
C0_CD, C0_CLKP, C0_P0_xa, C0_X3O,
C0_P4_xa, C0_X2O, C0_P8_xa, D0_N_116_C,
C0_X1O, C0_P13_xa, D0_N_3_C, C0_X0O,
C0_G3, C0_G2, C0_G1, C0_G0,
C0_P19, C0_IN12, C0_P13, C0_IN11,
C0_IN14, C0_P12, C0_IN15, C0_P8,
C0_IN4, C0_IN9, C0_IN11B, C0_IN13B,
C0_IN14B, C0_IN15B, C0_P4, C0_IN8,
C0_P0, C0_IN2, P0_N_178, P0_N_179,
P0_N_181, C1_CD, C1_CLKP, C1_P4_xa,
C1_X2O, C1_X1O, C1_X0O, C1_G3,
C1_G2, C1_G1, C1_F5, C1_F4,
C1_F1, C1_F0, C1_P19, C1_IN8,
C1_P18, C1_P17, C1_P16, C1_P15,
C1_P14, C1_IN6B, C1_IN16B, C1_P12,
C1_IN10, C1_P11, C1_P10, C1_P9,
C1_IN0B, C1_IN5, C1_IN7B, C1_IN13B,
C1_P7, C1_IN13, C1_P6, C1_IN3,
C1_IN7, C1_IN14B, C1_P5, C1_IN0,
C1_IN5B, C1_IN14, C1_P4, C1_IN11,
C1_P3, C1_IN1, C1_IN15B, C1_P2,
C1_IN2, C1_IN9, C1_IN12, C1_P1,
C1_IN6, P0_N_179_ffb, C1_P0, C1_IN2B,
C1_IN4B, C1_IN15, C1_IN16, N_39,
N_40, C2_CD, C2_CLKP, C2_X2MO,
C2_X2O, C2_P8_xa, C2_X1O, N_40_C,
C2_X0O, C2_G3, C2_G2, C2_G1,
C2_G0, C2_F5, C2_F4, C2_F1,
C2_F0, C2_P19, C2_IN8, C2_P17,
C2_P16, C2_IN4B, C2_P15, C2_IN9,
C2_IN10B, C2_P14, C2_IN11, C2_P13,
C2_IN1, C2_P12, C2_IN12, C2_P11,
C2_IN16B, C2_P10, C2_P8, C2_IN3B,
C2_P7, C2_P6, C2_IN3, C2_P3,
N_39_ffb, C2_P2, C2_IN16, C2_P1,
C2_IN6, C2_IN17B, N_40_ffb, C2_P0,
C2_IN1B, C2_IN4, C2_IN6B, C2_IN7,
C2_IN9B, C2_IN10, C2_IN11B, C2_IN13B,
C2_IN14B, C2_IN17, C3_P8_xa, AND_1372,
C3_X1O, OR_1401, C3_X0O, C3_G3,
C3_G2, C3_F5, C3_F4, C3_F1,
C3_F0, C3_P19, C3_P18, C3_P17,
C3_P16, C3_P15, C3_P14, C3_P13,
C3_P12, C3_P11, C3_P10, C3_P9,
C3_IN5, C3_IN11, C3_P8, C3_IN10,
C3_P7, C3_P6, C3_P5, C3_IN4B,
C3_IN16B, C3_P4, C3_IN6, C3_IN12,
C3_IN13, C3_P3, C3_IN0, C3_IN15B,
C3_P2, C3_IN7, AND_1372_ffb, C3_P1,
C3_IN9B, C3_IN16, C3_P0, C3_IN6B,
C3_IN7B, C3_IN9, C3_IN10B, C3_IN15,
OR_1400, C4_X0O, C4_G3, C4_F5,
C4_F4, C4_F1, C4_F0, C4_P18,
C4_P17, C4_P16, C4_P15, C4_P14,
C4_P13, C4_P12, C4_P11, C4_P10,
C4_IN10, C4_P9, C4_P8, C4_IN5,
C4_IN11, C4_P7, C4_P6, C4_P5,
C4_IN2B, C4_IN4B, C4_P4, C4_IN6,
C4_IN12, C4_IN13, C4_P3, C4_IN0,
C4_IN15B, C4_P2, C4_IN7, C4_P1,
C4_IN2, C4_IN9B, C4_P0, C4_IN6B,
C4_IN7B, C4_IN9, C4_IN10B, C4_IN15,
D0_N_115, C5_CD, C5_CLK, C5_P8_xa,
C5_X1O, OR_1396, C5_X0O, C5_G3,
C5_G2, C5_F5, C5_F0, C5_P19,
C5_IN0, C5_P18, C5_IN11, C5_P17,
C5_IN1, C5_P16, C5_IN7, C5_P15,
C5_IN12, C5_P14, C5_IN4, C5_P12,
C5_IN8, C5_P8, C5_IN9, C5_P3,
C5_IN6, C5_P2, C5_IN10, C5_P1,
C5_IN2, C5_IN3, C5_IN5, C5_IN13B,
C5_IN15B, C5_P0, C5_IN3B, C5_IN5B,
C5_IN13, C5_IN14, C5_IN15, P0_N_175_part1,
P0_N_175_part2, C6_CD, C6_CLKP, C6_X3MO,
C6_X3O, C6_X0MO, C6_X0O, C6_G3,
C6_G2, C6_G0, C6_F5, C6_F0,
C6_P19, C6_IN8, C6_P18, C6_IN13,
C6_P17, C6_IN2, C6_IN12, C6_P16,
C6_IN11B, C6_P15, C6_P14, C6_IN5B,
C6_P13, C6_IN5, C6_IN11, C6_P12,
C6_IN6, C6_P3, C6_IN9, C6_IN16B,
P0_N_175_part2_ffb, C6_P2, C6_IN14, C6_IN16,
C6_P1, C6_IN9B, C6_IN12B, C6_IN13B,
C6_IN14B, D0_N_116, C7_CD, C7_CLK,
C7_P8_xa, C7_X1O, OR_1395, C7_X0O,
C7_G3, C7_G2, C7_F5, C7_F0,
C7_P19, C7_IN1, C7_P18, C7_IN2,
C7_P17, C7_IN10, C7_P16, C7_IN3,
C7_IN15, C7_P15, C7_IN12, C7_P14,
C7_IN7, C7_IN11, C7_P12, C7_IN8,
C7_P8, C7_IN0, C7_P3, C7_IN14,
C7_P2, C7_IN5B, C7_IN13, C7_P1,
C7_IN4, C7_IN6B, C7_P0, C7_IN3B,
C7_IN5, C7_IN6, C7_IN9, C7_IN11B,
D0_N_114, D0_CD, D0_CLK, D0_P8_xa,
D0_X1O, OR_1397, D0_X0O, D0_G3,
D0_G2, D0_F5, D0_F0, D0_P19,
D0_IN0, D0_P18, D0_IN11, D0_P17,
D0_IN1, D0_P16, D0_IN7, D0_P15,
D0_IN12, D0_P14, D0_IN4, D0_P12,
D0_IN8, D0_P8, D0_IN9, D0_P3,
D0_IN6, D0_P2, D0_IN10, D0_P1,
D0_IN2, D0_IN3, D0_IN5, D0_IN13B,
D0_IN15B, D0_P0, D0_IN3B, D0_IN5B,
D0_IN13, D0_IN14, D0_IN15, N_38_part1,
N_38_part2, D1_CD, D1_CLKP, D1_X3O,
D1_P4_xa, P01_PIN, D1_X2O, D1_X0O,
D1_G3, D1_G1, D1_G0, D1_F5,
D1_F4, D1_F1, D1_F0, D1_P19,
D1_IN8, D1_P17, D1_P16, D1_P15,
D1_P14, D1_P13, D1_IN6B, D1_IN10B,
D1_P12, D1_IN7, D1_P11, D1_IN5B,
D1_P10, D1_IN11B, D1_P9, D1_IN5,
D1_IN9B, D1_IN11, D1_P7, D1_IN2,
D1_IN9, D1_P6, D1_IN6, D1_P5,
D1_IN2B, D1_IN4B, D1_IN10, D1_IN15,
D1_P4, D1_IN12, D1_P3, D1_IN13B,
D1_P2, D1_IN14B, D1_IN16, D1_P1,
D1_IN1, D1_IN3, D1_IN15B, N_38_part2_ffb,
D1_P0, D1_IN3B, D1_IN13, D1_IN14,
D1_IN16B, D0_N_15, D2_CD, D2_CLK,
D2_P8_xa, D2_X1O, OR_1393, D2_X0O,
D2_G3, D2_G2, D2_F5, D2_F0,
D0_N_15_ffb, D2_P19, D2_IN16, D2_P18,
D2_IN7, D2_P17, D2_IN9, D2_P16,
D2_IN3, D2_IN13, D2_P15, D2_IN4,
D2_P14, D2_IN1, D2_IN11, D2_P12,
D2_IN12, D2_P8, D2_IN2, D2_P3,
D2_IN15, D2_P2, D2_IN5, D2_P1,
D2_IN6B, D2_IN10, D2_IN14B, D2_P0,
D2_IN3B, D2_IN6, D2_IN8, D2_IN11B,
D2_IN14, D0_N_98, D0_N_99, D3_CD,
D3_CLKP, D3_P0_xa, D3_X3O, D3_P4_xa,
D3_X2O, D3_P13_xa, P0_N_195, D3_X0O,
D3_G3, D3_G1, D3_G0, P0_N_177_C,
D3_P19, D3_IN8, D3_P13, D3_IN9B,
D3_P12, D3_IN3B, D3_IN9, D3_IN13B,
D3_IN14B, D3_IN15, D3_P11, D3_IN5B,
D3_IN6, D3_P10, D3_IN1B, D3_IN4,
D3_IN5, D3_IN6B, D3_IN10, D3_IN11B,
D3_IN12, D3_P4, D3_IN2, D3_P0,
D3_IN0, D0_N_16, D0_N_40, D4_CD,
D4_CLKP, D4_P4_xa, D4_X2O, D4_P13_xa,
D4_X0O, D4_G3, D4_G1, D4_P19,
D4_IN12, D4_P13, D4_IN2, D4_P12,
D4_IN4, D4_IN6, D4_IN11, D4_IN13,
D4_IN14, D4_IN15B, D4_P4, D4_IN9,
D0_N_12, D0_N_36, D0_N_104, D0_N_6,
D5_CD, D5_CLKP, D5_P0_xa, D5_X3O,
D5_P4_xa, D5_X2O, D5_P8_xa, D5_X1O,
D5_P13_xa, D5_X0O, D5_G3, D5_G2,
D5_G1, D5_G0, D5_P19, D5_IN12,
D5_P13, D5_IN0, D5_P12, D5_IN4,
D5_IN6, D5_IN11B, D5_IN13, D5_IN14,
D5_IN15B, D5_P8, D5_IN8, D5_P4,
D5_IN2, D5_P0, D5_IN9, P0_N_238,
P0_N_239, P0_N_240, D6_CD, D6_CLKP,
D6_P4_xa, D6_X2O, D6_P8_xa, D6_X1O,
D6_P13_xa, D6_X0O, D6_G3, D6_G2,
D6_G1, RE_CPUX_grp, D6_P19, D6_IN12,
D6_P13, D6_IN0, ENX_grp, D6_P12,
D6_IN1B, D6_IN4, D6_IN10, D6_IN11,
D6_P8, D6_IN7, D6_P4, D6_IN15,
D0_N_102, D0_N_4, D0_N_38, D0_N_14,
L2L_KEYWD_RESET_glbb, D7_CD, D7_CLKP, D7_P0_xa,
D7_X3O, D7_P4_xa, D7_X2O, D7_P8_xa,
D7_X1O, D7_P13_xa, D7_X0O, D7_G3,
D7_G2, D7_G1, D7_G0, RE_PRGMX_grp,
D7_P19, D7_IN12, DI1X_grp, D7_P13,
D7_IN9, PRGMX_grp, CLKX_grp, D7_P12,
D7_IN4, D7_IN6, D7_IN11, D7_IN13,
D7_IN14B, D7_IN15B, DI2X_grp, D7_P8,
D7_IN2, DI0X_grp, D7_P4, D7_IN0,
DI3X_grp, D7_P0, D7_IN8 : std_logic;
COMPONENT PGAND5_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGAND5_main use entity work.PGAND5_main(behav);
COMPONENT PGORF72_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGORF72_main use entity work.PGORF72_main(behav);
COMPONENT PGORF76_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A5 : IN std_logic;
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGORF76_main use entity work.PGORF76_main(behav);
COMPONENT PGORF74_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGORF74_main use entity work.PGORF74_main(behav);
COMPONENT PGBUFI_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGBUFI_main use entity work.PGBUFI_main(behav);
COMPONENT PGXOR2_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGXOR2_main use entity work.PGXOR2_main(behav);
COMPONENT PGINVI_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A0 : IN std_logic;
ZN0 : OUT std_logic
);
END COMPONENT;
for all : PGINVI_main use entity work.PGINVI_main(behav);
COMPONENT PGAND2_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGAND2_main use entity work.PGAND2_main(behav);
COMPONENT PGDFFR_main
GENERIC (HLCQ, LHCQ, HLRQ, SUD0,
SUD1, HOLDD0, HOLDD1, POSC1,
POSC0, NEGC1, NEGC0, RECRC,
HOLDRC : TIME);
PORT (
RNESET : IN std_logic;
CD : IN std_logic;
CLK : IN std_logic;
D0 : IN std_logic;
Q0 : OUT std_logic
);
END COMPONENT;
for all : PGDFFR_main use entity work.PGDFFR_main(behav);
COMPONENT PGAND6_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A5 : IN std_logic;
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGAND6_main use entity work.PGAND6_main(behav);
COMPONENT PGAND3_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGAND3_main use entity work.PGAND3_main(behav);
COMPONENT PGORF73_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGORF73_main use entity work.PGORF73_main(behav);
COMPONENT PGAND4_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGAND4_main use entity work.PGAND4_main(behav);
COMPONENT PGORF77_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A6 : IN std_logic;
A5 : IN std_logic;
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGORF77_main use entity work.PGORF77_main(behav);
COMPONENT PGAND7_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A6 : IN std_logic;
A5 : IN std_logic;
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGAND7_main use entity work.PGAND7_main(behav);
COMPONENT PGORF75_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGORF75_main use entity work.PGORF75_main(behav);
COMPONENT PGAND10_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A9 : IN std_logic;
A8 : IN std_logic;
A7 : IN std_logic;
A6 : IN std_logic;
A5 : IN std_logic;
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGAND10_main use entity work.PGAND10_main(behav);
COMPONENT PGAND9_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A8 : IN std_logic;
A7 : IN std_logic;
A6 : IN std_logic;
A5 : IN std_logic;
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGAND9_main use entity work.PGAND9_main(behav);
COMPONENT PGAND8_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A7 : IN std_logic;
A6 : IN std_logic;
A5 : IN std_logic;
A4 : IN std_logic;
A3 : IN std_logic;
A2 : IN std_logic;
A1 : IN std_logic;
A0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PGAND8_main use entity work.PGAND8_main(behav);
COMPONENT PXIN_main
GENERIC (TRISE, TFALL : TIME);
PORT (
XI0 : IN std_logic;
Z0 : OUT std_logic
);
END COMPONENT;
for all : PXIN_main use entity work.PXIN_main(behav);
COMPONENT PXOUT_main
GENERIC (TRISE, TFALL : TIME);
PORT (
A0 : IN std_logic;
XO0 : OUT std_logic
);
END COMPONENT;
for all : PXOUT_main use entity work.PXOUT_main(behav);
BEGIN
GLB_A0_P19 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A0_P19, A4 => A0_IN0B, A3 => A0_IN4B, A2 => A0_IN5,
A1 => A0_IN9B, A0 => A0_IN10B);
GLB_A0_P18 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A0_P18, A4 => A0_IN0B, A3 => A0_IN1, A2 => A0_IN4B,
A1 => A0_IN9, A0 => A0_IN10B);
GLB_A0_P17 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A0_P17, A4 => A0_IN0B, A3 => A0_IN4B, A2 => A0_IN9B,
A1 => A0_IN10, A0 => A0_IN13);
GLB_A0_P16 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A0_P16, A4 => A0_IN0B, A3 => A0_IN4, A2 => A0_IN9B,
A1 => A0_IN10B, A0 => A0_IN12);
GLB_A0_P15 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A0_P15, A4 => A0_IN0, A3 => A0_IN4B, A2 => A0_IN6,
A1 => A0_IN9B, A0 => A0_IN10B);
GLB_A0_P14 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A0_P14, A4 => A0_IN0, A3 => A0_IN2, A2 => A0_IN4B,
A1 => A0_IN9, A0 => A0_IN10B);
GLB_A0_P3 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A0_P3, A4 => A0_IN0B, A3 => A0_IN4, A2 => A0_IN7,
A1 => A0_IN9, A0 => A0_IN10);
GLB_A0_P2 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A0_P2, A4 => A0_IN0B, A3 => A0_IN3, A2 => A0_IN4,
A1 => A0_IN9B, A0 => A0_IN10);
GLB_A0_P1 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A0_P1, A4 => A0_IN0B, A3 => A0_IN4, A2 => A0_IN9,
A1 => A0_IN10B, A0 => A0_IN11);
GLB_A0_P0 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A0_P0, A4 => A0_IN0B, A3 => A0_IN4B, A2 => A0_IN9,
A1 => A0_IN10, A0 => A0_IN14);
GLB_A0_G3 : PGORF72_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A0_G3, A1 => A0_F0, A0 => A0_F5);
GLB_A0_F5 : PGORF76_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => A0_F5, A5 => A0_P14, A4 => A0_P15, A3 => A0_P16,
A2 => A0_P19, A1 => A0_P17, A0 => A0_P18);
GLB_A0_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => A0_F0, A3 => A0_P0, A2 => A0_P1, A1 => A0_P2,
A0 => A0_P3);
GLB_N_41 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => N_41, A0 => A0_X0O);
GLB_A0_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A0_IN5, A0 => D0_N_113_grpi);
GLB_A0_IN1 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A0_IN1, A0 => D0_N_106_grpi);
GLB_A0_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A0_IN13, A0 => D0_N_105_grpi);
GLB_A0_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A0_IN12, A0 => D0_N_127_grpi);
GLB_A0_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A0_IN6, A0 => D0_N_49_grpi);
GLB_A0_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A0_IN2, A0 => D0_N_50_grpi);
GLB_A0_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A0_IN0, A0 => N_37_grpi);
GLB_A0_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A0_IN7, A0 => D0_N_100_grpi);
GLB_A0_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A0_IN3, A0 => D0_N_101_grpi);
GLB_A0_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A0_IN11, A0 => D0_N_102_grpi);
GLB_A0_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A0_IN4, A0 => N_38_part2_grpi);
GLB_A0_IN14 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A0_IN14, A0 => D0_N_104_grpi);
GLB_A0_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A0_IN10, A0 => N_39_grpi);
GLB_A0_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A0_IN9, A0 => N_40_grpi);
GLB_A0_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A0_X0O, A1 => GND, A0 => A0_G3);
GLB_A0_IN9B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A0_IN9B, A0 => N_40_grpi);
GLB_A0_IN10B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A0_IN10B, A0 => N_39_grpi);
GLB_A0_IN4B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A0_IN4B, A0 => N_38_part2_grpi);
GLB_A0_IN0B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A0_IN0B, A0 => N_37_grpi);
GLB_A1_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A1_P19, A0 => A1_IN3);
GLB_A1_P13 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A1_P13, A0 => A1_IN16B);
GLB_A1_P12 : PGAND2_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A1_P12, A1 => A1_IN5, A0 => A1_IN11);
GLB_A1_P11 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A1_P11, A1 => A1_IN16, A0 => A1_IN17B);
GLB_A1_P10 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A1_P10, A1 => A1_IN16B, A0 => A1_IN17);
GLB_A1_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A1_G3, A0 => GND);
GLB_A1_F2 : PGORF72_main
GENERIC MAP (TRISE => 2.400000 ns, TFALL => 2.400000 ns)
PORT MAP (Z0 => A1_F2, A1 => A1_P10, A0 => A1_P11);
GLB_A1_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => A1_CD, A0 => A1_P19);
GLB_A1_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.400000 ns, TFALL => 1.400000 ns)
PORT MAP (Z0 => A1_CLKP, A0 => A1_P12);
GLB_A1_P13_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A1_P13_xa, A0 => A1_P13);
GLB_A1_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A1_IN3, A0 => RE_CPUX_grp);
GLB_A1_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A1_IN11, A0 => CLKX_grp);
GLB_A1_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A1_IN5, A0 => ENX_grp);
GLB_A1_IN16 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A1_IN16, A0 => F0_N_7_ffb);
GLB_A1_IN17 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A1_IN17, A0 => F0_N_6_ffb);
GLB_A1_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A1_X0O, A1 => A1_P13_xa, A0 => A1_G3);
GLB_F0_N_6 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => F0_N_6, RNESET => L2L_KEYWD_RESET_glbb, CD => A1_CD, CLK => A1_CLK,
D0 => A1_F2);
GLB_F0_N_7 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => F0_N_7, RNESET => L2L_KEYWD_RESET_glbb, CD => A1_CD, CLK => A1_CLK,
D0 => A1_X0O);
GLB_A1_CLK : PGINVI_main
GENERIC MAP (TRISE => 0.500000 ns, TFALL => 0.500000 ns)
PORT MAP (ZN0 => A1_CLK, A0 => A1_CLKP);
GLB_A1_IN17B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A1_IN17B, A0 => F0_N_6_ffb);
GLB_A1_IN16B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A1_IN16B, A0 => F0_N_7_ffb);
GLB_A2_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A2_P19, A0 => A2_IN3);
GLB_A2_P13 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A2_P13, A0 => A2_IN13);
GLB_A2_P12 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A2_P12, A5 => A2_IN0, A4 => A2_IN1B, A3 => A2_IN2,
A2 => A2_IN4B, A1 => A2_IN9, A0 => A2_IN11);
GLB_A2_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A2_P8, A0 => A2_IN7);
GLB_A2_P4 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A2_P4, A0 => A2_IN15);
GLB_A2_P0 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A2_P0, A0 => A2_IN6);
GLB_A2_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A2_G3, A0 => GND);
GLB_A2_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A2_G2, A0 => GND);
GLB_A2_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A2_G1, A0 => GND);
GLB_A2_G0 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A2_G0, A0 => GND);
GLB_A2_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => A2_CD, A0 => A2_P19);
GLB_A2_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => A2_CLKP, A0 => A2_P12);
GLB_A2_P0_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A2_P0_xa, A0 => A2_P0);
GLB_A2_P4_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A2_P4_xa, A0 => A2_P4);
GLB_A2_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A2_P8_xa, A0 => A2_P8);
GLB_A2_P13_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A2_P13_xa, A0 => A2_P13);
GLB_A2_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A2_IN3, A0 => RE_PRGMX_grp);
GLB_A2_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A2_IN13, A0 => DI2X_grp);
GLB_A2_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A2_IN11, A0 => CLKX_grp);
GLB_A2_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A2_IN9, A0 => N_40_grpi);
GLB_A2_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A2_IN2, A0 => PRGMX_grp);
GLB_A2_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A2_IN0, A0 => N_37_grpi);
GLB_A2_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A2_IN7, A0 => DI3X_grp);
GLB_A2_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A2_IN15, A0 => DI0X_grp);
GLB_A2_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A2_IN6, A0 => DI1X_grp);
GLB_A2_X3O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A2_X3O, A1 => A2_P0_xa, A0 => A2_G0);
GLB_A2_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A2_X2O, A1 => A2_P4_xa, A0 => A2_G1);
GLB_A2_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A2_X1O, A1 => A2_P8_xa, A0 => A2_G2);
GLB_A2_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A2_X0O, A1 => A2_P13_xa, A0 => A2_G3);
GLB_D0_N_18 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_18, RNESET => L2L_KEYWD_RESET_glbb, CD => A2_CD, CLK => A2_CLKP,
D0 => A2_X3O);
GLB_D0_N_31 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_31, RNESET => L2L_KEYWD_RESET_glbb, CD => A2_CD, CLK => A2_CLKP,
D0 => A2_X2O);
GLB_D0_N_50 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_50, RNESET => L2L_KEYWD_RESET_glbb, CD => A2_CD, CLK => A2_CLKP,
D0 => A2_X1O);
GLB_D0_N_42 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_42, RNESET => L2L_KEYWD_RESET_glbb, CD => A2_CD, CLK => A2_CLKP,
D0 => A2_X0O);
GLB_A2_IN4B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A2_IN4B, A0 => N_38_part2_grpi);
GLB_A2_IN1B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A2_IN1B, A0 => N_39_grpi);
GLB_A3_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A3_P19, A0 => A3_IN3);
GLB_A3_P13 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A3_P13, A0 => A3_IN15);
GLB_A3_P12 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A3_P12, A5 => A3_IN0B, A4 => A3_IN1, A3 => A3_IN2,
A2 => A3_IN4B, A1 => A3_IN9B, A0 => A3_IN11);
GLB_A3_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A3_P8, A0 => A3_IN7);
GLB_A3_P4 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A3_P4, A0 => A3_IN6);
GLB_A3_P0 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A3_P0, A0 => A3_IN13);
GLB_A3_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A3_G3, A0 => GND);
GLB_A3_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A3_G2, A0 => GND);
GLB_A3_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A3_G1, A0 => GND);
GLB_A3_G0 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A3_G0, A0 => GND);
GLB_A3_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => A3_CD, A0 => A3_P19);
GLB_A3_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => A3_CLKP, A0 => A3_P12);
GLB_A3_P0_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A3_P0_xa, A0 => A3_P0);
GLB_A3_P4_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A3_P4_xa, A0 => A3_P4);
GLB_A3_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A3_P8_xa, A0 => A3_P8);
GLB_A3_P13_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A3_P13_xa, A0 => A3_P13);
GLB_A3_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A3_IN3, A0 => RE_PRGMX_grp);
GLB_A3_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A3_IN15, A0 => DI0X_grp);
GLB_A3_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A3_IN11, A0 => CLKX_grp);
GLB_A3_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A3_IN2, A0 => PRGMX_grp);
GLB_A3_IN1 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A3_IN1, A0 => N_39_grpi);
GLB_A3_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A3_IN7, A0 => DI3X_grp);
GLB_A3_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A3_IN6, A0 => DI1X_grp);
GLB_A3_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A3_IN13, A0 => DI2X_grp);
GLB_A3_X3O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A3_X3O, A1 => A3_P0_xa, A0 => A3_G0);
GLB_A3_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A3_X2O, A1 => A3_P4_xa, A0 => A3_G1);
GLB_A3_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A3_X1O, A1 => A3_P8_xa, A0 => A3_G2);
GLB_A3_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A3_X0O, A1 => A3_P13_xa, A0 => A3_G3);
GLB_D0_N_35 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_35, RNESET => L2L_KEYWD_RESET_glbb, CD => A3_CD, CLK => A3_CLKP,
D0 => A3_X3O);
GLB_D0_N_11 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_11, RNESET => L2L_KEYWD_RESET_glbb, CD => A3_CD, CLK => A3_CLKP,
D0 => A3_X2O);
GLB_D0_N_105 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_105, RNESET => L2L_KEYWD_RESET_glbb, CD => A3_CD, CLK => A3_CLKP,
D0 => A3_X1O);
GLB_D0_N_7 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_7, RNESET => L2L_KEYWD_RESET_glbb, CD => A3_CD, CLK => A3_CLKP,
D0 => A3_X0O);
GLB_A3_IN9B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A3_IN9B, A0 => N_40_grpi);
GLB_A3_IN4B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A3_IN4B, A0 => N_38_part2_grpi);
GLB_A3_IN0B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A3_IN0B, A0 => N_37_grpi);
GLB_A4_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A4_P19, A0 => A4_IN7);
GLB_A4_P16 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A4_P16, A5 => A4_IN0, A4 => A4_IN5, A3 => A4_IN6B,
A2 => A4_IN8B, A1 => A4_IN10, A0 => A4_IN12);
GLB_A4_P15 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A4_P15, A5 => A4_IN0, A4 => A4_IN6, A3 => A4_IN8B,
A2 => A4_IN11B, A1 => A4_IN12, A0 => A4_IN13B);
GLB_A4_P14 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A4_P14, A5 => A4_IN0, A4 => A4_IN6B, A3 => A4_IN8,
A2 => A4_IN11B, A1 => A4_IN12, A0 => A4_IN13B);
GLB_A4_P12 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A4_P12, A0 => A4_IN3);
GLB_A4_P11 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A4_P11, A5 => A4_IN0, A4 => A4_IN5B, A3 => A4_IN6B,
A2 => A4_IN8, A1 => A4_IN9B, A0 => A4_IN12);
GLB_A4_P10 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A4_P10, A5 => A4_IN0, A4 => A4_IN6, A3 => A4_IN8,
A2 => A4_IN9, A1 => A4_IN10, A0 => A4_IN12);
GLB_A4_P9 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A4_P9, A5 => A4_IN0, A4 => A4_IN5, A3 => A4_IN6,
A2 => A4_IN8, A1 => A4_IN10, A0 => A4_IN12);
GLB_A4_P8 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A4_P8, A5 => A4_IN0, A4 => A4_IN6B, A3 => A4_IN8B,
A2 => A4_IN9, A1 => A4_IN10, A0 => A4_IN12);
GLB_A4_P7 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A4_P7, A4 => A4_IN1, A3 => A4_IN2, A2 => A4_IN4,
A1 => A4_IN12B, A0 => A4_IN16B);
GLB_A4_P6 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A4_P6, A4 => A4_IN0, A3 => A4_IN6, A2 => A4_IN8,
A1 => A4_IN12, A0 => A4_IN13);
GLB_A4_P5 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A4_P5, A4 => A4_IN0, A3 => A4_IN6B, A2 => A4_IN8B,
A1 => A4_IN12, A0 => A4_IN13);
GLB_A4_P4 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A4_P4, A5 => A4_IN0, A4 => A4_IN5B, A3 => A4_IN6,
A2 => A4_IN8B, A1 => A4_IN9B, A0 => A4_IN12);
GLB_A4_P3 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A4_P3, A2 => A4_IN0B, A1 => A4_IN12, A0 => A4_IN15);
GLB_A4_P2 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A4_P2, A2 => A4_IN2B, A1 => A4_IN12B, A0 => A4_IN16);
GLB_A4_P1 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => A4_P1, A2 => A4_IN1B, A1 => A4_IN12B, A0 => A4_IN16);
GLB_A4_P0 : PGAND3_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A4_P0, A2 => A4_IN4B, A1 => A4_IN12B, A0 => A4_IN16);
GLB_A4_G3 : PGORF74_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A4_G3, A3 => A4_F0, A2 => A4_F1, A1 => A4_F4,
A0 => A4_F5);
GLB_A4_F5 : PGORF73_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => A4_F5, A2 => A4_P14, A1 => A4_P15, A0 => A4_P16);
GLB_A4_F4 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => A4_F4, A3 => A4_P8, A2 => A4_P9, A1 => A4_P10,
A0 => A4_P11);
GLB_A4_F1 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => A4_F1, A3 => A4_P4, A2 => A4_P5, A1 => A4_P6,
A0 => A4_P7);
GLB_A4_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => A4_F0, A3 => A4_P0, A2 => A4_P1, A1 => A4_P2,
A0 => A4_P3);
GLB_A4_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => A4_CD, A0 => A4_P19);
GLB_A4_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => A4_CLKP, A0 => A4_P12);
GLB_A4_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A4_IN7, A0 => RE_CPUX_grp);
GLB_A4_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A4_IN3, A0 => N_40_C_grpi);
GLB_A4_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A4_IN5, A0 => P0_N_179_grpi);
GLB_A4_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A4_IN10, A0 => OR_871_grpi);
GLB_A4_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A4_IN9, A0 => P0_N_176_grpi);
GLB_A4_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A4_IN4, A0 => N_38_part2_grpi);
GLB_A4_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A4_IN2, A0 => N_40_grpi);
GLB_A4_IN1 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A4_IN1, A0 => N_39_grpi);
GLB_A4_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A4_IN8, A0 => P0_N_177_grpi);
GLB_A4_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A4_IN13, A0 => AND_1372_grpi);
GLB_A4_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A4_IN6, A0 => P0_N_178_grpi);
GLB_A4_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A4_IN0, A0 => P0_N_212_grpi);
GLB_A4_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A4_IN15, A0 => P0_N_214_grpi);
GLB_A4_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A4_IN12, A0 => P0_N_195_grpi);
GLB_A4_IN16 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A4_IN16, A0 => N_37_ffb);
GLB_A4_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A4_X0O, A1 => GND, A0 => A4_G3);
GLB_N_37 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => N_37, RNESET => L2L_KEYWD_RESET_glbb, CD => A4_CD, CLK => A4_CLKP,
D0 => A4_X0O);
GLB_A4_IN13B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A4_IN13B, A0 => AND_1372_grpi);
GLB_A4_IN11B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A4_IN11B, A0 => OR_872_grpi);
GLB_A4_IN16B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A4_IN16B, A0 => N_37_ffb);
GLB_A4_IN6B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A4_IN6B, A0 => P0_N_178_grpi);
GLB_A4_IN9B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A4_IN9B, A0 => P0_N_176_grpi);
GLB_A4_IN8B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A4_IN8B, A0 => P0_N_177_grpi);
GLB_A4_IN5B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A4_IN5B, A0 => P0_N_179_grpi);
GLB_A4_IN0B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A4_IN0B, A0 => P0_N_212_grpi);
GLB_A4_IN2B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A4_IN2B, A0 => N_40_grpi);
GLB_A4_IN1B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A4_IN1B, A0 => N_39_grpi);
GLB_A4_IN12B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A4_IN12B, A0 => P0_N_195_grpi);
GLB_A4_IN4B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A4_IN4B, A0 => N_38_part2_grpi);
GLB_A5_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A5_P19, A0 => A5_IN3);
GLB_A5_P13 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A5_P13, A0 => A5_IN15);
GLB_A5_P12 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A5_P12, A5 => A5_IN0B, A4 => A5_IN1B, A3 => A5_IN2,
A2 => A5_IN4, A1 => A5_IN9B, A0 => A5_IN11);
GLB_A5_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A5_P8, A0 => A5_IN13);
GLB_A5_P4 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A5_P4, A0 => A5_IN6);
GLB_A5_P0 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A5_P0, A0 => A5_IN7);
GLB_A5_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A5_G3, A0 => GND);
GLB_A5_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A5_G2, A0 => GND);
GLB_A5_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A5_G1, A0 => GND);
GLB_A5_G0 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A5_G0, A0 => GND);
GLB_A5_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => A5_CD, A0 => A5_P19);
GLB_A5_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => A5_CLKP, A0 => A5_P12);
GLB_A5_P0_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A5_P0_xa, A0 => A5_P0);
GLB_A5_P4_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A5_P4_xa, A0 => A5_P4);
GLB_A5_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A5_P8_xa, A0 => A5_P8);
GLB_A5_P13_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A5_P13_xa, A0 => A5_P13);
GLB_A5_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A5_IN3, A0 => RE_PRGMX_grp);
GLB_A5_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A5_IN15, A0 => DI0X_grp);
GLB_A5_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A5_IN11, A0 => CLKX_grp);
GLB_A5_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A5_IN4, A0 => N_38_part2_grpi);
GLB_A5_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A5_IN2, A0 => PRGMX_grp);
GLB_A5_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A5_IN13, A0 => DI2X_grp);
GLB_A5_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A5_IN6, A0 => DI1X_grp);
GLB_A5_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A5_IN7, A0 => DI3X_grp);
GLB_A5_X3O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A5_X3O, A1 => A5_P0_xa, A0 => A5_G0);
GLB_A5_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A5_X2O, A1 => A5_P4_xa, A0 => A5_G1);
GLB_A5_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A5_X1O, A1 => A5_P8_xa, A0 => A5_G2);
GLB_A5_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A5_X0O, A1 => A5_P13_xa, A0 => A5_G3);
GLB_D0_N_127 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_127, RNESET => L2L_KEYWD_RESET_glbb, CD => A5_CD, CLK => A5_CLKP,
D0 => A5_X3O);
GLB_D0_N_13 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_13, RNESET => L2L_KEYWD_RESET_glbb, CD => A5_CD, CLK => A5_CLKP,
D0 => A5_X2O);
GLB_D0_N_37 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_37, RNESET => L2L_KEYWD_RESET_glbb, CD => A5_CD, CLK => A5_CLKP,
D0 => A5_X1O);
GLB_D0_N_5 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_5, RNESET => L2L_KEYWD_RESET_glbb, CD => A5_CD, CLK => A5_CLKP,
D0 => A5_X0O);
GLB_A5_IN9B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A5_IN9B, A0 => N_40_grpi);
GLB_A5_IN1B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A5_IN1B, A0 => N_39_grpi);
GLB_A5_IN0B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A5_IN0B, A0 => N_37_grpi);
GLB_A6_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A6_P19, A0 => A6_IN3);
GLB_A6_P13 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A6_P13, A0 => A6_IN15);
GLB_A6_P12 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A6_P12, A5 => A6_IN0B, A4 => A6_IN1B, A3 => A6_IN2,
A2 => A6_IN4B, A1 => A6_IN9, A0 => A6_IN11);
GLB_A6_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A6_P8, A0 => A6_IN13);
GLB_A6_P4 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A6_P4, A0 => A6_IN7);
GLB_A6_P0 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A6_P0, A0 => A6_IN6);
GLB_A6_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A6_G3, A0 => GND);
GLB_A6_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A6_G2, A0 => GND);
GLB_A6_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A6_G1, A0 => GND);
GLB_A6_G0 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A6_G0, A0 => GND);
GLB_A6_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => A6_CD, A0 => A6_P19);
GLB_A6_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => A6_CLKP, A0 => A6_P12);
GLB_A6_P0_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A6_P0_xa, A0 => A6_P0);
GLB_A6_P4_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A6_P4_xa, A0 => A6_P4);
GLB_A6_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A6_P8_xa, A0 => A6_P8);
GLB_A6_P13_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A6_P13_xa, A0 => A6_P13);
GLB_A6_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A6_IN3, A0 => RE_PRGMX_grp);
GLB_A6_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A6_IN15, A0 => DI0X_grp);
GLB_A6_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A6_IN11, A0 => CLKX_grp);
GLB_A6_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A6_IN9, A0 => N_40_grpi);
GLB_A6_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A6_IN2, A0 => PRGMX_grp);
GLB_A6_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A6_IN13, A0 => DI2X_grp);
GLB_A6_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A6_IN7, A0 => DI3X_grp);
GLB_A6_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A6_IN6, A0 => DI1X_grp);
GLB_A6_X3O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A6_X3O, A1 => A6_P0_xa, A0 => A6_G0);
GLB_A6_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A6_X2O, A1 => A6_P4_xa, A0 => A6_G1);
GLB_A6_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A6_X1O, A1 => A6_P8_xa, A0 => A6_G2);
GLB_A6_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A6_X0O, A1 => A6_P13_xa, A0 => A6_G3);
GLB_D0_N_10 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_10, RNESET => L2L_KEYWD_RESET_glbb, CD => A6_CD, CLK => A6_CLKP,
D0 => A6_X3O);
GLB_D0_N_106 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_106, RNESET => L2L_KEYWD_RESET_glbb, CD => A6_CD, CLK => A6_CLKP,
D0 => A6_X2O);
GLB_D0_N_34 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_34, RNESET => L2L_KEYWD_RESET_glbb, CD => A6_CD, CLK => A6_CLKP,
D0 => A6_X1O);
GLB_D0_N_8 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_8, RNESET => L2L_KEYWD_RESET_glbb, CD => A6_CD, CLK => A6_CLKP,
D0 => A6_X0O);
GLB_A6_IN4B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A6_IN4B, A0 => N_38_part2_grpi);
GLB_A6_IN1B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A6_IN1B, A0 => N_39_grpi);
GLB_A6_IN0B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A6_IN0B, A0 => N_37_grpi);
GLB_A7_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A7_P19, A0 => A7_IN3);
GLB_A7_P13 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A7_P13, A0 => A7_IN4);
GLB_A7_P12 : PGAND4_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A7_P12, A3 => A7_IN5, A2 => A7_IN11, A1 => A7_IN14,
A0 => A7_IN15B);
GLB_A7_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A7_P8, A0 => A7_IN8);
GLB_A7_P4 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A7_P4, A0 => A7_IN12);
GLB_A7_P0 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => A7_P0, A0 => A7_IN0);
GLB_A7_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A7_G3, A0 => GND);
GLB_A7_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A7_G2, A0 => GND);
GLB_A7_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A7_G1, A0 => GND);
GLB_A7_G0 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => A7_G0, A0 => GND);
GLB_A7_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => A7_CD, A0 => A7_P19);
GLB_A7_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => A7_CLKP, A0 => A7_P12);
GLB_A7_P0_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A7_P0_xa, A0 => A7_P0);
GLB_A7_P4_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A7_P4_xa, A0 => A7_P4);
GLB_A7_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A7_P8_xa, A0 => A7_P8);
GLB_A7_P13_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => A7_P13_xa, A0 => A7_P13);
GLB_A7_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A7_IN3, A0 => RE_CPUX_grp);
GLB_A7_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A7_IN4, A0 => OR_1397_grpi);
GLB_A7_IN14 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A7_IN14, A0 => F0_N_6_grpi);
GLB_A7_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A7_IN11, A0 => CLKX_grp);
GLB_A7_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A7_IN5, A0 => ENX_grp);
GLB_A7_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A7_IN8, A0 => OR_1393_grpi);
GLB_A7_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A7_IN12, A0 => OR_1395_grpi);
GLB_A7_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => A7_IN0, A0 => N_41_grpi);
GLB_A7_X3O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A7_X3O, A1 => A7_P0_xa, A0 => A7_G0);
GLB_A7_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A7_X2O, A1 => A7_P4_xa, A0 => A7_G1);
GLB_A7_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A7_X1O, A1 => A7_P8_xa, A0 => A7_G2);
GLB_A7_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => A7_X0O, A1 => A7_P13_xa, A0 => A7_G3);
GLB_P0_N_214 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_214, RNESET => L2L_KEYWD_RESET_glbb, CD => A7_CD, CLK => A7_CLKP,
D0 => A7_X3O);
GLB_P0_N_216 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_216, RNESET => L2L_KEYWD_RESET_glbb, CD => A7_CD, CLK => A7_CLKP,
D0 => A7_X2O);
GLB_P0_N_217 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_217, RNESET => L2L_KEYWD_RESET_glbb, CD => A7_CD, CLK => A7_CLKP,
D0 => A7_X1O);
GLB_P0_N_218 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_218, RNESET => L2L_KEYWD_RESET_glbb, CD => A7_CD, CLK => A7_CLKP,
D0 => A7_X0O);
GLB_A7_IN15B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => A7_IN15B, A0 => F0_N_7_grpi);
GLB_B0_P19 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B0_P19, A5 => B0_IN2, A4 => B0_IN4, A3 => B0_IN5,
A2 => B0_IN6B, A1 => B0_IN10, A0 => B0_IN12B);
GLB_B0_P18 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B0_P18, A5 => B0_IN4, A4 => B0_IN5, A3 => B0_IN6B,
A2 => B0_IN8, A1 => B0_IN10, A0 => B0_IN12B);
GLB_B0_P17 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B0_P17, A5 => B0_IN2, A4 => B0_IN4, A3 => B0_IN6B,
A2 => B0_IN9, A1 => B0_IN10, A0 => B0_IN12B);
GLB_B0_P16 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B0_P16, A5 => B0_IN2, A4 => B0_IN4, A3 => B0_IN6,
A2 => B0_IN9, A1 => B0_IN10, A0 => B0_IN12);
GLB_B0_P15 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B0_P15, A5 => B0_IN4, A4 => B0_IN5, A3 => B0_IN6,
A2 => B0_IN8, A1 => B0_IN10, A0 => B0_IN12);
GLB_B0_P14 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B0_P14, A5 => B0_IN2, A4 => B0_IN4, A3 => B0_IN5,
A2 => B0_IN6, A1 => B0_IN10, A0 => B0_IN12);
GLB_B0_P13 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B0_P13, A5 => B0_IN4, A4 => B0_IN6B, A3 => B0_IN8,
A2 => B0_IN9, A1 => B0_IN10, A0 => B0_IN12B);
GLB_B0_P12 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B0_P12, A0 => B0_IN3);
GLB_B0_P11 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B0_P11, A4 => B0_IN2, A3 => B0_IN6B, A2 => B0_IN8,
A1 => B0_IN9, A0 => B0_IN12B);
GLB_B0_P10 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B0_P10, A4 => B0_IN2, A3 => B0_IN5, A2 => B0_IN6B,
A1 => B0_IN8, A0 => B0_IN12B);
GLB_B0_P9 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B0_P9, A5 => B0_IN4, A4 => B0_IN6, A3 => B0_IN8,
A2 => B0_IN9, A1 => B0_IN10, A0 => B0_IN12);
GLB_B0_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B0_P8, A0 => B0_IN7);
GLB_B0_P7 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B0_P7, A3 => B0_IN0B, A2 => B0_IN6, A1 => B0_IN12B,
A0 => B0_IN13B);
GLB_B0_P6 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B0_P6, A3 => B0_IN0B, A2 => B0_IN6B, A1 => B0_IN12,
A0 => B0_IN13B);
GLB_B0_P5 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B0_P5, A4 => B0_IN2, A3 => B0_IN6, A2 => B0_IN8,
A1 => B0_IN9, A0 => B0_IN12);
GLB_B0_P4 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B0_P4, A4 => B0_IN2, A3 => B0_IN5, A2 => B0_IN6,
A1 => B0_IN8, A0 => B0_IN12);
GLB_B0_P3 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B0_P3, A2 => B0_IN6, A1 => B0_IN12, A0 => B0_IN13);
GLB_B0_P2 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B0_P2, A2 => B0_IN6B, A1 => B0_IN12B, A0 => B0_IN13);
GLB_B0_P1 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B0_P1, A3 => B0_IN5B, A2 => B0_IN6, A1 => B0_IN9B,
A0 => B0_IN12B);
GLB_B0_P0 : PGAND4_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B0_P0, A3 => B0_IN5B, A2 => B0_IN6B, A1 => B0_IN9B,
A0 => B0_IN12);
GLB_B0_G3 : PGORF74_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B0_G3, A3 => B0_F0, A2 => B0_F1, A1 => B0_F4,
A0 => B0_F5);
GLB_B0_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B0_G2, A0 => GND);
GLB_B0_F5 : PGORF77_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B0_F5, A6 => B0_P13, A5 => B0_P14, A4 => B0_P15,
A3 => B0_P16, A2 => B0_P19, A1 => B0_P17, A0 => B0_P18);
GLB_B0_F4 : PGORF73_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B0_F4, A2 => B0_P9, A1 => B0_P10, A0 => B0_P11);
GLB_B0_F1 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B0_F1, A3 => B0_P4, A2 => B0_P5, A1 => B0_P6,
A0 => B0_P7);
GLB_B0_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B0_F0, A3 => B0_P0, A2 => B0_P1, A1 => B0_P2,
A0 => B0_P3);
GLB_B0_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => B0_CD, A0 => B0_P12);
GLB_B0_CLK : PGBUFI_main
GENERIC MAP (TRISE => 0.500000 ns, TFALL => 0.500000 ns)
PORT MAP (Z0 => B0_CLK, A0 => D0_N_116_C_ck2f);
GLB_B0_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => B0_P8_xa, A0 => B0_P8);
GLB_P03_PIN : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => P03_PIN, A0 => B0_X0O);
GLB_B0_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B0_IN3, A0 => RE_PRGMX_grp);
GLB_B0_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B0_IN10, A0 => P0_N_174_grpi);
GLB_B0_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B0_IN4, A0 => P0_N_181_grpi);
GLB_B0_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B0_IN7, A0 => DI3X_grp);
GLB_B0_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B0_IN9, A0 => P0_N_176_grpi);
GLB_B0_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B0_IN8, A0 => P0_N_175_part2_grpi);
GLB_B0_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B0_IN5, A0 => P0_N_179_grpi);
GLB_B0_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B0_IN2, A0 => P0_N_180_grpi);
GLB_B0_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B0_IN13, A0 => AND_1372_grpi);
GLB_B0_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B0_IN6, A0 => P0_N_178_grpi);
GLB_B0_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B0_IN12, A0 => P0_N_177_grpi);
GLB_B0_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B0_X1O, A1 => B0_P8_xa, A0 => B0_G2);
GLB_B0_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B0_X0O, A1 => GND, A0 => B0_G3);
GLB_D0_N_113 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_113, RNESET => L2L_KEYWD_RESET_glbb, CD => B0_CD, CLK => B0_CLK,
D0 => B0_X1O);
GLB_B0_IN13B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B0_IN13B, A0 => AND_1372_grpi);
GLB_B0_IN0B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B0_IN0B, A0 => OR_872_grpi);
GLB_B0_IN12B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B0_IN12B, A0 => P0_N_177_grpi);
GLB_B0_IN9B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B0_IN9B, A0 => P0_N_176_grpi);
GLB_B0_IN6B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B0_IN6B, A0 => P0_N_178_grpi);
GLB_B0_IN5B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B0_IN5B, A0 => P0_N_179_grpi);
GLB_B1_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B1_P19, A0 => B1_IN3);
GLB_B1_P12 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B1_P12, A5 => B1_IN0B, A4 => B1_IN1, A3 => B1_IN2,
A2 => B1_IN4, A1 => B1_IN6, A0 => B1_IN11);
GLB_B1_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B1_P8, A0 => B1_IN15);
GLB_B1_P0 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B1_P0, A0 => B1_IN7);
GLB_B1_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B1_G2, A0 => GND);
GLB_B1_G0 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B1_G0, A0 => GND);
GLB_B1_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => B1_CD, A0 => B1_P19);
GLB_B1_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => B1_CLKP, A0 => B1_P12);
GLB_B1_P0_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => B1_P0_xa, A0 => B1_P0);
GLB_B1_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => B1_P8_xa, A0 => B1_P8);
GLB_B1_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B1_IN3, A0 => RE_PRGMX_grp);
GLB_B1_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B1_IN11, A0 => CLKX_grp);
GLB_B1_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B1_IN6, A0 => PRGMX_grp);
GLB_B1_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B1_IN4, A0 => N_38_part2_grpi);
GLB_B1_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B1_IN2, A0 => N_40_grpi);
GLB_B1_IN1 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B1_IN1, A0 => N_39_grpi);
GLB_B1_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B1_IN15, A0 => DI0X_grp);
GLB_B1_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B1_IN7, A0 => DI3X_grp);
GLB_B1_X3O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B1_X3O, A1 => B1_P0_xa, A0 => B1_G0);
GLB_B1_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B1_X1O, A1 => B1_P8_xa, A0 => B1_G2);
GLB_D0_N_100 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_100, RNESET => L2L_KEYWD_RESET_glbb, CD => B1_CD, CLK => B1_CLKP,
D0 => B1_X3O);
GLB_D0_N_2 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_2, RNESET => L2L_KEYWD_RESET_glbb, CD => B1_CD, CLK => B1_CLKP,
D0 => B1_X1O);
GLB_B1_IN0B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B1_IN0B, A0 => N_37_grpi);
GLB_B2_P16 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B2_P16, A1 => B2_IN0, A0 => B2_IN2);
GLB_B2_P15 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B2_P15, A2 => B2_IN0, A1 => B2_IN4, A0 => B2_IN10);
GLB_B2_P14 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B2_P14, A2 => B2_IN2, A1 => B2_IN4, A0 => B2_IN10);
GLB_B2_P11 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B2_P11, A1 => B2_IN4, A0 => B2_IN10B);
GLB_B2_P10 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B2_P10, A1 => B2_IN4B, A0 => B2_IN10);
GLB_B2_P7 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B2_P7, A3 => B2_IN0, A2 => B2_IN4, A1 => B2_IN10,
A0 => B2_IN13);
GLB_B2_P6 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B2_P6, A3 => B2_IN2, A2 => B2_IN4, A1 => B2_IN10,
A0 => B2_IN13);
GLB_B2_P5 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B2_P5, A4 => B2_IN0, A3 => B2_IN4, A2 => B2_IN5B,
A1 => B2_IN9B, A0 => B2_IN10);
GLB_B2_P4 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B2_P4, A4 => B2_IN2, A3 => B2_IN4, A2 => B2_IN5B,
A1 => B2_IN9B, A0 => B2_IN10);
GLB_B2_P3 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B2_P3, A2 => B2_IN0, A1 => B2_IN2, A0 => B2_IN13);
GLB_B2_P2 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B2_P2, A2 => B2_IN9, A1 => B2_IN13B, A0 => B2_IN17B);
GLB_B2_P1 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B2_P1, A2 => B2_IN5, A1 => B2_IN13B, A0 => B2_IN17B);
GLB_B2_P0 : PGAND4_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B2_P0, A3 => B2_IN0, A2 => B2_IN2, A1 => B2_IN5B,
A0 => B2_IN9B);
GLB_B2_G3 : PGORF72_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B2_G3, A1 => B2_F0, A0 => B2_F1);
GLB_B2_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B2_G1, A0 => B2_F5);
GLB_B2_G0 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B2_G0, A0 => B2_F5);
GLB_B2_F5 : PGORF73_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B2_F5, A2 => B2_P14, A1 => B2_P15, A0 => B2_P16);
GLB_P00_PIN : PGORF72_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => P00_PIN, A1 => B2_P10, A0 => B2_P11);
GLB_B2_F1 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B2_F1, A3 => B2_P4, A2 => B2_P5, A1 => B2_P6,
A0 => B2_P7);
GLB_B2_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B2_F0, A3 => B2_P0, A2 => B2_P1, A1 => B2_P2,
A0 => B2_P3);
GLB_OR_872 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => OR_872, A0 => B2_X3O);
GLB_OR_871 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => OR_871, A0 => B2_X2O);
GLB_P02_PIN : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => P02_PIN, A0 => B2_X0O);
GLB_B2_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B2_IN10, A0 => P0_N_174_grpi);
GLB_B2_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B2_IN4, A0 => P0_N_181_grpi);
GLB_B2_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B2_IN13, A0 => AND_1372_grpi);
GLB_B2_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B2_IN9, A0 => P0_N_176_grpi);
GLB_B2_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B2_IN5, A0 => P0_N_179_grpi);
GLB_B2_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B2_IN2, A0 => P0_N_180_grpi);
GLB_B2_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B2_IN0, A0 => P0_N_175_part1_grpi);
GLB_B2_X3O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B2_X3O, A1 => GND, A0 => B2_G0);
GLB_B2_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B2_X2O, A1 => GND, A0 => B2_G1);
GLB_B2_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B2_X0O, A1 => GND, A0 => B2_G3);
GLB_B2_IN10B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B2_IN10B, A0 => P0_N_174_grpi);
GLB_B2_IN4B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B2_IN4B, A0 => P0_N_181_grpi);
GLB_B2_IN17B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B2_IN17B, A0 => OR_872_ffb);
GLB_B2_IN13B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B2_IN13B, A0 => AND_1372_grpi);
GLB_B2_IN9B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B2_IN9B, A0 => P0_N_176_grpi);
GLB_B2_IN5B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B2_IN5B, A0 => P0_N_179_grpi);
GLB_B3_P19 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B3_P19, A4 => B3_IN1, A3 => B3_IN2, A2 => B3_IN4B,
A1 => B3_IN7, A0 => B3_IN9B);
GLB_B3_P18 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B3_P18, A4 => B3_IN1B, A3 => B3_IN4B, A2 => B3_IN7,
A1 => B3_IN8, A0 => B3_IN9);
GLB_B3_P17 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B3_P17, A4 => B3_IN1B, A3 => B3_IN4B, A2 => B3_IN7,
A1 => B3_IN9B, A0 => B3_IN13);
GLB_B3_P16 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B3_P16, A4 => B3_IN1, A3 => B3_IN4B, A2 => B3_IN6,
A1 => B3_IN7, A0 => B3_IN9);
GLB_B3_P15 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B3_P15, A4 => B3_IN1B, A3 => B3_IN4, A2 => B3_IN7B,
A1 => B3_IN9, A0 => B3_IN11);
GLB_B3_P14 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B3_P14, A4 => B3_IN1B, A3 => B3_IN4, A2 => B3_IN7B,
A1 => B3_IN9B, A0 => B3_IN14);
GLB_B3_P12 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B3_P12, A0 => B3_IN3);
GLB_B3_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B3_P8, A0 => B3_IN15);
GLB_B3_P3 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B3_P3, A4 => B3_IN0, A3 => B3_IN1B, A2 => B3_IN4B,
A1 => B3_IN7B, A0 => B3_IN9);
GLB_B3_P2 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B3_P2, A4 => B3_IN1, A3 => B3_IN4B, A2 => B3_IN7B,
A1 => B3_IN9B, A0 => B3_IN10);
GLB_B3_P1 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B3_P1, A4 => B3_IN1B, A3 => B3_IN4B, A2 => B3_IN5,
A1 => B3_IN7B, A0 => B3_IN9B);
GLB_B3_P0 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B3_P0, A4 => B3_IN1, A3 => B3_IN4B, A2 => B3_IN7B,
A1 => B3_IN9, A0 => B3_IN12);
GLB_B3_G3 : PGORF72_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B3_G3, A1 => B3_F0, A0 => B3_F5);
GLB_B3_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B3_G2, A0 => GND);
GLB_B3_F5 : PGORF76_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B3_F5, A5 => B3_P14, A4 => B3_P15, A3 => B3_P16,
A2 => B3_P19, A1 => B3_P17, A0 => B3_P18);
GLB_B3_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B3_F0, A3 => B3_P0, A2 => B3_P1, A1 => B3_P2,
A0 => B3_P3);
GLB_B3_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => B3_CD, A0 => B3_P12);
GLB_B3_CLK : PGBUFI_main
GENERIC MAP (TRISE => 0.500000 ns, TFALL => 0.500000 ns)
PORT MAP (Z0 => B3_CLK, A0 => D0_N_3_C_ck1f);
GLB_B3_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => B3_P8_xa, A0 => B3_P8);
GLB_OR_1392 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => OR_1392, A0 => B3_X0O);
GLB_B3_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN2, A0 => D0_N_15_grpi);
GLB_B3_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN8, A0 => D0_N_14_grpi);
GLB_B3_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN13, A0 => D0_N_13_grpi);
GLB_B3_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN7, A0 => N_38_part1_grpi);
GLB_B3_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN6, A0 => D0_N_16_grpi);
GLB_B3_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN11, A0 => D0_N_18_grpi);
GLB_B3_IN14 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN14, A0 => D0_N_99_grpi);
GLB_B3_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN4, A0 => N_37_grpi);
GLB_B3_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN3, A0 => RE_PRGMX_grp);
GLB_B3_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN15, A0 => DI0X_grp);
GLB_B3_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN0, A0 => D0_N_10_grpi);
GLB_B3_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN10, A0 => D0_N_11_grpi);
GLB_B3_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN5, A0 => D0_N_115_grpi);
GLB_B3_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN12, A0 => D0_N_12_grpi);
GLB_B3_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN9, A0 => N_40_grpi);
GLB_B3_IN1 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B3_IN1, A0 => N_39_grpi);
GLB_B3_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B3_X1O, A1 => B3_P8_xa, A0 => B3_G2);
GLB_B3_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B3_X0O, A1 => GND, A0 => B3_G3);
GLB_D0_N_3 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_3, RNESET => L2L_KEYWD_RESET_glbb, CD => B3_CD, CLK => B3_CLK,
D0 => B3_X1O);
GLB_B3_IN9B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B3_IN9B, A0 => N_40_grpi);
GLB_B3_IN1B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B3_IN1B, A0 => N_39_grpi);
GLB_B3_IN7B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B3_IN7B, A0 => N_38_part1_grpi);
GLB_B3_IN4B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B3_IN4B, A0 => N_37_grpi);
GLB_B4_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B4_P19, A0 => B4_IN7);
GLB_B4_P17 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B4_P17, A2 => B4_IN1B, A1 => B4_IN2, A0 => B4_IN9);
GLB_B4_P16 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B4_P16, A4 => B4_IN1B, A3 => B4_IN2B, A2 => B4_IN3B,
A1 => B4_IN10, A0 => B4_IN15);
GLB_B4_P15 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B4_P15, A2 => B4_IN1B, A1 => B4_IN3, A0 => B4_IN9);
GLB_B4_P14 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B4_P14, A2 => B4_IN0, A1 => B4_IN1, A0 => B4_IN17B);
GLB_B4_P13 : PGAND3_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B4_P13, A2 => B4_IN0B, A1 => B4_IN1, A0 => B4_IN17);
GLB_B4_P12 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B4_P12, A0 => B4_IN16);
GLB_B4_P11 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B4_P11, A6 => B4_IN1B, A5 => B4_IN2, A4 => B4_IN3B,
A3 => B4_IN4B, A2 => B4_IN5, A1 => B4_IN11, A0 => B4_IN14B);
GLB_B4_P10 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B4_P10, A6 => B4_IN1, A5 => B4_IN2B, A4 => B4_IN3B,
A3 => B4_IN4B, A2 => B4_IN5, A1 => B4_IN11, A0 => B4_IN14B);
GLB_B4_P7 : PGBUFI_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B4_P7, A0 => B4_IN1);
GLB_B4_P6 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B4_P6, A1 => B4_IN2B, A0 => B4_IN3B);
GLB_B4_P3 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B4_P3, A2 => B4_IN1, A1 => B4_IN10, A0 => B4_IN15);
GLB_B4_P2 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B4_P2, A4 => B4_IN0B, A3 => B4_IN1B, A2 => B4_IN2B,
A1 => B4_IN3B, A0 => B4_IN17);
GLB_B4_P1 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B4_P1, A4 => B4_IN0, A3 => B4_IN1B, A2 => B4_IN2B,
A1 => B4_IN3B, A0 => B4_IN17B);
GLB_B4_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B4_G3, A0 => B4_F1);
GLB_B4_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B4_G2, A0 => B4_F4);
GLB_B4_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B4_G1, A0 => B4_F5);
GLB_B4_G0 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B4_G0, A0 => B4_F0);
GLB_B4_F5 : PGORF75_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B4_F5, A4 => B4_P13, A3 => B4_P14, A2 => B4_P15,
A1 => B4_P16, A0 => B4_P17);
GLB_B4_F4 : PGORF72_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B4_F4, A1 => B4_P10, A0 => B4_P11);
GLB_B4_F1 : PGORF72_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B4_F1, A1 => B4_P6, A0 => B4_P7);
GLB_B4_F0 : PGORF73_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B4_F0, A2 => B4_P1, A1 => B4_P2, A0 => B4_P3);
GLB_B4_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => B4_CD, A0 => B4_P19);
GLB_B4_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => B4_CLKP, A0 => B4_P12);
GLB_B4_X2MO : PGBUFI_main
GENERIC MAP (TRISE => 0.500000 ns, TFALL => 0.500000 ns)
PORT MAP (Z0 => B4_X2MO, A0 => B4_G0);
GLB_P0_N_181_C : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => P0_N_181_C, A0 => B4_X1O);
GLB_P0_N_212 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => P0_N_212, A0 => B4_X0O);
GLB_B4_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B4_IN7, A0 => RE_CPUX_grp);
GLB_B4_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B4_IN9, A0 => P0_N_217_grpi);
GLB_B4_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B4_IN3, A0 => P0_N_240_grpi);
GLB_B4_IN16 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B4_IN16, A0 => P0_N_181_C_ffb);
GLB_B4_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B4_IN2, A0 => P0_N_239_grpi);
GLB_B4_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B4_IN11, A0 => CLKX_grp);
GLB_B4_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B4_IN5, A0 => ENX_grp);
GLB_B4_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B4_IN15, A0 => P0_N_181_grpi);
GLB_B4_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B4_IN10, A0 => P0_N_174_grpi);
GLB_B4_IN1 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B4_IN1, A0 => P0_N_238_grpi);
GLB_B4_IN17 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B4_IN17, A0 => P0_N_180_ffb);
GLB_B4_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B4_IN0, A0 => P0_N_175_part1_grpi);
GLB_B4_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B4_X2O, A1 => B4_X2MO, A0 => B4_G1);
GLB_B4_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B4_X1O, A1 => GND, A0 => B4_G2);
GLB_B4_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B4_X0O, A1 => GND, A0 => B4_G3);
GLB_P0_N_180 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_180, RNESET => L2L_KEYWD_RESET_glbb, CD => B4_CD, CLK => B4_CLKP,
D0 => B4_X2O);
GLB_B4_IN14B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B4_IN14B, A0 => F0_N_6_grpi);
GLB_B4_IN4B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B4_IN4B, A0 => F0_N_7_grpi);
GLB_B4_IN0B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B4_IN0B, A0 => P0_N_175_part1_grpi);
GLB_B4_IN17B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B4_IN17B, A0 => P0_N_180_ffb);
GLB_B4_IN3B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B4_IN3B, A0 => P0_N_240_grpi);
GLB_B4_IN2B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B4_IN2B, A0 => P0_N_239_grpi);
GLB_B4_IN1B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B4_IN1B, A0 => P0_N_238_grpi);
GLB_B5_P12 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B5_P12, A0 => B5_IN3);
GLB_B5_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B5_P8, A0 => B5_IN6);
GLB_B5_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B5_G2, A0 => GND);
GLB_B5_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => B5_CD, A0 => B5_P12);
GLB_B5_CLK : PGBUFI_main
GENERIC MAP (TRISE => 0.500000 ns, TFALL => 0.500000 ns)
PORT MAP (Z0 => B5_CLK, A0 => D0_N_3_C_ck1f);
GLB_B5_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => B5_P8_xa, A0 => B5_P8);
GLB_B5_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B5_IN3, A0 => RE_PRGMX_grp);
GLB_B5_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B5_IN6, A0 => DI2X_grp);
GLB_B5_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B5_X1O, A1 => B5_P8_xa, A0 => B5_G2);
GLB_D0_N_39 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_39, RNESET => L2L_KEYWD_RESET_glbb, CD => B5_CD, CLK => B5_CLK,
D0 => B5_X1O);
GLB_B6_P19 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B6_P19, A4 => B6_IN4B, A3 => B6_IN9B, A2 => B6_IN10,
A1 => B6_IN14, A0 => B6_IN15);
GLB_B6_P18 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B6_P18, A4 => B6_IN4B, A3 => B6_IN9, A2 => B6_IN10B,
A1 => B6_IN13, A0 => B6_IN15);
GLB_B6_P17 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B6_P17, A4 => B6_IN4B, A3 => B6_IN5, A2 => B6_IN9B,
A1 => B6_IN10B, A0 => B6_IN15);
GLB_B6_P16 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B6_P16, A4 => B6_IN0, A3 => B6_IN4B, A2 => B6_IN9,
A1 => B6_IN10, A0 => B6_IN15);
GLB_B6_P15 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B6_P15, A4 => B6_IN3, A3 => B6_IN4, A2 => B6_IN9B,
A1 => B6_IN10B, A0 => B6_IN15B);
GLB_B6_P14 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B6_P14, A4 => B6_IN4, A3 => B6_IN8, A2 => B6_IN9,
A1 => B6_IN10B, A0 => B6_IN15B);
GLB_B6_P13 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B6_P13, A0 => B6_IN12);
GLB_B6_P12 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B6_P12, A0 => B6_IN7);
GLB_B6_P3 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B6_P3, A4 => B6_IN1, A3 => B6_IN4B, A2 => B6_IN9B,
A1 => B6_IN10B, A0 => B6_IN15B);
GLB_B6_P2 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B6_P2, A4 => B6_IN2, A3 => B6_IN4B, A2 => B6_IN9,
A1 => B6_IN10B, A0 => B6_IN15B);
GLB_B6_P1 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B6_P1, A4 => B6_IN4B, A3 => B6_IN9B, A2 => B6_IN10,
A1 => B6_IN11, A0 => B6_IN15B);
GLB_B6_P0 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B6_P0, A4 => B6_IN4B, A3 => B6_IN6, A2 => B6_IN9,
A1 => B6_IN10, A0 => B6_IN15B);
GLB_B6_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B6_G3, A0 => GND);
GLB_B6_G0 : PGORF72_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B6_G0, A1 => B6_F0, A0 => B6_F5);
GLB_B6_F5 : PGORF76_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B6_F5, A5 => B6_P14, A4 => B6_P15, A3 => B6_P16,
A2 => B6_P19, A1 => B6_P17, A0 => B6_P18);
GLB_B6_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B6_F0, A3 => B6_P0, A2 => B6_P1, A1 => B6_P2,
A0 => B6_P3);
GLB_B6_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => B6_CD, A0 => B6_P12);
GLB_B6_CLK : PGBUFI_main
GENERIC MAP (TRISE => 0.500000 ns, TFALL => 0.500000 ns)
PORT MAP (Z0 => B6_CLK, A0 => D0_N_3_C_ck1f);
GLB_OR_1394 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => OR_1394, A0 => B6_X3O);
GLB_B6_P13_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => B6_P13_xa, A0 => B6_P13);
GLB_B6_IN14 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN14, A0 => D0_N_39_grpi);
GLB_B6_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN13, A0 => D0_N_38_grpi);
GLB_B6_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN5, A0 => D0_N_37_grpi);
GLB_B6_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN15, A0 => N_38_part2_grpi);
GLB_B6_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN0, A0 => D0_N_40_grpi);
GLB_B6_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN3, A0 => D0_N_41_grpi);
GLB_B6_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN8, A0 => D0_N_42_grpi);
GLB_B6_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN4, A0 => N_37_grpi);
GLB_B6_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN12, A0 => DI3X_grp);
GLB_B6_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN7, A0 => RE_PRGMX_grp);
GLB_B6_IN1 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN1, A0 => D0_N_114_grpi);
GLB_B6_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN2, A0 => D0_N_34_grpi);
GLB_B6_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN11, A0 => D0_N_35_grpi);
GLB_B6_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN10, A0 => N_39_grpi);
GLB_B6_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN9, A0 => N_40_grpi);
GLB_B6_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B6_IN6, A0 => D0_N_36_grpi);
GLB_B6_X3O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B6_X3O, A1 => GND, A0 => B6_G0);
GLB_B6_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B6_X0O, A1 => B6_P13_xa, A0 => B6_G3);
GLB_D0_N_101 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_101, RNESET => L2L_KEYWD_RESET_glbb, CD => B6_CD, CLK => B6_CLK,
D0 => B6_X0O);
GLB_B6_IN10B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B6_IN10B, A0 => N_39_grpi);
GLB_B6_IN9B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B6_IN9B, A0 => N_40_grpi);
GLB_B6_IN15B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B6_IN15B, A0 => N_38_part2_grpi);
GLB_B6_IN4B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B6_IN4B, A0 => N_37_grpi);
GLB_B7_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B7_P19, A0 => B7_IN7);
GLB_B7_P18 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B7_P18, A4 => B7_IN0, A3 => B7_IN4, A2 => B7_IN13,
A1 => B7_IN15, A0 => B7_IN17);
GLB_B7_P17 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B7_P17, A4 => B7_IN0, A3 => B7_IN4, A2 => B7_IN5B,
A1 => B7_IN6, A0 => B7_IN16B);
GLB_B7_P16 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B7_P16, A4 => B7_IN4, A3 => B7_IN6, A2 => B7_IN13,
A1 => B7_IN15, A0 => B7_IN17);
GLB_B7_P15 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B7_P15, A5 => B7_IN0, A4 => B7_IN4, A3 => B7_IN5B,
A2 => B7_IN15, A1 => B7_IN16B, A0 => B7_IN17);
GLB_B7_P14 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B7_P14, A5 => B7_IN4, A4 => B7_IN5B, A3 => B7_IN6,
A2 => B7_IN15, A1 => B7_IN16B, A0 => B7_IN17);
GLB_B7_P13 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B7_P13, A0 => B7_IN12);
GLB_B7_P12 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B7_P12, A0 => B7_IN9);
GLB_B7_P11 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B7_P11, A3 => B7_IN2B, A2 => B7_IN3B, A1 => B7_IN15,
A0 => B7_IN17B);
GLB_B7_P10 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B7_P10, A3 => B7_IN2B, A2 => B7_IN3B, A1 => B7_IN15B,
A0 => B7_IN17);
GLB_B7_P7 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B7_P7, A2 => B7_IN1B, A1 => B7_IN2, A0 => B7_IN8);
GLB_B7_P6 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B7_P6, A2 => B7_IN1B, A1 => B7_IN3, A0 => B7_IN8);
GLB_B7_P5 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B7_P5, A2 => B7_IN1, A1 => B7_IN15, A0 => B7_IN17B);
GLB_B7_P4 : PGAND3_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B7_P4, A2 => B7_IN1, A1 => B7_IN15B, A0 => B7_IN17);
GLB_B7_P3 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B7_P3, A1 => B7_IN4B, A0 => B7_IN10);
GLB_B7_P2 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B7_P2, A3 => B7_IN0, A2 => B7_IN4, A1 => B7_IN6,
A0 => B7_IN13);
GLB_B7_P1 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => B7_P1, A3 => B7_IN4, A2 => B7_IN11B, A1 => B7_IN13B,
A0 => B7_IN16);
GLB_B7_P0 : PGAND4_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => B7_P0, A3 => B7_IN4, A2 => B7_IN5, A1 => B7_IN11B,
A0 => B7_IN13B);
GLB_B7_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B7_G3, A0 => GND);
GLB_B7_G2 : PGORF72_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B7_G2, A1 => B7_F0, A0 => B7_F5);
GLB_B7_G1 : PGORF72_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => B7_G1, A1 => B7_F1, A0 => B7_F4);
GLB_B7_F5 : PGORF75_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B7_F5, A4 => B7_P14, A3 => B7_P15, A2 => B7_P16,
A1 => B7_P17, A0 => B7_P18);
GLB_B7_F4 : PGORF72_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B7_F4, A1 => B7_P10, A0 => B7_P11);
GLB_B7_F1 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B7_F1, A3 => B7_P4, A2 => B7_P5, A1 => B7_P6,
A0 => B7_P7);
GLB_B7_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => B7_F0, A3 => B7_P0, A2 => B7_P1, A1 => B7_P2,
A0 => B7_P3);
GLB_B7_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => B7_CD, A0 => B7_P19);
GLB_B7_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => B7_CLKP, A0 => B7_P12);
GLB_B7_P13_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => B7_P13_xa, A0 => B7_P13);
GLB_B7_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN7, A0 => RE_CPUX_grp);
GLB_B7_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN12, A0 => OR_1401_grpi);
GLB_B7_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN9, A0 => P0_N_177_C_grpi);
GLB_B7_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN2, A0 => P0_N_239_grpi);
GLB_B7_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN8, A0 => P0_N_218_grpi);
GLB_B7_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN3, A0 => P0_N_240_grpi);
GLB_B7_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN15, A0 => P0_N_181_grpi);
GLB_B7_IN17 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN17, A0 => P0_N_174_ffb);
GLB_B7_IN1 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN1, A0 => P0_N_238_grpi);
GLB_B7_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN10, A0 => P0_N_216_grpi);
GLB_B7_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN13, A0 => AND_1372_grpi);
GLB_B7_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN6, A0 => P0_N_180_grpi);
GLB_B7_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN0, A0 => P0_N_175_part1_grpi);
GLB_B7_IN16 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN16, A0 => P0_N_176_ffb);
GLB_B7_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN5, A0 => P0_N_179_grpi);
GLB_B7_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => B7_IN4, A0 => P0_N_212_grpi);
GLB_B7_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B7_X2O, A1 => GND, A0 => B7_G1);
GLB_B7_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B7_X1O, A1 => GND, A0 => B7_G2);
GLB_B7_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => B7_X0O, A1 => B7_P13_xa, A0 => B7_G3);
GLB_P0_N_174 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_174, RNESET => L2L_KEYWD_RESET_glbb, CD => B7_CD, CLK => B7_CLKP,
D0 => B7_X2O);
GLB_P0_N_176 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_176, RNESET => L2L_KEYWD_RESET_glbb, CD => B7_CD, CLK => B7_CLKP,
D0 => B7_X1O);
GLB_P0_N_177 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_177, RNESET => L2L_KEYWD_RESET_glbb, CD => B7_CD, CLK => B7_CLKP,
D0 => B7_X0O);
GLB_B7_IN16B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B7_IN16B, A0 => P0_N_176_ffb);
GLB_B7_IN5B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B7_IN5B, A0 => P0_N_179_grpi);
GLB_B7_IN3B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B7_IN3B, A0 => P0_N_240_grpi);
GLB_B7_IN2B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B7_IN2B, A0 => P0_N_239_grpi);
GLB_B7_IN1B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B7_IN1B, A0 => P0_N_238_grpi);
GLB_B7_IN17B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B7_IN17B, A0 => P0_N_174_ffb);
GLB_B7_IN15B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B7_IN15B, A0 => P0_N_181_grpi);
GLB_B7_IN4B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B7_IN4B, A0 => P0_N_212_grpi);
GLB_B7_IN13B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B7_IN13B, A0 => AND_1372_grpi);
GLB_B7_IN11B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => B7_IN11B, A0 => OR_872_grpi);
GLB_C0_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C0_P19, A0 => C0_IN12);
GLB_C0_P13 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C0_P13, A5 => C0_IN4, A4 => C0_IN9, A3 => C0_IN11,
A2 => C0_IN13B, A1 => C0_IN14, A0 => C0_IN15B);
GLB_C0_P12 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C0_P12, A5 => C0_IN4, A4 => C0_IN9, A3 => C0_IN11B,
A2 => C0_IN13B, A1 => C0_IN14B, A0 => C0_IN15);
GLB_C0_P8 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C0_P8, A5 => C0_IN4, A4 => C0_IN9, A3 => C0_IN11B,
A2 => C0_IN13B, A1 => C0_IN14B, A0 => C0_IN15B);
GLB_C0_P4 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C0_P4, A0 => C0_IN8);
GLB_C0_P0 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C0_P0, A0 => C0_IN2);
GLB_C0_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C0_G3, A0 => GND);
GLB_C0_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C0_G2, A0 => GND);
GLB_C0_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C0_G1, A0 => GND);
GLB_C0_G0 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C0_G0, A0 => GND);
GLB_C0_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => C0_CD, A0 => C0_P19);
GLB_C0_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => C0_CLKP, A0 => C0_P12);
GLB_C0_P0_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => C0_P0_xa, A0 => C0_P0);
GLB_C0_P4_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => C0_P4_xa, A0 => C0_P4);
GLB_C0_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => C0_P8_xa, A0 => C0_P8);
GLB_D0_N_116_C : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D0_N_116_C, A0 => C0_X1O);
GLB_C0_P13_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => C0_P13_xa, A0 => C0_P13);
GLB_D0_N_3_C : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D0_N_3_C, A0 => C0_X0O);
GLB_C0_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C0_IN12, A0 => RE_PRGMX_grp);
GLB_C0_IN14 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C0_IN14, A0 => N_39_grpi);
GLB_C0_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C0_IN11, A0 => N_38_part2_grpi);
GLB_C0_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C0_IN15, A0 => N_37_grpi);
GLB_C0_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C0_IN9, A0 => PRGMX_grp);
GLB_C0_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C0_IN4, A0 => CLKX_grp);
GLB_C0_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C0_IN8, A0 => DI3X_grp);
GLB_C0_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C0_IN2, A0 => DI2X_grp);
GLB_C0_X3O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C0_X3O, A1 => C0_P0_xa, A0 => C0_G0);
GLB_C0_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C0_X2O, A1 => C0_P4_xa, A0 => C0_G1);
GLB_C0_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C0_X1O, A1 => C0_P8_xa, A0 => C0_G2);
GLB_C0_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C0_X0O, A1 => C0_P13_xa, A0 => C0_G3);
GLB_D0_N_41 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_41, RNESET => L2L_KEYWD_RESET_glbb, CD => C0_CD, CLK => C0_CLKP,
D0 => C0_X3O);
GLB_D0_N_49 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_49, RNESET => L2L_KEYWD_RESET_glbb, CD => C0_CD, CLK => C0_CLKP,
D0 => C0_X2O);
GLB_C0_IN15B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C0_IN15B, A0 => N_37_grpi);
GLB_C0_IN14B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C0_IN14B, A0 => N_39_grpi);
GLB_C0_IN13B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C0_IN13B, A0 => N_40_grpi);
GLB_C0_IN11B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C0_IN11B, A0 => N_38_part2_grpi);
GLB_C1_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C1_P19, A0 => C1_IN8);
GLB_C1_P18 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C1_P18, A4 => C1_IN0, A3 => C1_IN2, A2 => C1_IN5,
A1 => C1_IN12, A0 => C1_IN15);
GLB_C1_P17 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C1_P17, A4 => C1_IN6B, A3 => C1_IN9, A2 => C1_IN12,
A1 => C1_IN15, A0 => C1_IN16B);
GLB_C1_P16 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C1_P16, A4 => C1_IN0, A3 => C1_IN2, A2 => C1_IN5,
A1 => C1_IN9, A0 => C1_IN15);
GLB_C1_P15 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C1_P15, A5 => C1_IN0, A4 => C1_IN5, A3 => C1_IN6B,
A2 => C1_IN12, A1 => C1_IN15, A0 => C1_IN16B);
GLB_C1_P14 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C1_P14, A5 => C1_IN0, A4 => C1_IN5, A3 => C1_IN6B,
A2 => C1_IN9, A1 => C1_IN15, A0 => C1_IN16B);
GLB_C1_P12 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C1_P12, A0 => C1_IN10);
GLB_C1_P11 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C1_P11, A2 => C1_IN0B, A1 => C1_IN5, A0 => C1_IN14);
GLB_C1_P10 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C1_P10, A3 => C1_IN0, A2 => C1_IN5B, A1 => C1_IN7B,
A0 => C1_IN13B);
GLB_C1_P9 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C1_P9, A3 => C1_IN0B, A2 => C1_IN5, A1 => C1_IN7B,
A0 => C1_IN13B);
GLB_C1_P7 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C1_P7, A2 => C1_IN3, A1 => C1_IN13, A0 => C1_IN14B);
GLB_C1_P6 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C1_P6, A2 => C1_IN3, A1 => C1_IN7, A0 => C1_IN14B);
GLB_C1_P5 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C1_P5, A2 => C1_IN0, A1 => C1_IN5B, A0 => C1_IN14);
GLB_C1_P4 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C1_P4, A0 => C1_IN11);
GLB_C1_P3 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C1_P3, A1 => C1_IN1, A0 => C1_IN15B);
GLB_C1_P2 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C1_P2, A3 => C1_IN2, A2 => C1_IN9, A1 => C1_IN12,
A0 => C1_IN15);
GLB_C1_P1 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C1_P1, A3 => C1_IN2B, A2 => C1_IN4B, A1 => C1_IN6,
A0 => C1_IN15);
GLB_C1_P0 : PGAND4_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C1_P0, A3 => C1_IN2B, A2 => C1_IN4B, A1 => C1_IN15,
A0 => C1_IN16);
GLB_C1_G3 : PGORF72_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C1_G3, A1 => C1_F1, A0 => C1_F4);
GLB_C1_G2 : PGORF72_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C1_G2, A1 => C1_F0, A0 => C1_F5);
GLB_C1_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C1_G1, A0 => GND);
GLB_C1_F5 : PGORF75_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C1_F5, A4 => C1_P14, A3 => C1_P15, A2 => C1_P16,
A1 => C1_P17, A0 => C1_P18);
GLB_C1_F4 : PGORF73_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C1_F4, A2 => C1_P9, A1 => C1_P10, A0 => C1_P11);
GLB_C1_F1 : PGORF73_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C1_F1, A2 => C1_P5, A1 => C1_P6, A0 => C1_P7);
GLB_C1_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C1_F0, A3 => C1_P0, A2 => C1_P1, A1 => C1_P2,
A0 => C1_P3);
GLB_C1_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => C1_CD, A0 => C1_P19);
GLB_C1_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => C1_CLKP, A0 => C1_P12);
GLB_C1_P4_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => C1_P4_xa, A0 => C1_P4);
GLB_C1_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN8, A0 => RE_CPUX_grp);
GLB_C1_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN10, A0 => P0_N_181_C_grpi);
GLB_C1_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN5, A0 => P0_N_174_grpi);
GLB_C1_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN13, A0 => P0_N_239_grpi);
GLB_C1_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN7, A0 => P0_N_240_grpi);
GLB_C1_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN3, A0 => P0_N_218_grpi);
GLB_C1_IN14 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN14, A0 => P0_N_238_grpi);
GLB_C1_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN0, A0 => P0_N_181_grpi);
GLB_C1_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN11, A0 => OR_1400_grpi);
GLB_C1_IN1 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN1, A0 => P0_N_216_grpi);
GLB_C1_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN12, A0 => P0_N_175_part2_grpi);
GLB_C1_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN9, A0 => P0_N_180_grpi);
GLB_C1_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN2, A0 => AND_1372_grpi);
GLB_C1_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN6, A0 => P0_N_176_grpi);
GLB_C1_IN16 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN16, A0 => P0_N_179_ffb);
GLB_C1_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C1_IN15, A0 => P0_N_212_grpi);
GLB_C1_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C1_X2O, A1 => C1_P4_xa, A0 => C1_G1);
GLB_C1_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C1_X1O, A1 => GND, A0 => C1_G2);
GLB_C1_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C1_X0O, A1 => GND, A0 => C1_G3);
GLB_P0_N_178 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_178, RNESET => L2L_KEYWD_RESET_glbb, CD => C1_CD, CLK => C1_CLKP,
D0 => C1_X2O);
GLB_P0_N_179 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_179, RNESET => L2L_KEYWD_RESET_glbb, CD => C1_CD, CLK => C1_CLKP,
D0 => C1_X1O);
GLB_P0_N_181 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_181, RNESET => L2L_KEYWD_RESET_glbb, CD => C1_CD, CLK => C1_CLKP,
D0 => C1_X0O);
GLB_C1_IN16B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C1_IN16B, A0 => P0_N_179_ffb);
GLB_C1_IN6B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C1_IN6B, A0 => P0_N_176_grpi);
GLB_C1_IN13B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C1_IN13B, A0 => P0_N_239_grpi);
GLB_C1_IN7B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C1_IN7B, A0 => P0_N_240_grpi);
GLB_C1_IN0B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C1_IN0B, A0 => P0_N_181_grpi);
GLB_C1_IN14B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C1_IN14B, A0 => P0_N_238_grpi);
GLB_C1_IN5B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C1_IN5B, A0 => P0_N_174_grpi);
GLB_C1_IN15B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C1_IN15B, A0 => P0_N_212_grpi);
GLB_C1_IN4B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C1_IN4B, A0 => OR_872_grpi);
GLB_C1_IN2B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C1_IN2B, A0 => AND_1372_grpi);
GLB_C2_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C2_P19, A0 => C2_IN8);
GLB_C2_P17 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C2_P17, A6 => C2_IN1B, A5 => C2_IN4, A4 => C2_IN7,
A3 => C2_IN9B, A2 => C2_IN10, A1 => C2_IN13B, A0 => C2_IN14B);
GLB_C2_P16 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C2_P16, A1 => C2_IN4B, A0 => C2_IN9);
GLB_C2_P15 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C2_P15, A1 => C2_IN9, A0 => C2_IN10B);
GLB_C2_P14 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C2_P14, A4 => C2_IN1B, A3 => C2_IN4, A2 => C2_IN9B,
A1 => C2_IN10, A0 => C2_IN11);
GLB_C2_P13 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C2_P13, A4 => C2_IN1, A3 => C2_IN4, A2 => C2_IN9B,
A1 => C2_IN10, A0 => C2_IN11B);
GLB_C2_P12 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C2_P12, A0 => C2_IN12);
GLB_C2_P11 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C2_P11, A1 => C2_IN16B, A0 => C2_IN17);
GLB_C2_P10 : PGAND10_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C2_P10, A9 => C2_IN1B, A8 => C2_IN4, A7 => C2_IN6B,
A6 => C2_IN7, A5 => C2_IN9B, A4 => C2_IN10, A3 => C2_IN11B,
A2 => C2_IN13B, A1 => C2_IN14B, A0 => C2_IN16);
GLB_C2_P8 : PGAND10_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C2_P8, A9 => C2_IN1B, A8 => C2_IN3B, A7 => C2_IN4,
A6 => C2_IN7, A5 => C2_IN9B, A4 => C2_IN10, A3 => C2_IN11B,
A2 => C2_IN13B, A1 => C2_IN14B, A0 => C2_IN17B);
GLB_C2_P7 : PGBUFI_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C2_P7, A0 => C2_IN17B);
GLB_C2_P6 : PGAND9_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C2_P6, A8 => C2_IN1B, A7 => C2_IN3, A6 => C2_IN4,
A5 => C2_IN7, A4 => C2_IN9B, A3 => C2_IN10, A2 => C2_IN11B,
A1 => C2_IN13B, A0 => C2_IN14B);
GLB_C2_P3 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C2_P3, A1 => C2_IN16, A0 => C2_IN17B);
GLB_C2_P2 : PGAND9_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C2_P2, A8 => C2_IN1B, A7 => C2_IN4, A6 => C2_IN7,
A5 => C2_IN9B, A4 => C2_IN10, A3 => C2_IN11B, A2 => C2_IN13B,
A1 => C2_IN14B, A0 => C2_IN16);
GLB_C2_P1 : PGAND10_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C2_P1, A9 => C2_IN1B, A8 => C2_IN4, A7 => C2_IN6,
A6 => C2_IN7, A5 => C2_IN9B, A4 => C2_IN10, A3 => C2_IN11B,
A2 => C2_IN13B, A1 => C2_IN14B, A0 => C2_IN17B);
GLB_C2_P0 : PGAND10_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C2_P0, A9 => C2_IN1B, A8 => C2_IN4, A7 => C2_IN6B,
A6 => C2_IN7, A5 => C2_IN9B, A4 => C2_IN10, A3 => C2_IN11B,
A2 => C2_IN13B, A1 => C2_IN14B, A0 => C2_IN17);
GLB_C2_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C2_G3, A0 => C2_F5);
GLB_C2_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C2_G2, A0 => C2_F1);
GLB_C2_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C2_G1, A0 => C2_F0);
GLB_C2_G0 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C2_G0, A0 => C2_F4);
GLB_C2_F5 : PGORF75_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C2_F5, A4 => C2_P13, A3 => C2_P14, A2 => C2_P15,
A1 => C2_P16, A0 => C2_P17);
GLB_C2_F4 : PGORF72_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C2_F4, A1 => C2_P10, A0 => C2_P11);
GLB_C2_F1 : PGORF72_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C2_F1, A1 => C2_P6, A0 => C2_P7);
GLB_C2_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C2_F0, A3 => C2_P0, A2 => C2_P1, A1 => C2_P2,
A0 => C2_P3);
GLB_C2_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => C2_CD, A0 => C2_P19);
GLB_C2_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => C2_CLKP, A0 => C2_P12);
GLB_C2_X2MO : PGBUFI_main
GENERIC MAP (TRISE => 0.500000 ns, TFALL => 0.500000 ns)
PORT MAP (Z0 => C2_X2MO, A0 => C2_G0);
GLB_C2_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => C2_P8_xa, A0 => C2_P8);
GLB_N_40_C : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => N_40_C, A0 => C2_X0O);
GLB_C2_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C2_IN8, A0 => RE_CPUX_grp);
GLB_C2_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C2_IN9, A0 => PRGMX_grp);
GLB_C2_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C2_IN11, A0 => F0_N_7_grpi);
GLB_C2_IN1 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C2_IN1, A0 => F0_N_6_grpi);
GLB_C2_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C2_IN12, A0 => N_40_C_grpi);
GLB_C2_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C2_IN3, A0 => P0_N_218_grpi);
GLB_C2_IN16 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C2_IN16, A0 => N_39_ffb);
GLB_C2_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C2_IN6, A0 => P0_N_217_grpi);
GLB_C2_IN17 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C2_IN17, A0 => N_40_ffb);
GLB_C2_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C2_IN10, A0 => ENX_grp);
GLB_C2_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C2_IN7, A0 => P0_N_240_grpi);
GLB_C2_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C2_IN4, A0 => CLKX_grp);
GLB_C2_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C2_X2O, A1 => C2_X2MO, A0 => C2_G1);
GLB_C2_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C2_X1O, A1 => C2_P8_xa, A0 => C2_G2);
GLB_C2_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C2_X0O, A1 => GND, A0 => C2_G3);
GLB_N_39 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => N_39, RNESET => L2L_KEYWD_RESET_glbb, CD => C2_CD, CLK => C2_CLKP,
D0 => C2_X2O);
GLB_N_40 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => N_40, RNESET => L2L_KEYWD_RESET_glbb, CD => C2_CD, CLK => C2_CLKP,
D0 => C2_X1O);
GLB_C2_IN4B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C2_IN4B, A0 => CLKX_grp);
GLB_C2_IN10B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C2_IN10B, A0 => ENX_grp);
GLB_C2_IN16B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C2_IN16B, A0 => N_39_ffb);
GLB_C2_IN3B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C2_IN3B, A0 => P0_N_218_grpi);
GLB_C2_IN17B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C2_IN17B, A0 => N_40_ffb);
GLB_C2_IN14B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C2_IN14B, A0 => P0_N_238_grpi);
GLB_C2_IN13B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C2_IN13B, A0 => P0_N_239_grpi);
GLB_C2_IN11B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C2_IN11B, A0 => F0_N_7_grpi);
GLB_C2_IN9B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C2_IN9B, A0 => PRGMX_grp);
GLB_C2_IN6B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C2_IN6B, A0 => P0_N_217_grpi);
GLB_C2_IN1B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C2_IN1B, A0 => F0_N_6_grpi);
GLB_C3_P19 : PGAND7_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C3_P19, A6 => C3_IN5, A5 => C3_IN7B, A4 => C3_IN9B,
A3 => C3_IN10, A2 => C3_IN11, A1 => C3_IN13, A0 => C3_IN15);
GLB_C3_P18 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C3_P18, A6 => C3_IN5, A5 => C3_IN7B, A4 => C3_IN9B,
A3 => C3_IN10, A2 => C3_IN11, A1 => C3_IN12, A0 => C3_IN15);
GLB_C3_P17 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C3_P17, A6 => C3_IN5, A5 => C3_IN6, A4 => C3_IN7B,
A3 => C3_IN9B, A2 => C3_IN11, A1 => C3_IN13, A0 => C3_IN15);
GLB_C3_P16 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C3_P16, A6 => C3_IN5, A5 => C3_IN6, A4 => C3_IN7,
A3 => C3_IN9, A2 => C3_IN11, A1 => C3_IN13, A0 => C3_IN15);
GLB_C3_P15 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C3_P15, A6 => C3_IN5, A5 => C3_IN7, A4 => C3_IN9,
A3 => C3_IN10, A2 => C3_IN11, A1 => C3_IN12, A0 => C3_IN15);
GLB_C3_P14 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C3_P14, A6 => C3_IN5, A5 => C3_IN7, A4 => C3_IN9,
A3 => C3_IN10, A2 => C3_IN11, A1 => C3_IN13, A0 => C3_IN15);
GLB_C3_P13 : PGAND7_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C3_P13, A6 => C3_IN5, A5 => C3_IN6, A4 => C3_IN7B,
A3 => C3_IN9B, A2 => C3_IN11, A1 => C3_IN12, A0 => C3_IN15);
GLB_C3_P12 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C3_P12, A5 => C3_IN7, A4 => C3_IN9, A3 => C3_IN10,
A2 => C3_IN12, A1 => C3_IN13, A0 => C3_IN15);
GLB_C3_P11 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C3_P11, A5 => C3_IN6, A4 => C3_IN7B, A3 => C3_IN9B,
A2 => C3_IN12, A1 => C3_IN13, A0 => C3_IN15);
GLB_C3_P10 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C3_P10, A5 => C3_IN7B, A4 => C3_IN9B, A3 => C3_IN10,
A2 => C3_IN12, A1 => C3_IN13, A0 => C3_IN15);
GLB_C3_P9 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C3_P9, A6 => C3_IN5, A5 => C3_IN6, A4 => C3_IN7,
A3 => C3_IN9, A2 => C3_IN11, A1 => C3_IN12, A0 => C3_IN15);
GLB_C3_P8 : PGAND2_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C3_P8, A1 => C3_IN6, A0 => C3_IN10);
GLB_C3_P7 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C3_P7, A4 => C3_IN6B, A3 => C3_IN7, A2 => C3_IN9B,
A1 => C3_IN10B, A0 => C3_IN15);
GLB_C3_P6 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C3_P6, A4 => C3_IN4B, A3 => C3_IN7B, A2 => C3_IN9,
A1 => C3_IN15, A0 => C3_IN16B);
GLB_C3_P5 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C3_P5, A4 => C3_IN4B, A3 => C3_IN7, A2 => C3_IN9B,
A1 => C3_IN15, A0 => C3_IN16B);
GLB_C3_P4 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C3_P4, A5 => C3_IN6, A4 => C3_IN7, A3 => C3_IN9,
A2 => C3_IN12, A1 => C3_IN13, A0 => C3_IN15);
GLB_C3_P3 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C3_P3, A1 => C3_IN0, A0 => C3_IN15B);
GLB_C3_P2 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C3_P2, A3 => C3_IN7, A2 => C3_IN9, A1 => C3_IN15,
A0 => C3_IN16);
GLB_C3_P1 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C3_P1, A3 => C3_IN7B, A2 => C3_IN9B, A1 => C3_IN15,
A0 => C3_IN16);
GLB_C3_P0 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C3_P0, A4 => C3_IN6B, A3 => C3_IN7B, A2 => C3_IN9,
A1 => C3_IN10B, A0 => C3_IN15);
GLB_C3_G3 : PGORF74_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C3_G3, A3 => C3_F0, A2 => C3_F1, A1 => C3_F4,
A0 => C3_F5);
GLB_C3_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C3_G2, A0 => GND);
GLB_C3_F5 : PGORF77_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C3_F5, A6 => C3_P13, A5 => C3_P14, A4 => C3_P15,
A3 => C3_P16, A2 => C3_P19, A1 => C3_P17, A0 => C3_P18);
GLB_C3_F4 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C3_F4, A3 => C3_P9, A2 => C3_P10, A1 => C3_P11,
A0 => C3_P12);
GLB_C3_F1 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C3_F1, A3 => C3_P4, A2 => C3_P5, A1 => C3_P6,
A0 => C3_P7);
GLB_C3_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C3_F0, A3 => C3_P0, A2 => C3_P1, A1 => C3_P2,
A0 => C3_P3);
GLB_C3_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => C3_P8_xa, A0 => C3_P8);
GLB_AND_1372 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => AND_1372, A0 => C3_X1O);
GLB_OR_1401 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => OR_1401, A0 => C3_X0O);
GLB_C3_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C3_IN11, A0 => P0_N_181_grpi);
GLB_C3_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C3_IN5, A0 => P0_N_174_grpi);
GLB_C3_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C3_IN10, A0 => P0_N_179_grpi);
GLB_C3_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C3_IN13, A0 => P0_N_180_grpi);
GLB_C3_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C3_IN12, A0 => P0_N_175_part2_grpi);
GLB_C3_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C3_IN6, A0 => P0_N_176_grpi);
GLB_C3_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C3_IN0, A0 => P0_N_214_grpi);
GLB_C3_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C3_IN7, A0 => P0_N_177_grpi);
GLB_C3_IN16 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C3_IN16, A0 => AND_1372_ffb);
GLB_C3_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C3_IN15, A0 => P0_N_212_grpi);
GLB_C3_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C3_IN9, A0 => P0_N_178_grpi);
GLB_C3_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C3_X1O, A1 => C3_P8_xa, A0 => C3_G2);
GLB_C3_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C3_X0O, A1 => GND, A0 => C3_G3);
GLB_C3_IN16B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C3_IN16B, A0 => AND_1372_ffb);
GLB_C3_IN4B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C3_IN4B, A0 => OR_872_grpi);
GLB_C3_IN15B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C3_IN15B, A0 => P0_N_212_grpi);
GLB_C3_IN9B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C3_IN9B, A0 => P0_N_178_grpi);
GLB_C3_IN10B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C3_IN10B, A0 => P0_N_179_grpi);
GLB_C3_IN7B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C3_IN7B, A0 => P0_N_177_grpi);
GLB_C3_IN6B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C3_IN6B, A0 => P0_N_176_grpi);
GLB_C4_P18 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C4_P18, A6 => C4_IN5, A5 => C4_IN7B, A4 => C4_IN9B,
A3 => C4_IN10, A2 => C4_IN11, A1 => C4_IN13, A0 => C4_IN15);
GLB_C4_P17 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C4_P17, A6 => C4_IN5, A5 => C4_IN7B, A4 => C4_IN9B,
A3 => C4_IN10, A2 => C4_IN11, A1 => C4_IN12, A0 => C4_IN15);
GLB_C4_P16 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C4_P16, A6 => C4_IN5, A5 => C4_IN7, A4 => C4_IN9,
A3 => C4_IN10, A2 => C4_IN11, A1 => C4_IN12, A0 => C4_IN15);
GLB_C4_P15 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C4_P15, A6 => C4_IN5, A5 => C4_IN7, A4 => C4_IN9,
A3 => C4_IN10, A2 => C4_IN11, A1 => C4_IN13, A0 => C4_IN15);
GLB_C4_P14 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C4_P14, A6 => C4_IN5, A5 => C4_IN6, A4 => C4_IN7B,
A3 => C4_IN9B, A2 => C4_IN11, A1 => C4_IN12, A0 => C4_IN15);
GLB_C4_P13 : PGAND7_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C4_P13, A6 => C4_IN5, A5 => C4_IN6, A4 => C4_IN7B,
A3 => C4_IN9B, A2 => C4_IN11, A1 => C4_IN13, A0 => C4_IN15);
GLB_C4_P12 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C4_P12, A5 => C4_IN7, A4 => C4_IN9, A3 => C4_IN10,
A2 => C4_IN12, A1 => C4_IN13, A0 => C4_IN15);
GLB_C4_P11 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C4_P11, A5 => C4_IN6, A4 => C4_IN7B, A3 => C4_IN9B,
A2 => C4_IN12, A1 => C4_IN13, A0 => C4_IN15);
GLB_C4_P10 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C4_P10, A5 => C4_IN7B, A4 => C4_IN9B, A3 => C4_IN10,
A2 => C4_IN12, A1 => C4_IN13, A0 => C4_IN15);
GLB_C4_P9 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C4_P9, A6 => C4_IN5, A5 => C4_IN6, A4 => C4_IN7,
A3 => C4_IN9, A2 => C4_IN11, A1 => C4_IN12, A0 => C4_IN15);
GLB_C4_P8 : PGAND7_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C4_P8, A6 => C4_IN5, A5 => C4_IN6, A4 => C4_IN7,
A3 => C4_IN9, A2 => C4_IN11, A1 => C4_IN13, A0 => C4_IN15);
GLB_C4_P7 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C4_P7, A4 => C4_IN6B, A3 => C4_IN7, A2 => C4_IN9B,
A1 => C4_IN10B, A0 => C4_IN15);
GLB_C4_P6 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C4_P6, A4 => C4_IN2B, A3 => C4_IN4B, A2 => C4_IN7B,
A1 => C4_IN9, A0 => C4_IN15);
GLB_C4_P5 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C4_P5, A4 => C4_IN2B, A3 => C4_IN4B, A2 => C4_IN7,
A1 => C4_IN9B, A0 => C4_IN15);
GLB_C4_P4 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C4_P4, A5 => C4_IN6, A4 => C4_IN7, A3 => C4_IN9,
A2 => C4_IN12, A1 => C4_IN13, A0 => C4_IN15);
GLB_C4_P3 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C4_P3, A1 => C4_IN0, A0 => C4_IN15B);
GLB_C4_P2 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C4_P2, A3 => C4_IN2, A2 => C4_IN7, A1 => C4_IN9,
A0 => C4_IN15);
GLB_C4_P1 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C4_P1, A3 => C4_IN2, A2 => C4_IN7B, A1 => C4_IN9B,
A0 => C4_IN15);
GLB_C4_P0 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C4_P0, A4 => C4_IN6B, A3 => C4_IN7B, A2 => C4_IN9,
A1 => C4_IN10B, A0 => C4_IN15);
GLB_C4_G3 : PGORF74_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C4_G3, A3 => C4_F0, A2 => C4_F1, A1 => C4_F4,
A0 => C4_F5);
GLB_C4_F5 : PGORF76_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C4_F5, A5 => C4_P13, A4 => C4_P14, A3 => C4_P15,
A2 => C4_P16, A1 => C4_P17, A0 => C4_P18);
GLB_C4_F4 : PGORF75_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C4_F4, A4 => C4_P8, A3 => C4_P9, A2 => C4_P10,
A1 => C4_P11, A0 => C4_P12);
GLB_C4_F1 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C4_F1, A3 => C4_P4, A2 => C4_P5, A1 => C4_P6,
A0 => C4_P7);
GLB_C4_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C4_F0, A3 => C4_P0, A2 => C4_P1, A1 => C4_P2,
A0 => C4_P3);
GLB_OR_1400 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => OR_1400, A0 => C4_X0O);
GLB_C4_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C4_IN10, A0 => P0_N_179_grpi);
GLB_C4_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C4_IN11, A0 => P0_N_181_grpi);
GLB_C4_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C4_IN5, A0 => P0_N_174_grpi);
GLB_C4_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C4_IN13, A0 => P0_N_180_grpi);
GLB_C4_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C4_IN12, A0 => P0_N_175_part2_grpi);
GLB_C4_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C4_IN6, A0 => P0_N_176_grpi);
GLB_C4_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C4_IN0, A0 => P0_N_214_grpi);
GLB_C4_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C4_IN7, A0 => P0_N_177_grpi);
GLB_C4_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C4_IN2, A0 => AND_1372_grpi);
GLB_C4_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C4_IN15, A0 => P0_N_212_grpi);
GLB_C4_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C4_IN9, A0 => P0_N_178_grpi);
GLB_C4_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C4_X0O, A1 => GND, A0 => C4_G3);
GLB_C4_IN4B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C4_IN4B, A0 => OR_872_grpi);
GLB_C4_IN2B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C4_IN2B, A0 => AND_1372_grpi);
GLB_C4_IN15B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C4_IN15B, A0 => P0_N_212_grpi);
GLB_C4_IN9B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C4_IN9B, A0 => P0_N_178_grpi);
GLB_C4_IN10B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C4_IN10B, A0 => P0_N_179_grpi);
GLB_C4_IN7B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C4_IN7B, A0 => P0_N_177_grpi);
GLB_C4_IN6B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C4_IN6B, A0 => P0_N_176_grpi);
GLB_C5_P19 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C5_P19, A4 => C5_IN0, A3 => C5_IN3B, A2 => C5_IN5,
A1 => C5_IN13, A0 => C5_IN15B);
GLB_C5_P18 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C5_P18, A4 => C5_IN3, A3 => C5_IN5B, A2 => C5_IN11,
A1 => C5_IN13B, A0 => C5_IN15B);
GLB_C5_P17 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C5_P17, A4 => C5_IN1, A3 => C5_IN3, A2 => C5_IN5B,
A1 => C5_IN13, A0 => C5_IN15B);
GLB_C5_P16 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C5_P16, A4 => C5_IN3B, A3 => C5_IN5, A2 => C5_IN7,
A1 => C5_IN13B, A0 => C5_IN15B);
GLB_C5_P15 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C5_P15, A4 => C5_IN3B, A3 => C5_IN5B, A2 => C5_IN12,
A1 => C5_IN13, A0 => C5_IN15B);
GLB_C5_P14 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C5_P14, A4 => C5_IN3B, A3 => C5_IN4, A2 => C5_IN5B,
A1 => C5_IN13B, A0 => C5_IN15);
GLB_C5_P12 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C5_P12, A0 => C5_IN8);
GLB_C5_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C5_P8, A0 => C5_IN9);
GLB_C5_P3 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C5_P3, A4 => C5_IN3B, A3 => C5_IN5B, A2 => C5_IN6,
A1 => C5_IN13B, A0 => C5_IN15B);
GLB_C5_P2 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C5_P2, A4 => C5_IN3, A3 => C5_IN5, A2 => C5_IN10,
A1 => C5_IN13, A0 => C5_IN15B);
GLB_C5_P1 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C5_P1, A4 => C5_IN2, A3 => C5_IN3, A2 => C5_IN5,
A1 => C5_IN13B, A0 => C5_IN15B);
GLB_C5_P0 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C5_P0, A4 => C5_IN3B, A3 => C5_IN5B, A2 => C5_IN13,
A1 => C5_IN14, A0 => C5_IN15);
GLB_C5_G3 : PGORF72_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C5_G3, A1 => C5_F0, A0 => C5_F5);
GLB_C5_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C5_G2, A0 => GND);
GLB_C5_F5 : PGORF76_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C5_F5, A5 => C5_P14, A4 => C5_P15, A3 => C5_P16,
A2 => C5_P19, A1 => C5_P17, A0 => C5_P18);
GLB_C5_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C5_F0, A3 => C5_P0, A2 => C5_P1, A1 => C5_P2,
A0 => C5_P3);
GLB_C5_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => C5_CD, A0 => C5_P12);
GLB_C5_CLK : PGBUFI_main
GENERIC MAP (TRISE => 0.500000 ns, TFALL => 0.500000 ns)
PORT MAP (Z0 => C5_CLK, A0 => D0_N_116_C_ck2f);
GLB_C5_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => C5_P8_xa, A0 => C5_P8);
GLB_OR_1396 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => OR_1396, A0 => C5_X0O);
GLB_C5_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN0, A0 => D0_N_6_grpi);
GLB_C5_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN11, A0 => D0_N_5_grpi);
GLB_C5_IN1 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN1, A0 => D0_N_4_grpi);
GLB_C5_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN7, A0 => D0_N_7_grpi);
GLB_C5_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN12, A0 => D0_N_8_grpi);
GLB_C5_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN4, A0 => D0_N_98_grpi);
GLB_C5_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN8, A0 => RE_PRGMX_grp);
GLB_C5_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN9, A0 => DI1X_grp);
GLB_C5_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN6, A0 => D0_N_116_grpi);
GLB_C5_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN10, A0 => D0_N_2_grpi);
GLB_C5_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN5, A0 => N_39_grpi);
GLB_C5_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN3, A0 => N_38_part1_grpi);
GLB_C5_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN2, A0 => D0_N_3_grpi);
GLB_C5_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN15, A0 => N_37_grpi);
GLB_C5_IN14 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN14, A0 => D0_N_31_grpi);
GLB_C5_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C5_IN13, A0 => N_40_grpi);
GLB_C5_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C5_X1O, A1 => C5_P8_xa, A0 => C5_G2);
GLB_C5_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C5_X0O, A1 => GND, A0 => C5_G3);
GLB_D0_N_115 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_115, RNESET => L2L_KEYWD_RESET_glbb, CD => C5_CD, CLK => C5_CLK,
D0 => C5_X1O);
GLB_C5_IN15B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C5_IN15B, A0 => N_37_grpi);
GLB_C5_IN13B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C5_IN13B, A0 => N_40_grpi);
GLB_C5_IN5B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C5_IN5B, A0 => N_39_grpi);
GLB_C5_IN3B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C5_IN3B, A0 => N_38_part1_grpi);
GLB_C6_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C6_P19, A0 => C6_IN8);
GLB_C6_P18 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C6_P18, A2 => C6_IN2, A1 => C6_IN13, A0 => C6_IN14B);
GLB_C6_P17 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C6_P17, A2 => C6_IN2, A1 => C6_IN12, A0 => C6_IN14B);
GLB_C6_P16 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C6_P16, A4 => C6_IN11B, A3 => C6_IN12B, A2 => C6_IN13B,
A1 => C6_IN14B, A0 => C6_IN16B);
GLB_C6_P15 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C6_P15, A4 => C6_IN5, A3 => C6_IN11, A2 => C6_IN12B,
A1 => C6_IN13B, A0 => C6_IN16);
GLB_C6_P14 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C6_P14, A4 => C6_IN5B, A3 => C6_IN12B, A2 => C6_IN13B,
A1 => C6_IN14B, A0 => C6_IN16B);
GLB_C6_P13 : PGAND3_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C6_P13, A2 => C6_IN5, A1 => C6_IN11, A0 => C6_IN14);
GLB_C6_P12 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C6_P12, A0 => C6_IN6);
GLB_C6_P3 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C6_P3, A2 => C6_IN9, A1 => C6_IN14, A0 => C6_IN16B);
GLB_C6_P2 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C6_P2, A2 => C6_IN9B, A1 => C6_IN14, A0 => C6_IN16);
GLB_C6_P1 : PGAND4_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C6_P1, A3 => C6_IN9B, A2 => C6_IN12B, A1 => C6_IN13B,
A0 => C6_IN14B);
GLB_C6_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C6_G3, A0 => C6_F5);
GLB_C6_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C6_G2, A0 => C6_F0);
GLB_C6_G0 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C6_G0, A0 => C6_F0);
GLB_C6_F5 : PGORF76_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C6_F5, A5 => C6_P13, A4 => C6_P14, A3 => C6_P15,
A2 => C6_P16, A1 => C6_P17, A0 => C6_P18);
GLB_C6_F0 : PGORF73_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C6_F0, A2 => C6_P1, A1 => C6_P2, A0 => C6_P3);
GLB_C6_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => C6_CD, A0 => C6_P19);
GLB_C6_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => C6_CLKP, A0 => C6_P12);
GLB_C6_X3MO : PGBUFI_main
GENERIC MAP (TRISE => 0.500000 ns, TFALL => 0.500000 ns)
PORT MAP (Z0 => C6_X3MO, A0 => C6_G3);
GLB_C6_X0MO : PGBUFI_main
GENERIC MAP (TRISE => 0.500000 ns, TFALL => 0.500000 ns)
PORT MAP (Z0 => C6_X0MO, A0 => C6_G2);
GLB_C6_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C6_IN8, A0 => RE_CPUX_grp);
GLB_C6_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C6_IN13, A0 => P0_N_239_grpi);
GLB_C6_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C6_IN12, A0 => P0_N_240_grpi);
GLB_C6_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C6_IN2, A0 => P0_N_217_grpi);
GLB_C6_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C6_IN11, A0 => P0_N_181_grpi);
GLB_C6_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C6_IN5, A0 => P0_N_174_grpi);
GLB_C6_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C6_IN6, A0 => P0_N_177_C_grpi);
GLB_C6_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C6_IN9, A0 => P0_N_180_grpi);
GLB_C6_IN16 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C6_IN16, A0 => P0_N_175_part2_ffb);
GLB_C6_IN14 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C6_IN14, A0 => P0_N_238_grpi);
GLB_C6_X3O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C6_X3O, A1 => C6_X3MO, A0 => C6_G0);
GLB_C6_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C6_X0O, A1 => C6_X0MO, A0 => C6_G3);
GLB_P0_N_175_part1 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_175_part1, RNESET => L2L_KEYWD_RESET_glbb, CD => C6_CD, CLK => C6_CLKP,
D0 => C6_X3O);
GLB_P0_N_175_part2 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_175_part2, RNESET => L2L_KEYWD_RESET_glbb, CD => C6_CD, CLK => C6_CLKP,
D0 => C6_X0O);
GLB_C6_IN11B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C6_IN11B, A0 => P0_N_181_grpi);
GLB_C6_IN5B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C6_IN5B, A0 => P0_N_174_grpi);
GLB_C6_IN16B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C6_IN16B, A0 => P0_N_175_part2_ffb);
GLB_C6_IN14B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C6_IN14B, A0 => P0_N_238_grpi);
GLB_C6_IN13B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C6_IN13B, A0 => P0_N_239_grpi);
GLB_C6_IN12B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C6_IN12B, A0 => P0_N_240_grpi);
GLB_C6_IN9B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C6_IN9B, A0 => P0_N_180_grpi);
GLB_C7_P19 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C7_P19, A4 => C7_IN1, A3 => C7_IN3, A2 => C7_IN5,
A1 => C7_IN6B, A0 => C7_IN11B);
GLB_C7_P18 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C7_P18, A4 => C7_IN2, A3 => C7_IN3, A2 => C7_IN5B,
A1 => C7_IN6, A0 => C7_IN11B);
GLB_C7_P17 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C7_P17, A4 => C7_IN3, A3 => C7_IN5B, A2 => C7_IN6B,
A1 => C7_IN10, A0 => C7_IN11B);
GLB_C7_P16 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C7_P16, A4 => C7_IN3, A3 => C7_IN5, A2 => C7_IN6,
A1 => C7_IN11B, A0 => C7_IN15);
GLB_C7_P15 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C7_P15, A4 => C7_IN3B, A3 => C7_IN5B, A2 => C7_IN6B,
A1 => C7_IN11, A0 => C7_IN12);
GLB_C7_P14 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C7_P14, A4 => C7_IN3B, A3 => C7_IN5B, A2 => C7_IN6,
A1 => C7_IN7, A0 => C7_IN11);
GLB_C7_P12 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C7_P12, A0 => C7_IN8);
GLB_C7_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C7_P8, A0 => C7_IN0);
GLB_C7_P3 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C7_P3, A4 => C7_IN3B, A3 => C7_IN5B, A2 => C7_IN6B,
A1 => C7_IN11B, A0 => C7_IN14);
GLB_C7_P2 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C7_P2, A4 => C7_IN3B, A3 => C7_IN5B, A2 => C7_IN6,
A1 => C7_IN11B, A0 => C7_IN13);
GLB_C7_P1 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => C7_P1, A4 => C7_IN3B, A3 => C7_IN4, A2 => C7_IN5,
A1 => C7_IN6B, A0 => C7_IN11B);
GLB_C7_P0 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => C7_P0, A4 => C7_IN3B, A3 => C7_IN5, A2 => C7_IN6,
A1 => C7_IN9, A0 => C7_IN11B);
GLB_C7_G3 : PGORF72_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C7_G3, A1 => C7_F0, A0 => C7_F5);
GLB_C7_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => C7_G2, A0 => GND);
GLB_C7_F5 : PGORF76_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C7_F5, A5 => C7_P14, A4 => C7_P15, A3 => C7_P16,
A2 => C7_P19, A1 => C7_P17, A0 => C7_P18);
GLB_C7_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => C7_F0, A3 => C7_P0, A2 => C7_P1, A1 => C7_P2,
A0 => C7_P3);
GLB_C7_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => C7_CD, A0 => C7_P12);
GLB_C7_CLK : PGBUFI_main
GENERIC MAP (TRISE => 0.500000 ns, TFALL => 0.500000 ns)
PORT MAP (Z0 => C7_CLK, A0 => D0_N_116_C_ck2f);
GLB_C7_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => C7_P8_xa, A0 => C7_P8);
GLB_OR_1395 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => OR_1395, A0 => C7_X0O);
GLB_C7_IN1 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN1, A0 => D0_N_39_grpi);
GLB_C7_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN2, A0 => D0_N_38_grpi);
GLB_C7_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN10, A0 => D0_N_37_grpi);
GLB_C7_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN15, A0 => D0_N_40_grpi);
GLB_C7_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN3, A0 => N_38_part1_grpi);
GLB_C7_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN12, A0 => D0_N_41_grpi);
GLB_C7_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN11, A0 => N_37_grpi);
GLB_C7_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN7, A0 => D0_N_42_grpi);
GLB_C7_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN8, A0 => RE_PRGMX_grp);
GLB_C7_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN0, A0 => DI0X_grp);
GLB_C7_IN14 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN14, A0 => D0_N_114_grpi);
GLB_C7_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN13, A0 => D0_N_34_grpi);
GLB_C7_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN4, A0 => D0_N_35_grpi);
GLB_C7_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN9, A0 => D0_N_36_grpi);
GLB_C7_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN6, A0 => N_40_grpi);
GLB_C7_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => C7_IN5, A0 => N_39_grpi);
GLB_C7_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C7_X1O, A1 => C7_P8_xa, A0 => C7_G2);
GLB_C7_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => C7_X0O, A1 => GND, A0 => C7_G3);
GLB_D0_N_116 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_116, RNESET => L2L_KEYWD_RESET_glbb, CD => C7_CD, CLK => C7_CLK,
D0 => C7_X1O);
GLB_C7_IN5B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C7_IN5B, A0 => N_39_grpi);
GLB_C7_IN6B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C7_IN6B, A0 => N_40_grpi);
GLB_C7_IN11B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C7_IN11B, A0 => N_37_grpi);
GLB_C7_IN3B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => C7_IN3B, A0 => N_38_part1_grpi);
GLB_D0_P19 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D0_P19, A4 => D0_IN0, A3 => D0_IN3B, A2 => D0_IN5,
A1 => D0_IN13, A0 => D0_IN15B);
GLB_D0_P18 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D0_P18, A4 => D0_IN3, A3 => D0_IN5B, A2 => D0_IN11,
A1 => D0_IN13B, A0 => D0_IN15B);
GLB_D0_P17 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D0_P17, A4 => D0_IN1, A3 => D0_IN3, A2 => D0_IN5B,
A1 => D0_IN13, A0 => D0_IN15B);
GLB_D0_P16 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D0_P16, A4 => D0_IN3B, A3 => D0_IN5, A2 => D0_IN7,
A1 => D0_IN13B, A0 => D0_IN15B);
GLB_D0_P15 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D0_P15, A4 => D0_IN3B, A3 => D0_IN5B, A2 => D0_IN12,
A1 => D0_IN13, A0 => D0_IN15B);
GLB_D0_P14 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D0_P14, A4 => D0_IN3B, A3 => D0_IN4, A2 => D0_IN5B,
A1 => D0_IN13B, A0 => D0_IN15);
GLB_D0_P12 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D0_P12, A0 => D0_IN8);
GLB_D0_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D0_P8, A0 => D0_IN9);
GLB_D0_P3 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D0_P3, A4 => D0_IN3B, A3 => D0_IN5B, A2 => D0_IN6,
A1 => D0_IN13B, A0 => D0_IN15B);
GLB_D0_P2 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D0_P2, A4 => D0_IN3, A3 => D0_IN5, A2 => D0_IN10,
A1 => D0_IN13, A0 => D0_IN15B);
GLB_D0_P1 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D0_P1, A4 => D0_IN2, A3 => D0_IN3, A2 => D0_IN5,
A1 => D0_IN13B, A0 => D0_IN15B);
GLB_D0_P0 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D0_P0, A4 => D0_IN3B, A3 => D0_IN5B, A2 => D0_IN13,
A1 => D0_IN14, A0 => D0_IN15);
GLB_D0_G3 : PGORF72_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D0_G3, A1 => D0_F0, A0 => D0_F5);
GLB_D0_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D0_G2, A0 => GND);
GLB_D0_F5 : PGORF76_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => D0_F5, A5 => D0_P14, A4 => D0_P15, A3 => D0_P16,
A2 => D0_P19, A1 => D0_P17, A0 => D0_P18);
GLB_D0_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => D0_F0, A3 => D0_P0, A2 => D0_P1, A1 => D0_P2,
A0 => D0_P3);
GLB_D0_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => D0_CD, A0 => D0_P12);
GLB_D0_CLK : PGBUFI_main
GENERIC MAP (TRISE => 0.500000 ns, TFALL => 0.500000 ns)
PORT MAP (Z0 => D0_CLK, A0 => D0_N_116_C_ck2f);
GLB_D0_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D0_P8_xa, A0 => D0_P8);
GLB_OR_1397 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => OR_1397, A0 => D0_X0O);
GLB_D0_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN0, A0 => D0_N_6_grpi);
GLB_D0_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN11, A0 => D0_N_5_grpi);
GLB_D0_IN1 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN1, A0 => D0_N_4_grpi);
GLB_D0_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN7, A0 => D0_N_7_grpi);
GLB_D0_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN12, A0 => D0_N_8_grpi);
GLB_D0_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN4, A0 => D0_N_98_grpi);
GLB_D0_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN8, A0 => RE_PRGMX_grp);
GLB_D0_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN9, A0 => DI2X_grp);
GLB_D0_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN6, A0 => D0_N_116_grpi);
GLB_D0_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN10, A0 => D0_N_2_grpi);
GLB_D0_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN5, A0 => N_39_grpi);
GLB_D0_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN3, A0 => N_38_part1_grpi);
GLB_D0_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN2, A0 => D0_N_3_grpi);
GLB_D0_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN15, A0 => N_37_grpi);
GLB_D0_IN14 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN14, A0 => D0_N_31_grpi);
GLB_D0_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D0_IN13, A0 => N_40_grpi);
GLB_D0_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D0_X1O, A1 => D0_P8_xa, A0 => D0_G2);
GLB_D0_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D0_X0O, A1 => GND, A0 => D0_G3);
GLB_D0_N_114 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_114, RNESET => L2L_KEYWD_RESET_glbb, CD => D0_CD, CLK => D0_CLK,
D0 => D0_X1O);
GLB_D0_IN15B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D0_IN15B, A0 => N_37_grpi);
GLB_D0_IN13B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D0_IN13B, A0 => N_40_grpi);
GLB_D0_IN5B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D0_IN5B, A0 => N_39_grpi);
GLB_D0_IN3B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D0_IN3B, A0 => N_38_part1_grpi);
GLB_D1_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D1_P19, A0 => D1_IN8);
GLB_D1_P17 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D1_P17, A6 => D1_IN3, A5 => D1_IN5, A4 => D1_IN6B,
A3 => D1_IN9, A2 => D1_IN10B, A1 => D1_IN11, A0 => D1_IN15);
GLB_D1_P16 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D1_P16, A5 => D1_IN3, A4 => D1_IN6B, A3 => D1_IN9,
A2 => D1_IN10B, A1 => D1_IN12, A0 => D1_IN15);
GLB_D1_P15 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D1_P15, A5 => D1_IN2, A4 => D1_IN3, A3 => D1_IN5,
A2 => D1_IN11, A1 => D1_IN12, A0 => D1_IN15);
GLB_D1_P14 : PGAND6_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D1_P14, A5 => D1_IN2, A4 => D1_IN3, A3 => D1_IN5,
A2 => D1_IN9, A1 => D1_IN11, A0 => D1_IN15);
GLB_D1_P13 : PGAND7_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D1_P13, A6 => D1_IN3, A5 => D1_IN5, A4 => D1_IN6B,
A3 => D1_IN10B, A2 => D1_IN11, A1 => D1_IN12, A0 => D1_IN15);
GLB_D1_P12 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D1_P12, A0 => D1_IN7);
GLB_D1_P11 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D1_P11, A1 => D1_IN5B, A0 => D1_IN9);
GLB_D1_P10 : PGAND2_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D1_P10, A1 => D1_IN9, A0 => D1_IN11B);
GLB_D1_P9 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D1_P9, A2 => D1_IN5, A1 => D1_IN9B, A0 => D1_IN11);
GLB_D1_P7 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D1_P7, A4 => D1_IN2, A3 => D1_IN3, A2 => D1_IN9,
A1 => D1_IN12, A0 => D1_IN15);
GLB_D1_P6 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D1_P6, A4 => D1_IN2B, A3 => D1_IN3, A2 => D1_IN4B,
A1 => D1_IN6, A0 => D1_IN15);
GLB_D1_P5 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D1_P5, A4 => D1_IN2B, A3 => D1_IN3, A2 => D1_IN4B,
A1 => D1_IN10, A0 => D1_IN15);
GLB_D1_P4 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D1_P4, A0 => D1_IN12);
GLB_D1_P3 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D1_P3, A2 => D1_IN3B, A1 => D1_IN13B, A0 => D1_IN16);
GLB_D1_P2 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D1_P2, A2 => D1_IN3B, A1 => D1_IN14B, A0 => D1_IN16);
GLB_D1_P1 : PGAND3_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D1_P1, A2 => D1_IN1, A1 => D1_IN3, A0 => D1_IN15B);
GLB_D1_P0 : PGAND4_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D1_P0, A3 => D1_IN3B, A2 => D1_IN13, A1 => D1_IN14,
A0 => D1_IN16B);
GLB_D1_G3 : PGORF73_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D1_G3, A2 => D1_F0, A1 => D1_F1, A0 => D1_F5);
GLB_D1_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D1_G1, A0 => D1_F4);
GLB_D1_G0 : PGORF73_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D1_G0, A2 => D1_F0, A1 => D1_F1, A0 => D1_F5);
GLB_D1_F5 : PGORF75_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => D1_F5, A4 => D1_P13, A3 => D1_P14, A2 => D1_P15,
A1 => D1_P16, A0 => D1_P17);
GLB_D1_F4 : PGORF73_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => D1_F4, A2 => D1_P9, A1 => D1_P10, A0 => D1_P11);
GLB_D1_F1 : PGORF73_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => D1_F1, A2 => D1_P5, A1 => D1_P6, A0 => D1_P7);
GLB_D1_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => D1_F0, A3 => D1_P0, A2 => D1_P1, A1 => D1_P2,
A0 => D1_P3);
GLB_D1_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => D1_CD, A0 => D1_P19);
GLB_D1_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => D1_CLKP, A0 => D1_P12);
GLB_D1_P4_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D1_P4_xa, A0 => D1_P4);
GLB_P01_PIN : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => P01_PIN, A0 => D1_X2O);
GLB_D1_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D1_IN8, A0 => RE_CPUX_grp);
GLB_D1_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D1_IN7, A0 => N_40_C_grpi);
GLB_D1_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D1_IN11, A0 => P0_N_181_grpi);
GLB_D1_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D1_IN5, A0 => P0_N_174_grpi);
GLB_D1_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D1_IN9, A0 => P0_N_180_grpi);
GLB_D1_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D1_IN2, A0 => AND_1372_grpi);
GLB_D1_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D1_IN6, A0 => P0_N_176_grpi);
GLB_D1_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D1_IN15, A0 => P0_N_212_grpi);
GLB_D1_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D1_IN10, A0 => P0_N_179_grpi);
GLB_D1_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D1_IN12, A0 => P0_N_175_part2_grpi);
GLB_D1_IN16 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D1_IN16, A0 => N_38_part2_ffb);
GLB_D1_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D1_IN3, A0 => P0_N_195_grpi);
GLB_D1_IN1 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D1_IN1, A0 => P0_N_216_grpi);
GLB_D1_IN14 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D1_IN14, A0 => N_39_grpi);
GLB_D1_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D1_IN13, A0 => N_40_grpi);
GLB_D1_X3O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D1_X3O, A1 => GND, A0 => D1_G0);
GLB_D1_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D1_X2O, A1 => D1_P4_xa, A0 => D1_G1);
GLB_D1_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D1_X0O, A1 => GND, A0 => D1_G3);
GLB_N_38_part1 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => N_38_part1, RNESET => L2L_KEYWD_RESET_glbb, CD => D1_CD, CLK => D1_CLKP,
D0 => D1_X3O);
GLB_N_38_part2 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => N_38_part2, RNESET => L2L_KEYWD_RESET_glbb, CD => D1_CD, CLK => D1_CLKP,
D0 => D1_X0O);
GLB_D1_IN10B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D1_IN10B, A0 => P0_N_179_grpi);
GLB_D1_IN6B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D1_IN6B, A0 => P0_N_176_grpi);
GLB_D1_IN5B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D1_IN5B, A0 => P0_N_174_grpi);
GLB_D1_IN11B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D1_IN11B, A0 => P0_N_181_grpi);
GLB_D1_IN9B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D1_IN9B, A0 => P0_N_180_grpi);
GLB_D1_IN4B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D1_IN4B, A0 => OR_872_grpi);
GLB_D1_IN2B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D1_IN2B, A0 => AND_1372_grpi);
GLB_D1_IN13B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D1_IN13B, A0 => N_40_grpi);
GLB_D1_IN14B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D1_IN14B, A0 => N_39_grpi);
GLB_D1_IN15B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D1_IN15B, A0 => P0_N_212_grpi);
GLB_D1_IN16B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D1_IN16B, A0 => N_38_part2_ffb);
GLB_D1_IN3B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D1_IN3B, A0 => P0_N_195_grpi);
GLB_D2_P19 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D2_P19, A4 => D2_IN3, A3 => D2_IN6B, A2 => D2_IN11B,
A1 => D2_IN14, A0 => D2_IN16);
GLB_D2_P18 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D2_P18, A4 => D2_IN3, A3 => D2_IN6, A2 => D2_IN7,
A1 => D2_IN11B, A0 => D2_IN14B);
GLB_D2_P17 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D2_P17, A4 => D2_IN3, A3 => D2_IN6B, A2 => D2_IN9,
A1 => D2_IN11B, A0 => D2_IN14B);
GLB_D2_P16 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D2_P16, A4 => D2_IN3, A3 => D2_IN6, A2 => D2_IN11B,
A1 => D2_IN13, A0 => D2_IN14);
GLB_D2_P15 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D2_P15, A4 => D2_IN3B, A3 => D2_IN4, A2 => D2_IN6,
A1 => D2_IN11, A0 => D2_IN14B);
GLB_D2_P14 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D2_P14, A4 => D2_IN1, A3 => D2_IN3B, A2 => D2_IN6B,
A1 => D2_IN11, A0 => D2_IN14B);
GLB_D2_P12 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D2_P12, A0 => D2_IN12);
GLB_D2_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D2_P8, A0 => D2_IN2);
GLB_D2_P3 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D2_P3, A4 => D2_IN3B, A3 => D2_IN6, A2 => D2_IN11B,
A1 => D2_IN14B, A0 => D2_IN15);
GLB_D2_P2 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D2_P2, A4 => D2_IN3B, A3 => D2_IN5, A2 => D2_IN6B,
A1 => D2_IN11B, A0 => D2_IN14);
GLB_D2_P1 : PGAND5_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D2_P1, A4 => D2_IN3B, A3 => D2_IN6B, A2 => D2_IN10,
A1 => D2_IN11B, A0 => D2_IN14B);
GLB_D2_P0 : PGAND5_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D2_P0, A4 => D2_IN3B, A3 => D2_IN6, A2 => D2_IN8,
A1 => D2_IN11B, A0 => D2_IN14);
GLB_D2_G3 : PGORF72_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D2_G3, A1 => D2_F0, A0 => D2_F5);
GLB_D2_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D2_G2, A0 => GND);
GLB_D2_F5 : PGORF76_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => D2_F5, A5 => D2_P14, A4 => D2_P15, A3 => D2_P16,
A2 => D2_P19, A1 => D2_P17, A0 => D2_P18);
GLB_D2_F0 : PGORF74_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => D2_F0, A3 => D2_P0, A2 => D2_P1, A1 => D2_P2,
A0 => D2_P3);
GLB_D2_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => D2_CD, A0 => D2_P12);
GLB_D2_CLK : PGBUFI_main
GENERIC MAP (TRISE => 0.500000 ns, TFALL => 0.500000 ns)
PORT MAP (Z0 => D2_CLK, A0 => D0_N_3_C_ck1f);
GLB_D2_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D2_P8_xa, A0 => D2_P8);
GLB_OR_1393 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => OR_1393, A0 => D2_X0O);
GLB_D2_IN16 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN16, A0 => D0_N_15_ffb);
GLB_D2_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN7, A0 => D0_N_14_grpi);
GLB_D2_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN9, A0 => D0_N_13_grpi);
GLB_D2_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN13, A0 => D0_N_16_grpi);
GLB_D2_IN3 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN3, A0 => N_38_part1_grpi);
GLB_D2_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN4, A0 => D0_N_18_grpi);
GLB_D2_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN11, A0 => N_37_grpi);
GLB_D2_IN1 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN1, A0 => D0_N_99_grpi);
GLB_D2_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN12, A0 => RE_PRGMX_grp);
GLB_D2_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN2, A0 => DI1X_grp);
GLB_D2_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN15, A0 => D0_N_10_grpi);
GLB_D2_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN5, A0 => D0_N_11_grpi);
GLB_D2_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN10, A0 => D0_N_115_grpi);
GLB_D2_IN14 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN14, A0 => N_39_grpi);
GLB_D2_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN8, A0 => D0_N_12_grpi);
GLB_D2_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D2_IN6, A0 => N_40_grpi);
GLB_D2_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D2_X1O, A1 => D2_P8_xa, A0 => D2_G2);
GLB_D2_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D2_X0O, A1 => GND, A0 => D2_G3);
GLB_D0_N_15 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_15, RNESET => L2L_KEYWD_RESET_glbb, CD => D2_CD, CLK => D2_CLK,
D0 => D2_X1O);
GLB_D2_IN14B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D2_IN14B, A0 => N_39_grpi);
GLB_D2_IN6B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D2_IN6B, A0 => N_40_grpi);
GLB_D2_IN11B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D2_IN11B, A0 => N_37_grpi);
GLB_D2_IN3B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D2_IN3B, A0 => N_38_part1_grpi);
GLB_D3_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D3_P19, A0 => D3_IN8);
GLB_D3_P13 : PGAND8_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D3_P13, A7 => D3_IN1B, A6 => D3_IN4, A5 => D3_IN5B,
A4 => D3_IN6B, A3 => D3_IN9B, A2 => D3_IN10, A1 => D3_IN11B,
A0 => D3_IN12);
GLB_D3_P12 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D3_P12, A5 => D3_IN3B, A4 => D3_IN4, A3 => D3_IN9,
A2 => D3_IN13B, A1 => D3_IN14B, A0 => D3_IN15);
GLB_D3_P11 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D3_P11, A6 => D3_IN1B, A5 => D3_IN4, A4 => D3_IN5B,
A3 => D3_IN6, A2 => D3_IN10, A1 => D3_IN11B, A0 => D3_IN12);
GLB_D3_P10 : PGAND7_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => D3_P10, A6 => D3_IN1B, A5 => D3_IN4, A4 => D3_IN5,
A3 => D3_IN6B, A2 => D3_IN10, A1 => D3_IN11B, A0 => D3_IN12);
GLB_D3_P4 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D3_P4, A0 => D3_IN2);
GLB_D3_P0 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D3_P0, A0 => D3_IN0);
GLB_D3_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D3_G3, A0 => GND);
GLB_D3_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D3_G1, A0 => GND);
GLB_D3_G0 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D3_G0, A0 => GND);
GLB_P0_N_177_C : PGORF72_main
GENERIC MAP (TRISE => 4.000000 ns, TFALL => 4.000000 ns)
PORT MAP (Z0 => P0_N_177_C, A1 => D3_P10, A0 => D3_P11);
GLB_D3_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => D3_CD, A0 => D3_P19);
GLB_D3_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => D3_CLKP, A0 => D3_P12);
GLB_D3_P0_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D3_P0_xa, A0 => D3_P0);
GLB_D3_P4_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D3_P4_xa, A0 => D3_P4);
GLB_D3_P13_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D3_P13_xa, A0 => D3_P13);
GLB_P0_N_195 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => P0_N_195, A0 => D3_X0O);
GLB_D3_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D3_IN8, A0 => RE_PRGMX_grp);
GLB_D3_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D3_IN15, A0 => N_37_grpi);
GLB_D3_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D3_IN9, A0 => PRGMX_grp);
GLB_D3_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D3_IN6, A0 => P0_N_239_grpi);
GLB_D3_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D3_IN12, A0 => P0_N_240_grpi);
GLB_D3_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D3_IN10, A0 => ENX_grp);
GLB_D3_IN5 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D3_IN5, A0 => P0_N_238_grpi);
GLB_D3_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D3_IN4, A0 => CLKX_grp);
GLB_D3_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D3_IN2, A0 => DI1X_grp);
GLB_D3_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D3_IN0, A0 => DI0X_grp);
GLB_D3_X3O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D3_X3O, A1 => D3_P0_xa, A0 => D3_G0);
GLB_D3_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D3_X2O, A1 => D3_P4_xa, A0 => D3_G1);
GLB_D3_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D3_X0O, A1 => D3_P13_xa, A0 => D3_G3);
GLB_D0_N_98 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_98, RNESET => L2L_KEYWD_RESET_glbb, CD => D3_CD, CLK => D3_CLKP,
D0 => D3_X3O);
GLB_D0_N_99 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_99, RNESET => L2L_KEYWD_RESET_glbb, CD => D3_CD, CLK => D3_CLKP,
D0 => D3_X2O);
GLB_D3_IN9B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D3_IN9B, A0 => PRGMX_grp);
GLB_D3_IN14B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D3_IN14B, A0 => N_39_grpi);
GLB_D3_IN13B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D3_IN13B, A0 => N_40_grpi);
GLB_D3_IN3B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D3_IN3B, A0 => N_38_part1_grpi);
GLB_D3_IN5B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D3_IN5B, A0 => P0_N_238_grpi);
GLB_D3_IN11B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D3_IN11B, A0 => F0_N_7_grpi);
GLB_D3_IN6B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D3_IN6B, A0 => P0_N_239_grpi);
GLB_D3_IN1B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D3_IN1B, A0 => F0_N_6_grpi);
GLB_D4_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D4_P19, A0 => D4_IN12);
GLB_D4_P13 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D4_P13, A0 => D4_IN2);
GLB_D4_P12 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D4_P12, A5 => D4_IN4, A4 => D4_IN6, A3 => D4_IN11,
A2 => D4_IN13, A1 => D4_IN14, A0 => D4_IN15B);
GLB_D4_P4 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D4_P4, A0 => D4_IN9);
GLB_D4_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D4_G3, A0 => GND);
GLB_D4_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D4_G1, A0 => GND);
GLB_D4_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => D4_CD, A0 => D4_P19);
GLB_D4_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => D4_CLKP, A0 => D4_P12);
GLB_D4_P4_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D4_P4_xa, A0 => D4_P4);
GLB_D4_P13_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D4_P13_xa, A0 => D4_P13);
GLB_D4_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D4_IN12, A0 => RE_PRGMX_grp);
GLB_D4_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D4_IN2, A0 => DI2X_grp);
GLB_D4_IN14 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D4_IN14, A0 => N_39_grpi);
GLB_D4_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D4_IN13, A0 => PRGMX_grp);
GLB_D4_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D4_IN11, A0 => N_38_part2_grpi);
GLB_D4_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D4_IN6, A0 => N_40_grpi);
GLB_D4_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D4_IN4, A0 => CLKX_grp);
GLB_D4_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D4_IN9, A0 => DI1X_grp);
GLB_D4_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D4_X2O, A1 => D4_P4_xa, A0 => D4_G1);
GLB_D4_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D4_X0O, A1 => D4_P13_xa, A0 => D4_G3);
GLB_D0_N_16 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_16, RNESET => L2L_KEYWD_RESET_glbb, CD => D4_CD, CLK => D4_CLKP,
D0 => D4_X2O);
GLB_D0_N_40 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_40, RNESET => L2L_KEYWD_RESET_glbb, CD => D4_CD, CLK => D4_CLKP,
D0 => D4_X0O);
GLB_D4_IN15B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D4_IN15B, A0 => N_37_grpi);
GLB_D5_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D5_P19, A0 => D5_IN12);
GLB_D5_P13 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D5_P13, A0 => D5_IN0);
GLB_D5_P12 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D5_P12, A5 => D5_IN4, A4 => D5_IN6, A3 => D5_IN11B,
A2 => D5_IN13, A1 => D5_IN14, A0 => D5_IN15B);
GLB_D5_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D5_P8, A0 => D5_IN8);
GLB_D5_P4 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D5_P4, A0 => D5_IN2);
GLB_D5_P0 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D5_P0, A0 => D5_IN9);
GLB_D5_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D5_G3, A0 => GND);
GLB_D5_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D5_G2, A0 => GND);
GLB_D5_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D5_G1, A0 => GND);
GLB_D5_G0 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D5_G0, A0 => GND);
GLB_D5_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => D5_CD, A0 => D5_P19);
GLB_D5_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => D5_CLKP, A0 => D5_P12);
GLB_D5_P0_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D5_P0_xa, A0 => D5_P0);
GLB_D5_P4_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D5_P4_xa, A0 => D5_P4);
GLB_D5_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D5_P8_xa, A0 => D5_P8);
GLB_D5_P13_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D5_P13_xa, A0 => D5_P13);
GLB_D5_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D5_IN12, A0 => RE_PRGMX_grp);
GLB_D5_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D5_IN0, A0 => DI0X_grp);
GLB_D5_IN14 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D5_IN14, A0 => N_39_grpi);
GLB_D5_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D5_IN13, A0 => PRGMX_grp);
GLB_D5_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D5_IN6, A0 => N_40_grpi);
GLB_D5_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D5_IN4, A0 => CLKX_grp);
GLB_D5_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D5_IN8, A0 => DI3X_grp);
GLB_D5_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D5_IN2, A0 => DI2X_grp);
GLB_D5_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D5_IN9, A0 => DI1X_grp);
GLB_D5_X3O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D5_X3O, A1 => D5_P0_xa, A0 => D5_G0);
GLB_D5_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D5_X2O, A1 => D5_P4_xa, A0 => D5_G1);
GLB_D5_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D5_X1O, A1 => D5_P8_xa, A0 => D5_G2);
GLB_D5_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D5_X0O, A1 => D5_P13_xa, A0 => D5_G3);
GLB_D0_N_12 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_12, RNESET => L2L_KEYWD_RESET_glbb, CD => D5_CD, CLK => D5_CLKP,
D0 => D5_X3O);
GLB_D0_N_36 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_36, RNESET => L2L_KEYWD_RESET_glbb, CD => D5_CD, CLK => D5_CLKP,
D0 => D5_X2O);
GLB_D0_N_104 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_104, RNESET => L2L_KEYWD_RESET_glbb, CD => D5_CD, CLK => D5_CLKP,
D0 => D5_X1O);
GLB_D0_N_6 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_6, RNESET => L2L_KEYWD_RESET_glbb, CD => D5_CD, CLK => D5_CLKP,
D0 => D5_X0O);
GLB_D5_IN15B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D5_IN15B, A0 => N_37_grpi);
GLB_D5_IN11B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D5_IN11B, A0 => N_38_part2_grpi);
GLB_D6_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D6_P19, A0 => D6_IN12);
GLB_D6_P13 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D6_P13, A0 => D6_IN0);
GLB_D6_P12 : PGAND4_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D6_P12, A3 => D6_IN1B, A2 => D6_IN4, A1 => D6_IN10,
A0 => D6_IN11);
GLB_D6_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D6_P8, A0 => D6_IN7);
GLB_D6_P4 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D6_P4, A0 => D6_IN15);
GLB_D6_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D6_G3, A0 => GND);
GLB_D6_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D6_G2, A0 => GND);
GLB_D6_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D6_G1, A0 => GND);
GLB_D6_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => D6_CD, A0 => D6_P19);
GLB_D6_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => D6_CLKP, A0 => D6_P12);
GLB_D6_P4_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D6_P4_xa, A0 => D6_P4);
GLB_D6_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D6_P8_xa, A0 => D6_P8);
GLB_D6_P13_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D6_P13_xa, A0 => D6_P13);
GLB_D6_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D6_IN12, A0 => RE_CPUX_grp);
GLB_D6_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D6_IN0, A0 => OR_1396_grpi);
GLB_D6_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D6_IN11, A0 => F0_N_7_grpi);
GLB_D6_IN10 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D6_IN10, A0 => ENX_grp);
GLB_D6_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D6_IN4, A0 => CLKX_grp);
GLB_D6_IN7 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D6_IN7, A0 => OR_1392_grpi);
GLB_D6_IN15 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D6_IN15, A0 => OR_1394_grpi);
GLB_D6_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D6_X2O, A1 => D6_P4_xa, A0 => D6_G1);
GLB_D6_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D6_X1O, A1 => D6_P8_xa, A0 => D6_G2);
GLB_D6_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D6_X0O, A1 => D6_P13_xa, A0 => D6_G3);
GLB_P0_N_238 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_238, RNESET => L2L_KEYWD_RESET_glbb, CD => D6_CD, CLK => D6_CLKP,
D0 => D6_X2O);
GLB_P0_N_239 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_239, RNESET => L2L_KEYWD_RESET_glbb, CD => D6_CD, CLK => D6_CLKP,
D0 => D6_X1O);
GLB_P0_N_240 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => P0_N_240, RNESET => L2L_KEYWD_RESET_glbb, CD => D6_CD, CLK => D6_CLKP,
D0 => D6_X0O);
GLB_D6_IN1B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D6_IN1B, A0 => F0_N_6_grpi);
GLB_D7_P19 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D7_P19, A0 => D7_IN12);
GLB_D7_P13 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D7_P13, A0 => D7_IN9);
GLB_D7_P12 : PGAND6_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D7_P12, A5 => D7_IN4, A4 => D7_IN6, A3 => D7_IN11,
A2 => D7_IN13, A1 => D7_IN14B, A0 => D7_IN15B);
GLB_D7_P8 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D7_P8, A0 => D7_IN2);
GLB_D7_P4 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D7_P4, A0 => D7_IN0);
GLB_D7_P0 : PGBUFI_main
GENERIC MAP (TRISE => 3.700000 ns, TFALL => 3.700000 ns)
PORT MAP (Z0 => D7_P0, A0 => D7_IN8);
GLB_D7_G3 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D7_G3, A0 => GND);
GLB_D7_G2 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D7_G2, A0 => GND);
GLB_D7_G1 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D7_G1, A0 => GND);
GLB_D7_G0 : PGBUFI_main
GENERIC MAP (TRISE => 1.600000 ns, TFALL => 1.600000 ns)
PORT MAP (Z0 => D7_G0, A0 => GND);
GLB_D7_CD : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => D7_CD, A0 => D7_P19);
GLB_D7_CLKP : PGBUFI_main
GENERIC MAP (TRISE => 1.900000 ns, TFALL => 1.900000 ns)
PORT MAP (Z0 => D7_CLKP, A0 => D7_P12);
GLB_D7_P0_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D7_P0_xa, A0 => D7_P0);
GLB_D7_P4_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D7_P4_xa, A0 => D7_P4);
GLB_D7_P8_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D7_P8_xa, A0 => D7_P8);
GLB_D7_P13_xa : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => D7_P13_xa, A0 => D7_P13);
GLB_D7_IN12 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D7_IN12, A0 => RE_PRGMX_grp);
GLB_D7_IN9 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D7_IN9, A0 => DI1X_grp);
GLB_D7_IN13 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D7_IN13, A0 => PRGMX_grp);
GLB_D7_IN11 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D7_IN11, A0 => N_38_part2_grpi);
GLB_D7_IN6 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D7_IN6, A0 => N_40_grpi);
GLB_D7_IN4 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D7_IN4, A0 => CLKX_grp);
GLB_D7_IN2 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D7_IN2, A0 => DI2X_grp);
GLB_D7_IN0 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D7_IN0, A0 => DI0X_grp);
GLB_D7_IN8 : PGBUFI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (Z0 => D7_IN8, A0 => DI3X_grp);
GLB_D7_X3O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D7_X3O, A1 => D7_P0_xa, A0 => D7_G0);
GLB_D7_X2O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D7_X2O, A1 => D7_P4_xa, A0 => D7_G1);
GLB_D7_X1O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D7_X1O, A1 => D7_P8_xa, A0 => D7_G2);
GLB_D7_X0O : PGXOR2_main
GENERIC MAP (TRISE => 0.800000 ns, TFALL => 0.800000 ns)
PORT MAP (Z0 => D7_X0O, A1 => D7_P13_xa, A0 => D7_G3);
GLB_D0_N_102 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_102, RNESET => L2L_KEYWD_RESET_glbb, CD => D7_CD, CLK => D7_CLKP,
D0 => D7_X3O);
GLB_D0_N_4 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_4, RNESET => L2L_KEYWD_RESET_glbb, CD => D7_CD, CLK => D7_CLKP,
D0 => D7_X2O);
GLB_D0_N_38 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_38, RNESET => L2L_KEYWD_RESET_glbb, CD => D7_CD, CLK => D7_CLKP,
D0 => D7_X1O);
GLB_D0_N_14 : PGDFFR_main
GENERIC MAP (HLCQ => 2.400000 ns, LHCQ => 2.400000 ns, HLRQ => 6.800000 ns, SUD0 => 1.000000 ns,
SUD1 => 1.000000 ns, HOLDD0 => 8.300000 ns, HOLDD1 => 8.300000 ns, POSC1 => 5.000000 ns,
POSC0 => 5.000000 ns, NEGC1 => 5.000000 ns, NEGC0 => 5.000000 ns, RECRC => 0.000000 ns,
HOLDRC => 0.000000 ns)
PORT MAP (Q0 => D0_N_14, RNESET => L2L_KEYWD_RESET_glbb, CD => D7_CD, CLK => D7_CLKP,
D0 => D7_X0O);
GLB_D7_IN15B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D7_IN15B, A0 => N_37_grpi);
GLB_D7_IN14B : PGINVI_main
GENERIC MAP (TRISE => 1.100000 ns, TFALL => 1.100000 ns)
PORT MAP (ZN0 => D7_IN14B, A0 => N_39_grpi);
IOC_L2L_KEYWD_RESET : PXIN_main
GENERIC MAP (TRISE => 3.100000 ns, TFALL => 3.100000 ns)
PORT MAP (Z0 => L2L_KEYWD_RESETb, XI0 => XRESET);
IOC_IO51_IBUFO : PXIN_main
GENERIC MAP (TRISE => 0.300000 ns, TFALL => 0.300000 ns)
PORT MAP (Z0 => IO51_IBUFO, XI0 => RE_PRGM);
IOC_IO3_IBUFO : PXIN_main
GENERIC MAP (TRISE => 0.300000 ns, TFALL => 0.300000 ns)
PORT MAP (Z0 => IO3_IBUFO, XI0 => RE_CPU);
IOC_IO18_IBUFO : PXIN_main
GENERIC MAP (TRISE => 0.300000 ns, TFALL => 0.300000 ns)
PORT MAP (Z0 => IO18_IBUFO, XI0 => PRGM);
IOC_IO53_IBUFO : PXIN_main
GENERIC MAP (TRISE => 0.300000 ns, TFALL => 0.300000 ns)
PORT MAP (Z0 => IO53_IBUFO, XI0 => EN);
IOC_IO39_IBUFO : PXIN_main
GENERIC MAP (TRISE => 0.300000 ns, TFALL => 0.300000 ns)
PORT MAP (Z0 => IO39_IBUFO, XI0 => DI3);
IOC_IO38_IBUFO : PXIN_main
GENERIC MAP (TRISE => 0.300000 ns, TFALL => 0.300000 ns)
PORT MAP (Z0 => IO38_IBUFO, XI0 => DI2);
IOC_IO22_IBUFO : PXIN_main
GENERIC MAP (TRISE => 0.300000 ns, TFALL => 0.300000 ns)
PORT MAP (Z0 => IO22_IBUFO, XI0 => DI1);
IOC_IO15_IBUFO : PXIN_main
GENERIC MAP (TRISE => 0.300000 ns, TFALL => 0.300000 ns)
PORT MAP (Z0 => IO15_IBUFO, XI0 => DI0);
IOC_IO47_IBUFO : PXIN_main
GENERIC MAP (TRISE => 0.300000 ns, TFALL => 0.300000 ns)
PORT MAP (Z0 => IO47_IBUFO, XI0 => CLK);
IOC_P03 : PXOUT_main
GENERIC MAP (TRISE => 2.200000 ns, TFALL => 2.200000 ns)
PORT MAP (XO0 => P03, A0 => IO16_OBUFI);
IOC_IO16_OBUFI : PGBUFI_main
GENERIC MAP (TRISE => 0.400000 ns, TFALL => 0.400000 ns)
PORT MAP (Z0 => IO16_OBUFI, A0 => P03_PIN_iomux);
IOC_P02 : PXOUT_main
GENERIC MAP (TRISE => 2.200000 ns, TFALL => 2.200000 ns)
PORT MAP (XO0 => P02, A0 => IO20_OBUFI);
IOC_IO20_OBUFI : PGBUFI_main
GENERIC MAP (TRISE => 0.400000 ns, TFALL => 0.400000 ns)
PORT MAP (Z0 => IO20_OBUFI, A0 => P02_PIN_iomux);
IOC_P01 : PXOUT_main
GENERIC MAP (TRISE => 2.200000 ns, TFALL => 2.200000 ns)
PORT MAP (XO0 => P01, A0 => IO50_OBUFI);
IOC_IO50_OBUFI : PGBUFI_main
GENERIC MAP (TRISE => 0.400000 ns, TFALL => 0.400000 ns)
PORT MAP (Z0 => IO50_OBUFI, A0 => P01_PIN_iomux);
IOC_P00 : PXOUT_main
GENERIC MAP (TRISE => 2.200000 ns, TFALL => 2.200000 ns)
PORT MAP (XO0 => P00, A0 => IO17_OBUFI);
IOC_IO17_OBUFI : PGBUFI_main
GENERIC MAP (TRISE => 0.400000 ns, TFALL => 0.400000 ns)
PORT MAP (Z0 => IO17_OBUFI, A0 => P00_PIN_iomux);
GRP_N_41_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => N_41_grpi, A0 => N_41);
GRP_D0_N_100_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => D0_N_100_grpi, A0 => D0_N_100);
GRP_D0_N_101_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => D0_N_101_grpi, A0 => D0_N_101);
GRP_D0_N_102_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => D0_N_102_grpi, A0 => D0_N_102);
GRP_D0_N_104_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => D0_N_104_grpi, A0 => D0_N_104);
GRP_D0_N_105_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => D0_N_105_grpi, A0 => D0_N_105);
GRP_D0_N_106_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => D0_N_106_grpi, A0 => D0_N_106);
GRP_D0_N_113_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => D0_N_113_grpi, A0 => D0_N_113);
GRP_D0_N_127_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => D0_N_127_grpi, A0 => D0_N_127);
GRP_D0_N_49_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => D0_N_49_grpi, A0 => D0_N_49);
GRP_D0_N_50_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => D0_N_50_grpi, A0 => D0_N_50);
GRP_N_37_ffb : PGBUFI_main
GENERIC MAP (TRISE => 1.300000 ns, TFALL => 1.300000 ns)
PORT MAP (Z0 => N_37_ffb, A0 => N_37);
GRP_N_37_grpi : PGBUFI_main
GENERIC MAP (TRISE => 4.100000 ns, TFALL => 4.100000 ns)
PORT MAP (Z0 => N_37_grpi, A0 => N_37);
GRP_N_38_part2_ffb : PGBUFI_main
GENERIC MAP (TRISE => 1.300000 ns, TFALL => 1.300000 ns)
PORT MAP (Z0 => N_38_part2_ffb, A0 => N_38_part2);
GRP_N_38_part2_grpi : PGBUFI_main
GENERIC MAP (TRISE => 3.600000 ns, TFALL => 3.600000 ns)
PORT MAP (Z0 => N_38_part2_grpi, A0 => N_38_part2);
GRP_N_39_ffb : PGBUFI_main
GENERIC MAP (TRISE => 1.300000 ns, TFALL => 1.300000 ns)
PORT MAP (Z0 => N_39_ffb, A0 => N_39);
GRP_N_39_grpi : PGBUFI_main
GENERIC MAP (TRISE => 4.300000 ns, TFALL => 4.300000 ns)
PORT MAP (Z0 => N_39_grpi, A0 => N_39);
GRP_N_40_ffb : PGBUFI_main
GENERIC MAP (TRISE => 1.300000 ns, TFALL => 1.300000 ns)
PORT MAP (Z0 => N_40_ffb, A0 => N_40);
GRP_N_40_grpi : PGBUFI_main
GENERIC MAP (TRISE => 4.300000 ns, TFALL => 4.300000 ns)
PORT MAP (Z0 => N_40_grpi, A0 => N_40);
GRP_F0_N_7_ffb : PGBUFI_main
GENERIC MAP (TRISE => 1.300000 ns, TFALL => 1.300000 ns)
PORT MAP (Z0 => F0_N_7_ffb, A0 => F0_N_7);
GRP_F0_N_7_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.900000 ns, TFALL => 2.900000 ns)
PORT MAP (Z0 => F0_N_7_grpi, A0 => F0_N_7);
GRP_F0_N_6_ffb : PGBUFI_main
GENERIC MAP (TRISE => 1.300000 ns, TFALL => 1.300000 ns)
PORT MAP (Z0 => F0_N_6_ffb, A0 => F0_N_6);
GRP_F0_N_6_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.900000 ns, TFALL => 2.900000 ns)
PORT MAP (Z0 => F0_N_6_grpi, A0 => F0_N_6);
GRP_CLKX_grp : PGBUFI_main
GENERIC MAP (TRISE => 3.900000 ns, TFALL => 3.900000 ns)
PORT MAP (Z0 => CLKX_grp, A0 => IO47_IBUFO);
GRP_ENX_grp : PGBUFI_main
GENERIC MAP (TRISE => 3.000000 ns, TFALL => 3.000000 ns)
PORT MAP (Z0 => ENX_grp, A0 => IO53_IBUFO);
GRP_RE_CPUX_grp : PGBUFI_main
GENERIC MAP (TRISE => 3.400000 ns, TFALL => 3.400000 ns)
PORT MAP (Z0 => RE_CPUX_grp, A0 => IO3_IBUFO);
GRP_D0_N_42_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_42_grpi, A0 => D0_N_42);
GRP_D0_N_31_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_31_grpi, A0 => D0_N_31);
GRP_D0_N_18_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_18_grpi, A0 => D0_N_18);
GRP_DI0X_grp : PGBUFI_main
GENERIC MAP (TRISE => 3.400000 ns, TFALL => 3.400000 ns)
PORT MAP (Z0 => DI0X_grp, A0 => IO15_IBUFO);
GRP_DI1X_grp : PGBUFI_main
GENERIC MAP (TRISE => 3.400000 ns, TFALL => 3.400000 ns)
PORT MAP (Z0 => DI1X_grp, A0 => IO22_IBUFO);
GRP_DI2X_grp : PGBUFI_main
GENERIC MAP (TRISE => 3.400000 ns, TFALL => 3.400000 ns)
PORT MAP (Z0 => DI2X_grp, A0 => IO38_IBUFO);
GRP_DI3X_grp : PGBUFI_main
GENERIC MAP (TRISE => 3.400000 ns, TFALL => 3.400000 ns)
PORT MAP (Z0 => DI3X_grp, A0 => IO39_IBUFO);
GRP_PRGMX_grp : PGBUFI_main
GENERIC MAP (TRISE => 3.500000 ns, TFALL => 3.500000 ns)
PORT MAP (Z0 => PRGMX_grp, A0 => IO18_IBUFO);
GRP_RE_PRGMX_grp : PGBUFI_main
GENERIC MAP (TRISE => 4.200000 ns, TFALL => 4.200000 ns)
PORT MAP (Z0 => RE_PRGMX_grp, A0 => IO51_IBUFO);
GRP_D0_N_7_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_7_grpi, A0 => D0_N_7);
GRP_D0_N_35_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_35_grpi, A0 => D0_N_35);
GRP_D0_N_11_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_11_grpi, A0 => D0_N_11);
GRP_N_40_C_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => N_40_C_grpi, A0 => N_40_C);
GRP_P0_N_176_ffb : PGBUFI_main
GENERIC MAP (TRISE => 1.300000 ns, TFALL => 1.300000 ns)
PORT MAP (Z0 => P0_N_176_ffb, A0 => P0_N_176);
GRP_P0_N_176_grpi : PGBUFI_main
GENERIC MAP (TRISE => 3.100000 ns, TFALL => 3.100000 ns)
PORT MAP (Z0 => P0_N_176_grpi, A0 => P0_N_176);
GRP_P0_N_177_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.800000 ns, TFALL => 2.800000 ns)
PORT MAP (Z0 => P0_N_177_grpi, A0 => P0_N_177);
GRP_P0_N_178_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.800000 ns, TFALL => 2.800000 ns)
PORT MAP (Z0 => P0_N_178_grpi, A0 => P0_N_178);
GRP_P0_N_179_ffb : PGBUFI_main
GENERIC MAP (TRISE => 1.300000 ns, TFALL => 1.300000 ns)
PORT MAP (Z0 => P0_N_179_ffb, A0 => P0_N_179);
GRP_P0_N_179_grpi : PGBUFI_main
GENERIC MAP (TRISE => 3.100000 ns, TFALL => 3.100000 ns)
PORT MAP (Z0 => P0_N_179_grpi, A0 => P0_N_179);
GRP_P0_N_195_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => P0_N_195_grpi, A0 => P0_N_195);
GRP_P0_N_212_grpi : PGBUFI_main
GENERIC MAP (TRISE => 3.000000 ns, TFALL => 3.000000 ns)
PORT MAP (Z0 => P0_N_212_grpi, A0 => P0_N_212);
GRP_P0_N_214_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => P0_N_214_grpi, A0 => P0_N_214);
GRP_AND_1372_ffb : PGBUFI_main
GENERIC MAP (TRISE => 1.300000 ns, TFALL => 1.300000 ns)
PORT MAP (Z0 => AND_1372_ffb, A0 => AND_1372);
GRP_AND_1372_grpi : PGBUFI_main
GENERIC MAP (TRISE => 3.100000 ns, TFALL => 3.100000 ns)
PORT MAP (Z0 => AND_1372_grpi, A0 => AND_1372);
GRP_OR_871_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => OR_871_grpi, A0 => OR_871);
GRP_OR_872_ffb : PGBUFI_main
GENERIC MAP (TRISE => 1.300000 ns, TFALL => 1.300000 ns)
PORT MAP (Z0 => OR_872_ffb, A0 => OR_872);
GRP_OR_872_grpi : PGBUFI_main
GENERIC MAP (TRISE => 3.100000 ns, TFALL => 3.100000 ns)
PORT MAP (Z0 => OR_872_grpi, A0 => OR_872);
GRP_D0_N_5_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_5_grpi, A0 => D0_N_5);
GRP_D0_N_37_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_37_grpi, A0 => D0_N_37);
GRP_D0_N_13_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_13_grpi, A0 => D0_N_13);
GRP_D0_N_8_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_8_grpi, A0 => D0_N_8);
GRP_D0_N_34_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_34_grpi, A0 => D0_N_34);
GRP_D0_N_10_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_10_grpi, A0 => D0_N_10);
GRP_P0_N_218_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => P0_N_218_grpi, A0 => P0_N_218);
GRP_P0_N_217_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => P0_N_217_grpi, A0 => P0_N_217);
GRP_P0_N_216_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => P0_N_216_grpi, A0 => P0_N_216);
GRP_OR_1393_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => OR_1393_grpi, A0 => OR_1393);
GRP_OR_1395_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => OR_1395_grpi, A0 => OR_1395);
GRP_OR_1397_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => OR_1397_grpi, A0 => OR_1397);
GRP_P03_PIN_iomux : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => P03_PIN_iomux, A0 => P03_PIN);
GRP_P0_N_174_ffb : PGBUFI_main
GENERIC MAP (TRISE => 1.300000 ns, TFALL => 1.300000 ns)
PORT MAP (Z0 => P0_N_174_ffb, A0 => P0_N_174);
GRP_P0_N_174_grpi : PGBUFI_main
GENERIC MAP (TRISE => 3.200000 ns, TFALL => 3.200000 ns)
PORT MAP (Z0 => P0_N_174_grpi, A0 => P0_N_174);
GRP_P0_N_175_part2_ffb : PGBUFI_main
GENERIC MAP (TRISE => 1.300000 ns, TFALL => 1.300000 ns)
PORT MAP (Z0 => P0_N_175_part2_ffb, A0 => P0_N_175_part2);
GRP_P0_N_175_part2_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.900000 ns, TFALL => 2.900000 ns)
PORT MAP (Z0 => P0_N_175_part2_grpi, A0 => P0_N_175_part2);
GRP_P0_N_180_ffb : PGBUFI_main
GENERIC MAP (TRISE => 1.300000 ns, TFALL => 1.300000 ns)
PORT MAP (Z0 => P0_N_180_ffb, A0 => P0_N_180);
GRP_P0_N_180_grpi : PGBUFI_main
GENERIC MAP (TRISE => 3.200000 ns, TFALL => 3.200000 ns)
PORT MAP (Z0 => P0_N_180_grpi, A0 => P0_N_180);
GRP_P0_N_181_grpi : PGBUFI_main
GENERIC MAP (TRISE => 3.300000 ns, TFALL => 3.300000 ns)
PORT MAP (Z0 => P0_N_181_grpi, A0 => P0_N_181);
GRP_D0_N_116_C_ck2f : PGBUFI_main
GENERIC MAP (TRISE => 1.800000 ns, TFALL => 1.800000 ns)
PORT MAP (Z0 => D0_N_116_C_ck2f, A0 => D0_N_116_C);
GRP_D0_N_2_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_2_grpi, A0 => D0_N_2);
GRP_P02_PIN_iomux : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => P02_PIN_iomux, A0 => P02_PIN);
GRP_P00_PIN_iomux : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => P00_PIN_iomux, A0 => P00_PIN);
GRP_P0_N_175_part1_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.700000 ns, TFALL => 2.700000 ns)
PORT MAP (Z0 => P0_N_175_part1_grpi, A0 => P0_N_175_part1);
GRP_OR_1392_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => OR_1392_grpi, A0 => OR_1392);
GRP_D0_N_3_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_3_grpi, A0 => D0_N_3);
GRP_D0_N_115_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_115_grpi, A0 => D0_N_115);
GRP_D0_N_12_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_12_grpi, A0 => D0_N_12);
GRP_D0_N_14_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_14_grpi, A0 => D0_N_14);
GRP_D0_N_15_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => D0_N_15_grpi, A0 => D0_N_15);
GRP_D0_N_15_ffb : PGBUFI_main
GENERIC MAP (TRISE => 1.300000 ns, TFALL => 1.300000 ns)
PORT MAP (Z0 => D0_N_15_ffb, A0 => D0_N_15);
GRP_D0_N_16_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_16_grpi, A0 => D0_N_16);
GRP_D0_N_99_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_99_grpi, A0 => D0_N_99);
GRP_N_38_part1_grpi : PGBUFI_main
GENERIC MAP (TRISE => 3.000000 ns, TFALL => 3.000000 ns)
PORT MAP (Z0 => N_38_part1_grpi, A0 => N_38_part1);
GRP_D0_N_3_C_ck1f : PGBUFI_main
GENERIC MAP (TRISE => 1.800000 ns, TFALL => 1.800000 ns)
PORT MAP (Z0 => D0_N_3_C_ck1f, A0 => D0_N_3_C);
GRP_P0_N_181_C_ffb : PGBUFI_main
GENERIC MAP (TRISE => 1.300000 ns, TFALL => 1.300000 ns)
PORT MAP (Z0 => P0_N_181_C_ffb, A0 => P0_N_181_C);
GRP_P0_N_181_C_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => P0_N_181_C_grpi, A0 => P0_N_181_C);
GRP_P0_N_238_grpi : PGBUFI_main
GENERIC MAP (TRISE => 3.000000 ns, TFALL => 3.000000 ns)
PORT MAP (Z0 => P0_N_238_grpi, A0 => P0_N_238);
GRP_P0_N_239_grpi : PGBUFI_main
GENERIC MAP (TRISE => 3.000000 ns, TFALL => 3.000000 ns)
PORT MAP (Z0 => P0_N_239_grpi, A0 => P0_N_239);
GRP_P0_N_240_grpi : PGBUFI_main
GENERIC MAP (TRISE => 3.000000 ns, TFALL => 3.000000 ns)
PORT MAP (Z0 => P0_N_240_grpi, A0 => P0_N_240);
GRP_D0_N_39_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_39_grpi, A0 => D0_N_39);
GRP_OR_1394_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => OR_1394_grpi, A0 => OR_1394);
GRP_D0_N_114_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_114_grpi, A0 => D0_N_114);
GRP_D0_N_36_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_36_grpi, A0 => D0_N_36);
GRP_D0_N_38_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_38_grpi, A0 => D0_N_38);
GRP_D0_N_40_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_40_grpi, A0 => D0_N_40);
GRP_D0_N_41_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_41_grpi, A0 => D0_N_41);
GRP_P0_N_177_C_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => P0_N_177_C_grpi, A0 => P0_N_177_C);
GRP_OR_1401_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => OR_1401_grpi, A0 => OR_1401);
GRP_OR_1400_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => OR_1400_grpi, A0 => OR_1400);
GRP_OR_1396_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.500000 ns, TFALL => 2.500000 ns)
PORT MAP (Z0 => OR_1396_grpi, A0 => OR_1396);
GRP_D0_N_116_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_116_grpi, A0 => D0_N_116);
GRP_D0_N_4_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_4_grpi, A0 => D0_N_4);
GRP_D0_N_6_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_6_grpi, A0 => D0_N_6);
GRP_D0_N_98_grpi : PGBUFI_main
GENERIC MAP (TRISE => 2.600000 ns, TFALL => 2.600000 ns)
PORT MAP (Z0 => D0_N_98_grpi, A0 => D0_N_98);
GRP_P01_PIN_iomux : PGBUFI_main
GENERIC MAP (TRISE => 1.000000 ns, TFALL => 1.000000 ns)
PORT MAP (Z0 => P01_PIN_iomux, A0 => P01_PIN);
GRP_L2L_KEYWD_RESET_glb : PXIN_main
GENERIC MAP (TRISE => 1.500000 ns, TFALL => 1.500000 ns)
PORT MAP (Z0 => L2L_KEYWD_RESET_glbb, XI0 => L2L_KEYWD_RESETb);
END main_STRUCTURE;
|
<reponame>lxsang/APF51-0V7670<filename>hardware/obtr_hdl/object_position_unit.vhd
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity object_position_unit is
port (
clk : in std_logic;
reset : in std_logic;
strobe : in std_logic;
cycle : in std_logic;
-- The address of the circuit
-- supplied by the interface manager
addr : in std_logic_vector(2 downto 0) ;
sum_x_in: in std_logic_vector(31 downto 0) ;
sum_y_in: in std_logic_vector(31 downto 0) ;
n_in : in std_logic_vector(31 downto 0) ;
frame_ok: in std_logic;
c_sel : in std_logic;
ack : out std_logic;
wr : in std_logic;
dout : out std_logic_vector(15 downto 0)
) ;
end object_position_unit; --entity
architecture arch of object_position_unit is
--signal sum, sum_next: std_logic_vector(31 downto 0) ;
--signal n,n_next : std_logic_vector(31 downto 0) ;
begin
ack <= c_sel and strobe;
-- write process
-- write_proc : process( clk,reset )
-- begin
-- if(reset = '1') then
-- sum <= (others => '0');
-- n<= (others=>'0');
-- elsif rising_edge(clk) then
-- sum <= sum_next;
-- n <= n_next;
-- end if;
-- end process ; -- write_proc
--sum_next <= sum_in when frame_ok = '1' else sum;
--n_next <= n_in when frame_ok = '1' else n;
--dout <= reg;
--read proc
read_proc : process( clk,reset )
begin
if(reset = '1') then
dout <= (others=>'0');
elsif rising_edge(clk) then
if(strobe = '1' and wr = '0' and cycle = '1' and c_sel = '1') then
if addr = "000" then
dout <= sum_x_in(15 downto 0);
elsif addr = "001" then
dout <= sum_x_in(31 downto 16);
elsif addr = "010" then
dout <= sum_y_in(15 downto 0);
elsif addr = "011" then
dout <= sum_y_in(31 downto 16);
elsif addr = "100" then
dout <= n_in(15 downto 0);
elsif addr = "101" then
dout <= n_in(31 downto 16);
else
dout<= (others=>'0');
end if;
else
dout <= (others=>'0');
end if;
end if;
end process ; -- read_proc
end architecture ; -- arch
|
----------------------------------------------------------------------------------
-- Created By: <NAME>
--
-- Design Name: SDRAM Controller with SEU EDAC (Error-Detection-And-Correction) mechanisms
-- Module Name: tmr_voter - behave
-- Project Name: SEUD-MIST KTH Royal Institute Of Technology
-- Tested Devices:
-- FPGA: Cyclone IV, Artix-7
-- Memories: IS42/45S16320B, IS42/45R86400D/16320D/32160D, IS42/45S86400D/16320D/32160D, IS42/45SM/RM/VM16160K
-- Comments:
-- Requires tmr_error_generator.vhd
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.utils_pack.all;
entity tmr_voter is
generic(
DATA_WIDTH : Integer := 32;
GEN_ERR_INJ : Boolean := FALSE
);
port(
clk_i : in std_logic := '0';
en_i : in std_logic := '0';
en_err_test_i: in std_logic := '0';
rd_data_1_i, rd_data_2_i, rd_data_3_i : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
voted_data_o : out std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
err_count_o : out std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0')
);
end tmr_voter;
architecture behave of tmr_voter is
attribute keep_hierarchy : string;
attribute keep_hierarchy of behave : architecture is "yes";
component tmr_random_generator is
generic ( DATA_WIDTH : integer := 32; INDEX_WIDTH : integer := 2; INDEX_MAX : integer := 2 );
port (
clk, en : in std_logic :='0';
random_num : out std_logic_vector (DATA_WIDTH-1 downto 0) := (others=>'0'); --output vector
random_index : out integer range 0 to INDEX_MAX := 0 --output index
);
end component tmr_random_generator;
signal rand_num : std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
signal rand_ind : integer range 0 to 3 := 0;
begin
--majority voter
latch_voting : process(en_i, en_err_test_i, rd_data_1_i, rd_data_2_i, rd_data_3_i, rand_ind, rand_num)
variable rd_data_w_err_int_1, rd_data_w_err_int_2, rd_data_w_err_int_3 : std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
variable diff_data : std_logic_vector(DATA_WIDTH-1 downto 0) := (others=>'0');
begin
if GEN_ERR_INJ=TRUE then
if en_err_test_i='1' then
case rand_ind is
when 0=> rd_data_w_err_int_1 := rand_num;
when others=> rd_data_w_err_int_1 := rd_data_1_i;
end case;
case rand_ind is
when 1=> rd_data_w_err_int_2 := rand_num;
when others=> rd_data_w_err_int_2 := rd_data_2_i;
end case;
case rand_ind is
when 2=> rd_data_w_err_int_3 := rand_num;
when others=> rd_data_w_err_int_3 := rd_data_3_i;
end case;
else
rd_data_w_err_int_1 := rd_data_1_i;
rd_data_w_err_int_2 := rd_data_2_i;
rd_data_w_err_int_3 := rd_data_3_i;
end if;
else
rd_data_w_err_int_1 := rd_data_1_i;
rd_data_w_err_int_2 := rd_data_2_i;
rd_data_w_err_int_3 := rd_data_3_i;
end if;
voted_data_o <= majority_vote(rd_data_w_err_int_1, rd_data_w_err_int_2, rd_data_w_err_int_3);
diff_data := majority_err_detect(rd_data_w_err_int_1, rd_data_w_err_int_2, rd_data_w_err_int_3);
if en_i='1' then
err_count_o <= std_logic_vector(count_ones_in_vector(diff_data));
else
err_count_o <= (others=>'0');
end if;
end process;
ERROR_INJ: if GEN_ERR_INJ=TRUE generate
tmr_rand_gen_inst : tmr_random_generator generic map( DATA_WIDTH=>DATA_WIDTH, INDEX_WIDTH=>2, INDEX_MAX=>2) port map(clk=>clk_i, en=>en_err_test_i, random_num=>rand_num, random_index=> rand_ind);
end generate ERROR_INJ;
end behave;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:47:08 08/10/2020
-- Design Name:
-- Module Name: shift_register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_register is
generic (
sr_depth : integer:=9
);
Port ( clk : in STD_LOGIC;
load : in STD_LOGIC;
en : in STD_LOGIC;
S_sr: in STD_LOGIC_VECTOR (7 downto 0);
sr_port : out STD_LOGIC_VECTOR (sr_depth - 2 downto 0));
end shift_register;
architecture Behavioral of shift_register is
signal sr : STD_LOGIC_VECTOR(sr_depth - 2 downto 0);
begin
process(clk,load,sr,S_sr)
begin
if (load = '1') and (en = '0') then
sr<= S_sr;
elsif (en = '1') and (load = '0') then
if rising_edge (clk) then
sr <= '0' & sr(sr'high downto sr'low + 1) ;
end if;
end if;
end process;
sr_port <= sr;
end Behavioral;
|
-------------------------------------------------------------------------------
--! @file nShiftRegRtl.vhd
--
--! @brief Shift register with n-bit-width
--
--! @details This shift register implementation provides a configurable width.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact <EMAIL>
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library libcommon;
use libcommon.global.all;
entity nShiftReg is
generic (
--! Data width
gWidth : natural := 8;
--! Number of tabs
gTabs : natural := 4;
--! Shift direction ("left" or "right")
gShiftDir : string := "left"
);
port (
--! Asynchronous reset
iArst : in std_logic;
--! Clock
iClk : in std_logic;
--! Parallel Load
iLoad : in std_logic;
--! Shift Enable
iShift : in std_logic;
--! Load Data (gTabs x gWidth)
iLoadData : in std_logic_vector(gWidth*gTabs-1 downto 0);
--! Parallel Output Data
oParData : out std_logic_vector(gWidth*gTabs-1 downto 0);
--! Input Shift Data
iData : in std_logic_vector(gWidth-1 downto 0);
--! Ouptut Shift Data
oData : out std_logic_vector(gWidth-1 downto 0)
);
end nShiftReg;
architecture rtl of nShiftReg is
--! Shift register type
type tShiftReg is
array (gTabs-1 downto 0) of std_logic_vector(gWidth-1 downto 0);
--! Function to convert std_logic_vector into tShiftReg
function convStdLogicToShiftReg (din : std_logic_vector)
return tShiftReg is
variable vTmp : tShiftReg;
begin
--default
vTmp := (others => (others => cInactivated));
--loop tab-wise
for i in gTabs-1 downto 0 loop
vTmp(i) := din((i+1)*gWidth-1 downto i*gWidth);
end loop;
return vTmp;
end function;
--! Function to convert tShiftReg into std_logic_vector
function convShiftRegToStdLogic (din : tShiftReg)
return std_logic_vector is
variable vTmp : std_logic_vector(gWidth*gTabs-1 downto 0);
begin
--default
vTmp := (others => cInactivated);
--loop tab-wise
for i in gTabs-1 downto 0 loop
vTmp((i+1)*gWidth-1 downto i*gWidth) := din(i);
end loop;
return vTmp;
end function;
--! Shift register
signal reg, reg_next : tShiftReg;
begin
assert (gShiftDir = "left" or gShiftDir = "right") report
"Set either left or right for shift direction!" severity failure;
--serial output
oData <= reg(reg'right) when gShiftDir = "right" else
reg(reg'left);
--parallel output
oParData <= convShiftRegToStdLogic(reg);
--! Process doing loading and shifting
comb : process (
reg,
iLoad, iShift,
iLoadData, iData
)
begin
--default
reg_next <= reg;
if iLoad = cActivated then
reg_next <= convStdLogicToShiftReg(iLoadData);
elsif iShift = cActivated then
if gShiftDir = "right" then
reg_next <= iData & reg(reg'left downto 1);
else
reg_next <= reg(reg'left-1 downto 0) & iData;
end if;
end if;
end process;
--! Register process
regClk : process(iArst, iClk)
begin
if iArst = cActivated then
reg <= (others => (others => cInactivated));
elsif rising_edge(iClk) then
reg <= reg_next;
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
-- Title : XYZ routing for a router at position (Xis,Yis,Zis) in a
-- A-3D NOC
-- Project : modular, heterogenous 3D NoC
-------------------------------------------------------------------------------
-- File : xyz_routing.vhd
-- Author : <NAME> <<EMAIL>>
-- Company : ITEM.ids, University of Bremen
-- Created : 2018-04-03
-- Last update: 2018-11-13
-- Platform : Linux Debian 8
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-04-03 1.0 bamberg Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
entity xyz_routing is
generic(
Xis : natural := 1;
Yis : natural := 1;
Zis : natural := 1);
--port_num : positive := 7;)
port(
address : in address_inf;
enable : in std_logic;
-- in dependence of the possible routes not all bit of "routing" are used
routing : out std_logic_vector(6 downto 0));
end xyz_routing;
architecture rtl of xyz_routing is
begin
process(address, enable)
begin
routing <= (others => '0');
if enable = '1' then
if (to_integer(unsigned(address.x_dest)) < Xis) then
routing(int_west) <= '1'; -- Route neg. X
elsif (to_integer(unsigned(address.x_dest)) > Xis) then
routing(int_east) <= '1'; -- Route pos. X
elsif (to_integer(unsigned(address.y_dest)) < Yis) then
routing(int_south) <= '1'; -- Route neg. Y
elsif (to_integer(unsigned(address.y_dest)) > Yis) then
routing(int_north) <= '1'; -- Route pos. Y
elsif (to_integer(unsigned(address.z_dest)) < Zis) then
routing(int_down) <= '1'; -- Route Down
elsif (to_integer(unsigned(address.z_dest)) > Zis) then
routing(int_up) <= '1'; -- Route pos. Z
else
routing(int_local) <= '1'; -- Route local
end if;
end if;
end process;
end architecture;
|
<filename>impl/rtl/crossing.vhdl<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity crossing_controller is
port(
-- 4 Hz clock
clk : in std_ulogic;
reset : in std_ulogic;
wait_btn : in std_ulogic;
-- traffic lights 0: red, 1: Amber, 2: Green
lights : out std_ulogic_vector(2 DOWNTO 0);
buzzer : out std_ulogic;
spinner : out std_ulogic
);
end crossing_controller;
-- Transision timings
-- btn -> amber 1s
-- amber -> red 2s
-- red -> red amber 4s
-- red amber -> green 2s
architecture rtl of crossing_controller is
type state_machine_type is (in_reset, green, amber, red, red_amber);
signal state : state_machine_type := in_reset;
signal btn_debounce : std_ulogic := '0';
-- Longest transision is 4 seconds, which is 4 * 4 clock ticks
-- so 5 bits should be enough to count this down
-- When next_state is in_reset this means that no change is in progress
signal delay_change : integer range 16 DOWNTO 0 := 0;
signal next_state : state_machine_type := in_reset;
begin
buzzer <= '0';
spinner <= '0';
process(clk, reset, state)
begin
if reset = '1' then
state <= in_reset;
elsif rising_edge(clk) then
if state = in_reset then
state <= green;
end if;
if state = green
and wait_btn = '1'
and btn_debounce = '0'
and next_state = in_reset then
-- Stop the button being pressed again
btn_debounce <= '1';
delay_change <= (1 * 4) - 1;
next_state <= amber;
elsif next_state /= in_reset then
-- We are counting down to a change!
if delay_change = 0 then
-- Time to change our state!
state <= next_state;
-- Start the next transition
case next_state is
when amber =>
-- Next state is red in 2 seconds
next_state <= red;
delay_change <= (2 * 4) - 1;
when red =>
-- Next state is red amber is 4 seconds
next_state <= red_amber;
delay_change <= (4 * 4) - 1;
when red_amber =>
next_state <= green;
delay_change <= (2 * 4) - 1;
when others =>
delay_change <= 0;
next_state <= in_reset;
end case;
else
delay_change <= delay_change - 1;
end if;
end if;
if wait_btn = '0' and btn_debounce = '1' then
-- Allow the button to be pressed again, it has been released
btn_debounce <= '0';
end if;
end if;
case state is
when in_reset =>
lights <= (others => '0');
btn_debounce <= '0';
delay_change <= 0;
next_state <= in_reset;
when green =>
lights <= "001";
when amber =>
lights <= "010";
when red =>
lights <= "100";
when red_amber =>
lights <= "110";
end case;
end process;
end rtl;
|
-- Copyright (c) 2012-2016 <NAME>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
entity prog_amp_tb is
end entity;
architecture beh of prog_amp_tb is
signal clk_s, rst_s : std_logic;
signal set_gain_s, done_s : std_logic;
signal a_gain_s, b_gain_s : std_logic_vector(3 downto 0);
signal spi_owned_out_s : std_logic;
signal spi_mosi_s, spi_sck_s, spi_miso_s, amp_ncs_s : std_logic;
constant CLOCK_PERIOD : time := 20 ns;
begin
prog_amp_i : entity work.prog_amp(beh)
port map (
clk => clk_s, rst => rst_s,
a_gain => a_gain_s, b_gain => b_gain_s,
set_gain => set_gain_s, done => done_s,
spi_owned_out => spi_owned_out_s,
spi_mosi => spi_mosi_s, spi_sck => spi_sck_s,
spi_miso => spi_miso_s, amp_ncs => amp_ncs_s);
signal_gen : process
begin
spi_miso_s <= '0'; -- Block does not need this
a_gain_s <= b"1010";
b_gain_s <= b"0101";
-- Clk starts at 0, so I already have half cycle in advance
rst_s <= '0';
set_gain_s <= '0';
wait for CLOCK_PERIOD;
-- (reset)
rst_s <= '1';
set_gain_s <= '0';
wait for CLOCK_PERIOD;
-- (request run)
rst_s <= '0';
set_gain_s <= '1';
wait for CLOCK_PERIOD;
-- (verify done has gone down)
set_gain_s <= '0';
assert done_s = '0' report "DONE didn't go down!" severity error;
-- (wait until process finishes)
-- YES, I know I should check the bytes are correct but ... this is just a quick tb. It
-- needs visual inspection :D
wait on clk_s until done_s = '1';
wait on clk_s until falling_edge(clk_s); -- Wait for one full cycle
assert spi_owned_out_s = '0' report "SPI still owned by element!" severity error;
-- (request run, new values
a_gain_s <= b"1001";
b_gain_s <= b"0110";
rst_s <= '0';
set_gain_s <= '1';
wait for CLOCK_PERIOD;
-- (verify done has gone down)
set_gain_s <= '0';
assert done_s = '0' report "DONE didn't go down!" severity error;
-- (wait until process finishes)
-- YES, I know I should check the bytes are correct but ... this is just a quick tb. It
-- needs visual inspection :D
wait on clk_s until done_s = '1';
wait on clk_s until falling_edge(clk_s); -- Wait for one full cycle
assert spi_owned_out_s = '0' report "SPI still owned by element!" severity error;
wait;
end process;
clock : process
begin
clk_s <= '0';
wait for CLOCK_PERIOD / 2;
clk_s <= '1';
wait for CLOCK_PERIOD / 2;
end process clock;
end;
|
-- Testbench automatically generated online
-- at https://vhdl.lapinoo.net
-- Generation date : 21.10.2021 20:57:40 UTC
library ieee;
use ieee.std_logic_1164.all;
entity tb_exp5_desafio is
end tb_exp5_desafio;
architecture tb of tb_exp5_desafio is
component exp5_desafio
port (clock : in std_logic;
reset : in std_logic;
ligar : in std_logic;
echo : in std_logic;
trigger : out std_logic;
pwm : out std_logic;
posicao : out std_logic_vector (2 downto 0);
distancia : out std_logic_vector (11 downto 0);
distancia0 : out std_logic_vector (6 downto 0);
distancia1 : out std_logic_vector (6 downto 0);
distancia2 : out std_logic_vector (6 downto 0);
db_estado : out std_logic_vector (6 downto 0);
db_posicao : out std_logic_vector (6 downto 0);
db_reset : out std_logic;
db_ligar : out std_logic);
end component;
signal clock : std_logic;
signal reset : std_logic;
signal ligar : std_logic;
signal echo : std_logic;
signal trigger : std_logic;
signal pwm : std_logic;
signal posicao : std_logic_vector (2 downto 0);
signal distancia : std_logic_vector (11 downto 0);
signal distancia0 : std_logic_vector (6 downto 0);
signal distancia1 : std_logic_vector (6 downto 0);
signal distancia2 : std_logic_vector (6 downto 0);
signal db_estado : std_logic_vector (6 downto 0);
signal db_posicao : std_logic_vector (6 downto 0);
signal db_reset : std_logic;
signal db_ligar : std_logic;
constant TbPeriod : time := 20 ns; -- EDIT Put right period here
signal TbClock : std_logic := '0';
signal TbSimEnded : std_logic := '0';
begin
dut : exp5_desafio
port map (clock => clock,
reset => reset,
ligar => ligar,
echo => echo,
trigger => trigger,
pwm => pwm,
posicao => posicao,
distancia => distancia,
distancia0 => distancia0,
distancia1 => distancia1,
distancia2 => distancia2,
db_estado => db_estado,
db_posicao => db_posicao,
db_reset => db_reset,
db_ligar => db_ligar);
-- Clock generation
TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
-- EDIT: Check that clock is really your main clock signal
clock <= TbClock;
stimuli : process
begin
-- EDIT Adapt initialization as needed
ligar <= '0';
echo <= '0';
-- Reset generation
-- EDIT: Check that reset is really your reset signal
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for 100 ns;
ligar <= '1';
wait until trigger = '1';
wait for 50*TbPeriod;
echo <= '1';
wait for 700000 ns;
echo <= '0';
wait until trigger = '1';
wait for 50*TbPeriod;
echo <= '1';
wait for 800000 ns;
echo <= '0';
wait until trigger = '1';
wait for 50*TbPeriod;
echo <= '1';
wait for 900000 ns;
echo <= '0';
-- EDIT Add stimuli here
wait for 1000*TbPeriod;
ligar <= '0';
wait for 5*TbPeriod;
-- Stop the clock and hence terminate the simulation
TbSimEnded <= '1';
wait;
end process;
end tb;
-- Configuration block below is required by some simulators. Usually no need to edit.
configuration cfg_tb_exp5_desafio of tb_exp5_desafio is
for tb
end for;
end cfg_tb_exp5_desafio;
|
<reponame>ispras/hdl-benchmarks
---------------------------------------------------------------------
---- ----
---- OpenCores IDE Controller ----
---- Wishbone Slave (common for all OCIDEC cores) ----
---- ----
---- Author: <NAME> ----
---- <EMAIL> ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2002 <NAME> ----
---- <EMAIL> ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
--
-- CVS Log
--
-- $Id: atahost_wb_slave.vhd,v 1.1 2002/02/18 14:29:38 rherveille Exp $
--
-- $Date: 2002/02/18 14:29:38 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: atahost_wb_slave.vhd,v $
-- Revision 1.1 2002/02/18 14:29:38 rherveille
-- renamed 'atahost.vhd' to 'atahost_top.vhd'
-- renamed 'controller.vhd' to 'atahost_controller.vhd'
-- renamed 'pio_tctrl.vhd' to 'atahost_pio_tctrl.vhd'
-- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
-- changed resD input to generic RESD in ud_cnt.vhd
-- changed ID input to generic ID in ro_cnt.vhd
-- changed core to reflect changes in ro_cnt.vhd
-- removed references to 'count' library
-- changed IO names
-- added disclaimer
-- added CVS log
-- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
-- core is now equivalent to verilog version
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity atahost_wb_slave is
generic(
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
-- Multiword DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port(
DeviceID : in unsigned(3 downto 0) := x"0";
RevisionNo : in unsigned(3 downto 0) := x"0";
-- WISHBONE SYSCON signals
clk_i : in std_logic; -- master clock in
arst_i : in std_logic := '1'; -- asynchronous active low reset
rst_i : in std_logic := '0'; -- synchronous active high reset
-- WISHBONE SLAVE signals
cyc_i : in std_logic; -- valid bus cycle input
stb_i : in std_logic; -- strobe/core select input
ack_o : out std_logic; -- strobe acknowledge output
rty_o : out std_logic; -- retry output
err_o : out std_logic; -- error output
adr_i : in unsigned(6 downto 2); -- A6 = '1' ATA devices selected
-- A5 = '1' CS1- asserted, '0' CS0- asserted
-- A4..A2 ATA address lines
-- A6 = '0' ATA controller selected
dat_i : in std_logic_vector(31 downto 0); -- Databus in
dat_o : out std_logic_vector(31 downto 0); -- Databus out
sel_i : in std_logic_vector(3 downto 0); -- Byte select signals
we_i : in std_logic; -- Write enable input
inta_o : out std_logic; -- interrupt request signal IDE0
-- PIO control input
PIOsel : buffer std_logic;
PIOtip, -- PIO transfer in progress
PIOack : in std_logic; -- PIO acknowledge signal
PIOq : in std_logic_vector(15 downto 0); -- PIO data input
PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full
irq : in std_logic; -- interrupt signal input
-- DMA control inputs
DMAsel : out std_logic;
DMAtip, -- DMA transfer in progress
DMAack, -- DMA transfer acknowledge
DMARxEmpty, -- DMA receive buffer empty
DMATxFull, -- DMA transmit buffer full
DMA_dmarq : in std_logic; -- wishbone DMA request
DMAq : in std_logic_vector(31 downto 0);
-- outputs
-- control register outputs
IDEctrl_rst,
IDEctrl_IDEen,
IDEctrl_FATR1,
IDEctrl_FATR0,
IDEctrl_ppen,
DMActrl_DMAen,
DMActrl_dir,
DMActrl_BeLeC0,
DMActrl_BeLeC1 : out std_logic;
-- CMD port timing registers
PIO_cmdport_T1,
PIO_cmdport_T2,
PIO_cmdport_T4,
PIO_cmdport_Teoc : buffer unsigned(7 downto 0);
PIO_cmdport_IORDYen : out std_logic;
-- data-port0 timing registers
PIO_dport0_T1,
PIO_dport0_T2,
PIO_dport0_T4,
PIO_dport0_Teoc : buffer unsigned(7 downto 0);
PIO_dport0_IORDYen : out std_logic;
-- data-port1 timing registers
PIO_dport1_T1,
PIO_dport1_T2,
PIO_dport1_T4,
PIO_dport1_Teoc : buffer unsigned(7 downto 0);
PIO_dport1_IORDYen : out std_logic;
-- DMA device0 timing registers
DMA_dev0_Tm,
DMA_dev0_Td,
DMA_dev0_Teoc : buffer unsigned(7 downto 0);
-- DMA device1 timing registers
DMA_dev1_Tm,
DMA_dev1_Td,
DMA_dev1_Teoc : buffer unsigned(7 downto 0)
);
end entity atahost_wb_slave;
architecture structural of atahost_wb_slave is
--
-- constants
--
-- addresses
alias ATA_DEV_ADR : std_logic is adr_i(6);
alias ATA_ADR : unsigned(3 downto 0) is adr_i(5 downto 2);
constant ATA_CTRL_REG : unsigned(3 downto 0) := "0000";
constant ATA_STAT_REG : unsigned(3 downto 0) := "0001";
constant ATA_PIO_CMD : unsigned(3 downto 0) := "0010";
constant ATA_PIO_DP0 : unsigned(3 downto 0) := "0011";
constant ATA_PIO_DP1 : unsigned(3 downto 0) := "0100";
constant ATA_DMA_DEV0 : unsigned(3 downto 0) := "0101";
constant ATA_DMA_DEV1 : unsigned(3 downto 0) := "0110";
-- reserved --
constant ATA_DMA_PORT : unsigned(3 downto 0) := "1111";
--
-- function declarations
--
-- overload '=' to compare two unsigned numbers
function "=" (a, b : unsigned) return std_logic is
alias la: unsigned(1 to a'length) is a;
alias lb: unsigned(1 to b'length) is b;
variable result : std_logic;
begin
-- check vector length
assert a'length = b'length
report "std_logic_vector comparison: operands of unequal lengths"
severity FAILURE;
result := '1';
for n in 1 to a'length loop
result := result and not (la(n) xor lb(n));
end loop;
return result;
end;
-- primary address decoder
signal CONsel : std_logic; -- controller select, IDE devices select
signal berr, brty : std_logic; -- bus error, bus retry
-- registers
signal CtrlReg, StatReg : std_logic_vector(31 downto 0); -- control and status registers
begin
--
-- generate bus cycle / address decoder
--
gen_bc_dec: block
signal w_acc, dw_acc : std_logic; -- word access, double word access
signal store_pp_full : std_logic;
begin
-- word / double word
w_acc <= sel_i(1) and sel_i(0);
dw_acc <= sel_i(3) and sel_i(2) and sel_i(1) and sel_i(0);
-- bus error
berr <= not w_acc when (ATA_DEV_ADR = '1') else not dw_acc;
-- PIO accesses at least 16bit wide, no PIO access during DMAtip or pingpong full
PIOsel <= cyc_i and stb_i and ATA_DEV_ADR and w_acc and not (DMAtip or store_pp_full);
-- CON accesses only 32bit wide
CONsel <= cyc_i and stb_i and not ATA_DEV_ADR and dw_acc;
DMAsel <= CONsel and (ATA_ADR = ATA_DMA_PORT);
-- bus retry (OCIDEC-3 and above)
-- store PIOpp_full, we don't want a PPfull based retry initiated by the current bus-cycle
process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (PIOsel = '0') then
store_pp_full <= PIOpp_full;
end if;
end if;
end process;
brty <= (ATA_DEV_ADR and w_acc) and (DMAtip or store_pp_full);
end block gen_bc_dec;
--
-- generate registers
--
register_block : block
signal sel_PIO_cmdport, sel_PIO_dport0, sel_PIO_dport1 : std_logic; -- PIO timing registers
signal sel_DMA_dev0, sel_DMA_dev1 : std_logic; -- DMA timing registers
signal sel_ctrl, sel_stat : std_logic; -- control / status register
begin
-- generate register select signals
sel_ctrl <= CONsel and we_i and (ATA_ADR = ATA_CTRL_REG);
sel_stat <= CONsel and we_i and (ATA_ADR = ATA_STAT_REG);
sel_PIO_cmdport <= CONsel and we_i and (ATA_ADR = ATA_PIO_CMD);
sel_PIO_dport0 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP0);
sel_PIO_dport1 <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP1);
sel_DMA_dev0 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV0);
sel_DMA_dev1 <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV1);
-- reserved 0x1C-0x38 --
-- reserved 0x3C : DMA port --
-- generate control register
gen_ctrl_reg: process(clk_i, arst_i)
begin
if (arst_i = '0') then
CtrlReg(31 downto 1) <= (others => '0');
CtrlReg(0) <= '1'; -- set reset bit
elsif (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
CtrlReg(31 downto 1) <= (others => '0');
CtrlReg(0) <= '1'; -- set reset bit
elsif (sel_ctrl = '1') then
CtrlReg <= dat_i;
end if;
end if;
end process gen_ctrl_reg;
-- assign bits
DMActrl_DMAen <= CtrlReg(15);
DMActrl_dir <= CtrlReg(13);
DMActrl_BeLeC1 <= CtrlReg(9);
DMActrl_BeLeC0 <= CtrlReg(8);
IDEctrl_IDEen <= CtrlReg(7);
IDEctrl_FATR1 <= CtrlReg(6);
IDEctrl_FATR0 <= CtrlReg(5);
IDEctrl_ppen <= CtrlReg(4);
PIO_dport1_IORDYen <= CtrlReg(3);
PIO_dport0_IORDYen <= CtrlReg(2);
PIO_cmdport_IORDYen <= CtrlReg(1);
IDEctrl_rst <= CtrlReg(0);
-- generate status register clearable bits
gen_stat_reg: block
signal dirq, int : std_logic;
begin
gen_irq: process(clk_i, arst_i)
begin
if (arst_i = '0') then
int <= '0';
dirq <= '0';
elsif (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
int <= '0';
dirq <= '0';
else
int <= (int or (irq and not dirq)) and not (sel_stat and not dat_i(0));
dirq <= irq;
end if;
end if;
end process gen_irq;
gen_stat: process(DMAtip, DMARxEmpty, DMATxFull, DMA_dmarq, PIOtip, int, PIOpp_full)
begin
StatReg(31 downto 0) <= (others => '0'); -- clear all bits (read unused bits as '0')
StatReg(31 downto 28) <= std_logic_vector(DeviceId); -- set Device ID
StatReg(27 downto 24) <= std_logic_vector(RevisionNo); -- set revision number
StatReg(15) <= DMAtip;
StatReg(10) <= DMARxEmpty;
StatReg(9) <= DMATxFull;
StatReg(8) <= DMA_dmarq;
StatReg(7) <= PIOtip;
StatReg(6) <= PIOpp_full;
StatReg(0) <= int;
end process;
end block gen_stat_reg;
-- generate PIO compatible / command-port timing register
gen_PIO_cmdport_reg: process(clk_i, arst_i)
begin
if (arst_i = '0') then
PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8);
PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8);
PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8);
PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);
elsif (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
PIO_cmdport_T1 <= conv_unsigned(PIO_mode0_T1, 8);
PIO_cmdport_T2 <= conv_unsigned(PIO_mode0_T2, 8);
PIO_cmdport_T4 <= conv_unsigned(PIO_mode0_T4, 8);
PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);
elsif (sel_PIO_cmdport = '1') then
PIO_cmdport_T1 <= unsigned(dat_i( 7 downto 0));
PIO_cmdport_T2 <= unsigned(dat_i(15 downto 8));
PIO_cmdport_T4 <= unsigned(dat_i(23 downto 16));
PIO_cmdport_Teoc <= unsigned(dat_i(31 downto 24));
end if;
end if;
end process gen_PIO_cmdport_reg;
-- generate PIO device0 timing register
gen_PIO_dport0_reg: process(clk_i, arst_i)
begin
if (arst_i = '0') then
PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8);
PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8);
PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8);
PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);
elsif (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
PIO_dport0_T1 <= conv_unsigned(PIO_mode0_T1, 8);
PIO_dport0_T2 <= conv_unsigned(PIO_mode0_T2, 8);
PIO_dport0_T4 <= conv_unsigned(PIO_mode0_T4, 8);
PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);
elsif (sel_PIO_dport0 = '1') then
PIO_dport0_T1 <= unsigned(dat_i( 7 downto 0));
PIO_dport0_T2 <= unsigned(dat_i(15 downto 8));
PIO_dport0_T4 <= unsigned(dat_i(23 downto 16));
PIO_dport0_Teoc <= unsigned(dat_i(31 downto 24));
end if;
end if;
end process gen_PIO_dport0_reg;
-- generate PIO device1 timing register
gen_PIO_dport1_reg: process(clk_i, arst_i)
begin
if (arst_i = '0') then
PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8);
PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8);
PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8);
PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);
elsif (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
PIO_dport1_T1 <= conv_unsigned(PIO_mode0_T1, 8);
PIO_dport1_T2 <= conv_unsigned(PIO_mode0_T2, 8);
PIO_dport1_T4 <= conv_unsigned(PIO_mode0_T4, 8);
PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);
elsif (sel_PIO_dport1 = '1') then
PIO_dport1_T1 <= unsigned(dat_i( 7 downto 0));
PIO_dport1_T2 <= unsigned(dat_i(15 downto 8));
PIO_dport1_T4 <= unsigned(dat_i(23 downto 16));
PIO_dport1_Teoc <= unsigned(dat_i(31 downto 24));
end if;
end if;
end process gen_PIO_dport1_reg;
-- generate DMA device0 timing register
gen_DMA_dev0_reg: process(clk_i, arst_i)
begin
if (arst_i = '0') then
DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8);
DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8);
DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8);
elsif (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
DMA_dev0_Tm <= conv_unsigned(DMA_mode0_Tm, 8);
DMA_dev0_Td <= conv_unsigned(DMA_mode0_Td, 8);
DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8);
elsif (sel_DMA_dev0 = '1') then
DMA_dev0_Tm <= unsigned(dat_i( 7 downto 0));
DMA_dev0_Td <= unsigned(dat_i(15 downto 8));
DMA_dev0_Teoc <= unsigned(dat_i(31 downto 24));
end if;
end if;
end process gen_DMA_dev0_reg;
-- generate DMA device1 timing register
gen_DMA_dev1_reg: process(clk_i, arst_i)
begin
if (arst_i = '0') then
DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8);
DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8);
DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8);
elsif (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
DMA_dev1_Tm <= conv_unsigned(DMA_mode0_Tm, 8);
DMA_dev1_Td <= conv_unsigned(DMA_mode0_Td, 8);
DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8);
elsif (sel_DMA_dev1 = '1') then
DMA_dev1_Tm <= unsigned(dat_i( 7 downto 0));
DMA_dev1_Td <= unsigned(dat_i(15 downto 8));
DMA_dev1_Teoc <= unsigned(dat_i(31 downto 24));
end if;
end if;
end process gen_DMA_dev1_reg;
end block register_block;
--
-- generate WISHBONE interconnect signals
--
gen_WB_sigs: block
signal Q : std_logic_vector(31 downto 0);
begin
-- generate acknowledge signal
ack_o <= PIOack or CONsel; -- or DMAack; -- since DMAack is derived from CONsel this is OK
-- generate error signal
err_o <= cyc_i and stb_i and berr;
-- generate retry signal
rty_o <= cyc_i and stb_i and brty;
-- assign interrupt signal
inta_o <= StatReg(0);
-- generate output multiplexor
with ATA_ADR select
Q <= CtrlReg when ATA_CTRL_REG, -- control register
StatReg when ATA_STAT_REG, -- status register
std_logic_vector(PIO_cmdport_Teoc & PIO_cmdport_T4 & PIO_cmdport_T2 & PIO_cmdport_T1) when ATA_PIO_CMD, -- PIO compatible / cmd-port timing register
std_logic_vector(PIO_dport0_Teoc & PIO_dport0_T4 & PIO_dport0_T2 & PIO_dport0_T1) when ATA_PIO_DP0, -- PIO fast timing register device0
std_logic_vector(PIO_dport1_Teoc & PIO_dport1_T4 & PIO_dport1_T2 & PIO_dport1_T1) when ATA_PIO_DP1, -- PIO fast timing register device1
std_logic_vector(DMA_dev0_Teoc & x"00" & DMA_dev0_Td & DMA_dev0_Tm) when ATA_DMA_DEV0, -- DMA timing register device0
std_logic_vector(DMA_dev1_Teoc & x"00" & DMA_dev1_Td & DMA_dev1_Tm) when ATA_DMA_DEV1, -- DMA timing register device1
DMAq when ATA_DMA_PORT, -- DMA port, DMA receive register
(others => '0') when others;
dat_o <= (x"0000" & PIOq) when (ATA_DEV_ADR = '1') else Q;
end block gen_WB_sigs;
end architecture structural;
|
<gh_stars>0
-- _/\/\/\/\/\/\_ _/\/\/\/\_ ___/\/\/\/\___
-- _/\/\_________ ___/\/\___ _/\/\____/\/\_
-- _/\/\/\/\/\___ ___/\/\___ _/\/\____/\/\_
-- _/\/\_________ ___/\/\___ _/\/\____/\/\_
-- _/\/\_________ _/\/\/\/\_ ___/\/\/\/\___
-- ______________ __________ ______________
-- LEGv8 CPU Assembler, CPU, and I/O System
-- "I want to take responsibility for my work to the very end" --<NAME>
--
-- pipelinedcpu3.vhd
-- <NAME> | <NAME> | <NAME>
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity PipelinedCPU3 is
port(
clk : in std_logic;
rst : in std_logic;
--IMEM ports
IMEM_ADDR : out std_logic_vector(63 downto 0);
IMEM_DATA : in std_logic_vector(31 downto 0);
--DMEM ports
DMEM_ADDR : out std_logic_vector(63 downto 0);
DMEM_WRITE_DATA : out std_logic_vector(63 downto 0);
DMEM_READ_DATA : in std_logic_vector(63 downto 0);
DMEM_READ : out std_logic;
DMEM_WRITE : out std_logic;
DMEM_OPCODE : out std_logic_vector(2 downto 0);
--Probe ports used for testing
DEBUG_IF_FLUSH : out std_logic;
DEBUG_REG_EQUAL : out std_logic;
-- Forwarding control signals
DEBUG_FORWARDA : out std_logic_vector(1 downto 0);
DEBUG_FORWARDB : out std_logic_vector(1 downto 0);
--The current address (AddressOut from the PC)
DEBUG_PC : out std_logic_vector(63 downto 0);
--Value of PC.write_enable
DEBUG_PC_WRITE_ENABLE : out STD_LOGIC;
--The current instruction (Instruction output of IMEM)
DEBUG_INSTRUCTION : out std_logic_vector(31 downto 0);
--DEBUG ports from other components
DEBUG_TMP_REGS : out std_logic_vector(64*4 - 1 downto 0);
DEBUG_SAVED_REGS : out std_logic_vector(64*4 - 1 downto 0);
DEBUG_MEM_CONTENTS : out std_logic_vector(64*4 - 1 downto 0)
);
end PipelinedCPU3;
architecture structural of PipelinedCPU3 is
----Initialize Signals----
signal I_DEBUG_TMP_REGS : std_logic_vector(64*4-1 downto 0);
signal I_DEBUG_SAVED_REGS : std_logic_vector(64*4-1 downto 0);
----Data Lines by pipeline stage----
--IF Stage
signal IF_new_PC : std_logic_vector(63 downto 0);
signal IF_curr_PC : std_logic_vector(63 downto 0);
signal IF_instruction : std_logic_vector(31 downto 0);
signal IF_flush : std_logic;
--ID Stage
signal ID_instruction : std_logic_vector(31 downto 0);
signal ID_immediate : std_logic_vector(63 downto 0);
signal ID_RR2 : std_logic_vector(4 downto 0);
signal ID_RD1 : std_logic_vector(63 downto 0);
signal ID_RD2 : std_logic_vector(63 downto 0);
signal ID_WR : std_logic_vector(4 downto 0);
signal ID_shamt : std_logic_vector(5 downto 0) := (others => '0');
--ID Branch lines
signal ID_ubranch : std_logic := '0';
signal ID_cbranch : std_logic := '0';
signal ID_curr_PC : std_logic_vector(63 downto 0);
signal ID_branch_PC : std_logic_vector(63 downto 0);
signal ID_branch : std_logic := '0';
signal ID_zero : std_logic := '0';
--EX Stage
signal EX_immediate : std_logic_vector(63 downto 0);
signal EX_RD1 : std_logic_vector(63 downto 0);
signal EX_RD2 : std_logic_vector(63 downto 0);
signal EX_RR1 : std_logic_vector(4 downto 0);
signal EX_RR2 : std_logic_vector(4 downto 0);
signal EX_FWDED_RD2 : std_logic_vector(63 downto 0);
signal EX_WR : std_logic_vector(4 downto 0);
signal EX_ALU_A : std_logic_vector(63 downto 0);
signal EX_ALU_A_SH : std_logic_vector(63 downto 0);
signal EX_ALU_B : std_logic_vector(63 downto 0);
signal EX_ALU_zero : std_logic;
signal EX_ALU_overflow : std_logic;
signal EX_ALU_result : std_logic_vector(63 downto 0);
signal EX_shamt : std_logic_vector(5 downto 0);
--MEM Stage
signal MM_WR : std_logic_vector(4 downto 0);
signal MM_RD2 : std_logic_vector(63 downto 0);
signal MM_ALU_zero : std_logic;
signal MM_ALU_result : std_logic_vector(63 downto 0);
signal MM_memory_data : std_logic_vector(63 downto 0);
--WB Stage
signal WB_WR : std_logic_vector(4 downto 0);
signal WB_WD : std_logic_vector(63 downto 0);
signal WB_ALU_result : std_logic_vector(63 downto 0);
signal WB_memory_data : std_logic_vector(63 downto 0);
----Control Lines by pipeline stage----
--ID Stage
signal ID_regdst : std_logic := '0';
signal ID_memread : std_logic := '0';
signal ID_memwrite : std_logic := '0';
signal ID_memtoreg : std_logic := '0';
signal ID_multoreg : std_logic := '0';
signal ID_ALUsrc : std_logic := '0';
signal ID_regwrite : std_logic := '0';
signal ID_opcode : std_logic_vector(10 downto 0);
signal ID_ALUOpShort : std_logic_vector(1 downto 0);
signal ID_Stall : std_logic;
signal ID_shift : std_logic := '0';
signal ID_MEMOp : std_logic_vector(1 downto 0) := "11";
signal ID_MEMExt : std_logic := '0';
--EX Stage
signal EX_ubranch : std_logic := '0';
signal EX_cbranch : std_logic := '0';
signal EX_memread : std_logic := '0';
signal EX_memwrite : std_logic := '0';
signal EX_memtoreg : std_logic := '0';
signal EX_multoreg : std_logic := '0';
signal EX_ALUsrc : std_logic := '0';
signal EX_regwrite : std_logic := '0';
signal EX_opcode : std_logic_vector(10 downto 0);
signal EX_ALUOpShort : std_logic_vector(1 downto 0);
signal EX_ALUOpLong : std_logic_vector(3 downto 0);
signal EX_forwardA : std_logic_vector(1 downto 0);
signal EX_forwardB : std_logic_vector(1 downto 0);
signal EX_shift : std_logic := '1';
signal EX_MEMOp : std_logic_vector(1 downto 0) := "11";
signal EX_MEMExt : std_logic := '0';
--MEM Stage
signal MM_memread : std_logic := '0';
signal MM_memwrite : std_logic := '0';
signal MM_memtoreg : std_logic := '0';
signal MM_multoreg : std_logic := '0';
signal MM_regwrite : std_logic := '0';
signal MM_MEMOp : std_logic_vector(1 downto 0) := "11";
signal MM_MEMExt : std_logic := '0';
--WB Stage
signal WB_multoreg : std_logic := '0';
signal WB_memtoreg : std_logic := '0';
signal WB_regwrite : std_logic := '0';
----Initialize Components----
--Initialize Control Stages
component CPUControl is
port(
Opcode : in STD_LOGIC_VECTOR(10 downto 0);
Stall : in STD_LOGIC;
RegDst : out STD_LOGIC;
CBranch : out STD_LOGIC; --conditional
MemRead : out STD_LOGIC;
MemtoReg : out STD_LOGIC;
MultoReg : out STD_LOGIC;
MemWrite : out STD_LOGIC;
ALUSrc : out STD_LOGIC;
RegWrite : out STD_LOGIC;
UBranch : out STD_LOGIC; -- This is unconditional
ALUOp : out STD_LOGIC_VECTOR(1 downto 0);
Shift : out STD_LOGIC
);
end component;
component ALUControl is
port(
ALUOp : in STD_LOGIC_VECTOR(1 downto 0);
Opcode : in STD_LOGIC_VECTOR(10 downto 0);
Operation : out STD_LOGIC_VECTOR(3 downto 0)
);
end component;
--Initialize Other Components
component PC is
port(
clk : in STD_LOGIC;
write_enable : in STD_LOGIC;
rst : in STD_LOGIC;
AddressIn : in STD_LOGIC_VECTOR(63 downto 0); -- Next PC address
AddressOut : out STD_LOGIC_VECTOR(63 downto 0) -- Current PC address
);
end component;
component registers is
port(
RR1 : in STD_LOGIC_VECTOR (4 downto 0);
RR2 : in STD_LOGIC_VECTOR (4 downto 0);
WR : in STD_LOGIC_VECTOR (4 downto 0);
WD : in STD_LOGIC_VECTOR (63 downto 0);
RegWrite : in STD_LOGIC;
Clock : in STD_LOGIC;
RD1 : out STD_LOGIC_VECTOR (63 downto 0);
RD2 : out STD_LOGIC_VECTOR (63 downto 0);
DEBUG_TMP_REGS : out STD_LOGIC_VECTOR(64*4 - 1 downto 0);
DEBUG_SAVED_REGS : out STD_LOGIC_VECTOR(64*4 - 1 downto 0)
);
end component;
component ALU is
port(
in0 : in STD_LOGIC_VECTOR(63 downto 0);
in1 : in STD_LOGIC_VECTOR(63 downto 0);
operation : in STD_LOGIC_VECTOR(3 downto 0);
result : buffer STD_LOGIC_VECTOR(63 downto 0);
zero : buffer STD_LOGIC;
overflow : buffer STD_LOGIC
);
end component;
component shifter is
port (
shamt : in std_logic_vector(5 downto 0);
Rnin : in std_logic_vector(63 downto 0);
Rnout : out std_logic_vector(63 downto 0);
enable : in std_logic;
direction : in std_logic
);
end component;
component forwardUnit is
port(
MM_WR : in std_logic_vector(4 downto 0);
WB_WR : in std_logic_vector(4 downto 0);
MM_regwrite : in std_logic;
WB_regwrite : in std_logic;
EX_RR1 : in std_logic_vector(4 downto 0);
EX_RR2 : in std_logic_vector(4 downto 0);
forwardA : out std_logic_vector(1 downto 0);
forwardB : out std_logic_vector(1 downto 0)
);
end component;
component hazardDetectionUnit is
port(
clk : in std_logic;
rst : in std_logic;
ID_branch : in std_logic;
EX_MemRead : in std_logic;
EX_WR : in std_logic_vector(4 downto 0);
MM_WR : in std_logic_vector(4 downto 0);
ID_RR1 : in std_logic_vector(4 downto 0);
ID_RR2 : in std_logic_vector(4 downto 0);
EX_regwrite : in std_logic;
ID_cbranch : in std_logic;
MM_memread : in std_logic;
--outputs
Stall : out std_logic;
Flush : out std_logic
);
end component;
component zeroCheck is
port (
--input
ID_RD2 : in std_logic_vector(63 downto 0); -- standard input
MM_WD : in std_logic_vector(63 downto 0);
WB_WD : in std_logic_vector(63 downto 0);
ID_RR2 : in std_logic_vector(4 downto 0); -- for forwarding check
MM_WR : in std_logic_vector(4 downto 0);
WB_WR : in std_logic_vector(4 downto 0);
MM_regwrite : in std_logic;
WB_regwrite : in std_logic;
--output
ID_zero : out std_logic
);
end component;
--Initialize Pipeline Registers
component IFIDRegister is
port(
--clk/reset
clk : in STD_LOGIC;
en : in STD_LOGIC;
rst : in STD_LOGIC;
flush : in STD_LOGIC;
--inputs
IF_curr_PC : in std_logic_vector(63 downto 0);
IF_instruction : in std_logic_vector(31 downto 0);
--outputs
ID_instruction : out std_logic_vector(31 downto 0);
ID_curr_PC : out std_logic_vector(63 downto 0)
);
end component;
component IDEXRegister is
port(
--clk/reset
clk : in STD_LOGIC;
rst : in STD_LOGIC;
--inputs
ID_ubranch : in std_logic;
ID_cbranch : in std_logic;
ID_memread : in std_logic;
ID_memwrite : in std_logic;
ID_memtoreg : in std_logic;
ID_multoreg : in std_logic;
ID_ALUsrc : in std_logic;
ID_regwrite : in std_logic;
ID_opcode : in std_logic_vector(10 downto 0);
ID_ALUOpShort : in std_logic_vector(1 downto 0);
ID_WR : in std_logic_vector(4 downto 0);
ID_RR1 : in std_logic_vector(4 downto 0);
ID_RR2 : in std_logic_vector(4 downto 0);
ID_RD1 : in std_logic_vector(63 downto 0);
ID_RD2 : in std_logic_vector(63 downto 0);
ID_immediate : in std_logic_vector(63 downto 0);
ID_curr_PC : in std_logic_vector(63 downto 0);
ID_shift : in std_logic;
ID_shamt : in std_logic_vector(5 downto 0) := (others => '0');
ID_MEMOp : in std_logic_vector(1 downto 0);
ID_MEMExt : in std_logic;
--outputs
EX_ubranch : out std_logic;
EX_cbranch : out std_logic;
EX_memread : out std_logic;
EX_memwrite : out std_logic;
EX_memtoreg : out std_logic;
EX_multoreg : out std_logic;
EX_ALUsrc : out std_logic;
EX_regwrite : out std_logic;
EX_opcode : out std_logic_vector(10 downto 0);
EX_ALUOpShort : out std_logic_vector(1 downto 0);
EX_WR : out std_logic_vector(4 downto 0);
EX_RR1 : out std_logic_vector(4 downto 0);
EX_RR2 : out std_logic_vector(4 downto 0);
EX_RD1 : out std_logic_vector(63 downto 0);
EX_RD2 : out std_logic_vector(63 downto 0);
EX_immediate : out std_logic_vector(63 downto 0);
EX_curr_PC : out std_logic_vector(63 downto 0);
EX_shift : out std_logic;
EX_shamt : out std_logic_vector(5 downto 0);
EX_MEMOp : out std_logic_vector(1 downto 0);
EX_MEMExt : out std_logic
);
end component;
component EXMMRegister is
port(
--clk/reset
clk : in STD_LOGIC;
rst : in STD_LOGIC;
--inputs
EX_ubranch : in std_logic;
EX_cbranch : in std_logic;
EX_memread : in std_logic;
EX_memwrite : in std_logic;
EX_memtoreg : in std_logic;
EX_multoreg : in std_logic;
EX_regwrite : in std_logic;
EX_WR : in std_logic_vector(4 downto 0);
EX_RD2 : in std_logic_vector(63 downto 0);
EX_ALU_zero : in std_logic;
EX_ALU_result : in std_logic_vector(63 downto 0);
EX_branch_PC : in std_logic_vector(63 downto 0);
EX_MEMOp : in std_logic_vector(1 downto 0);
EX_MEMExt : in std_logic;
--outputs
MM_ubranch : out std_logic;
MM_cbranch : out std_logic;
MM_memread : out std_logic;
MM_memwrite : out std_logic;
MM_memtoreg : out std_logic;
MM_multoreg : out std_logic;
MM_regwrite : out std_logic;
MM_WR : out std_logic_vector(4 downto 0);
MM_RD2 : out std_logic_vector(63 downto 0);
MM_ALU_zero : out std_logic;
MM_ALU_result : out std_logic_vector(63 downto 0);
MM_branch_PC : out std_logic_vector(63 downto 0);
MM_MEMOp : out std_logic_vector(1 downto 0);
MM_MEMExt : out std_logic
);
end component;
component MMWBRegister is
port(
--clk/reset
clk : in STD_LOGIC;
rst : in STD_LOGIC;
--inputs
MM_memtoreg : in std_logic;
MM_multoreg : in std_logic;
MM_regwrite : in std_logic;
MM_WR : in std_logic_vector(4 downto 0);
MM_ALU_result : in std_logic_vector(63 downto 0);
MM_memory_data : in std_logic_vector(63 downto 0);
--outputs
WB_memtoreg : out std_logic;
WB_multoreg : out std_logic;
WB_regwrite : out std_logic;
WB_WR : out std_logic_vector(4 downto 0);
WB_ALU_result : out std_logic_vector(63 downto 0);
WB_memory_data : out std_logic_vector(63 downto 0)
);
end component;
begin
----Memory Compoonents----
MM_memory_data <= DMEM_READ_DATA;
DMEM_WRITE_DATA <= MM_RD2;
DMEM_READ <= MM_memread;
DMEM_WRITE <= MM_memwrite;
DMEM_ADDR <= MM_ALU_result;
DMEM_OPCODE <= MM_MEMOp & MM_MEMExt;
IF_instruction <= IMEM_DATA;
IMEM_ADDR <= IF_curr_PC;
----Map All Components----
PC_0 : PC port map(
clk => clk,
write_enable => "not"(ID_stall),
rst => rst,
addressIn => IF_new_PC,
addressOut => IF_curr_PC
);
registers_0 : registers port map(
RR1 => ID_instruction(9 downto 5),
RR2 => ID_RR2,
WR => WB_WR,
WD => WB_WD,
RegWrite => WB_regwrite,
Clock => clk,
RD1 => ID_RD1,
RD2 => ID_RD2,
DEBUG_TMP_REGS => I_DEBUG_TMP_REGS,
DEBUG_SAVED_REGS=> I_DEBUG_SAVED_REGS
);
CPUControl_0 : CPUControl port map(
Opcode => ID_opcode,
Stall => ID_stall,
RegDst => ID_RegDst,
CBranch => ID_cbranch,
MemRead => ID_memread,
MemtoReg => ID_memtoreg,
MultoReg => ID_MultoReg,
MemWrite => ID_memwrite,
ALUSrc => ID_ALUsrc,
RegWrite => ID_regwrite,
ALUOp => ID_ALUOpShort,
Ubranch => ID_ubranch,
Shift => ID_shift
);
ALU_0 : ALU port map(
in0 => EX_ALU_A_SH,
in1 => EX_ALU_B,
operation => EX_ALUOpLong,
result => EX_ALU_result,
zero => EX_ALU_zero,
overflow => EX_ALU_overflow
);
SH_0 : shifter port map(
shamt => EX_shamt,
Rnin => EX_ALU_A,
Rnout => EX_ALU_A_SH,
enable => EX_shift,
direction => EX_opcode(0)
);
ALUControl_0 : ALUControl port map(
ALUOp => EX_ALUOpShort,
Opcode => EX_opcode,
Operation => EX_ALUOpLong
);
FWUnit_0 : forwardUnit port map(
MM_WR => MM_WR,
WB_WR => WB_WR,
MM_regwrite => MM_regwrite,
WB_regwrite => WB_regwrite,
EX_RR1 => EX_RR1,
EX_RR2 => EX_RR2,
forwardA => EX_forwardA,
forwardB => EX_forwardB
);
HDU_0 : hazardDetectionUnit port map(
clk => clk,
rst => rst,
ID_branch => ID_branch,
EX_memread => EX_memread,
EX_WR => EX_WR,
MM_WR => MM_WR,
ID_RR1 => ID_instruction(9 downto 5),
ID_RR2 => ID_RR2,
EX_regwrite => EX_regwrite,
ID_cbranch => ID_cbranch,
MM_memread => MM_memread,
Stall => ID_Stall,
Flush => IF_flush
);
ZC_0 : zeroCheck port map (
ID_RD2 => ID_RD2,
MM_WD => MM_ALU_Result,
WB_WD => WB_WD,
ID_RR2 => ID_RR2,
MM_WR => MM_WR,
WB_WR => WB_WR,
MM_regwrite => MM_regwrite,
WB_regwrite => WB_regwrite,
ID_zero => ID_zero
);
--Mapping pipeline registers
IFID_0 : IFIDRegister port map(
clk => clk,
en => "not"(ID_stall),
rst => rst,
flush => IF_flush,
IF_curr_PC => IF_curr_PC,
IF_instruction => IF_instruction,
--outputs
ID_instruction => ID_instruction,
ID_curr_PC => ID_curr_PC
);
IDEX_0 : IDEXRegister port map(
clk => clk,
rst => rst,
ID_ubranch => ID_ubranch,
ID_cbranch => ID_cbranch,
ID_memread => ID_memread,
ID_memwrite => ID_memwrite,
ID_memtoreg => ID_memtoreg,
ID_multoreg => ID_multoreg,
ID_ALUsrc => ID_ALUsrc,
ID_regwrite => ID_regwrite,
ID_opcode => ID_opcode,
ID_ALUOpShort => ID_ALUOpShort,
ID_WR => ID_WR,
ID_RR1 => ID_instruction(9 downto 5),
ID_RR2 => ID_RR2,
ID_RD1 => ID_RD1,
ID_RD2 => ID_RD2,
ID_immediate => ID_immediate,
ID_curr_PC => (others => '0'),
ID_shift => ID_shift,
ID_shamt => ID_shamt,
ID_MEMOp => ID_MEMOp,
ID_MEMExt => ID_MEMExt,
EX_ubranch => EX_ubranch,
EX_cbranch => EX_cbranch,
EX_memread => EX_memread,
EX_memwrite => EX_memwrite,
EX_memtoreg => EX_memtoreg,
EX_multoreg => EX_multoreg,
EX_ALUsrc => EX_ALUsrc,
EX_regwrite => EX_regwrite,
EX_opcode => EX_opcode,
EX_ALUOpShort => EX_ALUOpShort,
EX_WR => EX_WR,
EX_RR1 => EX_RR1,
EX_RR2 => EX_RR2,
EX_RD1 => EX_RD1,
EX_RD2 => EX_RD2,
EX_immediate => EX_immediate,
EX_shift => EX_shift,
EX_shamt => EX_shamt,
EX_MEMOp => EX_MEMOp,
EX_MEMExt => EX_MEMExt
);
EXMM_0 : EXMMRegister port map(
clk => clk,
rst => rst,
EX_ubranch => '0',
EX_cbranch => '0',
EX_memread => EX_memread,
EX_memwrite => EX_memwrite,
EX_memtoreg => EX_memtoreg,
EX_multoreg => EX_multoreg,
EX_regwrite => EX_regwrite,
EX_WR => EX_WR,
EX_RD2 => EX_FWDED_RD2,
EX_ALU_zero => EX_ALU_zero,
EX_ALU_result => EX_ALU_result,
EX_branch_PC => (others => '0'),
EX_MEMOp => EX_MEMOp,
EX_MEMExt => EX_MEMExt,
MM_memread => MM_memread,
MM_memwrite => MM_memwrite,
MM_memtoreg => MM_memtoreg,
MM_multoreg => MM_multoreg,
MM_regwrite => MM_regwrite,
MM_WR => MM_WR,
MM_RD2 => MM_RD2,
MM_ALU_zero => MM_ALU_zero,
MM_ALU_result => MM_ALU_result,
MM_MEMOp => MM_MEMOp,
MM_MEMExt => MM_MEMExt
);
MMWB_0 : MMWBRegister port map(
clk => clk,
rst => rst,
MM_memtoreg => MM_memtoreg,
MM_multoreg => MM_multoreg,
MM_regwrite => MM_regwrite,
MM_WR => MM_WR,
MM_ALU_result => MM_ALU_result,
MM_memory_data => MM_memory_data,
WB_memtoreg => WB_memtoreg,
WB_multoreg => WB_multoreg,
WB_regwrite => WB_regwrite,
WB_WR => WB_WR,
WB_ALU_result => WB_ALU_result,
WB_memory_data => WB_memory_data
);
----Setup Combinational Programming----
--Reg 2 selection
ID_RR2 <= ID_instruction(20 downto 16) when ID_RegDst = '0' else
ID_instruction(4 downto 0);
--ALU Op B Selection
EX_ALU_B <= EX_FWDED_RD2 when EX_ALUSrc = '0' else
EX_immediate;
--Register read data
WB_WD <= WB_ALU_result when (WB_memtoreg and WB_multoreg) = '0' else --TODO ADD MULIPLY RESULT
WB_memory_data;
--Branch Combinational Logic --TODO May need forwarding
ID_branch <= ((ID_zero and ID_cbranch and (not ID_opcode(3))) or --CBZ
((not ID_zero) and ID_cbranch and ID_opcode(3)) or --CBNZ
ID_ubranch);
--PC Calculation
ID_branch_PC <= std_logic_vector(unsigned(ID_curr_PC)
+ shift_left(unsigned(ID_immediate), 2));
--PC Selection
IF_new_PC <= std_logic_vector(unsigned(IF_curr_PC) + to_unsigned(4, 64))
when ID_branch = '0' else ID_branch_PC;
--Immediate Logic
ID_immediate <= std_logic_vector(resize(signed(ID_instruction(25 downto 0)), 64))
when (ID_ubranch and not ID_cbranch) = '1' else
std_logic_vector(resize(signed(ID_instruction(23 downto 5)), 64))
when (ID_cbranch and not ID_ubranch) = '1' else
std_logic_vector(resize(unsigned(ID_instruction(20 downto 12)), 64))
when (ID_memread or ID_memwrite) = '1' else
std_logic_vector(resize(signed(ID_instruction(21 downto 10)), 64));
--Memory Handling Outputs
--Forwarding
with EX_forwardA select
EX_ALU_A <= MM_ALU_result when "10",
WB_WD when "01",
EX_RD1 when others;
with EX_forwardB select
EX_FWDED_RD2 <= MM_ALU_result when "10",
WB_WD when "01",
EX_RD2 when others;
--Connect outputs
----Assignment----
DEBUG_PC <= IF_curr_PC;
DEBUG_INSTRUCTION <= IF_instruction;
ID_opcode <= ID_instruction(31 downto 21);
ID_WR <= ID_instruction(4 downto 0);
DEBUG_FORWARDA <= EX_forwardA;
DEBUG_FORWARDB <= EX_forwardB;
ID_shamt <= ID_instruction(15 downto 10);
----Internal Debug Signals----
DEBUG_IF_FLUSH <= IF_flush;
DEBUG_REG_EQUAL <= ID_zero;
DEBUG_PC_WRITE_ENABLE <= not ID_stall;
DEBUG_TMP_REGS <= I_DEBUG_TMP_REGS;
DEBUG_SAVED_REGS <= I_DEBUG_SAVED_REGS;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sseg_mux is
port(
clk, reset: in std_logic;
in0, in1, in2, in3: in std_logic_vector(7 downto 0);
en: out std_logic_vector(3 downto 0);
sseg: out std_logic_vector(7 downto 0)
);
end sseg_mux;
architecture mux_arch of sseg_mux is
constant N: integer := 10;
signal q, q_next: std_logic_vector(N - 1 downto 0);
signal sel: std_logic_vector(1 downto 0);
begin
q_next <= q + 1;
process(clk, reset)
begin
if (reset = '1') then
q <= (others => '0');
elsif (clk'event and clk = '0') then
q <= q_next;
end if;
end process;
sel <= q(N - 1 downto N - 2);
process(sel, in0, in1, in2, in3)
begin
case sel is
when "00" =>
en <= "1110";
sseg <= in0;
when "01" =>
en <= "1101";
sseg <= in1;
when "10" =>
en <= "1011";
sseg <= in2;
when others =>
en <= "0111";
sseg <= in3;
end case;
end process;
end mux_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 31.10.2019 22:56:35
-- Design Name:
-- Module Name: DIVIDER - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DIVIDER is
Port ( CLK_IN : in STD_LOGIC;
CLK_OUT : out STD_LOGIC);
end DIVIDER;
architecture Behavioral of DIVIDER is
signal i: integer := 0;
signal temp: std_logic := '0';
constant divide_value: integer := 200000000;
begin
process (CLK_IN)
begin
if CLK_IN' event and CLK_IN = '1' then
if (i = divide_value) then
i <= 0;
temp <= not temp;
else i <= i + 1;
end if;
end if;
end process;
CLK_OUT <= temp;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: DHBW
-- Engineer: <NAME>
--
-- Create Date: 05/01/2021 09:10:02 AM
-- Design Name: PMP_PMA_checker
-- Module Name: PMP_checker
-- Project Name: EDRICO
-- Target Devices: Arty Z7
-- Tool Versions:
-- Description:
-- module to instantiate the PMP_unit modules and determine
-- whether or not an access is enabled. If exceptions are raised,
-- the PMP_checker determines which sort of exception (load,
-- instruction or storeAMO access fault exceptions are possible).
-- Dependencies:
-- PMP_unit.vhd
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library PMP_lib;
use PMP_lib.PMP_PMA_pkg.all;
entity PMP_checker is
port(
------------------------------------------------------------------------------
--input signals
------------------------------------------------------------------------------
--PMP information
pmpcfg: in type_pmpcfg; --array of 16 7-bit std_logic_vector
pmpaddr: in type_pmpaddr; --array of 16 32-bit std_logic_vector
--address to check
address: in std_logic_vector(31 downto 0);
--control signals
readWrite: in std_logic;
instruction: in std_logic;
enable: in std_logic;
size: in std_logic_vector(1 downto 0);
------------------------------------------------------------------------------
--output signals
------------------------------------------------------------------------------
--debug outputs
address_hit_verify : out std_logic_vector(15 downto 0);
load_afe_verify : out std_logic_vector(15 downto 0);
storeAMO_afe_verify : out std_logic_vector(15 downto 0);
instruction_afe_verify : out std_logic_vector(15 downto 0);
address_upper_verify : out std_logic_vector(31 downto 0);
--enable signal
enable_pmp: out std_logic;
--exception signals
load_afe_P: out std_logic;
instruction_afe_P: out std_logic;
storeAMO_afe_P: out std_logic
);
end entity;
architecture rtl of PMP_checker is
----------------------------------------------------------------------------------
--signals
----------------------------------------------------------------------------------
signal access_size: std_logic_vector(31 downto 0); --hold upper border for access
signal address_upper: std_logic_vector(31 downto 0); --hold access size in 32-bit binary
signal address_hit: std_logic_vector(15 downto 0); --16-bit address_hit vector
signal load_afe_P_unit: std_logic_vector(15 downto 0); --16-bit exception_hit vector
signal storeAMO_afe_P_unit: std_logic_vector(15 downto 0); --16-bit exception_hit vector
signal instruction_afe_P_unit: std_logic_vector(15 downto 0); --16-bit exception_hit vector
signal enable_int: std_logic; --internal enable signal
signal exception_vect: std_logic_vector(2 downto 0); --internal exception signal exception_vect(2) = load_afe_P, exception_vect(1) = storeAMO_afe_P, exception_vect(0) = instruction_afe_P
begin
--debug outputs
address_hit_verify <=address_hit;
load_afe_verify <= load_afe_P_unit;
storeAMO_afe_verify <= storeAMO_afe_P_unit;
instruction_afe_verify <= instruction_afe_P_unit;
address_upper_verify <= address_upper;
----------------------------------------------------------------------------------
--upper address calc
-- calculate upper bounds of access
----------------------------------------------------------------------------------
--caclualte access_size from coded signal to actual number
access_size <= x"00000000" when size = "00" else
x"00000001" when size = "01" else
x"00000003" when size = "10" else
x"00000000"; --is that okay? what happens if size is "11", should not happen but still be defined
--calculate upper address border for access.
address_upper <= std_logic_vector(unsigned(address)+unsigned(access_size));--overflow should not be a sproblem since RISC-V address space wraps arround (cehck this!)
----------------------------------------------------------------------------------
--PMP unit generation
-- implement 16 PMPunits
----------------------------------------------------------------------------------
--first PMP unit outside generate since pmpaddrLOW must be set to x"00000000"
unit0: PMP_unit
port map(
------------------------------------------------------------------------------
--input signals
------------------------------------------------------------------------------
--PMP register inputs
pmpcfg => pmpcfg(0),
pmpaddr => pmpaddr(0),
pmpaddrLow => x"00000000",
--control signal inputs
address_upper => address_upper,
readWrite => readWrite,
instruction => instruction,
--address to check
address => address,
------------------------------------------------------------------------------
--output signals
------------------------------------------------------------------------------
address_hit => address_hit(0),
load_afe_P => load_afe_P_unit(0),
storeAMO_afe_P => storeAMO_afe_P_unit(0),
instruction_afe_P => instruction_afe_P_unit(0)
);
--generation of upper 15 PMP_unit instances
unit_gen: for k in 1 to 15 generate
unit: PMP_unit
port map(
------------------------------------------------------------------------------
--input signals
------------------------------------------------------------------------------
--PMP register inputs
pmpcfg => pmpcfg(k),
pmpaddr => pmpaddr(k),
pmpaddrLow => pmpaddr(k-1),
--control signal inputs
address_upper => address_upper,
readWrite => readWrite,
instruction => instruction,
--address to check
address => address,
------------------------------------------------------------------------------
--output signals
------------------------------------------------------------------------------
address_hit => address_hit(k),
load_afe_P => load_afe_P_unit(k),
storeAMO_afe_P => storeAMO_afe_P_unit(k),
instruction_afe_P => instruction_afe_P_unit(k)
);
end generate;
----------------------------------------------------------------------------------
--exception signal generation
-- multiplexer and logic network to generate the exception signals on a hit
-- (and for the correct hit, if multiple are detected)
----------------------------------------------------------------------------------
exception_vect <= load_afe_P_unit(0) & storeAMO_afe_P_unit(0) & instruction_afe_P_unit(0) when address_hit(0) = '1' else
load_afe_P_unit(1) & storeAMO_afe_P_unit(1) & instruction_afe_P_unit(1) when address_hit(1 downto 0) = "10" else
load_afe_P_unit(2) & storeAMO_afe_P_unit(2) & instruction_afe_P_unit(2) when address_hit(2 downto 0) = "100" else
load_afe_P_unit(3) & storeAMO_afe_P_unit(3) & instruction_afe_P_unit(3) when address_hit(3 downto 0) = x"8" else
load_afe_P_unit(4) & storeAMO_afe_P_unit(4) & instruction_afe_P_unit(4) when address_hit(4 downto 0) = "1" & x"0" else
load_afe_P_unit(5) & storeAMO_afe_P_unit(5) & instruction_afe_P_unit(5) when address_hit(5 downto 0) = "10" & x"0" else
load_afe_P_unit(6) & storeAMO_afe_P_unit(6) & instruction_afe_P_unit(6) when address_hit(6 downto 0) = "100" & x"0" else
load_afe_P_unit(7) & storeAMO_afe_P_unit(7) & instruction_afe_P_unit(7) when address_hit(7 downto 0) = x"80" else
load_afe_P_unit(8) & storeAMO_afe_P_unit(8) & instruction_afe_P_unit(8) when address_hit(8 downto 0) = "1" & x"00" else
load_afe_P_unit(9) & storeAMO_afe_P_unit(9) & instruction_afe_P_unit(9) when address_hit(9 downto 0) = "10" & x"00" else
load_afe_P_unit(10) & storeAMO_afe_P_unit(10) & instruction_afe_P_unit(10) when address_hit(10 downto 0) = "100" & x"00" else
load_afe_P_unit(11) & storeAMO_afe_P_unit(11) & instruction_afe_P_unit(11) when address_hit(11 downto 0) = x"800" else
load_afe_P_unit(12) & storeAMO_afe_P_unit(12) & instruction_afe_P_unit(12) when address_hit(12 downto 0) = "1" & x"000" else
load_afe_P_unit(13) & storeAMO_afe_P_unit(13) & instruction_afe_P_unit(13) when address_hit(13 downto 0) = "10" & x"000" else
load_afe_P_unit(14) & storeAMO_afe_P_unit(14) & instruction_afe_P_unit(14) when address_hit(14 downto 0) = "100" & x"000" else
load_afe_P_unit(15) & storeAMO_afe_P_unit(15) & instruction_afe_P_unit(15) when address_hit(15 downto 0) = x"8000" else
"000";
--connect raised exceptions to the corresponding outputs
load_afe_P <= exception_vect(2) and enable;
storeAMO_afe_P <= exception_vect(1) and enable;
instruction_afe_P <= exception_vect(0) and enable;
----------------------------------------------------------------------------------
--enable_PMP signal generation
-- multiplexer to generate an enbale_PMP signal depending on which PMP unit
-- detected a hit
----------------------------------------------------------------------------------
enable_int <= not (exception_vect(2) or exception_vect(1) or exception_vect(0));
enable_PMP <= enable_int and enable;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity bar_m is
port (
clock : in std_logic;
a : in std_logic;
b : in std_logic;
x : out std_logic;
y : out std_logic
);
end entity;
architecture rtl of bar_m is
begin
process (clock) begin
if (rising_edge(clock)) then
x <= a xor b;
y <= not (a and b);
end if;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- PandA Motion Project - 2016
-- Diamond Light Source, Oxford, UK
-- SOLEIL Synchrotron, GIF-sur-YVETTE, France
--
-- Author : Dr. <NAME> (<EMAIL>)
--------------------------------------------------------------------------------
--
-- Description : LED status management for TTL input and outputs
-- TTL signals are monitored at 50ms interval and a packet
-- containing led status is sent to SlowFPGA
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.support.all;
use work.top_defines.all;
use work.slow_defines.all;
use work.addr_defines.all;
entity led_management is
port (
-- Clock and Reset
clk_i : in std_logic;
reset_i : in std_logic;
-- Block Input and Outputs
ttlin_i : in std_logic_vector(TTLIN_NUM-1 downto 0);
ttlout_i : in std_logic_vector(TTLOUT_NUM-1 downto 0);
inenc_conn_i : in std_logic_vector(ENC_NUM-1 downto 0);
outenc_conn_i : in std_logic_vector(ENC_NUM-1 downto 0);
pcap_act_i : in std_logic;
slow_tlp_o : out slow_packet
);
end led_management;
architecture rtl of led_management is
-- Total number of LEDs to control
constant LED_COUNT : natural := TTLIN_NUM + TTLOUT_NUM;
signal check_tick : std_logic;
signal val : std_logic_vector(LED_COUNT-1 downto 0);
signal val_prev : std_logic_vector(LED_COUNT-1 downto 0);
signal changed : std_logic_vector(LED_COUNT-1 downto 0);
signal ttlio_leds : std_logic_vector(LED_COUNT-1 downto 0);
signal status_leds : std_logic_vector(3 downto 0) := (others => '0');
signal data : std_logic_vector(31 downto 0) := (others => '0');
signal data_prev : std_logic_vector(31 downto 0);
signal pcap_act_reg : std_logic;
begin
--------------------------------------------------------------------------
-- 1 second heartbeat to LED from Zynq -> SlowFPGA
--------------------------------------------------------------------------
process(clk_i)
variable counter : integer range 0 to 62500000;
begin
if rising_edge(clk_i) then
pcap_act_reg <= pcap_act_i;
if (counter = 62499999) then
status_leds(0) <= not status_leds(0);
counter := 0;
else
counter := counter + 1;
end if;
status_leds(3) <= pcap_act_reg;
end if;
end process;
--------------------------------------------------------------------------
-- 50ms counter tick
--------------------------------------------------------------------------
frame_presc : entity work.prescaler
port map (
clk_i => clk_i,
reset_i => reset_i,
PERIOD => TO_SVECTOR(6250000, 32),
pulse_o => check_tick
);
--------------------------------------------------------------------------
-- Detect change on I/O @check_tick, and toggle led pulses accordingly.
-- LEDs are toggled in sync with the check_tick, not actual I/O transition.
--------------------------------------------------------------------------
process(clk_i) begin
if rising_edge(clk_i) then
if (reset_i = '1') then
val <= (others => '0');
val_prev <= (others => '0');
changed <= (others => '0');
ttlio_leds <= (others => '0');
else
-- Combine all I/O to detect change bits
val <= ttlin_i & ttlout_i;
val_prev <= val;
-- Check whether a transition occured during 50ms
if (check_tick = '1') then
changed <= (others => '0');
else
changed <= (val xor val_prev) or changed;
end if;
-- Toggle individual ttlio_leds
FOR I IN 0 TO LED_COUNT-1 LOOP
if (check_tick = '1') then
if (changed(I) = '1') then
ttlio_leds(I) <= not ttlio_leds(I);
else
ttlio_leds(I) <= val(I);
end if;
end if;
END LOOP;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- Custom bits currently includes OutEnc disconnect action.
--------------------------------------------------------------------------
data <= ZEROS(4) & inenc_conn_i & status_leds & outenc_conn_i & ttlio_leds;
--------------------------------------------------------------------------
-- Send a packet to Slow FPGA only if data is changed
--------------------------------------------------------------------------
SLOW_WRITE : process(clk_i)
begin
if rising_edge(clk_i) then
if (reset_i = '1') then
slow_tlp_o.strobe <= '0';
slow_tlp_o.address <= (others => '0');
slow_tlp_o.data <= (others => '0');
data_prev <= (others => '0');
else
data_prev <= data;
slow_tlp_o.strobe <= '0';
-- Transfer TLP to Slow FPGA only when data changes to keep the
-- traffic low.
if (data /= data_prev) then
slow_tlp_o.strobe <= '1';
slow_tlp_o.data <= data;
slow_tlp_o.address <= TO_SVECTOR(TTL_LEDS, PAGE_AW);
end if;
end if;
end if;
end process;
end rtl;
|
------------------------------------------------------------------------------
-- Testbench for the tstbitat0 function of the zunit
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/tb_arch/tstbitat0/tb_tstbitat0.vhd $
-- Author : <NAME> <<EMAIL>>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2004/10/26
-- Last changed: $LastChangedDate: 2005-01-13 17:52:03 +0100 (Thu, 13 Jan 2005) $
-- $Id: tb_tstbitat0.vhd 217 2005-01-13 16:52:03Z plessl $
------------------------------------------------------------------------------
-- This testbench tests the tstbitat0 function of the zunit.
--
-- The primary goal of this testbench is to provide an example of a testbench
-- that can be used for standalone simulation and co-simulation to verify the
-- correct function of the zunit.
--
-- There a 2 main purposes of the testbench:
-- a) specific testing of newly added components and features
-- b) regression testing of the whole architecture
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-05 CP created (based on the tb_zarch testbench by <NAME>)
-- 2004-10-26 CP extended for automated verification of testvectors
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_TSTBITAT0.all;
entity tb_tstbitat0 is
end tb_tstbitat0;
architecture arch of tb_tstbitat0 is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal cycle : integer := 1;
constant NDATA : integer := 6; -- nr. of data elements
constant NRUNCYCLES : integer := NDATA+2; -- nr. of run cycles
type tbstatusType is (tbstart, idle, done, rst, wr_cfg, set_cmptr,
push_data_fifo0, push_data_fifo1, inlevel,
wr_ncycl, rd_ncycl, running,
outlevel, pop_data, finished);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- configuration stuff
signal Cfg : engineConfigRec :=
tstbitat0cfg;
signal CfgxD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Cfg);
signal CfgPrt : cfgPartArray := partition_config(CfgxD);
file HFILE : text open write_mode is "tstbitat0_cfg.h";
type fifo_array is array (0 to (3*NDATA)-1) of
std_logic_vector(15 downto 0);
--------------------------------------------------------------------
-- test vectors
-- out = tst_bitsat0(a,b)
-- array contains: contents for fifo0, contents for fifo1, expected
-- result
--------------------------------------------------------------------
constant TESTV : fifo_array :=
(b"0000_0000_0000_0000", -- a 0000
b"0000_1111_0000_1111", -- b 0F0F
b"1111_1111_1111_1111", -- out FFFF
b"0000_0000_0000_0000", -- a 0000
b"0000_0000_0000_0000", -- b 0000
b"1111_1111_1111_1111", -- out FFFF
b"0111_1101_1010_0101", -- a 7DA5
b"1000_0010_0000_1000", -- b 8208
b"1111_1111_1111_1111", -- out FFFF
b"1101_0101_1101_1000", -- a D5D8
b"1011_0000_0010_0000", -- b B020
b"0000_0000_0000_0000", -- out 0000
b"1001_0111_1110_0001", -- a 97E1
b"0010_1100_0000_0000", -- b 2C00
b"0000_0000_0000_0000", -- out 0000
b"1001_0111_1110_0001", -- a 97E1
b"0010_1000_0000_0010", -- b 2802
b"1111_1111_1111_1111" -- out FFFF
);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
begin -- process hFileGen
gen_cfghfile(HFILE, CfgPrt);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
variable expectedresponse : std_logic_vector(15 downto 0) := (others => '0');
variable response : std_logic_vector(15 downto 0) := (others => '0');
begin -- process stimuliTb
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- reset (ZREG_RST:W)
-------------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write configuration slices (ZREG_CFGMEM0:W)
-------------------------------------------------
tbStatus <= wr_cfg;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in CfgPrt'low to CfgPrt'high loop
DataInxD <= CfgPrt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- push data into FIFO0 (ZREG_FIFO0:W)
-------------------------------------------------
tbStatus <= push_data_fifo0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
DataInxD <= (others => '0');
DataInxD(15 downto 0) <= TESTV(i*3);
-- assert false
-- report "writing to FIFO0:" & hstr(TESTV(i*3))
-- severity note;
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- push data into FIFO1 (ZREG_FIFO1:W)
-------------------------------------------------
tbStatus <= push_data_fifo1;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
for i in 0 to NDATA-1 loop
DataInxD <= (others => '0');
DataInxD(15 downto 0) <= TESTV(i*3+1);
-- assert false
-- report "writing to FIFO1:" & hstr(TESTV(i*3+1))
-- severity note;
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- write cycle count register (ZREG_CYCLECNT:W)
-------------------------------------------------
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(NRUNCYCLES, IFWIDTH));
wait for CLK_PERIOD;
-------------------------------------------------
-- computation running
-------------------------------------------------
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
for i in 1 to NRUNCYCLES loop
wait for CLK_PERIOD;
end loop; -- i
-- -----------------------------------------------
-- pop data from out buffer (ZREG_FIFO0:R)
-- -----------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
wait for CLK_PERIOD;
expectedresponse := TESTV(3*i+2);
response := DataOutxD(15 downto 0);
assert response = expectedresponse
report "FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE" & LF &
"regression test failed, response " & hstr(response) &
" does NOT match expected response "
& hstr(expectedresponse) & " tv: " & str(i) & LF &
"FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE"
severity failure;
assert not(response = expectedresponse)
report "response " & hstr(response) & " matches expected " &
"response " & hstr(expectedresponse)
severity note;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-----------------------------------------------
-- done stop simulation
-----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
---------------------------------------------------------------------------
-- stopping the simulation is done by using the following TCL script
-- in modelsim, since terminating the simulation with an assert failure is
-- a crude hack:
--
-- when {/tbStatus == done} {
-- echo "At Time $now Ending the simulation"
-- quit -f
-- }
---------------------------------------------------------------------------
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "Testbench successfully terminated after " & str(cycle) &
" cycles, no errors found!"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
cycle <= cycle + 1;
end if;
end process cyclecounter;
end arch;
|
-- Copyright (C) 2019 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
-- VENDOR "Altera"
-- PROGRAM "Quartus Prime"
-- VERSION "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition"
-- DATE "04/12/2022 16:40:42"
--
-- Device: Altera EP4CE115F29C7 Package FBGA780
--
--
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
--
LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY hard_block IS
PORT (
devoe : IN std_logic;
devclrn : IN std_logic;
devpor : IN std_logic
);
END hard_block;
-- Design Ports Information
-- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
ARCHITECTURE structure OF hard_block IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
BEGIN
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
END structure;
LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CmpN_Demo IS
PORT (
LEDG : OUT std_logic_vector(3 DOWNTO 0);
SW : IN std_logic_vector(17 DOWNTO 0);
LEDr : OUT std_logic_vector(3 DOWNTO 0)
);
END CmpN_Demo;
-- Design Ports Information
-- LEDG[3] => Location: PIN_E24, I/O Standard: 2.5 V, Current Strength: Default
-- LEDG[2] => Location: PIN_E25, I/O Standard: 2.5 V, Current Strength: Default
-- LEDG[1] => Location: PIN_E22, I/O Standard: 2.5 V, Current Strength: Default
-- LEDG[0] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default
-- LEDr[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default
-- LEDr[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
-- LEDr[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
-- LEDr[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
-- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default
-- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default
-- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
-- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
-- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default
-- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
-- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default
-- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
-- SW[11] => Location: PIN_AB24, I/O Standard: 2.5 V, Current Strength: Default
-- SW[17] => Location: PIN_Y23, I/O Standard: 2.5 V, Current Strength: Default
-- SW[12] => Location: PIN_AB23, I/O Standard: 2.5 V, Current Strength: Default
-- SW[16] => Location: PIN_Y24, I/O Standard: 2.5 V, Current Strength: Default
-- SW[9] => Location: PIN_AB25, I/O Standard: 2.5 V, Current Strength: Default
-- SW[8] => Location: PIN_AC25, I/O Standard: 2.5 V, Current Strength: Default
-- SW[13] => Location: PIN_AA24, I/O Standard: 2.5 V, Current Strength: Default
-- SW[14] => Location: PIN_AA23, I/O Standard: 2.5 V, Current Strength: Default
-- SW[10] => Location: PIN_AC24, I/O Standard: 2.5 V, Current Strength: Default
-- SW[15] => Location: PIN_AA22, I/O Standard: 2.5 V, Current Strength: Default
ARCHITECTURE structure OF CmpN_Demo IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_LEDG : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_SW : std_logic_vector(17 DOWNTO 0);
SIGNAL ww_LEDr : std_logic_vector(3 DOWNTO 0);
SIGNAL \LEDG[3]~output_o\ : std_logic;
SIGNAL \LEDG[2]~output_o\ : std_logic;
SIGNAL \LEDG[1]~output_o\ : std_logic;
SIGNAL \LEDG[0]~output_o\ : std_logic;
SIGNAL \LEDr[3]~output_o\ : std_logic;
SIGNAL \LEDr[2]~output_o\ : std_logic;
SIGNAL \LEDr[1]~output_o\ : std_logic;
SIGNAL \LEDr[0]~output_o\ : std_logic;
SIGNAL \SW[3]~input_o\ : std_logic;
SIGNAL \SW[7]~input_o\ : std_logic;
SIGNAL \inst|LessThan1~2_combout\ : std_logic;
SIGNAL \SW[4]~input_o\ : std_logic;
SIGNAL \SW[0]~input_o\ : std_logic;
SIGNAL \inst|LessThan1~1_combout\ : std_logic;
SIGNAL \SW[1]~input_o\ : std_logic;
SIGNAL \SW[5]~input_o\ : std_logic;
SIGNAL \SW[6]~input_o\ : std_logic;
SIGNAL \SW[2]~input_o\ : std_logic;
SIGNAL \inst|Equal0~0_combout\ : std_logic;
SIGNAL \inst|LessThan1~0_combout\ : std_logic;
SIGNAL \inst|LessThan1~3_combout\ : std_logic;
SIGNAL \inst|LessThan1~4_combout\ : std_logic;
SIGNAL \inst|LessThan0~0_combout\ : std_logic;
SIGNAL \inst|Equal0~1_combout\ : std_logic;
SIGNAL \SW[13]~input_o\ : std_logic;
SIGNAL \SW[9]~input_o\ : std_logic;
SIGNAL \SW[8]~input_o\ : std_logic;
SIGNAL \SW[14]~input_o\ : std_logic;
SIGNAL \inst8|LessThan1~2_combout\ : std_logic;
SIGNAL \SW[15]~input_o\ : std_logic;
SIGNAL \SW[10]~input_o\ : std_logic;
SIGNAL \SW[17]~input_o\ : std_logic;
SIGNAL \SW[12]~input_o\ : std_logic;
SIGNAL \SW[11]~input_o\ : std_logic;
SIGNAL \SW[16]~input_o\ : std_logic;
SIGNAL \inst8|LessThan1~1_combout\ : std_logic;
SIGNAL \inst8|LessThan1~3_combout\ : std_logic;
SIGNAL \inst8|LessThan1~0_combout\ : std_logic;
SIGNAL \inst8|LessThan1~4_combout\ : std_logic;
SIGNAL \inst8|LessThan0~0_combout\ : std_logic;
SIGNAL \inst8|Equal0~0_combout\ : std_logic;
SIGNAL \inst8|Equal0~1_combout\ : std_logic;
SIGNAL \inst8|ALT_INV_Equal0~1_combout\ : std_logic;
SIGNAL \inst|ALT_INV_Equal0~1_combout\ : std_logic;
COMPONENT hard_block
PORT (
devoe : IN std_logic;
devclrn : IN std_logic;
devpor : IN std_logic);
END COMPONENT;
BEGIN
LEDG <= ww_LEDG;
ww_SW <= SW;
LEDr <= ww_LEDr;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\inst8|ALT_INV_Equal0~1_combout\ <= NOT \inst8|Equal0~1_combout\;
\inst|ALT_INV_Equal0~1_combout\ <= NOT \inst|Equal0~1_combout\;
auto_generated_inst : hard_block
PORT MAP (
devoe => ww_devoe,
devclrn => ww_devclrn,
devpor => ww_devpor);
-- Location: IOOBUF_X85_Y73_N23
\LEDG[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \inst|LessThan1~4_combout\,
devoe => ww_devoe,
o => \LEDG[3]~output_o\);
-- Location: IOOBUF_X83_Y73_N2
\LEDG[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \inst|LessThan0~0_combout\,
devoe => ww_devoe,
o => \LEDG[2]~output_o\);
-- Location: IOOBUF_X111_Y73_N9
\LEDG[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \inst|ALT_INV_Equal0~1_combout\,
devoe => ww_devoe,
o => \LEDG[1]~output_o\);
-- Location: IOOBUF_X107_Y73_N9
\LEDG[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \inst|Equal0~1_combout\,
devoe => ww_devoe,
o => \LEDG[0]~output_o\);
-- Location: IOOBUF_X107_Y73_N16
\LEDr[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \inst8|LessThan1~4_combout\,
devoe => ww_devoe,
o => \LEDr[3]~output_o\);
-- Location: IOOBUF_X94_Y73_N9
\LEDr[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \inst8|LessThan0~0_combout\,
devoe => ww_devoe,
o => \LEDr[2]~output_o\);
-- Location: IOOBUF_X94_Y73_N2
\LEDr[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \inst8|ALT_INV_Equal0~1_combout\,
devoe => ww_devoe,
o => \LEDr[1]~output_o\);
-- Location: IOOBUF_X69_Y73_N16
\LEDr[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \inst8|Equal0~1_combout\,
devoe => ww_devoe,
o => \LEDr[0]~output_o\);
-- Location: IOIBUF_X115_Y13_N8
\SW[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(3),
o => \SW[3]~input_o\);
-- Location: IOIBUF_X115_Y15_N1
\SW[7]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(7),
o => \SW[7]~input_o\);
-- Location: LCCOMB_X114_Y17_N6
\inst|LessThan1~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|LessThan1~2_combout\ = \SW[3]~input_o\ $ (\SW[7]~input_o\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "0101101001011010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[3]~input_o\,
datac => \SW[7]~input_o\,
combout => \inst|LessThan1~2_combout\);
-- Location: IOIBUF_X115_Y18_N8
\SW[4]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(4),
o => \SW[4]~input_o\);
-- Location: IOIBUF_X115_Y17_N1
\SW[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(0),
o => \SW[0]~input_o\);
-- Location: LCCOMB_X114_Y17_N4
\inst|LessThan1~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|LessThan1~1_combout\ = (\SW[4]~input_o\ & !\SW[0]~input_o\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000000011110000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datac => \SW[4]~input_o\,
datad => \SW[0]~input_o\,
combout => \inst|LessThan1~1_combout\);
-- Location: IOIBUF_X115_Y14_N1
\SW[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(1),
o => \SW[1]~input_o\);
-- Location: IOIBUF_X115_Y11_N8
\SW[5]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(5),
o => \SW[5]~input_o\);
-- Location: IOIBUF_X115_Y10_N1
\SW[6]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(6),
o => \SW[6]~input_o\);
-- Location: IOIBUF_X115_Y15_N8
\SW[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(2),
o => \SW[2]~input_o\);
-- Location: LCCOMB_X114_Y17_N26
\inst|Equal0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Equal0~0_combout\ = (\SW[1]~input_o\ & (\SW[5]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\)))) # (!\SW[1]~input_o\ & (!\SW[5]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1001000000001001",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[1]~input_o\,
datab => \SW[5]~input_o\,
datac => \SW[6]~input_o\,
datad => \SW[2]~input_o\,
combout => \inst|Equal0~0_combout\);
-- Location: LCCOMB_X114_Y17_N24
\inst|LessThan1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|LessThan1~0_combout\ = (\SW[6]~input_o\ & (((!\SW[1]~input_o\ & \SW[5]~input_o\)) # (!\SW[2]~input_o\))) # (!\SW[6]~input_o\ & (!\SW[1]~input_o\ & (\SW[5]~input_o\ & !\SW[2]~input_o\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0100000011110100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[1]~input_o\,
datab => \SW[5]~input_o\,
datac => \SW[6]~input_o\,
datad => \SW[2]~input_o\,
combout => \inst|LessThan1~0_combout\);
-- Location: LCCOMB_X114_Y17_N0
\inst|LessThan1~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|LessThan1~3_combout\ = (!\inst|LessThan1~2_combout\ & ((\inst|LessThan1~0_combout\) # ((\inst|LessThan1~1_combout\ & \inst|Equal0~0_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0101010101000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \inst|LessThan1~2_combout\,
datab => \inst|LessThan1~1_combout\,
datac => \inst|Equal0~0_combout\,
datad => \inst|LessThan1~0_combout\,
combout => \inst|LessThan1~3_combout\);
-- Location: LCCOMB_X114_Y17_N10
\inst|LessThan1~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|LessThan1~4_combout\ = (\inst|LessThan1~3_combout\) # ((!\SW[3]~input_o\ & \SW[7]~input_o\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1101110011011100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[3]~input_o\,
datab => \inst|LessThan1~3_combout\,
datac => \SW[7]~input_o\,
combout => \inst|LessThan1~4_combout\);
-- Location: LCCOMB_X114_Y17_N12
\inst|LessThan0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|LessThan0~0_combout\ = (\inst|LessThan1~3_combout\) # ((\SW[3]~input_o\ & !\SW[7]~input_o\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100111011001110",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[3]~input_o\,
datab => \inst|LessThan1~3_combout\,
datac => \SW[7]~input_o\,
combout => \inst|LessThan0~0_combout\);
-- Location: LCCOMB_X114_Y17_N22
\inst|Equal0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|Equal0~1_combout\ = (!\inst|LessThan1~2_combout\ & (\inst|Equal0~0_combout\ & (\SW[4]~input_o\ $ (!\SW[0]~input_o\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0100000000010000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \inst|LessThan1~2_combout\,
datab => \SW[4]~input_o\,
datac => \inst|Equal0~0_combout\,
datad => \SW[0]~input_o\,
combout => \inst|Equal0~1_combout\);
-- Location: IOIBUF_X115_Y9_N22
\SW[13]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(13),
o => \SW[13]~input_o\);
-- Location: IOIBUF_X115_Y16_N8
\SW[9]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(9),
o => \SW[9]~input_o\);
-- Location: IOIBUF_X115_Y4_N22
\SW[8]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(8),
o => \SW[8]~input_o\);
-- Location: IOIBUF_X115_Y10_N8
\SW[14]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(14),
o => \SW[14]~input_o\);
-- Location: LCCOMB_X114_Y10_N12
\inst8|LessThan1~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst8|LessThan1~2_combout\ = (\SW[9]~input_o\ & (((!\SW[13]~input_o\ & \SW[8]~input_o\)) # (!\SW[14]~input_o\))) # (!\SW[9]~input_o\ & (!\SW[13]~input_o\ & (\SW[8]~input_o\ & !\SW[14]~input_o\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0100000011011100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[13]~input_o\,
datab => \SW[9]~input_o\,
datac => \SW[8]~input_o\,
datad => \SW[14]~input_o\,
combout => \inst8|LessThan1~2_combout\);
-- Location: IOIBUF_X115_Y6_N15
\SW[15]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(15),
o => \SW[15]~input_o\);
-- Location: IOIBUF_X115_Y4_N15
\SW[10]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(10),
o => \SW[10]~input_o\);
-- Location: IOIBUF_X115_Y14_N8
\SW[17]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(17),
o => \SW[17]~input_o\);
-- Location: IOIBUF_X115_Y7_N15
\SW[12]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(12),
o => \SW[12]~input_o\);
-- Location: IOIBUF_X115_Y5_N15
\SW[11]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(11),
o => \SW[11]~input_o\);
-- Location: IOIBUF_X115_Y13_N1
\SW[16]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(16),
o => \SW[16]~input_o\);
-- Location: LCCOMB_X114_Y10_N10
\inst8|LessThan1~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst8|LessThan1~1_combout\ = (\SW[17]~input_o\ & (\SW[12]~input_o\ & (\SW[11]~input_o\ $ (!\SW[16]~input_o\)))) # (!\SW[17]~input_o\ & (!\SW[12]~input_o\ & (\SW[11]~input_o\ $ (!\SW[16]~input_o\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1001000000001001",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[17]~input_o\,
datab => \SW[12]~input_o\,
datac => \SW[11]~input_o\,
datad => \SW[16]~input_o\,
combout => \inst8|LessThan1~1_combout\);
-- Location: LCCOMB_X114_Y10_N6
\inst8|LessThan1~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst8|LessThan1~3_combout\ = (\inst8|LessThan1~1_combout\ & ((\inst8|LessThan1~2_combout\ & ((\SW[10]~input_o\) # (!\SW[15]~input_o\))) # (!\inst8|LessThan1~2_combout\ & (!\SW[15]~input_o\ & \SW[10]~input_o\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1011001000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \inst8|LessThan1~2_combout\,
datab => \SW[15]~input_o\,
datac => \SW[10]~input_o\,
datad => \inst8|LessThan1~1_combout\,
combout => \inst8|LessThan1~3_combout\);
-- Location: LCCOMB_X114_Y10_N24
\inst8|LessThan1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst8|LessThan1~0_combout\ = (\SW[11]~input_o\ & (!\SW[16]~input_o\ & (\SW[17]~input_o\ $ (!\SW[12]~input_o\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000000010010000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[17]~input_o\,
datab => \SW[12]~input_o\,
datac => \SW[11]~input_o\,
datad => \SW[16]~input_o\,
combout => \inst8|LessThan1~0_combout\);
-- Location: LCCOMB_X114_Y10_N8
\inst8|LessThan1~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst8|LessThan1~4_combout\ = (\inst8|LessThan1~3_combout\) # ((\inst8|LessThan1~0_combout\) # ((\SW[12]~input_o\ & !\SW[17]~input_o\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111101011111110",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \inst8|LessThan1~3_combout\,
datab => \SW[12]~input_o\,
datac => \inst8|LessThan1~0_combout\,
datad => \SW[17]~input_o\,
combout => \inst8|LessThan1~4_combout\);
-- Location: LCCOMB_X114_Y10_N26
\inst8|LessThan0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst8|LessThan0~0_combout\ = (\inst8|LessThan1~3_combout\) # ((\inst8|LessThan1~0_combout\) # ((!\SW[12]~input_o\ & \SW[17]~input_o\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111101111111010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \inst8|LessThan1~3_combout\,
datab => \SW[12]~input_o\,
datac => \inst8|LessThan1~0_combout\,
datad => \SW[17]~input_o\,
combout => \inst8|LessThan0~0_combout\);
-- Location: LCCOMB_X114_Y10_N28
\inst8|Equal0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst8|Equal0~0_combout\ = (\SW[13]~input_o\ & (\SW[8]~input_o\ & (\SW[9]~input_o\ $ (!\SW[14]~input_o\)))) # (!\SW[13]~input_o\ & (!\SW[8]~input_o\ & (\SW[9]~input_o\ $ (!\SW[14]~input_o\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1000010000100001",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[13]~input_o\,
datab => \SW[9]~input_o\,
datac => \SW[8]~input_o\,
datad => \SW[14]~input_o\,
combout => \inst8|Equal0~0_combout\);
-- Location: LCCOMB_X114_Y10_N14
\inst8|Equal0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst8|Equal0~1_combout\ = (\inst8|LessThan1~1_combout\ & (\inst8|Equal0~0_combout\ & (\SW[10]~input_o\ $ (!\SW[15]~input_o\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1000000000001000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \inst8|LessThan1~1_combout\,
datab => \inst8|Equal0~0_combout\,
datac => \SW[10]~input_o\,
datad => \SW[15]~input_o\,
combout => \inst8|Equal0~1_combout\);
ww_LEDG(3) <= \LEDG[3]~output_o\;
ww_LEDG(2) <= \LEDG[2]~output_o\;
ww_LEDG(1) <= \LEDG[1]~output_o\;
ww_LEDG(0) <= \LEDG[0]~output_o\;
ww_LEDr(3) <= \LEDr[3]~output_o\;
ww_LEDr(2) <= \LEDr[2]~output_o\;
ww_LEDr(1) <= \LEDr[1]~output_o\;
ww_LEDr(0) <= \LEDr[0]~output_o\;
END structure;
|
library ieee;
use ieee.std_logic_1164.all;
entity aes_tb is
end entity;
architecture test of aes_tb is
signal r_key : std_logic_vector(127 downto 0);
signal r_plaintext : std_logic_vector(127 downto 0);
signal r_ciphertext : std_logic_vector(127 downto 0);
component aes is
port (
key : in std_logic_vector(127 downto 0);
plaintext : in std_logic_vector(127 downto 0);
ciphertext : out std_logic_vector(127 downto 0)
);
end component aes;
begin
dut : aes
port map (
key => r_key,
plaintext => r_plaintext,
ciphertext => r_ciphertext
);
process
begin
r_key <= x"<KEY>";
r_plaintext <= x"00112233445566778899aabbccddeeff";
wait;
end process;
end architecture;
|
-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.1 (lin64) Build 2883519 Mon May 4 20:18:30 MDT 2020
-- Date : Thu May 7 16:56:58 2020
-- Host : xsjrdevl100 running 64-bit CentOS Linux release 7.4.1708 (Core)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ pfm_dynamic_memory_subsystem_0_sim_netlist.vhdl
-- Design : pfm_dynamic_memory_subsystem_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcu200-fsgd2104-2-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_concat_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_concat_0 : entity is "bd_d216_calib_concat_0,xlconcat_v2_1_3_xlconcat,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_concat_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_concat_0 : entity is "xlconcat_v2_1_3_xlconcat,Vivado 2020.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_concat_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_concat_0 is
signal \^in0\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\^in0\(0) <= In0(0);
dout(0) <= \^in0\(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_vector_concat_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
In2 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_vector_concat_0 : entity is "bd_d216_calib_vector_concat_0,xlconcat_v2_1_3_xlconcat,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_vector_concat_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_vector_concat_0 : entity is "xlconcat_v2_1_3_xlconcat,Vivado 2020.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_vector_concat_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_vector_concat_0 is
signal \^in0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^in1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^in2\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\^in0\(0) <= In0(0);
\^in1\(0) <= In1(0);
\^in2\(0) <= In2(0);
dout(2) <= \^in2\(0);
dout(1) <= \^in1\(0);
dout(0) <= \^in0\(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interconnect_imp_6HQKUY is
port (
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 33 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 33 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
\bbstub_m_axi_awaddr[38]\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
\bbstub_m_axi_awlen[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
\bbstub_m_axi_awburst[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\bbstub_m_axi_awlock[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\bbstub_m_axi_awcache[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\bbstub_m_axi_awprot[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
\bbstub_m_axi_awqos[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
bbstub_m_axi_awvalid : out STD_LOGIC;
\bbstub_m_axi_wdata[511]\ : out STD_LOGIC_VECTOR ( 511 downto 0 );
\bbstub_m_axi_wstrb[63]\ : out STD_LOGIC_VECTOR ( 63 downto 0 );
bbstub_m_axi_wlast : out STD_LOGIC;
bbstub_m_axi_wvalid : out STD_LOGIC;
bbstub_m_axi_bready : out STD_LOGIC;
\bbstub_m_axi_araddr[38]\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
\bbstub_m_axi_arlen[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
\bbstub_m_axi_arburst[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\bbstub_m_axi_arlock[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\bbstub_m_axi_arcache[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\bbstub_m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
\bbstub_m_axi_arqos[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
bbstub_m_axi_arvalid : out STD_LOGIC;
bbstub_m_axi_rready : out STD_LOGIC;
S01_AXI_awready : out STD_LOGIC;
S01_AXI_wready : out STD_LOGIC;
S01_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_arready : out STD_LOGIC;
S01_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_rlast : out STD_LOGIC;
S01_AXI_rvalid : out STD_LOGIC;
S02_AXI_awready : out STD_LOGIC;
S02_AXI_wready : out STD_LOGIC;
S02_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_bvalid : out STD_LOGIC;
S02_AXI_arready : out STD_LOGIC;
S02_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S02_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_rlast : out STD_LOGIC;
S02_AXI_rvalid : out STD_LOGIC;
S04_AXI_awready : out STD_LOGIC;
S04_AXI_wready : out STD_LOGIC;
S04_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S04_AXI_bvalid : out STD_LOGIC;
S04_AXI_arready : out STD_LOGIC;
S04_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S04_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S04_AXI_rlast : out STD_LOGIC;
S04_AXI_rvalid : out STD_LOGIC;
S05_AXI_awready : out STD_LOGIC;
S05_AXI_wready : out STD_LOGIC;
S05_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S05_AXI_bvalid : out STD_LOGIC;
S05_AXI_arready : out STD_LOGIC;
S05_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S05_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S05_AXI_rlast : out STD_LOGIC;
S05_AXI_rvalid : out STD_LOGIC;
ddr4_mem01_ui_clk : in STD_LOGIC;
aclk : in STD_LOGIC;
interconnect_aresetn : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awready : in STD_LOGIC;
S_AXI_wready : in STD_LOGIC;
S_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : in STD_LOGIC;
S_AXI_arready : in STD_LOGIC;
S_AXI_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rlast : in STD_LOGIC;
S_AXI_rvalid : in STD_LOGIC;
aclk2 : in STD_LOGIC;
interconnect_aresetn1 : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_arready : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rvalid : in STD_LOGIC;
S01_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S01_AXI_wlast : in STD_LOGIC;
S01_AXI_wvalid : in STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S01_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arvalid : in STD_LOGIC;
S01_AXI_rready : in STD_LOGIC;
S02_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S02_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awvalid : in STD_LOGIC;
S02_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S02_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S02_AXI_wlast : in STD_LOGIC;
S02_AXI_wvalid : in STD_LOGIC;
S02_AXI_bready : in STD_LOGIC;
S02_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S02_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arvalid : in STD_LOGIC;
S02_AXI_rready : in STD_LOGIC;
S04_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S04_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S04_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S04_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S04_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_awvalid : in STD_LOGIC;
S04_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S04_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S04_AXI_wlast : in STD_LOGIC;
S04_AXI_wvalid : in STD_LOGIC;
S04_AXI_bready : in STD_LOGIC;
S04_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S04_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S04_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S04_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S04_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_arvalid : in STD_LOGIC;
S04_AXI_rready : in STD_LOGIC;
S05_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S05_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S05_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S05_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S05_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_awvalid : in STD_LOGIC;
S05_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S05_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S05_AXI_wlast : in STD_LOGIC;
S05_AXI_wvalid : in STD_LOGIC;
S05_AXI_bready : in STD_LOGIC;
S05_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S05_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S05_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S05_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S05_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_arvalid : in STD_LOGIC;
S05_AXI_rready : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interconnect_imp_6HQKUY;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interconnect_imp_6HQKUY is
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_interconnect_DDR4_MEM01_0 is
port (
aclk : in STD_LOGIC;
aclk1 : in STD_LOGIC;
aresetn : in STD_LOGIC;
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_awready : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wvalid : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_bready : in STD_LOGIC;
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_arready : out STD_LOGIC;
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S01_AXI_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awuser : in STD_LOGIC_VECTOR ( 113 downto 0 );
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_awready : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S01_AXI_wlast : in STD_LOGIC;
S01_AXI_wuser : in STD_LOGIC_VECTOR ( 13 downto 0 );
S01_AXI_wvalid : in STD_LOGIC;
S01_AXI_wready : out STD_LOGIC;
S01_AXI_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_buser : out STD_LOGIC_VECTOR ( 113 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S01_AXI_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_aruser : in STD_LOGIC_VECTOR ( 113 downto 0 );
S01_AXI_arvalid : in STD_LOGIC;
S01_AXI_arready : out STD_LOGIC;
S01_AXI_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_rlast : out STD_LOGIC;
S01_AXI_ruser : out STD_LOGIC_VECTOR ( 13 downto 0 );
S01_AXI_rvalid : out STD_LOGIC;
S01_AXI_rready : in STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 33 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_awready : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wvalid : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 33 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_arready : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_interconnect_DDR4_MEM01_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_interconnect_M00_AXI_MEM00_0 is
port (
aclk : in STD_LOGIC;
aclk1 : in STD_LOGIC;
aresetn : in STD_LOGIC;
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_awready : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wvalid : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_bready : in STD_LOGIC;
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_arready : out STD_LOGIC;
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_awready : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S01_AXI_wlast : in STD_LOGIC;
S01_AXI_wvalid : in STD_LOGIC;
S01_AXI_wready : out STD_LOGIC;
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S01_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arvalid : in STD_LOGIC;
S01_AXI_arready : out STD_LOGIC;
S01_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_rlast : out STD_LOGIC;
S01_AXI_rvalid : out STD_LOGIC;
S01_AXI_rready : in STD_LOGIC;
S02_AXI_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S02_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awuser : in STD_LOGIC_VECTOR ( 113 downto 0 );
S02_AXI_awvalid : in STD_LOGIC;
S02_AXI_awready : out STD_LOGIC;
S02_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S02_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S02_AXI_wlast : in STD_LOGIC;
S02_AXI_wuser : in STD_LOGIC_VECTOR ( 13 downto 0 );
S02_AXI_wvalid : in STD_LOGIC;
S02_AXI_wready : out STD_LOGIC;
S02_AXI_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_buser : out STD_LOGIC_VECTOR ( 113 downto 0 );
S02_AXI_bvalid : out STD_LOGIC;
S02_AXI_bready : in STD_LOGIC;
S02_AXI_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S02_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_aruser : in STD_LOGIC_VECTOR ( 113 downto 0 );
S02_AXI_arvalid : in STD_LOGIC;
S02_AXI_arready : out STD_LOGIC;
S02_AXI_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S02_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_rlast : out STD_LOGIC;
S02_AXI_ruser : out STD_LOGIC_VECTOR ( 13 downto 0 );
S02_AXI_rvalid : out STD_LOGIC;
S02_AXI_rready : in STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_awready : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wvalid : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_arready : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_interconnect_M00_AXI_MEM00_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_interconnect_S04_AXI_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_awready : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wvalid : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_bready : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_arready : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
M00_AXI_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awuser : out STD_LOGIC_VECTOR ( 113 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_awready : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wuser : out STD_LOGIC_VECTOR ( 13 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_buser : in STD_LOGIC_VECTOR ( 113 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_aruser : out STD_LOGIC_VECTOR ( 113 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_arready : in STD_LOGIC;
M00_AXI_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_ruser : in STD_LOGIC_VECTOR ( 13 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M01_AXI_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
M01_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M01_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_awuser : out STD_LOGIC_VECTOR ( 113 downto 0 );
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_awready : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
M01_AXI_wlast : out STD_LOGIC;
M01_AXI_wuser : out STD_LOGIC_VECTOR ( 13 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M01_AXI_wready : in STD_LOGIC;
M01_AXI_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_buser : in STD_LOGIC_VECTOR ( 113 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
M01_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M01_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M01_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_aruser : out STD_LOGIC_VECTOR ( 113 downto 0 );
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_arready : in STD_LOGIC;
M01_AXI_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rlast : in STD_LOGIC;
M01_AXI_ruser : in STD_LOGIC_VECTOR ( 13 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_rready : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_interconnect_S04_AXI_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_rs_M00_AXI_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_rs_M00_AXI_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_M00_AXI_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_M00_AXI_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_S01_AXI_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_S01_AXI_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_S02_AXI_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_S02_AXI_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_S04_AXI_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_S04_AXI_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_S05_AXI_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_S05_AXI_0;
signal interconnect_M00_AXI_MEM00_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_ARLOCK : STD_LOGIC;
signal interconnect_M00_AXI_MEM00_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_ARREADY : STD_LOGIC;
signal interconnect_M00_AXI_MEM00_M00_AXI_ARVALID : STD_LOGIC;
signal interconnect_M00_AXI_MEM00_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_AWLOCK : STD_LOGIC;
signal interconnect_M00_AXI_MEM00_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_AWREADY : STD_LOGIC;
signal interconnect_M00_AXI_MEM00_M00_AXI_AWVALID : STD_LOGIC;
signal interconnect_M00_AXI_MEM00_M00_AXI_BREADY : STD_LOGIC;
signal interconnect_M00_AXI_MEM00_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_BVALID : STD_LOGIC;
signal interconnect_M00_AXI_MEM00_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_RLAST : STD_LOGIC;
signal interconnect_M00_AXI_MEM00_M00_AXI_RREADY : STD_LOGIC;
signal interconnect_M00_AXI_MEM00_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_RVALID : STD_LOGIC;
signal interconnect_M00_AXI_MEM00_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_WLAST : STD_LOGIC;
signal interconnect_M00_AXI_MEM00_M00_AXI_WREADY : STD_LOGIC;
signal interconnect_M00_AXI_MEM00_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 63 downto 0 );
signal interconnect_M00_AXI_MEM00_M00_AXI_WVALID : STD_LOGIC;
signal interconnect_S04_AXI_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal interconnect_S04_AXI_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_S04_AXI_M00_AXI_ARID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_S04_AXI_M00_AXI_ARLOCK : STD_LOGIC;
signal interconnect_S04_AXI_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_S04_AXI_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_S04_AXI_M00_AXI_ARREADY : STD_LOGIC;
signal interconnect_S04_AXI_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_S04_AXI_M00_AXI_ARUSER : STD_LOGIC_VECTOR ( 113 downto 0 );
signal interconnect_S04_AXI_M00_AXI_ARVALID : STD_LOGIC;
signal interconnect_S04_AXI_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal interconnect_S04_AXI_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_S04_AXI_M00_AXI_AWID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_S04_AXI_M00_AXI_AWLOCK : STD_LOGIC;
signal interconnect_S04_AXI_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_S04_AXI_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_S04_AXI_M00_AXI_AWREADY : STD_LOGIC;
signal interconnect_S04_AXI_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_S04_AXI_M00_AXI_AWUSER : STD_LOGIC_VECTOR ( 113 downto 0 );
signal interconnect_S04_AXI_M00_AXI_AWVALID : STD_LOGIC;
signal interconnect_S04_AXI_M00_AXI_BID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M00_AXI_BREADY : STD_LOGIC;
signal interconnect_S04_AXI_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M00_AXI_BUSER : STD_LOGIC_VECTOR ( 113 downto 0 );
signal interconnect_S04_AXI_M00_AXI_BVALID : STD_LOGIC;
signal interconnect_S04_AXI_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal interconnect_S04_AXI_M00_AXI_RID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M00_AXI_RLAST : STD_LOGIC;
signal interconnect_S04_AXI_M00_AXI_RREADY : STD_LOGIC;
signal interconnect_S04_AXI_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M00_AXI_RUSER : STD_LOGIC_VECTOR ( 13 downto 0 );
signal interconnect_S04_AXI_M00_AXI_RVALID : STD_LOGIC;
signal interconnect_S04_AXI_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal interconnect_S04_AXI_M00_AXI_WLAST : STD_LOGIC;
signal interconnect_S04_AXI_M00_AXI_WREADY : STD_LOGIC;
signal interconnect_S04_AXI_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 63 downto 0 );
signal interconnect_S04_AXI_M00_AXI_WUSER : STD_LOGIC_VECTOR ( 13 downto 0 );
signal interconnect_S04_AXI_M00_AXI_WVALID : STD_LOGIC;
signal interconnect_S04_AXI_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal interconnect_S04_AXI_M01_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M01_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_S04_AXI_M01_AXI_ARID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M01_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_S04_AXI_M01_AXI_ARLOCK : STD_LOGIC;
signal interconnect_S04_AXI_M01_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_S04_AXI_M01_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_S04_AXI_M01_AXI_ARREADY : STD_LOGIC;
signal interconnect_S04_AXI_M01_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_S04_AXI_M01_AXI_ARUSER : STD_LOGIC_VECTOR ( 113 downto 0 );
signal interconnect_S04_AXI_M01_AXI_ARVALID : STD_LOGIC;
signal interconnect_S04_AXI_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal interconnect_S04_AXI_M01_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M01_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_S04_AXI_M01_AXI_AWID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M01_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_S04_AXI_M01_AXI_AWLOCK : STD_LOGIC;
signal interconnect_S04_AXI_M01_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_S04_AXI_M01_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_S04_AXI_M01_AXI_AWREADY : STD_LOGIC;
signal interconnect_S04_AXI_M01_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_S04_AXI_M01_AXI_AWUSER : STD_LOGIC_VECTOR ( 113 downto 0 );
signal interconnect_S04_AXI_M01_AXI_AWVALID : STD_LOGIC;
signal interconnect_S04_AXI_M01_AXI_BID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M01_AXI_BREADY : STD_LOGIC;
signal interconnect_S04_AXI_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M01_AXI_BUSER : STD_LOGIC_VECTOR ( 113 downto 0 );
signal interconnect_S04_AXI_M01_AXI_BVALID : STD_LOGIC;
signal interconnect_S04_AXI_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal interconnect_S04_AXI_M01_AXI_RID : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M01_AXI_RLAST : STD_LOGIC;
signal interconnect_S04_AXI_M01_AXI_RREADY : STD_LOGIC;
signal interconnect_S04_AXI_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_S04_AXI_M01_AXI_RUSER : STD_LOGIC_VECTOR ( 13 downto 0 );
signal interconnect_S04_AXI_M01_AXI_RVALID : STD_LOGIC;
signal interconnect_S04_AXI_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal interconnect_S04_AXI_M01_AXI_WLAST : STD_LOGIC;
signal interconnect_S04_AXI_M01_AXI_WREADY : STD_LOGIC;
signal interconnect_S04_AXI_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 63 downto 0 );
signal interconnect_S04_AXI_M01_AXI_WUSER : STD_LOGIC_VECTOR ( 13 downto 0 );
signal interconnect_S04_AXI_M01_AXI_WVALID : STD_LOGIC;
signal vip_M00_AXI_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal vip_M00_AXI_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_M00_AXI_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_M00_AXI_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal vip_M00_AXI_M_AXI_ARLOCK : STD_LOGIC;
signal vip_M00_AXI_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal vip_M00_AXI_M_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_M00_AXI_M_AXI_ARREADY : STD_LOGIC;
signal vip_M00_AXI_M_AXI_ARVALID : STD_LOGIC;
signal vip_M00_AXI_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal vip_M00_AXI_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_M00_AXI_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_M00_AXI_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal vip_M00_AXI_M_AXI_AWLOCK : STD_LOGIC;
signal vip_M00_AXI_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal vip_M00_AXI_M_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_M00_AXI_M_AXI_AWREADY : STD_LOGIC;
signal vip_M00_AXI_M_AXI_AWVALID : STD_LOGIC;
signal vip_M00_AXI_M_AXI_BREADY : STD_LOGIC;
signal vip_M00_AXI_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_M00_AXI_M_AXI_BVALID : STD_LOGIC;
signal vip_M00_AXI_M_AXI_RDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal vip_M00_AXI_M_AXI_RLAST : STD_LOGIC;
signal vip_M00_AXI_M_AXI_RREADY : STD_LOGIC;
signal vip_M00_AXI_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_M00_AXI_M_AXI_RVALID : STD_LOGIC;
signal vip_M00_AXI_M_AXI_WDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal vip_M00_AXI_M_AXI_WLAST : STD_LOGIC;
signal vip_M00_AXI_M_AXI_WREADY : STD_LOGIC;
signal vip_M00_AXI_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 63 downto 0 );
signal vip_M00_AXI_M_AXI_WVALID : STD_LOGIC;
signal vip_S01_AXI_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal vip_S01_AXI_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_S01_AXI_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S01_AXI_M_AXI_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S01_AXI_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal vip_S01_AXI_M_AXI_ARLOCK : STD_LOGIC;
signal vip_S01_AXI_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal vip_S01_AXI_M_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S01_AXI_M_AXI_ARREADY : STD_LOGIC;
signal vip_S01_AXI_M_AXI_ARVALID : STD_LOGIC;
signal vip_S01_AXI_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal vip_S01_AXI_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_S01_AXI_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S01_AXI_M_AXI_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S01_AXI_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal vip_S01_AXI_M_AXI_AWLOCK : STD_LOGIC;
signal vip_S01_AXI_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal vip_S01_AXI_M_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S01_AXI_M_AXI_AWREADY : STD_LOGIC;
signal vip_S01_AXI_M_AXI_AWVALID : STD_LOGIC;
signal vip_S01_AXI_M_AXI_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S01_AXI_M_AXI_BREADY : STD_LOGIC;
signal vip_S01_AXI_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_S01_AXI_M_AXI_BVALID : STD_LOGIC;
signal vip_S01_AXI_M_AXI_RDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal vip_S01_AXI_M_AXI_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S01_AXI_M_AXI_RLAST : STD_LOGIC;
signal vip_S01_AXI_M_AXI_RREADY : STD_LOGIC;
signal vip_S01_AXI_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_S01_AXI_M_AXI_RVALID : STD_LOGIC;
signal vip_S01_AXI_M_AXI_WDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal vip_S01_AXI_M_AXI_WLAST : STD_LOGIC;
signal vip_S01_AXI_M_AXI_WREADY : STD_LOGIC;
signal vip_S01_AXI_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 63 downto 0 );
signal vip_S01_AXI_M_AXI_WVALID : STD_LOGIC;
signal vip_S02_AXI_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal vip_S02_AXI_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_S02_AXI_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S02_AXI_M_AXI_ARID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S02_AXI_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal vip_S02_AXI_M_AXI_ARLOCK : STD_LOGIC;
signal vip_S02_AXI_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal vip_S02_AXI_M_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S02_AXI_M_AXI_ARREADY : STD_LOGIC;
signal vip_S02_AXI_M_AXI_ARVALID : STD_LOGIC;
signal vip_S02_AXI_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal vip_S02_AXI_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_S02_AXI_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S02_AXI_M_AXI_AWID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S02_AXI_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal vip_S02_AXI_M_AXI_AWLOCK : STD_LOGIC;
signal vip_S02_AXI_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal vip_S02_AXI_M_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S02_AXI_M_AXI_AWREADY : STD_LOGIC;
signal vip_S02_AXI_M_AXI_AWVALID : STD_LOGIC;
signal vip_S02_AXI_M_AXI_BID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S02_AXI_M_AXI_BREADY : STD_LOGIC;
signal vip_S02_AXI_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_S02_AXI_M_AXI_BVALID : STD_LOGIC;
signal vip_S02_AXI_M_AXI_RDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal vip_S02_AXI_M_AXI_RID : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S02_AXI_M_AXI_RLAST : STD_LOGIC;
signal vip_S02_AXI_M_AXI_RREADY : STD_LOGIC;
signal vip_S02_AXI_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_S02_AXI_M_AXI_RVALID : STD_LOGIC;
signal vip_S02_AXI_M_AXI_WDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal vip_S02_AXI_M_AXI_WLAST : STD_LOGIC;
signal vip_S02_AXI_M_AXI_WREADY : STD_LOGIC;
signal vip_S02_AXI_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 63 downto 0 );
signal vip_S02_AXI_M_AXI_WVALID : STD_LOGIC;
signal vip_S04_AXI_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal vip_S04_AXI_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S04_AXI_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal vip_S04_AXI_M_AXI_ARLOCK : STD_LOGIC;
signal vip_S04_AXI_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal vip_S04_AXI_M_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S04_AXI_M_AXI_ARREADY : STD_LOGIC;
signal vip_S04_AXI_M_AXI_ARVALID : STD_LOGIC;
signal vip_S04_AXI_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal vip_S04_AXI_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S04_AXI_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal vip_S04_AXI_M_AXI_AWLOCK : STD_LOGIC;
signal vip_S04_AXI_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal vip_S04_AXI_M_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S04_AXI_M_AXI_AWREADY : STD_LOGIC;
signal vip_S04_AXI_M_AXI_AWVALID : STD_LOGIC;
signal vip_S04_AXI_M_AXI_BREADY : STD_LOGIC;
signal vip_S04_AXI_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_S04_AXI_M_AXI_BVALID : STD_LOGIC;
signal vip_S04_AXI_M_AXI_RDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal vip_S04_AXI_M_AXI_RLAST : STD_LOGIC;
signal vip_S04_AXI_M_AXI_RREADY : STD_LOGIC;
signal vip_S04_AXI_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_S04_AXI_M_AXI_RVALID : STD_LOGIC;
signal vip_S04_AXI_M_AXI_WDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal vip_S04_AXI_M_AXI_WLAST : STD_LOGIC;
signal vip_S04_AXI_M_AXI_WREADY : STD_LOGIC;
signal vip_S04_AXI_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 63 downto 0 );
signal vip_S04_AXI_M_AXI_WVALID : STD_LOGIC;
signal vip_S05_AXI_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal vip_S05_AXI_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S05_AXI_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal vip_S05_AXI_M_AXI_ARLOCK : STD_LOGIC;
signal vip_S05_AXI_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal vip_S05_AXI_M_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S05_AXI_M_AXI_ARREADY : STD_LOGIC;
signal vip_S05_AXI_M_AXI_ARVALID : STD_LOGIC;
signal vip_S05_AXI_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 38 downto 0 );
signal vip_S05_AXI_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S05_AXI_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal vip_S05_AXI_M_AXI_AWLOCK : STD_LOGIC;
signal vip_S05_AXI_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal vip_S05_AXI_M_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_S05_AXI_M_AXI_AWREADY : STD_LOGIC;
signal vip_S05_AXI_M_AXI_AWVALID : STD_LOGIC;
signal vip_S05_AXI_M_AXI_BREADY : STD_LOGIC;
signal vip_S05_AXI_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_S05_AXI_M_AXI_BVALID : STD_LOGIC;
signal vip_S05_AXI_M_AXI_RDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal vip_S05_AXI_M_AXI_RLAST : STD_LOGIC;
signal vip_S05_AXI_M_AXI_RREADY : STD_LOGIC;
signal vip_S05_AXI_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_S05_AXI_M_AXI_RVALID : STD_LOGIC;
signal vip_S05_AXI_M_AXI_WDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal vip_S05_AXI_M_AXI_WLAST : STD_LOGIC;
signal vip_S05_AXI_M_AXI_WREADY : STD_LOGIC;
signal vip_S05_AXI_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 63 downto 0 );
signal vip_S05_AXI_M_AXI_WVALID : STD_LOGIC;
signal NLW_interconnect_ddr4_mem01_M00_AXI_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_interconnect_ddr4_mem01_M00_AXI_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_interconnect_m00_axi_mem00_M00_AXI_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_interconnect_m00_axi_mem00_M00_AXI_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_vip_s01_axi_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_vip_s01_axi_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_vip_s02_axi_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_vip_s02_axi_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_vip_s04_axi_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_vip_s04_axi_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_vip_s05_axi_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_vip_s05_axi_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of interconnect_ddr4_mem01 : label is "bd_e7f0,Vivado 2020.1";
attribute X_CORE_INFO of interconnect_m00_axi_mem00 : label is "bd_2b97,Vivado 2020.1";
attribute X_CORE_INFO of interconnect_s04_axi : label is "bd_8bbf,Vivado 2020.1";
attribute X_CORE_INFO of rs_m00_axi : label is "axi_register_slice_v2_1_21_axi_register_slice,Vivado 2020.1";
attribute X_CORE_INFO of vip_m00_axi : label is "axi_vip_v1_1_7_top,Vivado 2020.1";
attribute X_CORE_INFO of vip_s01_axi : label is "axi_vip_v1_1_7_top,Vivado 2020.1";
attribute X_CORE_INFO of vip_s02_axi : label is "axi_vip_v1_1_7_top,Vivado 2020.1";
attribute X_CORE_INFO of vip_s04_axi : label is "axi_vip_v1_1_7_top,Vivado 2020.1";
attribute X_CORE_INFO of vip_s05_axi : label is "axi_vip_v1_1_7_top,Vivado 2020.1";
begin
interconnect_ddr4_mem01: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_interconnect_DDR4_MEM01_0
port map (
M00_AXI_araddr(33 downto 0) => M00_AXI_araddr(33 downto 0),
M00_AXI_arburst(1 downto 0) => M00_AXI_arburst(1 downto 0),
M00_AXI_arcache(3 downto 0) => M00_AXI_arcache(3 downto 0),
M00_AXI_arlen(7 downto 0) => M00_AXI_arlen(7 downto 0),
M00_AXI_arlock(0) => M00_AXI_arlock(0),
M00_AXI_arprot(2 downto 0) => M00_AXI_arprot(2 downto 0),
M00_AXI_arqos(3 downto 0) => M00_AXI_arqos(3 downto 0),
M00_AXI_arready => S_AXI_arready,
M00_AXI_arsize(2 downto 0) => NLW_interconnect_ddr4_mem01_M00_AXI_arsize_UNCONNECTED(2 downto 0),
M00_AXI_arvalid => M00_AXI_arvalid,
M00_AXI_awaddr(33 downto 0) => M00_AXI_awaddr(33 downto 0),
M00_AXI_awburst(1 downto 0) => M00_AXI_awburst(1 downto 0),
M00_AXI_awcache(3 downto 0) => M00_AXI_awcache(3 downto 0),
M00_AXI_awlen(7 downto 0) => M00_AXI_awlen(7 downto 0),
M00_AXI_awlock(0) => M00_AXI_awlock(0),
M00_AXI_awprot(2 downto 0) => M00_AXI_awprot(2 downto 0),
M00_AXI_awqos(3 downto 0) => M00_AXI_awqos(3 downto 0),
M00_AXI_awready => S_AXI_awready,
M00_AXI_awsize(2 downto 0) => NLW_interconnect_ddr4_mem01_M00_AXI_awsize_UNCONNECTED(2 downto 0),
M00_AXI_awvalid => M00_AXI_awvalid,
M00_AXI_bready => M00_AXI_bready,
M00_AXI_bresp(1 downto 0) => S_AXI_bresp(1 downto 0),
M00_AXI_bvalid => S_AXI_bvalid,
M00_AXI_rdata(511 downto 0) => S_AXI_rdata(511 downto 0),
M00_AXI_rlast => S_AXI_rlast,
M00_AXI_rready => M00_AXI_rready,
M00_AXI_rresp(1 downto 0) => S_AXI_rresp(1 downto 0),
M00_AXI_rvalid => S_AXI_rvalid,
M00_AXI_wdata(511 downto 0) => M00_AXI_wdata(511 downto 0),
M00_AXI_wlast => M00_AXI_wlast,
M00_AXI_wready => S_AXI_wready,
M00_AXI_wstrb(63 downto 0) => M00_AXI_wstrb(63 downto 0),
M00_AXI_wvalid => M00_AXI_wvalid,
S00_AXI_araddr(38 downto 0) => vip_S02_AXI_M_AXI_ARADDR(38 downto 0),
S00_AXI_arburst(1 downto 0) => vip_S02_AXI_M_AXI_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => vip_S02_AXI_M_AXI_ARCACHE(3 downto 0),
S00_AXI_arid(3 downto 0) => vip_S02_AXI_M_AXI_ARID(3 downto 0),
S00_AXI_arlen(7 downto 0) => vip_S02_AXI_M_AXI_ARLEN(7 downto 0),
S00_AXI_arlock(0) => vip_S02_AXI_M_AXI_ARLOCK,
S00_AXI_arprot(2 downto 0) => vip_S02_AXI_M_AXI_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => vip_S02_AXI_M_AXI_ARQOS(3 downto 0),
S00_AXI_arready => vip_S02_AXI_M_AXI_ARREADY,
S00_AXI_arsize(2 downto 0) => B"110",
S00_AXI_arvalid => vip_S02_AXI_M_AXI_ARVALID,
S00_AXI_awaddr(38 downto 0) => vip_S02_AXI_M_AXI_AWADDR(38 downto 0),
S00_AXI_awburst(1 downto 0) => vip_S02_AXI_M_AXI_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => vip_S02_AXI_M_AXI_AWCACHE(3 downto 0),
S00_AXI_awid(3 downto 0) => vip_S02_AXI_M_AXI_AWID(3 downto 0),
S00_AXI_awlen(7 downto 0) => vip_S02_AXI_M_AXI_AWLEN(7 downto 0),
S00_AXI_awlock(0) => vip_S02_AXI_M_AXI_AWLOCK,
S00_AXI_awprot(2 downto 0) => vip_S02_AXI_M_AXI_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => vip_S02_AXI_M_AXI_AWQOS(3 downto 0),
S00_AXI_awready => vip_S02_AXI_M_AXI_AWREADY,
S00_AXI_awsize(2 downto 0) => B"110",
S00_AXI_awvalid => vip_S02_AXI_M_AXI_AWVALID,
S00_AXI_bid(3 downto 0) => vip_S02_AXI_M_AXI_BID(3 downto 0),
S00_AXI_bready => vip_S02_AXI_M_AXI_BREADY,
S00_AXI_bresp(1 downto 0) => vip_S02_AXI_M_AXI_BRESP(1 downto 0),
S00_AXI_bvalid => vip_S02_AXI_M_AXI_BVALID,
S00_AXI_rdata(511 downto 0) => vip_S02_AXI_M_AXI_RDATA(511 downto 0),
S00_AXI_rid(3 downto 0) => vip_S02_AXI_M_AXI_RID(3 downto 0),
S00_AXI_rlast => vip_S02_AXI_M_AXI_RLAST,
S00_AXI_rready => vip_S02_AXI_M_AXI_RREADY,
S00_AXI_rresp(1 downto 0) => vip_S02_AXI_M_AXI_RRESP(1 downto 0),
S00_AXI_rvalid => vip_S02_AXI_M_AXI_RVALID,
S00_AXI_wdata(511 downto 0) => vip_S02_AXI_M_AXI_WDATA(511 downto 0),
S00_AXI_wlast => vip_S02_AXI_M_AXI_WLAST,
S00_AXI_wready => vip_S02_AXI_M_AXI_WREADY,
S00_AXI_wstrb(63 downto 0) => vip_S02_AXI_M_AXI_WSTRB(63 downto 0),
S00_AXI_wvalid => vip_S02_AXI_M_AXI_WVALID,
S01_AXI_araddr(38 downto 0) => interconnect_S04_AXI_M00_AXI_ARADDR(38 downto 0),
S01_AXI_arburst(1 downto 0) => interconnect_S04_AXI_M00_AXI_ARBURST(1 downto 0),
S01_AXI_arcache(3 downto 0) => interconnect_S04_AXI_M00_AXI_ARCACHE(3 downto 0),
S01_AXI_arid(1 downto 0) => interconnect_S04_AXI_M00_AXI_ARID(1 downto 0),
S01_AXI_arlen(7 downto 0) => interconnect_S04_AXI_M00_AXI_ARLEN(7 downto 0),
S01_AXI_arlock(0) => interconnect_S04_AXI_M00_AXI_ARLOCK,
S01_AXI_arprot(2 downto 0) => interconnect_S04_AXI_M00_AXI_ARPROT(2 downto 0),
S01_AXI_arqos(3 downto 0) => interconnect_S04_AXI_M00_AXI_ARQOS(3 downto 0),
S01_AXI_arready => interconnect_S04_AXI_M00_AXI_ARREADY,
S01_AXI_arsize(2 downto 0) => interconnect_S04_AXI_M00_AXI_ARSIZE(2 downto 0),
S01_AXI_aruser(113 downto 0) => interconnect_S04_AXI_M00_AXI_ARUSER(113 downto 0),
S01_AXI_arvalid => interconnect_S04_AXI_M00_AXI_ARVALID,
S01_AXI_awaddr(38 downto 0) => interconnect_S04_AXI_M00_AXI_AWADDR(38 downto 0),
S01_AXI_awburst(1 downto 0) => interconnect_S04_AXI_M00_AXI_AWBURST(1 downto 0),
S01_AXI_awcache(3 downto 0) => interconnect_S04_AXI_M00_AXI_AWCACHE(3 downto 0),
S01_AXI_awid(1 downto 0) => interconnect_S04_AXI_M00_AXI_AWID(1 downto 0),
S01_AXI_awlen(7 downto 0) => interconnect_S04_AXI_M00_AXI_AWLEN(7 downto 0),
S01_AXI_awlock(0) => interconnect_S04_AXI_M00_AXI_AWLOCK,
S01_AXI_awprot(2 downto 0) => interconnect_S04_AXI_M00_AXI_AWPROT(2 downto 0),
S01_AXI_awqos(3 downto 0) => interconnect_S04_AXI_M00_AXI_AWQOS(3 downto 0),
S01_AXI_awready => interconnect_S04_AXI_M00_AXI_AWREADY,
S01_AXI_awsize(2 downto 0) => interconnect_S04_AXI_M00_AXI_AWSIZE(2 downto 0),
S01_AXI_awuser(113 downto 0) => interconnect_S04_AXI_M00_AXI_AWUSER(113 downto 0),
S01_AXI_awvalid => interconnect_S04_AXI_M00_AXI_AWVALID,
S01_AXI_bid(1 downto 0) => interconnect_S04_AXI_M00_AXI_BID(1 downto 0),
S01_AXI_bready => interconnect_S04_AXI_M00_AXI_BREADY,
S01_AXI_bresp(1 downto 0) => interconnect_S04_AXI_M00_AXI_BRESP(1 downto 0),
S01_AXI_buser(113 downto 0) => interconnect_S04_AXI_M00_AXI_BUSER(113 downto 0),
S01_AXI_bvalid => interconnect_S04_AXI_M00_AXI_BVALID,
S01_AXI_rdata(511 downto 0) => interconnect_S04_AXI_M00_AXI_RDATA(511 downto 0),
S01_AXI_rid(1 downto 0) => interconnect_S04_AXI_M00_AXI_RID(1 downto 0),
S01_AXI_rlast => interconnect_S04_AXI_M00_AXI_RLAST,
S01_AXI_rready => interconnect_S04_AXI_M00_AXI_RREADY,
S01_AXI_rresp(1 downto 0) => interconnect_S04_AXI_M00_AXI_RRESP(1 downto 0),
S01_AXI_ruser(13 downto 0) => interconnect_S04_AXI_M00_AXI_RUSER(13 downto 0),
S01_AXI_rvalid => interconnect_S04_AXI_M00_AXI_RVALID,
S01_AXI_wdata(511 downto 0) => interconnect_S04_AXI_M00_AXI_WDATA(511 downto 0),
S01_AXI_wlast => interconnect_S04_AXI_M00_AXI_WLAST,
S01_AXI_wready => interconnect_S04_AXI_M00_AXI_WREADY,
S01_AXI_wstrb(63 downto 0) => interconnect_S04_AXI_M00_AXI_WSTRB(63 downto 0),
S01_AXI_wuser(13 downto 0) => interconnect_S04_AXI_M00_AXI_WUSER(13 downto 0),
S01_AXI_wvalid => interconnect_S04_AXI_M00_AXI_WVALID,
aclk => ddr4_mem01_ui_clk,
aclk1 => aclk,
aresetn => interconnect_aresetn(0)
);
interconnect_m00_axi_mem00: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_interconnect_M00_AXI_MEM00_0
port map (
M00_AXI_araddr(38 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_ARADDR(38 downto 0),
M00_AXI_arburst(1 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arlen(7 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_ARLEN(7 downto 0),
M00_AXI_arlock(0) => interconnect_M00_AXI_MEM00_M00_AXI_ARLOCK,
M00_AXI_arprot(2 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => interconnect_M00_AXI_MEM00_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => NLW_interconnect_m00_axi_mem00_M00_AXI_arsize_UNCONNECTED(2 downto 0),
M00_AXI_arvalid => interconnect_M00_AXI_MEM00_M00_AXI_ARVALID,
M00_AXI_awaddr(38 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_AWADDR(38 downto 0),
M00_AXI_awburst(1 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awlen(7 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_AWLEN(7 downto 0),
M00_AXI_awlock(0) => interconnect_M00_AXI_MEM00_M00_AXI_AWLOCK,
M00_AXI_awprot(2 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => interconnect_M00_AXI_MEM00_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => NLW_interconnect_m00_axi_mem00_M00_AXI_awsize_UNCONNECTED(2 downto 0),
M00_AXI_awvalid => interconnect_M00_AXI_MEM00_M00_AXI_AWVALID,
M00_AXI_bready => interconnect_M00_AXI_MEM00_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => interconnect_M00_AXI_MEM00_M00_AXI_BVALID,
M00_AXI_rdata(511 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_RDATA(511 downto 0),
M00_AXI_rlast => interconnect_M00_AXI_MEM00_M00_AXI_RLAST,
M00_AXI_rready => interconnect_M00_AXI_MEM00_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => interconnect_M00_AXI_MEM00_M00_AXI_RVALID,
M00_AXI_wdata(511 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_WDATA(511 downto 0),
M00_AXI_wlast => interconnect_M00_AXI_MEM00_M00_AXI_WLAST,
M00_AXI_wready => interconnect_M00_AXI_MEM00_M00_AXI_WREADY,
M00_AXI_wstrb(63 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_WSTRB(63 downto 0),
M00_AXI_wvalid => interconnect_M00_AXI_MEM00_M00_AXI_WVALID,
S00_AXI_araddr(38 downto 0) => vip_S01_AXI_M_AXI_ARADDR(38 downto 0),
S00_AXI_arburst(1 downto 0) => vip_S01_AXI_M_AXI_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => vip_S01_AXI_M_AXI_ARCACHE(3 downto 0),
S00_AXI_arid(3 downto 0) => vip_S01_AXI_M_AXI_ARID(3 downto 0),
S00_AXI_arlen(7 downto 0) => vip_S01_AXI_M_AXI_ARLEN(7 downto 0),
S00_AXI_arlock(0) => vip_S01_AXI_M_AXI_ARLOCK,
S00_AXI_arprot(2 downto 0) => vip_S01_AXI_M_AXI_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => vip_S01_AXI_M_AXI_ARQOS(3 downto 0),
S00_AXI_arready => vip_S01_AXI_M_AXI_ARREADY,
S00_AXI_arsize(2 downto 0) => B"110",
S00_AXI_arvalid => vip_S01_AXI_M_AXI_ARVALID,
S00_AXI_awaddr(38 downto 0) => vip_S01_AXI_M_AXI_AWADDR(38 downto 0),
S00_AXI_awburst(1 downto 0) => vip_S01_AXI_M_AXI_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => vip_S01_AXI_M_AXI_AWCACHE(3 downto 0),
S00_AXI_awid(3 downto 0) => vip_S01_AXI_M_AXI_AWID(3 downto 0),
S00_AXI_awlen(7 downto 0) => vip_S01_AXI_M_AXI_AWLEN(7 downto 0),
S00_AXI_awlock(0) => vip_S01_AXI_M_AXI_AWLOCK,
S00_AXI_awprot(2 downto 0) => vip_S01_AXI_M_AXI_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => vip_S01_AXI_M_AXI_AWQOS(3 downto 0),
S00_AXI_awready => vip_S01_AXI_M_AXI_AWREADY,
S00_AXI_awsize(2 downto 0) => B"110",
S00_AXI_awvalid => vip_S01_AXI_M_AXI_AWVALID,
S00_AXI_bid(3 downto 0) => vip_S01_AXI_M_AXI_BID(3 downto 0),
S00_AXI_bready => vip_S01_AXI_M_AXI_BREADY,
S00_AXI_bresp(1 downto 0) => vip_S01_AXI_M_AXI_BRESP(1 downto 0),
S00_AXI_bvalid => vip_S01_AXI_M_AXI_BVALID,
S00_AXI_rdata(511 downto 0) => vip_S01_AXI_M_AXI_RDATA(511 downto 0),
S00_AXI_rid(3 downto 0) => vip_S01_AXI_M_AXI_RID(3 downto 0),
S00_AXI_rlast => vip_S01_AXI_M_AXI_RLAST,
S00_AXI_rready => vip_S01_AXI_M_AXI_RREADY,
S00_AXI_rresp(1 downto 0) => vip_S01_AXI_M_AXI_RRESP(1 downto 0),
S00_AXI_rvalid => vip_S01_AXI_M_AXI_RVALID,
S00_AXI_wdata(511 downto 0) => vip_S01_AXI_M_AXI_WDATA(511 downto 0),
S00_AXI_wlast => vip_S01_AXI_M_AXI_WLAST,
S00_AXI_wready => vip_S01_AXI_M_AXI_WREADY,
S00_AXI_wstrb(63 downto 0) => vip_S01_AXI_M_AXI_WSTRB(63 downto 0),
S00_AXI_wvalid => vip_S01_AXI_M_AXI_WVALID,
S01_AXI_araddr(38 downto 0) => vip_S05_AXI_M_AXI_ARADDR(38 downto 0),
S01_AXI_arburst(1 downto 0) => B"01",
S01_AXI_arcache(3 downto 0) => vip_S05_AXI_M_AXI_ARCACHE(3 downto 0),
S01_AXI_arlen(7 downto 0) => vip_S05_AXI_M_AXI_ARLEN(7 downto 0),
S01_AXI_arlock(0) => vip_S05_AXI_M_AXI_ARLOCK,
S01_AXI_arprot(2 downto 0) => vip_S05_AXI_M_AXI_ARPROT(2 downto 0),
S01_AXI_arqos(3 downto 0) => vip_S05_AXI_M_AXI_ARQOS(3 downto 0),
S01_AXI_arready => vip_S05_AXI_M_AXI_ARREADY,
S01_AXI_arsize(2 downto 0) => B"110",
S01_AXI_arvalid => vip_S05_AXI_M_AXI_ARVALID,
S01_AXI_awaddr(38 downto 0) => vip_S05_AXI_M_AXI_AWADDR(38 downto 0),
S01_AXI_awburst(1 downto 0) => B"01",
S01_AXI_awcache(3 downto 0) => vip_S05_AXI_M_AXI_AWCACHE(3 downto 0),
S01_AXI_awlen(7 downto 0) => vip_S05_AXI_M_AXI_AWLEN(7 downto 0),
S01_AXI_awlock(0) => vip_S05_AXI_M_AXI_AWLOCK,
S01_AXI_awprot(2 downto 0) => vip_S05_AXI_M_AXI_AWPROT(2 downto 0),
S01_AXI_awqos(3 downto 0) => vip_S05_AXI_M_AXI_AWQOS(3 downto 0),
S01_AXI_awready => vip_S05_AXI_M_AXI_AWREADY,
S01_AXI_awsize(2 downto 0) => B"110",
S01_AXI_awvalid => vip_S05_AXI_M_AXI_AWVALID,
S01_AXI_bready => vip_S05_AXI_M_AXI_BREADY,
S01_AXI_bresp(1 downto 0) => vip_S05_AXI_M_AXI_BRESP(1 downto 0),
S01_AXI_bvalid => vip_S05_AXI_M_AXI_BVALID,
S01_AXI_rdata(511 downto 0) => vip_S05_AXI_M_AXI_RDATA(511 downto 0),
S01_AXI_rlast => vip_S05_AXI_M_AXI_RLAST,
S01_AXI_rready => vip_S05_AXI_M_AXI_RREADY,
S01_AXI_rresp(1 downto 0) => vip_S05_AXI_M_AXI_RRESP(1 downto 0),
S01_AXI_rvalid => vip_S05_AXI_M_AXI_RVALID,
S01_AXI_wdata(511 downto 0) => vip_S05_AXI_M_AXI_WDATA(511 downto 0),
S01_AXI_wlast => vip_S05_AXI_M_AXI_WLAST,
S01_AXI_wready => vip_S05_AXI_M_AXI_WREADY,
S01_AXI_wstrb(63 downto 0) => vip_S05_AXI_M_AXI_WSTRB(63 downto 0),
S01_AXI_wvalid => vip_S05_AXI_M_AXI_WVALID,
S02_AXI_araddr(38 downto 0) => interconnect_S04_AXI_M01_AXI_ARADDR(38 downto 0),
S02_AXI_arburst(1 downto 0) => interconnect_S04_AXI_M01_AXI_ARBURST(1 downto 0),
S02_AXI_arcache(3 downto 0) => interconnect_S04_AXI_M01_AXI_ARCACHE(3 downto 0),
S02_AXI_arid(1 downto 0) => interconnect_S04_AXI_M01_AXI_ARID(1 downto 0),
S02_AXI_arlen(7 downto 0) => interconnect_S04_AXI_M01_AXI_ARLEN(7 downto 0),
S02_AXI_arlock(0) => interconnect_S04_AXI_M01_AXI_ARLOCK,
S02_AXI_arprot(2 downto 0) => interconnect_S04_AXI_M01_AXI_ARPROT(2 downto 0),
S02_AXI_arqos(3 downto 0) => interconnect_S04_AXI_M01_AXI_ARQOS(3 downto 0),
S02_AXI_arready => interconnect_S04_AXI_M01_AXI_ARREADY,
S02_AXI_arsize(2 downto 0) => interconnect_S04_AXI_M01_AXI_ARSIZE(2 downto 0),
S02_AXI_aruser(113 downto 0) => interconnect_S04_AXI_M01_AXI_ARUSER(113 downto 0),
S02_AXI_arvalid => interconnect_S04_AXI_M01_AXI_ARVALID,
S02_AXI_awaddr(38 downto 0) => interconnect_S04_AXI_M01_AXI_AWADDR(38 downto 0),
S02_AXI_awburst(1 downto 0) => interconnect_S04_AXI_M01_AXI_AWBURST(1 downto 0),
S02_AXI_awcache(3 downto 0) => interconnect_S04_AXI_M01_AXI_AWCACHE(3 downto 0),
S02_AXI_awid(1 downto 0) => interconnect_S04_AXI_M01_AXI_AWID(1 downto 0),
S02_AXI_awlen(7 downto 0) => interconnect_S04_AXI_M01_AXI_AWLEN(7 downto 0),
S02_AXI_awlock(0) => interconnect_S04_AXI_M01_AXI_AWLOCK,
S02_AXI_awprot(2 downto 0) => interconnect_S04_AXI_M01_AXI_AWPROT(2 downto 0),
S02_AXI_awqos(3 downto 0) => interconnect_S04_AXI_M01_AXI_AWQOS(3 downto 0),
S02_AXI_awready => interconnect_S04_AXI_M01_AXI_AWREADY,
S02_AXI_awsize(2 downto 0) => interconnect_S04_AXI_M01_AXI_AWSIZE(2 downto 0),
S02_AXI_awuser(113 downto 0) => interconnect_S04_AXI_M01_AXI_AWUSER(113 downto 0),
S02_AXI_awvalid => interconnect_S04_AXI_M01_AXI_AWVALID,
S02_AXI_bid(1 downto 0) => interconnect_S04_AXI_M01_AXI_BID(1 downto 0),
S02_AXI_bready => interconnect_S04_AXI_M01_AXI_BREADY,
S02_AXI_bresp(1 downto 0) => interconnect_S04_AXI_M01_AXI_BRESP(1 downto 0),
S02_AXI_buser(113 downto 0) => interconnect_S04_AXI_M01_AXI_BUSER(113 downto 0),
S02_AXI_bvalid => interconnect_S04_AXI_M01_AXI_BVALID,
S02_AXI_rdata(511 downto 0) => interconnect_S04_AXI_M01_AXI_RDATA(511 downto 0),
S02_AXI_rid(1 downto 0) => interconnect_S04_AXI_M01_AXI_RID(1 downto 0),
S02_AXI_rlast => interconnect_S04_AXI_M01_AXI_RLAST,
S02_AXI_rready => interconnect_S04_AXI_M01_AXI_RREADY,
S02_AXI_rresp(1 downto 0) => interconnect_S04_AXI_M01_AXI_RRESP(1 downto 0),
S02_AXI_ruser(13 downto 0) => interconnect_S04_AXI_M01_AXI_RUSER(13 downto 0),
S02_AXI_rvalid => interconnect_S04_AXI_M01_AXI_RVALID,
S02_AXI_wdata(511 downto 0) => interconnect_S04_AXI_M01_AXI_WDATA(511 downto 0),
S02_AXI_wlast => interconnect_S04_AXI_M01_AXI_WLAST,
S02_AXI_wready => interconnect_S04_AXI_M01_AXI_WREADY,
S02_AXI_wstrb(63 downto 0) => interconnect_S04_AXI_M01_AXI_WSTRB(63 downto 0),
S02_AXI_wuser(13 downto 0) => interconnect_S04_AXI_M01_AXI_WUSER(13 downto 0),
S02_AXI_wvalid => interconnect_S04_AXI_M01_AXI_WVALID,
aclk => aclk2,
aclk1 => aclk,
aresetn => interconnect_aresetn1(0)
);
interconnect_s04_axi: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_interconnect_S04_AXI_0
port map (
M00_AXI_araddr(38 downto 0) => interconnect_S04_AXI_M00_AXI_ARADDR(38 downto 0),
M00_AXI_arburst(1 downto 0) => interconnect_S04_AXI_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => interconnect_S04_AXI_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(1 downto 0) => interconnect_S04_AXI_M00_AXI_ARID(1 downto 0),
M00_AXI_arlen(7 downto 0) => interconnect_S04_AXI_M00_AXI_ARLEN(7 downto 0),
M00_AXI_arlock(0) => interconnect_S04_AXI_M00_AXI_ARLOCK,
M00_AXI_arprot(2 downto 0) => interconnect_S04_AXI_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => interconnect_S04_AXI_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => interconnect_S04_AXI_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => interconnect_S04_AXI_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_aruser(113 downto 0) => interconnect_S04_AXI_M00_AXI_ARUSER(113 downto 0),
M00_AXI_arvalid => interconnect_S04_AXI_M00_AXI_ARVALID,
M00_AXI_awaddr(38 downto 0) => interconnect_S04_AXI_M00_AXI_AWADDR(38 downto 0),
M00_AXI_awburst(1 downto 0) => interconnect_S04_AXI_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => interconnect_S04_AXI_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(1 downto 0) => interconnect_S04_AXI_M00_AXI_AWID(1 downto 0),
M00_AXI_awlen(7 downto 0) => interconnect_S04_AXI_M00_AXI_AWLEN(7 downto 0),
M00_AXI_awlock(0) => interconnect_S04_AXI_M00_AXI_AWLOCK,
M00_AXI_awprot(2 downto 0) => interconnect_S04_AXI_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => interconnect_S04_AXI_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => interconnect_S04_AXI_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => interconnect_S04_AXI_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awuser(113 downto 0) => interconnect_S04_AXI_M00_AXI_AWUSER(113 downto 0),
M00_AXI_awvalid => interconnect_S04_AXI_M00_AXI_AWVALID,
M00_AXI_bid(1 downto 0) => interconnect_S04_AXI_M00_AXI_BID(1 downto 0),
M00_AXI_bready => interconnect_S04_AXI_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => interconnect_S04_AXI_M00_AXI_BRESP(1 downto 0),
M00_AXI_buser(113 downto 0) => interconnect_S04_AXI_M00_AXI_BUSER(113 downto 0),
M00_AXI_bvalid => interconnect_S04_AXI_M00_AXI_BVALID,
M00_AXI_rdata(511 downto 0) => interconnect_S04_AXI_M00_AXI_RDATA(511 downto 0),
M00_AXI_rid(1 downto 0) => interconnect_S04_AXI_M00_AXI_RID(1 downto 0),
M00_AXI_rlast => interconnect_S04_AXI_M00_AXI_RLAST,
M00_AXI_rready => interconnect_S04_AXI_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => interconnect_S04_AXI_M00_AXI_RRESP(1 downto 0),
M00_AXI_ruser(13 downto 0) => interconnect_S04_AXI_M00_AXI_RUSER(13 downto 0),
M00_AXI_rvalid => interconnect_S04_AXI_M00_AXI_RVALID,
M00_AXI_wdata(511 downto 0) => interconnect_S04_AXI_M00_AXI_WDATA(511 downto 0),
M00_AXI_wlast => interconnect_S04_AXI_M00_AXI_WLAST,
M00_AXI_wready => interconnect_S04_AXI_M00_AXI_WREADY,
M00_AXI_wstrb(63 downto 0) => interconnect_S04_AXI_M00_AXI_WSTRB(63 downto 0),
M00_AXI_wuser(13 downto 0) => interconnect_S04_AXI_M00_AXI_WUSER(13 downto 0),
M00_AXI_wvalid => interconnect_S04_AXI_M00_AXI_WVALID,
M01_AXI_araddr(38 downto 0) => interconnect_S04_AXI_M01_AXI_ARADDR(38 downto 0),
M01_AXI_arburst(1 downto 0) => interconnect_S04_AXI_M01_AXI_ARBURST(1 downto 0),
M01_AXI_arcache(3 downto 0) => interconnect_S04_AXI_M01_AXI_ARCACHE(3 downto 0),
M01_AXI_arid(1 downto 0) => interconnect_S04_AXI_M01_AXI_ARID(1 downto 0),
M01_AXI_arlen(7 downto 0) => interconnect_S04_AXI_M01_AXI_ARLEN(7 downto 0),
M01_AXI_arlock(0) => interconnect_S04_AXI_M01_AXI_ARLOCK,
M01_AXI_arprot(2 downto 0) => interconnect_S04_AXI_M01_AXI_ARPROT(2 downto 0),
M01_AXI_arqos(3 downto 0) => interconnect_S04_AXI_M01_AXI_ARQOS(3 downto 0),
M01_AXI_arready => interconnect_S04_AXI_M01_AXI_ARREADY,
M01_AXI_arsize(2 downto 0) => interconnect_S04_AXI_M01_AXI_ARSIZE(2 downto 0),
M01_AXI_aruser(113 downto 0) => interconnect_S04_AXI_M01_AXI_ARUSER(113 downto 0),
M01_AXI_arvalid => interconnect_S04_AXI_M01_AXI_ARVALID,
M01_AXI_awaddr(38 downto 0) => interconnect_S04_AXI_M01_AXI_AWADDR(38 downto 0),
M01_AXI_awburst(1 downto 0) => interconnect_S04_AXI_M01_AXI_AWBURST(1 downto 0),
M01_AXI_awcache(3 downto 0) => interconnect_S04_AXI_M01_AXI_AWCACHE(3 downto 0),
M01_AXI_awid(1 downto 0) => interconnect_S04_AXI_M01_AXI_AWID(1 downto 0),
M01_AXI_awlen(7 downto 0) => interconnect_S04_AXI_M01_AXI_AWLEN(7 downto 0),
M01_AXI_awlock(0) => interconnect_S04_AXI_M01_AXI_AWLOCK,
M01_AXI_awprot(2 downto 0) => interconnect_S04_AXI_M01_AXI_AWPROT(2 downto 0),
M01_AXI_awqos(3 downto 0) => interconnect_S04_AXI_M01_AXI_AWQOS(3 downto 0),
M01_AXI_awready => interconnect_S04_AXI_M01_AXI_AWREADY,
M01_AXI_awsize(2 downto 0) => interconnect_S04_AXI_M01_AXI_AWSIZE(2 downto 0),
M01_AXI_awuser(113 downto 0) => interconnect_S04_AXI_M01_AXI_AWUSER(113 downto 0),
M01_AXI_awvalid => interconnect_S04_AXI_M01_AXI_AWVALID,
M01_AXI_bid(1 downto 0) => interconnect_S04_AXI_M01_AXI_BID(1 downto 0),
M01_AXI_bready => interconnect_S04_AXI_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => interconnect_S04_AXI_M01_AXI_BRESP(1 downto 0),
M01_AXI_buser(113 downto 0) => interconnect_S04_AXI_M01_AXI_BUSER(113 downto 0),
M01_AXI_bvalid => interconnect_S04_AXI_M01_AXI_BVALID,
M01_AXI_rdata(511 downto 0) => interconnect_S04_AXI_M01_AXI_RDATA(511 downto 0),
M01_AXI_rid(1 downto 0) => interconnect_S04_AXI_M01_AXI_RID(1 downto 0),
M01_AXI_rlast => interconnect_S04_AXI_M01_AXI_RLAST,
M01_AXI_rready => interconnect_S04_AXI_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => interconnect_S04_AXI_M01_AXI_RRESP(1 downto 0),
M01_AXI_ruser(13 downto 0) => interconnect_S04_AXI_M01_AXI_RUSER(13 downto 0),
M01_AXI_rvalid => interconnect_S04_AXI_M01_AXI_RVALID,
M01_AXI_wdata(511 downto 0) => interconnect_S04_AXI_M01_AXI_WDATA(511 downto 0),
M01_AXI_wlast => interconnect_S04_AXI_M01_AXI_WLAST,
M01_AXI_wready => interconnect_S04_AXI_M01_AXI_WREADY,
M01_AXI_wstrb(63 downto 0) => interconnect_S04_AXI_M01_AXI_WSTRB(63 downto 0),
M01_AXI_wuser(13 downto 0) => interconnect_S04_AXI_M01_AXI_WUSER(13 downto 0),
M01_AXI_wvalid => interconnect_S04_AXI_M01_AXI_WVALID,
S00_AXI_araddr(38 downto 0) => vip_S04_AXI_M_AXI_ARADDR(38 downto 0),
S00_AXI_arburst(1 downto 0) => B"01",
S00_AXI_arcache(3 downto 0) => vip_S04_AXI_M_AXI_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => vip_S04_AXI_M_AXI_ARLEN(7 downto 0),
S00_AXI_arlock(0) => vip_S04_AXI_M_AXI_ARLOCK,
S00_AXI_arprot(2 downto 0) => vip_S04_AXI_M_AXI_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => vip_S04_AXI_M_AXI_ARQOS(3 downto 0),
S00_AXI_arready => vip_S04_AXI_M_AXI_ARREADY,
S00_AXI_arsize(2 downto 0) => B"110",
S00_AXI_arvalid => vip_S04_AXI_M_AXI_ARVALID,
S00_AXI_awaddr(38 downto 0) => vip_S04_AXI_M_AXI_AWADDR(38 downto 0),
S00_AXI_awburst(1 downto 0) => B"01",
S00_AXI_awcache(3 downto 0) => vip_S04_AXI_M_AXI_AWCACHE(3 downto 0),
S00_AXI_awlen(7 downto 0) => vip_S04_AXI_M_AXI_AWLEN(7 downto 0),
S00_AXI_awlock(0) => vip_S04_AXI_M_AXI_AWLOCK,
S00_AXI_awprot(2 downto 0) => vip_S04_AXI_M_AXI_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => vip_S04_AXI_M_AXI_AWQOS(3 downto 0),
S00_AXI_awready => vip_S04_AXI_M_AXI_AWREADY,
S00_AXI_awsize(2 downto 0) => B"110",
S00_AXI_awvalid => vip_S04_AXI_M_AXI_AWVALID,
S00_AXI_bready => vip_S04_AXI_M_AXI_BREADY,
S00_AXI_bresp(1 downto 0) => vip_S04_AXI_M_AXI_BRESP(1 downto 0),
S00_AXI_bvalid => vip_S04_AXI_M_AXI_BVALID,
S00_AXI_rdata(511 downto 0) => vip_S04_AXI_M_AXI_RDATA(511 downto 0),
S00_AXI_rlast => vip_S04_AXI_M_AXI_RLAST,
S00_AXI_rready => vip_S04_AXI_M_AXI_RREADY,
S00_AXI_rresp(1 downto 0) => vip_S04_AXI_M_AXI_RRESP(1 downto 0),
S00_AXI_rvalid => vip_S04_AXI_M_AXI_RVALID,
S00_AXI_wdata(511 downto 0) => vip_S04_AXI_M_AXI_WDATA(511 downto 0),
S00_AXI_wlast => vip_S04_AXI_M_AXI_WLAST,
S00_AXI_wready => vip_S04_AXI_M_AXI_WREADY,
S00_AXI_wstrb(63 downto 0) => vip_S04_AXI_M_AXI_WSTRB(63 downto 0),
S00_AXI_wvalid => vip_S04_AXI_M_AXI_WVALID,
aclk => aclk,
aresetn => interconnect_aresetn(0)
);
rs_m00_axi: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_rs_M00_AXI_0
port map (
aclk => aclk2,
aresetn => interconnect_aresetn1(0),
m_axi_araddr(38 downto 0) => \bbstub_m_axi_araddr[38]\(38 downto 0),
m_axi_arburst(1 downto 0) => \bbstub_m_axi_arburst[1]\(1 downto 0),
m_axi_arcache(3 downto 0) => \bbstub_m_axi_arcache[3]\(3 downto 0),
m_axi_arlen(7 downto 0) => \bbstub_m_axi_arlen[7]\(7 downto 0),
m_axi_arlock(0) => \bbstub_m_axi_arlock[0]\(0),
m_axi_arprot(2 downto 0) => \bbstub_m_axi_arprot[2]\(2 downto 0),
m_axi_arqos(3 downto 0) => \bbstub_m_axi_arqos[3]\(3 downto 0),
m_axi_arready => M00_AXI_arready,
m_axi_arregion(3 downto 0) => M00_AXI_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => M00_AXI_arsize(2 downto 0),
m_axi_arvalid => bbstub_m_axi_arvalid,
m_axi_awaddr(38 downto 0) => \bbstub_m_axi_awaddr[38]\(38 downto 0),
m_axi_awburst(1 downto 0) => \bbstub_m_axi_awburst[1]\(1 downto 0),
m_axi_awcache(3 downto 0) => \bbstub_m_axi_awcache[3]\(3 downto 0),
m_axi_awlen(7 downto 0) => \bbstub_m_axi_awlen[7]\(7 downto 0),
m_axi_awlock(0) => \bbstub_m_axi_awlock[0]\(0),
m_axi_awprot(2 downto 0) => \bbstub_m_axi_awprot[2]\(2 downto 0),
m_axi_awqos(3 downto 0) => \bbstub_m_axi_awqos[3]\(3 downto 0),
m_axi_awready => M00_AXI_awready,
m_axi_awregion(3 downto 0) => M00_AXI_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => M00_AXI_awsize(2 downto 0),
m_axi_awvalid => bbstub_m_axi_awvalid,
m_axi_bready => bbstub_m_axi_bready,
m_axi_bresp(1 downto 0) => M00_AXI_bresp(1 downto 0),
m_axi_bvalid => M00_AXI_bvalid,
m_axi_rdata(511 downto 0) => M00_AXI_rdata(511 downto 0),
m_axi_rlast => M00_AXI_rlast,
m_axi_rready => bbstub_m_axi_rready,
m_axi_rresp(1 downto 0) => M00_AXI_rresp(1 downto 0),
m_axi_rvalid => M00_AXI_rvalid,
m_axi_wdata(511 downto 0) => \bbstub_m_axi_wdata[511]\(511 downto 0),
m_axi_wlast => bbstub_m_axi_wlast,
m_axi_wready => M00_AXI_wready,
m_axi_wstrb(63 downto 0) => \bbstub_m_axi_wstrb[63]\(63 downto 0),
m_axi_wvalid => bbstub_m_axi_wvalid,
s_axi_araddr(38 downto 0) => vip_M00_AXI_M_AXI_ARADDR(38 downto 0),
s_axi_arburst(1 downto 0) => vip_M00_AXI_M_AXI_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => vip_M00_AXI_M_AXI_ARCACHE(3 downto 0),
s_axi_arlen(7 downto 0) => vip_M00_AXI_M_AXI_ARLEN(7 downto 0),
s_axi_arlock(0) => vip_M00_AXI_M_AXI_ARLOCK,
s_axi_arprot(2 downto 0) => vip_M00_AXI_M_AXI_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => vip_M00_AXI_M_AXI_ARQOS(3 downto 0),
s_axi_arready => vip_M00_AXI_M_AXI_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"110",
s_axi_arvalid => vip_M00_AXI_M_AXI_ARVALID,
s_axi_awaddr(38 downto 0) => vip_M00_AXI_M_AXI_AWADDR(38 downto 0),
s_axi_awburst(1 downto 0) => vip_M00_AXI_M_AXI_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => vip_M00_AXI_M_AXI_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => vip_M00_AXI_M_AXI_AWLEN(7 downto 0),
s_axi_awlock(0) => vip_M00_AXI_M_AXI_AWLOCK,
s_axi_awprot(2 downto 0) => vip_M00_AXI_M_AXI_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => vip_M00_AXI_M_AXI_AWQOS(3 downto 0),
s_axi_awready => vip_M00_AXI_M_AXI_AWREADY,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"110",
s_axi_awvalid => vip_M00_AXI_M_AXI_AWVALID,
s_axi_bready => vip_M00_AXI_M_AXI_BREADY,
s_axi_bresp(1 downto 0) => vip_M00_AXI_M_AXI_BRESP(1 downto 0),
s_axi_bvalid => vip_M00_AXI_M_AXI_BVALID,
s_axi_rdata(511 downto 0) => vip_M00_AXI_M_AXI_RDATA(511 downto 0),
s_axi_rlast => vip_M00_AXI_M_AXI_RLAST,
s_axi_rready => vip_M00_AXI_M_AXI_RREADY,
s_axi_rresp(1 downto 0) => vip_M00_AXI_M_AXI_RRESP(1 downto 0),
s_axi_rvalid => vip_M00_AXI_M_AXI_RVALID,
s_axi_wdata(511 downto 0) => vip_M00_AXI_M_AXI_WDATA(511 downto 0),
s_axi_wlast => vip_M00_AXI_M_AXI_WLAST,
s_axi_wready => vip_M00_AXI_M_AXI_WREADY,
s_axi_wstrb(63 downto 0) => vip_M00_AXI_M_AXI_WSTRB(63 downto 0),
s_axi_wvalid => vip_M00_AXI_M_AXI_WVALID
);
vip_m00_axi: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_M00_AXI_0
port map (
aclk => aclk2,
aresetn => interconnect_aresetn1(0),
m_axi_araddr(38 downto 0) => vip_M00_AXI_M_AXI_ARADDR(38 downto 0),
m_axi_arburst(1 downto 0) => vip_M00_AXI_M_AXI_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => vip_M00_AXI_M_AXI_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => vip_M00_AXI_M_AXI_ARLEN(7 downto 0),
m_axi_arlock(0) => vip_M00_AXI_M_AXI_ARLOCK,
m_axi_arprot(2 downto 0) => vip_M00_AXI_M_AXI_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => vip_M00_AXI_M_AXI_ARQOS(3 downto 0),
m_axi_arready => vip_M00_AXI_M_AXI_ARREADY,
m_axi_arvalid => vip_M00_AXI_M_AXI_ARVALID,
m_axi_awaddr(38 downto 0) => vip_M00_AXI_M_AXI_AWADDR(38 downto 0),
m_axi_awburst(1 downto 0) => vip_M00_AXI_M_AXI_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => vip_M00_AXI_M_AXI_AWCACHE(3 downto 0),
m_axi_awlen(7 downto 0) => vip_M00_AXI_M_AXI_AWLEN(7 downto 0),
m_axi_awlock(0) => vip_M00_AXI_M_AXI_AWLOCK,
m_axi_awprot(2 downto 0) => vip_M00_AXI_M_AXI_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => vip_M00_AXI_M_AXI_AWQOS(3 downto 0),
m_axi_awready => vip_M00_AXI_M_AXI_AWREADY,
m_axi_awvalid => vip_M00_AXI_M_AXI_AWVALID,
m_axi_bready => vip_M00_AXI_M_AXI_BREADY,
m_axi_bresp(1 downto 0) => vip_M00_AXI_M_AXI_BRESP(1 downto 0),
m_axi_bvalid => vip_M00_AXI_M_AXI_BVALID,
m_axi_rdata(511 downto 0) => vip_M00_AXI_M_AXI_RDATA(511 downto 0),
m_axi_rlast => vip_M00_AXI_M_AXI_RLAST,
m_axi_rready => vip_M00_AXI_M_AXI_RREADY,
m_axi_rresp(1 downto 0) => vip_M00_AXI_M_AXI_RRESP(1 downto 0),
m_axi_rvalid => vip_M00_AXI_M_AXI_RVALID,
m_axi_wdata(511 downto 0) => vip_M00_AXI_M_AXI_WDATA(511 downto 0),
m_axi_wlast => vip_M00_AXI_M_AXI_WLAST,
m_axi_wready => vip_M00_AXI_M_AXI_WREADY,
m_axi_wstrb(63 downto 0) => vip_M00_AXI_M_AXI_WSTRB(63 downto 0),
m_axi_wvalid => vip_M00_AXI_M_AXI_WVALID,
s_axi_araddr(38 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_ARADDR(38 downto 0),
s_axi_arburst(1 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_ARCACHE(3 downto 0),
s_axi_arlen(7 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_ARLEN(7 downto 0),
s_axi_arlock(0) => interconnect_M00_AXI_MEM00_M00_AXI_ARLOCK,
s_axi_arprot(2 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_ARQOS(3 downto 0),
s_axi_arready => interconnect_M00_AXI_MEM00_M00_AXI_ARREADY,
s_axi_arvalid => interconnect_M00_AXI_MEM00_M00_AXI_ARVALID,
s_axi_awaddr(38 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_AWADDR(38 downto 0),
s_axi_awburst(1 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_AWCACHE(3 downto 0),
s_axi_awlen(7 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_AWLEN(7 downto 0),
s_axi_awlock(0) => interconnect_M00_AXI_MEM00_M00_AXI_AWLOCK,
s_axi_awprot(2 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_AWQOS(3 downto 0),
s_axi_awready => interconnect_M00_AXI_MEM00_M00_AXI_AWREADY,
s_axi_awvalid => interconnect_M00_AXI_MEM00_M00_AXI_AWVALID,
s_axi_bready => interconnect_M00_AXI_MEM00_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => interconnect_M00_AXI_MEM00_M00_AXI_BVALID,
s_axi_rdata(511 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_RDATA(511 downto 0),
s_axi_rlast => interconnect_M00_AXI_MEM00_M00_AXI_RLAST,
s_axi_rready => interconnect_M00_AXI_MEM00_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => interconnect_M00_AXI_MEM00_M00_AXI_RVALID,
s_axi_wdata(511 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_WDATA(511 downto 0),
s_axi_wlast => interconnect_M00_AXI_MEM00_M00_AXI_WLAST,
s_axi_wready => interconnect_M00_AXI_MEM00_M00_AXI_WREADY,
s_axi_wstrb(63 downto 0) => interconnect_M00_AXI_MEM00_M00_AXI_WSTRB(63 downto 0),
s_axi_wvalid => interconnect_M00_AXI_MEM00_M00_AXI_WVALID
);
vip_s01_axi: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_S01_AXI_0
port map (
aclk => aclk,
aresetn => interconnect_aresetn(0),
m_axi_araddr(38 downto 0) => vip_S01_AXI_M_AXI_ARADDR(38 downto 0),
m_axi_arburst(1 downto 0) => vip_S01_AXI_M_AXI_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => vip_S01_AXI_M_AXI_ARCACHE(3 downto 0),
m_axi_arid(3 downto 0) => vip_S01_AXI_M_AXI_ARID(3 downto 0),
m_axi_arlen(7 downto 0) => vip_S01_AXI_M_AXI_ARLEN(7 downto 0),
m_axi_arlock(0) => vip_S01_AXI_M_AXI_ARLOCK,
m_axi_arprot(2 downto 0) => vip_S01_AXI_M_AXI_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => vip_S01_AXI_M_AXI_ARQOS(3 downto 0),
m_axi_arready => vip_S01_AXI_M_AXI_ARREADY,
m_axi_arregion(3 downto 0) => NLW_vip_s01_axi_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arvalid => vip_S01_AXI_M_AXI_ARVALID,
m_axi_awaddr(38 downto 0) => vip_S01_AXI_M_AXI_AWADDR(38 downto 0),
m_axi_awburst(1 downto 0) => vip_S01_AXI_M_AXI_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => vip_S01_AXI_M_AXI_AWCACHE(3 downto 0),
m_axi_awid(3 downto 0) => vip_S01_AXI_M_AXI_AWID(3 downto 0),
m_axi_awlen(7 downto 0) => vip_S01_AXI_M_AXI_AWLEN(7 downto 0),
m_axi_awlock(0) => vip_S01_AXI_M_AXI_AWLOCK,
m_axi_awprot(2 downto 0) => vip_S01_AXI_M_AXI_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => vip_S01_AXI_M_AXI_AWQOS(3 downto 0),
m_axi_awready => vip_S01_AXI_M_AXI_AWREADY,
m_axi_awregion(3 downto 0) => NLW_vip_s01_axi_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awvalid => vip_S01_AXI_M_AXI_AWVALID,
m_axi_bid(3 downto 0) => vip_S01_AXI_M_AXI_BID(3 downto 0),
m_axi_bready => vip_S01_AXI_M_AXI_BREADY,
m_axi_bresp(1 downto 0) => vip_S01_AXI_M_AXI_BRESP(1 downto 0),
m_axi_bvalid => vip_S01_AXI_M_AXI_BVALID,
m_axi_rdata(511 downto 0) => vip_S01_AXI_M_AXI_RDATA(511 downto 0),
m_axi_rid(3 downto 0) => vip_S01_AXI_M_AXI_RID(3 downto 0),
m_axi_rlast => vip_S01_AXI_M_AXI_RLAST,
m_axi_rready => vip_S01_AXI_M_AXI_RREADY,
m_axi_rresp(1 downto 0) => vip_S01_AXI_M_AXI_RRESP(1 downto 0),
m_axi_rvalid => vip_S01_AXI_M_AXI_RVALID,
m_axi_wdata(511 downto 0) => vip_S01_AXI_M_AXI_WDATA(511 downto 0),
m_axi_wlast => vip_S01_AXI_M_AXI_WLAST,
m_axi_wready => vip_S01_AXI_M_AXI_WREADY,
m_axi_wstrb(63 downto 0) => vip_S01_AXI_M_AXI_WSTRB(63 downto 0),
m_axi_wvalid => vip_S01_AXI_M_AXI_WVALID,
s_axi_araddr(38 downto 0) => S01_AXI_araddr(38 downto 0),
s_axi_arburst(1 downto 0) => S01_AXI_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => S01_AXI_arcache(3 downto 0),
s_axi_arid(3 downto 0) => S01_AXI_arid(3 downto 0),
s_axi_arlen(7 downto 0) => S01_AXI_arlen(7 downto 0),
s_axi_arlock(0) => S01_AXI_arlock(0),
s_axi_arprot(2 downto 0) => S01_AXI_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => S01_AXI_arqos(3 downto 0),
s_axi_arready => S01_AXI_arready,
s_axi_arregion(3 downto 0) => S01_AXI_arregion(3 downto 0),
s_axi_arvalid => S01_AXI_arvalid,
s_axi_awaddr(38 downto 0) => S01_AXI_awaddr(38 downto 0),
s_axi_awburst(1 downto 0) => S01_AXI_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => S01_AXI_awcache(3 downto 0),
s_axi_awid(3 downto 0) => S01_AXI_awid(3 downto 0),
s_axi_awlen(7 downto 0) => S01_AXI_awlen(7 downto 0),
s_axi_awlock(0) => S01_AXI_awlock(0),
s_axi_awprot(2 downto 0) => S01_AXI_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => S01_AXI_awqos(3 downto 0),
s_axi_awready => S01_AXI_awready,
s_axi_awregion(3 downto 0) => S01_AXI_awregion(3 downto 0),
s_axi_awvalid => S01_AXI_awvalid,
s_axi_bid(3 downto 0) => S01_AXI_bid(3 downto 0),
s_axi_bready => S01_AXI_bready,
s_axi_bresp(1 downto 0) => S01_AXI_bresp(1 downto 0),
s_axi_bvalid => S01_AXI_bvalid,
s_axi_rdata(511 downto 0) => S01_AXI_rdata(511 downto 0),
s_axi_rid(3 downto 0) => S01_AXI_rid(3 downto 0),
s_axi_rlast => S01_AXI_rlast,
s_axi_rready => S01_AXI_rready,
s_axi_rresp(1 downto 0) => S01_AXI_rresp(1 downto 0),
s_axi_rvalid => S01_AXI_rvalid,
s_axi_wdata(511 downto 0) => S01_AXI_wdata(511 downto 0),
s_axi_wlast => S01_AXI_wlast,
s_axi_wready => S01_AXI_wready,
s_axi_wstrb(63 downto 0) => S01_AXI_wstrb(63 downto 0),
s_axi_wvalid => S01_AXI_wvalid
);
vip_s02_axi: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_S02_AXI_0
port map (
aclk => aclk,
aresetn => interconnect_aresetn(0),
m_axi_araddr(38 downto 0) => vip_S02_AXI_M_AXI_ARADDR(38 downto 0),
m_axi_arburst(1 downto 0) => vip_S02_AXI_M_AXI_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => vip_S02_AXI_M_AXI_ARCACHE(3 downto 0),
m_axi_arid(3 downto 0) => vip_S02_AXI_M_AXI_ARID(3 downto 0),
m_axi_arlen(7 downto 0) => vip_S02_AXI_M_AXI_ARLEN(7 downto 0),
m_axi_arlock(0) => vip_S02_AXI_M_AXI_ARLOCK,
m_axi_arprot(2 downto 0) => vip_S02_AXI_M_AXI_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => vip_S02_AXI_M_AXI_ARQOS(3 downto 0),
m_axi_arready => vip_S02_AXI_M_AXI_ARREADY,
m_axi_arregion(3 downto 0) => NLW_vip_s02_axi_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arvalid => vip_S02_AXI_M_AXI_ARVALID,
m_axi_awaddr(38 downto 0) => vip_S02_AXI_M_AXI_AWADDR(38 downto 0),
m_axi_awburst(1 downto 0) => vip_S02_AXI_M_AXI_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => vip_S02_AXI_M_AXI_AWCACHE(3 downto 0),
m_axi_awid(3 downto 0) => vip_S02_AXI_M_AXI_AWID(3 downto 0),
m_axi_awlen(7 downto 0) => vip_S02_AXI_M_AXI_AWLEN(7 downto 0),
m_axi_awlock(0) => vip_S02_AXI_M_AXI_AWLOCK,
m_axi_awprot(2 downto 0) => vip_S02_AXI_M_AXI_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => vip_S02_AXI_M_AXI_AWQOS(3 downto 0),
m_axi_awready => vip_S02_AXI_M_AXI_AWREADY,
m_axi_awregion(3 downto 0) => NLW_vip_s02_axi_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awvalid => vip_S02_AXI_M_AXI_AWVALID,
m_axi_bid(3 downto 0) => vip_S02_AXI_M_AXI_BID(3 downto 0),
m_axi_bready => vip_S02_AXI_M_AXI_BREADY,
m_axi_bresp(1 downto 0) => vip_S02_AXI_M_AXI_BRESP(1 downto 0),
m_axi_bvalid => vip_S02_AXI_M_AXI_BVALID,
m_axi_rdata(511 downto 0) => vip_S02_AXI_M_AXI_RDATA(511 downto 0),
m_axi_rid(3 downto 0) => vip_S02_AXI_M_AXI_RID(3 downto 0),
m_axi_rlast => vip_S02_AXI_M_AXI_RLAST,
m_axi_rready => vip_S02_AXI_M_AXI_RREADY,
m_axi_rresp(1 downto 0) => vip_S02_AXI_M_AXI_RRESP(1 downto 0),
m_axi_rvalid => vip_S02_AXI_M_AXI_RVALID,
m_axi_wdata(511 downto 0) => vip_S02_AXI_M_AXI_WDATA(511 downto 0),
m_axi_wlast => vip_S02_AXI_M_AXI_WLAST,
m_axi_wready => vip_S02_AXI_M_AXI_WREADY,
m_axi_wstrb(63 downto 0) => vip_S02_AXI_M_AXI_WSTRB(63 downto 0),
m_axi_wvalid => vip_S02_AXI_M_AXI_WVALID,
s_axi_araddr(38 downto 0) => S02_AXI_araddr(38 downto 0),
s_axi_arburst(1 downto 0) => S02_AXI_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => S02_AXI_arcache(3 downto 0),
s_axi_arid(3 downto 0) => S02_AXI_arid(3 downto 0),
s_axi_arlen(7 downto 0) => S02_AXI_arlen(7 downto 0),
s_axi_arlock(0) => S02_AXI_arlock(0),
s_axi_arprot(2 downto 0) => S02_AXI_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => S02_AXI_arqos(3 downto 0),
s_axi_arready => S02_AXI_arready,
s_axi_arregion(3 downto 0) => S02_AXI_arregion(3 downto 0),
s_axi_arvalid => S02_AXI_arvalid,
s_axi_awaddr(38 downto 0) => S02_AXI_awaddr(38 downto 0),
s_axi_awburst(1 downto 0) => S02_AXI_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => S02_AXI_awcache(3 downto 0),
s_axi_awid(3 downto 0) => S02_AXI_awid(3 downto 0),
s_axi_awlen(7 downto 0) => S02_AXI_awlen(7 downto 0),
s_axi_awlock(0) => S02_AXI_awlock(0),
s_axi_awprot(2 downto 0) => S02_AXI_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => S02_AXI_awqos(3 downto 0),
s_axi_awready => S02_AXI_awready,
s_axi_awregion(3 downto 0) => S02_AXI_awregion(3 downto 0),
s_axi_awvalid => S02_AXI_awvalid,
s_axi_bid(3 downto 0) => S02_AXI_bid(3 downto 0),
s_axi_bready => S02_AXI_bready,
s_axi_bresp(1 downto 0) => S02_AXI_bresp(1 downto 0),
s_axi_bvalid => S02_AXI_bvalid,
s_axi_rdata(511 downto 0) => S02_AXI_rdata(511 downto 0),
s_axi_rid(3 downto 0) => S02_AXI_rid(3 downto 0),
s_axi_rlast => S02_AXI_rlast,
s_axi_rready => S02_AXI_rready,
s_axi_rresp(1 downto 0) => S02_AXI_rresp(1 downto 0),
s_axi_rvalid => S02_AXI_rvalid,
s_axi_wdata(511 downto 0) => S02_AXI_wdata(511 downto 0),
s_axi_wlast => S02_AXI_wlast,
s_axi_wready => S02_AXI_wready,
s_axi_wstrb(63 downto 0) => S02_AXI_wstrb(63 downto 0),
s_axi_wvalid => S02_AXI_wvalid
);
vip_s04_axi: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_S04_AXI_0
port map (
aclk => aclk,
aresetn => interconnect_aresetn(0),
m_axi_araddr(38 downto 0) => vip_S04_AXI_M_AXI_ARADDR(38 downto 0),
m_axi_arcache(3 downto 0) => vip_S04_AXI_M_AXI_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => vip_S04_AXI_M_AXI_ARLEN(7 downto 0),
m_axi_arlock(0) => vip_S04_AXI_M_AXI_ARLOCK,
m_axi_arprot(2 downto 0) => vip_S04_AXI_M_AXI_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => vip_S04_AXI_M_AXI_ARQOS(3 downto 0),
m_axi_arready => vip_S04_AXI_M_AXI_ARREADY,
m_axi_arregion(3 downto 0) => NLW_vip_s04_axi_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arvalid => vip_S04_AXI_M_AXI_ARVALID,
m_axi_awaddr(38 downto 0) => vip_S04_AXI_M_AXI_AWADDR(38 downto 0),
m_axi_awcache(3 downto 0) => vip_S04_AXI_M_AXI_AWCACHE(3 downto 0),
m_axi_awlen(7 downto 0) => vip_S04_AXI_M_AXI_AWLEN(7 downto 0),
m_axi_awlock(0) => vip_S04_AXI_M_AXI_AWLOCK,
m_axi_awprot(2 downto 0) => vip_S04_AXI_M_AXI_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => vip_S04_AXI_M_AXI_AWQOS(3 downto 0),
m_axi_awready => vip_S04_AXI_M_AXI_AWREADY,
m_axi_awregion(3 downto 0) => NLW_vip_s04_axi_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awvalid => vip_S04_AXI_M_AXI_AWVALID,
m_axi_bready => vip_S04_AXI_M_AXI_BREADY,
m_axi_bresp(1 downto 0) => vip_S04_AXI_M_AXI_BRESP(1 downto 0),
m_axi_bvalid => vip_S04_AXI_M_AXI_BVALID,
m_axi_rdata(511 downto 0) => vip_S04_AXI_M_AXI_RDATA(511 downto 0),
m_axi_rlast => vip_S04_AXI_M_AXI_RLAST,
m_axi_rready => vip_S04_AXI_M_AXI_RREADY,
m_axi_rresp(1 downto 0) => vip_S04_AXI_M_AXI_RRESP(1 downto 0),
m_axi_rvalid => vip_S04_AXI_M_AXI_RVALID,
m_axi_wdata(511 downto 0) => vip_S04_AXI_M_AXI_WDATA(511 downto 0),
m_axi_wlast => vip_S04_AXI_M_AXI_WLAST,
m_axi_wready => vip_S04_AXI_M_AXI_WREADY,
m_axi_wstrb(63 downto 0) => vip_S04_AXI_M_AXI_WSTRB(63 downto 0),
m_axi_wvalid => vip_S04_AXI_M_AXI_WVALID,
s_axi_araddr(38 downto 0) => S04_AXI_araddr(38 downto 0),
s_axi_arcache(3 downto 0) => S04_AXI_arcache(3 downto 0),
s_axi_arlen(7 downto 0) => S04_AXI_arlen(7 downto 0),
s_axi_arlock(0) => S04_AXI_arlock(0),
s_axi_arprot(2 downto 0) => S04_AXI_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => S04_AXI_arqos(3 downto 0),
s_axi_arready => S04_AXI_arready,
s_axi_arregion(3 downto 0) => S04_AXI_arregion(3 downto 0),
s_axi_arvalid => S04_AXI_arvalid,
s_axi_awaddr(38 downto 0) => S04_AXI_awaddr(38 downto 0),
s_axi_awcache(3 downto 0) => S04_AXI_awcache(3 downto 0),
s_axi_awlen(7 downto 0) => S04_AXI_awlen(7 downto 0),
s_axi_awlock(0) => S04_AXI_awlock(0),
s_axi_awprot(2 downto 0) => S04_AXI_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => S04_AXI_awqos(3 downto 0),
s_axi_awready => S04_AXI_awready,
s_axi_awregion(3 downto 0) => S04_AXI_awregion(3 downto 0),
s_axi_awvalid => S04_AXI_awvalid,
s_axi_bready => S04_AXI_bready,
s_axi_bresp(1 downto 0) => S04_AXI_bresp(1 downto 0),
s_axi_bvalid => S04_AXI_bvalid,
s_axi_rdata(511 downto 0) => S04_AXI_rdata(511 downto 0),
s_axi_rlast => S04_AXI_rlast,
s_axi_rready => S04_AXI_rready,
s_axi_rresp(1 downto 0) => S04_AXI_rresp(1 downto 0),
s_axi_rvalid => S04_AXI_rvalid,
s_axi_wdata(511 downto 0) => S04_AXI_wdata(511 downto 0),
s_axi_wlast => S04_AXI_wlast,
s_axi_wready => S04_AXI_wready,
s_axi_wstrb(63 downto 0) => S04_AXI_wstrb(63 downto 0),
s_axi_wvalid => S04_AXI_wvalid
);
vip_s05_axi: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_S05_AXI_0
port map (
aclk => aclk,
aresetn => interconnect_aresetn(0),
m_axi_araddr(38 downto 0) => vip_S05_AXI_M_AXI_ARADDR(38 downto 0),
m_axi_arcache(3 downto 0) => vip_S05_AXI_M_AXI_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => vip_S05_AXI_M_AXI_ARLEN(7 downto 0),
m_axi_arlock(0) => vip_S05_AXI_M_AXI_ARLOCK,
m_axi_arprot(2 downto 0) => vip_S05_AXI_M_AXI_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => vip_S05_AXI_M_AXI_ARQOS(3 downto 0),
m_axi_arready => vip_S05_AXI_M_AXI_ARREADY,
m_axi_arregion(3 downto 0) => NLW_vip_s05_axi_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arvalid => vip_S05_AXI_M_AXI_ARVALID,
m_axi_awaddr(38 downto 0) => vip_S05_AXI_M_AXI_AWADDR(38 downto 0),
m_axi_awcache(3 downto 0) => vip_S05_AXI_M_AXI_AWCACHE(3 downto 0),
m_axi_awlen(7 downto 0) => vip_S05_AXI_M_AXI_AWLEN(7 downto 0),
m_axi_awlock(0) => vip_S05_AXI_M_AXI_AWLOCK,
m_axi_awprot(2 downto 0) => vip_S05_AXI_M_AXI_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => vip_S05_AXI_M_AXI_AWQOS(3 downto 0),
m_axi_awready => vip_S05_AXI_M_AXI_AWREADY,
m_axi_awregion(3 downto 0) => NLW_vip_s05_axi_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awvalid => vip_S05_AXI_M_AXI_AWVALID,
m_axi_bready => vip_S05_AXI_M_AXI_BREADY,
m_axi_bresp(1 downto 0) => vip_S05_AXI_M_AXI_BRESP(1 downto 0),
m_axi_bvalid => vip_S05_AXI_M_AXI_BVALID,
m_axi_rdata(511 downto 0) => vip_S05_AXI_M_AXI_RDATA(511 downto 0),
m_axi_rlast => vip_S05_AXI_M_AXI_RLAST,
m_axi_rready => vip_S05_AXI_M_AXI_RREADY,
m_axi_rresp(1 downto 0) => vip_S05_AXI_M_AXI_RRESP(1 downto 0),
m_axi_rvalid => vip_S05_AXI_M_AXI_RVALID,
m_axi_wdata(511 downto 0) => vip_S05_AXI_M_AXI_WDATA(511 downto 0),
m_axi_wlast => vip_S05_AXI_M_AXI_WLAST,
m_axi_wready => vip_S05_AXI_M_AXI_WREADY,
m_axi_wstrb(63 downto 0) => vip_S05_AXI_M_AXI_WSTRB(63 downto 0),
m_axi_wvalid => vip_S05_AXI_M_AXI_WVALID,
s_axi_araddr(38 downto 0) => S05_AXI_araddr(38 downto 0),
s_axi_arcache(3 downto 0) => S05_AXI_arcache(3 downto 0),
s_axi_arlen(7 downto 0) => S05_AXI_arlen(7 downto 0),
s_axi_arlock(0) => S05_AXI_arlock(0),
s_axi_arprot(2 downto 0) => S05_AXI_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => S05_AXI_arqos(3 downto 0),
s_axi_arready => S05_AXI_arready,
s_axi_arregion(3 downto 0) => S05_AXI_arregion(3 downto 0),
s_axi_arvalid => S05_AXI_arvalid,
s_axi_awaddr(38 downto 0) => S05_AXI_awaddr(38 downto 0),
s_axi_awcache(3 downto 0) => S05_AXI_awcache(3 downto 0),
s_axi_awlen(7 downto 0) => S05_AXI_awlen(7 downto 0),
s_axi_awlock(0) => S05_AXI_awlock(0),
s_axi_awprot(2 downto 0) => S05_AXI_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => S05_AXI_awqos(3 downto 0),
s_axi_awready => S05_AXI_awready,
s_axi_awregion(3 downto 0) => S05_AXI_awregion(3 downto 0),
s_axi_awvalid => S05_AXI_awvalid,
s_axi_bready => S05_AXI_bready,
s_axi_bresp(1 downto 0) => S05_AXI_bresp(1 downto 0),
s_axi_bvalid => S05_AXI_bvalid,
s_axi_rdata(511 downto 0) => S05_AXI_rdata(511 downto 0),
s_axi_rlast => S05_AXI_rlast,
s_axi_rready => S05_AXI_rready,
s_axi_rresp(1 downto 0) => S05_AXI_rresp(1 downto 0),
s_axi_rvalid => S05_AXI_rvalid,
s_axi_wdata(511 downto 0) => S05_AXI_wdata(511 downto 0),
s_axi_wlast => S05_AXI_wlast,
s_axi_wready => S05_AXI_wready,
s_axi_wstrb(63 downto 0) => S05_AXI_wstrb(63 downto 0),
s_axi_wvalid => S05_AXI_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory_imp_1K98CM8 is
port (
ddr4_mem_calib_vec : out STD_LOGIC_VECTOR ( 2 downto 0 );
ddr4_mem_calib_complete : out STD_LOGIC;
DDR4_MEM01_act_n : out STD_LOGIC;
DDR4_MEM01_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
DDR4_MEM01_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR4_MEM01_bg : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR4_MEM01_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM01_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM01_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM01_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM01_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM01_reset_n : out STD_LOGIC;
DDR4_MEM01_par : out STD_LOGIC;
ddr4_mem01_ui_clk : out STD_LOGIC;
S_AXI_CTRL_awready : out STD_LOGIC;
S_AXI_CTRL_wready : out STD_LOGIC;
S_AXI_CTRL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_CTRL_bvalid : out STD_LOGIC;
S_AXI_CTRL_arready : out STD_LOGIC;
S_AXI_CTRL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_CTRL_rvalid : out STD_LOGIC;
S_AXI_awready : out STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_arready : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rvalid : out STD_LOGIC;
DDR4_MEM01_dq : inout STD_LOGIC_VECTOR ( 71 downto 0 );
DDR4_MEM01_dqs_c : inout STD_LOGIC_VECTOR ( 17 downto 0 );
DDR4_MEM01_dqs_t : inout STD_LOGIC_VECTOR ( 17 downto 0 );
ddr4_mem01_sys_rst : in STD_LOGIC;
DDR4_MEM01_DIFF_CLK_clk_p : in STD_LOGIC;
DDR4_MEM01_DIFF_CLK_clk_n : in STD_LOGIC;
aclk1 : in STD_LOGIC;
S_AXI_CTRL_awaddr : in STD_LOGIC_VECTOR ( 24 downto 0 );
S_AXI_CTRL_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_CTRL_awvalid : in STD_LOGIC;
S_AXI_CTRL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_CTRL_wvalid : in STD_LOGIC;
S_AXI_CTRL_bready : in STD_LOGIC;
S_AXI_CTRL_araddr : in STD_LOGIC_VECTOR ( 24 downto 0 );
S_AXI_CTRL_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_CTRL_arvalid : in STD_LOGIC;
S_AXI_CTRL_rready : in STD_LOGIC;
aresetn : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 33 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 33 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rready : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory_imp_1K98CM8;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory_imp_1K98CM8 is
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_reduce_0 is
port (
Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Res : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_reduce_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_ddr4_mem01_0 is
port (
sys_rst : in STD_LOGIC;
c0_sys_clk_p : in STD_LOGIC;
c0_sys_clk_n : in STD_LOGIC;
c0_ddr4_act_n : out STD_LOGIC;
c0_ddr4_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
c0_ddr4_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
c0_ddr4_bg : out STD_LOGIC_VECTOR ( 1 downto 0 );
c0_ddr4_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_reset_n : out STD_LOGIC;
c0_ddr4_parity : out STD_LOGIC;
c0_ddr4_dq : inout STD_LOGIC_VECTOR ( 71 downto 0 );
c0_ddr4_dqs_c : inout STD_LOGIC_VECTOR ( 17 downto 0 );
c0_ddr4_dqs_t : inout STD_LOGIC_VECTOR ( 17 downto 0 );
c0_init_calib_complete : out STD_LOGIC;
c0_ddr4_ui_clk : out STD_LOGIC;
c0_ddr4_ui_clk_sync_rst : out STD_LOGIC;
addn_ui_clkout1 : out STD_LOGIC;
dbg_clk : out STD_LOGIC;
c0_ddr4_s_axi_ctrl_awvalid : in STD_LOGIC;
c0_ddr4_s_axi_ctrl_awready : out STD_LOGIC;
c0_ddr4_s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
c0_ddr4_s_axi_ctrl_wvalid : in STD_LOGIC;
c0_ddr4_s_axi_ctrl_wready : out STD_LOGIC;
c0_ddr4_s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
c0_ddr4_s_axi_ctrl_bvalid : out STD_LOGIC;
c0_ddr4_s_axi_ctrl_bready : in STD_LOGIC;
c0_ddr4_s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
c0_ddr4_s_axi_ctrl_arvalid : in STD_LOGIC;
c0_ddr4_s_axi_ctrl_arready : out STD_LOGIC;
c0_ddr4_s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
c0_ddr4_s_axi_ctrl_rvalid : out STD_LOGIC;
c0_ddr4_s_axi_ctrl_rready : in STD_LOGIC;
c0_ddr4_s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
c0_ddr4_s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
c0_ddr4_interrupt : out STD_LOGIC;
c0_ddr4_aresetn : in STD_LOGIC;
c0_ddr4_s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_s_axi_awaddr : in STD_LOGIC_VECTOR ( 33 downto 0 );
c0_ddr4_s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
c0_ddr4_s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
c0_ddr4_s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
c0_ddr4_s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
c0_ddr4_s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
c0_ddr4_s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
c0_ddr4_s_axi_awvalid : in STD_LOGIC;
c0_ddr4_s_axi_awready : out STD_LOGIC;
c0_ddr4_s_axi_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
c0_ddr4_s_axi_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
c0_ddr4_s_axi_wlast : in STD_LOGIC;
c0_ddr4_s_axi_wvalid : in STD_LOGIC;
c0_ddr4_s_axi_wready : out STD_LOGIC;
c0_ddr4_s_axi_bready : in STD_LOGIC;
c0_ddr4_s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
c0_ddr4_s_axi_bvalid : out STD_LOGIC;
c0_ddr4_s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_s_axi_araddr : in STD_LOGIC_VECTOR ( 33 downto 0 );
c0_ddr4_s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
c0_ddr4_s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
c0_ddr4_s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
c0_ddr4_s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
c0_ddr4_s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
c0_ddr4_s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
c0_ddr4_s_axi_arvalid : in STD_LOGIC;
c0_ddr4_s_axi_arready : out STD_LOGIC;
c0_ddr4_s_axi_rready : in STD_LOGIC;
c0_ddr4_s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
c0_ddr4_s_axi_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
c0_ddr4_s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
c0_ddr4_s_axi_rlast : out STD_LOGIC;
c0_ddr4_s_axi_rvalid : out STD_LOGIC;
dbg_bus : out STD_LOGIC_VECTOR ( 511 downto 0 )
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_ddr4_mem01_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_ddr4_mem01_ctrl_cc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_ddr4_mem01_ctrl_cc_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_interconnect_ddrmem_ctrl_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 24 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 24 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_interconnect_ddrmem_ctrl_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_psr_ctrl_interconnect_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_psr_ctrl_interconnect_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_psr_ddr4_mem01_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_psr_ddr4_mem01_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_DDR4_MEM01_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 33 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 33 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_DDR4_MEM01_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_ctrl_DDR4_MEM01_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_ctrl_DDR4_MEM01_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_ui_clk_DDR4_MEM01_0 is
port (
clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_ui_clk_DDR4_MEM01_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_ui_rst_DDR4_MEM01_0 is
port (
rst_in : in STD_LOGIC;
rst_out : out STD_LOGIC
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_ui_rst_DDR4_MEM01_0;
signal calib_concat_dout : STD_LOGIC;
signal ddr4_mem01_c0_ddr4_ui_clk : STD_LOGIC;
signal ddr4_mem01_c0_ddr4_ui_clk_sync_rst : STD_LOGIC;
signal ddr4_mem01_c0_init_calib_complete : STD_LOGIC;
signal ddr4_mem01_ctrl_cc_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ddr4_mem01_ctrl_cc_M_AXI_ARREADY : STD_LOGIC;
signal ddr4_mem01_ctrl_cc_M_AXI_ARVALID : STD_LOGIC;
signal ddr4_mem01_ctrl_cc_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ddr4_mem01_ctrl_cc_M_AXI_AWREADY : STD_LOGIC;
signal ddr4_mem01_ctrl_cc_M_AXI_AWVALID : STD_LOGIC;
signal ddr4_mem01_ctrl_cc_M_AXI_BREADY : STD_LOGIC;
signal ddr4_mem01_ctrl_cc_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ddr4_mem01_ctrl_cc_M_AXI_BVALID : STD_LOGIC;
signal ddr4_mem01_ctrl_cc_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ddr4_mem01_ctrl_cc_M_AXI_RREADY : STD_LOGIC;
signal ddr4_mem01_ctrl_cc_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ddr4_mem01_ctrl_cc_M_AXI_RVALID : STD_LOGIC;
signal ddr4_mem01_ctrl_cc_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ddr4_mem01_ctrl_cc_M_AXI_WREADY : STD_LOGIC;
signal ddr4_mem01_ctrl_cc_M_AXI_WVALID : STD_LOGIC;
signal \^ddr4_mem01_ui_clk\ : STD_LOGIC;
signal interconnect_ddrmem_ctrl_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_ddrmem_ctrl_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_ddrmem_ctrl_M_AXI_ARREADY : STD_LOGIC;
signal interconnect_ddrmem_ctrl_M_AXI_ARVALID : STD_LOGIC;
signal interconnect_ddrmem_ctrl_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_ddrmem_ctrl_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_ddrmem_ctrl_M_AXI_AWREADY : STD_LOGIC;
signal interconnect_ddrmem_ctrl_M_AXI_AWVALID : STD_LOGIC;
signal interconnect_ddrmem_ctrl_M_AXI_BREADY : STD_LOGIC;
signal interconnect_ddrmem_ctrl_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_ddrmem_ctrl_M_AXI_BVALID : STD_LOGIC;
signal interconnect_ddrmem_ctrl_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_ddrmem_ctrl_M_AXI_RREADY : STD_LOGIC;
signal interconnect_ddrmem_ctrl_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_ddrmem_ctrl_M_AXI_RVALID : STD_LOGIC;
signal interconnect_ddrmem_ctrl_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal interconnect_ddrmem_ctrl_M_AXI_WREADY : STD_LOGIC;
signal interconnect_ddrmem_ctrl_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_ddrmem_ctrl_M_AXI_WVALID : STD_LOGIC;
signal psr_ctrl_interconnect_interconnect_aresetn : STD_LOGIC;
signal psr_ddr4_mem01_interconnect_aresetn : STD_LOGIC;
signal vip_DDR4_MEM01_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 33 downto 0 );
signal vip_DDR4_MEM01_M_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_DDR4_MEM01_M_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_DDR4_MEM01_M_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal vip_DDR4_MEM01_M_AXI_ARLOCK : STD_LOGIC;
signal vip_DDR4_MEM01_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal vip_DDR4_MEM01_M_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_DDR4_MEM01_M_AXI_ARREADY : STD_LOGIC;
signal vip_DDR4_MEM01_M_AXI_ARVALID : STD_LOGIC;
signal vip_DDR4_MEM01_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 33 downto 0 );
signal vip_DDR4_MEM01_M_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_DDR4_MEM01_M_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_DDR4_MEM01_M_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal vip_DDR4_MEM01_M_AXI_AWLOCK : STD_LOGIC;
signal vip_DDR4_MEM01_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal vip_DDR4_MEM01_M_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_DDR4_MEM01_M_AXI_AWREADY : STD_LOGIC;
signal vip_DDR4_MEM01_M_AXI_AWVALID : STD_LOGIC;
signal vip_DDR4_MEM01_M_AXI_BREADY : STD_LOGIC;
signal vip_DDR4_MEM01_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_DDR4_MEM01_M_AXI_BVALID : STD_LOGIC;
signal vip_DDR4_MEM01_M_AXI_RDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal vip_DDR4_MEM01_M_AXI_RLAST : STD_LOGIC;
signal vip_DDR4_MEM01_M_AXI_RREADY : STD_LOGIC;
signal vip_DDR4_MEM01_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_DDR4_MEM01_M_AXI_RVALID : STD_LOGIC;
signal vip_DDR4_MEM01_M_AXI_WDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal vip_DDR4_MEM01_M_AXI_WLAST : STD_LOGIC;
signal vip_DDR4_MEM01_M_AXI_WREADY : STD_LOGIC;
signal vip_DDR4_MEM01_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 63 downto 0 );
signal vip_DDR4_MEM01_M_AXI_WVALID : STD_LOGIC;
signal vip_ctrl_DDR4_MEM01_M_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vip_ctrl_DDR4_MEM01_M_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal vip_ctrl_DDR4_MEM01_M_AXI_ARREADY : STD_LOGIC;
signal vip_ctrl_DDR4_MEM01_M_AXI_ARVALID : STD_LOGIC;
signal vip_ctrl_DDR4_MEM01_M_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vip_ctrl_DDR4_MEM01_M_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal vip_ctrl_DDR4_MEM01_M_AXI_AWREADY : STD_LOGIC;
signal vip_ctrl_DDR4_MEM01_M_AXI_AWVALID : STD_LOGIC;
signal vip_ctrl_DDR4_MEM01_M_AXI_BREADY : STD_LOGIC;
signal vip_ctrl_DDR4_MEM01_M_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_ctrl_DDR4_MEM01_M_AXI_BVALID : STD_LOGIC;
signal vip_ctrl_DDR4_MEM01_M_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vip_ctrl_DDR4_MEM01_M_AXI_RREADY : STD_LOGIC;
signal vip_ctrl_DDR4_MEM01_M_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal vip_ctrl_DDR4_MEM01_M_AXI_RVALID : STD_LOGIC;
signal vip_ctrl_DDR4_MEM01_M_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vip_ctrl_DDR4_MEM01_M_AXI_WREADY : STD_LOGIC;
signal vip_ctrl_DDR4_MEM01_M_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vip_ctrl_DDR4_MEM01_M_AXI_WVALID : STD_LOGIC;
signal vip_ui_rst_DDR4_MEM01_rst_out : STD_LOGIC;
signal NLW_ddr4_mem01_addn_ui_clkout1_UNCONNECTED : STD_LOGIC;
signal NLW_ddr4_mem01_c0_ddr4_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_ddr4_mem01_dbg_clk_UNCONNECTED : STD_LOGIC;
signal NLW_ddr4_mem01_c0_ddr4_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_ddr4_mem01_c0_ddr4_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_ddr4_mem01_dbg_bus_UNCONNECTED : STD_LOGIC_VECTOR ( 511 downto 0 );
signal NLW_ddr4_mem01_ctrl_cc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_ddr4_mem01_ctrl_cc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_ddr4_mem01_ctrl_cc_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_psr_ctrl_interconnect_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_psr_ctrl_interconnect_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_psr_ctrl_interconnect_peripheral_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_psr_ctrl_interconnect_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_psr_ddr4_mem01_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_psr_ddr4_mem01_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_psr_ddr4_mem01_peripheral_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_psr_ddr4_mem01_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of calib_concat : label is "bd_d216_calib_concat_0,xlconcat_v2_1_3_xlconcat,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of calib_concat : label is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of calib_concat : label is "xlconcat_v2_1_3_xlconcat,Vivado 2020.1";
attribute X_CORE_INFO of calib_reduce : label is "util_reduced_logic_v2_0_4_util_reduced_logic,Vivado 2020.1";
attribute CHECK_LICENSE_TYPE of calib_vector_concat : label is "bd_d216_calib_vector_concat_0,xlconcat_v2_1_3_xlconcat,{}";
attribute DowngradeIPIdentifiedWarnings of calib_vector_concat : label is "yes";
attribute X_CORE_INFO of calib_vector_concat : label is "xlconcat_v2_1_3_xlconcat,Vivado 2020.1";
attribute X_CORE_INFO of ddr4_mem01 : label is "ddr4_v2_2_9,Vivado 2020.1";
attribute X_CORE_INFO of ddr4_mem01_ctrl_cc : label is "axi_clock_converter_v2_1_20_axi_clock_converter,Vivado 2020.1";
attribute X_CORE_INFO of interconnect_ddrmem_ctrl : label is "axi_mmu_v2_1_19_top,Vivado 2020.1";
attribute X_CORE_INFO of psr_ctrl_interconnect : label is "proc_sys_reset,Vivado 2020.1";
attribute X_CORE_INFO of psr_ddr4_mem01 : label is "proc_sys_reset,Vivado 2020.1";
attribute X_CORE_INFO of vip_DDR4_MEM01 : label is "axi_vip_v1_1_7_top,Vivado 2020.1";
attribute X_CORE_INFO of vip_ctrl_DDR4_MEM01 : label is "axi_vip_v1_1_7_top,Vivado 2020.1";
attribute X_CORE_INFO of vip_ui_clk_DDR4_MEM01 : label is "clk_vip_v1_0_2_top,Vivado 2020.1";
attribute X_CORE_INFO of vip_ui_rst_DDR4_MEM01 : label is "rst_vip_v1_0_4_top,Vivado 2020.1";
begin
ddr4_mem01_ui_clk <= \^ddr4_mem01_ui_clk\;
calib_concat: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_concat_0
port map (
In0(0) => ddr4_mem01_c0_init_calib_complete,
dout(0) => calib_concat_dout
);
calib_reduce: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_reduce_0
port map (
Op1(0) => calib_concat_dout,
Res => ddr4_mem_calib_complete
);
calib_vector_concat: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_calib_vector_concat_0
port map (
In0(0) => '0',
In1(0) => ddr4_mem01_c0_init_calib_complete,
In2(0) => '0',
dout(2 downto 0) => ddr4_mem_calib_vec(2 downto 0)
);
ddr4_mem01: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_ddr4_mem01_0
port map (
addn_ui_clkout1 => NLW_ddr4_mem01_addn_ui_clkout1_UNCONNECTED,
c0_ddr4_act_n => DDR4_MEM01_act_n,
c0_ddr4_adr(16 downto 0) => DDR4_MEM01_adr(16 downto 0),
c0_ddr4_aresetn => psr_ddr4_mem01_interconnect_aresetn,
c0_ddr4_ba(1 downto 0) => DDR4_MEM01_ba(1 downto 0),
c0_ddr4_bg(1 downto 0) => DDR4_MEM01_bg(1 downto 0),
c0_ddr4_ck_c(0) => DDR4_MEM01_ck_c(0),
c0_ddr4_ck_t(0) => DDR4_MEM01_ck_t(0),
c0_ddr4_cke(0) => DDR4_MEM01_cke(0),
c0_ddr4_cs_n(0) => DDR4_MEM01_cs_n(0),
c0_ddr4_dq(71 downto 0) => DDR4_MEM01_dq(71 downto 0),
c0_ddr4_dqs_c(17 downto 0) => DDR4_MEM01_dqs_c(17 downto 0),
c0_ddr4_dqs_t(17 downto 0) => DDR4_MEM01_dqs_t(17 downto 0),
c0_ddr4_interrupt => NLW_ddr4_mem01_c0_ddr4_interrupt_UNCONNECTED,
c0_ddr4_odt(0) => DDR4_MEM01_odt(0),
c0_ddr4_parity => DDR4_MEM01_par,
c0_ddr4_reset_n => DDR4_MEM01_reset_n,
c0_ddr4_s_axi_araddr(33 downto 0) => vip_DDR4_MEM01_M_AXI_ARADDR(33 downto 0),
c0_ddr4_s_axi_arburst(1 downto 0) => vip_DDR4_MEM01_M_AXI_ARBURST(1 downto 0),
c0_ddr4_s_axi_arcache(3 downto 0) => vip_DDR4_MEM01_M_AXI_ARCACHE(3 downto 0),
c0_ddr4_s_axi_arid(0) => '0',
c0_ddr4_s_axi_arlen(7 downto 0) => vip_DDR4_MEM01_M_AXI_ARLEN(7 downto 0),
c0_ddr4_s_axi_arlock(0) => vip_DDR4_MEM01_M_AXI_ARLOCK,
c0_ddr4_s_axi_arprot(2 downto 0) => vip_DDR4_MEM01_M_AXI_ARPROT(2 downto 0),
c0_ddr4_s_axi_arqos(3 downto 0) => vip_DDR4_MEM01_M_AXI_ARQOS(3 downto 0),
c0_ddr4_s_axi_arready => vip_DDR4_MEM01_M_AXI_ARREADY,
c0_ddr4_s_axi_arsize(2 downto 0) => B"110",
c0_ddr4_s_axi_arvalid => vip_DDR4_MEM01_M_AXI_ARVALID,
c0_ddr4_s_axi_awaddr(33 downto 0) => vip_DDR4_MEM01_M_AXI_AWADDR(33 downto 0),
c0_ddr4_s_axi_awburst(1 downto 0) => vip_DDR4_MEM01_M_AXI_AWBURST(1 downto 0),
c0_ddr4_s_axi_awcache(3 downto 0) => vip_DDR4_MEM01_M_AXI_AWCACHE(3 downto 0),
c0_ddr4_s_axi_awid(0) => '0',
c0_ddr4_s_axi_awlen(7 downto 0) => vip_DDR4_MEM01_M_AXI_AWLEN(7 downto 0),
c0_ddr4_s_axi_awlock(0) => vip_DDR4_MEM01_M_AXI_AWLOCK,
c0_ddr4_s_axi_awprot(2 downto 0) => vip_DDR4_MEM01_M_AXI_AWPROT(2 downto 0),
c0_ddr4_s_axi_awqos(3 downto 0) => vip_DDR4_MEM01_M_AXI_AWQOS(3 downto 0),
c0_ddr4_s_axi_awready => vip_DDR4_MEM01_M_AXI_AWREADY,
c0_ddr4_s_axi_awsize(2 downto 0) => B"110",
c0_ddr4_s_axi_awvalid => vip_DDR4_MEM01_M_AXI_AWVALID,
c0_ddr4_s_axi_bid(0) => NLW_ddr4_mem01_c0_ddr4_s_axi_bid_UNCONNECTED(0),
c0_ddr4_s_axi_bready => vip_DDR4_MEM01_M_AXI_BREADY,
c0_ddr4_s_axi_bresp(1 downto 0) => vip_DDR4_MEM01_M_AXI_BRESP(1 downto 0),
c0_ddr4_s_axi_bvalid => vip_DDR4_MEM01_M_AXI_BVALID,
c0_ddr4_s_axi_ctrl_araddr(31 downto 0) => ddr4_mem01_ctrl_cc_M_AXI_ARADDR(31 downto 0),
c0_ddr4_s_axi_ctrl_arready => ddr4_mem01_ctrl_cc_M_AXI_ARREADY,
c0_ddr4_s_axi_ctrl_arvalid => ddr4_mem01_ctrl_cc_M_AXI_ARVALID,
c0_ddr4_s_axi_ctrl_awaddr(31 downto 0) => ddr4_mem01_ctrl_cc_M_AXI_AWADDR(31 downto 0),
c0_ddr4_s_axi_ctrl_awready => ddr4_mem01_ctrl_cc_M_AXI_AWREADY,
c0_ddr4_s_axi_ctrl_awvalid => ddr4_mem01_ctrl_cc_M_AXI_AWVALID,
c0_ddr4_s_axi_ctrl_bready => ddr4_mem01_ctrl_cc_M_AXI_BREADY,
c0_ddr4_s_axi_ctrl_bresp(1 downto 0) => ddr4_mem01_ctrl_cc_M_AXI_BRESP(1 downto 0),
c0_ddr4_s_axi_ctrl_bvalid => ddr4_mem01_ctrl_cc_M_AXI_BVALID,
c0_ddr4_s_axi_ctrl_rdata(31 downto 0) => ddr4_mem01_ctrl_cc_M_AXI_RDATA(31 downto 0),
c0_ddr4_s_axi_ctrl_rready => ddr4_mem01_ctrl_cc_M_AXI_RREADY,
c0_ddr4_s_axi_ctrl_rresp(1 downto 0) => ddr4_mem01_ctrl_cc_M_AXI_RRESP(1 downto 0),
c0_ddr4_s_axi_ctrl_rvalid => ddr4_mem01_ctrl_cc_M_AXI_RVALID,
c0_ddr4_s_axi_ctrl_wdata(31 downto 0) => ddr4_mem01_ctrl_cc_M_AXI_WDATA(31 downto 0),
c0_ddr4_s_axi_ctrl_wready => ddr4_mem01_ctrl_cc_M_AXI_WREADY,
c0_ddr4_s_axi_ctrl_wvalid => ddr4_mem01_ctrl_cc_M_AXI_WVALID,
c0_ddr4_s_axi_rdata(511 downto 0) => vip_DDR4_MEM01_M_AXI_RDATA(511 downto 0),
c0_ddr4_s_axi_rid(0) => NLW_ddr4_mem01_c0_ddr4_s_axi_rid_UNCONNECTED(0),
c0_ddr4_s_axi_rlast => vip_DDR4_MEM01_M_AXI_RLAST,
c0_ddr4_s_axi_rready => vip_DDR4_MEM01_M_AXI_RREADY,
c0_ddr4_s_axi_rresp(1 downto 0) => vip_DDR4_MEM01_M_AXI_RRESP(1 downto 0),
c0_ddr4_s_axi_rvalid => vip_DDR4_MEM01_M_AXI_RVALID,
c0_ddr4_s_axi_wdata(511 downto 0) => vip_DDR4_MEM01_M_AXI_WDATA(511 downto 0),
c0_ddr4_s_axi_wlast => vip_DDR4_MEM01_M_AXI_WLAST,
c0_ddr4_s_axi_wready => vip_DDR4_MEM01_M_AXI_WREADY,
c0_ddr4_s_axi_wstrb(63 downto 0) => vip_DDR4_MEM01_M_AXI_WSTRB(63 downto 0),
c0_ddr4_s_axi_wvalid => vip_DDR4_MEM01_M_AXI_WVALID,
c0_ddr4_ui_clk => ddr4_mem01_c0_ddr4_ui_clk,
c0_ddr4_ui_clk_sync_rst => ddr4_mem01_c0_ddr4_ui_clk_sync_rst,
c0_init_calib_complete => ddr4_mem01_c0_init_calib_complete,
c0_sys_clk_n => DDR4_MEM01_DIFF_CLK_clk_n,
c0_sys_clk_p => DDR4_MEM01_DIFF_CLK_clk_p,
dbg_bus(511 downto 0) => NLW_ddr4_mem01_dbg_bus_UNCONNECTED(511 downto 0),
dbg_clk => NLW_ddr4_mem01_dbg_clk_UNCONNECTED,
sys_rst => ddr4_mem01_sys_rst
);
ddr4_mem01_ctrl_cc: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_ddr4_mem01_ctrl_cc_0
port map (
m_axi_aclk => \^ddr4_mem01_ui_clk\,
m_axi_araddr(31 downto 0) => ddr4_mem01_ctrl_cc_M_AXI_ARADDR(31 downto 0),
m_axi_aresetn => psr_ddr4_mem01_interconnect_aresetn,
m_axi_arprot(2 downto 0) => NLW_ddr4_mem01_ctrl_cc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => ddr4_mem01_ctrl_cc_M_AXI_ARREADY,
m_axi_arvalid => ddr4_mem01_ctrl_cc_M_AXI_ARVALID,
m_axi_awaddr(31 downto 0) => ddr4_mem01_ctrl_cc_M_AXI_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => NLW_ddr4_mem01_ctrl_cc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => ddr4_mem01_ctrl_cc_M_AXI_AWREADY,
m_axi_awvalid => ddr4_mem01_ctrl_cc_M_AXI_AWVALID,
m_axi_bready => ddr4_mem01_ctrl_cc_M_AXI_BREADY,
m_axi_bresp(1 downto 0) => ddr4_mem01_ctrl_cc_M_AXI_BRESP(1 downto 0),
m_axi_bvalid => ddr4_mem01_ctrl_cc_M_AXI_BVALID,
m_axi_rdata(31 downto 0) => ddr4_mem01_ctrl_cc_M_AXI_RDATA(31 downto 0),
m_axi_rready => ddr4_mem01_ctrl_cc_M_AXI_RREADY,
m_axi_rresp(1 downto 0) => ddr4_mem01_ctrl_cc_M_AXI_RRESP(1 downto 0),
m_axi_rvalid => ddr4_mem01_ctrl_cc_M_AXI_RVALID,
m_axi_wdata(31 downto 0) => ddr4_mem01_ctrl_cc_M_AXI_WDATA(31 downto 0),
m_axi_wready => ddr4_mem01_ctrl_cc_M_AXI_WREADY,
m_axi_wstrb(3 downto 0) => NLW_ddr4_mem01_ctrl_cc_m_axi_wstrb_UNCONNECTED(3 downto 0),
m_axi_wvalid => ddr4_mem01_ctrl_cc_M_AXI_WVALID,
s_axi_aclk => aclk1,
s_axi_araddr(31 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_ARADDR(31 downto 0),
s_axi_aresetn => psr_ctrl_interconnect_interconnect_aresetn,
s_axi_arprot(2 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_ARPROT(2 downto 0),
s_axi_arready => vip_ctrl_DDR4_MEM01_M_AXI_ARREADY,
s_axi_arvalid => vip_ctrl_DDR4_MEM01_M_AXI_ARVALID,
s_axi_awaddr(31 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_AWPROT(2 downto 0),
s_axi_awready => vip_ctrl_DDR4_MEM01_M_AXI_AWREADY,
s_axi_awvalid => vip_ctrl_DDR4_MEM01_M_AXI_AWVALID,
s_axi_bready => vip_ctrl_DDR4_MEM01_M_AXI_BREADY,
s_axi_bresp(1 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_BRESP(1 downto 0),
s_axi_bvalid => vip_ctrl_DDR4_MEM01_M_AXI_BVALID,
s_axi_rdata(31 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_RDATA(31 downto 0),
s_axi_rready => vip_ctrl_DDR4_MEM01_M_AXI_RREADY,
s_axi_rresp(1 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_RRESP(1 downto 0),
s_axi_rvalid => vip_ctrl_DDR4_MEM01_M_AXI_RVALID,
s_axi_wdata(31 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_WDATA(31 downto 0),
s_axi_wready => vip_ctrl_DDR4_MEM01_M_AXI_WREADY,
s_axi_wstrb(3 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_WSTRB(3 downto 0),
s_axi_wvalid => vip_ctrl_DDR4_MEM01_M_AXI_WVALID
);
interconnect_ddrmem_ctrl: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_interconnect_ddrmem_ctrl_0
port map (
aclk => aclk1,
aresetn => psr_ctrl_interconnect_interconnect_aresetn,
m_axi_araddr(31 downto 0) => interconnect_ddrmem_ctrl_M_AXI_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => interconnect_ddrmem_ctrl_M_AXI_ARPROT(2 downto 0),
m_axi_arready => interconnect_ddrmem_ctrl_M_AXI_ARREADY,
m_axi_arvalid => interconnect_ddrmem_ctrl_M_AXI_ARVALID,
m_axi_awaddr(31 downto 0) => interconnect_ddrmem_ctrl_M_AXI_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => interconnect_ddrmem_ctrl_M_AXI_AWPROT(2 downto 0),
m_axi_awready => interconnect_ddrmem_ctrl_M_AXI_AWREADY,
m_axi_awvalid => interconnect_ddrmem_ctrl_M_AXI_AWVALID,
m_axi_bready => interconnect_ddrmem_ctrl_M_AXI_BREADY,
m_axi_bresp(1 downto 0) => interconnect_ddrmem_ctrl_M_AXI_BRESP(1 downto 0),
m_axi_bvalid => interconnect_ddrmem_ctrl_M_AXI_BVALID,
m_axi_rdata(31 downto 0) => interconnect_ddrmem_ctrl_M_AXI_RDATA(31 downto 0),
m_axi_rready => interconnect_ddrmem_ctrl_M_AXI_RREADY,
m_axi_rresp(1 downto 0) => interconnect_ddrmem_ctrl_M_AXI_RRESP(1 downto 0),
m_axi_rvalid => interconnect_ddrmem_ctrl_M_AXI_RVALID,
m_axi_wdata(31 downto 0) => interconnect_ddrmem_ctrl_M_AXI_WDATA(31 downto 0),
m_axi_wready => interconnect_ddrmem_ctrl_M_AXI_WREADY,
m_axi_wstrb(3 downto 0) => interconnect_ddrmem_ctrl_M_AXI_WSTRB(3 downto 0),
m_axi_wvalid => interconnect_ddrmem_ctrl_M_AXI_WVALID,
s_axi_araddr(24 downto 0) => S_AXI_CTRL_araddr(24 downto 0),
s_axi_arprot(2 downto 0) => S_AXI_CTRL_arprot(2 downto 0),
s_axi_arready => S_AXI_CTRL_arready,
s_axi_arvalid => S_AXI_CTRL_arvalid,
s_axi_awaddr(24 downto 0) => S_AXI_CTRL_awaddr(24 downto 0),
s_axi_awprot(2 downto 0) => S_AXI_CTRL_awprot(2 downto 0),
s_axi_awready => S_AXI_CTRL_awready,
s_axi_awvalid => S_AXI_CTRL_awvalid,
s_axi_bready => S_AXI_CTRL_bready,
s_axi_bresp(1 downto 0) => S_AXI_CTRL_bresp(1 downto 0),
s_axi_bvalid => S_AXI_CTRL_bvalid,
s_axi_rdata(31 downto 0) => S_AXI_CTRL_rdata(31 downto 0),
s_axi_rready => S_AXI_CTRL_rready,
s_axi_rresp(1 downto 0) => S_AXI_CTRL_rresp(1 downto 0),
s_axi_rvalid => S_AXI_CTRL_rvalid,
s_axi_wdata(31 downto 0) => S_AXI_CTRL_wdata(31 downto 0),
s_axi_wready => S_AXI_CTRL_wready,
s_axi_wstrb(3 downto 0) => S_AXI_CTRL_wstrb(3 downto 0),
s_axi_wvalid => S_AXI_CTRL_wvalid
);
psr_ctrl_interconnect: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_psr_ctrl_interconnect_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_psr_ctrl_interconnect_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => aresetn,
interconnect_aresetn(0) => psr_ctrl_interconnect_interconnect_aresetn,
mb_debug_sys_rst => '0',
mb_reset => NLW_psr_ctrl_interconnect_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => NLW_psr_ctrl_interconnect_peripheral_aresetn_UNCONNECTED(0),
peripheral_reset(0) => NLW_psr_ctrl_interconnect_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => aclk1
);
psr_ddr4_mem01: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_psr_ddr4_mem01_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_psr_ddr4_mem01_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => vip_ui_rst_DDR4_MEM01_rst_out,
interconnect_aresetn(0) => psr_ddr4_mem01_interconnect_aresetn,
mb_debug_sys_rst => '0',
mb_reset => NLW_psr_ddr4_mem01_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => NLW_psr_ddr4_mem01_peripheral_aresetn_UNCONNECTED(0),
peripheral_reset(0) => NLW_psr_ddr4_mem01_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => \^ddr4_mem01_ui_clk\
);
vip_DDR4_MEM01: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_DDR4_MEM01_0
port map (
aclk => \^ddr4_mem01_ui_clk\,
aresetn => psr_ddr4_mem01_interconnect_aresetn,
m_axi_araddr(33 downto 0) => vip_DDR4_MEM01_M_AXI_ARADDR(33 downto 0),
m_axi_arburst(1 downto 0) => vip_DDR4_MEM01_M_AXI_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => vip_DDR4_MEM01_M_AXI_ARCACHE(3 downto 0),
m_axi_arlen(7 downto 0) => vip_DDR4_MEM01_M_AXI_ARLEN(7 downto 0),
m_axi_arlock(0) => vip_DDR4_MEM01_M_AXI_ARLOCK,
m_axi_arprot(2 downto 0) => vip_DDR4_MEM01_M_AXI_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => vip_DDR4_MEM01_M_AXI_ARQOS(3 downto 0),
m_axi_arready => vip_DDR4_MEM01_M_AXI_ARREADY,
m_axi_arvalid => vip_DDR4_MEM01_M_AXI_ARVALID,
m_axi_awaddr(33 downto 0) => vip_DDR4_MEM01_M_AXI_AWADDR(33 downto 0),
m_axi_awburst(1 downto 0) => vip_DDR4_MEM01_M_AXI_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => vip_DDR4_MEM01_M_AXI_AWCACHE(3 downto 0),
m_axi_awlen(7 downto 0) => vip_DDR4_MEM01_M_AXI_AWLEN(7 downto 0),
m_axi_awlock(0) => vip_DDR4_MEM01_M_AXI_AWLOCK,
m_axi_awprot(2 downto 0) => vip_DDR4_MEM01_M_AXI_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => vip_DDR4_MEM01_M_AXI_AWQOS(3 downto 0),
m_axi_awready => vip_DDR4_MEM01_M_AXI_AWREADY,
m_axi_awvalid => vip_DDR4_MEM01_M_AXI_AWVALID,
m_axi_bready => vip_DDR4_MEM01_M_AXI_BREADY,
m_axi_bresp(1 downto 0) => vip_DDR4_MEM01_M_AXI_BRESP(1 downto 0),
m_axi_bvalid => vip_DDR4_MEM01_M_AXI_BVALID,
m_axi_rdata(511 downto 0) => vip_DDR4_MEM01_M_AXI_RDATA(511 downto 0),
m_axi_rlast => vip_DDR4_MEM01_M_AXI_RLAST,
m_axi_rready => vip_DDR4_MEM01_M_AXI_RREADY,
m_axi_rresp(1 downto 0) => vip_DDR4_MEM01_M_AXI_RRESP(1 downto 0),
m_axi_rvalid => vip_DDR4_MEM01_M_AXI_RVALID,
m_axi_wdata(511 downto 0) => vip_DDR4_MEM01_M_AXI_WDATA(511 downto 0),
m_axi_wlast => vip_DDR4_MEM01_M_AXI_WLAST,
m_axi_wready => vip_DDR4_MEM01_M_AXI_WREADY,
m_axi_wstrb(63 downto 0) => vip_DDR4_MEM01_M_AXI_WSTRB(63 downto 0),
m_axi_wvalid => vip_DDR4_MEM01_M_AXI_WVALID,
s_axi_araddr(33 downto 0) => S_AXI_araddr(33 downto 0),
s_axi_arburst(1 downto 0) => S_AXI_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => S_AXI_arcache(3 downto 0),
s_axi_arlen(7 downto 0) => S_AXI_arlen(7 downto 0),
s_axi_arlock(0) => S_AXI_arlock(0),
s_axi_arprot(2 downto 0) => S_AXI_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => S_AXI_arqos(3 downto 0),
s_axi_arready => S_AXI_arready,
s_axi_arvalid => S_AXI_arvalid,
s_axi_awaddr(33 downto 0) => S_AXI_awaddr(33 downto 0),
s_axi_awburst(1 downto 0) => S_AXI_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => S_AXI_awcache(3 downto 0),
s_axi_awlen(7 downto 0) => S_AXI_awlen(7 downto 0),
s_axi_awlock(0) => S_AXI_awlock(0),
s_axi_awprot(2 downto 0) => S_AXI_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => S_AXI_awqos(3 downto 0),
s_axi_awready => S_AXI_awready,
s_axi_awvalid => S_AXI_awvalid,
s_axi_bready => S_AXI_bready,
s_axi_bresp(1 downto 0) => S_AXI_bresp(1 downto 0),
s_axi_bvalid => S_AXI_bvalid,
s_axi_rdata(511 downto 0) => S_AXI_rdata(511 downto 0),
s_axi_rlast => S_AXI_rlast,
s_axi_rready => S_AXI_rready,
s_axi_rresp(1 downto 0) => S_AXI_rresp(1 downto 0),
s_axi_rvalid => S_AXI_rvalid,
s_axi_wdata(511 downto 0) => S_AXI_wdata(511 downto 0),
s_axi_wlast => S_AXI_wlast,
s_axi_wready => S_AXI_wready,
s_axi_wstrb(63 downto 0) => S_AXI_wstrb(63 downto 0),
s_axi_wvalid => S_AXI_wvalid
);
vip_ctrl_DDR4_MEM01: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_ctrl_DDR4_MEM01_0
port map (
aclk => aclk1,
aresetn => psr_ctrl_interconnect_interconnect_aresetn,
m_axi_araddr(31 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_ARPROT(2 downto 0),
m_axi_arready => vip_ctrl_DDR4_MEM01_M_AXI_ARREADY,
m_axi_arvalid => vip_ctrl_DDR4_MEM01_M_AXI_ARVALID,
m_axi_awaddr(31 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_AWPROT(2 downto 0),
m_axi_awready => vip_ctrl_DDR4_MEM01_M_AXI_AWREADY,
m_axi_awvalid => vip_ctrl_DDR4_MEM01_M_AXI_AWVALID,
m_axi_bready => vip_ctrl_DDR4_MEM01_M_AXI_BREADY,
m_axi_bresp(1 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_BRESP(1 downto 0),
m_axi_bvalid => vip_ctrl_DDR4_MEM01_M_AXI_BVALID,
m_axi_rdata(31 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_RDATA(31 downto 0),
m_axi_rready => vip_ctrl_DDR4_MEM01_M_AXI_RREADY,
m_axi_rresp(1 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_RRESP(1 downto 0),
m_axi_rvalid => vip_ctrl_DDR4_MEM01_M_AXI_RVALID,
m_axi_wdata(31 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_WDATA(31 downto 0),
m_axi_wready => vip_ctrl_DDR4_MEM01_M_AXI_WREADY,
m_axi_wstrb(3 downto 0) => vip_ctrl_DDR4_MEM01_M_AXI_WSTRB(3 downto 0),
m_axi_wvalid => vip_ctrl_DDR4_MEM01_M_AXI_WVALID,
s_axi_araddr(31 downto 0) => interconnect_ddrmem_ctrl_M_AXI_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => interconnect_ddrmem_ctrl_M_AXI_ARPROT(2 downto 0),
s_axi_arready => interconnect_ddrmem_ctrl_M_AXI_ARREADY,
s_axi_arvalid => interconnect_ddrmem_ctrl_M_AXI_ARVALID,
s_axi_awaddr(31 downto 0) => interconnect_ddrmem_ctrl_M_AXI_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => interconnect_ddrmem_ctrl_M_AXI_AWPROT(2 downto 0),
s_axi_awready => interconnect_ddrmem_ctrl_M_AXI_AWREADY,
s_axi_awvalid => interconnect_ddrmem_ctrl_M_AXI_AWVALID,
s_axi_bready => interconnect_ddrmem_ctrl_M_AXI_BREADY,
s_axi_bresp(1 downto 0) => interconnect_ddrmem_ctrl_M_AXI_BRESP(1 downto 0),
s_axi_bvalid => interconnect_ddrmem_ctrl_M_AXI_BVALID,
s_axi_rdata(31 downto 0) => interconnect_ddrmem_ctrl_M_AXI_RDATA(31 downto 0),
s_axi_rready => interconnect_ddrmem_ctrl_M_AXI_RREADY,
s_axi_rresp(1 downto 0) => interconnect_ddrmem_ctrl_M_AXI_RRESP(1 downto 0),
s_axi_rvalid => interconnect_ddrmem_ctrl_M_AXI_RVALID,
s_axi_wdata(31 downto 0) => interconnect_ddrmem_ctrl_M_AXI_WDATA(31 downto 0),
s_axi_wready => interconnect_ddrmem_ctrl_M_AXI_WREADY,
s_axi_wstrb(3 downto 0) => interconnect_ddrmem_ctrl_M_AXI_WSTRB(3 downto 0),
s_axi_wvalid => interconnect_ddrmem_ctrl_M_AXI_WVALID
);
vip_ui_clk_DDR4_MEM01: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_ui_clk_DDR4_MEM01_0
port map (
clk_in => ddr4_mem01_c0_ddr4_ui_clk,
clk_out => \^ddr4_mem01_ui_clk\
);
vip_ui_rst_DDR4_MEM01: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_vip_ui_rst_DDR4_MEM01_0
port map (
rst_in => ddr4_mem01_c0_ddr4_ui_clk_sync_rst,
rst_out => vip_ui_rst_DDR4_MEM01_rst_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_imp_1YKOSPE is
port (
interconnect_aresetn1 : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
aclk2 : in STD_LOGIC;
aresetn : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_imp_1YKOSPE;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_imp_1YKOSPE is
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_psr_aclk2_SLR1_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_psr_aclk2_SLR1_0;
component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_psr_aclk_SLR1_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_psr_aclk_SLR1_0;
signal NLW_psr_aclk2_SLR1_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_psr_aclk2_SLR1_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_psr_aclk2_SLR1_peripheral_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_psr_aclk2_SLR1_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_psr_aclk_SLR1_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_psr_aclk_SLR1_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_psr_aclk_SLR1_peripheral_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_psr_aclk_SLR1_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of psr_aclk2_SLR1 : label is "proc_sys_reset,Vivado 2020.1";
attribute X_CORE_INFO of psr_aclk_SLR1 : label is "proc_sys_reset,Vivado 2020.1";
begin
psr_aclk2_SLR1: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_psr_aclk2_SLR1_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_psr_aclk2_SLR1_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => aresetn,
interconnect_aresetn(0) => interconnect_aresetn1(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_psr_aclk2_SLR1_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => NLW_psr_aclk2_SLR1_peripheral_aresetn_UNCONNECTED(0),
peripheral_reset(0) => NLW_psr_aclk2_SLR1_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => aclk2
);
psr_aclk_SLR1: component decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216_psr_aclk_SLR1_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_psr_aclk_SLR1_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => aresetn,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_psr_aclk_SLR1_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => NLW_psr_aclk_SLR1_peripheral_aresetn_UNCONNECTED(0),
peripheral_reset(0) => NLW_psr_aclk_SLR1_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216 is
port (
DDR4_MEM00_DIFF_CLK_clk_n : in STD_LOGIC;
DDR4_MEM00_DIFF_CLK_clk_p : in STD_LOGIC;
DDR4_MEM00_act_n : out STD_LOGIC;
DDR4_MEM00_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
DDR4_MEM00_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR4_MEM00_bg : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR4_MEM00_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM00_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM00_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM00_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM00_dq : inout STD_LOGIC_VECTOR ( 71 downto 0 );
DDR4_MEM00_dqs_c : inout STD_LOGIC_VECTOR ( 17 downto 0 );
DDR4_MEM00_dqs_t : inout STD_LOGIC_VECTOR ( 17 downto 0 );
DDR4_MEM00_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM00_par : out STD_LOGIC;
DDR4_MEM00_reset_n : out STD_LOGIC;
DDR4_MEM01_DIFF_CLK_clk_n : in STD_LOGIC;
DDR4_MEM01_DIFF_CLK_clk_p : in STD_LOGIC;
DDR4_MEM01_act_n : out STD_LOGIC;
DDR4_MEM01_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
DDR4_MEM01_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR4_MEM01_bg : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR4_MEM01_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM01_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM01_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM01_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM01_dq : inout STD_LOGIC_VECTOR ( 71 downto 0 );
DDR4_MEM01_dqs_c : inout STD_LOGIC_VECTOR ( 17 downto 0 );
DDR4_MEM01_dqs_t : inout STD_LOGIC_VECTOR ( 17 downto 0 );
DDR4_MEM01_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM01_par : out STD_LOGIC;
DDR4_MEM01_reset_n : out STD_LOGIC;
DDR4_MEM02_DIFF_CLK_clk_n : in STD_LOGIC;
DDR4_MEM02_DIFF_CLK_clk_p : in STD_LOGIC;
DDR4_MEM02_act_n : out STD_LOGIC;
DDR4_MEM02_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
DDR4_MEM02_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR4_MEM02_bg : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR4_MEM02_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM02_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM02_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM02_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM02_dq : inout STD_LOGIC_VECTOR ( 71 downto 0 );
DDR4_MEM02_dqs_c : inout STD_LOGIC_VECTOR ( 17 downto 0 );
DDR4_MEM02_dqs_t : inout STD_LOGIC_VECTOR ( 17 downto 0 );
DDR4_MEM02_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM02_par : out STD_LOGIC;
DDR4_MEM02_reset_n : out STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S00_AXI_wvalid : in STD_LOGIC;
S01_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arready : out STD_LOGIC;
S01_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arvalid : in STD_LOGIC;
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awready : out STD_LOGIC;
S01_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_bready : in STD_LOGIC;
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S01_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_rlast : out STD_LOGIC;
S01_AXI_rready : in STD_LOGIC;
S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_rvalid : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S01_AXI_wlast : in STD_LOGIC;
S01_AXI_wready : out STD_LOGIC;
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S01_AXI_wvalid : in STD_LOGIC;
S02_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S02_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arready : out STD_LOGIC;
S02_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arvalid : in STD_LOGIC;
S02_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S02_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awready : out STD_LOGIC;
S02_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awvalid : in STD_LOGIC;
S02_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_bready : in STD_LOGIC;
S02_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_bvalid : out STD_LOGIC;
S02_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S02_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_rlast : out STD_LOGIC;
S02_AXI_rready : in STD_LOGIC;
S02_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_rvalid : out STD_LOGIC;
S02_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S02_AXI_wlast : in STD_LOGIC;
S02_AXI_wready : out STD_LOGIC;
S02_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S02_AXI_wvalid : in STD_LOGIC;
S03_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S03_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S03_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S03_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_arready : out STD_LOGIC;
S03_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_arvalid : in STD_LOGIC;
S03_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S03_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S03_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S03_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_awready : out STD_LOGIC;
S03_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_awvalid : in STD_LOGIC;
S03_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_bready : in STD_LOGIC;
S03_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_bvalid : out STD_LOGIC;
S03_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S03_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_rlast : out STD_LOGIC;
S03_AXI_rready : in STD_LOGIC;
S03_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_rvalid : out STD_LOGIC;
S03_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S03_AXI_wlast : in STD_LOGIC;
S03_AXI_wready : out STD_LOGIC;
S03_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S03_AXI_wvalid : in STD_LOGIC;
S04_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S04_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S04_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S04_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S04_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_arready : out STD_LOGIC;
S04_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_arvalid : in STD_LOGIC;
S04_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S04_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S04_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S04_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S04_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_awready : out STD_LOGIC;
S04_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_awvalid : in STD_LOGIC;
S04_AXI_bready : in STD_LOGIC;
S04_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S04_AXI_bvalid : out STD_LOGIC;
S04_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S04_AXI_rlast : out STD_LOGIC;
S04_AXI_rready : in STD_LOGIC;
S04_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S04_AXI_rvalid : out STD_LOGIC;
S04_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S04_AXI_wlast : in STD_LOGIC;
S04_AXI_wready : out STD_LOGIC;
S04_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S04_AXI_wvalid : in STD_LOGIC;
S05_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S05_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S05_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S05_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S05_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_arready : out STD_LOGIC;
S05_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_arvalid : in STD_LOGIC;
S05_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S05_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S05_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S05_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S05_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_awready : out STD_LOGIC;
S05_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_awvalid : in STD_LOGIC;
S05_AXI_bready : in STD_LOGIC;
S05_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S05_AXI_bvalid : out STD_LOGIC;
S05_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S05_AXI_rlast : out STD_LOGIC;
S05_AXI_rready : in STD_LOGIC;
S05_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S05_AXI_rvalid : out STD_LOGIC;
S05_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S05_AXI_wlast : in STD_LOGIC;
S05_AXI_wready : out STD_LOGIC;
S05_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S05_AXI_wvalid : in STD_LOGIC;
S_AXI_CTRL_araddr : in STD_LOGIC_VECTOR ( 24 downto 0 );
S_AXI_CTRL_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_CTRL_arready : out STD_LOGIC;
S_AXI_CTRL_arvalid : in STD_LOGIC;
S_AXI_CTRL_awaddr : in STD_LOGIC_VECTOR ( 24 downto 0 );
S_AXI_CTRL_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_CTRL_awready : out STD_LOGIC;
S_AXI_CTRL_awvalid : in STD_LOGIC;
S_AXI_CTRL_bready : in STD_LOGIC;
S_AXI_CTRL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_CTRL_bvalid : out STD_LOGIC;
S_AXI_CTRL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_rready : in STD_LOGIC;
S_AXI_CTRL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_CTRL_rvalid : out STD_LOGIC;
S_AXI_CTRL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_wready : out STD_LOGIC;
S_AXI_CTRL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_CTRL_wvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
aclk1 : in STD_LOGIC;
aclk2 : in STD_LOGIC;
aresetn : in STD_LOGIC;
ddr4_mem00_sys_rst : in STD_LOGIC;
ddr4_mem00_ui_clk : out STD_LOGIC;
ddr4_mem01_sys_rst : in STD_LOGIC;
ddr4_mem01_ui_clk : out STD_LOGIC;
ddr4_mem02_sys_rst : in STD_LOGIC;
ddr4_mem02_ui_clk : out STD_LOGIC;
ddr4_mem_calib_complete : out STD_LOGIC;
ddr4_mem_calib_vec : out STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216 : entity is "pfm_dynamic_memory_subsystem_0.hwdef";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216 is
signal \<const0>\ : STD_LOGIC;
signal \^ddr4_mem01_ui_clk\ : STD_LOGIC;
signal interconnect_DDR4_MEM01_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 33 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_ARLOCK : STD_LOGIC;
signal interconnect_DDR4_MEM01_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_ARREADY : STD_LOGIC;
signal interconnect_DDR4_MEM01_M00_AXI_ARVALID : STD_LOGIC;
signal interconnect_DDR4_MEM01_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 33 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_AWLOCK : STD_LOGIC;
signal interconnect_DDR4_MEM01_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_AWREADY : STD_LOGIC;
signal interconnect_DDR4_MEM01_M00_AXI_AWVALID : STD_LOGIC;
signal interconnect_DDR4_MEM01_M00_AXI_BREADY : STD_LOGIC;
signal interconnect_DDR4_MEM01_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_BVALID : STD_LOGIC;
signal interconnect_DDR4_MEM01_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_RLAST : STD_LOGIC;
signal interconnect_DDR4_MEM01_M00_AXI_RREADY : STD_LOGIC;
signal interconnect_DDR4_MEM01_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_RVALID : STD_LOGIC;
signal interconnect_DDR4_MEM01_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 511 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_WLAST : STD_LOGIC;
signal interconnect_DDR4_MEM01_M00_AXI_WREADY : STD_LOGIC;
signal interconnect_DDR4_MEM01_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 63 downto 0 );
signal interconnect_DDR4_MEM01_M00_AXI_WVALID : STD_LOGIC;
signal psr_aclk2_SLR1_interconnect_aresetn : STD_LOGIC;
signal psr_aclk_SLR1_interconnect_aresetn : STD_LOGIC;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of DDR4_MEM00_DIFF_CLK_clk_n : signal is "xilinx.com:interface:diff_clock:1.0 DDR4_MEM00_DIFF_CLK CLK_N";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of DDR4_MEM00_DIFF_CLK_clk_n : signal is "XIL_INTERFACENAME DDR4_MEM00_DIFF_CLK, CAN_DEBUG false, FREQ_HZ 300000000";
attribute X_INTERFACE_INFO of DDR4_MEM00_DIFF_CLK_clk_p : signal is "xilinx.com:interface:diff_clock:1.0 DDR4_MEM00_DIFF_CLK CLK_P";
attribute X_INTERFACE_INFO of DDR4_MEM00_act_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 ACT_N";
attribute X_INTERFACE_PARAMETER of DDR4_MEM00_act_n : signal is "XIL_INTERFACENAME DDR4_MEM00, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250";
attribute X_INTERFACE_INFO of DDR4_MEM00_par : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 PAR";
attribute X_INTERFACE_INFO of DDR4_MEM00_reset_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 RESET_N";
attribute X_INTERFACE_INFO of DDR4_MEM01_DIFF_CLK_clk_n : signal is "xilinx.com:interface:diff_clock:1.0 DDR4_MEM01_DIFF_CLK CLK_N";
attribute X_INTERFACE_PARAMETER of DDR4_MEM01_DIFF_CLK_clk_n : signal is "XIL_INTERFACENAME DDR4_MEM01_DIFF_CLK, CAN_DEBUG false, FREQ_HZ 300000000";
attribute X_INTERFACE_INFO of DDR4_MEM01_DIFF_CLK_clk_p : signal is "xilinx.com:interface:diff_clock:1.0 DDR4_MEM01_DIFF_CLK CLK_P";
attribute X_INTERFACE_INFO of DDR4_MEM01_act_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 ACT_N";
attribute X_INTERFACE_PARAMETER of DDR4_MEM01_act_n : signal is "XIL_INTERFACENAME DDR4_MEM01, AXI_ARBITRATION_SCHEME RD_PRI_REG, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 17, CAS_WRITE_LATENCY 12, CS_ENABLED true, CUSTOM_PARTS no_file_loaded, DATA_MASK_ENABLED NONE, DATA_WIDTH 72, MEMORY_PART MTA18ASF2G72PZ-2G3, MEMORY_TYPE RDIMMs, MEM_ADDR_MAP ROW_COLUMN_BANK_INTLV, SLOT Single, TIMEPERIOD_PS 833";
attribute X_INTERFACE_INFO of DDR4_MEM01_par : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 PAR";
attribute X_INTERFACE_INFO of DDR4_MEM01_reset_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 RESET_N";
attribute X_INTERFACE_INFO of DDR4_MEM02_DIFF_CLK_clk_n : signal is "xilinx.com:interface:diff_clock:1.0 DDR4_MEM02_DIFF_CLK CLK_N";
attribute X_INTERFACE_PARAMETER of DDR4_MEM02_DIFF_CLK_clk_n : signal is "XIL_INTERFACENAME DDR4_MEM02_DIFF_CLK, CAN_DEBUG false, FREQ_HZ 300000000";
attribute X_INTERFACE_INFO of DDR4_MEM02_DIFF_CLK_clk_p : signal is "xilinx.com:interface:diff_clock:1.0 DDR4_MEM02_DIFF_CLK CLK_P";
attribute X_INTERFACE_INFO of DDR4_MEM02_act_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 ACT_N";
attribute X_INTERFACE_PARAMETER of DDR4_MEM02_act_n : signal is "XIL_INTERFACENAME DDR4_MEM02, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250";
attribute X_INTERFACE_INFO of DDR4_MEM02_par : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 PAR";
attribute X_INTERFACE_INFO of DDR4_MEM02_reset_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 RESET_N";
attribute X_INTERFACE_INFO of M00_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY";
attribute X_INTERFACE_INFO of M00_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID";
attribute X_INTERFACE_INFO of M00_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY";
attribute X_INTERFACE_INFO of M00_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID";
attribute X_INTERFACE_INFO of M00_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BREADY";
attribute X_INTERFACE_INFO of M00_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BVALID";
attribute X_INTERFACE_INFO of M00_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RLAST";
attribute X_INTERFACE_INFO of M00_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RREADY";
attribute X_INTERFACE_INFO of M00_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RVALID";
attribute X_INTERFACE_INFO of M00_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WLAST";
attribute X_INTERFACE_INFO of M00_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WREADY";
attribute X_INTERFACE_INFO of M00_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WVALID";
attribute X_INTERFACE_INFO of S00_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
attribute X_INTERFACE_INFO of S00_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
attribute X_INTERFACE_INFO of S00_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
attribute X_INTERFACE_INFO of S00_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
attribute X_INTERFACE_INFO of S00_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
attribute X_INTERFACE_INFO of S00_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
attribute X_INTERFACE_INFO of S00_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RLAST";
attribute X_INTERFACE_INFO of S00_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
attribute X_INTERFACE_INFO of S00_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
attribute X_INTERFACE_INFO of S00_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WLAST";
attribute X_INTERFACE_INFO of S00_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
attribute X_INTERFACE_INFO of S00_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
attribute X_INTERFACE_INFO of S01_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARREADY";
attribute X_INTERFACE_INFO of S01_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARVALID";
attribute X_INTERFACE_INFO of S01_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWREADY";
attribute X_INTERFACE_INFO of S01_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWVALID";
attribute X_INTERFACE_INFO of S01_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BREADY";
attribute X_INTERFACE_INFO of S01_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BVALID";
attribute X_INTERFACE_INFO of S01_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RLAST";
attribute X_INTERFACE_INFO of S01_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RREADY";
attribute X_INTERFACE_INFO of S01_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RVALID";
attribute X_INTERFACE_INFO of S01_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WLAST";
attribute X_INTERFACE_INFO of S01_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WREADY";
attribute X_INTERFACE_INFO of S01_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WVALID";
attribute X_INTERFACE_INFO of S02_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARREADY";
attribute X_INTERFACE_INFO of S02_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARVALID";
attribute X_INTERFACE_INFO of S02_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWREADY";
attribute X_INTERFACE_INFO of S02_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWVALID";
attribute X_INTERFACE_INFO of S02_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S02_AXI BREADY";
attribute X_INTERFACE_INFO of S02_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI BVALID";
attribute X_INTERFACE_INFO of S02_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RLAST";
attribute X_INTERFACE_INFO of S02_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RREADY";
attribute X_INTERFACE_INFO of S02_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RVALID";
attribute X_INTERFACE_INFO of S02_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WLAST";
attribute X_INTERFACE_INFO of S02_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WREADY";
attribute X_INTERFACE_INFO of S02_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WVALID";
attribute X_INTERFACE_INFO of S03_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARREADY";
attribute X_INTERFACE_INFO of S03_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARVALID";
attribute X_INTERFACE_INFO of S03_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWREADY";
attribute X_INTERFACE_INFO of S03_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWVALID";
attribute X_INTERFACE_INFO of S03_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S03_AXI BREADY";
attribute X_INTERFACE_INFO of S03_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI BVALID";
attribute X_INTERFACE_INFO of S03_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RLAST";
attribute X_INTERFACE_INFO of S03_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RREADY";
attribute X_INTERFACE_INFO of S03_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RVALID";
attribute X_INTERFACE_INFO of S03_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WLAST";
attribute X_INTERFACE_INFO of S03_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WREADY";
attribute X_INTERFACE_INFO of S03_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WVALID";
attribute X_INTERFACE_INFO of S04_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARREADY";
attribute X_INTERFACE_INFO of S04_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARVALID";
attribute X_INTERFACE_INFO of S04_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWREADY";
attribute X_INTERFACE_INFO of S04_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWVALID";
attribute X_INTERFACE_INFO of S04_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S04_AXI BREADY";
attribute X_INTERFACE_INFO of S04_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI BVALID";
attribute X_INTERFACE_INFO of S04_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RLAST";
attribute X_INTERFACE_INFO of S04_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RREADY";
attribute X_INTERFACE_INFO of S04_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RVALID";
attribute X_INTERFACE_INFO of S04_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WLAST";
attribute X_INTERFACE_INFO of S04_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WREADY";
attribute X_INTERFACE_INFO of S04_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WVALID";
attribute X_INTERFACE_INFO of S05_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARREADY";
attribute X_INTERFACE_INFO of S05_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARVALID";
attribute X_INTERFACE_INFO of S05_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWREADY";
attribute X_INTERFACE_INFO of S05_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWVALID";
attribute X_INTERFACE_INFO of S05_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S05_AXI BREADY";
attribute X_INTERFACE_INFO of S05_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI BVALID";
attribute X_INTERFACE_INFO of S05_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RLAST";
attribute X_INTERFACE_INFO of S05_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RREADY";
attribute X_INTERFACE_INFO of S05_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RVALID";
attribute X_INTERFACE_INFO of S05_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WLAST";
attribute X_INTERFACE_INFO of S05_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WREADY";
attribute X_INTERFACE_INFO of S05_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WVALID";
attribute X_INTERFACE_INFO of S_AXI_CTRL_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL ARREADY";
attribute X_INTERFACE_INFO of S_AXI_CTRL_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL ARVALID";
attribute X_INTERFACE_INFO of S_AXI_CTRL_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL AWREADY";
attribute X_INTERFACE_INFO of S_AXI_CTRL_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL AWVALID";
attribute X_INTERFACE_INFO of S_AXI_CTRL_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL BREADY";
attribute X_INTERFACE_INFO of S_AXI_CTRL_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL BVALID";
attribute X_INTERFACE_INFO of S_AXI_CTRL_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL RREADY";
attribute X_INTERFACE_INFO of S_AXI_CTRL_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL RVALID";
attribute X_INTERFACE_INFO of S_AXI_CTRL_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL WREADY";
attribute X_INTERFACE_INFO of S_AXI_CTRL_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL WVALID";
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK CLK";
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.ACLK, ASSOCIATED_BUSIF S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI, ASSOCIATED_CLKEN m_sc_aclken, CLK_DOMAIN pfm_dynamic_clkwiz_kernel_clk_out1, FREQ_HZ 300000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000";
attribute X_INTERFACE_INFO of aclk1 : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK1 CLK";
attribute X_INTERFACE_PARAMETER of aclk1 : signal is "XIL_INTERFACENAME CLK.ACLK1, ASSOCIATED_BUSIF S_AXI_CTRL, CLK_DOMAIN pfm_dynamic_clkwiz_sysclks_clk_out2, FREQ_HZ 50925925, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000";
attribute X_INTERFACE_INFO of aclk2 : signal is "xilinx.com:signal:clock:1.0 CLK.ACLK2 CLK";
attribute X_INTERFACE_PARAMETER of aclk2 : signal is "XIL_INTERFACENAME CLK.ACLK2, ASSOCIATED_BUSIF M00_AXI, ASSOCIATED_CLKEN m_sc_aclken, CLK_DOMAIN pfm_dynamic_ddrmem_1_c0_ddr4_ui_clk, FREQ_HZ 300000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.ARESETN RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.ARESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of ddr4_mem00_sys_rst : signal is "xilinx.com:signal:reset:1.0 RST.DDR4_MEM00_SYS_RST RST";
attribute X_INTERFACE_PARAMETER of ddr4_mem00_sys_rst : signal is "XIL_INTERFACENAME RST.DDR4_MEM00_SYS_RST, INSERT_VIP 0, POLARITY ACTIVE_HIGH";
attribute X_INTERFACE_INFO of ddr4_mem00_ui_clk : signal is "xilinx.com:signal:clock:1.0 CLK.DDR4_MEM00_UI_CLK CLK";
attribute X_INTERFACE_PARAMETER of ddr4_mem00_ui_clk : signal is "XIL_INTERFACENAME CLK.DDR4_MEM00_UI_CLK, CLK_DOMAIN pfm_dynamic_memory_subsystem_0_ddr4_mem00_ui_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000";
attribute X_INTERFACE_INFO of ddr4_mem01_sys_rst : signal is "xilinx.com:signal:reset:1.0 RST.DDR4_MEM01_SYS_RST RST";
attribute X_INTERFACE_PARAMETER of ddr4_mem01_sys_rst : signal is "XIL_INTERFACENAME RST.DDR4_MEM01_SYS_RST, INSERT_VIP 0, POLARITY ACTIVE_HIGH";
attribute X_INTERFACE_INFO of ddr4_mem01_ui_clk : signal is "xilinx.com:signal:clock:1.0 CLK.DDR4_MEM01_UI_CLK CLK";
attribute X_INTERFACE_PARAMETER of ddr4_mem01_ui_clk : signal is "XIL_INTERFACENAME CLK.DDR4_MEM01_UI_CLK, CLK_DOMAIN bd_d216_ddr4_mem01_0_c0_ddr4_ui_clk, FREQ_HZ 300000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.00";
attribute X_INTERFACE_INFO of ddr4_mem02_sys_rst : signal is "xilinx.com:signal:reset:1.0 RST.DDR4_MEM02_SYS_RST RST";
attribute X_INTERFACE_PARAMETER of ddr4_mem02_sys_rst : signal is "XIL_INTERFACENAME RST.DDR4_MEM02_SYS_RST, INSERT_VIP 0, POLARITY ACTIVE_HIGH";
attribute X_INTERFACE_INFO of ddr4_mem02_ui_clk : signal is "xilinx.com:signal:clock:1.0 CLK.DDR4_MEM02_UI_CLK CLK";
attribute X_INTERFACE_PARAMETER of ddr4_mem02_ui_clk : signal is "XIL_INTERFACENAME CLK.DDR4_MEM02_UI_CLK, CLK_DOMAIN pfm_dynamic_memory_subsystem_0_ddr4_mem02_ui_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.000";
attribute X_INTERFACE_INFO of ddr4_mem_calib_complete : signal is "xilinx.com:signal:data:1.0 DATA.DDR4_MEM_CALIB_COMPLETE DATA";
attribute X_INTERFACE_PARAMETER of ddr4_mem_calib_complete : signal is "XIL_INTERFACENAME DATA.DDR4_MEM_CALIB_COMPLETE, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of DDR4_MEM00_adr : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 ADR";
attribute X_INTERFACE_INFO of DDR4_MEM00_ba : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 BA";
attribute X_INTERFACE_INFO of DDR4_MEM00_bg : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 BG";
attribute X_INTERFACE_INFO of DDR4_MEM00_ck_c : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 CK_C";
attribute X_INTERFACE_INFO of DDR4_MEM00_ck_t : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 CK_T";
attribute X_INTERFACE_INFO of DDR4_MEM00_cke : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 CKE";
attribute X_INTERFACE_INFO of DDR4_MEM00_cs_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 CS_N";
attribute X_INTERFACE_INFO of DDR4_MEM00_dq : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 DQ";
attribute X_INTERFACE_INFO of DDR4_MEM00_dqs_c : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 DQS_C";
attribute X_INTERFACE_INFO of DDR4_MEM00_dqs_t : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 DQS_T";
attribute X_INTERFACE_INFO of DDR4_MEM00_odt : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 ODT";
attribute X_INTERFACE_INFO of DDR4_MEM01_adr : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 ADR";
attribute X_INTERFACE_INFO of DDR4_MEM01_ba : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 BA";
attribute X_INTERFACE_INFO of DDR4_MEM01_bg : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 BG";
attribute X_INTERFACE_INFO of DDR4_MEM01_ck_c : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 CK_C";
attribute X_INTERFACE_INFO of DDR4_MEM01_ck_t : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 CK_T";
attribute X_INTERFACE_INFO of DDR4_MEM01_cke : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 CKE";
attribute X_INTERFACE_INFO of DDR4_MEM01_cs_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 CS_N";
attribute X_INTERFACE_INFO of DDR4_MEM01_dq : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 DQ";
attribute X_INTERFACE_INFO of DDR4_MEM01_dqs_c : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 DQS_C";
attribute X_INTERFACE_INFO of DDR4_MEM01_dqs_t : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 DQS_T";
attribute X_INTERFACE_INFO of DDR4_MEM01_odt : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 ODT";
attribute X_INTERFACE_INFO of DDR4_MEM02_adr : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 ADR";
attribute X_INTERFACE_INFO of DDR4_MEM02_ba : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 BA";
attribute X_INTERFACE_INFO of DDR4_MEM02_bg : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 BG";
attribute X_INTERFACE_INFO of DDR4_MEM02_ck_c : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 CK_C";
attribute X_INTERFACE_INFO of DDR4_MEM02_ck_t : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 CK_T";
attribute X_INTERFACE_INFO of DDR4_MEM02_cke : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 CKE";
attribute X_INTERFACE_INFO of DDR4_MEM02_cs_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 CS_N";
attribute X_INTERFACE_INFO of DDR4_MEM02_dq : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 DQ";
attribute X_INTERFACE_INFO of DDR4_MEM02_dqs_c : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 DQS_C";
attribute X_INTERFACE_INFO of DDR4_MEM02_dqs_t : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 DQS_T";
attribute X_INTERFACE_INFO of DDR4_MEM02_odt : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 ODT";
attribute X_INTERFACE_INFO of M00_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of M00_AXI_araddr : signal is "XIL_INTERFACENAME M00_AXI, ADDR_WIDTH 39, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN pfm_dynamic_ddrmem_1_c0_ddr4_ui_clk, DATA_WIDTH 512, FREQ_HZ 300000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 1, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of M00_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST";
attribute X_INTERFACE_INFO of M00_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE";
attribute X_INTERFACE_INFO of M00_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN";
attribute X_INTERFACE_INFO of M00_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK";
attribute X_INTERFACE_INFO of M00_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT";
attribute X_INTERFACE_INFO of M00_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS";
attribute X_INTERFACE_INFO of M00_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION";
attribute X_INTERFACE_INFO of M00_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE";
attribute X_INTERFACE_INFO of M00_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR";
attribute X_INTERFACE_INFO of M00_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST";
attribute X_INTERFACE_INFO of M00_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE";
attribute X_INTERFACE_INFO of M00_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN";
attribute X_INTERFACE_INFO of M00_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK";
attribute X_INTERFACE_INFO of M00_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT";
attribute X_INTERFACE_INFO of M00_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS";
attribute X_INTERFACE_INFO of M00_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION";
attribute X_INTERFACE_INFO of M00_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE";
attribute X_INTERFACE_INFO of M00_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BRESP";
attribute X_INTERFACE_INFO of M00_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RDATA";
attribute X_INTERFACE_INFO of M00_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RRESP";
attribute X_INTERFACE_INFO of M00_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WDATA";
attribute X_INTERFACE_INFO of M00_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB";
attribute X_INTERFACE_INFO of S00_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of S00_AXI_araddr : signal is "XIL_INTERFACENAME S00_AXI, ADDR_WIDTH 39, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN pfm_dynamic_clkwiz_kernel_clk_out1, DATA_WIDTH 512, FREQ_HZ 300000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 4, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 2, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 2, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of S00_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST";
attribute X_INTERFACE_INFO of S00_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE";
attribute X_INTERFACE_INFO of S00_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARID";
attribute X_INTERFACE_INFO of S00_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN";
attribute X_INTERFACE_INFO of S00_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK";
attribute X_INTERFACE_INFO of S00_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
attribute X_INTERFACE_INFO of S00_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS";
attribute X_INTERFACE_INFO of S00_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREGION";
attribute X_INTERFACE_INFO of S00_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE";
attribute X_INTERFACE_INFO of S00_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
attribute X_INTERFACE_INFO of S00_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST";
attribute X_INTERFACE_INFO of S00_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE";
attribute X_INTERFACE_INFO of S00_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWID";
attribute X_INTERFACE_INFO of S00_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN";
attribute X_INTERFACE_INFO of S00_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK";
attribute X_INTERFACE_INFO of S00_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
attribute X_INTERFACE_INFO of S00_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS";
attribute X_INTERFACE_INFO of S00_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREGION";
attribute X_INTERFACE_INFO of S00_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE";
attribute X_INTERFACE_INFO of S00_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BID";
attribute X_INTERFACE_INFO of S00_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
attribute X_INTERFACE_INFO of S00_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
attribute X_INTERFACE_INFO of S00_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RID";
attribute X_INTERFACE_INFO of S00_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
attribute X_INTERFACE_INFO of S00_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
attribute X_INTERFACE_INFO of S00_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
attribute X_INTERFACE_INFO of S01_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of S01_AXI_araddr : signal is "XIL_INTERFACENAME S01_AXI, ADDR_WIDTH 39, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN pfm_dynamic_clkwiz_kernel_clk_out1, DATA_WIDTH 512, FREQ_HZ 300000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 4, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 2, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 2, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of S01_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARBURST";
attribute X_INTERFACE_INFO of S01_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE";
attribute X_INTERFACE_INFO of S01_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARID";
attribute X_INTERFACE_INFO of S01_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARLEN";
attribute X_INTERFACE_INFO of S01_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK";
attribute X_INTERFACE_INFO of S01_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARPROT";
attribute X_INTERFACE_INFO of S01_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARQOS";
attribute X_INTERFACE_INFO of S01_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARREGION";
attribute X_INTERFACE_INFO of S01_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWADDR";
attribute X_INTERFACE_INFO of S01_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWBURST";
attribute X_INTERFACE_INFO of S01_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE";
attribute X_INTERFACE_INFO of S01_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWID";
attribute X_INTERFACE_INFO of S01_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWLEN";
attribute X_INTERFACE_INFO of S01_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK";
attribute X_INTERFACE_INFO of S01_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWPROT";
attribute X_INTERFACE_INFO of S01_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWQOS";
attribute X_INTERFACE_INFO of S01_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWREGION";
attribute X_INTERFACE_INFO of S01_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BID";
attribute X_INTERFACE_INFO of S01_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BRESP";
attribute X_INTERFACE_INFO of S01_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RDATA";
attribute X_INTERFACE_INFO of S01_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RID";
attribute X_INTERFACE_INFO of S01_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RRESP";
attribute X_INTERFACE_INFO of S01_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WDATA";
attribute X_INTERFACE_INFO of S01_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WSTRB";
attribute X_INTERFACE_INFO of S02_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of S02_AXI_araddr : signal is "XIL_INTERFACENAME S02_AXI, ADDR_WIDTH 39, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN pfm_dynamic_clkwiz_kernel_clk_out1, DATA_WIDTH 512, FREQ_HZ 300000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 4, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 2, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 2, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of S02_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARBURST";
attribute X_INTERFACE_INFO of S02_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARCACHE";
attribute X_INTERFACE_INFO of S02_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARID";
attribute X_INTERFACE_INFO of S02_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARLEN";
attribute X_INTERFACE_INFO of S02_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARLOCK";
attribute X_INTERFACE_INFO of S02_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARPROT";
attribute X_INTERFACE_INFO of S02_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARQOS";
attribute X_INTERFACE_INFO of S02_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARREGION";
attribute X_INTERFACE_INFO of S02_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWADDR";
attribute X_INTERFACE_INFO of S02_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWBURST";
attribute X_INTERFACE_INFO of S02_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWCACHE";
attribute X_INTERFACE_INFO of S02_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWID";
attribute X_INTERFACE_INFO of S02_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWLEN";
attribute X_INTERFACE_INFO of S02_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWLOCK";
attribute X_INTERFACE_INFO of S02_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWPROT";
attribute X_INTERFACE_INFO of S02_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWQOS";
attribute X_INTERFACE_INFO of S02_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWREGION";
attribute X_INTERFACE_INFO of S02_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI BID";
attribute X_INTERFACE_INFO of S02_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S02_AXI BRESP";
attribute X_INTERFACE_INFO of S02_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RDATA";
attribute X_INTERFACE_INFO of S02_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RID";
attribute X_INTERFACE_INFO of S02_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RRESP";
attribute X_INTERFACE_INFO of S02_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WDATA";
attribute X_INTERFACE_INFO of S02_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WSTRB";
attribute X_INTERFACE_INFO of S03_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of S03_AXI_araddr : signal is "XIL_INTERFACENAME S03_AXI, ADDR_WIDTH 39, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN pfm_dynamic_clkwiz_kernel_clk_out1, DATA_WIDTH 512, FREQ_HZ 300000000, HAS_BRESP 1, HAS_BURST 1, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 4, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 2, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 2, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of S03_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARBURST";
attribute X_INTERFACE_INFO of S03_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARCACHE";
attribute X_INTERFACE_INFO of S03_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARID";
attribute X_INTERFACE_INFO of S03_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARLEN";
attribute X_INTERFACE_INFO of S03_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARLOCK";
attribute X_INTERFACE_INFO of S03_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARPROT";
attribute X_INTERFACE_INFO of S03_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARQOS";
attribute X_INTERFACE_INFO of S03_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARREGION";
attribute X_INTERFACE_INFO of S03_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARSIZE";
attribute X_INTERFACE_INFO of S03_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWADDR";
attribute X_INTERFACE_INFO of S03_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWBURST";
attribute X_INTERFACE_INFO of S03_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWCACHE";
attribute X_INTERFACE_INFO of S03_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWID";
attribute X_INTERFACE_INFO of S03_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWLEN";
attribute X_INTERFACE_INFO of S03_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWLOCK";
attribute X_INTERFACE_INFO of S03_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWPROT";
attribute X_INTERFACE_INFO of S03_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWQOS";
attribute X_INTERFACE_INFO of S03_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWREGION";
attribute X_INTERFACE_INFO of S03_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWSIZE";
attribute X_INTERFACE_INFO of S03_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI BID";
attribute X_INTERFACE_INFO of S03_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S03_AXI BRESP";
attribute X_INTERFACE_INFO of S03_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RDATA";
attribute X_INTERFACE_INFO of S03_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RID";
attribute X_INTERFACE_INFO of S03_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RRESP";
attribute X_INTERFACE_INFO of S03_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WDATA";
attribute X_INTERFACE_INFO of S03_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WSTRB";
attribute X_INTERFACE_INFO of S04_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of S04_AXI_araddr : signal is "XIL_INTERFACENAME S04_AXI, ADDR_WIDTH 39, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN pfm_dynamic_clkwiz_kernel_clk_out1, DATA_WIDTH 512, FREQ_HZ 300000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of S04_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARCACHE";
attribute X_INTERFACE_INFO of S04_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARLEN";
attribute X_INTERFACE_INFO of S04_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARLOCK";
attribute X_INTERFACE_INFO of S04_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARPROT";
attribute X_INTERFACE_INFO of S04_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARQOS";
attribute X_INTERFACE_INFO of S04_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARREGION";
attribute X_INTERFACE_INFO of S04_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWADDR";
attribute X_INTERFACE_INFO of S04_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWCACHE";
attribute X_INTERFACE_INFO of S04_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWLEN";
attribute X_INTERFACE_INFO of S04_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWLOCK";
attribute X_INTERFACE_INFO of S04_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWPROT";
attribute X_INTERFACE_INFO of S04_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWQOS";
attribute X_INTERFACE_INFO of S04_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWREGION";
attribute X_INTERFACE_INFO of S04_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S04_AXI BRESP";
attribute X_INTERFACE_INFO of S04_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RDATA";
attribute X_INTERFACE_INFO of S04_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RRESP";
attribute X_INTERFACE_INFO of S04_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WDATA";
attribute X_INTERFACE_INFO of S04_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WSTRB";
attribute X_INTERFACE_INFO of S05_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARADDR";
attribute X_INTERFACE_PARAMETER of S05_AXI_araddr : signal is "XIL_INTERFACENAME S05_AXI, ADDR_WIDTH 39, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN pfm_dynamic_clkwiz_kernel_clk_out1, DATA_WIDTH 512, FREQ_HZ 300000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 1, HAS_LOCK 1, HAS_PROT 1, HAS_QOS 1, HAS_REGION 1, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 256, NUM_READ_OUTSTANDING 16, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 16, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of S05_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARCACHE";
attribute X_INTERFACE_INFO of S05_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARLEN";
attribute X_INTERFACE_INFO of S05_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARLOCK";
attribute X_INTERFACE_INFO of S05_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARPROT";
attribute X_INTERFACE_INFO of S05_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARQOS";
attribute X_INTERFACE_INFO of S05_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARREGION";
attribute X_INTERFACE_INFO of S05_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWADDR";
attribute X_INTERFACE_INFO of S05_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWCACHE";
attribute X_INTERFACE_INFO of S05_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWLEN";
attribute X_INTERFACE_INFO of S05_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWLOCK";
attribute X_INTERFACE_INFO of S05_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWPROT";
attribute X_INTERFACE_INFO of S05_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWQOS";
attribute X_INTERFACE_INFO of S05_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWREGION";
attribute X_INTERFACE_INFO of S05_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S05_AXI BRESP";
attribute X_INTERFACE_INFO of S05_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RDATA";
attribute X_INTERFACE_INFO of S05_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RRESP";
attribute X_INTERFACE_INFO of S05_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WDATA";
attribute X_INTERFACE_INFO of S05_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WSTRB";
attribute X_INTERFACE_INFO of S_AXI_CTRL_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL ARADDR";
attribute X_INTERFACE_PARAMETER of S_AXI_CTRL_araddr : signal is "XIL_INTERFACENAME S_AXI_CTRL, ADDR_WIDTH 25, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN pfm_dynamic_clkwiz_sysclks_clk_out2, DATA_WIDTH 32, FREQ_HZ 50925925, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, INSERT_VIP 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 2, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 2, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0";
attribute X_INTERFACE_INFO of S_AXI_CTRL_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL ARPROT";
attribute X_INTERFACE_INFO of S_AXI_CTRL_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL AWADDR";
attribute X_INTERFACE_INFO of S_AXI_CTRL_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL AWPROT";
attribute X_INTERFACE_INFO of S_AXI_CTRL_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL BRESP";
attribute X_INTERFACE_INFO of S_AXI_CTRL_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL RDATA";
attribute X_INTERFACE_INFO of S_AXI_CTRL_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL RRESP";
attribute X_INTERFACE_INFO of S_AXI_CTRL_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL WDATA";
attribute X_INTERFACE_INFO of S_AXI_CTRL_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL WSTRB";
attribute X_INTERFACE_INFO of ddr4_mem_calib_vec : signal is "xilinx.com:signal:data:1.0 DATA.DDR4_MEM_CALIB_VEC DATA";
attribute X_INTERFACE_PARAMETER of ddr4_mem_calib_vec : signal is "XIL_INTERFACENAME DATA.DDR4_MEM_CALIB_VEC, LAYERED_METADATA undef, PortWidth 3";
begin
DDR4_MEM00_act_n <= \<const0>\;
DDR4_MEM00_adr(16) <= \<const0>\;
DDR4_MEM00_adr(15) <= \<const0>\;
DDR4_MEM00_adr(14) <= \<const0>\;
DDR4_MEM00_adr(13) <= \<const0>\;
DDR4_MEM00_adr(12) <= \<const0>\;
DDR4_MEM00_adr(11) <= \<const0>\;
DDR4_MEM00_adr(10) <= \<const0>\;
DDR4_MEM00_adr(9) <= \<const0>\;
DDR4_MEM00_adr(8) <= \<const0>\;
DDR4_MEM00_adr(7) <= \<const0>\;
DDR4_MEM00_adr(6) <= \<const0>\;
DDR4_MEM00_adr(5) <= \<const0>\;
DDR4_MEM00_adr(4) <= \<const0>\;
DDR4_MEM00_adr(3) <= \<const0>\;
DDR4_MEM00_adr(2) <= \<const0>\;
DDR4_MEM00_adr(1) <= \<const0>\;
DDR4_MEM00_adr(0) <= \<const0>\;
DDR4_MEM00_ba(1) <= \<const0>\;
DDR4_MEM00_ba(0) <= \<const0>\;
DDR4_MEM00_bg(1) <= \<const0>\;
DDR4_MEM00_bg(0) <= \<const0>\;
DDR4_MEM00_ck_c(0) <= \<const0>\;
DDR4_MEM00_ck_t(0) <= \<const0>\;
DDR4_MEM00_cke(0) <= \<const0>\;
DDR4_MEM00_cs_n(0) <= \<const0>\;
DDR4_MEM00_odt(0) <= \<const0>\;
DDR4_MEM00_par <= \<const0>\;
DDR4_MEM00_reset_n <= \<const0>\;
DDR4_MEM02_act_n <= \<const0>\;
DDR4_MEM02_adr(16) <= \<const0>\;
DDR4_MEM02_adr(15) <= \<const0>\;
DDR4_MEM02_adr(14) <= \<const0>\;
DDR4_MEM02_adr(13) <= \<const0>\;
DDR4_MEM02_adr(12) <= \<const0>\;
DDR4_MEM02_adr(11) <= \<const0>\;
DDR4_MEM02_adr(10) <= \<const0>\;
DDR4_MEM02_adr(9) <= \<const0>\;
DDR4_MEM02_adr(8) <= \<const0>\;
DDR4_MEM02_adr(7) <= \<const0>\;
DDR4_MEM02_adr(6) <= \<const0>\;
DDR4_MEM02_adr(5) <= \<const0>\;
DDR4_MEM02_adr(4) <= \<const0>\;
DDR4_MEM02_adr(3) <= \<const0>\;
DDR4_MEM02_adr(2) <= \<const0>\;
DDR4_MEM02_adr(1) <= \<const0>\;
DDR4_MEM02_adr(0) <= \<const0>\;
DDR4_MEM02_ba(1) <= \<const0>\;
DDR4_MEM02_ba(0) <= \<const0>\;
DDR4_MEM02_bg(1) <= \<const0>\;
DDR4_MEM02_bg(0) <= \<const0>\;
DDR4_MEM02_ck_c(0) <= \<const0>\;
DDR4_MEM02_ck_t(0) <= \<const0>\;
DDR4_MEM02_cke(0) <= \<const0>\;
DDR4_MEM02_cs_n(0) <= \<const0>\;
DDR4_MEM02_odt(0) <= \<const0>\;
DDR4_MEM02_par <= \<const0>\;
DDR4_MEM02_reset_n <= \<const0>\;
S00_AXI_arready <= \<const0>\;
S00_AXI_awready <= \<const0>\;
S00_AXI_bid(3) <= \<const0>\;
S00_AXI_bid(2) <= \<const0>\;
S00_AXI_bid(1) <= \<const0>\;
S00_AXI_bid(0) <= \<const0>\;
S00_AXI_bresp(1) <= \<const0>\;
S00_AXI_bresp(0) <= \<const0>\;
S00_AXI_bvalid <= \<const0>\;
S00_AXI_rdata(511) <= \<const0>\;
S00_AXI_rdata(510) <= \<const0>\;
S00_AXI_rdata(509) <= \<const0>\;
S00_AXI_rdata(508) <= \<const0>\;
S00_AXI_rdata(507) <= \<const0>\;
S00_AXI_rdata(506) <= \<const0>\;
S00_AXI_rdata(505) <= \<const0>\;
S00_AXI_rdata(504) <= \<const0>\;
S00_AXI_rdata(503) <= \<const0>\;
S00_AXI_rdata(502) <= \<const0>\;
S00_AXI_rdata(501) <= \<const0>\;
S00_AXI_rdata(500) <= \<const0>\;
S00_AXI_rdata(499) <= \<const0>\;
S00_AXI_rdata(498) <= \<const0>\;
S00_AXI_rdata(497) <= \<const0>\;
S00_AXI_rdata(496) <= \<const0>\;
S00_AXI_rdata(495) <= \<const0>\;
S00_AXI_rdata(494) <= \<const0>\;
S00_AXI_rdata(493) <= \<const0>\;
S00_AXI_rdata(492) <= \<const0>\;
S00_AXI_rdata(491) <= \<const0>\;
S00_AXI_rdata(490) <= \<const0>\;
S00_AXI_rdata(489) <= \<const0>\;
S00_AXI_rdata(488) <= \<const0>\;
S00_AXI_rdata(487) <= \<const0>\;
S00_AXI_rdata(486) <= \<const0>\;
S00_AXI_rdata(485) <= \<const0>\;
S00_AXI_rdata(484) <= \<const0>\;
S00_AXI_rdata(483) <= \<const0>\;
S00_AXI_rdata(482) <= \<const0>\;
S00_AXI_rdata(481) <= \<const0>\;
S00_AXI_rdata(480) <= \<const0>\;
S00_AXI_rdata(479) <= \<const0>\;
S00_AXI_rdata(478) <= \<const0>\;
S00_AXI_rdata(477) <= \<const0>\;
S00_AXI_rdata(476) <= \<const0>\;
S00_AXI_rdata(475) <= \<const0>\;
S00_AXI_rdata(474) <= \<const0>\;
S00_AXI_rdata(473) <= \<const0>\;
S00_AXI_rdata(472) <= \<const0>\;
S00_AXI_rdata(471) <= \<const0>\;
S00_AXI_rdata(470) <= \<const0>\;
S00_AXI_rdata(469) <= \<const0>\;
S00_AXI_rdata(468) <= \<const0>\;
S00_AXI_rdata(467) <= \<const0>\;
S00_AXI_rdata(466) <= \<const0>\;
S00_AXI_rdata(465) <= \<const0>\;
S00_AXI_rdata(464) <= \<const0>\;
S00_AXI_rdata(463) <= \<const0>\;
S00_AXI_rdata(462) <= \<const0>\;
S00_AXI_rdata(461) <= \<const0>\;
S00_AXI_rdata(460) <= \<const0>\;
S00_AXI_rdata(459) <= \<const0>\;
S00_AXI_rdata(458) <= \<const0>\;
S00_AXI_rdata(457) <= \<const0>\;
S00_AXI_rdata(456) <= \<const0>\;
S00_AXI_rdata(455) <= \<const0>\;
S00_AXI_rdata(454) <= \<const0>\;
S00_AXI_rdata(453) <= \<const0>\;
S00_AXI_rdata(452) <= \<const0>\;
S00_AXI_rdata(451) <= \<const0>\;
S00_AXI_rdata(450) <= \<const0>\;
S00_AXI_rdata(449) <= \<const0>\;
S00_AXI_rdata(448) <= \<const0>\;
S00_AXI_rdata(447) <= \<const0>\;
S00_AXI_rdata(446) <= \<const0>\;
S00_AXI_rdata(445) <= \<const0>\;
S00_AXI_rdata(444) <= \<const0>\;
S00_AXI_rdata(443) <= \<const0>\;
S00_AXI_rdata(442) <= \<const0>\;
S00_AXI_rdata(441) <= \<const0>\;
S00_AXI_rdata(440) <= \<const0>\;
S00_AXI_rdata(439) <= \<const0>\;
S00_AXI_rdata(438) <= \<const0>\;
S00_AXI_rdata(437) <= \<const0>\;
S00_AXI_rdata(436) <= \<const0>\;
S00_AXI_rdata(435) <= \<const0>\;
S00_AXI_rdata(434) <= \<const0>\;
S00_AXI_rdata(433) <= \<const0>\;
S00_AXI_rdata(432) <= \<const0>\;
S00_AXI_rdata(431) <= \<const0>\;
S00_AXI_rdata(430) <= \<const0>\;
S00_AXI_rdata(429) <= \<const0>\;
S00_AXI_rdata(428) <= \<const0>\;
S00_AXI_rdata(427) <= \<const0>\;
S00_AXI_rdata(426) <= \<const0>\;
S00_AXI_rdata(425) <= \<const0>\;
S00_AXI_rdata(424) <= \<const0>\;
S00_AXI_rdata(423) <= \<const0>\;
S00_AXI_rdata(422) <= \<const0>\;
S00_AXI_rdata(421) <= \<const0>\;
S00_AXI_rdata(420) <= \<const0>\;
S00_AXI_rdata(419) <= \<const0>\;
S00_AXI_rdata(418) <= \<const0>\;
S00_AXI_rdata(417) <= \<const0>\;
S00_AXI_rdata(416) <= \<const0>\;
S00_AXI_rdata(415) <= \<const0>\;
S00_AXI_rdata(414) <= \<const0>\;
S00_AXI_rdata(413) <= \<const0>\;
S00_AXI_rdata(412) <= \<const0>\;
S00_AXI_rdata(411) <= \<const0>\;
S00_AXI_rdata(410) <= \<const0>\;
S00_AXI_rdata(409) <= \<const0>\;
S00_AXI_rdata(408) <= \<const0>\;
S00_AXI_rdata(407) <= \<const0>\;
S00_AXI_rdata(406) <= \<const0>\;
S00_AXI_rdata(405) <= \<const0>\;
S00_AXI_rdata(404) <= \<const0>\;
S00_AXI_rdata(403) <= \<const0>\;
S00_AXI_rdata(402) <= \<const0>\;
S00_AXI_rdata(401) <= \<const0>\;
S00_AXI_rdata(400) <= \<const0>\;
S00_AXI_rdata(399) <= \<const0>\;
S00_AXI_rdata(398) <= \<const0>\;
S00_AXI_rdata(397) <= \<const0>\;
S00_AXI_rdata(396) <= \<const0>\;
S00_AXI_rdata(395) <= \<const0>\;
S00_AXI_rdata(394) <= \<const0>\;
S00_AXI_rdata(393) <= \<const0>\;
S00_AXI_rdata(392) <= \<const0>\;
S00_AXI_rdata(391) <= \<const0>\;
S00_AXI_rdata(390) <= \<const0>\;
S00_AXI_rdata(389) <= \<const0>\;
S00_AXI_rdata(388) <= \<const0>\;
S00_AXI_rdata(387) <= \<const0>\;
S00_AXI_rdata(386) <= \<const0>\;
S00_AXI_rdata(385) <= \<const0>\;
S00_AXI_rdata(384) <= \<const0>\;
S00_AXI_rdata(383) <= \<const0>\;
S00_AXI_rdata(382) <= \<const0>\;
S00_AXI_rdata(381) <= \<const0>\;
S00_AXI_rdata(380) <= \<const0>\;
S00_AXI_rdata(379) <= \<const0>\;
S00_AXI_rdata(378) <= \<const0>\;
S00_AXI_rdata(377) <= \<const0>\;
S00_AXI_rdata(376) <= \<const0>\;
S00_AXI_rdata(375) <= \<const0>\;
S00_AXI_rdata(374) <= \<const0>\;
S00_AXI_rdata(373) <= \<const0>\;
S00_AXI_rdata(372) <= \<const0>\;
S00_AXI_rdata(371) <= \<const0>\;
S00_AXI_rdata(370) <= \<const0>\;
S00_AXI_rdata(369) <= \<const0>\;
S00_AXI_rdata(368) <= \<const0>\;
S00_AXI_rdata(367) <= \<const0>\;
S00_AXI_rdata(366) <= \<const0>\;
S00_AXI_rdata(365) <= \<const0>\;
S00_AXI_rdata(364) <= \<const0>\;
S00_AXI_rdata(363) <= \<const0>\;
S00_AXI_rdata(362) <= \<const0>\;
S00_AXI_rdata(361) <= \<const0>\;
S00_AXI_rdata(360) <= \<const0>\;
S00_AXI_rdata(359) <= \<const0>\;
S00_AXI_rdata(358) <= \<const0>\;
S00_AXI_rdata(357) <= \<const0>\;
S00_AXI_rdata(356) <= \<const0>\;
S00_AXI_rdata(355) <= \<const0>\;
S00_AXI_rdata(354) <= \<const0>\;
S00_AXI_rdata(353) <= \<const0>\;
S00_AXI_rdata(352) <= \<const0>\;
S00_AXI_rdata(351) <= \<const0>\;
S00_AXI_rdata(350) <= \<const0>\;
S00_AXI_rdata(349) <= \<const0>\;
S00_AXI_rdata(348) <= \<const0>\;
S00_AXI_rdata(347) <= \<const0>\;
S00_AXI_rdata(346) <= \<const0>\;
S00_AXI_rdata(345) <= \<const0>\;
S00_AXI_rdata(344) <= \<const0>\;
S00_AXI_rdata(343) <= \<const0>\;
S00_AXI_rdata(342) <= \<const0>\;
S00_AXI_rdata(341) <= \<const0>\;
S00_AXI_rdata(340) <= \<const0>\;
S00_AXI_rdata(339) <= \<const0>\;
S00_AXI_rdata(338) <= \<const0>\;
S00_AXI_rdata(337) <= \<const0>\;
S00_AXI_rdata(336) <= \<const0>\;
S00_AXI_rdata(335) <= \<const0>\;
S00_AXI_rdata(334) <= \<const0>\;
S00_AXI_rdata(333) <= \<const0>\;
S00_AXI_rdata(332) <= \<const0>\;
S00_AXI_rdata(331) <= \<const0>\;
S00_AXI_rdata(330) <= \<const0>\;
S00_AXI_rdata(329) <= \<const0>\;
S00_AXI_rdata(328) <= \<const0>\;
S00_AXI_rdata(327) <= \<const0>\;
S00_AXI_rdata(326) <= \<const0>\;
S00_AXI_rdata(325) <= \<const0>\;
S00_AXI_rdata(324) <= \<const0>\;
S00_AXI_rdata(323) <= \<const0>\;
S00_AXI_rdata(322) <= \<const0>\;
S00_AXI_rdata(321) <= \<const0>\;
S00_AXI_rdata(320) <= \<const0>\;
S00_AXI_rdata(319) <= \<const0>\;
S00_AXI_rdata(318) <= \<const0>\;
S00_AXI_rdata(317) <= \<const0>\;
S00_AXI_rdata(316) <= \<const0>\;
S00_AXI_rdata(315) <= \<const0>\;
S00_AXI_rdata(314) <= \<const0>\;
S00_AXI_rdata(313) <= \<const0>\;
S00_AXI_rdata(312) <= \<const0>\;
S00_AXI_rdata(311) <= \<const0>\;
S00_AXI_rdata(310) <= \<const0>\;
S00_AXI_rdata(309) <= \<const0>\;
S00_AXI_rdata(308) <= \<const0>\;
S00_AXI_rdata(307) <= \<const0>\;
S00_AXI_rdata(306) <= \<const0>\;
S00_AXI_rdata(305) <= \<const0>\;
S00_AXI_rdata(304) <= \<const0>\;
S00_AXI_rdata(303) <= \<const0>\;
S00_AXI_rdata(302) <= \<const0>\;
S00_AXI_rdata(301) <= \<const0>\;
S00_AXI_rdata(300) <= \<const0>\;
S00_AXI_rdata(299) <= \<const0>\;
S00_AXI_rdata(298) <= \<const0>\;
S00_AXI_rdata(297) <= \<const0>\;
S00_AXI_rdata(296) <= \<const0>\;
S00_AXI_rdata(295) <= \<const0>\;
S00_AXI_rdata(294) <= \<const0>\;
S00_AXI_rdata(293) <= \<const0>\;
S00_AXI_rdata(292) <= \<const0>\;
S00_AXI_rdata(291) <= \<const0>\;
S00_AXI_rdata(290) <= \<const0>\;
S00_AXI_rdata(289) <= \<const0>\;
S00_AXI_rdata(288) <= \<const0>\;
S00_AXI_rdata(287) <= \<const0>\;
S00_AXI_rdata(286) <= \<const0>\;
S00_AXI_rdata(285) <= \<const0>\;
S00_AXI_rdata(284) <= \<const0>\;
S00_AXI_rdata(283) <= \<const0>\;
S00_AXI_rdata(282) <= \<const0>\;
S00_AXI_rdata(281) <= \<const0>\;
S00_AXI_rdata(280) <= \<const0>\;
S00_AXI_rdata(279) <= \<const0>\;
S00_AXI_rdata(278) <= \<const0>\;
S00_AXI_rdata(277) <= \<const0>\;
S00_AXI_rdata(276) <= \<const0>\;
S00_AXI_rdata(275) <= \<const0>\;
S00_AXI_rdata(274) <= \<const0>\;
S00_AXI_rdata(273) <= \<const0>\;
S00_AXI_rdata(272) <= \<const0>\;
S00_AXI_rdata(271) <= \<const0>\;
S00_AXI_rdata(270) <= \<const0>\;
S00_AXI_rdata(269) <= \<const0>\;
S00_AXI_rdata(268) <= \<const0>\;
S00_AXI_rdata(267) <= \<const0>\;
S00_AXI_rdata(266) <= \<const0>\;
S00_AXI_rdata(265) <= \<const0>\;
S00_AXI_rdata(264) <= \<const0>\;
S00_AXI_rdata(263) <= \<const0>\;
S00_AXI_rdata(262) <= \<const0>\;
S00_AXI_rdata(261) <= \<const0>\;
S00_AXI_rdata(260) <= \<const0>\;
S00_AXI_rdata(259) <= \<const0>\;
S00_AXI_rdata(258) <= \<const0>\;
S00_AXI_rdata(257) <= \<const0>\;
S00_AXI_rdata(256) <= \<const0>\;
S00_AXI_rdata(255) <= \<const0>\;
S00_AXI_rdata(254) <= \<const0>\;
S00_AXI_rdata(253) <= \<const0>\;
S00_AXI_rdata(252) <= \<const0>\;
S00_AXI_rdata(251) <= \<const0>\;
S00_AXI_rdata(250) <= \<const0>\;
S00_AXI_rdata(249) <= \<const0>\;
S00_AXI_rdata(248) <= \<const0>\;
S00_AXI_rdata(247) <= \<const0>\;
S00_AXI_rdata(246) <= \<const0>\;
S00_AXI_rdata(245) <= \<const0>\;
S00_AXI_rdata(244) <= \<const0>\;
S00_AXI_rdata(243) <= \<const0>\;
S00_AXI_rdata(242) <= \<const0>\;
S00_AXI_rdata(241) <= \<const0>\;
S00_AXI_rdata(240) <= \<const0>\;
S00_AXI_rdata(239) <= \<const0>\;
S00_AXI_rdata(238) <= \<const0>\;
S00_AXI_rdata(237) <= \<const0>\;
S00_AXI_rdata(236) <= \<const0>\;
S00_AXI_rdata(235) <= \<const0>\;
S00_AXI_rdata(234) <= \<const0>\;
S00_AXI_rdata(233) <= \<const0>\;
S00_AXI_rdata(232) <= \<const0>\;
S00_AXI_rdata(231) <= \<const0>\;
S00_AXI_rdata(230) <= \<const0>\;
S00_AXI_rdata(229) <= \<const0>\;
S00_AXI_rdata(228) <= \<const0>\;
S00_AXI_rdata(227) <= \<const0>\;
S00_AXI_rdata(226) <= \<const0>\;
S00_AXI_rdata(225) <= \<const0>\;
S00_AXI_rdata(224) <= \<const0>\;
S00_AXI_rdata(223) <= \<const0>\;
S00_AXI_rdata(222) <= \<const0>\;
S00_AXI_rdata(221) <= \<const0>\;
S00_AXI_rdata(220) <= \<const0>\;
S00_AXI_rdata(219) <= \<const0>\;
S00_AXI_rdata(218) <= \<const0>\;
S00_AXI_rdata(217) <= \<const0>\;
S00_AXI_rdata(216) <= \<const0>\;
S00_AXI_rdata(215) <= \<const0>\;
S00_AXI_rdata(214) <= \<const0>\;
S00_AXI_rdata(213) <= \<const0>\;
S00_AXI_rdata(212) <= \<const0>\;
S00_AXI_rdata(211) <= \<const0>\;
S00_AXI_rdata(210) <= \<const0>\;
S00_AXI_rdata(209) <= \<const0>\;
S00_AXI_rdata(208) <= \<const0>\;
S00_AXI_rdata(207) <= \<const0>\;
S00_AXI_rdata(206) <= \<const0>\;
S00_AXI_rdata(205) <= \<const0>\;
S00_AXI_rdata(204) <= \<const0>\;
S00_AXI_rdata(203) <= \<const0>\;
S00_AXI_rdata(202) <= \<const0>\;
S00_AXI_rdata(201) <= \<const0>\;
S00_AXI_rdata(200) <= \<const0>\;
S00_AXI_rdata(199) <= \<const0>\;
S00_AXI_rdata(198) <= \<const0>\;
S00_AXI_rdata(197) <= \<const0>\;
S00_AXI_rdata(196) <= \<const0>\;
S00_AXI_rdata(195) <= \<const0>\;
S00_AXI_rdata(194) <= \<const0>\;
S00_AXI_rdata(193) <= \<const0>\;
S00_AXI_rdata(192) <= \<const0>\;
S00_AXI_rdata(191) <= \<const0>\;
S00_AXI_rdata(190) <= \<const0>\;
S00_AXI_rdata(189) <= \<const0>\;
S00_AXI_rdata(188) <= \<const0>\;
S00_AXI_rdata(187) <= \<const0>\;
S00_AXI_rdata(186) <= \<const0>\;
S00_AXI_rdata(185) <= \<const0>\;
S00_AXI_rdata(184) <= \<const0>\;
S00_AXI_rdata(183) <= \<const0>\;
S00_AXI_rdata(182) <= \<const0>\;
S00_AXI_rdata(181) <= \<const0>\;
S00_AXI_rdata(180) <= \<const0>\;
S00_AXI_rdata(179) <= \<const0>\;
S00_AXI_rdata(178) <= \<const0>\;
S00_AXI_rdata(177) <= \<const0>\;
S00_AXI_rdata(176) <= \<const0>\;
S00_AXI_rdata(175) <= \<const0>\;
S00_AXI_rdata(174) <= \<const0>\;
S00_AXI_rdata(173) <= \<const0>\;
S00_AXI_rdata(172) <= \<const0>\;
S00_AXI_rdata(171) <= \<const0>\;
S00_AXI_rdata(170) <= \<const0>\;
S00_AXI_rdata(169) <= \<const0>\;
S00_AXI_rdata(168) <= \<const0>\;
S00_AXI_rdata(167) <= \<const0>\;
S00_AXI_rdata(166) <= \<const0>\;
S00_AXI_rdata(165) <= \<const0>\;
S00_AXI_rdata(164) <= \<const0>\;
S00_AXI_rdata(163) <= \<const0>\;
S00_AXI_rdata(162) <= \<const0>\;
S00_AXI_rdata(161) <= \<const0>\;
S00_AXI_rdata(160) <= \<const0>\;
S00_AXI_rdata(159) <= \<const0>\;
S00_AXI_rdata(158) <= \<const0>\;
S00_AXI_rdata(157) <= \<const0>\;
S00_AXI_rdata(156) <= \<const0>\;
S00_AXI_rdata(155) <= \<const0>\;
S00_AXI_rdata(154) <= \<const0>\;
S00_AXI_rdata(153) <= \<const0>\;
S00_AXI_rdata(152) <= \<const0>\;
S00_AXI_rdata(151) <= \<const0>\;
S00_AXI_rdata(150) <= \<const0>\;
S00_AXI_rdata(149) <= \<const0>\;
S00_AXI_rdata(148) <= \<const0>\;
S00_AXI_rdata(147) <= \<const0>\;
S00_AXI_rdata(146) <= \<const0>\;
S00_AXI_rdata(145) <= \<const0>\;
S00_AXI_rdata(144) <= \<const0>\;
S00_AXI_rdata(143) <= \<const0>\;
S00_AXI_rdata(142) <= \<const0>\;
S00_AXI_rdata(141) <= \<const0>\;
S00_AXI_rdata(140) <= \<const0>\;
S00_AXI_rdata(139) <= \<const0>\;
S00_AXI_rdata(138) <= \<const0>\;
S00_AXI_rdata(137) <= \<const0>\;
S00_AXI_rdata(136) <= \<const0>\;
S00_AXI_rdata(135) <= \<const0>\;
S00_AXI_rdata(134) <= \<const0>\;
S00_AXI_rdata(133) <= \<const0>\;
S00_AXI_rdata(132) <= \<const0>\;
S00_AXI_rdata(131) <= \<const0>\;
S00_AXI_rdata(130) <= \<const0>\;
S00_AXI_rdata(129) <= \<const0>\;
S00_AXI_rdata(128) <= \<const0>\;
S00_AXI_rdata(127) <= \<const0>\;
S00_AXI_rdata(126) <= \<const0>\;
S00_AXI_rdata(125) <= \<const0>\;
S00_AXI_rdata(124) <= \<const0>\;
S00_AXI_rdata(123) <= \<const0>\;
S00_AXI_rdata(122) <= \<const0>\;
S00_AXI_rdata(121) <= \<const0>\;
S00_AXI_rdata(120) <= \<const0>\;
S00_AXI_rdata(119) <= \<const0>\;
S00_AXI_rdata(118) <= \<const0>\;
S00_AXI_rdata(117) <= \<const0>\;
S00_AXI_rdata(116) <= \<const0>\;
S00_AXI_rdata(115) <= \<const0>\;
S00_AXI_rdata(114) <= \<const0>\;
S00_AXI_rdata(113) <= \<const0>\;
S00_AXI_rdata(112) <= \<const0>\;
S00_AXI_rdata(111) <= \<const0>\;
S00_AXI_rdata(110) <= \<const0>\;
S00_AXI_rdata(109) <= \<const0>\;
S00_AXI_rdata(108) <= \<const0>\;
S00_AXI_rdata(107) <= \<const0>\;
S00_AXI_rdata(106) <= \<const0>\;
S00_AXI_rdata(105) <= \<const0>\;
S00_AXI_rdata(104) <= \<const0>\;
S00_AXI_rdata(103) <= \<const0>\;
S00_AXI_rdata(102) <= \<const0>\;
S00_AXI_rdata(101) <= \<const0>\;
S00_AXI_rdata(100) <= \<const0>\;
S00_AXI_rdata(99) <= \<const0>\;
S00_AXI_rdata(98) <= \<const0>\;
S00_AXI_rdata(97) <= \<const0>\;
S00_AXI_rdata(96) <= \<const0>\;
S00_AXI_rdata(95) <= \<const0>\;
S00_AXI_rdata(94) <= \<const0>\;
S00_AXI_rdata(93) <= \<const0>\;
S00_AXI_rdata(92) <= \<const0>\;
S00_AXI_rdata(91) <= \<const0>\;
S00_AXI_rdata(90) <= \<const0>\;
S00_AXI_rdata(89) <= \<const0>\;
S00_AXI_rdata(88) <= \<const0>\;
S00_AXI_rdata(87) <= \<const0>\;
S00_AXI_rdata(86) <= \<const0>\;
S00_AXI_rdata(85) <= \<const0>\;
S00_AXI_rdata(84) <= \<const0>\;
S00_AXI_rdata(83) <= \<const0>\;
S00_AXI_rdata(82) <= \<const0>\;
S00_AXI_rdata(81) <= \<const0>\;
S00_AXI_rdata(80) <= \<const0>\;
S00_AXI_rdata(79) <= \<const0>\;
S00_AXI_rdata(78) <= \<const0>\;
S00_AXI_rdata(77) <= \<const0>\;
S00_AXI_rdata(76) <= \<const0>\;
S00_AXI_rdata(75) <= \<const0>\;
S00_AXI_rdata(74) <= \<const0>\;
S00_AXI_rdata(73) <= \<const0>\;
S00_AXI_rdata(72) <= \<const0>\;
S00_AXI_rdata(71) <= \<const0>\;
S00_AXI_rdata(70) <= \<const0>\;
S00_AXI_rdata(69) <= \<const0>\;
S00_AXI_rdata(68) <= \<const0>\;
S00_AXI_rdata(67) <= \<const0>\;
S00_AXI_rdata(66) <= \<const0>\;
S00_AXI_rdata(65) <= \<const0>\;
S00_AXI_rdata(64) <= \<const0>\;
S00_AXI_rdata(63) <= \<const0>\;
S00_AXI_rdata(62) <= \<const0>\;
S00_AXI_rdata(61) <= \<const0>\;
S00_AXI_rdata(60) <= \<const0>\;
S00_AXI_rdata(59) <= \<const0>\;
S00_AXI_rdata(58) <= \<const0>\;
S00_AXI_rdata(57) <= \<const0>\;
S00_AXI_rdata(56) <= \<const0>\;
S00_AXI_rdata(55) <= \<const0>\;
S00_AXI_rdata(54) <= \<const0>\;
S00_AXI_rdata(53) <= \<const0>\;
S00_AXI_rdata(52) <= \<const0>\;
S00_AXI_rdata(51) <= \<const0>\;
S00_AXI_rdata(50) <= \<const0>\;
S00_AXI_rdata(49) <= \<const0>\;
S00_AXI_rdata(48) <= \<const0>\;
S00_AXI_rdata(47) <= \<const0>\;
S00_AXI_rdata(46) <= \<const0>\;
S00_AXI_rdata(45) <= \<const0>\;
S00_AXI_rdata(44) <= \<const0>\;
S00_AXI_rdata(43) <= \<const0>\;
S00_AXI_rdata(42) <= \<const0>\;
S00_AXI_rdata(41) <= \<const0>\;
S00_AXI_rdata(40) <= \<const0>\;
S00_AXI_rdata(39) <= \<const0>\;
S00_AXI_rdata(38) <= \<const0>\;
S00_AXI_rdata(37) <= \<const0>\;
S00_AXI_rdata(36) <= \<const0>\;
S00_AXI_rdata(35) <= \<const0>\;
S00_AXI_rdata(34) <= \<const0>\;
S00_AXI_rdata(33) <= \<const0>\;
S00_AXI_rdata(32) <= \<const0>\;
S00_AXI_rdata(31) <= \<const0>\;
S00_AXI_rdata(30) <= \<const0>\;
S00_AXI_rdata(29) <= \<const0>\;
S00_AXI_rdata(28) <= \<const0>\;
S00_AXI_rdata(27) <= \<const0>\;
S00_AXI_rdata(26) <= \<const0>\;
S00_AXI_rdata(25) <= \<const0>\;
S00_AXI_rdata(24) <= \<const0>\;
S00_AXI_rdata(23) <= \<const0>\;
S00_AXI_rdata(22) <= \<const0>\;
S00_AXI_rdata(21) <= \<const0>\;
S00_AXI_rdata(20) <= \<const0>\;
S00_AXI_rdata(19) <= \<const0>\;
S00_AXI_rdata(18) <= \<const0>\;
S00_AXI_rdata(17) <= \<const0>\;
S00_AXI_rdata(16) <= \<const0>\;
S00_AXI_rdata(15) <= \<const0>\;
S00_AXI_rdata(14) <= \<const0>\;
S00_AXI_rdata(13) <= \<const0>\;
S00_AXI_rdata(12) <= \<const0>\;
S00_AXI_rdata(11) <= \<const0>\;
S00_AXI_rdata(10) <= \<const0>\;
S00_AXI_rdata(9) <= \<const0>\;
S00_AXI_rdata(8) <= \<const0>\;
S00_AXI_rdata(7) <= \<const0>\;
S00_AXI_rdata(6) <= \<const0>\;
S00_AXI_rdata(5) <= \<const0>\;
S00_AXI_rdata(4) <= \<const0>\;
S00_AXI_rdata(3) <= \<const0>\;
S00_AXI_rdata(2) <= \<const0>\;
S00_AXI_rdata(1) <= \<const0>\;
S00_AXI_rdata(0) <= \<const0>\;
S00_AXI_rid(3) <= \<const0>\;
S00_AXI_rid(2) <= \<const0>\;
S00_AXI_rid(1) <= \<const0>\;
S00_AXI_rid(0) <= \<const0>\;
S00_AXI_rlast <= \<const0>\;
S00_AXI_rresp(1) <= \<const0>\;
S00_AXI_rresp(0) <= \<const0>\;
S00_AXI_rvalid <= \<const0>\;
S00_AXI_wready <= \<const0>\;
S03_AXI_arready <= \<const0>\;
S03_AXI_awready <= \<const0>\;
S03_AXI_bid(3) <= \<const0>\;
S03_AXI_bid(2) <= \<const0>\;
S03_AXI_bid(1) <= \<const0>\;
S03_AXI_bid(0) <= \<const0>\;
S03_AXI_bresp(1) <= \<const0>\;
S03_AXI_bresp(0) <= \<const0>\;
S03_AXI_bvalid <= \<const0>\;
S03_AXI_rdata(511) <= \<const0>\;
S03_AXI_rdata(510) <= \<const0>\;
S03_AXI_rdata(509) <= \<const0>\;
S03_AXI_rdata(508) <= \<const0>\;
S03_AXI_rdata(507) <= \<const0>\;
S03_AXI_rdata(506) <= \<const0>\;
S03_AXI_rdata(505) <= \<const0>\;
S03_AXI_rdata(504) <= \<const0>\;
S03_AXI_rdata(503) <= \<const0>\;
S03_AXI_rdata(502) <= \<const0>\;
S03_AXI_rdata(501) <= \<const0>\;
S03_AXI_rdata(500) <= \<const0>\;
S03_AXI_rdata(499) <= \<const0>\;
S03_AXI_rdata(498) <= \<const0>\;
S03_AXI_rdata(497) <= \<const0>\;
S03_AXI_rdata(496) <= \<const0>\;
S03_AXI_rdata(495) <= \<const0>\;
S03_AXI_rdata(494) <= \<const0>\;
S03_AXI_rdata(493) <= \<const0>\;
S03_AXI_rdata(492) <= \<const0>\;
S03_AXI_rdata(491) <= \<const0>\;
S03_AXI_rdata(490) <= \<const0>\;
S03_AXI_rdata(489) <= \<const0>\;
S03_AXI_rdata(488) <= \<const0>\;
S03_AXI_rdata(487) <= \<const0>\;
S03_AXI_rdata(486) <= \<const0>\;
S03_AXI_rdata(485) <= \<const0>\;
S03_AXI_rdata(484) <= \<const0>\;
S03_AXI_rdata(483) <= \<const0>\;
S03_AXI_rdata(482) <= \<const0>\;
S03_AXI_rdata(481) <= \<const0>\;
S03_AXI_rdata(480) <= \<const0>\;
S03_AXI_rdata(479) <= \<const0>\;
S03_AXI_rdata(478) <= \<const0>\;
S03_AXI_rdata(477) <= \<const0>\;
S03_AXI_rdata(476) <= \<const0>\;
S03_AXI_rdata(475) <= \<const0>\;
S03_AXI_rdata(474) <= \<const0>\;
S03_AXI_rdata(473) <= \<const0>\;
S03_AXI_rdata(472) <= \<const0>\;
S03_AXI_rdata(471) <= \<const0>\;
S03_AXI_rdata(470) <= \<const0>\;
S03_AXI_rdata(469) <= \<const0>\;
S03_AXI_rdata(468) <= \<const0>\;
S03_AXI_rdata(467) <= \<const0>\;
S03_AXI_rdata(466) <= \<const0>\;
S03_AXI_rdata(465) <= \<const0>\;
S03_AXI_rdata(464) <= \<const0>\;
S03_AXI_rdata(463) <= \<const0>\;
S03_AXI_rdata(462) <= \<const0>\;
S03_AXI_rdata(461) <= \<const0>\;
S03_AXI_rdata(460) <= \<const0>\;
S03_AXI_rdata(459) <= \<const0>\;
S03_AXI_rdata(458) <= \<const0>\;
S03_AXI_rdata(457) <= \<const0>\;
S03_AXI_rdata(456) <= \<const0>\;
S03_AXI_rdata(455) <= \<const0>\;
S03_AXI_rdata(454) <= \<const0>\;
S03_AXI_rdata(453) <= \<const0>\;
S03_AXI_rdata(452) <= \<const0>\;
S03_AXI_rdata(451) <= \<const0>\;
S03_AXI_rdata(450) <= \<const0>\;
S03_AXI_rdata(449) <= \<const0>\;
S03_AXI_rdata(448) <= \<const0>\;
S03_AXI_rdata(447) <= \<const0>\;
S03_AXI_rdata(446) <= \<const0>\;
S03_AXI_rdata(445) <= \<const0>\;
S03_AXI_rdata(444) <= \<const0>\;
S03_AXI_rdata(443) <= \<const0>\;
S03_AXI_rdata(442) <= \<const0>\;
S03_AXI_rdata(441) <= \<const0>\;
S03_AXI_rdata(440) <= \<const0>\;
S03_AXI_rdata(439) <= \<const0>\;
S03_AXI_rdata(438) <= \<const0>\;
S03_AXI_rdata(437) <= \<const0>\;
S03_AXI_rdata(436) <= \<const0>\;
S03_AXI_rdata(435) <= \<const0>\;
S03_AXI_rdata(434) <= \<const0>\;
S03_AXI_rdata(433) <= \<const0>\;
S03_AXI_rdata(432) <= \<const0>\;
S03_AXI_rdata(431) <= \<const0>\;
S03_AXI_rdata(430) <= \<const0>\;
S03_AXI_rdata(429) <= \<const0>\;
S03_AXI_rdata(428) <= \<const0>\;
S03_AXI_rdata(427) <= \<const0>\;
S03_AXI_rdata(426) <= \<const0>\;
S03_AXI_rdata(425) <= \<const0>\;
S03_AXI_rdata(424) <= \<const0>\;
S03_AXI_rdata(423) <= \<const0>\;
S03_AXI_rdata(422) <= \<const0>\;
S03_AXI_rdata(421) <= \<const0>\;
S03_AXI_rdata(420) <= \<const0>\;
S03_AXI_rdata(419) <= \<const0>\;
S03_AXI_rdata(418) <= \<const0>\;
S03_AXI_rdata(417) <= \<const0>\;
S03_AXI_rdata(416) <= \<const0>\;
S03_AXI_rdata(415) <= \<const0>\;
S03_AXI_rdata(414) <= \<const0>\;
S03_AXI_rdata(413) <= \<const0>\;
S03_AXI_rdata(412) <= \<const0>\;
S03_AXI_rdata(411) <= \<const0>\;
S03_AXI_rdata(410) <= \<const0>\;
S03_AXI_rdata(409) <= \<const0>\;
S03_AXI_rdata(408) <= \<const0>\;
S03_AXI_rdata(407) <= \<const0>\;
S03_AXI_rdata(406) <= \<const0>\;
S03_AXI_rdata(405) <= \<const0>\;
S03_AXI_rdata(404) <= \<const0>\;
S03_AXI_rdata(403) <= \<const0>\;
S03_AXI_rdata(402) <= \<const0>\;
S03_AXI_rdata(401) <= \<const0>\;
S03_AXI_rdata(400) <= \<const0>\;
S03_AXI_rdata(399) <= \<const0>\;
S03_AXI_rdata(398) <= \<const0>\;
S03_AXI_rdata(397) <= \<const0>\;
S03_AXI_rdata(396) <= \<const0>\;
S03_AXI_rdata(395) <= \<const0>\;
S03_AXI_rdata(394) <= \<const0>\;
S03_AXI_rdata(393) <= \<const0>\;
S03_AXI_rdata(392) <= \<const0>\;
S03_AXI_rdata(391) <= \<const0>\;
S03_AXI_rdata(390) <= \<const0>\;
S03_AXI_rdata(389) <= \<const0>\;
S03_AXI_rdata(388) <= \<const0>\;
S03_AXI_rdata(387) <= \<const0>\;
S03_AXI_rdata(386) <= \<const0>\;
S03_AXI_rdata(385) <= \<const0>\;
S03_AXI_rdata(384) <= \<const0>\;
S03_AXI_rdata(383) <= \<const0>\;
S03_AXI_rdata(382) <= \<const0>\;
S03_AXI_rdata(381) <= \<const0>\;
S03_AXI_rdata(380) <= \<const0>\;
S03_AXI_rdata(379) <= \<const0>\;
S03_AXI_rdata(378) <= \<const0>\;
S03_AXI_rdata(377) <= \<const0>\;
S03_AXI_rdata(376) <= \<const0>\;
S03_AXI_rdata(375) <= \<const0>\;
S03_AXI_rdata(374) <= \<const0>\;
S03_AXI_rdata(373) <= \<const0>\;
S03_AXI_rdata(372) <= \<const0>\;
S03_AXI_rdata(371) <= \<const0>\;
S03_AXI_rdata(370) <= \<const0>\;
S03_AXI_rdata(369) <= \<const0>\;
S03_AXI_rdata(368) <= \<const0>\;
S03_AXI_rdata(367) <= \<const0>\;
S03_AXI_rdata(366) <= \<const0>\;
S03_AXI_rdata(365) <= \<const0>\;
S03_AXI_rdata(364) <= \<const0>\;
S03_AXI_rdata(363) <= \<const0>\;
S03_AXI_rdata(362) <= \<const0>\;
S03_AXI_rdata(361) <= \<const0>\;
S03_AXI_rdata(360) <= \<const0>\;
S03_AXI_rdata(359) <= \<const0>\;
S03_AXI_rdata(358) <= \<const0>\;
S03_AXI_rdata(357) <= \<const0>\;
S03_AXI_rdata(356) <= \<const0>\;
S03_AXI_rdata(355) <= \<const0>\;
S03_AXI_rdata(354) <= \<const0>\;
S03_AXI_rdata(353) <= \<const0>\;
S03_AXI_rdata(352) <= \<const0>\;
S03_AXI_rdata(351) <= \<const0>\;
S03_AXI_rdata(350) <= \<const0>\;
S03_AXI_rdata(349) <= \<const0>\;
S03_AXI_rdata(348) <= \<const0>\;
S03_AXI_rdata(347) <= \<const0>\;
S03_AXI_rdata(346) <= \<const0>\;
S03_AXI_rdata(345) <= \<const0>\;
S03_AXI_rdata(344) <= \<const0>\;
S03_AXI_rdata(343) <= \<const0>\;
S03_AXI_rdata(342) <= \<const0>\;
S03_AXI_rdata(341) <= \<const0>\;
S03_AXI_rdata(340) <= \<const0>\;
S03_AXI_rdata(339) <= \<const0>\;
S03_AXI_rdata(338) <= \<const0>\;
S03_AXI_rdata(337) <= \<const0>\;
S03_AXI_rdata(336) <= \<const0>\;
S03_AXI_rdata(335) <= \<const0>\;
S03_AXI_rdata(334) <= \<const0>\;
S03_AXI_rdata(333) <= \<const0>\;
S03_AXI_rdata(332) <= \<const0>\;
S03_AXI_rdata(331) <= \<const0>\;
S03_AXI_rdata(330) <= \<const0>\;
S03_AXI_rdata(329) <= \<const0>\;
S03_AXI_rdata(328) <= \<const0>\;
S03_AXI_rdata(327) <= \<const0>\;
S03_AXI_rdata(326) <= \<const0>\;
S03_AXI_rdata(325) <= \<const0>\;
S03_AXI_rdata(324) <= \<const0>\;
S03_AXI_rdata(323) <= \<const0>\;
S03_AXI_rdata(322) <= \<const0>\;
S03_AXI_rdata(321) <= \<const0>\;
S03_AXI_rdata(320) <= \<const0>\;
S03_AXI_rdata(319) <= \<const0>\;
S03_AXI_rdata(318) <= \<const0>\;
S03_AXI_rdata(317) <= \<const0>\;
S03_AXI_rdata(316) <= \<const0>\;
S03_AXI_rdata(315) <= \<const0>\;
S03_AXI_rdata(314) <= \<const0>\;
S03_AXI_rdata(313) <= \<const0>\;
S03_AXI_rdata(312) <= \<const0>\;
S03_AXI_rdata(311) <= \<const0>\;
S03_AXI_rdata(310) <= \<const0>\;
S03_AXI_rdata(309) <= \<const0>\;
S03_AXI_rdata(308) <= \<const0>\;
S03_AXI_rdata(307) <= \<const0>\;
S03_AXI_rdata(306) <= \<const0>\;
S03_AXI_rdata(305) <= \<const0>\;
S03_AXI_rdata(304) <= \<const0>\;
S03_AXI_rdata(303) <= \<const0>\;
S03_AXI_rdata(302) <= \<const0>\;
S03_AXI_rdata(301) <= \<const0>\;
S03_AXI_rdata(300) <= \<const0>\;
S03_AXI_rdata(299) <= \<const0>\;
S03_AXI_rdata(298) <= \<const0>\;
S03_AXI_rdata(297) <= \<const0>\;
S03_AXI_rdata(296) <= \<const0>\;
S03_AXI_rdata(295) <= \<const0>\;
S03_AXI_rdata(294) <= \<const0>\;
S03_AXI_rdata(293) <= \<const0>\;
S03_AXI_rdata(292) <= \<const0>\;
S03_AXI_rdata(291) <= \<const0>\;
S03_AXI_rdata(290) <= \<const0>\;
S03_AXI_rdata(289) <= \<const0>\;
S03_AXI_rdata(288) <= \<const0>\;
S03_AXI_rdata(287) <= \<const0>\;
S03_AXI_rdata(286) <= \<const0>\;
S03_AXI_rdata(285) <= \<const0>\;
S03_AXI_rdata(284) <= \<const0>\;
S03_AXI_rdata(283) <= \<const0>\;
S03_AXI_rdata(282) <= \<const0>\;
S03_AXI_rdata(281) <= \<const0>\;
S03_AXI_rdata(280) <= \<const0>\;
S03_AXI_rdata(279) <= \<const0>\;
S03_AXI_rdata(278) <= \<const0>\;
S03_AXI_rdata(277) <= \<const0>\;
S03_AXI_rdata(276) <= \<const0>\;
S03_AXI_rdata(275) <= \<const0>\;
S03_AXI_rdata(274) <= \<const0>\;
S03_AXI_rdata(273) <= \<const0>\;
S03_AXI_rdata(272) <= \<const0>\;
S03_AXI_rdata(271) <= \<const0>\;
S03_AXI_rdata(270) <= \<const0>\;
S03_AXI_rdata(269) <= \<const0>\;
S03_AXI_rdata(268) <= \<const0>\;
S03_AXI_rdata(267) <= \<const0>\;
S03_AXI_rdata(266) <= \<const0>\;
S03_AXI_rdata(265) <= \<const0>\;
S03_AXI_rdata(264) <= \<const0>\;
S03_AXI_rdata(263) <= \<const0>\;
S03_AXI_rdata(262) <= \<const0>\;
S03_AXI_rdata(261) <= \<const0>\;
S03_AXI_rdata(260) <= \<const0>\;
S03_AXI_rdata(259) <= \<const0>\;
S03_AXI_rdata(258) <= \<const0>\;
S03_AXI_rdata(257) <= \<const0>\;
S03_AXI_rdata(256) <= \<const0>\;
S03_AXI_rdata(255) <= \<const0>\;
S03_AXI_rdata(254) <= \<const0>\;
S03_AXI_rdata(253) <= \<const0>\;
S03_AXI_rdata(252) <= \<const0>\;
S03_AXI_rdata(251) <= \<const0>\;
S03_AXI_rdata(250) <= \<const0>\;
S03_AXI_rdata(249) <= \<const0>\;
S03_AXI_rdata(248) <= \<const0>\;
S03_AXI_rdata(247) <= \<const0>\;
S03_AXI_rdata(246) <= \<const0>\;
S03_AXI_rdata(245) <= \<const0>\;
S03_AXI_rdata(244) <= \<const0>\;
S03_AXI_rdata(243) <= \<const0>\;
S03_AXI_rdata(242) <= \<const0>\;
S03_AXI_rdata(241) <= \<const0>\;
S03_AXI_rdata(240) <= \<const0>\;
S03_AXI_rdata(239) <= \<const0>\;
S03_AXI_rdata(238) <= \<const0>\;
S03_AXI_rdata(237) <= \<const0>\;
S03_AXI_rdata(236) <= \<const0>\;
S03_AXI_rdata(235) <= \<const0>\;
S03_AXI_rdata(234) <= \<const0>\;
S03_AXI_rdata(233) <= \<const0>\;
S03_AXI_rdata(232) <= \<const0>\;
S03_AXI_rdata(231) <= \<const0>\;
S03_AXI_rdata(230) <= \<const0>\;
S03_AXI_rdata(229) <= \<const0>\;
S03_AXI_rdata(228) <= \<const0>\;
S03_AXI_rdata(227) <= \<const0>\;
S03_AXI_rdata(226) <= \<const0>\;
S03_AXI_rdata(225) <= \<const0>\;
S03_AXI_rdata(224) <= \<const0>\;
S03_AXI_rdata(223) <= \<const0>\;
S03_AXI_rdata(222) <= \<const0>\;
S03_AXI_rdata(221) <= \<const0>\;
S03_AXI_rdata(220) <= \<const0>\;
S03_AXI_rdata(219) <= \<const0>\;
S03_AXI_rdata(218) <= \<const0>\;
S03_AXI_rdata(217) <= \<const0>\;
S03_AXI_rdata(216) <= \<const0>\;
S03_AXI_rdata(215) <= \<const0>\;
S03_AXI_rdata(214) <= \<const0>\;
S03_AXI_rdata(213) <= \<const0>\;
S03_AXI_rdata(212) <= \<const0>\;
S03_AXI_rdata(211) <= \<const0>\;
S03_AXI_rdata(210) <= \<const0>\;
S03_AXI_rdata(209) <= \<const0>\;
S03_AXI_rdata(208) <= \<const0>\;
S03_AXI_rdata(207) <= \<const0>\;
S03_AXI_rdata(206) <= \<const0>\;
S03_AXI_rdata(205) <= \<const0>\;
S03_AXI_rdata(204) <= \<const0>\;
S03_AXI_rdata(203) <= \<const0>\;
S03_AXI_rdata(202) <= \<const0>\;
S03_AXI_rdata(201) <= \<const0>\;
S03_AXI_rdata(200) <= \<const0>\;
S03_AXI_rdata(199) <= \<const0>\;
S03_AXI_rdata(198) <= \<const0>\;
S03_AXI_rdata(197) <= \<const0>\;
S03_AXI_rdata(196) <= \<const0>\;
S03_AXI_rdata(195) <= \<const0>\;
S03_AXI_rdata(194) <= \<const0>\;
S03_AXI_rdata(193) <= \<const0>\;
S03_AXI_rdata(192) <= \<const0>\;
S03_AXI_rdata(191) <= \<const0>\;
S03_AXI_rdata(190) <= \<const0>\;
S03_AXI_rdata(189) <= \<const0>\;
S03_AXI_rdata(188) <= \<const0>\;
S03_AXI_rdata(187) <= \<const0>\;
S03_AXI_rdata(186) <= \<const0>\;
S03_AXI_rdata(185) <= \<const0>\;
S03_AXI_rdata(184) <= \<const0>\;
S03_AXI_rdata(183) <= \<const0>\;
S03_AXI_rdata(182) <= \<const0>\;
S03_AXI_rdata(181) <= \<const0>\;
S03_AXI_rdata(180) <= \<const0>\;
S03_AXI_rdata(179) <= \<const0>\;
S03_AXI_rdata(178) <= \<const0>\;
S03_AXI_rdata(177) <= \<const0>\;
S03_AXI_rdata(176) <= \<const0>\;
S03_AXI_rdata(175) <= \<const0>\;
S03_AXI_rdata(174) <= \<const0>\;
S03_AXI_rdata(173) <= \<const0>\;
S03_AXI_rdata(172) <= \<const0>\;
S03_AXI_rdata(171) <= \<const0>\;
S03_AXI_rdata(170) <= \<const0>\;
S03_AXI_rdata(169) <= \<const0>\;
S03_AXI_rdata(168) <= \<const0>\;
S03_AXI_rdata(167) <= \<const0>\;
S03_AXI_rdata(166) <= \<const0>\;
S03_AXI_rdata(165) <= \<const0>\;
S03_AXI_rdata(164) <= \<const0>\;
S03_AXI_rdata(163) <= \<const0>\;
S03_AXI_rdata(162) <= \<const0>\;
S03_AXI_rdata(161) <= \<const0>\;
S03_AXI_rdata(160) <= \<const0>\;
S03_AXI_rdata(159) <= \<const0>\;
S03_AXI_rdata(158) <= \<const0>\;
S03_AXI_rdata(157) <= \<const0>\;
S03_AXI_rdata(156) <= \<const0>\;
S03_AXI_rdata(155) <= \<const0>\;
S03_AXI_rdata(154) <= \<const0>\;
S03_AXI_rdata(153) <= \<const0>\;
S03_AXI_rdata(152) <= \<const0>\;
S03_AXI_rdata(151) <= \<const0>\;
S03_AXI_rdata(150) <= \<const0>\;
S03_AXI_rdata(149) <= \<const0>\;
S03_AXI_rdata(148) <= \<const0>\;
S03_AXI_rdata(147) <= \<const0>\;
S03_AXI_rdata(146) <= \<const0>\;
S03_AXI_rdata(145) <= \<const0>\;
S03_AXI_rdata(144) <= \<const0>\;
S03_AXI_rdata(143) <= \<const0>\;
S03_AXI_rdata(142) <= \<const0>\;
S03_AXI_rdata(141) <= \<const0>\;
S03_AXI_rdata(140) <= \<const0>\;
S03_AXI_rdata(139) <= \<const0>\;
S03_AXI_rdata(138) <= \<const0>\;
S03_AXI_rdata(137) <= \<const0>\;
S03_AXI_rdata(136) <= \<const0>\;
S03_AXI_rdata(135) <= \<const0>\;
S03_AXI_rdata(134) <= \<const0>\;
S03_AXI_rdata(133) <= \<const0>\;
S03_AXI_rdata(132) <= \<const0>\;
S03_AXI_rdata(131) <= \<const0>\;
S03_AXI_rdata(130) <= \<const0>\;
S03_AXI_rdata(129) <= \<const0>\;
S03_AXI_rdata(128) <= \<const0>\;
S03_AXI_rdata(127) <= \<const0>\;
S03_AXI_rdata(126) <= \<const0>\;
S03_AXI_rdata(125) <= \<const0>\;
S03_AXI_rdata(124) <= \<const0>\;
S03_AXI_rdata(123) <= \<const0>\;
S03_AXI_rdata(122) <= \<const0>\;
S03_AXI_rdata(121) <= \<const0>\;
S03_AXI_rdata(120) <= \<const0>\;
S03_AXI_rdata(119) <= \<const0>\;
S03_AXI_rdata(118) <= \<const0>\;
S03_AXI_rdata(117) <= \<const0>\;
S03_AXI_rdata(116) <= \<const0>\;
S03_AXI_rdata(115) <= \<const0>\;
S03_AXI_rdata(114) <= \<const0>\;
S03_AXI_rdata(113) <= \<const0>\;
S03_AXI_rdata(112) <= \<const0>\;
S03_AXI_rdata(111) <= \<const0>\;
S03_AXI_rdata(110) <= \<const0>\;
S03_AXI_rdata(109) <= \<const0>\;
S03_AXI_rdata(108) <= \<const0>\;
S03_AXI_rdata(107) <= \<const0>\;
S03_AXI_rdata(106) <= \<const0>\;
S03_AXI_rdata(105) <= \<const0>\;
S03_AXI_rdata(104) <= \<const0>\;
S03_AXI_rdata(103) <= \<const0>\;
S03_AXI_rdata(102) <= \<const0>\;
S03_AXI_rdata(101) <= \<const0>\;
S03_AXI_rdata(100) <= \<const0>\;
S03_AXI_rdata(99) <= \<const0>\;
S03_AXI_rdata(98) <= \<const0>\;
S03_AXI_rdata(97) <= \<const0>\;
S03_AXI_rdata(96) <= \<const0>\;
S03_AXI_rdata(95) <= \<const0>\;
S03_AXI_rdata(94) <= \<const0>\;
S03_AXI_rdata(93) <= \<const0>\;
S03_AXI_rdata(92) <= \<const0>\;
S03_AXI_rdata(91) <= \<const0>\;
S03_AXI_rdata(90) <= \<const0>\;
S03_AXI_rdata(89) <= \<const0>\;
S03_AXI_rdata(88) <= \<const0>\;
S03_AXI_rdata(87) <= \<const0>\;
S03_AXI_rdata(86) <= \<const0>\;
S03_AXI_rdata(85) <= \<const0>\;
S03_AXI_rdata(84) <= \<const0>\;
S03_AXI_rdata(83) <= \<const0>\;
S03_AXI_rdata(82) <= \<const0>\;
S03_AXI_rdata(81) <= \<const0>\;
S03_AXI_rdata(80) <= \<const0>\;
S03_AXI_rdata(79) <= \<const0>\;
S03_AXI_rdata(78) <= \<const0>\;
S03_AXI_rdata(77) <= \<const0>\;
S03_AXI_rdata(76) <= \<const0>\;
S03_AXI_rdata(75) <= \<const0>\;
S03_AXI_rdata(74) <= \<const0>\;
S03_AXI_rdata(73) <= \<const0>\;
S03_AXI_rdata(72) <= \<const0>\;
S03_AXI_rdata(71) <= \<const0>\;
S03_AXI_rdata(70) <= \<const0>\;
S03_AXI_rdata(69) <= \<const0>\;
S03_AXI_rdata(68) <= \<const0>\;
S03_AXI_rdata(67) <= \<const0>\;
S03_AXI_rdata(66) <= \<const0>\;
S03_AXI_rdata(65) <= \<const0>\;
S03_AXI_rdata(64) <= \<const0>\;
S03_AXI_rdata(63) <= \<const0>\;
S03_AXI_rdata(62) <= \<const0>\;
S03_AXI_rdata(61) <= \<const0>\;
S03_AXI_rdata(60) <= \<const0>\;
S03_AXI_rdata(59) <= \<const0>\;
S03_AXI_rdata(58) <= \<const0>\;
S03_AXI_rdata(57) <= \<const0>\;
S03_AXI_rdata(56) <= \<const0>\;
S03_AXI_rdata(55) <= \<const0>\;
S03_AXI_rdata(54) <= \<const0>\;
S03_AXI_rdata(53) <= \<const0>\;
S03_AXI_rdata(52) <= \<const0>\;
S03_AXI_rdata(51) <= \<const0>\;
S03_AXI_rdata(50) <= \<const0>\;
S03_AXI_rdata(49) <= \<const0>\;
S03_AXI_rdata(48) <= \<const0>\;
S03_AXI_rdata(47) <= \<const0>\;
S03_AXI_rdata(46) <= \<const0>\;
S03_AXI_rdata(45) <= \<const0>\;
S03_AXI_rdata(44) <= \<const0>\;
S03_AXI_rdata(43) <= \<const0>\;
S03_AXI_rdata(42) <= \<const0>\;
S03_AXI_rdata(41) <= \<const0>\;
S03_AXI_rdata(40) <= \<const0>\;
S03_AXI_rdata(39) <= \<const0>\;
S03_AXI_rdata(38) <= \<const0>\;
S03_AXI_rdata(37) <= \<const0>\;
S03_AXI_rdata(36) <= \<const0>\;
S03_AXI_rdata(35) <= \<const0>\;
S03_AXI_rdata(34) <= \<const0>\;
S03_AXI_rdata(33) <= \<const0>\;
S03_AXI_rdata(32) <= \<const0>\;
S03_AXI_rdata(31) <= \<const0>\;
S03_AXI_rdata(30) <= \<const0>\;
S03_AXI_rdata(29) <= \<const0>\;
S03_AXI_rdata(28) <= \<const0>\;
S03_AXI_rdata(27) <= \<const0>\;
S03_AXI_rdata(26) <= \<const0>\;
S03_AXI_rdata(25) <= \<const0>\;
S03_AXI_rdata(24) <= \<const0>\;
S03_AXI_rdata(23) <= \<const0>\;
S03_AXI_rdata(22) <= \<const0>\;
S03_AXI_rdata(21) <= \<const0>\;
S03_AXI_rdata(20) <= \<const0>\;
S03_AXI_rdata(19) <= \<const0>\;
S03_AXI_rdata(18) <= \<const0>\;
S03_AXI_rdata(17) <= \<const0>\;
S03_AXI_rdata(16) <= \<const0>\;
S03_AXI_rdata(15) <= \<const0>\;
S03_AXI_rdata(14) <= \<const0>\;
S03_AXI_rdata(13) <= \<const0>\;
S03_AXI_rdata(12) <= \<const0>\;
S03_AXI_rdata(11) <= \<const0>\;
S03_AXI_rdata(10) <= \<const0>\;
S03_AXI_rdata(9) <= \<const0>\;
S03_AXI_rdata(8) <= \<const0>\;
S03_AXI_rdata(7) <= \<const0>\;
S03_AXI_rdata(6) <= \<const0>\;
S03_AXI_rdata(5) <= \<const0>\;
S03_AXI_rdata(4) <= \<const0>\;
S03_AXI_rdata(3) <= \<const0>\;
S03_AXI_rdata(2) <= \<const0>\;
S03_AXI_rdata(1) <= \<const0>\;
S03_AXI_rdata(0) <= \<const0>\;
S03_AXI_rid(3) <= \<const0>\;
S03_AXI_rid(2) <= \<const0>\;
S03_AXI_rid(1) <= \<const0>\;
S03_AXI_rid(0) <= \<const0>\;
S03_AXI_rlast <= \<const0>\;
S03_AXI_rresp(1) <= \<const0>\;
S03_AXI_rresp(0) <= \<const0>\;
S03_AXI_rvalid <= \<const0>\;
S03_AXI_wready <= \<const0>\;
ddr4_mem00_ui_clk <= \<const0>\;
ddr4_mem01_ui_clk <= \^ddr4_mem01_ui_clk\;
ddr4_mem02_ui_clk <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
interconnect: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interconnect_imp_6HQKUY
port map (
M00_AXI_araddr(33 downto 0) => interconnect_DDR4_MEM01_M00_AXI_ARADDR(33 downto 0),
M00_AXI_arburst(1 downto 0) => interconnect_DDR4_MEM01_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => interconnect_DDR4_MEM01_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arlen(7 downto 0) => interconnect_DDR4_MEM01_M00_AXI_ARLEN(7 downto 0),
M00_AXI_arlock(0) => interconnect_DDR4_MEM01_M00_AXI_ARLOCK,
M00_AXI_arprot(2 downto 0) => interconnect_DDR4_MEM01_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => interconnect_DDR4_MEM01_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => M00_AXI_arready,
M00_AXI_arregion(3 downto 0) => M00_AXI_arregion(3 downto 0),
M00_AXI_arsize(2 downto 0) => M00_AXI_arsize(2 downto 0),
M00_AXI_arvalid => interconnect_DDR4_MEM01_M00_AXI_ARVALID,
M00_AXI_awaddr(33 downto 0) => interconnect_DDR4_MEM01_M00_AXI_AWADDR(33 downto 0),
M00_AXI_awburst(1 downto 0) => interconnect_DDR4_MEM01_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => interconnect_DDR4_MEM01_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awlen(7 downto 0) => interconnect_DDR4_MEM01_M00_AXI_AWLEN(7 downto 0),
M00_AXI_awlock(0) => interconnect_DDR4_MEM01_M00_AXI_AWLOCK,
M00_AXI_awprot(2 downto 0) => interconnect_DDR4_MEM01_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => interconnect_DDR4_MEM01_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => M00_AXI_awready,
M00_AXI_awregion(3 downto 0) => M00_AXI_awregion(3 downto 0),
M00_AXI_awsize(2 downto 0) => M00_AXI_awsize(2 downto 0),
M00_AXI_awvalid => interconnect_DDR4_MEM01_M00_AXI_AWVALID,
M00_AXI_bready => interconnect_DDR4_MEM01_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => M00_AXI_bresp(1 downto 0),
M00_AXI_bvalid => M00_AXI_bvalid,
M00_AXI_rdata(511 downto 0) => M00_AXI_rdata(511 downto 0),
M00_AXI_rlast => M00_AXI_rlast,
M00_AXI_rready => interconnect_DDR4_MEM01_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => M00_AXI_rresp(1 downto 0),
M00_AXI_rvalid => M00_AXI_rvalid,
M00_AXI_wdata(511 downto 0) => interconnect_DDR4_MEM01_M00_AXI_WDATA(511 downto 0),
M00_AXI_wlast => interconnect_DDR4_MEM01_M00_AXI_WLAST,
M00_AXI_wready => M00_AXI_wready,
M00_AXI_wstrb(63 downto 0) => interconnect_DDR4_MEM01_M00_AXI_WSTRB(63 downto 0),
M00_AXI_wvalid => interconnect_DDR4_MEM01_M00_AXI_WVALID,
S01_AXI_araddr(38 downto 0) => S01_AXI_araddr(38 downto 0),
S01_AXI_arburst(1 downto 0) => S01_AXI_arburst(1 downto 0),
S01_AXI_arcache(3 downto 0) => S01_AXI_arcache(3 downto 0),
S01_AXI_arid(3 downto 0) => S01_AXI_arid(3 downto 0),
S01_AXI_arlen(7 downto 0) => S01_AXI_arlen(7 downto 0),
S01_AXI_arlock(0) => S01_AXI_arlock(0),
S01_AXI_arprot(2 downto 0) => S01_AXI_arprot(2 downto 0),
S01_AXI_arqos(3 downto 0) => S01_AXI_arqos(3 downto 0),
S01_AXI_arready => S01_AXI_arready,
S01_AXI_arregion(3 downto 0) => S01_AXI_arregion(3 downto 0),
S01_AXI_arvalid => S01_AXI_arvalid,
S01_AXI_awaddr(38 downto 0) => S01_AXI_awaddr(38 downto 0),
S01_AXI_awburst(1 downto 0) => S01_AXI_awburst(1 downto 0),
S01_AXI_awcache(3 downto 0) => S01_AXI_awcache(3 downto 0),
S01_AXI_awid(3 downto 0) => S01_AXI_awid(3 downto 0),
S01_AXI_awlen(7 downto 0) => S01_AXI_awlen(7 downto 0),
S01_AXI_awlock(0) => S01_AXI_awlock(0),
S01_AXI_awprot(2 downto 0) => S01_AXI_awprot(2 downto 0),
S01_AXI_awqos(3 downto 0) => S01_AXI_awqos(3 downto 0),
S01_AXI_awready => S01_AXI_awready,
S01_AXI_awregion(3 downto 0) => S01_AXI_awregion(3 downto 0),
S01_AXI_awvalid => S01_AXI_awvalid,
S01_AXI_bid(3 downto 0) => S01_AXI_bid(3 downto 0),
S01_AXI_bready => S01_AXI_bready,
S01_AXI_bresp(1 downto 0) => S01_AXI_bresp(1 downto 0),
S01_AXI_bvalid => S01_AXI_bvalid,
S01_AXI_rdata(511 downto 0) => S01_AXI_rdata(511 downto 0),
S01_AXI_rid(3 downto 0) => S01_AXI_rid(3 downto 0),
S01_AXI_rlast => S01_AXI_rlast,
S01_AXI_rready => S01_AXI_rready,
S01_AXI_rresp(1 downto 0) => S01_AXI_rresp(1 downto 0),
S01_AXI_rvalid => S01_AXI_rvalid,
S01_AXI_wdata(511 downto 0) => S01_AXI_wdata(511 downto 0),
S01_AXI_wlast => S01_AXI_wlast,
S01_AXI_wready => S01_AXI_wready,
S01_AXI_wstrb(63 downto 0) => S01_AXI_wstrb(63 downto 0),
S01_AXI_wvalid => S01_AXI_wvalid,
S02_AXI_araddr(38 downto 0) => S02_AXI_araddr(38 downto 0),
S02_AXI_arburst(1 downto 0) => S02_AXI_arburst(1 downto 0),
S02_AXI_arcache(3 downto 0) => S02_AXI_arcache(3 downto 0),
S02_AXI_arid(3 downto 0) => S02_AXI_arid(3 downto 0),
S02_AXI_arlen(7 downto 0) => S02_AXI_arlen(7 downto 0),
S02_AXI_arlock(0) => S02_AXI_arlock(0),
S02_AXI_arprot(2 downto 0) => S02_AXI_arprot(2 downto 0),
S02_AXI_arqos(3 downto 0) => S02_AXI_arqos(3 downto 0),
S02_AXI_arready => S02_AXI_arready,
S02_AXI_arregion(3 downto 0) => S02_AXI_arregion(3 downto 0),
S02_AXI_arvalid => S02_AXI_arvalid,
S02_AXI_awaddr(38 downto 0) => S02_AXI_awaddr(38 downto 0),
S02_AXI_awburst(1 downto 0) => S02_AXI_awburst(1 downto 0),
S02_AXI_awcache(3 downto 0) => S02_AXI_awcache(3 downto 0),
S02_AXI_awid(3 downto 0) => S02_AXI_awid(3 downto 0),
S02_AXI_awlen(7 downto 0) => S02_AXI_awlen(7 downto 0),
S02_AXI_awlock(0) => S02_AXI_awlock(0),
S02_AXI_awprot(2 downto 0) => S02_AXI_awprot(2 downto 0),
S02_AXI_awqos(3 downto 0) => S02_AXI_awqos(3 downto 0),
S02_AXI_awready => S02_AXI_awready,
S02_AXI_awregion(3 downto 0) => S02_AXI_awregion(3 downto 0),
S02_AXI_awvalid => S02_AXI_awvalid,
S02_AXI_bid(3 downto 0) => S02_AXI_bid(3 downto 0),
S02_AXI_bready => S02_AXI_bready,
S02_AXI_bresp(1 downto 0) => S02_AXI_bresp(1 downto 0),
S02_AXI_bvalid => S02_AXI_bvalid,
S02_AXI_rdata(511 downto 0) => S02_AXI_rdata(511 downto 0),
S02_AXI_rid(3 downto 0) => S02_AXI_rid(3 downto 0),
S02_AXI_rlast => S02_AXI_rlast,
S02_AXI_rready => S02_AXI_rready,
S02_AXI_rresp(1 downto 0) => S02_AXI_rresp(1 downto 0),
S02_AXI_rvalid => S02_AXI_rvalid,
S02_AXI_wdata(511 downto 0) => S02_AXI_wdata(511 downto 0),
S02_AXI_wlast => S02_AXI_wlast,
S02_AXI_wready => S02_AXI_wready,
S02_AXI_wstrb(63 downto 0) => S02_AXI_wstrb(63 downto 0),
S02_AXI_wvalid => S02_AXI_wvalid,
S04_AXI_araddr(38 downto 0) => S04_AXI_araddr(38 downto 0),
S04_AXI_arcache(3 downto 0) => S04_AXI_arcache(3 downto 0),
S04_AXI_arlen(7 downto 0) => S04_AXI_arlen(7 downto 0),
S04_AXI_arlock(0) => S04_AXI_arlock(0),
S04_AXI_arprot(2 downto 0) => S04_AXI_arprot(2 downto 0),
S04_AXI_arqos(3 downto 0) => S04_AXI_arqos(3 downto 0),
S04_AXI_arready => S04_AXI_arready,
S04_AXI_arregion(3 downto 0) => S04_AXI_arregion(3 downto 0),
S04_AXI_arvalid => S04_AXI_arvalid,
S04_AXI_awaddr(38 downto 0) => S04_AXI_awaddr(38 downto 0),
S04_AXI_awcache(3 downto 0) => S04_AXI_awcache(3 downto 0),
S04_AXI_awlen(7 downto 0) => S04_AXI_awlen(7 downto 0),
S04_AXI_awlock(0) => S04_AXI_awlock(0),
S04_AXI_awprot(2 downto 0) => S04_AXI_awprot(2 downto 0),
S04_AXI_awqos(3 downto 0) => S04_AXI_awqos(3 downto 0),
S04_AXI_awready => S04_AXI_awready,
S04_AXI_awregion(3 downto 0) => S04_AXI_awregion(3 downto 0),
S04_AXI_awvalid => S04_AXI_awvalid,
S04_AXI_bready => S04_AXI_bready,
S04_AXI_bresp(1 downto 0) => S04_AXI_bresp(1 downto 0),
S04_AXI_bvalid => S04_AXI_bvalid,
S04_AXI_rdata(511 downto 0) => S04_AXI_rdata(511 downto 0),
S04_AXI_rlast => S04_AXI_rlast,
S04_AXI_rready => S04_AXI_rready,
S04_AXI_rresp(1 downto 0) => S04_AXI_rresp(1 downto 0),
S04_AXI_rvalid => S04_AXI_rvalid,
S04_AXI_wdata(511 downto 0) => S04_AXI_wdata(511 downto 0),
S04_AXI_wlast => S04_AXI_wlast,
S04_AXI_wready => S04_AXI_wready,
S04_AXI_wstrb(63 downto 0) => S04_AXI_wstrb(63 downto 0),
S04_AXI_wvalid => S04_AXI_wvalid,
S05_AXI_araddr(38 downto 0) => S05_AXI_araddr(38 downto 0),
S05_AXI_arcache(3 downto 0) => S05_AXI_arcache(3 downto 0),
S05_AXI_arlen(7 downto 0) => S05_AXI_arlen(7 downto 0),
S05_AXI_arlock(0) => S05_AXI_arlock(0),
S05_AXI_arprot(2 downto 0) => S05_AXI_arprot(2 downto 0),
S05_AXI_arqos(3 downto 0) => S05_AXI_arqos(3 downto 0),
S05_AXI_arready => S05_AXI_arready,
S05_AXI_arregion(3 downto 0) => S05_AXI_arregion(3 downto 0),
S05_AXI_arvalid => S05_AXI_arvalid,
S05_AXI_awaddr(38 downto 0) => S05_AXI_awaddr(38 downto 0),
S05_AXI_awcache(3 downto 0) => S05_AXI_awcache(3 downto 0),
S05_AXI_awlen(7 downto 0) => S05_AXI_awlen(7 downto 0),
S05_AXI_awlock(0) => S05_AXI_awlock(0),
S05_AXI_awprot(2 downto 0) => S05_AXI_awprot(2 downto 0),
S05_AXI_awqos(3 downto 0) => S05_AXI_awqos(3 downto 0),
S05_AXI_awready => S05_AXI_awready,
S05_AXI_awregion(3 downto 0) => S05_AXI_awregion(3 downto 0),
S05_AXI_awvalid => S05_AXI_awvalid,
S05_AXI_bready => S05_AXI_bready,
S05_AXI_bresp(1 downto 0) => S05_AXI_bresp(1 downto 0),
S05_AXI_bvalid => S05_AXI_bvalid,
S05_AXI_rdata(511 downto 0) => S05_AXI_rdata(511 downto 0),
S05_AXI_rlast => S05_AXI_rlast,
S05_AXI_rready => S05_AXI_rready,
S05_AXI_rresp(1 downto 0) => S05_AXI_rresp(1 downto 0),
S05_AXI_rvalid => S05_AXI_rvalid,
S05_AXI_wdata(511 downto 0) => S05_AXI_wdata(511 downto 0),
S05_AXI_wlast => S05_AXI_wlast,
S05_AXI_wready => S05_AXI_wready,
S05_AXI_wstrb(63 downto 0) => S05_AXI_wstrb(63 downto 0),
S05_AXI_wvalid => S05_AXI_wvalid,
S_AXI_arready => interconnect_DDR4_MEM01_M00_AXI_ARREADY,
S_AXI_awready => interconnect_DDR4_MEM01_M00_AXI_AWREADY,
S_AXI_bresp(1 downto 0) => interconnect_DDR4_MEM01_M00_AXI_BRESP(1 downto 0),
S_AXI_bvalid => interconnect_DDR4_MEM01_M00_AXI_BVALID,
S_AXI_rdata(511 downto 0) => interconnect_DDR4_MEM01_M00_AXI_RDATA(511 downto 0),
S_AXI_rlast => interconnect_DDR4_MEM01_M00_AXI_RLAST,
S_AXI_rresp(1 downto 0) => interconnect_DDR4_MEM01_M00_AXI_RRESP(1 downto 0),
S_AXI_rvalid => interconnect_DDR4_MEM01_M00_AXI_RVALID,
S_AXI_wready => interconnect_DDR4_MEM01_M00_AXI_WREADY,
aclk => aclk,
aclk2 => aclk2,
\bbstub_m_axi_araddr[38]\(38 downto 0) => M00_AXI_araddr(38 downto 0),
\bbstub_m_axi_arburst[1]\(1 downto 0) => M00_AXI_arburst(1 downto 0),
\bbstub_m_axi_arcache[3]\(3 downto 0) => M00_AXI_arcache(3 downto 0),
\bbstub_m_axi_arlen[7]\(7 downto 0) => M00_AXI_arlen(7 downto 0),
\bbstub_m_axi_arlock[0]\(0) => M00_AXI_arlock(0),
\bbstub_m_axi_arprot[2]\(2 downto 0) => M00_AXI_arprot(2 downto 0),
\bbstub_m_axi_arqos[3]\(3 downto 0) => M00_AXI_arqos(3 downto 0),
bbstub_m_axi_arvalid => M00_AXI_arvalid,
\bbstub_m_axi_awaddr[38]\(38 downto 0) => M00_AXI_awaddr(38 downto 0),
\bbstub_m_axi_awburst[1]\(1 downto 0) => M00_AXI_awburst(1 downto 0),
\bbstub_m_axi_awcache[3]\(3 downto 0) => M00_AXI_awcache(3 downto 0),
\bbstub_m_axi_awlen[7]\(7 downto 0) => M00_AXI_awlen(7 downto 0),
\bbstub_m_axi_awlock[0]\(0) => M00_AXI_awlock(0),
\bbstub_m_axi_awprot[2]\(2 downto 0) => M00_AXI_awprot(2 downto 0),
\bbstub_m_axi_awqos[3]\(3 downto 0) => M00_AXI_awqos(3 downto 0),
bbstub_m_axi_awvalid => M00_AXI_awvalid,
bbstub_m_axi_bready => M00_AXI_bready,
bbstub_m_axi_rready => M00_AXI_rready,
\bbstub_m_axi_wdata[511]\(511 downto 0) => M00_AXI_wdata(511 downto 0),
bbstub_m_axi_wlast => M00_AXI_wlast,
\bbstub_m_axi_wstrb[63]\(63 downto 0) => M00_AXI_wstrb(63 downto 0),
bbstub_m_axi_wvalid => M00_AXI_wvalid,
ddr4_mem01_ui_clk => \^ddr4_mem01_ui_clk\,
interconnect_aresetn(0) => psr_aclk_SLR1_interconnect_aresetn,
interconnect_aresetn1(0) => psr_aclk2_SLR1_interconnect_aresetn
);
memory: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory_imp_1K98CM8
port map (
DDR4_MEM01_DIFF_CLK_clk_n => DDR4_MEM01_DIFF_CLK_clk_n,
DDR4_MEM01_DIFF_CLK_clk_p => DDR4_MEM01_DIFF_CLK_clk_p,
DDR4_MEM01_act_n => DDR4_MEM01_act_n,
DDR4_MEM01_adr(16 downto 0) => DDR4_MEM01_adr(16 downto 0),
DDR4_MEM01_ba(1 downto 0) => DDR4_MEM01_ba(1 downto 0),
DDR4_MEM01_bg(1 downto 0) => DDR4_MEM01_bg(1 downto 0),
DDR4_MEM01_ck_c(0) => DDR4_MEM01_ck_c(0),
DDR4_MEM01_ck_t(0) => DDR4_MEM01_ck_t(0),
DDR4_MEM01_cke(0) => DDR4_MEM01_cke(0),
DDR4_MEM01_cs_n(0) => DDR4_MEM01_cs_n(0),
DDR4_MEM01_dq(71 downto 0) => DDR4_MEM01_dq(71 downto 0),
DDR4_MEM01_dqs_c(17 downto 0) => DDR4_MEM01_dqs_c(17 downto 0),
DDR4_MEM01_dqs_t(17 downto 0) => DDR4_MEM01_dqs_t(17 downto 0),
DDR4_MEM01_odt(0) => DDR4_MEM01_odt(0),
DDR4_MEM01_par => DDR4_MEM01_par,
DDR4_MEM01_reset_n => DDR4_MEM01_reset_n,
S_AXI_CTRL_araddr(24 downto 0) => S_AXI_CTRL_araddr(24 downto 0),
S_AXI_CTRL_arprot(2 downto 0) => S_AXI_CTRL_arprot(2 downto 0),
S_AXI_CTRL_arready => S_AXI_CTRL_arready,
S_AXI_CTRL_arvalid => S_AXI_CTRL_arvalid,
S_AXI_CTRL_awaddr(24 downto 0) => S_AXI_CTRL_awaddr(24 downto 0),
S_AXI_CTRL_awprot(2 downto 0) => S_AXI_CTRL_awprot(2 downto 0),
S_AXI_CTRL_awready => S_AXI_CTRL_awready,
S_AXI_CTRL_awvalid => S_AXI_CTRL_awvalid,
S_AXI_CTRL_bready => S_AXI_CTRL_bready,
S_AXI_CTRL_bresp(1 downto 0) => S_AXI_CTRL_bresp(1 downto 0),
S_AXI_CTRL_bvalid => S_AXI_CTRL_bvalid,
S_AXI_CTRL_rdata(31 downto 0) => S_AXI_CTRL_rdata(31 downto 0),
S_AXI_CTRL_rready => S_AXI_CTRL_rready,
S_AXI_CTRL_rresp(1 downto 0) => S_AXI_CTRL_rresp(1 downto 0),
S_AXI_CTRL_rvalid => S_AXI_CTRL_rvalid,
S_AXI_CTRL_wdata(31 downto 0) => S_AXI_CTRL_wdata(31 downto 0),
S_AXI_CTRL_wready => S_AXI_CTRL_wready,
S_AXI_CTRL_wstrb(3 downto 0) => S_AXI_CTRL_wstrb(3 downto 0),
S_AXI_CTRL_wvalid => S_AXI_CTRL_wvalid,
S_AXI_araddr(33 downto 0) => interconnect_DDR4_MEM01_M00_AXI_ARADDR(33 downto 0),
S_AXI_arburst(1 downto 0) => interconnect_DDR4_MEM01_M00_AXI_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => interconnect_DDR4_MEM01_M00_AXI_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => interconnect_DDR4_MEM01_M00_AXI_ARLEN(7 downto 0),
S_AXI_arlock(0) => interconnect_DDR4_MEM01_M00_AXI_ARLOCK,
S_AXI_arprot(2 downto 0) => interconnect_DDR4_MEM01_M00_AXI_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => interconnect_DDR4_MEM01_M00_AXI_ARQOS(3 downto 0),
S_AXI_arready => interconnect_DDR4_MEM01_M00_AXI_ARREADY,
S_AXI_arvalid => interconnect_DDR4_MEM01_M00_AXI_ARVALID,
S_AXI_awaddr(33 downto 0) => interconnect_DDR4_MEM01_M00_AXI_AWADDR(33 downto 0),
S_AXI_awburst(1 downto 0) => interconnect_DDR4_MEM01_M00_AXI_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => interconnect_DDR4_MEM01_M00_AXI_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => interconnect_DDR4_MEM01_M00_AXI_AWLEN(7 downto 0),
S_AXI_awlock(0) => interconnect_DDR4_MEM01_M00_AXI_AWLOCK,
S_AXI_awprot(2 downto 0) => interconnect_DDR4_MEM01_M00_AXI_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => interconnect_DDR4_MEM01_M00_AXI_AWQOS(3 downto 0),
S_AXI_awready => interconnect_DDR4_MEM01_M00_AXI_AWREADY,
S_AXI_awvalid => interconnect_DDR4_MEM01_M00_AXI_AWVALID,
S_AXI_bready => interconnect_DDR4_MEM01_M00_AXI_BREADY,
S_AXI_bresp(1 downto 0) => interconnect_DDR4_MEM01_M00_AXI_BRESP(1 downto 0),
S_AXI_bvalid => interconnect_DDR4_MEM01_M00_AXI_BVALID,
S_AXI_rdata(511 downto 0) => interconnect_DDR4_MEM01_M00_AXI_RDATA(511 downto 0),
S_AXI_rlast => interconnect_DDR4_MEM01_M00_AXI_RLAST,
S_AXI_rready => interconnect_DDR4_MEM01_M00_AXI_RREADY,
S_AXI_rresp(1 downto 0) => interconnect_DDR4_MEM01_M00_AXI_RRESP(1 downto 0),
S_AXI_rvalid => interconnect_DDR4_MEM01_M00_AXI_RVALID,
S_AXI_wdata(511 downto 0) => interconnect_DDR4_MEM01_M00_AXI_WDATA(511 downto 0),
S_AXI_wlast => interconnect_DDR4_MEM01_M00_AXI_WLAST,
S_AXI_wready => interconnect_DDR4_MEM01_M00_AXI_WREADY,
S_AXI_wstrb(63 downto 0) => interconnect_DDR4_MEM01_M00_AXI_WSTRB(63 downto 0),
S_AXI_wvalid => interconnect_DDR4_MEM01_M00_AXI_WVALID,
aclk1 => aclk1,
aresetn => aresetn,
ddr4_mem01_sys_rst => ddr4_mem01_sys_rst,
ddr4_mem01_ui_clk => \^ddr4_mem01_ui_clk\,
ddr4_mem_calib_complete => ddr4_mem_calib_complete,
ddr4_mem_calib_vec(2 downto 0) => ddr4_mem_calib_vec(2 downto 0)
);
reset: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_imp_1YKOSPE
port map (
aclk => aclk,
aclk2 => aclk2,
aresetn => aresetn,
interconnect_aresetn(0) => psr_aclk_SLR1_interconnect_aresetn,
interconnect_aresetn1(0) => psr_aclk2_SLR1_interconnect_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aclk1 : in STD_LOGIC;
aclk2 : in STD_LOGIC;
aresetn : in STD_LOGIC;
S_AXI_CTRL_awaddr : in STD_LOGIC_VECTOR ( 24 downto 0 );
S_AXI_CTRL_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_CTRL_awvalid : in STD_LOGIC;
S_AXI_CTRL_awready : out STD_LOGIC;
S_AXI_CTRL_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_CTRL_wvalid : in STD_LOGIC;
S_AXI_CTRL_wready : out STD_LOGIC;
S_AXI_CTRL_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_CTRL_bvalid : out STD_LOGIC;
S_AXI_CTRL_bready : in STD_LOGIC;
S_AXI_CTRL_araddr : in STD_LOGIC_VECTOR ( 24 downto 0 );
S_AXI_CTRL_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_CTRL_arvalid : in STD_LOGIC;
S_AXI_CTRL_arready : out STD_LOGIC;
S_AXI_CTRL_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_CTRL_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_CTRL_rvalid : out STD_LOGIC;
S_AXI_CTRL_rready : in STD_LOGIC;
S00_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_awready : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wvalid : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_bready : in STD_LOGIC;
S00_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_arready : out STD_LOGIC;
S00_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_awready : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S01_AXI_wlast : in STD_LOGIC;
S01_AXI_wvalid : in STD_LOGIC;
S01_AXI_wready : out STD_LOGIC;
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S01_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_arvalid : in STD_LOGIC;
S01_AXI_arready : out STD_LOGIC;
S01_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_rlast : out STD_LOGIC;
S01_AXI_rvalid : out STD_LOGIC;
S01_AXI_rready : in STD_LOGIC;
S02_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S02_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awvalid : in STD_LOGIC;
S02_AXI_awready : out STD_LOGIC;
S02_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S02_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S02_AXI_wlast : in STD_LOGIC;
S02_AXI_wvalid : in STD_LOGIC;
S02_AXI_wready : out STD_LOGIC;
S02_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_bvalid : out STD_LOGIC;
S02_AXI_bready : in STD_LOGIC;
S02_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S02_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arvalid : in STD_LOGIC;
S02_AXI_arready : out STD_LOGIC;
S02_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S02_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_rlast : out STD_LOGIC;
S02_AXI_rvalid : out STD_LOGIC;
S02_AXI_rready : in STD_LOGIC;
S03_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S03_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S03_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S03_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_awvalid : in STD_LOGIC;
S03_AXI_awready : out STD_LOGIC;
S03_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S03_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S03_AXI_wlast : in STD_LOGIC;
S03_AXI_wvalid : in STD_LOGIC;
S03_AXI_wready : out STD_LOGIC;
S03_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_bvalid : out STD_LOGIC;
S03_AXI_bready : in STD_LOGIC;
S03_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S03_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S03_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S03_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_arvalid : in STD_LOGIC;
S03_AXI_arready : out STD_LOGIC;
S03_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S03_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_rlast : out STD_LOGIC;
S03_AXI_rvalid : out STD_LOGIC;
S03_AXI_rready : in STD_LOGIC;
S04_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S04_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S04_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S04_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S04_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_awvalid : in STD_LOGIC;
S04_AXI_awready : out STD_LOGIC;
S04_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S04_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S04_AXI_wlast : in STD_LOGIC;
S04_AXI_wvalid : in STD_LOGIC;
S04_AXI_wready : out STD_LOGIC;
S04_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S04_AXI_bvalid : out STD_LOGIC;
S04_AXI_bready : in STD_LOGIC;
S04_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S04_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S04_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S04_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S04_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_arvalid : in STD_LOGIC;
S04_AXI_arready : out STD_LOGIC;
S04_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S04_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S04_AXI_rlast : out STD_LOGIC;
S04_AXI_rvalid : out STD_LOGIC;
S04_AXI_rready : in STD_LOGIC;
S05_AXI_awaddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S05_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S05_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S05_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S05_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_awvalid : in STD_LOGIC;
S05_AXI_awready : out STD_LOGIC;
S05_AXI_wdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
S05_AXI_wstrb : in STD_LOGIC_VECTOR ( 63 downto 0 );
S05_AXI_wlast : in STD_LOGIC;
S05_AXI_wvalid : in STD_LOGIC;
S05_AXI_wready : out STD_LOGIC;
S05_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S05_AXI_bvalid : out STD_LOGIC;
S05_AXI_bready : in STD_LOGIC;
S05_AXI_araddr : in STD_LOGIC_VECTOR ( 38 downto 0 );
S05_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S05_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S05_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S05_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S05_AXI_arvalid : in STD_LOGIC;
S05_AXI_arready : out STD_LOGIC;
S05_AXI_rdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
S05_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S05_AXI_rlast : out STD_LOGIC;
S05_AXI_rvalid : out STD_LOGIC;
S05_AXI_rready : in STD_LOGIC;
DDR4_MEM00_dq : inout STD_LOGIC_VECTOR ( 71 downto 0 );
DDR4_MEM00_dqs_t : inout STD_LOGIC_VECTOR ( 17 downto 0 );
DDR4_MEM00_dqs_c : inout STD_LOGIC_VECTOR ( 17 downto 0 );
DDR4_MEM00_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
DDR4_MEM00_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR4_MEM00_bg : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR4_MEM00_act_n : out STD_LOGIC;
DDR4_MEM00_reset_n : out STD_LOGIC;
DDR4_MEM00_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM00_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM00_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM00_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM00_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM00_par : out STD_LOGIC;
DDR4_MEM01_dq : inout STD_LOGIC_VECTOR ( 71 downto 0 );
DDR4_MEM01_dqs_t : inout STD_LOGIC_VECTOR ( 17 downto 0 );
DDR4_MEM01_dqs_c : inout STD_LOGIC_VECTOR ( 17 downto 0 );
DDR4_MEM01_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
DDR4_MEM01_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR4_MEM01_bg : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR4_MEM01_act_n : out STD_LOGIC;
DDR4_MEM01_reset_n : out STD_LOGIC;
DDR4_MEM01_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM01_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM01_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM01_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM01_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM01_par : out STD_LOGIC;
DDR4_MEM02_dq : inout STD_LOGIC_VECTOR ( 71 downto 0 );
DDR4_MEM02_dqs_t : inout STD_LOGIC_VECTOR ( 17 downto 0 );
DDR4_MEM02_dqs_c : inout STD_LOGIC_VECTOR ( 17 downto 0 );
DDR4_MEM02_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
DDR4_MEM02_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR4_MEM02_bg : out STD_LOGIC_VECTOR ( 1 downto 0 );
DDR4_MEM02_act_n : out STD_LOGIC;
DDR4_MEM02_reset_n : out STD_LOGIC;
DDR4_MEM02_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM02_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM02_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM02_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM02_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
DDR4_MEM02_par : out STD_LOGIC;
DDR4_MEM00_DIFF_CLK_clk_p : in STD_LOGIC;
DDR4_MEM00_DIFF_CLK_clk_n : in STD_LOGIC;
DDR4_MEM01_DIFF_CLK_clk_p : in STD_LOGIC;
DDR4_MEM01_DIFF_CLK_clk_n : in STD_LOGIC;
DDR4_MEM02_DIFF_CLK_clk_p : in STD_LOGIC;
DDR4_MEM02_DIFF_CLK_clk_n : in STD_LOGIC;
ddr4_mem00_ui_clk : out STD_LOGIC;
ddr4_mem01_ui_clk : out STD_LOGIC;
ddr4_mem02_ui_clk : out STD_LOGIC;
ddr4_mem00_sys_rst : in STD_LOGIC;
ddr4_mem01_sys_rst : in STD_LOGIC;
ddr4_mem02_sys_rst : in STD_LOGIC;
ddr4_mem_calib_complete : out STD_LOGIC;
ddr4_mem_calib_vec : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_awready : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 511 downto 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wvalid : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 38 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_arready : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 511 downto 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
S01_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_rid : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "pfm_dynamic_memory_subsystem_0,bd_d216,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "bd_d216,Vivado 2020.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "pfm_dynamic_memory_subsystem_0.hwdef";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of DDR4_MEM00_DIFF_CLK_clk_n : signal is "xilinx.com:interface:diff_clock:1.0 DDR4_MEM00_DIFF_CLK CLK_N";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of DDR4_MEM00_DIFF_CLK_clk_n : signal is "XIL_INTERFACENAME DDR4_MEM00_DIFF_CLK, CAN_DEBUG false, FREQ_HZ 300000000";
attribute X_INTERFACE_INFO of DDR4_MEM00_DIFF_CLK_clk_p : signal is "xilinx.com:interface:diff_clock:1.0 DDR4_MEM00_DIFF_CLK CLK_P";
attribute X_INTERFACE_INFO of DDR4_MEM00_act_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 ACT_N";
attribute X_INTERFACE_INFO of DDR4_MEM00_par : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 PAR";
attribute X_INTERFACE_PARAMETER of DDR4_MEM00_par : signal is "XIL_INTERFACENAME DDR4_MEM00, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
attribute X_INTERFACE_INFO of DDR4_MEM00_reset_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 RESET_N";
attribute X_INTERFACE_INFO of DDR4_MEM01_DIFF_CLK_clk_n : signal is "xilinx.com:interface:diff_clock:1.0 DDR4_MEM01_DIFF_CLK CLK_N";
attribute X_INTERFACE_PARAMETER of DDR4_MEM01_DIFF_CLK_clk_n : signal is "XIL_INTERFACENAME DDR4_MEM01_DIFF_CLK, CAN_DEBUG false, FREQ_HZ 300000000";
attribute X_INTERFACE_INFO of DDR4_MEM01_DIFF_CLK_clk_p : signal is "xilinx.com:interface:diff_clock:1.0 DDR4_MEM01_DIFF_CLK CLK_P";
attribute X_INTERFACE_INFO of DDR4_MEM01_act_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 ACT_N";
attribute X_INTERFACE_INFO of DDR4_MEM01_par : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 PAR";
attribute X_INTERFACE_PARAMETER of DDR4_MEM01_par : signal is "XIL_INTERFACENAME DDR4_MEM01, CAN_DEBUG false, TIMEPERIOD_PS 833, MEMORY_TYPE RDIMMs, MEMORY_PART MTA18ASF2G72PZ-2G3, DATA_WIDTH 72, CS_ENABLED true, DATA_MASK_ENABLED NONE, SLOT Single, CUSTOM_PARTS no_file_loaded, MEM_ADDR_MAP ROW_COLUMN_BANK_INTLV, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME RD_PRI_REG, CAS_LATENCY 17, CAS_WRITE_LATENCY 12";
attribute X_INTERFACE_INFO of DDR4_MEM01_reset_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 RESET_N";
attribute X_INTERFACE_INFO of DDR4_MEM02_DIFF_CLK_clk_n : signal is "xilinx.com:interface:diff_clock:1.0 DDR4_MEM02_DIFF_CLK CLK_N";
attribute X_INTERFACE_PARAMETER of DDR4_MEM02_DIFF_CLK_clk_n : signal is "XIL_INTERFACENAME DDR4_MEM02_DIFF_CLK, CAN_DEBUG false, FREQ_HZ 300000000";
attribute X_INTERFACE_INFO of DDR4_MEM02_DIFF_CLK_clk_p : signal is "xilinx.com:interface:diff_clock:1.0 DDR4_MEM02_DIFF_CLK CLK_P";
attribute X_INTERFACE_INFO of DDR4_MEM02_act_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 ACT_N";
attribute X_INTERFACE_INFO of DDR4_MEM02_par : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 PAR";
attribute X_INTERFACE_PARAMETER of DDR4_MEM02_par : signal is "XIL_INTERFACENAME DDR4_MEM02, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
attribute X_INTERFACE_INFO of DDR4_MEM02_reset_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 RESET_N";
attribute X_INTERFACE_INFO of M00_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY";
attribute X_INTERFACE_INFO of M00_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID";
attribute X_INTERFACE_INFO of M00_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY";
attribute X_INTERFACE_INFO of M00_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID";
attribute X_INTERFACE_INFO of M00_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BREADY";
attribute X_INTERFACE_INFO of M00_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BVALID";
attribute X_INTERFACE_INFO of M00_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RLAST";
attribute X_INTERFACE_INFO of M00_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RREADY";
attribute X_INTERFACE_PARAMETER of M00_AXI_rready : signal is "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 300000000, ID_WIDTH 0, ADDR_WIDTH 39, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pfm_dynamic_ddrmem_1_c0_ddr4_ui_clk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
attribute X_INTERFACE_INFO of M00_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RVALID";
attribute X_INTERFACE_INFO of M00_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WLAST";
attribute X_INTERFACE_INFO of M00_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WREADY";
attribute X_INTERFACE_INFO of M00_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WVALID";
attribute X_INTERFACE_INFO of S00_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
attribute X_INTERFACE_INFO of S00_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
attribute X_INTERFACE_INFO of S00_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
attribute X_INTERFACE_INFO of S00_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
attribute X_INTERFACE_INFO of S00_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
attribute X_INTERFACE_INFO of S00_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
attribute X_INTERFACE_INFO of S00_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RLAST";
attribute X_INTERFACE_INFO of S00_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
attribute X_INTERFACE_PARAMETER of S00_AXI_rready : signal is "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 300000000, ID_WIDTH 4, ADDR_WIDTH 39, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pfm_dynamic_clkwiz_kernel_clk_out1, NUM_READ_THREADS 2, NUM_WRITE_THREADS 2, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
attribute X_INTERFACE_INFO of S00_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
attribute X_INTERFACE_INFO of S00_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WLAST";
attribute X_INTERFACE_INFO of S00_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
attribute X_INTERFACE_INFO of S00_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
attribute X_INTERFACE_INFO of S01_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARREADY";
attribute X_INTERFACE_INFO of S01_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARVALID";
attribute X_INTERFACE_INFO of S01_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWREADY";
attribute X_INTERFACE_INFO of S01_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWVALID";
attribute X_INTERFACE_INFO of S01_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BREADY";
attribute X_INTERFACE_INFO of S01_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BVALID";
attribute X_INTERFACE_INFO of S01_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RLAST";
attribute X_INTERFACE_INFO of S01_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RREADY";
attribute X_INTERFACE_INFO of S01_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RVALID";
attribute X_INTERFACE_INFO of S01_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WLAST";
attribute X_INTERFACE_INFO of S01_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WREADY";
attribute X_INTERFACE_INFO of S01_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WVALID";
attribute X_INTERFACE_INFO of S02_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARREADY";
attribute X_INTERFACE_INFO of S02_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARVALID";
attribute X_INTERFACE_INFO of S02_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWREADY";
attribute X_INTERFACE_INFO of S02_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWVALID";
attribute X_INTERFACE_INFO of S02_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S02_AXI BREADY";
attribute X_INTERFACE_INFO of S02_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI BVALID";
attribute X_INTERFACE_INFO of S02_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RLAST";
attribute X_INTERFACE_INFO of S02_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RREADY";
attribute X_INTERFACE_INFO of S02_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RVALID";
attribute X_INTERFACE_INFO of S02_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WLAST";
attribute X_INTERFACE_INFO of S02_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WREADY";
attribute X_INTERFACE_INFO of S02_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WVALID";
attribute X_INTERFACE_INFO of S03_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARREADY";
attribute X_INTERFACE_INFO of S03_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARVALID";
attribute X_INTERFACE_INFO of S03_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWREADY";
attribute X_INTERFACE_INFO of S03_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWVALID";
attribute X_INTERFACE_INFO of S03_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S03_AXI BREADY";
attribute X_INTERFACE_INFO of S03_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI BVALID";
attribute X_INTERFACE_INFO of S03_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RLAST";
attribute X_INTERFACE_INFO of S03_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RREADY";
attribute X_INTERFACE_PARAMETER of S03_AXI_rready : signal is "XIL_INTERFACENAME S03_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 300000000, ID_WIDTH 4, ADDR_WIDTH 39, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pfm_dynamic_clkwiz_kernel_clk_out1, NUM_READ_THREADS 2, NUM_WRITE_THREADS 2, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
attribute X_INTERFACE_INFO of S03_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RVALID";
attribute X_INTERFACE_INFO of S03_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WLAST";
attribute X_INTERFACE_INFO of S03_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WREADY";
attribute X_INTERFACE_INFO of S03_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WVALID";
attribute X_INTERFACE_INFO of S04_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARREADY";
attribute X_INTERFACE_INFO of S04_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARVALID";
attribute X_INTERFACE_INFO of S04_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWREADY";
attribute X_INTERFACE_INFO of S04_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWVALID";
attribute X_INTERFACE_INFO of S04_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S04_AXI BREADY";
attribute X_INTERFACE_INFO of S04_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI BVALID";
attribute X_INTERFACE_INFO of S04_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RLAST";
attribute X_INTERFACE_INFO of S04_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RREADY";
attribute X_INTERFACE_PARAMETER of S04_AXI_rready : signal is "XIL_INTERFACENAME S04_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 300000000, ID_WIDTH 0, ADDR_WIDTH 39, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pfm_dynamic_clkwiz_kernel_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
attribute X_INTERFACE_INFO of S04_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RVALID";
attribute X_INTERFACE_INFO of S04_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WLAST";
attribute X_INTERFACE_INFO of S04_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WREADY";
attribute X_INTERFACE_INFO of S04_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WVALID";
attribute X_INTERFACE_INFO of S05_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARREADY";
attribute X_INTERFACE_INFO of S05_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARVALID";
attribute X_INTERFACE_INFO of S05_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWREADY";
attribute X_INTERFACE_INFO of S05_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWVALID";
attribute X_INTERFACE_INFO of S05_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S05_AXI BREADY";
attribute X_INTERFACE_INFO of S05_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI BVALID";
attribute X_INTERFACE_INFO of S05_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RLAST";
attribute X_INTERFACE_INFO of S05_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RREADY";
attribute X_INTERFACE_PARAMETER of S05_AXI_rready : signal is "XIL_INTERFACENAME S05_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 300000000, ID_WIDTH 0, ADDR_WIDTH 39, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pfm_dynamic_clkwiz_kernel_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
attribute X_INTERFACE_INFO of S05_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RVALID";
attribute X_INTERFACE_INFO of S05_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WLAST";
attribute X_INTERFACE_INFO of S05_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WREADY";
attribute X_INTERFACE_INFO of S05_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WVALID";
attribute X_INTERFACE_INFO of S_AXI_CTRL_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL ARREADY";
attribute X_INTERFACE_INFO of S_AXI_CTRL_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL ARVALID";
attribute X_INTERFACE_INFO of S_AXI_CTRL_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL AWREADY";
attribute X_INTERFACE_INFO of S_AXI_CTRL_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL AWVALID";
attribute X_INTERFACE_INFO of S_AXI_CTRL_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL BREADY";
attribute X_INTERFACE_INFO of S_AXI_CTRL_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL BVALID";
attribute X_INTERFACE_INFO of S_AXI_CTRL_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL RREADY";
attribute X_INTERFACE_PARAMETER of S_AXI_CTRL_rready : signal is "XIL_INTERFACENAME S_AXI_CTRL, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50925925, ID_WIDTH 0, ADDR_WIDTH 25, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN pfm_dynamic_clkwiz_sysclks_clk_out2, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
attribute X_INTERFACE_INFO of S_AXI_CTRL_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL RVALID";
attribute X_INTERFACE_INFO of S_AXI_CTRL_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL WREADY";
attribute X_INTERFACE_INFO of S_AXI_CTRL_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL WVALID";
attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK.aclk CLK";
attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK.aclk, FREQ_HZ 300000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pfm_dynamic_clkwiz_kernel_clk_out1, ASSOCIATED_BUSIF S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI, INSERT_VIP 0, ASSOCIATED_CLKEN m_sc_aclken";
attribute X_INTERFACE_INFO of aclk1 : signal is "xilinx.com:signal:clock:1.0 CLK.aclk1 CLK";
attribute X_INTERFACE_PARAMETER of aclk1 : signal is "XIL_INTERFACENAME CLK.aclk1, FREQ_HZ 50925925, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pfm_dynamic_clkwiz_sysclks_clk_out2, ASSOCIATED_BUSIF S_AXI_CTRL, INSERT_VIP 0";
attribute X_INTERFACE_INFO of aclk2 : signal is "xilinx.com:signal:clock:1.0 CLK.aclk2 CLK";
attribute X_INTERFACE_PARAMETER of aclk2 : signal is "XIL_INTERFACENAME CLK.aclk2, FREQ_HZ 300000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pfm_dynamic_ddrmem_1_c0_ddr4_ui_clk, ASSOCIATED_BUSIF M00_AXI, INSERT_VIP 0, ASSOCIATED_CLKEN m_sc_aclken";
attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST.aresetn RST";
attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST.aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0";
attribute X_INTERFACE_INFO of ddr4_mem00_sys_rst : signal is "xilinx.com:signal:reset:1.0 RST.ddr4_mem00_sys_rst RST";
attribute X_INTERFACE_PARAMETER of ddr4_mem00_sys_rst : signal is "XIL_INTERFACENAME RST.ddr4_mem00_sys_rst, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
attribute X_INTERFACE_INFO of ddr4_mem00_ui_clk : signal is "xilinx.com:signal:clock:1.0 CLK.ddr4_mem00_ui_clk CLK";
attribute X_INTERFACE_PARAMETER of ddr4_mem00_ui_clk : signal is "XIL_INTERFACENAME CLK.ddr4_mem00_ui_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pfm_dynamic_memory_subsystem_0_ddr4_mem00_ui_clk, INSERT_VIP 0";
attribute X_INTERFACE_INFO of ddr4_mem01_sys_rst : signal is "xilinx.com:signal:reset:1.0 RST.ddr4_mem01_sys_rst RST";
attribute X_INTERFACE_PARAMETER of ddr4_mem01_sys_rst : signal is "XIL_INTERFACENAME RST.ddr4_mem01_sys_rst, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
attribute X_INTERFACE_INFO of ddr4_mem01_ui_clk : signal is "xilinx.com:signal:clock:1.0 CLK.ddr4_mem01_ui_clk CLK";
attribute X_INTERFACE_PARAMETER of ddr4_mem01_ui_clk : signal is "XIL_INTERFACENAME CLK.ddr4_mem01_ui_clk, FREQ_HZ 300000000, FREQ_TOLERANCE_HZ 0, PHASE 0.00, CLK_DOMAIN bd_d216_ddr4_mem01_0_c0_ddr4_ui_clk, INSERT_VIP 0";
attribute X_INTERFACE_INFO of ddr4_mem02_sys_rst : signal is "xilinx.com:signal:reset:1.0 RST.ddr4_mem02_sys_rst RST";
attribute X_INTERFACE_PARAMETER of ddr4_mem02_sys_rst : signal is "XIL_INTERFACENAME RST.ddr4_mem02_sys_rst, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
attribute X_INTERFACE_INFO of ddr4_mem02_ui_clk : signal is "xilinx.com:signal:clock:1.0 CLK.ddr4_mem02_ui_clk CLK";
attribute X_INTERFACE_PARAMETER of ddr4_mem02_ui_clk : signal is "XIL_INTERFACENAME CLK.ddr4_mem02_ui_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN pfm_dynamic_memory_subsystem_0_ddr4_mem02_ui_clk, INSERT_VIP 0";
attribute X_INTERFACE_INFO of ddr4_mem_calib_complete : signal is "xilinx.com:signal:data:1.0 DATA.ddr4_mem_calib_complete DATA";
attribute X_INTERFACE_PARAMETER of ddr4_mem_calib_complete : signal is "XIL_INTERFACENAME DATA.ddr4_mem_calib_complete, LAYERED_METADATA undef";
attribute X_INTERFACE_INFO of DDR4_MEM00_adr : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 ADR";
attribute X_INTERFACE_INFO of DDR4_MEM00_ba : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 BA";
attribute X_INTERFACE_INFO of DDR4_MEM00_bg : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 BG";
attribute X_INTERFACE_INFO of DDR4_MEM00_ck_c : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 CK_C";
attribute X_INTERFACE_INFO of DDR4_MEM00_ck_t : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 CK_T";
attribute X_INTERFACE_INFO of DDR4_MEM00_cke : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 CKE";
attribute X_INTERFACE_INFO of DDR4_MEM00_cs_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 CS_N";
attribute X_INTERFACE_INFO of DDR4_MEM00_dq : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 DQ";
attribute X_INTERFACE_INFO of DDR4_MEM00_dqs_c : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 DQS_C";
attribute X_INTERFACE_INFO of DDR4_MEM00_dqs_t : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 DQS_T";
attribute X_INTERFACE_INFO of DDR4_MEM00_odt : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM00 ODT";
attribute X_INTERFACE_INFO of DDR4_MEM01_adr : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 ADR";
attribute X_INTERFACE_INFO of DDR4_MEM01_ba : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 BA";
attribute X_INTERFACE_INFO of DDR4_MEM01_bg : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 BG";
attribute X_INTERFACE_INFO of DDR4_MEM01_ck_c : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 CK_C";
attribute X_INTERFACE_INFO of DDR4_MEM01_ck_t : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 CK_T";
attribute X_INTERFACE_INFO of DDR4_MEM01_cke : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 CKE";
attribute X_INTERFACE_INFO of DDR4_MEM01_cs_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 CS_N";
attribute X_INTERFACE_INFO of DDR4_MEM01_dq : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 DQ";
attribute X_INTERFACE_INFO of DDR4_MEM01_dqs_c : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 DQS_C";
attribute X_INTERFACE_INFO of DDR4_MEM01_dqs_t : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 DQS_T";
attribute X_INTERFACE_INFO of DDR4_MEM01_odt : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM01 ODT";
attribute X_INTERFACE_INFO of DDR4_MEM02_adr : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 ADR";
attribute X_INTERFACE_INFO of DDR4_MEM02_ba : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 BA";
attribute X_INTERFACE_INFO of DDR4_MEM02_bg : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 BG";
attribute X_INTERFACE_INFO of DDR4_MEM02_ck_c : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 CK_C";
attribute X_INTERFACE_INFO of DDR4_MEM02_ck_t : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 CK_T";
attribute X_INTERFACE_INFO of DDR4_MEM02_cke : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 CKE";
attribute X_INTERFACE_INFO of DDR4_MEM02_cs_n : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 CS_N";
attribute X_INTERFACE_INFO of DDR4_MEM02_dq : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 DQ";
attribute X_INTERFACE_INFO of DDR4_MEM02_dqs_c : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 DQS_C";
attribute X_INTERFACE_INFO of DDR4_MEM02_dqs_t : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 DQS_T";
attribute X_INTERFACE_INFO of DDR4_MEM02_odt : signal is "xilinx.com:interface:ddr4:1.0 DDR4_MEM02 ODT";
attribute X_INTERFACE_INFO of M00_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR";
attribute X_INTERFACE_INFO of M00_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST";
attribute X_INTERFACE_INFO of M00_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE";
attribute X_INTERFACE_INFO of M00_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN";
attribute X_INTERFACE_INFO of M00_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK";
attribute X_INTERFACE_INFO of M00_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT";
attribute X_INTERFACE_INFO of M00_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS";
attribute X_INTERFACE_INFO of M00_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION";
attribute X_INTERFACE_INFO of M00_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE";
attribute X_INTERFACE_INFO of M00_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR";
attribute X_INTERFACE_INFO of M00_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST";
attribute X_INTERFACE_INFO of M00_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE";
attribute X_INTERFACE_INFO of M00_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN";
attribute X_INTERFACE_INFO of M00_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK";
attribute X_INTERFACE_INFO of M00_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT";
attribute X_INTERFACE_INFO of M00_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS";
attribute X_INTERFACE_INFO of M00_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION";
attribute X_INTERFACE_INFO of M00_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE";
attribute X_INTERFACE_INFO of M00_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BRESP";
attribute X_INTERFACE_INFO of M00_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RDATA";
attribute X_INTERFACE_INFO of M00_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RRESP";
attribute X_INTERFACE_INFO of M00_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WDATA";
attribute X_INTERFACE_INFO of M00_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB";
attribute X_INTERFACE_INFO of S00_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
attribute X_INTERFACE_INFO of S00_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST";
attribute X_INTERFACE_INFO of S00_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE";
attribute X_INTERFACE_INFO of S00_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARID";
attribute X_INTERFACE_INFO of S00_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN";
attribute X_INTERFACE_INFO of S00_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK";
attribute X_INTERFACE_INFO of S00_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
attribute X_INTERFACE_INFO of S00_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS";
attribute X_INTERFACE_INFO of S00_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREGION";
attribute X_INTERFACE_INFO of S00_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE";
attribute X_INTERFACE_INFO of S00_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
attribute X_INTERFACE_INFO of S00_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST";
attribute X_INTERFACE_INFO of S00_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE";
attribute X_INTERFACE_INFO of S00_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWID";
attribute X_INTERFACE_INFO of S00_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN";
attribute X_INTERFACE_INFO of S00_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK";
attribute X_INTERFACE_INFO of S00_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
attribute X_INTERFACE_INFO of S00_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS";
attribute X_INTERFACE_INFO of S00_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREGION";
attribute X_INTERFACE_INFO of S00_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE";
attribute X_INTERFACE_INFO of S00_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BID";
attribute X_INTERFACE_INFO of S00_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
attribute X_INTERFACE_INFO of S00_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
attribute X_INTERFACE_INFO of S00_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RID";
attribute X_INTERFACE_INFO of S00_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
attribute X_INTERFACE_INFO of S00_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
attribute X_INTERFACE_INFO of S00_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
attribute X_INTERFACE_INFO of S01_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARADDR";
attribute X_INTERFACE_INFO of S01_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARBURST";
attribute X_INTERFACE_INFO of S01_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE";
attribute X_INTERFACE_INFO of S01_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARID";
attribute X_INTERFACE_INFO of S01_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARLEN";
attribute X_INTERFACE_INFO of S01_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK";
attribute X_INTERFACE_INFO of S01_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARPROT";
attribute X_INTERFACE_INFO of S01_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARQOS";
attribute X_INTERFACE_INFO of S01_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARREGION";
attribute X_INTERFACE_INFO of S01_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWADDR";
attribute X_INTERFACE_INFO of S01_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWBURST";
attribute X_INTERFACE_INFO of S01_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE";
attribute X_INTERFACE_INFO of S01_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWID";
attribute X_INTERFACE_INFO of S01_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWLEN";
attribute X_INTERFACE_INFO of S01_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK";
attribute X_INTERFACE_INFO of S01_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWPROT";
attribute X_INTERFACE_INFO of S01_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWQOS";
attribute X_INTERFACE_INFO of S01_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWREGION";
attribute X_INTERFACE_INFO of S01_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BID";
attribute X_INTERFACE_INFO of S01_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BRESP";
attribute X_INTERFACE_INFO of S01_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RDATA";
attribute X_INTERFACE_INFO of S01_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RID";
attribute X_INTERFACE_PARAMETER of S01_AXI_rid : signal is "XIL_INTERFACENAME S01_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 300000000, ID_WIDTH 4, ADDR_WIDTH 39, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pfm_dynamic_clkwiz_kernel_clk_out1, NUM_READ_THREADS 2, NUM_WRITE_THREADS 2, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
attribute X_INTERFACE_INFO of S01_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RRESP";
attribute X_INTERFACE_INFO of S01_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WDATA";
attribute X_INTERFACE_INFO of S01_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WSTRB";
attribute X_INTERFACE_INFO of S02_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARADDR";
attribute X_INTERFACE_INFO of S02_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARBURST";
attribute X_INTERFACE_INFO of S02_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARCACHE";
attribute X_INTERFACE_INFO of S02_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARID";
attribute X_INTERFACE_INFO of S02_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARLEN";
attribute X_INTERFACE_INFO of S02_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARLOCK";
attribute X_INTERFACE_INFO of S02_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARPROT";
attribute X_INTERFACE_INFO of S02_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARQOS";
attribute X_INTERFACE_INFO of S02_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARREGION";
attribute X_INTERFACE_INFO of S02_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWADDR";
attribute X_INTERFACE_INFO of S02_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWBURST";
attribute X_INTERFACE_INFO of S02_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWCACHE";
attribute X_INTERFACE_INFO of S02_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWID";
attribute X_INTERFACE_INFO of S02_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWLEN";
attribute X_INTERFACE_INFO of S02_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWLOCK";
attribute X_INTERFACE_INFO of S02_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWPROT";
attribute X_INTERFACE_INFO of S02_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWQOS";
attribute X_INTERFACE_INFO of S02_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWREGION";
attribute X_INTERFACE_INFO of S02_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI BID";
attribute X_INTERFACE_INFO of S02_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S02_AXI BRESP";
attribute X_INTERFACE_INFO of S02_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RDATA";
attribute X_INTERFACE_INFO of S02_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RID";
attribute X_INTERFACE_PARAMETER of S02_AXI_rid : signal is "XIL_INTERFACENAME S02_AXI, DATA_WIDTH 512, PROTOCOL AXI4, FREQ_HZ 300000000, ID_WIDTH 4, ADDR_WIDTH 39, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN pfm_dynamic_clkwiz_kernel_clk_out1, NUM_READ_THREADS 2, NUM_WRITE_THREADS 2, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
attribute X_INTERFACE_INFO of S02_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RRESP";
attribute X_INTERFACE_INFO of S02_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WDATA";
attribute X_INTERFACE_INFO of S02_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WSTRB";
attribute X_INTERFACE_INFO of S03_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARADDR";
attribute X_INTERFACE_INFO of S03_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARBURST";
attribute X_INTERFACE_INFO of S03_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARCACHE";
attribute X_INTERFACE_INFO of S03_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARID";
attribute X_INTERFACE_INFO of S03_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARLEN";
attribute X_INTERFACE_INFO of S03_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARLOCK";
attribute X_INTERFACE_INFO of S03_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARPROT";
attribute X_INTERFACE_INFO of S03_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARQOS";
attribute X_INTERFACE_INFO of S03_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARREGION";
attribute X_INTERFACE_INFO of S03_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARSIZE";
attribute X_INTERFACE_INFO of S03_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWADDR";
attribute X_INTERFACE_INFO of S03_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWBURST";
attribute X_INTERFACE_INFO of S03_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWCACHE";
attribute X_INTERFACE_INFO of S03_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWID";
attribute X_INTERFACE_INFO of S03_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWLEN";
attribute X_INTERFACE_INFO of S03_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWLOCK";
attribute X_INTERFACE_INFO of S03_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWPROT";
attribute X_INTERFACE_INFO of S03_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWQOS";
attribute X_INTERFACE_INFO of S03_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWREGION";
attribute X_INTERFACE_INFO of S03_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWSIZE";
attribute X_INTERFACE_INFO of S03_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI BID";
attribute X_INTERFACE_INFO of S03_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S03_AXI BRESP";
attribute X_INTERFACE_INFO of S03_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RDATA";
attribute X_INTERFACE_INFO of S03_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RID";
attribute X_INTERFACE_INFO of S03_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RRESP";
attribute X_INTERFACE_INFO of S03_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WDATA";
attribute X_INTERFACE_INFO of S03_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WSTRB";
attribute X_INTERFACE_INFO of S04_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARADDR";
attribute X_INTERFACE_INFO of S04_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARCACHE";
attribute X_INTERFACE_INFO of S04_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARLEN";
attribute X_INTERFACE_INFO of S04_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARLOCK";
attribute X_INTERFACE_INFO of S04_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARPROT";
attribute X_INTERFACE_INFO of S04_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARQOS";
attribute X_INTERFACE_INFO of S04_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARREGION";
attribute X_INTERFACE_INFO of S04_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWADDR";
attribute X_INTERFACE_INFO of S04_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWCACHE";
attribute X_INTERFACE_INFO of S04_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWLEN";
attribute X_INTERFACE_INFO of S04_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWLOCK";
attribute X_INTERFACE_INFO of S04_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWPROT";
attribute X_INTERFACE_INFO of S04_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWQOS";
attribute X_INTERFACE_INFO of S04_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWREGION";
attribute X_INTERFACE_INFO of S04_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S04_AXI BRESP";
attribute X_INTERFACE_INFO of S04_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RDATA";
attribute X_INTERFACE_INFO of S04_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RRESP";
attribute X_INTERFACE_INFO of S04_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WDATA";
attribute X_INTERFACE_INFO of S04_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WSTRB";
attribute X_INTERFACE_INFO of S05_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARADDR";
attribute X_INTERFACE_INFO of S05_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARCACHE";
attribute X_INTERFACE_INFO of S05_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARLEN";
attribute X_INTERFACE_INFO of S05_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARLOCK";
attribute X_INTERFACE_INFO of S05_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARPROT";
attribute X_INTERFACE_INFO of S05_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARQOS";
attribute X_INTERFACE_INFO of S05_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARREGION";
attribute X_INTERFACE_INFO of S05_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWADDR";
attribute X_INTERFACE_INFO of S05_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWCACHE";
attribute X_INTERFACE_INFO of S05_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWLEN";
attribute X_INTERFACE_INFO of S05_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWLOCK";
attribute X_INTERFACE_INFO of S05_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWPROT";
attribute X_INTERFACE_INFO of S05_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWQOS";
attribute X_INTERFACE_INFO of S05_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWREGION";
attribute X_INTERFACE_INFO of S05_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S05_AXI BRESP";
attribute X_INTERFACE_INFO of S05_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RDATA";
attribute X_INTERFACE_INFO of S05_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RRESP";
attribute X_INTERFACE_INFO of S05_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WDATA";
attribute X_INTERFACE_INFO of S05_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WSTRB";
attribute X_INTERFACE_INFO of S_AXI_CTRL_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL ARADDR";
attribute X_INTERFACE_INFO of S_AXI_CTRL_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL ARPROT";
attribute X_INTERFACE_INFO of S_AXI_CTRL_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL AWADDR";
attribute X_INTERFACE_INFO of S_AXI_CTRL_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL AWPROT";
attribute X_INTERFACE_INFO of S_AXI_CTRL_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL BRESP";
attribute X_INTERFACE_INFO of S_AXI_CTRL_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL RDATA";
attribute X_INTERFACE_INFO of S_AXI_CTRL_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL RRESP";
attribute X_INTERFACE_INFO of S_AXI_CTRL_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL WDATA";
attribute X_INTERFACE_INFO of S_AXI_CTRL_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI_CTRL WSTRB";
attribute X_INTERFACE_INFO of ddr4_mem_calib_vec : signal is "xilinx.com:signal:data:1.0 DATA.ddr4_mem_calib_vec DATA";
attribute X_INTERFACE_PARAMETER of ddr4_mem_calib_vec : signal is "XIL_INTERFACENAME DATA.ddr4_mem_calib_vec, LAYERED_METADATA undef, PortWidth 3";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_bd_d216
port map (
DDR4_MEM00_DIFF_CLK_clk_n => DDR4_MEM00_DIFF_CLK_clk_n,
DDR4_MEM00_DIFF_CLK_clk_p => DDR4_MEM00_DIFF_CLK_clk_p,
DDR4_MEM00_act_n => DDR4_MEM00_act_n,
DDR4_MEM00_adr(16 downto 0) => DDR4_MEM00_adr(16 downto 0),
DDR4_MEM00_ba(1 downto 0) => DDR4_MEM00_ba(1 downto 0),
DDR4_MEM00_bg(1 downto 0) => DDR4_MEM00_bg(1 downto 0),
DDR4_MEM00_ck_c(0) => DDR4_MEM00_ck_c(0),
DDR4_MEM00_ck_t(0) => DDR4_MEM00_ck_t(0),
DDR4_MEM00_cke(0) => DDR4_MEM00_cke(0),
DDR4_MEM00_cs_n(0) => DDR4_MEM00_cs_n(0),
DDR4_MEM00_dq(71 downto 0) => DDR4_MEM00_dq(71 downto 0),
DDR4_MEM00_dqs_c(17 downto 0) => DDR4_MEM00_dqs_c(17 downto 0),
DDR4_MEM00_dqs_t(17 downto 0) => DDR4_MEM00_dqs_t(17 downto 0),
DDR4_MEM00_odt(0) => DDR4_MEM00_odt(0),
DDR4_MEM00_par => DDR4_MEM00_par,
DDR4_MEM00_reset_n => DDR4_MEM00_reset_n,
DDR4_MEM01_DIFF_CLK_clk_n => DDR4_MEM01_DIFF_CLK_clk_n,
DDR4_MEM01_DIFF_CLK_clk_p => DDR4_MEM01_DIFF_CLK_clk_p,
DDR4_MEM01_act_n => DDR4_MEM01_act_n,
DDR4_MEM01_adr(16 downto 0) => DDR4_MEM01_adr(16 downto 0),
DDR4_MEM01_ba(1 downto 0) => DDR4_MEM01_ba(1 downto 0),
DDR4_MEM01_bg(1 downto 0) => DDR4_MEM01_bg(1 downto 0),
DDR4_MEM01_ck_c(0) => DDR4_MEM01_ck_c(0),
DDR4_MEM01_ck_t(0) => DDR4_MEM01_ck_t(0),
DDR4_MEM01_cke(0) => DDR4_MEM01_cke(0),
DDR4_MEM01_cs_n(0) => DDR4_MEM01_cs_n(0),
DDR4_MEM01_dq(71 downto 0) => DDR4_MEM01_dq(71 downto 0),
DDR4_MEM01_dqs_c(17 downto 0) => DDR4_MEM01_dqs_c(17 downto 0),
DDR4_MEM01_dqs_t(17 downto 0) => DDR4_MEM01_dqs_t(17 downto 0),
DDR4_MEM01_odt(0) => DDR4_MEM01_odt(0),
DDR4_MEM01_par => DDR4_MEM01_par,
DDR4_MEM01_reset_n => DDR4_MEM01_reset_n,
DDR4_MEM02_DIFF_CLK_clk_n => DDR4_MEM02_DIFF_CLK_clk_n,
DDR4_MEM02_DIFF_CLK_clk_p => DDR4_MEM02_DIFF_CLK_clk_p,
DDR4_MEM02_act_n => DDR4_MEM02_act_n,
DDR4_MEM02_adr(16 downto 0) => DDR4_MEM02_adr(16 downto 0),
DDR4_MEM02_ba(1 downto 0) => DDR4_MEM02_ba(1 downto 0),
DDR4_MEM02_bg(1 downto 0) => DDR4_MEM02_bg(1 downto 0),
DDR4_MEM02_ck_c(0) => DDR4_MEM02_ck_c(0),
DDR4_MEM02_ck_t(0) => DDR4_MEM02_ck_t(0),
DDR4_MEM02_cke(0) => DDR4_MEM02_cke(0),
DDR4_MEM02_cs_n(0) => DDR4_MEM02_cs_n(0),
DDR4_MEM02_dq(71 downto 0) => DDR4_MEM02_dq(71 downto 0),
DDR4_MEM02_dqs_c(17 downto 0) => DDR4_MEM02_dqs_c(17 downto 0),
DDR4_MEM02_dqs_t(17 downto 0) => DDR4_MEM02_dqs_t(17 downto 0),
DDR4_MEM02_odt(0) => DDR4_MEM02_odt(0),
DDR4_MEM02_par => DDR4_MEM02_par,
DDR4_MEM02_reset_n => DDR4_MEM02_reset_n,
M00_AXI_araddr(38 downto 0) => M00_AXI_araddr(38 downto 0),
M00_AXI_arburst(1 downto 0) => M00_AXI_arburst(1 downto 0),
M00_AXI_arcache(3 downto 0) => M00_AXI_arcache(3 downto 0),
M00_AXI_arlen(7 downto 0) => M00_AXI_arlen(7 downto 0),
M00_AXI_arlock(0) => M00_AXI_arlock(0),
M00_AXI_arprot(2 downto 0) => M00_AXI_arprot(2 downto 0),
M00_AXI_arqos(3 downto 0) => M00_AXI_arqos(3 downto 0),
M00_AXI_arready => M00_AXI_arready,
M00_AXI_arregion(3 downto 0) => M00_AXI_arregion(3 downto 0),
M00_AXI_arsize(2 downto 0) => M00_AXI_arsize(2 downto 0),
M00_AXI_arvalid => M00_AXI_arvalid,
M00_AXI_awaddr(38 downto 0) => M00_AXI_awaddr(38 downto 0),
M00_AXI_awburst(1 downto 0) => M00_AXI_awburst(1 downto 0),
M00_AXI_awcache(3 downto 0) => M00_AXI_awcache(3 downto 0),
M00_AXI_awlen(7 downto 0) => M00_AXI_awlen(7 downto 0),
M00_AXI_awlock(0) => M00_AXI_awlock(0),
M00_AXI_awprot(2 downto 0) => M00_AXI_awprot(2 downto 0),
M00_AXI_awqos(3 downto 0) => M00_AXI_awqos(3 downto 0),
M00_AXI_awready => M00_AXI_awready,
M00_AXI_awregion(3 downto 0) => M00_AXI_awregion(3 downto 0),
M00_AXI_awsize(2 downto 0) => M00_AXI_awsize(2 downto 0),
M00_AXI_awvalid => M00_AXI_awvalid,
M00_AXI_bready => M00_AXI_bready,
M00_AXI_bresp(1 downto 0) => M00_AXI_bresp(1 downto 0),
M00_AXI_bvalid => M00_AXI_bvalid,
M00_AXI_rdata(511 downto 0) => M00_AXI_rdata(511 downto 0),
M00_AXI_rlast => M00_AXI_rlast,
M00_AXI_rready => M00_AXI_rready,
M00_AXI_rresp(1 downto 0) => M00_AXI_rresp(1 downto 0),
M00_AXI_rvalid => M00_AXI_rvalid,
M00_AXI_wdata(511 downto 0) => M00_AXI_wdata(511 downto 0),
M00_AXI_wlast => M00_AXI_wlast,
M00_AXI_wready => M00_AXI_wready,
M00_AXI_wstrb(63 downto 0) => M00_AXI_wstrb(63 downto 0),
M00_AXI_wvalid => M00_AXI_wvalid,
S00_AXI_araddr(38 downto 0) => S00_AXI_araddr(38 downto 0),
S00_AXI_arburst(1 downto 0) => S00_AXI_arburst(1 downto 0),
S00_AXI_arcache(3 downto 0) => S00_AXI_arcache(3 downto 0),
S00_AXI_arid(3 downto 0) => S00_AXI_arid(3 downto 0),
S00_AXI_arlen(7 downto 0) => S00_AXI_arlen(7 downto 0),
S00_AXI_arlock(0) => S00_AXI_arlock(0),
S00_AXI_arprot(2 downto 0) => S00_AXI_arprot(2 downto 0),
S00_AXI_arqos(3 downto 0) => S00_AXI_arqos(3 downto 0),
S00_AXI_arready => S00_AXI_arready,
S00_AXI_arregion(3 downto 0) => S00_AXI_arregion(3 downto 0),
S00_AXI_arsize(2 downto 0) => S00_AXI_arsize(2 downto 0),
S00_AXI_arvalid => S00_AXI_arvalid,
S00_AXI_awaddr(38 downto 0) => S00_AXI_awaddr(38 downto 0),
S00_AXI_awburst(1 downto 0) => S00_AXI_awburst(1 downto 0),
S00_AXI_awcache(3 downto 0) => S00_AXI_awcache(3 downto 0),
S00_AXI_awid(3 downto 0) => S00_AXI_awid(3 downto 0),
S00_AXI_awlen(7 downto 0) => S00_AXI_awlen(7 downto 0),
S00_AXI_awlock(0) => S00_AXI_awlock(0),
S00_AXI_awprot(2 downto 0) => S00_AXI_awprot(2 downto 0),
S00_AXI_awqos(3 downto 0) => S00_AXI_awqos(3 downto 0),
S00_AXI_awready => S00_AXI_awready,
S00_AXI_awregion(3 downto 0) => S00_AXI_awregion(3 downto 0),
S00_AXI_awsize(2 downto 0) => S00_AXI_awsize(2 downto 0),
S00_AXI_awvalid => S00_AXI_awvalid,
S00_AXI_bid(3 downto 0) => S00_AXI_bid(3 downto 0),
S00_AXI_bready => S00_AXI_bready,
S00_AXI_bresp(1 downto 0) => S00_AXI_bresp(1 downto 0),
S00_AXI_bvalid => S00_AXI_bvalid,
S00_AXI_rdata(511 downto 0) => S00_AXI_rdata(511 downto 0),
S00_AXI_rid(3 downto 0) => S00_AXI_rid(3 downto 0),
S00_AXI_rlast => S00_AXI_rlast,
S00_AXI_rready => S00_AXI_rready,
S00_AXI_rresp(1 downto 0) => S00_AXI_rresp(1 downto 0),
S00_AXI_rvalid => S00_AXI_rvalid,
S00_AXI_wdata(511 downto 0) => S00_AXI_wdata(511 downto 0),
S00_AXI_wlast => S00_AXI_wlast,
S00_AXI_wready => S00_AXI_wready,
S00_AXI_wstrb(63 downto 0) => S00_AXI_wstrb(63 downto 0),
S00_AXI_wvalid => S00_AXI_wvalid,
S01_AXI_araddr(38 downto 0) => S01_AXI_araddr(38 downto 0),
S01_AXI_arburst(1 downto 0) => S01_AXI_arburst(1 downto 0),
S01_AXI_arcache(3 downto 0) => S01_AXI_arcache(3 downto 0),
S01_AXI_arid(3 downto 0) => S01_AXI_arid(3 downto 0),
S01_AXI_arlen(7 downto 0) => S01_AXI_arlen(7 downto 0),
S01_AXI_arlock(0) => S01_AXI_arlock(0),
S01_AXI_arprot(2 downto 0) => S01_AXI_arprot(2 downto 0),
S01_AXI_arqos(3 downto 0) => S01_AXI_arqos(3 downto 0),
S01_AXI_arready => S01_AXI_arready,
S01_AXI_arregion(3 downto 0) => S01_AXI_arregion(3 downto 0),
S01_AXI_arvalid => S01_AXI_arvalid,
S01_AXI_awaddr(38 downto 0) => S01_AXI_awaddr(38 downto 0),
S01_AXI_awburst(1 downto 0) => S01_AXI_awburst(1 downto 0),
S01_AXI_awcache(3 downto 0) => S01_AXI_awcache(3 downto 0),
S01_AXI_awid(3 downto 0) => S01_AXI_awid(3 downto 0),
S01_AXI_awlen(7 downto 0) => S01_AXI_awlen(7 downto 0),
S01_AXI_awlock(0) => S01_AXI_awlock(0),
S01_AXI_awprot(2 downto 0) => S01_AXI_awprot(2 downto 0),
S01_AXI_awqos(3 downto 0) => S01_AXI_awqos(3 downto 0),
S01_AXI_awready => S01_AXI_awready,
S01_AXI_awregion(3 downto 0) => S01_AXI_awregion(3 downto 0),
S01_AXI_awvalid => S01_AXI_awvalid,
S01_AXI_bid(3 downto 0) => S01_AXI_bid(3 downto 0),
S01_AXI_bready => S01_AXI_bready,
S01_AXI_bresp(1 downto 0) => S01_AXI_bresp(1 downto 0),
S01_AXI_bvalid => S01_AXI_bvalid,
S01_AXI_rdata(511 downto 0) => S01_AXI_rdata(511 downto 0),
S01_AXI_rid(3 downto 0) => S01_AXI_rid(3 downto 0),
S01_AXI_rlast => S01_AXI_rlast,
S01_AXI_rready => S01_AXI_rready,
S01_AXI_rresp(1 downto 0) => S01_AXI_rresp(1 downto 0),
S01_AXI_rvalid => S01_AXI_rvalid,
S01_AXI_wdata(511 downto 0) => S01_AXI_wdata(511 downto 0),
S01_AXI_wlast => S01_AXI_wlast,
S01_AXI_wready => S01_AXI_wready,
S01_AXI_wstrb(63 downto 0) => S01_AXI_wstrb(63 downto 0),
S01_AXI_wvalid => S01_AXI_wvalid,
S02_AXI_araddr(38 downto 0) => S02_AXI_araddr(38 downto 0),
S02_AXI_arburst(1 downto 0) => S02_AXI_arburst(1 downto 0),
S02_AXI_arcache(3 downto 0) => S02_AXI_arcache(3 downto 0),
S02_AXI_arid(3 downto 0) => S02_AXI_arid(3 downto 0),
S02_AXI_arlen(7 downto 0) => S02_AXI_arlen(7 downto 0),
S02_AXI_arlock(0) => S02_AXI_arlock(0),
S02_AXI_arprot(2 downto 0) => S02_AXI_arprot(2 downto 0),
S02_AXI_arqos(3 downto 0) => S02_AXI_arqos(3 downto 0),
S02_AXI_arready => S02_AXI_arready,
S02_AXI_arregion(3 downto 0) => S02_AXI_arregion(3 downto 0),
S02_AXI_arvalid => S02_AXI_arvalid,
S02_AXI_awaddr(38 downto 0) => S02_AXI_awaddr(38 downto 0),
S02_AXI_awburst(1 downto 0) => S02_AXI_awburst(1 downto 0),
S02_AXI_awcache(3 downto 0) => S02_AXI_awcache(3 downto 0),
S02_AXI_awid(3 downto 0) => S02_AXI_awid(3 downto 0),
S02_AXI_awlen(7 downto 0) => S02_AXI_awlen(7 downto 0),
S02_AXI_awlock(0) => S02_AXI_awlock(0),
S02_AXI_awprot(2 downto 0) => S02_AXI_awprot(2 downto 0),
S02_AXI_awqos(3 downto 0) => S02_AXI_awqos(3 downto 0),
S02_AXI_awready => S02_AXI_awready,
S02_AXI_awregion(3 downto 0) => S02_AXI_awregion(3 downto 0),
S02_AXI_awvalid => S02_AXI_awvalid,
S02_AXI_bid(3 downto 0) => S02_AXI_bid(3 downto 0),
S02_AXI_bready => S02_AXI_bready,
S02_AXI_bresp(1 downto 0) => S02_AXI_bresp(1 downto 0),
S02_AXI_bvalid => S02_AXI_bvalid,
S02_AXI_rdata(511 downto 0) => S02_AXI_rdata(511 downto 0),
S02_AXI_rid(3 downto 0) => S02_AXI_rid(3 downto 0),
S02_AXI_rlast => S02_AXI_rlast,
S02_AXI_rready => S02_AXI_rready,
S02_AXI_rresp(1 downto 0) => S02_AXI_rresp(1 downto 0),
S02_AXI_rvalid => S02_AXI_rvalid,
S02_AXI_wdata(511 downto 0) => S02_AXI_wdata(511 downto 0),
S02_AXI_wlast => S02_AXI_wlast,
S02_AXI_wready => S02_AXI_wready,
S02_AXI_wstrb(63 downto 0) => S02_AXI_wstrb(63 downto 0),
S02_AXI_wvalid => S02_AXI_wvalid,
S03_AXI_araddr(38 downto 0) => S03_AXI_araddr(38 downto 0),
S03_AXI_arburst(1 downto 0) => S03_AXI_arburst(1 downto 0),
S03_AXI_arcache(3 downto 0) => S03_AXI_arcache(3 downto 0),
S03_AXI_arid(3 downto 0) => S03_AXI_arid(3 downto 0),
S03_AXI_arlen(7 downto 0) => S03_AXI_arlen(7 downto 0),
S03_AXI_arlock(0) => S03_AXI_arlock(0),
S03_AXI_arprot(2 downto 0) => S03_AXI_arprot(2 downto 0),
S03_AXI_arqos(3 downto 0) => S03_AXI_arqos(3 downto 0),
S03_AXI_arready => S03_AXI_arready,
S03_AXI_arregion(3 downto 0) => S03_AXI_arregion(3 downto 0),
S03_AXI_arsize(2 downto 0) => S03_AXI_arsize(2 downto 0),
S03_AXI_arvalid => S03_AXI_arvalid,
S03_AXI_awaddr(38 downto 0) => S03_AXI_awaddr(38 downto 0),
S03_AXI_awburst(1 downto 0) => S03_AXI_awburst(1 downto 0),
S03_AXI_awcache(3 downto 0) => S03_AXI_awcache(3 downto 0),
S03_AXI_awid(3 downto 0) => S03_AXI_awid(3 downto 0),
S03_AXI_awlen(7 downto 0) => S03_AXI_awlen(7 downto 0),
S03_AXI_awlock(0) => S03_AXI_awlock(0),
S03_AXI_awprot(2 downto 0) => S03_AXI_awprot(2 downto 0),
S03_AXI_awqos(3 downto 0) => S03_AXI_awqos(3 downto 0),
S03_AXI_awready => S03_AXI_awready,
S03_AXI_awregion(3 downto 0) => S03_AXI_awregion(3 downto 0),
S03_AXI_awsize(2 downto 0) => S03_AXI_awsize(2 downto 0),
S03_AXI_awvalid => S03_AXI_awvalid,
S03_AXI_bid(3 downto 0) => S03_AXI_bid(3 downto 0),
S03_AXI_bready => S03_AXI_bready,
S03_AXI_bresp(1 downto 0) => S03_AXI_bresp(1 downto 0),
S03_AXI_bvalid => S03_AXI_bvalid,
S03_AXI_rdata(511 downto 0) => S03_AXI_rdata(511 downto 0),
S03_AXI_rid(3 downto 0) => S03_AXI_rid(3 downto 0),
S03_AXI_rlast => S03_AXI_rlast,
S03_AXI_rready => S03_AXI_rready,
S03_AXI_rresp(1 downto 0) => S03_AXI_rresp(1 downto 0),
S03_AXI_rvalid => S03_AXI_rvalid,
S03_AXI_wdata(511 downto 0) => S03_AXI_wdata(511 downto 0),
S03_AXI_wlast => S03_AXI_wlast,
S03_AXI_wready => S03_AXI_wready,
S03_AXI_wstrb(63 downto 0) => S03_AXI_wstrb(63 downto 0),
S03_AXI_wvalid => S03_AXI_wvalid,
S04_AXI_araddr(38 downto 0) => S04_AXI_araddr(38 downto 0),
S04_AXI_arcache(3 downto 0) => S04_AXI_arcache(3 downto 0),
S04_AXI_arlen(7 downto 0) => S04_AXI_arlen(7 downto 0),
S04_AXI_arlock(0) => S04_AXI_arlock(0),
S04_AXI_arprot(2 downto 0) => S04_AXI_arprot(2 downto 0),
S04_AXI_arqos(3 downto 0) => S04_AXI_arqos(3 downto 0),
S04_AXI_arready => S04_AXI_arready,
S04_AXI_arregion(3 downto 0) => S04_AXI_arregion(3 downto 0),
S04_AXI_arvalid => S04_AXI_arvalid,
S04_AXI_awaddr(38 downto 0) => S04_AXI_awaddr(38 downto 0),
S04_AXI_awcache(3 downto 0) => S04_AXI_awcache(3 downto 0),
S04_AXI_awlen(7 downto 0) => S04_AXI_awlen(7 downto 0),
S04_AXI_awlock(0) => S04_AXI_awlock(0),
S04_AXI_awprot(2 downto 0) => S04_AXI_awprot(2 downto 0),
S04_AXI_awqos(3 downto 0) => S04_AXI_awqos(3 downto 0),
S04_AXI_awready => S04_AXI_awready,
S04_AXI_awregion(3 downto 0) => S04_AXI_awregion(3 downto 0),
S04_AXI_awvalid => S04_AXI_awvalid,
S04_AXI_bready => S04_AXI_bready,
S04_AXI_bresp(1 downto 0) => S04_AXI_bresp(1 downto 0),
S04_AXI_bvalid => S04_AXI_bvalid,
S04_AXI_rdata(511 downto 0) => S04_AXI_rdata(511 downto 0),
S04_AXI_rlast => S04_AXI_rlast,
S04_AXI_rready => S04_AXI_rready,
S04_AXI_rresp(1 downto 0) => S04_AXI_rresp(1 downto 0),
S04_AXI_rvalid => S04_AXI_rvalid,
S04_AXI_wdata(511 downto 0) => S04_AXI_wdata(511 downto 0),
S04_AXI_wlast => S04_AXI_wlast,
S04_AXI_wready => S04_AXI_wready,
S04_AXI_wstrb(63 downto 0) => S04_AXI_wstrb(63 downto 0),
S04_AXI_wvalid => S04_AXI_wvalid,
S05_AXI_araddr(38 downto 0) => S05_AXI_araddr(38 downto 0),
S05_AXI_arcache(3 downto 0) => S05_AXI_arcache(3 downto 0),
S05_AXI_arlen(7 downto 0) => S05_AXI_arlen(7 downto 0),
S05_AXI_arlock(0) => S05_AXI_arlock(0),
S05_AXI_arprot(2 downto 0) => S05_AXI_arprot(2 downto 0),
S05_AXI_arqos(3 downto 0) => S05_AXI_arqos(3 downto 0),
S05_AXI_arready => S05_AXI_arready,
S05_AXI_arregion(3 downto 0) => S05_AXI_arregion(3 downto 0),
S05_AXI_arvalid => S05_AXI_arvalid,
S05_AXI_awaddr(38 downto 0) => S05_AXI_awaddr(38 downto 0),
S05_AXI_awcache(3 downto 0) => S05_AXI_awcache(3 downto 0),
S05_AXI_awlen(7 downto 0) => S05_AXI_awlen(7 downto 0),
S05_AXI_awlock(0) => S05_AXI_awlock(0),
S05_AXI_awprot(2 downto 0) => S05_AXI_awprot(2 downto 0),
S05_AXI_awqos(3 downto 0) => S05_AXI_awqos(3 downto 0),
S05_AXI_awready => S05_AXI_awready,
S05_AXI_awregion(3 downto 0) => S05_AXI_awregion(3 downto 0),
S05_AXI_awvalid => S05_AXI_awvalid,
S05_AXI_bready => S05_AXI_bready,
S05_AXI_bresp(1 downto 0) => S05_AXI_bresp(1 downto 0),
S05_AXI_bvalid => S05_AXI_bvalid,
S05_AXI_rdata(511 downto 0) => S05_AXI_rdata(511 downto 0),
S05_AXI_rlast => S05_AXI_rlast,
S05_AXI_rready => S05_AXI_rready,
S05_AXI_rresp(1 downto 0) => S05_AXI_rresp(1 downto 0),
S05_AXI_rvalid => S05_AXI_rvalid,
S05_AXI_wdata(511 downto 0) => S05_AXI_wdata(511 downto 0),
S05_AXI_wlast => S05_AXI_wlast,
S05_AXI_wready => S05_AXI_wready,
S05_AXI_wstrb(63 downto 0) => S05_AXI_wstrb(63 downto 0),
S05_AXI_wvalid => S05_AXI_wvalid,
S_AXI_CTRL_araddr(24 downto 0) => S_AXI_CTRL_araddr(24 downto 0),
S_AXI_CTRL_arprot(2 downto 0) => S_AXI_CTRL_arprot(2 downto 0),
S_AXI_CTRL_arready => S_AXI_CTRL_arready,
S_AXI_CTRL_arvalid => S_AXI_CTRL_arvalid,
S_AXI_CTRL_awaddr(24 downto 0) => S_AXI_CTRL_awaddr(24 downto 0),
S_AXI_CTRL_awprot(2 downto 0) => S_AXI_CTRL_awprot(2 downto 0),
S_AXI_CTRL_awready => S_AXI_CTRL_awready,
S_AXI_CTRL_awvalid => S_AXI_CTRL_awvalid,
S_AXI_CTRL_bready => S_AXI_CTRL_bready,
S_AXI_CTRL_bresp(1 downto 0) => S_AXI_CTRL_bresp(1 downto 0),
S_AXI_CTRL_bvalid => S_AXI_CTRL_bvalid,
S_AXI_CTRL_rdata(31 downto 0) => S_AXI_CTRL_rdata(31 downto 0),
S_AXI_CTRL_rready => S_AXI_CTRL_rready,
S_AXI_CTRL_rresp(1 downto 0) => S_AXI_CTRL_rresp(1 downto 0),
S_AXI_CTRL_rvalid => S_AXI_CTRL_rvalid,
S_AXI_CTRL_wdata(31 downto 0) => S_AXI_CTRL_wdata(31 downto 0),
S_AXI_CTRL_wready => S_AXI_CTRL_wready,
S_AXI_CTRL_wstrb(3 downto 0) => S_AXI_CTRL_wstrb(3 downto 0),
S_AXI_CTRL_wvalid => S_AXI_CTRL_wvalid,
aclk => aclk,
aclk1 => aclk1,
aclk2 => aclk2,
aresetn => aresetn,
ddr4_mem00_sys_rst => ddr4_mem00_sys_rst,
ddr4_mem00_ui_clk => ddr4_mem00_ui_clk,
ddr4_mem01_sys_rst => ddr4_mem01_sys_rst,
ddr4_mem01_ui_clk => ddr4_mem01_ui_clk,
ddr4_mem02_sys_rst => ddr4_mem02_sys_rst,
ddr4_mem02_ui_clk => ddr4_mem02_ui_clk,
ddr4_mem_calib_complete => ddr4_mem_calib_complete,
ddr4_mem_calib_vec(2 downto 0) => ddr4_mem_calib_vec(2 downto 0)
);
end STRUCTURE;
|
-- -------------------------------------------------------------
--
-- File Name: C:\Flat Earth\fpga-open-speech-tools\simulink_models\models\pFIR_Testing\hdlsrc\pFIR_Testing\pFIR_Testing_Channel_Data_Multiplexer.vhd
--
-- Generated by MATLAB 9.7 and HDL Coder 3.15
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: pFIR_Testing_Channel_Data_Multiplexer
-- Source Path: pFIR_Testing/dataplane/Test FIR with Custom FIR Libraries Sample Based Filtering/Channel_Data_Multiplexer
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY pFIR_Testing_Channel_Data_Multiplexer IS
PORT( dataPrev : IN std_logic_vector(31 DOWNTO 0); -- sfix32_En28
leftData : IN std_logic_vector(31 DOWNTO 0); -- sfix32_En28
leftValid : IN std_logic;
rightData : IN std_logic_vector(31 DOWNTO 0); -- sfix32_En28
rightValid : IN std_logic;
chanPrev : IN std_logic_vector(1 DOWNTO 0); -- ufix2
sourceData : OUT std_logic_vector(31 DOWNTO 0); -- sfix32_En28
sourceChannel : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
sourceValid : OUT std_logic -- ufix1
);
END pFIR_Testing_Channel_Data_Multiplexer;
ARCHITECTURE rtl OF pFIR_Testing_Channel_Data_Multiplexer IS
ATTRIBUTE multstyle : string;
-- Signals
SIGNAL dataPrev_signed : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL leftData_signed : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL rightData_signed : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL chanPrev_unsigned : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL sourceData_tmp : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL sourceChannel_tmp : unsigned(1 DOWNTO 0); -- ufix2
BEGIN
dataPrev_signed <= signed(dataPrev);
leftData_signed <= signed(leftData);
rightData_signed <= signed(rightData);
chanPrev_unsigned <= unsigned(chanPrev);
Channel_Data_Multiplexer_output : PROCESS (chanPrev_unsigned, dataPrev_signed, leftData_signed, leftValid,
rightData_signed, rightValid)
BEGIN
--MATLAB Function 'dataplane/Test FIR with Custom FIR Libraries Sample Based Filtering/Channel_Data_Multiplexer': '<S9>:1'
IF leftValid = '1' THEN
--'<S9>:1:3'
-- left channel ready
--'<S9>:1:4'
sourceData_tmp <= leftData_signed;
--'<S9>:1:5'
sourceChannel_tmp <= to_unsigned(16#0#, 2);
--'<S9>:1:6'
sourceValid <= '1';
ELSIF rightValid = '1' THEN
--'<S9>:1:7'
-- right channel ready
--'<S9>:1:8'
sourceData_tmp <= rightData_signed;
--'<S9>:1:9'
sourceChannel_tmp <= to_unsigned(16#1#, 2);
--'<S9>:1:10'
sourceValid <= '1';
ELSE
-- neither channel output is ready
--'<S9>:1:12'
sourceData_tmp <= dataPrev_signed;
--'<S9>:1:13'
sourceChannel_tmp <= chanPrev_unsigned;
--'<S9>:1:14'
sourceValid <= '0';
END IF;
END PROCESS Channel_Data_Multiplexer_output;
sourceData <= std_logic_vector(sourceData_tmp);
sourceChannel <= std_logic_vector(sourceChannel_tmp);
END rtl;
|
<filename>src/xilinx/AtomFpga_OlimexModVGA.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2009 <NAME>. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : AtomFpga_OlimexModVGA.vhd
-- /___/ /\ Timestamp : 02/03/2013 06:17:50
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomFpga_OlimexModVGA
--Device: spartan3A
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity AtomFpga_OlimexModVGA is
port (clk_25M00 : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ERSTn : in std_logic;
red : out std_logic_vector (2 downto 0);
green : out std_logic_vector (2 downto 0);
blue : out std_logic_vector (2 downto 0);
vsync : out std_logic;
hsync : out std_logic;
CE1 : out std_logic;
RAMWRn : out std_logic;
RAMOEn : out std_logic;
RamA : out std_logic_vector (15 downto 0);
RamD : inout std_logic_vector (15 downto 0);
audiol : out std_logic;
audioR : out std_logic;
FLASH_CS : out std_logic; -- Active low FLASH chip select
FLASH_SI : out std_logic; -- Serial output to FLASH chip SI pin
FLASH_CK : out std_logic; -- FLASH clock
FLASH_SO : in std_logic; -- Serial input from FLASH chip SO
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic);
end AtomFpga_OlimexModVGA;
architecture behavioral of AtomFpga_OlimexModVGA is
signal clock_16 : std_logic;
signal clock_25 : std_logic;
signal clock_32 : std_logic;
signal Phi2 : std_logic;
signal powerup_reset_n : std_logic;
signal hard_reset_n : std_logic;
signal reset_counter : std_logic_vector(15 downto 0);
signal RAM_A : std_logic_vector(18 downto 0);
signal RAM_Din : std_logic_vector(7 downto 0);
signal RAM_Dout : std_logic_vector(7 downto 0);
signal RAM_nWE : std_logic;
signal RAM_nOE : std_logic;
signal RAM_nCS : std_logic;
signal ExternCE : std_logic;
signal ExternWE : std_logic;
signal ExternA : std_logic_vector(18 downto 0);
signal ExternDin : std_logic_vector(7 downto 0);
signal ExternDout : std_logic_vector(7 downto 0);
-----------------------------------------------
-- Bootstrap ROM Image from SPI FLASH into SRAM
-----------------------------------------------
-- TODO: The user_ values below are a hack
-- specifying 030000/008000 did not work, although it should!
-- there seems to be something different about the way the AT45DB041D is addressed
-- but that's not obvious in the data sheet
-- https://www.adestotech.com/wp-content/uploads/doc3595.pdf
-- start address of user data in FLASH as obtained from bitmerge.py
constant user_address : std_logic_vector(23 downto 0) := x"000000";
-- lenth of user data in FLASH = 32KB (8x 4KB ROM) images
constant user_length : std_logic_vector(23 downto 0) := x"038000";
-- high when FLASH is being copied to SRAM, can be used by user as active high reset
signal bootstrap_busy : std_logic;
begin
inst_dcm2 : entity work.dcm2 port map(
CLKIN_IN => clk_25M00,
CLK0_OUT => clock_25,
CLKFX_OUT => clock_16);
inst_dcm3 : entity work.dcm3 port map (
CLKIN_IN => clock_16,
CLK0_OUT => clock_32,
CLK0_OUT1 => open,
CLK2X_OUT => open);
inst_AtomFpga_Core : entity work.AtomFpga_Core
generic map (
CImplSDDOS => true,
CImplAtoMMC2 => false,
CImplGraphicsExt => false,
CImplSoftChar => false,
CImplSID => true,
CImplVGA80x40 => false,
CImplHWScrolling => false,
CImplMouse => false,
CImplUart => false,
CImplDoubleVideo => false,
CImplRamRomNone => true,
CImplRamRomPhill => false,
CImplRamRomAtom2015 => false,
CImplRamRomSchakelKaart => false,
MainClockSpeed => 16000000,
DefaultBaud => 115200
)
port map(
clk_vga => clock_25,
clk_16M00 => clock_16,
clk_32M00 => clock_32,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
ps2_mouse_clk => open,
ps2_mouse_data => open,
ERSTn => hard_reset_n,
IRSTn => open,
red => red,
green => green,
blue => blue,
vsync => vsync,
hsync => hsync,
Phi2 => Phi2,
ExternCE => ExternCE,
ExternWE => ExternWE,
ExternA => ExternA,
ExternDin => ExternDin,
ExternDout => ExternDout,
sid_audio => audiol,
sid_audio_d => open,
atom_audio => audioR,
SDMISO => SDMISO,
SDSS => SDSS,
SDCLK => SDCLK,
SDMOSI => SDMOSI,
uart_RxD => '1',
uart_TxD => open,
avr_RxD => '1',
avr_TxD => open,
LED1 => open,
LED2 => open,
charSet => '0'
);
--------------------------------------------------------
-- Power Up Reset Generation
--------------------------------------------------------
-- On the Duo the external reset signal is not asserted on power up
-- This internal counter forces power up reset to happen
-- This is needed by the GODIL to initialize some of the registers
ResetProcess : process (clock_16)
begin
if rising_edge(clock_16) then
if (reset_counter(reset_counter'high) = '0') then
reset_counter <= reset_counter + 1;
end if;
powerup_reset_n <= ERSTn and reset_counter(reset_counter'high);
end if;
end process;
-- extend the version seen by the core to hold the 6502 reset during bootstrap
hard_reset_n <= powerup_reset_n and not bootstrap_busy;
--------------------------------------------------------
-- BOOTSTRAP SPI FLASH to SRAM
--------------------------------------------------------
inst_bootstrap: entity work.bootstrap
generic map (
gated_write => false,
user_length => user_length
)
port map(
clock => clock_16,
powerup_reset_n => powerup_reset_n,
bootstrap_busy => bootstrap_busy,
user_address => user_address,
RAM_nOE => RAM_nOE,
RAM_nWE => RAM_nWE,
RAM_nCS => RAM_nCS,
RAM_A => RAM_A,
RAM_Din => RAM_Din,
RAM_Dout => RAM_Dout,
SRAM_nOE => RamOEn,
SRAM_nWE => RamWRn,
SRAM_nCS => CE1,
SRAM_A(20 downto 16) => open,
SRAM_A(15 downto 0) => RamA,
SRAM_D => RamD(7 downto 0),
FLASH_CS => FLASH_CS,
FLASH_SI => FLASH_SI,
FLASH_CK => FLASH_CK,
FLASH_SO => FLASH_SO
);
RamD(15 downto 8) <= (others => 'Z');
MemProcess : process (clock_16)
begin
if rising_edge(clock_16) then
RAM_A <= ExternA xor ("000" & x"8000");
RAM_nCS <= not ExternCE;
RAM_nOE <= not ((not ExternWE) and ExternCE);
RAM_nWE <= not (ExternWE and ExternCE and phi2);
RAM_Din <= ExternDin;
end if;
end process;
ExternDout <= RAM_Dout;
end behavioral;
|
<reponame>ponymalt3/sl_processor
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sl_structs_p is
subtype reg_pc_t is unsigned(15 downto 0);
subtype reg_raw_t is std_ulogic_vector(31 downto 0);
subtype reg_addr_t is unsigned(31 downto 0);
type reg_addr_array_t is array (natural range <>) of reg_addr_t;
type reg_raw_array_t is array (natural range <>) of reg_raw_t;
type req_qfp_t is record
sign : std_ulogic;
exp : unsigned(1 downto 0);
mant : std_ulogic_vector(28 downto 0);
end record req_qfp_t;
constant CMD_MOV : std_ulogic_vector(3 downto 0) := "0000";
constant CMD_CMP : std_ulogic_vector(3 downto 0) := "0001";
constant CMD_ADD : std_ulogic_vector(3 downto 0) := "0010";
constant CMD_SUB : std_ulogic_vector(3 downto 0) := "0011";
constant CMD_MUL : std_ulogic_vector(3 downto 0) := "0100";
constant CMD_DIV : std_ulogic_vector(3 downto 0) := "0101";
constant CMD_LOG2 : std_ulogic_vector(3 downto 0) := "1000";
constant CMD_SHFT : std_ulogic_vector(3 downto 0) := "1001";
constant CMD_INVALID : std_ulogic_vector(3 downto 0) := "1111";
constant CMP_EQ : std_ulogic_vector(1 downto 0) := "00";
constant CMP_NEQ : std_ulogic_vector(1 downto 0) := "01";
constant CMP_LT : std_ulogic_vector(1 downto 0) := "10";
constant CMP_LE : std_ulogic_vector(1 downto 0) := "11";
constant MUX1_RESULT : std_ulogic := '0';
constant MUX1_MEM : std_ulogic := '1';
constant MUX2_MEM : std_ulogic := '0';
constant MUX2_IRS : std_ulogic := '1';
constant WBREG_AD0 : std_ulogic_vector(1 downto 0) := "00";
constant WBREG_AD1 : std_ulogic_vector(1 downto 0) := "01";
constant WBREG_IRS : std_ulogic_vector(1 downto 0) := "10";
constant WBREG_NONE : std_ulogic_vector(1 downto 0) := "11";
type sl_mem1_t is record
external_data : reg_raw_t;
end record sl_mem1_t;
type sl_mem2_t is record
read_data : reg_raw_array_t(1 downto 0);
wr_addr : reg_addr_t;
end record sl_mem2_t;
type sl_code_fetch_t is record
data : std_ulogic_vector(15 downto 0);
pc : reg_pc_t;
valid : std_ulogic;
end record sl_code_fetch_t;
type sl_decode_t is record
mux_ad0 : std_ulogic;
mux_ad1 : std_ulogic;
mux_a : std_ulogic; -- shortcut RESULT
mux_b : std_ulogic; -- select LOOP for MEM only
en_mem : std_ulogic;
en_irs : std_ulogic;
en_reg : std_ulogic;
cmd : std_ulogic_vector(3 downto 0);
wb_reg : std_ulogic_vector(1 downto 0);
c_data : std_ulogic_vector(9 downto 0);
c_data_ext : std_ulogic_vector(1 downto 0);
en_ad0 : std_ulogic;
en_ad1 : std_ulogic;
valid : std_ulogic;
goto : std_ulogic;
goto_const : std_ulogic;
load : std_ulogic;
cmp : std_ulogic;
neg : std_ulogic;
trunc : std_ulogic;
wait1 : std_ulogic;
signal1 : std_ulogic;
loop1 : std_ulogic;
cmp_mode : std_ulogic_vector(1 downto 0);
cmp_noX_cy : std_ulogic;
irs_addr : unsigned(15 downto 0);
mem_ex : std_ulogic;
cur_pc : reg_pc_t;
jmp_back : std_ulogic;
jmp_target_pc : reg_pc_t;
inc_ad0 : std_ulogic;
inc_ad1 : std_ulogic;
end record sl_decode_t;
type sl_decode_ex_t is record
cmd : std_ulogic_vector(3 downto 0);
memX : reg_raw_t;
mux0 : std_ulogic;
wr_addr : reg_addr_t;
wr_en : std_ulogic;
wr_ext : std_ulogic;
wb_en : std_ulogic;
wb_reg : std_ulogic_vector(1 downto 0);
cmp : std_ulogic;
cmp_mode : std_ulogic_vector(1 downto 0);
goto : std_ulogic;
neg : std_ulogic;
trunc : std_ulogic;
load : std_ulogic;
load_data : std_ulogic_vector(11 downto 0);
stall : std_ulogic;
end record sl_decode_ex_t;
constant S_FETCH : natural := 2;
constant S_DEC : natural := 1;
constant S_DECEX : natural := 1;
constant S_EXEC : natural := 0;
type sl_state_t is record
pc : reg_pc_t;
addr : reg_addr_array_t(1 downto 0);
irs : reg_addr_t;
load_state : std_ulogic_vector(2 downto 0);
enable : std_ulogic_vector(2 downto 0);
stall_exec_1d : std_ulogic;
loop_count : reg_raw_t;
result : reg_raw_t;
result_prefetch : std_ulogic; -- fetch result data when ready and set this flag (also used for const loading)
inc_ad0 : std_ulogic;
inc_ad1 : std_ulogic;
exec_next : std_ulogic;
end record sl_state_t;
type sl_alu_t is record
result : reg_raw_t;
int_result : reg_raw_t;
complete : std_ulogic;
same_unit_ready : std_ulogic;
idle : std_ulogic;
cmp_lt : std_ulogic;
cmp_eq : std_ulogic;
end record sl_alu_t;
type sl_exec_t is record
result : reg_raw_t;
complete : std_ulogic;
int_result : reg_raw_t;
exec_next : std_ulogic;
stall : std_ulogic;
flush : std_ulogic;
end record sl_exec_t;
type sl_stall_ctrl_t is record
stall_decex : std_ulogic;
stall_exec : std_ulogic;
flush_pipeline : std_ulogic;
enable : std_ulogic_vector(2 downto 0);
end record sl_stall_ctrl_t;
type sl_processor_t is record
state : sl_state_t;
fetch : sl_code_fetch_t;
dec : sl_decode_t;
decex : sl_decode_ex_t;
end record sl_processor_t;
end package sl_structs_p;
|
----------------------------------------------------------------------------------
-- COMPANY: Ruhr University Bochum, Embedded Security
-- AUTHOR: https://eprint.iacr.org/2018/203
----------------------------------------------------------------------------------
-- Copyright (c) 2019, <NAME>, <NAME>
-- All rights reserved.
-- BSD-3-Clause License
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of the copyright holder, their organization nor the
-- names of its contributors may be used to endorse or promote products
-- derived from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTERS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.functions.all;
entity Red_KeyPermutation is
Generic (
LFTable : STD_LOGIC_VECTOR(63 downto 0);
LFInvTable : STD_LOGIC_VECTOR(63 downto 0));
port(
data_in : in std_logic_vector(127 downto 0);
Red_FSM : in std_logic_vector(7 downto 0);
Red_RoundKey : out std_logic_vector(63 downto 0);
data_out : out std_logic_vector(127 downto 0));
end entity Red_KeyPermutation;
architecture behavioral of Red_KeyPermutation is
signal Input4 : STD_LOGIC_VECTOR(7 downto 0);
signal Input3 : STD_LOGIC_VECTOR(7 downto 0);
signal Input2 : STD_LOGIC_VECTOR(7 downto 0);
signal Input1 : STD_LOGIC_VECTOR(11 downto 0);
signal Input0 : STD_LOGIC_VECTOR(11 downto 0);
signal PermIn3 : STD_LOGIC_VECTOR(7 downto 0);
signal PermIn2 : STD_LOGIC_VECTOR(7 downto 0);
signal PermIn1 : STD_LOGIC_VECTOR(7 downto 0);
signal PermIn0 : STD_LOGIC_VECTOR(7 downto 0);
begin
Input4 <= data_in(31 downto 28) & data_in(15 downto 12);
Input3 <= data_in(27 downto 24) & data_in(11 downto 8);
Input2 <= data_in(23 downto 20) & data_in(7 downto 4);
Input1 <= Red_FSM(7 downto 4) & data_in(23 downto 20) & data_in(7 downto 4);
Input0 <= Red_FSM(3 downto 0) & data_in(19 downto 16) & data_in(3 downto 0);
GENRoundKey :
FOR i IN 0 TO 3 GENERATE
Red_KeyInst15: ENTITY work.Red_RoundKey2
Generic Map (i, LFTable, LFInvTable, 3, "10")
Port Map ( input4, Red_RoundKey(60+i));
Red_KeyInst14: ENTITY work.Red_RoundKey2
Generic Map (i, LFTable, LFInvTable, 2, "00")
Port Map ( input4, Red_RoundKey(56+i));
Red_KeyInst13: ENTITY work.Red_RoundKey2
Generic Map (i, LFTable, LFInvTable, 1, "00")
Port Map ( input4, Red_RoundKey(52+i));
Red_KeyInst12: ENTITY work.Red_RoundKey2
Generic Map (i, LFTable, LFInvTable, 0, "00")
Port Map ( input4, Red_RoundKey(48+i));
-----
Red_KeyInst11: ENTITY work.Red_RoundKey2
Generic Map (i, LFTable, LFInvTable, 3, "00")
Port Map ( input3, Red_RoundKey(44+i));
Red_KeyInst10: ENTITY work.Red_RoundKey2
Generic Map (i, LFTable, LFInvTable, 2, "00")
Port Map ( input3, Red_RoundKey(40+i));
Red_KeyInst9: ENTITY work.Red_RoundKey2
Generic Map (i, LFTable, LFInvTable, 1, "00")
Port Map ( input3, Red_RoundKey(36+i));
Red_KeyInst8: ENTITY work.Red_RoundKey2
Generic Map (i, LFTable, LFInvTable, 0, "00")
Port Map ( input3, Red_RoundKey(32+i));
-----
Red_KeyInst7: ENTITY work.Red_RoundKey2
Generic Map (i, LFTable, LFInvTable, 3, "00")
Port Map ( input2, Red_RoundKey(28+i));
Red_KeyInst6: ENTITY work.Red_RoundKey2
Generic Map (i, LFTable, LFInvTable, 2, "00")
Port Map ( input2, Red_RoundKey(24+i));
Red_KeyInst5: ENTITY work.Red_RoundKey3
Generic Map (i, LFTable, LFInvTable, 1, '0')
Port Map ( input1, Red_RoundKey(20+i));
Red_KeyInst4: ENTITY work.Red_RoundKey3
Generic Map (i, LFTable, LFInvTable, 0, '0')
Port Map ( input1, Red_RoundKey(16+i));
-----
Red_KeyInst3: ENTITY work.Red_RoundKey3
Generic Map (i, LFTable, LFInvTable, 3, '0')
Port Map ( input0, Red_RoundKey(12+i));
Red_KeyInst2: ENTITY work.Red_RoundKey3
Generic Map (i, LFTable, LFInvTable, 2, '0')
Port Map ( input0, Red_RoundKey(8+i));
Red_KeyInst1: ENTITY work.Red_RoundKey3
Generic Map (i, LFTable, LFInvTable, 1, '0')
Port Map ( input0, Red_RoundKey(4+i));
Red_KeyInst0: ENTITY work.Red_RoundKey3
Generic Map (i, LFTable, LFInvTable, 0, '0')
Port Map ( input0, Red_RoundKey(0+i));
END GENERATE;
-----
PermIn0 <= data_in(23 downto 16);
PermIn1 <= data_in(27 downto 20);
PermIn2 <= data_in(31 downto 24);
PermIn3 <= data_in(19 downto 16) & data_in(31 downto 28);
GENPerm :
FOR i IN 0 TO 3 GENERATE
PermInst0: ENTITY work.LookUp
Generic Map (size => 8, Table => MakePermKeyRedTable(i, LFTable, LFInvTable))
Port Map ( PermIn0, data_out(112+i));
PermInst1: ENTITY work.LookUp
Generic Map (size => 8, Table => MakePermKeyRedTable(i, LFTable, LFInvTable))
Port Map ( PermIn1, data_out(116+i));
PermInst2: ENTITY work.LookUp
Generic Map (size => 8, Table => MakePermKeyRedTable(i, LFTable, LFInvTable))
Port Map ( PermIn2, data_out(120+i));
PermInst3: ENTITY work.LookUp
Generic Map (size => 8, Table => MakePermKeyRedTable(i, LFTable, LFInvTable))
Port Map ( PermIn3, data_out(124+i));
END GENERATE;
data_out(111 downto 0) <= data_in(11 downto 0) & data_in(15 downto 12) & data_in(127 downto 32);
end architecture behavioral;
|
--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: code_4_b.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- <Description here>
--
-- Targeted device: <Family::ProASIC3L> <Die::A3P600L> <Package::484 FBGA>
-- Author: <Name>
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity code_4_b is
port (
--<port_name> : <direction> <type>;
DI1,DI2,DI3,DI4,DI94,DI98 : IN std_logic; -- example
DO8 : OUT std_logic -- example
--<other_ports>;
);
end code_4_b;
architecture architecture_code_4_b of code_4_b is
-- signal, component etc. declarations
signal INTERMED1,INTERMED2,INTERMED3,INTERMED4,INTERMED5 : std_logic; -- example
CONSTANT EN_C : STD_LOGIC := '1';
begin
INTERMED1 <= DI1 AND DI2 AND (DI3 OR DI4) ;
INTERMED2 <= (DI1 OR DI2) AND DI3 AND DI4 ;
INTERMED3 <= INTERMED1 OR INTERMED2 ;
INTERMED4 <= DI98 AND DI94 ;
INTERMED5 <= INTERMED3 AND INTERMED4;
DO8 <= INTERMED5 AND EN_C;
-- architecture body
end architecture_code_4_b;
|
<reponame>chandanpalai/VHDL-example-codes
library ieee;
use ieee.std_logic_1164.all;
entity dffrs_tb is
end entity dffrs_tb;
architecture dffrs_tb_arc of dffrs_tb is
component dasynrstpre is
port (
D : in std_logic; -- input
clk : in std_logic; -- input
rst : in std_logic; -- input
pre : in std_logic; -- input
Q : out std_logic); -- output
end component dasynrstpre;
signal D,clk,rst,pre : std_logic;
signal Q : std_logic := '0';
begin -- architecture dffrs_tb_arc
u0 : dasynrstpre port map (
D => D,
clk => clk,
rst => rst,
pre => pre,
Q => Q);
process
begin
rst<='1';pre<='0';clk<='0';D<='0';
wait for 10 ns;
rst<='0';pre<='1';clk<='0';D<='0';
wait for 10 ns;
rst<='0';pre<='0';clk<='0';D<='0';
wait for 10 ns;
rst<='0';pre<='0';clk<='1';D<='0';
wait for 10 ns;
rst<='0';pre<='0';clk<='0';D<='1';
wait for 10 ns;
rst<='0';pre<='0';clk<='1';D<='1';
wait for 10 ns;
rst<='1';pre<='0';clk<='0';D<='0';
wait for 10 ns;
rst<='0';pre<='0';clk<='1';D<='1';
wait for 10 ns;
rst<='0';pre<='0';clk<='0';D<='0';
wait for 10 ns;
rst<='0';pre<='0';clk<='1';D<='0';
wait for 10 ns;
rst<='0';pre<='1';clk<='0';D<='0';
wait for 10 ns;
wait;
end process;
end architecture dffrs_tb_arc;
|
<gh_stars>100-1000
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.common.all;
use work.decode_types.all;
entity divider is
port (
clk : in std_logic;
rst : in std_logic;
d_in : in Execute1ToDividerType;
d_out : out DividerToExecute1Type
);
end entity divider;
architecture behaviour of divider is
signal dend : std_ulogic_vector(128 downto 0);
signal div : unsigned(63 downto 0);
signal quot : std_ulogic_vector(63 downto 0);
signal result : std_ulogic_vector(63 downto 0);
signal sresult : std_ulogic_vector(64 downto 0);
signal oresult : std_ulogic_vector(63 downto 0);
signal running : std_ulogic;
signal count : unsigned(6 downto 0);
signal neg_result : std_ulogic;
signal is_modulus : std_ulogic;
signal is_32bit : std_ulogic;
signal extended : std_ulogic;
signal is_signed : std_ulogic;
signal overflow : std_ulogic;
signal ovf32 : std_ulogic;
signal did_ovf : std_ulogic;
begin
divider_0: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
dend <= (others => '0');
div <= (others => '0');
quot <= (others => '0');
running <= '0';
count <= "0000000";
elsif d_in.valid = '1' then
if d_in.is_extended = '1' then
dend <= '0' & d_in.dividend & x"0000000000000000";
else
dend <= '0' & x"0000000000000000" & d_in.dividend;
end if;
div <= unsigned(d_in.divisor);
quot <= (others => '0');
neg_result <= d_in.neg_result;
is_modulus <= d_in.is_modulus;
extended <= d_in.is_extended;
is_32bit <= d_in.is_32bit;
is_signed <= d_in.is_signed;
count <= "1111111";
running <= '1';
overflow <= '0';
ovf32 <= '0';
elsif running = '1' then
if count = "0111111" then
running <= '0';
end if;
overflow <= quot(63);
if dend(128) = '1' or unsigned(dend(127 downto 64)) >= div then
ovf32 <= ovf32 or quot(31);
dend <= std_ulogic_vector(unsigned(dend(127 downto 64)) - div) &
dend(63 downto 0) & '0';
quot <= quot(62 downto 0) & '1';
count <= count + 1;
elsif dend(128 downto 57) = x"000000000000000000" and count(6 downto 3) /= "0111" then
-- consume 8 bits of zeroes in one cycle
ovf32 <= or (ovf32 & quot(31 downto 24));
dend <= dend(120 downto 0) & x"00";
quot <= quot(55 downto 0) & x"00";
count <= count + 8;
else
ovf32 <= ovf32 or quot(31);
dend <= dend(127 downto 0) & '0';
quot <= quot(62 downto 0) & '0';
count <= count + 1;
end if;
else
count <= "0000000";
end if;
end if;
end process;
divider_1: process(all)
begin
if is_modulus = '1' then
result <= dend(128 downto 65);
else
result <= quot;
end if;
if neg_result = '1' then
sresult <= std_ulogic_vector(- signed('0' & result));
else
sresult <= '0' & result;
end if;
did_ovf <= '0';
if is_32bit = '0' then
did_ovf <= overflow or (is_signed and (sresult(64) xor sresult(63)));
elsif is_signed = '1' then
if ovf32 = '1' or sresult(32) /= sresult(31) then
did_ovf <= '1';
end if;
else
did_ovf <= ovf32;
end if;
if did_ovf = '1' then
oresult <= (others => '0');
elsif (is_32bit = '1') and (is_modulus = '0') then
-- 32-bit divisions set the top 32 bits of the result to 0
oresult <= x"00000000" & sresult(31 downto 0);
else
oresult <= sresult(63 downto 0);
end if;
end process;
divider_out: process(clk)
begin
if rising_edge(clk) then
d_out.valid <= '0';
d_out.write_reg_data <= oresult;
d_out.overflow <= did_ovf;
if count = "1000000" then
d_out.valid <= '1';
end if;
end if;
end process;
end architecture behaviour;
|
--------------------------------------------------------------------------------
-- PROJECT: RMII FIREWALL FPGA
--------------------------------------------------------------------------------
-- AUTHORS: <NAME> <<EMAIL>>
-- LICENSE: The MIT License, please read LICENSE file
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Only 100 Mbps full duplex mode is supported now.
entity RMII_MAC is
Port (
-- CLOCKS AND RESETS
RMII_CLK : in std_logic;
RMII_RST : in std_logic;
USER_CLK : in std_logic;
USER_RST : in std_logic;
-- RMII INTERFACE (RMII_CLK)
RMII_RXD : in std_logic_vector(1 downto 0);
RMII_CSR_DV : in std_logic;
RMII_TXD : out std_logic_vector(1 downto 0);
RMII_TX_EN : out std_logic;
-- USER OUTPUT STREAM INTERFACE (USER_CLK)
TX_DATA : out std_logic_vector(7 downto 0);
TX_SOP : out std_logic;
TX_EOP : out std_logic;
TX_VLD : out std_logic;
TX_RDY : in std_logic;
-- USER INPUT STREAM INTERFACE (USER_CLK)
RX_DATA : in std_logic_vector(7 downto 0);
RX_SOP : in std_logic;
RX_EOP : in std_logic;
RX_VLD : in std_logic;
RX_RDY : out std_logic;
-- WISHBONE SLAVE INTERFACE (USER_CLK)
WB_CYC : in std_logic;
WB_STB : in std_logic;
WB_WE : in std_logic;
WB_ADDR : in std_logic_vector(15 downto 0);
WB_DIN : in std_logic_vector(31 downto 0);
WB_STALL : out std_logic;
WB_ACK : out std_logic;
WB_DOUT : out std_logic_vector(31 downto 0)
);
end entity;
architecture RTL of RMII_MAC is
constant WB_PORTS : natural := 2;
signal split_wb_cyc : std_logic_vector(WB_PORTS-1 downto 0);
signal split_wb_stb : std_logic_vector(WB_PORTS-1 downto 0);
signal split_wb_we : std_logic_vector(WB_PORTS-1 downto 0);
signal split_wb_addr : std_logic_vector(WB_PORTS*16-1 downto 0);
signal split_wb_din : std_logic_vector(WB_PORTS*32-1 downto 0);
signal split_wb_stall : std_logic_vector(WB_PORTS-1 downto 0);
signal split_wb_ack : std_logic_vector(WB_PORTS-1 downto 0);
signal split_wb_dout : std_logic_vector(WB_PORTS*32-1 downto 0);
begin
rx_i : entity work.RX_RMII_MAC
port map (
RMII_CLK => RMII_CLK,
RMII_RST => RMII_RST,
USER_CLK => USER_CLK,
USER_RST => USER_RST,
RMII_RXD => RMII_RXD,
RMII_CSR_DV => RMII_CSR_DV,
TX_DATA => TX_DATA,
TX_SOP => TX_SOP,
TX_EOP => TX_EOP,
TX_VLD => TX_VLD,
TX_RDY => TX_RDY,
WB_CYC => split_wb_cyc(0),
WB_STB => split_wb_stb(0),
WB_WE => split_wb_we(0),
WB_ADDR => split_wb_addr(16-1 downto 0),
WB_DIN => split_wb_din(32-1 downto 0),
WB_STALL => split_wb_stall(0),
WB_ACK => split_wb_ack(0),
WB_DOUT => split_wb_dout(32-1 downto 0)
);
tx_i : entity work.TX_RMII_MAC
port map (
RMII_CLK => RMII_CLK,
RMII_RST => RMII_RST,
USER_CLK => USER_CLK,
USER_RST => USER_RST,
RMII_TXD => RMII_TXD,
RMII_TX_EN => RMII_TX_EN,
RX_DATA => RX_DATA,
RX_SOP => RX_SOP,
RX_EOP => RX_EOP,
RX_VLD => RX_VLD,
RX_RDY => RX_RDY,
WB_CYC => split_wb_cyc(1),
WB_STB => split_wb_stb(1),
WB_WE => split_wb_we(1),
WB_ADDR => split_wb_addr(32-1 downto 16),
WB_DIN => split_wb_din(64-1 downto 32),
WB_STALL => split_wb_stall(1),
WB_ACK => split_wb_ack(1),
WB_DOUT => split_wb_dout(64-1 downto 32)
);
wb_splitter_i : entity work.WB_SPLITTER
generic map (
MASTER_PORTS => WB_PORTS,
ADDR_OFFSET => 8
)
port map (
CLK => USER_CLK,
RST => USER_RST,
WB_S_CYC => WB_CYC,
WB_S_STB => WB_STB,
WB_S_WE => WB_WE,
WB_S_ADDR => WB_ADDR,
WB_S_DIN => WB_DIN,
WB_S_STALL => WB_STALL,
WB_S_ACK => WB_ACK,
WB_S_DOUT => WB_DOUT,
WB_M_CYC => split_wb_cyc,
WB_M_STB => split_wb_stb,
WB_M_WE => split_wb_we,
WB_M_ADDR => split_wb_addr,
WB_M_DOUT => split_wb_din,
WB_M_STALL => split_wb_stall,
WB_M_ACK => split_wb_ack,
WB_M_DIN => split_wb_dout
);
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX_TB is
end MUX_TB;
architecture Testbench of MUX_TB is
component MUX is
port (
S : in STD_LOGIC_VECTOR (1 downto 0);
LED : out STD_LOGIC;
CLK : in STD_LOGIC
);
end component;
signal input : STD_LOGIC_VECTOR (1 downto 0);
signal output, C_in : STD_LOGIC;
constant Period : time := 83.3333 ns; -- 12MHz clock
begin
uut : MUX
port map(S => input, LED => output, CLK => C_in); -- MUX Called
Clock : process -- 12MHz 50% duty cycle clock generator
begin
C_in <= '0'; -- low
wait for period/2;
C_in <= '1'; -- high
wait for period/2;
end process Clock;
simulus : process -- MUX simulation
begin
input <= "00"; -- choose S0 = '0' and S1 = '0'
wait for 2 sec; -- hold S0 = '0' and S1 = '0' 2 sec
input <= "01"; -- choose S0 = '0' and S1 = '1'
wait for 2 sec; -- hold S0 = '0' and S1 = '1' 2 sec
input <= "10"; -- choose S0 = '1' and S1 = '0'
wait for 2 sec; -- hold S0 = '1' and S1 = '0' 2 sec
input <= "11"; -- choose S0 = '1' and S1 = '1'
wait for 2 sec; -- hold S0 = '1' and S1 = '1' 2 sec
end process simulus;
end Testbench;
|
-- http://stevenmerrifield.com/max7219/index.html
-- Driver for MAX7219 with 8 digit 7-segment display
-- sjm 15 May 2017
library ieee;
use ieee.std_logic_1164.all;
entity M7219 is
port (
clk : in std_logic;
parallel : in std_logic_vector(31 downto 0);
clk_out : out std_logic;
data_out : out std_logic;
load : out std_logic
);
end entity;
architecture rtl of M7219 is
attribute syn_encoding : string;
type state_machine is (init_1, init_2, init_3, init_4, read_data, dig_7, dig_6, dig_5, dig_4, dig_3, dig_2, dig_1, dig_0);
attribute syn_encoding of state_machine : type is "safe";
signal state : state_machine := init_1;
type driver_machine is (idle, start, clk_data, clk_high, clk_low, finished);
attribute syn_encoding of driver_machine : type is "safe";
signal driver_state : driver_machine := idle;
signal command : std_logic_vector(15 downto 0) := x"0000";
signal driver_start : std_logic := '0';
function hex2seg(num : std_logic_vector(3 downto 0)) return std_logic_vector is
begin
case num is
when "0000" => return("01111110"); -- 0
when "0001" => return("00110000"); -- 1
when "0010" => return("01101101"); -- 2
when "0011" => return("01111001"); -- 3
when "0100" => return("00110011"); -- 4
when "0101" => return("01011011"); -- 5
when "0110" => return("01011111"); -- 6
when "0111" => return("01110000"); -- 7
when "1000" => return("01111111"); -- 8
when "1001" => return("01111011"); -- 9
when "1010" => return("01110111"); -- A
when "1011" => return("00011111"); -- b
when "1100" => return("00001101"); -- c
when "1101" => return("00111101"); -- d
when "1110" => return("01001111"); -- E
when "1111" => return("01000111"); -- F
when others => return("00000000");
end case;
end hex2seg;
begin
process
variable counter : integer := 0;
variable clk_counter : integer := 0;
variable latch_in : std_logic_vector(31 downto 0) := x"00000000";
variable dig0_data : std_logic_vector(7 downto 0) := x"00";
variable dig1_data : std_logic_vector(7 downto 0) := x"00";
variable dig2_data : std_logic_vector(7 downto 0) := x"00";
variable dig3_data : std_logic_vector(7 downto 0) := x"00";
variable dig4_data : std_logic_vector(7 downto 0) := x"00";
variable dig5_data : std_logic_vector(7 downto 0) := x"00";
variable dig6_data : std_logic_vector(7 downto 0) := x"00";
variable dig7_data : std_logic_vector(7 downto 0) := x"00";
begin
wait until rising_edge(clk);
case state is
when init_1 =>
if (driver_state = idle) then
command <= x"0c01"; -- shutdown / normal operation
driver_state <= start;
state <= init_2;
end if;
when init_2 =>
if (driver_state = idle) then
command <= x"0900"; -- decode mode
driver_state <= start;
state <= init_3;
end if;
when init_3 =>
if (driver_state = idle) then
command <= x"0A0A"; -- intensity
driver_state <= start;
state <= init_4;
end if;
when init_4 =>
if (driver_state = idle) then
command <= x"0B07"; -- scan limit
driver_state <= start;
state <= read_data;
end if;
when read_data =>
latch_in := parallel;
dig7_data := hex2seg(latch_in(31 downto 28));
dig6_data := hex2seg(latch_in(27 downto 24));
dig5_data := hex2seg(latch_in(23 downto 20));
dig4_data := hex2seg(latch_in(19 downto 16));
dig3_data := hex2seg(latch_in(15 downto 12));
dig2_data := hex2seg(latch_in(11 downto 8));
dig1_data := hex2seg(latch_in(7 downto 4));
dig0_data := hex2seg(latch_in(3 downto 0));
state <= dig_7;
when dig_7 =>
if (driver_state = idle) then
command <= x"08" & dig7_data;
driver_state <= start;
state <= dig_6;
end if;
when dig_6 =>
if (driver_state = idle) then
command <= x"07" & dig6_data;
driver_state <= start;
state <= dig_5;
end if;
when dig_5 =>
if (driver_state = idle) then
command <= x"06" & dig5_data;
driver_state <= start;
state <= dig_4;
end if;
when dig_4 =>
if (driver_state = idle) then
command <= x"05" & dig4_data;
driver_state <= start;
state <= dig_3;
end if;
when dig_3 =>
if (driver_state = idle) then
command <= x"04" & dig3_data;
driver_state <= start;
state <= dig_2;
end if;
when dig_2 =>
if (driver_state = idle) then
command <= x"03" & dig2_data;
driver_state <= start;
state <= dig_1;
end if;
when dig_1 =>
if (driver_state = idle) then
command <= x"02" & dig1_data;
driver_state <= start;
state <= dig_0;
end if;
when dig_0 =>
if (driver_state = idle) then
command <= x"01" & dig0_data;
driver_state <= start;
state <= read_data;
end if;
when others => null;
end case;
if (clk_counter < 100) then -- 100
clk_counter := clk_counter + 1;
else
clk_counter := 0;
case driver_state is
when idle =>
load <= '1';
clk_out <= '0';
when start =>
load <= '0';
counter := 16;
driver_state <= clk_data;
when clk_data =>
counter := counter - 1;
data_out <= command(counter);
driver_state <= clk_high;
when clk_high =>
clk_out <= '1';
driver_state <= clk_low;
when clk_low =>
clk_out <= '0';
if (counter = 0) then
load <= '1';
driver_state <= finished;
else
driver_state <= clk_data;
end if;
when finished =>
driver_state <= idle;
when others => null;
end case;
end if; -- clk_counter
end process;
end architecture;
|
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<filename>TE0720-01_TE0701-03_Base_Vivado-2014.1/src/system/ip/system_v_tc_1_0/v_tc_v6_1/hdl/vhdl/axi_lite_ipif.vhd
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|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.02.2021 20:16:28
-- Design Name:
-- Module Name: tb_mux_2bit_4to1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------
-- Entity declaration for testbench
------------------------------------------------------------------------
entity tb_comparator_2bit is
-- Entity of testbench is always empty
end entity tb_comparator_2bit;
------------------------------------------------------------------------
-- Architecture body for testbench
------------------------------------------------------------------------
architecture testbench of tb_comparator_2bit is
-- Local signals
signal s_a : std_logic_vector(2 - 1 downto 0);
signal s_b : std_logic_vector(2 - 1 downto 0);
signal s_c : std_logic_vector(2 - 1 downto 0);
signal s_d : std_logic_vector(2 - 1 downto 0);
signal s_f :std_logic_vector(2 - 1 downto 0);
signal s_sel :std_logic_vector(2 - 1 downto 0);
begin
-- Connecting testbench signals with comparator_2bit entity (Unit Under Test)
uut_comparator_2bit : entity work.comparator_2bit
port map(
a_i => s_a,
b_i => s_b,
c_i => s_a,
d_i => s_a,
f_o => s_f,
sel_i => s_sel
);
--------------------------------------------------------------------
-- Data generation process
--------------------------------------------------------------------
p_stimulus : process
begin
-- Report a note at the begining of stimulus process
report "Stimulus process started" severity note;
-- First test values
s_d <= "00"; s_c <= "00"; s_b <= "00"; s_a <= "00";
s_sel <= "00"; wait for 100 ns;
s_d <= "10"; s_c <= "01"; s_b <= "01"; s_a <= "00";
s_sel <= "00"; wait for 100 ns;
s_d <= "10"; s_c <= "01"; s_b <= "01"; s_a <= "11";
s_sel <= "00"; wait for 100 ns;
s_d <= "10"; s_c <= "01"; s_b <= "01"; s_a <= "00";
s_sel <= "01"; wait for 100 ns;
s_d <= "10"; s_c <= "01"; s_b <= "11"; s_a <= "00";
s_sel <= "00"; wait for 100 ns;
s_d <= "10"; s_c <= "01"; s_b <= "11"; s_a <= "00";
s_sel <= "01"; wait for 100 ns;
-- Expected output
-- WRITE OTHER TESTS HERE
-- Report a note at the end of stimulus process
report "Stimulus process finished" severity note;
wait;
end process p_stimulus;
end architecture testbench;
|
<filename>Code/Synthesis/computer_synth.vhd
-- Code by www.jk-quantized.com
-- Redistribution and use of this code in source and binary forms
-- must retain the above attribution notice and this condition.
library ieee;
use ieee.std_logic_1164.all;
use work.components_pk.all;
use work.UART_pk.all;
entity computer_synth is
port (
clk : in std_logic;
reset : in std_logic;
tx : out std_logic;
-- specific to development board
leds : out std_logic_vector( 2 downto 0 )
);
end entity;
architecture ac of computer_synth is
-- Computer
signal outputReady : std_logic;
signal outputRegOut : std_logic_vector( N - 1 downto 0 );
-- UART
--constant clksPerBit : integer := 26; -- small value for testbench
constant clksPerBit : integer := 434; -- 50M Hz / 115200 Hz
--constant clksPerBit : integer := 5208; -- 50M Hz / 9600 Hz
signal txActive, txDone : std_logic;
begin
comp_computer : computer port map (
clk,
reset,
txActive,
outputReady,
outputRegOut
);
comp_uartTX : UART_TX
generic map (
clksPerBit
)
port map (
clk,
outputReady,
outputRegOut,
tx,
txActive,
txDone
);
-- Specific to development board
-- turn off onboard LEDs (active low)
leds(0) <= '1';
leds(1) <= '1';
leds(2) <= '1';
end architecture;
--
|
<filename>DE1_Quartus/HexTo7SegmentDisplay.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity HexTo7SegmentDisplay is
Port (
Input1 : in std_logic_vector(7 downto 0);
Display1 : out std_logic_vector(6 downto 0) ;
Display0 : out std_logic_vector(6 downto 0)
);
end ;
architecture bhvr of HexTo7SegmentDisplay is
Begin
process(Input1)
Begin
if(Input1(7 downto 4) = X"0") then Display1 <= b"1000000";
elsif(Input1(7 downto 4) = X"1") then Display1 <= b"1111001";
elsif(Input1(7 downto 4) = X"2") then Display1 <= b"0100100";
elsif(Input1(7 downto 4) = X"3") then Display1 <= b"0110000";
elsif(Input1(7 downto 4) = X"4") then Display1 <= b"0011001";
elsif(Input1(7 downto 4) = X"5") then Display1 <= b"0010010";
elsif(Input1(7 downto 4) = X"6") then Display1 <= b"0000010";
elsif(Input1(7 downto 4) = X"7") then Display1 <= b"1111000";
elsif(Input1(7 downto 4) = X"8") then Display1 <= b"0000000";
elsif(Input1(7 downto 4) = X"9") then Display1 <= b"0010000";
elsif(Input1(7 downto 4) = X"A") then Display1 <= b"0001000";
elsif(Input1(7 downto 4) = X"B") then Display1 <= b"0000011";
elsif(Input1(7 downto 4) = X"C") then Display1 <= b"1000110";
elsif(Input1(7 downto 4) = X"D") then Display1 <= b"0100001";
elsif(Input1(7 downto 4) = X"E") then Display1 <= b"0000110";
else Display1 <= b"0001110";
end if;
End Process;
process(Input1)
Begin
if(Input1(3 downto 0) = X"0") then Display0 <= b"1000000";
elsif(Input1(3 downto 0) = X"1") then Display0 <= b"1111001";
elsif(Input1(3 downto 0) = X"2") then Display0 <= b"0100100";
elsif(Input1(3 downto 0) = X"3") then Display0 <= b"0110000";
elsif(Input1(3 downto 0) = X"4") then Display0 <= b"0011001";
elsif(Input1(3 downto 0) = X"5") then Display0 <= b"0010010";
elsif(Input1(3 downto 0) = X"6") then Display0 <= b"0000010";
elsif(Input1(3 downto 0) = X"7") then Display0 <= b"1111000";
elsif(Input1(3 downto 0) = X"8") then Display0 <= b"0000000";
elsif(Input1(3 downto 0) = X"9") then Display0 <= b"0010000";
elsif(Input1(3 downto 0) = X"A") then Display0 <= b"0001000";
elsif(Input1(3 downto 0) = X"B") then Display0 <= b"0000011";
elsif(Input1(3 downto 0) = X"C") then Display0 <= b"1000110";
elsif(Input1(3 downto 0) = X"D") then Display0 <= b"0100001";
elsif(Input1(3 downto 0) = X"E") then Display0 <= b"0000110";
else Display0 <= b"0001110";
end if ;
End Process;
End;
|
---------------------------------------------------------------------------------------------------
--
-- Title : NewDecoder
-- Design : NewDecoder
-- Author : YY
-- date : 6-2-2002
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.channel.all;
entity NewDecoder is
port(
AsyncMux_sel : out std_logic;
failed : out std_logic
);
end NewDecoder;
architecture NewDecoder of NewDecoder is
component hwvhdl
generic(
fheight : integer := 11;
fwidth : integer := 15;
pagesize : integer := 64
);
port (
cnt_ack : in std_logic;
dpCal_ack : in std_logic;
mem_ack : in std_logic;
mtt_ack : in std_logic;
reset : in std_logic;
AsyncMux_sel : out std_logic := '0';
DPdata : inout channel := init_channel;
cb : inout channel := init_channel;
cnt_req : inout std_logic := '0';
cr : inout channel := init_channel;
dpCal_req : inout std_logic := '0';
lum : inout channel := init_channel;
mem_req : inout std_logic := '0';
mtt_req : inout std_logic := '0';
outp : inout channel := init_channel
);
end component;
component swvhdl
generic(
fheight : integer := 11;
fwidth : integer := 15
);
port (
dpCal_req : in std_logic;
mem_req : in std_logic;
mtt_req : in std_logic;
failed : out std_logic := '0';
reset : out std_logic := '0';
DPdata : inout channel := init_channel;
cb : inout channel := init_channel;
cr : inout channel := init_channel;
dpCal_ack : inout std_logic := '0';
lum : inout channel := init_channel;
mem_ack : inout std_logic := '0';
mtt_ack : inout std_logic := '0';
outp : inout channel := init_channel
);
end component;
signal cb : channel := init_channel;
signal cnt_ack : std_logic;
signal cnt_req : std_logic;
signal cr : channel := init_channel;
signal dpCal_ack : std_logic;
signal dpCal_req : std_logic;
signal DPdata : channel := init_channel;
signal lum : channel := init_channel;
signal mem_ack : std_logic;
signal mem_req : std_logic;
signal mtt_ack : std_logic;
signal mtt_req : std_logic;
signal outp : channel := init_channel;
signal reset : std_logic;
begin
Decoder : hwvhdl
port map(
AsyncMux_sel => AsyncMux_sel,
DPdata => DPdata,
cb => cb,
cnt_ack => cnt_ack,
cnt_req => cnt_req,
cr => cr,
dpCal_ack => dpCal_ack,
dpCal_req => dpCal_req,
lum => lum,
mem_ack => mem_ack,
mem_req => mem_req,
mtt_ack => mtt_ack,
mtt_req => mtt_req,
outp => outp,
reset => reset
);
Enviorment : swvhdl
port map(
DPdata => DPdata,
cb => cb,
cr => cr,
failed => failed,
lum => lum,
outp => outp,
reset => reset
);
end NewDecoder;
|
<reponame>amirsoleix/mano-system-architecture<filename>src/Mano_DataPath/E_FF.vhd
----------------------------------------------------------------------------------
-- Company: Amirkabir University of Technology
-- Engineer: <NAME>
--
-- Module Name: E_FF - Behavioral
-- Project Name:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity E_FF is
Port ( Clk : in STD_LOGIC;
Rst : in STD_LOGIC;
LD : in STD_LOGIC;
Comp : in STD_LOGIC;
Ein : in STD_LOGIC;
Eout : out STD_LOGIC);
end E_FF;
architecture Behavioral of E_FF is
signal Eout_sig: STD_LOGIC;
begin
Eout <= Eout_sig;
process(Clk)
begin
if (Clk='1' and Clk'event) then
if (Rst='1') then
Eout_sig <= '0';
elsif (LD = '1') then
Eout_sig <= Ein;
elsif (Comp = '1') then
Eout_sig <= not Eout_sig;
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:58:08 01/31/2020
-- Design Name:
-- Module Name: SevenSegmentDriver - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SevenSegmentDriver is
Port ( Digit1 : in STD_LOGIC_VECTOR (7 downto 0);
Digit2 : in STD_LOGIC_VECTOR (7 downto 0);
Digit3 : in STD_LOGIC_VECTOR (7 downto 0);
Digit4 : in STD_LOGIC_VECTOR (7 downto 0);
Digit5 : in STD_LOGIC_VECTOR (7 downto 0);
Digit6 : in STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dig_out : out STD_LOGIC_VECTOR (7 downto 0);
sel_out : out STD_LOGIC_VECTOR (5 downto 0));
end SevenSegmentDriver;
architecture Behavioral of SevenSegmentDriver is
signal clk_tick : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal sel_buffer : STD_LOGIC_VECTOR(5 downto 0) := "111110";
begin
process(clk, reset)
begin
if rising_edge(clk) then
if reset = '0' then
sel_buffer <= "111110";
elsif clk_tick = x"FFFF" then
sel_buffer <= sel_buffer(4) & sel_buffer(3) & sel_buffer(2) & sel_buffer(1) & sel_buffer(0) & sel_buffer(5);
clk_tick <= (others => '0');
else
clk_tick <= clk_tick + 1;
end if;
end if;
end process;
sel_out <= sel_buffer;
dig_out <= Digit6 when (sel_buffer = "111110") else
Digit5 when (sel_buffer = "111101") else
Digit4 when (sel_buffer = "111011") else
Digit3 when (sel_buffer = "110111") else
Digit2 when (sel_buffer = "101111") else
Digit1 when (sel_buffer = "011111") else
(others => '1');
end Behavioral;
|
<reponame>Kolchuzhin/micro_mirror_cell_in_VHDL-AMS<gh_stars>1-10
package electromagnetic_system is
nature electrical is real across real through electrical_ground reference;
nature translational is real across real through mechanical_ground reference;
end package electromagnetic_system;
use work.s_dat_130.all;
use work.ca12_dat_130.all;
use work.ca13_dat_130.all;
use work.ca23_dat_130.all;
use work.initial.all;
use work.electromagnetic_system.all;
entity transducer is
generic (delay:time; el_load1, el_load2:real);
port (terminal struc1,struc2:translational;
terminal lagrange1,lagrange2,lagrange3:translational;
terminal master1,master2,master3:translational;
terminal elec1,elec2,elec3:electrical);
end;
architecture behav of transducer is
type ret_type is array(1 to 4) of real;
quantity q1 across fm1 through struc1;
quantity q2 across fm2 through struc2;
quantity p1 across r1 through lagrange1;
quantity p2 across r2 through lagrange2;
quantity p3 across r3 through lagrange3;
quantity u1 across f1 through master1;
quantity u2 across f2 through master2;
quantity u3 across f3 through master3;
quantity v1 across i1 through elec1;
quantity v2 across i2 through elec2;
quantity v3 across i3 through elec3;
-------------------------------------------------------------------------------------
-- The following function us used to evaluate the strain energy and the capacities --
-- at the operating point. Results are the function value itself --
-- and the first derivatives with respect to the modal coordinates --
-------------------------------------------------------------------------------------
function spoly_calc(qx, qy, qz : in real:=0.0; s_type,s_inve : integer :=0;
s_ord, s_fak, s_data:real_vector) return ret_type is
constant Sx:integer:=integer(s_ord(1))+1;
constant Sy:integer:=integer(s_ord(2))+1;
constant Sz:integer:=integer(s_ord(3))+1;
variable fwx:real_vector(1 to Sx):=(others=>0.0);
variable fwy:real_vector(1 to Sy):=(others=>0.0);
variable fwz:real_vector(1 to 1):=(others=>0.0);
variable dfwx:real_vector(1 to Sx):=(others=>0.0);
variable dfwy:real_vector(1 to Sy):=(others=>0.0);
variable dfwz:real_vector(1 to 1):=(others=>0.0);
variable res_val:ret_type:=(others=>0.0);
variable fwv,dfwvx,dfwvy,dfwvz,fak2:real:=0.0;
variable Px_s,Py_s,Px,Py,Lx,Ly,Lz,ii:integer:=0;
begin
Lx:=integer(s_ord(1));
Ly:=integer(s_ord(2));
Lz:=integer(s_ord(3));
for i in 1 to Lx+1 loop
fwx(i):=qx**(i-1)*s_fak(1)**(i-1);
if i=2 then
dfwx(i):=s_fak(1)**(i-1);
end if;
if i>2 then
dfwx(i):=real(i-1)*qx**(i-2)*s_fak(1)**(i-1);
end if;
end loop;
for i in 1 to Ly+1 loop
fwy(i):=qy**(i-1)*s_fak(2)**(i-1);
if i=2 then
dfwy(i):=s_fak(2)**(i-1);
end if;
if i>2 then
dfwy(i):=real(i-1)*qy**(i-2)*s_fak(2)**(i-1);
end if;
end loop;
for i in 1 to Lz+1 loop
fwz(i):=qz**(i-1)*s_fak(3)**(i-1);
if i=2 then
dfwz(i):=s_fak(3)**(i-1);
end if;
if i>2 then
dfwz(i):=real(i-1)*qz**(i-2)*s_fak(3)**(i-1);
end if;
end loop;
if s_type=1 then
ii:=1;
for zi in 0 to Lz loop
for yi in 0 to Ly loop
for xi in 0 to Lx loop
fwv:=fwv+s_data(ii)*fwx(xi+1)*fwy(yi+1)*fwz(zi+1);
dfwvx:=dfwvx+s_data(ii)*dfwx(xi+1)*fwy(yi+1)*fwz(zi+1);
dfwvy:=dfwvy+s_data(ii)*fwx(xi+1)*dfwy(yi+1)*fwz(zi+1);
dfwvz:=dfwvz+s_data(ii)*fwx(xi+1)*fwy(yi+1)*dfwz(zi+1);
ii:=ii+1;
end loop;
end loop;
end loop;
end if;
if s_type=2 then
ii:=1;
Px_s:=integer(s_ord(1));
Py_s:=integer(s_ord(2));
for zi in 0 to Lz loop
Px:=Px_s-zi;
Py:=Py_s;
for yi in 0 to Py loop
for xi in 0 to Px loop
fwv:=fwv+s_data(ii)*fwx(xi+1)*fwy(yi+1)*fwz(zi+1);
dfwvx:=dfwvx+s_data(ii)*dfwx(xi+1)*fwy(yi+1)*fwz(zi+1);
dfwvy:=dfwvy+s_data(ii)*fwx(xi+1)*dfwy(yi+1)*fwz(zi+1);
dfwvz:=dfwvz+s_data(ii)*fwx(xi+1)*fwy(yi+1)*dfwz(zi+1);
ii:=ii+1;
end loop;
Px:=Px-1;
end loop;
Py:=Py-1;
end loop;
end if;
if s_type=3 then
ii:=1;
for yi in 0 to Ly loop
for xi in 0 to Lx loop
fwv:=fwv+s_data(ii)*fwx(xi+1)*fwy(yi+1);
dfwvx:=dfwvx+s_data(ii)*dfwx(xi+1)*fwy(yi+1);
dfwvy:=dfwvy+s_data(ii)*fwx(xi+1)*dfwy(yi+1);
dfwvz:=dfwvz+0.0;
ii:=ii+1;
end loop;
end loop;
for zi in 1 to Lz loop
for xi in 0 to Lx loop
fwv:=fwv+s_data(ii)*fwx(xi+1)*fwz(zi+1);
dfwvx:=dfwvx+s_data(ii)*dfwx(xi+1)*fwz(zi+1);
dfwvy:=dfwvy+0.0;
dfwvz:=dfwvz+s_data(ii)*fwx(xi+1)*dfwz(zi+1);
ii:=ii+1;
end loop;
end loop;
for zi in 1 to Lz loop
for yi in 1 to Ly loop
fwv:=fwv+s_data(ii)*fwy(yi+1)*fwz(zi+1);
dfwvx:=dfwvx+0.0;
dfwvy:=dfwvy+s_data(ii)*dfwy(yi+1)*fwz(zi+1);
dfwvz:=dfwvz+s_data(ii)*fwy(yi+1)*dfwz(zi+1);
ii:=ii+1;
end loop;
end loop;
end if;
if s_type=4 then
ii:=1;
Px:=integer(s_ord(1));
Py:=integer(s_ord(2));
for yi in 0 to Py loop
for xi in 0 to Px loop
fwv:=fwv+s_data(ii)*fwx(xi+1)*fwy(yi+1);
dfwvx:=dfwvx+s_data(ii)*dfwx(xi+1)*fwy(yi+1);
dfwvy:=dfwvy+s_data(ii)*fwx(xi+1)*dfwy(yi+1);
dfwvz:=dfwvz+0.0;
ii:=ii+1;
end loop;
Px:=Px-1;
end loop;
Px:=integer(s_ord(1));
for zi in 1 to Lz loop
for xi in 0 to Px-1 loop
fwv:=fwv+s_data(ii)*fwx(xi+1)*fwz(zi+1);
dfwvx:=dfwvx+s_data(ii)*dfwx(xi+1)*fwz(zi+1);
dfwvy:=dfwvy+0.0;
dfwvz:=dfwvz+s_data(ii)*fwx(xi+1)*dfwz(zi+1);
ii:=ii+1;
end loop;
Px:=Px-1;
end loop;
for zi in 1 to Lz-1 loop
for yi in 1 to Py-1 loop
fwv:=fwv+s_data(ii)*fwy(yi+1)*fwz(zi+1);
dfwvx:=dfwvx+0.0;
dfwvy:=dfwvy+s_data(ii)*dfwy(yi+1)*fwz(zi+1);
dfwvz:=dfwvz+s_data(ii)*fwy(yi+1)*dfwz(zi+1);
ii:=ii+1;
end loop;
Py:=Py-1;
end loop;
end if;
if s_inve=1 then
fwv:=fwv*s_fak(4);
dfwvx:=dfwvx*s_fak(4);
dfwvy:=dfwvy*s_fak(4);
dfwvz:=dfwvz*s_fak(4);
else
fak2:=1.0/s_fak(4);
dfwvx:=-dfwvx/(fwv**2);
dfwvy:=-dfwvy/(fwv**2);
dfwvz:=-dfwvz/(fwv**2);
fwv:=1.0/fwv;
fwv:=fwv*fak2;
dfwvx:=dfwvx*fak2;
dfwvy:=dfwvy*fak2;
dfwvz:=dfwvz*fak2;
end if;
res_val:=(fwv, dfwvx, dfwvy, dfwvz);
return res_val;
end spoly_calc;
-------------------------------------------------------------------------------------
-- end _spoly_calc_ function --
-------------------------------------------------------------------------------------
signal sene_130:ret_type;
signal ca12_130:ret_type;
signal ca13_130:ret_type;
signal ca23_130:ret_type;
begin
p1:process
begin
sene_130<= spoly_calc(q1,q2,0.0,s_type130,s_inve130,s_ord130,s_fak130,s_data130);
ca12_130<= spoly_calc(q1,q2,0.0,ca12_type130,ca12_inve130,ca12_ord130,ca12_fak130,ca12_data130);
ca13_130<= spoly_calc(q1,q2,0.0,ca13_type130,ca13_inve130,ca13_ord130,ca13_fak130,ca13_data130);
ca23_130<= spoly_calc(q1,q2,0.0,ca23_type130,ca23_inve130,ca23_ord130,ca23_fak130,ca23_data130);
wait for delay;
end process;
break on sene_130(2),sene_130(3),sene_130(4),ca12_130(2),ca12_130(3),ca12_130(4),ca13_130(2),ca13_130(3),ca13_130(4),ca23_130(2),ca23_130(3),ca23_130(4);
-- The following lines describe the governing differential equation at each pin:
fm1==mm_1*q1'dot'dot + dm_1*q1'dot +sene_130(2) -ca12_130(2)*(v1-v2)**2/2.0 -ca13_130(2)*(v1-v3)**2/2.0 -ca23_130(2)*(v2-v3)**2/2.0 +fi1_1*p1 +fi2_1*p2 +fi3_1*p3 -el1_1*el_load1 -el2_1*el_load2;
fm2==mm_2*q2'dot'dot + dm_2*q2'dot +sene_130(3) -ca12_130(3)*(v1-v2)**2/2.0 -ca13_130(3)*(v1-v3)**2/2.0 -ca23_130(3)*(v2-v3)**2/2.0 +fi1_2*p1 +fi2_2*p2 +fi3_2*p3 -el1_2*el_load1 -el2_2*el_load2;
--fm1==mm_1*q1'dot'dot + dm_1*q1'dot +sene_130(2);
--fm2==mm_2*q2'dot'dot + dm_2*q2'dot +sene_130(3);
--fm1==mm_1*q1'dot'dot + dm_1*q1'dot + 173.038*q1;
--fm2==mm_2*q2'dot'dot + dm_2*q2'dot + 924.245*q2;
r1==fi1_1*q1+fi1_2*q2-u1;
r2==fi2_1*q1+fi2_2*q2-u2;
r3==fi3_1*q1+fi3_2*q2-u3;
f1==-p1;
f2==-p2;
f3==-p3;
i1==+((v1-v2)*(ca12_130(2)*q1'dot+ca12_130(3)*q2'dot)+(v1'dot-v2'dot)*ca12_130(1))+((v1-v3)*(ca13_130(2)*q1'dot+ca13_130(3)*q2'dot)+(v1'dot-v3'dot)*ca13_130(1));
i2==-((v1-v2)*(ca12_130(2)*q1'dot+ca12_130(3)*q2'dot)+(v1'dot-v2'dot)*ca12_130(1))+((v2-v3)*(ca23_130(2)*q1'dot+ca23_130(3)*q2'dot)+(v2'dot-v3'dot)*ca23_130(1));
i3==-((v1-v3)*(ca13_130(2)*q1'dot+ca13_130(3)*q2'dot)+(v1'dot-v3'dot)*ca13_130(1))-((v2-v3)*(ca23_130(2)*q1'dot+ca23_130(3)*q2'dot)+(v2'dot-v3'dot)*ca23_130(1));
end;
|
library ieee, myLibrary;
use ieee.std_logic_1164.all;
use myLibrary.felipe.all;
entity maquina is
port (
start: in std_logic;
reset: in std_logic;
clk: in std_logic;
state: inout estado:= inicial;
cont: out natural := 0;
sinalVermelhoV: out std_logic;
sinalAmareloV: out std_logic;
sinalVerdeV: buffer std_logic;
sinalVermelhoP: out std_logic;
sinalVerdeP: buffer std_logic
);
end maquina;
architecture maquina_arq of maquina is
signal aux: natural :=0;
begin
process(start, reset, clk) is
begin
if reset = '0' then
state <= inicial;
aux <= 0;
elsif state = inicial then
sinalVermelhoV <= '1'; --Estado inicial dos semaforos
sinalAmareloV <= '1';
sinalVerdeV <= '0';
sinalVermelhoP <= '0';
sinalVerdeP <= '1';
if (start'event and start = '0') then
state <= espera;
end if;
aux <= 0;
elsif state = espera then
state <= piscaVerdeVec;
elsif state = piscaVerdeVec then
sinalVerdeV <= not sinalVerdeV;
sinalVerdeV <= not sinalVerdeV;
sinalVerdeV <= not sinalVerdeV;
state <= luzAmarelaVec;
aux <= 0;
elsif state = luzAmarelaVec then
sinalVermelhoV <= '1';
sinalAmareloV <= '0';
sinalVerdeV <= '1';
sinalVermelhoP <= '0';
sinalVerdeP <= '1';
state <= luzVermelhaVec;
aux <= 0;
elsif state = luzVermelhaVec then
sinalVermelhoV <= '0';
sinalAmareloV <= '1';
sinalVerdeV <= '1';
sinalVermelhoP <= '0';
sinalVerdeP <= '1';
state <= atravessa;
aux <= 0;
elsif state = atravessa then
sinalVermelhoV <= '0';
sinalAmareloV <= '1';
sinalVerdeV <= '1';
sinalVermelhoP <= '1';
sinalVerdeP <= '0';
state <= piscaVerdePed;
aux <= 0;
elsif state = piscaVerdeVec then
sinalVerdeP <= not sinalVerdeP;
sinalVerdeP <= not sinalVerdeP;
sinalVerdeP <= not sinalVerdeP;
state <= luzVermelhaPed;
aux <= 0;
elsif state = luzVermelhaPed then
sinalVermelhoV <= '0';
sinalAmareloV <= '1';
sinalVerdeV <= '1';
sinalVermelhoP <= '0';
sinalVerdeP <= '1';
state <= inicial;
aux <= 0;
elsif (clk'event and clk = '1') then
if aux < 3 then
aux <= aux + 1;
end if;
end if;
end process;
cont <= aux;
end maquina_arq;
|
---------------------------------------------------------------------------
-- Copyright 2018 <NAME>, <NAME>
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- When you publish any results arising from the use of this code, we will
-- appreciate it if you can cite our webpage.
-- (https://github.com/UoPeceHWSec/FlexLECO)
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- AES-key/data component - Crypto FPGA Side
--
-- File name : Crypto_Algo_In.vhd
-- Version : Version beta 1.0
-- Created : 2/JAN/2016
-- Last update : 12/JAN/2016
-- Desgined by : <NAME>
---------------------------------------------
library IEEE;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_1164.ALL;
entity Crypto_Algo_In is
generic (N: integer:=16; K: integer:=8; INS: integer:=2; DAO: integer:=1; EXBITS: integer:=0);
port ( -------------- Clock and Reset
clk: in std_logic;
rst: in std_logic;
---- Crypto Bus ----
blk_in1: out std_logic_vector (8*N-1 downto 0); --(Interface -> Cryptographic module) --generic
blk_in5: out std_logic_vector (8*N-1 downto 0); --(Interface -> Cryptographic module) --generic
-- blk_in4: out std_logic_vector (8*N-1 downto 0); --(Interface -> Cryptographic module) --generic
-- blk_in3: out std_logic_vector (8*N-1 downto 0); --(Interface -> Cryptographic module) --generic
-- blk_in2: out std_logic_vector (8*N-1 downto 0); --(Interface -> Cryptographic module) --generic
s_krdy_cr: out std_logic;
s_drdy_cr: out std_logic;
---- Slow Local Bus ----
s_krdy: in std_logic;
s_drdy: in std_logic;
s_kvld: out std_logic;
s_dvld: out std_logic;
hyperegin: in std_logic_vector (INS*8*N-1 downto 0));
end Crypto_Algo_In;
architecture arch of Crypto_Algo_In is
signal in1: std_logic_vector (8*N-1 downto 0);
signal in2: std_logic_vector (8*N-1 downto 0);
signal in3: std_logic_vector (8*N-1 downto 0);
signal in4: std_logic_vector (8*N-1 downto 0);
signal in5: std_logic_vector (8*N-1 downto 0);
signal kvld: std_logic;
signal dvld: std_logic;
begin
AESproc: process (clk)
begin
if (clk'event and clk='1') then
if rst='1' then
in1 <= (others=>'0');
in5 <= (others=>'0');
-- in4 <= (others=>'0');
-- in3 <= (others=>'0');
-- in2 <= (others=>'0');
kvld <= '0';
dvld <= '0';
else
case s_krdy is
when '1' =>
in1(8*N-1 downto 0) <= hyperegin(8*N-1 downto 0);
kvld <= '1';
when others =>
in1 <= in1;
kvld <= '0';
end case;
case s_drdy is
when '1' =>
in5(8*N-1 downto 0) <= hyperegin (8*N-1 downto 0);
-- in4(8*N-1 downto 0) <= hyperegin((2*8*N-1) downto (8*N));
-- in3(8*N-1 downto 0) <= hyperegin((3*8*N-1) downto (2*8*N));
-- in2(8*N-1 downto 0) <= hyperegin((4*8*N-1) downto (3*8*N));
dvld <= '1';
when others =>
in5 <= in5;
in4 <= in4;
in3 <= in3;
in2 <= in2;
dvld <= '0';
end case;
end if;
end if;
end process;
s_krdy_cr <= kvld;
s_drdy_cr <= dvld;
s_kvld <= kvld;
s_dvld <= dvld;
blk_in1 <= in1;
blk_in5 <= in5;
-- blk_in4 <= in4;
-- blk_in3 <= in3;
-- blk_in2 <= in2;
end arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.03.2021 12:24:49
-- Design Name:
-- Module Name: tb_d_latch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_d_latch is
-- Port ( );
end tb_d_latch;
architecture Behavioral of tb_d_latch is
signal s_en : std_logic;
signal s_arst : std_logic;
signal s_d : std_logic;
signal s_q : std_logic;
signal s_qbar : std_logic;
begin
uut_d_latch : entity work.d_latch
port map(
en => s_en,
arst => s_arst,
d => s_d,
q => s_q,
q_bar => s_qbar
);
p_reset_gen : process
begin
s_arst <= '0';
wait for 40 ns;
-- Reset activated
s_arst <= '1';
wait for 50 ns;
--Reset deactivated
s_arst <= '0';
wait for 85 ns;
s_arst <= '1';
wait;
end process p_reset_gen;
--------------------------------------------------------------------
-- Data generation process
--------------------------------------------------------------------
p_stimulus : process
begin
report "Stimulus process started" severity note;
s_d <= '0';
s_en <= '0';
--d sekv (en <= '0')
wait for 10 ns;
s_d <= '1';
wait for 10 ns;
s_d <= '0';
wait for 5 ns;
assert(s_q = '0' and s_qbar = '1')
report "Chyba" severity error;
wait for 5 ns;
s_d <= '1';
wait for 10 ns;
s_d <= '0';
wait for 10 ns;
s_d <= '1';
wait for 10 ns;
s_d <= '0';
s_en <= '1';
--d sekv (en <= '1')
wait for 10 ns;
s_d <= '1';
wait for 10 ns;
s_d <= '0';
wait for 10 ns;
s_d <= '1';
wait for 10 ns;
s_d <= '0';
wait for 10 ns;
s_d <= '0';
s_en <= '0';
--d sekv (en <= '0')
wait for 10 ns;
s_d <= '1';
wait for 5 ns;
wait for 5 ns;
s_d <= '0';
wait for 10 ns;
s_d <= '1';
wait for 10 ns;
s_d <= '0';
wait for 10 ns;
s_d <= '0';
s_en <= '1';
--d sekv (en <= '1')
wait for 5 ns;
wait for 5 ns;
s_d <= '1';
wait for 6 ns;
wait for 4 ns;
s_d <= '0';
wait for 10 ns;
s_d <= '1';
wait for 10 ns;
s_d <= '0';
wait for 10 ns;
report "Stimulus process finished" severity note;
wait;
end process p_stimulus;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_tb is
end entity;
architecture testbench of counter_tb is
component counter
port(
clk: in std_logic;
n_rst: in std_logic;
cout: out std_logic_vector (7 downto 0)
);
end component;
signal clk: std_logic;
signal n_rst: std_logic;
signal cout: std_logic_vector (7 downto 0);
begin
dut: counter port map (clk, n_rst, cout);
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
process
begin
n_rst <= '0';
wait for 10 ns;
n_rst <= '1';
wait for 250 ns;
end process;
end;
|
<reponame>gggmmm/BFSK-demodulator
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.my_package.all;
entity TB_BUTTERFLY_8_TW is
end entity TB_BUTTERFLY_8_TW;
architecture TB_BUTTERFLY_8_TW_ARCH of TB_BUTTERFLY_8_TW is
component butterfly_8_TW is
port(
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
start2 : in std_logic;
op0 : in complex12;
op1 : in complex12;
op2 : in complex12;
op3 : in complex12;
op4 : in complex12;
op5 : in complex12;
op6 : in complex12;
op7 : in complex12;
res0 : out complex12;
res1 : out complex12;
res2 : out complex12;
res3 : out complex12;
res4 : out complex12;
res5 : out complex12;
res6 : out complex12;
res7 : out complex12
);
end component butterfly_8_TW;
signal clock : std_logic := '0';
signal reset : std_logic;
signal start : std_logic;
signal start2 : std_logic;
signal op0 : complex12;
signal op1 : complex12;
signal op2 : complex12;
signal op3 : complex12;
signal op4 : complex12;
signal op5 : complex12;
signal op6 : complex12;
signal op7 : complex12;
signal res0 : complex12;
signal res1 : complex12;
signal res2 : complex12;
signal res3 : complex12;
signal res4 : complex12;
signal res5 : complex12;
signal res6 : complex12;
signal res7 : complex12;
begin
B: butterfly_8_tw port map(
clock => clock,
reset => reset,
start => start,
start2 => start2,
op0 => op0,
op1 => op1,
op2 => op2,
op3 => op3,
op4 => op4,
op5 => op5,
op6 => op6,
op7 => op7,
res0 => res0,
res1 => res1,
res2 => res2,
res3 => res3,
res4 => res4,
res5 => res5,
res6 => res6,
res7 => res7
);
clock <= not clock after 10 ns;
process
variable test : integer := 0;
variable total : integer := 0;
begin
start <= '0';
start2 <= '0';
reset <= '1';
wait for 50 ns;
reset <= '0';
-- ===== TEST 1 =====
op0.c <= '0'; op0.l.s <= '0'; op0.l.m <= std_logic_vector(to_unsigned(128,op0.r.m'length)); op0.r.s <= '0'; op0.r.m <= std_logic_vector(to_unsigned(0,op0.r.m'length));
op1.c <= '0'; op1.l.s <= '0'; op1.l.m <= std_logic_vector(to_unsigned(256,op0.r.m'length)); op1.r.s <= '0'; op1.r.m <= std_logic_vector(to_unsigned(0,op1.r.m'length));
op2.c <= '0'; op2.l.s <= '0'; op2.l.m <= std_logic_vector(to_unsigned(384,op0.r.m'length)); op2.r.s <= '0'; op2.r.m <= std_logic_vector(to_unsigned(0,op2.r.m'length));
op3.c <= '0'; op3.l.s <= '0'; op3.l.m <= std_logic_vector(to_unsigned(512,op0.r.m'length)); op3.r.s <= '0'; op3.r.m <= std_logic_vector(to_unsigned(0,op3.r.m'length));
op4.c <= '0'; op4.l.s <= '0'; op4.l.m <= std_logic_vector(to_unsigned(640,op0.r.m'length)); op4.r.s <= '0'; op4.r.m <= std_logic_vector(to_unsigned(0,op4.r.m'length));
op5.c <= '0'; op5.l.s <= '0'; op5.l.m <= std_logic_vector(to_unsigned(768,op0.r.m'length)); op5.r.s <= '0'; op5.r.m <= std_logic_vector(to_unsigned(0,op5.r.m'length));
op6.c <= '0'; op6.l.s <= '0'; op6.l.m <= std_logic_vector(to_unsigned(896,op0.r.m'length)); op6.r.s <= '0'; op6.r.m <= std_logic_vector(to_unsigned(0,op6.r.m'length));
op7.c <= '0'; op7.l.s <= '0'; op7.l.m <= std_logic_vector(to_unsigned(1024,op0.r.m'length)); op7.r.s <= '0'; op7.r.m <= std_logic_vector(to_unsigned(0,op7.r.m'length));
start <= '1';
wait for 20 ns;
start <= '0';
start2 <= '1';
wait for 20 ns;
start2 <= '0';
wait for 70 ns;
if res0.l.s='0' and res0.l.m= std_logic_vector(to_unsigned(128,op0.r.m'length)) and res0.r.s='1' and res0.r.m= std_logic_vector(to_unsigned(640,op0.r.m'length)) and
res1.l.s='1' and res1.l.m= std_logic_vector(to_unsigned(57,op0.r.m'length)) and res1.r.s='1' and res1.r.m= std_logic_vector(to_unsigned(806,op0.r.m'length)) and
res2.l.s='1' and res2.l.m= std_logic_vector(to_unsigned(362,op0.r.m'length)) and res2.r.s='1' and res2.r.m= std_logic_vector(to_unsigned(904,op0.r.m'length)) and
res3.l.s='1' and res3.l.m= std_logic_vector(to_unsigned(751,op0.r.m'length)) and res3.r.s='1' and res3.r.m= std_logic_vector(to_unsigned(864,op0.r.m'length)) and
res4.l.s='0' and res4.l.m= std_logic_vector(to_unsigned(128,op0.r.m'length)) and res4.r.s='0' and res4.r.m= std_logic_vector(to_unsigned(640,op0.r.m'length)) and
res5.l.s='0' and res5.l.m= std_logic_vector(to_unsigned(529,op0.r.m'length)) and res5.r.s='0' and res5.r.m= std_logic_vector(to_unsigned(612,op0.r.m'length)) and
res6.l.s='0' and res6.l.m= std_logic_vector(to_unsigned(904,op0.r.m'length)) and res6.r.s='0' and res6.r.m= std_logic_vector(to_unsigned(362,op0.r.m'length)) and
res7.l.s='0' and res7.l.m= std_logic_vector(to_unsigned(1141,op0.r.m'length)) and res7.r.s='1' and res7.r.m= std_logic_vector(to_unsigned(82,op0.r.m'length)) then
test := test +1;
else
report "FAILED 1";
end if;
total := total +1;
wait for 50 ns;
-- ===== TEST 2 =====
-- ===== INPUT =====
-- 0.728250001826079 + 1.00391836847305i
-- 0.910846857843460 - 0.659739961761865i
-- -0.658975755475809 - 0.709758034785561i
-- -1.33181094914586 - 0.439874977626711i
-- -0.880887556599902 + 0.167419467753168i
-- -1.48067623408917 + 0.845272067101903i
-- -0.127630875472146 + 0.600136118643648i
-- 0.679817053124255 + 0.906310375643243i
-- 93 + 128 i
-- 116 - 84 i
-- -84 - 90 i
-- -170 - 56 i
-- -112 + 21 i
-- -189 + 108 i
-- -16 + 76 i
-- 87 + 116 i
-- ===== OUTPUT =====
-- 0.89567 + 1.8848 i
-- 1.9366 + 0.086409 i
-- -0.45323 - 0.37002 i
-- -1.1973 - 0.035376 i
-- 0.56083 + 0.12303 i
-- -0.75852 - 2.0026 i
-- -1.4824 + 0.2982 i
-- -0.63481 + 2.1596 i
-- 112 + 240i
-- 244 + 12i
-- -58 - 46i
-- -150 - 4i
-- 72 + 16i
-- -94 - 252i
-- -186 + 38i
-- -78 + 274i
op0.c <= '0'; op0.l.s <= '0'; op0.r.s <= '0';
op0.l.m <= std_logic_vector(to_unsigned(Integer(floor(0.728250001826079*128)),op0.r.m'length)); op0.r.m <= std_logic_vector(to_unsigned(Integer(floor(1.00391836847305*128)),op0.r.m'length));
op1.c <= '0'; op1.l.s <= '0'; op1.r.s <= '1';
op1.l.m <= std_logic_vector(to_unsigned(Integer(floor(0.910846857843460*128)),op1.r.m'length)); op1.r.m <= std_logic_vector(to_unsigned(Integer(floor(0.659739961761865*128)),op1.r.m'length));
op2.c <= '0'; op2.l.s <= '1'; op2.r.s <= '1';
op2.l.m <= std_logic_vector(to_unsigned(Integer(floor(0.658975755475809*128)),op2.r.m'length)); op2.r.m <= std_logic_vector(to_unsigned(Integer(floor(0.709758034785561*128)),op2.r.m'length));
op3.c <= '0'; op3.l.s <= '1'; op3.r.s <= '1';
op3.l.m <= std_logic_vector(to_unsigned(Integer(floor(1.33181094914586*128)),op3.r.m'length)); op3.r.m <= std_logic_vector(to_unsigned(Integer(floor(0.439874977626711*128)),op3.r.m'length));
op4.c <= '0'; op4.l.s <= '1'; op4.r.s <= '0';
op4.l.m <= std_logic_vector(to_unsigned(Integer(floor(0.880887556599902*128)),op4.r.m'length)); op4.r.m <= std_logic_vector(to_unsigned(Integer(floor(0.167419467753168*128)),op4.r.m'length));
op5.c <= '0'; op5.l.s <= '1'; op5.r.s <= '0';
op5.l.m <= std_logic_vector(to_unsigned(Integer(floor(1.48067623408917*128)),op5.r.m'length)); op5.r.m <= std_logic_vector(to_unsigned(Integer(floor(0.845272067101903*128)),op5.r.m'length));
op6.c <= '0'; op6.l.s <= '1'; op6.r.s <= '0';
op6.l.m <= std_logic_vector(to_unsigned(Integer(floor(0.127630875472146*128)),op6.r.m'length)); op6.r.m <= std_logic_vector(to_unsigned(Integer(floor(0.600136118643648*128)),op6.r.m'length));
op7.c <= '0'; op7.l.s <= '0'; op7.r.s <= '0';
op7.l.m <= std_logic_vector(to_unsigned(Integer(floor(0.679817053124255*128)),op7.r.m'length)); op7.r.m <= std_logic_vector(to_unsigned(Integer(floor(0.906310375643243*128)),op7.r.m'length));
start <= '1';
wait for 20 ns;
start <= '0';
start2 <= '1';
wait for 20 ns;
start2 <= '0';
wait for 70 ns;
if res0.l.s='0' and res0.l.m=std_logic_vector(to_unsigned(114, res0.l.m'length)) and res0.r.s='0' and res0.r.m=std_logic_vector(to_unsigned(240, res0.r.m'length)) and
res1.l.s='0' and res1.l.m=std_logic_vector(to_unsigned(246, res1.l.m'length)) and res1.r.s='0' and res1.r.m=std_logic_vector(to_unsigned(12, res1.r.m'length)) and
res2.l.s='1' and res2.l.m=std_logic_vector(to_unsigned(58, res2.l.m'length)) and res2.r.s='1' and res2.r.m=std_logic_vector(to_unsigned(46, res2.r.m'length)) and
res3.l.s='1' and res3.l.m=std_logic_vector(to_unsigned(152, res3.l.m'length)) and res3.r.s='1' and res3.r.m=std_logic_vector(to_unsigned(4, res3.r.m'length)) and
res4.l.s='0' and res4.l.m=std_logic_vector(to_unsigned(72, res4.l.m'length)) and res4.r.s='0' and res4.r.m=std_logic_vector(to_unsigned(16, res4.r.m'length)) and
res5.l.s='1' and res5.l.m=std_logic_vector(to_unsigned(96, res5.l.m'length)) and res5.r.s='1' and res5.r.m=std_logic_vector(to_unsigned(254, res5.r.m'length)) and
res6.l.s='1' and res6.l.m=std_logic_vector(to_unsigned(186, res6.l.m'length)) and res6.r.s='0' and res6.r.m=std_logic_vector(to_unsigned(38, res6.r.m'length)) and
res7.l.s='1' and res7.l.m=std_logic_vector(to_unsigned(80, res7.l.m'length)) and res7.r.s='0' and res7.r.m=std_logic_vector(to_unsigned(276, res7.r.m'length)) then
test := test +1;
else
report "FAILED 2";
end if;
total := total +1;
wait for 50 ns;
-- ========== PRINT RESULTS ==========
report integer'image(test) & "/" & integer'image(total);
wait;
end process;
end TB_BUTTERFLY_8_TW_ARCH;
|
<gh_stars>1-10
--state_machine.vhd
-- Main control block switching data outputs to display driver,
--activates resets and lights up status LED's.
-- made by <NAME> (221339)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity state_machine is
port(
startstop : in std_logic; -- st command from button_int
clk : in std_logic; -- global 100MHz clock
rst : in std_logic; -- rst command from button_int
up_i : in std_logic; -- up command from button_int
down_i : in std_logic; -- down command from button_int
data_1 : in unsigned(15 downto 0); --data from km_cnt
data_2 : in unsigned(15 downto 0); --data from time_cnt
data_3 : in unsigned(15 downto 0); --data from kal_cnt
data_4 : in unsigned(15 downto 0); --data from avg_speed
data_o : inout unsigned(15 downto 0) := (others => '0'); --data to 7seg
mode_o : inout std_logic := '0'; --trip running signal
enable_o : inout std_logic := '0'; --trip pause/stop signal
toggle_o : inout std_logic := '0'; --stopwatch toggle
reset_1 : inout std_logic := '0'; --reset to km_cnt
reset_2 : inout std_logic := '0'; --reset to time_cnt
reset_3 : inout std_logic := '0'; --reset to kal_cnt
reset_4 : inout std_logic := '0'; --global trip reset
dp_o : out std_logic := '0';
dd_o : out std_logic := '0';
LED_1 : inout std_logic := '0'; --display km LED
LED_2 : inout std_logic := '0'; --display time LED
LED_3 : inout std_logic := '0'; --display kals LED
LED_4 : inout std_logic := '0'; --display speed LED
LED_5 : inout std_logic := '0' --display trip running LED
);
end entity state_machine;
architecture Behavioral of state_machine is
--signls for rising edge detection
signal s_up_d : std_logic := '0';
signal s_up_re : std_logic;
signal s_down_d : std_logic := '0';
signal s_down_re : std_logic;
signal s_startstop_d : std_logic := '0';
signal s_startstop_re : std_logic;
signal s_rst_d : std_logic := '0';
signal s_rst_re : std_logic;
--state machine variable
type t_State is (km_cnt, time_cnt, speed_cnt, kal_cnt, trip_ena);
signal State : t_State := km_cnt;
begin
--State switching process
p_switch : process(clk)
begin
if rising_edge(clk)then
--rising_edge conversion for input signals
s_up_d <= up_i;
s_up_re <= not s_up_d and up_i;
s_down_d <= down_i;
s_down_re <= not s_down_d and down_i;
s_startstop_d <= startstop;
s_startstop_re <= not s_startstop_d and startstop;
s_rst_d <= rst;
s_rst_re <= not s_rst_d and rst;
case State is
when km_cnt =>
if --rising_edge(up_i) then
(s_up_re = '1')then
State <= time_cnt; --move to next data to display
elsif --rising_edge(down_i) then
(s_down_re = '1')then
State <= trip_ena; --move to previous data to display
end if;
when time_cnt =>
if --rising_edge(up_i) then
(s_up_re = '1')then
State <= kal_cnt;
elsif --rising_edge(down_i) then
(s_down_re = '1')then
State <= km_cnt;
end if;
when kal_cnt =>
if --rising_edge(up_i) then
(s_up_re = '1')then
State <= speed_cnt;
elsif --rising_edge(down_i) then
(s_down_re = '1')then
State <= time_cnt;
end if;
when speed_cnt =>
if --rising_edge(up_i) then
(s_up_re = '1')then
State <= trip_ena;
elsif --rising_edge(down_i) then
(s_down_re = '1')then
State <= kal_cnt;
end if;
when trip_ena =>
if --rising_edge(up_i) then
(s_up_re = '1')then
State <= km_cnt;
elsif --rising_edge(down_i) then
(s_down_re = '1')then
State <= speed_cnt;
end if;
when others =>
State <= km_cnt;
end case;
end if;
end process p_switch;
--State data output process
p_output : process(clk)
variable temp_trip : std_logic := '0'; --trip status variable
begin
if rising_edge(clk) then
case State is
when km_cnt =>
--turns on status LED, routes correct data and reset
LED_1 <= '1';
LED_2 <= '0';
LED_3 <= '0';
LED_4 <= '0';
LED_4 <= '0';
dp_o <= '1';
dd_o <= '0';
reset_1 <= rst;
data_o <= data_1;
when time_cnt =>
LED_1 <= '0';
LED_2 <= '1';
LED_3 <= '0';
LED_4 <= '0';
dp_o <= '0';
dd_o <= '1';
reset_2 <= rst;
data_o <= data_2;
if --rising_edge(startstop) then
(s_startstop_re = '1')then --starts/pauses timer
toggle_o <= not toggle_o;
end if;
when kal_cnt =>
LED_1 <= '0';
LED_2 <= '0';
LED_3 <= '1';
LED_4 <= '0';
dp_o <= '0';
dd_o <= '0';
reset_3 <= rst;
data_o <= data_3;
when speed_cnt =>
LED_1 <= '0';
LED_2 <= '0';
LED_3 <= '0';
LED_4 <= '1';
dp_o <= '1';
dd_o <= '0';
--avg speed has no reset
data_o <= data_4;
when trip_ena =>
LED_1 <= '0';
LED_2 <= '0';
LED_3 <= '0';
LED_4 <= '0';
dp_o <= '1';
dd_o <= '0';
data_o <= (others => '0'); --blanks the display
if --rising_edge(startstop) then
(s_startstop_re = '1')then --starts/pauses trip
temp_trip := not temp_trip;
LED_5 <= temp_trip; --status LED
toggle_o <= not toggle_o; --start/pause timer
enable_o <= temp_trip; --enable for blocks
mode_o <= '1';
end if;
if --rising_edge(s_rst_re) then
(s_rst_re = '1')then --stops trip
reset_4 <= rst; --resets all trip data on all blocks
temp_trip := '0';
LED_5 <= '0';
enable_o <= '0';
toggle_o <= '0';
mode_o <= '0'; --trip is off
data_o <= (others => '0'); --blanks display
end if;
end case;
end if;
end process p_output;
end architecture Behavioral;
|
<gh_stars>10-100
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use STD.TEXTIO.ALL;
entity testOnlyFile is
end testOnlyFile;
architecture Behavioral of testOnlyFile is
component parallelThree
port(
EI: in std_logic;
inputVec: in std_logic_vector(0 to 7);
EO, GS: out std_logic;
A: out std_logic_vector(2 downto 0)
);
end component;
signal EI: std_logic;
signal inputVec: std_logic_vector(0 to 7);
signal EO, GS: std_logic;
signal A: std_logic_vector(2 downto 0);
signal A0: std_logic;
signal A1: std_logic;
signal A2: std_logic;
signal I0: std_logic;
signal I1: std_logic;
signal I2: std_logic;
signal I3: std_logic;
signal I4: std_logic;
signal I5: std_logic;
signal I6: std_logic;
signal I7: std_logic;
file output : text open read_mode is "output.txt";
file test_input : text open read_mode is "input.txt";
constant passed : string(1 to 6) := "passed";
constant error : string(1 to 5) := "ERROR";
begin
instance_p: parallelThree port map(
EI => EI,
inputVec => inputVec,
EO => EO,
GS => GS,
A => A
);
A0 <= A(0);
A1 <= A(1);
A2 <= A(2);
I0 <= inputVec(0);
I1 <= inputVec(1);
I2 <= inputVec(2);
I3 <= inputVec(3);
I4 <= inputVec(4);
I5 <= inputVec(5);
I6 <= inputVec(6);
I7 <= inputVec(7);
process
variable curr_line, output_line : line;
variable vector_value : std_logic_vector(8 downto 0);
variable output_value : std_logic_vector(4 downto 0);
begin
while not endfile(test_input) loop
--read input variable
readline(test_input, curr_line);
read(curr_line, vector_value);
for i in 0 to 7 loop
inputVec(i) <= vector_value(i);
end loop;
EI <= vector_value(8);
--read output variable
readline(output, output_line);
read(output_line, output_value);
wait for 1 ns;
if (A = output_value(4 downto 2)) and (EO = output_value(1)) and (GS = output_value(0)) then
report passed;
else
report error severity failure;
end if;
end loop;
wait;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 25.06.2020 16:47:11
-- Design Name:
-- Module Name: spi_sram_ctrl - rtl
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: This version merges the SERDES into the spi_sram_ctrl
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity qspi_sram_23lc1024_ctrl is
Generic(
DEBUG_ILAS : boolean := false;
-- SERDES_WORD_SIZE : integer := 8;
DATA_W : integer := 32; -- must be a multiple of SERDES_WORD_SIZE
ADDR_W : integer := 17 -- not reparameterisable, some padding logic depends on this
);
Port (
spi_clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- Pins for 23LC1024
-- NOTE Directions are "from the chips perspective": NOT the FPGA perspective
SCK : out std_logic := '0'; -- clock that goes out to the SRAM chip
CS_N : out std_logic;
SI_SIO0 : inout std_logic;
SO_SIO1 : inout std_logic;
SIO2 : inout std_logic;
HOLD_N_SIO3 : inout std_logic;
cmd_ready_out : out STD_LOGIC;
cmd_valid_in : in STD_LOGIC;
cmd_address_in : in STD_LOGIC_VECTOR(ADDR_W-1 downto 0);
cmd_rw_in : in STD_LOGIC;
cmd_wdata_in : in STD_LOGIC_VECTOR(DATA_W-1 downto 0);
rsp_rdata_out : out STD_LOGIC_VECTOR(DATA_W-1 downto 0);
rsp_ready_in : in STD_LOGIC;
rsp_valid_out : out STD_LOGIC
);
end qspi_sram_23lc1024_ctrl;
architecture rtl of qspi_sram_23lc1024_ctrl is
-- begin read/write by bringing CS_N LOW
-- end read/write by bringing CS_N HIGH
-- READ Sequence
-- select device by bringing CS_N LOW
-- send 8-bit READ instruction
-- send 24-bit address (first 7 MSBs are don't care)
-- data then gets shifted out on the SO pin
-- if in sequential mode, keep clocking with CS_N enabled to continue the read
-- deselect device by bringing CS_N HIGH
-- WRITE Sequence
-- select device by bringing CS_N LOW
-- send 8-bit WRITE instruction
-- send 24-bit address (first 7 MSBs are don't care)
-- send data byte to write
-- (can shift in additional write bytes if in page/sequential mode)
-- Instructions
-- 0000_0011 0x03 READ Read Command
-- 0000_0010 0x02 WRITE Write Command
-- 0011_1011 0x3B EDIO Enter SDI Mode
-- 0011_1000 0x38 EQIO Enter SQI Mode
-- 1111_1111 0xFF RSTIO Reset to SPI Extended Mode
-- 0000_0101 0x05 RDMR Read 'Mode Register'
-- 0000_0001 0x01 WRMR Write 'Mode Register'
-- Mode Register
-- 0000_0000 0x00 BYTE
-- 1000_0000 0x80 PAGE
-- 0100_0000 0x40 SEQUENTIAL (default)
-- 1100_0000 0xC0 Reserved
-- 23LC1024 has an 8-bit instruction register, and never uses full-duplex communication, which makes the controller easier
-- Simplex: one-way communication
-- Half Duplex: two-way communication, only one way at a time (SPI, SDI, SQI)
-- Full Duplex: simultaneous two-way communication (SPI only)
-- 23LC1024 Address is 17-bit byte addressable
-- bytes 0x00000 - 0x1FFFF
-- These are sent as 24-bit addresses, with the first 7 bits as dummmy bits
-- state machine for commands
type t_state is (SRESET, START, RESET_MODE_SPI, DEASSERT_CS_0, SET_MODE_SQI, DEASSERT_CS_1, IDLE, SEND_CMD_ADDR_WDATA, DUMMY, RDATA, DEASSERT_CS);
signal state : t_state := SRESET;
type t_mode is (SPI, SQI);
signal spi_mode : t_mode := SPI;
signal SCK_EN : std_logic := '0';
-- from the IO buffers
signal sqi_pin_direction : std_logic; -- 1 for write, 0 for read
signal io_buf_output_disable : std_logic_vector(3 downto 0); -- T
signal serial_in : std_logic_vector(3 downto 0);
signal serial_out : std_logic_vector(3 downto 0);
-- register commands as they come in
signal cmd_address_reg : std_logic_vector(ADDR_W-1 downto 0);
signal cmd_rw_reg : std_logic;
signal cmd_wdata_reg : std_logic_vector(DATA_W-1 downto 0);
-- we are switching to oversize Data Shifters to make the state machine quicker to construct
-- may separate out CMD and ADDR sending later to make it easier to follow on a waveform
constant SPI_CMD_W : integer := 8; -- 8 bit 23lc1024 command
constant SPI_ADDR_W : integer := 24; -- 3 byte addressing
constant SPI_SHIFT_OUT_W : integer := SPI_CMD_W + SPI_ADDR_W + DATA_W;
constant SPI_CMD_H : integer := 63;
constant SPI_CMD_L : integer := 56;
constant SPI_ADDR_PAD_H : integer := 55;
constant SPI_ADDR_PAD_L : integer := 49;
constant SPI_ADDR_H : integer := 48;
constant SPI_ADDR_L : integer := 32;
constant SPI_WDATA_H : integer := 31;
constant SPI_WDATA_L : integer := 0;
constant SPI_DUMMY_H : integer := 31; -- only need 1 dummy byte but we might as well 0 the rest of the register
constant SPI_DUMMY_L : integer := 0;
-- TODO: allow runtime changing of burst length
signal data_shifter_in : std_logic_vector(DATA_W-1 downto 0); -- Read data, max 1 data word for now
signal data_shifter_out : std_logic_vector(SPI_SHIFT_OUT_W-1 downto 0); -- Command (8), Address (24), Write Data
signal clk_counter : integer; -- counts cycles of SPI transmission
constant SPI_CMD_READ : std_logic_vector(SPI_CMD_W-1 downto 0) := x"03";
constant SPI_CMD_WRITE : std_logic_vector(SPI_CMD_W-1 downto 0) := x"02";
constant SPI_CMD_EDIO : std_logic_vector(SPI_CMD_W-1 downto 0) := x"3B";
constant SPI_CMD_EQIO : std_logic_vector(SPI_CMD_W-1 downto 0) := x"38";
constant SPI_CMD_RSTIO : std_logic_vector(SPI_CMD_W-1 downto 0) := x"FF";
constant SPI_CMD_RDMR : std_logic_vector(SPI_CMD_W-1 downto 0) := x"05";
constant SPI_CMD_WRMR : std_logic_vector(SPI_CMD_W-1 downto 0) := x"01";
constant BYTES_TO_TRANSFER : integer := 4;
attribute MARK_DEBUG : boolean;
attribute MARK_DEBUG of CS_N : signal is DEBUG_ILAS;
attribute MARK_DEBUG of serial_in : signal is DEBUG_ILAS;
attribute MARK_DEBUG of serial_out : signal is DEBUG_ILAS;
attribute MARK_DEBUG of clk_counter : signal is DEBUG_ILAS;
attribute MARK_DEBUG of rsp_rdata_out : signal is DEBUG_ILAS;
attribute MARK_DEBUG of rsp_valid_out : signal is DEBUG_ILAS;
attribute MARK_DEBUG of data_shifter_in : signal is DEBUG_ILAS;
attribute MARK_DEBUG of data_shifter_out : signal is DEBUG_ILAS;
attribute MARK_DEBUG of io_buf_output_disable : signal is DEBUG_ILAS;
attribute MARK_DEBUG of SCK_EN : signal is DEBUG_ILAS;
attribute MARK_DEBUG of cmd_address_reg : signal is DEBUG_ILAS;
attribute MARK_DEBUG of cmd_rw_reg : signal is DEBUG_ILAS;
attribute MARK_DEBUG of cmd_wdata_reg : signal is DEBUG_ILAS;
attribute MARK_DEBUG of state : signal is DEBUG_ILAS;
begin
-- NOTE ABOUT SCK, spi_clk and CS_n
--
-- To make sure CS_n is asserted before the data arrives, the ODDR SCK output inverts the spi_clk to make SCK
-- this has the effect of "delaying" the data clock by half a cycle, so we can set CS and data on the same cycle of spi_clk
-- to make our state machine easier
-- We need to make sure that we keep the CS asserted for one additional cycle beyond our final data bit to prevent it from deasserting too soon
--
-- we send MSB first
-- T is '1' when we use the inout as an input pin, '0' when we are using the inout as an output pin
-- as 'T' disables the output buffer
-- Signal : Direction SPI : Function SPI : Direction SQI : Function SQI
----------------------------------------------------------------------------------------
-- SI_SIO0 : output (T=0) : MOSI : T : MOSI/MISO 0
-- SO_SIO1 : input (T=1) : MISO : T : MOSI/MISO 1
-- SIO2 : output (T=0) : N/A (Keep 0) : T : MOSI/MISO 2
-- SIO3_HOLD_N : output (T=0) : Hold (Keep 1) : T : MOSI/MISO 3
spi_mode_comb_proc : process(all) is
begin
-- defaults to prevent latches
-- data_shifter_in(3 downto 0) <= x"0"; -- this won't work as depending on SPI or SQI
-- serial_out(3 downto 0) <= x"0";
case(spi_mode) is
when SPI =>
io_buf_output_disable <= b"0010"; -- set T
-- TODO: These infer latches when synthesised
serial_out(0) <= data_shifter_out(DATA_W-1+32); -- this goes to MOSI pin SI_SIO0
-- data_shifter_in(0) <= serial_in(1); -- this comes from the MISO pin SO_SIO1
serial_out(1) <= '0'; -- unused, but needed to avoid latch
serial_out(2) <= '0'; -- SIO2, keep '0'
serial_out(3) <= '1'; -- HOLD_N, keep '1'
when SQI =>
io_buf_output_disable <= (others => not sqi_pin_direction); -- set T
serial_out(3 downto 0) <= data_shifter_out(SPI_SHIFT_OUT_W-1 downto SPI_SHIFT_OUT_W-1-3); -- output the top 4 bits of the output data shifter
-- data_shifter_in(3 downto 0) <= serial_in(3 downto 0); -- take the serial_in as the bottom 4 bits of the input data_shifter
end case;
end process spi_mode_comb_proc;
spi_proc : process(spi_clk) is
begin
if rising_edge(spi_clk) then
-- when we reset, the RAM chip won't be reset, so it will remain in whatever state it was in before - so we set all the output pins to '1'
-- and clock out 8 times to make sure we are in a known state
if reset = '1' then
state <= SRESET;
CS_N <= '1'; -- deassert chip select
SCK_EN <= '0'; -- stop SCK
cmd_ready_out <= '0'; -- not ready to receive new command
else
case state is
when SRESET =>
state <= START;
when START =>
-- make sure the RAM chip is in a known state
state <= RESET_MODE_SPI;
sqi_pin_direction <= '1'; -- write
spi_mode <= SQI;
-- assert chip select (half cycle ahead of data)
CS_N <= '0';
SCK_EN <= '1'; -- and start SCK
-- load top 8 bits with command
data_shifter_out(SPI_CMD_H downto SPI_CMD_L) <= SPI_CMD_RSTIO;
-- reset clk_counter
clk_counter <= 0;
when RESET_MODE_SPI =>
-- if we have had 8 cycles out outputting SPI_CMD_RSTIO (FF)
clk_counter <= clk_counter + 1;
if clk_counter = 8-1 then
state <= DEASSERT_CS_0;
-- note: CS_N is half a cycle ahead of this state machine, so deassert it one cycle later to make sure it lines up with our data
CS_N <= '1'; -- 1/2 cycle after data has gone
SCK_EN <= '0'; -- and stop SCK
end if;
when DEASSERT_CS_0 =>
spi_mode <= SPI; -- we are now in SPI mode
-- after that is finished, start sending the next command to move us into Quad mode
if CS_N = '1' then -- deasserted
state <= SET_MODE_SQI;
CS_N <= '0'; -- assert CS_N again
SCK_EN <= '1'; -- and start SCK
-- load top 8 bits with command
data_shifter_out(SPI_CMD_H downto SPI_CMD_L) <= SPI_CMD_EQIO; --0x38
clk_counter <= 0;
end if;
when SET_MODE_SQI =>
-- we know we are in SPI mode, so we need 8 cycles to shift out the whole word into the SRAM
clk_counter <= clk_counter + 1;
data_shifter_out(SPI_SHIFT_OUT_W-1 downto 0) <= data_shifter_out(SPI_SHIFT_OUT_W-2 downto 0) & b"0";
if clk_counter = 8-1 then
state <= DEASSERT_CS_1;
-- note: CS_N is half a cycle ahead, so deassert it one cycle later to make sure it lines up with our data
CS_N <= '1'; -- 1/2 cycle after data has gone
SCK_EN <= '0'; -- and stop SCK
end if;
when DEASSERT_CS_1 =>
spi_mode <= SQI; -- we are now in SQI mode
-- after that is finished, start sending the next command to move us into Quad mode
if CS_N = '1' then -- deasserted
state <= IDLE;
cmd_ready_out <= '1'; -- default ready to receive new command
end if;
when IDLE =>
cmd_ready_out <= '1'; -- default ready to receive new command
if cmd_valid_in = '1' then -- when new command is ready
-- accept command and block further commands being accepted
cmd_ready_out <= '0';
cmd_rw_reg <= cmd_rw_in;
cmd_address_reg <= cmd_address_in;
cmd_wdata_reg <= cmd_wdata_in;
-- start a new transaction (use unregistered cmd as same clock cycle)
state <= SEND_CMD_ADDR_WDATA;
sqi_pin_direction <= '1'; -- write
CS_N <= '0'; -- note: CS_N is half a cycle ahead, so deassert it one cycle later to make sure it lines up with our data
SCK_EN <= '1'; -- and start SCK
clk_counter <= 0;
-- Set up data shifter to write all components out over SQI
if cmd_rw_in = '1' then
-- write
data_shifter_out(SPI_CMD_H downto SPI_CMD_L) <= SPI_CMD_WRITE;
data_shifter_out(SPI_ADDR_PAD_H downto SPI_ADDR_PAD_L) <= (others=>'0');
data_shifter_out(SPI_ADDR_H downto SPI_ADDR_L) <= cmd_address_in;
data_shifter_out(SPI_WDATA_H downto SPI_WDATA_L) <= cmd_wdata_in;
else -- read
data_shifter_out(SPI_CMD_H downto SPI_CMD_L) <= SPI_CMD_READ;
data_shifter_out(SPI_ADDR_PAD_H downto SPI_ADDR_PAD_L) <= (others=>'0');
data_shifter_out(SPI_ADDR_H downto SPI_ADDR_L) <= cmd_address_in;
data_shifter_out(SPI_DUMMY_H downto SPI_DUMMY_L) <= (others => '0');
end if;
end if;
when SEND_CMD_ADDR_WDATA =>
clk_counter <= clk_counter + 1;
-- shift data out 4 bits (SQI)
data_shifter_out(SPI_SHIFT_OUT_W-1 downto 0) <= data_shifter_out(SPI_SHIFT_OUT_W-1-4 downto 0) & b"0000";
if cmd_rw_reg = '1' then -- write
-- we shift out cmd, addr and wdata so there is nothing left to do
if clk_counter = 2+6+BYTES_TO_TRANSFER*2-1 then -- command, address and wdata (8 clocks then 2 clocks per byte as required)
state <= DEASSERT_CS;
CS_N <= '1'; -- 1/2 cycle after data has gone
SCK_EN <= '0'; -- and stop SCK
rsp_valid_out <= '1';
end if;
else -- read
if clk_counter = 2+6+2-1 then -- command, address and dummy byte (10 clocks total)
state <= RDATA;
sqi_pin_direction <= '0'; -- read
clk_counter <= 0; -- reset to send out
end if;
end if;
when DUMMY =>
when RDATA =>
clk_counter <= clk_counter+1;
-- old, relied on latch
-- data_shifter_in(DATA_W-1 downto 4) <= data_shifter_in(DATA_W-1-4 downto 0); -- bottom 4 bits are assigned combinationally to serial_in(3 downto 0) (from SIO3-SIO0)
data_shifter_in(DATA_W-1 downto 0) <= data_shifter_in(DATA_W-1-4 downto 0) & serial_in (3 downto 0);
if clk_counter = BYTES_TO_TRANSFER*2-1 then
state <= DEASSERT_CS;
CS_N <= '1'; -- 1/2 cycle after data has gone
SCK_EN <= '0'; -- and stop SCK
-- old, relied on latch
-- rsp_rdata_out <= data_shifter_in;
rsp_rdata_out <= data_shifter_in(DATA_W-1-4 downto 0) & serial_in (3 downto 0);
rsp_valid_out <= '1';
end if;
when DEASSERT_CS =>
sqi_pin_direction <= '1'; -- write
-- wait for response to be accepted and go back to IDLE ready to receive a new command
--
if rsp_ready_in = '1' then
rsp_valid_out <= '0';
state <= IDLE;
cmd_ready_out <= '1'; -- default ready to receive new command
end if;
when others =>
state <= SRESET;
end case;
end if;
end if;
end process;
-- Output Dual Data Rate Flip Flop to output a clock
clk_output_buffer: ODDR
port map(
Q => SCK, -- output to pin 6 of JA PMOD
C => spi_clk, -- input from clock tree PLL
CE => SCK_EN, -- always enable
D1 => '0', -- invert the clock
D2 => '1' -- invert the clock
);
-- IO Buffers
SIO0_IOBUF : IOBUF
generic map (drive => 12, iostandard => "DEFAULT", slew => "FAST")
port map(
O => serial_in(0), -- buffer output
IO => SI_SIO0, -- buffer inout port (connect directly to top level pin)
I => serial_out(0), -- buffer input
T => io_buf_output_disable(0) -- 3-state enable input - high=input, low=output
);
SIO1_IOBUF : IOBUF
generic map (drive => 12, iostandard => "DEFAULT", slew => "FAST")
port map(
O => serial_in(1), -- buffer output
IO => SO_SIO1, -- buffer inout port (connect directly to top level pin)
I => serial_out(1), -- buffer input
T => io_buf_output_disable(1) -- 3-state enable input - high=input, low=output
);
SIO2_IOBUF : IOBUF
generic map (drive => 12, iostandard => "DEFAULT", slew => "FAST")
port map(
O => serial_in(2), -- buffer output
IO => SIO2, -- buffer inout port (connect directly to top level pin)
I => serial_out(2), -- buffer input
T => io_buf_output_disable(2) -- 3-state enable input - high=input, low=output
);
SIO3_IOBUF : IOBUF
generic map (drive => 12, iostandard => "DEFAULT", slew => "FAST")
port map(
O => serial_in(3), -- buffer output
IO => HOLD_N_SIO3, -- buffer inout port (connect directly to top level pin)
I => serial_out(3), -- buffer input
T => io_buf_output_disable(3) -- 3-state enable input - high=input, low=output
);
end rtl;
|
<filename>src/alu.vhd
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.std_logic_unsigned.all;
entity alu is
port(a, b: in STD_LOGIC_VECTOR(31 downto 0);
alucontrol: in STD_LOGIC_VECTOR(2 downto 0);
result: buffer STD_LOGIC_VECTOR(31 downto 0);
zero: out STD_LOGIC);
end alu ;
architecture arch of alu is
function bool_to_slv(X : boolean)
return STD_LOGIC_VECTOR is
begin
if X then
return (x"00000001");
else
return (x"00000000");
end if;
end bool_to_slv;
begin
with alucontrol select
result <= a + b when "010",
a - b when "110",
a and b when "000",
a or b when "001",
a xor b when "011",
bool_to_slv(a < b) when "111" ,
a when others;
zero<= '1' when result =x"00000000" else '0';
end architecture ;
|
library verilog;
use verilog.vl_types.all;
entity PushBox is
port(
VGA_HS : out vl_logic;
SW : in vl_logic_vector(2 downto 0);
CLOCK_50 : in vl_logic;
VGA_VS : out vl_logic;
HEX0 : out vl_logic_vector(6 downto 0);
KEY : in vl_logic_vector(3 downto 0);
HEX1 : out vl_logic_vector(6 downto 0);
LEDG : out vl_logic_vector(0 downto 0);
VGA_B : out vl_logic_vector(3 downto 0);
VGA_G : out vl_logic_vector(3 downto 0);
VGA_R : out vl_logic_vector(3 downto 0)
);
end PushBox;
|
<reponame>ktobro/uart_bfm_comments
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <<EMAIL>>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_pif_pkg
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package irqc_pif_pkg is
-- Change this to a generic when generic in packages is allowed (VHDL 2008)
constant C_NUM_SOURCES : integer := 8;
-- Notation for regs: (Included in constant name as info to SW)
-- - RW: Readable and writable reg.
-- - RO: Read only reg. (output from IP)
-- - WO: Write only reg. (typically single cycle strobe to IP)
-- Notation for signals (or fields in record) going between PIF and core:
-- Same notations as for register-constants above, but
-- a preceeding 'a' (e.g. awo) means the register is auxiliary to the PIF.
-- This means no flop in the PIF, but in the core. (Or just a dummy-register with no flop)
constant C_ADDR_IRR : integer := 0;
constant C_ADDR_IER : integer := 1;
constant C_ADDR_ITR : integer := 2;
constant C_ADDR_ICR : integer := 3;
constant C_ADDR_IPR : integer := 4;
constant C_ADDR_IRQ2CPU_ENA : integer := 5;
constant C_ADDR_IRQ2CPU_DISABLE : integer := 6;
constant C_ADDR_IRQ2CPU_ALLOWED : integer := 7;
-- Signals from pif to core
type t_p2c is record
rw_ier : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_itr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_icr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_irq2cpu_ena : std_logic;
awt_irq2cpu_disable : std_logic;
end record t_p2c;
-- Signals from core to PIF
type t_c2p is record
aro_irr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
aro_ipr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
aro_irq2cpu_allowed : std_logic;
end record t_c2p;
end package irqc_pif_pkg;
|
--synopsys translate_off
library pcsd_work;
use pcsd_work.all;
library IEEE;
use IEEE.std_logic_1164.all;
entity PCSD is
GENERIC(
CONFIG_FILE : String;
QUAD_MODE : String;
CH0_CDR_SRC : String := "REFCLK_EXT";
CH1_CDR_SRC : String := "REFCLK_EXT";
CH2_CDR_SRC : String := "REFCLK_EXT";
CH3_CDR_SRC : String := "REFCLK_EXT";
PLL_SRC : String
-- CONFIG_FILE : String := "hdmi_pcs.txt";
-- QUAD_MODE : String := "SINGLE";
-- CH0_CDR_SRC : String := "REFCLK_EXT";
-- CH1_CDR_SRC : String := "REFCLK_EXT";
-- CH2_CDR_SRC : String := "REFCLK_EXT";
-- CH3_CDR_SRC : String := "REFCLK_EXT";
-- PLL_SRC : String := "REFCLK_CORE"
);
port (
HDINN0 : in std_logic;
HDINN1 : in std_logic;
HDINN2 : in std_logic;
HDINN3 : in std_logic;
HDINP0 : in std_logic;
HDINP1 : in std_logic;
HDINP2 : in std_logic;
HDINP3 : in std_logic;
REFCLKN : in std_logic;
REFCLKP : in std_logic;
CIN0 : in std_logic;
CIN1 : in std_logic;
CIN2 : in std_logic;
CIN3 : in std_logic;
CIN4 : in std_logic;
CIN5 : in std_logic;
CIN6 : in std_logic;
CIN7 : in std_logic;
CIN8 : in std_logic;
CIN9 : in std_logic;
CIN10 : in std_logic;
CIN11 : in std_logic;
CYAWSTN : in std_logic;
FF_EBRD_CLK_0 : in std_logic;
FF_EBRD_CLK_1 : in std_logic;
FF_EBRD_CLK_2 : in std_logic;
FF_EBRD_CLK_3 : in std_logic;
FF_RXI_CLK_0 : in std_logic;
FF_RXI_CLK_1 : in std_logic;
FF_RXI_CLK_2 : in std_logic;
FF_RXI_CLK_3 : in std_logic;
FF_TX_D_0_0 : in std_logic;
FF_TX_D_0_1 : in std_logic;
FF_TX_D_0_2 : in std_logic;
FF_TX_D_0_3 : in std_logic;
FF_TX_D_0_4 : in std_logic;
FF_TX_D_0_5 : in std_logic;
FF_TX_D_0_6 : in std_logic;
FF_TX_D_0_7 : in std_logic;
FF_TX_D_0_8 : in std_logic;
FF_TX_D_0_9 : in std_logic;
FF_TX_D_0_10 : in std_logic;
FF_TX_D_0_11 : in std_logic;
FF_TX_D_0_12 : in std_logic;
FF_TX_D_0_13 : in std_logic;
FF_TX_D_0_14 : in std_logic;
FF_TX_D_0_15 : in std_logic;
FF_TX_D_0_16 : in std_logic;
FF_TX_D_0_17 : in std_logic;
FF_TX_D_0_18 : in std_logic;
FF_TX_D_0_19 : in std_logic;
FF_TX_D_0_20 : in std_logic;
FF_TX_D_0_21 : in std_logic;
FF_TX_D_0_22 : in std_logic;
FF_TX_D_0_23 : in std_logic;
FF_TX_D_1_0 : in std_logic;
FF_TX_D_1_1 : in std_logic;
FF_TX_D_1_2 : in std_logic;
FF_TX_D_1_3 : in std_logic;
FF_TX_D_1_4 : in std_logic;
FF_TX_D_1_5 : in std_logic;
FF_TX_D_1_6 : in std_logic;
FF_TX_D_1_7 : in std_logic;
FF_TX_D_1_8 : in std_logic;
FF_TX_D_1_9 : in std_logic;
FF_TX_D_1_10 : in std_logic;
FF_TX_D_1_11 : in std_logic;
FF_TX_D_1_12 : in std_logic;
FF_TX_D_1_13 : in std_logic;
FF_TX_D_1_14 : in std_logic;
FF_TX_D_1_15 : in std_logic;
FF_TX_D_1_16 : in std_logic;
FF_TX_D_1_17 : in std_logic;
FF_TX_D_1_18 : in std_logic;
FF_TX_D_1_19 : in std_logic;
FF_TX_D_1_20 : in std_logic;
FF_TX_D_1_21 : in std_logic;
FF_TX_D_1_22 : in std_logic;
FF_TX_D_1_23 : in std_logic;
FF_TX_D_2_0 : in std_logic;
FF_TX_D_2_1 : in std_logic;
FF_TX_D_2_2 : in std_logic;
FF_TX_D_2_3 : in std_logic;
FF_TX_D_2_4 : in std_logic;
FF_TX_D_2_5 : in std_logic;
FF_TX_D_2_6 : in std_logic;
FF_TX_D_2_7 : in std_logic;
FF_TX_D_2_8 : in std_logic;
FF_TX_D_2_9 : in std_logic;
FF_TX_D_2_10 : in std_logic;
FF_TX_D_2_11 : in std_logic;
FF_TX_D_2_12 : in std_logic;
FF_TX_D_2_13 : in std_logic;
FF_TX_D_2_14 : in std_logic;
FF_TX_D_2_15 : in std_logic;
FF_TX_D_2_16 : in std_logic;
FF_TX_D_2_17 : in std_logic;
FF_TX_D_2_18 : in std_logic;
FF_TX_D_2_19 : in std_logic;
FF_TX_D_2_20 : in std_logic;
FF_TX_D_2_21 : in std_logic;
FF_TX_D_2_22 : in std_logic;
FF_TX_D_2_23 : in std_logic;
FF_TX_D_3_0 : in std_logic;
FF_TX_D_3_1 : in std_logic;
FF_TX_D_3_2 : in std_logic;
FF_TX_D_3_3 : in std_logic;
FF_TX_D_3_4 : in std_logic;
FF_TX_D_3_5 : in std_logic;
FF_TX_D_3_6 : in std_logic;
FF_TX_D_3_7 : in std_logic;
FF_TX_D_3_8 : in std_logic;
FF_TX_D_3_9 : in std_logic;
FF_TX_D_3_10 : in std_logic;
FF_TX_D_3_11 : in std_logic;
FF_TX_D_3_12 : in std_logic;
FF_TX_D_3_13 : in std_logic;
FF_TX_D_3_14 : in std_logic;
FF_TX_D_3_15 : in std_logic;
FF_TX_D_3_16 : in std_logic;
FF_TX_D_3_17 : in std_logic;
FF_TX_D_3_18 : in std_logic;
FF_TX_D_3_19 : in std_logic;
FF_TX_D_3_20 : in std_logic;
FF_TX_D_3_21 : in std_logic;
FF_TX_D_3_22 : in std_logic;
FF_TX_D_3_23 : in std_logic;
FF_TXI_CLK_0 : in std_logic;
FF_TXI_CLK_1 : in std_logic;
FF_TXI_CLK_2 : in std_logic;
FF_TXI_CLK_3 : in std_logic;
FFC_CK_CORE_RX_0 : in std_logic;
FFC_CK_CORE_RX_1 : in std_logic;
FFC_CK_CORE_RX_2 : in std_logic;
FFC_CK_CORE_RX_3 : in std_logic;
FFC_CK_CORE_TX : in std_logic;
FFC_EI_EN_0 : in std_logic;
FFC_EI_EN_1 : in std_logic;
FFC_EI_EN_2 : in std_logic;
FFC_EI_EN_3 : in std_logic;
FFC_ENABLE_CGALIGN_0 : in std_logic;
FFC_ENABLE_CGALIGN_1 : in std_logic;
FFC_ENABLE_CGALIGN_2 : in std_logic;
FFC_ENABLE_CGALIGN_3 : in std_logic;
FFC_FB_LOOPBACK_0 : in std_logic;
FFC_FB_LOOPBACK_1 : in std_logic;
FFC_FB_LOOPBACK_2 : in std_logic;
FFC_FB_LOOPBACK_3 : in std_logic;
FFC_LANE_RX_RST_0 : in std_logic;
FFC_LANE_RX_RST_1 : in std_logic;
FFC_LANE_RX_RST_2 : in std_logic;
FFC_LANE_RX_RST_3 : in std_logic;
FFC_LANE_TX_RST_0 : in std_logic;
FFC_LANE_TX_RST_1 : in std_logic;
FFC_LANE_TX_RST_2 : in std_logic;
FFC_LANE_TX_RST_3 : in std_logic;
FFC_MACRO_RST : in std_logic;
FFC_PCI_DET_EN_0 : in std_logic;
FFC_PCI_DET_EN_1 : in std_logic;
FFC_PCI_DET_EN_2 : in std_logic;
FFC_PCI_DET_EN_3 : in std_logic;
FFC_PCIE_CT_0 : in std_logic;
FFC_PCIE_CT_1 : in std_logic;
FFC_PCIE_CT_2 : in std_logic;
FFC_PCIE_CT_3 : in std_logic;
FFC_PFIFO_CLR_0 : in std_logic;
FFC_PFIFO_CLR_1 : in std_logic;
FFC_PFIFO_CLR_2 : in std_logic;
FFC_PFIFO_CLR_3 : in std_logic;
FFC_QUAD_RST : in std_logic;
FFC_RRST_0 : in std_logic;
FFC_RRST_1 : in std_logic;
FFC_RRST_2 : in std_logic;
FFC_RRST_3 : in std_logic;
FFC_RXPWDNB_0 : in std_logic;
FFC_RXPWDNB_1 : in std_logic;
FFC_RXPWDNB_2 : in std_logic;
FFC_RXPWDNB_3 : in std_logic;
FFC_SB_INV_RX_0 : in std_logic;
FFC_SB_INV_RX_1 : in std_logic;
FFC_SB_INV_RX_2 : in std_logic;
FFC_SB_INV_RX_3 : in std_logic;
FFC_SB_PFIFO_LP_0 : in std_logic;
FFC_SB_PFIFO_LP_1 : in std_logic;
FFC_SB_PFIFO_LP_2 : in std_logic;
FFC_SB_PFIFO_LP_3 : in std_logic;
FFC_SIGNAL_DETECT_0 : in std_logic;
FFC_SIGNAL_DETECT_1 : in std_logic;
FFC_SIGNAL_DETECT_2 : in std_logic;
FFC_SIGNAL_DETECT_3 : in std_logic;
FFC_SYNC_TOGGLE : in std_logic;
FFC_TRST : in std_logic;
FFC_TXPWDNB_0 : in std_logic;
FFC_TXPWDNB_1 : in std_logic;
FFC_TXPWDNB_2 : in std_logic;
FFC_TXPWDNB_3 : in std_logic;
FFC_RATE_MODE_RX_0 : in std_logic;
FFC_RATE_MODE_RX_1 : in std_logic;
FFC_RATE_MODE_RX_2 : in std_logic;
FFC_RATE_MODE_RX_3 : in std_logic;
FFC_RATE_MODE_TX_0 : in std_logic;
FFC_RATE_MODE_TX_1 : in std_logic;
FFC_RATE_MODE_TX_2 : in std_logic;
FFC_RATE_MODE_TX_3 : in std_logic;
FFC_DIV11_MODE_RX_0 : in std_logic;
FFC_DIV11_MODE_RX_1 : in std_logic;
FFC_DIV11_MODE_RX_2 : in std_logic;
FFC_DIV11_MODE_RX_3 : in std_logic;
FFC_DIV11_MODE_TX_0 : in std_logic;
FFC_DIV11_MODE_TX_1 : in std_logic;
FFC_DIV11_MODE_TX_2 : in std_logic;
FFC_DIV11_MODE_TX_3 : in std_logic;
LDR_CORE2TX_0 : in std_logic;
LDR_CORE2TX_1 : in std_logic;
LDR_CORE2TX_2 : in std_logic;
LDR_CORE2TX_3 : in std_logic;
FFC_LDR_CORE2TX_EN_0 : in std_logic;
FFC_LDR_CORE2TX_EN_1 : in std_logic;
FFC_LDR_CORE2TX_EN_2 : in std_logic;
FFC_LDR_CORE2TX_EN_3 : in std_logic;
PCIE_POWERDOWN_0_0 : in std_logic;
PCIE_POWERDOWN_0_1 : in std_logic;
PCIE_POWERDOWN_1_0 : in std_logic;
PCIE_POWERDOWN_1_1 : in std_logic;
PCIE_POWERDOWN_2_0 : in std_logic;
PCIE_POWERDOWN_2_1 : in std_logic;
PCIE_POWERDOWN_3_0 : in std_logic;
PCIE_POWERDOWN_3_1 : in std_logic;
PCIE_RXPOLARITY_0 : in std_logic;
PCIE_RXPOLARITY_1 : in std_logic;
PCIE_RXPOLARITY_2 : in std_logic;
PCIE_RXPOLARITY_3 : in std_logic;
PCIE_TXCOMPLIANCE_0 : in std_logic;
PCIE_TXCOMPLIANCE_1 : in std_logic;
PCIE_TXCOMPLIANCE_2 : in std_logic;
PCIE_TXCOMPLIANCE_3 : in std_logic;
PCIE_TXDETRX_PR2TLB_0 : in std_logic;
PCIE_TXDETRX_PR2TLB_1 : in std_logic;
PCIE_TXDETRX_PR2TLB_2 : in std_logic;
PCIE_TXDETRX_PR2TLB_3 : in std_logic;
SCIADDR0 : in std_logic;
SCIADDR1 : in std_logic;
SCIADDR2 : in std_logic;
SCIADDR3 : in std_logic;
SCIADDR4 : in std_logic;
SCIADDR5 : in std_logic;
SCIENAUX : in std_logic;
SCIENCH0 : in std_logic;
SCIENCH1 : in std_logic;
SCIENCH2 : in std_logic;
SCIENCH3 : in std_logic;
SCIRD : in std_logic;
SCISELAUX : in std_logic;
SCISELCH0 : in std_logic;
SCISELCH1 : in std_logic;
SCISELCH2 : in std_logic;
SCISELCH3 : in std_logic;
SCIWDATA0 : in std_logic;
SCIWDATA1 : in std_logic;
SCIWDATA2 : in std_logic;
SCIWDATA3 : in std_logic;
SCIWDATA4 : in std_logic;
SCIWDATA5 : in std_logic;
SCIWDATA6 : in std_logic;
SCIWDATA7 : in std_logic;
SCIWSTN : in std_logic;
REFCLK_FROM_NQ : in std_logic;
HDOUTN0 : out std_logic;
HDOUTN1 : out std_logic;
HDOUTN2 : out std_logic;
HDOUTN3 : out std_logic;
HDOUTP0 : out std_logic;
HDOUTP1 : out std_logic;
HDOUTP2 : out std_logic;
HDOUTP3 : out std_logic;
COUT0 : out std_logic;
COUT1 : out std_logic;
COUT2 : out std_logic;
COUT3 : out std_logic;
COUT4 : out std_logic;
COUT5 : out std_logic;
COUT6 : out std_logic;
COUT7 : out std_logic;
COUT8 : out std_logic;
COUT9 : out std_logic;
COUT10 : out std_logic;
COUT11 : out std_logic;
COUT12 : out std_logic;
COUT13 : out std_logic;
COUT14 : out std_logic;
COUT15 : out std_logic;
COUT16 : out std_logic;
COUT17 : out std_logic;
COUT18 : out std_logic;
COUT19 : out std_logic;
FF_RX_D_0_0 : out std_logic;
FF_RX_D_0_1 : out std_logic;
FF_RX_D_0_2 : out std_logic;
FF_RX_D_0_3 : out std_logic;
FF_RX_D_0_4 : out std_logic;
FF_RX_D_0_5 : out std_logic;
FF_RX_D_0_6 : out std_logic;
FF_RX_D_0_7 : out std_logic;
FF_RX_D_0_8 : out std_logic;
FF_RX_D_0_9 : out std_logic;
FF_RX_D_0_10 : out std_logic;
FF_RX_D_0_11 : out std_logic;
FF_RX_D_0_12 : out std_logic;
FF_RX_D_0_13 : out std_logic;
FF_RX_D_0_14 : out std_logic;
FF_RX_D_0_15 : out std_logic;
FF_RX_D_0_16 : out std_logic;
FF_RX_D_0_17 : out std_logic;
FF_RX_D_0_18 : out std_logic;
FF_RX_D_0_19 : out std_logic;
FF_RX_D_0_20 : out std_logic;
FF_RX_D_0_21 : out std_logic;
FF_RX_D_0_22 : out std_logic;
FF_RX_D_0_23 : out std_logic;
FF_RX_D_1_0 : out std_logic;
FF_RX_D_1_1 : out std_logic;
FF_RX_D_1_2 : out std_logic;
FF_RX_D_1_3 : out std_logic;
FF_RX_D_1_4 : out std_logic;
FF_RX_D_1_5 : out std_logic;
FF_RX_D_1_6 : out std_logic;
FF_RX_D_1_7 : out std_logic;
FF_RX_D_1_8 : out std_logic;
FF_RX_D_1_9 : out std_logic;
FF_RX_D_1_10 : out std_logic;
FF_RX_D_1_11 : out std_logic;
FF_RX_D_1_12 : out std_logic;
FF_RX_D_1_13 : out std_logic;
FF_RX_D_1_14 : out std_logic;
FF_RX_D_1_15 : out std_logic;
FF_RX_D_1_16 : out std_logic;
FF_RX_D_1_17 : out std_logic;
FF_RX_D_1_18 : out std_logic;
FF_RX_D_1_19 : out std_logic;
FF_RX_D_1_20 : out std_logic;
FF_RX_D_1_21 : out std_logic;
FF_RX_D_1_22 : out std_logic;
FF_RX_D_1_23 : out std_logic;
FF_RX_D_2_0 : out std_logic;
FF_RX_D_2_1 : out std_logic;
FF_RX_D_2_2 : out std_logic;
FF_RX_D_2_3 : out std_logic;
FF_RX_D_2_4 : out std_logic;
FF_RX_D_2_5 : out std_logic;
FF_RX_D_2_6 : out std_logic;
FF_RX_D_2_7 : out std_logic;
FF_RX_D_2_8 : out std_logic;
FF_RX_D_2_9 : out std_logic;
FF_RX_D_2_10 : out std_logic;
FF_RX_D_2_11 : out std_logic;
FF_RX_D_2_12 : out std_logic;
FF_RX_D_2_13 : out std_logic;
FF_RX_D_2_14 : out std_logic;
FF_RX_D_2_15 : out std_logic;
FF_RX_D_2_16 : out std_logic;
FF_RX_D_2_17 : out std_logic;
FF_RX_D_2_18 : out std_logic;
FF_RX_D_2_19 : out std_logic;
FF_RX_D_2_20 : out std_logic;
FF_RX_D_2_21 : out std_logic;
FF_RX_D_2_22 : out std_logic;
FF_RX_D_2_23 : out std_logic;
FF_RX_D_3_0 : out std_logic;
FF_RX_D_3_1 : out std_logic;
FF_RX_D_3_2 : out std_logic;
FF_RX_D_3_3 : out std_logic;
FF_RX_D_3_4 : out std_logic;
FF_RX_D_3_5 : out std_logic;
FF_RX_D_3_6 : out std_logic;
FF_RX_D_3_7 : out std_logic;
FF_RX_D_3_8 : out std_logic;
FF_RX_D_3_9 : out std_logic;
FF_RX_D_3_10 : out std_logic;
FF_RX_D_3_11 : out std_logic;
FF_RX_D_3_12 : out std_logic;
FF_RX_D_3_13 : out std_logic;
FF_RX_D_3_14 : out std_logic;
FF_RX_D_3_15 : out std_logic;
FF_RX_D_3_16 : out std_logic;
FF_RX_D_3_17 : out std_logic;
FF_RX_D_3_18 : out std_logic;
FF_RX_D_3_19 : out std_logic;
FF_RX_D_3_20 : out std_logic;
FF_RX_D_3_21 : out std_logic;
FF_RX_D_3_22 : out std_logic;
FF_RX_D_3_23 : out std_logic;
FF_RX_F_CLK_0 : out std_logic;
FF_RX_F_CLK_1 : out std_logic;
FF_RX_F_CLK_2 : out std_logic;
FF_RX_F_CLK_3 : out std_logic;
FF_RX_H_CLK_0 : out std_logic;
FF_RX_H_CLK_1 : out std_logic;
FF_RX_H_CLK_2 : out std_logic;
FF_RX_H_CLK_3 : out std_logic;
FF_TX_F_CLK_0 : out std_logic;
FF_TX_F_CLK_1 : out std_logic;
FF_TX_F_CLK_2 : out std_logic;
FF_TX_F_CLK_3 : out std_logic;
FF_TX_H_CLK_0 : out std_logic;
FF_TX_H_CLK_1 : out std_logic;
FF_TX_H_CLK_2 : out std_logic;
FF_TX_H_CLK_3 : out std_logic;
FFS_CC_OVERRUN_0 : out std_logic;
FFS_CC_OVERRUN_1 : out std_logic;
FFS_CC_OVERRUN_2 : out std_logic;
FFS_CC_OVERRUN_3 : out std_logic;
FFS_CC_UNDERRUN_0 : out std_logic;
FFS_CC_UNDERRUN_1 : out std_logic;
FFS_CC_UNDERRUN_2 : out std_logic;
FFS_CC_UNDERRUN_3 : out std_logic;
FFS_LS_SYNC_STATUS_0 : out std_logic;
FFS_LS_SYNC_STATUS_1 : out std_logic;
FFS_LS_SYNC_STATUS_2 : out std_logic;
FFS_LS_SYNC_STATUS_3 : out std_logic;
FFS_CDR_TRAIN_DONE_0 : out std_logic;
FFS_CDR_TRAIN_DONE_1 : out std_logic;
FFS_CDR_TRAIN_DONE_2 : out std_logic;
FFS_CDR_TRAIN_DONE_3 : out std_logic;
FFS_PCIE_CON_0 : out std_logic;
FFS_PCIE_CON_1 : out std_logic;
FFS_PCIE_CON_2 : out std_logic;
FFS_PCIE_CON_3 : out std_logic;
FFS_PCIE_DONE_0 : out std_logic;
FFS_PCIE_DONE_1 : out std_logic;
FFS_PCIE_DONE_2 : out std_logic;
FFS_PCIE_DONE_3 : out std_logic;
FFS_PLOL : out std_logic;
FFS_RLOL_0 : out std_logic;
FFS_RLOL_1 : out std_logic;
FFS_RLOL_2 : out std_logic;
FFS_RLOL_3 : out std_logic;
FFS_RLOS_HI_0 : out std_logic;
FFS_RLOS_HI_1 : out std_logic;
FFS_RLOS_HI_2 : out std_logic;
FFS_RLOS_HI_3 : out std_logic;
FFS_RLOS_LO_0 : out std_logic;
FFS_RLOS_LO_1 : out std_logic;
FFS_RLOS_LO_2 : out std_logic;
FFS_RLOS_LO_3 : out std_logic;
FFS_RXFBFIFO_ERROR_0 : out std_logic;
FFS_RXFBFIFO_ERROR_1 : out std_logic;
FFS_RXFBFIFO_ERROR_2 : out std_logic;
FFS_RXFBFIFO_ERROR_3 : out std_logic;
FFS_TXFBFIFO_ERROR_0 : out std_logic;
FFS_TXFBFIFO_ERROR_1 : out std_logic;
FFS_TXFBFIFO_ERROR_2 : out std_logic;
FFS_TXFBFIFO_ERROR_3 : out std_logic;
PCIE_PHYSTATUS_0 : out std_logic;
PCIE_PHYSTATUS_1 : out std_logic;
PCIE_PHYSTATUS_2 : out std_logic;
PCIE_PHYSTATUS_3 : out std_logic;
PCIE_RXVALID_0 : out std_logic;
PCIE_RXVALID_1 : out std_logic;
PCIE_RXVALID_2 : out std_logic;
PCIE_RXVALID_3 : out std_logic;
FFS_SKP_ADDED_0 : out std_logic;
FFS_SKP_ADDED_1 : out std_logic;
FFS_SKP_ADDED_2 : out std_logic;
FFS_SKP_ADDED_3 : out std_logic;
FFS_SKP_DELETED_0 : out std_logic;
FFS_SKP_DELETED_1 : out std_logic;
FFS_SKP_DELETED_2 : out std_logic;
FFS_SKP_DELETED_3 : out std_logic;
LDR_RX2CORE_0 : out std_logic;
LDR_RX2CORE_1 : out std_logic;
LDR_RX2CORE_2 : out std_logic;
LDR_RX2CORE_3 : out std_logic;
REFCK2CORE : out std_logic;
SCIINT : out std_logic;
SCIRDATA0 : out std_logic;
SCIRDATA1 : out std_logic;
SCIRDATA2 : out std_logic;
SCIRDATA3 : out std_logic;
SCIRDATA4 : out std_logic;
SCIRDATA5 : out std_logic;
SCIRDATA6 : out std_logic;
SCIRDATA7 : out std_logic;
REFCLK_TO_NQ : out std_logic
);
end PCSD;
architecture PCSD_arch of PCSD is
component PCSD_sim
GENERIC(
CONFIG_FILE : String;
QUAD_MODE : String;
CH0_CDR_SRC : String;
CH1_CDR_SRC : String;
CH2_CDR_SRC : String;
CH3_CDR_SRC : String;
PLL_SRC : String
);
port (
HDINN0 : in std_logic;
HDINN1 : in std_logic;
HDINN2 : in std_logic;
HDINN3 : in std_logic;
HDINP0 : in std_logic;
HDINP1 : in std_logic;
HDINP2 : in std_logic;
HDINP3 : in std_logic;
REFCLKN : in std_logic;
REFCLKP : in std_logic;
CIN0 : in std_logic;
CIN1 : in std_logic;
CIN2 : in std_logic;
CIN3 : in std_logic;
CIN4 : in std_logic;
CIN5 : in std_logic;
CIN6 : in std_logic;
CIN7 : in std_logic;
CIN8 : in std_logic;
CIN9 : in std_logic;
CIN10 : in std_logic;
CIN11 : in std_logic;
CYAWSTN : in std_logic;
FF_EBRD_CLK_0 : in std_logic;
FF_EBRD_CLK_1 : in std_logic;
FF_EBRD_CLK_2 : in std_logic;
FF_EBRD_CLK_3 : in std_logic;
FF_RXI_CLK_0 : in std_logic;
FF_RXI_CLK_1 : in std_logic;
FF_RXI_CLK_2 : in std_logic;
FF_RXI_CLK_3 : in std_logic;
FF_TX_D_0_0 : in std_logic;
FF_TX_D_0_1 : in std_logic;
FF_TX_D_0_2 : in std_logic;
FF_TX_D_0_3 : in std_logic;
FF_TX_D_0_4 : in std_logic;
FF_TX_D_0_5 : in std_logic;
FF_TX_D_0_6 : in std_logic;
FF_TX_D_0_7 : in std_logic;
FF_TX_D_0_8 : in std_logic;
FF_TX_D_0_9 : in std_logic;
FF_TX_D_0_10 : in std_logic;
FF_TX_D_0_11 : in std_logic;
FF_TX_D_0_12 : in std_logic;
FF_TX_D_0_13 : in std_logic;
FF_TX_D_0_14 : in std_logic;
FF_TX_D_0_15 : in std_logic;
FF_TX_D_0_16 : in std_logic;
FF_TX_D_0_17 : in std_logic;
FF_TX_D_0_18 : in std_logic;
FF_TX_D_0_19 : in std_logic;
FF_TX_D_0_20 : in std_logic;
FF_TX_D_0_21 : in std_logic;
FF_TX_D_0_22 : in std_logic;
FF_TX_D_0_23 : in std_logic;
FF_TX_D_1_0 : in std_logic;
FF_TX_D_1_1 : in std_logic;
FF_TX_D_1_2 : in std_logic;
FF_TX_D_1_3 : in std_logic;
FF_TX_D_1_4 : in std_logic;
FF_TX_D_1_5 : in std_logic;
FF_TX_D_1_6 : in std_logic;
FF_TX_D_1_7 : in std_logic;
FF_TX_D_1_8 : in std_logic;
FF_TX_D_1_9 : in std_logic;
FF_TX_D_1_10 : in std_logic;
FF_TX_D_1_11 : in std_logic;
FF_TX_D_1_12 : in std_logic;
FF_TX_D_1_13 : in std_logic;
FF_TX_D_1_14 : in std_logic;
FF_TX_D_1_15 : in std_logic;
FF_TX_D_1_16 : in std_logic;
FF_TX_D_1_17 : in std_logic;
FF_TX_D_1_18 : in std_logic;
FF_TX_D_1_19 : in std_logic;
FF_TX_D_1_20 : in std_logic;
FF_TX_D_1_21 : in std_logic;
FF_TX_D_1_22 : in std_logic;
FF_TX_D_1_23 : in std_logic;
FF_TX_D_2_0 : in std_logic;
FF_TX_D_2_1 : in std_logic;
FF_TX_D_2_2 : in std_logic;
FF_TX_D_2_3 : in std_logic;
FF_TX_D_2_4 : in std_logic;
FF_TX_D_2_5 : in std_logic;
FF_TX_D_2_6 : in std_logic;
FF_TX_D_2_7 : in std_logic;
FF_TX_D_2_8 : in std_logic;
FF_TX_D_2_9 : in std_logic;
FF_TX_D_2_10 : in std_logic;
FF_TX_D_2_11 : in std_logic;
FF_TX_D_2_12 : in std_logic;
FF_TX_D_2_13 : in std_logic;
FF_TX_D_2_14 : in std_logic;
FF_TX_D_2_15 : in std_logic;
FF_TX_D_2_16 : in std_logic;
FF_TX_D_2_17 : in std_logic;
FF_TX_D_2_18 : in std_logic;
FF_TX_D_2_19 : in std_logic;
FF_TX_D_2_20 : in std_logic;
FF_TX_D_2_21 : in std_logic;
FF_TX_D_2_22 : in std_logic;
FF_TX_D_2_23 : in std_logic;
FF_TX_D_3_0 : in std_logic;
FF_TX_D_3_1 : in std_logic;
FF_TX_D_3_2 : in std_logic;
FF_TX_D_3_3 : in std_logic;
FF_TX_D_3_4 : in std_logic;
FF_TX_D_3_5 : in std_logic;
FF_TX_D_3_6 : in std_logic;
FF_TX_D_3_7 : in std_logic;
FF_TX_D_3_8 : in std_logic;
FF_TX_D_3_9 : in std_logic;
FF_TX_D_3_10 : in std_logic;
FF_TX_D_3_11 : in std_logic;
FF_TX_D_3_12 : in std_logic;
FF_TX_D_3_13 : in std_logic;
FF_TX_D_3_14 : in std_logic;
FF_TX_D_3_15 : in std_logic;
FF_TX_D_3_16 : in std_logic;
FF_TX_D_3_17 : in std_logic;
FF_TX_D_3_18 : in std_logic;
FF_TX_D_3_19 : in std_logic;
FF_TX_D_3_20 : in std_logic;
FF_TX_D_3_21 : in std_logic;
FF_TX_D_3_22 : in std_logic;
FF_TX_D_3_23 : in std_logic;
FF_TXI_CLK_0 : in std_logic;
FF_TXI_CLK_1 : in std_logic;
FF_TXI_CLK_2 : in std_logic;
FF_TXI_CLK_3 : in std_logic;
FFC_CK_CORE_RX_0 : in std_logic;
FFC_CK_CORE_RX_1 : in std_logic;
FFC_CK_CORE_RX_2 : in std_logic;
FFC_CK_CORE_RX_3 : in std_logic;
FFC_CK_CORE_TX : in std_logic;
FFC_EI_EN_0 : in std_logic;
FFC_EI_EN_1 : in std_logic;
FFC_EI_EN_2 : in std_logic;
FFC_EI_EN_3 : in std_logic;
FFC_ENABLE_CGALIGN_0 : in std_logic;
FFC_ENABLE_CGALIGN_1 : in std_logic;
FFC_ENABLE_CGALIGN_2 : in std_logic;
FFC_ENABLE_CGALIGN_3 : in std_logic;
FFC_FB_LOOPBACK_0 : in std_logic;
FFC_FB_LOOPBACK_1 : in std_logic;
FFC_FB_LOOPBACK_2 : in std_logic;
FFC_FB_LOOPBACK_3 : in std_logic;
FFC_LANE_RX_RST_0 : in std_logic;
FFC_LANE_RX_RST_1 : in std_logic;
FFC_LANE_RX_RST_2 : in std_logic;
FFC_LANE_RX_RST_3 : in std_logic;
FFC_LANE_TX_RST_0 : in std_logic;
FFC_LANE_TX_RST_1 : in std_logic;
FFC_LANE_TX_RST_2 : in std_logic;
FFC_LANE_TX_RST_3 : in std_logic;
FFC_MACRO_RST : in std_logic;
FFC_PCI_DET_EN_0 : in std_logic;
FFC_PCI_DET_EN_1 : in std_logic;
FFC_PCI_DET_EN_2 : in std_logic;
FFC_PCI_DET_EN_3 : in std_logic;
FFC_PCIE_CT_0 : in std_logic;
FFC_PCIE_CT_1 : in std_logic;
FFC_PCIE_CT_2 : in std_logic;
FFC_PCIE_CT_3 : in std_logic;
FFC_PFIFO_CLR_0 : in std_logic;
FFC_PFIFO_CLR_1 : in std_logic;
FFC_PFIFO_CLR_2 : in std_logic;
FFC_PFIFO_CLR_3 : in std_logic;
FFC_QUAD_RST : in std_logic;
FFC_RRST_0 : in std_logic;
FFC_RRST_1 : in std_logic;
FFC_RRST_2 : in std_logic;
FFC_RRST_3 : in std_logic;
FFC_RXPWDNB_0 : in std_logic;
FFC_RXPWDNB_1 : in std_logic;
FFC_RXPWDNB_2 : in std_logic;
FFC_RXPWDNB_3 : in std_logic;
FFC_SB_INV_RX_0 : in std_logic;
FFC_SB_INV_RX_1 : in std_logic;
FFC_SB_INV_RX_2 : in std_logic;
FFC_SB_INV_RX_3 : in std_logic;
FFC_SB_PFIFO_LP_0 : in std_logic;
FFC_SB_PFIFO_LP_1 : in std_logic;
FFC_SB_PFIFO_LP_2 : in std_logic;
FFC_SB_PFIFO_LP_3 : in std_logic;
FFC_SIGNAL_DETECT_0 : in std_logic;
FFC_SIGNAL_DETECT_1 : in std_logic;
FFC_SIGNAL_DETECT_2 : in std_logic;
FFC_SIGNAL_DETECT_3 : in std_logic;
FFC_SYNC_TOGGLE : in std_logic;
FFC_TRST : in std_logic;
FFC_TXPWDNB_0 : in std_logic;
FFC_TXPWDNB_1 : in std_logic;
FFC_TXPWDNB_2 : in std_logic;
FFC_TXPWDNB_3 : in std_logic;
FFC_RATE_MODE_RX_0 : in std_logic;
FFC_RATE_MODE_RX_1 : in std_logic;
FFC_RATE_MODE_RX_2 : in std_logic;
FFC_RATE_MODE_RX_3 : in std_logic;
FFC_RATE_MODE_TX_0 : in std_logic;
FFC_RATE_MODE_TX_1 : in std_logic;
FFC_RATE_MODE_TX_2 : in std_logic;
FFC_RATE_MODE_TX_3 : in std_logic;
FFC_DIV11_MODE_RX_0 : in std_logic;
FFC_DIV11_MODE_RX_1 : in std_logic;
FFC_DIV11_MODE_RX_2 : in std_logic;
FFC_DIV11_MODE_RX_3 : in std_logic;
FFC_DIV11_MODE_TX_0 : in std_logic;
FFC_DIV11_MODE_TX_1 : in std_logic;
FFC_DIV11_MODE_TX_2 : in std_logic;
FFC_DIV11_MODE_TX_3 : in std_logic;
LDR_CORE2TX_0 : in std_logic;
LDR_CORE2TX_1 : in std_logic;
LDR_CORE2TX_2 : in std_logic;
LDR_CORE2TX_3 : in std_logic;
FFC_LDR_CORE2TX_EN_0 : in std_logic;
FFC_LDR_CORE2TX_EN_1 : in std_logic;
FFC_LDR_CORE2TX_EN_2 : in std_logic;
FFC_LDR_CORE2TX_EN_3 : in std_logic;
PCIE_POWERDOWN_0_0 : in std_logic;
PCIE_POWERDOWN_0_1 : in std_logic;
PCIE_POWERDOWN_1_0 : in std_logic;
PCIE_POWERDOWN_1_1 : in std_logic;
PCIE_POWERDOWN_2_0 : in std_logic;
PCIE_POWERDOWN_2_1 : in std_logic;
PCIE_POWERDOWN_3_0 : in std_logic;
PCIE_POWERDOWN_3_1 : in std_logic;
PCIE_RXPOLARITY_0 : in std_logic;
PCIE_RXPOLARITY_1 : in std_logic;
PCIE_RXPOLARITY_2 : in std_logic;
PCIE_RXPOLARITY_3 : in std_logic;
PCIE_TXCOMPLIANCE_0 : in std_logic;
PCIE_TXCOMPLIANCE_1 : in std_logic;
PCIE_TXCOMPLIANCE_2 : in std_logic;
PCIE_TXCOMPLIANCE_3 : in std_logic;
PCIE_TXDETRX_PR2TLB_0 : in std_logic;
PCIE_TXDETRX_PR2TLB_1 : in std_logic;
PCIE_TXDETRX_PR2TLB_2 : in std_logic;
PCIE_TXDETRX_PR2TLB_3 : in std_logic;
SCIADDR0 : in std_logic;
SCIADDR1 : in std_logic;
SCIADDR2 : in std_logic;
SCIADDR3 : in std_logic;
SCIADDR4 : in std_logic;
SCIADDR5 : in std_logic;
SCIENAUX : in std_logic;
SCIENCH0 : in std_logic;
SCIENCH1 : in std_logic;
SCIENCH2 : in std_logic;
SCIENCH3 : in std_logic;
SCIRD : in std_logic;
SCISELAUX : in std_logic;
SCISELCH0 : in std_logic;
SCISELCH1 : in std_logic;
SCISELCH2 : in std_logic;
SCISELCH3 : in std_logic;
SCIWDATA0 : in std_logic;
SCIWDATA1 : in std_logic;
SCIWDATA2 : in std_logic;
SCIWDATA3 : in std_logic;
SCIWDATA4 : in std_logic;
SCIWDATA5 : in std_logic;
SCIWDATA6 : in std_logic;
SCIWDATA7 : in std_logic;
SCIWSTN : in std_logic;
REFCLK_FROM_NQ : in std_logic;
HDOUTN0 : out std_logic;
HDOUTN1 : out std_logic;
HDOUTN2 : out std_logic;
HDOUTN3 : out std_logic;
HDOUTP0 : out std_logic;
HDOUTP1 : out std_logic;
HDOUTP2 : out std_logic;
HDOUTP3 : out std_logic;
COUT0 : out std_logic;
COUT1 : out std_logic;
COUT2 : out std_logic;
COUT3 : out std_logic;
COUT4 : out std_logic;
COUT5 : out std_logic;
COUT6 : out std_logic;
COUT7 : out std_logic;
COUT8 : out std_logic;
COUT9 : out std_logic;
COUT10 : out std_logic;
COUT11 : out std_logic;
COUT12 : out std_logic;
COUT13 : out std_logic;
COUT14 : out std_logic;
COUT15 : out std_logic;
COUT16 : out std_logic;
COUT17 : out std_logic;
COUT18 : out std_logic;
COUT19 : out std_logic;
FF_RX_D_0_0 : out std_logic;
FF_RX_D_0_1 : out std_logic;
FF_RX_D_0_2 : out std_logic;
FF_RX_D_0_3 : out std_logic;
FF_RX_D_0_4 : out std_logic;
FF_RX_D_0_5 : out std_logic;
FF_RX_D_0_6 : out std_logic;
FF_RX_D_0_7 : out std_logic;
FF_RX_D_0_8 : out std_logic;
FF_RX_D_0_9 : out std_logic;
FF_RX_D_0_10 : out std_logic;
FF_RX_D_0_11 : out std_logic;
FF_RX_D_0_12 : out std_logic;
FF_RX_D_0_13 : out std_logic;
FF_RX_D_0_14 : out std_logic;
FF_RX_D_0_15 : out std_logic;
FF_RX_D_0_16 : out std_logic;
FF_RX_D_0_17 : out std_logic;
FF_RX_D_0_18 : out std_logic;
FF_RX_D_0_19 : out std_logic;
FF_RX_D_0_20 : out std_logic;
FF_RX_D_0_21 : out std_logic;
FF_RX_D_0_22 : out std_logic;
FF_RX_D_0_23 : out std_logic;
FF_RX_D_1_0 : out std_logic;
FF_RX_D_1_1 : out std_logic;
FF_RX_D_1_2 : out std_logic;
FF_RX_D_1_3 : out std_logic;
FF_RX_D_1_4 : out std_logic;
FF_RX_D_1_5 : out std_logic;
FF_RX_D_1_6 : out std_logic;
FF_RX_D_1_7 : out std_logic;
FF_RX_D_1_8 : out std_logic;
FF_RX_D_1_9 : out std_logic;
FF_RX_D_1_10 : out std_logic;
FF_RX_D_1_11 : out std_logic;
FF_RX_D_1_12 : out std_logic;
FF_RX_D_1_13 : out std_logic;
FF_RX_D_1_14 : out std_logic;
FF_RX_D_1_15 : out std_logic;
FF_RX_D_1_16 : out std_logic;
FF_RX_D_1_17 : out std_logic;
FF_RX_D_1_18 : out std_logic;
FF_RX_D_1_19 : out std_logic;
FF_RX_D_1_20 : out std_logic;
FF_RX_D_1_21 : out std_logic;
FF_RX_D_1_22 : out std_logic;
FF_RX_D_1_23 : out std_logic;
FF_RX_D_2_0 : out std_logic;
FF_RX_D_2_1 : out std_logic;
FF_RX_D_2_2 : out std_logic;
FF_RX_D_2_3 : out std_logic;
FF_RX_D_2_4 : out std_logic;
FF_RX_D_2_5 : out std_logic;
FF_RX_D_2_6 : out std_logic;
FF_RX_D_2_7 : out std_logic;
FF_RX_D_2_8 : out std_logic;
FF_RX_D_2_9 : out std_logic;
FF_RX_D_2_10 : out std_logic;
FF_RX_D_2_11 : out std_logic;
FF_RX_D_2_12 : out std_logic;
FF_RX_D_2_13 : out std_logic;
FF_RX_D_2_14 : out std_logic;
FF_RX_D_2_15 : out std_logic;
FF_RX_D_2_16 : out std_logic;
FF_RX_D_2_17 : out std_logic;
FF_RX_D_2_18 : out std_logic;
FF_RX_D_2_19 : out std_logic;
FF_RX_D_2_20 : out std_logic;
FF_RX_D_2_21 : out std_logic;
FF_RX_D_2_22 : out std_logic;
FF_RX_D_2_23 : out std_logic;
FF_RX_D_3_0 : out std_logic;
FF_RX_D_3_1 : out std_logic;
FF_RX_D_3_2 : out std_logic;
FF_RX_D_3_3 : out std_logic;
FF_RX_D_3_4 : out std_logic;
FF_RX_D_3_5 : out std_logic;
FF_RX_D_3_6 : out std_logic;
FF_RX_D_3_7 : out std_logic;
FF_RX_D_3_8 : out std_logic;
FF_RX_D_3_9 : out std_logic;
FF_RX_D_3_10 : out std_logic;
FF_RX_D_3_11 : out std_logic;
FF_RX_D_3_12 : out std_logic;
FF_RX_D_3_13 : out std_logic;
FF_RX_D_3_14 : out std_logic;
FF_RX_D_3_15 : out std_logic;
FF_RX_D_3_16 : out std_logic;
FF_RX_D_3_17 : out std_logic;
FF_RX_D_3_18 : out std_logic;
FF_RX_D_3_19 : out std_logic;
FF_RX_D_3_20 : out std_logic;
FF_RX_D_3_21 : out std_logic;
FF_RX_D_3_22 : out std_logic;
FF_RX_D_3_23 : out std_logic;
FF_RX_F_CLK_0 : out std_logic;
FF_RX_F_CLK_1 : out std_logic;
FF_RX_F_CLK_2 : out std_logic;
FF_RX_F_CLK_3 : out std_logic;
FF_RX_H_CLK_0 : out std_logic;
FF_RX_H_CLK_1 : out std_logic;
FF_RX_H_CLK_2 : out std_logic;
FF_RX_H_CLK_3 : out std_logic;
FF_TX_F_CLK_0 : out std_logic;
FF_TX_F_CLK_1 : out std_logic;
FF_TX_F_CLK_2 : out std_logic;
FF_TX_F_CLK_3 : out std_logic;
FF_TX_H_CLK_0 : out std_logic;
FF_TX_H_CLK_1 : out std_logic;
FF_TX_H_CLK_2 : out std_logic;
FF_TX_H_CLK_3 : out std_logic;
FFS_CC_OVERRUN_0 : out std_logic;
FFS_CC_OVERRUN_1 : out std_logic;
FFS_CC_OVERRUN_2 : out std_logic;
FFS_CC_OVERRUN_3 : out std_logic;
FFS_CC_UNDERRUN_0 : out std_logic;
FFS_CC_UNDERRUN_1 : out std_logic;
FFS_CC_UNDERRUN_2 : out std_logic;
FFS_CC_UNDERRUN_3 : out std_logic;
FFS_LS_SYNC_STATUS_0 : out std_logic;
FFS_LS_SYNC_STATUS_1 : out std_logic;
FFS_LS_SYNC_STATUS_2 : out std_logic;
FFS_LS_SYNC_STATUS_3 : out std_logic;
FFS_CDR_TRAIN_DONE_0 : out std_logic;
FFS_CDR_TRAIN_DONE_1 : out std_logic;
FFS_CDR_TRAIN_DONE_2 : out std_logic;
FFS_CDR_TRAIN_DONE_3 : out std_logic;
FFS_PCIE_CON_0 : out std_logic;
FFS_PCIE_CON_1 : out std_logic;
FFS_PCIE_CON_2 : out std_logic;
FFS_PCIE_CON_3 : out std_logic;
FFS_PCIE_DONE_0 : out std_logic;
FFS_PCIE_DONE_1 : out std_logic;
FFS_PCIE_DONE_2 : out std_logic;
FFS_PCIE_DONE_3 : out std_logic;
FFS_PLOL : out std_logic;
FFS_RLOL_0 : out std_logic;
FFS_RLOL_1 : out std_logic;
FFS_RLOL_2 : out std_logic;
FFS_RLOL_3 : out std_logic;
FFS_RLOS_HI_0 : out std_logic;
FFS_RLOS_HI_1 : out std_logic;
FFS_RLOS_HI_2 : out std_logic;
FFS_RLOS_HI_3 : out std_logic;
FFS_RLOS_LO_0 : out std_logic;
FFS_RLOS_LO_1 : out std_logic;
FFS_RLOS_LO_2 : out std_logic;
FFS_RLOS_LO_3 : out std_logic;
FFS_RXFBFIFO_ERROR_0 : out std_logic;
FFS_RXFBFIFO_ERROR_1 : out std_logic;
FFS_RXFBFIFO_ERROR_2 : out std_logic;
FFS_RXFBFIFO_ERROR_3 : out std_logic;
FFS_TXFBFIFO_ERROR_0 : out std_logic;
FFS_TXFBFIFO_ERROR_1 : out std_logic;
FFS_TXFBFIFO_ERROR_2 : out std_logic;
FFS_TXFBFIFO_ERROR_3 : out std_logic;
PCIE_PHYSTATUS_0 : out std_logic;
PCIE_PHYSTATUS_1 : out std_logic;
PCIE_PHYSTATUS_2 : out std_logic;
PCIE_PHYSTATUS_3 : out std_logic;
PCIE_RXVALID_0 : out std_logic;
PCIE_RXVALID_1 : out std_logic;
PCIE_RXVALID_2 : out std_logic;
PCIE_RXVALID_3 : out std_logic;
FFS_SKP_ADDED_0 : out std_logic;
FFS_SKP_ADDED_1 : out std_logic;
FFS_SKP_ADDED_2 : out std_logic;
FFS_SKP_ADDED_3 : out std_logic;
FFS_SKP_DELETED_0 : out std_logic;
FFS_SKP_DELETED_1 : out std_logic;
FFS_SKP_DELETED_2 : out std_logic;
FFS_SKP_DELETED_3 : out std_logic;
LDR_RX2CORE_0 : out std_logic;
LDR_RX2CORE_1 : out std_logic;
LDR_RX2CORE_2 : out std_logic;
LDR_RX2CORE_3 : out std_logic;
REFCK2CORE : out std_logic;
SCIINT : out std_logic;
SCIRDATA0 : out std_logic;
SCIRDATA1 : out std_logic;
SCIRDATA2 : out std_logic;
SCIRDATA3 : out std_logic;
SCIRDATA4 : out std_logic;
SCIRDATA5 : out std_logic;
SCIRDATA6 : out std_logic;
SCIRDATA7 : out std_logic;
REFCLK_TO_NQ : out std_logic
);
end component;
begin
PCSD_sim_inst : PCSD_sim
generic map (
CONFIG_FILE => CONFIG_FILE,
QUAD_MODE => QUAD_MODE,
CH0_CDR_SRC => CH0_CDR_SRC,
CH1_CDR_SRC => CH1_CDR_SRC,
CH2_CDR_SRC => CH2_CDR_SRC,
CH3_CDR_SRC => CH3_CDR_SRC,
PLL_SRC => PLL_SRC
)
port map (
HDINN0 => HDINN0,
HDINN1 => HDINN1,
HDINN2 => HDINN2,
HDINN3 => HDINN3,
HDINP0 => HDINP0,
HDINP1 => HDINP1,
HDINP2 => HDINP2,
HDINP3 => HDINP3,
REFCLKN => REFCLKN,
REFCLKP => REFCLKP,
CIN11 => CIN11,
CIN10 => CIN10,
CIN9 => CIN9,
CIN8 => CIN8,
CIN7 => CIN7,
CIN6 => CIN6,
CIN5 => CIN5,
CIN4 => CIN4,
CIN3 => CIN3,
CIN2 => CIN2,
CIN1 => CIN1,
CIN0 => CIN0,
CYAWSTN => CYAWSTN,
FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
FF_RXI_CLK_3 => FF_RXI_CLK_3,
FF_RXI_CLK_2 => FF_RXI_CLK_2,
FF_RXI_CLK_1 => FF_RXI_CLK_1,
FF_RXI_CLK_0 => FF_RXI_CLK_0,
FF_TX_D_0_0 => FF_TX_D_0_0,
FF_TX_D_0_1 => FF_TX_D_0_1,
FF_TX_D_0_2 => FF_TX_D_0_2,
FF_TX_D_0_3 => FF_TX_D_0_3,
FF_TX_D_0_4 => FF_TX_D_0_4,
FF_TX_D_0_5 => FF_TX_D_0_5,
FF_TX_D_0_6 => FF_TX_D_0_6,
FF_TX_D_0_7 => FF_TX_D_0_7,
FF_TX_D_0_8 => FF_TX_D_0_8,
FF_TX_D_0_9 => FF_TX_D_0_9,
FF_TX_D_0_10 => FF_TX_D_0_10,
FF_TX_D_0_11 => FF_TX_D_0_11,
FF_TX_D_0_12 => FF_TX_D_0_12,
FF_TX_D_0_13 => FF_TX_D_0_13,
FF_TX_D_0_14 => FF_TX_D_0_14,
FF_TX_D_0_15 => FF_TX_D_0_15,
FF_TX_D_0_16 => FF_TX_D_0_16,
FF_TX_D_0_17 => FF_TX_D_0_17,
FF_TX_D_0_18 => FF_TX_D_0_18,
FF_TX_D_0_19 => FF_TX_D_0_19,
FF_TX_D_0_20 => FF_TX_D_0_20,
FF_TX_D_0_21 => FF_TX_D_0_21,
FF_TX_D_0_22 => FF_TX_D_0_22,
FF_TX_D_0_23 => FF_TX_D_0_23,
FF_TX_D_1_0 => FF_TX_D_1_0,
FF_TX_D_1_1 => FF_TX_D_1_1,
FF_TX_D_1_2 => FF_TX_D_1_2,
FF_TX_D_1_3 => FF_TX_D_1_3,
FF_TX_D_1_4 => FF_TX_D_1_4,
FF_TX_D_1_5 => FF_TX_D_1_5,
FF_TX_D_1_6 => FF_TX_D_1_6,
FF_TX_D_1_7 => FF_TX_D_1_7,
FF_TX_D_1_8 => FF_TX_D_1_8,
FF_TX_D_1_9 => FF_TX_D_1_9,
FF_TX_D_1_10 => FF_TX_D_1_10,
FF_TX_D_1_11 => FF_TX_D_1_11,
FF_TX_D_1_12 => FF_TX_D_1_12,
FF_TX_D_1_13 => FF_TX_D_1_13,
FF_TX_D_1_14 => FF_TX_D_1_14,
FF_TX_D_1_15 => FF_TX_D_1_15,
FF_TX_D_1_16 => FF_TX_D_1_16,
FF_TX_D_1_17 => FF_TX_D_1_17,
FF_TX_D_1_18 => FF_TX_D_1_18,
FF_TX_D_1_19 => FF_TX_D_1_19,
FF_TX_D_1_20 => FF_TX_D_1_20,
FF_TX_D_1_21 => FF_TX_D_1_21,
FF_TX_D_1_22 => FF_TX_D_1_22,
FF_TX_D_1_23 => FF_TX_D_1_23,
FF_TX_D_2_0 => FF_TX_D_2_0,
FF_TX_D_2_1 => FF_TX_D_2_1,
FF_TX_D_2_2 => FF_TX_D_2_2,
FF_TX_D_2_3 => FF_TX_D_2_3,
FF_TX_D_2_4 => FF_TX_D_2_4,
FF_TX_D_2_5 => FF_TX_D_2_5,
FF_TX_D_2_6 => FF_TX_D_2_6,
FF_TX_D_2_7 => FF_TX_D_2_7,
FF_TX_D_2_8 => FF_TX_D_2_8,
FF_TX_D_2_9 => FF_TX_D_2_9,
FF_TX_D_2_10 => FF_TX_D_2_10,
FF_TX_D_2_11 => FF_TX_D_2_11,
FF_TX_D_2_12 => FF_TX_D_2_12,
FF_TX_D_2_13 => FF_TX_D_2_13,
FF_TX_D_2_14 => FF_TX_D_2_14,
FF_TX_D_2_15 => FF_TX_D_2_15,
FF_TX_D_2_16 => FF_TX_D_2_16,
FF_TX_D_2_17 => FF_TX_D_2_17,
FF_TX_D_2_18 => FF_TX_D_2_18,
FF_TX_D_2_19 => FF_TX_D_2_19,
FF_TX_D_2_20 => FF_TX_D_2_20,
FF_TX_D_2_21 => FF_TX_D_2_21,
FF_TX_D_2_22 => FF_TX_D_2_22,
FF_TX_D_2_23 => FF_TX_D_2_23,
FF_TX_D_3_0 => FF_TX_D_3_0,
FF_TX_D_3_1 => FF_TX_D_3_1,
FF_TX_D_3_2 => FF_TX_D_3_2,
FF_TX_D_3_3 => FF_TX_D_3_3,
FF_TX_D_3_4 => FF_TX_D_3_4,
FF_TX_D_3_5 => FF_TX_D_3_5,
FF_TX_D_3_6 => FF_TX_D_3_6,
FF_TX_D_3_7 => FF_TX_D_3_7,
FF_TX_D_3_8 => FF_TX_D_3_8,
FF_TX_D_3_9 => FF_TX_D_3_9,
FF_TX_D_3_10 => FF_TX_D_3_10,
FF_TX_D_3_11 => FF_TX_D_3_11,
FF_TX_D_3_12 => FF_TX_D_3_12,
FF_TX_D_3_13 => FF_TX_D_3_13,
FF_TX_D_3_14 => FF_TX_D_3_14,
FF_TX_D_3_15 => FF_TX_D_3_15,
FF_TX_D_3_16 => FF_TX_D_3_16,
FF_TX_D_3_17 => FF_TX_D_3_17,
FF_TX_D_3_18 => FF_TX_D_3_18,
FF_TX_D_3_19 => FF_TX_D_3_19,
FF_TX_D_3_20 => FF_TX_D_3_20,
FF_TX_D_3_21 => FF_TX_D_3_21,
FF_TX_D_3_22 => FF_TX_D_3_22,
FF_TX_D_3_23 => FF_TX_D_3_23,
FF_TXI_CLK_0 => FF_TXI_CLK_0,
FF_TXI_CLK_1 => FF_TXI_CLK_1,
FF_TXI_CLK_2 => FF_TXI_CLK_2,
FF_TXI_CLK_3 => FF_TXI_CLK_3,
FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
FFC_CK_CORE_TX => FFC_CK_CORE_TX,
FFC_EI_EN_0 => FFC_EI_EN_0,
FFC_EI_EN_1 => FFC_EI_EN_1,
FFC_EI_EN_2 => FFC_EI_EN_2,
FFC_EI_EN_3 => FFC_EI_EN_3,
FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
FFC_MACRO_RST => FFC_MACRO_RST,
FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
FFC_QUAD_RST => FFC_QUAD_RST,
FFC_RRST_0 => FFC_RRST_0,
FFC_RRST_1 => FFC_RRST_1,
FFC_RRST_2 => FFC_RRST_2,
FFC_RRST_3 => FFC_RRST_3,
FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
FFC_TRST => FFC_TRST,
FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
LDR_CORE2TX_0 => LDR_CORE2TX_0,
LDR_CORE2TX_1 => LDR_CORE2TX_1,
LDR_CORE2TX_2 => LDR_CORE2TX_2,
LDR_CORE2TX_3 => LDR_CORE2TX_3,
FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
SCIADDR0 => SCIADDR0,
SCIADDR1 => SCIADDR1,
SCIADDR2 => SCIADDR2,
SCIADDR3 => SCIADDR3,
SCIADDR4 => SCIADDR4,
SCIADDR5 => SCIADDR5,
SCIENAUX => SCIENAUX,
SCIENCH0 => SCIENCH0,
SCIENCH1 => SCIENCH1,
SCIENCH2 => SCIENCH2,
SCIENCH3 => SCIENCH3,
SCIRD => SCIRD,
SCISELAUX => SCISELAUX,
SCISELCH0 => SCISELCH0,
SCISELCH1 => SCISELCH1,
SCISELCH2 => SCISELCH2,
SCISELCH3 => SCISELCH3,
SCIWDATA0 => SCIWDATA0,
SCIWDATA1 => SCIWDATA1,
SCIWDATA2 => SCIWDATA2,
SCIWDATA3 => SCIWDATA3,
SCIWDATA4 => SCIWDATA4,
SCIWDATA5 => SCIWDATA5,
SCIWDATA6 => SCIWDATA6,
SCIWDATA7 => SCIWDATA7,
SCIWSTN => SCIWSTN,
HDOUTN0 => HDOUTN0,
HDOUTN1 => HDOUTN1,
HDOUTN2 => HDOUTN2,
HDOUTN3 => HDOUTN3,
HDOUTP0 => HDOUTP0,
HDOUTP1 => HDOUTP1,
HDOUTP2 => HDOUTP2,
HDOUTP3 => HDOUTP3,
COUT19 => COUT19,
COUT18 => COUT18,
COUT17 => COUT17,
COUT16 => COUT16,
COUT15 => COUT15,
COUT14 => COUT14,
COUT13 => COUT13,
COUT12 => COUT12,
COUT11 => COUT11,
COUT10 => COUT10,
COUT9 => COUT9,
COUT8 => COUT8,
COUT7 => COUT7,
COUT6 => COUT6,
COUT5 => COUT5,
COUT4 => COUT4,
COUT3 => COUT3,
COUT2 => COUT2,
COUT1 => COUT1,
COUT0 => COUT0,
FF_RX_D_0_0 => FF_RX_D_0_0,
FF_RX_D_0_1 => FF_RX_D_0_1,
FF_RX_D_0_2 => FF_RX_D_0_2,
FF_RX_D_0_3 => FF_RX_D_0_3,
FF_RX_D_0_4 => FF_RX_D_0_4,
FF_RX_D_0_5 => FF_RX_D_0_5,
FF_RX_D_0_6 => FF_RX_D_0_6,
FF_RX_D_0_7 => FF_RX_D_0_7,
FF_RX_D_0_8 => FF_RX_D_0_8,
FF_RX_D_0_9 => FF_RX_D_0_9,
FF_RX_D_0_10 => FF_RX_D_0_10,
FF_RX_D_0_11 => FF_RX_D_0_11,
FF_RX_D_0_12 => FF_RX_D_0_12,
FF_RX_D_0_13 => FF_RX_D_0_13,
FF_RX_D_0_14 => FF_RX_D_0_14,
FF_RX_D_0_15 => FF_RX_D_0_15,
FF_RX_D_0_16 => FF_RX_D_0_16,
FF_RX_D_0_17 => FF_RX_D_0_17,
FF_RX_D_0_18 => FF_RX_D_0_18,
FF_RX_D_0_19 => FF_RX_D_0_19,
FF_RX_D_0_20 => FF_RX_D_0_20,
FF_RX_D_0_21 => FF_RX_D_0_21,
FF_RX_D_0_22 => FF_RX_D_0_22,
FF_RX_D_0_23 => FF_RX_D_0_23,
FF_RX_D_1_0 => FF_RX_D_1_0,
FF_RX_D_1_1 => FF_RX_D_1_1,
FF_RX_D_1_2 => FF_RX_D_1_2,
FF_RX_D_1_3 => FF_RX_D_1_3,
FF_RX_D_1_4 => FF_RX_D_1_4,
FF_RX_D_1_5 => FF_RX_D_1_5,
FF_RX_D_1_6 => FF_RX_D_1_6,
FF_RX_D_1_7 => FF_RX_D_1_7,
FF_RX_D_1_8 => FF_RX_D_1_8,
FF_RX_D_1_9 => FF_RX_D_1_9,
FF_RX_D_1_10 => FF_RX_D_1_10,
FF_RX_D_1_11 => FF_RX_D_1_11,
FF_RX_D_1_12 => FF_RX_D_1_12,
FF_RX_D_1_13 => FF_RX_D_1_13,
FF_RX_D_1_14 => FF_RX_D_1_14,
FF_RX_D_1_15 => FF_RX_D_1_15,
FF_RX_D_1_16 => FF_RX_D_1_16,
FF_RX_D_1_17 => FF_RX_D_1_17,
FF_RX_D_1_18 => FF_RX_D_1_18,
FF_RX_D_1_19 => FF_RX_D_1_19,
FF_RX_D_1_20 => FF_RX_D_1_20,
FF_RX_D_1_21 => FF_RX_D_1_21,
FF_RX_D_1_22 => FF_RX_D_1_22,
FF_RX_D_1_23 => FF_RX_D_1_23,
FF_RX_D_2_0 => FF_RX_D_2_0,
FF_RX_D_2_1 => FF_RX_D_2_1,
FF_RX_D_2_2 => FF_RX_D_2_2,
FF_RX_D_2_3 => FF_RX_D_2_3,
FF_RX_D_2_4 => FF_RX_D_2_4,
FF_RX_D_2_5 => FF_RX_D_2_5,
FF_RX_D_2_6 => FF_RX_D_2_6,
FF_RX_D_2_7 => FF_RX_D_2_7,
FF_RX_D_2_8 => FF_RX_D_2_8,
FF_RX_D_2_9 => FF_RX_D_2_9,
FF_RX_D_2_10 => FF_RX_D_2_10,
FF_RX_D_2_11 => FF_RX_D_2_11,
FF_RX_D_2_12 => FF_RX_D_2_12,
FF_RX_D_2_13 => FF_RX_D_2_13,
FF_RX_D_2_14 => FF_RX_D_2_14,
FF_RX_D_2_15 => FF_RX_D_2_15,
FF_RX_D_2_16 => FF_RX_D_2_16,
FF_RX_D_2_17 => FF_RX_D_2_17,
FF_RX_D_2_18 => FF_RX_D_2_18,
FF_RX_D_2_19 => FF_RX_D_2_19,
FF_RX_D_2_20 => FF_RX_D_2_20,
FF_RX_D_2_21 => FF_RX_D_2_21,
FF_RX_D_2_22 => FF_RX_D_2_22,
FF_RX_D_2_23 => FF_RX_D_2_23,
FF_RX_D_3_0 => FF_RX_D_3_0,
FF_RX_D_3_1 => FF_RX_D_3_1,
FF_RX_D_3_2 => FF_RX_D_3_2,
FF_RX_D_3_3 => FF_RX_D_3_3,
FF_RX_D_3_4 => FF_RX_D_3_4,
FF_RX_D_3_5 => FF_RX_D_3_5,
FF_RX_D_3_6 => FF_RX_D_3_6,
FF_RX_D_3_7 => FF_RX_D_3_7,
FF_RX_D_3_8 => FF_RX_D_3_8,
FF_RX_D_3_9 => FF_RX_D_3_9,
FF_RX_D_3_10 => FF_RX_D_3_10,
FF_RX_D_3_11 => FF_RX_D_3_11,
FF_RX_D_3_12 => FF_RX_D_3_12,
FF_RX_D_3_13 => FF_RX_D_3_13,
FF_RX_D_3_14 => FF_RX_D_3_14,
FF_RX_D_3_15 => FF_RX_D_3_15,
FF_RX_D_3_16 => FF_RX_D_3_16,
FF_RX_D_3_17 => FF_RX_D_3_17,
FF_RX_D_3_18 => FF_RX_D_3_18,
FF_RX_D_3_19 => FF_RX_D_3_19,
FF_RX_D_3_20 => FF_RX_D_3_20,
FF_RX_D_3_21 => FF_RX_D_3_21,
FF_RX_D_3_22 => FF_RX_D_3_22,
FF_RX_D_3_23 => FF_RX_D_3_23,
FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
FFS_PLOL => FFS_PLOL,
FFS_RLOL_0 => FFS_RLOL_0,
FFS_RLOL_1 => FFS_RLOL_1,
FFS_RLOL_2 => FFS_RLOL_2,
FFS_RLOL_3 => FFS_RLOL_3,
FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
PCIE_RXVALID_0 => PCIE_RXVALID_0,
PCIE_RXVALID_1 => PCIE_RXVALID_1,
PCIE_RXVALID_2 => PCIE_RXVALID_2,
PCIE_RXVALID_3 => PCIE_RXVALID_3,
FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
LDR_RX2CORE_0 => LDR_RX2CORE_0,
LDR_RX2CORE_1 => LDR_RX2CORE_1,
LDR_RX2CORE_2 => LDR_RX2CORE_2,
LDR_RX2CORE_3 => LDR_RX2CORE_3,
REFCK2CORE => REFCK2CORE,
SCIINT => SCIINT,
SCIRDATA0 => SCIRDATA0,
SCIRDATA1 => SCIRDATA1,
SCIRDATA2 => SCIRDATA2,
SCIRDATA3 => SCIRDATA3,
SCIRDATA4 => SCIRDATA4,
SCIRDATA5 => SCIRDATA5,
SCIRDATA6 => SCIRDATA6,
SCIRDATA7 => SCIRDATA7,
REFCLK_FROM_NQ => REFCLK_FROM_NQ,
REFCLK_TO_NQ => REFCLK_TO_NQ
);
end PCSD_arch;
--synopsys translate_on
--THIS MODULE IS INSTANTIATED PER TX QUAD
--TX Reset Sequence state machine--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity hdmi_pcstx_reset_sm is
generic (count_index: integer :=18);
port (
rst_n : in std_logic;
refclkdiv2 : in std_logic;
tx_pll_lol_qd_s : in std_logic;
rst_qd_c : out std_logic;
tx_pcs_rst_ch_c : out std_logic
);
end hdmi_pcstx_reset_sm;
architecture tx_reset_sm_arch of hdmi_pcstx_reset_sm is
type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL);
signal cs: statetype; -- current state of lsm
signal ns: statetype; -- next state of lsm
attribute syn_encoding : string;
attribute syn_encoding of cs : signal is "safe";
attribute syn_encoding of ns : signal is "safe";
signal tx_pll_lol_qd_s_int : std_logic;
signal tx_pcs_rst_ch_c_int : std_logic_vector(3 downto 0);
signal rst_qd_c_int : std_logic;
signal reset_timer1: std_logic;
signal reset_timer2: std_logic;
signal counter1: std_logic_vector(2 downto 0);
signal TIMER1: std_logic;
signal counter2: std_logic_vector(18 downto 0);
signal TIMER2: std_logic;
signal rstn_m1: std_logic;
signal rstn_m2: std_logic;
signal sync_rst_n: std_logic;
begin
process (refclkdiv2, rst_n)
begin
if rst_n = '0' then
rstn_m1 <= '0';
rstn_m2 <= '0';
else if rising_edge(refclkdiv2) then
rstn_m1 <= '1';
rstn_m2 <= rstn_m1;
end if;
end if;
end process;
sync_rst_n <= rstn_m2;
process (refclkdiv2, sync_rst_n)
begin
if sync_rst_n = '0' then
cs <= QUAD_RESET;
tx_pll_lol_qd_s_int <= '1';
tx_pcs_rst_ch_c <= '1';
rst_qd_c <= '1';
else if rising_edge(refclkdiv2) then
cs <= ns;
tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int(0);
rst_qd_c <= rst_qd_c_int;
end if;
end if;
end process;
--TIMER1 = 20ns;
--Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
-- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
process (refclkdiv2, reset_timer1)
begin
if rising_edge(refclkdiv2) then
if reset_timer1 = '1' then
counter1 <= "000";
TIMER1 <= '0';
else
if counter1(2) = '1' then
TIMER1 <= '1';
else
TIMER1 <='0';
counter1 <= counter1 + 1 ;
end if;
end if;
end if;
end process;
--TIMER2 = 1,400,000 UI;
--WORST CASE CYCLES is with smallest multipier factor.
-- This would be with X8 clock multiplier in DIV2 mode
-- IN this casse, 1 UI = 2/8 REFCLK CYCLES = 1/8 REFCLKDIV2 CYCLES
-- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
-- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
process(refclkdiv2, reset_timer2)
begin
if rising_edge(refclkdiv2) then
if reset_timer2 = '1' then
counter2 <= "0000000000000000000";
TIMER2 <= '0';
else
if counter2(count_index) = '1' then
TIMER2 <='1';
else
TIMER2 <='0';
counter2 <= counter2 + 1 ;
end if;
end if;
end if;
end process;
process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int)
begin
reset_timer1 <= '0';
reset_timer2 <= '0';
case cs is
when QUAD_RESET =>
tx_pcs_rst_ch_c_int <= "1111";
rst_qd_c_int <= '1';
reset_timer1 <= '1';
ns <= WAIT_FOR_TIMER1;
when WAIT_FOR_TIMER1 =>
tx_pcs_rst_ch_c_int <= "1111";
rst_qd_c_int <= '1';
if TIMER1 = '1' then
ns <= CHECK_PLOL;
else
ns <= WAIT_FOR_TIMER1;
end if;
when CHECK_PLOL =>
tx_pcs_rst_ch_c_int <= "1111";
rst_qd_c_int <= '0';
reset_timer2 <= '1';
ns <= WAIT_FOR_TIMER2;
when WAIT_FOR_TIMER2 =>
tx_pcs_rst_ch_c_int <= "1111";
rst_qd_c_int <= '0';
if TIMER2 = '1' then
if tx_pll_lol_qd_s_int = '1' then
ns <= QUAD_RESET;
else
ns <= NORMAL;
end if;
else
ns <= WAIT_FOR_TIMER2;
end if;
when NORMAL =>
tx_pcs_rst_ch_c_int <= "0000";
rst_qd_c_int <= '0';
if tx_pll_lol_qd_s_int = '1' then
ns <= QUAD_RESET;
else
ns <= NORMAL;
end if;
when others =>
ns <= QUAD_RESET;
end case;
end process;
end tx_reset_sm_arch;
--synopsys translate_off
library ECP3;
use ECP3.components.all;
--synopsys translate_on
library IEEE, STD;
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
entity hdmi_pcs is
GENERIC (USER_CONFIG_FILE : String := "hdmi_pcs.txt");
port (
------------------
-- CH0 --
hdoutp_ch0, hdoutn_ch0 : out std_logic;
sci_sel_ch0 : in std_logic;
txiclk_ch0 : in std_logic;
tx_full_clk_ch0 : out std_logic;
tx_half_clk_ch0 : out std_logic;
txdata_ch0 : in std_logic_vector (9 downto 0);
tx_pwrup_ch0_c : in std_logic;
tx_div2_mode_ch0_c : in std_logic;
-- CH1 --
hdoutp_ch1, hdoutn_ch1 : out std_logic;
sci_sel_ch1 : in std_logic;
txiclk_ch1 : in std_logic;
tx_full_clk_ch1 : out std_logic;
tx_half_clk_ch1 : out std_logic;
txdata_ch1 : in std_logic_vector (9 downto 0);
tx_pwrup_ch1_c : in std_logic;
tx_div2_mode_ch1_c : in std_logic;
-- CH2 --
hdoutp_ch2, hdoutn_ch2 : out std_logic;
sci_sel_ch2 : in std_logic;
txiclk_ch2 : in std_logic;
tx_full_clk_ch2 : out std_logic;
tx_half_clk_ch2 : out std_logic;
txdata_ch2 : in std_logic_vector (9 downto 0);
tx_pwrup_ch2_c : in std_logic;
tx_div2_mode_ch2_c : in std_logic;
-- CH3 --
hdoutp_ch3, hdoutn_ch3 : out std_logic;
sci_sel_ch3 : in std_logic;
txiclk_ch3 : in std_logic;
tx_full_clk_ch3 : out std_logic;
tx_half_clk_ch3 : out std_logic;
txdata_ch3 : in std_logic_vector (9 downto 0);
tx_pwrup_ch3_c : in std_logic;
tx_div2_mode_ch3_c : in std_logic;
---- Miscillaneous ports
sci_wrdata : in std_logic_vector (7 downto 0);
sci_addr : in std_logic_vector (5 downto 0);
sci_rddata : out std_logic_vector (7 downto 0);
sci_sel_quad : in std_logic;
sci_rd : in std_logic;
sci_wrn : in std_logic;
sci_int : out std_logic;
fpga_txrefclk : in std_logic;
tx_serdes_rst_c : in std_logic;
tx_pll_lol_qd_s : out std_logic;
tx_sync_qd_c : in std_logic;
refclk2fpga : out std_logic;
rst_n : in std_logic;
serdes_rst_qd_c : in std_logic);
end hdmi_pcs;
architecture hdmi_pcs_arch of hdmi_pcs is
component VLO
port (
Z : out std_logic);
end component;
component VHI
port (
Z : out std_logic);
end component;
component hdmi_pcstx_reset_sm
generic (count_index: integer :=18);
port (
rst_n : in std_logic;
refclkdiv2 : in std_logic;
tx_pll_lol_qd_s : in std_logic;
rst_qd_c : out std_logic;
tx_pcs_rst_ch_c : out std_logic
);
end component;
component PCSD
--synopsys translate_off
GENERIC(
CONFIG_FILE : String;
QUAD_MODE : String;
CH0_CDR_SRC : String := "REFCLK_EXT";
CH1_CDR_SRC : String := "REFCLK_EXT";
CH2_CDR_SRC : String := "REFCLK_EXT";
CH3_CDR_SRC : String := "REFCLK_EXT";
PLL_SRC : String
);
--synopsys translate_on
port (
HDINN0 : in std_logic;
HDINN1 : in std_logic;
HDINN2 : in std_logic;
HDINN3 : in std_logic;
HDINP0 : in std_logic;
HDINP1 : in std_logic;
HDINP2 : in std_logic;
HDINP3 : in std_logic;
REFCLKN : in std_logic;
REFCLKP : in std_logic;
CIN0 : in std_logic;
CIN1 : in std_logic;
CIN2 : in std_logic;
CIN3 : in std_logic;
CIN4 : in std_logic;
CIN5 : in std_logic;
CIN6 : in std_logic;
CIN7 : in std_logic;
CIN8 : in std_logic;
CIN9 : in std_logic;
CIN10 : in std_logic;
CIN11 : in std_logic;
CYAWSTN : in std_logic;
FF_EBRD_CLK_0 : in std_logic;
FF_EBRD_CLK_1 : in std_logic;
FF_EBRD_CLK_2 : in std_logic;
FF_EBRD_CLK_3 : in std_logic;
FF_RXI_CLK_0 : in std_logic;
FF_RXI_CLK_1 : in std_logic;
FF_RXI_CLK_2 : in std_logic;
FF_RXI_CLK_3 : in std_logic;
FF_TX_D_0_0 : in std_logic;
FF_TX_D_0_1 : in std_logic;
FF_TX_D_0_2 : in std_logic;
FF_TX_D_0_3 : in std_logic;
FF_TX_D_0_4 : in std_logic;
FF_TX_D_0_5 : in std_logic;
FF_TX_D_0_6 : in std_logic;
FF_TX_D_0_7 : in std_logic;
FF_TX_D_0_8 : in std_logic;
FF_TX_D_0_9 : in std_logic;
FF_TX_D_0_10 : in std_logic;
FF_TX_D_0_11 : in std_logic;
FF_TX_D_0_12 : in std_logic;
FF_TX_D_0_13 : in std_logic;
FF_TX_D_0_14 : in std_logic;
FF_TX_D_0_15 : in std_logic;
FF_TX_D_0_16 : in std_logic;
FF_TX_D_0_17 : in std_logic;
FF_TX_D_0_18 : in std_logic;
FF_TX_D_0_19 : in std_logic;
FF_TX_D_0_20 : in std_logic;
FF_TX_D_0_21 : in std_logic;
FF_TX_D_0_22 : in std_logic;
FF_TX_D_0_23 : in std_logic;
FF_TX_D_1_0 : in std_logic;
FF_TX_D_1_1 : in std_logic;
FF_TX_D_1_2 : in std_logic;
FF_TX_D_1_3 : in std_logic;
FF_TX_D_1_4 : in std_logic;
FF_TX_D_1_5 : in std_logic;
FF_TX_D_1_6 : in std_logic;
FF_TX_D_1_7 : in std_logic;
FF_TX_D_1_8 : in std_logic;
FF_TX_D_1_9 : in std_logic;
FF_TX_D_1_10 : in std_logic;
FF_TX_D_1_11 : in std_logic;
FF_TX_D_1_12 : in std_logic;
FF_TX_D_1_13 : in std_logic;
FF_TX_D_1_14 : in std_logic;
FF_TX_D_1_15 : in std_logic;
FF_TX_D_1_16 : in std_logic;
FF_TX_D_1_17 : in std_logic;
FF_TX_D_1_18 : in std_logic;
FF_TX_D_1_19 : in std_logic;
FF_TX_D_1_20 : in std_logic;
FF_TX_D_1_21 : in std_logic;
FF_TX_D_1_22 : in std_logic;
FF_TX_D_1_23 : in std_logic;
FF_TX_D_2_0 : in std_logic;
FF_TX_D_2_1 : in std_logic;
FF_TX_D_2_2 : in std_logic;
FF_TX_D_2_3 : in std_logic;
FF_TX_D_2_4 : in std_logic;
FF_TX_D_2_5 : in std_logic;
FF_TX_D_2_6 : in std_logic;
FF_TX_D_2_7 : in std_logic;
FF_TX_D_2_8 : in std_logic;
FF_TX_D_2_9 : in std_logic;
FF_TX_D_2_10 : in std_logic;
FF_TX_D_2_11 : in std_logic;
FF_TX_D_2_12 : in std_logic;
FF_TX_D_2_13 : in std_logic;
FF_TX_D_2_14 : in std_logic;
FF_TX_D_2_15 : in std_logic;
FF_TX_D_2_16 : in std_logic;
FF_TX_D_2_17 : in std_logic;
FF_TX_D_2_18 : in std_logic;
FF_TX_D_2_19 : in std_logic;
FF_TX_D_2_20 : in std_logic;
FF_TX_D_2_21 : in std_logic;
FF_TX_D_2_22 : in std_logic;
FF_TX_D_2_23 : in std_logic;
FF_TX_D_3_0 : in std_logic;
FF_TX_D_3_1 : in std_logic;
FF_TX_D_3_2 : in std_logic;
FF_TX_D_3_3 : in std_logic;
FF_TX_D_3_4 : in std_logic;
FF_TX_D_3_5 : in std_logic;
FF_TX_D_3_6 : in std_logic;
FF_TX_D_3_7 : in std_logic;
FF_TX_D_3_8 : in std_logic;
FF_TX_D_3_9 : in std_logic;
FF_TX_D_3_10 : in std_logic;
FF_TX_D_3_11 : in std_logic;
FF_TX_D_3_12 : in std_logic;
FF_TX_D_3_13 : in std_logic;
FF_TX_D_3_14 : in std_logic;
FF_TX_D_3_15 : in std_logic;
FF_TX_D_3_16 : in std_logic;
FF_TX_D_3_17 : in std_logic;
FF_TX_D_3_18 : in std_logic;
FF_TX_D_3_19 : in std_logic;
FF_TX_D_3_20 : in std_logic;
FF_TX_D_3_21 : in std_logic;
FF_TX_D_3_22 : in std_logic;
FF_TX_D_3_23 : in std_logic;
FF_TXI_CLK_0 : in std_logic;
FF_TXI_CLK_1 : in std_logic;
FF_TXI_CLK_2 : in std_logic;
FF_TXI_CLK_3 : in std_logic;
FFC_CK_CORE_RX_0 : in std_logic;
FFC_CK_CORE_RX_1 : in std_logic;
FFC_CK_CORE_RX_2 : in std_logic;
FFC_CK_CORE_RX_3 : in std_logic;
FFC_CK_CORE_TX : in std_logic;
FFC_EI_EN_0 : in std_logic;
FFC_EI_EN_1 : in std_logic;
FFC_EI_EN_2 : in std_logic;
FFC_EI_EN_3 : in std_logic;
FFC_ENABLE_CGALIGN_0 : in std_logic;
FFC_ENABLE_CGALIGN_1 : in std_logic;
FFC_ENABLE_CGALIGN_2 : in std_logic;
FFC_ENABLE_CGALIGN_3 : in std_logic;
FFC_FB_LOOPBACK_0 : in std_logic;
FFC_FB_LOOPBACK_1 : in std_logic;
FFC_FB_LOOPBACK_2 : in std_logic;
FFC_FB_LOOPBACK_3 : in std_logic;
FFC_LANE_RX_RST_0 : in std_logic;
FFC_LANE_RX_RST_1 : in std_logic;
FFC_LANE_RX_RST_2 : in std_logic;
FFC_LANE_RX_RST_3 : in std_logic;
FFC_LANE_TX_RST_0 : in std_logic;
FFC_LANE_TX_RST_1 : in std_logic;
FFC_LANE_TX_RST_2 : in std_logic;
FFC_LANE_TX_RST_3 : in std_logic;
FFC_MACRO_RST : in std_logic;
FFC_PCI_DET_EN_0 : in std_logic;
FFC_PCI_DET_EN_1 : in std_logic;
FFC_PCI_DET_EN_2 : in std_logic;
FFC_PCI_DET_EN_3 : in std_logic;
FFC_PCIE_CT_0 : in std_logic;
FFC_PCIE_CT_1 : in std_logic;
FFC_PCIE_CT_2 : in std_logic;
FFC_PCIE_CT_3 : in std_logic;
FFC_PFIFO_CLR_0 : in std_logic;
FFC_PFIFO_CLR_1 : in std_logic;
FFC_PFIFO_CLR_2 : in std_logic;
FFC_PFIFO_CLR_3 : in std_logic;
FFC_QUAD_RST : in std_logic;
FFC_RRST_0 : in std_logic;
FFC_RRST_1 : in std_logic;
FFC_RRST_2 : in std_logic;
FFC_RRST_3 : in std_logic;
FFC_RXPWDNB_0 : in std_logic;
FFC_RXPWDNB_1 : in std_logic;
FFC_RXPWDNB_2 : in std_logic;
FFC_RXPWDNB_3 : in std_logic;
FFC_SB_INV_RX_0 : in std_logic;
FFC_SB_INV_RX_1 : in std_logic;
FFC_SB_INV_RX_2 : in std_logic;
FFC_SB_INV_RX_3 : in std_logic;
FFC_SB_PFIFO_LP_0 : in std_logic;
FFC_SB_PFIFO_LP_1 : in std_logic;
FFC_SB_PFIFO_LP_2 : in std_logic;
FFC_SB_PFIFO_LP_3 : in std_logic;
FFC_SIGNAL_DETECT_0 : in std_logic;
FFC_SIGNAL_DETECT_1 : in std_logic;
FFC_SIGNAL_DETECT_2 : in std_logic;
FFC_SIGNAL_DETECT_3 : in std_logic;
FFC_SYNC_TOGGLE : in std_logic;
FFC_TRST : in std_logic;
FFC_TXPWDNB_0 : in std_logic;
FFC_TXPWDNB_1 : in std_logic;
FFC_TXPWDNB_2 : in std_logic;
FFC_TXPWDNB_3 : in std_logic;
FFC_RATE_MODE_RX_0 : in std_logic;
FFC_RATE_MODE_RX_1 : in std_logic;
FFC_RATE_MODE_RX_2 : in std_logic;
FFC_RATE_MODE_RX_3 : in std_logic;
FFC_RATE_MODE_TX_0 : in std_logic;
FFC_RATE_MODE_TX_1 : in std_logic;
FFC_RATE_MODE_TX_2 : in std_logic;
FFC_RATE_MODE_TX_3 : in std_logic;
FFC_DIV11_MODE_RX_0 : in std_logic;
FFC_DIV11_MODE_RX_1 : in std_logic;
FFC_DIV11_MODE_RX_2 : in std_logic;
FFC_DIV11_MODE_RX_3 : in std_logic;
FFC_DIV11_MODE_TX_0 : in std_logic;
FFC_DIV11_MODE_TX_1 : in std_logic;
FFC_DIV11_MODE_TX_2 : in std_logic;
FFC_DIV11_MODE_TX_3 : in std_logic;
LDR_CORE2TX_0 : in std_logic;
LDR_CORE2TX_1 : in std_logic;
LDR_CORE2TX_2 : in std_logic;
LDR_CORE2TX_3 : in std_logic;
FFC_LDR_CORE2TX_EN_0 : in std_logic;
FFC_LDR_CORE2TX_EN_1 : in std_logic;
FFC_LDR_CORE2TX_EN_2 : in std_logic;
FFC_LDR_CORE2TX_EN_3 : in std_logic;
PCIE_POWERDOWN_0_0 : in std_logic;
PCIE_POWERDOWN_0_1 : in std_logic;
PCIE_POWERDOWN_1_0 : in std_logic;
PCIE_POWERDOWN_1_1 : in std_logic;
PCIE_POWERDOWN_2_0 : in std_logic;
PCIE_POWERDOWN_2_1 : in std_logic;
PCIE_POWERDOWN_3_0 : in std_logic;
PCIE_POWERDOWN_3_1 : in std_logic;
PCIE_RXPOLARITY_0 : in std_logic;
PCIE_RXPOLARITY_1 : in std_logic;
PCIE_RXPOLARITY_2 : in std_logic;
PCIE_RXPOLARITY_3 : in std_logic;
PCIE_TXCOMPLIANCE_0 : in std_logic;
PCIE_TXCOMPLIANCE_1 : in std_logic;
PCIE_TXCOMPLIANCE_2 : in std_logic;
PCIE_TXCOMPLIANCE_3 : in std_logic;
PCIE_TXDETRX_PR2TLB_0 : in std_logic;
PCIE_TXDETRX_PR2TLB_1 : in std_logic;
PCIE_TXDETRX_PR2TLB_2 : in std_logic;
PCIE_TXDETRX_PR2TLB_3 : in std_logic;
SCIADDR0 : in std_logic;
SCIADDR1 : in std_logic;
SCIADDR2 : in std_logic;
SCIADDR3 : in std_logic;
SCIADDR4 : in std_logic;
SCIADDR5 : in std_logic;
SCIENAUX : in std_logic;
SCIENCH0 : in std_logic;
SCIENCH1 : in std_logic;
SCIENCH2 : in std_logic;
SCIENCH3 : in std_logic;
SCIRD : in std_logic;
SCISELAUX : in std_logic;
SCISELCH0 : in std_logic;
SCISELCH1 : in std_logic;
SCISELCH2 : in std_logic;
SCISELCH3 : in std_logic;
SCIWDATA0 : in std_logic;
SCIWDATA1 : in std_logic;
SCIWDATA2 : in std_logic;
SCIWDATA3 : in std_logic;
SCIWDATA4 : in std_logic;
SCIWDATA5 : in std_logic;
SCIWDATA6 : in std_logic;
SCIWDATA7 : in std_logic;
SCIWSTN : in std_logic;
REFCLK_FROM_NQ : in std_logic;
HDOUTN0 : out std_logic;
HDOUTN1 : out std_logic;
HDOUTN2 : out std_logic;
HDOUTN3 : out std_logic;
HDOUTP0 : out std_logic;
HDOUTP1 : out std_logic;
HDOUTP2 : out std_logic;
HDOUTP3 : out std_logic;
COUT0 : out std_logic;
COUT1 : out std_logic;
COUT2 : out std_logic;
COUT3 : out std_logic;
COUT4 : out std_logic;
COUT5 : out std_logic;
COUT6 : out std_logic;
COUT7 : out std_logic;
COUT8 : out std_logic;
COUT9 : out std_logic;
COUT10 : out std_logic;
COUT11 : out std_logic;
COUT12 : out std_logic;
COUT13 : out std_logic;
COUT14 : out std_logic;
COUT15 : out std_logic;
COUT16 : out std_logic;
COUT17 : out std_logic;
COUT18 : out std_logic;
COUT19 : out std_logic;
FF_RX_D_0_0 : out std_logic;
FF_RX_D_0_1 : out std_logic;
FF_RX_D_0_2 : out std_logic;
FF_RX_D_0_3 : out std_logic;
FF_RX_D_0_4 : out std_logic;
FF_RX_D_0_5 : out std_logic;
FF_RX_D_0_6 : out std_logic;
FF_RX_D_0_7 : out std_logic;
FF_RX_D_0_8 : out std_logic;
FF_RX_D_0_9 : out std_logic;
FF_RX_D_0_10 : out std_logic;
FF_RX_D_0_11 : out std_logic;
FF_RX_D_0_12 : out std_logic;
FF_RX_D_0_13 : out std_logic;
FF_RX_D_0_14 : out std_logic;
FF_RX_D_0_15 : out std_logic;
FF_RX_D_0_16 : out std_logic;
FF_RX_D_0_17 : out std_logic;
FF_RX_D_0_18 : out std_logic;
FF_RX_D_0_19 : out std_logic;
FF_RX_D_0_20 : out std_logic;
FF_RX_D_0_21 : out std_logic;
FF_RX_D_0_22 : out std_logic;
FF_RX_D_0_23 : out std_logic;
FF_RX_D_1_0 : out std_logic;
FF_RX_D_1_1 : out std_logic;
FF_RX_D_1_2 : out std_logic;
FF_RX_D_1_3 : out std_logic;
FF_RX_D_1_4 : out std_logic;
FF_RX_D_1_5 : out std_logic;
FF_RX_D_1_6 : out std_logic;
FF_RX_D_1_7 : out std_logic;
FF_RX_D_1_8 : out std_logic;
FF_RX_D_1_9 : out std_logic;
FF_RX_D_1_10 : out std_logic;
FF_RX_D_1_11 : out std_logic;
FF_RX_D_1_12 : out std_logic;
FF_RX_D_1_13 : out std_logic;
FF_RX_D_1_14 : out std_logic;
FF_RX_D_1_15 : out std_logic;
FF_RX_D_1_16 : out std_logic;
FF_RX_D_1_17 : out std_logic;
FF_RX_D_1_18 : out std_logic;
FF_RX_D_1_19 : out std_logic;
FF_RX_D_1_20 : out std_logic;
FF_RX_D_1_21 : out std_logic;
FF_RX_D_1_22 : out std_logic;
FF_RX_D_1_23 : out std_logic;
FF_RX_D_2_0 : out std_logic;
FF_RX_D_2_1 : out std_logic;
FF_RX_D_2_2 : out std_logic;
FF_RX_D_2_3 : out std_logic;
FF_RX_D_2_4 : out std_logic;
FF_RX_D_2_5 : out std_logic;
FF_RX_D_2_6 : out std_logic;
FF_RX_D_2_7 : out std_logic;
FF_RX_D_2_8 : out std_logic;
FF_RX_D_2_9 : out std_logic;
FF_RX_D_2_10 : out std_logic;
FF_RX_D_2_11 : out std_logic;
FF_RX_D_2_12 : out std_logic;
FF_RX_D_2_13 : out std_logic;
FF_RX_D_2_14 : out std_logic;
FF_RX_D_2_15 : out std_logic;
FF_RX_D_2_16 : out std_logic;
FF_RX_D_2_17 : out std_logic;
FF_RX_D_2_18 : out std_logic;
FF_RX_D_2_19 : out std_logic;
FF_RX_D_2_20 : out std_logic;
FF_RX_D_2_21 : out std_logic;
FF_RX_D_2_22 : out std_logic;
FF_RX_D_2_23 : out std_logic;
FF_RX_D_3_0 : out std_logic;
FF_RX_D_3_1 : out std_logic;
FF_RX_D_3_2 : out std_logic;
FF_RX_D_3_3 : out std_logic;
FF_RX_D_3_4 : out std_logic;
FF_RX_D_3_5 : out std_logic;
FF_RX_D_3_6 : out std_logic;
FF_RX_D_3_7 : out std_logic;
FF_RX_D_3_8 : out std_logic;
FF_RX_D_3_9 : out std_logic;
FF_RX_D_3_10 : out std_logic;
FF_RX_D_3_11 : out std_logic;
FF_RX_D_3_12 : out std_logic;
FF_RX_D_3_13 : out std_logic;
FF_RX_D_3_14 : out std_logic;
FF_RX_D_3_15 : out std_logic;
FF_RX_D_3_16 : out std_logic;
FF_RX_D_3_17 : out std_logic;
FF_RX_D_3_18 : out std_logic;
FF_RX_D_3_19 : out std_logic;
FF_RX_D_3_20 : out std_logic;
FF_RX_D_3_21 : out std_logic;
FF_RX_D_3_22 : out std_logic;
FF_RX_D_3_23 : out std_logic;
FF_RX_F_CLK_0 : out std_logic;
FF_RX_F_CLK_1 : out std_logic;
FF_RX_F_CLK_2 : out std_logic;
FF_RX_F_CLK_3 : out std_logic;
FF_RX_H_CLK_0 : out std_logic;
FF_RX_H_CLK_1 : out std_logic;
FF_RX_H_CLK_2 : out std_logic;
FF_RX_H_CLK_3 : out std_logic;
FF_TX_F_CLK_0 : out std_logic;
FF_TX_F_CLK_1 : out std_logic;
FF_TX_F_CLK_2 : out std_logic;
FF_TX_F_CLK_3 : out std_logic;
FF_TX_H_CLK_0 : out std_logic;
FF_TX_H_CLK_1 : out std_logic;
FF_TX_H_CLK_2 : out std_logic;
FF_TX_H_CLK_3 : out std_logic;
FFS_CC_OVERRUN_0 : out std_logic;
FFS_CC_OVERRUN_1 : out std_logic;
FFS_CC_OVERRUN_2 : out std_logic;
FFS_CC_OVERRUN_3 : out std_logic;
FFS_CC_UNDERRUN_0 : out std_logic;
FFS_CC_UNDERRUN_1 : out std_logic;
FFS_CC_UNDERRUN_2 : out std_logic;
FFS_CC_UNDERRUN_3 : out std_logic;
FFS_LS_SYNC_STATUS_0 : out std_logic;
FFS_LS_SYNC_STATUS_1 : out std_logic;
FFS_LS_SYNC_STATUS_2 : out std_logic;
FFS_LS_SYNC_STATUS_3 : out std_logic;
FFS_CDR_TRAIN_DONE_0 : out std_logic;
FFS_CDR_TRAIN_DONE_1 : out std_logic;
FFS_CDR_TRAIN_DONE_2 : out std_logic;
FFS_CDR_TRAIN_DONE_3 : out std_logic;
FFS_PCIE_CON_0 : out std_logic;
FFS_PCIE_CON_1 : out std_logic;
FFS_PCIE_CON_2 : out std_logic;
FFS_PCIE_CON_3 : out std_logic;
FFS_PCIE_DONE_0 : out std_logic;
FFS_PCIE_DONE_1 : out std_logic;
FFS_PCIE_DONE_2 : out std_logic;
FFS_PCIE_DONE_3 : out std_logic;
FFS_PLOL : out std_logic;
FFS_RLOL_0 : out std_logic;
FFS_RLOL_1 : out std_logic;
FFS_RLOL_2 : out std_logic;
FFS_RLOL_3 : out std_logic;
FFS_RLOS_HI_0 : out std_logic;
FFS_RLOS_HI_1 : out std_logic;
FFS_RLOS_HI_2 : out std_logic;
FFS_RLOS_HI_3 : out std_logic;
FFS_RLOS_LO_0 : out std_logic;
FFS_RLOS_LO_1 : out std_logic;
FFS_RLOS_LO_2 : out std_logic;
FFS_RLOS_LO_3 : out std_logic;
FFS_RXFBFIFO_ERROR_0 : out std_logic;
FFS_RXFBFIFO_ERROR_1 : out std_logic;
FFS_RXFBFIFO_ERROR_2 : out std_logic;
FFS_RXFBFIFO_ERROR_3 : out std_logic;
FFS_TXFBFIFO_ERROR_0 : out std_logic;
FFS_TXFBFIFO_ERROR_1 : out std_logic;
FFS_TXFBFIFO_ERROR_2 : out std_logic;
FFS_TXFBFIFO_ERROR_3 : out std_logic;
PCIE_PHYSTATUS_0 : out std_logic;
PCIE_PHYSTATUS_1 : out std_logic;
PCIE_PHYSTATUS_2 : out std_logic;
PCIE_PHYSTATUS_3 : out std_logic;
PCIE_RXVALID_0 : out std_logic;
PCIE_RXVALID_1 : out std_logic;
PCIE_RXVALID_2 : out std_logic;
PCIE_RXVALID_3 : out std_logic;
FFS_SKP_ADDED_0 : out std_logic;
FFS_SKP_ADDED_1 : out std_logic;
FFS_SKP_ADDED_2 : out std_logic;
FFS_SKP_ADDED_3 : out std_logic;
FFS_SKP_DELETED_0 : out std_logic;
FFS_SKP_DELETED_1 : out std_logic;
FFS_SKP_DELETED_2 : out std_logic;
FFS_SKP_DELETED_3 : out std_logic;
LDR_RX2CORE_0 : out std_logic;
LDR_RX2CORE_1 : out std_logic;
LDR_RX2CORE_2 : out std_logic;
LDR_RX2CORE_3 : out std_logic;
REFCK2CORE : out std_logic;
SCIINT : out std_logic;
SCIRDATA0 : out std_logic;
SCIRDATA1 : out std_logic;
SCIRDATA2 : out std_logic;
SCIRDATA3 : out std_logic;
SCIRDATA4 : out std_logic;
SCIRDATA5 : out std_logic;
SCIRDATA6 : out std_logic;
SCIRDATA7 : out std_logic;
REFCLK_TO_NQ : out std_logic
);
end component;
attribute CONFIG_FILE: string;
attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
attribute QUAD_MODE: string;
attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
attribute PLL_SRC: string;
attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
attribute CH0_CDR_SRC: string;
attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_EXT";
attribute CH1_CDR_SRC: string;
attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_EXT";
attribute CH2_CDR_SRC: string;
attribute CH2_CDR_SRC of PCSD_INST : label is "REFCLK_EXT";
attribute CH3_CDR_SRC: string;
attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_EXT";
attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000";
attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "250.000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "125.000";
attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "150.000";
attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "150.000";
attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "150.000";
attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "150.000";
attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "75.0000";
attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "75.0000";
attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "75.0000";
attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "75.0000";
attribute FREQUENCY_PIN_REFCK2CORE: string;
attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "150.0";
attribute black_box_pad_pin: string;
attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
signal refclk_from_nq : std_logic := '0';
signal fpsc_vlo : std_logic := '0';
signal fpsc_vhi : std_logic := '1';
signal cin : std_logic_vector (11 downto 0) := "000000000000";
signal cout : std_logic_vector (19 downto 0);
signal tx_full_clk_ch0_sig : std_logic;
signal tx_full_clk_ch1_sig : std_logic;
signal tx_full_clk_ch2_sig : std_logic;
signal tx_full_clk_ch3_sig : std_logic;
signal refclk2fpga_sig : std_logic;
signal tx_pll_lol_qd_sig : std_logic;
signal rx_los_low_ch0_sig : std_logic;
signal rx_los_low_ch1_sig : std_logic;
signal rx_los_low_ch2_sig : std_logic;
signal rx_los_low_ch3_sig : std_logic;
signal rx_cdr_lol_ch0_sig : std_logic;
signal rx_cdr_lol_ch1_sig : std_logic;
signal rx_cdr_lol_ch2_sig : std_logic;
signal rx_cdr_lol_ch3_sig : std_logic;
signal refclkdiv2_tx_ch : std_logic;
signal tx_pcs_rst_ch_c : std_logic;
signal rst_qd_c : std_logic;
begin
vlo_inst : VLO port map(Z => fpsc_vlo);
vhi_inst : VHI port map(Z => fpsc_vhi);
refclk2fpga <= refclk2fpga_sig;
tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
tx_full_clk_ch2 <= tx_full_clk_ch2_sig;
tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
-- pcs_quad instance
PCSD_INST : PCSD
--synopsys translate_off
generic map (CONFIG_FILE => USER_CONFIG_FILE,
QUAD_MODE => "SINGLE",
CH0_CDR_SRC => "REFCLK_EXT",
CH1_CDR_SRC => "REFCLK_EXT",
CH2_CDR_SRC => "REFCLK_EXT",
CH3_CDR_SRC => "REFCLK_EXT",
PLL_SRC => "REFCLK_CORE"
)
--synopsys translate_on
port map (
REFCLKP => fpsc_vlo,
REFCLKN => fpsc_vlo,
----- CH0 -----
HDOUTP0 => hdoutp_ch0,
HDOUTN0 => hdoutn_ch0,
HDINP0 => fpsc_vlo,
HDINN0 => fpsc_vlo,
PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
PCIE_RXPOLARITY_0 => fpsc_vlo,
PCIE_POWERDOWN_0_0 => fpsc_vlo,
PCIE_POWERDOWN_0_1 => fpsc_vlo,
PCIE_RXVALID_0 => open,
PCIE_PHYSTATUS_0 => open,
SCISELCH0 => sci_sel_ch0,
SCIENCH0 => fpsc_vhi,
FF_RXI_CLK_0 => fpsc_vlo,
FF_TXI_CLK_0 => txiclk_ch0,
FF_EBRD_CLK_0 => fpsc_vlo,
FF_RX_F_CLK_0 => open,
FF_RX_H_CLK_0 => open,
FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
FF_TX_H_CLK_0 => tx_half_clk_ch0,
FFC_CK_CORE_RX_0 => fpsc_vlo,
FF_TX_D_0_0 => txdata_ch0(0),
FF_TX_D_0_1 => txdata_ch0(1),
FF_TX_D_0_2 => txdata_ch0(2),
FF_TX_D_0_3 => txdata_ch0(3),
FF_TX_D_0_4 => txdata_ch0(4),
FF_TX_D_0_5 => txdata_ch0(5),
FF_TX_D_0_6 => txdata_ch0(6),
FF_TX_D_0_7 => txdata_ch0(7),
FF_TX_D_0_8 => txdata_ch0(8),
FF_TX_D_0_9 => txdata_ch0(9),
FF_TX_D_0_10 => fpsc_vlo,
FF_TX_D_0_11 => fpsc_vlo,
FF_TX_D_0_12 => fpsc_vlo,
FF_TX_D_0_13 => fpsc_vlo,
FF_TX_D_0_14 => fpsc_vlo,
FF_TX_D_0_15 => fpsc_vlo,
FF_TX_D_0_16 => fpsc_vlo,
FF_TX_D_0_17 => fpsc_vlo,
FF_TX_D_0_18 => fpsc_vlo,
FF_TX_D_0_19 => fpsc_vlo,
FF_TX_D_0_20 => fpsc_vlo,
FF_TX_D_0_21 => fpsc_vlo,
FF_TX_D_0_22 => fpsc_vlo,
FF_TX_D_0_23 => fpsc_vlo,
FF_RX_D_0_0 => open,
FF_RX_D_0_1 => open,
FF_RX_D_0_2 => open,
FF_RX_D_0_3 => open,
FF_RX_D_0_4 => open,
FF_RX_D_0_5 => open,
FF_RX_D_0_6 => open,
FF_RX_D_0_7 => open,
FF_RX_D_0_8 => open,
FF_RX_D_0_9 => open,
FF_RX_D_0_10 => open,
FF_RX_D_0_11 => open,
FF_RX_D_0_12 => open,
FF_RX_D_0_13 => open,
FF_RX_D_0_14 => open,
FF_RX_D_0_15 => open,
FF_RX_D_0_16 => open,
FF_RX_D_0_17 => open,
FF_RX_D_0_18 => open,
FF_RX_D_0_19 => open,
FF_RX_D_0_20 => open,
FF_RX_D_0_21 => open,
FF_RX_D_0_22 => open,
FF_RX_D_0_23 => open,
FFC_RRST_0 => fpsc_vlo,
FFC_SIGNAL_DETECT_0 => fpsc_vlo,
FFC_SB_PFIFO_LP_0 => fpsc_vlo,
FFC_PFIFO_CLR_0 => fpsc_vlo,
FFC_SB_INV_RX_0 => fpsc_vlo,
FFC_PCIE_CT_0 => fpsc_vlo,
FFC_PCI_DET_EN_0 => fpsc_vlo,
FFC_FB_LOOPBACK_0 => fpsc_vlo,
FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
FFC_EI_EN_0 => fpsc_vlo,
FFC_LANE_TX_RST_0 => tx_pcs_rst_ch_c,
FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
FFC_LANE_RX_RST_0 => fpsc_vlo,
FFC_RXPWDNB_0 => fpsc_vlo,
FFS_RLOS_LO_0 => open,
FFS_RLOS_HI_0 => open,
FFS_PCIE_CON_0 => open,
FFS_PCIE_DONE_0 => open,
FFS_LS_SYNC_STATUS_0 => open,
FFS_CC_OVERRUN_0 => open,
FFS_CC_UNDERRUN_0 => open,
FFS_SKP_ADDED_0 => open,
FFS_SKP_DELETED_0 => open,
FFS_RLOL_0 => open,
FFS_RXFBFIFO_ERROR_0 => open,
FFS_TXFBFIFO_ERROR_0 => open,
LDR_CORE2TX_0 => fpsc_vlo,
FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
LDR_RX2CORE_0 => open,
FFS_CDR_TRAIN_DONE_0 => open,
FFC_DIV11_MODE_TX_0 => fpsc_vlo,
FFC_RATE_MODE_TX_0 => tx_div2_mode_ch0_c,
FFC_DIV11_MODE_RX_0 => fpsc_vlo,
FFC_RATE_MODE_RX_0 => fpsc_vlo,
----- CH1 -----
HDOUTP1 => hdoutp_ch1,
HDOUTN1 => hdoutn_ch1,
HDINP1 => fpsc_vlo,
HDINN1 => fpsc_vlo,
PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
PCIE_RXPOLARITY_1 => fpsc_vlo,
PCIE_POWERDOWN_1_0 => fpsc_vlo,
PCIE_POWERDOWN_1_1 => fpsc_vlo,
PCIE_RXVALID_1 => open,
PCIE_PHYSTATUS_1 => open,
SCISELCH1 => sci_sel_ch1,
SCIENCH1 => fpsc_vhi,
FF_RXI_CLK_1 => fpsc_vlo,
FF_TXI_CLK_1 => txiclk_ch1,
FF_EBRD_CLK_1 => fpsc_vlo,
FF_RX_F_CLK_1 => open,
FF_RX_H_CLK_1 => open,
FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
FF_TX_H_CLK_1 => tx_half_clk_ch1,
FFC_CK_CORE_RX_1 => fpsc_vlo,
FF_TX_D_1_0 => txdata_ch1(0),
FF_TX_D_1_1 => txdata_ch1(1),
FF_TX_D_1_2 => txdata_ch1(2),
FF_TX_D_1_3 => txdata_ch1(3),
FF_TX_D_1_4 => txdata_ch1(4),
FF_TX_D_1_5 => txdata_ch1(5),
FF_TX_D_1_6 => txdata_ch1(6),
FF_TX_D_1_7 => txdata_ch1(7),
FF_TX_D_1_8 => txdata_ch1(8),
FF_TX_D_1_9 => txdata_ch1(9),
FF_TX_D_1_10 => fpsc_vlo,
FF_TX_D_1_11 => fpsc_vlo,
FF_TX_D_1_12 => fpsc_vlo,
FF_TX_D_1_13 => fpsc_vlo,
FF_TX_D_1_14 => fpsc_vlo,
FF_TX_D_1_15 => fpsc_vlo,
FF_TX_D_1_16 => fpsc_vlo,
FF_TX_D_1_17 => fpsc_vlo,
FF_TX_D_1_18 => fpsc_vlo,
FF_TX_D_1_19 => fpsc_vlo,
FF_TX_D_1_20 => fpsc_vlo,
FF_TX_D_1_21 => fpsc_vlo,
FF_TX_D_1_22 => fpsc_vlo,
FF_TX_D_1_23 => fpsc_vlo,
FF_RX_D_1_0 => open,
FF_RX_D_1_1 => open,
FF_RX_D_1_2 => open,
FF_RX_D_1_3 => open,
FF_RX_D_1_4 => open,
FF_RX_D_1_5 => open,
FF_RX_D_1_6 => open,
FF_RX_D_1_7 => open,
FF_RX_D_1_8 => open,
FF_RX_D_1_9 => open,
FF_RX_D_1_10 => open,
FF_RX_D_1_11 => open,
FF_RX_D_1_12 => open,
FF_RX_D_1_13 => open,
FF_RX_D_1_14 => open,
FF_RX_D_1_15 => open,
FF_RX_D_1_16 => open,
FF_RX_D_1_17 => open,
FF_RX_D_1_18 => open,
FF_RX_D_1_19 => open,
FF_RX_D_1_20 => open,
FF_RX_D_1_21 => open,
FF_RX_D_1_22 => open,
FF_RX_D_1_23 => open,
FFC_RRST_1 => fpsc_vlo,
FFC_SIGNAL_DETECT_1 => fpsc_vlo,
FFC_SB_PFIFO_LP_1 => fpsc_vlo,
FFC_PFIFO_CLR_1 => fpsc_vlo,
FFC_SB_INV_RX_1 => fpsc_vlo,
FFC_PCIE_CT_1 => fpsc_vlo,
FFC_PCI_DET_EN_1 => fpsc_vlo,
FFC_FB_LOOPBACK_1 => fpsc_vlo,
FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
FFC_EI_EN_1 => fpsc_vlo,
FFC_LANE_TX_RST_1 => tx_pcs_rst_ch_c,
FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
FFC_LANE_RX_RST_1 => fpsc_vlo,
FFC_RXPWDNB_1 => fpsc_vlo,
FFS_RLOS_LO_1 => open,
FFS_RLOS_HI_1 => open,
FFS_PCIE_CON_1 => open,
FFS_PCIE_DONE_1 => open,
FFS_LS_SYNC_STATUS_1 => open,
FFS_CC_OVERRUN_1 => open,
FFS_CC_UNDERRUN_1 => open,
FFS_SKP_ADDED_1 => open,
FFS_SKP_DELETED_1 => open,
FFS_RLOL_1 => open,
FFS_RXFBFIFO_ERROR_1 => open,
FFS_TXFBFIFO_ERROR_1 => open,
LDR_CORE2TX_1 => fpsc_vlo,
FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
LDR_RX2CORE_1 => open,
FFS_CDR_TRAIN_DONE_1 => open,
FFC_DIV11_MODE_TX_1 => fpsc_vlo,
FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
FFC_DIV11_MODE_RX_1 => fpsc_vlo,
FFC_RATE_MODE_RX_1 => fpsc_vlo,
----- CH2 -----
HDOUTP2 => hdoutp_ch2,
HDOUTN2 => hdoutn_ch2,
HDINP2 => fpsc_vlo,
HDINN2 => fpsc_vlo,
PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
PCIE_RXPOLARITY_2 => fpsc_vlo,
PCIE_POWERDOWN_2_0 => fpsc_vlo,
PCIE_POWERDOWN_2_1 => fpsc_vlo,
PCIE_RXVALID_2 => open,
PCIE_PHYSTATUS_2 => open,
SCISELCH2 => sci_sel_ch2,
SCIENCH2 => fpsc_vhi,
FF_RXI_CLK_2 => fpsc_vlo,
FF_TXI_CLK_2 => txiclk_ch2,
FF_EBRD_CLK_2 => fpsc_vlo,
FF_RX_F_CLK_2 => open,
FF_RX_H_CLK_2 => open,
FF_TX_F_CLK_2 => tx_full_clk_ch2_sig,
FF_TX_H_CLK_2 => tx_half_clk_ch2,
FFC_CK_CORE_RX_2 => fpsc_vlo,
FF_TX_D_2_0 => txdata_ch2(0),
FF_TX_D_2_1 => txdata_ch2(1),
FF_TX_D_2_2 => txdata_ch2(2),
FF_TX_D_2_3 => txdata_ch2(3),
FF_TX_D_2_4 => txdata_ch2(4),
FF_TX_D_2_5 => txdata_ch2(5),
FF_TX_D_2_6 => txdata_ch2(6),
FF_TX_D_2_7 => txdata_ch2(7),
FF_TX_D_2_8 => txdata_ch2(8),
FF_TX_D_2_9 => txdata_ch2(9),
FF_TX_D_2_10 => fpsc_vlo,
FF_TX_D_2_11 => fpsc_vlo,
FF_TX_D_2_12 => fpsc_vlo,
FF_TX_D_2_13 => fpsc_vlo,
FF_TX_D_2_14 => fpsc_vlo,
FF_TX_D_2_15 => fpsc_vlo,
FF_TX_D_2_16 => fpsc_vlo,
FF_TX_D_2_17 => fpsc_vlo,
FF_TX_D_2_18 => fpsc_vlo,
FF_TX_D_2_19 => fpsc_vlo,
FF_TX_D_2_20 => fpsc_vlo,
FF_TX_D_2_21 => fpsc_vlo,
FF_TX_D_2_22 => fpsc_vlo,
FF_TX_D_2_23 => fpsc_vlo,
FF_RX_D_2_0 => open,
FF_RX_D_2_1 => open,
FF_RX_D_2_2 => open,
FF_RX_D_2_3 => open,
FF_RX_D_2_4 => open,
FF_RX_D_2_5 => open,
FF_RX_D_2_6 => open,
FF_RX_D_2_7 => open,
FF_RX_D_2_8 => open,
FF_RX_D_2_9 => open,
FF_RX_D_2_10 => open,
FF_RX_D_2_11 => open,
FF_RX_D_2_12 => open,
FF_RX_D_2_13 => open,
FF_RX_D_2_14 => open,
FF_RX_D_2_15 => open,
FF_RX_D_2_16 => open,
FF_RX_D_2_17 => open,
FF_RX_D_2_18 => open,
FF_RX_D_2_19 => open,
FF_RX_D_2_20 => open,
FF_RX_D_2_21 => open,
FF_RX_D_2_22 => open,
FF_RX_D_2_23 => open,
FFC_RRST_2 => fpsc_vlo,
FFC_SIGNAL_DETECT_2 => fpsc_vlo,
FFC_SB_PFIFO_LP_2 => fpsc_vlo,
FFC_PFIFO_CLR_2 => fpsc_vlo,
FFC_SB_INV_RX_2 => fpsc_vlo,
FFC_PCIE_CT_2 => fpsc_vlo,
FFC_PCI_DET_EN_2 => fpsc_vlo,
FFC_FB_LOOPBACK_2 => fpsc_vlo,
FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
FFC_EI_EN_2 => fpsc_vlo,
FFC_LANE_TX_RST_2 => tx_pcs_rst_ch_c,
FFC_TXPWDNB_2 => tx_pwrup_ch2_c,
FFC_LANE_RX_RST_2 => fpsc_vlo,
FFC_RXPWDNB_2 => fpsc_vlo,
FFS_RLOS_LO_2 => open,
FFS_RLOS_HI_2 => open,
FFS_PCIE_CON_2 => open,
FFS_PCIE_DONE_2 => open,
FFS_LS_SYNC_STATUS_2 => open,
FFS_CC_OVERRUN_2 => open,
FFS_CC_UNDERRUN_2 => open,
FFS_SKP_ADDED_2 => open,
FFS_SKP_DELETED_2 => open,
FFS_RLOL_2 => open,
FFS_RXFBFIFO_ERROR_2 => open,
FFS_TXFBFIFO_ERROR_2 => open,
LDR_CORE2TX_2 => fpsc_vlo,
FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
LDR_RX2CORE_2 => open,
FFS_CDR_TRAIN_DONE_2 => open,
FFC_DIV11_MODE_TX_2 => fpsc_vlo,
FFC_RATE_MODE_TX_2 => tx_div2_mode_ch2_c,
FFC_DIV11_MODE_RX_2 => fpsc_vlo,
FFC_RATE_MODE_RX_2 => fpsc_vlo,
----- CH3 -----
HDOUTP3 => hdoutp_ch3,
HDOUTN3 => hdoutn_ch3,
HDINP3 => fpsc_vlo,
HDINN3 => fpsc_vlo,
PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
PCIE_RXPOLARITY_3 => fpsc_vlo,
PCIE_POWERDOWN_3_0 => fpsc_vlo,
PCIE_POWERDOWN_3_1 => fpsc_vlo,
PCIE_RXVALID_3 => open,
PCIE_PHYSTATUS_3 => open,
SCISELCH3 => sci_sel_ch3,
SCIENCH3 => fpsc_vhi,
FF_RXI_CLK_3 => fpsc_vlo,
FF_TXI_CLK_3 => txiclk_ch3,
FF_EBRD_CLK_3 => fpsc_vlo,
FF_RX_F_CLK_3 => open,
FF_RX_H_CLK_3 => open,
FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
FF_TX_H_CLK_3 => tx_half_clk_ch3,
FFC_CK_CORE_RX_3 => fpsc_vlo,
FF_TX_D_3_0 => txdata_ch3(0),
FF_TX_D_3_1 => txdata_ch3(1),
FF_TX_D_3_2 => txdata_ch3(2),
FF_TX_D_3_3 => txdata_ch3(3),
FF_TX_D_3_4 => txdata_ch3(4),
FF_TX_D_3_5 => txdata_ch3(5),
FF_TX_D_3_6 => txdata_ch3(6),
FF_TX_D_3_7 => txdata_ch3(7),
FF_TX_D_3_8 => txdata_ch3(8),
FF_TX_D_3_9 => txdata_ch3(9),
FF_TX_D_3_10 => fpsc_vlo,
FF_TX_D_3_11 => fpsc_vlo,
FF_TX_D_3_12 => fpsc_vlo,
FF_TX_D_3_13 => fpsc_vlo,
FF_TX_D_3_14 => fpsc_vlo,
FF_TX_D_3_15 => fpsc_vlo,
FF_TX_D_3_16 => fpsc_vlo,
FF_TX_D_3_17 => fpsc_vlo,
FF_TX_D_3_18 => fpsc_vlo,
FF_TX_D_3_19 => fpsc_vlo,
FF_TX_D_3_20 => fpsc_vlo,
FF_TX_D_3_21 => fpsc_vlo,
FF_TX_D_3_22 => fpsc_vlo,
FF_TX_D_3_23 => fpsc_vlo,
FF_RX_D_3_0 => open,
FF_RX_D_3_1 => open,
FF_RX_D_3_2 => open,
FF_RX_D_3_3 => open,
FF_RX_D_3_4 => open,
FF_RX_D_3_5 => open,
FF_RX_D_3_6 => open,
FF_RX_D_3_7 => open,
FF_RX_D_3_8 => open,
FF_RX_D_3_9 => open,
FF_RX_D_3_10 => open,
FF_RX_D_3_11 => open,
FF_RX_D_3_12 => open,
FF_RX_D_3_13 => open,
FF_RX_D_3_14 => open,
FF_RX_D_3_15 => open,
FF_RX_D_3_16 => open,
FF_RX_D_3_17 => open,
FF_RX_D_3_18 => open,
FF_RX_D_3_19 => open,
FF_RX_D_3_20 => open,
FF_RX_D_3_21 => open,
FF_RX_D_3_22 => open,
FF_RX_D_3_23 => open,
FFC_RRST_3 => fpsc_vlo,
FFC_SIGNAL_DETECT_3 => fpsc_vlo,
FFC_SB_PFIFO_LP_3 => fpsc_vlo,
FFC_PFIFO_CLR_3 => fpsc_vlo,
FFC_SB_INV_RX_3 => fpsc_vlo,
FFC_PCIE_CT_3 => fpsc_vlo,
FFC_PCI_DET_EN_3 => fpsc_vlo,
FFC_FB_LOOPBACK_3 => fpsc_vlo,
FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
FFC_EI_EN_3 => fpsc_vlo,
FFC_LANE_TX_RST_3 => tx_pcs_rst_ch_c,
FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
FFC_LANE_RX_RST_3 => fpsc_vlo,
FFC_RXPWDNB_3 => fpsc_vlo,
FFS_RLOS_LO_3 => open,
FFS_RLOS_HI_3 => open,
FFS_PCIE_CON_3 => open,
FFS_PCIE_DONE_3 => open,
FFS_LS_SYNC_STATUS_3 => open,
FFS_CC_OVERRUN_3 => open,
FFS_CC_UNDERRUN_3 => open,
FFS_SKP_ADDED_3 => open,
FFS_SKP_DELETED_3 => open,
FFS_RLOL_3 => open,
FFS_RXFBFIFO_ERROR_3 => open,
FFS_TXFBFIFO_ERROR_3 => open,
LDR_CORE2TX_3 => fpsc_vlo,
FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
LDR_RX2CORE_3 => open,
FFS_CDR_TRAIN_DONE_3 => open,
FFC_DIV11_MODE_TX_3 => fpsc_vlo,
FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
FFC_DIV11_MODE_RX_3 => fpsc_vlo,
FFC_RATE_MODE_RX_3 => fpsc_vlo,
----- Auxilliary ----
SCIWDATA7 => sci_wrdata(7),
SCIWDATA6 => sci_wrdata(6),
SCIWDATA5 => sci_wrdata(5),
SCIWDATA4 => sci_wrdata(4),
SCIWDATA3 => sci_wrdata(3),
SCIWDATA2 => sci_wrdata(2),
SCIWDATA1 => sci_wrdata(1),
SCIWDATA0 => sci_wrdata(0),
SCIADDR5 => sci_addr(5),
SCIADDR4 => sci_addr(4),
SCIADDR3 => sci_addr(3),
SCIADDR2 => sci_addr(2),
SCIADDR1 => sci_addr(1),
SCIADDR0 => sci_addr(0),
SCIRDATA7 => sci_rddata(7),
SCIRDATA6 => sci_rddata(6),
SCIRDATA5 => sci_rddata(5),
SCIRDATA4 => sci_rddata(4),
SCIRDATA3 => sci_rddata(3),
SCIRDATA2 => sci_rddata(2),
SCIRDATA1 => sci_rddata(1),
SCIRDATA0 => sci_rddata(0),
SCIENAUX => fpsc_vhi,
SCISELAUX => sci_sel_quad,
SCIRD => sci_rd,
SCIWSTN => sci_wrn,
CYAWSTN => fpsc_vlo,
SCIINT => sci_int,
FFC_CK_CORE_TX => fpga_txrefclk,
FFC_MACRO_RST => serdes_rst_qd_c,
FFC_QUAD_RST => rst_qd_c,
FFC_TRST => tx_serdes_rst_c,
FFS_PLOL => tx_pll_lol_qd_sig,
FFC_SYNC_TOGGLE => tx_sync_qd_c,
REFCK2CORE => refclk2fpga_sig,
CIN0 => fpsc_vlo,
CIN1 => fpsc_vlo,
CIN2 => fpsc_vlo,
CIN3 => fpsc_vlo,
CIN4 => fpsc_vlo,
CIN5 => fpsc_vlo,
CIN6 => fpsc_vlo,
CIN7 => fpsc_vlo,
CIN8 => fpsc_vlo,
CIN9 => fpsc_vlo,
CIN10 => fpsc_vlo,
CIN11 => fpsc_vlo,
COUT0 => open,
COUT1 => open,
COUT2 => open,
COUT3 => open,
COUT4 => open,
COUT5 => open,
COUT6 => open,
COUT7 => open,
COUT8 => open,
COUT9 => open,
COUT10 => open,
COUT11 => open,
COUT12 => open,
COUT13 => open,
COUT14 => open,
COUT15 => open,
COUT16 => open,
COUT17 => open,
COUT18 => open,
COUT19 => open,
REFCLK_FROM_NQ => refclk_from_nq,
REFCLK_TO_NQ => open);
P5 : PROCESS(fpga_txrefclk, rst_n)
BEGIN
IF (rst_n = '0') THEN
refclkdiv2_tx_ch <= '0';
ELSIF (fpga_txrefclk'event and fpga_txrefclk = '1') THEN
refclkdiv2_tx_ch <= not refclkdiv2_tx_ch;
END IF;
END PROCESS;
-- reset sequence for tx
tx_reset_sm_ch : hdmi_pcstx_reset_sm
--synopsys translate_off
generic map (count_index => 4)
--synopsys translate_on
port map (
rst_n => rst_n,
refclkdiv2 => refclkdiv2_tx_ch,
tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
rst_qd_c => rst_qd_c,
tx_pcs_rst_ch_c => tx_pcs_rst_ch_c
);
--synopsys translate_off
file_read : PROCESS
VARIABLE open_status : file_open_status;
FILE config : text;
BEGIN
file_open (open_status, config, USER_CONFIG_FILE, read_mode);
IF (open_status = name_error) THEN
report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!"
severity ERROR;
END IF;
wait;
END PROCESS;
--synopsys translate_on
end hdmi_pcs_arch ;
|
<reponame>PacoReinaCampo/MPSoC-DBG<filename>rtl/pu/riscv/vhdl/ahb3/ahb3/mpsoc_dbg_ahb3_biu.vhd
-- Converted from rtl/verilog/ahb3/mpsoc_dbg_ahb3_biu.sv
-- by verilog2vhdl - QueenField
--//////////////////////////////////////////////////////////////////////////////
-- __ _ _ _ //
-- / _(_) | | | | //
-- __ _ _ _ ___ ___ _ __ | |_ _ ___| | __| | //
-- / _` | | | |/ _ \/ _ \ '_ \| _| |/ _ \ |/ _` | //
-- | (_| | |_| | __/ __/ | | | | | | __/ | (_| | //
-- \__, |\__,_|\___|\___|_| |_|_| |_|\___|_|\__,_| //
-- | | //
-- |_| //
-- //
-- //
-- MPSoC-RISCV CPU //
-- Degub Interface //
-- AMBA3 AHB-Lite Bus Interface //
-- //
--//////////////////////////////////////////////////////////////////////////////
-- Copyright (c) 2018-2019 by the author(s)
-- *
-- * Permission is hereby granted, free of charge, to any person obtaining a copy
-- * of this software and associated documentation files (the "Software"), to deal
-- * in the Software without restriction, including without limitation the rights
-- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- * copies of the Software, and to permit persons to whom the Software is
-- * furnished to do so, subject to the following conditions:
-- *
-- * The above copyright notice and this permission notice shall be included in
-- * all copies or substantial portions of the Software.
-- *
-- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- * THE SOFTWARE.
-- *
-- * =============================================================================
-- * Author(s):
-- * <NAME> <<EMAIL>>
-- * <NAME> <<EMAIL>>
-- */
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mpsoc_dbg_pkg.all;
entity mpsoc_dbg_ahb3_biu is
generic (
LITTLE_ENDIAN : std_logic := '1';
ADDR_WIDTH : integer := 32;
DATA_WIDTH : integer := 32
);
port (
-- Debug interface signals
biu_clk : in std_logic;
biu_rst : in std_logic;
biu_di : in std_logic_vector(DATA_WIDTH-1 downto 0);
biu_do : out std_logic_vector(DATA_WIDTH-1 downto 0);
biu_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
biu_strb : in std_logic;
biu_rw : in std_logic;
biu_rdy : out std_logic;
biu_err : out std_logic;
biu_word_size : in std_logic_vector(3 downto 0);
-- AHB Master signals
HCLK : in std_logic;
HRESETn : in std_logic;
HSEL : out std_logic;
HADDR : out std_logic_vector(ADDR_WIDTH-1 downto 0);
HWDATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
HRDATA : in std_logic_vector(DATA_WIDTH-1 downto 0);
HWRITE : out std_logic;
HSIZE : out std_logic_vector(2 downto 0);
HBURST : out std_logic_vector(2 downto 0);
HPROT : out std_logic_vector(3 downto 0);
HTRANS : out std_logic_vector(1 downto 0);
HMASTLOCK : out std_logic;
HREADY : in std_logic;
HRESP : in std_logic
);
end mpsoc_dbg_ahb3_biu;
architecture RTL of mpsoc_dbg_ahb3_biu is
--////////////////////////////////////////////////////////////////
--
-- Constants
--
constant IDLE : std_logic_vector(1 downto 0) := "10";
constant ADDRESS : std_logic_vector(1 downto 0) := "01";
constant DATA : std_logic_vector(1 downto 0) := "00";
--////////////////////////////////////////////////////////////////
--
-- Variables
--
signal data_out_reg : std_logic_vector(DATA_WIDTH-1 downto 0); -- AHB->dbg
signal str_sync : std_logic; -- This is 'active-toggle' rather than -high or -low.
signal rdy_sync : std_logic; -- ditto, active-toggle
-- Sync registers. TFF indicates TCK domain, AFF indicates AHB domain
signal ahb_rstn_sync : std_logic_vector(1 downto 0);
signal ahb_rstn : std_logic;
signal rdy_sync_tff1 : std_logic;
signal rdy_sync_tff2 : std_logic;
signal rdy_sync_tff2q : std_logic; -- used to detect toggles
signal str_sync_aff1 : std_logic;
signal str_sync_aff2 : std_logic;
signal str_sync_aff2q : std_logic; -- used to detect toggles
-- Internal signals
signal start_toggle : std_logic; -- AHB domain, indicates a toggle on the start strobe
signal start_toggle_hold : std_logic; -- hold start_toggle if AHB bus busy (not-ready)
signal ahb_transfer_ack : std_logic; -- AHB bus responded to data transfer
--AHB FSM
signal ahb_fsm_state : std_logic_vector(1 downto 0);
signal biu_rdy_sgn : std_logic;
signal HADDR_SGN : std_logic_vector(ADDR_WIDTH-1 downto 0);
begin
--////////////////////////////////////////////////////////////////
--
-- Module Body
--
--////////////////////////////////////////////////////
-- TCK clock domain
--
-- There is no FSM here, just signal latching and clock domain synchronization
-- Create byte enable signals from word_size and address
processing_0 : process (biu_clk)
begin
if (rising_edge(biu_clk)) then
if (biu_strb = '1' and biu_rdy_sgn = '1') then
case ((biu_word_size)) is
when X"1" =>
HSIZE <= HSIZE_BYTE;
when X"2" =>
HSIZE <= HSIZE_HWORD;
when X"4" =>
HSIZE <= HSIZE_WORD;
when others =>
HSIZE <= HSIZE_DWORD;
end case;
end if;
end if;
end process;
generating_0 : if (DATA_WIDTH = 32) generate
processing_1 : process (biu_clk)
begin
if (rising_edge(biu_clk)) then
if (biu_strb = '1' and biu_rdy_sgn = '1') then
case ((biu_word_size)) is
when X"1" =>
HWDATA <= (biu_di(31 downto 31-8+1) & biu_di(31 downto 31-8+1) &
biu_di(31 downto 31-8+1) & biu_di(31 downto 31-8+1));
when X"2" =>
HWDATA <= (biu_di(31 downto 31-16+1) & biu_di(31 downto 31-16+1));
when others =>
HWDATA <= biu_di;
end case;
end if;
end if;
end process;
elsif (DATA_WIDTH = 64) generate
processing_2 : process (biu_clk)
begin
if (rising_edge(biu_clk)) then
if (biu_strb = '1' and biu_rdy_sgn = '1') then
case ((biu_word_size)) is
when X"1" =>
HWDATA <= (biu_di(63 downto 63-8+1) & biu_di(63 downto 63-8+1) &
biu_di(63 downto 63-8+1) & biu_di(63 downto 63-8+1) &
biu_di(63 downto 63-8+1) & biu_di(63 downto 63-8+1) &
biu_di(63 downto 63-8+1) & biu_di(63 downto 63-8+1));
when X"2" =>
HWDATA <= (biu_di(63 downto 63-16+1) & biu_di(63 downto 63-16+1) &
biu_di(63 downto 63-16+1) & biu_di(63 downto 63-16+1));
when X"4" =>
HWDATA <= (biu_di(63 downto 63-32+1) & biu_di(63 downto 63-32+1));
when others =>
HWDATA <= biu_di;
end case;
end if;
end if;
end process;
end generate;
-- Latch input data on 'start' strobe, if ready.
processing_3 : process (biu_clk, biu_rst)
begin
if (biu_rst = '1') then
HADDR_SGN <= X"0";
HWRITE <= '0';
elsif (rising_edge(biu_clk)) then
if (biu_strb = '1' and biu_rdy_sgn = '1') then
HADDR_SGN <= biu_addr;
HWRITE <= not biu_rw;
end if;
end if;
end process;
HADDR <= HADDR_SGN;
-- Create toggle-active strobe signal for clock sync. This will start a transaction
-- on the AHB once the toggle propagates to the FSM in the AHB domain.
processing_4 : process (biu_clk, biu_rst)
begin
if (biu_rst = '1') then
str_sync <= '0';
elsif (rising_edge(biu_clk)) then
if (biu_strb = '1' and biu_rdy_sgn = '1') then
str_sync <= not str_sync;
end if;
end if;
end process;
-- Create biu_rdy output. Set on reset, clear on strobe (if set), set on input toggle
processing_5 : process (biu_clk, biu_rst)
begin
if (biu_rst = '1') then
rdy_sync_tff1 <= '0';
rdy_sync_tff2 <= '0';
rdy_sync_tff2q <= '0';
biu_rdy_sgn <= '1';
elsif (rising_edge(biu_clk)) then
rdy_sync_tff1 <= rdy_sync; -- Synchronize the ready signal across clock domains
rdy_sync_tff2 <= rdy_sync_tff1;
rdy_sync_tff2q <= rdy_sync_tff2; -- used to detect toggles
if (biu_strb = '1' and biu_rdy_sgn = '1') then
biu_rdy_sgn <= '0';
elsif (rdy_sync_tff2 /= rdy_sync_tff2q) then
biu_rdy_sgn <= '1';
end if;
end if;
end process;
biu_rdy <= biu_rdy_sgn;
--/////////////////////////////////////////////////////
-- AHB clock domain
--
-- synchronize asynchronous active high reset
processing_6 : process (HCLK, biu_rst)
begin
if (biu_rst = '1') then
ahb_rstn_sync <= (others => '0');
elsif (rising_edge(HCLK)) then
ahb_rstn_sync <= ('1' & ahb_rstn_sync(1));
end if;
end process;
ahb_rstn <= not (not HRESETn or not ahb_rstn_sync(0));
-- synchronize the start strobe
processing_7 : process (HCLK, ahb_rstn)
begin
if (ahb_rstn = '0') then
str_sync_aff1 <= '0';
str_sync_aff2 <= '0';
str_sync_aff2q <= '0';
elsif (rising_edge(HCLK)) then
str_sync_aff1 <= str_sync;
str_sync_aff2 <= str_sync_aff1;
str_sync_aff2q <= str_sync_aff2; -- used to detect toggles
end if;
end process;
start_toggle <= to_stdlogic(str_sync_aff2 /= str_sync_aff2q);
processing_8 : process (HCLK, ahb_rstn)
begin
if (ahb_rstn = '0') then
start_toggle_hold <= '0';
elsif (rising_edge(HCLK)) then
start_toggle_hold <= not ahb_transfer_ack and (start_toggle or start_toggle_hold);
end if;
end process;
-- Bus Error register
processing_9 : process (HCLK, ahb_rstn)
begin
if (ahb_rstn = '0') then
biu_err <= '0';
elsif (rising_edge(HCLK)) then
if (ahb_transfer_ack = '1') then
biu_err <= HRESP;
end if;
end if;
end process;
-- Received data register
generating_1 : if (DATA_WIDTH = 32) generate
processing_10 : process (HCLK)
variable state_haddr_b : std_logic_vector(1 downto 0);
variable state_haddr_d : std_logic;
begin
if (rising_edge(HCLK)) then
if (ahb_transfer_ack = '1') then
case ((biu_word_size)) is
when X"1" =>
case (state_haddr_b) is
when "00" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"000000" & HRDATA(7 downto 7-8+1));
else
biu_do <= (X"000000" & HRDATA(31 downto 31-8+1));
end if;
when "01" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"000000" & HRDATA(15 downto 15-8+1));
else
biu_do <= (X"000000" & HRDATA(23 downto 23-8+1));
end if;
when "10" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"000000" & HRDATA(23 downto 23-8+1));
else
biu_do <= (X"000000" & HRDATA(15 downto 15-8+1));
end if;
when "11" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"000000" & HRDATA(31 downto 31-8+1));
else
biu_do <= (X"000000" & HRDATA(7 downto 7-8+1));
end if;
when others =>
null;
end case;
when X"2" =>
case (state_haddr_d) is
when '0' =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"00000000" & HRDATA(15 downto 15-16+1));
else
biu_do <= (X"00000000" & HRDATA(31 downto 31-16+1));
end if;
when '1' =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"00000000" & HRDATA(31 downto 31-16+1));
else
biu_do <= (X"00000000" & HRDATA(15 downto 15-16+1));
end if;
when others =>
null;
end case;
when others =>
biu_do <= HRDATA;
end case;
end if;
end if;
state_haddr_b := HADDR_SGN(1 downto 0);
state_haddr_d := HADDR_SGN(1);
end process;
elsif (DATA_WIDTH = 64) generate
processing_11 : process (HCLK)
variable state_haddr_a : std_logic_vector(2 downto 0);
variable state_haddr_c : std_logic_vector(1 downto 0);
variable state_haddr_e : std_logic;
begin
if (rising_edge(HCLK)) then
if (ahb_transfer_ack = '1') then
case ((biu_word_size)) is
when X"1" =>
case (state_haddr_a) is
when "000" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"00000000000000" & HRDATA(7 downto 7-8+1));
else
biu_do <= (X"00000000000000" & HRDATA(63 downto 63-8+1));
end if;
when "001" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"00000000000000" & HRDATA(15 downto 15-8+1));
else
biu_do <= (X"00000000000000" & HRDATA(55 downto 55-8+1));
end if;
when "010" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"00000000000000" & HRDATA(23 downto 23-8+1));
else
biu_do <= (X"00000000000000" & HRDATA(47 downto 47-8+1));
end if;
when "011" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"00000000000000" & HRDATA(31 downto 31-8+1));
else
biu_do <= (X"00000000000000" & HRDATA(39 downto 39-8+1));
end if;
when "100" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"00000000000000" & HRDATA(39 downto 39-8+1));
else
biu_do <= (X"00000000000000" & HRDATA(31 downto 31-8+1));
end if;
when "101" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"00000000000000" & HRDATA(47 downto 47-8+1));
else
biu_do <= (X"00000000000000" & HRDATA(23 downto 23-8+1));
end if;
when "110" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"00000000000000" & HRDATA(55 downto 55-8+1));
else
biu_do <= (X"00000000000000" & HRDATA(15 downto 15-8+1));
end if;
when "111" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"00000000000000" & HRDATA(63 downto 63-8+1));
else
biu_do <= (X"00000000000000" & HRDATA(7 downto 7-8+1));
end if;
when others =>
null;
end case;
when X"2" =>
case (state_haddr_c) is
when "00" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"000000000000" & HRDATA(15 downto 15-16+1));
else
biu_do <= (X"000000000000" & HRDATA(63 downto 63-16+1));
end if;
when "01" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"000000000000" & HRDATA(31 downto 31-16+1));
else
biu_do <= (X"000000000000" & HRDATA(47 downto 47-16+1));
end if;
when "10" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"000000000000" & HRDATA(47 downto 47-16+1));
else
biu_do <= (X"000000000000" & HRDATA(31 downto 31-16+1));
end if;
when "11" =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"000000000000" & HRDATA(63 downto 63-16+1));
else
biu_do <= (X"000000000000" & HRDATA(15 downto 15-16+1));
end if;
when others =>
null;
end case;
when X"4" =>
case (state_haddr_e) is
when '0' =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"00000000" & HRDATA(31 downto 31-32+1));
else
biu_do <= (X"0000" & HRDATA(63 downto 63-32+1));
end if;
when '1' =>
if (LITTLE_ENDIAN = '1') then
biu_do <= (X"00000000" & HRDATA(63 downto 63-32+1));
else
biu_do <= (X"0000" & HRDATA(31 downto 31-32+1));
end if;
when others =>
null;
end case;
when others =>
biu_do <= HRDATA;
end case;
end if;
end if;
state_haddr_a := HADDR_SGN(2 downto 0);
state_haddr_c := HADDR_SGN(2 downto 1);
state_haddr_e := HADDR_SGN(2);
end process;
end generate;
-- Create a toggle-active ready signal to send to the TCK domain
processing_12 : process (HCLK, ahb_rstn)
begin
if (ahb_rstn = '0') then
rdy_sync <= '0';
elsif (rising_edge(HCLK)) then
if (ahb_transfer_ack = '1') then
rdy_sync <= not rdy_sync;
end if;
end if;
end process;
-- State machine to create AHB accesses
ahb_transfer_ack <= HREADY and to_stdlogic(ahb_fsm_state = DATA);
HSEL <= '1';
HPROT <= HPROT_DATA or HPROT_PRIVILEGED or HPROT_NON_BUFFERABLE or HPROT_NON_CACHEABLE;
HMASTLOCK <= '0';
processing_13 : process (HCLK, ahb_rstn)
begin
if (ahb_rstn = '0') then
HTRANS <= HTRANS_IDLE;
ahb_fsm_state <= IDLE;
elsif (rising_edge(HCLK)) then
case ((ahb_fsm_state)) is
when IDLE =>
if (start_toggle = '1' or start_toggle_hold = '1') then
HTRANS <= HTRANS_NONSEQ;
ahb_fsm_state <= ADDRESS;
end if;
when ADDRESS =>
HTRANS <= HTRANS_IDLE;
ahb_fsm_state <= DATA;
when DATA =>
if (HREADY = '1') then
ahb_fsm_state <= IDLE;
end if;
when others =>
HTRANS <= HTRANS_IDLE;
ahb_fsm_state <= IDLE;
end case;
end if;
end process;
--Only single accesses; no bursts
HBURST <= HBURST_SINGLE;
end RTL;
|
<gh_stars>0
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.03.2021 20:51:07
-- Design Name:
-- Module Name: tb_t_ff_rst - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_t_ff_rst is
-- Port ( );
end tb_t_ff_rst;
architecture Behavioral of tb_t_ff_rst is
constant c_CLK_100MHZ_PERIOD : time := 10 ns;
signal s_clk_100MHz : std_logic;
signal s_rst : std_logic;
signal s_t : std_logic;
signal s_q : std_logic;
signal s_q_bar : std_logic;
begin
uut_t_ff_rst : entity work.t_ff_rst
port map(
clk => s_clk_100MHz,
rst => s_rst,
t => s_t,
q => s_q,
q_bar => s_q_bar
);
p_clk_gen : process
begin
while now < 750 ns loop -- 75 periods of 100MHz clock
s_clk_100MHz <= '0';
wait for c_CLK_100MHZ_PERIOD / 2;
s_clk_100MHz <= '1';
wait for c_CLK_100MHZ_PERIOD / 2;
end loop;
wait; -- Process is suspended forever
end process p_clk_gen;
p_rst_gen : process
begin
s_rst <= '0';
wait for 10ns; -- 10ns
s_rst <= '1';
wait for 10 ns; -- 20ns
s_rst <= '0';
wait for 73 ns; -- 93ns
s_rst <= '1';
wait;
end process p_rst_gen;
p_stimulus : process
begin
report "Stimulus process started" severity note;
wait for 23 ns; -- 23ns
s_t <= '1'; -- toggle 0 -> 1
wait for 10 ns; -- 33ns
s_t <= '0'; -- no change 1 -> 1
wait for 10 ns; -- 43ns
s_t <= '1'; -- toggle 1 -> 0
wait for 10 ns; -- 53ns
s_t <= '0'; -- no change 0 -> 0
wait for 10 ns; -- 63ns
s_t <= '1'; -- keep toggling forever
report "Stimulus process end" severity note;
wait;
end process p_stimulus;
p_assert_gen : process
begin
report "Assert generation started" severity note;
wait for 27 ns; -- 27ns
assert(s_clk_100MHz = '1' and s_rst = '0' and s_t = '1' and s_q = '1' and s_q_bar = '0') report "Test error" severity error;
wait for 10 ns; -- 37ns
assert(s_clk_100MHz = '1' and s_rst = '0' and s_t = '0' and s_q = '1' and s_q_bar = '0') report "Test error" severity error;
wait for 10 ns; -- 47ns
assert(s_clk_100MHz = '1' and s_rst = '0' and s_t = '1' and s_q = '0' and s_q_bar = '1') report "Test error" severity error;
wait for 10 ns; -- 57ns
assert(s_clk_100MHz = '1' and s_rst = '0' and s_t = '0' and s_q = '0' and s_q_bar = '1') report "Test error" severity error;
report "Assert generation end" severity note;
wait;
end process p_assert_gen;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:20:56 08/07/2020
-- Design Name:
-- Module Name: ripple_carry_adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ripple_carry_adder is
Port ( x : in STD_LOGIC_VECTOR (31 downto 0);
y : in STD_LOGIC_VECTOR (31 downto 0);
s_out : out STD_LOGIC_VECTOR (31 downto 0);
cout : out STD_LOGIC_VECTOR (31 downto 0);
cin : in STD_LOGIC );
end ripple_carry_adder;
architecture Behavioral of ripple_carry_adder is
component fulladder
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
signal s_port : STD_LOGIC_VECTOR (31 downto 0);
signal c_port : STD_LOGIC_VECTOR (31 downto 0);
begin
fa : fulladder port map (a=> x(0), b=> y(0), cin => cin, s=>s_port(0), cout => c_port(0));
loop1 : for n in 1 to 31 generate
fa1: fulladder port map ( a=> x(n), b=> y(n), cin => c_port(n-1), s => s_port(n), cout => c_port(n));
end generate loop1;
cout <= c_port;
s_out <= s_port;
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity mux32bit_2_1 is
port(
result : out vl_logic_vector(31 downto 0);
S0 : in vl_logic;
I1 : in vl_logic_vector(31 downto 0);
I0 : in vl_logic_vector(31 downto 0)
);
end mux32bit_2_1;
|
<reponame>SabaFathi/SteganographyCryptography_VHDL<filename>codes/generic_buffer_testbench.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY generic_buffer_testbench IS
END generic_buffer_testbench;
ARCHITECTURE behavior OF generic_buffer_testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT generic_buffer
generic(input_size : integer := 8;
output_size : integer := 8;
buffer_size : integer := 256);
port(data_in : in std_logic_vector(0 to input_size-1);
input_enable : in std_logic;
output_enable : in std_logic;
reset : in std_logic;
clk_in : in std_logic;
clk_out: in std_logic;
data_out : out std_logic_vector(0 to output_size-1);
full : out std_logic;
empty : out std_logic );
END COMPONENT;
--Inputs
signal data_in_1bit : std_logic_vector(0 to 0) := "0";
signal data_in_2bit : std_logic_vector(0 to 1) := "00";
signal data_in_3bit : std_logic_vector(0 to 2) := "000";
signal input_enable : std_logic := '0';
signal output_enable : std_logic := '0';
signal reset : std_logic := '0';
signal clk_in : std_logic := '0';
signal clk_out : std_logic := '0';
--Outputs
signal data_out_uut1 : std_logic_vector(0 to 2);
signal full_uut1 : std_logic;
signal empty_uut1 : std_logic;
signal data_out_uut2 : std_logic_vector(0 to 1);
signal full_uut2 : std_logic;
signal empty_uut2 : std_logic;
signal data_out_uut3 : std_logic_vector(0 to 1);
signal full_uut3 : std_logic;
signal empty_uut3 : std_logic;
signal data_out_uut4 : std_logic_vector(0 to 2);
signal full_uut4 : std_logic;
signal empty_uut4 : std_logic;
signal data_out_uut5 : std_logic_vector(0 to 0);
signal full_uut5 : std_logic;
signal empty_uut5 : std_logic;
constant data_test_allzero : std_logic_vector(0 to 3) := "0000";
constant data_test_allone : std_logic_vector(0 to 3) := "1111";
constant data_test_nopattern : std_logic_vector(0 to 53) := "100001110111001010001110110100101111000001100110110101";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut1: generic_buffer
GENERIC MAP(
input_size => 3,
output_size => 3,
buffer_size => 11
)
PORT MAP(
data_in => data_in_3bit,
input_enable => input_enable,
output_enable => output_enable,
reset => reset,
clk_in => clk_in,
clk_out => clk_out,
data_out => data_out_uut1,
full => full_uut1,
empty => empty_uut1
);
uut2: generic_buffer
GENERIC MAP(
input_size => 2,
output_size => 2,
buffer_size => 8
)
PORT MAP(
data_in => data_in_2bit,
input_enable => input_enable,
output_enable => output_enable,
reset => reset,
clk_in => clk_in,
clk_out => clk_out,
data_out => data_out_uut2,
full => full_uut2,
empty => empty_uut2
);
uut3: generic_buffer
GENERIC MAP(
input_size => 3,
output_size => 2,
buffer_size => 9
)
PORT MAP(
data_in => data_in_3bit,
input_enable => input_enable,
output_enable => output_enable,
reset => reset,
clk_in => clk_in,
clk_out => clk_out,
data_out => data_out_uut3,
full => full_uut3,
empty => empty_uut3
);
uut4: generic_buffer
GENERIC MAP(
input_size => 2,
output_size => 3,
buffer_size => 9
)
PORT MAP(
data_in => data_in_2bit,
input_enable => input_enable,
output_enable => output_enable,
reset => reset,
clk_in => clk_in,
clk_out => clk_out,
data_out => data_out_uut4,
full => full_uut4,
empty => empty_uut4
);
uut5: generic_buffer
GENERIC MAP(
input_size => 1,
output_size => 1,
buffer_size => 8
)
PORT MAP(
data_in => data_in_1bit,
input_enable => input_enable,
output_enable => output_enable,
reset => reset,
clk_in => clk_in,
clk_out => clk_out,
data_out => data_out_uut5,
full => full_uut5,
empty => empty_uut5
);
clk_in <= not clk_in after 5 ns;
clk_out <= not clk_out after 5 ns;
reset <= '0' after 0 ns, '1' after 260 ns;
input_enable <= '1' after 0 ns , '0' after 90 ns, '1' after 180 ns;
output_enable <= '0' after 0 ns, '1' after 90 ns;
--data_in_1bit <= data_test_allone(0 to 0);
--data_in_2bit <= data_test_allone(0 to 1);
--data_in_3bit <= data_test_allone(0 to 2);
data_in_1bit <= data_test_nopattern(0 to 0) after 0 ns,
data_test_nopattern(1 to 1) after 10 ns,
data_test_nopattern(2 to 2) after 20 ns,
data_test_nopattern(3 to 3) after 30 ns,
data_test_nopattern(4 to 4) after 40 ns,
data_test_nopattern(5 to 5) after 50 ns,
data_test_nopattern(6 to 6) after 60 ns,
data_test_nopattern(7 to 7) after 70 ns,
data_test_nopattern(8 to 8) after 80 ns,
data_test_nopattern(9 to 9) after 90 ns,
data_test_nopattern(10 to 10) after 180 ns,
data_test_nopattern(11 to 11) after 190 ns,
data_test_nopattern(12 to 12) after 200 ns,
data_test_nopattern(13 to 13) after 210 ns,
data_test_nopattern(14 to 14) after 220 ns,
data_test_nopattern(15 to 15) after 230 ns,
data_test_nopattern(16 to 16) after 240 ns,
data_test_nopattern(17 to 17) after 250 ns;
data_in_2bit <= data_test_nopattern(0 to 1) after 0 ns,
data_test_nopattern(2 to 3) after 10 ns,
data_test_nopattern(4 to 5) after 20 ns,
data_test_nopattern(6 to 7) after 30 ns,
data_test_nopattern(8 to 9) after 40 ns,
data_test_nopattern(10 to 11) after 50 ns,
data_test_nopattern(12 to 13) after 60 ns,
data_test_nopattern(14 to 15) after 70 ns,
data_test_nopattern(16 to 17) after 80 ns,
data_test_nopattern(18 to 19) after 90 ns,
data_test_nopattern(20 to 21) after 180 ns,
data_test_nopattern(22 to 23) after 190 ns,
data_test_nopattern(24 to 25) after 200 ns,
data_test_nopattern(26 to 27) after 210 ns,
data_test_nopattern(28 to 29) after 220 ns,
data_test_nopattern(30 to 31) after 230 ns,
data_test_nopattern(32 to 33) after 240 ns,
data_test_nopattern(34 to 35) after 250 ns;
data_in_3bit <= data_test_nopattern(0 to 2) after 0 ns,
data_test_nopattern(3 to 5) after 10 ns,
data_test_nopattern(6 to 8) after 20 ns,
data_test_nopattern(9 to 11) after 30 ns,
data_test_nopattern(12 to 14) after 40 ns,
data_test_nopattern(15 to 17) after 50 ns,
data_test_nopattern(18 to 20) after 60 ns,
data_test_nopattern(21 to 23) after 70 ns,
data_test_nopattern(24 to 26) after 80 ns,
data_test_nopattern(27 to 29) after 90 ns,
data_test_nopattern(30 to 32) after 180 ns,
data_test_nopattern(33 to 35) after 190 ns,
data_test_nopattern(36 to 38) after 200 ns,
data_test_nopattern(39 to 41) after 210 ns,
data_test_nopattern(42 to 44) after 220 ns,
data_test_nopattern(45 to 47) after 230 ns,
data_test_nopattern(48 to 50) after 240 ns,
data_test_nopattern(51 to 53) after 250 ns;
--expected : uut1
----data_out :
----full :
----empty :
END;
|
<reponame>ukalla1/direct-mapped-cache-memory
library STD;
library ieee;
use ieee.std_logic_1164.all;
entity and3 is
port ( input1, input2, input3: in std_logic;
output : out std_logic);
end and3;
architecture structural of and3 is
begin
output <= input1 and input2 and input3;
end structural;
|
<filename>VHDL/SIMON_CIPHER_TB.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:00:46 10/04/2015
-- Design Name:
-- Module Name: D:/Work/Code/Simon_Speck_Ciphers/VHDL/SIMON_CIPHER_TB.vhd
-- Project Name: Simon
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SIMON_CIPHER
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.SIMON_CONSTANTS.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY SIMON_CIPHER_TB IS
END SIMON_CIPHER_TB;
ARCHITECTURE behavior OF SIMON_CIPHER_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SIMON_CIPHER
GENERIC(KEY_SIZE : integer range 0 to 256;
BLOCK_SIZE : integer range 0 to 128;
ROUND_LIMIT: integer range 0 to 72);
PORT(
SYS_CLK : IN std_logic;
RST : IN std_logic;
BUSY : OUT std_logic;
CONTROL : IN std_logic_vector(1 downto 0);
KEY : IN std_logic_vector(KEY_SIZE - 1 downto 0);
BLOCK_INPUT : IN std_logic_vector(BLOCK_SIZE - 1 downto 0);
BLOCK_OUTPUT : OUT std_logic_vector(BLOCK_SIZE - 1 downto 0)
);
END COMPONENT;
--Global Inputs
signal SYS_CLK : std_logic := '0';
signal RST : std_logic := '0';
signal CONTROL : std_logic_vector(1 downto 0) := (others => '0');
--UUT 1
signal KEY_1 : std_logic_vector(63 downto 0) := (others => '0');
signal BLOCK_INPUT_1 : std_logic_vector(31 downto 0) := (others => '0');
signal BUSY_1 : std_logic;
signal BLOCK_OUTPUT_1 : std_logic_vector(31 downto 0);
--UUT 2
signal KEY_2 : std_logic_vector(71 downto 0) := (others => '0');
signal BLOCK_INPUT_2 : std_logic_vector(47 downto 0) := (others => '0');
signal BUSY_2 : std_logic;
signal BLOCK_OUTPUT_2 : std_logic_vector(47 downto 0);
--UUT 3
signal KEY_3 : std_logic_vector(95 downto 0) := (others => '0');
signal BLOCK_INPUT_3 : std_logic_vector(47 downto 0) := (others => '0');
signal BUSY_3 : std_logic;
signal BLOCK_OUTPUT_3 : std_logic_vector(47 downto 0);
--UUT 4
signal KEY_4 : std_logic_vector(95 downto 0) := (others => '0');
signal BLOCK_INPUT_4 : std_logic_vector(63 downto 0) := (others => '0');
signal BUSY_4 : std_logic;
signal BLOCK_OUTPUT_4 : std_logic_vector(63 downto 0);
--UUT 5
signal KEY_5 : std_logic_vector(127 downto 0) := (others => '0');
signal BLOCK_INPUT_5 : std_logic_vector(63 downto 0) := (others => '0');
signal BUSY_5 : std_logic;
signal BLOCK_OUTPUT_5 : std_logic_vector(63 downto 0);
--UUT 6
signal KEY_6 : std_logic_vector(95 downto 0) := (others => '0');
signal BLOCK_INPUT_6 : std_logic_vector(95 downto 0) := (others => '0');
signal BUSY_6 : std_logic;
signal BLOCK_OUTPUT_6 : std_logic_vector(95 downto 0);
--UUT 7
signal KEY_7 : std_logic_vector(143 downto 0) := (others => '0');
signal BLOCK_INPUT_7 : std_logic_vector(95 downto 0) := (others => '0');
signal BUSY_7 : std_logic;
signal BLOCK_OUTPUT_7 : std_logic_vector(95 downto 0);
--UUT 8
signal KEY_8 : std_logic_vector(127 downto 0) := (others => '0');
signal BLOCK_INPUT_8 : std_logic_vector(127 downto 0) := (others => '0');
signal BUSY_8 : std_logic;
signal BLOCK_OUTPUT_8 : std_logic_vector(127 downto 0);
--UUT 9
signal KEY_9 : std_logic_vector(191 downto 0) := (others => '0');
signal BLOCK_INPUT_9 : std_logic_vector(127 downto 0) := (others => '0');
signal BUSY_9 : std_logic;
signal BLOCK_OUTPUT_9 : std_logic_vector(127 downto 0);
--UUT 10
signal KEY_10 : std_logic_vector(255 downto 0) := (others => '0');
signal BLOCK_INPUT_10 : std_logic_vector(127 downto 0) := (others => '0');
signal BUSY_10 : std_logic;
signal BLOCK_OUTPUT_10 : std_logic_vector(127 downto 0);
-- Clock period definitions
constant SYS_CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut_1: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 64,
BLOCK_SIZE => 32,
ROUND_LIMIT => Round_Count_Lookup(64, 32))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_1,
CONTROL => CONTROL,
KEY => KEY_1,
BLOCK_INPUT => BLOCK_INPUT_1,
BLOCK_OUTPUT => BLOCK_OUTPUT_1
);
uut_2: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 72,
BLOCK_SIZE => 48,
ROUND_LIMIT => Round_Count_Lookup(72, 48))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_2,
CONTROL => CONTROL,
KEY => KEY_2,
BLOCK_INPUT => BLOCK_INPUT_2,
BLOCK_OUTPUT => BLOCK_OUTPUT_2
);
uut_3: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 96,
BLOCK_SIZE => 48,
ROUND_LIMIT => Round_Count_Lookup(96, 48))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_3,
CONTROL => CONTROL,
KEY => KEY_3,
BLOCK_INPUT => BLOCK_INPUT_3,
BLOCK_OUTPUT => BLOCK_OUTPUT_3
);
uut_4: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 96,
BLOCK_SIZE => 64,
ROUND_LIMIT => Round_Count_Lookup(96, 64))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_4,
CONTROL => CONTROL,
KEY => KEY_4,
BLOCK_INPUT => BLOCK_INPUT_4,
BLOCK_OUTPUT => BLOCK_OUTPUT_4
);
uut_5: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 128,
BLOCK_SIZE => 64,
ROUND_LIMIT => Round_Count_Lookup(128, 64))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_5,
CONTROL => CONTROL,
KEY => KEY_5,
BLOCK_INPUT => BLOCK_INPUT_5,
BLOCK_OUTPUT => BLOCK_OUTPUT_5
);
uut_6: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 96,
BLOCK_SIZE => 96,
ROUND_LIMIT => Round_Count_Lookup(96, 96))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_6,
CONTROL => CONTROL,
KEY => KEY_6,
BLOCK_INPUT => BLOCK_INPUT_6,
BLOCK_OUTPUT => BLOCK_OUTPUT_6
);
uut_7: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 144,
BLOCK_SIZE => 96,
ROUND_LIMIT => Round_Count_Lookup(144, 96))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_7,
CONTROL => CONTROL,
KEY => KEY_7,
BLOCK_INPUT => BLOCK_INPUT_7,
BLOCK_OUTPUT => BLOCK_OUTPUT_7
);
uut_8: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 128,
BLOCK_SIZE => 128,
ROUND_LIMIT => Round_Count_Lookup(128, 128))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_8,
CONTROL => CONTROL,
KEY => KEY_8,
BLOCK_INPUT => BLOCK_INPUT_8,
BLOCK_OUTPUT => BLOCK_OUTPUT_8
);
uut_9: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 192,
BLOCK_SIZE => 128,
ROUND_LIMIT => Round_Count_Lookup(192, 128))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_9,
CONTROL => CONTROL,
KEY => KEY_9,
BLOCK_INPUT => BLOCK_INPUT_9,
BLOCK_OUTPUT => BLOCK_OUTPUT_9
);
uut_10: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 256,
BLOCK_SIZE => 128,
ROUND_LIMIT => Round_Count_Lookup(256, 128))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_10,
CONTROL => CONTROL,
KEY => KEY_10,
BLOCK_INPUT => BLOCK_INPUT_10,
BLOCK_OUTPUT => BLOCK_OUTPUT_10
);
-- Clock process definitions
SYS_CLK_process :process
begin
SYS_CLK <= '0';
wait for SYS_CLK_period/2;
SYS_CLK <= '1';
wait for SYS_CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for SYS_CLK_period*10;
KEY_1 <= X"1918111009080100";
KEY_2 <= X"1211100a0908020100";
KEY_3 <= X"<KEY>";
KEY_4 <= X"131211100b0a090803020100";
KEY_5 <= X"1b1a1918131211100b0a090803020100";
KEY_6 <= X"<KEY>";
KEY_7 <= X"<KEY>";
KEY_8 <= X"0f0e0d0c0b0a09080706050403020100";
KEY_9 <= X"17161514131211100f0e0d0c0b0a09080706050403020100";
KEY_10 <= X"1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050403020100";
CONTROL <= "01";
wait for SYS_CLK_period*3;
CONTROL <= "00";
wait for SYS_CLK_period*100;
BLOCK_INPUT_1 <= X"65656877";
BLOCK_INPUT_2 <= X"6120676e696c";
BLOCK_INPUT_3 <= X"72696320646e";
BLOCK_INPUT_4 <= X"6f7220676e696c63";
BLOCK_INPUT_5 <= X"656b696c20646e75";
BLOCK_INPUT_6 <= X"2072616c6c69702065687420";
BLOCK_INPUT_7 <= X"74616874207473756420666f";
BLOCK_INPUT_8 <= X"63736564207372656c6c657661727420";
BLOCK_INPUT_9 <= X"206572656874206e6568772065626972";
BLOCK_INPUT_10 <= X"74206e69206d6f6f6d69732061207369";
CONTROL <= "11";
wait for SYS_CLK_period*3;
CONTROL <= "00";
wait for SYS_CLK_period*100;
assert BLOCK_OUTPUT_1 /= X"c69be9bb" report "UUT1 Encryption Success" severity note;
assert BLOCK_OUTPUT_1 = X"c69be9bb" report "UUT1 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_2 /= X"dae5ac292cac" report "UUT2 Encryption Success" severity note;
assert BLOCK_OUTPUT_2 = X"dae5ac292cac" report "UUT2 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_3 /= X"6e06a5acf156" report "UUT3 Encryption Success" severity note;
assert BLOCK_OUTPUT_3 = X"6e06a5acf156" report "UUT3 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_4 /= X"5ca2e27f111a8fc8" report "UUT4 Encryption Success" severity note;
assert BLOCK_OUTPUT_4 = X"5ca2e27f111a8fc8" report "UUT4 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_5 /= X"44c8fc20b9dfa07a" report "UUT5 Encryption Success" severity note;
assert BLOCK_OUTPUT_5 = X"44c8fc20b9dfa07a" report "UUT5 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_6 /= X"602807a462b469063d8ff082" report "UUT6 Encryption Success" severity note;
assert BLOCK_OUTPUT_6 = X"602807a462b469063d8ff082" report "UUT6 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_7 /= X"ecad1c6c451e3f59c5db1ae9" report "UUT7 Encryption Success" severity note;
assert BLOCK_OUTPUT_7 = X"ecad1c6c451e3f59c5db1ae9" report "UUT7 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_8 /= X"49681b1e1e54fe3f65aa832af84e0bbc" report "UUT8 Encryption Success" severity note;
assert BLOCK_OUTPUT_8 = X"49681b1e1e54fe3f65aa832af84e0bbc" report "UUT8 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_9 /= X"c4ac61effcdc0d4f6c9c8d6e2597b85b" report "UUT9 Encryption Success" severity note;
assert BLOCK_OUTPUT_9 = X"c4ac61effcdc0d4f6c9c8d6e2597b85b" report "UUT9 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_10 /= X"8d2b5579afc8a3a03bf72a87efe7b868" report "UUT10 Encryption Success" severity note;
assert BLOCK_OUTPUT_10 = X"8d2b5579afc8a3a03bf72a87efe7b868" report "UUT10 Encryption Failed" severity failure;
BLOCK_INPUT_1 <= X"c69be9bb";
BLOCK_INPUT_2 <= X"dae5ac292cac";
BLOCK_INPUT_3 <= X"6e06a5acf156";
BLOCK_INPUT_4 <= X"5ca2e27f111a8fc8";
BLOCK_INPUT_5 <= X"44c8fc20b9dfa07a";
BLOCK_INPUT_6 <= X"602807a462b469063d8ff082";
BLOCK_INPUT_7 <= X"ecad1c6c451e3f59c5db1ae9";
BLOCK_INPUT_8 <= X"49681b1e1e54fe3f65aa832af84e0bbc";
BLOCK_INPUT_9 <= X"c4ac61effcdc0d4f6c9c8d6e2597b85b";
BLOCK_INPUT_10 <= X"8d2b5579afc8a3a03bf72a87efe7b868";
CONTROL <= "10";
wait for SYS_CLK_period*3;
CONTROL <= "00";
wait for SYS_CLK_period*100;
assert BLOCK_OUTPUT_1 /= X"65656877" report "UUT1 Decryption Success" severity note;
assert BLOCK_OUTPUT_1 = X"65656877" report "UUT1 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_2 /= X"6120676e696c" report "UUT2 Decryption Success" severity note;
assert BLOCK_OUTPUT_2 = X"6120676e696c" report "UUT2 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_3 /= X"72696320646e" report "UUT3 Decryption Success" severity note;
assert BLOCK_OUTPUT_3 = X"72696320646e" report "UUT3 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_4 /= X"6f7220676e696c63" report "UUT4 Decryption Success" severity note;
assert BLOCK_OUTPUT_4 = X"6f7220676e696c63" report "UUT4 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_5 /= X"656b696c20646e75" report "UUT5 Decryption Success" severity note;
assert BLOCK_OUTPUT_5 = X"656b696c20646e75" report "UUT5 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_6 /= X"2072616c6c69702065687420" report "UUT6 Decryption Success" severity note;
assert BLOCK_OUTPUT_6 = X"2072616c6c69702065687420" report "UUT6 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_7 /= X"74616874207473756420666f" report "UUT7 Decryption Success" severity note;
assert BLOCK_OUTPUT_7 = X"74616874207473756420666f" report "UUT7 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_8 /= X"63736564207372656c6c657661727420" report "UUT8 Decryption Success" severity note;
assert BLOCK_OUTPUT_8 = X"63736564207372656c6c657661727420" report "UUT8 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_9 /= X"206572656874206e6568772065626972" report "UUT9 Decryption Success" severity note;
assert BLOCK_OUTPUT_9 = X"206572656874206e6568772065626972" report "UUT9 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_10 /= X"74206e69206d6f6f6d69732061207369" report "UUT10 Decryption Success" severity note;
assert BLOCK_OUTPUT_10 = X"74206e69206d6f6f6d69732061207369" report "UUT10 Decryption Failed" severity failure;
-- insert stimulus here
wait;
end process;
END;
|
-- ------------------------------------------------------------------------
-- Copyright (C) 2010 <NAME>
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- End Of License.
-- ------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity kasumi is
port (
pt : in bit_vector ( 31 downto 0);
ldpt : in bit;
key : in bit_vector ( 63 downto 0);
ldk : in bit;
--probe
--L_prb : out bit_vector ( 31 downto 0);
--R_prb : out bit_vector ( 31 downto 0);
--FL_prb : out bit_vector ( 31 downto 0);
--ikey_prb : out bit_vector ( 15 downto 0);
--FO_prb : out bit_vector ( 15 downto 0);
--FI_prb : out bit_vector ( 15 downto 0);
--st_prb : out bit_vector ( 3 downto 0);
--rnd_prb : out bit_vector ( 1 downto 0);
--even_prb : out bit;
--probe
ct : out bit_vector ( 63 downto 0);
v : out bit;
clk : in bit;
rst : in bit
);
end kasumi;
architecture phy of kasumi is
signal ireg1 : bit_vector ( 63 downto 0);
signal ikey : bit_vector ( 15 downto 0);
signal ipt : bit_vector ( 31 downto 0);
signal iptt : bit_vector ( 31 downto 0);
signal r : bit_vector ( 31 downto 0);
signal l : bit_vector ( 31 downto 0);
signal ir : bit_vector ( 31 downto 0);
signal il : bit_vector ( 31 downto 0);
signal F : bit_vector ( 31 downto 0);
signal FL : bit_vector ( 31 downto 0);
signal FLl : bit_vector ( 15 downto 0);
signal FLr : bit_vector ( 15 downto 0);
signal FL0 : bit_vector ( 15 downto 0);
signal FL1 : bit_vector ( 15 downto 0);
signal LFL : bit_vector ( 15 downto 0);
signal RFL : bit_vector ( 15 downto 0);
signal FO : bit_vector ( 15 downto 0);
signal FI : bit_vector ( 15 downto 0);
signal x7a : bit_vector ( 6 downto 0);
signal x9a : bit_vector ( 8 downto 0);
signal x7b : bit_vector ( 6 downto 0);
signal x9b : bit_vector ( 8 downto 0);
signal y7a : bit_vector ( 6 downto 0);
signal y9a : bit_vector ( 8 downto 0);
signal y7b : bit_vector ( 6 downto 0);
signal y9b : bit_vector ( 8 downto 0);
signal st : bit_vector ( 3 downto 0); -- 16 states
signal c3b : bit_vector ( 2 downto 0);
signal c3b_cr : bit_vector ( 2 downto 0);
signal c3b_rst : bit;
signal rnd : bit_vector ( 1 downto 0);
signal rnd_cr : bit_vector ( 1 downto 0);
signal rnd_rst : bit;
signal even : bit;
signal vld : bit;
signal ildpt : bit;
signal ildpt_rst : bit;
signal ildptt : bit;
component sbox
port (
x7 : in bit_vector ( 6 downto 0);
x9 : in bit_vector ( 8 downto 0);
y7 : out bit_vector ( 6 downto 0);
y9 : out bit_vector ( 8 downto 0)
);
end component;
component keyschedule
port (
key : in bit_vector ( 63 downto 0);
st : in bit_vector ( 3 downto 0);
ldk : in bit;
rk : out bit_vector ( 15 downto 0);
clk : in bit;
rst : in bit
);
end component;
begin
s1 : sbox
port map (
x7 => x7a,
x9 => x9a,
y7 => y7a,
y9 => y9a
);
s2 : sbox
port map (
x7 => x7b,
x9 => x9b,
y7 => y7b,
y9 => y9b
);
roundkey : keyschedule
port map (
key => key,
st => st,
ldk => ldk,
rk => ikey,
clk => clk,
rst => rst
);
--probe
--L_prb <= l;
--R_prb <= r;
--ikey_prb <= ikey;
--FL_prb <= FL;
--FI_prb <= FI;
--FO_prb <= FO;
--st_prb <= st;
--rnd_prb <= rnd;
--even_prb <= even;
--probe
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
ildpt <= '0';
ildptt <= '0';
ipt <= (others => '0');
-- ikey <= (others => '0');
iptt <= (others => '0');
else
ildptt <= ldpt;
ildpt <= ildptt;
iptt <= pt;
ipt <= iptt;
-- ikey <= key;
end if;
end if;
end process;
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
even <= '0';
elsif (c3b = O"7") then
even <= not(even);
end if;
end if;
end process;
c3b_cr(0) <= '0'; -- LSB always zero
c3b_cr( 2 downto 1) <= ( ((c3b( 1 downto 0) and B"01") or (c3b( 1 downto 0) and c3b_cr( 1 downto 0))) or (B"01" and c3b_cr( 1 downto 0)) );
process (clk)
begin
if (clk = '1' and clk'event) then
if (c3b_rst = '1') then
c3b <= B"000";
else
c3b <= ((c3b xor B"001") xor c3b_cr);
end if;
end if;
end process;
ildpt_rst <= ((ildpt xor ildptt) and ildpt);
c3b_rst <= rst or ildpt_rst;
l <= ireg1( 63 downto 32);
r <= ireg1( 31 downto 0);
--0-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+
--1-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+
--2-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+
--3-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+
st <= even & c3b;
process (st,rst,FL,FO,FI,FL0,FL1,r)
begin
if (rst = '1') then
LFL <= (others => '0');
RFL <= (others => '0');
else
case st is
when X"0" =>
LFL <= FL(31 downto 16);
RFL <= FL0;
when X"1" =>
LFL <= FL1;
RFL <= FL(15 downto 0);
when X"2" =>
LFL <= FO;
RFL <= FL(15 downto 0);
when X"3" =>
LFL <= FL(15 downto 0);
RFL <= FI xor FL(15 downto 0);
when X"4" =>
LFL <= FO;
RFL <= FL(15 downto 0);
when X"5" =>
LFL <= FL(15 downto 0);
RFL <= FI xor FL(15 downto 0);
when X"6" =>
LFL <= FO;
RFL <= FL(15 downto 0);
when X"7" =>
LFL <= FL(15 downto 0) xor r(31 downto 16); -- xor R
RFL <= FI xor FL(15 downto 0) xor r(15 downto 0); -- xor R
when X"8" =>
LFL <= FO;
RFL <= FL(15 downto 0);
when X"9" =>
LFL <= FL(15 downto 0);
RFL <= FI xor FL(15 downto 0);
when X"a" =>
LFL <= FO;
RFL <= FL(15 downto 0);
when X"b" =>
LFL <= FL(15 downto 0);
RFL <= FI xor FL(15 downto 0);
when X"c" =>
LFL <= FO;
RFL <= FL(15 downto 0);
when X"d" =>
LFL <= FL(15 downto 0);
RFL <= FI xor FL(15 downto 0);
when X"e" =>
LFL <= FL(31 downto 16);
RFL <= FL0;
when X"f" =>
LFL <= FL1 xor r(31 downto 16); -- xor R
RFL <= FL(15 downto 0) xor r(15 downto 0); -- xor R
end case;
end if;
end process;
FLl <= l(31 downto 16) when even = '0' else FL(31 downto 16);
FLr <= l(15 downto 0) when even = '0' else FL(15 downto 0);
--FL(R') == FL(R) xor ROTL1{FL(L) and KLi1}
FL0 <= FLr xor ((FLl(14 downto 0) and ikey(14 downto 0)) & (FLl(15) and ikey(15)));
--FL(L') == FL(L) xor ROTL1{FL(R') or KLi2}
FL1 <= FLl xor ((FL (14 downto 0) or ikey(14 downto 0)) & (FL (15) or ikey(15)));
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
FL <= (others => '0');
else
FL <= LFL & RFL;
end if;
end if;
end process;
--FO == Lj-1 xor KOij
FO <= FL(31 downto 16) xor ikey(15 downto 0);
--FI-function
-- L1 == R0 R1 == S9[L0] xor ZE(R0)
-- L2 == R1 xor KIij2 R2 == S7[L1] xor TR(R1) xor KIij1
-- L3 == R2 R3 == S9[L2] xor ZE(R2)
-- L4 == S7[L3] xor TR(R3) R4 == R3
-- Return L4 || R4
--L0
x9a <= FL(31 downto 23);
--R0
x7a <= FL(22 downto 16);
--L2 == S9[L0] xor ZE (R0) xor KIi,j,2 (9 bit)
x9b <= y9a(8 downto 0) xor (B"00" & x7a) xor ikey( 8 downto 0);
--R2 == S7[L1] xor TR(R1) xor KIi,j,1 (7 bit)
x7b <= y7a xor y9a(6 downto 0) xor x7a xor ikey(15 downto 9);
--R3 == S9[L2] xor ZE (R2)
FI( 8 downto 0) <= y9b(8 downto 0) xor (B"00" & x7b);
--L4 == S7[L3] xor TR(R3)
FI(15 downto 9) <= y7b xor FI(6 downto 0);
--Rj == FI(Lj-1 xor KOij, KIij) xor Rj-1
il <= LFL & RFL;
--R' == Li-1
ir <= l;
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
ireg1 <= (others => '0');
elsif (ildpt = '1') then
ireg1 <= ireg1( 31 downto 0) & ipt;
elsif (c3b = O"7") then
ireg1(31 downto 0)<= ir;
ireg1(63 downto 32)<= il;
end if;
end if;
end process;
rnd_cr <= rnd(0) & '0';
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
rnd <= B"00";
elsif (st = X"f") then
rnd <= ((rnd xor B"01") xor rnd_cr);
end if;
end if;
end process;
process (clk)
begin
if ((clk = '1') and clk'event) then
if (rst = '1') then
vld <= '0';
elsif ((rnd & st) = B"111111") then
vld <= '1';
else
vld <= '0';
end if;
end if;
end process;
v <= vld;
ct <= l & r;
end phy;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY Rotation IS
PORT (
Input1, Input2 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Cin : IN STD_LOGIC;
Op : IN STD_LOGIC;
Output1 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
Cout : OUT STD_LOGIC);
END Rotation;
ARCHITECTURE Behavioral OF Rotation IS
-- Defining Signals
-- Input1 with Carry
SIGNAL Input1_C : STD_LOGIC_VECTOR (8 DOWNTO 0);
-- Output1 with Carry
SIGNAL Output1_C : STD_LOGIC_VECTOR (8 DOWNTO 0);
BEGIN
Input1_C <= Cin & Input1;
PROCESS (Input1, Input2, Op, Input1_C, Output1_C)
-- NumofPosVRL : Number of Position of Variable Rotation Left
VARIABLE NumofPosVRL : INTEGER;
-- NumofPosVRL : Number of Position of Variable Rotation Left with Carry
VARIABLE NumofPosVRLC : INTEGER;
BEGIN
-- Rotation is periodic with period 8.
NumofPosVRL := CONV_INTEGER(Input2) REM 8;
-- Rotation with carry is periodic with period 9.
NumofPosVRLC := CONV_INTEGER(Input2) REM 9;
-- Variable Rotation Left: Op = '0'
-- Variable Rotation Left with Carry: Op = '1'
-- Determining Output1 and Cout for Each Operation
IF Op = '0' THEN
IF NumofPosVRL = 0 THEN
Output1 <= Input1;
ELSE
Output1 <= Input1(7 - NumofPosVRL DOWNTO 0) & Input1(7 DOWNTO 8 - NumofPosVRL);
END IF;
Cout <= '0';
Output1_C <= (OTHERS => '0');
ELSE
IF NumofPosVRLC = 0 THEN
Output1_C <= Input1_C;
ELSE
Output1_C <= Input1_C(8 - NumofPosVRLC DOWNTO 0) & Input1_C(8 DOWNTO 9 - NumofPosVRLC);
END IF;
Output1 <= Output1_C(7 DOWNTO 0);
Cout <= Output1_C(8);
END IF;
END PROCESS;
END Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity memoria_programa is
generic (
m : integer := 9;
n : integer := 25
);
Port ( pc : in STD_LOGIC_VECTOR (m-1 downto 0);
inst : out STD_LOGIC_VECTOR (n-1 downto 0)
);
end entity;
architecture Behavioral of memoria_programa is
type arreglo is array (0 to (2**m - 1)) of STD_LOGIC_VECTOR (n-1 downto 0);
signal mem : arreglo := (others=>(others=>'0'));
constant code_LI : std_logic_vector (4 downto 0) := "00001";
constant code_LWI : std_logic_vector (4 downto 0) := "00010";
constant code_LW : std_logic_vector (4 downto 0) := "10111";
constant code_SW : std_logic_vector (4 downto 0) := "00100";
constant code_SWI : std_logic_vector (4 downto 0) := "00011";
constant code_ADDI : std_logic_vector (4 downto 0) := "00101";
constant code_BGTI : std_logic_vector (4 downto 0) := "10001";
constant code_BLTI : std_logic_vector (4 downto 0) := "01111";
constant code_BLETI : std_logic_vector (4 downto 0) := "10000";
constant code_BNEI : std_logic_vector (4 downto 0) := "01110";
constant code_NOP : std_logic_vector (4 downto 0) := "10110";
constant code_B : std_logic_vector (4 downto 0) := "10011";
constant code_fun : std_logic_vector (4 downto 0) := "00000";
constant fun_ADD : std_logic_vector (3 downto 0) := "0000";
constant SU : std_logic_vector (3 downto 0) := "0000";
constant R0 : std_logic_vector (3 downto 0) := "0000";
constant R1 : std_logic_vector (3 downto 0) := "0001";
constant R2 : std_logic_vector (3 downto 0) := "0010";
constant R3 : std_logic_vector (3 downto 0) := "0011";
constant R4 : std_logic_vector (3 downto 0) := "0100";
constant R5 : std_logic_vector (3 downto 0) := "0101";
constant R6 : std_logic_vector (3 downto 0) := "0110";
constant R7 : std_logic_vector (3 downto 0) := "0111";
begin
--Inicializar arreglo
mem(0) <= code_LI & R0 & x"0000"; -- R0 = 0
mem(1) <= code_LI & R1 & x"0007"; -- R1 = #
mem(2) <= code_SW & R1 & R0 & x"000"; -- Mem[R0 + 0] = R1
mem(3) <= code_LI & R1 & x"0003"; -- R1 = #
mem(4) <= code_SW & R1 & R0 & x"001"; -- Mem[R0 + 1] = R1
mem(5) <= code_LI & R1 & x"000A"; -- R1 = #
mem(6) <= code_SW & R1 & R0 & x"002"; -- Mem[R0 + 2] = R1
mem(7) <= code_LI & R1 & x"00A0"; -- R1 = #
mem(8) <= code_SW & R1 & R0 & x"003"; -- Mem[R0 + 3] = R1
mem(9) <= code_LI & R1 & x"000B"; -- R1 = #
mem(10) <= code_SW & R1 & R0 & x"004"; -- Mem[R0 + 4] = R1
mem(11) <= code_LI & R1 & x"0060"; -- R1 = #
mem(12) <= code_SW & R1 & R0 & x"005"; -- Mem[R0 + 5] = R1
mem(13) <= code_LI & R1 & x"00B2"; -- R1 = #
mem(14) <= code_SW & R1 & R0 & x"006"; -- Mem[R0 + 6] = R1
mem(15) <= code_LI & R1 & x"00A0"; -- R1 = #
mem(16) <= code_SW & R1 & R0 & x"007"; -- Mem[R0 + 7] = R1
mem(17) <= code_LI & R1 & x"0A00"; -- R1 = #
mem(18) <= code_SW & R1 & R0 & x"008"; -- Mem[R0 + 8] = R1
mem(19) <= code_LI & R1 & x"00C0"; -- R1 = #
mem(20) <= code_SW & R1 & R0 & x"009"; -- Mem[R0 + 9] = R1
mem(21) <= code_LI & R1 & x"0017"; -- R1 = #
mem(22) <= code_SW & R1 & R0 & x"00A"; -- Mem[R0 + 10] = R1
mem(23) <= code_LI & R1 & x"00B9"; -- R1 = #
mem(24) <= code_SW & R1 & R0 & x"00B"; -- Mem[R0 + 11] = R1
mem(25) <= code_LI & R1 & x"0C01"; -- R1 = #
mem(26) <= code_SW & R1 & R0 & x"00C"; -- Mem[R0 + 12] = R1
mem(27) <= code_LI & R1 & x"00B2"; -- R1 = #
mem(28) <= code_SW & R1 & R0 & x"00D"; -- Mem[R0 + 13] = R1
mem(29) <= code_LI & R1 & x"0003"; -- R1 = #
mem(30) <= code_SW & R1 & R0 & x"00E"; -- Mem[R0 + 14] = R1
--Obtener el menor del arreglo
mem(31) <= code_LI & R2 & x"000E"; -- R2 = 14
mem(32) <= code_LW & R1 & R0 & x"000"; -- R1 = Mem[R0 + 0]
mem(33) <= code_BGTI & R2 & R0 & x"006"; --if (R0 > R2) goto 33+6
mem(34) <= code_LW & R3 & R0 & x"000"; -- R3 = Mem[R0 + 0]
mem(35) <= code_BGTI & R1 & R3 & x"002"; --if (R3 > R1) goto 35+2
mem(36) <= code_ADDI & R1 & R3 & x"000"; -- ADDI R1 = R3 + 0
mem(37) <= code_ADDI & R0 & R0 & x"001"; -- ADDI R0 = R0 + 1
mem(38) <= code_B & SU & x"0021"; -- B 33
--Fibonacci
mem(39) <= code_LI & R4 & x"0000"; -- R4 = 0
mem(40) <= code_BLETI & R4 & R1 & x"009"; --if (R1 <= R4) goto 40+9
mem(41) <= code_LI & R5 & x"0000"; -- R5 = 0
mem(42) <= code_LI & R6 & x"0001"; -- R6 = 1
mem(43) <= code_fun & R7 & R5 & R6 & SU & fun_ADD; -- ADD R7 = R5 + R6
mem(44) <= code_SW & R7 & R4 & x"00F"; -- Mem[R4 + 15] = R7
mem(45) <= code_ADDI & R4 & R4 & x"001"; -- ADDI R4 = R4 + 1
mem(46) <= code_ADDI & R5 & R6 & x"000"; -- ADDI R5 = R6 + 0
mem(47) <= code_ADDI & R6 & R7 & x"000"; -- ADDI R6 = R7 + 0
mem(48) <= code_BGTI & R4 & R1 & x"FFB"; --if (R1 > R4) goto 48-5
mem(49) <= code_NOP & SU & SU & SU & SU & SU;
mem(50) <= code_B & SU & x"0031"; -- B 49
inst <= mem(conv_integer(pc));
end Behavioral;
|
-------------------------------------------
-- Block code: uart_shiftreg_s2p.vhd
-- History: 14.Nov.2012 - 1st version (dqtm)
-- <date> - <changes> (<author>)
-- Function: modulo divider with generic width. Output MSB with 50% duty cycle.
-- Can be used for clock-divider when no exact ratio required.
-------------------------------------------
-- Library & Use Statements
-------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Entity Declaration
-------------------------------------------
entity uart_shiftreg_s2p is
port(Clk : in std_logic;
reset_n : in std_logic;
shift_enable : in std_logic;
serdata_sync : in std_logic;
parallel_out : out std_logic_vector(9 downto 0)
);
end uart_shiftreg_s2p;
architecture rtl of uart_shiftreg_s2p is
signal shiftreg : std_logic_vector(9 downto 0);
signal next_shiftreg : std_logic_vector(9 downto 0);
begin
--------------------------------------------------
-- PROCESS FOR COMBINATORIAL LOGIC
--------------------------------------------------
comb_logic : process(all)
begin
if shift_enable = '1' then
next_shiftreg <=serdata_sync & shiftreg(9 downto 1);
else
next_shiftreg <= shiftreg; --sonst bleibt es gleiche zahl
end if;
end process comb_logic;
--------------------------------------------------
-- PROCESS FOR REGISTERS
--------------------------------------------------
flip_flops : process(all)
begin
if reset_n = '0' then
shiftreg <= (others => '0');
elsif rising_edge(Clk) then
shiftreg <= next_shiftreg;
end if;
end process flip_flops;
parallel_out <= shiftreg; --when (shift_enable = '0') else "0000000000";
end rtl;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "uart_tx"
-------------------------------------------------------------------------------
-- Author : <NAME>
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart_pkg.all;
-------------------------------------------------------------------------------
entity uart_tx_tb is
end entity uart_tx_tb;
-------------------------------------------------------------------------------
architecture behavourial of uart_tx_tb is
-- component ports
signal txd : std_logic;
signal busy : std_logic;
signal data : std_logic_vector(7 downto 0) := (others => '0');
signal empty : std_logic := '1';
signal re : std_logic;
signal clk_tx_en : std_logic := '0';
signal clk : std_logic := '0';
begin
-- component instantiation
dut : entity work.uart_tx
port map (
txd_p => txd,
busy_p => busy,
data_p => data,
empty_p => empty,
re_p => re,
clk_tx_en => clk_tx_en,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- Generate a bit clock
bitclock : process
begin
wait until rising_edge(clk);
clk_tx_en <= '1';
wait until rising_edge(clk);
clk_tx_en <= '0';
wait for 40 ns;
end process bitclock;
-- waveform generation
waveform : process
begin
wait until rising_edge(clk);
empty <= '0';
data <= "00000000"; -- partiy = 1
wait until falling_edge(re);
data <= "11001010"; -- partiy = 1
wait until falling_edge(re);
data <= "00001011"; -- partiy = 0
wait until falling_edge(re);
empty <= '1';
wait for 2 us;
empty <= '0';
data <= "11100101"; -- partiy = 0
wait until falling_edge(re);
data <= "11100100"; -- partiy = 1
wait until falling_edge(re);
empty <= '1';
wait;
end process waveform;
end architecture behavourial;
|
<gh_stars>0
-----------------------------------------------------------------------------
-- Filename: gh_baud_rate_gen.vhd
--
-- Description:
-- a 16 bit baud rate generator
--
-- Copyright (c) 2005 by <NAME>
-- an OpenCores.org Project
-- free to use, but see documentation for conditions
--
-- Revision History:
-- Revision Date Author Comment
-- -------- ---------- --------- -----------
-- 1.0 01/28/06 <NAME> Initial revision
-- 2.0 02/04/06 <NAME> reload counter with register load
-- 2.1 04/10/06 <NAME> Fix error in rCLK
--
-----------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
entity gh_baud_rate_gen is
port(
clk : in std_logic;
BR_clk : in std_logic;
rst : in std_logic;
WR : in std_logic;
BE : in std_logic_vector (1 downto 0); -- byte enable
D : in std_logic_vector (15 downto 0);
RD : out std_logic_vector (15 downto 0);
rCE : out std_logic;
rCLK : out std_logic
);
end entity;
architecture a of gh_baud_rate_gen is
COMPONENT gh_register_ce is
GENERIC (size: INTEGER := 8);
PORT(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
CE : IN STD_LOGIC; -- clock enable
D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT gh_counter_down_ce_ld is
GENERIC (size: INTEGER :=8);
PORT(
CLK : IN STD_LOGIC;
rst : IN STD_LOGIC;
LOAD : IN STD_LOGIC;
CE : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
);
END COMPONENT;
signal UB_LD : std_logic;
signal LB_LD : std_logic;
signal rate : std_logic_vector(15 downto 0);
signal C_LD : std_logic;
signal C_CE : std_logic;
signal irLD : std_logic; -- added 02/04/06
signal rLD : std_logic; -- added 02/04/06
signal count : std_logic_vector(15 downto 0);
begin
rCE <= '1' when (count = x"01") else
'0';
process(BR_clk,rst)
begin
if (rst = '1') then
rCLK <= '0';
rLD <= '0';
elsif (rising_edge(BR_CLK)) then
rLD <= irLD;
if (count > ('0' & (rate(15 downto 1)))) then -- fixed 04/10/06
rCLK <= '1';
else
rCLK <= '0';
end if;
end if;
end process;
RD <= rate;
----------------------------------------------
----------------------------------------------
UB_LD <= '0' when (WR = '0') else
'0' when (BE(1) = '0') else
'1';
u1 : gh_register_ce
generic map (8)
port map(
clk => clk,
rst => rst,
ce => UB_LD,
D => d(15 downto 8),
Q => rate(15 downto 8)
);
LB_LD <= '0' when (WR = '0') else
'0' when (BE(0) = '0') else
'1';
u2 : gh_register_ce
generic map (8)
port map(
clk => clk,
rst => rst,
ce => LB_LD,
D => d(7 downto 0),
Q => rate(7 downto 0)
);
------------------------------------------------------------
------------ baud rate counter -----------------------------
------------------------------------------------------------
process(clk,rst)
begin
if (rst = '1') then
irLD <= '0';
elsif (rising_edge(CLK)) then
if ((UB_LD or LB_LD) = '1') then
irLD <= '1';
elsif (rLD = '1') then
irLD <= '0';
end if;
end if;
end process;
C_LD <= '1' when (count = x"01") else
'1' when (rLD = '1') else
'0';
C_CE <= '1' when (rate > x"01") else
'0';
U3 : gh_counter_down_ce_ld
Generic Map (size => 16)
PORT MAP (
clk => BR_clk,
rst => rst,
LOAD => C_LD,
CE => C_CE,
D => rate,
Q => count);
end a;
|
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<KEY>
`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:15:48 03/12/2022
-- Design Name:
-- Module Name: ADD16 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ADD16 is
Port ( A: in std_logic_vector(15 downto 0);
B: in std_logic_vector(15 downto 0);
--cin: in std_logic;
sum16: out std_logic_vector(15 downto 0);
f_cry: out std_logic
);
end ADD16;
architecture Behavioral of ADD16 is
signal cry16 : std_logic_vector(14 downto 0);
begin
FA0: entity work.ADD1 port map (
a => A(0) , b =>B(0) , c => '0', sum => sum16(0) , cry => cry16(0)
);
FA1: entity work.ADD1 port map (
a => A(1) , b =>B(1) , c => cry16(0), sum => sum16(1) , cry => cry16(1)
);
FA2: entity work.ADD1 port map (
a => A(2) , b =>B(2) , c => cry16(1), sum => sum16(2) , cry => cry16(2)
);
FA3: entity work.ADD1 port map (
a => A(3) , b =>B(3) , c => cry16(2), sum => sum16(3) , cry => cry16(3)
);
FA4: entity work.ADD1 port map (
a => A(4) , b =>B(4) , c => cry16(3), sum => sum16(4) , cry => cry16(4)
);
FA5: entity work.ADD1 port map (
a => A(5) , b =>B(5) , c => cry16(4), sum => sum16(5) , cry => cry16(5)
);
FA6: entity work.ADD1 port map (
a => A(6) , b =>B(6) , c => cry16(5), sum => sum16(6) , cry => cry16(6)
);
FA7: entity work.ADD1 port map (
a => A(7) , b =>B(7) , c => cry16(6), sum => sum16(7) , cry => cry16(7)
);
FA8: entity work.ADD1 port map (
a => A(8) , b =>B(8) , c => cry16(7), sum => sum16(8) , cry => cry16(8)
);
FA9: entity work.ADD1 port map (
a => A(9) , b =>B(9) , c => cry16(8), sum => sum16(9) , cry => cry16(9)
);
FA10: entity work.ADD1 port map (
a => A(10) , b =>B(10) , c => cry16(9), sum => sum16(10) , cry => cry16(10)
);
FA11: entity work.ADD1 port map (
a => A(11) , b =>B(11) , c => cry16(10), sum => sum16(11) , cry => cry16(11)
);
FA12: entity work.ADD1 port map (
a => A(11) , b =>B(12) , c => cry16(11), sum => sum16(12) , cry => cry16(12)
);
FA13: entity work.ADD1 port map (
a => A(11) , b =>B(13) , c => cry16(12), sum => sum16(13) , cry => cry16(13)
);
FA14: entity work.ADD1 port map (
a => A(11) , b =>B(14) , c => cry16(13), sum => sum16(14) , cry => cry16(14)
);
FA15: entity work.ADD1 port map (
a => A(11) , b =>B(15) , c => cry16(14), sum => sum16(15) , cry => f_cry
);
end Behavioral;
|
--
-- VHDL Test Bench CAD_lib.lab9_regReadWrite_tb.lab9_regReadWrite_tester
--
-- Created:
-- by - W.UNKNOWN (DESKTOP-86TQKQ1)
-- at - 01:12:43 04/10/2021
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2018.2 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY lab9_regReadWrite_tb IS
GENERIC (
size : NATURAL RANGE 2 TO 64 := 32
);
END lab9_regReadWrite_tb;
LIBRARY CAD_lib;
USE CAD_lib.ALL;
ARCHITECTURE rtl OF lab9_regReadWrite_tb IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL D : std_ulogic_vector(size - 1 DOWNTO 0);
SIGNAL Q1 : std_logic_vector(size - 1 DOWNTO 0);
SIGNAL Q2 : std_logic_vector(size - 1 DOWNTO 0);
SIGNAL Clk : std_ulogic;
SIGNAL LE : std_ulogic;
SIGNAL OE1 : std_ulogic;
SIGNAL OE2 : std_ulogic;
-- Component declarations
COMPONENT lab9_regReadWrite
GENERIC (
size : NATURAL RANGE 2 TO 64 := 32
);
PORT (
D : IN std_ulogic_vector(size - 1 DOWNTO 0);
Q1 : OUT std_logic_vector(size - 1 DOWNTO 0);
Q2 : OUT std_logic_vector(size - 1 DOWNTO 0);
Clk : IN std_ulogic;
LE : IN std_ulogic;
OE1 : IN std_ulogic;
OE2 : IN std_ulogic
);
END COMPONENT;
-- embedded configurations
-- pragma synthesis_off
FOR U_0 : lab9_regReadWrite USE ENTITY CAD_lib.lab9_regReadWrite;
-- pragma synthesis_on
BEGIN
U_0 : lab9_regReadWrite
GENERIC MAP (
size => size
)
PORT MAP (
D => D,
Q1 => Q1,
Q2 => Q2,
Clk => Clk,
LE => LE,
OE1 => OE1,
OE2 => OE2
);
process
begin
D<=x"ffffffff";
LE<='1';
clk<='0'; wait for 100ns;
clk<='1'; wait for 100ns;
OE1<='1';
OE2<='1';
clk<='0'; wait for 100ns;
clk<='1'; wait for 100ns;
OE1<='0';
OE2<='1';
clk<='0'; wait for 100ns;
clk<='1'; wait for 100ns;
OE1<='1';
OE2<='0';
clk<='0'; wait for 100ns;
clk<='1'; wait for 100ns;
OE1<='0';
OE2<='0';
clk<='0'; wait for 100ns;
clk<='1'; wait for 100ns;
wait;
end process;
END rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ClkDividerN is
generic(divFactor : positive := 2);
port(clkIn : in std_logic;
clkOut : out std_logic);
end ClkDividerN;
architecture Behavioral of ClkDividerN is
subtype TCounter is natural range 0 to (divFactor - 1);
signal s_divCounter : TCounter;
begin
assert(divFactor >= 2);
count_proc : process(clkIn)
begin
if (rising_edge(clkIn)) then
if (s_divCounter >= divFactor - 1) then
s_divCounter <= 0;
else
s_divCounter <= s_divCounter + 1;
end if;
end if;
end process;
out_proc : process(clkIn)
begin
if (rising_edge(clkIn)) then
if (s_divCounter >= (divFactor / 2 - 1)) then
clkOut <= '1';
else
clkOut <= '0';
end if;
end if;
end process;
end Behavioral;
|
<reponame>clnrp/ep4ce6e22c8_vhdl<filename>flipflop_d.vhd
-- ep4ce6e22c8 - test microcontroller
-- flipflop D type
-- Author: <NAME>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FlipFlop_D is
port
(
Clk : in std_logic;
Rst : in std_logic;
D : in std_logic;
Q : out std_logic
);
end entity FlipFlop_D;
architecture arch of FlipFlop_D is
begin
process (Clk) is
begin
if rising_edge(Clk) then
if (Rst='1') then
Q <= '0';
else
if (D ='1') then
Q <= '1';
elsif (D ='0') then
Q <= '0';
end if;
end if;
end if;
end process;
end arch;
|
<filename>Hardware/npos.vhd
-- Positive Iteration Cordic, <NAME>, Final Project
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
entity npos is
generic (N: INTEGER:= 32;
EXP: INTEGER:= 7;
FR: INTEGER:= 16);
port (clock, resetn, s, mode: in std_logic;
Xin, Yin, Zin: in std_logic_vector (N-1 downto 0);
Xout, Yout, Zout: out std_logic_vector (N-1 downto 0);
done: out std_logic);
end npos;
architecture structure of npos is
component fsmPos
generic (N: INTEGER:= 32);
port (clock, resetn, s, mode: in std_logic;
X, Y, Z: in std_logic_vector(N-1 downto 0);
i: out std_logic_vector(3 downto 0);
E, di, s_xyz, done: out std_logic);
end component;
component my_posLUT
generic (N: INTEGER:= 16);
port (s: in std_logic_vector (3 downto 0);
y: out std_logic_vector (N-1 downto 0));
end component;
component my_rege
generic (N: INTEGER:= 32);
port ( clock, resetn: in std_logic;
E : in std_logic; -- sclr: Synchronous clear
D: in std_logic_vector (N-1 downto 0);
Q: out std_logic_vector (N-1 downto 0));
end component;
component busMux
generic (N: INTEGER:= 32); -- Length of each input signal
port (a,b: in std_logic_vector (N-1 downto 0);
s: in std_logic;
y: out std_logic_vector (N-1 downto 0));
end component;
component my_addsub
generic (N: INTEGER:= 32);
port( addsub : in std_logic;
x, y : in std_logic_vector (N-1 downto 0);
s : out std_logic_vector (N-1 downto 0);
overflow : out std_logic;
cout : out std_logic);
end component;
component FloP_AddSub_Generic_top
Generic ( expWidth : integer := 11; fracWidth : integer := 52 );
Port ( input1 : in std_logic_vector (expWidth+fracWidth downto 0);
input2 : in std_logic_vector (expWidth+fracWidth downto 0);
addSub : in std_logic;
sum : out std_logic_vector (expWidth+fracWidth downto 0));
end component;
component FloP_Shifter_Generic
Generic ( expWidth, fracWidth : integer );
Port ( inputData : in STD_LOGIC_VECTOR ((expWidth+fracWidth) downto 0);
shiftAmt : in STD_LOGIC_VECTOR (expWidth-1 downto 0);
leftRight : in STD_LOGIC;
outputData : out STD_LOGIC_VECTOR ((expWidth+fracWidth) downto 0) );
end component;
signal data_x, data_y, xt, yt, Xs, Ys: std_logic_vector(N-1 downto 0);
signal next_x, next_y: std_logic_vector(N-1 downto 0);
signal s_xyz, E, di, diz: std_logic;
signal e_i, data_z, zt, next_z: std_logic_vector(N-1 downto 0);
signal i: std_logic_vector(3 downto 0);
begin
---------------------------------------------------------------------------------------
-- Mux for X
mux1: busMux generic map(N => N)
port map (a => next_x, b => Xin, s => s_xyz, y => data_x);
-- Mux for Y
mux2: busMux generic map(N => N)
port map (a => next_y, b => Yin, s => s_xyz, y => data_y);
-- Mux for Z
mux3: busMux generic map(N => N)
port map (a => next_z, b => Zin, s => s_xyz, y => data_z);
-------------------------------------------------------------------------------------------
-- Register for X
reg1: my_rege generic map(N => N)
port map (clock => clock, resetn => resetn, E => E, D => data_x, Q => xt);
-- Register for Y
reg2: my_rege generic map(N => N)
port map (clock => clock, resetn => resetn, E => E, D => data_y, Q => yt);
-- Register for Z
reg3: my_rege generic map(N => N)
port map (clock => clock, resetn => resetn, E => E, D => data_z, Q => zt);
--------------------------------------------------------------------------------------------------
-- Barrel shifter for X
bs1: FloP_Shifter_Generic generic map (expWidth => EXP, fracWidth => FR)
port map (inputData => xt, shiftAmt(3 downto 0) => i, shiftAmt(EXP-1 downto 4) => (others => '0'), leftRight => '1', outputData => Xs);
-- Barrel shifter for Y
bs2: FloP_Shifter_Generic generic map (expWidth => EXP, fracWidth => FR)
port map(inputData => yt, shiftAmt(3 downto 0) => i, shiftAmt(EXP-1 downto 4) => (others => '0'), leftRight => '1', outputData => Ys);
------------------------------------------------------------------------------------------------------
-- LUT using BusMux
lut1: my_posLUT generic map (N => N)
port map(s => i, y => e_i);
---------------------------------------------------------------------------------------------------------
-- Generate not(di) for X and Z add/sub
diz <= not(di);
--------------------------------------------------------------------------------------------------------
-- addsub for X
full1: FloP_AddSub_Generic_top generic map(expWidth => EXP, fracWidth => FR)
port map (addSub => di, input1 => xt, input2 => Ys, sum => next_x);
-- addsub for Y
full2: FloP_AddSub_Generic_top generic map(expWidth => EXP, fracWidth => FR)
port map (addSub => di, input1 => yt, input2 => Xs, sum => next_y);
-- addsub for Z
full3: FloP_AddSub_Generic_top generic map(expWidth => EXP, fracWidth => FR)
port map (addSub => diz, input1 => zt, input2 => e_i, sum => next_z);
------------------------------------------------------------------------------------------------------------
-- Finite State Machine
fsm1: fsmPos generic map(N => N)
port map (clock => clock, resetn => resetn, s => s, mode => mode, X => xt, Y => yt, Z => zt, di => di, s_xyz => s_xyz, E => E, i => i, done => done);
---------------------------------------------------------------------------------------------------------
Xout <= xt;
Yout <= yt;
Zout <= zt;
end structure;
|
<gh_stars>1-10
LIBRARY ieee ;
USE ieee.NUMERIC_STD.all ;
USE ieee.std_logic_1164.all ;
use ieee.math_real.all;
use work.float_type_definitions_pkg.all;
use work.float_to_real_conversions_pkg.all;
use work.normalizer_pkg.all;
library vunit_lib;
use vunit_lib.run_pkg.all;
entity tb_normalizer is
generic (runner_cfg : string);
end;
architecture vunit_simulation of tb_normalizer is
signal simulation_running : boolean;
signal simulator_clock : std_logic;
constant clock_per : time := 1 ns;
constant clock_half_per : time := 0.5 ns;
constant simtime_in_clocks : integer := 50;
signal simulation_counter : natural := 0;
-----------------------------------
-- simulation specific signals ----
signal smaller : float_record := to_float(0.5);
signal larger : float_record := to_float(6.0);
signal normalizer : normalizer_record := init_normalizer;
signal test_float_normalization : float_record := ('0', to_signed(0, exponent_length), (0 => '1', others => '0'));
signal test_float_normalization2 : float_record := ('0', to_signed(9, exponent_length), (0 => '1', others => '1'));
signal test_float_normalization3 : float_record := ('0', to_signed(15, exponent_length), (4 => '1', others => '0'));
signal number_zeroes : integer := number_of_leading_zeroes(test_float_normalization.mantissa, 5);
signal normalizer_array : float_array(0 to 3) := (zero,zero,zero,zero);
signal normalizer_result : float_record := zero;
begin
------------------------------------------------------------------------
simtime : process
begin
test_runner_setup(runner, runner_cfg);
simulation_running <= true;
wait for simtime_in_clocks*clock_per;
simulation_running <= false;
test_runner_cleanup(runner); -- Simulation ends here
wait;
end process simtime;
------------------------------------------------------------------------
sim_clock_gen : process
begin
simulator_clock <= '0';
wait for clock_half_per;
while simulation_running loop
wait for clock_half_per;
simulator_clock <= not simulator_clock;
end loop;
wait;
end process;
------------------------------------------------------------------------
stimulus : process(simulator_clock)
begin
if rising_edge(simulator_clock) then
simulation_counter <= simulation_counter + 1;
create_normalizer(normalizer);
CASE simulation_counter is
WHEN 0 =>
request_normalizer(normalizer, test_float_normalization);
WHEN 1 =>
request_normalizer(normalizer, test_float_normalization2);
WHEN 2 =>
request_normalizer(normalizer, test_float_normalization3);
WHEN others => -- do nothing
end CASE;
normalizer_array(0) <= normalize(test_float_normalization , mantissa_high/4);
normalizer_array(1) <= normalize(normalizer_array(0) , mantissa_high/4);
normalizer_array(2) <= normalize(normalizer_array(1) , mantissa_high/4);
normalizer_array(3) <= normalize(normalizer_array(2) , mantissa_high/4);
if normalizer_is_ready(normalizer) then
normalizer_result <= get_normalizer_result(normalizer);
end if;
smaller <= normalize(smaller);
end if; -- rising_edge
end process stimulus;
------------------------------------------------------------------------
end vunit_simulation;
|
-- RRRH
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
----------------------------------------
ENTITY flipflopT IS
PORT (
clk, reset, t : IN STD_LOGIC;
q, nq : OUT STD_LOGIC
);
END flipflopT;
----
ARCHITECTURE arq_t OF flipflopT IS
BEGIN
PROCESS (clk, reset)
VARIABLE temp : STD_LOGIC;
BEGIN
IF (reset = '1') THEN
temp := '0';
ELSIF (clk'event AND clk = '1') THEN
temp := t XOR temp;
END IF;
q <= temp;
nq <= NOT temp;
END PROCESS;
END arq_t;
|
----------------------------------------------------------------------------------
-- (C) 2020 Hochschule Augsburg, University of Applied Sciences
----------------------------------------------------------------------------------
--
-- Entity: i2s_serializer_tb
--
-- Company: Efficient Embedded Systems Group
-- University of Applied Sciences, Augsburg, Germany
--
-- Author: <NAME>
-- Date: 2020-07-08
--
-- Description: Testbench for the i2s_serializer module.
--
----------------------------------------------------------------------------------
--! @file i2s_serializer_tb.vhd
--! @brief Testbench for the i2s_serializer module.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2s_serializer_tb is
end i2s_serializer_tb;
architecture TESTBENCH of i2s_serializer_tb is
component i2s_serializer is
port (
clk: in std_logic;
reset: in std_logic;
l_data: in std_logic_vector(15 downto 0);
r_data: in std_logic_vector(15 downto 0);
next_sample: out std_logic;
i2s_mclk: out std_logic;
i2s_bclk: out std_logic;
i2s_pblrc: out std_logic;
i2s_pbdat: out std_logic;
i2s_mute: out std_logic
);
end component i2s_serializer;
-- Clock period ...
constant period: time := 20 ns; -- 50MHz
signal clk : std_logic;
signal reset : std_logic;
signal l_data, r_data : std_logic_vector(15 downto 0);
signal next_sample : std_logic;
signal i2s_mclk : std_logic;
signal i2s_bclk : std_logic;
signal i2s_pblrc : std_logic;
signal i2s_pbdat : std_logic;
signal i2s_mute : std_logic;
begin
uut_i2s_serializer : i2s_serializer
port map(
clk => clk,
reset => reset,
l_data => l_data,
r_data => r_data,
next_sample => next_sample,
i2s_mclk => i2s_mclk,
i2s_bclk => i2s_bclk,
i2s_pblrc => i2s_pblrc,
i2s_pbdat => i2s_pbdat,
i2s_mute => i2s_mute
);
-- Process for applying patterns
process
-- Helper to perform one clock cycle...
procedure run_cycle is
begin
clk <= '0';
wait for period / 2;
clk <= '1';
wait for period / 2;
end procedure;
begin
l_data <= x"0000";
r_data <= x"0000";
for n in 1 to 2 loop run_cycle; end loop;
reset <= '1';
for n in 1 to 2 loop run_cycle; end loop;
reset <= '0';
for n in 1 to 3000 loop run_cycle; end loop;
l_data <= x"ffff";
r_data <= x"aaaa";
for n in 1 to 2000 loop run_cycle; end loop;
l_data <= x"aaaa";
r_data <= x"5555";
for n in 1 to 2000 loop run_cycle; end loop;
l_data <= x"ffff";
r_data <= x"ffff";
for n in 1 to 2000 loop run_cycle; end loop;
l_data <= x"0000";
r_data <= x"0000";
for n in 1 to 2000 loop run_cycle; end loop;
l_data <= x"ffff";
r_data <= x"ffff";
for n in 1 to 2000 loop run_cycle; end loop;
-- Print a note & finish simulation...
assert false report "Simulation finished" severity note;
wait;
end process;
end TESTBENCH;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.04.2021 20:09:06
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port (
CLK100MHZ : in STD_LOGIC;
ja : in STD_LOGIC_VECTOR (8-1 downto 0); -- sensor in
jb : out STD_LOGIC_VECTOR (8-1 downto 0); -- ledbar
jc : out STD_LOGIC_VECTOR (2-1 downto 0) -- sensor out, buzzer
);
end top;
architecture Behavioral of top is
signal s_outputdistance : integer := 0;
signal s_clk : std_logic;
begin
uut_sensor : entity work.sensor
port map(
clk_i => CLK100MHZ,
trig_o => jc(0),
echo_i => ja(0),
outputdistace_o => s_outputdistance
);
uut_led_bar : entity work.led_bar
port map(
outputdistance_i => s_outputdistance,
led_bar_o(0) => jb(0),
led_bar_o(1) => jb(1),
led_bar_o(2) => jb(2),
led_bar_o(3) => jb(3),
led_bar_o(4) => jb(4),
led_bar_o(5) => jb(5),
led_bar_o(6) => jb(6),
led_bar_o(7) => jb(7)
);
uut_clock_buzzer : entity work.clock_buzzer
port map(
clk_i => CLK100MHZ,
clk_buzz_o => s_clk
);
uut_buzzer : entity work.buzzer
port map(
outputdistance_i => s_outputdistance,
buzzer_o => jc(1),
clk_buzz_i => s_clk
);
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Adder is
port
(
input_1 : in std_logic_vector(15 downto 0);
input_2 : in std_logic_vector(15 downto 0);
cin : in std_logic;
cout : out std_logic;
sum_output : out std_logic_vector(15 downto 0)
);
end Adder;
architecture behave of Adder is
signal c : std_logic_vector(16 downto 0);
signal s_propagate : std_logic_vector(7 downto 0);
signal s_generate : std_logic_vector(7 downto 0);
begin
process(input_1, input_2, cin , s_propagate, s_generate, c)
variable i : integer;
begin
c(0) <= cin;
-- CLA for the first 4 bits of data--
for i in 0 to 3 loop
s_propagate(i) <= input_1(i) xor input_2(i);
s_generate(i) <= input_1(i) and input_2(i);
sum_output(i) <= s_propagate(i) xor s_generate(i);
c(i + 1) <= s_generate(i) or (c(i) and s_propagate(i));
end loop;
c(5) <= c(4);
-- CLA for the second 4 bits of data--
for i in 4 to 7 loop
s_propagate(i) <= input_1(i) xor input_2(i);
s_generate(i) <= input_1(i) and input_2(i);
sum_output(i) <= s_propagate(i) xor s_generate(i);
c(i + 1) <= s_generate(i) or (c(i) and s_propagate(i));
end loop;
c(9) <= c(8);
-- RCA for the third 4 bits of data--
for i in 8 to 11 loop
sum_output(i) <= input_1(i) xor input_2(i) xor c(i);
c(i+1) <= (input_1(i) and input_2(i)) or (input_2(i) and c(i)) or (c(i) and input_1(i));
end loop;
c(13) <= c(12);
-- RCA for the final 4 bits of data--
for i in 12 to 15 loop
sum_output(i) <= input_1(i) xor input_2(i) xor c(i);
c(i+1) <= (input_1(i) and input_2(i)) or (input_2(i) and c(i)) or (c(i) and input_1(i));
end loop;
cout <= c(16);
end process;
end behave;
|
--processador KARR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_signed.all;
USE IEEE.NUMERIC_STD.ALL;
--Entidade
ENTITY processador_mips_8_bits IS
PORT(
reset: IN std_logic;
clock: IN std_logic;
--indice: IN std_logic_vector(7 downto 0);
alu_result: OUT std_logic_vector(7 downto 0)
);
END processador_mips_8_bits;
--Arquitetura
ARCHITECTURE Main OF processador_mips_8_bits IS
--variaveis gerais
SIGNAL instrucao_atual: std_logic_vector(7 downto 0);
SIGNAL valor_reg1: std_logic_vector(7 downto 0);
SIGNAL valor_reg2: std_logic_vector(7 downto 0);
SIGNAL valor_reg_write: std_logic_vector(7 downto 0);
SIGNAL entrada_seletor: std_logic_vector(7 downto 0);
SIGNAL mult1x4_valor: std_logic_vector(7 downto 0);
SIGNAL saida_ULA: std_logic_vector(7 downto 0);
SIGNAL saida_memory: std_logic_vector(7 downto 0);
SIGNAL extensao_8bits: std_logic_vector(7 downto 0);
SIGNAL indice_aux: std_logic_vector(7 downto 0);
SIGNAL zero: std_logic_vector(1 downto 0);
SIGNAL saidaA_seletor: std_logic_vector(7 downto 0);
SIGNAL saidaB_seletor: std_logic_vector(7 downto 0);
--variaveis do controlador
SIGNAL reg_data: std_logic_vector(1 downto 0);
SIGNAL loop_func: std_logic_vector(1 downto 0);
SIGNAL reg_write: std_logic;
SIGNAL seletor_f: std_logic;
SIGNAL alu_op: std_logic_vector(1 downto 0);
SIGNAL men_write: std_logic;
--Declaraçao dos componentes
COMPONENT PC IS
PORT(
clk, reset :IN std_logic;
loop_f: IN std_logic_vector(1 downto 0);
beq_f: IN std_logic_vector(1 downto 0);
loop_valor : IN std_logic_vector(3 downto 0);
beq : IN std_logic_vector(1 downto 0);
indice: OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT instrucoes IS
PORT (
pc : IN std_logic_vector(7 downto 0);
instrucao : out std_logic_vector(7 downto 0);
instrucao_dado : out std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT banco_regs IS
PORT (
reg_write_en: in std_logic; --reg write 1 = sim 0 = nao
reg_write_data: in std_logic_vector(7 downto 0); --dado a ser escrito no reg write
reg_write_addr: in std_logic_vector(1 downto 0); --endereço do reg write
reg_read_addr_1: in std_logic_vector(1 downto 0); --endereço do reg 1
reg_read_addr_2: in std_logic_vector(1 downto 0); --endereço do reg 2
reg_read_data_1: out std_logic_vector(7 downto 0); --dado do reg 1
reg_read_data_2: out std_logic_vector(7 downto 0) --dado do reg 2
);
END COMPONENT;
COMPONENT seletor1x2 IS
PORT (
controle: in std_logic;
entrada: in std_logic_vector(7 downto 0);
saidaA: out std_logic_vector(7 downto 0);
saidaB: out std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT mult1x4 IS
PORT (
controle: in std_logic_vector(1 downto 0);
A: in std_logic_vector(7 downto 0);
B: in std_logic_vector(7 downto 0);
C: in std_logic_vector(7 downto 0);
D: in std_logic_vector(7 downto 0);
saida: out std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT ULA IS
PORT(
a,b : in std_logic_vector(7 downto 0); -- registrador 1, registrador 2
alu_op : in std_logic_vector(1 downto 0); --seletor de funcao
alu_result: out std_logic_vector(7 downto 0); -- saida do resultado
zero: out std_logic_vector(1 downto 0) --saida zero
);
END COMPONENT;
COMPONENT memory_data IS
PORT(
mem_addr_data : IN std_logic_vector(7 downto 0);
mem_read_data : OUT std_logic_vector(7 downto 0);
mem_write_data : IN std_logic_vector(7 downto 0);
mem_write_enable : IN std_logic
);
END COMPONENT;
COMPONENT controlador IS
PORT(
op_code: IN std_logic_vector(1 downto 0);
func: IN std_logic_vector(1 downto 0);
reg_data: out std_logic_vector(1 downto 0);
loop_func: out std_logic_vector(1 downto 0);
reg_write: out std_logic;
seletor: out std_logic;
alu_op: out std_logic_vector(1 downto 0);
men_write: out std_logic
);
END COMPONENT;
BEGIN
--indice_aux <= indice;
--==================Program counter====================
p_counter: PC port map(
clk => clock,
reset => reset,
loop_f => loop_func,
beq_f => zero,
loop_valor => instrucao_atual(5 downto 2),
beq => instrucao_atual(1 downto 0),
indice => indice_aux
);
--==================Instrucoes====================
banco_de_instrucao: instrucoes port map(
--entradas
pc => indice_aux,
--saidas
instrucao => instrucao_atual,
instrucao_dado => entrada_seletor
);
--==================banco regs====================
banco_de_registradores: banco_regs
port map(
--entradas
reg_write_en => reg_write,
reg_write_data => valor_reg_write, --dado a ser escrito no reg write
reg_write_addr => instrucao_atual(5 downto 4), --endereço do reg write
reg_read_addr_1 => instrucao_atual(5 downto 4), --endereço do reg 1
reg_read_addr_2 => instrucao_atual(3 downto 2), --endereço do reg 2
--saidas
reg_read_data_1 => valor_reg1, --dado do reg 1
reg_read_data_2 => valor_reg2 --dado do reg 2
);
--==================seletor 1x2====================
seletor_1x2: seletor1x2
port map(
--entrada
controle => seletor_f,
entrada => entrada_seletor,
--saida
saidaA => saidaA_seletor,
saidaB => saidaB_seletor
);
--==================ULA====================
unidade_de_logica_aritimetica: ula
port map(
--entradas
a => valor_reg1, -- valor 1
b => valor_reg2, -- valor 2
alu_op => alu_op, --seletor de funcao
--saidas
alu_result => saida_ULA,
zero => zero
);
--==================Memory data====================
data_memory: memory_data
port map(
--entradas
mem_addr_data => saidaB_seletor,
mem_write_data => valor_reg1,
mem_write_enable => men_write,
--saidas
mem_read_data => saida_memory
);
--==================mult 1x4====================
multiplexador1x4: mult1x4
port map(
--entradas
controle => reg_data,
A => saidaA_seletor,
B => saida_memory,
C => saida_ULA,
D => valor_reg2,
--saidas
saida => valor_reg_write
);
--==================controlador====================
controle: controlador
port map(
--entrada
op_code => instrucao_atual(7 downto 6),
func => instrucao_atual(1 downto 0),
--saida
reg_data => reg_data,
loop_func => loop_func,
reg_write => reg_write,
seletor => seletor_f,
alu_op => alu_op,
men_write => men_write
);
alu_result <= saida_ULA;
END Main;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Window is
Port (
in_clk : in STD_LOGIC;
in_ready : in STD_LOGIC;
in_data : in STD_LOGIC_VECTOR ((15 * 8 - 1) downto 0);
out_ready : out STD_LOGIC;
out_data : out STD_LOGIC_VECTOR ((15 * 15 * 8 - 1) downto 0)
);
end Window;
architecture arch_window of Window is
signal window_reg : STD_LOGIC_VECTOR ((15 * 15 * 8 - 1) downto 0);
begin
out_data <= window_reg;
window_reg_shift : process (in_clk)
begin
if rising_edge(in_clk) then
if in_ready = '1' then
for i in 14 downto 0 loop
window_reg((15 * 8 * i - 8 - 1) downto (15 * 8 * i)) <=
window_reg((15 * 8 * i - 1) downto (15 * 8 * i + 8));
end loop;
for i in 15 downto 1 loop
window_reg((15 * 8 * i + 15 * 8 - 1) downto (15 * 8 * i + 14 * 8)) <= in_data((8 * i - 1) downto (8 * (i - 1)));
end loop;
else
out_ready <= '0';
end if;
end if;
end process window_reg_shift;
end arch_window;
|
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconcat
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of bus concatenater
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconcat is
generic (
NUM_PORTS : integer := 2; -- Number of input ports to concat
IN0_WIDTH : integer := 1; -- Width of a In0 input
IN1_WIDTH : integer := 1; -- Width of a In1 input
IN2_WIDTH : integer := 1; -- Width of a In2 input
IN3_WIDTH : integer := 1; -- Width of a In3 input
IN4_WIDTH : integer := 1; -- Width of a In4 input
IN5_WIDTH : integer := 1; -- Width of a In5 input
IN6_WIDTH : integer := 1; -- Width of a In6 input
IN7_WIDTH : integer := 1; -- Width of a In7 input
IN8_WIDTH : integer := 1; -- Width of a In8 input
IN9_WIDTH : integer := 1; -- Width of a In9 input
IN10_WIDTH : integer := 1; -- Width of a In10 input
IN11_WIDTH : integer := 1; -- Width of a In10 input
IN12_WIDTH : integer := 1; -- Width of a In10 input
IN13_WIDTH : integer := 1; -- Width of a In10 input
IN14_WIDTH : integer := 1; -- Width of a In10 input
IN15_WIDTH : integer := 1; -- Width of a In15 input
IN16_WIDTH : integer := 1; -- Width of a In16 input
IN17_WIDTH : integer := 1; -- Width of a In17 input
IN18_WIDTH : integer := 1; -- Width of a In18 input
IN19_WIDTH : integer := 1; -- Width of a In19 input
IN20_WIDTH : integer := 1; -- Width of a In20 input
IN21_WIDTH : integer := 1; -- Width of a In21 input
IN22_WIDTH : integer := 1; -- Width of a In22 input
IN23_WIDTH : integer := 1; -- Width of a In23 input
IN24_WIDTH : integer := 1; -- Width of a In24 input
IN25_WIDTH : integer := 1; -- Width of a In25 input
IN26_WIDTH : integer := 1; -- Width of a In26 input
IN27_WIDTH : integer := 1; -- Width of a In27 input
IN28_WIDTH : integer := 1; -- Width of a In28 input
IN29_WIDTH : integer := 1; -- Width of a In29 input
IN30_WIDTH : integer := 1; -- Width of a In30 input
IN31_WIDTH : integer := 1; -- Width of a In31 input
dout_width : integer := 2); -- Width of output
port (
In0 : in std_logic_vector (IN0_WIDTH-1 downto 0);
In1 : in std_logic_vector (IN1_WIDTH-1 downto 0);
In2 : in std_logic_vector (IN2_WIDTH-1 downto 0);
In3 : in std_logic_vector (IN3_WIDTH-1 downto 0);
In4 : in std_logic_vector (IN4_WIDTH-1 downto 0);
In5 : in std_logic_vector (IN5_WIDTH-1 downto 0);
In6 : in std_logic_vector (IN6_WIDTH-1 downto 0);
In7 : in std_logic_vector (IN7_WIDTH-1 downto 0);
In8 : in std_logic_vector (IN8_WIDTH-1 downto 0);
In9 : in std_logic_vector (IN9_WIDTH-1 downto 0);
In10 : in std_logic_vector (IN10_WIDTH-1 downto 0);
In11 : in std_logic_vector (IN11_WIDTH-1 downto 0);
In12 : in std_logic_vector (IN12_WIDTH-1 downto 0);
In13 : in std_logic_vector (IN13_WIDTH-1 downto 0);
In14 : in std_logic_vector (IN14_WIDTH-1 downto 0);
In15 : in std_logic_vector (IN15_WIDTH-1 downto 0);
In16 : in std_logic_vector (IN16_WIDTH-1 downto 0);
In17 : in std_logic_vector (IN17_WIDTH-1 downto 0);
In18 : in std_logic_vector (IN18_WIDTH-1 downto 0);
In19 : in std_logic_vector (IN19_WIDTH-1 downto 0);
In20 : in std_logic_vector (IN20_WIDTH-1 downto 0);
In21 : in std_logic_vector (IN21_WIDTH-1 downto 0);
In22 : in std_logic_vector (IN22_WIDTH-1 downto 0);
In23 : in std_logic_vector (IN23_WIDTH-1 downto 0);
In24 : in std_logic_vector (IN24_WIDTH-1 downto 0);
In25 : in std_logic_vector (IN25_WIDTH-1 downto 0);
In26 : in std_logic_vector (IN26_WIDTH-1 downto 0);
In27 : in std_logic_vector (IN27_WIDTH-1 downto 0);
In28 : in std_logic_vector (IN28_WIDTH-1 downto 0);
In29 : in std_logic_vector (IN29_WIDTH-1 downto 0);
In30 : in std_logic_vector (IN30_WIDTH-1 downto 0);
In31 : in std_logic_vector (IN31_WIDTH-1 downto 0);
dout : out std_logic_vector (dout_width-1 downto 0)
);
end xlconcat;
architecture behavioral of xlconcat is
begin
NUM_1_INST : if NUM_PORTS = 1 generate
begin
dout <= In0;
end generate NUM_1_INST;
NUM_2_INST : if NUM_PORTS = 2 generate
begin
dout <= In1 & In0;
end generate NUM_2_INST;
NUM_3_INST : if NUM_PORTS = 3 generate
begin
dout <= In2 & In1 & In0;
end generate NUM_3_INST;
NUM_4_INST : if NUM_PORTS = 4 generate
begin
dout <= In3 & In2 & In1 & In0;
end generate NUM_4_INST;
NUM_5_INST : if NUM_PORTS = 5 generate
begin
dout <= In4 & In3 & In2 & In1 & In0;
end generate NUM_5_INST;
NUM_6_INST : if NUM_PORTS = 6 generate
begin
dout <= In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_6_INST;
NUM_7_INST : if NUM_PORTS = 7 generate
begin
dout <= In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_7_INST;
NUM_8_INST : if NUM_PORTS = 8 generate
begin
dout <= In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_8_INST;
NUM_9_INST : if NUM_PORTS = 9 generate
begin
dout <= In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_9_INST;
NUM_10_INST : if NUM_PORTS = 10 generate
begin
dout <= In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_10_INST;
NUM_11_INST : if NUM_PORTS = 11 generate
begin
dout <= In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_11_INST;
NUM_12_INST : if NUM_PORTS = 12 generate
begin
dout <= In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_12_INST;
NUM_13_INST : if NUM_PORTS = 13 generate
begin
dout <= In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_13_INST;
NUM_14_INST : if NUM_PORTS = 14 generate
begin
dout <= In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_14_INST;
NUM_15_INST : if NUM_PORTS = 15 generate
begin
dout <= In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_15_INST;
NUM_16_INST : if NUM_PORTS = 16 generate
begin
dout <= In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_16_INST;
NUM_17_INST : if NUM_PORTS = 17 generate
begin
dout <= In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_17_INST;
NUM_18_INST : if NUM_PORTS = 18 generate
begin
dout <= In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_18_INST;
NUM_19_INST : if NUM_PORTS = 19 generate
begin
dout <= In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_19_INST;
NUM_20_INST : if NUM_PORTS = 20 generate
begin
dout <= In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_20_INST;
NUM_21_INST : if NUM_PORTS = 21 generate
begin
dout <= In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_21_INST;
NUM_22_INST : if NUM_PORTS = 22 generate
begin
dout <= In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_22_INST;
NUM_23_INST : if NUM_PORTS = 23 generate
begin
dout <= In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_23_INST;
NUM_24_INST : if NUM_PORTS = 24 generate
begin
dout <= In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_24_INST;
NUM_25_INST : if NUM_PORTS = 25 generate
begin
dout <= In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_25_INST;
NUM_26_INST : if NUM_PORTS = 26 generate
begin
dout <= In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_26_INST;
NUM_27_INST : if NUM_PORTS = 27 generate
begin
dout <= In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_27_INST;
NUM_28_INST : if NUM_PORTS = 28 generate
begin
dout <= In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_28_INST;
NUM_29_INST : if NUM_PORTS = 29 generate
begin
dout <= In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_29_INST;
NUM_30_INST : if NUM_PORTS = 30 generate
begin
dout <= In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_30_INST;
NUM_31_INST : if NUM_PORTS = 31 generate
begin
dout <= In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_31_INST;
NUM_32_INST : if NUM_PORTS = 32 generate
begin
dout <= In31 & In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_32_INST;
end behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ROB_Insert_Control is
Port ( Reset : in STD_LOGIC;
Issue_WrEn : in STD_LOGIC;
Issue_Tag : in STD_LOGIC_VECTOR (4 downto 0);
Insert_0 : out STD_LOGIC:= '0';
Insert_1 : out STD_LOGIC:= '0';
Insert_2 : out STD_LOGIC:= '0';
Insert_3 : out STD_LOGIC:= '0';
Insert_4 : out STD_LOGIC:= '0';
Insert_5 : out STD_LOGIC:= '0';
Insert_6 : out STD_LOGIC:= '0';
Insert_7 : out STD_LOGIC:= '0';
Tail_FIFO_Out : out STD_LOGIC_VECTOR (2 downto 0):= "000");
end ROB_Insert_Control;
architecture Behavioral of ROB_Insert_Control is
signal Tail_FIFO: STD_LOGIC_VECTOR (2 downto 0):= "000";
begin
process(Reset, Issue_Tag)
begin
if Reset = '1' then
Tail_FIFO <= "000";
else
if Issue_WrEn = '1' then
case Tail_FIFO is
when "000" =>
Tail_FIFO <= "001";--Dieuthinsi epomenis egrafis
Insert_0 <= '1';
Insert_1 <= '0';
Insert_2 <= '0';
Insert_3 <= '0';
Insert_4 <= '0';
Insert_5 <= '0';
Insert_6 <= '0';
Insert_7 <= '0';
when "001" =>
Tail_FIFO <= "010";--Dieuthinsi epomenis egrafis
Insert_0 <= '0';
Insert_1 <= '1';
Insert_2 <= '0';
Insert_3 <= '0';
Insert_4 <= '0';
Insert_5 <= '0';
Insert_6 <= '0';
Insert_7 <= '0';
when "010" =>
Tail_FIFO <= "011";--Dieuthinsi epomenis egrafis
Insert_0 <= '0';
Insert_1 <= '0';
Insert_2 <= '1';
Insert_3 <= '0';
Insert_4 <= '0';
Insert_5 <= '0';
Insert_6 <= '0';
Insert_7 <= '0';
when "011" =>
Tail_FIFO <= "100";--Dieuthinsi epomenis egrafis
Insert_0 <= '0';
Insert_1 <= '0';
Insert_2 <= '0';
Insert_3 <= '1';
Insert_4 <= '0';
Insert_5 <= '0';
Insert_6 <= '0';
Insert_7 <= '0';
when "100" =>
Tail_FIFO <= "101";--Dieuthinsi epomenis egrafis
Insert_0 <= '0';
Insert_1 <= '0';
Insert_2 <= '0';
Insert_3 <= '0';
Insert_4 <= '1';
Insert_5 <= '0';
Insert_6 <= '0';
Insert_7 <= '0';
when "101" =>
Tail_FIFO <= "110";--Dieuthinsi epomenis egrafis
Insert_0 <= '0';
Insert_1 <= '0';
Insert_2 <= '0';
Insert_3 <= '0';
Insert_4 <= '0';
Insert_5 <= '1';
Insert_6 <= '0';
Insert_7 <= '0';
when "110" =>
Tail_FIFO <= "111";--Dieuthinsi epomenis egrafis
Insert_0 <= '0';
Insert_1 <= '0';
Insert_2 <= '0';
Insert_3 <= '0';
Insert_4 <= '0';
Insert_5 <= '0';
Insert_6 <= '1';
Insert_7 <= '0';
when "111" =>
Tail_FIFO <= "000";--Dieuthinsi epomenis egrafis
Insert_0 <= '0';
Insert_1 <= '0';
Insert_2 <= '0';
Insert_3 <= '0';
Insert_4 <= '0';
Insert_5 <= '0';
Insert_6 <= '0';
Insert_7 <= '1';
when others =>
null;
end case;
else
Insert_0 <= '0';
Insert_1 <= '0';
Insert_2 <= '0';
Insert_3 <= '0';
Insert_4 <= '0';
Insert_5 <= '0';
Insert_6 <= '0';
Insert_7 <= '0';
end if;
end if;
end process;
Tail_FIFO_Out <= Tail_FIFO;
end Behavioral;
|
<reponame>Niels3RT/KC854_MiSTer
--
-- Port to MiSTer by <NAME>
--
-- Original Copyright notice:
--
-- Copyright (c) 2015, $ME
-- All rights reserved.
--
-- Redistribution and use in source and synthezised forms, with or without modification, are permitted
-- provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this list of conditions
-- and the following disclaimer.
--
-- 2. Redistributions in synthezised form must reproduce the above copyright notice, this list of conditions
-- and the following disclaimer in the documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-- WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
-- KC854 Toplevel
--
library IEEE;
use IEEE.std_logic_1164.all;
entity kc854 is
generic (
RESET_DELAY : integer := 100000
);
port(
cpuclk : in std_logic; -- 56,75Mhz
--vgaclk : in std_logic; -- 8,867238Mhz PAL/65MHz VGA
clkLocked : in std_logic;
reset_sig : in std_logic;
ps2_key : in std_logic_vector(10 downto 0);
joystick_0 : in std_logic_vector(31 downto 0);
turbo : in std_logic_vector(1 downto 0);
scandouble : in std_logic;
ce_pix : out std_logic;
HBlank : out std_logic;
HSync : out std_logic;
VBlank : out std_logic;
VSync : out std_logic;
VGA_R : out std_logic_vector(7 downto 0);
VGA_G : out std_logic_vector(7 downto 0);
VGA_B : out std_logic_vector(7 downto 0);
clk_audio : in std_logic; -- 24.576 MHz
AUDIO_L : out std_logic_vector(15 downto 0);
AUDIO_R : out std_logic_vector(15 downto 0);
--AUDIO_S : out std_logic;
--AUDIO_MIX : out std_logic_vector(1 downto 0);
audioEn_n : in std_logic;
tapeEn : in std_logic;
LED_USER : out std_logic;
LED_POWER : out std_logic_vector(1 downto 0);
LED_DISK : out std_logic_vector(1 downto 0);
USER_OUT : out std_logic_vector(6 downto 0);
hps_status : in std_logic_vector(31 downto 0);
ioctl_download : in std_logic;
ioctl_index : in std_logic_vector(7 downto 0);
ioctl_wr : in std_logic;
ioctl_addr : in std_logic_vector(24 downto 0);
ioctl_data : in std_logic_vector(7 downto 0);
ioctl_wait : out std_logic
);
end kc854;
architecture struct of kc854 is
constant NUMINTS : integer := 2 + 4 + 6 + 2 + 4; -- (M008 + CTC + SIO + PIO + CTC)
signal cpuReset_n : std_logic;
signal cpuAddr : std_logic_vector(15 downto 0);
signal cpuDataIn : std_logic_vector(7 downto 0);
signal cpuDataOut : std_logic_vector(7 downto 0);
signal cpuEn : std_logic;
signal cpuWait : std_logic;
signal cpuTick : std_logic;
signal cpuInt_n : std_logic := '1';
signal cpuM1_n : std_logic;
signal cpuMReq_n : std_logic;
signal cpuRfsh_n : std_logic;
signal cpuIorq_n : std_logic;
signal cpuRD_n : std_logic;
signal cpuWR_n : std_logic;
signal cpuRETI_n : std_logic;
signal cpuIntEna_n : std_logic;
signal umsr : std_logic;
signal afe : std_logic := '1'; -- 1 for poweron, 0 for reset
signal cnt_M1_n : integer range 0 to 15;
signal cpuM1_n_old : std_logic;
signal memDataOut : std_logic_vector(7 downto 0);
signal vidTick : std_logic;
signal irm_adr : std_logic_vector(13 downto 0);
signal irmPb0_do_2 : std_logic_vector(7 downto 0);
signal irmCb0_do_2 : std_logic_vector(7 downto 0);
signal irmPb1_do_2 : std_logic_vector(7 downto 0);
signal irmCb1_do_2 : std_logic_vector(7 downto 0);
signal set_img : std_logic;
signal set_cmode : std_logic;
signal set_blinken : std_logic;
signal zi_n : std_logic;
signal bi_n : std_logic;
signal h4 : std_logic;
signal ioSel : boolean;
signal memCS_n : std_logic;
signal pioCS_n : std_logic;
signal pioAIn : std_logic_vector(7 downto 0);
signal pioAOut : std_logic_vector(7 downto 0);
signal pioARdy : std_logic;
signal pioAStb : std_logic;
signal pioBIn : std_logic_vector(7 downto 0);
signal pioBOut : std_logic_vector(7 downto 0);
signal pioBRdy : std_logic;
signal pioBStb : std_logic;
signal pioDataOut : std_logic_vector(7 downto 0);
signal modDataOut : std_logic_vector(7 downto 0);
signal modcs_n : std_logic;
signal ctcCS_n : std_logic;
signal ctcDataOut : std_logic_vector(7 downto 0);
signal ctcClkTrg : std_logic_vector(3 downto 0);
signal ctcZcTo : std_logic_vector(3 downto 0);
signal intPeriph : std_logic_vector(NUMINTS-1 downto 0);
signal intAckPeriph : std_logic_vector(NUMINTS-1 downto 0);
signal resetDelay : integer range 0 to RESET_DELAY := RESET_DELAY;
signal ps2_rcvd : std_logic;
signal ps2_state : std_logic;
signal ps2_code : std_logic_vector(7 downto 0);
signal old_stb : std_logic;
-- TEMP audio_l debug
signal AUDIO_L_DBG : std_logic_vector(15 downto 0);
signal AUDIO_R_DBG : std_logic_vector(15 downto 0);
begin
LED_USER <= '0';
LED_POWER <= b"10";
-- reset
cpuReset_n <= '0' when resetDelay /= 0 else '1';
reset : process
begin
wait until rising_edge(cpuclk);
-- delay reset
if resetDelay > 0 then -- Reset verzoegern?
resetDelay <= resetDelay - 1;
end if;
-- begin reset
if clkLocked = '0' or reset_sig = '1' then -- Reset
resetDelay <= RESET_DELAY;
-- reset vector adr 1 for powerup, 0 for reset
if clkLocked = '0' then
afe <= '1';
else
afe <= '0';
end if;
end if;
-- -- 2. Flanke -> startup fertig
-- some pullup voodoo to make Z80 read initial reset vector from eprom
-- switch to real addressing after a couple of cycles
if cnt_M1_n = 2 then
umsr <= '1';
end if;
-- end startup after reading reset vector from rom
if cpuEn = '1' then
-- startup according to schematics
cpuM1_n_old <= cpuM1_n;
if cpuReset_n = '1' and cpuM1_n_old = '1' and cpuM1_n = '0' and cnt_M1_n < 3 then
cnt_M1_n <= cnt_M1_n + 1;
end if;
end if;
-- reset cycle counter and address messing signal
if cpuReset_n = '0' then
umsr <= '0';
cnt_M1_n <= 0;
end if;
end process;
-- video controller
video : entity work.video
port map (
clk_sys => cpuclk,
tick_vid => vidTick,
ce_pix => ce_pix,
vgaRed => VGA_R,
vgaGreen => VGA_G,
vgaBlue => VGA_B,
vgaHSync => HSync,
vgaVSync => VSync,
vgaHBlank => HBlank,
vgaVBlank => VBlank,
zi_n => zi_n,
bi_n => bi_n,
h4 => h4,
irm_adr => irm_adr,
irmPb0_do_2 => irmPb0_do_2,
irmCb0_do_2 => irmCb0_do_2,
irmPb1_do_2 => irmPb1_do_2,
irmCb1_do_2 => irmCb1_do_2,
set_img => set_img,
set_cmode => set_cmode,
set_blinken => set_blinken,
blink => ctcZcTo(2)
);
-- memory controller
memcontrol : entity work.memcontrol
port map (
clk => cpuclk,
reset_n => cpuReset_n,
cpuAddr => cpuAddr,
cpuDOut => memDataOut,
cpuDIn => cpuDataOut,
cpuWR_n => cpuWR_n,
cpuRD_n => cpuRD_n,
cpuMREQ_n => cpuMReq_n,
cpuM1_n => cpuM1_n,
cpuIORQ_n => cpuIorq_n,
umsr => umsr,
afe => afe,
cpuEn => cpuEn,
cpuWait => cpuWait,
memCS_n => memCS_n,
cpuTick => cpuTick,
pioPortA => pioAOut,
pioPortB => pioBOut,
irm_adr => irm_adr,
irmPb0_do_2 => irmPb0_do_2,
irmCb0_do_2 => irmCb0_do_2,
irmPb1_do_2 => irmPb1_do_2,
irmCb1_do_2 => irmCb1_do_2,
set_img => set_img,
set_cmode => set_cmode,
set_blinken => set_blinken
);
-- CPU data-in multiplexer
cpuDataIn <=
ctcDataOut when ctcCS_n = '0' or intAckPeriph(3 downto 0) /= "0000" else
pioDataOut when pioCS_n = '0' or intAckPeriph(5 downto 4) /= "00" else
memDataOut when memCS_n = '0' else
modDataOut when modcs_n = '0' or intAckPeriph(17 downto 6) /= "000000000000" else
x"ff" when ioSel else -- make other modules play dead
x"ff"; -- pullups on d0-d7
-- T80 CPU
cpu : entity work.T80se
generic map(Mode => 1, T2Write => 1, IOWait => 0)
port map(
RESET_n => cpuReset_n,
CLK_n => cpuclk,
CLKEN => cpuEn,
WAIT_n => cpuWait,
INT_n => cpuInt_n,
NMI_n => '1',
BUSRQ_n => '1',
M1_n => cpuM1_n,
MREQ_n => cpuMReq_n,
IORQ_n => cpuIorq_n,
RD_n => cpuRD_n,
WR_n => cpuWR_n,
RFSH_n => open,
HALT_n => open,
BUSAK_n => open,
A => cpuAddr,
DI => cpuDataIn,
DO => cpuDataOut,
IntE => cpuIntEna_n,
RETI_n => cpuRETI_n
);
ioSel <= cpuIorq_n = '0' and cpuM1_n='1' and (cpuRD_n = '0' or cpuWR_n = '0');
-- PIO: 88H-8BH
pioCS_n <= '0' when cpuAddr(7 downto 2) = "100010" and ioSel else '1';
--pioAStb <= '1';
pioAIn <= (others => '1');
pioBIn <= (others => '1');
pio : entity work.pio
port map (
clk => cpuclk,
res_n => cpuReset_n,
dIn => cpuDataOut,
dOut => pioDataOut,
baSel => cpuAddr(0),
cdSel => cpuAddr(1),
cs_n => pioCS_n,
m1_n => cpuM1_n,
iorq_n => cpuIorq_n,
rd_n => cpuRD_n,
wr_n => cpuWR_n,
intAck => intAckPeriph(5 downto 4),
int => intPeriph(5 downto 4),
aIn => pioAIn,
aOut => pioAOut,
aRdy => pioARdy,
aStb => pioAStb,
bIn => pioBIn,
bOut => pioBOut,
bRdy => pioBRdy,
bStb => pioBStb
);
-- audio output
AUDIO_L <= AUDIO_L_DBG;
AUDIO_R <= AUDIO_R_DBG;
audio_out : entity work.audio
port map (
clk => clk_audio,
reset_n => cpuReset_n,
--AUDIO_L => AUDIO_L,
AUDIO_L => AUDIO_L_DBG,
AUDIO_R => AUDIO_R_DBG,
--AUDIO_S => AUDIO_S,
--AUDIO_MIX => AUDIO_MIX,
audioEn_n => audioEn_n,
tapeEn => tapeEn,
tape_out => pioAStb,
pioB => pioBOut,
ctcTcTo => ctcZcTo(1 downto 0)
);
-- keyboard
keyboard : entity work.keyboard
port map (
clk => cpuclk,
res_n => cpuReset_n,
tick_cpu => cpuEn,
turbo => turbo,
scancode => ps2_code,
scanstate => ps2_state,
rcvd => ps2_rcvd,
remo => pioBStb
);
-- detect pressed key from MiSTer
process (ps2_key, cpuclk)
begin
if rising_edge(cpuclk) then
old_stb <= ps2_key(10);
if old_stb /= ps2_key(10) then
--LED_USER <= ps2_key(9);
ps2_state <= ps2_key(9); -- 1 key down, 0 not down
ps2_code <= ps2_key(7 downto 0);
ps2_rcvd <= '1';
else
ps2_rcvd <= '0';
end if;
end if;
end process;
-- system clocks
sysclock : entity work.sysclock
port map (
clk => cpuclk,
reset_n => cpuReset_n,
cpuEn => cpuEn,
turbo => turbo,
tick_cpu => cpuTick,
tick_vid => vidTick
);
-- CTC: 8CH-8FH
ctcCS_n <= '0' when cpuAddr(7 downto 2) = "100011" and ioSel else '1';
ctcClkTrg(0) <= h4;
ctcClkTrg(1) <= h4;
ctcClkTrg(2) <= bi_n;
ctcClkTrg(3) <= bi_n;
ctc : entity work.ctc
port map (
clk => cpuclk,
sysClkEn => cpuTick,
res_n => cpuReset_n,
cs => ctcCS_n,
dIn => cpuDataOut,
dOut => ctcDataOut,
chanSel => cpuAddr(1 downto 0),
m1_n => cpuM1_n,
iorq_n => cpuIorq_n,
rd_n => cpuRD_n,
wr_n => cpuWR_n,
int => intPeriph(3 downto 0),
intAck => intAckPeriph(3 downto 0),
clk_trg => ctcClkTrg,
zc_to => ctcZcTo
);
-- tape
tape : entity work.tape
port map (
clk => cpuclk,
reset_n => cpuReset_n,
tick_cpu => cpuEn,
LED_DISK => LED_DISK,
tape_out => pioAStb,
turbo => turbo,
hps_status => hps_status,
ioctl_download => ioctl_download,
ioctl_index => ioctl_index,
ioctl_wr => ioctl_wr,
ioctl_addr => ioctl_addr,
ioctl_data => ioctl_data,
ioctl_wait => ioctl_wait
);
-- interrupt controller
intController : entity work.intController
generic map (
NUMINTS => NUMINTS
)
port map (
clk => cpuclk,
res_n => cpuReset_n,
int_n => cpuInt_n,
intPeriph => intPeriph,
intAck => intAckPeriph,
m1_n => cpuM1_n,
iorq_n => cpuIorq_n,
rd_n => cpuRD_n,
reti_n => cpuRETI_n,
intEna_n => cpuIntEna_n
);
-- modules
modules : entity work.modules
generic map (
NUMINTS => NUMINTS
)
port map (
cpuclk => cpuclk,
cpuEn => cpuEn,
cpuReset_n => cpuReset_n,
ioSel => ioSel,
addr => cpuAddr,
dIn => cpuDataOut,
dOut => modDataOut,
m1_n => cpuM1_n,
mreq_n => cpuMReq_n,
iorq_n => cpuIorq_n,
rd_n => cpuRD_n,
wr_n => cpuWR_n,
int => intPeriph(NUMINTS-1 downto 6),
intAck => intAckPeriph,
modcs_n => modcs_n,
bi_n => bi_n,
joystick_0 => joystick_0,
ioctl_download => ioctl_download,
ioctl_index => ioctl_index,
ioctl_wr => ioctl_wr,
ioctl_addr => ioctl_addr,
ioctl_data => ioctl_data
);
end;
|
<reponame>foxxy777/leros<gh_stars>10-100
--
-- Copyright 2011 <NAME> <<EMAIL>>,
-- Technical University of Denmark, DTU Informatics.
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER ``AS IS'' AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-- NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation are
-- those of the authors and should not be interpreted as representing official
-- policies, either expressed or implied, of the copyright holder.
--
--
-- leros_de2-70.vhd
--
-- top level for Altera DE2-70 board
--
-- 2011-02-20 creation
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.leros_types.all;
entity leros_top_de2 is
port (
clk : in std_logic;
oLEDG : out std_logic_vector(7 downto 0);
iKEY : in std_logic_vector(3 downto 0);
ser_txd : out std_logic;
ser_rxd : in std_logic
);
end leros_top_de2;
architecture rtl of leros_top_de2 is
signal clk_int : std_logic;
-- for generation of internal reset
signal int_res : std_logic;
signal res_cnt : unsigned(2 downto 0) := "000"; -- for the simulation
attribute altera_attribute : string;
attribute altera_attribute of res_cnt : signal is "POWER_UP_LEVEL=LOW";
signal ioout : io_out_type;
signal ioin : io_in_type;
signal outp : std_logic_vector(15 downto 0);
signal btn_reg : std_logic_vector(3 downto 0);
begin
-- clk input is 50 MHz
-- for now 100 MHz is enough
pll_inst : entity work.pll generic map(
multiply_by => 2,
divide_by => 1
)
port map (
inclk0 => clk,
c0 => clk_int
);
--
-- internal reset generation
-- should include the PLL lock signal
--
process(clk_int)
begin
if rising_edge(clk_int) then
if (res_cnt/="111") then
res_cnt <= res_cnt+1;
end if;
int_res <= not res_cnt(0) or not res_cnt(1) or not res_cnt(2);
end if;
end process;
cpu: entity work.leros
port map(clk_int, int_res, ioout, ioin);
-- ioin.rddata(15 downto 4) <= (others => '0');
ua: entity work.uart generic map (
clk_freq => 100000000,
baud_rate => 115200,
txf_depth => 1,
rxf_depth => 1
)
port map(
clk => clk_int,
reset => int_res,
address => ioout.addr(0),
wr_data => ioout.wrdata,
rd => ioout.rd,
wr => ioout.wr,
rd_data => ioin.rddata,
txd => ser_txd,
rxd => ser_rxd
);
process(clk_int)
begin
if rising_edge(clk_int) then
if ioout.wr='1' then
outp <= ioout.wrdata;
end if;
oLEDG <= outp(7 downto 0);
btn_reg <= iKEY;
-- ioin.rddata(3 downto 0) <= not btn_reg;
end if;
end process;
end rtl;
|
<filename>lab_4/lab_4/lab_4.srcs/sources_1/ip/data_mem/data_mem_sim_netlist.vhdl
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
-- Date : Tue Jan 4 21:42:44 2022
-- Host : DESKTOP-NQNJDGK running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- d:/yingzong/step_into_mips-lab_4/lab_4/lab_4/lab_4.srcs/sources_1/ip/data_mem/data_mem_sim_netlist.vhdl
-- Design : data_mem
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tfgg484-1
-- --------------------------------------------------------------------------------
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2021.2"
`protect key_keyowner="Synopsys", key_keyname="<KEY>", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
<KEY>
`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
<KEY>
`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
<KEY>
`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
<KEY>
`protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
<KEY>
`protect key_keyowner="Xilinx", key_keyname="xilinxt_2021_01", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
<KEY>
`protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
HUtfqZ9dh5oZTOAt9a0ebo+wQbzg3izFQ0kVqZN81S4cBjQEF53WUiVlTKBDVjvLNUby4Se9WZjj
<KEY>
`protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=384)
`protect key_block
vYYu2Kvhv3RZi0pFbjRTQ/BBwfilCrGpkMls+Dz6HBGTZvSaC/anWgymoDS0XnoSENGG3Pz3EBF0
19OqLbyna95IHFe2bA7f8RgU9SEUffZ8eXGigfOjAWpZCN07Q77RkhGUKal7okWe3Q6xHtZy83l2
kW8ma3kOYL7GzQjtpbP3lINHLMqpGEo0dzbOHiJ5r6W5U6DsILGsoLQOXcw+MwrevvNRB0KkSklj
QnL8K2AK8PIsJGM6F8dj5KwRYhSBYNb1opuVpiJWlbHgADoeM+dhiRxBLmnaDE8PWs1ReY6uMzzH
SvvO6UEyxQtvS/Smm/uogr1eUFedUaBHPMEXnYlTAv/SKrh942GeknsqfrjGkZxWTN2NEnvpRUwT
<KEY>
`protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
<KEY>
`protect key_keyowner="Synplicity", key_keyname="<KEY>", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
<KEY>
`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
<KEY>aWhnUn7GNrudg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 38336)
`protect data_block
<KEY>
`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity data_mem is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of data_mem : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of data_mem : entity is "data_mem,blk_mem_gen_v8_4_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of data_mem : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of data_mem : entity is "blk_mem_gen_v8_4_5,Vivado 2021.2";
end data_mem;
architecture STRUCTURE of data_mem is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.96495 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "data_mem.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 1024;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 1024;
attribute C_READ_LATENCY_A : integer;
attribute C_READ_LATENCY_A of U0 : label is 1;
attribute C_READ_LATENCY_B : integer;
attribute C_READ_LATENCY_B of U0 : label is 1;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 1024;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 1024;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute is_du_within_envelope : string;
attribute is_du_within_envelope of U0 : label is "true";
attribute x_interface_info : string;
attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
begin
U0: entity work.data_mem_blk_mem_gen_v8_4_5
port map (
addra(31 downto 12) => B"00000000000000000000",
addra(11 downto 2) => addra(11 downto 2),
addra(1 downto 0) => B"00",
addrb(31 downto 0) => B"00000000000000000000000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => B"00000000000000000000000000000000",
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => NLW_U0_doutb_UNCONNECTED(31 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(31 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(31 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(31 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(31 downto 0),
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(3 downto 0) => B"0000",
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => B"0000"
);
end STRUCTURE;
|
<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
LIBRARY altera_mf;
USE altera_mf.all;
entity pcie_top is
port (
inclk_125 : IN std_logic;
pcie_perstn : IN std_logic;
pcie_refclk : IN std_logic;
pcie_rx : IN std_logic_vector(3 DOWNTO 0);
pcie_tx : OUT std_logic_vector(3 DOWNTO 0);
user_led : OUT std_logic_vector(3 DOWNTO 0);
pcie_bus_clk : OUT std_LOGIC;
tx_fifo32_aclr : in std_logic;
tx_fifo32_wrclk : in std_LOGIC;
tx_fifo32_wr : in std_LOGIC;
tx_fifo32_data : in std_LOGIC_vector(63 downto 0);
tx_fifo32_wusedw : out std_LOGIC_vector(11 downto 0);
tx_fifo32_wfull : out std_logic;
rx_fifo32_wfull : in std_logic;
rx_fifo32_wr : out std_logic;
rx_fifo32_data : out std_logic_vector(31 downto 0);
rx_fifo32_reset_req : out std_logic;
--FIFO8 interfaces
exfifo_clk : in std_logic;
exfifo_of_d : in std_logic_vector(7 downto 0);
exfifo_of_wrfull : out std_logic;
exfifo_of_wr : in std_logic;
exfifo_if_d : out std_logic_vector(7 downto 0);
exfifo_if_rdempty : out std_logic;
exfifo_if_rd : in std_logic;
stream_rx_en : in std_logic;
read_32_open : out std_logic
);
end pcie_top;
architecture sample_arch of pcie_top is
component xillybus
port (
clk_125 : IN std_logic;
clk_50 : IN std_logic;
reconfig_clk_locked : IN std_logic;
pcie_perstn : IN std_logic;
pcie_refclk : IN std_logic;
pcie_rx : IN std_logic_vector(3 DOWNTO 0);
bus_clk : OUT std_logic;
pcie_tx : OUT std_logic_vector(3 DOWNTO 0);
quiesce : OUT std_logic;
user_led : OUT std_logic_vector(3 DOWNTO 0);
user_r_mem_8_rden : OUT std_logic;
user_r_mem_8_empty : IN std_logic;
user_r_mem_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_mem_8_eof : IN std_logic;
user_r_mem_8_open : OUT std_logic;
user_w_mem_8_wren : OUT std_logic;
user_w_mem_8_full : IN std_logic;
user_w_mem_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_mem_8_open : OUT std_logic;
user_mem_8_addr : OUT std_logic_vector(4 DOWNTO 0);
user_mem_8_addr_update : OUT std_logic;
user_r_read_32_rden : OUT std_logic;
user_r_read_32_empty : IN std_logic;
user_r_read_32_data : IN std_logic_vector(31 DOWNTO 0);
user_r_read_32_eof : IN std_logic;
user_r_read_32_open : OUT std_logic;
user_r_read_8_rden : OUT std_logic;
user_r_read_8_empty : IN std_logic;
user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_read_8_eof : IN std_logic;
user_r_read_8_open : OUT std_logic;
user_w_write_32_wren : OUT std_logic;
user_w_write_32_full : IN std_logic;
user_w_write_32_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_write_32_open : OUT std_logic;
user_w_write_8_wren : OUT std_logic;
user_w_write_8_full : IN std_logic;
user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_write_8_open : OUT std_logic);
end component;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_fbout : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clk6 : STRING;
port_clk7 : STRING;
port_clk8 : STRING;
port_clk9 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
self_reset_on_loss_lock : STRING;
using_fbmimicbidir_port : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_8b IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrfull : OUT STD_LOGIC
);
END COMPONENT;
component fpga_outfifo IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
rdusedw : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
);
END component;
-- type demo_mem is array(0 TO 31) of std_logic_vector(7 DOWNTO 0);
-- signal demoarray : demo_mem;
signal bus_clk : std_logic;
signal quiesce : std_logic;
signal reset_8 : std_logic;
signal reset_32: std_logic;
signal ram_addr : integer range 0 to 31;
signal user_r_mem_8_rden : std_logic;
signal user_r_mem_8_empty : std_logic;
signal user_r_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_mem_8_eof : std_logic;
signal user_r_mem_8_open : std_logic;
signal user_w_mem_8_wren : std_logic;
signal user_w_mem_8_full : std_logic;
signal user_w_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_mem_8_open : std_logic;
signal user_mem_8_addr : std_logic_vector(4 DOWNTO 0);
signal user_mem_8_addr_update : std_logic;
signal user_r_read_32_rden : std_logic;
signal user_r_read_32_empty : std_logic;
signal user_r_read_32_rdusedw : std_logic_vector(12 downto 0);
signal user_r_read_32_data : std_logic_vector(31 DOWNTO 0);
signal user_r_read_32_eof : std_logic;
signal user_r_read_32_open : std_logic;
signal user_r_read_32_cnt : unsigned(15 downto 0);
signal user_r_read_8_rden : std_logic;
signal user_r_read_8_empty : std_logic;
signal user_r_read_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_read_8_eof : std_logic;
signal user_r_read_8_open : std_logic;
signal user_w_write_32_wren : std_logic;
signal user_w_write_32_full : std_logic;
signal user_w_write_32_data : std_logic_vector(31 DOWNTO 0);
signal user_w_write_32_open : std_logic;
signal user_w_write_8_wren : std_logic;
signal user_w_write_8_full : std_logic;
signal user_w_write_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_write_8_open : std_logic;
signal pll_areset : std_logic;
signal noclock : std_logic;
signal reconfig_clk_locked : std_logic;
signal out_clocks : std_logic_vector(9 DOWNTO 0);
signal in_clocks : std_logic_vector(1 DOWNTO 0);
signal clk_50 : std_logic;
signal clk_125 : std_logic;
signal clr_rx_fifo : std_logic;
signal pct_rdy : std_logic;
type array_type is array (0 to 15) of std_logic_vector(31 downto 0);
type array_type2 is array (0 to 7) of std_logic_vector(11 downto 0);
signal fpga_outfifo_q : std_logic_vector(31 downto 0);
signal fpga_outfifo_empty : std_logic;
signal fpga_outfifo_empty_gen : std_logic;
signal stream_rx_en_sync : std_logic;
signal stream_rx_en_reg0 : std_logic;
signal stream_rx_en_reg1 : std_logic;
signal stream_rx_en_reg2 : std_logic;
begin
sync_reg0 : entity work.sync_reg
port map(bus_clk, '1', stream_rx_en, stream_rx_en_sync);
-- ----------------------------------------------------------------------------
--For synchronising enable signal to bus_clk
-- ----------------------------------------------------------------------------
process(bus_clk, clr_rx_fifo)
begin
if clr_rx_fifo='1' then
stream_rx_en_reg0<='0';
stream_rx_en_reg1<='0';
stream_rx_en_reg2<='0';
elsif (bus_clk'event and bus_clk='1') then
stream_rx_en_reg0<=stream_rx_en_sync;
stream_rx_en_reg1<=stream_rx_en_reg0;
stream_rx_en_reg2<=stream_rx_en_reg1;
end if;
end process;
--pcie bus clock for user needs
pcie_bus_clk <= bus_clk;
-- ----------------------------------------------------------------------------
-- PLL inst for Xillybus
-- ----------------------------------------------------------------------------
clkpll : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 5,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
inclk0_input_frequency => 8000,
intended_device_family => "Cyclone IV",
lpm_hint => "CBX_MODULE_PREFIX=pll_vhdl",
lpm_type => "altpll",
operation_mode => "NO_COMPENSATION",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_fbout => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clk6 => "PORT_UNUSED",
port_clk7 => "PORT_UNUSED",
port_clk8 => "PORT_UNUSED",
port_clk9 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
using_fbmimicbidir_port => "OFF",
width_clock => 10
)
PORT MAP (
areset => pll_areset,
inclk => in_clocks,
locked => reconfig_clk_locked,
clk => out_clocks
);
pll_areset <= '0';
noclock <= '0';
in_clocks <= noclock & inclk_125;
clk_125 <= out_clocks(0);
clk_50 <= out_clocks(1);
-- ----------------------------------------------------------------------------
-- Xillybus inst
-- ----------------------------------------------------------------------------
xillybus_inst : xillybus
port map (
-- Ports related to /dev/xillybus_mem_8
-- FPGA to CPU signals:
user_r_mem_8_rden => user_r_mem_8_rden,
user_r_mem_8_empty => user_r_mem_8_empty,
user_r_mem_8_data => user_r_mem_8_data,
user_r_mem_8_eof => user_r_mem_8_eof,
user_r_mem_8_open => user_r_mem_8_open,
-- CPU to FPGA signals:
user_w_mem_8_wren => user_w_mem_8_wren,
user_w_mem_8_full => user_w_mem_8_full,
user_w_mem_8_data => user_w_mem_8_data,
user_w_mem_8_open => user_w_mem_8_open,
-- Address signals:
user_mem_8_addr => user_mem_8_addr,
user_mem_8_addr_update => user_mem_8_addr_update,
-- Ports related to /dev/xillybus_read_32
-- FPGA to CPU signals:
user_r_read_32_rden => user_r_read_32_rden,
user_r_read_32_empty => user_r_read_32_empty,
user_r_read_32_data => user_r_read_32_data,
user_r_read_32_eof => user_r_read_32_eof,
user_r_read_32_open => user_r_read_32_open,
-- Ports related to /dev/xillybus_read_8
-- FPGA to CPU signals:
user_r_read_8_rden => user_r_read_8_rden,
user_r_read_8_empty => user_r_read_8_empty,
user_r_read_8_data => user_r_read_8_data,
user_r_read_8_eof => user_r_read_8_eof,
user_r_read_8_open => user_r_read_8_open,
-- Ports related to /dev/xillybus_write_32
-- CPU to FPGA signals:
user_w_write_32_wren => user_w_write_32_wren,
user_w_write_32_full => user_w_write_32_full,
user_w_write_32_data => user_w_write_32_data,
user_w_write_32_open => user_w_write_32_open,
-- Ports related to /dev/xillybus_write_8
-- CPU to FPGA signals:
user_w_write_8_wren => user_w_write_8_wren,
user_w_write_8_full => user_w_write_8_full,
user_w_write_8_data => user_w_write_8_data,
user_w_write_8_open => user_w_write_8_open,
-- General signals
clk_125 => clk_125,
clk_50 => clk_50,
reconfig_clk_locked => reconfig_clk_locked,
pcie_perstn => pcie_perstn,
pcie_refclk => pcie_refclk,
pcie_rx => pcie_rx,
bus_clk => bus_clk,
pcie_tx => pcie_tx,
quiesce => quiesce,
user_led => user_led
);
-- ----------------------------------------------------------------------------
-- A simple inferred RAM for Xillybus
-- ----------------------------------------------------------------------------
ram_addr <= conv_integer(user_mem_8_addr);
-- process (bus_clk)
-- begin
-- if (bus_clk'event and bus_clk = '1') then
-- if (user_w_mem_8_wren = '1') then
-- demoarray(ram_addr) <= user_w_mem_8_data;
-- end if;
-- if (user_r_mem_8_rden = '1') then
-- user_r_mem_8_data <= demoarray(ram_addr);
-- end if;
-- end if;
-- end process;
user_r_mem_8_empty <= '0';
user_r_mem_8_eof <= '0';
user_w_mem_8_full <= '0';
rx_fifo32_wr <= user_w_write_32_wren;
rx_fifo32_data <= user_w_write_32_data;
rx_fifo32_reset_req <= not user_w_write_32_open;
read_32_open <= user_r_read_32_open;
-- ----------------------------------------------------------------------------
-- 32 - bit data path
-- ----------------------------------------------------------------------------
fpga_outfifo_inst : fpga_outfifo PORT MAP (
aclr => clr_rx_fifo,
data => tx_fifo32_data,
rdclk => bus_clk,
rdreq => user_r_read_32_rden,
wrclk => tx_fifo32_wrclk,
wrreq => tx_fifo32_wr,
q => fpga_outfifo_q,--user_r_read_32_data,
rdempty => fpga_outfifo_empty,
rdusedw => user_r_read_32_rdusedw,
wrfull => open,
wrusedw => tx_fifo32_wusedw
);
reset_32 <= not (user_w_write_32_open or user_r_read_32_open);
clr_rx_fifo <= not user_r_read_32_open;
--user_r_read_32_eof <= '0';
-- ----------------------------------------------------------------------------
-- 32b data path eof generation
-- ----------------------------------------------------------------------------
process (bus_clk)
begin
if (bus_clk'event and bus_clk='1') then
if user_r_read_32_rden = '1' and stream_rx_en_reg1='0' then
user_r_read_32_eof <= '1';
elsif (stream_rx_en_reg2='1' and stream_rx_en_reg1='0') and user_r_read_32_empty='1' then
user_r_read_32_eof <= '1';
else
user_r_read_32_eof <= '0';
end if;
end if;
end process;
-- ----------------------------------------------------------------------------
-- 8 - bit data path.
-- ----------------------------------------------------------------------------
--dual port FIFO
fifo_8b_fpga2pc : fifo_8b PORT MAP (
aclr => reset_8,
data => exfifo_of_d,
rdclk => bus_clk,
rdreq => user_r_read_8_rden,
wrclk => exfifo_clk,
wrreq => exfifo_of_wr,
q => user_r_read_8_data,
rdempty => user_r_read_8_empty,
wrfull => exfifo_of_wrfull
);
fifo_8b_pc2fpga : fifo_8b PORT MAP (
aclr => reset_8,
data => user_w_write_8_data,
rdclk => exfifo_clk,
rdreq => exfifo_if_rd,
wrclk => bus_clk,
wrreq => user_w_write_8_wren,
q => exfifo_if_d,
rdempty => exfifo_if_rdempty,
wrfull => user_w_write_8_full
);
user_r_read_32_empty <=fpga_outfifo_empty;
user_w_write_32_full <=rx_fifo32_wfull;
user_r_read_32_data <=fpga_outfifo_q;
reset_8 <= not (user_w_write_8_open or user_r_read_8_open);
user_r_read_8_eof <= '0';
end sample_arch;
|
library verilog;
use verilog.vl_types.all;
entity eth_audio_transmit is
generic(
BOARD_MAC : vl_logic_vector(0 to 47) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1, Hi0, Hi0, Hi0, Hi1, Hi0, Hi0, Hi1, Hi0, Hi0, Hi0, Hi1, Hi0, Hi0, Hi0, Hi1, Hi1, Hi0, Hi0, Hi1, Hi1, Hi0, Hi1, Hi0, Hi0, Hi0, Hi1, Hi0, Hi0, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1);
BOARD_IP : vl_logic_vector(31 downto 0) := (Hi1, Hi1, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1, Hi0, Hi1, Hi1, Hi1, Hi1, Hi0, Hi1, Hi1);
DES_MAC : vl_logic_vector(0 to 47) := (Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1);
DES_IP : vl_logic_vector(31 downto 0) := (Hi1, Hi1, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1, Hi0, Hi1, Hi1, Hi1, Hi1, Hi0, Hi1, Hi1)
);
port(
sys_clk : in vl_logic;
sys_rst_n : in vl_logic;
eth_rx_clk : in vl_logic;
eth_rxdv : in vl_logic;
eth_tx_clk : in vl_logic;
eth_rx_data : in vl_logic_vector(3 downto 0);
eth_tx_en : out vl_logic;
eth_tx_data : out vl_logic_vector(3 downto 0);
eth_rst_n : out vl_logic;
aud_bclk : in vl_logic;
aud_lrc : in vl_logic;
aud_adcdat : in vl_logic;
aud_mclk : out vl_logic;
aud_dacdat : out vl_logic;
aud_scl : out vl_logic;
aud_sda : inout vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of BOARD_MAC : constant is 1;
attribute mti_svvh_generic_type of BOARD_IP : constant is 1;
attribute mti_svvh_generic_type of DES_MAC : constant is 1;
attribute mti_svvh_generic_type of DES_IP : constant is 1;
end eth_audio_transmit;
|
-- ----------------------------------------------------------------------------
-- FILE: sl_ctrl.vhd
-- DESCRIPTION: writes to fifo and checks for unused samples
-- DATE: Jan 25, 2015
-- AUTHOR(s): <NAME>
-- REVISIONS:
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity rfifo_ctrl is
port(
data : in std_logic_vector(31 downto 0);
wrreq : in std_logic;
wrreq_o : out std_logic
);
end rfifo_ctrl;
architecture arc of rfifo_ctrl is
signal data_msb, data_lsb : std_logic_vector(15 downto 0);
begin
data_msb <= data(31 downto 16);
data_lsb <= data(15 downto 0);
ctrl_proc : process(wrreq, data_msb, data_lsb)
begin
wrreq_o <= '0';
if wrreq = '1' then
if data_msb(15) = '1' or data_lsb(15) = '1' then
wrreq_o <= '0';
else
wrreq_o <= '1';
end if;
end if;
end process;
end arc;
|
-- Instruction Input Controller
--
-- Input:
-- CCLK:
-- INCI: Add an instruction later
-- DECI: Remove the previous instruction
-- RST: Reset instruction number to zero
--
-- Output:
-- ADDR: Instruction Write Address(Number of instructions)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY IIC IS
PORT(
CLK : IN STD_LOGIC;
INC_DEC : IN STD_LOGIC;
RST : IN STD_LOGIC := '0';
ADDR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END IIC;
ARCHITECTURE SYN OF IIC IS
SIGNAL count : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
BEGIN
PROCESS(CLK, INC_DEC, RST)
BEGIN
IF RST = '1' THEN
count <= "0000";
ELSIF CLK'EVENT AND CLK = '1' THEN
IF INC_DEC = '0' THEN
IF count < "1111" THEN
count <= count + 1;
END IF;
ELSE
IF count > "0000" THEN
count <= count - 1;
END IF;
END IF;
END IF;
END PROCESS;
ADDR <= count;
END SYN;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity zero_counter is
port (
rs : in std_ulogic_vector(63 downto 0);
count_right : in std_ulogic;
is_32bit : in std_ulogic;
result : out std_ulogic_vector(63 downto 0)
);
end entity zero_counter;
architecture behaviour of zero_counter is
signal y, z : std_ulogic_vector(3 downto 0);
signal v16 : std_ulogic_vector(15 downto 0);
signal v4 : std_ulogic_vector(3 downto 0);
signal sel : std_ulogic_vector(5 downto 0);
-- Return the index of the leftmost or rightmost 1 in a set of 4 bits.
-- Assumes v is not "0000"; if it is, return (right ? "11" : "00").
function encoder(v: std_ulogic_vector(3 downto 0); right: std_ulogic) return std_ulogic_vector is
begin
if right = '0' then
if v(3) = '1' then
return "11";
elsif v(2) = '1' then
return "10";
elsif v(1) = '1' then
return "01";
else
return "00";
end if;
else
if v(0) = '1' then
return "00";
elsif v(1) = '1' then
return "01";
elsif v(2) = '1' then
return "10";
else
return "11";
end if;
end if;
end;
begin
zerocounter0: process(all)
begin
-- Test 4 groups of 16 bits each.
-- The top 2 groups are considered to be zero in 32-bit mode.
z(0) <= or (rs(15 downto 0));
z(1) <= or (rs(31 downto 16));
z(2) <= or (rs(47 downto 32));
z(3) <= or (rs(63 downto 48));
if is_32bit = '0' then
sel(5 downto 4) <= encoder(z, count_right);
else
sel(5) <= '0';
if count_right = '0' then
sel(4) <= z(1);
else
sel(4) <= not z(0);
end if;
end if;
-- Select the leftmost/rightmost non-zero group of 16 bits
case sel(5 downto 4) is
when "00" =>
v16 <= rs(15 downto 0);
when "01" =>
v16 <= rs(31 downto 16);
when "10" =>
v16 <= rs(47 downto 32);
when others =>
v16 <= rs(63 downto 48);
end case;
-- Test 4 groups of 4 bits
y(0) <= or (v16(3 downto 0));
y(1) <= or (v16(7 downto 4));
y(2) <= or (v16(11 downto 8));
y(3) <= or (v16(15 downto 12));
sel(3 downto 2) <= encoder(y, count_right);
-- Select the leftmost/rightmost non-zero group of 4 bits
case sel(3 downto 2) is
when "00" =>
v4 <= v16(3 downto 0);
when "01" =>
v4 <= v16(7 downto 4);
when "10" =>
v4 <= v16(11 downto 8);
when others =>
v4 <= v16(15 downto 12);
end case;
sel(1 downto 0) <= encoder(v4, count_right);
-- sel is now the index of the leftmost/rightmost 1 bit in rs
if v4 = "0000" then
-- operand is zero, return 32 for 32-bit, else 64
result <= x"00000000000000" & '0' & not is_32bit & is_32bit & "00000";
elsif count_right = '0' then
-- return (63 - sel), trimmed to 5 bits in 32-bit mode
result <= x"00000000000000" & "00" & (not sel(5) and not is_32bit) & not sel(4 downto 0);
else
result <= x"00000000000000" & "00" & sel;
end if;
end process;
end behaviour;
|
------------------------------------------------------------
--DESIGN CELLPC BEGINS here : It is the basic building block of pch and pcl
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity CELLPC is
port( C : out std_ulogic;
load_en :in std_logic ;
count_en :in std_logic ;
data_in :in std_logic ;
clrn :in std_logic ;
clk :in std_logic );
end CELLPC;
architecture behav of CELLPC is
signal C_sig: std_logic ;
signal net20, net10 ,net16 : std_ulogic;
begin
process(load_en,count_en,data_in,clrn,clk)
variable sel : std_logic_vector(1 downto 0) ;
begin
sel := load_en&count_en ;
if(clrn = '1') then
C_sig <= '0' ;
elsif(rising_edge(clk)) then
case sel is
when "00" =>
C_sig <= C_sig;
when "01" =>
C_sig <= not(C_sig);
when "10" =>
C_sig <= data_in;
when "11" =>
C_sig <= not(C_sig);
when others =>
null ;
end case ;
end if ;
end process ;
C <= C_sig ;
end behav ;
------------------------------------------------------------
--DESIGN CELLPC ENDS here
------------------------------------------------------------
|
<filename>src/vhdl/examples/invent_a_chip_uart_test_trigger.vhdl
----------------------------------------------------------------------
-- Project : Invent a Chip
-- Authors : <NAME>
-- Year : 2013
-- Description : This example waits for a specific trigger word to
-- receive over UART. After the trigger-command is
-- detected some predefined datawords are send to
-- the PC.
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end invent_a_chip;
architecture rtl of invent_a_chip is
-- number of words to send after start command
constant CV_NO_DATA : natural := 5;
-- state register
type state_t is (WAIT_FOR_COMMAND, SEND_DATA);
signal state, state_nxt : state_t;
-- counter register
signal cnt, cnt_nxt : unsigned(to_log2(CV_NO_DATA)-1 downto 0);
-- start-command
constant CV_START_COMMAND : std_ulogic_vector(7 downto 0) := "00000011";
-- data to be send after command
type data_t is array (0 to CV_NO_DATA-1) of std_ulogic_vector(7 downto 0);
constant data : data_t := ("10101010", "01010101", "11110000", "00001111", "11001100");
begin
-- sequential process
process (clock, reset)
begin
-- async reset
if reset = '1' then
state <= WAIT_FOR_COMMAND;
cnt <= (others => '0');
elsif rising_edge(clock) then
state <= state_nxt;
cnt <= cnt_nxt;
end if;
end process;
-- logic
process (state, cnt, uart_irq_rx, uart_irq_tx, uart_din)
begin
-- standard assignments
-- hold values of registers
state_nxt <= state;
cnt_nxt <= cnt;
-- set bus signals to standard values (not in use)
uart_cs <= '0';
uart_wr <= '0';
uart_addr <= (others => '0');
uart_dout <= (others => '0');
uart_ack_rx <= '0';
uart_ack_tx <= '0';
-- turn of leds
led_green <= (others => '0');
led_red <= (others => '0');
-- state machine
case state is
-- wait for interrupt from UART
when WAIT_FOR_COMMAND =>
-- indicate state WAIT_FOR_COMMAND
led_green(0) <= '1';
-- data is ready in receive-register
if uart_irq_rx = '1' then
-- select uart-interface
uart_cs <= '1';
-- address of send/receive-register
uart_addr <= CV_ADDR_UART_DATA_RX;
-- read-mode
uart_wr <= '0';
-- check if received data is = start-command
if uart_din(7 downto 0) = CV_START_COMMAND then
-- next state
state_nxt <= SEND_DATA;
-- reset counter
cnt_nxt <= (others => '0');
end if;
end if;
-- send data from data-array
when SEND_DATA =>
-- indicate state SEND_DATA
led_green(1) <= '1';
-- check if send-register is empty
if uart_irq_tx = '1' then
-- select uart-interface
uart_cs <= '1';
-- address of send/receive-register
uart_addr <= CV_ADDR_UART_DATA_TX;
-- write-mode
uart_wr <= '1';
-- select data from array
uart_dout(7 downto 0) <= data(to_integer(cnt));
-- IS NOT last word
if cnt /= to_unsigned(CV_NO_DATA-1, cnt'length) then
-- inc counter
cnt_nxt <= cnt + to_unsigned(1, cnt'length);
-- IS last word
else
-- next state
state_nxt <= WAIT_FOR_COMMAND;
end if;
end if;
end case;
end process;
-- default assignments for unused signals
gp_ctrl <= (others => '0');
gp_out <= (others => '0');
sevenseg_cs <= '0';
sevenseg_wr <= '0';
sevenseg_addr <= (others => '0');
sevenseg_dout <= (others => '0');
adc_dac_cs <= '0';
adc_dac_wr <= '0';
adc_dac_addr <= (others => '0');
adc_dac_dout <= (others => '0');
audio_cs <= '0';
audio_wr <= '0';
audio_addr <= (others => '0');
audio_dout <= (others => '0');
audio_ack_left <= '0';
audio_ack_right <= '0';
ir_cs <= '0';
ir_wr <= '0';
ir_addr <= (others => '0');
ir_dout <= (others => '0');
ir_ack_rx <= '0';
lcd_cs <= '0';
lcd_wr <= '0';
lcd_addr <= (others => '0');
lcd_dout <= (others => '0');
lcd_ack_rdy <= '0';
sram_cs <= '0';
sram_wr <= '0';
sram_addr <= (others => '0');
sram_dout <= (others => '0');
end rtl;
|
<gh_stars>1-10
--------------------------------------------------------------------------------
-- __ _ _ _ --
-- / _(_) | | | | --
-- __ _ _ _ ___ ___ _ __ | |_ _ ___| | __| | --
-- / _` | | | |/ _ \/ _ \ '_ \| _| |/ _ \ |/ _` | --
-- | (_| | |_| | __/ __/ | | | | | | __/ | (_| | --
-- \__, |\__,_|\___|\___|_| |_|_| |_|\___|_|\__,_| --
-- | | --
-- |_| --
-- --
-- --
-- Peripheral-NTM for MPSoC --
-- Neural Turing Machine for MPSoC --
-- --
--------------------------------------------------------------------------------
-- Copyright (c) 2020-2021 by the author(s)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
--------------------------------------------------------------------------------
-- Author(s):
-- <NAME> <<EMAIL>>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ntm_math_pkg.all;
use work.dnc_core_pkg.all;
use work.ntm_lstm_controller_pkg.all;
entity dnc_top is
generic (
DATA_SIZE : integer := 512
);
port (
-- GLOBAL
CLK : in std_logic;
RST : in std_logic;
-- CONTROL
START : in std_logic;
READY : out std_logic;
W_IN_L_ENABLE : in std_logic; -- for l in 0 to L-1
W_IN_X_ENABLE : in std_logic; -- for x in 0 to X-1
K_IN_I_ENABLE : in std_logic; -- for i in 0 to R-1 (read heads flow)
K_IN_L_ENABLE : in std_logic; -- for l in 0 to L-1
K_IN_K_ENABLE : in std_logic; -- for k in 0 to W-1
B_IN_ENABLE : in std_logic; -- for l in 0 to L-1
X_IN_ENABLE : in std_logic; -- for x in 0 to X-1
Y_OUT_ENABLE : out std_logic; -- for y in 0 to Y-1
-- DATA
SIZE_X_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_Y_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_N_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_W_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_L_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
SIZE_R_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
W_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
K_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
B_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
X_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
Y_OUT : out std_logic_vector(DATA_SIZE-1 downto 0)
);
end entity;
architecture dnc_top_architecture of dnc_top is
-----------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- CONTROLLER
-----------------------------------------------------------------------
-- CONTROLLER
-- CONTROL
signal start_controller : std_logic;
signal ready_controller : std_logic;
signal w_in_l_enable_controller : std_logic;
signal w_in_x_enable_controller : std_logic;
signal k_in_i_enable_controller : std_logic;
signal k_in_l_enable_controller : std_logic;
signal k_in_k_enable_controller : std_logic;
signal b_in_enable_controller : std_logic;
signal x_in_enable_controller : std_logic;
signal r_in_i_enable_controller : std_logic;
signal r_in_k_enable_controller : std_logic;
signal h_out_enable_controller : std_logic;
-- DATA
signal size_x_in_controller : std_logic_vector(DATA_SIZE-1 downto 0);
signal size_w_in_controller : std_logic_vector(DATA_SIZE-1 downto 0);
signal size_l_in_controller : std_logic_vector(DATA_SIZE-1 downto 0);
signal size_r_in_controller : std_logic_vector(DATA_SIZE-1 downto 0);
signal w_in_controller : std_logic_vector(DATA_SIZE-1 downto 0);
signal k_in_controller : std_logic_vector(DATA_SIZE-1 downto 0);
signal b_in_controller : std_logic_vector(DATA_SIZE-1 downto 0);
signal x_in_controller : std_logic_vector(DATA_SIZE-1 downto 0);
signal r_in_controller : std_logic_vector(DATA_SIZE-1 downto 0);
signal h_out_controller : std_logic_vector(DATA_SIZE-1 downto 0);
-- CONTROLLER OUTPUT VECTOR
-- CONTROL
signal start_controller_output_vector : std_logic;
signal ready_controller_output_vector : std_logic;
signal u_in_j_enable_controller_output_vector : std_logic;
signal u_in_l_enable_controller_output_vector : std_logic;
signal h_in_enable_controller_output_vector : std_logic;
signal nu_out_enable_controller_output_vector : std_logic;
-- DATA
signal size_y_in_controller_output_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal size_l_in_controller_output_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal u_in_controller_output_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal h_in_controller_output_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal nu_out_controller_output_vector : std_logic_vector(DATA_SIZE-1 downto 0);
-- OUTPUT VECTOR
-- CONTROL
signal start_output_vector : std_logic;
signal ready_output_vector : std_logic;
signal k_in_i_enable_output_vector : std_logic;
signal k_in_y_enable_output_vector : std_logic;
signal k_in_k_enable_output_vector : std_logic;
signal r_in_i_enable_output_vector : std_logic;
signal r_in_k_enable_output_vector : std_logic;
signal nu_in_enable_output_vector : std_logic;
signal y_in_enable_output_vector : std_logic;
-- DATA
signal size_y_in_output_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal size_w_in_output_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal size_r_in_output_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal k_in_output_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal r_in_output_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal nu_in_output_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal y_out_output_vector : std_logic_vector(DATA_SIZE-1 downto 0);
-----------------------------------------------------------------------
-- READ HEADS
-----------------------------------------------------------------------
-- FREE GATES
-- CONTROL
signal f_in_enable_free_gates : std_logic;
signal f_out_enable_free_gates : std_logic;
signal start_free_gates : std_logic;
signal ready_free_gates : std_logic;
-- DATA
signal size_r_in_free_gates : std_logic_vector(DATA_SIZE-1 downto 0);
signal f_in_free_gates : std_logic_vector(DATA_SIZE-1 downto 0);
signal f_out_free_gates : std_logic;
-- READ KEYS
-- CONTROL
signal k_in_i_enable_read_keys : std_logic;
signal k_in_k_enable_read_keys : std_logic;
signal k_out_i_enable_read_keys : std_logic;
signal k_out_k_enable_read_keys : std_logic;
signal start_read_keys : std_logic;
signal ready_read_keys : std_logic;
-- DATA
signal size_r_in_read_keys : std_logic_vector(DATA_SIZE-1 downto 0);
signal size_w_in_read_keys : std_logic_vector(DATA_SIZE-1 downto 0);
signal k_in_read_keys : std_logic_vector(DATA_SIZE-1 downto 0);
signal k_out_read_keys : std_logic_vector(DATA_SIZE-1 downto 0);
-- READ MODES
-- CONTROL
signal start_read_modes : std_logic;
signal ready_read_modes : std_logic;
signal pi_in_i_enable_read_modes : std_logic;
signal pi_in_p_enable_read_modes : std_logic;
signal pi_out_i_enable_read_modes : std_logic;
signal pi_out_p_enable_read_modes : std_logic;
-- DATA
signal size_r_in_read_modes : std_logic_vector(DATA_SIZE-1 downto 0);
signal pi_in_read_modes : std_logic_vector(DATA_SIZE-1 downto 0);
signal pi_out_read_modes : std_logic_vector(DATA_SIZE-1 downto 0);
-- READ STRENGTHS
-- CONTROL
signal beta_in_enable_read_strengths : std_logic;
signal beta_out_enable_read_strengths : std_logic;
signal start_read_strengths : std_logic;
signal ready_read_strengths : std_logic;
-- DATA
signal size_r_in_read_strengths : std_logic_vector(DATA_SIZE-1 downto 0);
signal beta_in_read_strengths : std_logic_vector(DATA_SIZE-1 downto 0);
signal beta_out_read_strengths : std_logic_vector(DATA_SIZE-1 downto 0);
-- READ INTERFACE VECTOR
-- CONTROL
signal start_read_interface_vector : std_logic;
signal ready_read_interface_vector : std_logic;
-- Read Key
signal wk_in_i_enable_read_interface_vector : std_logic;
signal wk_in_l_enable_read_interface_vector : std_logic;
signal wk_in_k_enable_read_interface_vector : std_logic;
signal k_out_i_enable_read_interface_vector : std_logic;
signal k_out_k_enable_read_interface_vector : std_logic;
-- Read Strength
signal wbeta_in_i_enable_read_interface_vector : std_logic;
signal wbeta_in_l_enable_read_interface_vector : std_logic;
signal beta_out_enable_read_interface_vector : std_logic;
-- Free Gate
signal wf_in_i_enable_read_interface_vector : std_logic;
signal wf_in_l_enable_read_interface_vector : std_logic;
signal f_out_enable_read_interface_vector : std_logic;
-- Read Mode
signal wpi_in_i_enable_read_interface_vector : std_logic;
signal wpi_in_l_enable_read_interface_vector : std_logic;
signal pi_out_enable_read_interface_vector : std_logic;
-- Hidden State
signal h_in_enable_read_interface_vector : std_logic;
-- DATA
signal size_w_in_read_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal size_l_in_read_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal size_r_in_read_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal wk_in_read_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal wbeta_in_read_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal wf_in_read_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal wpi_in_read_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal h_in_read_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal k_out_read_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal beta_out_read_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal f_out_read_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal pi_out_read_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
-----------------------------------------------------------------------
-- WRITE HEADS
-----------------------------------------------------------------------
-- ALLOCATION GATE
-- CONTROL
signal start_allocation_gate : std_logic;
signal ready_allocation_gate : std_logic;
-- DATA
signal ga_in_allocation_gate : std_logic_vector(DATA_SIZE-1 downto 0);
signal ga_out_allocation_gate : std_logic;
-- ERASE VECTOR
-- CONTROL
signal start_erase_vector : std_logic;
signal ready_erase_vector : std_logic;
signal e_in_enable_erase_vector : std_logic;
signal e_out_enable_erase_vector : std_logic;
-- DATA
signal size_w_in_erase_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal e_in_erase_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal e_out_erase_vector : std_logic;
-- WRITE GATE
-- CONTROL
signal start_write_gate : std_logic;
signal ready_write_gate : std_logic;
-- DATA
signal gw_in_write_gate : std_logic_vector(DATA_SIZE-1 downto 0);
signal gw_out_write_gate : std_logic;
-- WRITE KEY
-- CONTROL
signal start_write_key : std_logic;
signal ready_write_key : std_logic;
signal k_in_enable_write_key : std_logic;
signal k_out_enable_write_key : std_logic;
-- DATA
signal size_w_in_write_key : std_logic_vector(DATA_SIZE-1 downto 0);
signal k_in_write_key : std_logic_vector(DATA_SIZE-1 downto 0);
signal k_out_write_key : std_logic_vector(DATA_SIZE-1 downto 0);
-- WRITE STRENGHT
-- CONTROL
signal start_write_strength : std_logic;
signal ready_write_strength : std_logic;
-- DATA
signal beta_in_write_strength : std_logic_vector(DATA_SIZE-1 downto 0);
signal beta_out_write_strength : std_logic_vector(DATA_SIZE-1 downto 0);
-- WRITE VECTOR
-- CONTROL
signal start_write_vector : std_logic;
signal ready_write_vector : std_logic;
signal v_in_enable_write_vector : std_logic;
signal v_out_enable_write_vector : std_logic;
-- DATA
signal size_w_in_write_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal v_in_write_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal v_out_write_vector : std_logic_vector(DATA_SIZE-1 downto 0);
-- WRITE INTERFACE VECTOR
-- CONTROL
signal start_write_interface_vector : std_logic;
signal ready_write_interface_vector : std_logic;
-- Write Key
signal wk_in_l_enable_write_interface_vector : std_logic;
signal wk_in_k_enable_write_interface_vector : std_logic;
signal k_out_enable_write_interface_vector : std_logic;
-- Write Strength
signal wbeta_in_enable_write_interface_vector : std_logic;
-- Erase Vector
signal we_in_l_enable_write_interface_vector : std_logic;
signal we_in_k_enable_write_interface_vector : std_logic;
signal e_out_enable_write_interface_vector : std_logic;
-- Write Vector
signal wv_in_l_enable_write_interface_vector : std_logic;
signal wv_in_k_enable_write_interface_vector : std_logic;
signal v_out_enable_write_interface_vector : std_logic;
-- Allocation Gate
signal wga_in_enable_write_interface_vector : std_logic;
-- Write Gate
signal wgw_in_enable_write_interface_vector : std_logic;
-- Hidden State
signal h_in_enable_write_interface_vector : std_logic;
-- DATA
signal size_w_in_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal size_l_in_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal size_r_in_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal wk_in_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal wbeta_in_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal we_in_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal wv_in_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal wga_in_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal wgw_in_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal h_in_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal k_out_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal beta_out_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal e_out_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal v_out_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal ga_out_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
signal gw_out_write_interface_vector : std_logic_vector(DATA_SIZE-1 downto 0);
-----------------------------------------------------------------------
-- MEMORY
-----------------------------------------------------------------------
-- CONTROL
signal start_addressing : std_logic;
signal ready_addressing : std_logic;
signal k_read_in_i_enable_addressing : std_logic;
signal k_read_in_k_enable_addressing : std_logic;
signal beta_read_in_enable_addressing : std_logic;
signal f_read_in_enable_addressing : std_logic;
signal pi_read_in_enable_addressing : std_logic;
signal k_write_in_k_enable_addressing : std_logic;
signal e_write_in_k_enable_addressing : std_logic;
signal v_write_in_k_enable_addressing : std_logic;
-- DATA
signal size_r_in_addressing : std_logic_vector(DATA_SIZE-1 downto 0);
signal size_w_in_addressing : std_logic_vector(DATA_SIZE-1 downto 0);
signal k_read_in_addressing : std_logic_vector(DATA_SIZE-1 downto 0);
signal beta_read_in_addressing : std_logic_vector(DATA_SIZE-1 downto 0);
signal f_read_in_addressing : std_logic_vector(DATA_SIZE-1 downto 0);
signal pi_read_in_addressing : std_logic_vector(DATA_SIZE-1 downto 0);
signal k_write_in_addressing : std_logic_vector(DATA_SIZE-1 downto 0);
signal beta_write_in_addressing : std_logic_vector(DATA_SIZE-1 downto 0);
signal e_write_in_addressing : std_logic_vector(DATA_SIZE-1 downto 0);
signal v_write_in_addressing : std_logic_vector(DATA_SIZE-1 downto 0);
signal ga_write_in_addressing : std_logic_vector(DATA_SIZE-1 downto 0);
signal gw_write_in_addressing : std_logic_vector(DATA_SIZE-1 downto 0);
signal r_out_addressing : std_logic_vector(DATA_SIZE-1 downto 0);
begin
-----------------------------------------------------------------------
-- Body
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- CONTROLLER
-----------------------------------------------------------------------
ntm_controller_i : ntm_controller
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_controller,
READY => ready_controller,
W_IN_L_ENABLE => w_in_l_enable_controller,
W_IN_X_ENABLE => w_in_x_enable_controller,
K_IN_I_ENABLE => k_in_i_enable_controller,
K_IN_L_ENABLE => k_in_l_enable_controller,
K_IN_K_ENABLE => k_in_k_enable_controller,
B_IN_ENABLE => b_in_enable_controller,
X_IN_ENABLE => x_in_enable_controller,
R_IN_I_ENABLE => r_in_i_enable_controller,
R_IN_K_ENABLE => r_in_k_enable_controller,
H_OUT_ENABLE => h_out_enable_controller,
-- DATA
SIZE_X_IN => size_x_in_controller,
SIZE_W_IN => size_w_in_controller,
SIZE_L_IN => size_l_in_controller,
SIZE_R_IN => size_r_in_controller,
W_IN => w_in_controller,
K_IN => k_in_controller,
B_IN => b_in_controller,
X_IN => x_in_controller,
R_IN => r_in_controller,
H_OUT => h_out_controller
);
-- CONTROLLER OUTPUT VECTOR
controller_output_vector : dnc_controller_output_vector
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_controller_output_vector,
READY => ready_controller_output_vector,
U_IN_Y_ENABLE => u_in_j_enable_controller_output_vector,
U_IN_L_ENABLE => u_in_l_enable_controller_output_vector,
H_IN_ENABLE => h_in_enable_controller_output_vector,
NU_ENABLE_OUT => nu_out_enable_controller_output_vector,
-- DATA
SIZE_Y_IN => size_y_in_controller_output_vector,
SIZE_L_IN => size_l_in_controller_output_vector,
U_IN => u_in_controller_output_vector,
H_IN => h_in_controller_output_vector,
NU_OUT => nu_out_controller_output_vector
);
-- OUTPUT VECTOR
output_vector_i : dnc_output_vector
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_output_vector,
READY => ready_output_vector,
K_IN_I_ENABLE => k_in_i_enable_output_vector,
K_IN_Y_ENABLE => k_in_y_enable_output_vector,
K_IN_K_ENABLE => k_in_k_enable_output_vector,
R_IN_I_ENABLE => r_in_i_enable_output_vector,
R_IN_K_ENABLE => r_in_k_enable_output_vector,
NU_IN_ENABLE => nu_in_enable_output_vector,
Y_OUT_ENABLE => y_in_enable_output_vector,
-- DATA
SIZE_Y_IN => size_y_in_output_vector,
SIZE_W_IN => size_w_in_output_vector,
SIZE_R_IN => size_r_in_output_vector,
K_IN => k_in_output_vector,
R_IN => r_in_output_vector,
NU_IN => nu_in_output_vector,
Y_OUT => y_out_output_vector
);
-----------------------------------------------------------------------
-- READ HEADS
-----------------------------------------------------------------------
-- FREE GATES
free_gates : dnc_free_gates
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_free_gates,
READY => ready_free_gates,
F_IN_ENABLE => f_in_enable_free_gates,
F_OUT_ENABLE => f_out_enable_free_gates,
-- DATA
SIZE_R_IN => size_r_in_free_gates,
F_IN => f_in_free_gates,
F_OUT => f_out_free_gates
);
-- READ KEYS
read_keys : dnc_read_keys
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_read_keys,
READY => ready_read_keys,
K_IN_I_ENABLE => k_in_i_enable_read_keys,
K_IN_K_ENABLE => k_in_k_enable_read_keys,
K_OUT_I_ENABLE => k_out_i_enable_read_keys,
K_OUT_K_ENABLE => k_out_k_enable_read_keys,
-- DATA
SIZE_R_IN => size_r_in_read_keys,
SIZE_W_IN => size_w_in_read_keys,
K_IN => k_in_read_keys,
K_OUT => k_out_read_keys
);
-- READ MODES
read_modes : dnc_read_modes
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_read_modes,
READY => ready_read_modes,
PI_IN_I_ENABLE => pi_in_i_enable_read_modes,
PI_IN_P_ENABLE => pi_in_p_enable_read_modes,
PI_OUT_I_ENABLE => pi_out_i_enable_read_modes,
PI_OUT_P_ENABLE => pi_out_p_enable_read_modes,
-- DATA
SIZE_R_IN => size_r_in_free_gates,
PI_IN => pi_in_read_modes,
PI_OUT => pi_out_read_modes
);
-- READ STRENGTHS
read_strengths : dnc_read_strengths
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_read_strengths,
READY => ready_read_strengths,
BETA_IN_ENABLE => beta_in_enable_read_strengths,
BETA_OUT_ENABLE => beta_out_enable_read_strengths,
-- DATA
SIZE_R_IN => size_r_in_free_gates,
BETA_IN => beta_in_read_strengths,
BETA_OUT => beta_out_read_strengths
);
-- READ INTERFACE VECTOR
read_interface_vector : dnc_read_interface_vector
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_read_interface_vector,
READY => ready_read_interface_vector,
-- Read Key
WK_IN_I_ENABLE => wk_in_i_enable_read_interface_vector,
WK_IN_L_ENABLE => wk_in_l_enable_read_interface_vector,
WK_IN_K_ENABLE => wk_in_k_enable_read_interface_vector,
K_OUT_I_ENABLE => k_out_i_enable_read_interface_vector,
K_OUT_K_ENABLE => k_out_k_enable_read_interface_vector,
-- Read Strength
WBETA_IN_I_ENABLE => wbeta_in_i_enable_read_interface_vector,
WBETA_IN_L_ENABLE => wbeta_in_l_enable_read_interface_vector,
BETA_OUT_ENABLE => beta_out_enable_read_interface_vector,
-- Free Gate
WF_IN_I_ENABLE => wf_in_i_enable_read_interface_vector,
WF_IN_L_ENABLE => wf_in_l_enable_read_interface_vector,
F_OUT_ENABLE => f_out_enable_read_interface_vector,
-- Read Mode
WPI_IN_I_ENABLE => wpi_in_i_enable_read_interface_vector,
WPI_IN_L_ENABLE => wpi_in_l_enable_read_interface_vector,
PI_OUT_ENABLE => pi_out_enable_read_interface_vector,
-- Hidden State
H_IN_ENABLE => h_in_enable_read_interface_vector,
-- DATA
SIZE_W_IN => size_w_in_read_interface_vector,
SIZE_L_IN => size_l_in_read_interface_vector,
SIZE_R_IN => size_r_in_read_interface_vector,
WK_IN => wk_in_read_interface_vector,
WBETA_IN => wbeta_in_read_interface_vector,
WF_IN => wf_in_read_interface_vector,
WPI_IN => wpi_in_read_interface_vector,
H_IN => h_in_read_interface_vector,
K_OUT => k_out_read_interface_vector,
BETA_OUT => beta_out_read_interface_vector,
F_OUT => f_out_read_interface_vector,
PI_OUT => pi_out_read_interface_vector
);
-----------------------------------------------------------------------
-- WRITE HEADS
-----------------------------------------------------------------------
-- ALLOCATION GATE
allocation_gate : dnc_allocation_gate
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_allocation_gate,
READY => ready_allocation_gate,
-- DATA
GA_IN => ga_in_allocation_gate,
GA_OUT => ga_out_allocation_gate
);
-- ERASE VECTOR
erase_vector : dnc_erase_vector
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_erase_vector,
READY => ready_erase_vector,
E_IN_ENABLE => e_in_enable_erase_vector,
E_OUT_ENABLE => e_out_enable_erase_vector,
-- DATA
SIZE_W_IN => size_w_in_erase_vector,
E_IN => e_in_erase_vector,
E_OUT => e_out_erase_vector
);
-- WRITE GATE
write_gate : dnc_write_gate
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_write_gate,
READY => ready_write_gate,
-- DATA
GW_IN => gw_in_write_gate,
GW_OUT => gw_out_write_gate
);
-- WRITE KEY
write_key : dnc_write_key
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_write_key,
READY => ready_write_key,
K_IN_ENABLE => k_in_enable_write_key,
K_OUT_ENABLE => k_out_enable_write_key,
-- DATA
SIZE_W_IN => size_w_in_write_key,
K_IN => k_in_write_key,
K_OUT => k_out_write_key
);
-- WRITE STRENGTH
write_strength : dnc_write_strength
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_write_strength,
READY => ready_write_strength,
-- DATA
BETA_IN => beta_in_write_strength,
BETA_OUT => beta_out_write_strength
);
-- WRITE VECTOR
write_vector : dnc_write_vector
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_write_vector,
READY => ready_write_vector,
V_IN_ENABLE => v_in_enable_write_vector,
V_OUT_ENABLE => v_out_enable_write_vector,
-- DATA
SIZE_W_IN => size_w_in_write_vector,
V_IN => v_in_write_vector,
V_OUT => v_out_write_vector
);
-- WRITE INTERFACE VECTOR
write_interface_vector : dnc_write_interface_vector
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_write_interface_vector,
READY => ready_write_interface_vector,
-- Write Key
WK_IN_L_ENABLE => wk_in_l_enable_write_interface_vector,
WK_IN_K_ENABLE => wk_in_k_enable_write_interface_vector,
K_OUT_ENABLE => k_out_enable_write_interface_vector,
-- Write Strength
WBETA_IN_ENABLE => wbeta_in_enable_write_interface_vector,
-- Erase Vector
WE_IN_L_ENABLE => we_in_l_enable_write_interface_vector,
WE_IN_K_ENABLE => we_in_k_enable_write_interface_vector,
E_OUT_ENABLE => e_out_enable_write_interface_vector,
-- Write Vector
WV_IN_L_ENABLE => wv_in_l_enable_write_interface_vector,
WV_IN_K_ENABLE => wv_in_k_enable_write_interface_vector,
V_OUT_ENABLE => v_out_enable_write_interface_vector,
-- Allocation Gate
WGA_IN_ENABLE => wga_in_enable_write_interface_vector,
-- Write Gate
WGW_IN_ENABLE => wgw_in_enable_write_interface_vector,
-- Hidden State
H_IN_ENABLE => h_in_enable_write_interface_vector,
-- DATA
SIZE_W_IN => size_w_in_write_interface_vector,
SIZE_L_IN => size_l_in_write_interface_vector,
SIZE_R_IN => size_r_in_write_interface_vector,
WK_IN => wk_in_write_interface_vector,
WBETA_IN => wbeta_in_write_interface_vector,
WE_IN => we_in_write_interface_vector,
WV_IN => wv_in_write_interface_vector,
WGA_IN => wga_in_write_interface_vector,
WGW_IN => wgw_in_write_interface_vector,
H_IN => h_in_write_interface_vector,
K_OUT => k_out_write_interface_vector,
BETA_OUT => beta_out_write_interface_vector,
E_OUT => e_out_write_interface_vector,
V_OUT => v_out_write_interface_vector,
GA_OUT => ga_out_write_interface_vector,
GW_OUT => gw_out_write_interface_vector
);
-----------------------------------------------------------------------
-- MEMORY
-----------------------------------------------------------------------
addressing : dnc_addressing
generic map (
DATA_SIZE => DATA_SIZE
)
port map (
-- GLOBAL
CLK => CLK,
RST => RST,
-- CONTROL
START => start_addressing,
READY => ready_addressing,
K_READ_IN_I_ENABLE => k_read_in_i_enable_addressing,
K_READ_IN_K_ENABLE => k_read_in_k_enable_addressing,
BETA_READ_IN_ENABLE => beta_read_in_enable_addressing,
F_READ_IN_ENABLE => f_read_in_enable_addressing,
PI_READ_IN_ENABLE => pi_read_in_enable_addressing,
K_WRITE_IN_K_ENABLE => k_write_in_k_enable_addressing,
E_WRITE_IN_K_ENABLE => e_write_in_k_enable_addressing,
V_WRITE_IN_K_ENABLE => v_write_in_k_enable_addressing,
-- DATA
SIZE_R_IN => size_r_in_addressing,
SIZE_W_IN => size_w_in_addressing,
K_READ_IN => k_read_in_addressing,
BETA_READ_IN => beta_read_in_addressing,
F_READ_IN => f_read_in_addressing,
PI_READ_IN => pi_read_in_addressing,
K_WRITE_IN => k_write_in_addressing,
BETA_WRITE_IN => beta_write_in_addressing,
E_WRITE_IN => e_write_in_addressing,
V_WRITE_IN => v_write_in_addressing,
GA_WRITE_IN => ga_write_in_addressing,
GW_WRITE_IN => gw_write_in_addressing,
R_OUT => r_out_addressing
);
end architecture;
|
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------------
ENTITY rp_top IS
PORT (
CLK : IN STD_LOGIC;
BTN : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
LED : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
DISP_SEG : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
DISP_DIG : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END rp_top;
----------------------------------------------------------------------------------
ARCHITECTURE Structural OF rp_top IS
----------------------------------------------------------------------------------
SIGNAL cnt_sig : STD_LOGIC_VECTOR(31 DOWNTO 0);
COMPONENT seg_disp_driver
PORT (
clk : IN STD_LOGIC;
dig_1_i : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
dig_2_i : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
dig_3_i : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
dig_4_i : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
dp_i : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- [DP4 DP3 DP2 DP1]
dots_i : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- [L3 L2 L1]
disp_seg_o : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
disp_dig_o : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
COMPONENT cnt_bin
PORT( clk : in STD_LOGIC;
ce : in STD_LOGIC;
srst : in STD_LOGIC;
cnt_load : in STD_LOGIC;
cnt_up : in STD_LOGIC;
cnt : out STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
--------------------------------------------------------------------------------
----------------------------------------------------------------------------------
BEGIN
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--
-- DIG 1 DIG 2 DIG 3 DIG 4
-- L3
-- ----- ----- ----- o -----
-- | | | | L1 | | | |
-- | | | | o | | | |
-- ----- ----- ----- -----
-- | | | | o | | | |
-- | | | | L2 | | | |
-- ----- o ----- o ----- o ----- o
-- DP1 DP2 DP3 DP4
--
--------------------------------------------------------------------------------
seg_disp_driver_i : seg_disp_driver
PORT MAP (
clk => CLK,
dig_1_i => cnt_sig(31 DOWNTO 28),
dig_2_i => cnt_sig(27 DOWNTO 24),
dig_3_i => cnt_sig(23 DOWNTO 20),
dig_4_i => cnt_sig(19 DOWNTO 16),
dp_i => "0000",
dots_i => "011",
disp_seg_o => DISP_SEG,
disp_dig_o => DISP_DIG
);
--------------------------------------------------------------------------------
cnt_bin_i : cnt_bin
PORT MAP(
clk => CLK,
cnt_up => SW(3),
ce => SW(2),
cnt_load => BTN(1),
srst => BTN(2),
cnt => cnt_sig
);
LED <= cnt_sig(31 DOWNTO 24);
----------------------------------------------------------------------------------
END Structural;
----------------------------------------------------------------------------------
|
<reponame>Dashboy1998/AES-128
library ieee;
use ieee.std_logic_1164.all;
use work.data_types.all;
entity cryptionRounds is -- Used for encryption and decryption rounds 1 to N-1
port(
data: in std_logic_vector(127 downto 0);
Keys: in ARounds; -- In order for encryption
ED: in std_logic;
Xout: out std_logic_vector(127 downto 0)
);
end entity cryptionRounds;
architecture dataflow of cryptionRounds is
component cryption is
port(
data: in std_logic_vector(127 downto 0);
key: in std_logic_vector(127 downto 0);
ED: in std_logic;
Xout: out std_logic_vector(127 downto 0)
);
end component cryption;
component cryption_final is
port(
data: in std_logic_vector(127 downto 0);
key: in std_logic_vector(127 downto 0);
ED: in std_logic;
Xout: out std_logic_vector(127 downto 0)
);
end component cryption_final;
signal R: ARounds;
begin
R(0) <= data xor Keys(0);
Gen_R: for i in 1 to (numRounds - 1) generate
C: cryption port map(R(i-1), Keys(i), ED, R(i));
end generate;
F: cryption_final port map(R(numRounds-1), Keys(numRounds), ED, R(numRounds));
Xout <= R(numRounds);
end architecture;
|
<filename>GRBC/src/GRBC_ent.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.stream.all;
entity GRBC is
port(
IO: inout Qword; -- Used as input for plain text/cipher and key, and output of plain text/cipher
ED: in std_logic; -- Used to indicate if encrypting or decrypting
Start: in std_logic; -- Used to start the encrpytion/decryption
Clk: in std_logic; -- Clk signal
Done: inout std_logic:='0' -- Signal to indicate if done
);
end entity;
|
<reponame>lucastrschneider/PCS3115
-------------------------------------------------------
--! @file littlesort_tb.vhd
--! @brief testbench for littlesort circuit
--! @author <NAME> (<EMAIL>)
--! @date 2020-06-19
-------------------------------------------------------
-------------------------------------------------------
--! @brief 2-to-1 1-bit multiplexer
--! @author <NAME> (<EMAIL>)
--! @date 2020-06-30
-------------------------------------------------------
entity mux_2to1 is
port
(
SEL : in bit;
A : in bit;
B : in bit;
Y : out bit
);
end entity;
architecture with_select of mux_2to1 is
begin
with SEL select
Y <= A when '0',
B when '1',
'0' when others;
end architecture;
-------------------------------------------------------
--! @brief testbench for littlesort circuit
--! @author <NAME> (<EMAIL>)
--! @date 2020-06-19
-------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
use std.textio.all;
-- entidade do testbench
entity littlesort_tb is
end entity;
architecture tb of littlesort_tb is
-- Funcoes usadas para o report para bit_vector
-- autor: <NAME> (<EMAIL>)
function to_bstring(b : bit) return string is
variable b_str_v : string(1 to 3);
begin
b_str_v := bit'image(b);
return "" & b_str_v(2);
end function;
function to_bstring(bv : bit_vector) return string is
alias bv_norm : bit_vector(1 to bv'length) is bv;
variable b_str_v : string(1 to 1);
variable res_v : string(1 to bv'length);
begin
for idx in bv_norm'range loop
b_str_v := to_bstring(bv_norm(idx));
res_v(idx) := b_str_v(1);
end loop;
return res_v;
end function;
-- Componente a ser testado (Device Under Test -- DUT)
component littlesort
port
(
clock: in bit;
reset: in bit;
Iniciar: in bit;
mem_we: out bit;
mem_endereco: out bit_vector(3 downto 0);
mem_dado_write: out bit_vector(3 downto 0);
mem_dado_read: in bit_vector(3 downto 0);
Pronto: out bit
);
end component;
-- componente da memoria externa ao circuito
component ram16x4
generic
(
data_file_name : string
);
port
(
clock : in bit;
addr : in bit_vector(3 downto 0);
we : in bit;
data_i : in bit_vector(3 downto 0);
data_o : out bit_vector(3 downto 0)
);
end component;
-- componente do mux de endereco da memoria
component mux4_2to1
port
(
SEL : in bit;
A : in bit_vector (3 downto 0);
B : in bit_vector (3 downto 0);
Y : out bit_vector (3 downto 0)
);
end component;
-- componente do mux para o we
component mux_2to1 is
port
(
SEL : in bit;
A : in bit;
B : in bit;
Y : out bit
);
end component;
---- Declaração de sinais para conectar a componente
signal clk_in: bit := '0';
signal rst_in: bit := '0';
---- Declaracao dos sinais iniciar e pronto dos casos de teste
signal iniciar_in, pronto_out: bit := '0';
---- Declaracao dos sinais de conexao com as memorias dos casos de teste
-- conexao com a memoria
signal mem_we: bit;
signal mem_endereco: bit_vector(3 downto 0);
signal mem_dado_write: bit_vector(3 downto 0);
signal mem_dado_read: bit_vector(3 downto 0);
-- conexao com muxes
signal tb_sel_mux: bit;
signal dut_endereco: bit_vector(3 downto 0);
signal tb_endereco: bit_vector(3 downto 0);
signal dut_we: bit;
signal tb_we: bit;
-- Configurações do clock
signal keep_simulating: bit := '0'; -- delimita o tempo de geração do clock
constant clockPeriod : time := 1 ns;
begin
-- Gerador de clock: executa enquanto 'keep_simulating = 1', com o período especificado.
-- Quando keep_simulating=0, clock é interrompido, bem como a simulação de eventos
clk_in <= (not clk_in) and keep_simulating after clockPeriod/2;
---- DUT para Caso de Teste
dut: littlesort
port map
(
clock=> clk_in,
reset=> rst_in,
Iniciar=> iniciar_in,
mem_we=> dut_we,
mem_endereco=> dut_endereco,
mem_dado_write=> mem_dado_write,
mem_dado_read=> mem_dado_read,
Pronto=> pronto_out
);
mem: ram16x4
generic map
(
data_file_name => "EP4/memoria1.dat"
)
port map
(
clock=> clk_in,
addr=> mem_endereco,
we=> mem_we,
data_i=> mem_dado_write,
data_o=> mem_dado_read
);
mux1: mux4_2to1
port map
(
SEL=> tb_sel_mux,
A => dut_endereco,
B => tb_endereco,
Y => mem_endereco
);
mux2: mux_2to1
port map
(
SEL=> tb_sel_mux,
A => dut_we,
B => tb_we,
Y => mem_we
);
---- Gera sinais de estimulo
stimulus: process is
begin
-- inicio da simulacao
report "inicio da simulacao";
keep_simulating <= '1';
-->> Caso de teste: memoria1.dat (aleatorio, maior no meio) <<
--- Fase 1: DUT
tb_sel_mux <= '0'; -- DUT acessa a memoria
iniciar_in <= '0';
-- gera pulso de reset (1 periodo de clock)
rst_in <= '1';
wait for clockPeriod;
rst_in <= '0';
wait until falling_edge(clk_in);
-- pulso do sinal de Iniciar
iniciar_in <= '1';
wait until falling_edge(clk_in);
iniciar_in <= '0';
-- espera pelo termino da ordenacao
wait until pronto_out='1';
report "fim da ordenacao";
wait for clockPeriod;
--- Fase 2: verificacao da memoria
tb_we <= '0';
tb_sel_mux <= '1'; -- TB acessa a memoria
wait for clockPeriod;
-- Teste 1 - Verifica posicao 2 da memoria (valor esperado A)
tb_endereco <= "0010"; -- posicao 2
wait for clockPeriod;
-- mostra conteudo da memoria
report "memoria1[0010]=" & to_bstring(mem_dado_read);
wait for clockPeriod;
-- Teste 2 - Verifica ultima posicao da memoria (valor esperado F)
tb_endereco <= "1111"; -- ultima posicao
wait for clockPeriod;
-- mostra conteudo da memoria
report "memoria1[1111]=" & to_bstring(mem_dado_read);
wait for clockPeriod;
tb_sel_mux <= '0';
---- final do testbench
report "fim da simulacao";
keep_simulating <= '0';
wait; -- fim da simulação: processo aguarda indefinidamente
end process;
end architecture;
|
--
-----------------------------------------------------------------
-- COMPANY : Ruhr University Bochum
-- AUTHOR : <NAME> (<EMAIL>) <NAME> (<EMAIL>)
-- DOCUMENT: https://doi.org/10.46586/tches.v2021.i1.305-342
-- -----------------------------------------------------------------
--
-- Copyright (c) 2020, <NAME>, <NAME>
--
-- All rights reserved.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTERS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Please see LICENSE and README for license and further instructions.
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY PRINCE_Round IS
PORT ( input_s1 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
input_s2 : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
k_1 : IN STD_LOGIC_VECTOR (63 downto 0);
k_1_2 : IN STD_LOGIC_VECTOR (63 downto 0);
result_s1 : OUT STD_LOGIC_VECTOR (63 downto 0);
result_s2 : OUT STD_LOGIC_VECTOR (63 downto 0);
enc_dec : IN STD_LOGIC;
clk : IN STD_LOGIC;
round_number : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
roundStart_Select : IN STD_LOGIC;
roundHalf_Select : IN STD_LOGIC;
roundEnd_Select : IN STD_LOGIC);
END PRINCE_Round;
ARCHITECTURE behavioral OF PRINCE_Round IS
COMPONENT ScanFF IS
GENERIC (SIZE : integer);
PORT ( CLK : IN STD_LOGIC;
SE : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR((SIZE-1) DOWNTO 0);
DS : IN STD_LOGIC_VECTOR((SIZE-1) DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR((SIZE-1) DOWNTO 0));
END COMPONENT;
COMPONENT roundConstant_MUX IS
PORT ( round : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
enc_dec: IN STD_LOGIC;
roundConstant : OUT STD_LOGIC_VECTOR (63 DOWNTO 0));
END COMPONENT;
COMPONENT ShiftRows_Inverse is
PORT ( state : in STD_LOGIC_VECTOR (63 downto 0);
result : out STD_LOGIC_VECTOR (63 downto 0));
END COMPONENT;
COMPONENT matrixMultiplication IS
PORT ( state : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0));
END COMPONENT;
COMPONENT ShiftRows is
PORT ( state : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0));
END COMPONENT;
SIGNAL round_Constant : STD_LOGIC_VECTOR (63 DOWNTO 0);
SIGNAL k1_XOR_round_Constant,
roundReg_out_s1,
roundReg_out_s2,
SR_Result_s1,
SR_Result_s2,
sub_Inv_Result_s1,
sub_Inv_Result_s2,
mul_input_s1,
mul_input_s2,
mul_result_s1,
mul_result_s2,
SR_Inv_Result_s1,
SR_Inv_Result_s2,
sub_Result_s1,
sub_Result_s2,
sub_Inv_Result_XOR_keyRCON_s1,
sub_Inv_Result_XOR_keyRCON_s2,
round_inputXORkeyRCON_s1,
round_inputXORkeyRCON_s2,
Sbox_Input_s1,
Sbox_Input_s2: STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
constant_MUX : roundConstant_MUX
PORT MAP ( round => round_number,
enc_dec => enc_dec,
roundConstant => round_Constant);
k1_XOR_round_Constant <= k_1 XOR round_Constant;
-------------------------------------------------------
roundResult_Reg_s1: ScanFF
GENERIC MAP ( SIZE => 64)
PORT MAP (
CLK => clk,
SE => roundStart_Select,
D => mul_Result_s1,
DS => input_s1,
Q => roundReg_out_s1);
roundResult_Reg_s2: ScanFF
GENERIC MAP ( SIZE => 64)
PORT MAP (
CLK => clk,
SE => roundStart_Select,
D => mul_Result_s2,
DS => input_s2,
Q => roundReg_out_s2);
-------------------------------------------------------
SR_s1: ShiftRows
PORT MAP ( state => roundReg_out_s1,
result => SR_Result_s1);
SR_s2: ShiftRows
PORT MAP ( state => roundReg_out_s2,
result => SR_Result_s2);
-------------------------------------------------------
round_inputXORkeyRCON_s1 <= SR_Result_s1 XOR k1_XOR_round_Constant;
round_inputXORkeyRCON_s2 <= SR_Result_s2 XOR k_1_2;
-------------------------------------------------------
MUX_inst0: ENTITY work.MUX
GENERIC Map ( size => 64)
PORT Map (
sel => roundHalf_Select,
D0 => round_inputXORkeyRCON_s1,
D1 => roundReg_out_s1,
Q => Sbox_Input_s1);
MUX_inst1: ENTITY work.MUX
GENERIC Map ( size => 64)
PORT Map (
sel => roundHalf_Select,
D0 => round_inputXORkeyRCON_s2,
D1 => roundReg_out_s2,
Q => Sbox_Input_s2);
sub : ENTITY work.substitutionCombined
PORT MAP ( state_s1 => Sbox_Input_s1,
state_s2 => Sbox_Input_s2,
sel => roundHalf_Select,
clk => clk,
result_s1 => sub_Inv_Result_s1,
result_s2 => sub_Inv_Result_s2);
sub_Result_s1 <= sub_Inv_Result_s1;
sub_Result_s2 <= sub_Inv_Result_s2;
-------------------------------------------------------
sub_Inv_Result_XOR_keyRCON_s1 <= sub_Inv_Result_s1 XOR k1_XOR_round_Constant;
sub_Inv_Result_XOR_keyRCON_s2 <= sub_Inv_Result_s2 XOR k_1_2;
-------------------------------------------------------
SR_Inv_s1: ShiftRows_Inverse
Port MAP ( state => sub_Inv_Result_XOR_keyRCON_s1,
result => SR_Inv_Result_s1);
SR_Inv_s2: ShiftRows_Inverse
Port MAP ( state => sub_Inv_Result_XOR_keyRCON_s2,
result => SR_Inv_Result_s2);
-------------------------------------------------------
mul_input_s1 <= sub_Result_s1 when roundEnd_Select = '0' else SR_Inv_Result_s1;
mul_input_s2 <= sub_Result_s2 when roundEnd_Select = '0' else SR_Inv_Result_s2;
-------------------------------------------------------
mul_s1: matrixMultiplication
PORT MAP ( state => mul_input_s1,
result => mul_Result_s1);
mul_s2: matrixMultiplication
PORT MAP ( state => mul_input_s2,
result => mul_Result_s2);
-------------------------------------------------------
result_s1 <= sub_Inv_Result_XOR_keyRCON_s1;
result_s2 <= sub_Inv_Result_XOR_keyRCON_s2;
END behavioral;
|
<reponame>tudortimi/ipxact<gh_stars>1-10
-- ****************************************************************************
-- ** Leon 2 code
-- ** Revision: $Revision: 1506 $
-- ** Date: $Date: 2009-04-25 23:51:56 -0700 (Sat, 25 Apr 2009) $
-- **
-- ** Copyright (c) 2008, 2009 The SPIRIT Consortium.
-- **
-- ** This work forms part of a deliverable of The SPIRIT Consortium.
-- **
-- ** Use of these materials are governed by the legal terms and conditions
-- ** outlined in the disclaimer available from www.spiritconsortium.org.
-- **
-- ** This source file is provided on an AS IS basis. The SPIRIT
-- ** Consortium disclaims any warranty express or implied including
-- ** any warranty of merchantability and fitness for use for a
-- ** particular purpose.
-- **
-- ** The user of the source file shall indemnify and hold The SPIRIT
-- ** Consortium and its members harmless from any damages or liability.
-- ** Users are requested to provide feedback to The SPIRIT Consortium
-- ** using either mailto:<EMAIL> or the forms at
-- ** http://www.spiritconsortium.org/about/contact_us/
-- **
-- ** This file may be copied, and distributed, with or without
-- ** modifications; this notice must be included on any copy.
-- ****************************************************************************
-- Derived from European Space Agency (ESA) code as described below
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: device
-- File: device.vhd
-- Author: <NAME> - Gaisler Research
-- Description: package to select current device configuration
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
package device is
-----------------------------------------------------------------------------
-- Automatically generated by tkonfig/mkdevice
-----------------------------------------------------------------------------
constant apbslvcfg_tkconfig : apb_slv_config_vector(0 to APB_SLV_MAX-1) := (
-- first last index enable function PADDR[9:0]
( "000000000000000000", "000000000000001000", 0, true), -- memory controller, 0x00 - 0x08
( "000000000000001100", "000000000000010000", 1, false), -- AHB status reg., 0x0C - 0x10
( "000000000000010100", "000000000000011000", 2, true), -- cache controller, 0x14 - 0x18
( "000000000000011100", "000000000000100000", 3, false), -- write protection, 0x1C - 0x20
( "000000000000100100", "000000000000100100", 4, true), -- config register, 0x24 - 0x24
( "000000000001000000", "000000000001101100", 5, true), -- timers, 0x40 - 0x6C
( "000000000001110000", "000000000001111100", 6, true), -- uart1, 0x70 - 0x7C
( "000000000010000000", "000000000010001100", 7, true), -- uart2, 0x80 - 0x8C
( "000000000010010000", "000000000010011100", 8, true), -- interrupt ctrl 0x90 - 0x9C
( "000000000010100000", "000000000010101100", 9, true), -- I/O port 0xA0 - 0xAC
( "000000000010110000", "000000000010111100", 10, false),-- 2nd interrupt ctrl 0xB0 - 0xBC
( "000000000011000000", "000000000011001100", 11, false), -- DSU uart 0xC0 - 0xCC
( "000000000100000000", "000000000111111100", 12, false), -- PCI configuration 0x100- 0x1FC
( "000000001000000000", "000000001011111100", 13, false), -- PCI arbiter 0x200- 0x2FC
others => apb_slv_config_void);
constant apb_tkconfig : apb_config_type := (table => apbslvcfg_tkconfig);
constant ahbslvcfg_tkconfig : ahb_slv_config_vector(0 to AHB_SLV_MAX-1) := (
-- first last index split enable function HADDR[31:28]
("0000", "0111", 0, false, true), -- memory controller, 0x0- 0x7
("1000", "1000", 1, false, true), -- APB bridge, 128 MB 0x8- 0x8
("1001", "1001", 2, false, false), -- DSU 128 MB 0x9- 0x9
("1010", "1111", 3, false, false), -- PCI initiator 0xA- 0xF
others => ahb_slv_config_void);
constant ahb_tkconfig : ahb_config_type := ( masters => 1, defmst => 0,
split => false, slvtable => ahbslvcfg_tkconfig, testmod => false);
constant syn_tkconfig : syn_config_type := (
targettech => gen, infer_pads => false,
infer_ram => false, infer_regf => false, infer_rom => true,
infer_mult => false, rftype => 1);
constant iu_tkconfig : iu_config_type := (
nwindows => 8, multiplier => none, divider => none, mac => false,
fpuen => 0, cpen => false, fastjump => false, icchold => false,
lddelay => 1, fastdecode => false, watchpoints => 0, impl => 0,
version => 0, rflowpow => false);
constant fpu_tkconfig : fpu_config_type :=
(core => meiko, interface => none, fregs => 0, version => 0);
constant cache_tkconfig : cache_config_type := ( icachesize => 2,
ilinesize => 4, dcachesize => 2, dlinesize => 4, dsnoop => none,
cachetable => cachetbl_std);
constant mctrl_tkconfig : mctrl_config_type := (
bus8en => false, bus16en => false, wendfb => false, ramsel5 => false,
sdramen => false, sdinvclk => false);
constant peri_tkconfig : peri_config_type := (
cfgreg => true, ahbstat => false, wprot => false, wdog => false,
irq2cfg => irq2none);
constant debug_tkconfig : debug_config_type := ( enable => true, uart => false,
iureg => false, fpureg => false, nohalt => false, pclow => 2,
dsuenable => false, dsutrace => false, dsumixed => false,
dsudpram => false, tracelines => 64);
constant boot_tkconfig : boot_config_type := (boot => memory, ramrws => 0,
ramwws => 0, sysclk => 25000000, baud => 19200, extbaud => false,
pabits => 11);
constant pci_tkconfig : pci_config_type := (
pcicore => none, ahbmasters => 0, ahbslaves => 0,
arbiter => false, fixpri => false, prilevels => 4, pcimasters => 4,
vendorid => 16#0000#, deviceid => 16#0000#, subsysid => 16#0000#,
revisionid => 16#00#, classcode =>16#000000#, pmepads => false,
p66pad => false, pcirstall => false);
constant tkconfig : config_type := (
synthesis => syn_tkconfig, iu => iu_tkconfig, fpu => fpu_tkconfig,
cp => cp_none, cache => cache_tkconfig, ahb => ahb_tkconfig,
apb => apb_tkconfig, mctrl => mctrl_tkconfig, boot => boot_tkconfig,
debug => debug_tkconfig, pci => pci_tkconfig, peri => peri_tkconfig);
-----------------------------------------------------------------------------
-- end of automatic configuration
-----------------------------------------------------------------------------
----------------------------------------------------------------------
-- This is the current device configuration
----------------------------------------------------------------------
constant conf : config_type := tkconfig;
-- constant conf : config_type := fpga_2k2k;
-- constant conf : config_type := fpga_2k2k_v8;
-- constant conf : config_type := fpga_2k2k_irq2;
-- constant conf : config_type := fpga_2k2k_softprom;
-- constant conf : config_type := fpga_2k2k_v8_softprom;
-- constant conf : config_type := fpga_4k4k_v8_fpu;
-- constant conf : config_type := fpga_4k4k_v8_fpu_softprom;
-- constant conf : config_type := fpga_2k2k_v8_mac_softprom;
-- constant conf : config_type := virtex_2k2k_blockprom;
-- constant conf : config_type := virtex_4k2k_dsu;
-- constant conf : config_type := virtex_4k2k_dsu_sdram;
-- constant conf : config_type := virtex_4k2k_dsu_sdram_invclk;
-- constant conf : config_type := virtex_8k8k_dsu_pci_actel_sdram;
-- constant conf : config_type := virtex_8k8k_dsu_pci_actel_sdram_v8_fpu;
-- constant conf : config_type := virtex_8k8k_dsu_pci_is_sdram_invclk;
-- constant conf : config_type := virtex_4k2k_dsu_pci;
-- constant conf : config_type := virtex_4k2k_v8_dsu;
-- constant conf : config_type := virtex_2k2k_v8_fpu_dsu;
-- constant conf : config_type := virtex_2k1k_rdbmon;
-- constant conf : config_type := virtex_2k2k_v8_blockprom;
-- constant conf : config_type := gen_atc25;
-- constant conf : config_type := gen_atc25_meiko;
-- constant conf : config_type := gen_atc25_fpc;
-- constant conf : config_type := gen_atc25_insilicon_pci;
-- constant conf : config_type := gen_atc35;
-- constant conf : config_type := systel_fpga;
-- constant conf : config_type := systel_asic;
-- constant conf : config_type := gen_fs90;
-- constant conf : config_type := gen_umc18;
-- constant conf : config_type := gen_tsmc25_8k8k;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sniffer_tb is
end Sniffer_tb;
architecture Simul of Sniffer_tb is
signal stop : boolean;
signal prepare : std_logic;
signal addr : std_logic_vector(7 downto 0);
signal data : std_logic_vector(31 downto 0);
signal aclk, aresetn : std_logic;
signal awvalid, awready : std_logic;
signal arvalid, arready : std_logic;
begin
p_clock : process -- 150 MHz
begin
aclk <= '1';
while not stop loop
wait for 6.66 ns / 2;
aclk <= not aclk;
end loop;
wait;
end process p_clock;
aresetn <= '0', '1' after 20 ns;
SimpleAxiSniffer_inst : entity work.SimpleAxiSniffer
port map (
aclk_i => aclk,
aresetn_i => aresetn,
prepare_i => prepare,
-- Write
awvalid_i => awvalid,
awready_i => awready,
wvalid_i => '1',
wready_i => '1',
wlast_i => '1',
bvalid_i => '1',
bready_i => '1',
awprot_i => (others => '0'),
awlen_i => (others => '0'),
awsize_i => (others => '0'),
awburst_i => (others => '0'),
awcache_i => (others => '0'),
awlock_i => (others => '0'),
-- Read
arvalid_i => arvalid,
arready_i => arready,
rvalid_i => '1',
rready_i => '1',
rlast_i => '1',
arlen_i => (others => '0'),
arsize_i => (others => '0'),
arburst_i => (others => '0'),
arcache_i => (others => '0'),
arprot_i => (others => '0'),
arlock_i => (others => '0'),
--
addr_i => addr,
data_o => data
);
p_test: process
variable data_to_send : std_logic_vector(15 downto 0);
begin
prepare <= '0';
awvalid <= '0';
awready <= '0';
arvalid <= '0';
arready <= '0';
wait until aresetn='1';
wait until rising_edge(aclk);
prepare <= '1';
wait until rising_edge(aclk);
prepare <= '0';
wait until rising_edge(aclk);
awvalid <= '1';
awready <= '1';
wait until rising_edge(aclk);
awvalid <= '0';
awready <= '0';
wait until rising_edge(aclk);
arvalid <= '1';
arready <= '1';
wait until rising_edge(aclk);
arvalid <= '0';
arready <= '0';
wait until rising_edge(aclk);
wait for 1 us;
for i in 0 to 255 loop
addr <= std_logic_vector(to_unsigned(i,8));
wait until rising_edge(aclk);
end loop;
stop <= TRUE;
wait;
end process p_test;
end architecture Simul;
|
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