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<filename>models/Beamer/ip/fft_filter/fft_filters_addr_B_gen.vhd
-- -------------------------------------------------------------
--
-- File Name: C:\Users\conno\Documents\NIH-GitHub\simulink_models\models\fft_filters\hdlsrc\fft_filters\fft_filters_addr_B_gen.vhd
--
-- Generated by MATLAB 9.9 and HDL Coder 3.17
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: fft_filters_addr_B_gen
-- Source Path: fft_filters/dataplane/FFT_Analysis_Synthesis_Left/Analysis/FFT Frame Buffering/addr_B_gen
-- Hierarchy Level: 4
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY fft_filters_addr_B_gen IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
start : IN std_logic;
enable : IN std_logic;
addr_B : OUT std_logic_vector(7 DOWNTO 0); -- uint8
Frame_counter : OUT std_logic_vector(7 DOWNTO 0); -- uint8
FFT_Valid : OUT std_logic
);
END fft_filters_addr_B_gen;
ARCHITECTURE rtl OF fft_filters_addr_B_gen IS
-- Component Declarations
COMPONENT fft_filters_addr_B_gen_enable
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
start : IN std_logic;
enable_B : OUT std_logic;
Start_Address : OUT std_logic_vector(7 DOWNTO 0); -- uint8
Frame_Index : OUT std_logic_vector(7 DOWNTO 0) -- uint8
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : fft_filters_addr_B_gen_enable
USE ENTITY work.fft_filters_addr_B_gen_enable(rtl);
-- Signals
SIGNAL addr_B_gen_enable_out1 : std_logic;
SIGNAL addr_B_gen_enable_out2 : std_logic_vector(7 DOWNTO 0); -- ufix8
SIGNAL addr_B_gen_enable_out3 : std_logic_vector(7 DOWNTO 0); -- ufix8
SIGNAL addr_B_gen_enable_out2_unsigned : unsigned(7 DOWNTO 0); -- uint8
SIGNAL Logical_Operator1_out1 : std_logic;
SIGNAL counter_B_out1 : unsigned(7 DOWNTO 0); -- uint8
BEGIN
-- Counter values [0 FFT_size-1] that
-- is used to lookup the window values
-- being applied.
--
-- Valid data is being streamed to the FFT Engine.
--
-- Enable signal that indicates
-- there is data in the buffer
-- and FFTs can start.
--
-- The start pulse sets the starting count to Start_Address
-- and the counter counts from Start_Address to Start_Address + FFT_size - 1
-- which is the address sent to Port B of the dual port memory.
u_addr_B_gen_enable : fft_filters_addr_B_gen_enable
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
start => start,
enable_B => addr_B_gen_enable_out1,
Start_Address => addr_B_gen_enable_out2, -- uint8
Frame_Index => addr_B_gen_enable_out3 -- uint8
);
addr_B_gen_enable_out2_unsigned <= unsigned(addr_B_gen_enable_out2);
Logical_Operator1_out1 <= addr_B_gen_enable_out1 AND enable;
-- Free running, Unsigned Counter
-- initial value = 246
-- step value = 1
counter_B_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
counter_B_out1 <= to_unsigned(16#F6#, 8);
ELSIF rising_edge(clk) THEN
IF enb_1_16_0 = '1' THEN
IF start = '1' THEN
counter_B_out1 <= addr_B_gen_enable_out2_unsigned;
ELSIF Logical_Operator1_out1 = '1' THEN
counter_B_out1 <= counter_B_out1 + to_unsigned(16#01#, 8);
END IF;
END IF;
END IF;
END PROCESS counter_B_process;
addr_B <= std_logic_vector(counter_B_out1);
Frame_counter <= addr_B_gen_enable_out3;
FFT_Valid <= Logical_Operator1_out1;
END rtl;
|
----------------------------------------------------------------------------------
-- Engineer: <NAME> <<EMAIL>>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
port(
clk: in std_logic;
resend: in std_logic;
config_finished : out std_logic;
sioc: out std_logic;
siod: inout std_logic;
reset: out std_logic;
pwdn: out std_logic;
xclk: out std_logic
);
end ov7670_controller;
architecture Structural of ov7670_controller is
component ov7670_registers is
port(
clk: in std_logic;
resend: in std_logic;
advance: in std_logic;
command: out std_logic_vector(15 downto 0);
finished: out std_logic
);
end component;
component i2c_sender is
port (
clk: in std_logic;
siod: inout std_logic;
sioc: out std_logic;
taken: out std_logic;
send: in std_logic;
id: in std_logic_vector(7 downto 0);
reg: in std_logic_vector(7 downto 0);
value: in std_logic_vector(7 downto 0)
);
end component;
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender port map(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
Inst_ov7670_registers: ov7670_registers port map(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
end Structural;
|
<reponame>evoredy/RF_Tools
-------------------------------------------------------------------------------
-- Title : 1000base-X MAC/Endpoint - TX packet injection unit
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : ep_tx_packet_injection.vhd
-- Author : <NAME>
-- Company : CERN BE-CO-HT
-- Created : 2012-11-01
-- Last update: 2013-03-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Asynchronously sends pre-defined packets upon a hardware request.
-- Packet contents are defined in a buffer accessible via Wishbone. The buffer
-- is shared with the TX VLAN unit and can contain templates of up to 8 packets
-- of up to 128 bytes of size. It is possible to replace a selected 16-bit word
-- within each template with a user-provided value.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-11-01 1.0 twlostow Created
-- 2013-03-12 1.1 mlipinsk added empty-template protaciton
-- prepared signals for RMON
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.endpoint_private_pkg.all;
use work.endpoint_pkg.all;
entity ep_tx_packet_injection is
port
(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
snk_fab_i : in t_ep_internal_fabric;
snk_dreq_o : out std_logic;
src_fab_o : out t_ep_internal_fabric;
src_dreq_i : in std_logic;
inject_req_i : in std_logic;
inject_ready_o : out std_logic;
inject_packet_sel_i : in std_logic_vector(2 downto 0);
inject_user_value_i : in std_logic_vector(15 downto 0);
inject_mode_i : in std_logic_vector(1 downto 0);
-- 0 : default
-- 1 : corrupt
-- 2 : unused
-- 3 : unused
mem_addr_o : out std_logic_vector(9 downto 0);
mem_data_i : in std_logic_vector(17 downto 0)
);
end ep_tx_packet_injection;
architecture rtl of ep_tx_packet_injection is
type t_state is (WAIT_IDLE, SOF, DO_INJECT, EOF);
alias template_last : std_logic is mem_data_i(16);
alias template_first : std_logic is mem_data_i(16);
alias template_user : std_logic is mem_data_i(17);
signal state : t_state;
signal counter : unsigned(8 downto 0);
signal within_packet : std_logic;
signal select_inject : std_logic;
signal inj_src : t_ep_internal_fabric;
signal inject_req_latched : std_logic;
signal first_word : std_logic; -- ML: used for masking the first word (we use the
-- same bit for SOF and EOF
-- ML: singals for RMON counters
signal no_template_error : std_logic; -- ML: indicates that injection was attempted with no valid template
signal inject_done : std_logic; -- ML: indicates that requrested injection was successful
begin -- rtl
snk_dreq_o <= '0' when (state = DO_INJECT) else src_dreq_i;
inject_done <= '1' when (state = EOF and src_dreq_i = '1') else '0';
p_detect_within : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
within_packet <= '0';
else
if(snk_fab_i.sof = '1')then
within_packet <= '1';
end if;
if(snk_fab_i.eof = '1' or snk_fab_i.error = '1') then
within_packet <= '0';
end if;
end if;
end if;
end process;
p_injection_request_ready : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
inject_ready_o <= '1';
inject_req_latched <= '0';
else
if(inject_req_i = '1') then
inject_ready_o <= '0';
inject_req_latched <= '1';
elsif(state = EOF and src_dreq_i = '1' ) then
inject_ready_o <= '1';
inject_req_latched <= '0';
elsif(no_template_error = '1') then
inject_ready_o <= '1';
inject_req_latched <= '0';
end if;
end if;
end if;
end process;
p_injection_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= WAIT_IDLE;
select_inject <= '0';
no_template_error <= '0';
inj_src.sof <= '0';
inj_src.eof <= '0';
inj_src.dvalid <= '0';
inj_src.error <= '0';
first_word <= '0';
else
case state is
when WAIT_IDLE =>
inj_src.sof <= '0';
inj_src.eof <= '0';
inj_src.dvalid <= '0';
inj_src.error <= '0';
no_template_error <= '0';
first_word <= '0';
if(inject_req_i = '1') then --ML: we make sure that we remember the packet_sel_i
-- only when req_i HIGH
counter(8 downto 6) <= unsigned(inject_packet_sel_i);
counter(5 downto 0) <= (others => '0');
end if;
if(within_packet = '0' and inject_req_latched = '1' and no_template_error = '0') then
state <= SOF;
select_inject <= '1';
else
select_inject <= '0';
end if;
when SOF =>
if(template_first = '0') then -- ML: check that the first word is valid, abort if error
state <= WAIT_IDLE;
no_template_error <= '1';
elsif(src_dreq_i = '1') then
first_word <= '1'; -- since the same bit is for SOF and EOF, we need to mask SOF
-- during first word
inj_src.sof <= '1';
state <= DO_INJECT;
end if;
when DO_INJECT =>
inj_src.sof <= '0';
if(src_dreq_i = '1') then
inj_src.dvalid <= '1';
counter <= counter + 1;
else
inj_src.dvalid <= '0';
end if;
if(first_word = '1' and template_first = '0') then -- ML: first word read
first_word <= '0';
end if;
if(template_last = '1' and inj_src.dvalid = '1' and first_word = '0' and src_dreq_i = '1') then
inj_src.dvalid <= '0';
state <= EOF;
if(inject_mode_i = "01") then
inj_src.error <= '1';
else
inj_src.eof <= '1';
end if;
end if;
when EOF =>
inj_src.eof <= '0';
inj_src.error <= '0';
if(src_dreq_i = '1') then
state <= WAIT_IDLE;
select_inject <= '0';
end if;
end case;
end if;
end if;
end process;
-- inj_src.bytesel <= '0';
-- the last word cannot be user-defined as we use the user bit to indicate odd size
inj_src.bytesel <= template_user when (template_last = '1' and first_word = '0') else '0';
-- inj_src.error <= '0';
p_inj_src_data : process(template_user, inject_user_value_i, mem_data_i,template_last,first_word)
begin
if(template_user = '1' and template_last = '0' and first_word = '0') then
inj_src.data <= inject_user_value_i;
else
inj_src.data <= mem_data_i(15 downto 0);
end if;
end process;
src_fab_o <= inj_src when select_inject = '1' else snk_fab_i;
mem_addr_o <= '1' & std_logic_vector(counter);
end rtl;
|
-- @TODO ouvrir OneNote
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Signalisation is
Port ( clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
capteur : in STD_LOGIC;
timer : in STD_LOGIC;
feuxP1 : out std_logic_vector (1 downto 0);
feuxP2 : out std_logic_vector (1 downto 0);
feuxS : out std_logic_vector (1 downto 0));
end Signalisation;
architecture Behavioral of Signalisation is
--Declare type, subtype
subtype t_state is std_logic_vector(2 DOWNTO 0);
--Declare constantes
-- convention bit(1)=R, bit(0)=V
constant c_vert : std_logic_vector (1 downto 0) := "10";
constant c_orange : std_logic_vector (1 downto 0) := "11";
constant c_rouge : std_logic_vector (1 downto 0) := "01";
constant c_PRVSECR : t_state := "000";
constant c_PROSECR : t_state := "001";
constant c_PRRSECR : t_state := "010";
constant c_PRRSECV : t_state := "011";
constant c_PRRSECO : t_state := "100";
constant c_PRRSECR2 : t_state := "101";
--Declare signaux
signal state : t_state;
begin
P1:PROCESS(clk, reset_n) BEGIN
IF reset_n = '0' THEN
state <= c_PRVSECR;
ELSIF (clk'EVENT AND clk = '1') THEN
CASE state IS
WHEN c_PRVSECR =>
IF capteur = '1' THEN
state <= c_PROSECR;
ELSE
state <= c_PRVSECR;
END IF;
WHEN c_PROSECR =>
IF capteur = '1' THEN
state <= c_PRRSECR;
END IF;
WHEN c_PRRSECR =>
IF capteur = '1' THEN
state <= c_PRRSECV;
END IF;
WHEN c_PRRSECV =>
IF timer = '1' THEN
state <= c_PRRSECO;
ELSE
state <= c_PRRSECV;
END IF;
WHEN c_PRRSECO =>
IF timer = '1' THEN
state <= c_PRRSECR2;
END IF;
WHEN c_PRRSECR2 =>
IF timer = '1' THEN
state <= c_PRVSECR;
END IF;
WHEN OTHERS =>
state <= c_PRVSECR;
END CASE;
END IF;
END PROCESS;
--Assignation des sorties combinatoire fonction des etats uniquement (Machine de Moore)
feuxP1 <= c_rouge WHEN state = c_PRVSECR ELSE
c_orange WHEN state = c_PROSECR ELSE
c_vert;
feuxP2 <= c_rouge WHEN state = c_PRVSECR ELSE
c_orange WHEN state = c_PROSECR ELSE
c_vert;
feuxS <= c_orange WHEN state = c_PRRSECO ELSE
c_rouge WHEN state = c_PRRSECV ELSE
c_vert;
end Behavioral;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
|
-- =============================================================================
-- Whatis : combinational adder
-- Project : FPGA-LPLIB_ALU
-- -----------------------------------------------------------------------------
-- File : add_comb.vhd
-- Language : VHDL-93
-- Module : add_comb
-- Library : lplib_alu
-- -----------------------------------------------------------------------------
-- Author(s) : <NAME> <pilato[punto]lu[chiocciola]gmail[punto]com>
--
-- Company :
-- Addr :
-- -----------------------------------------------------------------------------
-- Description
--
-- More than one rtl architecture, just as examples.
--
-- -----------------------------------------------------------------------------
-- Dependencies
--
-- -----------------------------------------------------------------------------
-- Issues
--
-- -----------------------------------------------------------------------------
-- Copyright (c) 2021 <NAME>
-- MIT License
-- -----------------------------------------------------------------------------
-- date who changes
-- 2019-11-06 <NAME> file creation
-- =============================================================================
-- IEEE lib
-- ----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity add_comb is
generic (
N : positive := 8
);
port (
a : in std_logic_vector(N-1 downto 0);
b : in std_logic_vector(N-1 downto 0);
cin : in std_logic;
s : out std_logic_vector(N-1 downto 0);
cout : out std_logic;
c2ovf : out std_logic
);
end add_comb;
-- Ripple Carry Adder with generate FA statements
-- ----------------------------------------
architecture rtl of add_comb is
signal cchain : std_logic_vector(N downto 0);
begin
cchain(0) <= cin;
gen_adder: for i in 0 to N-1 generate
s(i) <= a(i) xor b(i) xor cchain(i);
cchain(i+1) <= (a(i) and b(i)) or ((a(i) xor b(i)) and cchain(i));
end generate gen_adder;
cout <= cchain(N);
c2ovf <= cchain(N) xor cchain(N-1);
end rtl;
-- Ripple Carry Adder with unsigned extended cast
-- ----------------------------------------
architecture rtl2 of add_comb is
signal a_un : unsigned(N downto 0);
signal b_un : unsigned(N downto 0);
signal s_un : unsigned(N downto 0);
begin
a_un <= '0' & unsigned(a) ; -- extended unsigned
b_un <= '0' & unsigned(b) ; -- extended unsigned
--
s_un <= a_un + b_un + unsigned('0' & cin); -- very tricky: convert to vector, then allowed unsigned cast and '+'
s <= std_logic_vector(s_un(N-1 downto 0));
--
cout <= std_logic(s_un(N));
c2ovf <= ( a(N-1) and b(N-1) and (not s_un(N-1)) ) or
( (not a(N-1)) and (not a(N-1)) and s_un(N-1) );
end rtl2;
-- Ripple Carry Adder with FA combinational process
-- ----------------------------------------
architecture rtl3 of add_comb is
begin
proc_add: process(a,b,cin) -- process(all)
variable c : std_logic;
variable c_prev : std_logic;
begin
c := cin;
for i in 0 to N-1 loop
s(i) <= a(i) xor b(i) xor c;
c_prev := c;
c := (a(i) and b(i)) or (a(i) and c) or (b(i) and c);
end loop;
--
cout <= c;
c2ovf <= c xor c_prev;
--
end process proc_add;
end rtl3;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity communication_module is
Port (
JC : in std_logic_vector(3 downto 0);
arduino_signal: in std_logic;
arduino_ready: in std_logic;
clk: in std_logic;
done: out std_logic;
fpga_ready: out std_logic;
result: out std_logic_vector(1 downto 0);
led : out std_logic_vector(7 downto 0); -- Debug
seg: out std_logic_vector(6 downto 0); -- Debug
an: out std_logic_vector(3 downto 0); -- Debug
dp: out std_logic -- Debug
);
end communication_module;
architecture Behavioral of communication_module is
component clock_divider
Port (
clk : in STD_LOGIC;
refresh_clk : out STD_LOGIC;
second_clk : out STD_LOGIC
);
end component;
component display
Port (
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
C : in STD_LOGIC_VECTOR(3 downto 0);
D : in STD_LOGIC_VECTOR(3 downto 0);
E : in STD_LOGIC;
CLK: in STD_LOGIC;
seg: out STD_LOGIC_VECTOR(6 downto 0);
an: out STD_LOGIC_VECTOR(3 downto 0);
dp: out STD_LOGIC
);
end component;
signal input_vector : std_logic_vector(15 downto 0) := "0000000000000000";
signal i: integer := 0;
signal refresh_clk: std_logic;
signal unused: std_logic_vector(7 downto 0);
signal state: std_logic := '1';
signal arduino_signal_buffer : std_logic := '0';
signal done_signal: std_logic := '1';
signal done_counter: std_logic_vector(5 downto 0) := "111111";
begin
CD1: clock_divider port map(clk => clk, refresh_clk => refresh_clk, second_clk => unused(0));
D1: display port map(
A => input_vector(15 downto 12), B => input_vector(11 downto 8), C => input_vector(7 downto 4), D => input_vector(3 downto 0),
E => '1', clk => refresh_clk, seg => seg, an => an, dp => dp
);
led(3 downto 0) <= JC;
led(4) <= arduino_ready;
led(7 downto 5) <= "000";
done <= done_signal;
fpga_ready <= '1';
result <= "10";
process(clk)
variable temp_arduino_signal_buffer: std_logic;
variable temp_input_value: std_logic_vector(3 downto 0);
begin
if(rising_edge(clk)) then
if (state = '1' and done_signal = '0') then
if (done_counter < "111111") then
done_counter <= done_counter + 1;
else
done_signal <= '1';
end if;
end if;
if (arduino_ready = '0') then
i <= 0;
state <= '1';
elsif (arduino_signal_buffer = '0' and arduino_signal = '1') then
state <= '0';
done_signal <= '0';
elsif (state = '0') then
temp_input_value := JC;
input_vector(i+3 downto i) <= temp_input_value;
if i < 12 then
i <= i + 4;
else
i <= 0;
end if;
done_counter <= "000000";
state <= '1';
end if;
if (arduino_signal = '1' or arduino_signal = '0') then
temp_arduino_signal_buffer := arduino_signal;
arduino_signal_buffer <= temp_arduino_signal_buffer;
end if;
end if;
end process;
end Behavioral;
|
-- memory io entity
library ieee;
use ieee.std_logic_1164.all;
entity memio is
port (
clk1 : in std_logic;
reset : in std_logic;
mem_addr : inout std_logic_vector(20 downto 0);
mem_data_write : inout std_logic_vector(31 downto 0);
mem_rw : inout std_logic;
mem_sixteenbit : inout std_logic;
mem_addressready : out std_logic;
mem_data_read : inout std_logic_vector(31 downto 0);
mem_dataready_inv: in std_logic;
serial_character_ready: in std_logic;
fsmStateCodeMem : out std_ulogic_vector(1 downto 0) -- DEBUG
);
end;
architecture dataflow of memio is
type States is (MemWait, MemSet, MemReadWrite);
signal currentState: States := MemWait;
begin
FSM: process(clk1, reset, mem_dataready_inv)
begin
if reset = '1' then
currentState <= MemWait;
elsif rising_edge(clk1) then
case currentState is
when MemWait =>
if mem_dataready_inv = '1' then
currentState <= MemSet;
end if;
when MemSet =>
mem_addressready <= '1';
if mem_dataready_inv = '0' then
currentState <= MemReadWrite;
end if;
when MemReadWrite =>
mem_addressready <= '0';
currentState <= MemWait;
end case;
end if;
end process;
-- Diagnostics
with currentState select
fsmStateCodeMem <= "00" when MemWait,
"01" when MemSet,
"10" when MemReadWrite,
"11" when others;
end architecture dataflow;
|
<filename>Task1_TreeOfAdders/Task1_TreeOfAdders.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package array_package is
type custom_array is array(natural range <>) of std_logic_vector; --Работает только в VHDL 2008
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.array_package.all;
entity Task1_TreeOfAdders is
generic (N : positive := 3);
port
(
arr: in custom_array (1 to 8)(N - 1 downto 0);
res: out integer
);
end Task1_TreeOfAdders;
architecture rtl of Task1_TreeOfAdders is
begin
process (arr) is
variable sum11, sum12, sum13, sum14 : integer;
variable sum21, sum22 : integer;
begin
sum11 := to_integer(signed(arr(1))) + to_integer(signed(arr(2))); --т.к. в задании говорилось
sum12 := to_integer(signed(arr(3))) + to_integer(signed(arr(4))); --про целые числа, то
sum13 := to_integer(signed(arr(5))) + to_integer(signed(arr(6))); --предполагается, что подаются
sum14 := to_integer(signed(arr(7))) + to_integer(signed(arr(8))); --битовые знаковые
sum21 := sum11 + sum12;
sum22 := sum13 + sum14;
res <= sum21 + sum22;
end process;
end rtl;
|
---------------------------------------------------------------------
-- Coprocessor
--
-- Part of the LXP32 test platform
--
-- Copyright (c) 2016 by <NAME>
--
-- Performs a simple arithmetic operation, uses interrupt to wake
-- up the CPU.
--
-- Note: regardless of whether this description is synthesizable,
-- it was designed exclusively for simulation purposes.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity coprocessor is
port(
clk_i: in std_logic;
rst_i: in std_logic;
wbs_cyc_i: in std_logic;
wbs_stb_i: in std_logic;
wbs_we_i: in std_logic;
wbs_sel_i: in std_logic_vector(3 downto 0);
wbs_ack_o: out std_logic;
wbs_adr_i: in std_logic_vector(27 downto 2);
wbs_dat_i: in std_logic_vector(31 downto 0);
wbs_dat_o: out std_logic_vector(31 downto 0);
irq_o: out std_logic
);
end entity;
architecture rtl of coprocessor is
signal value: unsigned(31 downto 0):=(others=>'0');
signal result: unsigned(31 downto 0):=(others=>'0');
signal cnt: integer range 0 to 5:=0;
signal irq: std_logic:='0';
begin
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
value<=(others=>'0');
cnt<=0;
irq<='0';
else
if cnt>0 then
cnt<=cnt-1;
end if;
if cnt=1 then
irq<='1';
else
irq<='0';
end if;
if wbs_cyc_i='1' and wbs_stb_i='1' and wbs_we_i='1' then
for i in wbs_sel_i'range loop
if wbs_sel_i(i)='1' then
if wbs_adr_i="00"&X"000000" then
value(i*8+7 downto i*8)<=
unsigned(wbs_dat_i(i*8+7 downto i*8));
cnt<=5;
end if;
end if;
end loop;
end if;
end if;
end if;
end process;
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
result<=(others=>'0');
else
result<=shift_left(value,1)+value;
end if;
end if;
end process;
wbs_ack_o<=wbs_cyc_i and wbs_stb_i;
wbs_dat_o<=std_logic_vector(value) when wbs_adr_i="00"&X"000000" else
std_logic_vector(result) when wbs_adr_i="00"&X"000001" else
(others=>'-');
irq_o<=irq;
end architecture;
|
<filename>apps/hls_examples/camera_ready_synthesis/app_files/big_apps_8_shifts/sharpen/sharpen/hls_target/impl/ip/hdl/vhdl/call_Loop_LB2D_buf_p.vhd<gh_stars>1-10
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity call_Loop_LB2D_buf_p is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
start_full_n : IN STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
start_out : OUT STD_LOGIC;
start_write : OUT STD_LOGIC;
in_stream_V_value_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
in_stream_V_value_V_empty_n : IN STD_LOGIC;
in_stream_V_value_V_read : OUT STD_LOGIC;
slice_stream_V_value_V_din : OUT STD_LOGIC_VECTOR (23 downto 0);
slice_stream_V_value_V_full_n : IN STD_LOGIC;
slice_stream_V_value_V_write : OUT STD_LOGIC );
end;
architecture behav of call_Loop_LB2D_buf_p is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv11_0 : STD_LOGIC_VECTOR (10 downto 0) := "00000000000";
constant ap_const_lv11_438 : STD_LOGIC_VECTOR (10 downto 0) := "10000111000";
constant ap_const_lv11_1 : STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
constant ap_const_lv11_780 : STD_LOGIC_VECTOR (10 downto 0) := "11110000000";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv63_0 : STD_LOGIC_VECTOR (62 downto 0) := "000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_FFFFFFFFFFFFFFFE : STD_LOGIC_VECTOR (63 downto 0) := "1111111111111111111111111111111111111111111111111111111111111110";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
signal real_start : STD_LOGIC;
signal real_start_status_reg : STD_LOGIC := '0';
signal internal_ap_ready : STD_LOGIC;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal start_once_reg : STD_LOGIC := '0';
signal start_control_reg : STD_LOGIC := '0';
signal in_stream_V_value_V_blk_n : STD_LOGIC;
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal tmp_2_reg_290 : STD_LOGIC_VECTOR (0 downto 0);
signal slice_stream_V_value_V_blk_n : STD_LOGIC;
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal icmp_reg_286 : STD_LOGIC_VECTOR (0 downto 0);
signal write_idx_1_1_reg_146 : STD_LOGIC_VECTOR (63 downto 0);
signal col_reg_157 : STD_LOGIC_VECTOR (10 downto 0);
signal tmp_fu_168_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal row_1_fu_174_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal row_1_reg_281 : STD_LOGIC_VECTOR (10 downto 0);
signal icmp_fu_190_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_fu_196_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_block_state3_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state5_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal col_1_fu_202_p2 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal icmp1_fu_224_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal icmp1_reg_299 : STD_LOGIC_VECTOR (0 downto 0);
signal buffer_0_value_V_ad_reg_304 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_pp0_iter1_buffer_0_value_V_ad_reg_304 : STD_LOGIC_VECTOR (10 downto 0);
signal buffer_1_value_V_ad_reg_310 : STD_LOGIC_VECTOR (10 downto 0);
signal ap_reg_pp0_iter1_buffer_1_value_V_ad_reg_310 : STD_LOGIC_VECTOR (10 downto 0);
signal p_write_idx_1_1_fu_236_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_value_V_2_reg_321 : STD_LOGIC_VECTOR (7 downto 0);
signal buffer_0_value_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal buffer_0_value_V_lo_reg_328 : STD_LOGIC_VECTOR (7 downto 0);
signal buffer_1_value_V_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal buffer_1_value_V_lo_reg_334 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_9_fu_243_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_9_reg_340 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_247_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_reg_346 : STD_LOGIC_VECTOR (0 downto 0);
signal write_idx_1_2_fu_271_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state3 : STD_LOGIC;
signal buffer_0_value_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal buffer_0_value_V_ce0 : STD_LOGIC;
signal buffer_0_value_V_address1 : STD_LOGIC_VECTOR (10 downto 0);
signal buffer_0_value_V_ce1 : STD_LOGIC;
signal buffer_0_value_V_we1 : STD_LOGIC;
signal buffer_1_value_V_address0 : STD_LOGIC_VECTOR (10 downto 0);
signal buffer_1_value_V_ce0 : STD_LOGIC;
signal buffer_1_value_V_ce1 : STD_LOGIC;
signal buffer_1_value_V_we1 : STD_LOGIC;
signal write_idx_1_reg_123 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_state1 : BOOLEAN;
signal row_reg_135 : STD_LOGIC_VECTOR (10 downto 0);
signal write_idx_1_1_phi_fu_149_p4 : STD_LOGIC_VECTOR (63 downto 0);
signal col_cast_fu_208_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage0_flag00001001 : BOOLEAN;
signal tmp_6_fu_180_p4 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_8_fu_214_p4 : STD_LOGIC_VECTOR (62 downto 0);
signal write_idx_1_3_fu_230_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal p_Val2_2_1_phi_fu_256_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal p_Val2_2_0_phi_fu_251_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
signal ap_block_pp0 : BOOLEAN;
signal ap_enable_operation_55 : BOOLEAN;
signal ap_enable_state5_pp0_iter2_stage0 : BOOLEAN;
signal ap_enable_operation_35 : BOOLEAN;
signal ap_enable_state3_pp0_iter0_stage0 : BOOLEAN;
signal ap_enable_operation_42 : BOOLEAN;
signal ap_enable_state4_pp0_iter1_stage0 : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component call_Loop_LB2D_bubkb IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (10 downto 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR (7 downto 0);
address1 : IN STD_LOGIC_VECTOR (10 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (7 downto 0) );
end component;
begin
buffer_0_value_V_U : component call_Loop_LB2D_bubkb
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => buffer_0_value_V_address0,
ce0 => buffer_0_value_V_ce0,
q0 => buffer_0_value_V_q0,
address1 => buffer_0_value_V_address1,
ce1 => buffer_0_value_V_ce1,
we1 => buffer_0_value_V_we1,
d1 => tmp_value_V_2_reg_321);
buffer_1_value_V_U : component call_Loop_LB2D_bubkb
generic map (
DataWidth => 8,
AddressRange => 1920,
AddressWidth => 11)
port map (
clk => ap_clk,
reset => ap_rst,
address0 => buffer_1_value_V_address0,
ce0 => buffer_1_value_V_ce0,
q0 => buffer_1_value_V_q0,
address1 => ap_reg_pp0_iter1_buffer_1_value_V_ad_reg_310,
ce1 => buffer_1_value_V_ce1,
we1 => buffer_1_value_V_we1,
d1 => tmp_value_V_2_reg_321);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_168_p2 = ap_const_lv1_1))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_0 = tmp_fu_168_p2))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state3)) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state3 xor ap_const_logic_1);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_0 = tmp_fu_168_p2))) then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
real_start_status_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
real_start_status_reg <= ap_const_logic_0;
else
if ((start_full_n = ap_const_logic_1)) then
real_start_status_reg <= ap_const_logic_0;
elsif (((ap_const_logic_0 = start_full_n) and (ap_const_logic_1 = internal_ap_ready))) then
real_start_status_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
start_control_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
start_control_reg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = real_start) and ((ap_const_logic_1 = internal_ap_ready) or (ap_const_logic_0 = start_once_reg)))) then
start_control_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = start_control_reg)) then
start_control_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
start_once_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
start_once_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = real_start)) then
start_once_reg <= ap_const_logic_1;
elsif ((ap_const_logic_0 = ap_start)) then
start_once_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
col_reg_157_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_lv1_0 = tmp_2_fu_196_p2))) then
col_reg_157 <= col_1_fu_202_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_0 = tmp_fu_168_p2))) then
col_reg_157 <= ap_const_lv11_0;
end if;
end if;
end process;
row_reg_135_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
row_reg_135 <= row_1_reg_281;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = real_start) or (ap_done_reg = ap_const_logic_1))))) then
row_reg_135 <= ap_const_lv11_0;
end if;
end if;
end process;
write_idx_1_1_reg_146_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (tmp_2_reg_290 = ap_const_lv1_0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
write_idx_1_1_reg_146 <= p_write_idx_1_1_fu_236_p3;
elsif (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_0 = tmp_fu_168_p2))) then
write_idx_1_1_reg_146 <= write_idx_1_reg_123;
end if;
end if;
end process;
write_idx_1_reg_123_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
write_idx_1_reg_123 <= write_idx_1_2_fu_271_p2;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = real_start) or (ap_done_reg = ap_const_logic_1))))) then
write_idx_1_reg_123 <= ap_const_lv64_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_reg_pp0_iter1_buffer_0_value_V_ad_reg_304 <= buffer_0_value_V_ad_reg_304;
ap_reg_pp0_iter1_buffer_1_value_V_ad_reg_310 <= buffer_1_value_V_ad_reg_310;
tmp_10_reg_346 <= tmp_10_fu_247_p1;
tmp_2_reg_290 <= tmp_2_fu_196_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = tmp_2_fu_196_p2))) then
buffer_0_value_V_ad_reg_304 <= col_cast_fu_208_p1(11 - 1 downto 0);
buffer_1_value_V_ad_reg_310 <= col_cast_fu_208_p1(11 - 1 downto 0);
icmp1_reg_299 <= icmp1_fu_224_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (tmp_2_reg_290 = ap_const_lv1_0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
buffer_0_value_V_lo_reg_328 <= buffer_0_value_V_q0;
buffer_1_value_V_lo_reg_334 <= buffer_1_value_V_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_0 = tmp_fu_168_p2))) then
icmp_reg_286 <= icmp_fu_190_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
row_1_reg_281 <= row_1_fu_174_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_lv1_0 = icmp_reg_286) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
tmp_9_reg_340 <= tmp_9_fu_243_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (tmp_2_reg_290 = ap_const_lv1_0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
tmp_value_V_2_reg_321 <= in_stream_V_value_V_dout;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (real_start, ap_done_reg, ap_CS_fsm, ap_CS_fsm_state1, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, tmp_fu_168_p2, ap_CS_fsm_state2, tmp_2_fu_196_p2, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = real_start) or (ap_done_reg = ap_const_logic_1))))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_168_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) and not(((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (tmp_2_fu_196_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (tmp_2_fu_196_p2 = ap_const_lv1_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0)))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_state6 =>
ap_NS_fsm <= ap_ST_fsm_state2;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(2);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state6 <= ap_CS_fsm(3);
ap_block_pp0_assign_proc : process(ap_block_pp0_stage0_flag00011011)
begin
ap_block_pp0 <= (ap_const_boolean_1 = ap_block_pp0_stage0_flag00011011);
end process;
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00001001_assign_proc : process(in_stream_V_value_V_empty_n, slice_stream_V_value_V_full_n, ap_enable_reg_pp0_iter1, tmp_2_reg_290, ap_enable_reg_pp0_iter2, icmp_reg_286)
begin
ap_block_pp0_stage0_flag00001001 <= (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (tmp_2_reg_290 = ap_const_lv1_0) and (ap_const_logic_0 = in_stream_V_value_V_empty_n)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_lv1_0 = icmp_reg_286) and (ap_const_logic_0 = slice_stream_V_value_V_full_n)));
end process;
ap_block_pp0_stage0_flag00011001_assign_proc : process(in_stream_V_value_V_empty_n, slice_stream_V_value_V_full_n, ap_enable_reg_pp0_iter1, tmp_2_reg_290, ap_enable_reg_pp0_iter2, icmp_reg_286)
begin
ap_block_pp0_stage0_flag00011001 <= (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (tmp_2_reg_290 = ap_const_lv1_0) and (ap_const_logic_0 = in_stream_V_value_V_empty_n)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_lv1_0 = icmp_reg_286) and (ap_const_logic_0 = slice_stream_V_value_V_full_n)));
end process;
ap_block_pp0_stage0_flag00011011_assign_proc : process(in_stream_V_value_V_empty_n, slice_stream_V_value_V_full_n, ap_enable_reg_pp0_iter1, tmp_2_reg_290, ap_enable_reg_pp0_iter2, icmp_reg_286)
begin
ap_block_pp0_stage0_flag00011011 <= (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (tmp_2_reg_290 = ap_const_lv1_0) and (ap_const_logic_0 = in_stream_V_value_V_empty_n)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_lv1_0 = icmp_reg_286) and (ap_const_logic_0 = slice_stream_V_value_V_full_n)));
end process;
ap_block_state1_assign_proc : process(real_start, ap_done_reg)
begin
ap_block_state1 <= ((ap_const_logic_0 = real_start) or (ap_done_reg = ap_const_logic_1));
end process;
ap_block_state3_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage0_iter1_assign_proc : process(in_stream_V_value_V_empty_n, tmp_2_reg_290)
begin
ap_block_state4_pp0_stage0_iter1 <= ((tmp_2_reg_290 = ap_const_lv1_0) and (ap_const_logic_0 = in_stream_V_value_V_empty_n));
end process;
ap_block_state5_pp0_stage0_iter2_assign_proc : process(slice_stream_V_value_V_full_n, icmp_reg_286)
begin
ap_block_state5_pp0_stage0_iter2 <= ((ap_const_lv1_0 = icmp_reg_286) and (ap_const_logic_0 = slice_stream_V_value_V_full_n));
end process;
ap_condition_pp0_exit_iter0_state3_assign_proc : process(tmp_2_fu_196_p2)
begin
if ((tmp_2_fu_196_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state3 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_done_reg, tmp_fu_168_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_168_p2 = ap_const_lv1_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_done_reg;
end if;
end process;
ap_enable_operation_35_assign_proc : process(tmp_2_fu_196_p2)
begin
ap_enable_operation_35 <= (ap_const_lv1_0 = tmp_2_fu_196_p2);
end process;
ap_enable_operation_42_assign_proc : process(tmp_2_reg_290)
begin
ap_enable_operation_42 <= (tmp_2_reg_290 = ap_const_lv1_0);
end process;
ap_enable_operation_55_assign_proc : process(tmp_10_reg_346)
begin
ap_enable_operation_55 <= (ap_const_lv1_0 = tmp_10_reg_346);
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_enable_state3_pp0_iter0_stage0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0)
begin
ap_enable_state3_pp0_iter0_stage0 <= ((ap_CS_fsm_pp0_stage0 = ap_const_logic_1) and (ap_enable_reg_pp0_iter0 = ap_const_logic_1));
end process;
ap_enable_state4_pp0_iter1_stage0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1)
begin
ap_enable_state4_pp0_iter1_stage0 <= ((ap_CS_fsm_pp0_stage0 = ap_const_logic_1) and (ap_enable_reg_pp0_iter1 = ap_const_logic_1));
end process;
ap_enable_state5_pp0_iter2_stage0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter2)
begin
ap_enable_state5_pp0_iter2_stage0 <= ((ap_enable_reg_pp0_iter2 = ap_const_logic_1) and (ap_CS_fsm_pp0_stage0 = ap_const_logic_1));
end process;
ap_idle_assign_proc : process(real_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = real_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter0)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_ready <= internal_ap_ready;
buffer_0_value_V_address0 <= col_cast_fu_208_p1(11 - 1 downto 0);
buffer_0_value_V_address1 <= ap_reg_pp0_iter1_buffer_0_value_V_ad_reg_304;
buffer_0_value_V_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter0)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
buffer_0_value_V_ce0 <= ap_const_logic_1;
else
buffer_0_value_V_ce0 <= ap_const_logic_0;
end if;
end process;
buffer_0_value_V_ce1_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
buffer_0_value_V_ce1 <= ap_const_logic_1;
else
buffer_0_value_V_ce1 <= ap_const_logic_0;
end if;
end process;
buffer_0_value_V_we1_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, tmp_10_reg_346)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = tmp_10_reg_346))) then
buffer_0_value_V_we1 <= ap_const_logic_1;
else
buffer_0_value_V_we1 <= ap_const_logic_0;
end if;
end process;
buffer_1_value_V_address0 <= col_cast_fu_208_p1(11 - 1 downto 0);
buffer_1_value_V_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_flag00011001, ap_enable_reg_pp0_iter0)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
buffer_1_value_V_ce0 <= ap_const_logic_1;
else
buffer_1_value_V_ce0 <= ap_const_logic_0;
end if;
end process;
buffer_1_value_V_ce1_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
buffer_1_value_V_ce1 <= ap_const_logic_1;
else
buffer_1_value_V_ce1 <= ap_const_logic_0;
end if;
end process;
buffer_1_value_V_we1_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, tmp_10_reg_346)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (tmp_10_reg_346 = ap_const_lv1_1))) then
buffer_1_value_V_we1 <= ap_const_logic_1;
else
buffer_1_value_V_we1 <= ap_const_logic_0;
end if;
end process;
col_1_fu_202_p2 <= std_logic_vector(unsigned(col_reg_157) + unsigned(ap_const_lv11_1));
col_cast_fu_208_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(col_reg_157),64));
icmp1_fu_224_p2 <= "0" when (tmp_8_fu_214_p4 = ap_const_lv63_0) else "1";
icmp_fu_190_p2 <= "1" when (tmp_6_fu_180_p4 = ap_const_lv10_0) else "0";
in_stream_V_value_V_blk_n_assign_proc : process(in_stream_V_value_V_empty_n, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, tmp_2_reg_290)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (tmp_2_reg_290 = ap_const_lv1_0))) then
in_stream_V_value_V_blk_n <= in_stream_V_value_V_empty_n;
else
in_stream_V_value_V_blk_n <= ap_const_logic_1;
end if;
end process;
in_stream_V_value_V_read_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, tmp_2_reg_290, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (tmp_2_reg_290 = ap_const_lv1_0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
in_stream_V_value_V_read <= ap_const_logic_1;
else
in_stream_V_value_V_read <= ap_const_logic_0;
end if;
end process;
internal_ap_ready_assign_proc : process(tmp_fu_168_p2, ap_CS_fsm_state2)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (tmp_fu_168_p2 = ap_const_lv1_1))) then
internal_ap_ready <= ap_const_logic_1;
else
internal_ap_ready <= ap_const_logic_0;
end if;
end process;
p_Val2_2_0_phi_fu_251_p3 <=
buffer_1_value_V_lo_reg_334 when (tmp_9_reg_340(0) = '1') else
buffer_0_value_V_lo_reg_328;
p_Val2_2_1_phi_fu_256_p3 <=
buffer_0_value_V_lo_reg_328 when (tmp_9_reg_340(0) = '1') else
buffer_1_value_V_lo_reg_334;
p_write_idx_1_1_fu_236_p3 <=
write_idx_1_3_fu_230_p2 when (icmp1_reg_299(0) = '1') else
write_idx_1_1_reg_146;
real_start_assign_proc : process(ap_start, real_start_status_reg)
begin
if ((ap_const_logic_1 = real_start_status_reg)) then
real_start <= ap_const_logic_0;
else
real_start <= ap_start;
end if;
end process;
row_1_fu_174_p2 <= std_logic_vector(unsigned(row_reg_135) + unsigned(ap_const_lv11_1));
slice_stream_V_value_V_blk_n_assign_proc : process(slice_stream_V_value_V_full_n, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter2, icmp_reg_286)
begin
if (((ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_lv1_0 = icmp_reg_286))) then
slice_stream_V_value_V_blk_n <= slice_stream_V_value_V_full_n;
else
slice_stream_V_value_V_blk_n <= ap_const_logic_1;
end if;
end process;
slice_stream_V_value_V_din <= ((tmp_value_V_2_reg_321 & p_Val2_2_1_phi_fu_256_p3) & p_Val2_2_0_phi_fu_251_p3);
slice_stream_V_value_V_write_assign_proc : process(ap_enable_reg_pp0_iter2, icmp_reg_286, ap_block_pp0_stage0_flag00011001)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_const_lv1_0 = icmp_reg_286) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
slice_stream_V_value_V_write <= ap_const_logic_1;
else
slice_stream_V_value_V_write <= ap_const_logic_0;
end if;
end process;
start_out <= real_start;
start_write <= (ap_start and start_control_reg);
tmp_10_fu_247_p1 <= p_write_idx_1_1_fu_236_p3(1 - 1 downto 0);
tmp_2_fu_196_p2 <= "1" when (col_reg_157 = ap_const_lv11_780) else "0";
tmp_6_fu_180_p4 <= row_reg_135(10 downto 1);
tmp_8_fu_214_p4 <= write_idx_1_1_phi_fu_149_p4(63 downto 1);
tmp_9_fu_243_p1 <= p_write_idx_1_1_fu_236_p3(1 - 1 downto 0);
tmp_fu_168_p2 <= "1" when (row_reg_135 = ap_const_lv11_438) else "0";
write_idx_1_1_phi_fu_149_p4_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000, tmp_2_reg_290, write_idx_1_1_reg_146, p_write_idx_1_1_fu_236_p3)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (tmp_2_reg_290 = ap_const_lv1_0))) then
write_idx_1_1_phi_fu_149_p4 <= p_write_idx_1_1_fu_236_p3;
else
write_idx_1_1_phi_fu_149_p4 <= write_idx_1_1_reg_146;
end if;
end process;
write_idx_1_2_fu_271_p2 <= std_logic_vector(unsigned(write_idx_1_1_reg_146) + unsigned(ap_const_lv64_1));
write_idx_1_3_fu_230_p2 <= std_logic_vector(unsigned(write_idx_1_1_reg_146) + unsigned(ap_const_lv64_FFFFFFFFFFFFFFFE));
end behav;
|
-----Libraries-----
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-----Entity-----
entity tester is
port( KEY : in std_logic_vector(1 downto 0);
SW : in std_logic_vector(11 downto 0);
HEX0, HEX1, HEX2, HEX3 : out std_logic_vector(6 downto 0)
);
end tester;
-----Architecture-----
architecture TEST of tester is
signal data_val : std_logic_vector(20 downto 0) := "111111111111111111111";
begin
HEX3 <= "1111111";
MX : entity work.Multiplexer port map (data => data_val, bin_in => SW, ab => KEY);
DMX : entity work.Demultiplexer port map (data_in => data_val, disp0 => HEX0, disp1 => HEX1, disp2 => HEX2);
end TEST;
|
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<KEY>
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<KEY>
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<KEY>
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<KEY>
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<KEY>
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`protect end_protected
|
-------------------------------------------------------------
-- Calculates a carry-in value for a carry look-ahead adder
-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- carry-in calculator entity
entity carry_calc is
-- generic paramter for which carry-in bit to calculate, e.g.
-- 3 will calculate carry-in for index 3
generic (g_BIT_INDEX: positive);
-- inputs are original carry in, plus carry propagate and
-- carry generate for all previous bits. Output is the
-- carry-in bit for the given index
port (i_c0: in std_logic;
i_p, i_g: in std_logic_vector(g_BIT_INDEX-1 downto 0);
o_c: out std_logic);
end carry_calc;
-- carry-in calculator architecture
architecture struct of carry_calc is
-- internal signal for previous (less significant index) carry-in bit
signal w_c_prev: std_logic;
begin
-- recursively calculate previous carry in
G_RECURSIVE_CARRY_CALC: if g_BIT_INDEX > 1 generate
E_CC: entity work.carry_calc(struct)
generic map (g_BIT_INDEX-1)
port map (i_c0,
i_p(g_BIT_INDEX-2 downto 0),
i_g(g_BIT_INDEX-2 downto 0),
w_c_prev);
end generate;
-- base condition for recursive calculation: previous carry-in bit
-- is original carry-in bit when calculating carry-in at index 1
G_BASE_CARRY_CALC: if g_BIT_INDEX = 1 generate
w_c_prev <= i_c0;
end generate;
-- calculate carry-in based on recursively calculated previous carry-in
o_c <= i_g(g_BIT_INDEX-1) or (i_p(g_BIT_INDEX-1) and w_c_prev);
end struct;
|
<gh_stars>0
-- ==============================================================
-- Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit)
-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity houghlines_accel_xfHoughLines_0_480_640_0_1_1_2u_1u_32_800_0_180_s_accum_V_180_ram is
generic(
MEM_TYPE : string := "block";
DWIDTH : integer := 1;
AWIDTH : integer := 10;
MEM_SIZE : integer := 801
);
port (
addr0 : in std_logic_vector(AWIDTH-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(DWIDTH-1 downto 0);
we0 : in std_logic;
clk : in std_logic
);
end entity;
architecture rtl of houghlines_accel_xfHoughLines_0_480_640_0_1_1_2u_1u_32_800_0_180_s_accum_V_180_ram is
type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is MEM_TYPE;
begin
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0)) := d0;
end if;
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity houghlines_accel_xfHoughLines_0_480_640_0_1_1_2u_1u_32_800_0_180_s_accum_V_180 is
generic (
DataWidth : INTEGER := 1;
AddressRange : INTEGER := 801;
AddressWidth : INTEGER := 10);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of houghlines_accel_xfHoughLines_0_480_640_0_1_1_2u_1u_32_800_0_180_s_accum_V_180 is
component houghlines_accel_xfHoughLines_0_480_640_0_1_1_2u_1u_32_800_0_180_s_accum_V_180_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR);
end component;
begin
houghlines_accel_xfHoughLines_0_480_640_0_1_1_2u_1u_32_800_0_180_s_accum_V_180_ram_U : component houghlines_accel_xfHoughLines_0_480_640_0_1_1_2u_1u_32_800_0_180_s_accum_V_180_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
we0 => we0,
d0 => d0);
end architecture;
|
-- BSD 3-Clause License
--
-- Copyright (c) 2018, <NAME>
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
-- * Neither the name of the copyright holder nor the names of its
-- contributors may be used to endorse or promote products derived from
-- this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
-- CLOCK GENERATOR TESTBENCH
----------------------------------------------------------------------------------
-- Tests the generated MMCM via Clocking Wizard + Block Design
-- (via Waveform Viewer)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_logic_1164.all;
entity MMCM_unit_wrapper_tb is
Generic (
g_clock_period : TIME := 10 ns -- input clock 100 MHz
);
end;
architecture bench of MMCM_unit_wrapper_tb is
component MMCM_unit_wrapper
port (
clk_in1 : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
clk_out3 : out STD_LOGIC;
clk_out4 : out STD_LOGIC;
clk_out5 : out STD_LOGIC;
clk_out6 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component;
signal r_CLK_IN: STD_LOGIC;
signal r_RESET: STD_LOGIC;
signal w_clk_out1: STD_LOGIC;
signal w_clk_out2: STD_LOGIC;
signal w_clk_out3: STD_LOGIC;
signal w_clk_out4: STD_LOGIC;
signal w_clk_out5: STD_LOGIC;
signal w_clk_out6: STD_LOGIC;
signal w_locked: STD_LOGIC;
begin
uut: MMCM_unit_wrapper
port map (
clk_in1 => r_CLK_IN,
reset => r_RESET,
clk_out1 => w_clk_out1,
clk_out2 => w_clk_out2,
clk_out3 => w_clk_out3,
clk_out4 => w_clk_out4,
clk_out5 => w_clk_out5,
clk_out6 => w_clk_out6,
locked => w_locked
);
PROC_stimulus: process
begin
r_RESET <= '0';
wait for 2 us;
-- MMCM process continues running, even if the PROC_clock process
-- would be stopped, therefore stopped using assert FALSE.
assert FALSE
report "Simulation finished!"
severity failure;
wait;
end process PROC_stimulus;
PROC_clock: process
begin
while TRUE loop
r_CLK_IN <= '0';
wait for g_clock_period/2;
r_CLK_IN <= '1';
wait for g_clock_period/2;
end loop;
wait;
end process PROC_clock;
end architecture;
|
<filename>Kintex7_Coprocessor/ip_repo/AXIS_picnic_l5_sign_1.0/src/keccak_pkg.vhd
library ieee;
use ieee.std_logic_1164.all;
library work;
package keccak_pkg is
constant CUBE_LEN : integer := 5;
constant W : integer := 64;
constant B : integer := 1600;
constant KECCAK_N : integer := 24;
subtype T_ROW is std_logic_vector((W - 1) downto 0);
type T_COLUMN is array (0 to CUBE_LEN - 1) of T_ROW;
type T_STATE is array (0 to CUBE_LEN - 1) of T_COLUMN;
type T_ROT is array(0 to 24) of integer;
type T_RC is array(0 to KECCAK_N - 1) of std_logic_vector((W - 1) downto 0);
constant ROT : T_ROT := (
0, 1, 62, 28, 27, 36, 44, 6, 55, 20, 3, 10, 43, 25, 39,
41, 45, 15, 21, 8, 18, 2, 61, 56, 14
);
constant RC : T_RC := (
x"0000000000000001",
x"0000000000008082",
x"800000000000808a",
x"8000000080008000",
x"000000000000808b",
x"0000000080000001",
x"8000000080008081",
x"8000000000008009",
x"000000000000008a",
x"0000000000000088",
x"0000000080008009",
x"000000008000000a",
x"000000008000808b",
x"800000000000008b",
x"8000000000008089",
x"8000000000008003",
x"8000000000008002",
x"8000000000000080",
x"000000000000800a",
x"800000008000000a",
x"8000000080008081",
x"8000000000008080",
x"0000000080000001",
x"8000000080008008"
);
end keccak_pkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity VGA_tb is
-- Port ( );
end VGA_tb;
architecture Behavioral of VGA_tb is
component VGA is
Port (
clock : in std_logic;
reset : in std_logic;
char : in std_logic_vector (7 downto 0);
getchar : out std_logic;
hsync : out std_logic;
vsync : out std_logic;
red : out std_logic_vector (3 downto 0);
green : out std_logic_vector (3 downto 0);
blue : out std_logic_vector (3 downto 0)
);
end component;
signal clock : std_logic := '0';
signal reset : std_logic;
signal char : std_logic_vector (7 downto 0) := "01001011";
signal getchar : std_logic;
constant CLK_PERIOD : time := 10 ns;
begin
UUT : VGA
port map(
clock => clock,
reset => reset,
char => char,
hsync => open,
vsync => open,
getchar => getchar,
red => open,
green => open,
blue => open
);
CLK_STIMULUS : process
begin
for I in 0 to 100000 loop
clock <= not clock;
wait for CLK_PERIOD/2;
end loop;
end process;
OTH_STIMULI : process
begin
-- Reset
reset <= '1';
wait for CLK_PERIOD * 3;
reset <= '0';
wait until getchar = '1';
wait for CLK_PERIOD * 3;
char <= "00100100"; --E
wait until getchar = '1';
wait for CLK_PERIOD * 3;
char <= "00100011"; --D
wait until getchar = '1';
wait for CLK_PERIOD * 3;
char <= "00101001"; --Space
wait until getchar = '1';
wait for CLK_PERIOD * 3;
char <= "00011110"; --1
wait until getchar = '1';
wait for CLK_PERIOD * 3;
char <= "00101001"; --Space
wait until getchar = '1';
wait for CLK_PERIOD * 3;
char <= "01000100"; --O
wait until getchar = '1';
wait for CLK_PERIOD * 3;
char <= "00110001"; --N
wait until getchar = '1';
wait for CLK_PERIOD * 3;
char <= "01011010"; --Enter
--for i in 0 to 2 loop
end process;
end architecture;
|
<gh_stars>0
-- --------------------------------------------------------------------
-- Title : TEST_STRING < IEEE std 1076.3 >
--
-- Library : This is test code which may be compile into any work library
--
-- Developers: VHDL-200X FT Working Group, PAR 1076B
--
-- Purpose : Test of "to_string" functions in numeric_std
-- and std_logic_1164
--
-- Last Modified: $Date: 2006-06-08 11:01:00-04 $
-- RCS ID: $Id: test_string.vhdl,v 1.1 2006-06-08 11:01:00-04 l435385 Exp $
--
-- Limitation:
--
-- --------------------------------------------------------------------
library vunit_lib;
context vunit_lib.vunit_context;
entity test_string is
generic (
runner_cfg : string);
end entity test_string;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
architecture testbench of test_string is
-- purpose: reports an error
procedure report_error (
constant errmes : STRING; -- error message
actual : in STRING; -- data from algorithm
constant expected : STRING) is -- reference data
variable L : LINE;
begin -- function report_error
assert (actual = expected)
report "TEST_STRING: " & errmes & CR
& "Actual " & actual & " /= " & CR
& "Expected " & expected
severity failure;
return;
end procedure report_error;
signal start_readtest, readtest_done : BOOLEAN := false; -- start reading test
signal start_stest, stest_done : BOOLEAN := false; -- start reading test
begin -- architecture testbench
-- purpose: Checks basic string functions
-- type : combinational
-- inputs :
-- outputs:
Test_process : process is
variable checknum : UNSIGNED (23 downto 0); -- checknum
variable checknum1 : UNSIGNED (24 downto 0); -- checknum
variable checknum2 : UNSIGNED (25 downto 0); -- checknum
variable checknum3 : UNSIGNED (26 downto 0); -- checknum
variable checkstr, checkstrx : STRING (1 to 24);
variable checkstrb : STRING (24 downto 1); -- downto string
variable checkstr1, checkstrx1 : STRING (1 to 25);
variable checkstr2, checkstrx2 : STRING (1 to 26);
variable checkstr3, checkstrx3 : STRING (1 to 27);
variable checknums : SIGNED (23 downto 0); -- signed number
variable checkst1 : STRING (1 to 1); -- 1 char
variable checkst2 : STRING (1 to 2); -- 2 char
variable checkst3 : STRING (1 to 3); -- 3 char
variable checkstr4 : STRING (1 to 4); -- 4 char
variable checkstr5 : STRING (1 to 5); -- 5 char
variable checkstr6 : STRING (1 to 6); -- 6 char
variable checkstr7 : STRING (1 to 7); -- 7 char
variable checkstr8 : STRING (1 to 8); -- 7 char
variable checkstr9 : STRING (1 to 9); -- 7 char
begin
test_runner_setup(runner, runner_cfg);
while test_suite loop
if run("Test to_string") then
checknum := "000000000000000000000000";
checkstr := to_string (checknum);
report_error ("First string test", checkstr,
"000000000000000000000000");
checknum := "000000000000000000000011";
checkstr := to_string (checknum);
report_error ("right string test", checkstr,
"000000000000000000000011");
checknum := "011000000000000000000000";
checkstr := to_string (checknum);
report_error ("left string test", checkstr,
"011000000000000000000000");
checknum := "000000000000UX01ZWLH-000";
checkstr := to_string (checknum);
report_error ("MVL string test", checkstr,
"000000000000UX01ZWLH-000");
checknum := "000000000000000000000011";
checkstr := to_string (checknum);
report_error ("string left justify 0", checkstr,
"000000000000000000000011");
checknum := "000000000000000000000011";
--checkstr1 := justify (to_string (checknum), left, 25);
--report_error ("string left justify 25", checkstr1,
-- "000000000000000000000011 ");
--checknum := "000000000000000000000011";
--checkstr1 := justify (to_string (checknum), right, 25);
--report_error ("string right justify 25", checkstr1,
-- " 000000000000000000000011");
checknum := "000000000000000000000011";
checkstr := to_string (checknum);
report_error ("string right justify 0", checkstr,
"000000000000000000000011");
elsif run("Test to_ostring") then
checknum := "000000000000000000000011";
checkstr8 := to_ostring (checknum);
report_error ("First octal test", checkstr8,
"00000003");
checknum := "111110101100011010001000";
checkstr8 := to_ostring (checknum);
report_error ("First octal test", checkstr8,
"76543210");
checknum := "001010011100101110000111";
checkstr8 := to_ostring (checknum);
report_error ("First octal test", checkstr8,
"12345607");
checknum := "00U00X00-X0000Z00W00L00H";
checkstr8 := to_ostring (checknum);
report_error ("unknown hole octal test", checkstr8,
"XXXXXX01");
checknum := "UUUXXX---ZZZWWWLLLHHHZZZ";
checkstr8 := to_ostring (checknum);
report_error ("unknown octal test", checkstr8,
"XXXZX07Z");
elsif run("Test to_ostring with padding") then
checknum1 := "0000000000000000000000011";
checkstr9 := to_ostring (checknum1);
report_error ("Octal padding test 1", checkstr9,
"000000003");
checknum2 := "11111110101100011010001000";
checkstr9 := to_ostring (checknum2);
report_error ("Octal padding test 2", checkstr9,
"376543210");
checknum1 := "1001010011100101110000111";
checkstr9 := to_ostring (checknum1);
report_error ("Octal padding test 3", checkstr9,
"112345607");
checknum1 := "Z001010011100101110000111";
checkstr9 := to_ostring (checknum1);
report_error ("Octal Z padding test 1", checkstr9,
"Z12345607");
checknum2 := "ZZ001010011100101110000111";
checkstr9 := to_ostring (checknum2);
report_error ("Octal Z padding test 2", checkstr9,
"Z12345607");
checknums := "100000000000000000000011";
checkstr8 := to_ostring (checknums);
report_error ("Octal signed test", checkstr8,
"40000003");
elsif run("Test to_hstring") then
checknum := "000000000000000000000011";
checkstr6 := to_hstring (checknum);
report_error ("First hex test", checkstr6,
"000003");
checknum := "010101000011001000010000";
checkstr6 := to_hstring (checknum);
report_error ("First hex number test", checkstr6,
"543210");
checknum := "101110101001100001110110";
checkstr6 := to_hstring (checknum);
report_error ("second hex number test", checkstr6,
"BA9876");
checknum := "111111101101110010111010";
checkstr6 := to_hstring (checknum);
report_error ("3 hex letter test", checkstr6,
"FEDCBA");
checknum := "001010011100101110000111";
checkstr6 := to_hstring (checknum);
report_error ("hex octal test", checkstr6,
"29CB87");
checknum := "U000X000-000Z000W000LHHH";
checkstr6 := to_hstring (checknum);
report_error ("unknown hole hex test", checkstr6,
"XXXXX7");
checknum := "ZZZZHHHHLLLL00LLHH11ZZZZ";
checkstr6 := to_hstring (checknum);
report_error ("ZH hex test", checkstr6,
"ZF00FZ");
checknum1 := "0000000000000000000000011";
checkstr7 := to_hstring (checknum1);
report_error ("Hex padding test 1", checkstr7,
"0000003");
checknum2 := "01000000000000000000000011";
checkstr7 := to_hstring (checknum2);
report_error ("Hex padding test 2", checkstr7,
"1000003");
checknum3 := "101000000000000000000000011";
checkstr7 := to_hstring (checknum3);
report_error ("Hex padding test 3", checkstr7,
"5000003");
checknum3 := "UX-000000000000000000000011";
checkstr7 := to_hstring (checknum3);
report_error ("Hex padding test 4", checkstr7,
"X000003");
checknum3 := "ZZZ000000000000000000000011";
checkstr7 := to_hstring (checknum3);
report_error ("Hex padding Z test 1", checkstr7,
"Z000003");
checknums := "100000000000000000000011";
checkstr6 := to_hstring (checknums);
report_error ("signed hex test", checkstr6,
"800003");
--elsif run("Test to_dstring") then
-- checknum := "000000000000000000000011";
-- checkst1 := to_dstring (checknum);
-- report_error ("First decimal test", checkst1,
-- "3");
-- checknum := "000000000000000000001111";
-- checkst2 := to_dstring (checknum);
-- report_error ("2 decimal test", checkst2,
-- "15");
-- checknum := "0000000000000000LLLLHHHH";
-- checkst2 := to_dstring (checknum);
-- report_error ("HL decimal test", checkst2,
-- "15");
-- checknum := "X00000000000000000000011";
-- checkst1 := to_dstring (checknum);
-- report_error ("X decimal test", checkst1,
-- "X");
-- checknum := "Z00000000000000000000011";
-- checkst1 := to_dstring (checknum);
-- report_error ("Z decimal test", checkst1,
-- "X");
-- checknum := "W00000000000000000000011";
-- checkst1 := to_dstring (checknum);
-- report_error ("W decimal test", checkst1,
-- "X");
-- checknum := "U00000000000000000000011";
-- checkst1 := to_dstring (checknum);
-- report_error ("U decimal test", checkst1,
-- "X");
-- checknum := "-00000000000000000000011";
-- checkst1 := to_dstring (checknum);
-- report_error ("- decimal test", checkst1,
-- "X");
-- checknums := "111111111111111111111111";
-- report_error ("dec signed test", to_dstring (checknums),
-- "-1");
-- checknums := "111111111111111111110000";
-- report_error ("dec signed test 2", to_dstring (checknums),
-- "-16");
elsif run("Test the read routines") or
run("Expected to fail: Test HREAD vector truncated error 1") or
run("Expected to fail: Test HREAD vector truncated error 2") or
run("Expected to fail: Test OREAD vector truncated error 1") or
run("Expected to fail: Test OREAD vector truncated error 2") then
start_readtest <= true;
wait until readtest_done;
end if;
end loop;
test_runner_cleanup(runner);
wait;
end process Test_process;
-- purpose: test the read routines
-- type : combinational
-- inputs :
-- outputs:
read_test : process is
constant rstring : STRING := "110010101011"; -- constant string
constant rstringh : STRING := "CAB"; -- constant string
constant rstringo : STRING := "6253"; -- constant string
constant rstringd : STRING := "3243"; -- constant string
constant rstringn : STRING := "-853"; -- constant string
constant bstring1 : STRING := ""; -- empty string
constant bstring2 : STRING := "11*111*1111*"; -- illegal characters
constant bstring3 : STRING := "11 111 1111"; -- space characters
constant bstring4 : STRING := " 11 "; -- space padding
variable checknum : UNSIGNED (11 downto 0); -- unsigned
variable checknums : SIGNED (11 downto 0); -- signed
variable checknums2 : SIGNED (12 downto 0); -- signed
variable l : LINE; -- line variable
variable checkbool : BOOLEAN; -- check boolean
begin -- process read_test
wait until start_readtest;
if running_test_case = "Test the read routines" then
L := new STRING'(rstring);
read (L, checknum);
report_error ("Error in binary Read",
to_string(checknum),
"110010101011");
deallocate (L);
checknum := (others => '-');
L := new STRING'(rstringh);
hread (L, checknum);
report_error ("Error in hex read",
to_string(checknum),
"110010101011");
deallocate (L);
checknum := (others => '-');
L := new STRING'(rstringo);
oread (L, checknum);
report_error ("Error in octal read",
to_string(checknum),
"110010101011");
deallocate (L);
-- L := new string'(rstringd);
-- checknum := (others => '-');
-- dread (L, checknum);
-- report_error ("Error in decimal read",
-- to_string(checknum),
-- "110010101011");
-- deallocate (L);
L := new STRING'(rstring);
read (L, checknums);
report_error ("Error in binary Read",
to_string(checknums),
"110010101011");
deallocate (L);
checknums := (others => '-');
L := new STRING'(rstringh);
hread (L, checknums);
report_error ("Error in hex read",
to_string(checknums),
"110010101011");
deallocate (L);
checknums := (others => '-');
L := new STRING'(rstringo);
oread (L, checknums);
report_error ("Error in octal read",
to_string(checknums),
"110010101011");
deallocate (L);
-- Play with some signed values
checknums2 := (others => '0');
L := new STRING'("1001");
hread (L, checknums2, checkbool);
assert (not checkbool)
report "short hread (1001) failed to report error"
severity failure;
deallocate (L);
checknums2 := (others => '0');
L := new STRING'("2001");
hread (L, checknums2, checkbool);
assert (not checkbool)
report "short hread (2001) failed to report error"
severity failure;
deallocate (L);
checknums2 := (others => '0');
L := new STRING'("3001");
hread (L, checknums2, checkbool);
assert (not checkbool)
report "short hread (3001) failed to report error"
severity failure;
deallocate (L);
checknums2 := (others => '0');
L := new STRING'("8001");
hread (L, checknums2, checkbool);
assert (not checkbool)
report "short hread (8001) failed to report error"
severity failure;
deallocate (L);
checknums2 := (others => '0');
L := new STRING'("0001");
hread (L, checknums2, checkbool);
assert (checkbool) report "short hread(0001) reported error"
severity failure;
report_error ("SIGNED hex read w/ bool",
to_string (checknums2), "0000000000001");
deallocate (L);
checknums2 := (others => '0');
L := new STRING'("0001");
hread (L, checknums2);
report_error ("SIGNED hex read",
to_string (checknums2), "0000000000001");
deallocate (L);
checknums2 := (others => '-');
L := new STRING'("F001");
hread (L, checknums2, checkbool);
assert (checkbool) report "short hread(F001) reported error"
severity failure;
report_error ("SIGNED hex -read w/ bool",
to_string (checknums2), "1000000000001");
deallocate (L);
checknums2 := (others => '0');
L := new STRING'("F001");
hread (L, checknums2);
report_error ("SIGNED hex -read",
to_string (checknums2), "1000000000001");
deallocate (L);
checknums2 := (others => '-');
L := new STRING'("ZZZZ");
hread (L, checknums2);
report_error ("SIGNED hex read(ZZZZ)",
to_string (checknums2), "ZZZZZZZZZZZZZ");
deallocate (L);
checknums2 := (others => '-');
L := new STRING'("XXXX");
hread (L, checknums2);
report_error ("SIGNED hex read(XXXX)",
to_string (checknums2), "XXXXXXXXXXXXX");
deallocate (L);
checknums2 := (others => '-');
L := new STRING'("ZZZZ");
hread (L, checknums2, checkbool);
assert (checkbool) report "short hread(ZZZZ) reported error"
severity failure;
report_error ("SIGNED hex read(ZZZZ) w/ bool",
to_string (checknums2), "ZZZZZZZZZZZZZ");
deallocate (L);
checknums2 := (others => '-');
L := new STRING'("XXXX");
hread (L, checknums2, checkbool);
assert (checkbool) report "short hread(XXXX) reported error"
severity failure;
report_error ("SIGNED hex read(XXXX) w/ bool",
to_string (checknums2), "XXXXXXXXXXXXX");
deallocate (L);
checknums2 := (others => '-');
L := new STRING'("01007"); -- octal
oread (L, checknums2);
report_error ("SIGNED oct read",
to_string (checknums2), "0001000000111");
deallocate (L);
L := new STRING'("01007"); -- octal
oread (L, checknums2, checkbool);
assert (checkbool) report "short oread(01007) reported error"
severity failure;
report_error ("SIGNED oct read w/ bool",
to_string (checknums2), "0001000000111");
deallocate (L);
L := new STRING'("71007"); -- octal
oread (L, checknums2);
report_error ("SIGNED oct read 71007",
to_string (checknums2), "1001000000111");
deallocate (L);
L := new STRING'("71007"); -- octal
oread (L, checknums2, checkbool);
assert (checkbool) report "short oread(71007) reported error"
severity failure;
report_error ("SIGNED oct read 71007 w/ bool",
to_string (checknums2), "1001000000111");
deallocate (L);
L := new STRING'("17005");
oread (L, checknums2, checkbool);
assert not (checkbool) report "short oread(17005) not reported error"
severity failure;
deallocate (L);
L := new STRING'("23005");
oread (L, checknums2, checkbool);
assert not (checkbool) report "short oread(23005) not reported error"
severity failure;
deallocate (L);
L := new STRING'("ZZZZZ");
oread (L, checknums2);
report_error ("oread (ZZZZZ) SIGNED short",
to_string (checknums2), "ZZZZZZZZZZZZZ");
deallocate (L);
L := new STRING'("XXXXX");
oread (L, checknums2);
report_error ("oread (XXXXX) SIGNED short",
to_string (checknums2), "XXXXXXXXXXXXX");
deallocate (L);
L := new STRING'("ZZZZZ");
oread (L, checknums2, checkbool);
assert (checkbool)
report "oread(ZZZZZ) signed short reported error" severity failure;
report_error ("oread (ZZZZZ) SIGNED short",
to_string (checknums2), "ZZZZZZZZZZZZZ");
deallocate (L);
L := new STRING'("XXXXX");
oread (L, checknums2, checkbool);
assert (checkbool)
report "oread(XXXXX) signed short reported error" severity failure;
report_error ("oread (XXXXX) SIGNED short",
to_string (checknums2), "XXXXXXXXXXXXX");
deallocate (L);
-- L := new string'(rstringd);
-- dread (L, checknums2);
-- report_error ("Error in decimal read",
-- to_string(checknums2),
-- "0110010101011");
-- deallocate (L);
-- checknums := (others => '-');
-- L := new string'(rstringn);
-- dread (L, checknums);
-- report_error ("Error in negative decimal read",
-- to_string(checknums),
-- "110010101011");
-- deallocate (L);
-- read with boolean checks
L := new STRING'(rstring);
checknum := (others => '-');
read (L, checknum, checkbool);
assert (checkbool) report "TEST_STRING: Read reported error condition"
severity failure;
report_error ("Error in binary Read",
to_string(checknum),
"110010101011");
deallocate (L);
checknum := (others => '-');
L := new STRING'(rstringh);
hread (L, checknum, checkbool);
assert (checkbool) report "TEST_STRING: Read reported error condition"
severity failure;
report_error ("Error in hex read",
to_string(checknum),
"110010101011");
deallocate (L);
checknum := (others => '-');
L := new STRING'(rstringo);
oread (L, checknum, checkbool);
assert (checkbool) report "TEST_STRING: Read reported error condition"
severity failure;
report_error ("Error in unsigned octal read",
to_string(checknum),
"110010101011");
deallocate (L);
-- checknum := (others => '-');
-- L := new string'(rstringd);
-- dread (L, checknum, checkbool);
-- assert (checkbool) report "TEST_STRING: Read reported error condition"
-- severity failure;
-- report_error ("Error in decimal read",
-- to_string(checknum),
-- "110010101011");
-- deallocate (L);
checknums := (others => '-');
L := new STRING'(rstring);
read (L, checknums, checkbool);
assert (checkbool) report "TEST_STRING: Read reported error condition"
severity failure;
report_error ("Error in binary Read",
to_string(checknums),
"110010101011");
deallocate (L);
checknums := (others => '-');
L := new STRING'(rstringh);
hread (L, checknums, checkbool);
assert (checkbool) report "TEST_STRING: Read reported error condition"
severity failure;
report_error ("Error in hex read",
to_string(checknums),
"110010101011");
deallocate (L);
checknums := (others => '-');
L := new STRING'(rstringo);
oread (L, checknums, checkbool);
assert (checkbool) report "TEST_STRING: Read reported error condition"
severity failure;
report_error ("Error in signed octal read",
to_string(checknums),
"110010101011");
-- deallocate (L);
-- checknums2 := (others => '-');
-- L := new string'(rstringd);
-- dread (L, checknums2, checkbool);
-- assert (checkbool) report "TEST_STRING: Read reported error condition"
-- severity failure;
-- report_error ("Error in decimal read",
-- to_string(checknums2),
-- "0110010101011");
-- deallocate (L);
-- checknums := (others => '-');
-- L := new string'(rstringn);
-- dread (L, checknums, checkbool);
-- assert (checkbool) report "TEST_STRING: Read reported error condition"
-- severity failure;
-- report_error ("Error in negative decimal read",
-- to_string(checknums),
-- "110010101011");
deallocate (L);
L := null;
checknum := "110010101011";
write (L, checknum);
report_error ("Error in unsigned write",
L.all,
"110010101011");
deallocate (L);
L := null;
checknum := "110010101011";
hwrite (L, checknum);
report_error ("Error in unsigned hwrite",
L.all,
rstringh);
deallocate (L);
L := null;
checknum := "110010101011";
owrite (L, checknum);
report_error ("Error in unsigned owrite",
L.all,
rstringo);
deallocate (L);
-- L := null;
-- checknum := "110010101011";
-- dwrite ( L, checknum );
-- report_error ("Error in unsigned dwrite",
-- L.all,
-- rstringd);
L := null;
checknums := "110010101011";
write (L, checknums);
report_error ("Error in signed write",
L.all,
"110010101011");
deallocate (L);
L := null;
checknums := "110010101011";
hwrite (L, checknums);
report_error ("Error in signed hwrite",
L.all,
rstringh);
deallocate (L);
L := null;
checknums := "110010101011";
owrite (L, checknums);
report_error ("Error in signed owrite",
L.all,
rstringo);
deallocate (L);
-- L := null;
-- checknums := "110010101011";
-- dwrite ( L, checknums );
-- report_error ("Error in signed dwrite",
-- L.all,
-- rstringn);
-- Verify read error conditions
-- read with boolean checks
L := new STRING'(bstring1);
checknum := (others => '-');
read (L, checknum, checkbool);
assert (not checkbool)
report "TEST_STRING: Read unreported error condition"
severity failure;
report_error ("Error in bad binary Read",
to_string(checknum),
"UUUUUUUUUUUU");
deallocate (L);
L := new STRING'(bstring1);
checknum := (others => '-');
hread (L, checknum, checkbool);
assert (not checkbool)
report "TEST_STRING: hRead unreported error condition"
severity failure;
deallocate (L);
L := new STRING'(bstring1);
checknum := (others => '-');
oread (L, checknum, checkbool);
assert (not checkbool)
report "TEST_STRING: oRead unreported error condition"
severity failure;
-- deallocate (L);
-- L := new string'(bstring1);
-- checknum := (others => '-');
-- dread (L, checknum, checkbool);
-- assert (not checkbool) report "TEST_STRING: dRead unreported error condition"
-- severity failure;
-- report_error ("Error in bad decmial Read",
-- to_string(checknum),
-- "UUUUUUUUUUUU");
deallocate (L);
L := new STRING'(bstring1);
checknums := (others => '-');
read (L, checknums, checkbool);
assert (not checkbool)
report "TEST_STRING: Read unreported error condition"
severity failure;
deallocate (L);
L := new STRING'(bstring1);
checknums := (others => '-');
hread (L, checknums, checkbool);
assert (not checkbool)
report "TEST_STRING: hRead unreported error condition"
severity failure;
deallocate (L);
L := new STRING'(bstring1);
checknums := (others => '-');
oread (L, checknums, checkbool);
assert (not checkbool)
report "TEST_STRING: oRead unreported error condition"
severity failure;
deallocate (L);
-- L := new string'(bstring1);
-- checknums := (others => '-');
-- dread (L, checknums, checkbool);
-- assert (not checkbool) report "TEST_STRING: dRead unreported error condition"
-- severity failure;
-- report_error ("Error in bad decmial Read",
-- to_string(checknums),
-- "UUUUUUUUUUUU");
-- deallocate (L);
L := new STRING'(bstring2);
checknum := (others => '-');
read (L, checknum, checkbool);
assert (not checkbool)
report "TEST_STRING: Read2 unreported error condition"
severity failure;
deallocate (L);
L := new STRING'(bstring2);
checknum := (others => '-');
hread (L, checknum, checkbool);
assert (not checkbool)
report "TEST_STRING: hRead2 unreported error condition"
severity failure;
deallocate (L);
L := new STRING'(bstring2);
checknum := (others => '-');
oread (L, checknum, checkbool);
assert (not checkbool)
report "TEST_STRING: oRead2 unreported error condition"
severity failure;
-- deallocate (L);
-- L := new string'(bstring2);
-- checknum := (others => '-');
-- dread (L, checknum, checkbool); -- Will read "11" from this string
-- assert (checkbool) report "TEST_STRING: dRead2 reported error condition"
-- severity failure;
-- report_error ("Error in bad decmial Read",
-- to_string(checknum),
-- "000000001011");
deallocate (L);
L := new STRING'(bstring2);
checknums := (others => '-');
read (L, checknums, checkbool);
assert (not checkbool)
report "TEST_STRING: Read2 unreported error condition"
severity failure;
deallocate (L);
L := new STRING'(bstring2);
checknums := (others => '-');
hread (L, checknums, checkbool);
assert (not checkbool)
report "TEST_STRING: hRead2 unreported error condition"
severity failure;
deallocate (L);
L := new STRING'(bstring2);
checknums := (others => '-');
oread (L, checknums, checkbool);
assert (not checkbool)
report "TEST_STRING: oRead2 unreported error condition"
severity failure;
deallocate (L);
-- L := new string'(bstring2);
-- checknums := (others => '-');
-- dread (L, checknums, checkbool); -- Will read "11" from this string
-- assert (checkbool) report "TEST_STRING: dRead2 reported error condition"
-- severity failure;
-- report_error ("Error in bad decmial Read",
-- to_string(checknums),
-- "000000001011");
-- deallocate (L);
L := new STRING'(bstring3);
checknum := (others => '-');
read (L, checknum, checkbool);
assert (not checkbool)
report "TEST_STRING: Read3 unreported error condition"
severity failure;
deallocate (L);
L := new STRING'(bstring3);
checknum := (others => '-');
hread (L, checknum, checkbool);
assert (not checkbool)
report "TEST_STRING: hRead3 unreported error condition"
severity failure;
deallocate (L);
L := new STRING'(bstring3);
checknum := (others => '-');
oread (L, checknum, checkbool);
assert (not checkbool)
report "TEST_STRING: oRead3 unreported error condition"
severity failure;
deallocate (L);
-- L := new string'(bstring3);
-- checknum := (others => '-');
-- dread (L, checknum, checkbool); -- Will read "11" from this string
-- assert (checkbool) report "TEST_STRING: dRead3 reported error condition"
-- severity failure;
-- report_error ("Error in bad decmial Read",
-- to_string(checknum),
-- "000000001011");
-- deallocate (L);
L := new STRING'(bstring3);
checknums := (others => '-');
read (L, checknums, checkbool);
assert (not checkbool)
report "TEST_STRING: Read3 unreported error condition"
severity failure;
deallocate (L);
L := new STRING'(bstring3);
checknums := (others => '-');
hread (L, checknums, checkbool);
assert (not checkbool)
report "TEST_STRING: hRead3 unreported error condition"
severity failure;
deallocate (L);
L := new STRING'(bstring3);
checknums := (others => '-');
oread (L, checknums, checkbool);
assert (not checkbool)
report "TEST_STRING: oRead3 unreported error condition"
severity failure;
deallocate (L);
-- L := new string'(bstring3);
-- checknums := (others => '-');
-- dread (L, checknums, checkbool); -- Will read "11" from this string
-- assert (checkbool) report "TEST_STRING: dRead3 reported error condition"
-- severity failure;
-- report_error ("Error in bad decmial Read",
-- to_string(checknums),
-- "000000001011");
-- deallocate (L);
elsif running_test_case = "Expected to fail: Test HREAD vector truncated error 1" then
checknums2 := (others => '-');
L := new STRING'("8001");
hread (L, checknums2);
deallocate (L);
elsif running_test_case = "Expected to fail: Test HREAD vector truncated error 2" then
checknums2 := (others => '-');
L := new STRING'("2001");
hread (L, checknums2);
deallocate (L);
elsif running_test_case = "Expected to fail: Test OREAD vector truncated error 1" then
L := new STRING'("17005");
oread (L, checknums2);
deallocate (L);
elsif running_test_case = "Expected to fail: Test OREAD vector truncated error 2" then
L := new STRING'("23005");
oread (L, checknums2);
deallocate (L);
end if;
readtest_done <= true;
wait;
end process read_test;
end architecture testbench;
|
-- Project: 12 bits multiplier
-- Author: <NAME>
-- Date: 07/27/2021
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity multiplier_12bits is
port
(
A : in signed(11 downto 0);
B : in signed(11 downto 0);
R : out signed(23 downto 0)
);
end multiplier_12bits;
architecture behavioral of multiplier_12bits is
begin
R <= A * B;
end behavioral;
|
<reponame>yuhanchengo/Logic_Design<gh_stars>0
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity alu IS
PORT(A,B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END alu;
ARCHITECTURE dataflow of alu IS
BEGIN
with S SELECT
Y <= (A+B) WHEN "000",
(A-B) WHEN "001",
A and B WHEN "010",
A or B WHEN "011",
(NOT A) WHEN "100",
A XOR B WHEN "101",
A WHEN others;
END dataflow;
|
<gh_stars>1-10
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity test_dataMemory is
end test_dataMemory;
architecture tb of test_dataMemory is
component dataMemory is port(
clk : in std_logic;
Addr : in std_logic_vector(5 downto 0);
writeD : in std_logic_vector(31 downto 0);
we : in std_logic;
re : in std_logic;
readD : out std_logic_vector(31 downto 0));
end component;
signal clk1 : std_logic;
signal Addr1 : std_logic_vector(5 downto 0);
signal writeD1 : std_logic_vector(31 downto 0);
signal we1 : std_logic;
signal re1 : std_logic;
signal readD1 : std_logic_vector(31 downto 0);
begin
pMap : dataMemory port map(
clk=>clk1, Addr=>Addr1, writeD=>writeD1, we=>we1, re=>re1, readD=>readD1);
process begin
clk1 <= '0'; wait for 50 ps; clk1 <= '1'; wait for 50 ps;
we1 <= '1'; re1 <= '0';
Addr1<="000000"; writeD1 <= "01010101010101010101010101010101";
clk1 <= '0'; wait for 50 ps; clk1 <= '1'; wait for 50 ps;
Addr1<="000001"; writeD1 <= "11011101110111011101110111011101";
clk1 <= '0'; wait for 50 ps; clk1 <= '1'; wait for 50 ps;
Addr1<="000010"; writeD1 <= "00100010001000100010001000100010";
clk1 <= '0'; wait for 50 ps; clk1 <= '1'; wait for 50 ps;
Addr1<="000011"; writeD1 <= "10011001100110011001100110011001";
clk1 <= '0'; wait for 50 ps; clk1 <= '1'; wait for 50 ps;
we1 <= '0'; re1 <= '1';
Addr1 <= "000000";
clk1 <= '0'; wait for 50 ps; clk1 <= '1'; wait for 50 ps;
Addr1 <= "000001";
clk1 <= '0'; wait for 50 ps; clk1 <= '1'; wait for 50 ps;
end process;
end tb;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity ProgramCounter is
Port ( PC_Phase : in STD_LOGIC;
PC_State : in STD_LOGIC_VECTOR (2 downto 0);
PC_Offset : in STD_LOGIC_VECTOR (7 downto 0);
PC_Reset : in STD_LOGIC;
PC_Addr : inout STD_LOGIC_VECTOR (15 downto 0));
end ProgramCounter;
architecture Behavioral of ProgramCounter is
begin
process (PC_Reset, PC_Phase, PC_State)
begin
if PC_Reset = '1' then
PC_Addr <= "0000000000000000";
elsif falling_edge(PC_Phase) and (PC_State = "010" or PC_State = "101") then
PC_Addr <= std_logic_vector(unsigned(PC_Addr) + unsigned(PC_Offset));
end if;
end process;
end Behavioral;
|
<filename>rtl/techmap/bufg/ibuf_inferred.vhd<gh_stars>100-1000
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author <NAME>
--! @brief Input buffer for simulation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ibuf_inferred is
port (
o : out std_logic;
i : in std_logic
);
end;
architecture rtl of ibuf_inferred is
begin
o <= i;
end;
|
<gh_stars>10-100
-------------------------------------------------------------------------------
-- Title : Components package
-- Project : Loa
-------------------------------------------------------------------------------
-- File :
-- Author : strongly-typed
-- Created : 2012-04-10
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 strongyl-typed
-------------------------------------------------------------------------------
-- Revisions :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
package adc_ltc2351_pkg is
-- The LTC2351 is a 14-bit ADC
type adc_ltc2351_values_type is array (natural range <>) of std_logic_vector(13 downto 0);
-- The LTC2351 is configured by port pins, no real SPI
type adc_ltc2351_spi_out_type is record
conv : std_logic;
sck : std_logic;
end record;
-- The LTC2351 outputs it's data on a single pin, no real SPI
type adc_ltc2351_spi_in_type is record
sdo : std_logic;
end record;
-- ---------------------------------------------------------------------------
-- Component declarations
-- ---------------------------------------------------------------------------
component adc_ltc2351
port (
-- signal to and from real hardware
adc_out : out adc_ltc2351_spi_out_type;
adc_in : in adc_ltc2351_spi_in_type;
-- signals to other logic in FPGA
start_p : in std_logic;
values_p : out adc_ltc2351_values_type(5 downto 0);
done_p : out std_logic;
-- clock
clk : in std_logic
);
end component;
component adc_ltc2351_model
port (
sck : in std_logic;
conv : in std_logic;
sdo : out std_logic := 'Z');
end component;
component adc_ltc2351_module
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#);
port (
adc_out_p : out adc_ltc2351_spi_out_type;
adc_in_p : in adc_ltc2351_spi_in_type;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
adc_values_o : out adc_ltc2351_values_type(5 downto 0);
done_p : out std_logic;
clk : in std_logic);
end component;
end adc_ltc2351_pkg;
-------------------------------------------------------------------------------
|
library verilog;
use verilog.vl_types.all;
entity controller_vlg_check_tst is
port(
stack_pop : in vl_logic;
stack_push : in vl_logic;
stack_push_value: in vl_logic_vector(7 downto 0);
sampler_rx : in vl_logic
);
end controller_vlg_check_tst;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.12.2019 22:02:14
-- Design Name:
-- Module Name: Decryption - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decryption is
Port ( ciphertext : in STD_LOGIC_VECTOR (127 downto 0);
key : in STD_LOGIC_VECTOR (127 downto 0);
clk : in STD_LOGIC;
reset :in STD_LOGIC;
run : in STD_LOGIC;
done : out STD_LOGIC;
plaintext : out STD_LOGIC_VECTOR (127 downto 0));
end Decryption;
architecture Behavioral of Decryption is
component pre is
Port ( prein : in STD_LOGIC_VECTOR (127 downto 0);
prekey : in STD_LOGIC_VECTOR (127 downto 0);
preout : out STD_LOGIC_VECTOR (127 downto 0));
end component;
component inv_rounds is
Port ( roundin : in STD_LOGIC_VECTOR (127 downto 0);
keyin : in STD_LOGIC_VECTOR (127 downto 0);
keyout : inout STD_LOGIC_VECTOR (127 downto 0);
rcon : in STD_LOGIC_VECTOR (7 downto 0);
roundout : out STD_LOGIC_VECTOR (127 downto 0));
end component;
component invlastround is
Port ( lastin : in STD_LOGIC_VECTOR (127 downto 0);
lastkey : in STD_LOGIC_VECTOR (127 downto 0);
rcon : in STD_LOGIC_VECTOR (7 downto 0);
plaintext : out STD_LOGIC_VECTOR (127 downto 0));
end component;
--signal i : std_logic_vector (3 downto 0) := "0000";
signal preout, roundout1, roundout2, roundout3, roundout4, roundout5, roundout6, roundout7, roundout8, roundout9, lastout : std_logic_vector (127 downto 0);
signal key1,key2,key3,key4,key5,key6,key7,key8,key9 : std_logic_vector (127 downto 0);
type StateType is (initial, roundpre, firstround, secondround, thirdround, fourthround, fifthround, sixthround, seventhround, eighthround, ninthround, tenthround);
signal currentstate, nextstate : StateType;
begin
preround: pre port map (prein => ciphertext,
prekey => key,
preout => preout);
round1: inv_rounds port map(roundin => preout,
keyin => key,
keyout => key1,
rcon => x"36",
roundout => roundout1);
round2: inv_rounds port map(roundin => roundout1,
keyin => key1,
keyout => key2,
rcon => x"1b",
roundout => roundout2);
round3: inv_rounds port map(roundin => roundout2,
keyin => key2,
keyout => key3,
rcon => x"80",
roundout => roundout3);
round4: inv_rounds port map(roundin => roundout3,
keyin => key3,
keyout => key4,
rcon => x"40",
roundout => roundout4);
round5: inv_rounds port map(roundin => roundout4,
keyin => key4,
keyout => key5,
rcon => x"20",
roundout => roundout5);
round6: inv_rounds port map(roundin => roundout5,
keyin => key5,
keyout => key6,
rcon => x"10",
roundout => roundout6);
round7: inv_rounds port map(roundin => roundout6,
keyin => key6,
keyout => key7,
rcon => x"08",
roundout => roundout7);
round8: inv_rounds port map(roundin => roundout7,
keyin => key7,
keyout => key8,
rcon => x"04",
roundout => roundout8);
round9: inv_rounds port map(roundin => roundout8,
keyin => key8,
keyout => key9,
rcon => x"02",
roundout => roundout9);
round10: invlastround port map(lastin => roundout9,
lastkey => key9,
rcon => x"01",
plaintext => lastout);
memorylogic : process (reset,clk)
--variable i : integer range 0 to 10;
begin
if(reset = '0') then
currentstate <= initial;
elsif (clk'event and clk = '1') then
currentstate <= nextstate;
end if;
end process;
nextstatelogic : process (currentstate, run)
begin
case (currentstate) is
when initial => if(run = '1') then
nextstate <= roundpre;
else
nextstate <= initial;
done <= '0';
end if;
when roundpre => if(run = '1') then
nextstate <= firstround;
else
nextstate <= initial;
done <= '0';
end if;
when firstround => if(run = '1') then
nextstate <= secondround;
else
nextstate <= initial;
done <= '0';
end if;
when secondround => if(run = '1') then
nextstate <= thirdround;
else
nextstate <= initial;
done <= '0';
end if;
when thirdround => if(run = '1') then
nextstate <= fourthround;
else
nextstate <= initial;
done <= '0';
end if;
when fourthround => if(run = '1') then
nextstate <= fifthround;
else
nextstate <= initial;
done <= '0';
end if;
when fifthround => if(run = '1') then
nextstate <= sixthround;
else
nextstate <= initial;
done <= '0';
end if;
when sixthround => if(run = '1') then
nextstate <= seventhround;
else
nextstate <= initial;
done <= '0';
end if;
when seventhround => if(run = '1') then
nextstate <= eighthround;
else
nextstate <= initial;
done <= '0';
end if;
when eighthround => if(run = '1') then
nextstate <= ninthround;
else
nextstate <= initial;
done <= '0';
end if;
when ninthround => if(run = '1') then
nextstate <= tenthround;
else
nextstate <= initial;
done <= '0';
end if;
when tenthround => if(run = '1') then
done <= '1';
else
done <= '0';
end if;
when others => nextstate <= initial;
end case;
end process;
outputlogic : process (currentstate, run)
begin
case (currentstate) is
when initial => plaintext <= ciphertext;
when roundpre => if( run = '1') then
plaintext <= preout;
else
plaintext <= ciphertext;
end if;
when firstround => if( run = '1') then
plaintext <= roundout1;
else
plaintext <= ciphertext;
end if;
when secondround => if( run = '1') then
plaintext <= roundout2;
else
plaintext <= ciphertext;
end if;
when thirdround => if( run = '1') then
plaintext <= roundout3;
else
plaintext <= ciphertext;
end if;
when fourthround => if( run = '1') then
plaintext <= roundout4;
else
plaintext <= ciphertext;
end if;
when fifthround => if( run = '1') then
plaintext <= roundout5;
else
plaintext <= ciphertext;
end if;
when sixthround => if( run = '1') then
plaintext <= roundout6;
else
plaintext <= ciphertext;
end if;
when seventhround => if( run = '1') then
plaintext <= roundout7;
else
plaintext <= ciphertext;
end if;
when eighthround => if( run = '1') then
plaintext <= roundout8;
else
plaintext <= ciphertext;
end if;
when ninthround => if( run = '1') then
plaintext <= roundout9;
else
plaintext <= ciphertext;
end if;
when tenthround => if (run = '1') then
plaintext <= lastout;
else
plaintext <= ciphertext;
end if;
when others => plaintext <= ciphertext;
end case;
end process;
end Behavioral;
|
<reponame>katrinamo/vhdl_projects<filename>spi/spi_controller.vhd
-- File: spi_controller.vhd
-- Description: A simple implementation of a SPI controller. Defaults to a 50 MHz input clock and 1 MHz serial clock.
-- While adjustable, please note clock division assumes MHz.
-- Author: <NAME>
-- libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;
entity spi_controller is
generic(
DATA_WIDTH : integer := 8;
CLK_IN_MHZ : integer := 50;
CLK_OUT_MHZ : integer := 1
);
port(
clk : in std_logic;
rst_n : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
miso : in std_logic; -- Master in, slave out
tx_en : in std_logic; -- Start transmission
tx_done : out std_logic; -- signal TX is done
mosi : out std_logic; -- Master out, slave in
cs_n : out std_logic; -- Chip select (active low)
sclk : out std_logic -- Serial clock
);
end entity spi_controller;
architecture behavioral of spi_controller is
-- Clock signals
constant spulse_width : integer := CLK_IN_MHZ / CLK_OUT_MHZ;
signal ctr : integer range 0 to spulse_width/2 - 1;
signal sclk_en : std_logic := '0';
-- TX FSM signals
type tx_state is (TX_IDLE, TX_BIT, TX_END);
signal cur_state : tx_state;
signal bit : integer range 0 to DATA_WIDTH - 1;
begin
-- Simple clock divider. Generates a 50% duty cycle clock.
sclk_gen : process(clk, rst_n)
begin
if (rst_n = '0') then
sclk <= '0';
elsif rising_edge(clk)then
if (sclk_en = '1') then
if (ctr = spulse_width/2 - 1) then
sclk <= not sclk;
ctr <= 0;
else
ctr <= ctr+1;
end if;
end if;
end if;
end process sclk_gen;
spi_proc : process(clk, rst_n, sclk)
begin
if (rst_n = '0') then
mosi <= '0';
sclk_en <= '0';
cur_state <= TX_IDLE;
bit <= DATA_WIDTH-1;
elsif(rising_edge(clk) or falling_edge(sclk)) then
case cur_state is
-- If we receive an enable, start transmission
when TX_IDLE =>
tx_done <= '0';
if (tx_en = '1') then
sclk_en <= '1';
cur_state <= TX_BIT;
else
sclk_en <= '0';
cur_state <= TX_IDLE;
end if;
-- Send all bits
when TX_BIT =>
mosi <= data(bit);
if (falling_edge(sclk)) and (bit > 0) then
cur_state <= TX_BIT;
bit <= bit-1;
elsif (falling_edge(sclk)) and (bit = 0) then
cur_state <= TX_END;
bit <= DATA_WIDTH-1;
else
cur_state <= TX_BIT;
end if;
-- Hold last bit and then go to idle
when TX_END =>
if (ctr = spulse_width/4 - 1) then
sclk_en <= '0';
tx_done <= '1';
cur_state <= TX_IDLE;
else
cur_state <= TX_END;
end if;
end case;
end if;
end process spi_proc;
-- Just do chip 1 for now
cs_n <= '1';
end architecture behavioral;
|
ENTITY comparator IS
PORT (
a, b: IN BIT;
s: OUT BIT_VECTOR(2 downto 0)
);
END comparator;
ARCHITECTURE structural OF comparator IS
BEGIN
s(0) <= ((a AND b) or (NOT a AND NOT b));
s(1) <= (a AND NOT b);
s(2) <= (NOT a AND b);
END structural;
|
<reponame>hibagus/64pointFFTProcessor<filename>VHDL/dff_segment_for_output.vhd<gh_stars>1-10
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY dff_segment_for_output IS
PORT (
D7 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
D1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
clk : IN STD_LOGIC;
hold : IN STD_LOGIC;
in_sel : IN STD_LOGIC;
rst : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END dff_segment_for_output;
ARCHITECTURE structural of dff_segment_for_output IS
COMPONENT dff_with_hold_32b IS
PORT (
D : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
clk : IN STD_LOGIC;
hold : IN STD_LOGIC;
rst : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT dff_with_hold_input_ctrl IS
PORT (
D1 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
D2 : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
clk : IN STD_LOGIC;
hold : IN STD_LOGIC;
in_sel : IN STD_LOGIC;
rst : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
SIGNAL DFF_0_OUT: STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL DFF_1_OUT: STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL DFF_2_OUT: STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL DFF_3_OUT: STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL DFF_4_OUT: STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL DFF_5_OUT: STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL DFF_6_OUT: STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL DFF_7_OUT: STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
Q <= DFF_0_OUT;
-- Port Map
DFF_7 :
dff_with_hold_32b
PORT MAP (
D =>D7,
clk =>clk,
hold=>hold,
rst =>rst,
Q =>DFF_7_OUT
);
DFF_6 :
dff_with_hold_32b
PORT MAP (
D =>DFF_7_OUT,
clk =>clk,
hold=>hold,
rst =>rst,
Q =>DFF_6_OUT
);
DFF_5 :
dff_with_hold_32b
PORT MAP (
D =>DFF_6_OUT,
clk =>clk,
hold=>hold,
rst =>rst,
Q =>DFF_5_OUT
);
DFF_4 :
dff_with_hold_32b
PORT MAP (
D =>DFF_5_OUT,
clk =>clk,
hold=>hold,
rst =>rst,
Q =>DFF_4_OUT
);
DFF_3 :
dff_with_hold_32b
PORT MAP (
D =>DFF_4_OUT,
clk =>clk,
hold=>hold,
rst =>rst,
Q =>DFF_3_OUT
);
DFF_2 :
dff_with_hold_32b
PORT MAP (
D =>DFF_3_OUT,
clk =>clk,
hold=>hold,
rst =>rst,
Q =>DFF_2_OUT
);
DFF_1 :
dff_with_hold_32b
PORT MAP (
D =>DFF_2_OUT,
clk =>clk,
hold=>hold,
rst =>rst,
Q =>DFF_1_OUT
);
DFF_0 :
dff_with_hold_input_ctrl
PORT MAP (
D1 =>DFF_1_OUT,
D2 =>D1,
clk =>clk,
hold =>hold,
in_sel=>in_sel,
rst =>rst,
Q =>DFF_0_OUT
);
END structural;
|
<reponame>nallen01/phd-thesis-benchmarks<filename>haml-benchmarks/vhdl/nuclear_plant/NuclearPlantNetwork/plant.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.config.all;
use work.lib.all;
-- Entity
entity Plant is
port (
clk : in std_logic;
-- Declare Inputs
add1_in : in boolean;
remove1_in : in boolean;
add2_in : in boolean;
remove2_in : in boolean;
-- Declare Outputs
x_out : out signed(31 downto 0)
);
end;
-- Architecture
architecture behavior of Plant is
-- States
type PLANT_STATE is (
PLANT_P1,
PLANT_P2,
PLANT_P3
);
-- Declare State
signal state : PLANT_STATE := PLANT_P1;
-- Declare Outputs
signal x : signed(31 downto 0) := CREATE_FP(510.0);
begin
process(clk)
-- State Variable
variable state_update : PLANT_STATE := PLANT_P1;
-- Outputs
variable x_update : signed(31 downto 0) := CREATE_FP(510.0);
begin
if clk'event and clk = '1' then
-- Run the state machine for transition logic
if state = PLANT_P1 then -- Logic for state p1
if add1_in then
-- Perform Update Operations
x_update := CREATE_FP(550.0);
-- Next state is p2
state_update := PLANT_P2;
elsif add2_in then
-- Perform Update Operations
x_update := CREATE_FP(550.0);
-- Next state is p3
state_update := PLANT_P3;
elsif not add1_in and not add2_in then
-- Perform Flow Operations
x_update := x + FP_MULT((FP_MULT(CREATE_FP(0.1), x) - CREATE_FP(50.0)), step_size);
end if;
elsif state = PLANT_P2 then -- Logic for state p2
if remove1_in then
-- Perform Update Operations
x_update := CREATE_FP(510.0);
-- Next state is p1
state_update := PLANT_P1;
elsif not remove1_in then
-- Perform Flow Operations
x_update := x + FP_MULT((FP_MULT(CREATE_FP(0.1), x) - CREATE_FP(56.0)), step_size);
end if;
elsif state = PLANT_P3 then -- Logic for state p3
if remove2_in then
-- Perform Update Operations
x_update := CREATE_FP(510.0);
-- Next state is p1
state_update := PLANT_P1;
elsif not remove2_in then
-- Perform Flow Operations
x_update := x + FP_MULT((FP_MULT(CREATE_FP(0.1), x) - CREATE_FP(60.0)), step_size);
end if;
end if;
-- Map State
state <= state_update;
-- Map Outputs
x_out <= x_update;
x <= x_update;
end if;
end process;
end architecture;
|
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<filename>boards/Pynq-Z1/base/one_wire_ip/build/vhdl/mission_control.vhd
-------------------------------------------------------------------------------
-- Title : 1 Wire Master with simple bus interface
-- Project :
-------------------------------------------------------------------------------
-- File : mission_control.vhd
-- Author : <NAME>
-- Company :
-- Created : 2015-08-03
-- Last update: 2015-09-17
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: This module handles;
-- Control/Status Registers,
-- Simple user bus interface,
-- state machine to kick off sub_commands EG. Search Rom,
-- Read Data block, Write Data block etc
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-07-21 1.0 <NAME> Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.ALL;
use work.zpack.all;
entity mission_control is
port
(
i_clk_ui : in std_logic ; -- user interface clock
i_rst : in std_logic ;
i_1wdata : in std_logic ; -- 1wire data input
i32_ui_addr : in std_logic_vector(31 downto 0) ;
i32_ui_idata : in std_logic_vector(31 downto 0) ;
i_wen_ui_wrreg : in std_logic ;
i_ren_ui_wrreg : in std_logic ;
i_ren_ui_rdreg : in std_logic ;
ia_ui_rdreg : in ui_rdreg_type ;
i_rdblk_done : in std_logic ;
i_rst_done : in std_logic ;
i_srchmem_err : in std_logic ;
i_search_err : in std_logic ;
i8_roms_found : in std_logic_vector(7 downto 0) ;
i_search_done : in std_logic ;
i_wrblk_done : in std_logic ;
i_pre : in std_logic ;
i_crce : in std_logic ;
i_1w_int : in std_logic ;
o_cmd : out std_logic := '0' ;
o_rdblk : out std_logic := '0' ;
o_rst : out std_logic := '0' ;
o_search : out std_logic := '0' ;
o_wrblk : out std_logic := '0' ;
o32_ui_odata : out std_logic_vector(31 downto 0) ;
oa_ui_wrreg : out ui_wrreg_type
);
end mission_control;
architecture rtl of mission_control is
signal s_rst : std_logic := '0';
signal sa_ui_rdreg : ui_rdreg_type := (others => (others => '0'));
signal sa_ui_wrreg : ui_wrreg_type := (others => (others => '0'));
type FSMMC_state is (MC_IDLE, MC_SEARCH, MC_CMD, MC_WRBLK, MC_RDBLK, MC_RST, MC_DONE);
signal mcfsm_state : FSMMC_state;
begin
U_local_reset: local_reset
port map
(
i_clk => i_clk_ui,
i_rst => i_rst,
o_rst => s_rst
);
oa_ui_wrreg <= sa_ui_wrreg;
sa_ui_rdreg(c_uir_rd_data0) <= ia_ui_rdreg(c_uir_rd_data0);
sa_ui_rdreg(c_uir_rd_data1) <= ia_ui_rdreg(c_uir_rd_data1);
sa_ui_rdreg(c_uir_rd_data2) <= ia_ui_rdreg(c_uir_rd_data2);
sa_ui_rdreg(c_uir_rd_data3) <= ia_ui_rdreg(c_uir_rd_data3);
o32_ui_odata <= sa_ui_wrreg(to_integer(unsigned(i32_ui_addr))) when (i_ren_ui_wrreg = '1') else sa_ui_rdreg(to_integer(unsigned(i32_ui_addr)));
user_i: process (i_clk_ui)
begin
if rising_edge(i_clk_ui) then
if (s_rst = '1') then
mcfsm_state <= MC_IDLE;
sa_ui_wrreg <= (others => (others => '0')); -- zero control registers
else
if (i_wen_ui_wrreg = '1') then
if (mcfsm_state = MC_IDLE) then
sa_ui_wrreg(to_integer(unsigned(i32_ui_addr))) <= i32_ui_idata;
end if;
end if;
if ((i_ren_ui_rdreg = '1') and (to_integer(unsigned(i32_ui_addr)) = c_uir_status)) then
sa_ui_rdreg(c_uir_status)(30 downto 0) <= (others => '0'); -- clear status flags on read status reg
end if;
case mcfsm_state is
when MC_IDLE =>
if (sa_ui_wrreg(c_uir_control)(c_uir_rst) = '1') then
o_rst <= '1';
sa_ui_rdreg(c_uir_status)(c_uir_busy) <= '1';
mcfsm_state <= MC_RST;
else
o_rst <= '0';
if (sa_ui_wrreg(c_uir_control)(c_uir_srb) = '1') then -- if search rom or search alarm
o_search <= '1';
sa_ui_rdreg(c_uir_status)(c_uir_busy) <= '1';
mcfsm_state <= MC_SEARCH;
else
o_search <= '0';
if (sa_ui_wrreg(c_uir_control)(c_uir_cmden) = '1') then
o_cmd <= '1';
sa_ui_rdreg(c_uir_status)(c_uir_busy) <= '1';
mcfsm_state <= MC_CMD;
else
o_cmd <= '0';
if (sa_ui_wrreg(c_uir_control)(c_uir_wren) = '1') then
o_wrblk <= '1';
sa_ui_rdreg(c_uir_status)(c_uir_busy) <= '1';
mcfsm_state <= MC_WRBLK;
else
o_wrblk <= '0';
if (sa_ui_wrreg(c_uir_control)(c_uir_rden) = '1') then
o_rdblk <= '1';
sa_ui_rdreg(c_uir_status)(c_uir_busy) <= '1';
mcfsm_state <= MC_RDBLK;
else
o_rdblk <= '0';
sa_ui_rdreg(c_uir_status)(c_uir_busy) <= '0'; -- reset status reg busy bit
end if;
end if;
end if;
end if;
end if;
when MC_RST =>
if (i_rst_done = '1') then
sa_ui_wrreg(c_uir_control)(c_uir_rst) <= '0'; -- 1wire reset comeplete, disable bit
sa_ui_rdreg(c_uir_status)(c_uir_rsd) <= '1'; -- set status flag
mcfsm_state <= MC_DONE;
end if;
when MC_SEARCH =>
if (i_search_done = '1') then
sa_ui_wrreg(c_uir_control)(c_uir_srb) <= '0'; -- 1wire search comeplete, disable bit
sa_ui_rdreg(c_uir_status)(c_uir_srd) <= '1';
mcfsm_state <= MC_DONE;
end if;
if (i_srchmem_err = '1') then
sa_ui_rdreg(c_uir_status)(c_uir_srme) <= '1';
end if;
if (i_search_err = '1') then
sa_ui_rdreg(c_uir_status)(c_uir_srche) <= '1';
end if;
sa_ui_rdreg(c_uir_roms_fnd) <= c32_zeros(31 downto 8) & i8_roms_found;
when MC_CMD =>
if (i_wrblk_done = '1') then
sa_ui_wrreg(c_uir_control)(c_uir_cmden) <= '0'; -- 1wire command sent, disable bit
sa_ui_rdreg(c_uir_status)(c_uir_cmdd) <= '1';
mcfsm_state <= MC_DONE;
end if;
when MC_WRBLK =>
if (i_wrblk_done = '1') then
sa_ui_wrreg(c_uir_control)(c_uir_wren) <= '0'; -- 1wire block written comeplete, disable bit
sa_ui_rdreg(c_uir_status)(c_uir_wrd) <= '1';
mcfsm_state <= MC_DONE;
end if;
when MC_RDBLK =>
if (i_rdblk_done = '1') then
sa_ui_wrreg(c_uir_control)(c_uir_rden) <= '0'; -- 1wire block read comeplete, disable bit
sa_ui_rdreg(c_uir_status)(c_uir_rdd) <= '1';
mcfsm_state <= MC_DONE;
end if;
when MC_DONE =>
o_rst <= '0';
o_search <= '0';
o_cmd <= '0';
o_wrblk <= '0';
o_rdblk <= '0';
if ((i_wrblk_done = '0') and (i_rdblk_done = '0') and (i_search_done = '0') and (i_rst_done = '0')) then
mcfsm_state <= MC_IDLE;
end if;
when others => null;
end case;
end if;
end if;
end process user_i;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library unisim;
use unisim.vcomponents.all;
entity PhaseDetector is
generic (
FLEN_G : natural := 16;
USE_MMCM_G : boolean := true;
DECM_MULT_G : positive := 1;
CLK_PERIOD_G : real -- in ns.
);
port (
pclk : in std_logic_vector(1 downto 0);
clk : in std_logic;
rst : in std_logic;
phas : out signed(FLEN_G - 1 downto 0);
locked : out std_logic
);
end entity PhaseDetector;
architecture rtl of PhaseDetector is
constant USE_IIR_C : boolean := false;
-- fdet = fin * (FBDIV_INT_C*8 + FBDIV_8TH_C)/(ODIV_INT_C*8 + ODIV_8TH_C);
--
-- fdel = fin - fdet = fdet ((8*ODIV_INT_C + ODIV_8TH_C) / (FBDIV_INT_C*8 + FBDIV_8TH_C) - 1)
-- assuming ODIV_INT_C == FBDIV_INT_C
-- fdel = fdet * (ODIV_8TH_C - FBDIV_8TH_C)/(FBDIV_INT_C*8 + FBDIV_8TH_C)
--
-- fdel smallest if | ODIV_8TH_C - FBDIV_8TH_C | = 1
-- ODIV_8TH_C = FBDIV_8TH_C +/- 1
function check(constant l : string; constant x : real) return real is
begin
report l & " " & real'image(x);
return x;
end function check;
function check(constant l : string; constant x : natural) return natural is
begin
report l & " " & integer'image(x);
return x;
end function check;
constant VCO_MAX_C : real := 1.4400; -- GHz
constant FBDIV_REA_C : real := check("FBDIV_REA_C", VCO_MAX_C * CLK_PERIOD_G);
constant FBDIV_INT_C : natural := check("FBDIV_INT_C", natural( floor( FBDIV_REA_C ) ));
constant FBDIV_FRC_C : real := check("FBDIV_FRC_C", FBDIV_REA_C - real(FBDIV_INT_C));
constant FBDIV_8TH_C : natural := check("FBDIV_8TH_C", natural( check("FBDIV_8TH_PRE", floor( 8.0 * FBDIV_FRC_C) ) ));
constant ODIV_INT_C : natural := FBDIV_INT_C;
constant ODIV_8TH_C : natural := FBDIV_8TH_C + 1;
constant MULT_F_C : real := real(FBDIV_INT_C) + 0.125*real(FBDIV_8TH_C);
constant DIV0_F_C : real := real(ODIV_INT_C ) + 0.125*real(ODIV_8TH_C );
constant PHAS_MAX_C : natural := DECM_MULT_G * (8 * FBDIV_INT_C + FBDIV_8TH_C);
function PHAS_BITS_F return natural is
variable l : natural;
begin
-- full range is - PHAS_MAX_C .. + PHAS_MAX_C;
l := natural( floor( log2( real( 2 * PHAS_MAX_C ) ) ) ) + 1;
if ( l < FLEN_G ) then
l := FLEN_G;
end if;
return l;
end function PHAS_BITS_F;
signal pclk_i : std_logic_vector(pclk'range);
signal detclk : std_logic;
signal detclk_i : std_logic;
signal clkfb : std_logic;
signal phas_i : signed(PHAS_BITS_F - 1 downto 0) := (others => '0');
signal det : std_logic;
signal pclk10 : std_logic;
signal pclk10_i : std_logic;
signal pclk_ii : std_logic_vector(pclk'range);
begin
assert false report "DIV_i " & integer'image(ODIV_INT_C)
& " ODIV_f " & integer'image(ODIV_8TH_C)
& " FDIV_f " & integer'image(FBDIV_8TH_C)
severity note;
GEN_FF : for i in pclk'range generate
signal ffp : std_logic_vector(pclk'range) := (others => '0');
signal ffn : std_logic_vector(pclk'range) := (others => '0');
begin
P_FF : process ( pclk(i) ) is
begin
if ( rising_edge( pclk(i) ) ) then
ffp(i) <= not ffp(i);
end if;
if ( falling_edge( pclk(i) ) ) then
ffn(i) <= ffp(i);
end if;
end process P_FF;
pclk_ii(i) <= ffp(i) xor ffn(i);
U_SYNC : entity work.Synchronizer
generic map (
STAGES_G => 3
)
port map (
clk => detclk,
rst => '0',
dataIn => pclk_ii(i),
dataOut => pclk_i(i)
);
end generate GEN_FF;
GEN_MMCM : if ( USE_MMCM_G ) generate
signal vld_wr : std_logic := '0';
signal vld_rd : std_logic;
signal ack_rd : std_logic := '0';
signal ack_wr : std_logic;
signal mbox_wr: signed(phas'range) := (others => '0');
signal mbox_rd: signed(phas'range) := (others => '0');
begin
U_MMCM : MMCME2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW)
-- Artix-7 VCO fmax[MHz]: 1600 (speed -3), 1440 (speed -2), 1200 (speed -1)
CLKFBOUT_MULT_F => MULT_F_C, -- Multiply value for all CLKOUT (2.000-64.000).
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000).
CLKIN1_PERIOD => CLK_PERIOD_G, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT1_DIVIDE => 7,
CLKOUT2_DIVIDE => 7,
CLKOUT3_DIVIDE => 7,
CLKOUT4_DIVIDE => 7,
CLKOUT5_DIVIDE => 7,
CLKOUT6_DIVIDE => 7,
CLKOUT0_DIVIDE_F => DIV0_F_C, -- Divide amount for CLKOUT0 (1.000-128.000).
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT6_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
DIVCLK_DIVIDE => 1, -- Master division value (1-106)
REF_JITTER1 => 0.0, -- Reference input jitter in UI (0.000-0.999).
STARTUP_WAIT => FALSE -- Delays DONE until MMCM is locked (FALSE, TRUE)
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => detclk_i, -- 1-bit output: CLKOUT0
CLKOUT0B => open, -- 1-bit output: Inverted CLKOUT0
CLKOUT1 => open, -- 1-bit output: CLKOUT1
CLKOUT1B => open, -- 1-bit output: Inverted CLKOUT1
CLKOUT2 => open, -- 1-bit output: CLKOUT2
CLKOUT2B => open, -- 1-bit output: Inverted CLKOUT2
CLKOUT3 => open, -- 1-bit output: CLKOUT3
CLKOUT3B => open, -- 1-bit output: Inverted CLKOUT3
CLKOUT4 => open, -- 1-bit output: CLKOUT4
CLKOUT5 => open, -- 1-bit output: CLKOUT5
CLKOUT6 => open, -- 1-bit output: CLKOUT6
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => clkfb, -- 1-bit output: Feedback clock
CLKFBOUTB => open, -- 1-bit output: Inverted CLKFBOUT
-- Status Ports: 1-bit (each) output: MMCM status ports
LOCKED => locked, -- 1-bit output: LOCK
-- Clock Inputs: 1-bit (each) input: Clock input
CLKIN1 => pclk(0), -- 1-bit input: Clock
-- Control Ports: 1-bit (each) input: MMCM control ports
PWRDWN => '0', -- 1-bit input: Power-down
RST => rst, -- 1-bit input: Reset
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => clkfb -- 1-bit input: Feedback clock
);
U_BUF : BUFG
port map (
I => detclk_i,
O => detclk
);
U_SYNC_V : entity work.Synchronizer
generic map (
STAGES_G => 3
)
port map (
clk => clk,
rst => '0',
dataIn => vld_wr,
dataOut => vld_rd
);
U_SYNC_A : entity work.Synchronizer
generic map (
STAGES_G => 3
)
port map (
clk => detclk,
rst => '0',
dataIn => ack_rd,
dataOut => ack_wr
);
P_MBOX_WR : process ( detclk ) is
begin
if ( rising_edge( detclk ) ) then
if ( ack_wr = vld_wr ) then
vld_wr <= not vld_wr;
mbox_wr <= phas_i(phas_i'left downto phas_i'left - mbox_wr'length + 1);
end if;
end if;
end process P_MBOX_WR;
P_MBOX_RD : process ( clk ) is
begin
if ( rising_edge( clk ) ) then
if ( ack_rd /= vld_rd ) then
ack_rd <= not ack_rd;
mbox_rd <= mbox_wr;
end if;
end if;
end process P_MBOX_RD;
phas <= mbox_rd;
end generate GEN_MMCM;
GEN_NO_MMCM : if ( not USE_MMCM_G ) generate
locked <= '1';
detclk <= clk;
phas <= phas_i(phas_i'left downto phas_i'left - phas'length + 1);
end generate GEN_NO_MMCM;
U_SYNC_10 : entity work.Synchronizer
generic map (
STAGES_G => 3
)
port map (
clk => pclk(0),
rst => '0',
dataIn => pclk_ii(1),
dataOut => pclk10_i
);
U_SYNC_P : entity work.Synchronizer
generic map (
STAGES_G => 3
)
port map (
clk => detclk,
rst => '0',
dataIn => pclk10_i,
dataOut => pclk10
);
det <= pclk_i(0) xor pclk_i(1);
G_IIR : if ( USE_IIR_C ) generate
P_FILT : process ( detclk ) is
function PONE_F(constant x : in signed) return signed is
variable v : signed(x'range);
begin
v := (others => '0');
v( v'left ) := '0';
v( v'left - 1 ) := '1';
return v;
end function PONE_F;
constant PONE : signed(phas_i'range) := PONE_F(phas_i);
constant MONE : signed(phas_i'range) := - PONE;
constant ZERO : signed(phas_i'range) := (others => '0');
constant SHFT : natural := phas_i'length - 13;
begin
if ( rising_edge ( detclk ) ) then
if ( det = '1' ) then
if ( pclk10 = '1' ) then
phas_i <= phas_i + shift_right(PONE - phas_i, SHFT);
else
phas_i <= phas_i + shift_right(MONE - phas_i, SHFT);
end if;
else
phas_i <= phas_i + shift_right(ZERO - phas_i, SHFT);
end if;
end if;
end process P_FILT;
end generate G_IIR;
G_CIC : if ( not USE_IIR_C ) generate
constant DECM_C : natural := PHAS_MAX_C - 1;
signal phas_l : signed(phas_i'range) := (others => '0');
signal phas_a : signed(phas_i'range) := (others => '0');
signal decm : natural range 0 to DECM_C := 0;
begin
P_FILT : process ( detclk ) is
begin
if ( rising_edge ( detclk ) ) then
if ( decm = 0 ) then
phas_l <= phas_a;
phas_i <= phas_a - phas_l;
decm <= DECM_C;
else
decm <= decm - 1;
end if;
if ( det = '1' ) then
if ( pclk10 = '1' ) then
phas_a <= phas_a + 1;
else
phas_a <= phas_a - 1;
end if;
end if;
end if;
end process P_FILT;
end generate G_CIC;
end architecture rtl;
|
<reponame>chenjiec/testing_project
-- NAME: SHIFTER -- shift right and shift left
-- DESC: 32 bits shifter
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity shifter32 is
port(
DIN : in std_logic_vector(31 downto 0);--input
shbits : in std_logic_vector(4 downto 0);--the number of bits to be shifted
dir : in std_logic;--dir=0, left; dir=1, right
sign : in std_logic;
res : out std_logic_vector(31 downto 0)--the output
);
end entity shifter32;
-- architecture rtl of shifter32 is
architecture beh of shifter32 is
begin
SHIFTER_BEHAVE: process (DIN, shbits, dir, sign)
type matrix_masks is array (0 to 3) of std_logic_vector(39 downto 0);
variable masks : matrix_masks; --vectors of masks: mask00, mask08, mask16, mask24
type matrix_res is array (0 to 7) of std_logic_vector(31 downto 0);
variable res_array : matrix_res;
variable resLevelS : std_logic_vector(39 downto 0);
variable intm : integer; -- intermediate variable
variable temp : integer; --will contain the integer form of select number
variable chtemp : unsigned(4 downto 0);
begin
Level_1: --generate masks
if dir = '0' then -- shift left, need generate the mask0, mask 8L, mask16L, mask24L
MASKL_GEN:for i in 0 to 3 loop
intm := 31 - i * 8;
masks(i)(39 downto 39-intm) := DIN(intm downto 0);
masks(i)(39-intm-1 downto 0) := (others => '0');
end loop;
else --shift right, need generate the mask8R, mask16R, mask24R, mask32R
MASKR_GEN:for i in 0 to 3 loop
intm := i*8;
masks(i)(31-intm downto 0) := DIN (31 downto intm);
if sign = '1' then --arithmetic right shift
masks(i)(39 downto 32-intm) := (others => DIN(31));
else --positive number
masks(i)(39 downto 32-intm) := (others => '0');
end if;
end loop;
end if;
Level_2: --generate coarse grains
chtemp := unsigned (shbits(4 downto 0));
temp := to_integer(chtemp(4 downto 3));--to choose the mask we need
resLevelS := masks(temp);
Level_3: --generate fine grains
if dir = '1' then --shift right
for i in 0 to 7 loop
res_array(i) := resLevelS(31+i downto i);
end loop;
else --shift left
for i in 0 to 7 loop
--consider the negated value issue here when doing left shift
res_array(i) := resLevelS(39-i downto 8-i);
end loop;
end if;
temp := to_integer(chtemp(2 downto 0));
res <= res_array(temp);
end process;
end beh;
|
--------------------------------------------------------------------------------
-- Copyright 2017-2018 <NAME>
-- github.com/dominiksalvet/uvod_do_vhdl
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity or_gate_tb is
end or_gate_tb;
architecture or_gate_tb_arch of or_gate_tb is
component or_gate is
port(
a: in std_logic;
b: in std_logic;
y: out std_logic
);
end component;
signal a: std_logic;
signal b: std_logic;
signal y: std_logic;
begin
or_gate_0: or_gate
port map(
a => a,
b => b,
y => y
);
sim: process
begin
a <= '0';
b <= '0';
wait for 10 ns;
a <= '1';
wait for 10 ns;
a <= '0';
b <= '1';
wait for 10 ns;
a <= '1';
wait for 10 ns;
wait;
end process sim;
end or_gate_tb_arch;
|
<gh_stars>0
ARCHITECTURE ar1 OF top IS
-- PIN ASSIGMENT
ATTRIBUTE chip_pin : string;
ATTRIBUTE chip_pin of rb_i : SIGNAL IS "E6"; -- S2_USR_BTN_akt_low
ATTRIBUTE chip_pin of cp_i : SIGNAL IS "H6"; -- CLK_12MHz
ATTRIBUTE chip_pin of cl_i : SIGNAL IS "G12"; -- Digital in -J2/9
ATTRIBUTE chip_pin of s1_i : SIGNAL IS "L12"; -- Digital in -J2/1
ATTRIBUTE chip_pin of s2_i : SIGNAL IS "J12"; -- Digital in -J2/2
ATTRIBUTE chip_pin of s3_i : SIGNAL IS "J13"; -- Digital in -J2/3
ATTRIBUTE chip_pin of rb_o : SIGNAL IS "A8"; -- LED1
ATTRIBUTE chip_pin of sound_o : SIGNAL IS "A9"; -- LED2
ATTRIBUTE chip_pin of sec_o : SIGNAL IS "A11"; -- LED3
ATTRIBUTE chip_pin of grn_o : SIGNAL IS "B10"; -- LED5
ATTRIBUTE chip_pin of red_o : SIGNAL IS "C9"; -- LED6
ATTRIBUTE chip_pin of tled_o : SIGNAL IS "C10"; -- LED7
ATTRIBUTE chip_pin of txd_o : SIGNAL IS "K11"; -- Digital out -J2/4
ATTRIBUTE chip_pin of sdo_o : SIGNAL IS "K12"; -- Digital out -J2/5
ATTRIBUTE chip_pin of sdv_o : SIGNAL IS "J10"; -- Digital out -J2/6
ATTRIBUTE chip_pin of stx_o : SIGNAL IS "H10"; -- Digital out -J2/7
--------------------------------------------------------------------
-- INTERNAL SIGNALS
SIGNAL br_s : std_logic; --- baud rate signal 9600 Hz
SIGNAL sec_s : std_logic; --- 1hz signal
SIGNAL headcount_s : std_logic_vector(5 DOWNTO 0); -- number of people
SIGNAL maxr_s : std_logic; --- max is reached signal
SIGNAL cup_s : std_logic; -- increment counter
SIGNAL cdown_s : std_logic; -- decrement counter
SIGNAL event_s : std_logic_vector(1 DOWNTO 0); -- event vector
SIGNAL detect_s : std_logic; -- submit serial (data valid)
SIGNAL red_s: std_logic;
SIGNAL grn_s: std_logic;
SIGNAL sound_s: std_logic;
SIGNAL txd_s : std_logic;
SIGNAL tled_s : std_logic;
SIGNAL done_s : std_logic; --- from UART, done transmitting
SIGNAL sdo_s : std_logic;
SIGNAL sdv_s : std_logic;
SIGNAL stx_s : std_logic;
SIGNAL finish_s : std_logic; --- from 3 wire interface, finishing transmitting
SIGNAL pls_s : std_logic; -- active pulse
SIGNAL s1_s : std_logic; -- debounced sensor 1 signal
SIGNAL s2_s : std_logic; -- debounced sensor 2 signal
SIGNAL s3_s : std_logic; -- debounced sensor 3 signal
BEGIN
----------------------------------------------------------------
-- debouncers for buttons
db1 : debnc GENERIC MAP (debounce_const)
PORT MAP (cp_i,rb_i,s1_i,s1_s);
db2 : debnc GENERIC MAP (debounce_const)
PORT MAP (cp_i,rb_i,s2_i,s2_s);
db3 : debnc GENERIC MAP (debounce_const)
PORT MAP (cp_i,rb_i,s3_i,s3_s);
----------------------------------------------------------------
-- clock divider for baud and 1 hz signals
top_clock_divider : clock_divider
PORT MAP (cp_i,rb_i,br_s,sec_s);
----------------------------------------------------------------
-- Counting Unit
counting_unit: cu1
PORT MAP (cp_i, rb_i, cl_i, cup_s,cdown_s, headcount_s, maxr_s);
----------------------------------------------------------------
-- Event logger/sensing unit
top_event_logger : event_logger
PORT MAP (cp_i, rb_i, cl_i, s1_s, s2_s, s3_s, done_s, finish_s,maxr_s, cup_s, cdown_s, event_s,detect_s, red_s, grn_s, sound_s);
----------------------------------------------------------------
-- UART
uart : uat
PORT MAP (cp_i, rb_i, detect_s, br_s, headcount_s, event_s, txd_s, tled_s,done_s);
----------------------------------------------------------------
-- 3WireInterface
int : interface
PORT MAP (cp_i, rb_i, br_s, event_s, headcount_s, detect_s, sdo_s, sdv_s, stx_s,finish_s);
----------------------------------------------------------------
-- Toggle for LED
tgl : toggl
PORT MAP (cp_i, rb_i, sec_s,pls_s);
--------------------------------------------------
-- SETTING OUTPUTS
txd_o <= txd_s; -- data transmission
tled_o <= tled_s; -- data transmission indication
sec_o <= pls_s; -- device alive
sdo_o <= sdo_s; -- ic3 interface
sdv_o <= sdv_s; -- ic3 interface
stx_o <= stx_s; -- ic3 interface
red_o <= red_s; -- red LED
grn_o <= grn_s; -- green LED
sound_o <= sound_s;
rb_o <= not rb_i; -- reset indication
END ar1;
|
<reponame>hamsternz/simple-riscv
--###############################################################################
--# ./hdl/cpu/decode/decode_unit.vhd - Instruction decoder
--#
--# Part of the simple-riscv project. A simple three-stage RISC-V compatible CPU.
--#
--# See https://github.com/hamsternz/simple-riscv
--#
--# MIT License
--#
--###############################################################################
--#
--# Copyright (c) 2020 <NAME>
--#
--# Permission is hereby granted, free of charge, to any person obtaining a copy
--# of this software and associated documentation files (the "Software"), to deal
--# in the Software without restriction, including without limitation the rights
--# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--# copies of the Software, and to permit persons to whom the Software is
--# furnished to do so, subject to the following conditions:
--#
--# The above copyright notice and this permission notice shall be included in all
--# copies or substantial portions of the Software.
--#
--# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--# SOFTWARE.
--#
--###############################################################################
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.cpu_constants.ALL;
entity decode_unit is
Port ( clk : in STD_LOGIC;
-- From the exec unit
exec_decode_next : in STD_LOGIC;
exec_m_epc : in STD_LOGIC_VECTOR(31 downto 0);
-- From the interrupt/exception unit
intex_exception_raise : in STD_LOGIC;
intex_exception_cause : in STD_LOGIC_VECTOR (31 downto 0);
intex_exception_vector : in STD_LOGIC_VECTOR (31 downto 0);
-- from the fetch unit
fetch_opcode : in STD_LOGIC_VECTOR (31 downto 0);
fetch_addr : in STD_LOGIC_VECTOR (31 downto 0);
fetch_instr_misaligned : in std_logic;
fetch_except_instr_access : in std_logic;
decode_addr : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
decode_immed : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
decode_reg_a : out STD_LOGIC_VECTOR(4 downto 0) := (others => '0');
decode_select_a : out STD_LOGIC_VECTOR(0 downto 0) := (others => '0');
decode_reg_b : out STD_LOGIC_VECTOR(4 downto 0) := (others => '0');
decode_select_b : out STD_LOGIC_VECTOR(0 downto 0) := (others => '0');
decode_jump_enable : out STD_LOGIC := '0';
decode_pc_mode : out STD_LOGIC_VECTOR(1 downto 0) := "00";
decode_pc_jump_offset : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
decode_loadstore_offset : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
decode_loadstore_enable : out STD_LOGIC := '0';
decode_loadstore_write : out STD_LOGIC := '0';
decode_loadstore_width : out STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
decode_loadstore_ex_mode : out STD_LOGIC_VECTOR(0 downto 0) := "0";
decode_loadstore_ex_width : out STD_LOGIC_VECTOR(1 downto 0) := "00";
decode_alu_enable : out STD_LOGIC := '0';
decode_alu_mode : out STD_LOGIC_VECTOR(2 downto 0) := "000";
decode_csr_enable : out STD_LOGIC := '0';
decode_csr_mode : out STD_LOGIC_VECTOR(2 downto 0) := "000";
decode_csr_reg : out STD_LOGIC_VECTOR(11 downto 0) := (others => '0');
decode_branchtest_enable : out STD_LOGIC := '0';
decode_branchtest_mode : out STD_LOGIC_VECTOR(2 downto 0) := "000";
decode_shift_enable : out STD_LOGIC := '0';
decode_shift_mode : out STD_LOGIC_VECTOR(1 downto 0) := "00";
decode_result_src : out STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
decode_rdest : out STD_LOGIC_VECTOR(4 downto 0) := (others => '0');
decode_m_int_enter : out STD_LOGIC := '0';
decode_m_int_return : out STD_LOGIC := '0';
decode_mcause : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
decode_instr_misaligned : out std_logic := '0';
decode_instr_access : out std_logic := '0';
decode_ecall : out std_logic := '0';
decode_ebreak : out std_logic := '0';
-- To allow interrupts to be forced
decode_force_complete : out STD_LOGIC := '0');
end decode_unit;
architecture Behavioral of decode_unit is
-- decoding the instruction
signal opcode : STD_LOGIC_VECTOR( 6 downto 0);
signal rd : STD_LOGIC_VECTOR( 4 downto 0);
signal rs1 : STD_LOGIC_VECTOR( 4 downto 0);
signal rs2 : STD_LOGIC_VECTOR( 4 downto 0);
signal func3 : STD_LOGIC_VECTOR( 2 downto 0);
signal func7 : STD_LOGIC_VECTOR( 6 downto 0);
signal func12 : STD_LOGIC_VECTOR(11 downto 0);
signal immed_I : STD_LOGIC_VECTOR(31 downto 0);
signal immed_S : STD_LOGIC_VECTOR(31 downto 0);
signal immed_B : STD_LOGIC_VECTOR(31 downto 0);
signal immed_U : STD_LOGIC_VECTOR(31 downto 0);
signal immed_J : STD_LOGIC_VECTOR(31 downto 0);
signal immed_Z : STD_LOGIC_VECTOR(31 downto 0);
signal instr31 : STD_LOGIC_VECTOR(31 downto 0);
-- Exception handling/Interrupts
signal launched_exception : std_logic := '0' ;
begin
with fetch_opcode(31) select instr31 <= x"FFFFFFFF" when '1', x"00000000" when others;
-- Break down the R, I, S, B, U. J-type instructions, as per ISA
opcode <= fetch_opcode( 6 downto 0);
rd <= fetch_opcode(11 downto 7);
func3 <= fetch_opcode(14 downto 12);
func7 <= fetch_opcode(31 downto 25);
func12 <= fetch_opcode(31 downto 20);
rs1 <= fetch_opcode(19 downto 15);
rs2 <= fetch_opcode(24 downto 20);
immed_I <= instr31(31 downto 12) & fetch_opcode(31 downto 20);
immed_S <= instr31(31 downto 12) & fetch_opcode(31 downto 25) & fetch_opcode(11 downto 7);
immed_B <= instr31(31 downto 12) & fetch_opcode(7) & fetch_opcode(30 downto 25) & fetch_opcode(11 downto 8) & "0";
immed_U <= fetch_opcode(31 downto 12) & x"000";
immed_J <= instr31(31 downto 20) & fetch_opcode(19 downto 12) & fetch_opcode(20) & fetch_opcode(30 downto 21) & "0" ;
immed_Z <= "000000000000000000000000000" & rs1;
process(clk)
begin
if rising_edge(clk) then
if exec_decode_next = '1' then
launched_exception <= '0';
decode_instr_misaligned <= fetch_instr_misaligned;
decode_instr_access <= fetch_except_instr_access;
-- Set defaults for invalid instructions
decode_addr <= fetch_addr;
decode_immed <= immed_I;
decode_force_complete <= '0';
decode_csr_enable <= '0';
decode_alu_enable <= '0';
decode_jump_enable <= '0';
decode_shift_enable <= '0';
decode_branchtest_enable <= '0';
decode_ecall <= '0';
decode_ebreak <= '0';
decode_reg_a <= rs1;
decode_select_a <= A_BUS_REGISTER;
decode_reg_b <= rs2;
decode_select_b <= B_BUS_REGISTER;
decode_pc_mode <= PC_JMP_RELATIVE_CONDITIONAL;
decode_branchtest_mode <= func3;
decode_branchtest_enable <= '0';
decode_pc_jump_offset <= immed_B;
if opcode(5) = '1' then
decode_loadstore_offset <= immed_S;
else
decode_loadstore_offset <= immed_I;
end if;
decode_alu_mode <= ALU_ADD; -- Adds are used for memory addressing when minimal size is built
decode_csr_mode <= CSR_NOACTION;
decode_csr_reg <= func12;
decode_shift_mode <= SHIFTER_LEFT_LOGICAL;
decode_result_src <= RESULT_ALU;
decode_rdest <= "00000"; -- By default write to register zero (which stays zero)
decode_m_int_enter <= '0';
decode_m_int_return <= '0';
decode_mcause <= (others => '0');
decode_loadstore_width <= func3(1 downto 0);
decode_loadstore_write <= '0';
decode_loadstore_enable <= '0';
decode_loadstore_ex_width <= SIGN_EX_WIDTH_W;
decode_loadstore_ex_mode <= SIGN_EX_UNSIGNED;
case opcode is
----------------- LUI --------------------
when "0110111" =>
decode_alu_enable <= '1';
decode_immed <= immed_U;
decode_reg_a <= "00000";
decode_select_b <= B_BUS_IMMEDIATE;
decode_alu_mode <= ALU_OR;
decode_rdest <= rd;
----------------- AUIPC-------------------
when "0010111" =>
decode_alu_enable <= '1';
decode_immed <= immed_U;
decode_select_a <= A_BUS_PC;
decode_select_b <= B_BUS_IMMEDIATE;
decode_alu_mode <= ALU_ADD;
decode_rdest <= rd;
----------------- JAL -------------------
when "1101111" =>
decode_jump_enable <= '1';
decode_pc_jump_offset <= immed_J;
decode_result_src <= RESULT_PC_PLUS_4;
decode_rdest <= rd;
decode_pc_mode <= PC_JMP_RELATIVE;
----------------- JALR -------------------
when "1100111" =>
if func3 = "000" then
decode_jump_enable <= '1';
decode_pc_jump_offset <= immed_I;
decode_select_b <= B_BUS_IMMEDIATE;
decode_result_src <= RESULT_PC_PLUS_4;
decode_rdest <= rd;
decode_pc_mode <= PC_JMP_REG_RELATIVE;
end if;
----------------- BEQ, BNE, BLT, BGE, BLTU, BGEU -------------------
when "1100011" =>
case func3 is
when "000" =>
----------------- BEQ -------------------
-- offset and branch condition already set as defaults
decode_branchtest_enable <= '1';
decode_pc_mode <= PC_JMP_RELATIVE_CONDITIONAL;
when "001" =>
----------------- BNE ------------------
-- offsets already set as defaults
decode_branchtest_enable <= '1';
decode_pc_mode <= PC_JMP_RELATIVE_CONDITIONAL;
when "100" =>
----------------- BLT -------------------
-- offsets already set as defaults
decode_branchtest_enable <= '1';
decode_pc_mode <= PC_JMP_RELATIVE_CONDITIONAL;
when "101" =>
----------------- BGE -------------------
-- offsets already set as defaults
decode_branchtest_enable <= '1';
decode_pc_mode <= PC_JMP_RELATIVE_CONDITIONAL;
when "110" =>
----------------- BLTU -------------------
-- offsets already set as defaults
decode_branchtest_enable <= '1';
decode_pc_mode <= PC_JMP_RELATIVE_CONDITIONAL;
when "111" =>
----------------- BGEU -------------------
-- offsets already set as defaults
decode_branchtest_enable <= '1';
decode_pc_mode <= PC_JMP_RELATIVE_CONDITIONAL;
when others => NULL;
-- Undecoded for opcode 1100011
end case;
when "0000011" =>
case func3 is
when "000" =>
------------ LB ------------------
decode_loadstore_enable <= '1';
decode_immed <= immed_I;
decode_loadstore_width <= "00";
decode_loadstore_ex_width <= SIGN_EX_WIDTH_B;
decode_loadstore_ex_mode <= SIGN_EX_SIGNED;
decode_rdest <= rd;
decode_result_src <= RESULT_MEMORY;
when "001" =>
------------ LH ------------------
decode_loadstore_enable <= '1';
decode_immed <= immed_I;
decode_loadstore_width <= "01";
decode_loadstore_ex_width <= SIGN_EX_WIDTH_H;
decode_loadstore_ex_mode <= SIGN_EX_SIGNED;
decode_rdest <= rd;
decode_result_src <= RESULT_MEMORY;
when "010" =>
------------ LW ------------------
decode_loadstore_enable <= '1';
decode_immed <= immed_I;
decode_loadstore_width <= "10";
decode_loadstore_ex_width <= SIGN_EX_WIDTH_W;
decode_loadstore_ex_mode <= SIGN_EX_SIGNED;
decode_rdest <= rd;
decode_result_src <= RESULT_MEMORY;
when "100" =>
------------ LBU ------------------
decode_immed <= immed_I;
decode_loadstore_width <= "00";
decode_loadstore_enable <= '1';
decode_loadstore_ex_width <= SIGN_EX_WIDTH_B;
decode_loadstore_ex_mode <= SIGN_EX_UNSIGNED;
decode_rdest <= rd;
decode_result_src <= RESULT_MEMORY;
when "101" =>
------------ LHU ------------------
decode_immed <= immed_I;
decode_loadstore_width <= "01";
decode_loadstore_enable <= '1';
decode_loadstore_ex_width <= SIGN_EX_WIDTH_H;
decode_loadstore_ex_mode <= SIGN_EX_UNSIGNED;
decode_rdest <= rd;
decode_result_src <= RESULT_MEMORY;
when others => NULL;
-- Undecoded for opcode 0000011
end case;
when "0100011" =>
case func3 is
when "000" =>
------------ SB ------------------
decode_loadstore_enable <= '1';
decode_loadstore_width <= "00";
decode_loadstore_write <= '1';
decode_rdest <= (others => '0');
when "001" =>
------------ SH ------------------
decode_loadstore_enable <= '1';
decode_loadstore_width <= "01";
decode_loadstore_write <= '1';
decode_rdest <= (others => '0');
when "010" =>
------------ SW ------------------
decode_loadstore_enable <= '1';
decode_loadstore_width <= "10";
decode_loadstore_write <= '1';
decode_rdest <= (others => '0');
when others => NULL;
-- Undecoded for opcode 0100011
end case;
when "0010011" =>
decode_immed <= immed_I;
case func3 is
when "000" =>
------------ ADDI ------------------
decode_alu_enable <= '1';
decode_select_b <= B_BUS_IMMEDIATE;
decode_alu_mode <= ALU_ADD;
decode_rdest <= rd;
when "001" =>
case func7 is
when "0000000" =>
------------ SLLI ------------------
decode_shift_enable <= '1';
decode_select_b <= B_BUS_IMMEDIATE;
decode_result_src <= RESULT_SHIFTER;
decode_shift_mode <= SHIFTER_LEFT_LOGICAL;
decode_rdest <= rd;
when others =>
end case;
when "010" =>
------------ SLTI ------------------
decode_alu_enable <= '1';
decode_select_b <= B_BUS_IMMEDIATE;
decode_alu_mode <= ALU_LESS_THAN_SIGNED;
decode_rdest <= rd;
when "011" =>
------------ SLTIU ------------------
decode_alu_enable <= '1';
decode_select_b <= B_BUS_IMMEDIATE;
decode_alu_mode <= ALU_LESS_THAN_UNSIGNED;
decode_rdest <= rd;
when "100" =>
------------ XORI ------------------
decode_alu_enable <= '1';
decode_select_b <= B_BUS_IMMEDIATE;
decode_alu_mode <= ALU_XOR;
decode_rdest <= rd;
when "101" =>
case func7 is
when "0000000" =>
------------ SRLI ------------------
decode_shift_enable <= '1';
decode_select_b <= B_BUS_IMMEDIATE;
decode_result_src <= RESULT_SHIFTER;
decode_shift_mode <= SHIFTER_RIGHT_LOGICAL;
decode_rdest <= rd;
when "0100000" =>
------------ SRAI ------------------
decode_shift_enable <= '1';
decode_select_b <= B_BUS_IMMEDIATE;
decode_result_src <= RESULT_SHIFTER;
decode_shift_mode <= SHIFTER_RIGHT_ARITH;
decode_rdest <= rd;
when others =>
end case;
when "110" =>
------------ ORI ------------------
decode_alu_enable <= '1';
decode_select_b <= B_BUS_IMMEDIATE;
decode_alu_mode <= ALU_OR;
decode_rdest <= rd;
when "111" =>
------------ ANDI ------------------
decode_alu_enable <= '1';
decode_select_b <= B_BUS_IMMEDIATE;
decode_alu_mode <= ALU_AND;
decode_rdest <= rd;
when others => NULL;
-- Undecoded for opcode 0100011
end case;
when "0110011" =>
case func7 is
when "0000000" =>
case func3 is
when "000" =>
------------ ADD ------------------
decode_alu_enable <= '1';
decode_alu_mode <= ALU_ADD;
decode_rdest <= rd;
when "001" =>
------------ SLL ------------------
decode_shift_enable <= '1';
decode_result_src <= RESULT_SHIFTER;
decode_shift_mode <= SHIFTER_LEFT_LOGICAL;
decode_rdest <= rd;
when "010" =>
------------ SLT ------------------
decode_alu_enable <= '1';
decode_alu_mode <= ALU_LESS_THAN_SIGNED;
decode_rdest <= rd;
when "011" =>
------------ SLTU ------------------
decode_alu_enable <= '1';
decode_alu_mode <= ALU_LESS_THAN_UNSIGNED;
decode_rdest <= rd;
when "100" =>
------------ XOR ------------------
decode_alu_enable <= '1';
decode_alu_mode <= ALU_XOR;
decode_rdest <= rd;
when "101" =>
------------ SRL ------------------
decode_shift_enable <= '1';
decode_result_src <= RESULT_SHIFTER;
decode_shift_mode <= SHIFTER_RIGHT_LOGICAL;
decode_rdest <= rd;
when "110" =>
------------ OR ------------------
decode_alu_enable <= '1';
decode_alu_mode <= ALU_OR;
decode_rdest <= rd;
when "111" =>
------------ AND ------------------
decode_alu_enable <= '1';
decode_alu_mode <= ALU_AND;
decode_rdest <= rd;
when others => NULL;
end case;
when "0100000" =>
case func3 is
when "000" =>
------------ SUB ------------------
decode_alu_enable <= '1';
decode_alu_mode <= ALU_SUB;
decode_rdest <= rd;
when "101" =>
------------ SRA ------------------
decode_shift_enable <= '1';
decode_result_src <= RESULT_SHIFTER;
decode_shift_mode <= SHIFTER_RIGHT_ARITH;
decode_rdest <= rd;
when others => NULL;
end case;
when "0001111" =>
case func3 is
when "000" =>
------------ FENCE ------------------
-- TODO
when others => NULL;
-- Undecoded for opcode 0001111
end case;
when others =>
end case;
when "1110011" =>
case func3 is
when "000" =>
if rs1 = "00000" and rd = "00000" then
case fetch_opcode(31 downto 20) is
when "000000000000" =>
------------- ECALL ---------------
decode_ecall <= '1';
when "000000000001" =>
------------- EBREAK --------------
decode_ebreak <= '1';
when "001100000010" =>
------------- MRET --------------
decode_m_int_return <= '1';
decode_jump_enable <= '1';
decode_alu_enable <= '0';
decode_shift_enable <= '0';
decode_branchtest_enable <= '0';
decode_reg_a <= "00000";
decode_reg_b <= "00000";
decode_rdest <= "00000";
decode_select_b <= B_BUS_IMMEDIATE; -- Not sure if needed
decode_pc_mode <= PC_JMP_REG_RELATIVE;
decode_mcause <= intex_exception_cause;
decode_pc_jump_offset <= exec_m_epc;
when others =>
end case;
end if;
when "001" =>
------------ CSRRW -------------------
decode_csr_enable <= '1';
decode_immed <= immed_Z;
decode_result_src <= RESULT_CSR;
decode_rdest <= rd;
if rd = "00000" then
decode_csr_mode <= CSR_WRITE;
else
decode_csr_mode <= CSR_READWRITE;
end if;
when "010" =>
------------ CSRRS -------------------
decode_csr_enable <= '1';
decode_immed <= immed_Z;
decode_result_src <= RESULT_CSR;
decode_rdest <= rd;
if rs1 = "00000" then
if rd = "00000" then
decode_csr_mode <= CSR_NOACTION;
else
decode_csr_mode <= CSR_READ;
end if;
else
if rd = "00000" then
decode_csr_mode <= CSR_WRITESET;
else
decode_csr_mode <= CSR_READWRITESET;
end if;
end if;
when "011" =>
------------ CSRRC -------------------
decode_csr_enable <= '1';
decode_immed <= immed_Z;
decode_result_src <= RESULT_CSR;
decode_rdest <= rd;
if rs1 = "00000" then
if rd = "00000" then
decode_csr_mode <= CSR_NOACTION;
else
decode_csr_mode <= CSR_READ;
end if;
else
if rd = "00000" then
decode_csr_mode <= CSR_WRITECLEAR;
else
decode_csr_mode <= CSR_READWRITECLEAR;
end if;
end if;
when "100" =>
-- Added to reduce logic usage ---
decode_csr_enable <= '0';
decode_csr_mode <= CSR_NOACTION;
decode_immed <= immed_Z;
decode_select_b <= B_BUS_IMMEDIATE;
decode_result_src <= RESULT_CSR;
when "101" =>
------------ CSRRWI -------------------
decode_csr_enable <= '1';
decode_immed <= immed_Z;
decode_select_b <= B_BUS_IMMEDIATE;
decode_result_src <= RESULT_CSR;
decode_rdest <= rd;
if rd = "00000" then
decode_csr_mode <= CSR_WRITE;
else
decode_csr_mode <= CSR_READWRITE;
end if;
when "110" =>
------------ CSRRSI -------------------
decode_csr_enable <= '1';
decode_immed <= immed_Z;
decode_select_b <= B_BUS_IMMEDIATE;
decode_result_src <= RESULT_CSR;
decode_rdest <= rd;
-- rs1 in this context is an immedaite value for the CSR update
if rs1 = "00000" then
if rd = "00000" then
decode_csr_mode <= CSR_NOACTION;
else
decode_csr_mode <= CSR_READ;
end if;
else
if rd = "00000" then
decode_csr_mode <= CSR_WRITESET;
else
decode_csr_mode <= CSR_READWRITESET;
end if;
end if;
when "111" =>
------------ CSRRCI -------------------
decode_csr_enable <= '1';
decode_immed <= immed_Z;
decode_select_b <= B_BUS_IMMEDIATE;
decode_result_src <= RESULT_CSR;
decode_rdest <= rd;
-- rs1 in this context is an immedaite value for the CSR update
if rs1 = "00000" then
if rd = "00000" then
decode_csr_mode <= CSR_NOACTION;
else
decode_csr_mode <= CSR_READ;
end if;
else
if rd = "00000" then
decode_csr_mode <= CSR_WRITECLEAR;
else
decode_csr_mode <= CSR_READWRITECLEAR;
end if;
end if;
when others =>
-- Undecoded for opcode 1110011
end case;
when others =>
-- Undecoded for opcodes
end case;
---- Now override with exceptions, traps or interrupts
if intex_exception_raise = '1' and launched_exception = '0' then
launched_exception <= '1';
decode_force_complete <= '1';
decode_jump_enable <= '1';
decode_alu_enable <= '0';
decode_shift_enable <= '0';
decode_branchtest_enable <= '0';
decode_reg_a <= "00000";
decode_reg_b <= "00000";
decode_rdest <= "00000";
decode_select_b <= B_BUS_IMMEDIATE; -- Not sure if needed
decode_pc_mode <= PC_JMP_REG_RELATIVE;
decode_mcause <= intex_exception_cause;
decode_m_int_enter <= '1';
decode_pc_jump_offset <= intex_exception_vector;
end if;
end if;
end if;
end process;
end Behavioral;
|
<filename>TUL_KCU115/ultraScale_KCU115_HLS_acceleration_vector_mult/IP/PCIe_Bridge_ICAP_complex/ip/PCIe_Bridge_ICAP_complex_pr_decoupler_0_0/prd_PCIe_Bridge_ICAP_complex_pr_decoupler_0_0.vhd
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|
<filename>chapter03/async_counter_tb.vhdl
-- test bench for the solution of exercise 12, chapter 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity async_counter_test_bench is
end entity async_counter_test_bench;
architecture test_counter of async_counter_test_bench is
signal clk, load_en : std_ulogic := '0';
signal data_in, result : natural := 0;
begin
counter_dut : entity work.async_counter(behav)
port map ( clk, data_in, load_en, result );
stimulus : process is
begin
wait for 20 ns;
-- count down 10 times
for i in 0 to 10 loop
clk <= '1'; wait for 10 ns;
clk <= '0'; wait for 10 ns;
end loop;
-- reset asynchronous to 13
load_en <= '1'; data_in <= 13; wait for 10 ns;
load_en <= '0'; wait for 5 ns;
-- count down another 10 times
for i in 0 to 10 loop
clk <= '1'; wait for 10 ns;
clk <= '0'; wait for 10 ns;
end loop;
wait; -- suspend indefinetly
end process stimulus;
end architecture test_counter;
|
<reponame>mkotormus/G3_OrchestraConductorDemo
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
<KEY>
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
<KEY>
`protect key_keyowner = "Synopsys", key_keyname= "<KEY>", key_method = "rsa"
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<KEY>
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<KEY>
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q2vtHnukOxIKfBz8tBl2R0+xNz13uhOOWpazulDa1i3I/MpKRZt1rWA=
`protect end_protected
|
<gh_stars>10-100
--!
--! Copyright 2018 <NAME>, <EMAIL>
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library ambalib;
use ambalib.types_amba.all;
package types_mem is
component srambytes_tech is
generic (
memtech : integer := 0;
abits : integer := 16;
init_file : string := ""
);
port (
clk : in std_logic;
raddr : in std_logic_vector(abits-1 downto 0);
rdata : out std_logic_vector(31 downto 0);
waddr : in std_logic_vector(abits-1 downto 0);
we : in std_logic;
wstrb : in std_logic_vector(3 downto 0);
wdata : in std_logic_vector(31 downto 0)
);
end component;
end;
|
<gh_stars>0
--------------------------------------------------------------------------------------------------
-- Multirate Fir Filter Testbench
--------------------------------------------------------------------------------------------------
-- <NAME> - <EMAIL>
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tb_clockgen_pkg.all;
use work.tb_read_csv_pkg.all;
use work.tb_write_csv_pkg.all;
use work.dsp_pkg.all;
use work.multirate_fir_filter_pkg.all;
--This module is a test-bench for simulating the fir filter
entity tb_multirate_fir_filter is
end tb_multirate_fir_filter;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture sim of tb_multirate_fir_filter is
constant INPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\multirate\mixedsigs.csv";
constant OUTPUT_FILE : string
:= "X:\Education\Masters Thesis\matlab\multirate\interpolated_filtered_sig.csv";
signal rst : std_logic := '0';
signal clk_10ns : std_logic := '0';
signal clk_20ns : std_logic := '0';
signal sig_in : sig := (others => '0');
signal sig_out : sig := (others => '0');
begin
--Instantiate clock generator
clk1 : tb_clockgen
generic map(PERIOD => 10ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_10ns);
clk2 : tb_clockgen
generic map(PERIOD => 20ns,
DUTY_CYCLE => 0.50)
port map( clk => clk_20ns);
--Instantiate file reader
reader : tb_read_csv
generic map(FILENAME => INPUT_FILE)
port map( clk => clk_10ns,
sig(data) => sig_in);
--Unit under test
uut : multirate_fir_filter
generic map(h => LOW_PASS_41)
port map( clk_low => clk_20ns,
clk_high => clk_10ns,
rst => rst,
x => sig_in,
y => sig_out);
--Instantiate a file writer
writer : tb_write_csv
generic map(FILENAME => OUTPUT_FILE)
port map( clk => clk_10ns,
data => std_logic_vector(sig_out));
--Main Process
--TODO: Add a check for end of file, once reached terminate simulation.
main: process
begin
rst <= '1';
wait for 36ns;
rst <= '0';
wait;
end process;
end sim;
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Sun Jul 12 11:55:51 2020
-- Host : GreatAtuin running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mb_design_axis_data_fifo_0_0_sim_netlist.vhdl
-- Design : mb_design_axis_data_fifo_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst is
port (
src_rst : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_rst : out STD_LOGIC
);
attribute DEF_VAL : string;
attribute DEF_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is "1'b0";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is 4;
attribute INIT : string;
attribute INIT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is "0";
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is 1;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is 0;
attribute VERSION : integer;
attribute VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is "TRUE";
attribute xpm_cdc : string;
attribute xpm_cdc of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is "SYNC_RST";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst is
signal syncstages_ff : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[2]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[2]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[2]\ : label is "SYNC_RST";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[3]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[3]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[3]\ : label is "SYNC_RST";
begin
dest_rst <= syncstages_ff(3);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => src_rst,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
\syncstages_ff_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(1),
Q => syncstages_ff(2),
R => '0'
);
\syncstages_ff_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(2),
Q => syncstages_ff(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0\ is
port (
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg\ : out STD_LOGIC;
\FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : out STD_LOGIC;
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\ : out STD_LOGIC;
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\ : in STD_LOGIC_VECTOR ( 14 downto 0 );
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\ : in STD_LOGIC_VECTOR ( 14 downto 0 );
ram_empty_i : in STD_LOGIC;
rd_en : in STD_LOGIC;
\count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
ram_wr_en_i : in STD_LOGIC;
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1\ : in STD_LOGIC;
clr_full : in STD_LOGIC;
\count_value_i_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0\ is
signal \^co\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal \count_value_i[3]_i_2__0_n_0\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__0_n_1\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__0_n_2\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__0_n_3\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__0_n_4\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__0_n_5\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__0_n_6\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__0_n_7\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1__0_n_2\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1__0_n_3\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1__0_n_5\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1__0_n_6\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1__0_n_7\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__0_n_1\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__0_n_2\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__0_n_3\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__0_n_4\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__0_n_5\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__0_n_6\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__0_n_7\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__0_n_1\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__0_n_2\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__0_n_3\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__0_n_4\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__0_n_5\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__0_n_6\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__0_n_7\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_13_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_14_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_15_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_16_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_6_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_8_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_9_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_1\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_2\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_3\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_7_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_7_n_1\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_7_n_2\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_7_n_3\ : STD_LOGIC;
signal going_full1 : STD_LOGIC;
signal \NLW_count_value_i_reg[14]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_count_value_i_reg[14]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
CO(0) <= \^co\(0);
\FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ <= \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\;
Q(14 downto 0) <= \^q\(14 downto 0);
\count_value_i[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAA5455"
)
port map (
I0 => ram_empty_i,
I1 => rd_en,
I2 => \count_value_i_reg[0]_0\(0),
I3 => \count_value_i_reg[0]_0\(1),
I4 => \^q\(0),
O => \count_value_i[3]_i_2__0_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
D => \count_value_i_reg[3]_i_1__0_n_7\,
Q => \^q\(0),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
D => \count_value_i_reg[11]_i_1__0_n_5\,
Q => \^q\(10),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
D => \count_value_i_reg[11]_i_1__0_n_4\,
Q => \^q\(11),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[11]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \count_value_i_reg[7]_i_1__0_n_0\,
CO(3) => \count_value_i_reg[11]_i_1__0_n_0\,
CO(2) => \count_value_i_reg[11]_i_1__0_n_1\,
CO(1) => \count_value_i_reg[11]_i_1__0_n_2\,
CO(0) => \count_value_i_reg[11]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \count_value_i_reg[11]_i_1__0_n_4\,
O(2) => \count_value_i_reg[11]_i_1__0_n_5\,
O(1) => \count_value_i_reg[11]_i_1__0_n_6\,
O(0) => \count_value_i_reg[11]_i_1__0_n_7\,
S(3 downto 0) => \^q\(11 downto 8)
);
\count_value_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
D => \count_value_i_reg[14]_i_1__0_n_7\,
Q => \^q\(12),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
D => \count_value_i_reg[14]_i_1__0_n_6\,
Q => \^q\(13),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
D => \count_value_i_reg[14]_i_1__0_n_5\,
Q => \^q\(14),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[14]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \count_value_i_reg[11]_i_1__0_n_0\,
CO(3 downto 2) => \NLW_count_value_i_reg[14]_i_1__0_CO_UNCONNECTED\(3 downto 2),
CO(1) => \count_value_i_reg[14]_i_1__0_n_2\,
CO(0) => \count_value_i_reg[14]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_count_value_i_reg[14]_i_1__0_O_UNCONNECTED\(3),
O(2) => \count_value_i_reg[14]_i_1__0_n_5\,
O(1) => \count_value_i_reg[14]_i_1__0_n_6\,
O(0) => \count_value_i_reg[14]_i_1__0_n_7\,
S(3) => '0',
S(2 downto 0) => \^q\(14 downto 12)
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
D => \count_value_i_reg[3]_i_1__0_n_6\,
Q => \^q\(1),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
D => \count_value_i_reg[3]_i_1__0_n_5\,
Q => \^q\(2),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
D => \count_value_i_reg[3]_i_1__0_n_4\,
Q => \^q\(3),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[3]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \count_value_i_reg[3]_i_1__0_n_0\,
CO(2) => \count_value_i_reg[3]_i_1__0_n_1\,
CO(1) => \count_value_i_reg[3]_i_1__0_n_2\,
CO(0) => \count_value_i_reg[3]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^q\(0),
O(3) => \count_value_i_reg[3]_i_1__0_n_4\,
O(2) => \count_value_i_reg[3]_i_1__0_n_5\,
O(1) => \count_value_i_reg[3]_i_1__0_n_6\,
O(0) => \count_value_i_reg[3]_i_1__0_n_7\,
S(3 downto 1) => \^q\(3 downto 1),
S(0) => \count_value_i[3]_i_2__0_n_0\
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
D => \count_value_i_reg[7]_i_1__0_n_7\,
Q => \^q\(4),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
D => \count_value_i_reg[7]_i_1__0_n_6\,
Q => \^q\(5),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
D => \count_value_i_reg[7]_i_1__0_n_5\,
Q => \^q\(6),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
D => \count_value_i_reg[7]_i_1__0_n_4\,
Q => \^q\(7),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[7]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \count_value_i_reg[3]_i_1__0_n_0\,
CO(3) => \count_value_i_reg[7]_i_1__0_n_0\,
CO(2) => \count_value_i_reg[7]_i_1__0_n_1\,
CO(1) => \count_value_i_reg[7]_i_1__0_n_2\,
CO(0) => \count_value_i_reg[7]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \count_value_i_reg[7]_i_1__0_n_4\,
O(2) => \count_value_i_reg[7]_i_1__0_n_5\,
O(1) => \count_value_i_reg[7]_i_1__0_n_6\,
O(0) => \count_value_i_reg[7]_i_1__0_n_7\,
S(3 downto 0) => \^q\(7 downto 4)
);
\count_value_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
D => \count_value_i_reg[11]_i_1__0_n_7\,
Q => \^q\(8),
R => \count_value_i_reg[0]_1\(0)
);
\count_value_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
D => \count_value_i_reg[11]_i_1__0_n_6\,
Q => \^q\(9),
R => \count_value_i_reg[0]_1\(0)
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000FFF0088"
)
port map (
I0 => ram_wr_en_i,
I1 => going_full1,
I2 => \^co\(0),
I3 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1\,
I5 => clr_full,
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FABAFBBBFBBBFBBB"
)
port map (
I0 => clr_full,
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1\,
I2 => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\,
I3 => \^co\(0),
I4 => going_full1,
I5 => ram_wr_en_i,
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(6),
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(6),
I2 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(8),
I3 => \^q\(8),
I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(7),
I5 => \^q\(7),
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10_n_0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(3),
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(3),
I2 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(5),
I3 => \^q\(5),
I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(4),
I5 => \^q\(4),
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11_n_0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(0),
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(0),
I2 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(2),
I3 => \^q\(2),
I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(1),
I5 => \^q\(1),
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12_n_0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(9),
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(9),
I2 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(11),
I3 => \^q\(11),
I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(10),
I5 => \^q\(10),
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_13_n_0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(6),
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(6),
I2 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(8),
I3 => \^q\(8),
I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(7),
I5 => \^q\(7),
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_14_n_0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(3),
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(3),
I2 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(5),
I3 => \^q\(5),
I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(4),
I5 => \^q\(4),
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_15_n_0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(0),
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(0),
I2 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(2),
I3 => \^q\(2),
I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(1),
I5 => \^q\(1),
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_16_n_0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(12),
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(12),
I2 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(14),
I3 => \^q\(14),
I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(13),
I5 => \^q\(13),
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_6_n_0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(12),
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(12),
I2 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(14),
I3 => \^q\(14),
I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(13),
I5 => \^q\(13),
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_8_n_0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(9),
I1 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(9),
I2 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(11),
I3 => \^q\(11),
I4 => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(10),
I5 => \^q\(10),
O => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_9_n_0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_0\,
CO(3 downto 1) => \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_CO_UNCONNECTED\(3 downto 1),
CO(0) => \^co\(0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_6_n_0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_7_n_0\,
CO(3 downto 1) => \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_CO_UNCONNECTED\(3 downto 1),
CO(0) => going_full1,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_8_n_0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_0\,
CO(2) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_1\,
CO(1) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_2\,
CO(0) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_5_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_9_n_0\,
S(2) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_10_n_0\,
S(1) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_11_n_0\,
S(0) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_12_n_0\
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_7\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_7_n_0\,
CO(2) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_7_n_1\,
CO(1) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_7_n_2\,
CO(0) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_7_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_7_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_13_n_0\,
S(2) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_14_n_0\,
S(1) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_15_n_0\,
S(0) => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_16_n_0\
);
\gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FD"
)
port map (
I0 => \count_value_i_reg[0]_0\(1),
I1 => \count_value_i_reg[0]_0\(0),
I2 => rd_en,
I3 => ram_empty_i,
O => \^fsm_sequential_gen_fwft.curr_fwft_state_reg[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_0\ is
port (
ram_empty_i0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\gen_pntr_flags_cc.ram_empty_i_reg\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_i : in STD_LOGIC;
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\ : in STD_LOGIC_VECTOR ( 14 downto 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 );
\count_value_i_reg[14]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_0\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal \count_value_i_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1_n_1\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1_n_2\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1_n_3\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1_n_4\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1_n_5\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1_n_6\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1_n_7\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1_n_2\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1_n_3\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1_n_5\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1_n_6\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1_n_7\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \gen_pntr_flags_cc.ram_empty_i_i_4_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.ram_empty_i_i_5_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.ram_empty_i_i_6_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.ram_empty_i_i_7_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.ram_empty_i_i_8_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.ram_empty_i_reg_i_3_n_0\ : STD_LOGIC;
signal \gen_pntr_flags_cc.ram_empty_i_reg_i_3_n_1\ : STD_LOGIC;
signal \gen_pntr_flags_cc.ram_empty_i_reg_i_3_n_2\ : STD_LOGIC;
signal \gen_pntr_flags_cc.ram_empty_i_reg_i_3_n_3\ : STD_LOGIC;
signal going_empty1 : STD_LOGIC;
signal \NLW_count_value_i_reg[14]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_count_value_i_reg[14]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
Q(14 downto 0) <= \^q\(14 downto 0);
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[3]_i_1_n_7\,
Q => \^q\(0),
R => \count_value_i_reg[14]_0\(0)
);
\count_value_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[11]_i_1_n_5\,
Q => \^q\(10),
R => \count_value_i_reg[14]_0\(0)
);
\count_value_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[11]_i_1_n_4\,
Q => \^q\(11),
R => \count_value_i_reg[14]_0\(0)
);
\count_value_i_reg[11]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \count_value_i_reg[7]_i_1_n_0\,
CO(3) => \count_value_i_reg[11]_i_1_n_0\,
CO(2) => \count_value_i_reg[11]_i_1_n_1\,
CO(1) => \count_value_i_reg[11]_i_1_n_2\,
CO(0) => \count_value_i_reg[11]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \count_value_i_reg[11]_i_1_n_4\,
O(2) => \count_value_i_reg[11]_i_1_n_5\,
O(1) => \count_value_i_reg[11]_i_1_n_6\,
O(0) => \count_value_i_reg[11]_i_1_n_7\,
S(3 downto 0) => \^q\(11 downto 8)
);
\count_value_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[14]_i_1_n_7\,
Q => \^q\(12),
R => \count_value_i_reg[14]_0\(0)
);
\count_value_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[14]_i_1_n_6\,
Q => \^q\(13),
R => \count_value_i_reg[14]_0\(0)
);
\count_value_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[14]_i_1_n_5\,
Q => \^q\(14),
R => \count_value_i_reg[14]_0\(0)
);
\count_value_i_reg[14]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \count_value_i_reg[11]_i_1_n_0\,
CO(3 downto 2) => \NLW_count_value_i_reg[14]_i_1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \count_value_i_reg[14]_i_1_n_2\,
CO(0) => \count_value_i_reg[14]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_count_value_i_reg[14]_i_1_O_UNCONNECTED\(3),
O(2) => \count_value_i_reg[14]_i_1_n_5\,
O(1) => \count_value_i_reg[14]_i_1_n_6\,
O(0) => \count_value_i_reg[14]_i_1_n_7\,
S(3) => '0',
S(2 downto 0) => \^q\(14 downto 12)
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[3]_i_1_n_6\,
Q => \^q\(1),
R => \count_value_i_reg[14]_0\(0)
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[3]_i_1_n_5\,
Q => \^q\(2),
R => \count_value_i_reg[14]_0\(0)
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[3]_i_1_n_4\,
Q => \^q\(3),
R => \count_value_i_reg[14]_0\(0)
);
\count_value_i_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \count_value_i_reg[3]_i_1_n_0\,
CO(2) => \count_value_i_reg[3]_i_1_n_1\,
CO(1) => \count_value_i_reg[3]_i_1_n_2\,
CO(0) => \count_value_i_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^q\(0),
O(3) => \count_value_i_reg[3]_i_1_n_4\,
O(2) => \count_value_i_reg[3]_i_1_n_5\,
O(1) => \count_value_i_reg[3]_i_1_n_6\,
O(0) => \count_value_i_reg[3]_i_1_n_7\,
S(3 downto 1) => \^q\(3 downto 1),
S(0) => S(0)
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[7]_i_1_n_7\,
Q => \^q\(4),
R => \count_value_i_reg[14]_0\(0)
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[7]_i_1_n_6\,
Q => \^q\(5),
R => \count_value_i_reg[14]_0\(0)
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[7]_i_1_n_5\,
Q => \^q\(6),
R => \count_value_i_reg[14]_0\(0)
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[7]_i_1_n_4\,
Q => \^q\(7),
R => \count_value_i_reg[14]_0\(0)
);
\count_value_i_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \count_value_i_reg[3]_i_1_n_0\,
CO(3) => \count_value_i_reg[7]_i_1_n_0\,
CO(2) => \count_value_i_reg[7]_i_1_n_1\,
CO(1) => \count_value_i_reg[7]_i_1_n_2\,
CO(0) => \count_value_i_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \count_value_i_reg[7]_i_1_n_4\,
O(2) => \count_value_i_reg[7]_i_1_n_5\,
O(1) => \count_value_i_reg[7]_i_1_n_6\,
O(0) => \count_value_i_reg[7]_i_1_n_7\,
S(3 downto 0) => \^q\(7 downto 4)
);
\count_value_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[11]_i_1_n_7\,
Q => \^q\(8),
R => \count_value_i_reg[14]_0\(0)
);
\count_value_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[11]_i_1_n_6\,
Q => \^q\(9),
R => \count_value_i_reg[14]_0\(0)
);
\gen_pntr_flags_cc.ram_empty_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFF0088"
)
port map (
I0 => \gen_pntr_flags_cc.ram_empty_i_reg\,
I1 => going_empty1,
I2 => CO(0),
I3 => E(0),
I4 => ram_empty_i,
O => ram_empty_i0
);
\gen_pntr_flags_cc.ram_empty_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(12),
I1 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(12),
I2 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(14),
I3 => \^q\(14),
I4 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(13),
I5 => \^q\(13),
O => \gen_pntr_flags_cc.ram_empty_i_i_4_n_0\
);
\gen_pntr_flags_cc.ram_empty_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(9),
I1 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(9),
I2 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(11),
I3 => \^q\(11),
I4 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(10),
I5 => \^q\(10),
O => \gen_pntr_flags_cc.ram_empty_i_i_5_n_0\
);
\gen_pntr_flags_cc.ram_empty_i_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(6),
I1 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(6),
I2 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(8),
I3 => \^q\(8),
I4 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(7),
I5 => \^q\(7),
O => \gen_pntr_flags_cc.ram_empty_i_i_6_n_0\
);
\gen_pntr_flags_cc.ram_empty_i_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(3),
I1 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(3),
I2 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(5),
I3 => \^q\(5),
I4 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(4),
I5 => \^q\(4),
O => \gen_pntr_flags_cc.ram_empty_i_i_7_n_0\
);
\gen_pntr_flags_cc.ram_empty_i_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(0),
I1 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(0),
I2 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(2),
I3 => \^q\(2),
I4 => \gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(1),
I5 => \^q\(1),
O => \gen_pntr_flags_cc.ram_empty_i_i_8_n_0\
);
\gen_pntr_flags_cc.ram_empty_i_reg_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \gen_pntr_flags_cc.ram_empty_i_reg_i_3_n_0\,
CO(3 downto 1) => \NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_CO_UNCONNECTED\(3 downto 1),
CO(0) => going_empty1,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_2_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \gen_pntr_flags_cc.ram_empty_i_i_4_n_0\
);
\gen_pntr_flags_cc.ram_empty_i_reg_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gen_pntr_flags_cc.ram_empty_i_reg_i_3_n_0\,
CO(2) => \gen_pntr_flags_cc.ram_empty_i_reg_i_3_n_1\,
CO(1) => \gen_pntr_flags_cc.ram_empty_i_reg_i_3_n_2\,
CO(0) => \gen_pntr_flags_cc.ram_empty_i_reg_i_3_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gen_pntr_flags_cc.ram_empty_i_reg_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_pntr_flags_cc.ram_empty_i_i_5_n_0\,
S(2) => \gen_pntr_flags_cc.ram_empty_i_i_6_n_0\,
S(1) => \gen_pntr_flags_cc.ram_empty_i_i_7_n_0\,
S(0) => \gen_pntr_flags_cc.ram_empty_i_i_8_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1\ is
port (
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
ram_empty_i : in STD_LOGIC;
rd_en : in STD_LOGIC;
\count_value_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1\ is
signal \^q\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal \count_value_i[3]_i_2__1_n_0\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__1_n_1\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__1_n_2\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__1_n_3\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__1_n_4\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__1_n_5\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__1_n_6\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__1_n_7\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1__1_n_2\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1__1_n_3\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1__1_n_5\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1__1_n_6\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1__1_n_7\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__1_n_1\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__1_n_2\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__1_n_3\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__1_n_4\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__1_n_5\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__1_n_6\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__1_n_7\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__1_n_1\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__1_n_2\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__1_n_3\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__1_n_4\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__1_n_5\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__1_n_6\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__1_n_7\ : STD_LOGIC;
signal \NLW_count_value_i_reg[14]_i_1__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_count_value_i_reg[14]_i_1__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
Q(14 downto 0) <= \^q\(14 downto 0);
\count_value_i[3]_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAA5455"
)
port map (
I0 => ram_empty_i,
I1 => rd_en,
I2 => \count_value_i_reg[3]_0\(0),
I3 => \count_value_i_reg[3]_0\(1),
I4 => \^q\(0),
O => \count_value_i[3]_i_2__1_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[3]_i_1__1_n_7\,
Q => \^q\(0),
S => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[11]_i_1__1_n_5\,
Q => \^q\(10),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[11]_i_1__1_n_4\,
Q => \^q\(11),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[11]_i_1__1\: unisim.vcomponents.CARRY4
port map (
CI => \count_value_i_reg[7]_i_1__1_n_0\,
CO(3) => \count_value_i_reg[11]_i_1__1_n_0\,
CO(2) => \count_value_i_reg[11]_i_1__1_n_1\,
CO(1) => \count_value_i_reg[11]_i_1__1_n_2\,
CO(0) => \count_value_i_reg[11]_i_1__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \count_value_i_reg[11]_i_1__1_n_4\,
O(2) => \count_value_i_reg[11]_i_1__1_n_5\,
O(1) => \count_value_i_reg[11]_i_1__1_n_6\,
O(0) => \count_value_i_reg[11]_i_1__1_n_7\,
S(3 downto 0) => \^q\(11 downto 8)
);
\count_value_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[14]_i_1__1_n_7\,
Q => \^q\(12),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[14]_i_1__1_n_6\,
Q => \^q\(13),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[14]_i_1__1_n_5\,
Q => \^q\(14),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[14]_i_1__1\: unisim.vcomponents.CARRY4
port map (
CI => \count_value_i_reg[11]_i_1__1_n_0\,
CO(3 downto 2) => \NLW_count_value_i_reg[14]_i_1__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \count_value_i_reg[14]_i_1__1_n_2\,
CO(0) => \count_value_i_reg[14]_i_1__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_count_value_i_reg[14]_i_1__1_O_UNCONNECTED\(3),
O(2) => \count_value_i_reg[14]_i_1__1_n_5\,
O(1) => \count_value_i_reg[14]_i_1__1_n_6\,
O(0) => \count_value_i_reg[14]_i_1__1_n_7\,
S(3) => '0',
S(2 downto 0) => \^q\(14 downto 12)
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[3]_i_1__1_n_6\,
Q => \^q\(1),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[3]_i_1__1_n_5\,
Q => \^q\(2),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[3]_i_1__1_n_4\,
Q => \^q\(3),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[3]_i_1__1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \count_value_i_reg[3]_i_1__1_n_0\,
CO(2) => \count_value_i_reg[3]_i_1__1_n_1\,
CO(1) => \count_value_i_reg[3]_i_1__1_n_2\,
CO(0) => \count_value_i_reg[3]_i_1__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^q\(0),
O(3) => \count_value_i_reg[3]_i_1__1_n_4\,
O(2) => \count_value_i_reg[3]_i_1__1_n_5\,
O(1) => \count_value_i_reg[3]_i_1__1_n_6\,
O(0) => \count_value_i_reg[3]_i_1__1_n_7\,
S(3 downto 1) => \^q\(3 downto 1),
S(0) => \count_value_i[3]_i_2__1_n_0\
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[7]_i_1__1_n_7\,
Q => \^q\(4),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[7]_i_1__1_n_6\,
Q => \^q\(5),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[7]_i_1__1_n_5\,
Q => \^q\(6),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[7]_i_1__1_n_4\,
Q => \^q\(7),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[7]_i_1__1\: unisim.vcomponents.CARRY4
port map (
CI => \count_value_i_reg[3]_i_1__1_n_0\,
CO(3) => \count_value_i_reg[7]_i_1__1_n_0\,
CO(2) => \count_value_i_reg[7]_i_1__1_n_1\,
CO(1) => \count_value_i_reg[7]_i_1__1_n_2\,
CO(0) => \count_value_i_reg[7]_i_1__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \count_value_i_reg[7]_i_1__1_n_4\,
O(2) => \count_value_i_reg[7]_i_1__1_n_5\,
O(1) => \count_value_i_reg[7]_i_1__1_n_6\,
O(0) => \count_value_i_reg[7]_i_1__1_n_7\,
S(3 downto 0) => \^q\(7 downto 4)
);
\count_value_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[11]_i_1__1_n_7\,
Q => \^q\(8),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[11]_i_1__1_n_6\,
Q => \^q\(9),
R => \count_value_i_reg[0]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_1\ is
port (
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\count_value_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_1\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_1\ is
signal \^q\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal \count_value_i_reg[11]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__2_n_1\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__2_n_2\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__2_n_3\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__2_n_4\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__2_n_5\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__2_n_6\ : STD_LOGIC;
signal \count_value_i_reg[11]_i_1__2_n_7\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1__2_n_2\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1__2_n_3\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1__2_n_5\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1__2_n_6\ : STD_LOGIC;
signal \count_value_i_reg[14]_i_1__2_n_7\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__2_n_1\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__2_n_2\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__2_n_3\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__2_n_4\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__2_n_5\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__2_n_6\ : STD_LOGIC;
signal \count_value_i_reg[3]_i_1__2_n_7\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__2_n_1\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__2_n_2\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__2_n_3\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__2_n_4\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__2_n_5\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__2_n_6\ : STD_LOGIC;
signal \count_value_i_reg[7]_i_1__2_n_7\ : STD_LOGIC;
signal \NLW_count_value_i_reg[14]_i_1__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_count_value_i_reg[14]_i_1__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
Q(14 downto 0) <= \^q\(14 downto 0);
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[3]_i_1__2_n_7\,
Q => \^q\(0),
S => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[11]_i_1__2_n_5\,
Q => \^q\(10),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[11]_i_1__2_n_4\,
Q => \^q\(11),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[11]_i_1__2\: unisim.vcomponents.CARRY4
port map (
CI => \count_value_i_reg[7]_i_1__2_n_0\,
CO(3) => \count_value_i_reg[11]_i_1__2_n_0\,
CO(2) => \count_value_i_reg[11]_i_1__2_n_1\,
CO(1) => \count_value_i_reg[11]_i_1__2_n_2\,
CO(0) => \count_value_i_reg[11]_i_1__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \count_value_i_reg[11]_i_1__2_n_4\,
O(2) => \count_value_i_reg[11]_i_1__2_n_5\,
O(1) => \count_value_i_reg[11]_i_1__2_n_6\,
O(0) => \count_value_i_reg[11]_i_1__2_n_7\,
S(3 downto 0) => \^q\(11 downto 8)
);
\count_value_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[14]_i_1__2_n_7\,
Q => \^q\(12),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[14]_i_1__2_n_6\,
Q => \^q\(13),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[14]_i_1__2_n_5\,
Q => \^q\(14),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[14]_i_1__2\: unisim.vcomponents.CARRY4
port map (
CI => \count_value_i_reg[11]_i_1__2_n_0\,
CO(3 downto 2) => \NLW_count_value_i_reg[14]_i_1__2_CO_UNCONNECTED\(3 downto 2),
CO(1) => \count_value_i_reg[14]_i_1__2_n_2\,
CO(0) => \count_value_i_reg[14]_i_1__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_count_value_i_reg[14]_i_1__2_O_UNCONNECTED\(3),
O(2) => \count_value_i_reg[14]_i_1__2_n_5\,
O(1) => \count_value_i_reg[14]_i_1__2_n_6\,
O(0) => \count_value_i_reg[14]_i_1__2_n_7\,
S(3) => '0',
S(2 downto 0) => \^q\(14 downto 12)
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[3]_i_1__2_n_6\,
Q => \^q\(1),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[3]_i_1__2_n_5\,
Q => \^q\(2),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[3]_i_1__2_n_4\,
Q => \^q\(3),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[3]_i_1__2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \count_value_i_reg[3]_i_1__2_n_0\,
CO(2) => \count_value_i_reg[3]_i_1__2_n_1\,
CO(1) => \count_value_i_reg[3]_i_1__2_n_2\,
CO(0) => \count_value_i_reg[3]_i_1__2_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^q\(0),
O(3) => \count_value_i_reg[3]_i_1__2_n_4\,
O(2) => \count_value_i_reg[3]_i_1__2_n_5\,
O(1) => \count_value_i_reg[3]_i_1__2_n_6\,
O(0) => \count_value_i_reg[3]_i_1__2_n_7\,
S(3 downto 1) => \^q\(3 downto 1),
S(0) => \count_value_i_reg[3]_0\(0)
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[7]_i_1__2_n_7\,
Q => \^q\(4),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[7]_i_1__2_n_6\,
Q => \^q\(5),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[7]_i_1__2_n_5\,
Q => \^q\(6),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[7]_i_1__2_n_4\,
Q => \^q\(7),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[7]_i_1__2\: unisim.vcomponents.CARRY4
port map (
CI => \count_value_i_reg[3]_i_1__2_n_0\,
CO(3) => \count_value_i_reg[7]_i_1__2_n_0\,
CO(2) => \count_value_i_reg[7]_i_1__2_n_1\,
CO(1) => \count_value_i_reg[7]_i_1__2_n_2\,
CO(0) => \count_value_i_reg[7]_i_1__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \count_value_i_reg[7]_i_1__2_n_4\,
O(2) => \count_value_i_reg[7]_i_1__2_n_5\,
O(1) => \count_value_i_reg[7]_i_1__2_n_6\,
O(0) => \count_value_i_reg[7]_i_1__2_n_7\,
S(3 downto 0) => \^q\(7 downto 4)
);
\count_value_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[11]_i_1__2_n_7\,
Q => \^q\(8),
R => \count_value_i_reg[0]_0\(0)
);
\count_value_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
D => \count_value_i_reg[11]_i_1__2_n_6\,
Q => \^q\(9),
R => \count_value_i_reg[0]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit is
port (
rst_d1 : out STD_LOGIC;
clr_full : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 0 to 0 );
d_out_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
\count_value_i_reg[3]\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
\count_value_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\count_value_i_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit is
signal \^rst_d1\ : STD_LOGIC;
begin
rst_d1 <= \^rst_d1\;
\count_value_i[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0100"
)
port map (
I0 => \^rst_d1\,
I1 => Q(0),
I2 => \count_value_i_reg[3]\,
I3 => wr_en,
I4 => \count_value_i_reg[3]_0\(0),
O => S(0)
);
\count_value_i[3]_i_2__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0100"
)
port map (
I0 => \^rst_d1\,
I1 => Q(0),
I2 => \count_value_i_reg[3]\,
I3 => wr_en,
I4 => \count_value_i_reg[3]_1\(0),
O => d_out_reg_0(0)
);
d_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => Q(0),
Q => \^rst_d1\,
R => '0'
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => rst,
I1 => \^rst_d1\,
I2 => Q(0),
O => clr_full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC;
\count_value_i_reg[14]\ : in STD_LOGIC;
rst_d1 : in STD_LOGIC;
wr_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst is
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_rst_cc.fifo_wr_rst_cc\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_0_in : STD_LOGIC;
signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC;
signal rst_i : STD_LOGIC;
begin
Q(0) <= \^q\(0);
\gen_rst_cc.fifo_wr_rst_cc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_0_in,
I1 => rst,
O => rst_i
);
\gen_rst_cc.fifo_wr_rst_cc_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
Q => \gen_rst_cc.fifo_wr_rst_cc\(0),
S => rst_i
);
\gen_rst_cc.fifo_wr_rst_cc_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \gen_rst_cc.fifo_wr_rst_cc\(0),
Q => \gen_rst_cc.fifo_wr_rst_cc\(1),
S => rst_i
);
\gen_rst_cc.fifo_wr_rst_cc_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \gen_rst_cc.fifo_wr_rst_cc\(1),
Q => \^q\(0),
S => rst_i
);
\gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => wr_en,
I1 => \count_value_i_reg[14]\,
I2 => \^q\(0),
I3 => rst_d1,
O => E(0)
);
\power_on_rst_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
Q => \power_on_rst_reg_n_0_[0]\,
R => '0'
);
\power_on_rst_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \power_on_rst_reg_n_0_[0]\,
Q => p_0_in,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base is
port (
sleep : in STD_LOGIC;
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 43 downto 0 );
injectsbiterra : in STD_LOGIC;
injectdbiterra : in STD_LOGIC;
douta : out STD_LOGIC_VECTOR ( 43 downto 0 );
sbiterra : out STD_LOGIC;
dbiterra : out STD_LOGIC;
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 14 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 43 downto 0 );
injectsbiterrb : in STD_LOGIC;
injectdbiterrb : in STD_LOGIC;
doutb : out STD_LOGIC_VECTOR ( 43 downto 0 );
sbiterrb : out STD_LOGIC;
dbiterrb : out STD_LOGIC
);
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 15;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 15;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 44;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 44;
attribute CASCADE_HEIGHT : integer;
attribute CASCADE_HEIGHT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "";
attribute MEMORY_OPTIMIZATION : string;
attribute MEMORY_OPTIMIZATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "true";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1441792;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 32768;
attribute P_MEMORY_OPT : string;
attribute P_MEMORY_OPT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "yes";
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "auto";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 44;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 44;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 44;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 44;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 44;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 15;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 15;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 15;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 15;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 44;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 44;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 44;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 44;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 2;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 2;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "";
attribute RST_MODE_A : string;
attribute RST_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "SYNC";
attribute RST_MODE_B : string;
attribute RST_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "SYNC";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute USE_EMBEDDED_CONSTRAINT : integer;
attribute USE_EMBEDDED_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute VERSION : integer;
attribute VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 44;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 44;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 2;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 2;
attribute XPM_MODULE : string;
attribute XPM_MODULE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "TRUE";
attribute rsta_loop_iter : integer;
attribute rsta_loop_iter of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 44;
attribute rstb_loop_iter : integer;
attribute rstb_loop_iter of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 44;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base is
signal \<const0>\ : STD_LOGIC;
signal \^doutb\ : STD_LOGIC_VECTOR ( 43 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ : integer;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ : integer;
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 0;
attribute \MEM.PORTA.DATA_MSB\ : integer;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 0;
attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ : integer;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ : integer;
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 0;
attribute \MEM.PORTB.DATA_MSB\ : integer;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 0;
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is "";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 1441792;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 32767;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 0;
attribute ram_addr_begin : integer;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 0;
attribute ram_addr_end : integer;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 32767;
attribute ram_offset : integer;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 0;
attribute ram_slice_begin : integer;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 0;
attribute ram_slice_end : integer;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_0\ : label is 0;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 1;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 1;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 1;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 1;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 1;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 1;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 1;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_1\ : label is 1;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 10;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 10;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 10;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 10;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 10;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 10;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 10;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_10\ : label is 10;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 11;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 11;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 11;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 11;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 11;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 11;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 11;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_11\ : label is 11;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 12;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 12;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 12;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 12;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 12;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 12;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 12;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_12\ : label is 12;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 13;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 13;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 13;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 13;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 13;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 13;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 13;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_13\ : label is 13;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 14;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 14;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 14;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 14;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 14;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 14;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 14;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_14\ : label is 14;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 15;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 15;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 15;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 15;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 15;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 15;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 15;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_15\ : label is 15;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 16;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 16;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 16;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 16;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 16;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 16;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 16;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_16\ : label is 16;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 17;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 17;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 17;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 17;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 17;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 17;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 17;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_17\ : label is 17;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 18;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 18;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 18;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 18;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 18;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 18;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 18;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_18\ : label is 18;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 19;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 19;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 19;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 19;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 19;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 19;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 19;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_19\ : label is 19;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 2;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 2;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 2;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 2;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 2;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 2;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 2;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_2\ : label is 2;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 20;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 20;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 20;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 20;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 20;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 20;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 20;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_20\ : label is 20;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 21;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 21;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 21;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 21;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 21;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 21;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 21;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_21\ : label is 21;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 22;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 22;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 22;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 22;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 22;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 22;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 22;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_22\ : label is 22;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 23;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 23;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 23;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 23;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 23;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 23;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 23;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_23\ : label is 23;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 24;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 24;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 24;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 24;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 24;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 24;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 24;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_24\ : label is 24;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 25;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 25;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 25;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 25;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 25;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 25;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 25;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_25\ : label is 25;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 26;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 26;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 26;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 26;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 26;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 26;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 26;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_26\ : label is 26;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 27;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 27;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 27;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 27;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 27;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 27;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 27;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_27\ : label is 27;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 28;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 28;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 28;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 28;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 28;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 28;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 28;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_28\ : label is 28;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 29;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 29;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 29;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 29;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 29;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 29;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 29;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_29\ : label is 29;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 3;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 3;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 3;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 3;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 3;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 3;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 3;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_3\ : label is 3;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 30;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 30;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 30;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 30;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 30;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 30;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 30;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_30\ : label is 30;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 31;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 31;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 31;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 31;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 31;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 31;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 31;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_31\ : label is 31;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 32;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 32;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 32;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 32;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 32;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 32;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 32;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_32\ : label is 32;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 33;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 33;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 33;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 33;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 33;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 33;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 33;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_33\ : label is 33;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 34;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 34;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 34;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 34;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 34;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 34;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 34;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_34\ : label is 34;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 35;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 35;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 35;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 35;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 35;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 35;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 35;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_35\ : label is 35;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 36;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 36;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 36;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 36;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 36;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 36;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 36;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_36\ : label is 36;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 4;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 4;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 4;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 4;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 4;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 4;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 4;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_4\ : label is 4;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 5;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 5;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 5;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 5;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 5;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 5;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 5;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_5\ : label is 5;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 6;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 6;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 6;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 6;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 6;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 6;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 6;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_6\ : label is 6;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 7;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 7;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 7;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 7;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 7;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 7;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 7;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_7\ : label is 7;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 8;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 8;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 8;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 8;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 8;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 8;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 8;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_8\ : label is 8;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 32767;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is "p0_d1";
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 9;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 9;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 32767;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is "p0_d1";
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 9;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 9;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is "";
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 1441792;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute bram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 0;
attribute bram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 32767;
attribute bram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 9;
attribute bram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 9;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 0;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 32767;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 0;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 9;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg_0_9\ : label is 9;
begin
dbiterra <= \<const0>\;
dbiterrb <= \<const0>\;
douta(43) <= \<const0>\;
douta(42) <= \<const0>\;
douta(41) <= \<const0>\;
douta(40) <= \<const0>\;
douta(39) <= \<const0>\;
douta(38) <= \<const0>\;
douta(37) <= \<const0>\;
douta(36) <= \<const0>\;
douta(35) <= \<const0>\;
douta(34) <= \<const0>\;
douta(33) <= \<const0>\;
douta(32) <= \<const0>\;
douta(31) <= \<const0>\;
douta(30) <= \<const0>\;
douta(29) <= \<const0>\;
douta(28) <= \<const0>\;
douta(27) <= \<const0>\;
douta(26) <= \<const0>\;
douta(25) <= \<const0>\;
douta(24) <= \<const0>\;
douta(23) <= \<const0>\;
douta(22) <= \<const0>\;
douta(21) <= \<const0>\;
douta(20) <= \<const0>\;
douta(19) <= \<const0>\;
douta(18) <= \<const0>\;
douta(17) <= \<const0>\;
douta(16) <= \<const0>\;
douta(15) <= \<const0>\;
douta(14) <= \<const0>\;
douta(13) <= \<const0>\;
douta(12) <= \<const0>\;
douta(11) <= \<const0>\;
douta(10) <= \<const0>\;
douta(9) <= \<const0>\;
douta(8) <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
doutb(43) <= \^doutb\(43);
doutb(42) <= \<const0>\;
doutb(41) <= \<const0>\;
doutb(40) <= \<const0>\;
doutb(39 downto 36) <= \^doutb\(39 downto 36);
doutb(35) <= \<const0>\;
doutb(34) <= \<const0>\;
doutb(33) <= \<const0>\;
doutb(32) <= \<const0>\;
doutb(31 downto 0) <= \^doutb\(31 downto 0);
sbiterra <= \<const0>\;
sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_wr_a.gen_word_narrow.mem_reg_0_0\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(0),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_0_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_1\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(1),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(1),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_1_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_10\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(10),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(10),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_10_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_11\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(11),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(11),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_11_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_12\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(12),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(12),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_12_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_13\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(13),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(13),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_13_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_14\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(14),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(14),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_14_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_15\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(15),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(15),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_15_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_16\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(16),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(16),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_16_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_17\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(17),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(17),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_17_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_18\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(18),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(18),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_18_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_19\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(19),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(19),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_19_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_2\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(2),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(2),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_2_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_20\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(20),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(20),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_20_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_21\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(21),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(21),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_21_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_22\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(22),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(22),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_22_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_23\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(23),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(23),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_23_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_24\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(24),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(24),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_24_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_25\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(25),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(25),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_25_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_26\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(26),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(26),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_26_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_27\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(27),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(27),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_27_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_28\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(28),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(28),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_28_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
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generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(29),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(29),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_29_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_3\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(3),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(3),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_3_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_30\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(30),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(30),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_30_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_31\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(31),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(31),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_31_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_32\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(36),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(36),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_32_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_33\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(37),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(37),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_33_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_34\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(38),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(38),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_34_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_35\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(39),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(39),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_35_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_36\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(43),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(43),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_36_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_4\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(4),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(4),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_4_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_5\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(5),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(5),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_5_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_6\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(6),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(6),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_6_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_7\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(7),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(7),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_7_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_8\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(8),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(8),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_8_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
\gen_wr_a.gen_word_narrow.mem_reg_0_9\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(9),
DIBDI(31 downto 0) => B"00000000000000000000000000000001",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \^doutb\(9),
DOPADOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => wea(0),
ENBWREN => enb,
INJECTDBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
SBITERR => \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_9_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => '1',
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base is
port (
sleep : in STD_LOGIC;
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 43 downto 0 );
full : out STD_LOGIC;
full_n : out STD_LOGIC;
prog_full : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 15 downto 0 );
overflow : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 43 downto 0 );
empty : out STD_LOGIC;
prog_empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 15 downto 0 );
underflow : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
almost_empty : out STD_LOGIC;
data_valid : out STD_LOGIC;
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC
);
attribute CASCADE_HEIGHT : integer;
attribute CASCADE_HEIGHT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute CDC_DEST_SYNC_FF : integer;
attribute CDC_DEST_SYNC_FF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 3;
attribute COMMON_CLOCK : integer;
attribute COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1;
attribute DOUT_RESET_VALUE : string;
attribute DOUT_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "";
attribute ECC_MODE : integer;
attribute ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute ENABLE_ECC : integer;
attribute ENABLE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute EN_ADV_FEATURE : string;
attribute EN_ADV_FEATURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "16'b0001000000000000";
attribute EN_AE : string;
attribute EN_AE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0";
attribute EN_AF : string;
attribute EN_AF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0";
attribute EN_DVLD : string;
attribute EN_DVLD of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1";
attribute EN_OF : string;
attribute EN_OF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0";
attribute EN_PE : string;
attribute EN_PE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0";
attribute EN_PF : string;
attribute EN_PF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0";
attribute EN_RDC : string;
attribute EN_RDC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0";
attribute EN_UF : string;
attribute EN_UF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0";
attribute EN_WACK : string;
attribute EN_WACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0";
attribute EN_WDC : string;
attribute EN_WDC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0";
attribute FG_EQ_ASYM_DOUT : string;
attribute FG_EQ_ASYM_DOUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0";
attribute FIFO_MEMORY_TYPE : integer;
attribute FIFO_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute FIFO_MEM_TYPE : integer;
attribute FIFO_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute FIFO_READ_DEPTH : integer;
attribute FIFO_READ_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 32768;
attribute FIFO_READ_LATENCY : integer;
attribute FIFO_READ_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute FIFO_SIZE : integer;
attribute FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1441792;
attribute FIFO_WRITE_DEPTH : integer;
attribute FIFO_WRITE_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 32768;
attribute FULL_RESET_VALUE : integer;
attribute FULL_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1;
attribute FULL_RST_VAL : string;
attribute FULL_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1";
attribute PE_THRESH_ADJ : integer;
attribute PE_THRESH_ADJ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 3;
attribute PE_THRESH_MAX : integer;
attribute PE_THRESH_MAX of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 32763;
attribute PE_THRESH_MIN : integer;
attribute PE_THRESH_MIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 5;
attribute PF_THRESH_ADJ : integer;
attribute PF_THRESH_ADJ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 9;
attribute PF_THRESH_MAX : integer;
attribute PF_THRESH_MAX of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 32763;
attribute PF_THRESH_MIN : integer;
attribute PF_THRESH_MIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 5;
attribute PROG_EMPTY_THRESH : integer;
attribute PROG_EMPTY_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 5;
attribute PROG_FULL_THRESH : integer;
attribute PROG_FULL_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 11;
attribute RD_DATA_COUNT_WIDTH : integer;
attribute RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 16;
attribute RD_DC_WIDTH_EXT : integer;
attribute RD_DC_WIDTH_EXT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 16;
attribute RD_LATENCY : integer;
attribute RD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 2;
attribute RD_MODE : integer;
attribute RD_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1;
attribute RD_PNTR_WIDTH : integer;
attribute RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 15;
attribute READ_DATA_WIDTH : integer;
attribute READ_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 44;
attribute READ_MODE : integer;
attribute READ_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1;
attribute RELATED_CLOCKS : integer;
attribute RELATED_CLOCKS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute REMOVE_WR_RD_PROT_LOGIC : integer;
attribute REMOVE_WR_RD_PROT_LOGIC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute USE_ADV_FEATURES : integer;
attribute USE_ADV_FEATURES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 825241648;
attribute VERSION : integer;
attribute VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute WIDTH_RATIO : integer;
attribute WIDTH_RATIO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1;
attribute WRITE_DATA_WIDTH : integer;
attribute WRITE_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 44;
attribute WR_DATA_COUNT_WIDTH : integer;
attribute WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 16;
attribute WR_DC_WIDTH_EXT : integer;
attribute WR_DC_WIDTH_EXT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 16;
attribute WR_DEPTH_LOG : integer;
attribute WR_DEPTH_LOG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 15;
attribute WR_PNTR_WIDTH : integer;
attribute WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 15;
attribute WR_RD_RATIO : integer;
attribute WR_RD_RATIO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute WR_WIDTH_LOG : integer;
attribute WR_WIDTH_LOG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 6;
attribute XPM_MODULE : string;
attribute XPM_MODULE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "TRUE";
attribute both_stages_valid : integer;
attribute both_stages_valid of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 3;
attribute invalid : integer;
attribute invalid of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute stage1_valid : integer;
attribute stage1_valid of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 2;
attribute stage2_valid : integer;
attribute stage2_valid of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base is
signal \<const0>\ : STD_LOGIC;
signal clr_full : STD_LOGIC;
signal \count_value_i__0\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal data_valid_fwft1 : STD_LOGIC;
signal \^dout\ : STD_LOGIC_VECTOR ( 43 downto 0 );
signal \gen_fwft.empty_fwft_i_reg_n_0\ : STD_LOGIC;
signal \gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0\ : STD_LOGIC;
signal \gen_fwft.ram_regout_en\ : STD_LOGIC;
signal \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_n_0\ : STD_LOGIC;
signal leaving_empty0 : STD_LOGIC;
signal \next_fwft_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ram_empty_i : STD_LOGIC;
signal ram_empty_i0 : STD_LOGIC;
signal ram_wr_en_i : STD_LOGIC;
signal rd_pntr_ext : STD_LOGIC_VECTOR ( 14 downto 0 );
signal rdp_inst_n_16 : STD_LOGIC;
signal rdp_inst_n_17 : STD_LOGIC;
signal rdp_inst_n_18 : STD_LOGIC;
signal rdpp1_inst_n_0 : STD_LOGIC;
signal rdpp1_inst_n_1 : STD_LOGIC;
signal rdpp1_inst_n_10 : STD_LOGIC;
signal rdpp1_inst_n_11 : STD_LOGIC;
signal rdpp1_inst_n_12 : STD_LOGIC;
signal rdpp1_inst_n_13 : STD_LOGIC;
signal rdpp1_inst_n_14 : STD_LOGIC;
signal rdpp1_inst_n_2 : STD_LOGIC;
signal rdpp1_inst_n_3 : STD_LOGIC;
signal rdpp1_inst_n_4 : STD_LOGIC;
signal rdpp1_inst_n_5 : STD_LOGIC;
signal rdpp1_inst_n_6 : STD_LOGIC;
signal rdpp1_inst_n_7 : STD_LOGIC;
signal rdpp1_inst_n_8 : STD_LOGIC;
signal rdpp1_inst_n_9 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal rst_d1_inst_n_2 : STD_LOGIC;
signal rst_d1_inst_n_3 : STD_LOGIC;
signal wr_pntr_ext : STD_LOGIC_VECTOR ( 14 downto 0 );
signal xpm_fifo_rst_inst_n_1 : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 43 downto 0 );
signal \NLW_gen_sdpram.xpm_memory_base_inst_doutb_UNCONNECTED\ : STD_LOGIC_VECTOR ( 42 downto 32 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair0";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
attribute SOFT_HLUTNM of \gen_fwft.gdvld_fwft.data_valid_fwft_i_1\ : label is "soft_lutpair0";
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 15;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 15;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute \MEM.ADDRESS_SPACE\ : boolean;
attribute \MEM.ADDRESS_SPACE\ of \gen_sdpram.xpm_memory_base_inst\ : label is std.standard.true;
attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer;
attribute \MEM.ADDRESS_SPACE_BEGIN\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 36;
attribute \MEM.ADDRESS_SPACE_END\ : integer;
attribute \MEM.ADDRESS_SPACE_END\ of \gen_sdpram.xpm_memory_base_inst\ : label is 32767;
attribute \MEM.CORE_MEMORY_WIDTH\ : integer;
attribute \MEM.CORE_MEMORY_WIDTH\ of \gen_sdpram.xpm_memory_base_inst\ : label is 37;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is "";
attribute MEMORY_OPTIMIZATION : string;
attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 1441792;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 32768;
attribute P_MEMORY_OPT : string;
attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "auto";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 15;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 15;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 15;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 15;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "";
attribute RST_MODE_A : string;
attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
attribute RST_MODE_B : string;
attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute USE_EMBEDDED_CONSTRAINT : integer;
attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE";
attribute rsta_loop_iter : integer;
attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
attribute rstb_loop_iter : integer;
attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 44;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
dbiterr <= \<const0>\;
dout(43) <= \^dout\(43);
dout(42) <= \<const0>\;
dout(41) <= \<const0>\;
dout(40) <= \<const0>\;
dout(39 downto 36) <= \^dout\(39 downto 36);
dout(35) <= \<const0>\;
dout(34) <= \<const0>\;
dout(33) <= \<const0>\;
dout(32) <= \<const0>\;
dout(31 downto 0) <= \^dout\(31 downto 0);
empty <= \<const0>\;
full <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(15) <= \<const0>\;
rd_data_count(14) <= \<const0>\;
rd_data_count(13) <= \<const0>\;
rd_data_count(12) <= \<const0>\;
rd_data_count(11) <= \<const0>\;
rd_data_count(10) <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(15) <= \<const0>\;
wr_data_count(14) <= \<const0>\;
wr_data_count(13) <= \<const0>\;
wr_data_count(12) <= \<const0>\;
wr_data_count(11) <= \<const0>\;
wr_data_count(10) <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
\FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A85"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => curr_fwft_state(1),
I3 => ram_empty_i,
O => \next_fwft_state__0\(0)
);
\FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7C"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
O => \next_fwft_state__0\(1)
);
\FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \next_fwft_state__0\(0),
Q => curr_fwft_state(0),
R => xpm_fifo_rst_inst_n_1
);
\FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \next_fwft_state__0\(1),
Q => curr_fwft_state(1),
R => xpm_fifo_rst_inst_n_1
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_fwft.empty_fwft_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F380"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(0),
I2 => curr_fwft_state(1),
I3 => \gen_fwft.empty_fwft_i_reg_n_0\,
O => data_valid_fwft1
);
\gen_fwft.empty_fwft_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => data_valid_fwft1,
Q => \gen_fwft.empty_fwft_i_reg_n_0\,
S => xpm_fifo_rst_inst_n_1
);
\gen_fwft.gdvld_fwft.data_valid_fwft_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"3575"
)
port map (
I0 => \gen_fwft.empty_fwft_i_reg_n_0\,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => \gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0\
);
\gen_fwft.gdvld_fwft.data_valid_fwft_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0\,
Q => data_valid,
R => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rdp_inst_n_16,
Q => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_n_0\,
S => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rdp_inst_n_18,
Q => full_n,
R => xpm_fifo_rst_inst_n_1
);
\gen_pntr_flags_cc.ram_empty_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_empty_i0,
Q => ram_empty_i,
S => xpm_fifo_rst_inst_n_1
);
\gen_sdpram.xpm_memory_base_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base
port map (
addra(14 downto 0) => wr_pntr_ext(14 downto 0),
addrb(14 downto 0) => rd_pntr_ext(14 downto 0),
clka => wr_clk,
clkb => '0',
dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\,
dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\,
dina(43) => din(43),
dina(42 downto 40) => B"000",
dina(39 downto 36) => din(39 downto 36),
dina(35 downto 32) => B"0000",
dina(31 downto 0) => din(31 downto 0),
dinb(43 downto 0) => B"00000000000000000000000000000000000000000000",
douta(43 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(43 downto 0),
doutb(43) => \^dout\(43),
doutb(42 downto 40) => \NLW_gen_sdpram.xpm_memory_base_inst_doutb_UNCONNECTED\(42 downto 40),
doutb(39 downto 36) => \^dout\(39 downto 36),
doutb(35 downto 32) => \NLW_gen_sdpram.xpm_memory_base_inst_doutb_UNCONNECTED\(35 downto 32),
doutb(31 downto 0) => \^dout\(31 downto 0),
ena => '0',
enb => rdp_inst_n_17,
injectdbiterra => '0',
injectdbiterrb => '0',
injectsbiterra => '0',
injectsbiterrb => '0',
regcea => '0',
regceb => \gen_fwft.ram_regout_en\,
rsta => '0',
rstb => xpm_fifo_rst_inst_n_1,
sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\,
sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\,
sleep => sleep,
wea(0) => ram_wr_en_i,
web(0) => '0'
);
\gen_sdpram.xpm_memory_base_inst_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"62"
)
port map (
I0 => curr_fwft_state(0),
I1 => curr_fwft_state(1),
I2 => rd_en,
O => \gen_fwft.ram_regout_en\
);
rdp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0\
port map (
CO(0) => leaving_empty0,
\FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ => rdp_inst_n_17,
Q(14 downto 0) => rd_pntr_ext(14 downto 0),
clr_full => clr_full,
\count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
\count_value_i_reg[0]_1\(0) => xpm_fifo_rst_inst_n_1,
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg\ => rdp_inst_n_16,
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_0\ => rdp_inst_n_18,
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_1\ => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_n_0\,
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_3_0\(14 downto 0) => wr_pntr_ext(14 downto 0),
\gen_pntr_flags_cc.gen_full_rst_val.ram_full_n_reg_i_4_0\(14 downto 0) => \count_value_i__0\(14 downto 0),
ram_empty_i => ram_empty_i,
ram_wr_en_i => ram_wr_en_i,
rd_en => rd_en,
wr_clk => wr_clk
);
rdpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1\
port map (
E(0) => rdp_inst_n_17,
Q(14) => rdpp1_inst_n_0,
Q(13) => rdpp1_inst_n_1,
Q(12) => rdpp1_inst_n_2,
Q(11) => rdpp1_inst_n_3,
Q(10) => rdpp1_inst_n_4,
Q(9) => rdpp1_inst_n_5,
Q(8) => rdpp1_inst_n_6,
Q(7) => rdpp1_inst_n_7,
Q(6) => rdpp1_inst_n_8,
Q(5) => rdpp1_inst_n_9,
Q(4) => rdpp1_inst_n_10,
Q(3) => rdpp1_inst_n_11,
Q(2) => rdpp1_inst_n_12,
Q(1) => rdpp1_inst_n_13,
Q(0) => rdpp1_inst_n_14,
\count_value_i_reg[0]_0\(0) => xpm_fifo_rst_inst_n_1,
\count_value_i_reg[3]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
ram_empty_i => ram_empty_i,
rd_en => rd_en,
wr_clk => wr_clk
);
rst_d1_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit
port map (
Q(0) => xpm_fifo_rst_inst_n_1,
S(0) => rst_d1_inst_n_2,
clr_full => clr_full,
\count_value_i_reg[3]\ => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_n_0\,
\count_value_i_reg[3]_0\(0) => wr_pntr_ext(0),
\count_value_i_reg[3]_1\(0) => \count_value_i__0\(0),
d_out_reg_0(0) => rst_d1_inst_n_3,
rst => rst,
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_en => wr_en
);
wrp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_0\
port map (
CO(0) => leaving_empty0,
E(0) => ram_wr_en_i,
Q(14 downto 0) => wr_pntr_ext(14 downto 0),
S(0) => rst_d1_inst_n_2,
\count_value_i_reg[14]_0\(0) => xpm_fifo_rst_inst_n_1,
\gen_pntr_flags_cc.ram_empty_i_reg\ => rdp_inst_n_17,
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(14) => rdpp1_inst_n_0,
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(13) => rdpp1_inst_n_1,
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(12) => rdpp1_inst_n_2,
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(11) => rdpp1_inst_n_3,
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(10) => rdpp1_inst_n_4,
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(9) => rdpp1_inst_n_5,
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(8) => rdpp1_inst_n_6,
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(7) => rdpp1_inst_n_7,
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(6) => rdpp1_inst_n_8,
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(5) => rdpp1_inst_n_9,
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(4) => rdpp1_inst_n_10,
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(3) => rdpp1_inst_n_11,
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(2) => rdpp1_inst_n_12,
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(1) => rdpp1_inst_n_13,
\gen_pntr_flags_cc.ram_empty_i_reg_i_2_0\(0) => rdpp1_inst_n_14,
ram_empty_i => ram_empty_i,
ram_empty_i0 => ram_empty_i0,
wr_clk => wr_clk
);
wrpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_1\
port map (
E(0) => ram_wr_en_i,
Q(14 downto 0) => \count_value_i__0\(14 downto 0),
\count_value_i_reg[0]_0\(0) => xpm_fifo_rst_inst_n_1,
\count_value_i_reg[3]_0\(0) => rst_d1_inst_n_3,
wr_clk => wr_clk
);
xpm_fifo_rst_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst
port map (
E(0) => ram_wr_en_i,
Q(0) => xpm_fifo_rst_inst_n_1,
\count_value_i_reg[14]\ => \gen_pntr_flags_cc.gen_full_rst_val.ram_full_i_reg_n_0\,
rst => rst,
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis is
port (
s_aresetn : in STD_LOGIC;
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
prog_full_axis : out STD_LOGIC;
wr_data_count_axis : out STD_LOGIC_VECTOR ( 15 downto 0 );
almost_full_axis : out STD_LOGIC;
prog_empty_axis : out STD_LOGIC;
rd_data_count_axis : out STD_LOGIC_VECTOR ( 15 downto 0 );
almost_empty_axis : out STD_LOGIC;
injectsbiterr_axis : in STD_LOGIC;
injectdbiterr_axis : in STD_LOGIC;
sbiterr_axis : out STD_LOGIC;
dbiterr_axis : out STD_LOGIC
);
attribute AXIS_DATA_WIDTH : integer;
attribute AXIS_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 44;
attribute AXIS_FINAL_DATA_WIDTH : integer;
attribute AXIS_FINAL_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 44;
attribute CASCADE_HEIGHT : integer;
attribute CASCADE_HEIGHT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 0;
attribute CDC_SYNC_STAGES : integer;
attribute CDC_SYNC_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 3;
attribute CLOCKING_MODE : string;
attribute CLOCKING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is "common_clock";
attribute ECC_MODE : string;
attribute ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is "no_ecc";
attribute EN_ADV_FEATURE_AXIS : string;
attribute EN_ADV_FEATURE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is "16'b0001000000000000";
attribute EN_ADV_FEATURE_AXIS_INT : string;
attribute EN_ADV_FEATURE_AXIS_INT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is "16'b0001000000000000";
attribute EN_ALMOST_EMPTY_INT : string;
attribute EN_ALMOST_EMPTY_INT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is "1'b0";
attribute EN_ALMOST_FULL_INT : string;
attribute EN_ALMOST_FULL_INT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is "1'b0";
attribute EN_DATA_VALID_INT : string;
attribute EN_DATA_VALID_INT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is "1'b1";
attribute FIFO_DEPTH : integer;
attribute FIFO_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 32768;
attribute FIFO_MEMORY_TYPE : string;
attribute FIFO_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is "auto";
attribute LOG_DEPTH_AXIS : integer;
attribute LOG_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 15;
attribute PACKET_FIFO : string;
attribute PACKET_FIFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is "false";
attribute PKT_SIZE_LT8 : string;
attribute PKT_SIZE_LT8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is "1'b0";
attribute PROG_EMPTY_THRESH : integer;
attribute PROG_EMPTY_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 5;
attribute PROG_FULL_THRESH : integer;
attribute PROG_FULL_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 11;
attribute P_COMMON_CLOCK : integer;
attribute P_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 1;
attribute P_ECC_MODE : integer;
attribute P_ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 0;
attribute P_FIFO_MEMORY_TYPE : integer;
attribute P_FIFO_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 0;
attribute P_PKT_MODE : integer;
attribute P_PKT_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 0;
attribute RD_DATA_COUNT_WIDTH : integer;
attribute RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 16;
attribute RELATED_CLOCKS : integer;
attribute RELATED_CLOCKS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 0;
attribute TDATA_OFFSET : integer;
attribute TDATA_OFFSET of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 32;
attribute TDATA_WIDTH : integer;
attribute TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 32;
attribute TDEST_OFFSET : integer;
attribute TDEST_OFFSET of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 42;
attribute TDEST_WIDTH : integer;
attribute TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 1;
attribute TID_OFFSET : integer;
attribute TID_OFFSET of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 41;
attribute TID_WIDTH : integer;
attribute TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 1;
attribute TKEEP_OFFSET : integer;
attribute TKEEP_OFFSET of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 40;
attribute TSTRB_OFFSET : integer;
attribute TSTRB_OFFSET of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 36;
attribute TUSER_MAX_WIDTH : integer;
attribute TUSER_MAX_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 4053;
attribute TUSER_OFFSET : integer;
attribute TUSER_OFFSET of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 43;
attribute TUSER_WIDTH : integer;
attribute TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 1;
attribute USE_ADV_FEATURES : integer;
attribute USE_ADV_FEATURES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 825241648;
attribute USE_ADV_FEATURES_INT : integer;
attribute USE_ADV_FEATURES_INT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 825241648;
attribute WR_DATA_COUNT_WIDTH : integer;
attribute WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is 16;
attribute XPM_MODULE : string;
attribute XPM_MODULE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis : entity is "TRUE";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis is
signal \<const0>\ : STD_LOGIC;
signal \gaxis_rst_sync.xpm_cdc_sync_rst_inst_i_1_n_0\ : STD_LOGIC;
signal \^m_axis_tvalid\ : STD_LOGIC;
signal rst_axis : STD_LOGIC;
signal xpm_fifo_base_inst_i_1_n_0 : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_empty_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_full_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_xpm_fifo_base_inst_dout_UNCONNECTED : STD_LOGIC_VECTOR ( 42 downto 32 );
signal NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute DEF_VAL : string;
attribute DEF_VAL of \gaxis_rst_sync.xpm_cdc_sync_rst_inst\ : label is "1'b0";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \gaxis_rst_sync.xpm_cdc_sync_rst_inst\ : label is 4;
attribute INIT : string;
attribute INIT of \gaxis_rst_sync.xpm_cdc_sync_rst_inst\ : label is "0";
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \gaxis_rst_sync.xpm_cdc_sync_rst_inst\ : label is 1;
attribute SIM_ASSERT_CHK of \gaxis_rst_sync.xpm_cdc_sync_rst_inst\ : label is 0;
attribute VERSION : integer;
attribute VERSION of \gaxis_rst_sync.xpm_cdc_sync_rst_inst\ : label is 0;
attribute XPM_CDC : string;
attribute XPM_CDC of \gaxis_rst_sync.xpm_cdc_sync_rst_inst\ : label is "SYNC_RST";
attribute XPM_MODULE of \gaxis_rst_sync.xpm_cdc_sync_rst_inst\ : label is "TRUE";
attribute CASCADE_HEIGHT of xpm_fifo_base_inst : label is 0;
attribute CDC_DEST_SYNC_FF : integer;
attribute CDC_DEST_SYNC_FF of xpm_fifo_base_inst : label is 3;
attribute COMMON_CLOCK : integer;
attribute COMMON_CLOCK of xpm_fifo_base_inst : label is 1;
attribute DOUT_RESET_VALUE : string;
attribute DOUT_RESET_VALUE of xpm_fifo_base_inst : label is "";
attribute ECC_MODE_integer : integer;
attribute ECC_MODE_integer of xpm_fifo_base_inst : label is 0;
attribute ENABLE_ECC : integer;
attribute ENABLE_ECC of xpm_fifo_base_inst : label is 0;
attribute EN_ADV_FEATURE : string;
attribute EN_ADV_FEATURE of xpm_fifo_base_inst : label is "16'b0001000000000000";
attribute EN_AE : string;
attribute EN_AE of xpm_fifo_base_inst : label is "1'b0";
attribute EN_AF : string;
attribute EN_AF of xpm_fifo_base_inst : label is "1'b0";
attribute EN_DVLD : string;
attribute EN_DVLD of xpm_fifo_base_inst : label is "1'b1";
attribute EN_OF : string;
attribute EN_OF of xpm_fifo_base_inst : label is "1'b0";
attribute EN_PE : string;
attribute EN_PE of xpm_fifo_base_inst : label is "1'b0";
attribute EN_PF : string;
attribute EN_PF of xpm_fifo_base_inst : label is "1'b0";
attribute EN_RDC : string;
attribute EN_RDC of xpm_fifo_base_inst : label is "1'b0";
attribute EN_UF : string;
attribute EN_UF of xpm_fifo_base_inst : label is "1'b0";
attribute EN_WACK : string;
attribute EN_WACK of xpm_fifo_base_inst : label is "1'b0";
attribute EN_WDC : string;
attribute EN_WDC of xpm_fifo_base_inst : label is "1'b0";
attribute FG_EQ_ASYM_DOUT : string;
attribute FG_EQ_ASYM_DOUT of xpm_fifo_base_inst : label is "1'b0";
attribute FIFO_MEMORY_TYPE_integer : integer;
attribute FIFO_MEMORY_TYPE_integer of xpm_fifo_base_inst : label is 0;
attribute FIFO_MEM_TYPE : integer;
attribute FIFO_MEM_TYPE of xpm_fifo_base_inst : label is 0;
attribute FIFO_READ_DEPTH : integer;
attribute FIFO_READ_DEPTH of xpm_fifo_base_inst : label is 32768;
attribute FIFO_READ_LATENCY : integer;
attribute FIFO_READ_LATENCY of xpm_fifo_base_inst : label is 0;
attribute FIFO_SIZE : integer;
attribute FIFO_SIZE of xpm_fifo_base_inst : label is 1441792;
attribute FIFO_WRITE_DEPTH : integer;
attribute FIFO_WRITE_DEPTH of xpm_fifo_base_inst : label is 32768;
attribute FULL_RESET_VALUE : integer;
attribute FULL_RESET_VALUE of xpm_fifo_base_inst : label is 1;
attribute FULL_RST_VAL : string;
attribute FULL_RST_VAL of xpm_fifo_base_inst : label is "1'b1";
attribute PE_THRESH_ADJ : integer;
attribute PE_THRESH_ADJ of xpm_fifo_base_inst : label is 3;
attribute PE_THRESH_MAX : integer;
attribute PE_THRESH_MAX of xpm_fifo_base_inst : label is 32763;
attribute PE_THRESH_MIN : integer;
attribute PE_THRESH_MIN of xpm_fifo_base_inst : label is 5;
attribute PF_THRESH_ADJ : integer;
attribute PF_THRESH_ADJ of xpm_fifo_base_inst : label is 9;
attribute PF_THRESH_MAX : integer;
attribute PF_THRESH_MAX of xpm_fifo_base_inst : label is 32763;
attribute PF_THRESH_MIN : integer;
attribute PF_THRESH_MIN of xpm_fifo_base_inst : label is 5;
attribute PROG_EMPTY_THRESH of xpm_fifo_base_inst : label is 5;
attribute PROG_FULL_THRESH of xpm_fifo_base_inst : label is 11;
attribute RD_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 16;
attribute RD_DC_WIDTH_EXT : integer;
attribute RD_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 16;
attribute RD_LATENCY : integer;
attribute RD_LATENCY of xpm_fifo_base_inst : label is 2;
attribute RD_MODE : integer;
attribute RD_MODE of xpm_fifo_base_inst : label is 1;
attribute RD_PNTR_WIDTH : integer;
attribute RD_PNTR_WIDTH of xpm_fifo_base_inst : label is 15;
attribute READ_DATA_WIDTH : integer;
attribute READ_DATA_WIDTH of xpm_fifo_base_inst : label is 44;
attribute READ_MODE : integer;
attribute READ_MODE of xpm_fifo_base_inst : label is 1;
attribute RELATED_CLOCKS of xpm_fifo_base_inst : label is 0;
attribute REMOVE_WR_RD_PROT_LOGIC : integer;
attribute REMOVE_WR_RD_PROT_LOGIC of xpm_fifo_base_inst : label is 0;
attribute SIM_ASSERT_CHK of xpm_fifo_base_inst : label is 0;
attribute USE_ADV_FEATURES of xpm_fifo_base_inst : label is 825241648;
attribute VERSION of xpm_fifo_base_inst : label is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of xpm_fifo_base_inst : label is 0;
attribute WIDTH_RATIO : integer;
attribute WIDTH_RATIO of xpm_fifo_base_inst : label is 1;
attribute WRITE_DATA_WIDTH : integer;
attribute WRITE_DATA_WIDTH of xpm_fifo_base_inst : label is 44;
attribute WR_DATA_COUNT_WIDTH of xpm_fifo_base_inst : label is 16;
attribute WR_DC_WIDTH_EXT : integer;
attribute WR_DC_WIDTH_EXT of xpm_fifo_base_inst : label is 16;
attribute WR_DEPTH_LOG : integer;
attribute WR_DEPTH_LOG of xpm_fifo_base_inst : label is 15;
attribute WR_PNTR_WIDTH : integer;
attribute WR_PNTR_WIDTH of xpm_fifo_base_inst : label is 15;
attribute WR_RD_RATIO : integer;
attribute WR_RD_RATIO of xpm_fifo_base_inst : label is 0;
attribute WR_WIDTH_LOG : integer;
attribute WR_WIDTH_LOG of xpm_fifo_base_inst : label is 6;
attribute XPM_MODULE of xpm_fifo_base_inst : label is "TRUE";
attribute both_stages_valid : integer;
attribute both_stages_valid of xpm_fifo_base_inst : label is 3;
attribute invalid : integer;
attribute invalid of xpm_fifo_base_inst : label is 0;
attribute stage1_valid : integer;
attribute stage1_valid of xpm_fifo_base_inst : label is 2;
attribute stage2_valid : integer;
attribute stage2_valid of xpm_fifo_base_inst : label is 1;
begin
almost_empty_axis <= \<const0>\;
almost_full_axis <= \<const0>\;
dbiterr_axis <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tstrb(3) <= \<const0>\;
m_axis_tstrb(2) <= \<const0>\;
m_axis_tstrb(1) <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \^m_axis_tvalid\;
prog_empty_axis <= \<const0>\;
prog_full_axis <= \<const0>\;
rd_data_count_axis(15) <= \<const0>\;
rd_data_count_axis(14) <= \<const0>\;
rd_data_count_axis(13) <= \<const0>\;
rd_data_count_axis(12) <= \<const0>\;
rd_data_count_axis(11) <= \<const0>\;
rd_data_count_axis(10) <= \<const0>\;
rd_data_count_axis(9) <= \<const0>\;
rd_data_count_axis(8) <= \<const0>\;
rd_data_count_axis(7) <= \<const0>\;
rd_data_count_axis(6) <= \<const0>\;
rd_data_count_axis(5) <= \<const0>\;
rd_data_count_axis(4) <= \<const0>\;
rd_data_count_axis(3) <= \<const0>\;
rd_data_count_axis(2) <= \<const0>\;
rd_data_count_axis(1) <= \<const0>\;
rd_data_count_axis(0) <= \<const0>\;
sbiterr_axis <= \<const0>\;
wr_data_count_axis(15) <= \<const0>\;
wr_data_count_axis(14) <= \<const0>\;
wr_data_count_axis(13) <= \<const0>\;
wr_data_count_axis(12) <= \<const0>\;
wr_data_count_axis(11) <= \<const0>\;
wr_data_count_axis(10) <= \<const0>\;
wr_data_count_axis(9) <= \<const0>\;
wr_data_count_axis(8) <= \<const0>\;
wr_data_count_axis(7) <= \<const0>\;
wr_data_count_axis(6) <= \<const0>\;
wr_data_count_axis(5) <= \<const0>\;
wr_data_count_axis(4) <= \<const0>\;
wr_data_count_axis(3) <= \<const0>\;
wr_data_count_axis(2) <= \<const0>\;
wr_data_count_axis(1) <= \<const0>\;
wr_data_count_axis(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gaxis_rst_sync.xpm_cdc_sync_rst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst
port map (
dest_clk => s_aclk,
dest_rst => rst_axis,
src_rst => \gaxis_rst_sync.xpm_cdc_sync_rst_inst_i_1_n_0\
);
\gaxis_rst_sync.xpm_cdc_sync_rst_inst_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_aresetn,
O => \gaxis_rst_sync.xpm_cdc_sync_rst_inst_i_1_n_0\
);
xpm_fifo_base_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base
port map (
almost_empty => NLW_xpm_fifo_base_inst_almost_empty_UNCONNECTED,
almost_full => NLW_xpm_fifo_base_inst_almost_full_UNCONNECTED,
data_valid => \^m_axis_tvalid\,
dbiterr => NLW_xpm_fifo_base_inst_dbiterr_UNCONNECTED,
din(43) => s_axis_tlast,
din(42 downto 40) => B"000",
din(39 downto 36) => s_axis_tkeep(3 downto 0),
din(35 downto 32) => B"0000",
din(31 downto 0) => s_axis_tdata(31 downto 0),
dout(43) => m_axis_tlast,
dout(42 downto 40) => NLW_xpm_fifo_base_inst_dout_UNCONNECTED(42 downto 40),
dout(39 downto 36) => m_axis_tkeep(3 downto 0),
dout(35 downto 32) => NLW_xpm_fifo_base_inst_dout_UNCONNECTED(35 downto 32),
dout(31 downto 0) => m_axis_tdata(31 downto 0),
empty => NLW_xpm_fifo_base_inst_empty_UNCONNECTED,
full => NLW_xpm_fifo_base_inst_full_UNCONNECTED,
full_n => s_axis_tready,
injectdbiterr => '0',
injectsbiterr => '0',
overflow => NLW_xpm_fifo_base_inst_overflow_UNCONNECTED,
prog_empty => NLW_xpm_fifo_base_inst_prog_empty_UNCONNECTED,
prog_full => NLW_xpm_fifo_base_inst_prog_full_UNCONNECTED,
rd_clk => '0',
rd_data_count(15 downto 0) => NLW_xpm_fifo_base_inst_rd_data_count_UNCONNECTED(15 downto 0),
rd_en => xpm_fifo_base_inst_i_1_n_0,
rd_rst_busy => NLW_xpm_fifo_base_inst_rd_rst_busy_UNCONNECTED,
rst => rst_axis,
sbiterr => NLW_xpm_fifo_base_inst_sbiterr_UNCONNECTED,
sleep => '0',
underflow => NLW_xpm_fifo_base_inst_underflow_UNCONNECTED,
wr_ack => NLW_xpm_fifo_base_inst_wr_ack_UNCONNECTED,
wr_clk => s_aclk,
wr_data_count(15 downto 0) => NLW_xpm_fifo_base_inst_wr_data_count_UNCONNECTED(15 downto 0),
wr_en => s_axis_tvalid,
wr_rst_busy => NLW_xpm_fifo_base_inst_wr_rst_busy_UNCONNECTED
);
xpm_fifo_base_inst_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_axis_tvalid\,
I1 => m_axis_tready,
O => xpm_fifo_base_inst_i_1_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top is
port (
s_axis_aclk : in STD_LOGIC;
s_axis_aresetn : in STD_LOGIC;
s_axis_aclken : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
almost_full : out STD_LOGIC;
prog_full : out STD_LOGIC;
axis_wr_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
m_axis_aclk : in STD_LOGIC;
m_axis_aclken : in STD_LOGIC;
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
almost_empty : out STD_LOGIC;
prog_empty : out STD_LOGIC;
axis_rd_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC
);
attribute C_ACLKEN_CONV_MODE : integer;
attribute C_ACLKEN_CONV_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 0;
attribute C_AXIS_SIGNAL_SET : string;
attribute C_AXIS_SIGNAL_SET of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is "32'b00000000000000000000000000011011";
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 32;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 1;
attribute C_ECC_MODE : integer;
attribute C_ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is "artix7";
attribute C_FIFO_DEPTH : integer;
attribute C_FIFO_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 32768;
attribute C_FIFO_MEMORY_TYPE : string;
attribute C_FIFO_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is "auto";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 1;
attribute C_IS_ACLK_ASYNC : integer;
attribute C_IS_ACLK_ASYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 0;
attribute C_PROG_EMPTY_THRESH : integer;
attribute C_PROG_EMPTY_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 5;
attribute C_PROG_FULL_THRESH : integer;
attribute C_PROG_FULL_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 11;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 3;
attribute C_USE_ADV_FEATURES : integer;
attribute C_USE_ADV_FEATURES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 825241648;
attribute G_INDX_SS_TDATA : integer;
attribute G_INDX_SS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 1;
attribute G_INDX_SS_TDEST : integer;
attribute G_INDX_SS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 6;
attribute G_INDX_SS_TID : integer;
attribute G_INDX_SS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 5;
attribute G_INDX_SS_TKEEP : integer;
attribute G_INDX_SS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 3;
attribute G_INDX_SS_TLAST : integer;
attribute G_INDX_SS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 4;
attribute G_INDX_SS_TREADY : integer;
attribute G_INDX_SS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 0;
attribute G_INDX_SS_TSTRB : integer;
attribute G_INDX_SS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 2;
attribute G_INDX_SS_TUSER : integer;
attribute G_INDX_SS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 7;
attribute G_MASK_SS_TDATA : integer;
attribute G_MASK_SS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 2;
attribute G_MASK_SS_TDEST : integer;
attribute G_MASK_SS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 64;
attribute G_MASK_SS_TID : integer;
attribute G_MASK_SS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 32;
attribute G_MASK_SS_TKEEP : integer;
attribute G_MASK_SS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 8;
attribute G_MASK_SS_TLAST : integer;
attribute G_MASK_SS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 16;
attribute G_MASK_SS_TREADY : integer;
attribute G_MASK_SS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 1;
attribute G_MASK_SS_TSTRB : integer;
attribute G_MASK_SS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 4;
attribute G_MASK_SS_TUSER : integer;
attribute G_MASK_SS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 128;
attribute G_TASK_SEVERITY_ERR : integer;
attribute G_TASK_SEVERITY_ERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 2;
attribute G_TASK_SEVERITY_INFO : integer;
attribute G_TASK_SEVERITY_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 0;
attribute G_TASK_SEVERITY_WARNING : integer;
attribute G_TASK_SEVERITY_WARNING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 1;
attribute LP_CDC_SYNC_STAGES : integer;
attribute LP_CDC_SYNC_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 3;
attribute LP_CLOCKING_MODE : string;
attribute LP_CLOCKING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is "common_clock";
attribute LP_ECC_MODE : string;
attribute LP_ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is "no_ecc";
attribute LP_FIFO_DEPTH : integer;
attribute LP_FIFO_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 32768;
attribute LP_FIFO_MEMORY_TYPE : string;
attribute LP_FIFO_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is "auto";
attribute LP_M_ACLKEN_CAN_TOGGLE : integer;
attribute LP_M_ACLKEN_CAN_TOGGLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 0;
attribute LP_PACKET_FIFO : string;
attribute LP_PACKET_FIFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is "false";
attribute LP_PROG_EMPTY_THRESH : integer;
attribute LP_PROG_EMPTY_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 5;
attribute LP_PROG_FULL_THRESH : integer;
attribute LP_PROG_FULL_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 11;
attribute LP_RD_DATA_COUNT_WIDTH : integer;
attribute LP_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 16;
attribute LP_RELATED_CLOCKS : integer;
attribute LP_RELATED_CLOCKS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 0;
attribute LP_S_ACLKEN_CAN_TOGGLE : integer;
attribute LP_S_ACLKEN_CAN_TOGGLE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 0;
attribute LP_TDATA_WIDTH : integer;
attribute LP_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 32;
attribute LP_TDEST_WIDTH : integer;
attribute LP_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 1;
attribute LP_TID_WIDTH : integer;
attribute LP_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 1;
attribute LP_TUSER_WIDTH : integer;
attribute LP_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 1;
attribute LP_USE_ADV_FEATURES : integer;
attribute LP_USE_ADV_FEATURES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 825241648;
attribute LP_WR_DATA_COUNT_WIDTH : integer;
attribute LP_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top : entity is 16;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^axis_rd_data_count\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^axis_wr_data_count\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_gen_fifo.xpm_fifo_axis_inst_m_axis_tdest_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_fifo.xpm_fifo_axis_inst_m_axis_tid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_fifo.xpm_fifo_axis_inst_m_axis_tstrb_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_fifo.xpm_fifo_axis_inst_m_axis_tuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute AXIS_DATA_WIDTH : integer;
attribute AXIS_DATA_WIDTH of \gen_fifo.xpm_fifo_axis_inst\ : label is 44;
attribute AXIS_FINAL_DATA_WIDTH : integer;
attribute AXIS_FINAL_DATA_WIDTH of \gen_fifo.xpm_fifo_axis_inst\ : label is 44;
attribute CASCADE_HEIGHT : integer;
attribute CASCADE_HEIGHT of \gen_fifo.xpm_fifo_axis_inst\ : label is 0;
attribute CDC_SYNC_STAGES : integer;
attribute CDC_SYNC_STAGES of \gen_fifo.xpm_fifo_axis_inst\ : label is 3;
attribute CLOCKING_MODE : string;
attribute CLOCKING_MODE of \gen_fifo.xpm_fifo_axis_inst\ : label is "common_clock";
attribute ECC_MODE : string;
attribute ECC_MODE of \gen_fifo.xpm_fifo_axis_inst\ : label is "no_ecc";
attribute EN_ADV_FEATURE_AXIS : string;
attribute EN_ADV_FEATURE_AXIS of \gen_fifo.xpm_fifo_axis_inst\ : label is "16'b0001000000000000";
attribute EN_ADV_FEATURE_AXIS_INT : string;
attribute EN_ADV_FEATURE_AXIS_INT of \gen_fifo.xpm_fifo_axis_inst\ : label is "16'b0001000000000000";
attribute EN_ALMOST_EMPTY_INT : string;
attribute EN_ALMOST_EMPTY_INT of \gen_fifo.xpm_fifo_axis_inst\ : label is "1'b0";
attribute EN_ALMOST_FULL_INT : string;
attribute EN_ALMOST_FULL_INT of \gen_fifo.xpm_fifo_axis_inst\ : label is "1'b0";
attribute EN_DATA_VALID_INT : string;
attribute EN_DATA_VALID_INT of \gen_fifo.xpm_fifo_axis_inst\ : label is "1'b1";
attribute FIFO_DEPTH : integer;
attribute FIFO_DEPTH of \gen_fifo.xpm_fifo_axis_inst\ : label is 32768;
attribute FIFO_MEMORY_TYPE : string;
attribute FIFO_MEMORY_TYPE of \gen_fifo.xpm_fifo_axis_inst\ : label is "auto";
attribute LOG_DEPTH_AXIS : integer;
attribute LOG_DEPTH_AXIS of \gen_fifo.xpm_fifo_axis_inst\ : label is 15;
attribute PACKET_FIFO : string;
attribute PACKET_FIFO of \gen_fifo.xpm_fifo_axis_inst\ : label is "false";
attribute PKT_SIZE_LT8 : string;
attribute PKT_SIZE_LT8 of \gen_fifo.xpm_fifo_axis_inst\ : label is "1'b0";
attribute PROG_EMPTY_THRESH : integer;
attribute PROG_EMPTY_THRESH of \gen_fifo.xpm_fifo_axis_inst\ : label is 5;
attribute PROG_FULL_THRESH : integer;
attribute PROG_FULL_THRESH of \gen_fifo.xpm_fifo_axis_inst\ : label is 11;
attribute P_COMMON_CLOCK : integer;
attribute P_COMMON_CLOCK of \gen_fifo.xpm_fifo_axis_inst\ : label is 1;
attribute P_ECC_MODE : integer;
attribute P_ECC_MODE of \gen_fifo.xpm_fifo_axis_inst\ : label is 0;
attribute P_FIFO_MEMORY_TYPE : integer;
attribute P_FIFO_MEMORY_TYPE of \gen_fifo.xpm_fifo_axis_inst\ : label is 0;
attribute P_PKT_MODE : integer;
attribute P_PKT_MODE of \gen_fifo.xpm_fifo_axis_inst\ : label is 0;
attribute RD_DATA_COUNT_WIDTH : integer;
attribute RD_DATA_COUNT_WIDTH of \gen_fifo.xpm_fifo_axis_inst\ : label is 16;
attribute RELATED_CLOCKS : integer;
attribute RELATED_CLOCKS of \gen_fifo.xpm_fifo_axis_inst\ : label is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \gen_fifo.xpm_fifo_axis_inst\ : label is 0;
attribute TDATA_OFFSET : integer;
attribute TDATA_OFFSET of \gen_fifo.xpm_fifo_axis_inst\ : label is 32;
attribute TDATA_WIDTH : integer;
attribute TDATA_WIDTH of \gen_fifo.xpm_fifo_axis_inst\ : label is 32;
attribute TDEST_OFFSET : integer;
attribute TDEST_OFFSET of \gen_fifo.xpm_fifo_axis_inst\ : label is 42;
attribute TDEST_WIDTH : integer;
attribute TDEST_WIDTH of \gen_fifo.xpm_fifo_axis_inst\ : label is 1;
attribute TID_OFFSET : integer;
attribute TID_OFFSET of \gen_fifo.xpm_fifo_axis_inst\ : label is 41;
attribute TID_WIDTH : integer;
attribute TID_WIDTH of \gen_fifo.xpm_fifo_axis_inst\ : label is 1;
attribute TKEEP_OFFSET : integer;
attribute TKEEP_OFFSET of \gen_fifo.xpm_fifo_axis_inst\ : label is 40;
attribute TSTRB_OFFSET : integer;
attribute TSTRB_OFFSET of \gen_fifo.xpm_fifo_axis_inst\ : label is 36;
attribute TUSER_MAX_WIDTH : integer;
attribute TUSER_MAX_WIDTH of \gen_fifo.xpm_fifo_axis_inst\ : label is 4053;
attribute TUSER_OFFSET : integer;
attribute TUSER_OFFSET of \gen_fifo.xpm_fifo_axis_inst\ : label is 43;
attribute TUSER_WIDTH : integer;
attribute TUSER_WIDTH of \gen_fifo.xpm_fifo_axis_inst\ : label is 1;
attribute USE_ADV_FEATURES : integer;
attribute USE_ADV_FEATURES of \gen_fifo.xpm_fifo_axis_inst\ : label is 825241648;
attribute USE_ADV_FEATURES_INT : integer;
attribute USE_ADV_FEATURES_INT of \gen_fifo.xpm_fifo_axis_inst\ : label is 825241648;
attribute WR_DATA_COUNT_WIDTH : integer;
attribute WR_DATA_COUNT_WIDTH of \gen_fifo.xpm_fifo_axis_inst\ : label is 16;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \gen_fifo.xpm_fifo_axis_inst\ : label is "TRUE";
begin
axis_rd_data_count(31) <= \<const0>\;
axis_rd_data_count(30) <= \<const0>\;
axis_rd_data_count(29) <= \<const0>\;
axis_rd_data_count(28) <= \<const0>\;
axis_rd_data_count(27) <= \<const0>\;
axis_rd_data_count(26) <= \<const0>\;
axis_rd_data_count(25) <= \<const0>\;
axis_rd_data_count(24) <= \<const0>\;
axis_rd_data_count(23) <= \<const0>\;
axis_rd_data_count(22) <= \<const0>\;
axis_rd_data_count(21) <= \<const0>\;
axis_rd_data_count(20) <= \<const0>\;
axis_rd_data_count(19) <= \<const0>\;
axis_rd_data_count(18) <= \<const0>\;
axis_rd_data_count(17) <= \<const0>\;
axis_rd_data_count(16) <= \<const0>\;
axis_rd_data_count(15 downto 0) <= \^axis_rd_data_count\(15 downto 0);
axis_wr_data_count(31) <= \<const0>\;
axis_wr_data_count(30) <= \<const0>\;
axis_wr_data_count(29) <= \<const0>\;
axis_wr_data_count(28) <= \<const0>\;
axis_wr_data_count(27) <= \<const0>\;
axis_wr_data_count(26) <= \<const0>\;
axis_wr_data_count(25) <= \<const0>\;
axis_wr_data_count(24) <= \<const0>\;
axis_wr_data_count(23) <= \<const0>\;
axis_wr_data_count(22) <= \<const0>\;
axis_wr_data_count(21) <= \<const0>\;
axis_wr_data_count(20) <= \<const0>\;
axis_wr_data_count(19) <= \<const0>\;
axis_wr_data_count(18) <= \<const0>\;
axis_wr_data_count(17) <= \<const0>\;
axis_wr_data_count(16) <= \<const0>\;
axis_wr_data_count(15 downto 0) <= \^axis_wr_data_count\(15 downto 0);
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tstrb(3) <= \<const1>\;
m_axis_tstrb(2) <= \<const1>\;
m_axis_tstrb(1) <= \<const1>\;
m_axis_tstrb(0) <= \<const1>\;
m_axis_tuser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_fifo.xpm_fifo_axis_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_axis
port map (
almost_empty_axis => almost_empty,
almost_full_axis => almost_full,
dbiterr_axis => dbiterr,
injectdbiterr_axis => injectdbiterr,
injectsbiterr_axis => injectsbiterr,
m_aclk => s_axis_aclk,
m_axis_tdata(31 downto 0) => m_axis_tdata(31 downto 0),
m_axis_tdest(0) => \NLW_gen_fifo.xpm_fifo_axis_inst_m_axis_tdest_UNCONNECTED\(0),
m_axis_tid(0) => \NLW_gen_fifo.xpm_fifo_axis_inst_m_axis_tid_UNCONNECTED\(0),
m_axis_tkeep(3 downto 0) => m_axis_tkeep(3 downto 0),
m_axis_tlast => m_axis_tlast,
m_axis_tready => m_axis_tready,
m_axis_tstrb(3 downto 0) => \NLW_gen_fifo.xpm_fifo_axis_inst_m_axis_tstrb_UNCONNECTED\(3 downto 0),
m_axis_tuser(0) => \NLW_gen_fifo.xpm_fifo_axis_inst_m_axis_tuser_UNCONNECTED\(0),
m_axis_tvalid => m_axis_tvalid,
prog_empty_axis => prog_empty,
prog_full_axis => prog_full,
rd_data_count_axis(15 downto 0) => \^axis_rd_data_count\(15 downto 0),
s_aclk => s_axis_aclk,
s_aresetn => s_axis_aresetn,
s_axis_tdata(31 downto 0) => s_axis_tdata(31 downto 0),
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(3 downto 0) => s_axis_tkeep(3 downto 0),
s_axis_tlast => s_axis_tlast,
s_axis_tready => s_axis_tready,
s_axis_tstrb(3 downto 0) => B"0000",
s_axis_tuser(0) => '0',
s_axis_tvalid => s_axis_tvalid,
sbiterr_axis => sbiterr,
wr_data_count_axis(15 downto 0) => \^axis_wr_data_count\(15 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axis_aresetn : in STD_LOGIC;
s_axis_aclk : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mb_design_axis_data_fifo_0_0,axis_data_fifo_v2_0_2_top,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axis_data_fifo_v2_0_2_top,Vivado 2019.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_inst_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_inst_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_inst_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_inst_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_inst_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_inst_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACLKEN_CONV_MODE : integer;
attribute C_ACLKEN_CONV_MODE of inst : label is 0;
attribute C_AXIS_SIGNAL_SET : string;
attribute C_AXIS_SIGNAL_SET of inst : label is "32'b00000000000000000000000000011011";
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of inst : label is 32;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of inst : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of inst : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of inst : label is 1;
attribute C_ECC_MODE : integer;
attribute C_ECC_MODE of inst : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "artix7";
attribute C_FIFO_DEPTH : integer;
attribute C_FIFO_DEPTH of inst : label is 32768;
attribute C_FIFO_MEMORY_TYPE : string;
attribute C_FIFO_MEMORY_TYPE of inst : label is "auto";
attribute C_FIFO_MODE : integer;
attribute C_FIFO_MODE of inst : label is 1;
attribute C_IS_ACLK_ASYNC : integer;
attribute C_IS_ACLK_ASYNC of inst : label is 0;
attribute C_PROG_EMPTY_THRESH : integer;
attribute C_PROG_EMPTY_THRESH of inst : label is 5;
attribute C_PROG_FULL_THRESH : integer;
attribute C_PROG_FULL_THRESH of inst : label is 11;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of inst : label is 3;
attribute C_USE_ADV_FEATURES : integer;
attribute C_USE_ADV_FEATURES of inst : label is 825241648;
attribute G_INDX_SS_TDATA : integer;
attribute G_INDX_SS_TDATA of inst : label is 1;
attribute G_INDX_SS_TDEST : integer;
attribute G_INDX_SS_TDEST of inst : label is 6;
attribute G_INDX_SS_TID : integer;
attribute G_INDX_SS_TID of inst : label is 5;
attribute G_INDX_SS_TKEEP : integer;
attribute G_INDX_SS_TKEEP of inst : label is 3;
attribute G_INDX_SS_TLAST : integer;
attribute G_INDX_SS_TLAST of inst : label is 4;
attribute G_INDX_SS_TREADY : integer;
attribute G_INDX_SS_TREADY of inst : label is 0;
attribute G_INDX_SS_TSTRB : integer;
attribute G_INDX_SS_TSTRB of inst : label is 2;
attribute G_INDX_SS_TUSER : integer;
attribute G_INDX_SS_TUSER of inst : label is 7;
attribute G_MASK_SS_TDATA : integer;
attribute G_MASK_SS_TDATA of inst : label is 2;
attribute G_MASK_SS_TDEST : integer;
attribute G_MASK_SS_TDEST of inst : label is 64;
attribute G_MASK_SS_TID : integer;
attribute G_MASK_SS_TID of inst : label is 32;
attribute G_MASK_SS_TKEEP : integer;
attribute G_MASK_SS_TKEEP of inst : label is 8;
attribute G_MASK_SS_TLAST : integer;
attribute G_MASK_SS_TLAST of inst : label is 16;
attribute G_MASK_SS_TREADY : integer;
attribute G_MASK_SS_TREADY of inst : label is 1;
attribute G_MASK_SS_TSTRB : integer;
attribute G_MASK_SS_TSTRB of inst : label is 4;
attribute G_MASK_SS_TUSER : integer;
attribute G_MASK_SS_TUSER of inst : label is 128;
attribute G_TASK_SEVERITY_ERR : integer;
attribute G_TASK_SEVERITY_ERR of inst : label is 2;
attribute G_TASK_SEVERITY_INFO : integer;
attribute G_TASK_SEVERITY_INFO of inst : label is 0;
attribute G_TASK_SEVERITY_WARNING : integer;
attribute G_TASK_SEVERITY_WARNING of inst : label is 1;
attribute LP_CDC_SYNC_STAGES : integer;
attribute LP_CDC_SYNC_STAGES of inst : label is 3;
attribute LP_CLOCKING_MODE : string;
attribute LP_CLOCKING_MODE of inst : label is "common_clock";
attribute LP_ECC_MODE : string;
attribute LP_ECC_MODE of inst : label is "no_ecc";
attribute LP_FIFO_DEPTH : integer;
attribute LP_FIFO_DEPTH of inst : label is 32768;
attribute LP_FIFO_MEMORY_TYPE : string;
attribute LP_FIFO_MEMORY_TYPE of inst : label is "auto";
attribute LP_M_ACLKEN_CAN_TOGGLE : integer;
attribute LP_M_ACLKEN_CAN_TOGGLE of inst : label is 0;
attribute LP_PACKET_FIFO : string;
attribute LP_PACKET_FIFO of inst : label is "false";
attribute LP_PROG_EMPTY_THRESH : integer;
attribute LP_PROG_EMPTY_THRESH of inst : label is 5;
attribute LP_PROG_FULL_THRESH : integer;
attribute LP_PROG_FULL_THRESH of inst : label is 11;
attribute LP_RD_DATA_COUNT_WIDTH : integer;
attribute LP_RD_DATA_COUNT_WIDTH of inst : label is 16;
attribute LP_RELATED_CLOCKS : integer;
attribute LP_RELATED_CLOCKS of inst : label is 0;
attribute LP_S_ACLKEN_CAN_TOGGLE : integer;
attribute LP_S_ACLKEN_CAN_TOGGLE of inst : label is 0;
attribute LP_TDATA_WIDTH : integer;
attribute LP_TDATA_WIDTH of inst : label is 32;
attribute LP_TDEST_WIDTH : integer;
attribute LP_TDEST_WIDTH of inst : label is 1;
attribute LP_TID_WIDTH : integer;
attribute LP_TID_WIDTH of inst : label is 1;
attribute LP_TUSER_WIDTH : integer;
attribute LP_TUSER_WIDTH of inst : label is 1;
attribute LP_USE_ADV_FEATURES : integer;
attribute LP_USE_ADV_FEATURES of inst : label is 825241648;
attribute LP_WR_DATA_COUNT_WIDTH : integer;
attribute LP_WR_DATA_COUNT_WIDTH of inst : label is 16;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of m_axis_tlast : signal is "xilinx.com:interface:axis:1.0 M_AXIS TLAST";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of m_axis_tlast : signal is "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_1_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0";
attribute X_INTERFACE_INFO of m_axis_tready : signal is "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
attribute X_INTERFACE_INFO of m_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
attribute X_INTERFACE_INFO of s_axis_aclk : signal is "xilinx.com:signal:clock:1.0 S_CLKIF CLK";
attribute X_INTERFACE_PARAMETER of s_axis_aclk : signal is "XIL_INTERFACENAME S_CLKIF, ASSOCIATED_BUSIF S_AXIS:M_AXIS, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_1_clk_out1, ASSOCIATED_RESET s_axis_aresetn, INSERT_VIP 0, ASSOCIATED_CLKEN s_axis_aclken";
attribute X_INTERFACE_INFO of s_axis_aresetn : signal is "xilinx.com:signal:reset:1.0 S_RSTIF RST";
attribute X_INTERFACE_PARAMETER of s_axis_aresetn : signal is "XIL_INTERFACENAME S_RSTIF, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT";
attribute X_INTERFACE_INFO of s_axis_tlast : signal is "xilinx.com:interface:axis:1.0 S_AXIS TLAST";
attribute X_INTERFACE_PARAMETER of s_axis_tlast : signal is "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_1_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0";
attribute X_INTERFACE_INFO of s_axis_tready : signal is "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
attribute X_INTERFACE_INFO of s_axis_tvalid : signal is "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
attribute X_INTERFACE_INFO of m_axis_tdata : signal is "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
attribute X_INTERFACE_INFO of m_axis_tkeep : signal is "xilinx.com:interface:axis:1.0 M_AXIS TKEEP";
attribute X_INTERFACE_INFO of s_axis_tdata : signal is "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
attribute X_INTERFACE_INFO of s_axis_tkeep : signal is "xilinx.com:interface:axis:1.0 S_AXIS TKEEP";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axis_data_fifo_v2_0_2_top
port map (
almost_empty => NLW_inst_almost_empty_UNCONNECTED,
almost_full => NLW_inst_almost_full_UNCONNECTED,
axis_rd_data_count(31 downto 0) => NLW_inst_axis_rd_data_count_UNCONNECTED(31 downto 0),
axis_wr_data_count(31 downto 0) => NLW_inst_axis_wr_data_count_UNCONNECTED(31 downto 0),
dbiterr => NLW_inst_dbiterr_UNCONNECTED,
injectdbiterr => '0',
injectsbiterr => '0',
m_axis_aclk => '0',
m_axis_aclken => '1',
m_axis_tdata(31 downto 0) => m_axis_tdata(31 downto 0),
m_axis_tdest(0) => NLW_inst_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_inst_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(3 downto 0) => m_axis_tkeep(3 downto 0),
m_axis_tlast => m_axis_tlast,
m_axis_tready => m_axis_tready,
m_axis_tstrb(3 downto 0) => NLW_inst_m_axis_tstrb_UNCONNECTED(3 downto 0),
m_axis_tuser(0) => NLW_inst_m_axis_tuser_UNCONNECTED(0),
m_axis_tvalid => m_axis_tvalid,
prog_empty => NLW_inst_prog_empty_UNCONNECTED,
prog_full => NLW_inst_prog_full_UNCONNECTED,
s_axis_aclk => s_axis_aclk,
s_axis_aclken => '1',
s_axis_aresetn => s_axis_aresetn,
s_axis_tdata(31 downto 0) => s_axis_tdata(31 downto 0),
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(3 downto 0) => s_axis_tkeep(3 downto 0),
s_axis_tlast => s_axis_tlast,
s_axis_tready => s_axis_tready,
s_axis_tstrb(3 downto 0) => B"1111",
s_axis_tuser(0) => '0',
s_axis_tvalid => s_axis_tvalid,
sbiterr => NLW_inst_sbiterr_UNCONNECTED
);
end STRUCTURE;
|
<filename>modules/fmc_acq427/hdl/fmc_dac_interface.vhd
---------------------------------------------------------------------------------------
--! @file
--! @brief ACQ427FMC Module Address Decode and Control - PandA
--! @author <NAME>, <NAME>
--! @date 10th May 2016
--! @details
--! D-TACQ Solutions Ltd Copyright 2013-2018
--!
--! Standard Libraries - numeric.std for all designs
library ieee;
use ieee.std_logic_1164.all; --! Standard Logic Functions
use ieee.numeric_std.all; --! Numeric Functions for Signed / Unsigned Arithmetic
--! If using Xilinx primitives need the Xilinx library
library UNISIM;
use UNISIM.VComponents.all; --! Xilinx Primitives
--! Local Functions and Types
use work.ACQ427TYPES.all; --! Local Types
Entity ACQ427FMC_DAC_INTERFACE is
Port(
clk_PANDA : in std_logic; --! 125 MHz clock from Zynq core
-- Connections to PandA registers
DAC_CLKDIV_REG : in std_logic_vector(31 downto 0);
DAC_FIFO_RESET_REG : in std_logic_vector(31 downto 0);
DAC_FIFO_ENABLE_REG : in std_logic_vector(31 downto 0);
DAC_RESET_REG : in std_logic_vector(31 downto 0);
DAC_ENABLE_REG : in std_logic_vector(31 downto 0);
-- I/Os to DACs
clk_DAC_IOB : out std_logic; --! DAC SPI Clk for IOBs
DAC_SPI_CLK : out std_logic; --! DAC SPI Clock
DAC_SDI : out std_logic_vector( 4 downto 1); --! DAC SPI Data In
DAC_SDO : in std_logic_vector( 4 downto 1); --! DAC SPI Data Out
DAC_SYNC_n : out std_logic; --! DAC SPI SYNC
DAC_LD_n : out std_logic; --! DAC Load
DAC_RST_n : out std_logic; --! DAC Reset
DAC_DATAIN : in std_logic_vector(127 downto 0)
);
end ACQ427FMC_DAC_INTERFACE;
architecture RTL of ACQ427FMC_DAC_INTERFACE is
component fmc_acq427_dac_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR (5 downto 0 );
wr_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
--*************************************************************************************************************************
-- PandA_clk Domain signals
--*************************************************************************************************************************
signal FIFO_DATAOUT : std_logic_vector(31 downto 0) := (others => '0'); --! FIFO data to AXI_DATA_ENGINE
signal FIFO_FULL : std_logic := '0'; --! FIFO FULL signal: to REGISTERS
signal FIFO_EMPTY : std_logic := '0'; --! FIFO EMPTY signal: to REGISTERS
signal DACCLK_FIFO_EMPTY : std_logic := '0'; --! FIFO FULL signal on the IP is in the Write Clock Domain
signal FIFO_WR_DATA : std_logic_vector(127 downto 0); --! FIFO Write Data from AXI or SidePort
signal FIFO_WR_EN : std_logic := '0'; --! FIFO Write control
signal DIV_CLK_d0 : std_logic := '0'; --! DIV_CLK De-bounced in the 66 MHz Domain
signal DIV_CLK_RISING : std_logic := '0'; --! DIV_CLK Rising Edge in the 66 MHz Domain
signal DAC_FIFO_WR_COUNT : std_logic_vector(3 downto 0) := (others => '0'); --! DAC FIFO WR Count
--*************************************************************************************************************************
-- DAC_clk Domain
--*************************************************************************************************************************
signal DAC_FIFO_ENABLE : std_logic := '0';
signal DAC_FIFO_RESET : std_logic := '0';
signal DAC_FIFO_RD_COUNT : std_logic_vector(5 downto 0) := (others => '0'); --! DAC FIFO RD Count
signal DACCLK_FIFO_AVAIL : std_logic; --! There is a sample of data in the FIFO
signal DIV_CLK : std_logic; --! Divided Down Clock for Asynchronous Logic
--signal DIV_CLK_SEL : std_logic; --! Select between Divided Down Clock and input clock for the special case of divide by 1 --GBC:20190321 (unused)
signal CONV_ACTIVE : std_logic; --! Conversion Active - Enabled
signal DAC_DATA_RD : std_logic := '0'; --! FIFO Read from the DAC Logic
signal DAC_RESET : std_logic := '0'; --! Reset the DAC logic
signal DAC_RESET_d0 : std_logic := '0'; --!
signal DAC_RESET_FALLING : std_logic := '0'; --!
signal DAC_RESET_FALLING_d0 : std_logic := '0'; --!
signal DAC_RESET_FALLING_d1 : std_logic := '0'; --!
signal DAC_RESET_FALLING_d2 : std_logic := '0'; --!
signal DAC_RESET_FALLING_STRETCH : std_logic := '0'; --!
signal CLK_SEL_DAC_RESET : std_logic := '0'; --! Reset the DAC logic
signal DAC_ENABLE, DAC_ENABLE_a : std_logic := '0'; --! Combination of ALG Enable and ICS_OE_CLK_s
signal DATA_SIZE : std_logic; --! Pack data in 32/16 bits
signal DAC_CLK_DIV : std_logic_vector(15 downto 0) := (others => '0'); --! Clock Divider to generate DAC Sample Clock
--signal CLOCK_EST_COUNTER : unsigned(27 downto 0) := (others => '0'); --! Clock Speed Counter Counter --GBC:20190321
--signal CLOCK_EST_COUNTER_LATCH : std_logic_vector(27 downto 0) := (others => '0'); --! Clock Speed Counter Counter Latched --GBC:20190321
--signal CLOCK_EST_THECLK_IN : std_logic; --! Clock Speed Counter Clock --GBC:20190321
--signal CLOCK_EST_d0 : std_logic; --! Clock Speed Estimator Clock debounced against the 100M Clock --GBC:20190321
--signal CLOCK_EST_d1 : std_logic; --! Clock Speed Estimator Clock debounced against the 100M Clock --GBC:20190321
--signal SAMPLE_COUNTER : unsigned(31 downto 0) := (others => '0'); --! Samples since Trigger Counter --GBC:20190321
--signal SAMPLE_COUNTER_LATCH : std_logic_vector(31 downto 0) := (others => '0'); --! Samples since Trigger Counter --GBC:20190321
signal clk_SPI : std_logic; --! SPI Clock to shifting logic
signal CONTROL_WRITE : std_logic; --! Write Control Data
signal CONTROL_WRITE_COMPL : std_logic; --! Write Control Data Complete
signal SPI_CONTROL_DATA : std_logic_vector(23 downto 0); --! DAC Control Register Write Data
signal CONTROL_READ : std_logic; --! Read Control Data
signal DACCLK_CONTROL_READ : std_logic; --! Read Control Data
signal CONTROL_READ_COMPL : std_logic; --! Write Control Data Complete
signal CONTROL_READBACK : std_logic_vector(23 downto 0); --! DAC Control Register ReadBack
signal s_CLK_GEN_CLK : std_logic; --! Generated Clock for the DACs
signal CLKDIV_COUNTER : std_logic_vector (15 downto 0); --! Divide the Selected Clock for use as the Internal Sample Clock
signal CLKDIV_COUNTER_RESET : std_logic; --! Reset the Counter
--signal DIVIDE2 : std_logic_vector (15 downto 0); --! Divide by 2 calculation to get close to 50/50 duty cycle --GBC:20190321
signal clk_62_5M : std_logic;
signal clk_62_5M_raw : std_logic := '0';
signal DAC_INIT_COUNTER : unsigned(10 downto 0); --! Counter to space SPI DAC Init writes in time
signal FAST_DAC_RD_EN : std_logic;
attribute ASYNC_REG : string;
attribute ASYNC_REG of DAC_ENABLE, DAC_ENABLE_a : signal is "TRUE";
type DAC_SPI_INIT_STATE_V is (
IDLE, -- Idle State
WAIT0, -- Wait for Write Complete
CW1, -- Write 1st Control Word to DACs
WAIT1, -- Wait for Write Complete
CW2, -- Write 2nd Control Word to DACs
WAIT2, -- Wait for Write Complete
CW3 -- Write 3rd Control Word to DACs and stall until reset
);
signal CONTROL_STATE,NEXT_CONTROL_STATE : DAC_SPI_INIT_STATE_V; --! DAC SPI Init State Machine
--------------------------------------------------------------------------------------
-- debug test using mark_debug
---------------------------------------------------------------------------------------
--attribute mark_debug : string; --GBC:20190321
--attribute keep : string; --GBC:20190321
begin
--*************************************************************************************************************************
-- Clock Domain Crossing clk_PANDA and clk_62_5M
--*************************************************************************************************************************
Cross_Clock_Buffer_AXI : Process(clk_PANDA)
begin
if Rising_Edge(clk_PANDA) then
FIFO_EMPTY <= DACCLK_FIFO_EMPTY;
end if;
end process Cross_Clock_Buffer_AXI;
FAST_DAC_RD_EN <= DAC_DATA_RD and DAC_FIFO_ENABLE;
--! DAC Buffer FIFO using Xilinx IP Module to move between DAC Clock Domain and PandA Clock Domain generate this based on the ADC one
--FAST_DAC_MEMORY : entity work.DAC_FIFO
FAST_DAC_MEMORY : fmc_acq427_dac_fifo
port map(
rst => DAC_FIFO_RESET,
full => FIFO_FULL,
empty => DACCLK_FIFO_EMPTY,
wr_clk => clk_PANDA,
din => FIFO_WR_DATA,
wr_en => FIFO_WR_EN,
rd_clk => clk_62_5M,
rd_en => FAST_DAC_RD_EN,
dout => FIFO_DATAOUT,
rd_data_count => DAC_FIFO_RD_COUNT,
wr_data_count => DAC_FIFO_WR_COUNT
);
PCAP_WRITE_FIFO : process(clk_PANDA)
begin
if rising_edge(clk_PANDA) then
if unsigned(DAC_FIFO_WR_COUNT) < 1 then
FIFO_WR_EN <= '1';
else
FIFO_WR_EN <= '0';
end if;
end if;
end process;
FIFO_WR_DATA <= DAC_DATAIN;
--! Process to adjust the High Tide count depending on Data Packing
SAMPLE_IN_DATA_FIFO: process(DATA_SIZE,DAC_FIFO_RD_COUNT,DACCLK_FIFO_EMPTY)
begin
if DATA_SIZE = '0' then -- packed 2 counts per sample
if unsigned(DAC_FIFO_RD_COUNT) > 1 and DACCLK_FIFO_EMPTY = '0' then
DACCLK_FIFO_AVAIL <= '1';
else
DACCLK_FIFO_AVAIL <= '0';
end if;
else -- unpacked 4 counts per sample
if unsigned(DAC_FIFO_RD_COUNT) > 3 and DACCLK_FIFO_EMPTY = '0' then
DACCLK_FIFO_AVAIL <= '1';
else
DACCLK_FIFO_AVAIL <= '0';
end if;
end if;
end process SAMPLE_IN_DATA_FIFO;
--! This process is used to cross from the PandA to the DAC Clock domains for register bits that are required in the other domain.
Cross_Clock_Buffer : Process(clk_62_5M)
begin
if Rising_Edge(clk_62_5M) then
DAC_CLK_DIV <= DAC_CLKDIV_REG(15 downto 0);
DAC_ENABLE_a <= DAC_ENABLE_REG(0);
DAC_ENABLE <= DAC_ENABLE_A;
end if;
end process;
-- Decode of Register Control bits
DAC_RESET <= DAC_RESET_REG(0);
DAC_FIFO_ENABLE <= DAC_FIFO_ENABLE_REG(0);
DAC_FIFO_RESET <= DAC_FIFO_RESET_REG(0);
DATA_SIZE <= '1'; --Always unpacked for DLS
-- Detect Rising Edge of RESET
RESET_RISING_DETECT : process(clk_PANDA)
begin
if rising_edge(clk_PANDA) then
DAC_RESET_d0 <= DAC_RESET;
if DAC_RESET = '0' and DAC_RESET_d0 = '1' then
DAC_RESET_FALLING <= '1';
else
DAC_RESET_FALLING <= '0';
end if;
DAC_RESET_FALLING_d0 <= DAC_RESET_FALLING;
DAC_RESET_FALLING_d1 <= DAC_RESET_FALLING_d0;
DAC_RESET_FALLING_d2 <= DAC_RESET_FALLING_d1;
end if;
end process RESET_RISING_DETECT;
DAC_RESET_FALLING_STRETCH <= DAC_RESET_FALLING or DAC_RESET_FALLING_d0 or DAC_RESET_FALLING_d1 or DAC_RESET_FALLING_d2;
-- Deal with DAC SPI Initialisation in HW
--! This process describes the state update on each clock transition
process (clk_62_5M)
begin
if Rising_edge(clk_62_5M) then
CONTROL_STATE <= NEXT_CONTROL_STATE;
end if;
end process ;
GENERATE_DAC_INIT_COUNT : process (clk_62_5M)
begin
if Rising_edge(clk_62_5M) then
if CONTROL_STATE = WAIT0 or CONTROL_STATE = WAIT1 or CONTROL_STATE = WAIT2 then
DAC_INIT_COUNTER <= DAC_INIT_COUNTER - 1;
else
DAC_INIT_COUNTER <= "11111111111";
end if;
end if;
end process GENERATE_DAC_INIT_COUNT;
DAC_SPI_INIT_STATE_MACHINE: process (CONTROL_STATE,DAC_ENABLE,DAC_RESET,DAC_RESET_FALLING_STRETCH,CONTROL_WRITE_COMPL,DAC_INIT_COUNTER)
begin
NEXT_CONTROL_STATE <= CONTROL_STATE;
case CONTROL_STATE is
when IDLE =>
if DAC_ENABLE = '0' and DAC_RESET_FALLING_STRETCH = '1' then -- Start the Sequence when DACs come out of reset
NEXT_CONTROL_STATE <= WAIT0;
end if;
when WAIT0 =>
if DAC_INIT_COUNTER = 0 then
NEXT_CONTROL_STATE <= CW1;
end if;
when CW1 =>
if CONTROL_WRITE_COMPL = '1' then
NEXT_CONTROL_STATE <= WAIT1;
end if;
when WAIT1 =>
if DAC_INIT_COUNTER = 0 then
NEXT_CONTROL_STATE <= CW2;
end if;
when CW2 =>
if CONTROL_WRITE_COMPL = '1' then
NEXT_CONTROL_STATE <= WAIT2;
end if;
when WAIT2 =>
if DAC_INIT_COUNTER = 0 then
NEXT_CONTROL_STATE <= CW3;
end if;
when CW3 =>
if DAC_RESET = '1' then
NEXT_CONTROL_STATE <= IDLE;
end if;
end case;
end process DAC_SPI_INIT_STATE_MACHINE;
DAC_SPI_INIT_OUTPUTS : process (clk_62_5M)
begin
if Rising_edge(clk_62_5M) then
case CONTROL_STATE is
when IDLE =>
CONTROL_WRITE <= '0';
SPI_CONTROL_DATA <= x"000000";
when WAIT0 =>
CONTROL_WRITE <= '0';
SPI_CONTROL_DATA <= x"300000";
when CW1 =>
CONTROL_WRITE <= '1';
SPI_CONTROL_DATA <= x"300000";
when WAIT1 =>
CONTROL_WRITE <= '0';
SPI_CONTROL_DATA <= x"400002";
when CW2 =>
CONTROL_WRITE <= '1';
SPI_CONTROL_DATA <= x"400002";
when WAIT2 =>
CONTROL_WRITE <= '0';
SPI_CONTROL_DATA <= x"200000";
when CW3 =>
CONTROL_WRITE <= '1';
SPI_CONTROL_DATA <= x"200000";
end case;
end if;
end process DAC_SPI_INIT_OUTPUTS;
--*************************************************************************************************************************
-- clk_62_5M Domain
--*************************************************************************************************************************
--! Sync the DAC_RESET to the selected Clock
--DAC_RESET_RESYNC: process(clk_62_5M,DAC_RESET) --GBC:20190321
DAC_RESET_RESYNC: process(clk_62_5M)
begin
if Rising_edge(clk_62_5M) then
CLK_SEL_DAC_RESET <= DAC_RESET;
end if;
end process DAC_RESET_RESYNC;
-- OK a Key part here is that the Sync MUST be synchronous with the selected divider clock so in theory no need to sync it it's a don't care for the Internal Reset
CLKDIV_COUNTER_RESET <= '1' when CLK_SEL_DAC_RESET = '1' else '0';
--! This Process Described the Main Divider
--MAINDIV: process (clk_62_5M, DAC_CLK_DIV) --GBC:20190321
MAINDIV: process (clk_62_5M)
begin
--DIVIDE2 <= std_logic_vector(unsigned('0' & DAC_CLK_DIV(15 downto 1)) + 1); --GBC:20190321
if Rising_edge(clk_62_5M) then
if CLKDIV_COUNTER_RESET = '1' then
CLKDIV_COUNTER <= DAC_CLK_DIV;
elsif CLKDIV_COUNTER = X"0001" then
CLKDIV_COUNTER <= DAC_CLK_DIV; -- Normal Reload
else
CLKDIV_COUNTER <= std_logic_vector(unsigned(CLKDIV_COUNTER) - 1); -- Count Down
end if;
end if;
end process MAINDIV;
--! This Process describes the clock output
CLKOUTPUT: process (clk_62_5M)
variable DIVIDE2 : std_logic_vector(15 downto 0);
begin
if Rising_edge(clk_62_5M) then
DIVIDE2 := std_logic_vector(unsigned('0' & DAC_CLK_DIV(15 downto 1)) + 1);
if CLKDIV_COUNTER_RESET = '1' then
s_CLK_GEN_CLK <= '0';
elsif CLKDIV_COUNTER = DIVIDE2 then
s_CLK_GEN_CLK <= '0';
elsif CLKDIV_COUNTER = X"0001" then
s_CLK_GEN_CLK <= '1';
end if;
end if;
end process CLKOUTPUT;
--! This process controls the bypass should the divider be set to 0
BYPASS_DIVIDER: process(DAC_CLK_DIV,clk_62_5M,s_CLK_GEN_CLK)
begin
if DAC_CLK_DIV = x"0001" then
DIV_CLK <= clk_62_5M;
-- DIV_CLK_SEL <= '0';
else
DIV_CLK <= s_CLK_GEN_CLK;
-- DIV_CLK_SEL <= '1';
end if;
end process BYPASS_DIVIDER;
--CLOCK_EST_THECLK_IN <= DIV_CLK; --GBC:20190321
-- Detect the rising edge of the Sample Clock to synchronise all counters too
CLK_DIV_RISING_EDGE: process(clk_62_5M,DIV_CLK_d0,DIV_CLK)
begin
if Rising_edge(clk_62_5M) then
DIV_CLK_d0 <= DIV_CLK;
end if;
if DIV_CLK = '1' and DIV_CLK_d0 = '0' then
DIV_CLK_RISING <= '1';
else
DIV_CLK_RISING <= '0';
end if;
end process CLK_DIV_RISING_EDGE;
--! Set CONV_ACTIVE the main control for writing into the data FIFO
SET_CON_ACTIVE: process(clk_62_5M)
begin
if Rising_edge(clk_62_5M) then
if DIV_CLK_RISING = '1' then
if DAC_ENABLE = '1' then
CONV_ACTIVE <= '1';
else
CONV_ACTIVE <= '0';
end if;
end if;
end if;
end process SET_CON_ACTIVE;
--GBC:20190321
--! Simple Counter that allows the software to Estimate a Clock Frequency
--THE_CLOCK_ESTIMATOR: process(clk_62_5M)
--begin
-- if Rising_edge(clk_62_5M) then
-- CLOCK_EST_d1 <= CLOCK_EST_d0;
-- CLOCK_EST_d0 <= CLOCK_EST_THECLK_IN;
-- if CLOCK_EST_D0 = '1' and CLOCK_EST_D1 = '0' then
-- CLOCK_EST_COUNTER <= CLOCK_EST_COUNTER + 1;
-- end if;
-- end if;
--end process THE_CLOCK_ESTIMATOR;
--! Simple Counter that counts the number of Samples acquired since CONV_ACTIVE
--THE_SAMPLE_COUNTER: process(clk_62_5M)
--begin
-- if Rising_edge(clk_62_5M) then
-- if DIV_CLK_RISING = '1' then
-- if CONV_ACTIVE = '0' then
-- SAMPLE_COUNTER <= (others => '0');
-- else
-- SAMPLE_COUNTER <= SAMPLE_COUNTER + 1;
-- end if;
-- end if;
-- end if;
--end process THE_SAMPLE_COUNTER;
--************************************************************************************************************************
-- Clock Domain Crossing clk_PANDA for read back
--*************************************************************************************************************************
--! De-bounce the counters against the PandA clock to ensure no meta-stable bits in the software read
--DEBOUNCE_THE_COUNTER: process(clk_PANDA)
--begin
-- if Rising_edge(clk_PANDA) then
-- CLOCK_EST_COUNTER_LATCH <= std_logic_vector(CLOCK_EST_COUNTER);
-- SAMPLE_COUNTER_LATCH <= std_logic_vector(SAMPLE_COUNTER);
-- end if;
--end process DEBOUNCE_THE_COUNTER;
--GBC:20190321
-- Half PandA clock to derive D-TACQ standard comparable logic clock rate. This is then halfed again at the SPI level to produce DAC SPI Clock
HALFPANDA_CLK : process (clk_PANDA)
begin
if Rising_edge(clk_PANDA) then
clk_62_5M_raw <= not clk_62_5M_raw;
end if;
end process HALFPANDA_CLK;
SEL_CLK_SEL : BUFG
port map (
O => clk_62_5M,
I => clk_62_5M_raw);
clk_DAC_IOB <= clk_62_5M;
--! DAC SPI Logic
THE_AO420FMC : entity work.ACQ427FMC_DAC_SPI(RTL)
port map (
clk_SPI => clk_62_5M, --! 62.5 MHz source clock to be used as SPI Clock for the DACs
DAC_RESET => DAC_RESET, --! Reset the DACs to their Power on State
DATA_SIZE => DATA_SIZE, --! Pack data in 32/16 bits
FIFO_AVAIL => DACCLK_FIFO_AVAIL, --! Data Available in the FIFO
DAC_ENABLE => DAC_ENABLE, --! Enable the DAC Sub-System
CONV_ACTIVE => CONV_ACTIVE, --! Enable and Triggered of the DAC Sub-System
LOW_LATENCY => '0', --! Low Latency do not wait for Sample Clock
FIFO_DATAOUT => FIFO_DATAOUT, --! DAC Data From FIFO
DAC_DATA_RD => DAC_DATA_RD, --! DAC Read Next Sample From FIFO
DAC_CNV_CLK => DIV_CLK, --! DAC Convert Clock
CONTROL_WRITE => CONTROL_WRITE, --! Write Control Data
CONTROL_WRITE_COMPL => CONTROL_WRITE_COMPL, --! Write Control Data Complete
SPI_CONTROL_DATA => SPI_CONTROL_DATA, --! DAC Control Register Write Data
CONTROL_READ => DACCLK_CONTROL_READ, --! Read Control Data
CONTROL_READ_COMPL => CONTROL_READ_COMPL, --! Write Control Data Complete
CONTROL_READBACK => CONTROL_READBACK, --! DAC Control Register ReadBack
-- I/Os to DACs
DAC_SPI_CLK => DAC_SPI_CLK, --! DAC SPI Clock
DAC_SDI => DAC_SDI, --! DAC SPI Data In
DAC_SDO => DAC_SDO, --! DAC SPI Data Out
DAC_SYNC_n => DAC_SYNC_n, --! DAC SPI SYNC
DAC_LD_n => DAC_LD_n, --! DAC Load
DAC_RST_n => DAC_RST_n --! DAC Reset
);
end RTL;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/uz_pmsm_model/uz_pmsm_model_src_nfp_convert_single2double.vhd
-- Created: 2021-07-23 16:45:56
--
-- Generated by MATLAB 9.10 and HDL Coder 3.18
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: uz_pmsm_model_src_nfp_convert_single2double
-- Source Path: uz_pmsm_model/uz_pmsm_model/nfp_convert_single2double
-- Hierarchy Level: 1
--
-- {Latency Strategy = "Min"}
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY uz_pmsm_model_src_nfp_convert_single2double IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
nfp_in : IN std_logic_vector(31 DOWNTO 0); -- ufix32
nfp_out : OUT std_logic_vector(63 DOWNTO 0) -- ufix64
);
END uz_pmsm_model_src_nfp_convert_single2double;
ARCHITECTURE rtl OF uz_pmsm_model_src_nfp_convert_single2double IS
-- Signals
SIGNAL Delay1_ctrl_const_out : std_logic; -- ufix1
SIGNAL Delay1_ctrl_delay_out : std_logic; -- ufix1
SIGNAL Delay1_Initial_Val_out : std_logic; -- ufix1
SIGNAL Constant8_out1 : std_logic; -- ufix1
SIGNAL Delay4_ctrl_const_out : std_logic; -- ufix1
SIGNAL Delay4_ctrl_delay_out : std_logic; -- ufix1
SIGNAL Delay4_Initial_Val_out : std_logic; -- ufix1
SIGNAL Constant7_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Relational_Operator_out1 : std_logic; -- ufix1
SIGNAL Delay4_out1 : std_logic; -- ufix1
SIGNAL Logical_Operator_out1 : std_logic; -- ufix1
SIGNAL Data_Type_Conversion_out1 : std_logic; -- ufix1
SIGNAL Add_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Delay3_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Add_add_cast : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Relational_Operator_relop1 : std_logic;
SIGNAL Delay1_out1 : std_logic; -- ufix1
SIGNAL nfp_in_unsigned : unsigned(31 DOWNTO 0); -- ufix32
SIGNAL inSign : std_logic; -- ufix1
SIGNAL inExponent : unsigned(7 DOWNTO 0); -- uint8
SIGNAL inMantissa : unsigned(22 DOWNTO 0); -- ufix23
SIGNAL Delay12_PS_2_4_reg : std_logic_vector(0 TO 2); -- ufix1 [3]
SIGNAL Delay12_PS_2_4_reg_next : std_logic_vector(0 TO 2); -- ufix1 [3]
SIGNAL Delay12_PS_2_4_out1 : std_logic; -- ufix1
SIGNAL Constant1_out1 : std_logic; -- ufix1
SIGNAL Switch1_out1 : std_logic; -- ufix1
SIGNAL Delay1_PS_1_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL inExponent_inType_Exponent_out1 : std_logic; -- ufix1
SIGNAL Delay13_PS_2_4_reg : std_logic_vector(0 TO 1); -- ufix1 [2]
SIGNAL Delay13_PS_2_4_reg_next : std_logic_vector(0 TO 1); -- ufix1 [2]
SIGNAL Delay13_PS_2_4_out1 : std_logic; -- ufix1
SIGNAL inExponent_0_out1 : std_logic; -- ufix1
SIGNAL Delay2_PS_1_out1 : unsigned(22 DOWNTO 0); -- ufix23
SIGNAL inMantissa_0_out1 : std_logic; -- ufix1
SIGNAL alphainExponent_0_inMantis_out1 : std_logic; -- ufix1
SIGNAL Delay14_PS_2_4_reg : std_logic_vector(0 TO 1); -- ufix1 [2]
SIGNAL Delay14_PS_2_4_reg_next : std_logic_vector(0 TO 1); -- ufix1 [2]
SIGNAL Delay14_PS_2_4_out1 : std_logic; -- ufix1
SIGNAL Exponent_0_out1 : std_logic; -- ufix1
SIGNAL C_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL if_Exponent_0_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL Delay8_PS_2_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL inType_ExponentBias_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL int32_storedInteger_ExpCorrect_sub_cast : signed(8 DOWNTO 0); -- sfix9
SIGNAL int32_storedInteger_ExpCorrect_sub_cast_1 : signed(8 DOWNTO 0); -- sfix9
SIGNAL int32_storedInteger_ExpCorrect_out1 : signed(10 DOWNTO 0); -- sfix11
SIGNAL Delay18_PS_3_out1 : signed(10 DOWNTO 0); -- sfix11
SIGNAL cfType_ExponentBias_out1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL int32_storedInteger_ExpCorrect_add_cast : signed(12 DOWNTO 0); -- sfix13
SIGNAL int32_storedInteger_ExpCorrect_add_temp : signed(12 DOWNTO 0); -- sfix13
SIGNAL int32_storedInteger_ExpCorrect_out1_1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL uint8_MantAppended_x_WordLengt_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Exponent_0_out1_1 : std_logic; -- ufix1
SIGNAL cfType_Exponent_Inf_or_NaN_out1 : std_logic; -- ufix1
SIGNAL alphaExponent_0_cfType_Exp_out1 : std_logic; -- ufix1
SIGNAL alpha1_out1 : std_logic; -- ufix1
SIGNAL Bit_Concat1_out1 : unsigned(23 DOWNTO 0); -- ufix24
SIGNAL alpha0_out1 : std_logic; -- ufix1
SIGNAL Bit_Concat_out1 : unsigned(23 DOWNTO 0); -- ufix24
SIGNAL if_Exponent_0_cfType_Exp_out1 : unsigned(23 DOWNTO 0); -- ufix24
SIGNAL Delay7_PS_2_out1 : unsigned(23 DOWNTO 0); -- ufix24
SIGNAL Bit_Slice6_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL Bit_Slice16_out1 : std_logic; -- ufix1
SIGNAL Bit_Slice15_out1 : std_logic; -- ufix1
SIGNAL Logical_Operator5_out1 : std_logic; -- ufix1
SIGNAL Bit_Slice14_out1 : std_logic; -- ufix1
SIGNAL Bit_Slice13_out1 : std_logic; -- ufix1
SIGNAL Logical_Operator7_out1 : std_logic; -- ufix1
SIGNAL Logical_Operator6_out1 : std_logic; -- ufix1
SIGNAL Bit_Slice12_out1 : std_logic; -- ufix1
SIGNAL Bit_Slice11_out1 : std_logic; -- ufix1
SIGNAL Logical_Operator4_out1 : std_logic; -- ufix1
SIGNAL Bit_Slice10_out1 : std_logic; -- ufix1
SIGNAL Bit_Slice9_out1 : std_logic; -- ufix1
SIGNAL Logical_Operator14_out1 : std_logic; -- ufix1
SIGNAL Logical_Operator13_out1 : std_logic; -- ufix1
SIGNAL Bit_Slice1_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL Bit_Slice16_out1_1 : std_logic; -- ufix1
SIGNAL Bit_Slice15_out1_1 : std_logic; -- ufix1
SIGNAL Logical_Operator5_out1_1 : std_logic; -- ufix1
SIGNAL Bit_Slice14_out1_1 : std_logic; -- ufix1
SIGNAL Bit_Slice13_out1_1 : std_logic; -- ufix1
SIGNAL Logical_Operator7_out1_1 : std_logic; -- ufix1
SIGNAL Logical_Operator6_out1_1 : std_logic; -- ufix1
SIGNAL Bit_Slice12_out1_1 : std_logic; -- ufix1
SIGNAL Bit_Slice11_out1_1 : std_logic; -- ufix1
SIGNAL Logical_Operator4_out1_1 : std_logic; -- ufix1
SIGNAL Bit_Slice10_out1_1 : std_logic; -- ufix1
SIGNAL Bit_Slice9_out1_1 : std_logic; -- ufix1
SIGNAL Logical_Operator14_out1_1 : std_logic; -- ufix1
SIGNAL Logical_Operator13_out1_1 : std_logic; -- ufix1
SIGNAL Bit_Slice4_out1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL Bit_Slice8_out1 : std_logic; -- ufix1
SIGNAL Bit_Slice7_out1 : std_logic; -- ufix1
SIGNAL Logical_Operator1_out1 : std_logic; -- ufix1
SIGNAL Bit_Slice6_out1_1 : std_logic; -- ufix1
SIGNAL Bit_Slice5_out1 : std_logic; -- ufix1
SIGNAL Logical_Operator3_out1 : std_logic; -- ufix1
SIGNAL Bit_Slice3_out1 : std_logic; -- ufix1
SIGNAL Bit_Slice2_out1 : std_logic; -- ufix1
SIGNAL Bit_Slice4_out1_1 : std_logic; -- ufix1
SIGNAL Constant_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Bit_Slice1_out1_1 : std_logic; -- ufix1
SIGNAL Constant1_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch2_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Logical_Operator_out1_1 : std_logic; -- ufix1
SIGNAL Constant2_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch1_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant3_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant4_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Logical_Operator2_out1 : std_logic; -- ufix1
SIGNAL Switch3_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch4_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant5_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant6_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch6_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant7_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant8_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch8_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Logical_Operator12_out1 : std_logic; -- ufix1
SIGNAL Switch9_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch10_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant9_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant10_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch12_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant11_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant12_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch15_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch16_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant13_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant14_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch18_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant15_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant16_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch20_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch21_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Logical_Operator12_out1_1 : std_logic; -- ufix1
SIGNAL Switch13_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant9_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant10_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch12_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant11_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant12_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch15_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch16_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant13_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant14_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch18_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant15_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Constant16_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch20_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch21_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch13_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Switch1_out1_2 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL Delay17_PS_3_out1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL uint8_MantAppended_x_WordLengt_sub_cast : signed(6 DOWNTO 0); -- sfix7
SIGNAL uint8_MantAppended_x_WordLengt_sub_cast_1 : signed(6 DOWNTO 0); -- sfix7
SIGNAL uint8_MantAppended_x_WordLengt_sub_temp : signed(6 DOWNTO 0); -- sfix7
SIGNAL uint8_MantAppended_x_WordLengt_out1_1 : unsigned(5 DOWNTO 0); -- ufix6
SIGNAL DTC2_out1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL e_int32_shift_length_sub_cast : signed(11 DOWNTO 0); -- sfix12
SIGNAL e_int32_shift_length_sub_cast_1 : signed(11 DOWNTO 0); -- sfix12
SIGNAL e_int32_shift_length_sub_temp : signed(11 DOWNTO 0); -- sfix12
SIGNAL e_int32_shift_length_out1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL C11_out1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL if_inExponent_0_inMantis_Exponent_out1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL C12_out1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL if_inExponent_inType_Exponent_Exponent_out1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL Constant2_out1_1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL Switch5_out1 : unsigned(10 DOWNTO 0); -- ufix11
SIGNAL Delay16_PS_3_out1 : unsigned(23 DOWNTO 0); -- ufix24
SIGNAL bitsll_MantAppended_x_shift_l_out1 : unsigned(23 DOWNTO 0); -- ufix24
SIGNAL alpha0_out1_1 : unsigned(29 DOWNTO 0); -- ufix30
SIGNAL Bit_Concat_out1_1 : unsigned(53 DOWNTO 0); -- ufix54
SIGNAL Bit_Slice_out1 : unsigned(51 DOWNTO 0); -- ufix52
SIGNAL C13_out1 : unsigned(51 DOWNTO 0); -- ufix52
SIGNAL if_inExponent_0_inMantis_Mantissa_out1 : unsigned(51 DOWNTO 0); -- ufix52
SIGNAL Constant_out1_1 : unsigned(28 DOWNTO 0); -- ufix29
SIGNAL Delay6_PS_2_out1 : unsigned(22 DOWNTO 0); -- ufix23
SIGNAL Bit_Concat1_out1_1 : unsigned(51 DOWNTO 0); -- ufix52
SIGNAL Delay15_PS_3_out1 : unsigned(51 DOWNTO 0); -- ufix52
SIGNAL if_inExponent_inType_Exponent_Mantissa_out1 : unsigned(51 DOWNTO 0); -- ufix52
SIGNAL Constant3_out1_1 : unsigned(51 DOWNTO 0); -- ufix52
SIGNAL Switch6_out1_1 : unsigned(51 DOWNTO 0); -- ufix52
SIGNAL nfp_out_pack : unsigned(63 DOWNTO 0); -- ufix64
BEGIN
Delay1_ctrl_const_out <= '1';
Delay1_ctrl_delay_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay1_ctrl_delay_out <= '0';
ELSIF enb = '1' THEN
Delay1_ctrl_delay_out <= Delay1_ctrl_const_out;
END IF;
END IF;
END PROCESS Delay1_ctrl_delay_process;
Delay1_Initial_Val_out <= '1';
Constant8_out1 <= '1';
Delay4_ctrl_const_out <= '1';
Delay4_ctrl_delay_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay4_ctrl_delay_out <= '0';
ELSIF enb = '1' THEN
Delay4_ctrl_delay_out <= Delay4_ctrl_const_out;
END IF;
END IF;
END PROCESS Delay4_ctrl_delay_process;
Delay4_Initial_Val_out <= '1';
Constant7_out1 <= to_unsigned(16#02#, 6);
Delay4_out1 <= Delay4_Initial_Val_out WHEN Delay4_ctrl_delay_out = '0' ELSE
Relational_Operator_out1;
Logical_Operator_out1 <= Constant8_out1 AND Delay4_out1;
Data_Type_Conversion_out1 <= Logical_Operator_out1;
Delay3_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay3_out1 <= to_unsigned(16#00#, 6);
ELSIF enb = '1' THEN
Delay3_out1 <= Add_out1;
END IF;
END IF;
END PROCESS Delay3_process;
Add_add_cast <= '0' & '0' & '0' & '0' & '0' & Data_Type_Conversion_out1;
Add_out1 <= Delay3_out1 + Add_add_cast;
Relational_Operator_relop1 <= '1' WHEN Add_out1 <= Constant7_out1 ELSE
'0';
reduced_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Relational_Operator_out1 <= '0';
ELSIF enb = '1' THEN
Relational_Operator_out1 <= Relational_Operator_relop1;
END IF;
END IF;
END PROCESS reduced_process;
Delay1_out1 <= Delay1_Initial_Val_out WHEN Delay1_ctrl_delay_out = '0' ELSE
Relational_Operator_out1;
nfp_in_unsigned <= unsigned(nfp_in);
-- Split 32 bit word into FP sign, exponent, mantissa
inSign <= nfp_in_unsigned(31);
inExponent <= nfp_in_unsigned(30 DOWNTO 23);
inMantissa <= nfp_in_unsigned(22 DOWNTO 0);
Delay12_PS_2_4_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay12_PS_2_4_reg(0) <= '0';
Delay12_PS_2_4_reg(1) <= '0';
Delay12_PS_2_4_reg(2) <= '0';
ELSIF enb = '1' THEN
Delay12_PS_2_4_reg(0) <= Delay12_PS_2_4_reg_next(0);
Delay12_PS_2_4_reg(1) <= Delay12_PS_2_4_reg_next(1);
Delay12_PS_2_4_reg(2) <= Delay12_PS_2_4_reg_next(2);
END IF;
END IF;
END PROCESS Delay12_PS_2_4_process;
Delay12_PS_2_4_out1 <= Delay12_PS_2_4_reg(2);
Delay12_PS_2_4_reg_next(0) <= inSign;
Delay12_PS_2_4_reg_next(1) <= Delay12_PS_2_4_reg(0);
Delay12_PS_2_4_reg_next(2) <= Delay12_PS_2_4_reg(1);
Constant1_out1 <= '0';
Switch1_out1 <= Delay12_PS_2_4_out1 WHEN Delay1_out1 = '0' ELSE
Constant1_out1;
Delay1_PS_1_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay1_PS_1_out1 <= to_unsigned(16#00#, 8);
ELSIF enb = '1' THEN
Delay1_PS_1_out1 <= inExponent;
END IF;
END IF;
END PROCESS Delay1_PS_1_process;
inExponent_inType_Exponent_out1 <= '1' WHEN Delay1_PS_1_out1 = to_unsigned(16#FF#, 8) ELSE
'0';
Delay13_PS_2_4_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay13_PS_2_4_reg(0) <= '0';
Delay13_PS_2_4_reg(1) <= '0';
ELSIF enb = '1' THEN
Delay13_PS_2_4_reg(0) <= Delay13_PS_2_4_reg_next(0);
Delay13_PS_2_4_reg(1) <= Delay13_PS_2_4_reg_next(1);
END IF;
END IF;
END PROCESS Delay13_PS_2_4_process;
Delay13_PS_2_4_out1 <= Delay13_PS_2_4_reg(1);
Delay13_PS_2_4_reg_next(0) <= inExponent_inType_Exponent_out1;
Delay13_PS_2_4_reg_next(1) <= Delay13_PS_2_4_reg(0);
inExponent_0_out1 <= '1' WHEN Delay1_PS_1_out1 = to_unsigned(16#00#, 8) ELSE
'0';
Delay2_PS_1_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay2_PS_1_out1 <= to_unsigned(16#000000#, 23);
ELSIF enb = '1' THEN
Delay2_PS_1_out1 <= inMantissa;
END IF;
END IF;
END PROCESS Delay2_PS_1_process;
inMantissa_0_out1 <= '1' WHEN Delay2_PS_1_out1 = to_unsigned(16#000000#, 23) ELSE
'0';
alphainExponent_0_inMantis_out1 <= inExponent_0_out1 AND inMantissa_0_out1;
Delay14_PS_2_4_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay14_PS_2_4_reg(0) <= '0';
Delay14_PS_2_4_reg(1) <= '0';
ELSIF enb = '1' THEN
Delay14_PS_2_4_reg(0) <= Delay14_PS_2_4_reg_next(0);
Delay14_PS_2_4_reg(1) <= Delay14_PS_2_4_reg_next(1);
END IF;
END IF;
END PROCESS Delay14_PS_2_4_process;
Delay14_PS_2_4_out1 <= Delay14_PS_2_4_reg(1);
Delay14_PS_2_4_reg_next(0) <= alphainExponent_0_inMantis_out1;
Delay14_PS_2_4_reg_next(1) <= Delay14_PS_2_4_reg(0);
Exponent_0_out1 <= '1' WHEN Delay1_PS_1_out1 = to_unsigned(16#00#, 8) ELSE
'0';
C_out1 <= to_unsigned(16#01#, 8);
if_Exponent_0_out1 <= Delay1_PS_1_out1 WHEN Exponent_0_out1 = '0' ELSE
C_out1;
Delay8_PS_2_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay8_PS_2_out1 <= to_unsigned(16#00#, 8);
ELSIF enb = '1' THEN
Delay8_PS_2_out1 <= if_Exponent_0_out1;
END IF;
END IF;
END PROCESS Delay8_PS_2_process;
inType_ExponentBias_out1 <= to_unsigned(16#7F#, 8);
int32_storedInteger_ExpCorrect_sub_cast <= signed(resize(Delay8_PS_2_out1, 9));
int32_storedInteger_ExpCorrect_sub_cast_1 <= signed(resize(inType_ExponentBias_out1, 9));
int32_storedInteger_ExpCorrect_out1 <= resize(int32_storedInteger_ExpCorrect_sub_cast - int32_storedInteger_ExpCorrect_sub_cast_1, 11);
Delay18_PS_3_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay18_PS_3_out1 <= to_signed(16#000#, 11);
ELSIF enb = '1' THEN
Delay18_PS_3_out1 <= int32_storedInteger_ExpCorrect_out1;
END IF;
END IF;
END PROCESS Delay18_PS_3_process;
cfType_ExponentBias_out1 <= to_unsigned(16#3FF#, 11);
int32_storedInteger_ExpCorrect_add_cast <= signed(resize(cfType_ExponentBias_out1, 13));
int32_storedInteger_ExpCorrect_add_temp <= resize(Delay18_PS_3_out1, 13) + int32_storedInteger_ExpCorrect_add_cast;
int32_storedInteger_ExpCorrect_out1_1 <= unsigned(int32_storedInteger_ExpCorrect_add_temp(10 DOWNTO 0));
uint8_MantAppended_x_WordLengt_out1 <= to_unsigned(16#18#, 6);
Exponent_0_out1_1 <= '1' WHEN Delay1_PS_1_out1 = to_unsigned(16#00#, 8) ELSE
'0';
cfType_Exponent_Inf_or_NaN_out1 <= '1' WHEN Delay1_PS_1_out1 = to_unsigned(16#FF#, 8) ELSE
'0';
alphaExponent_0_cfType_Exp_out1 <= Exponent_0_out1_1 OR cfType_Exponent_Inf_or_NaN_out1;
alpha1_out1 <= '1';
Bit_Concat1_out1 <= alpha1_out1 & Delay2_PS_1_out1;
alpha0_out1 <= '0';
Bit_Concat_out1 <= alpha0_out1 & Delay2_PS_1_out1;
if_Exponent_0_cfType_Exp_out1 <= Bit_Concat1_out1 WHEN alphaExponent_0_cfType_Exp_out1 = '0' ELSE
Bit_Concat_out1;
Delay7_PS_2_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay7_PS_2_out1 <= to_unsigned(16#000000#, 24);
ELSIF enb = '1' THEN
Delay7_PS_2_out1 <= if_Exponent_0_cfType_Exp_out1;
END IF;
END IF;
END PROCESS Delay7_PS_2_process;
Bit_Slice6_out1 <= Delay7_PS_2_out1(23 DOWNTO 16);
Bit_Slice16_out1 <= Bit_Slice6_out1(7);
Bit_Slice15_out1 <= Bit_Slice6_out1(6);
Logical_Operator5_out1 <= Bit_Slice16_out1 OR Bit_Slice15_out1;
Bit_Slice14_out1 <= Bit_Slice6_out1(5);
Bit_Slice13_out1 <= Bit_Slice6_out1(4);
Logical_Operator7_out1 <= Bit_Slice14_out1 OR Bit_Slice13_out1;
Logical_Operator6_out1 <= Logical_Operator5_out1 OR Logical_Operator7_out1;
Bit_Slice12_out1 <= Bit_Slice6_out1(3);
Bit_Slice11_out1 <= Bit_Slice6_out1(2);
Logical_Operator4_out1 <= Bit_Slice12_out1 OR Bit_Slice11_out1;
Bit_Slice10_out1 <= Bit_Slice6_out1(1);
Bit_Slice9_out1 <= Bit_Slice6_out1(0);
Logical_Operator14_out1 <= Bit_Slice10_out1 OR Bit_Slice9_out1;
Logical_Operator13_out1 <= Logical_Operator4_out1 OR Logical_Operator14_out1;
Bit_Slice1_out1 <= Delay7_PS_2_out1(15 DOWNTO 8);
Bit_Slice16_out1_1 <= Bit_Slice1_out1(7);
Bit_Slice15_out1_1 <= Bit_Slice1_out1(6);
Logical_Operator5_out1_1 <= Bit_Slice16_out1_1 OR Bit_Slice15_out1_1;
Bit_Slice14_out1_1 <= Bit_Slice1_out1(5);
Bit_Slice13_out1_1 <= Bit_Slice1_out1(4);
Logical_Operator7_out1_1 <= Bit_Slice14_out1_1 OR Bit_Slice13_out1_1;
Logical_Operator6_out1_1 <= Logical_Operator5_out1_1 OR Logical_Operator7_out1_1;
Bit_Slice12_out1_1 <= Bit_Slice1_out1(3);
Bit_Slice11_out1_1 <= Bit_Slice1_out1(2);
Logical_Operator4_out1_1 <= Bit_Slice12_out1_1 OR Bit_Slice11_out1_1;
Bit_Slice10_out1_1 <= Bit_Slice1_out1(1);
Bit_Slice9_out1_1 <= Bit_Slice1_out1(0);
Logical_Operator14_out1_1 <= Bit_Slice10_out1_1 OR Bit_Slice9_out1_1;
Logical_Operator13_out1_1 <= Logical_Operator4_out1_1 OR Logical_Operator14_out1_1;
Bit_Slice4_out1 <= Delay7_PS_2_out1(7 DOWNTO 0);
Bit_Slice8_out1 <= Bit_Slice4_out1(7);
Bit_Slice7_out1 <= Bit_Slice4_out1(6);
Logical_Operator1_out1 <= Bit_Slice8_out1 OR Bit_Slice7_out1;
Bit_Slice6_out1_1 <= Bit_Slice4_out1(5);
Bit_Slice5_out1 <= Bit_Slice4_out1(4);
Logical_Operator3_out1 <= Bit_Slice6_out1_1 OR Bit_Slice5_out1;
Bit_Slice3_out1 <= Bit_Slice4_out1(3);
Bit_Slice2_out1 <= Bit_Slice4_out1(2);
Bit_Slice4_out1_1 <= Bit_Slice4_out1(0);
Constant_out1 <= to_unsigned(16#00#, 6);
Bit_Slice1_out1_1 <= Bit_Slice4_out1(1);
Constant1_out1_1 <= to_unsigned(16#01#, 6);
Switch2_out1 <= Constant_out1 WHEN Bit_Slice4_out1_1 = '0' ELSE
Constant1_out1_1;
Logical_Operator_out1_1 <= Bit_Slice3_out1 OR Bit_Slice2_out1;
Constant2_out1 <= to_unsigned(16#02#, 6);
Switch1_out1_1 <= Switch2_out1 WHEN Bit_Slice1_out1_1 = '0' ELSE
Constant2_out1;
Constant3_out1 <= to_unsigned(16#03#, 6);
Constant4_out1 <= to_unsigned(16#04#, 6);
Logical_Operator2_out1 <= Logical_Operator1_out1 OR Logical_Operator3_out1;
Switch3_out1 <= Constant3_out1 WHEN Bit_Slice3_out1 = '0' ELSE
Constant4_out1;
Switch4_out1 <= Switch1_out1_1 WHEN Logical_Operator_out1_1 = '0' ELSE
Switch3_out1;
Constant5_out1 <= to_unsigned(16#05#, 6);
Constant6_out1 <= to_unsigned(16#06#, 6);
Switch6_out1 <= Constant5_out1 WHEN Bit_Slice6_out1_1 = '0' ELSE
Constant6_out1;
Constant7_out1_1 <= to_unsigned(16#07#, 6);
Constant8_out1_1 <= to_unsigned(16#08#, 6);
Switch8_out1 <= Constant7_out1_1 WHEN Bit_Slice8_out1 = '0' ELSE
Constant8_out1_1;
Logical_Operator12_out1 <= Logical_Operator6_out1_1 OR Logical_Operator13_out1_1;
Switch9_out1 <= Switch6_out1 WHEN Logical_Operator1_out1 = '0' ELSE
Switch8_out1;
Switch10_out1 <= Switch4_out1 WHEN Logical_Operator2_out1 = '0' ELSE
Switch9_out1;
Constant9_out1 <= to_unsigned(16#09#, 6);
Constant10_out1 <= to_unsigned(16#0A#, 6);
Switch12_out1 <= Constant9_out1 WHEN Bit_Slice10_out1_1 = '0' ELSE
Constant10_out1;
Constant11_out1 <= to_unsigned(16#0B#, 6);
Constant12_out1 <= to_unsigned(16#0C#, 6);
Switch15_out1 <= Constant11_out1 WHEN Bit_Slice12_out1_1 = '0' ELSE
Constant12_out1;
Switch16_out1 <= Switch12_out1 WHEN Logical_Operator4_out1_1 = '0' ELSE
Switch15_out1;
Constant13_out1 <= to_unsigned(16#0D#, 6);
Constant14_out1 <= to_unsigned(16#0E#, 6);
Switch18_out1 <= Constant13_out1 WHEN Bit_Slice14_out1_1 = '0' ELSE
Constant14_out1;
Constant15_out1 <= to_unsigned(16#0F#, 6);
Constant16_out1 <= to_unsigned(16#10#, 6);
Switch20_out1 <= Constant15_out1 WHEN Bit_Slice16_out1_1 = '0' ELSE
Constant16_out1;
Switch21_out1 <= Switch18_out1 WHEN Logical_Operator5_out1_1 = '0' ELSE
Switch20_out1;
Logical_Operator12_out1_1 <= Logical_Operator6_out1 OR Logical_Operator13_out1;
Switch13_out1 <= Switch16_out1 WHEN Logical_Operator6_out1_1 = '0' ELSE
Switch21_out1;
Switch_out1 <= Switch10_out1 WHEN Logical_Operator12_out1 = '0' ELSE
Switch13_out1;
Constant9_out1_1 <= to_unsigned(16#11#, 6);
Constant10_out1_1 <= to_unsigned(16#12#, 6);
Switch12_out1_1 <= Constant9_out1_1 WHEN Bit_Slice10_out1 = '0' ELSE
Constant10_out1_1;
Constant11_out1_1 <= to_unsigned(16#13#, 6);
Constant12_out1_1 <= to_unsigned(16#14#, 6);
Switch15_out1_1 <= Constant11_out1_1 WHEN Bit_Slice12_out1 = '0' ELSE
Constant12_out1_1;
Switch16_out1_1 <= Switch12_out1_1 WHEN Logical_Operator4_out1 = '0' ELSE
Switch15_out1_1;
Constant13_out1_1 <= to_unsigned(16#15#, 6);
Constant14_out1_1 <= to_unsigned(16#16#, 6);
Switch18_out1_1 <= Constant13_out1_1 WHEN Bit_Slice14_out1 = '0' ELSE
Constant14_out1_1;
Constant15_out1_1 <= to_unsigned(16#17#, 6);
Constant16_out1_1 <= to_unsigned(16#18#, 6);
Switch20_out1_1 <= Constant15_out1_1 WHEN Bit_Slice16_out1 = '0' ELSE
Constant16_out1_1;
Switch21_out1_1 <= Switch18_out1_1 WHEN Logical_Operator5_out1 = '0' ELSE
Switch20_out1_1;
Switch13_out1_1 <= Switch16_out1_1 WHEN Logical_Operator6_out1 = '0' ELSE
Switch21_out1_1;
Switch1_out1_2 <= Switch_out1 WHEN Logical_Operator12_out1_1 = '0' ELSE
Switch13_out1_1;
Delay17_PS_3_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay17_PS_3_out1 <= to_unsigned(16#00#, 6);
ELSIF enb = '1' THEN
Delay17_PS_3_out1 <= Switch1_out1_2;
END IF;
END IF;
END PROCESS Delay17_PS_3_process;
uint8_MantAppended_x_WordLengt_sub_cast <= signed(resize(uint8_MantAppended_x_WordLengt_out1, 7));
uint8_MantAppended_x_WordLengt_sub_cast_1 <= signed(resize(Delay17_PS_3_out1, 7));
uint8_MantAppended_x_WordLengt_sub_temp <= uint8_MantAppended_x_WordLengt_sub_cast - uint8_MantAppended_x_WordLengt_sub_cast_1;
uint8_MantAppended_x_WordLengt_out1_1 <= unsigned(uint8_MantAppended_x_WordLengt_sub_temp(5 DOWNTO 0));
DTC2_out1 <= resize(uint8_MantAppended_x_WordLengt_out1_1, 11);
e_int32_shift_length_sub_cast <= signed(resize(int32_storedInteger_ExpCorrect_out1_1, 12));
e_int32_shift_length_sub_cast_1 <= signed(resize(DTC2_out1, 12));
e_int32_shift_length_sub_temp <= e_int32_shift_length_sub_cast - e_int32_shift_length_sub_cast_1;
e_int32_shift_length_out1 <= unsigned(e_int32_shift_length_sub_temp(10 DOWNTO 0));
C11_out1 <= to_unsigned(16#000#, 11);
if_inExponent_0_inMantis_Exponent_out1 <= e_int32_shift_length_out1 WHEN Delay14_PS_2_4_out1 = '0' ELSE
C11_out1;
C12_out1 <= to_unsigned(16#7FF#, 11);
if_inExponent_inType_Exponent_Exponent_out1 <= if_inExponent_0_inMantis_Exponent_out1 WHEN Delay13_PS_2_4_out1 = '0' ELSE
C12_out1;
Constant2_out1_1 <= to_unsigned(16#000#, 11);
Switch5_out1 <= if_inExponent_inType_Exponent_Exponent_out1 WHEN Delay1_out1 = '0' ELSE
Constant2_out1_1;
Delay16_PS_3_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay16_PS_3_out1 <= to_unsigned(16#000000#, 24);
ELSIF enb = '1' THEN
Delay16_PS_3_out1 <= Delay7_PS_2_out1;
END IF;
END IF;
END PROCESS Delay16_PS_3_process;
bitsll_MantAppended_x_shift_l_out1 <= Delay16_PS_3_out1 sll to_integer(uint8_MantAppended_x_WordLengt_out1_1);
alpha0_out1_1 <= to_unsigned(16#00000000#, 30);
Bit_Concat_out1_1 <= bitsll_MantAppended_x_shift_l_out1 & alpha0_out1_1;
Bit_Slice_out1 <= Bit_Concat_out1_1(52 DOWNTO 1);
C13_out1 <= to_unsigned(0, 52);
if_inExponent_0_inMantis_Mantissa_out1 <= Bit_Slice_out1 WHEN Delay14_PS_2_4_out1 = '0' ELSE
C13_out1;
Constant_out1_1 <= to_unsigned(16#00000000#, 29);
Delay6_PS_2_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay6_PS_2_out1 <= to_unsigned(16#000000#, 23);
ELSIF enb = '1' THEN
Delay6_PS_2_out1 <= Delay2_PS_1_out1;
END IF;
END IF;
END PROCESS Delay6_PS_2_process;
Bit_Concat1_out1_1 <= Constant_out1_1 & Delay6_PS_2_out1;
Delay15_PS_3_process : PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF reset = '1' THEN
Delay15_PS_3_out1 <= to_unsigned(0, 52);
ELSIF enb = '1' THEN
Delay15_PS_3_out1 <= Bit_Concat1_out1_1;
END IF;
END IF;
END PROCESS Delay15_PS_3_process;
if_inExponent_inType_Exponent_Mantissa_out1 <= if_inExponent_0_inMantis_Mantissa_out1 WHEN Delay13_PS_2_4_out1 = '0' ELSE
Delay15_PS_3_out1;
Constant3_out1_1 <= to_unsigned(0, 52);
Switch6_out1_1 <= if_inExponent_inType_Exponent_Mantissa_out1 WHEN Delay1_out1 = '0' ELSE
Constant3_out1_1;
-- Combine FP sign, exponent, mantissa into 64 bit word
nfp_out_pack <= Switch1_out1 & Switch5_out1 & Switch6_out1_1;
nfp_out <= std_logic_vector(nfp_out_pack);
END rtl;
|
----------------------------------------------------------------------------
-- Entity: ScoreBoard
-- Written By: <NAME>
-- Date Created: December 12, 2020
-- Description: VHDL model of the score board for a Pong game
--
-- Revision History (date, initials, description):
--
-- Dependencies:
-- ScoreBoardFSM
-- ScoreBoardDatapath
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
----------------------------------------------------------------------------
entity ScoreBoard is
port (
P1POINT : in STD_LOGIC;
P2POINT : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
P1SCORE : out STD_LOGIC_VECTOR(7 downto 0);
P2SCORE : out STD_LOGIC_VECTOR(7 downto 0)
);
end entity;
----------------------------------------------------------------------------
architecture Structural of ScoreBoard is
component ScoreBoardFSM is
port (
P1POINT : in STD_LOGIC;
P2POINT : in STD_LOGIC;
EQU10 : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
LOADP1 : out STD_LOGIC;
LOADP2 : out STD_LOGIC;
P1ORP2 : out STD_LOGIC;
ADD1OR6 : out STD_LOGIC
);
end component;
component ScoreBoardDatapath is
port (
LOADP1 : in STD_LOGIC;
LOADP2 : in STD_LOGIC;
P1ORP2 : in STD_LOGIC;
ADD1OR6 : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
P1SCORE : out STD_LOGIC_VECTOR(7 downto 0);
P2SCORE : out STD_LOGIC_VECTOR(7 downto 0);
EQU10 : out STD_LOGIC
);
end component;
-- internal signals --
signal load_p1_int : STD_LOGIC;
signal load_p2_int : STD_LOGIC;
signal p1_or_p2_int : STD_LOGIC;
signal add_1_or_6_int : STD_LOGIC;
signal equ_10_int : STD_LOGIC;
begin
score_board_FSM_1: ScoreBoardFSM
port map (
P1POINT => P1POINT,
P2POINT => P2POINT,
EQU10 => equ_10_int,
CLK => CLK,
RESET => RESET,
LOADP1 => load_p1_int,
LOADP2 => load_p2_int,
P1ORP2 => p1_or_p2_int,
ADD1OR6 => add_1_or_6_int
);
score_board_datapath_1: ScoreBoardDatapath
port map (
LOADP1 => load_p1_int,
LOADP2 => load_p2_int,
P1ORP2 => p1_or_p2_int,
ADD1OR6 => add_1_or_6_int,
CLK => CLK,
RESET => RESET,
P1SCORE => P1SCORE,
P2SCORE => P2SCORE,
EQU10 => equ_10_int
);
end architecture;
|
-- *** MOCS-COPYRIGHT-NOTICE-BEGIN ***
--
-- This copyright notice is auto-generated by ./add-copyright-notice.
-- Additional copyright notices must be added below the last line of this notice.
--
-- MoCS (https://lewis.cs.uni-saarland.de/tools/mocs/): "vhdl/d.vhdl".
-- The content of this file is copyright of Saarland University -
-- Copyright (C) 2009 Saarland University, Reactive Systems Group, <NAME>.
--
-- This file is part of MoCS (https://lewis.cs.uni-saarland.de/tools/mocs/).
--
-- License: three-clause BSD style license.
-- The license text can be found in the file LICENSE.
--
-- *** MOCS-COPYRIGHT-NOTICE-END ***
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- A very simple D-flip-flop (I hope)
entity dff is
Port (CLOCK : in STD_LOGIC;
input : in STD_LOGIC;
output: out STD_LOGIC := '0');
end dff;
architecture Behavioral of dff is
begin
process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
output <= input;
end if;
end process;
end Behavioral;
|
<gh_stars>0
--------------------------------------------------------------------------------
-- __ _ _ _ --
-- / _(_) | | | | --
-- __ _ _ _ ___ ___ _ __ | |_ _ ___| | __| | --
-- / _` | | | |/ _ \/ _ \ '_ \| _| |/ _ \ |/ _` | --
-- | (_| | |_| | __/ __/ | | | | | | __/ | (_| | --
-- \__, |\__,_|\___|\___|_| |_|_| |_|\___|_|\__,_| --
-- | | --
-- |_| --
-- --
-- --
-- Peripheral-NTM for MPSoC --
-- Neural Turing Machine for MPSoC --
-- --
--------------------------------------------------------------------------------
-- Copyright (c) 2020-2021 by the author(s)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
--------------------------------------------------------------------------------
-- Author(s):
-- <NAME> <<EMAIL>>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.float_pkg.all;
use work.ntm_arithmetic_pkg.all;
use work.ntm_math_pkg.all;
entity ntm_vector_cosine_similarity is
generic (
DATA_SIZE : integer := 32;
CONTROL_SIZE : integer := 64
);
port (
-- GLOBAL
CLK : in std_logic;
RST : in std_logic;
-- CONTROL
START : in std_logic;
READY : out std_logic;
DATA_A_IN_ENABLE : in std_logic;
DATA_B_IN_ENABLE : in std_logic;
DATA_ENABLE : out std_logic;
DATA_OUT_ENABLE : out std_logic;
-- DATA
LENGTH_IN : in std_logic_vector(CONTROL_SIZE-1 downto 0);
DATA_A_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
DATA_B_IN : in std_logic_vector(DATA_SIZE-1 downto 0);
DATA_OUT : out std_logic_vector(DATA_SIZE-1 downto 0)
);
end entity;
architecture ntm_vector_cosine_similarity_architecture of ntm_vector_cosine_similarity is
-----------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------
-- Finite State Machine
type cosine_similarity_ctrl_fsm is (
STARTER_STATE, -- STEP 0
INPUT_STATE, -- STEP 1
ENDER_STATE, -- STEP 2
COSINE_SIMILARITY_STATE, -- STEP 3
CLEAN_STATE, -- STEP 4
OPERATION_STATE -- STEP 5
);
-- Buffer
type vector_buffer is array (CONTROL_SIZE-1 downto 0) of std_logic_vector(DATA_SIZE-1 downto 0);
-----------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------
constant ZERO_CONTROL : std_logic_vector(CONTROL_SIZE-1 downto 0) := std_logic_vector(to_unsigned(0, CONTROL_SIZE));
constant ONE_CONTROL : std_logic_vector(CONTROL_SIZE-1 downto 0) := std_logic_vector(to_unsigned(1, CONTROL_SIZE));
constant TWO_CONTROL : std_logic_vector(CONTROL_SIZE-1 downto 0) := std_logic_vector(to_unsigned(2, CONTROL_SIZE));
constant THREE_CONTROL : std_logic_vector(CONTROL_SIZE-1 downto 0) := std_logic_vector(to_unsigned(3, CONTROL_SIZE));
constant ZERO_DATA : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_float(0.0));
constant ONE_DATA : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_float(1.0));
constant TWO_DATA : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_float(2.0));
constant THREE_DATA : std_logic_vector(DATA_SIZE-1 downto 0) := std_logic_vector(to_float(3.0));
constant FULL : std_logic_vector(DATA_SIZE-1 downto 0) := (others => '1');
constant EMPTY : std_logic_vector(DATA_SIZE-1 downto 0) := (others => '0');
constant EULER : std_logic_vector(DATA_SIZE-1 downto 0) := (others => '0');
-----------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------
-- Finite State Machine
signal cosine_similarity_ctrl_fsm_int : cosine_similarity_ctrl_fsm;
-- Buffer
signal vector_a_int : vector_buffer;
signal vector_b_int : vector_buffer;
signal vector_out_int : vector_buffer;
-- Internal Signals
signal index_loop : std_logic_vector(CONTROL_SIZE-1 downto 0);
signal data_a_in_cosine_similarity_int : std_logic;
signal data_b_in_cosine_similarity_int : std_logic;
begin
-----------------------------------------------------------------------
-- Body
-----------------------------------------------------------------------
-- DATA_OUT = DATA_A_IN · DATA_B_IN
-- CONTROL
ctrl_fsm : process(CLK, RST)
variable data_a_int : std_logic_vector(DATA_SIZE-1 downto 0);
variable data_b_int : std_logic_vector(DATA_SIZE-1 downto 0);
variable data_p_int : vector_buffer;
begin
if (RST = '0') then
-- Data Outputs
DATA_OUT <= ZERO_DATA;
-- Control Outputs
READY <= '0';
DATA_ENABLE <= '0';
DATA_OUT_ENABLE <= '0';
-- Control Internal
data_a_in_cosine_similarity_int <= '0';
data_b_in_cosine_similarity_int <= '0';
index_loop <= ZERO_CONTROL;
elsif (rising_edge(CLK)) then
case cosine_similarity_ctrl_fsm_int is
when STARTER_STATE => -- STEP 0
-- Control Outputs
READY <= '0';
DATA_ENABLE <= '0';
DATA_OUT_ENABLE <= '0';
if (START = '1') then
-- Control Internal
index_loop <= ZERO_CONTROL;
-- FSM Control
cosine_similarity_ctrl_fsm_int <= INPUT_STATE;
end if;
when INPUT_STATE => -- STEP 1
if (DATA_A_IN_ENABLE = '1') then
-- Data Inputs
vector_a_int(to_integer(unsigned(index_loop))) <= DATA_A_IN;
-- Control Internal
data_a_in_cosine_similarity_int <= '1';
end if;
if (DATA_B_IN_ENABLE = '1') then
-- Data Inputs
vector_b_int(to_integer(unsigned(index_loop))) <= DATA_B_IN;
-- Control Internal
data_b_in_cosine_similarity_int <= '1';
end if;
if (data_a_in_cosine_similarity_int = '1' and data_b_in_cosine_similarity_int = '1') then
-- Control Internal
data_a_in_cosine_similarity_int <= '0';
data_b_in_cosine_similarity_int <= '0';
-- FSM Control
cosine_similarity_ctrl_fsm_int <= ENDER_STATE;
end if;
-- Control Outputs
DATA_ENABLE <= '0';
when ENDER_STATE => -- STEP 2
if (unsigned(index_loop) = unsigned(LENGTH_IN)-unsigned(ONE_CONTROL)) then
-- Control Internal
index_loop <= ZERO_CONTROL;
-- FSM Control
cosine_similarity_ctrl_fsm_int <= COSINE_SIMILARITY_STATE;
else
-- Control Internal
index_loop <= std_logic_vector(unsigned(index_loop)+unsigned(ONE_CONTROL));
-- Control Outputs
DATA_ENABLE <= '1';
-- FSM Control
cosine_similarity_ctrl_fsm_int <= INPUT_STATE;
end if;
-- Data Outputs
DATA_OUT <= ZERO_DATA;
when COSINE_SIMILARITY_STATE => -- STEP 3
-- Data Inputs
data_a_int := ZERO_DATA;
data_b_int := ZERO_DATA;
for i in 0 to to_integer(unsigned(LENGTH_IN))-1 loop
data_p_int(i) := ZERO_DATA;
end loop;
for i in 0 to to_integer(unsigned(LENGTH_IN))-1 loop
data_a_int := std_logic_vector(to_float(to_real(to_float(data_a_int)) + (to_real(to_float(vector_a_int(i)))*to_real(to_float(vector_a_int(i))))));
data_b_int := std_logic_vector(to_float(to_real(to_float(data_b_int)) + (to_real(to_float(vector_b_int(i)))*to_real(to_float(vector_b_int(i))))));
data_p_int(i) := std_logic_vector(to_float(to_real(to_float(data_p_int(i))) + (to_real(to_float(vector_a_int(i)))*to_real(to_float(vector_b_int(i))))));
end loop;
for i in 0 to to_integer(unsigned(LENGTH_IN))-1 loop
vector_out_int(i) <= std_logic_vector(to_float(to_real(to_float(data_p_int(i)))/(to_real(to_float(data_a_int))*to_real(to_float(data_b_int)))));
end loop;
-- FSM Control
cosine_similarity_ctrl_fsm_int <= CLEAN_STATE;
when CLEAN_STATE => -- STEP 4
-- Control Outputs
DATA_ENABLE <= '0';
DATA_OUT_ENABLE <= '0';
-- FSM Control
cosine_similarity_ctrl_fsm_int <= OPERATION_STATE;
when OPERATION_STATE => -- STEP 5
if (unsigned(index_loop) = unsigned(LENGTH_IN)-unsigned(ONE_CONTROL)) then
-- Control Outputs
READY <= '1';
-- Control Internal
index_loop <= ZERO_CONTROL;
-- FSM Control
cosine_similarity_ctrl_fsm_int <= STARTER_STATE;
else
-- Control Internal
index_loop <= std_logic_vector(unsigned(index_loop)+unsigned(ONE_CONTROL));
-- FSM Control
cosine_similarity_ctrl_fsm_int <= CLEAN_STATE;
end if;
-- Data Outputs
DATA_OUT <= vector_out_int(to_integer(unsigned(index_loop)));
-- Control Outputs
DATA_OUT_ENABLE <= '1';
when others =>
-- FSM Control
cosine_similarity_ctrl_fsm_int <= STARTER_STATE;
end case;
end if;
end process;
end architecture;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis AXISTREAM library : axistream_simple_tb
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library bitvis_vip_axistream;
use bitvis_vip_axistream.axistream_bfm_pkg.all;
--hdlunit:tb
-- Test case entity
entity axistream_simple_tb is
generic (
GC_TESTCASE : string := "UVVM";
GC_DATA_WIDTH : natural := 32; -- number of bits in AXI-Stream IF tdata
GC_USER_WIDTH : natural := 1; -- number of bits in AXI-Stream IF tuser
GC_ID_WIDTH : natural := 1; -- number of bits in AXI-Stream IF tID
GC_DEST_WIDTH : natural := 1; -- number of bits in AXI-Stream IF tDEST
GC_USE_SETUP_AND_HOLD : boolean := false -- use setup and hold times to synchronise the BFM
);
end entity;
-- Test case architecture
architecture func of axistream_simple_tb is
--------------------------------------------------------------------------------
-- Types and constants declarations
--------------------------------------------------------------------------------
constant C_CLK_PERIOD : time := 10 ns;
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
constant c_max_bytes : natural := 100; -- max bytes per packet to send
constant GC_DUT_FIFO_DEPTH : natural := 4;
--------------------------------------------------------------------------------
-- Signal declarations
--------------------------------------------------------------------------------
signal clk : std_logic := '0';
signal areset : std_logic := '0';
signal clock_ena : boolean := false;
-- signals
-- The axistream interface is gathered in one record, so procedures that use the
-- axistream interface have less arguments
signal axistream_if_m : t_axistream_if(tdata(GC_DATA_WIDTH -1 downto 0),
tkeep((GC_DATA_WIDTH/8)-1 downto 0),
tuser( GC_USER_WIDTH -1 downto 0),
tstrb((GC_DATA_WIDTH/8)-1 downto 0),
tid( GC_ID_WIDTH -1 downto 0),
tdest( GC_DEST_WIDTH -1 downto 0)
);
signal axistream_if_s : t_axistream_if(tdata( GC_DATA_WIDTH -1 downto 0),
tkeep((GC_DATA_WIDTH/8)-1 downto 0),
tuser( GC_USER_WIDTH -1 downto 0),
tstrb((GC_DATA_WIDTH/8)-1 downto 0),
tid( GC_ID_WIDTH -1 downto 0),
tdest( GC_DEST_WIDTH -1 downto 0)
);
--------------------------------------------------------------------------------
-- Component declarations
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
begin
-----------------------------
-- Instantiate Testharness
-----------------------------
i_axistream_test_harness : entity bitvis_vip_axistream.test_harness(struct_simple)
generic map(
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_USER_WIDTH => GC_USER_WIDTH,
GC_ID_WIDTH => GC_ID_WIDTH,
GC_DEST_WIDTH => GC_DEST_WIDTH,
GC_DUT_FIFO_DEPTH => GC_DUT_FIFO_DEPTH
)
port map(
clk => clk,
areset => areset,
axistream_if_m_VVC2FIFO => axistream_if_m,
axistream_if_s_FIFO2VVC => axistream_if_s
);
-- Set up clock generator
p_clock : clock_generator(clk, clock_ena, C_CLK_PERIOD, "axistream CLK");
------------------------------------------------
-- PROCESS: p_main
-- Process for transmitting packets and stopping the test bench.
------------------------------------------------
p_main : process
-- BFM config
variable axistream_bfm_config : t_axistream_bfm_config := C_AXIStream_BFM_CONFIG_DEFAULT;
variable v_cnt : integer := 0;
variable v_numBytes : integer := 0;
variable v_numWords : integer := 0;
variable v_data_array : t_byte_array(0 to c_max_bytes-1);
variable v_user_array : t_user_array(v_data_array'range) := (others => (others => '0'));
variable v_strb_array : t_strb_array(v_data_array'range) := (others => (others => '0'));
variable v_id_array : t_id_array(v_data_array'range) := (others => (others => '0'));
variable v_dest_array : t_dest_array(v_data_array'range) := (others => (others => '0'));
begin
-- To avoid that log files from different test cases (run in separate
-- simulations) overwrite each other.
set_log_file_name(GC_TESTCASE & "_Log.txt");
set_alert_file_name(GC_TESTCASE & "_Alert.txt");
-- override default config with settings for this testbench
axistream_bfm_config.max_wait_cycles := 1000;
axistream_bfm_config.max_wait_cycles_severity := error;
axistream_bfm_config.check_packet_length := true;
if GC_USE_SETUP_AND_HOLD then
axistream_bfm_config.clock_period := C_CLK_PERIOD;
axistream_bfm_config.setup_time := C_CLK_PERIOD/4;
axistream_bfm_config.hold_time := C_CLK_PERIOD/4;
axistream_bfm_config.bfm_sync := SYNC_WITH_SETUP_AND_HOLD;
end if;
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
enable_log_msg(ALL_MESSAGES);
--disable_log_msg(ALL_MESSAGES);
--enable_log_msg(ID_LOG_HDR);
log(ID_LOG_HDR, "Start Simulation of TB for AXISTREAM 1", C_SCOPE);
------------------------------------------------------------
clock_ena <= true; -- the axistream_reset routine assumes the clock is running
log("TC: axistream transmits: ");
-- Directly assigning args
v_data_array(0 to 2) := (x"a0" , x"a1" , x"a2");
axistream_transmit_bytes(v_data_array(0 to 2), "Directly assign args", clk, axistream_if_m, C_SCOPE, shared_msg_id_panel, axistream_bfm_config);
if GC_USER_WIDTH = 1 then
-- When calling axistream_expect later, setting tuser for second word to dont care to support cases where number of words are only 1 (depends on GC_DATA_WIDTH)
v_data_array(0 to 1) := (x"D0", x"D1");
v_user_array(0 to 1) := (x"01", x"00");
axistream_transmit_bytes( v_data_array(0 to 1), v_user_array(0 to 1), "Directly assign args including tuser", clk, axistream_if_m, C_SCOPE, shared_msg_id_panel, axistream_bfm_config);
end if;
for i in 1 to v_data_array'high loop
v_numBytes := i;
v_numWords := integer(ceil(real(v_numBytes)/(real(GC_DATA_WIDTH)/8.0)));
-- Generate packet data
v_cnt := i;
for byte in 0 to v_numBytes-1 loop
v_data_array(byte) := std_logic_vector(to_unsigned(v_cnt, v_data_array(0)'length));
v_user_array(byte) := std_logic_vector(to_unsigned(v_cnt, v_user_array(0)'length));
v_strb_array(byte) := std_logic_vector(to_unsigned(v_cnt, v_strb_array(0)'length));
v_id_array(byte) := std_logic_vector(to_unsigned(v_cnt, v_id_array(0)'length));
v_dest_array(byte) := std_logic_vector(to_unsigned(v_cnt, v_dest_array(0)'length));
v_cnt := v_cnt + 1;
end loop;
-- BFM calls.
if i = 0 then
-- use a default tuser
axistream_transmit_bytes(v_data_array(0 to v_numBytes-1), "transmit, default tuser, tstrb etc", clk, axistream_if_m, C_SCOPE, shared_msg_id_panel, axistream_bfm_config);
else
-- tstrb, tid, tdest are tested in axistream_vvc_simple_tb.
axistream_transmit_bytes(v_data_array(0 to v_numBytes-1), v_user_array(0 to v_numWords-1), "transmit, setting tuser. Default tstrb etc", clk, axistream_if_m, C_SCOPE, shared_msg_id_panel, axistream_bfm_config);
end if;
-- Sometimes insert gap between packets
if random(0, 1) = 1 then
wait for 100 ns;
end if;
end loop;
-----------------------------------------------------------------------------
-- Ending the simulation
-----------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
-- Finish the simulation
std.env.stop;
wait; -- to stop completely
end process p_main;
-- Process for receiving packets
p_slave : process
variable v_cnt : integer := 0;
variable v_numBytes : integer := 0;
variable v_numWords : integer := 0;
variable v_data_array : t_byte_array(0 to c_max_bytes-1);
variable v_user_array : t_user_array(v_data_array'range) := (others => (others => '0'));
variable v_strb_array : t_strb_array(v_data_array'range) := (others => (others => '0'));
variable v_id_array : t_id_array(v_data_array'range) := (others => (others => '0'));
variable v_dest_array : t_dest_array(v_data_array'range) := (others => (others => '0'));
-- BFM config
variable axistream_bfm_config : t_axistream_bfm_config := C_AXIStream_BFM_CONFIG_DEFAULT;
begin
-- override default config with settings for this testbench
axistream_bfm_config.max_wait_cycles := 1000;
axistream_bfm_config.max_wait_cycles_severity := error;
axistream_bfm_config.check_packet_length := true;
if GC_USE_SETUP_AND_HOLD then
axistream_bfm_config.clock_period := C_CLK_PERIOD;
axistream_bfm_config.setup_time := C_CLK_PERIOD/4;
axistream_bfm_config.hold_time := C_CLK_PERIOD/4;
axistream_bfm_config.bfm_sync := SYNC_WITH_SETUP_AND_HOLD;
end if;
v_data_array(0 to 2) := (x"a0" , x"a1" , x"a2");
axistream_expect_bytes(v_data_array(0 to 2),
"Directly assigned args, " &
".", clk, axistream_if_s, error, C_SCOPE, shared_msg_id_panel, axistream_bfm_config); --
if GC_USER_WIDTH = 1 then
-- setting tuser for second word to dont care to support cases where number of words are only 1 (depends on GC_DATA_WIDTH)
v_data_array(0 to 1) := (x"D0" , x"D1");
v_user_array(0 to 1) := (x"01", "--------");
axistream_expect_bytes(v_data_array(0 to 1), v_user_array(0 to 1),
"Directly assigned args, including tuser " &
".", clk, axistream_if_s, error, C_SCOPE, shared_msg_id_panel, axistream_bfm_config); --
end if;
for i in 1 to v_data_array'high loop
v_numBytes := i;
v_numWords := integer(ceil(real(v_numBytes)/(real(GC_DATA_WIDTH)/8.0)));
-- Generate expected packet. Must match the formula in p_main
v_cnt := i;
for byte in 0 to v_numBytes-1 loop
v_data_array(byte) := std_logic_vector(to_unsigned(v_cnt, v_data_array(0)'length));
v_user_array(byte) := std_logic_vector(to_unsigned(v_cnt, v_user_array(0)'length));
v_strb_array(byte) := std_logic_vector(to_unsigned(v_cnt, v_strb_array(0)'length));
v_id_array(byte) := std_logic_vector(to_unsigned(v_cnt, v_id_array(0)'length));
v_dest_array(byte) := std_logic_vector(to_unsigned(v_cnt, v_dest_array(0)'length));
v_cnt := v_cnt + 1;
end loop;
-- Configure the sink BFM for this packet.
axistream_bfm_config.ready_low_at_word_num := random(0, v_numWords-1);
axistream_bfm_config.ready_low_duration := random(0, 4);
if random(0, 1) = 1 then
axistream_bfm_config.ready_default_value := not axistream_bfm_config.ready_default_value;
end if;
-- BFM call
if i = 0 then
-- Test the overload without exp_user_array, exp_strb_array etc
axistream_expect_bytes(v_data_array(0 to v_numBytes-1),
"ready_low_at_word_num = " & to_string(axistream_bfm_config.ready_low_at_word_num) &
"ready_low_duration = " & to_string(axistream_bfm_config.ready_low_duration) &
"ready_default_value = " & to_string(axistream_bfm_config.ready_default_value) &
"i="&to_string(i), clk, axistream_if_s, error, C_SCOPE, shared_msg_id_panel, axistream_bfm_config); --
else
-- Test the overload without exp_strb_array, exp_id_array, exp_dest_array
-- More tstrb, tid, tdest tests in axistream_vvc_simple_tb.
axistream_expect_bytes(v_data_array(0 to v_numBytes-1), v_user_array(0 to v_numWords-1),
"ready_low_at_word_num = " & to_string(axistream_bfm_config.ready_low_at_word_num) &
"ready_low_duration = " & to_string(axistream_bfm_config.ready_low_duration) &
"ready_default_value = " & to_string(axistream_bfm_config.ready_default_value) &
"i="&to_string(i), clk, axistream_if_s, error, C_SCOPE, shared_msg_id_panel, axistream_bfm_config); --
end if;
end loop;
wait;
end process p_slave;
end func;
|
<filename>s2i/RHFSM_SORT.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RHFSM_SORT is
generic (RHFSM_STACK_ADDR_SIZE: integer := 12;
LOCAL_STACK_ADDR_SIZE: integer := 12;
RHFSM_X_WIDTH: integer := 10;
RHFSM_Y_WIDTH: integer := 18;
DATA_SIZE: integer := 14;
RAM_ADDR_SIZE: integer := 12);
port (clk, rst: in STD_LOGIC;
dataflow: in STD_LOGIC;
data_in: in STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0);
data_out: out STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0);
ready, new_data, next_data: out STD_LOGIC);
end RHFSM_SORT;
architecture RHFSM_SORT_arch of RHFSM_SORT is
component RHFSM is
generic (STACK_ADDR_SIZE: integer;
X_WIDTH: integer;
Y_WIDTH: integer);
port (clk, rst: in STD_LOGIC;
X: in STD_LOGIC_VECTOR (X_WIDTH downto 1);
Y: out STD_LOGIC_VECTOR (Y_WIDTH downto 1);
stack_upper_bound, stack_lower_bound: out STD_LOGIC);
end component;
component DATAPATH is
generic (DATA_SIZE: integer;
RAM_ADDR_SIZE: integer;
LOCAL_ADDR_SIZE: integer;
RHFSM_X_WIDTH: integer;
RHFSM_Y_WIDTH: integer);
port (clk, rst: in STD_LOGIC;
X: out STD_LOGIC_VECTOR (RHFSM_X_WIDTH downto 1);
Y: in STD_LOGIC_VECTOR (RHFSM_Y_WIDTH downto 1);
data_in: in STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0);
data_out: out STD_LOGIC_VECTOR (DATA_SIZE-1 downto 0);
dataflow: in STD_LOGIC;
ready, new_data, next_data: out STD_LOGIC;
local_full, local_empty: out STD_LOGIC;
RAM_full: out STD_LOGIC);
end component;
signal X: STD_LOGIC_VECTOR (RHFSM_X_WIDTH downto 1);
signal Y: STD_LOGIC_VECTOR (RHFSM_Y_WIDTH downto 1);
begin
CONTROL_UNIT:RHFSM
generic map (RHFSM_STACK_ADDR_SIZE, RHFSM_X_WIDTH, RHFSM_Y_WIDTH)
port map (clk, rst, X, Y, open, open);
DATAPATH_UNIT:DATAPATH
generic map (DATA_SIZE, RAM_ADDR_SIZE, LOCAL_STACK_ADDR_SIZE, RHFSM_X_WIDTH, RHFSM_Y_WIDTH)
port map (clk, rst, X, Y, data_in, data_out, dataflow, ready, new_data, next_data, open, open, open);
end RHFSM_SORT_arch;
|
-- ****************************************************
-- Proyecto Final
-- ****************************************************
-- Integrantes:
-- <NAME>
-- <NAME>
-- <NAME>
-- ****************************************************
-- ****************************************************
-- Modulo para controlar la sincronización
-- horizontal y vertical (escenarios)
-- ****************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.start.all;
use work.logo.all;
use work.background.all;
use work.sprite.all;
entity sync is
port(
-- Reloj de 25 MHz
clk: in std_logic;
switch : in std_logic;
-- Habilitación de sincronización horizontal o vertical
hsync, vsync: out std_logic;
-- Control del color para cada pixel
r,g,b : out std_logic_vector(3 downto 0);
-- MOvimientos en general Arriba, Derecha, Abajo e Izquierda
movement: in std_logic_vector(4 downto 0);
bullet_signal: out std_logic;
shot_enable : out std_logic;
shot_created: in std_logic;
c_type: in std_logic_vector(1 downto 0);
hpos_o, vpos_o, fig_x1_o, fig_y1_o: out integer;
rgb_bullet: in std_logic_vector(11 downto 0);
draw_bullet: in std_logic;
button_debounced: in std_logic;
fairy_signal: out std_logic;
rgb_fairy: in std_logic_vector(11 downto 0);
draw_fairy: in std_logic;
e_type: in std_logic_vector(1 downto 0);
b1_del, b2_del, b3_del, b4_del, b5_del, b6_del: in std_logic;
e1_x, e2_x, e3_x, e4_x, e5_x, e6_x, e7_x, e8_x, e9_x: in integer;
e1_y, e2_y, e3_y, e4_y, e5_y, e6_y, e7_y, e8_y, e9_y: in integer;
e1_del, e2_del, e3_del, e4_del, e5_del, e6_del, e7_del, e8_del, e9_del: out std_logic := '0'
);
end sync;
architecture main of sync is
-- Variable auxiliar para el movimiento de los
-- pacman en logo
signal mov_auto: std_logic;
signal cuenta_mov: integer range 0 to 185116 := 0;
-- Variable auxiliar para mover los escenarios del juego
signal numero_escenario: integer range 0 to 2 := 0;
signal cuenta_escenario: integer range 0 to 125000000 := 0;
signal cambio_escenario: std_logic;
-- Variable auxiliar para manejar el color RBG
signal rgb_f: std_logic_vector(11 downto 0);
signal rgb_bp: std_logic_vector(11 downto 0);
signal rgb_bs: std_logic_vector(11 downto 0);
signal rgb_bl: std_logic_vector(11 downto 0);
-- Variable auxiliar para dibujar en la pantalla
signal draw_f: std_logic;
signal draw_bs: std_logic;
signal draw_bl: std_logic;
-- Variables referencia para dibujar personaje en pantalla
signal fig_x1: integer range 0 to 800 := 480;
signal fig_y1: integer range 0 to 525 := 350;
-- Variables generales para determinar las posiciones horizontal
-- y vertical en la pantalla
signal hpos: integer range 0 to 800 := 0;
signal vpos: integer range 0 to 525 := 0;
-- Variable para indicar el movimiento de los botones
constant despl: integer range 0 to 480:= 10;
-- Variables para controloar el sprite usado (personaje)
signal count_sprite: integer := 0;
signal charac: std_logic_vector(1 downto 0);
-- Variable para controlar la animación del sprite
signal animationsignal: std_logic_vector(3 downto 0);
-- Se declaran variables auxiliares para definir un cuadrado,
-- considerar que este se movera de arriba hacia abajo
signal y1_rec: integer range 0 to 525 := 45;
signal y2_rec: integer range 0 to 525:= 58;
signal aux_mov: integer range 0 to 1 := 0;
-- Se declaran variables auxiliares para tener un control
-- de los niveles, las vidas y el score
signal nivel: integer range 0 to 4 := 1;
signal vida: integer range 0 to 3 := 3;
signal vida_aux :integer := 6;
signal sc_u,sc_d,sc_c,sc_m,sc_mm: integer range 0 to 9 := 0;
signal asc_c,asc_m,asc_mm: std_logic;
----disparos
signal fireable: std_logic := '1';
signal eisfee: STD_LOGIC_VECTOR(27 downto 0):=X"01201AE";
signal defeat: std_logic := '0';
begin
-- Referencias para el centro de la pantalla
-- Centro horizontal
-- fig_x1 <=480;
-- Centro vertical
-- fig_y1 <=285;
-- Inicio de la pantalla
-- Inicio horizontal
-- fig_x1 <= 160;
-- Inicio vertical
-- fig_y1 <= 45;
-- Divisor de frecuencia para desplazar los pacman del logo
process(clk)
begin
hpos_o <= hpos;
vpos_o <= vpos;
fig_x1_o <= fig_x1;
fig_y1_o <= fig_y1;
if rising_edge(clk) then
if (cuenta_mov = 185115) then
cuenta_mov <= 0;
mov_auto <= '1';
else
cuenta_mov <= cuenta_mov + 1;
mov_auto <= '0';
end if;
end if;
end process;
-- Se verifica el tope del movimiento de los pacman del logo
process(y1_rec)
begin
if(y1_rec = 45) then
aux_mov <= 0;
elsif(y1_rec = 511) then
aux_mov <= 1;
end if;
end process;
-- Se verifica si el desplazamiento es arriba o abajo
-- de los pacman del logo
process(mov_auto)
begin
if(mov_auto='1') then
if(aux_mov = 0) then
y1_rec <= y1_rec + 1;
y2_rec <= y2_rec + 1;
else
y1_rec <= y1_rec - 1;
y2_rec <= y2_rec - 1;
end if;
end if;
end process;
process (vida_aux)
begin
if(vida_aux = 6) then
vida <= 3;
elsif(vida_aux = 4) then
vida <= 2;
elsif(vida_aux = 2) then
vida <= 1;
elsif(vida_aux = 0) then
vida <= 0;
end if;
end process;
-- Divisor de frecuencia para el escenario
-- Se contabilizan los flancos de subida de la señal de reloj
-- para indicar un cambio cada 5 segundos aproximadamente
process(clk)
begin
if rising_edge(clk) then
if (cuenta_escenario = 124999999) then
-- Provisional en lo que se crea la dinámica del juego
if (numero_escenario < 2) then
numero_escenario <= numero_escenario + 1;
end if;
cuenta_escenario <= 0;
else
cuenta_escenario <= cuenta_escenario + 1;
end if;
if(defeat = '1') then
cuenta_escenario <= 0;
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk))then
if(((fig_x1 > e1_x and fig_x1 <= e1_x+37) or (fig_x1+25 > e1_x and fig_x1+25 <= e1_x+37)) and ((fig_y1 > e1_y and fig_y1 <= e1_y+27) or (fig_y1+47 > e1_y and fig_y1+47 <= e1_y+27)) and fig_x1 /= 0) then
e1_del <= '1';
if(vida > 0)then
vida_aux <= vida_aux - 1;
defeat <= '0';
else
vida_aux <= 6;
defeat <= '1';
end if;
elsif(((fig_x1 > e2_x and fig_x1 <= e2_x+37) or (fig_x1+25 > e2_x and fig_x1+25 <= e2_x+37)) and ((fig_y1 > e2_y and fig_y1 <= e2_y+27) or (fig_y1+47 > e2_y and fig_y1+47 <= e2_y+37)) and fig_x1 /= 0) then
e2_del <= '1';
if(vida > 0)then
vida_aux <= vida_aux - 1;
defeat <= '0';
else
vida_aux <= 6;
defeat <= '1';
end if;
elsif(((fig_x1 > e3_x and fig_x1 <= e3_x+37) or (fig_x1+25 > e3_x and fig_x1+25 <= e3_x+37)) and ((fig_y1 > e3_y and fig_y1 <= e3_y+27) or (fig_y1+47 > e3_y and fig_y1+47 <= e3_y+37)) and fig_x1 /= 0) then
e3_del <= '1';
if(vida > 0)then
vida_aux <= vida_aux - 1;
defeat <= '0';
else
vida_aux <= 6;
defeat <= '1';
end if;
elsif(((fig_x1 > e4_x and fig_x1 <= e4_x+37) or (fig_x1+25 > e4_x and fig_x1+25 <= e4_x+37)) and ((fig_y1 > e4_y and fig_y1 <= e4_y+27) or (fig_y1+47 > e4_y and fig_y1+47 <= e4_y+37)) and fig_x1 /= 0) then
e4_del <= '1';
if(vida > 0)then
vida_aux <= vida_aux - 1;
defeat <= '0';
else
vida_aux <= 6;
defeat <= '1';
end if;
elsif(((fig_x1 > e5_x and fig_x1 <= e5_x+37) or (fig_x1+25 > e5_x and fig_x1+25 <= e5_x+37)) and ((fig_y1 > e5_y and fig_y1 <= e5_y+27) or (fig_y1+47 > e5_y and fig_y1+47 <= e5_y+37)) and fig_x1 /= 0) then
e5_del <= '1';
if(vida > 0)then
vida_aux <= vida_aux - 1;
defeat <= '0';
else
vida_aux <= 6;
defeat <= '1';
end if;
elsif(((fig_x1 > e6_x and fig_x1 <= e6_x+37) or (fig_x1+25 > e6_x and fig_x1+25 <= e6_x+37)) and ((fig_y1 > e6_y and fig_y1 <= e6_y+27) or (fig_y1+47 > e6_y and fig_y1+47 <= e6_y+37)) and fig_x1 /= 0) then
e6_del <= '1';
if(vida > 0)then
vida_aux <= vida_aux - 1;
defeat <= '0';
else
vida_aux <= 6;
defeat <= '1';
end if;
elsif(((fig_x1 > e7_x and fig_x1 <= e7_x+37) or (fig_x1+25 > e7_x and fig_x1+25 <= e7_x+37)) and ((fig_y1 > e7_y and fig_y1 <= e7_y+27) or (fig_y1+47 > e7_y and fig_y1+47 <= e7_y+37)) and fig_x1 /= 0) then
e7_del <= '1';
if(vida > 0)then
vida_aux <= vida_aux - 1;
defeat <= '0';
else
vida_aux <= 6;
defeat <= '1';
end if;
elsif(((fig_x1 > e8_x and fig_x1 <= e8_x+37) or (fig_x1+25 > e8_x and fig_x1+25 <= e8_x+37)) and ((fig_y1 > e8_y and fig_y1 <= e8_y+27) or (fig_y1+47 > e8_y and fig_y1+47 <= e8_y+37)) and fig_x1 /= 0) then
e8_del <= '1';
if(vida > 0)then
vida_aux <= vida_aux - 1;
defeat <= '0';
else
vida_aux <= 6;
defeat <= '1';
end if;
elsif(((fig_x1 > e9_x and fig_x1 <= e9_x+37) or (fig_x1+25 > e9_x and fig_x1+25 <= e9_x+37)) and ((fig_y1 > e9_y and fig_y1 <= e9_y+27) or (fig_y1+47 > e9_y and fig_y1+47 <= e9_y+37)) and fig_x1 /= 0) then
e9_del <= '1';
if(vida > 0)then
vida_aux <= vida_aux - 1;
defeat <= '0';
else
vida_aux <= 6;
defeat <= '1';
end if;
else
e1_del <= '0';
e2_del <= '0';
e3_del <= '0';
e4_del <= '0';
e5_del <= '0';
e6_del <= '0';
e7_del <= '0';
e8_del <= '0';
e9_del <= '0';
defeat <= '0';
end if;
end if;
end process;
-- Proceso provicional para ver el aumento del score
-- solo hay que cambiar cada cuanto hay que sumar
process(b1_del, b2_del, b3_del, b4_del, b5_del, b6_del, defeat)
begin
-- if (fireable = '1') then
-- shot_enable <= '1';
-- else
-- shot_enable <= '0';
-- end if;
if (b1_del or b2_del or b3_del or b4_del or b5_del or b6_del) then
if(sc_d = 9) then
sc_d <= 0;
asc_c <= '1';
else
sc_d <= sc_d + 1;
asc_c <= '0';
end if;
end if;
if (defeat) then
sc_d <= 0;
asc_c <= '0';
end if;
end process;
process(asc_c)
begin
if (asc_c) then
if(sc_c = 9) then
sc_c <= 0;
asc_m <= '1';
else
sc_c <= sc_c + 1;
asc_m <= '0';
end if;
end if;
if (defeat) then
sc_c <= 0;
asc_m <= '0';
end if;
end process;
process(asc_m, defeat)
begin
if rising_edge(asc_m) then
if(sc_m = 9) then
sc_m <= 0;
asc_mm <= '1';
else
sc_m <= sc_m + 1;
asc_mm <= '0';
end if;
end if;
if (defeat) then
sc_m <= 0;
asc_mm <= '0';
end if;
end process;
process(asc_mm, defeat)
begin
if rising_edge(asc_mm) then
if(sc_mm = 9) then
sc_mm <= 0;
else
sc_mm <= sc_mm + 1;
end if;
end if;
if (defeat) then
sc_mm <= 0;
end if;
end process;
-- Proceso que se encarga de verificar a partir del score
-- el nivel en el cual se encuentra provisional
process(asc_c,defeat)
begin
if rising_edge(asc_c) then
if (sc_c = 1) then
eisfee <= X"01201AE";
nivel <= 1;
elsif (sc_c = 2) then
eisfee <= x"00E014E";
nivel <= 2;
elsif (sc_c = 3) then
eisfee <= x"00A00EE";
nivel <= 3;
elsif (sc_c = 4) then
eisfee <= x"006008F";
nivel <= 4;
end if;
end if;
if (defeat) then
eisfee <= X"01201AE";
nivel <= 1;
end if;
end process;
-- Diviso de frequencia para la animación
process(clk)
variable cuenta: STD_LOGIC_VECTOR(27 downto 0):=X"0000000";
begin
if rising_edge(clk) then
-- Animación 1
if (cuenta <= X"1805A3") then
animationsignal <= x"0";
-- Animación 2
elsif (cuenta > x"1805A3" and cuenta <= x"300B46") then
animationsignal <= x"1";
-- ANimación 3
elsif (cuenta > x"300B46" and cuenta <= x"4810E9") then
animationsignal <= x"2";
-- Animación 4
elsif (cuenta > x"4810E9" and cuenta <= x"60168C") then
animationsignal <= x"3";
-- Animación 5
elsif (cuenta > x"60168C" and cuenta <= x"781C2F") then
animationsignal <= x"4";
-- Animación 6
elsif (cuenta > x"781C2F" and cuenta <= x"9021D2") then
animationsignal <= x"5";
-- Animación 7
elsif (cuenta > x"9021D2" and cuenta <= x"A82775") then
animationsignal <= x"6";
-- Animación 8
elsif (cuenta > x"A82775" and cuenta <= x"C02D18") then
animationsignal <= x"7";
-- Animación 9
elsif (cuenta > X"C02D18") then
cuenta:=X"0000000";
end if;
cuenta:=cuenta+1;
end if;
end process;
updatebullet: process(clk)
variable timecount: STD_LOGIC_VECTOR(27 downto 0):=X"0000000";
begin
if rising_edge(clk) then
-- if (timecount <= X"c011ec") then
-- fireable <= '0';
-- timecount:=timecount+1;
--
-- elsif (timecount >= X"c011ec" and movement(4) = '1') then
-- timecount :=X"0000000";
-- fireable <= '1';
-- end if;
if (timecount <= X"1fb109") then
bullet_signal <= '0';
elsif (timecount > X"1fb109") then
bullet_signal <= '1';
timecount :=X"0000000";
end if;
timecount := timecount + 1;
end if;
end process;
updatefairy: process(clk)
variable timecount: STD_LOGIC_VECTOR(27 downto 0):=X"0000000";
begin
if rising_edge(clk) then
-- if (timecount <= X"c011ec") then
-- fireable <= '0';
-- timecount:=timecount+1;
--
-- elsif (timecount >= X"c011ec" and movement(4) = '1') then
-- timecount :=X"0000000";
-- fireable <= '1';
-- end if;
if (timecount <= eisfee) then
fairy_signal <= '0';
elsif (timecount > eisfee) then
fairy_signal <= '1';
timecount :=X"0000000";
end if;
timecount := timecount + 1;
end if;
end process;
-- firetimer: process(clk)
-- variable timecount: STD_LOGIC_VECTOR(27 downto 0):=X"0000000";
-- begin
-- if rising_edge(clk) then
-- if (timecount <= X"c011ec") then
-- fireable <= '0';
-- timecount:=timecount+1;
--
-- elsif (timecount > X"c011ec" and button_debounced = '1') then
-- timecount :=X"0000000";
-- fireable <= '1';
-- else if (timecount > X"c011ec" and button_debounced = '1')
-- end if;
--
---- if (timecount <= X"6008f6") then
---- bullet_signal <= '0';
---- elsif (timecount > X"6008f6") then
---- bullet_signal <= '1';
---- timecount :=X"0000000";
---- else
---- timecount := timecount + 1;
---- end if;
-- end if;
-- end process;
-- Se pasan los respectivos parametros a este
-- procedimiento que se empleara en background
background_play(hpos, vpos, rgb_bp, nivel, vida, sc_u, sc_d, sc_c, sc_m, sc_mm);
-- Se pasan los respectivos parametros a este
-- procedimiento que se empleara en start
background_start(hpos, vpos, rgb_bs, draw_bs);
-- Se pasan los respectivos parametros a este
-- procedimiento que se empleara en logo
background_logo(hpos, vpos, rgb_bl, draw_bl, y1_rec, y2_rec);
-- Se pasan los respectivos parametros a este
-- procedimiento que se empleara en sprite
figure(hpos, vpos, fig_x1, fig_y1, rgb_f, draw_f, count_sprite, charac, animationsignal);
-- Se encarga de mostrar el escenario respectivo
process(clk)
begin
if rising_edge(clk) then
-- Escenario START
if (numero_escenario = 0) then
-- Verificación de tiempo para cambio de escenario
if(draw_bs = '1')then
r<=rgb_bs(11 downto 8);
g<=rgb_bs(7 downto 4);
b<=rgb_bs(3 downto 0);
else
r<=x"0";
g<=x"0";
b<=x"0";
end if;
-- Escenario LOGO
elsif (numero_escenario = 1) then
if(draw_bl = '1')then
r<=rgb_bl(11 downto 8);
g<=rgb_bl(7 downto 4);
b<=rgb_bl(3 downto 0);
else
r<=x"f";
g<=x"f";
b<=x"f";
end if;
-- Escenario BACKGROUND y SPRITE
elsif (numero_escenario = 2) then
-- El siguiente procedimiento controla el
-- pixel que se está actualizando
-- Fondo en general
if (draw_f /= '0') then
-- Sprite, según el mapa de bits
-- [01 dibujo] [00 no dibujo] [10 transparencia] [11 reset]
if(charac = "01")then
r<=rgb_f(11 downto 8);
g<=rgb_f(7 downto 4);
b<=rgb_f(3 downto 0);
count_sprite <= count_sprite + 1;
elsif (charac = "11") then
count_sprite <= 0;
elsif (charac = "10")then
r<=rgb_bp(11 downto 8);
g<=rgb_bp(7 downto 4);
b<=rgb_bp(3 downto 0);
count_sprite <= count_sprite + 1;
end if;
elsif(draw_bullet /= '0') then
if (c_type = "01") then
r<=rgb_bullet(11 downto 8);
g<=rgb_bullet(7 downto 4);
b<=rgb_bullet(3 downto 0);
elsif (c_type = "10")then
r<=rgb_bp(11 downto 8);
g<=rgb_bp(7 downto 4);
b<=rgb_bp(3 downto 0);
end if;
elsif(draw_fairy /= '0') then
if (e_type = "01") then
r<=rgb_fairy(11 downto 8);
g<=rgb_fairy(7 downto 4);
b<=rgb_fairy(3 downto 0);
elsif (e_type = "10")then
r<=rgb_bp(11 downto 8);
g<=rgb_bp(7 downto 4);
b<=rgb_bp(3 downto 0);
end if;
else
r<=rgb_bp(11 downto 8);
g<=rgb_bp(7 downto 4);
b<=rgb_bp(3 downto 0);
end if;
end if;
-- Recorrido horizontal y vertical 640x480
if (hpos < 800) then
hpos <= hpos + 1;
else
hpos <= 0;
if(vpos<525) then
vpos <= vpos + 1;
else
vpos <= 0;
-- Control del movimiento
-- Movimiento arriba
if(movement(3)='1') then
if(fig_y1 >= 45 + despl) then
fig_y1 <= fig_y1 - despl;
end if;
end if;
-- MOvimiento derecha
if (movement(2)='1') then
if(fig_x1<=700 - 25 - despl) then
fig_x1 <= fig_x1 + despl;
end if;
end if;
-- Movimiento abajo
if (movement(1)= '1') then
if(fig_y1<= 525 - 47 - despl) then
fig_y1 <= fig_y1 + despl;
end if;
end if;
-- Movimiento izquierda
if (movement(0)= '1') then
if(fig_x1>=160 + despl) then
fig_x1 <= fig_x1 - despl;
end if;
end if;
end if;
end if;
-- Señal de sincronización horizontal
if (hpos > 16 and hpos < 112) then
-- Esto es porque el pulso de sync es bajo
hsync <= '0';
else
hsync <= '1';
end if;
-- Señal de sincronización vertical
if (vpos > 10 and vpos < 12) then
-- Esto es porque el pulso de sync es bajo
vsync <= '0';
else
vsync <= '1';
end if;
-- Cuando se este en fp
-- hSync, bp y lf ó vSync, bp y tb se deben
-- mantener las señales de los colores en 0
if ((hpos > 0 and hpos < 160) or (vpos > 0 and vpos < 45)) then
r <= (others => '0');
g <= (others => '0');
b <= (others => '0');
end if;
end if;
end process;
end main;
|
--
-- Copyright (c) 2011-2015 <NAME>, University of Zagreb
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-- OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-- SUCH DAMAGE.
--
-- $Id$
--
-- this is new and potentially buggy
-- variant of standard ULX2S SRAM
-- with most features
--
-- MIPS CPU 81.25 MHz
-- 1MB SDRAM
-- TV framebuffer (tip of 3.5 mm jack)
-- PCM audio (ring of 3.5 mm jack)
-- 2 SPI ports (flash and SD card)
-- FM/RDS transmitter 87-108 MHz
-- PID controller (3 HW channels + 1 SW simulation)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.numeric_std.all; -- we need signed type
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.MATH_REAL.ALL;
use work.f32c_pack.all;
use work.sram_pack.all;
-- vendor specific libs (lattice)
library xp2;
use xp2.components.all;
-- this is new and potentially buggy
-- variant of feature-rich ULX2S SRAM
--
-- 1MB SRAM
-- TV framebuffer
-- 16 GPIO with interrupts
-- 1 timer (2xPWM, 2xICP)
-- 1 channel PCM audio out
-- 2 SPI ports (flash and SD card)
-- PCM audio with DMA
-- FM RDS transmitter 87-108MHz (FM plays PCM audio)
-- 4 PID controllers (3 hardware, 1 simulation)
-- 8 LEDs, 5 buttons, 4 switches
entity toplevel is
generic (
-- Main clock: 25, 50, 62, 75, 81, 87, 100, 112, 125, 137, 150 MHz
C_clk_freq: integer := 50;
-- ISA options
C_arch: integer := ARCH_MI32;
C_big_endian: boolean := false;
-- C_boot_rom = true: bootloader will try to chainboot SPI flash ROM, fallback to serial
-- C_boot_rom = false: -- serial bootloader only
C_boot_rom: boolean := true;
C_mult_enable: boolean := true;
C_branch_likely: boolean := true;
C_sign_extend: boolean := true;
C_ll_sc: boolean := false;
C_PC_mask: std_logic_vector(31 downto 0) := x"800fffff"; -- 1MB limit from 0x80000000
-- C_PC_mask: std_logic_vector(31 downto 0) := x"100fffff"; -- 1MB limit from 0x10000000
-- COP0 options
C_exceptions: boolean := true;
C_cop0_count: boolean := true;
C_cop0_compare: boolean := true;
C_cop0_config: boolean := true;
-- CPU core configuration options
C_branch_prediction: boolean := true;
C_full_shifter: boolean := true;
C_result_forwarding: boolean := true;
C_load_aligner: boolean := true;
-- This may negatively influence timing closure:
C_movn_movz: boolean := false; -- true: +16 LUT4, -DMIPS, incomplete
-- Debugging / testing options (should be turned off)
C_debug: boolean := false;
-- SoC configuration options
C_bram_size: integer := 8; -- 8 or 16 KBytes
C_i_rom_only: boolean := true;
C_icache_size: integer := 2; -- 0, 2, 4 or 8 KBytes
C_dcache_size: integer := 2; -- 0, 2, 4 or 8 KBytes
C_xram_base: std_logic_vector(31 downto 28) := x"8"; -- RAM start address x"8" -> 0x80000000 (need C_PC_mask := x"800fffff")
-- C_xram_base: std_logic_vector(31 downto 28) := x"1"; -- RAM start address x"1" -> 0x10000000 (need C_PC_mask := x"100fffff")
C_cached_addr_bits: integer := 20; -- number of lower RAM address bits 2^20 -> 1MB to be cached
C_sram: boolean := true;
C_sram_refresh: boolean := true; -- RED ULX2S need it, others don't (exclusive: textmode or refresh)
C_sram_wait_cycles: integer := 4; -- ISSI, OK do 87.5 MHz
-- C_sram_pipelined_read: boolean := true; -- works only at 81.25 MHz !!! defined below as constant
C_sio: integer := 1; -- number of rs232 serial ports
C_simple_out: integer := 32; -- LEDs (only 8 used but quantized to 32)
C_simple_in: integer := 32; -- buttons and switches (not all used)
C_gpio: integer := 32; -- number of GPIO pins
C_spi: integer := 2; -- number of SPI interfaces
C_video_mode: integer := 1;
C_vgahdmi: boolean := true; -- simple VGA bitmap with compositing
-- currently on ulx2s video cache doesn't work
-- some mixtures of bugs, might not directly be the fault in cache itself
C_vgahdmi_cache_size: integer := 0; -- KB (0 to disable, also disable C_sram_refresh then fmax=81.25MHz, 2,4,8,16,32 to enable fmax=50MHz)
C_vgahdmi_cache_use_i: boolean := false; -- must be false, some data corruption with i-cache = true
C_vgahdmi_fifo_fast_ram: boolean := true; -- should be set true with cache, cache is faster than pixel shifter
-- normally this should be actual bits per pixel
C_vgahdmi_fifo_data_width: integer range 8 to 32 := 8;
-- width of FIFO address space -> size of fifo
-- for 640 pixel wide compositing use 11 -> 2048 bytes 8bpp
--C_vgahdmi_fifo_addr_width: integer := 11;
-- VGA textmode doesn't work on ulx2s any more
-- it used to work at 50MHz about january 2016,
-- at august 2016 it no longe works
-- arcagol shows screen corruption
-- other example may look like ok but it isn't
C_vgatext: boolean := false; -- Xark's feature-rich bitmap+textmode VGA
C_vgatext_label: string := "f32c: Lattice FX2 MIPS compatible soft-core 50MHz 1MB SRAM"; -- default banner in screen memory
-- C_vgatext_mode: integer := 0; -- 640x480
C_vgatext_bits: integer := 4; -- 16 possible colors
C_vgatext_bram_mem: integer := 0; -- 4KB text+font memory
C_vgatext_bram_base: std_logic_vector(31 downto 28) := x"4"; -- textmode bram at 0x40000000
C_vgatext_external_mem: integer := 1024; -- 1MB external SRAM/SDRAM
C_vgatext_reset: boolean := true; -- reset registers to default with async reset
C_vgatext_palette: boolean := true; -- yes, color palette
C_vgatext_text: boolean := true; -- enable optional text generation
C_vgatext_font_bram8: boolean := true; -- font in separate bram8 file (for Lattice XP2 BRAM or non power-of-two BRAM sizes)
C_vgatext_char_height: integer := 16; -- character cell height
C_vgatext_font_height: integer := 16; -- font height
C_vgatext_font_depth: integer := 8; -- font char depth, 7=128 characters or 8=256 characters
C_vgatext_font_linedouble: boolean := false; -- double font height by doubling each line (e.g., so 8x8 font fills 8x16 cell)
C_vgatext_font_widthdouble: boolean := false; -- double font width by doubling each pixel (e.g., so 8 wide font is 16 wide cell)
C_vgatext_monochrome: boolean := false; -- true for 2-color text for whole screen, else additional color attribute byte per character
C_vgatext_finescroll: boolean := true; -- true for pixel level character scrolling and line length modulo
C_vgatext_cursor: boolean := true; -- true for optional text cursor
C_vgatext_cursor_blink: boolean := true; -- true for optional blinking text cursor
C_vgatext_bus_write: boolean := true; -- true to allow writing vgatext BRAM from CPU bus. false: no writing
C_vgatext_bus_read: boolean := false; -- true to allow reading vgatext BRAM from CPU bus (may affect fmax). false is write only
C_vgatext_reg_read: boolean := false; -- true to allow reading vgatext BRAM from CPU bus (may affect fmax). false is write only
C_vgatext_text_fifo: boolean := true; -- enable text memory FIFO
C_vgatext_text_fifo_postpone_step: integer := 0;
C_vgatext_text_fifo_step: integer := (82*2)/4; -- step for the FIFO refill and rewind
C_vgatext_text_fifo_width: integer := 6; -- width of FIFO address space (default=4) length = 2^width * 4 bytes
C_vgatext_bitmap: boolean := true; -- true for optional bitmap generation
C_vgatext_bitmap_depth: integer := 8; -- 8-bpp 256-color bitmap
C_vgatext_bitmap_fifo: boolean := true; -- enable bitmap FIFO
-- 8 bpp compositing
-- step=horizontal width in pixels
C_vgatext_bitmap_fifo_step: integer := 640;
-- height=vertical height in pixels
C_vgatext_bitmap_fifo_height: integer := 480;
-- output data width 8bpp
C_vgatext_bitmap_fifo_data_width: integer := 8; -- should be equal to bitmap depth
-- width of FIFO address space -> size of fifo
-- for 640 pixel wide compositing use 11 -> 2048 bytes 8bpp
C_vgatext_bitmap_fifo_addr_width: integer := 11;
C_ledstrip: boolean := false;
-- input number of counts per full circle
C_ledstrip_full_circle: integer := 200; -- counts
-- number of pixels in each channel: 72
C_ledstrip_fifo_width: integer := 72;
-- number of scan lines: 50
C_ledstrip_fifo_height: integer := 50;
-- normally this should be actual bits per pixel
C_ledstrip_fifo_data_width: integer range 8 to 32 := 8;
-- width of FIFO address space -> size of fifo
-- for 640 pixel wide compositing use 11 -> 2048 bytes 8bpp
C_ledstrip_fifo_addr_width: integer := 11;
C_pcm: boolean := true;
C_timer: boolean := true;
C_cw_simple_out: integer := -1; -- simple_out (default 7) bit for 433MHz modulator. -1 to disable. set (C_framebuffer := false, C_dds := false) for 433MHz transmitter
C_fmrds: boolean := false; -- either FM or tx433
C_fm_stereo: boolean := true;
C_fm_filter: boolean := true;
C_fm_downsample: boolean := false;
C_rds_msg_len: integer := 260; -- bytes of RDS binary message, usually 52 (8-char PS) or 260 (8 PS + 64 RT)
C_fmdds_hz: integer := 325000000; -- Hz clk_fmdds (>2*108 MHz, e.g. 250 MHz, 325 MHz)
--C_rds_clock_multiply: integer := 57; -- multiply and divide from cpu clk 100 MHz
--C_rds_clock_divide: integer := 3125; -- to get 1.824 MHz for RDS logic
C_rds_clock_multiply: integer := 912; -- multiply and divide from cpu clk 81.25 MHz
C_rds_clock_divide: integer := 40625; -- to get 1.824 MHz for RDS logic
C_pids: integer := 0; -- 4 PIDs can fit but with other modules like video
-- can pose routing/timing problems in lattice XP2 so enable them as needed
-- manifestation of timing problems is that f32c CPU erraticaly slows down
-- or speeds up while executing arduino delay(1000);
C_pid_simulator: std_logic_vector(7 downto 0) := ext("1000", 8); -- for each pid choose simulator/real
C_dds: boolean := false
);
port (
clk_25m: in std_logic;
rs232_tx: out std_logic;
rs232_rx: in std_logic;
flash_so: in std_logic;
flash_cen, flash_sck, flash_si: out std_logic;
sdcard_so: in std_logic;
sdcard_cen, sdcard_sck, sdcard_si: out std_logic;
p_ring: out std_logic;
p_tip: out std_logic_vector(3 downto 0);
led: out std_logic_vector(7 downto 0);
btn_left, btn_right, btn_up, btn_down, btn_center: in std_logic;
sw: in std_logic_vector(3 downto 0);
j1_2, j1_3, j1_4, j1_8, j1_9, j1_13, j1_14, j1_15: inout std_logic;
j1_16, j1_17, j1_18, j1_19, j1_20, j1_21, j1_22, j1_23: inout std_logic;
j2_2, j2_3, j2_4, j2_5, j2_6, j2_7, j2_8, j2_9: inout std_logic;
j2_10, j2_11, j2_12, j2_13, j2_16: inout std_logic;
sram_a: out std_logic_vector(18 downto 0);
sram_d: inout std_logic_vector(15 downto 0);
sram_wel, sram_lbl, sram_ubl: out std_logic
-- sram_oel: out std_logic -- XXX the old ULXP2 board needs this!
);
end toplevel;
architecture Behavioral of toplevel is
constant C_sram_pipelined_read: boolean := C_clk_freq = 81; -- works only at 81.25 MHz !!!
signal clk, clk_325m, ena_325m: std_logic;
signal clk_112M5, clk_433m: std_logic;
signal pll_lock: std_logic;
signal reset_when_clock_stable: std_logic;
signal rs232_break: std_logic;
signal btn: std_logic_vector(4 downto 0);
signal gpio_28, fm_antenna, cw_antenna: std_logic;
signal motor_bridge, motor_encoder: std_logic_vector(1 downto 0);
begin
--
-- Clock synthesizer
--
clk_81_325: if C_clk_freq > 25 and C_cw_simple_out < 0 generate
-- no CW output (FM possible if enabled)
clkgen_video: entity work.clkgen
generic map (
C_clk_freq => C_clk_freq
)
port map (
clk_25m => clk_25m, ena_325m => ena_325m,
clk => clk, clk_325m => clk_325m, res => '0'
);
-- ena_325m <= R_dds_enable when R_fb_mode = "11" else '1';
ena_325m <= '1';
G_normal_gpio28: if not C_fmrds generate
j2_16 <= gpio_28;
end generate; -- G_normal_gpio28
G_fm_antenna: if C_fmrds generate
j2_16 <= fm_antenna;
end generate; -- G_fm_antenna
end generate;
clk_81_433: if C_clk_freq = 81 and C_cw_simple_out >= 0 generate
clkgen_tx433M33: entity work.clkgen
generic map (
C_clk_freq => C_clk_freq
)
port map (
clk_25m => clk_25m, ena_325m => '0',
clk => clk, clk_325m => open, res => '0'
);
ena_325m <= '0';
-- warning: from 81.25 MHz PLL produces 433.33 MHz
-- correct frequency should be 433.92 MHz
-- the difference results in reduced range
clk433M33gen: entity work.pll_81M25_433M33
port map (
CLK => clk, CLKOP => clk_433m
);
j2_16 <= cw_antenna;
end generate;
G_clk_25: if C_clk_freq = 25 generate -- 25 MHz CPU clock
clk <= clk_25m;
-- latice XP2 using 2 PLLs can generate correct frequency
-- 25 MHz -> 112.5 MHz -> 433.92 MHz
G_clk_25_112_433: if C_cw_simple_out >= 0 generate
clk112M5gen: entity work.pll_25M_112M5
port map (
CLK => clk_25m, CLKOP => clk_112m5,
lock => pll_lock
);
reset_when_clock_stable <= pll_lock;
-- reset assures clean start at power up
-- not only after upload of bitstream
gsr_inst_25MHz: GSR
port map (
gsr => reset_when_clock_stable
);
clk433M92gen: entity work.pll_112M5_433M92
port map (
CLK => clk_112m5, CLKOP => clk_433m
);
j2_16 <= cw_antenna;
end generate;
end generate; -- 25 MHz clock
btn <= btn_left & btn_right & btn_up & btn_down & btn_center;
inst_glue_xram: entity work.glue_xram
generic map (
C_clk_freq => C_clk_freq,
C_arch => C_arch,
C_big_endian => C_big_endian,
C_boot_rom => C_boot_rom,
C_mult_enable => C_mult_enable,
C_branch_likely => C_branch_likely,
C_sign_extend => C_sign_extend,
C_ll_sc => C_ll_sc,
C_PC_mask => C_PC_mask,
C_exceptions => C_exceptions,
C_cop0_count => C_cop0_count,
C_cop0_compare => C_cop0_compare,
C_cop0_config => C_cop0_config,
C_branch_prediction => C_branch_prediction,
C_full_shifter => C_full_shifter,
C_result_forwarding => C_result_forwarding,
C_load_aligner => C_load_aligner,
C_movn_movz => C_movn_movz,
C_debug => C_debug,
C_bram_size => C_bram_size,
-- C_i_rom_only => C_i_rom_only,
C_icache_size => C_icache_size, -- 0, 2, 4 or 8 KBytes
C_dcache_size => C_dcache_size, -- 0, 2, 4 or 8 KBytes
C_xram_base => C_xram_base,
C_cached_addr_bits => C_cached_addr_bits,
C_sram => C_sram,
C_sram_refresh => C_sram_refresh,
C_sram_wait_cycles => C_sram_wait_cycles, -- ISSI, OK do 87.5 MHz
C_sram_pipelined_read => C_sram_pipelined_read, -- works only at 81.25 MHz !!!
C_sio => C_sio,
C_spi => C_spi,
C_simple_out => C_simple_out,
C_simple_in => C_simple_in,
C_gpio => C_gpio,
-- vga simple bitmap
C_vgahdmi => C_vgahdmi,
C_vgahdmi_mode => C_video_mode,
C_vgahdmi_cache_size => C_vgahdmi_cache_size,
C_vgahdmi_cache_use_i => C_vgahdmi_cache_use_i,
C_vgahdmi_fifo_fast_ram => C_vgahdmi_fifo_fast_ram,
--C_vgahdmi_fifo_width => C_vgahdmi_fifo_width,
--C_vgahdmi_fifo_height => C_vgahdmi_fifo_height,
C_vgahdmi_fifo_data_width => C_vgahdmi_fifo_data_width,
--C_vgahdmi_fifo_addr_width => C_vgahdmi_fifo_addr_width,
-- led strip simple compositing bitmap only graphics
C_ledstrip => C_ledstrip,
C_ledstrip_full_circle => C_ledstrip_full_circle,
C_ledstrip_fifo_width => C_ledstrip_fifo_width,
C_ledstrip_fifo_height => C_ledstrip_fifo_height,
C_ledstrip_fifo_data_width => C_ledstrip_fifo_data_width,
C_ledstrip_fifo_addr_width => C_ledstrip_fifo_addr_width,
-- vga textmode
C_vgatext => C_vgatext,
C_vgatext_label => C_vgatext_label,
C_vgatext_mode => C_video_mode,
C_vgatext_bits => C_vgatext_bits,
C_vgatext_bram_mem => C_vgatext_bram_mem,
C_vgatext_bram_base => C_vgatext_bram_base,
C_vgatext_external_mem => C_vgatext_external_mem,
C_vgatext_reset => C_vgatext_reset,
C_vgatext_palette => C_vgatext_palette,
C_vgatext_text => C_vgatext_text,
C_vgatext_font_bram8 => C_vgatext_font_bram8,
-- C_vgatext_bus_write => C_vgatext_bus_write,
C_vgatext_bus_read => C_vgatext_bus_read,
C_vgatext_reg_read => C_vgatext_reg_read,
C_vgatext_text_fifo => C_vgatext_text_fifo,
C_vgatext_text_fifo_step => C_vgatext_text_fifo_step,
C_vgatext_text_fifo_width => C_vgatext_text_fifo_width,
C_vgatext_char_height => C_vgatext_char_height,
C_vgatext_font_height => C_vgatext_font_height,
C_vgatext_font_depth => C_vgatext_font_depth,
C_vgatext_font_linedouble => C_vgatext_font_linedouble,
C_vgatext_font_widthdouble => C_vgatext_font_widthdouble,
C_vgatext_monochrome => C_vgatext_monochrome,
C_vgatext_finescroll => C_vgatext_finescroll,
C_vgatext_cursor => C_vgatext_cursor,
C_vgatext_cursor_blink => C_vgatext_cursor_blink,
C_vgatext_bitmap => C_vgatext_bitmap,
C_vgatext_bitmap_depth => C_vgatext_bitmap_depth,
C_vgatext_bitmap_fifo => C_vgatext_bitmap_fifo,
C_vgatext_bitmap_fifo_step => C_vgatext_bitmap_fifo_step,
C_vgatext_bitmap_fifo_height => C_vgatext_bitmap_fifo_height,
C_vgatext_bitmap_fifo_data_width => C_vgatext_bitmap_fifo_data_width,
C_vgatext_bitmap_fifo_addr_width => C_vgatext_bitmap_fifo_addr_width,
C_pcm => C_pcm,
C_timer => C_timer,
C_pids => C_pids,
C_pid_simulator => C_pid_simulator, -- for each pid choose simulator/real
C_cw_simple_out => C_cw_simple_out, -- CW is for 433 MHz. -1 to disable. set (C_framebuffer => false, C_dds => false) for 433MHz transmitter
C_fmrds => C_fmrds, -- either FM or tx433
C_fm_stereo => C_fm_stereo,
C_fm_filter => C_fm_filter,
C_fm_downsample => C_fm_downsample,
C_rds_msg_len => C_rds_msg_len, -- bytes of RDS binary message, usually 52 (8-char PS) or 260 (8 PS + 64 RT)
C_fmdds_hz => C_fmdds_hz, -- Hz clk_fmdds (>2*108 MHz, e.g. 250 MHz, 325 MHz)
C_rds_clock_multiply => C_rds_clock_multiply, -- multiply and divide from cpu clk 81.25 MHz
C_rds_clock_divide => C_rds_clock_divide -- to get 1.824 MHz for RDS logic
--C_dds => C_dds
)
port map (
clk => clk,
clk_pixel => clk_25m,
clk_fmdds => clk_325m,
clk_cw => clk_433m,
sio_txd(0) => rs232_tx, sio_rxd(0) => rs232_rx, sio_break(0) => rs232_break,
spi_sck(0) => flash_sck, spi_ss(0) => flash_cen,
spi_mosi(0) => flash_si, spi_miso(0) => flash_so,
spi_sck(1) => sdcard_sck, spi_ss(1) => sdcard_cen,
spi_mosi(1) => sdcard_si, spi_miso(1) => sdcard_so,
jack_ring(3) => p_ring,
jack_tip => p_tip,
simple_out(7 downto 0) => led(7 downto 0),
simple_in(4 downto 0) => btn,
simple_in(19 downto 16) => sw,
gpio(0) => j1_2, gpio(1) => j1_3, gpio(2) => j1_4, gpio(3) => j1_8,
gpio(4) => j1_9, gpio(5) => j1_4, gpio(6) => j1_14, gpio(7) => j1_15,
gpio(8) => j1_16, gpio(9) => j1_17, gpio(10) => j1_18, gpio(11) => j1_19,
gpio(12) => j1_20, gpio(13) => j1_21, gpio(14) => j1_22, gpio(15) => j1_23,
-- gpio(27 downto 16) multifuncition GPIO/VGA/PID
-- **** GPIO **** gpio(27 downto 16)
--gpio(16) => j2_2, gpio(17) => j2_3, gpio(18) => j2_4, gpio(19) => j2_5, -- PID0
--gpio(20) => j2_6, gpio(21) => j2_7, gpio(22) => j2_8, gpio(23) => j2_9, -- PID1
--gpio(24) => j2_10, gpio(25) => j2_11, gpio(26) => j2_12, gpio(27) => j2_13, -- PID2
-- **** PID **** gpio(27 downto 16)
--pid_encoder_a(0) => j2_2, pid_encoder_b(0) => j2_3, pid_bridge_f(0) => j2_4, pid_bridge_r(0) => j2_5, -- PID0
--pid_encoder_a(1) => j2_6, pid_encoder_b(1) => j2_7, pid_bridge_f(1) => j2_8, pid_bridge_r(1) => j2_9, -- PID1
--pid_encoder_a(2) => j2_10, pid_encoder_b(2) => j2_11, pid_bridge_f(2) => j2_12, pid_bridge_r(2) => j2_13, -- PID2
-- **** LEDSTRIP ****, gpio the rest
--ledstrip_rotation => j2_2, -- motor provides only a single channel pulse for the counter
--ledstrip_out(0) => j2_6, ledstrip_out(1) => j2_7, -- ws2812b outputs
--gpio(16) => open, gpio(17) => open, gpio(18) => j2_4, gpio(19) => j2_5,
--gpio(20) => open, gpio(21) => open, gpio(22) => j2_8, gpio(23) => j2_9,
--gpio(24) => j2_10, gpio(25) => j2_11, gpio(26) => j2_12, gpio(27) => j2_13,
-- **** VGA **** gpio(27 downto 16)
vga_vsync => j2_3,
vga_hsync => j2_4,
vga_b(5) => j2_5, vga_b(6) => j2_6, vga_b(7) => j2_7,
vga_g(5) => j2_8, vga_g(6) => j2_9, vga_g(7) => j2_10,
vga_r(5) => j2_11, vga_r(6) => j2_12, vga_r(7) => j2_13,
-- gpio(28) multifunction: antenna
gpio(28) => gpio_28, -- j2_16
cw_antenna => cw_antenna, -- output 433MHz
fm_antenna => fm_antenna, -- output 87-108MHz
sram_a(18 downto 0) => sram_a, sram_d => sram_d,
sram_lbl => sram_lbl, sram_ubl => sram_ubl,
sram_wel => sram_wel
);
-- simulation for the ledstrip motor (forward-only motor)
ledstrip_motor_simulation: if false generate
motor_bridge <= '0' & led(1); -- led(1) is PWM out (arduino pin 9 in Fade example)
motor: entity work.simotor
generic map
(
prescaler => 4,
motor_power => 4, -- acceleration
motor_speed => 20, -- inverse log2 friction proportional to speed
-- larger motor_speed values allow higher motor top speed
motor_friction => 1 -- static friction
)
port map
(
clock => clk,
bridge => motor_bridge,
encoder => motor_encoder
);
end generate; -- ledstrip_motor_simulation
end Behavioral;
|
<reponame>stnolting/neo430
-- #################################################################################################
-- # << NEO430 - Processor Top Entity using resolved signal types (std_logic) only >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, <NAME>. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_top_std_logic is
generic (
-- general configuration --
CLOCK_SPEED : natural := 100000000; -- main clock in Hz
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := true; -- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
GPIO_USE : boolean := true; -- implement GPIO unit? (default=true)
TIMER_USE : boolean := true; -- implement timer? (default=true)
UART_USE : boolean := true; -- implement UART? (default=true)
CRC_USE : boolean := true; -- implement CRC unit? (default=true)
CFU_USE : boolean := false; -- implement custom functions unit? (default=false)
PWM_USE : boolean := true; -- implement PWM controller?
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
TRNG_USE : boolean := false; -- implement TRNG? (default=false)
EXIRQ_USE : boolean := true; -- implement EXIRQ? (default=true)
FREQ_GEN_USE : boolean := true; -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
);
port (
-- global control --
clk_i : in std_logic; -- global clock, rising edge
rst_i : in std_logic; -- global reset, async, low-active
-- gpio --
gpio_o : out std_logic_vector(15 downto 0); -- parallel output
gpio_i : in std_logic_vector(15 downto 0); -- parallel input
-- pwm channels --
pwm_o : out std_logic_vector(03 downto 0); -- pwm channels
-- arbitrary frequency generator --
freq_gen_o : out std_logic_vector(02 downto 0); -- programmable frequency output
-- serial com --
uart_txd_o : out std_logic; -- UART send data
uart_rxd_i : in std_logic; -- UART receive data
spi_sclk_o : out std_logic; -- serial clock line
spi_mosi_o : out std_logic; -- serial data line out
spi_miso_i : in std_logic; -- serial data line in
spi_cs_o : out std_logic_vector(05 downto 0); -- SPI CS
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- 32-bit wishbone interface --
wb_adr_o : out std_logic_vector(31 downto 0); -- address
wb_dat_i : in std_logic_vector(31 downto 0); -- read data
wb_dat_o : out std_logic_vector(31 downto 0); -- write data
wb_we_o : out std_logic; -- read/write
wb_sel_o : out std_logic_vector(03 downto 0); -- byte enable
wb_stb_o : out std_logic; -- strobe
wb_cyc_o : out std_logic; -- valid cycle
wb_ack_i : in std_logic; -- transfer acknowledge
-- external interrupts --
ext_irq_i : in std_logic_vector(07 downto 0); -- external interrupt request lines
ext_ack_o : out std_logic_vector(07 downto 0) -- external interrupt request acknowledges
);
end neo430_top_std_logic;
architecture neo430_top_std_logic_rtl of neo430_top_std_logic is
-- other signals for conversion --
constant usrcode_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(USER_CODE);
signal clk_i_int : std_ulogic;
signal rst_i_int : std_ulogic;
signal gpio_o_int : std_ulogic_vector(15 downto 0);
signal gpio_i_int : std_ulogic_vector(15 downto 0);
signal pwm_o_int : std_ulogic_vector(03 downto 0);
signal uart_txd_o_int : std_ulogic;
signal uart_rxd_i_int : std_ulogic;
signal spi_sclk_o_int : std_ulogic;
signal spi_mosi_o_int : std_ulogic;
signal spi_miso_i_int : std_ulogic;
signal spi_cs_o_int : std_ulogic_vector(05 downto 0);
signal irq_i_int : std_ulogic_vector(07 downto 0);
signal irq_ack_o_int : std_ulogic_vector(07 downto 0);
signal wb_adr_o_int : std_ulogic_vector(31 downto 0);
signal wb_dat_i_int : std_ulogic_vector(31 downto 0);
signal wb_dat_o_int : std_ulogic_vector(31 downto 0);
signal wb_we_o_int : std_ulogic;
signal wb_sel_o_int : std_ulogic_vector(03 downto 0);
signal wb_stb_o_int : std_ulogic;
signal wb_cyc_o_int : std_ulogic;
signal wb_ack_i_int : std_ulogic;
signal freq_gen_o_int : std_ulogic_vector(02 downto 0);
begin
-- CPU ----------------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_top_inst: neo430_top
generic map (
-- general configuration --
CLOCK_SPEED => CLOCK_SPEED, -- main clock in Hz
IMEM_SIZE => IMEM_SIZE, -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE => DMEM_SIZE, -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE => usrcode_c, -- custom user code
-- module configuration --
MULDIV_USE => MULDIV_USE, -- implement multiplier/divider unit? (default=true)
WB32_USE => WB32_USE, -- implement WB32 unit? (default=true)
WDT_USE => WDT_USE, -- implement WDT? (default=true)
GPIO_USE => GPIO_USE, -- implement GPIO unit? (default=true)
TIMER_USE => TIMER_USE, -- implement timer? (default=true)
UART_USE => UART_USE, -- implement UART? (default=true)
CRC_USE => CRC_USE, -- implement CRC unit? (default=true)
CFU_USE => CFU_USE, -- implement CF unit? (default=false)
PWM_USE => PWM_USE, -- implement PWM controller? (default=true)
TWI_USE => TWI_USE, -- implement two wire serial interface? (default=true)
SPI_USE => SPI_USE, -- implement SPI? (default=true)
TRNG_USE => TRNG_USE, -- implement TRNG? (default=false)
EXIRQ_USE => EXIRQ_USE, -- implement EXIRQ? (default=true)
FREQ_GEN_USE => FREQ_GEN_USE, -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory? (default=false)
)
port map (
-- global control --
clk_i => clk_i_int, -- global clock, rising edge
rst_i => rst_i_int, -- global reset, async, low-active
-- parallel io --
gpio_o => gpio_o_int, -- parallel output
gpio_i => gpio_i_int, -- parallel input
-- pwm channels --
pwm_o => pwm_o_int, -- pwm channels
-- arbitrary frequency generator --
freq_gen_o => freq_gen_o_int, -- programmable frequency output
-- serial com --
uart_txd_o => uart_txd_o_int, -- UART send data
uart_rxd_i => uart_rxd_i_int, -- UART receive data
spi_sclk_o => spi_sclk_o_int, -- serial clock line
spi_mosi_o => spi_mosi_o_int, -- serial data line out
spi_miso_i => spi_miso_i_int, -- serial data line in
spi_cs_o => spi_cs_o_int, -- SPI CS 0..7
twi_sda_io => twi_sda_io, -- twi serial data line
twi_scl_io => twi_scl_io, -- twi serial clock line
-- 32-bit wishbone interface --
wb_adr_o => wb_adr_o_int, -- address
wb_dat_i => wb_dat_i_int, -- read data
wb_dat_o => wb_dat_o_int, -- write data
wb_we_o => wb_we_o_int, -- read/write
wb_sel_o => wb_sel_o_int, -- byte enable
wb_stb_o => wb_stb_o_int, -- strobe
wb_cyc_o => wb_cyc_o_int, -- valid cycle
wb_ack_i => wb_ack_i_int, -- transfer acknowledge
-- interrupts --
ext_irq_i => irq_i_int, -- external interrupt request line
ext_ack_o => irq_ack_o_int -- external interrupt request acknowledge
);
-- Type Conversion ----------------------------------------------------------
-- -----------------------------------------------------------------------------
clk_i_int <= std_ulogic(clk_i);
rst_i_int <= std_ulogic(rst_i);
gpio_i_int <= std_ulogic_vector(gpio_i);
uart_rxd_i_int <= std_ulogic(uart_rxd_i);
spi_miso_i_int <= std_ulogic(spi_miso_i);
wb_dat_i_int <= std_ulogic_vector(wb_dat_i);
wb_ack_i_int <= std_ulogic(wb_ack_i);
irq_i_int <= std_ulogic_vector(ext_irq_i);
gpio_o <= std_logic_vector(gpio_o_int);
pwm_o <= std_logic_vector(pwm_o_int);
uart_txd_o <= std_logic(uart_txd_o_int);
spi_sclk_o <= std_logic(spi_sclk_o_int);
spi_mosi_o <= std_logic(spi_mosi_o_int);
spi_cs_o <= std_logic_vector(spi_cs_o_int);
wb_adr_o <= std_logic_vector(wb_adr_o_int);
wb_dat_o <= std_logic_vector(wb_dat_o_int);
wb_we_o <= std_logic(wb_we_o_int);
wb_sel_o <= std_logic_vector(wb_sel_o_int);
wb_stb_o <= std_logic(wb_stb_o_int);
wb_cyc_o <= std_logic(wb_cyc_o_int);
ext_ack_o <= std_logic_vector(irq_ack_o_int);
freq_gen_o <= std_logic_vector(freq_gen_o_int);
end neo430_top_std_logic_rtl;
|
-- =============================================================================
-- Whatis : testbench
-- Project : FPGA-LPLIB_DSP
-- -----------------------------------------------------------------------------
-- File : tb_polymac_3ord.vhd
-- Language : VHDL-93
-- Module : tb
-- Library : lplib_dsp_verif
-- -----------------------------------------------------------------------------
-- Author(s) : <NAME> <pilato[punto]lu[chiocciola]gmail[punto]com>
--
-- Company :
-- Addr :
-- -----------------------------------------------------------------------------
-- Description
--
-- -----------------------------------------------------------------------------
-- Dependencies
--
-- lplib_dsp.polymac_3ord(rtl)
--
-- -----------------------------------------------------------------------------
-- Issues
--
-- -----------------------------------------------------------------------------
-- Copyright (c) 2021 <NAME>
-- MIT License
-- -----------------------------------------------------------------------------
-- date who changes
-- 2021-04-29 <NAME> file creation
-- =============================================================================
-- STD lib
-- ----------------------------------------
use std.textio.all;
-- IEEE lib
-- ----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_textio.all;
-- User lib
-- ----------------------------------------
library lplib_dsp;
-- library lplib_dsp_verif;
entity tb is
end entity tb;
architecture beh of tb is
-- TB common parameters and signals
-- ----------------------------------------
constant RST_POL : std_logic := '0';
-- constant CLK_FREQ : positive := 50000000; -- 50 MHz (20 ns)
-- constant CLK_FREQ : positive := 33000000; -- 33 MHz (30.303 ns)
-- constant CLK_FREQ : positive := 25000000; -- 25 MHz (40 ns)
-- constant CLK_FREQ : positive := 20000000; -- 20 MHz (50 ns)
constant CLK_FREQ : positive := 10000000; -- 10 MHz (100 ns)
--
constant TCLK : time := 1.0e10/real(CLK_FREQ) * (0.1 ns); -- clock period
constant DUTYCLK : real := 0.5; -- clock duty-cycle
signal en_clk : std_logic;
--
signal clk : std_logic := '0';
signal rst : std_logic := RST_POL;
--
signal tcase : integer := 0;
-- Check Process
-- ----------------------------------------
signal err_counter : integer := 0;
signal check_err_counter : integer := 0;
-- Constant
-- ----------------------------------------
constant N : integer := 4;
constant K : integer := 0;
-- Signals
-- ----------------------------------------
signal x : std_logic_vector(N-1 downto 0);
signal a : std_logic_vector(N-1 downto 0);
signal b : std_logic_vector(N-1 downto 0);
signal c : std_logic_vector(N-1 downto 0);
signal d : std_logic_vector(N-1 downto 0);
signal go : std_logic;
signal ready : std_logic;
signal y : std_logic_vector(N-1 downto 0);
-- Procedures
-- ----------------------------------------
type str_ptr is access string;
--
procedure print_tcase (
signal tcase : in integer;
variable msg_ptr : in str_ptr
) is
begin
wait for 0 ns; -- trick to update signals
write(OUTPUT, "################################################################");
write(OUTPUT, ">>> tcase: " & integer'image(tcase));
write(OUTPUT, ">>> " & msg_ptr.all);
write(OUTPUT, ">>> VHDL time now " & time'image(now) & LF);
write(OUTPUT, "################################################################");
end procedure print_tcase;
--
procedure print_msg (
variable msg_ptr : in str_ptr
) is
begin
-- wait for 0 ns; -- trick to update signals
write(OUTPUT, ">>> " & msg_ptr.all);
write(OUTPUT, ">>> VHDL time now " & time'image(now) & LF);
end procedure print_msg;
begin
-- clock generator 50%
-- ----------------------------------------
clk <= not clk after TCLK/2 when en_clk='1' else '0';
-- Unit(s) Under Test
-- ----------------------------------------
i_polymac_3ord: entity lplib_dsp.polymac_3ord(rtl)
generic map (
RST_POL => RST_POL ,
N => N , -- the actual data width
K => K -- the range extension
)
port map (
clk => clk ,
rst => rst ,
x => x ,
a => a ,
b => b ,
c => c ,
d => d ,
go => go ,
ready => ready ,
y => y
);
-- Drive Process
-- ----------------------------------------
proc_drive: process
constant YMAX : integer := +2**(N-1)-1;
constant YMIN : integer := -2**(N-1);
constant YFBMAX : integer := +2**(N+K-1)-1;
constant YFBMIN : integer := -2**(N+K-1);
variable msg_ptr : str_ptr := NULL;
variable y_check : integer;
begin
tcase <= 0;
msg_ptr := new string'("SIMULATION START");
print_tcase(tcase, msg_ptr);
--
x <= std_logic_vector(TO_SIGNED(0,N));
a <= std_logic_vector(TO_SIGNED(0,N));
b <= std_logic_vector(TO_SIGNED(0,N));
c <= std_logic_vector(TO_SIGNED(0,N));
d <= std_logic_vector(TO_SIGNED(0,N));
go <= '0';
--
--
--
wait for 123 ns;
en_clk <= '1';
wait for 123 ns;
wait until falling_edge(clk);
-- reset release
rst <= not RST_POL;
wait for 123 ns;
wait until rising_edge(clk);
--
--
--
--
--
--
-- ========================================================
tcase <= 1;
msg_ptr := new string'("sinusoid approximation 3ord polynomials");
print_tcase(tcase, msg_ptr);
wait until rising_edge(clk);
--
d <= std_logic_vector(TO_SIGNED(0,N));
c <= std_logic_vector(TO_SIGNED(YMAX,N));
b <= std_logic_vector(TO_SIGNED(0,N));
a <= std_logic_vector(TO_SIGNED(YMIN,N));
for i in 0 to 1000 loop
for xx in YMIN to YMAX loop
x <= std_logic_vector(TO_SIGNED(xx,N));
go <= '1';
wait until rising_edge(clk);
go <= '0';
wait until rising_edge(clk) and ready='1';
end loop;
end loop;
--
wait for 300 us;
--
--
-- ========================================================
tcase <= 2;
msg_ptr := new string'("swap all 3ord polynomials");
print_tcase(tcase, msg_ptr);
wait until rising_edge(clk);
--
--
--
-- YMAX eq to XMAX
-- YMIN eq to XMIN
for dd in YMIN to YMAX loop
d <= std_logic_vector(TO_SIGNED(dd,N));
for cc in YMIN to YMAX loop
c <= std_logic_vector(TO_SIGNED(cc,N));
for bb in YMIN to YMAX loop
b <= std_logic_vector(TO_SIGNED(bb,N));
for aa in YMIN to YMAX loop
a <= std_logic_vector(TO_SIGNED(aa,N));
for xx in YMIN to YMAX loop
x <= std_logic_vector(TO_SIGNED(xx,N));
go <= '1';
wait until rising_edge(clk);
go <= '0';
wait until rising_edge(clk) and ready='1';
--
-- integer computation check
--
-- loop1
y_check := xx*aa + 2**(N-1)*bb;
-- trunc
y_check := integer(FLOOR(real(y_check)/2.0**(N-1)));
-- feedback sat
if y_check > YFBMAX then
y_check := YFBMAX;
elsif y_check < YFBMIN then
y_check := YFBMIN;
end if;
--
-- loop2
y_check := xx*y_check + 2**(N-1)*cc;
-- trunc
y_check := integer(FLOOR(real(y_check)/2.0**(N-1)));
-- feedback sat
if y_check > YFBMAX then
y_check := YFBMAX;
elsif y_check < YFBMIN then
y_check := YFBMIN;
end if;
--
-- loop3
y_check := xx*y_check + 2**(N-1)*dd;
-- trunc
y_check := integer(FLOOR(real(y_check)/2.0**(N-1)));
-- final sat
if y_check > YMAX then
y_check := YMAX;
elsif y_check < YMIN then
y_check := YMIN;
end if;
--
-- check
if TO_INTEGER(signed(y)) /= y_check then
msg_ptr := new string'(
"ERROR: expected " & integer'image(y_check) &
" got " & integer'image(TO_INTEGER(signed(y)))
);
print_msg(msg_ptr);
err_counter <= err_counter + 1;
end if;
--
end loop;
wait for 10 us;
wait until rising_edge(clk);
end loop;
wait for 20 us;
wait until rising_edge(clk);
end loop;
wait for 30 us;
wait until rising_edge(clk);
end loop;
wait for 40 us;
wait until rising_edge(clk);
end loop;
--
--
wait for 300 us;
--
--
--
-- ========================================================
tcase <= -1;
wait until rising_edge(clk);
--
wait for 333 ns;
wait until rising_edge(clk);
rst <= '0';
wait for 333 ns;
en_clk <= '0';
wait for 333 ns;
--
err_counter <= err_counter + check_err_counter;
wait for 333 ns;
--
--
write(OUTPUT, "================================================================");
write(OUTPUT, ">>> SIMULATION END");
write(OUTPUT, ">>> VHDL time now " & time'image(now) & LF);
-- write(OUTPUT, "Time now " & to_string(now)); -- if VHDL-2008
write(OUTPUT, "================================================================");
if err_counter /= 0 then
write(OUTPUT, ">>> TEST FAILED ...sorry");
else
write(OUTPUT, ">>> TEST SUCCESS ...Wubba Lubba Dub Dub!");
end if;
write(OUTPUT, ">>> err_counter: " & integer'image(err_counter));
write(OUTPUT, "================================================================");
--
wait;
end process proc_drive;
end beh;
|
<gh_stars>1-10
-----------------------------------------------------------------
-- COMPANY : Ruhr University Bochum
-- AUTHOR : <NAME> (<EMAIL>) and <NAME> (<EMAIL>)
-- DOCUMENT: [New First-Order Secure AES Performance Records](IACR Transactions on Cryptographic Hardware and Embeded Systems 2021(2))
-- -----------------------------------------------------------------
--
-- Copyright (c) 2021, <NAME>, <NAME>,
--
-- All rights reserved.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTERS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Please see LICENSE and README for license and further instructions.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Round is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
Dec : in STD_LOGIC;
FirstKey : in STD_LOGIC;
FinalRound : in STD_LOGIC;
KeyRegEn : in STD_LOGIC;
Rcon : in STD_LOGIC_VECTOR ( 7 downto 0);
InputData : in STD_LOGIC_VECTOR (127 downto 0);
InputKey : in STD_LOGIC_VECTOR (127 downto 0);
AddRoundKeyOutput : out STD_LOGIC_VECTOR (127 downto 0);
SBoxOutput : in STD_LOGIC_VECTOR (127 downto 0);
KeySboxInput : out STD_LOGIC_VECTOR ( 31 downto 0);
KeySboxOutput : in STD_LOGIC_VECTOR ( 31 downto 0));
end Round;
architecture Behavioral of Round is
---------------------------------
---- Encryption Process ---------
signal MuxOutput : STD_LOGIC_VECTOR(127 downto 0);
signal Reg_SBoxOutput : STD_LOGIC_VECTOR(127 downto 0);
signal ShiftRowOutput : STD_LOGIC_VECTOR(127 downto 0);
signal ShiftRowInvOutput : STD_LOGIC_VECTOR(127 downto 0);
signal MCOutput : STD_LOGIC_VECTOR(127 downto 0);
signal Selected_SR : STD_LOGIC_VECTOR(127 downto 0);
signal FeedBack : STD_LOGIC_VECTOR(127 downto 0);
signal s0, s1, s2, s3 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s4, s5, s6, s7 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s8, s9, s10, s11 : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal s12, s13, s14, s15 : STD_LOGIC_VECTOR (7 DOWNTO 0);
---------------------------------
signal SR0, SR1, SR2, SR3 : STD_LOGIC_VECTOR(7 downto 0);
signal SR4, SR5, SR6, SR7 : STD_LOGIC_VECTOR(7 downto 0);
signal SR8, SR9, SR10, SR11 : STD_LOGIC_VECTOR(7 downto 0);
signal SR12, SR13, SR14, SR15 : STD_LOGIC_VECTOR(7 downto 0);
signal SR0_2, SR4_6, SR8_10, SR12_14 : STD_LOGIC_VECTOR(7 downto 0);
signal SR1_3, SR5_7, SR9_11, SR13_15 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult20_2, Mult24_6, Mult28_10, Mult212_14 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult21_3, Mult25_7, Mult29_11, Mult213_15 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult40_2, Mult44_6, Mult48_10, Mult412_14 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult41_3, Mult45_7, Mult49_11, Mult413_15 : STD_LOGIC_VECTOR(7 downto 0);
signal PI0, PI1, PI2, PI3 : STD_LOGIC_VECTOR(7 downto 0);
signal PI4, PI5, PI6, PI7 : STD_LOGIC_VECTOR(7 downto 0);
signal PI8, PI9, PI10, PI11 : STD_LOGIC_VECTOR(7 downto 0);
signal PI12, PI13, PI14, PI15 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult2PI0, Mult2PI1, Mult2PI2, Mult2PI3 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult2PI4, Mult2PI5, Mult2PI6, Mult2PI7 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult2PI8, Mult2PI9, Mult2PI10, Mult2PI11 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult2PI12, Mult2PI13, Mult2PI14, Mult2PI15 : STD_LOGIC_VECTOR(7 downto 0);
---------------------------------
---- Key Schedule ---------------
signal KeyMUXOutput : STD_LOGIC_VECTOR(127 downto 0);
signal ShiftedSBKey : STD_LOGIC_VECTOR( 31 downto 0);
signal w0, w1, w2, w3 : STD_LOGIC_VECTOR( 31 downto 0);
signal KeyExpansionOutput : STD_LOGIC_VECTOR(127 downto 0);
signal KeyStateRegOutput : STD_LOGIC_VECTOR(127 downto 0);
signal Selected_Key : STD_LOGIC_VECTOR(127 downto 0);
signal w1dec, w2dec, w3dec : STD_LOGIC_VECTOR( 31 downto 0);
signal MCInvK : STD_LOGIC_VECTOR(127 downto 0);
signal K0, K1, K2, K3 : STD_LOGIC_VECTOR(7 downto 0);
signal K4, K5, K6, K7 : STD_LOGIC_VECTOR(7 downto 0);
signal K8, K9, K10, K11 : STD_LOGIC_VECTOR(7 downto 0);
signal K12, K13, K14, K15 : STD_LOGIC_VECTOR(7 downto 0);
signal K0_2, K4_6, K8_10, K12_14 : STD_LOGIC_VECTOR(7 downto 0);
signal K1_3, K5_7, K9_11, K13_15 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult2K0_2, Mult2K4_6, Mult2K8_10, Mult2K12_14 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult2K1_3, Mult2K5_7, Mult2K9_11, Mult2K13_15 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult4K0_2, Mult4K4_6, Mult4K8_10, Mult4K12_14 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult4K1_3, Mult4K5_7, Mult4K9_11, Mult4K13_15 : STD_LOGIC_VECTOR(7 downto 0);
signal PIK0, PIK1, PIK2, PIK3 : STD_LOGIC_VECTOR(7 downto 0);
signal PIK4, PIK5, PIK6, PIK7 : STD_LOGIC_VECTOR(7 downto 0);
signal PIK8, PIK9, PIK10, PIK11 : STD_LOGIC_VECTOR(7 downto 0);
signal PIK12, PIK13, PIK14, PIK15 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult2PIK0, Mult2PIK1, Mult2PIK2, Mult2PIK3 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult2PIK4, Mult2PIK5, Mult2PIK6, Mult2PIK7 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult2PIK8, Mult2PIK9, Mult2PIK10, Mult2PIK11 : STD_LOGIC_VECTOR(7 downto 0);
signal Mult2PIK12, Mult2PIK13, Mult2PIK14, Mult2PIK15 : STD_LOGIC_VECTOR(7 downto 0);
begin
---------------------------------
---- Encryption Process ---------
MuxOutput <= InputData when rst = '1' else FeedBack;
AddRoundKeyOutput <= MuxOutput XOR Selected_Key;
---------------------------------
reg_gen: PROCESS(clk, ShiftRowOutput)
BEGIN
IF RISING_EDGE(clk) THEN
Reg_SBoxOutput <= SBoxOutput;
END IF;
END PROCESS;
---------------------------------
s15 <= Reg_SBoxOutput(8*16-1 downto 8*15);
s14 <= Reg_SBoxOutput(8*15-1 downto 8*14);
s13 <= Reg_SBoxOutput(8*14-1 downto 8*13);
s12 <= Reg_SBoxOutput(8*13-1 downto 8*12);
s11 <= Reg_SBoxOutput(8*12-1 downto 8*11);
s10 <= Reg_SBoxOutput(8*11-1 downto 8*10);
s9 <= Reg_SBoxOutput(8*10-1 downto 8*9);
s8 <= Reg_SBoxOutput(8*9-1 downto 8*8);
s7 <= Reg_SBoxOutput(8*8-1 downto 8*7);
s6 <= Reg_SBoxOutput(8*7-1 downto 8*6);
s5 <= Reg_SBoxOutput(8*6-1 downto 8*5);
s4 <= Reg_SBoxOutput(8*5-1 downto 8*4);
s3 <= Reg_SBoxOutput(8*4-1 downto 8*3);
s2 <= Reg_SBoxOutput(8*3-1 downto 8*2);
s1 <= Reg_SBoxOutput(8*2-1 downto 8*1);
s0 <= Reg_SBoxOutput(8*1-1 downto 8*0);
ShiftRowOutput <= s11 & s6 & s1 & s12 & s7 & s2 & s13 & s8 & s3 & s14 & s9 & s4 & s15 & s10 & s5 & s0;
ShiftRowInvOutput <= s3 & s6 & s9 & s12 & s15 & s2 & s5 & s8 & s11 & s14 & s1 & s4 & s7 & s10 & s13 & s0;
Selected_SR <= ShiftRowOutput when Dec = '0' else ShiftRowInvOutput;
---------------------------------
SR15 <= Selected_SR(8*16-1 downto 8*15);
SR14 <= Selected_SR(8*15-1 downto 8*14);
SR13 <= Selected_SR(8*14-1 downto 8*13);
SR12 <= Selected_SR(8*13-1 downto 8*12);
SR11 <= Selected_SR(8*12-1 downto 8*11);
SR10 <= Selected_SR(8*11-1 downto 8*10);
SR9 <= Selected_SR(8*10-1 downto 8*9);
SR8 <= Selected_SR(8*9-1 downto 8*8);
SR7 <= Selected_SR(8*8-1 downto 8*7);
SR6 <= Selected_SR(8*7-1 downto 8*6);
SR5 <= Selected_SR(8*6-1 downto 8*5);
SR4 <= Selected_SR(8*5-1 downto 8*4);
SR3 <= Selected_SR(8*4-1 downto 8*3);
SR2 <= Selected_SR(8*3-1 downto 8*2);
SR1 <= Selected_SR(8*2-1 downto 8*1);
SR0 <= Selected_SR(8*1-1 downto 8*0);
---------------------------------
SR0_2 <= SR0 XOR SR2;
SR1_3 <= SR1 XOR SR3;
SR4_6 <= SR4 XOR SR6;
SR5_7 <= SR5 XOR SR7;
SR8_10 <= SR8 XOR SR10;
SR9_11 <= SR9 XOR SR11;
SR12_14 <= SR12 XOR SR14;
SR13_15 <= SR13 XOR SR15;
Mult20_2 <= (SR0_2(6 downto 0) & "0") XOR ("000" & SR0_2(7) & SR0_2(7) & "0" & SR0_2(7) & SR0_2(7));
Mult21_3 <= (SR1_3(6 downto 0) & "0") XOR ("000" & SR1_3(7) & SR1_3(7) & "0" & SR1_3(7) & SR1_3(7));
Mult24_6 <= (SR4_6(6 downto 0) & "0") XOR ("000" & SR4_6(7) & SR4_6(7) & "0" & SR4_6(7) & SR4_6(7));
Mult25_7 <= (SR5_7(6 downto 0) & "0") XOR ("000" & SR5_7(7) & SR5_7(7) & "0" & SR5_7(7) & SR5_7(7));
Mult28_10 <= (SR8_10(6 downto 0) & "0") XOR ("000" & SR8_10(7) & SR8_10(7) & "0" & SR8_10(7) & SR8_10(7));
Mult29_11 <= (SR9_11(6 downto 0) & "0") XOR ("000" & SR9_11(7) & SR9_11(7) & "0" & SR9_11(7) & SR9_11(7));
Mult212_14 <= (SR12_14(6 downto 0) & "0") XOR ("000" & SR12_14(7) & SR12_14(7) & "0" & SR12_14(7) & SR12_14(7));
Mult213_15 <= (SR13_15(6 downto 0) & "0") XOR ("000" & SR13_15(7) & SR13_15(7) & "0" & SR13_15(7) & SR13_15(7));
Mult40_2 <= (Mult20_2(6 downto 0) & "0") XOR ("000" & Mult20_2(7) & Mult20_2(7) & "0" & Mult20_2(7) & Mult20_2(7));
Mult41_3 <= (Mult21_3(6 downto 0) & "0") XOR ("000" & Mult21_3(7) & Mult21_3(7) & "0" & Mult21_3(7) & Mult21_3(7));
Mult44_6 <= (Mult24_6(6 downto 0) & "0") XOR ("000" & Mult24_6(7) & Mult24_6(7) & "0" & Mult24_6(7) & Mult24_6(7));
Mult45_7 <= (Mult25_7(6 downto 0) & "0") XOR ("000" & Mult25_7(7) & Mult25_7(7) & "0" & Mult25_7(7) & Mult25_7(7));
Mult48_10 <= (Mult28_10(6 downto 0) & "0") XOR ("000" & Mult28_10(7) & Mult28_10(7) & "0" & Mult28_10(7) & Mult28_10(7));
Mult49_11 <= (Mult29_11(6 downto 0) & "0") XOR ("000" & Mult29_11(7) & Mult29_11(7) & "0" & Mult29_11(7) & Mult29_11(7));
Mult412_14 <= (Mult212_14(6 downto 0) & "0") XOR ("000" & Mult212_14(7) & Mult212_14(7) & "0" & Mult212_14(7) & Mult212_14(7));
Mult413_15 <= (Mult213_15(6 downto 0) & "0") XOR ("000" & Mult213_15(7) & Mult213_15(7) & "0" & Mult213_15(7) & Mult213_15(7));
PI0 <= (SR0 XOR Mult40_2) when Dec = '1' else SR0;
PI1 <= (SR1 XOR Mult41_3) when Dec = '1' else SR1;
PI2 <= (SR2 XOR Mult40_2) when Dec = '1' else SR2;
PI3 <= (SR3 XOR Mult41_3) when Dec = '1' else SR3;
PI4 <= (SR4 XOR Mult44_6) when Dec = '1' else SR4;
PI5 <= (SR5 XOR Mult45_7) when Dec = '1' else SR5;
PI6 <= (SR6 XOR Mult44_6) when Dec = '1' else SR6;
PI7 <= (SR7 XOR Mult45_7) when Dec = '1' else SR7;
PI8 <= (SR8 XOR Mult48_10) when Dec = '1' else SR8;
PI9 <= (SR9 XOR Mult49_11) when Dec = '1' else SR9;
PI10 <= (SR10 XOR Mult48_10) when Dec = '1' else SR10;
PI11 <= (SR11 XOR Mult49_11) when Dec = '1' else SR11;
PI12 <= (SR12 XOR Mult412_14) when Dec = '1' else SR12;
PI13 <= (SR13 XOR Mult413_15) when Dec = '1' else SR13;
PI14 <= (SR14 XOR Mult412_14) when Dec = '1' else SR14;
PI15 <= (SR15 XOR Mult413_15) when Dec = '1' else SR15;
Mult2PI0 <= (PI0(6 downto 0) & "0") XOR ("000" & PI0(7) & PI0(7) & "0" & PI0(7) & PI0(7));
Mult2PI1 <= (PI1(6 downto 0) & "0") XOR ("000" & PI1(7) & PI1(7) & "0" & PI1(7) & PI1(7));
Mult2PI2 <= (PI2(6 downto 0) & "0") XOR ("000" & PI2(7) & PI2(7) & "0" & PI2(7) & PI2(7));
Mult2PI3 <= (PI3(6 downto 0) & "0") XOR ("000" & PI3(7) & PI3(7) & "0" & PI3(7) & PI3(7));
Mult2PI4 <= (PI4(6 downto 0) & "0") XOR ("000" & PI4(7) & PI4(7) & "0" & PI4(7) & PI4(7));
Mult2PI5 <= (PI5(6 downto 0) & "0") XOR ("000" & PI5(7) & PI5(7) & "0" & PI5(7) & PI5(7));
Mult2PI6 <= (PI6(6 downto 0) & "0") XOR ("000" & PI6(7) & PI6(7) & "0" & PI6(7) & PI6(7));
Mult2PI7 <= (PI7(6 downto 0) & "0") XOR ("000" & PI7(7) & PI7(7) & "0" & PI7(7) & PI7(7));
Mult2PI8 <= (PI8(6 downto 0) & "0") XOR ("000" & PI8(7) & PI8(7) & "0" & PI8(7) & PI8(7));
Mult2PI9 <= (PI9(6 downto 0) & "0") XOR ("000" & PI9(7) & PI9(7) & "0" & PI9(7) & PI9(7));
Mult2PI10 <= (PI10(6 downto 0) & "0") XOR ("000" & PI10(7) & PI10(7) & "0" & PI10(7) & PI10(7));
Mult2PI11 <= (PI11(6 downto 0) & "0") XOR ("000" & PI11(7) & PI11(7) & "0" & PI11(7) & PI11(7));
Mult2PI12 <= (PI12(6 downto 0) & "0") XOR ("000" & PI12(7) & PI12(7) & "0" & PI12(7) & PI12(7));
Mult2PI13 <= (PI13(6 downto 0) & "0") XOR ("000" & PI13(7) & PI13(7) & "0" & PI13(7) & PI13(7));
Mult2PI14 <= (PI14(6 downto 0) & "0") XOR ("000" & PI14(7) & PI14(7) & "0" & PI14(7) & PI14(7));
Mult2PI15 <= (PI15(6 downto 0) & "0") XOR ("000" & PI15(7) & PI15(7) & "0" & PI15(7) & PI15(7));
MCOutput( 1*8-1 downto 0*8) <= Mult2PI0 XOR Mult2PI1 XOR PI1 XOR PI2 XOR PI3;
MCOutput( 2*8-1 downto 1*8) <= Mult2PI1 XOR Mult2PI2 XOR PI2 XOR PI3 XOR PI0;
MCOutput( 3*8-1 downto 2*8) <= Mult2PI2 XOR Mult2PI3 XOR PI3 XOR PI0 XOR PI1;
MCOutput( 4*8-1 downto 3*8) <= Mult2PI3 XOR Mult2PI0 XOR PI0 XOR PI1 XOR PI2;
MCOutput( 5*8-1 downto 4*8) <= Mult2PI4 XOR Mult2PI5 XOR PI5 XOR PI6 XOR PI7;
MCOutput( 6*8-1 downto 5*8) <= Mult2PI5 XOR Mult2PI6 XOR PI6 XOR PI7 XOR PI4;
MCOutput( 7*8-1 downto 6*8) <= Mult2PI6 XOR Mult2PI7 XOR PI7 XOR PI4 XOR PI5;
MCOutput( 8*8-1 downto 7*8) <= Mult2PI7 XOR Mult2PI4 XOR PI4 XOR PI5 XOR PI6;
MCOutput( 9*8-1 downto 8*8) <= Mult2PI8 XOR Mult2PI9 XOR PI9 XOR PI10 XOR PI11;
MCOutput(10*8-1 downto 9*8) <= Mult2PI9 XOR Mult2PI10 XOR PI10 XOR PI11 XOR PI8;
MCOutput(11*8-1 downto 10*8) <= Mult2PI10 XOR Mult2PI11 XOR PI11 XOR PI8 XOR PI9;
MCOutput(12*8-1 downto 11*8) <= Mult2PI11 XOR Mult2PI8 XOR PI8 XOR PI9 XOR PI10;
MCOutput(13*8-1 downto 12*8) <= Mult2PI12 XOR Mult2PI13 XOR PI13 XOR PI14 XOR PI15;
MCOutput(14*8-1 downto 13*8) <= Mult2PI13 XOR Mult2PI14 XOR PI14 XOR PI15 XOR PI12;
MCOutput(15*8-1 downto 14*8) <= Mult2PI14 XOR Mult2PI15 XOR PI15 XOR PI12 XOR PI13;
MCOutput(16*8-1 downto 15*8) <= Mult2PI15 XOR Mult2PI12 XOR PI12 XOR PI13 XOR PI14;
---------------------------------
FeedBack <= MCOutput when FinalRound = '0' else Selected_SR;
---------------------------------
---- Key Schedule ---------------
KeyMUXOutput <= InputKey when rst = '1' else KeyStateRegOutput;
w3dec <= KeyMUXOutput(95 downto 64) XOR KeyMUXOutput(127 downto 96);
w2dec <= KeyMUXOutput(63 downto 32) XOR KeyMUXOutput( 95 downto 64);
w1dec <= KeyMUXOutput(31 downto 0) XOR KeyMUXOutput( 63 downto 32);
KeySboxInput <= KeyMUXOutput(127 downto 96) when Dec = '0' else w3dec;
---------------------------------
ShiftedSBKey <= KeySboxOutput(7 downto 0) & KeySboxOutput(31 downto 16) & (KeySboxOutput(15 downto 8) XOR Rcon);
w0 <= ShiftedSBKey XOR KeyMUXOutput(31 downto 0);
w1 <= w0 XOR KeyMUXOutput(63 downto 32);
w2 <= w1 XOR KeyMUXOutput(95 downto 64);
w3 <= w2 XOR KeyMUXOutput(127 downto 96);
KeyExpansionOutput( 31 downto 0) <= w0;
KeyExpansionOutput(127 downto 32) <= (w3 & w2 & w1) when Dec = '0' else (w3dec & w2dec & w1dec);
---------------------------------
Keyreg_gen: PROCESS(clk, KeyExpansionOutput)
BEGIN
IF RISING_EDGE(clk) THEN
IF KeyRegEn = '1' THEN
KeyStateRegOutput <= KeyExpansionOutput;
END IF;
END IF;
END PROCESS;
---------------------------------
---- Key select -----------------
K15 <= KeyMUXOutput(8*16-1 downto 8*15);
K14 <= KeyMUXOutput(8*15-1 downto 8*14);
K13 <= KeyMUXOutput(8*14-1 downto 8*13);
K12 <= KeyMUXOutput(8*13-1 downto 8*12);
K11 <= KeyMUXOutput(8*12-1 downto 8*11);
K10 <= KeyMUXOutput(8*11-1 downto 8*10);
K9 <= KeyMUXOutput(8*10-1 downto 8*9);
K8 <= KeyMUXOutput(8*9-1 downto 8*8);
K7 <= KeyMUXOutput(8*8-1 downto 8*7);
K6 <= KeyMUXOutput(8*7-1 downto 8*6);
K5 <= KeyMUXOutput(8*6-1 downto 8*5);
K4 <= KeyMUXOutput(8*5-1 downto 8*4);
K3 <= KeyMUXOutput(8*4-1 downto 8*3);
K2 <= KeyMUXOutput(8*3-1 downto 8*2);
K1 <= KeyMUXOutput(8*2-1 downto 8*1);
K0 <= KeyMUXOutput(8*1-1 downto 8*0);
---------------------------------
K0_2 <= K0 XOR K2;
K1_3 <= K1 XOR K3;
K4_6 <= K4 XOR K6;
K5_7 <= K5 XOR K7;
K8_10 <= K8 XOR K10;
K9_11 <= K9 XOR K11;
K12_14 <= K12 XOR K14;
K13_15 <= K13 XOR K15;
Mult2K0_2 <= (K0_2(6 downto 0) & "0") XOR ("000" & K0_2(7) & K0_2(7) & "0" & K0_2(7) & K0_2(7));
Mult2K1_3 <= (K1_3(6 downto 0) & "0") XOR ("000" & K1_3(7) & K1_3(7) & "0" & K1_3(7) & K1_3(7));
Mult2K4_6 <= (K4_6(6 downto 0) & "0") XOR ("000" & K4_6(7) & K4_6(7) & "0" & K4_6(7) & K4_6(7));
Mult2K5_7 <= (K5_7(6 downto 0) & "0") XOR ("000" & K5_7(7) & K5_7(7) & "0" & K5_7(7) & K5_7(7));
Mult2K8_10 <= (K8_10(6 downto 0) & "0") XOR ("000" & K8_10(7) & K8_10(7) & "0" & K8_10(7) & K8_10(7));
Mult2K9_11 <= (K9_11(6 downto 0) & "0") XOR ("000" & K9_11(7) & K9_11(7) & "0" & K9_11(7) & K9_11(7));
Mult2K12_14 <= (K12_14(6 downto 0) & "0") XOR ("000" & K12_14(7) & K12_14(7) & "0" & K12_14(7) & K12_14(7));
Mult2K13_15 <= (K13_15(6 downto 0) & "0") XOR ("000" & K13_15(7) & K13_15(7) & "0" & K13_15(7) & K13_15(7));
Mult4K0_2 <= (Mult2K0_2(6 downto 0) & "0") XOR ("000" & Mult2K0_2(7) & Mult2K0_2(7) & "0" & Mult2K0_2(7) & Mult2K0_2(7));
Mult4K1_3 <= (Mult2K1_3(6 downto 0) & "0") XOR ("000" & Mult2K1_3(7) & Mult2K1_3(7) & "0" & Mult2K1_3(7) & Mult2K1_3(7));
Mult4K4_6 <= (Mult2K4_6(6 downto 0) & "0") XOR ("000" & Mult2K4_6(7) & Mult2K4_6(7) & "0" & Mult2K4_6(7) & Mult2K4_6(7));
Mult4K5_7 <= (Mult2K5_7(6 downto 0) & "0") XOR ("000" & Mult2K5_7(7) & Mult2K5_7(7) & "0" & Mult2K5_7(7) & Mult2K5_7(7));
Mult4K8_10 <= (Mult2K8_10(6 downto 0) & "0") XOR ("000" & Mult2K8_10(7) & Mult2K8_10(7) & "0" & Mult2K8_10(7) & Mult2K8_10(7));
Mult4K9_11 <= (Mult2K9_11(6 downto 0) & "0") XOR ("000" & Mult2K9_11(7) & Mult2K9_11(7) & "0" & Mult2K9_11(7) & Mult2K9_11(7));
Mult4K12_14 <= (Mult2K12_14(6 downto 0) & "0") XOR ("000" & Mult2K12_14(7) & Mult2K12_14(7) & "0" & Mult2K12_14(7) & Mult2K12_14(7));
Mult4K13_15 <= (Mult2K13_15(6 downto 0) & "0") XOR ("000" & Mult2K13_15(7) & Mult2K13_15(7) & "0" & Mult2K13_15(7) & Mult2K13_15(7));
PIK0 <= K0 XOR Mult4K0_2;
PIK1 <= K1 XOR Mult4K1_3;
PIK2 <= K2 XOR Mult4K0_2;
PIK3 <= K3 XOR Mult4K1_3;
PIK4 <= K4 XOR Mult4K4_6;
PIK5 <= K5 XOR Mult4K5_7;
PIK6 <= K6 XOR Mult4K4_6;
PIK7 <= K7 XOR Mult4K5_7;
PIK8 <= K8 XOR Mult4K8_10;
PIK9 <= K9 XOR Mult4K9_11;
PIK10 <= K10 XOR Mult4K8_10;
PIK11 <= K11 XOR Mult4K9_11;
PIK12 <= K12 XOR Mult4K12_14;
PIK13 <= K13 XOR Mult4K13_15;
PIK14 <= K14 XOR Mult4K12_14;
PIK15 <= K15 XOR Mult4K13_15;
Mult2PIK0 <= (PIK0(6 downto 0) & "0") XOR ("000" & PIK0(7) & PIK0(7) & "0" & PIK0(7) & PIK0(7));
Mult2PIK1 <= (PIK1(6 downto 0) & "0") XOR ("000" & PIK1(7) & PIK1(7) & "0" & PIK1(7) & PIK1(7));
Mult2PIK2 <= (PIK2(6 downto 0) & "0") XOR ("000" & PIK2(7) & PIK2(7) & "0" & PIK2(7) & PIK2(7));
Mult2PIK3 <= (PIK3(6 downto 0) & "0") XOR ("000" & PIK3(7) & PIK3(7) & "0" & PIK3(7) & PIK3(7));
Mult2PIK4 <= (PIK4(6 downto 0) & "0") XOR ("000" & PIK4(7) & PIK4(7) & "0" & PIK4(7) & PIK4(7));
Mult2PIK5 <= (PIK5(6 downto 0) & "0") XOR ("000" & PIK5(7) & PIK5(7) & "0" & PIK5(7) & PIK5(7));
Mult2PIK6 <= (PIK6(6 downto 0) & "0") XOR ("000" & PIK6(7) & PIK6(7) & "0" & PIK6(7) & PIK6(7));
Mult2PIK7 <= (PIK7(6 downto 0) & "0") XOR ("000" & PIK7(7) & PIK7(7) & "0" & PIK7(7) & PIK7(7));
Mult2PIK8 <= (PIK8(6 downto 0) & "0") XOR ("000" & PIK8(7) & PIK8(7) & "0" & PIK8(7) & PIK8(7));
Mult2PIK9 <= (PIK9(6 downto 0) & "0") XOR ("000" & PIK9(7) & PIK9(7) & "0" & PIK9(7) & PIK9(7));
Mult2PIK10 <= (PIK10(6 downto 0) & "0") XOR ("000" & PIK10(7) & PIK10(7) & "0" & PIK10(7) & PIK10(7));
Mult2PIK11 <= (PIK11(6 downto 0) & "0") XOR ("000" & PIK11(7) & PIK11(7) & "0" & PIK11(7) & PIK11(7));
Mult2PIK12 <= (PIK12(6 downto 0) & "0") XOR ("000" & PIK12(7) & PIK12(7) & "0" & PIK12(7) & PIK12(7));
Mult2PIK13 <= (PIK13(6 downto 0) & "0") XOR ("000" & PIK13(7) & PIK13(7) & "0" & PIK13(7) & PIK13(7));
Mult2PIK14 <= (PIK14(6 downto 0) & "0") XOR ("000" & PIK14(7) & PIK14(7) & "0" & PIK14(7) & PIK14(7));
Mult2PIK15 <= (PIK15(6 downto 0) & "0") XOR ("000" & PIK15(7) & PIK15(7) & "0" & PIK15(7) & PIK15(7));
MCInvK( 1*8-1 downto 0*8) <= Mult2PIK0 XOR Mult2PIK1 XOR PIK1 XOR PIK2 XOR PIK3;
MCInvK( 2*8-1 downto 1*8) <= Mult2PIK1 XOR Mult2PIK2 XOR PIK2 XOR PIK3 XOR PIK0;
MCInvK( 3*8-1 downto 2*8) <= Mult2PIK2 XOR Mult2PIK3 XOR PIK3 XOR PIK0 XOR PIK1;
MCInvK( 4*8-1 downto 3*8) <= Mult2PIK3 XOR Mult2PIK0 XOR PIK0 XOR PIK1 XOR PIK2;
MCInvK( 5*8-1 downto 4*8) <= Mult2PIK4 XOR Mult2PIK5 XOR PIK5 XOR PIK6 XOR PIK7;
MCInvK( 6*8-1 downto 5*8) <= Mult2PIK5 XOR Mult2PIK6 XOR PIK6 XOR PIK7 XOR PIK4;
MCInvK( 7*8-1 downto 6*8) <= Mult2PIK6 XOR Mult2PIK7 XOR PIK7 XOR PIK4 XOR PIK5;
MCInvK( 8*8-1 downto 7*8) <= Mult2PIK7 XOR Mult2PIK4 XOR PIK4 XOR PIK5 XOR PIK6;
MCInvK( 9*8-1 downto 8*8) <= Mult2PIK8 XOR Mult2PIK9 XOR PIK9 XOR PIK10 XOR PIK11;
MCInvK(10*8-1 downto 9*8) <= Mult2PIK9 XOR Mult2PIK10 XOR PIK10 XOR PIK11 XOR PIK8;
MCInvK(11*8-1 downto 10*8) <= Mult2PIK10 XOR Mult2PIK11 XOR PIK11 XOR PIK8 XOR PIK9;
MCInvK(12*8-1 downto 11*8) <= Mult2PIK11 XOR Mult2PIK8 XOR PIK8 XOR PIK9 XOR PIK10;
MCInvK(13*8-1 downto 12*8) <= Mult2PIK12 XOR Mult2PIK13 XOR PIK13 XOR PIK14 XOR PIK15;
MCInvK(14*8-1 downto 13*8) <= Mult2PIK13 XOR Mult2PIK14 XOR PIK14 XOR PIK15 XOR PIK12;
MCInvK(15*8-1 downto 14*8) <= Mult2PIK14 XOR Mult2PIK15 XOR PIK15 XOR PIK12 XOR PIK13;
MCInvK(16*8-1 downto 15*8) <= Mult2PIK15 XOR Mult2PIK12 XOR PIK12 XOR PIK13 XOR PIK14;
---------------------------------
Selected_Key <= KeyMUXOutput when FirstKey = '1' else MCInvK;
end Behavioral;
|
<gh_stars>1-10
-------------------------------------------------------
--! @file
--! @brief 2:1 Mux using with-select
-------------------------------------------------------
--! Use standard library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Mux entity brief description
--! Detailed description of this
--! mux design element.
entity mux_using_with is
port (
din_0 : in std_logic; --! Mux first input
din_1 : in std_logic; --! Mux Second input
sel : in std_logic; --! Select input
mux_out : out std_logic --! Mux output
);
end entity;
--! @brief Architecture definition of the MUX
--! @details More details about this mux element.
architecture behavior of mux_using_with is
begin
with (sel) select
mux_out <= din_0 when '0',
din_1 when others;
end architecture;
|
--
--
-- FPGA Display Handler IP Core By <NAME> (http://mehran.ahadi.me)
-- This IP allows you to draw shapes and print texts on VGA screen.
-- Copyright (C) 2015-2016 <NAME>
-- This work is released under MIT License.
--
-- VGA Signal Generator File
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DisplayOut is
Generic (
w_pixels: integer;
w_fp: integer;
w_synch: integer;
w_bp: integer;
w_syncval: std_logic;
h_pixels: integer;
h_fp: integer;
h_synch: integer;
h_bp: integer;
h_syncval: std_logic
);
Port (
PIXEL_CLK :in STD_LOGIC;
COMP_SYNCH : out STD_LOGIC;
OUT_BLANK_Z : out STD_LOGIC;
HSYNC : out STD_LOGIC;
VSYNC : out STD_LOGIC;
R : out STD_LOGIC_VECTOR(7 downto 0);
G : out STD_LOGIC_VECTOR(7 downto 0);
B : out STD_LOGIC_VECTOR(7 downto 0);
MEMORY_ADDRESS: OUT std_logic_VECTOR(19 downto 0);
MEMORY_OUT: IN std_logic_VECTOR(0 downto 0)
);
end DisplayOut;
architecture Behavioral of DisplayOut is
constant w_total : integer := w_pixels + w_fp + w_synch + w_bp;
constant h_total : integer := h_pixels + h_fp + h_synch + h_bp;
begin
COMP_SYNCH <= '0'; -- Disable "sync on green"
R <= (others => MEMORY_OUT(0));
G <= (others => MEMORY_OUT(0));
B <= (others => MEMORY_OUT(0));
process(PIXEL_CLK)
variable clk_x: integer range 0 to w_total - 1 := 0;
variable clk_y: integer range 0 to h_total - 1 := 0;
variable clk_xy: STD_LOGIC_VECTOR (19 downto 0) := "00000000000000000000"; -- 1048576 = 2 ^ 20 as we have 20 bits.
begin
if PIXEL_CLK'event and PIXEL_CLK='1' then
-- VGA Signals
if clk_x < w_pixels + w_fp or clk_x >= w_pixels + w_fp + w_synch then
HSYNC <= not w_syncval; -- not on synch location
else
HSYNC <= w_syncval; -- on synch location
end if;
if clk_y < h_pixels + h_fp or clk_y >= h_pixels + h_fp + h_synch then
VSYNC <= not h_syncval; -- not on synch location
else
VSYNC <= h_syncval; -- on synch location
end if;
if clk_x >= w_pixels or clk_y >= h_pixels then
OUT_BLANK_Z <= '0';
else
OUT_BLANK_Z <= '1';
end if;
-- Increment coordinate counters
if clk_x < w_total - 1 then
clk_x := clk_x + 1;
else
clk_x := 0;
if clk_y < h_total - 1 then
clk_y := clk_y + 1;
else
clk_y := 0;
end if;
end if;
-- Let it be one clock ahead
if clk_x = w_pixels - 1 then
if clk_y < h_pixels - 1 then
clk_xy (19 downto 10) := clk_xy (19 downto 10) + 1;
clk_xy (9 downto 0) := "0000000000";
elsif clk_y = h_total - 1 then
clk_xy := "00000000000000000000";
end if;
elsif clk_x < w_pixels - 1 then
-- add up
clk_xy := clk_xy + '1';
end if;
MEMORY_ADDRESS <= clk_xy;
end if;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, <NAME>
-- Copyright (C) 2015 - 2017, <NAME>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: aximem
-- File: aximem.vhd
-- Author: <NAME>, Cobham Gaisler AB
-- Modified <NAME>, Cobham Gaisler AB
-- Description: Simulation AXI3/4 slave with SREC loader
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.sim.all;
entity axixmem is
generic (
fname: string;
axibits: integer := AXIDW;
rstmode: integer range 0 to 1
);
port (
clk : in std_ulogic;
rst : in std_ulogic;
axisi: in axix_mosi_type;
axiso: out axi_somi_type;
conf_in : in aximem_conf_type := aximem_conf_type_def
);
end;
architecture sim of axixmem is
constant simCTO: time := 1 ns;
constant nerror : integer := 100;
signal axiso_int: axi_somi_type;
constant axi_somi_idle : axi_somi_type := (
aw => (ready => '0'),
w => (ready => '0'),
b => (id => "0000", resp => "00", valid => '0'),
ar => (ready => '0'),
r => (id => "0000", data => (others => '0'), resp => "00", last => '0', valid => '0')
);
signal rbin: ramback_in_array(1 to 1) := (others => ramback_in_none);
signal rbout: ramback_out_array(1 to 1);
signal rac_wait_for_valid : std_logic := '0';
signal wac_wait_for_valid : std_logic := '0';
signal wdc_wait_for_valid : std_logic := '0';
type rwq_entry is record
valid: boolean;
id: std_logic_vector(3 downto 0);
addr: std_logic_vector(31 downto 0);
len: std_logic_vector(7 downto 0);
size: std_logic_vector(2 downto 0);
error : std_logic_vector(1 downto 0);
done: boolean; -- write queue only
end record;
type rwq_type is array(natural range <>) of rwq_entry;
type wdataq_entry is record
valid: boolean;
id: std_logic_vector(3 downto 0);
data: std_logic_vector(axibits-1 downto 0);
strb: std_logic_vector(axibits/8-1 downto 0);
end record;
type wdataq_type is array(natural range <>) of wdataq_entry;
type error_addr_type is array (0 to nerror-1) of std_logic_vector(31 downto 0);
type error_type is record
enabled : std_logic;
dstype : std_logic_vector(nerror-1 downto 0); --0->slv_error,1->dec_error
valid : std_logic_vector(nerror-1 downto 0);
addr : error_addr_type;
mask : error_addr_type;
end record;
constant error_reset : error_type := (
enabled => '0',
dstype => (others=>'0'),
valid => (others=>'0'),
addr => (others=>(others=>'0')),
mask => (others=>(others=>'0'))
);
function bool10(b: boolean) return std_ulogic is
begin
if b then return '1'; else return '0'; end if;
end bool10;
signal rqdbg: rwq_type(0 to 3);
signal err_arr : error_type := error_reset;
begin
axiso <= axiso_int after simCTO;
rb: ramback
generic map (
abits => 32-log2(axibits/8),
dbits => axibits,
fname => fname,
autoload => 1,
nports => 1,
endian => 1,
rstmode => rstmode)
port map (
bein => rbin,
beout => rbout
);
p: process
variable o,po: axi_somi_type := axi_somi_idle;
variable rq, wq: rwq_type(0 to 3);
variable wdq: wdataq_type(0 to 7);
variable i : integer;
variable vaddr: std_logic_vector(31 downto 0);
variable vwr : std_logic_vector(15 downto 0);
variable err_match : std_logic;
begin
wait until rising_edge(clk);
po := o;
o.r.resp := "00";
--------------------------------------------------------------------------
-- Read handling
--------------------------------------------------------------------------
-- Enqueue on read address queue
if po.ar.ready='1' and axisi.ar.valid='1' then
i := 0;
while rq(i).valid loop i:=i+1; end loop;
rq(i).valid := true;
rq(i).id := axisi.ar.id;
rq(i).addr := axisi.ar.addr;
rq(i).len := axisi.ar.len;
rq(i).size := axisi.ar.size;
end if;
-- Advance read queue
if po.r.valid='1' and axisi.r.ready='1' then
assert rq(0).valid;
if po.r.last='1' then
assert rq(0).len = "00000000";
rq(0 to rq'high-1) := rq(1 to rq'high);
rq(rq'high).valid := false;
else
assert rq(0).len /= "00000000";
rq(0).addr := std_logic_vector(unsigned(rq(0).addr)+2**(to_integer(unsigned(rq(0).size))));
rq(0).len := std_logic_vector(unsigned(rq(0).len)-1);
end if;
end if;
if rac_wait_for_valid = '0' then
o.ar.ready := bool10(not rq(rq'high).valid);
else
o.ar.ready := '0';
if (bool10(not rq(rq'high).valid) = '1') and axisi.ar.valid = '1' then
o.ar.ready := '1';
end if;
end if;
o.r.valid := bool10(rq(0).valid);
o.r.id := rq(0).id;
o.r.last := bool10(rq(0).valid and rq(0).len="00000000");
if rq(0).valid then
-- Do read
vaddr := (others => '0');
vaddr(31-log2(axibits/8) downto 0) := rq(0).addr(31 downto log2(axibits/8));
rbin(1).addr <= vaddr;
if rbout(1).addr /= vaddr then
wait until rbout(1).addr=vaddr;
end if;
o.r.data(axibits-1 downto 0) := rbout(1).dout(axibits-1 downto 0);
if err_arr.enabled = '1' then
for i in 0 to nerror-1 loop
if err_arr.valid(i) = '1' then
err_match := '1';
for j in 0 to 31 loop
if (rq(0).addr(j) /= err_arr.addr(i)(j)) and (err_arr.mask(i)(j) = '0') then
err_match := '0';
exit;
end if;
end loop;
if err_match = '1' then
if err_arr.dstype(i) = '0' then
o.r.resp := "10";
else
o.r.resp := "11";
end if;
exit;
end if;
end if;
end loop;
end if;
end if;
--------------------------------------------------------------------------
-- Write handling
--------------------------------------------------------------------------
-- Retire write addr queue
if po.b.valid='1' and axisi.b.ready='1' then
assert wq(0).valid and wq(0).done and wq(0).id=po.b.id;
wq(0 to wq'high-1) := wq(1 to wq'high);
wq(wq'high).valid := false;
end if;
-- Enqueue on write address queue
if po.aw.ready='1' and axisi.aw.valid='1' then
i := 0;
while wq(i).valid loop i:=i+1; end loop;
wq(i).valid := true;
wq(i).done := false;
wq(i).id := axisi.aw.id;
wq(i).addr := axisi.aw.addr;
wq(i).len := axisi.aw.len;
wq(i).size := axisi.aw.size;
wq(i).error := "00";
end if;
-- Enqueue on write data queue
if po.w.ready='1' and axisi.w.valid='1' then
i := 0;
while wdq(i).valid loop i:=i+1; end loop;
wdq(i).valid := true;
wdq(i).id := axisi.w.id;
wdq(i).data := axisi.w.data;
wdq(i).strb := axisi.w.strb;
end if;
-- Advance write data
if wdq(0).valid then
i := 0;
while wq(i).valid and wq(i).id /= wdq(0).id loop i:=i+1; end loop;
if wq(i).valid then
assert not wq(i).done;
vaddr := (others => '0');
vaddr(31-log2(axibits/8) downto 0) := wq(i).addr(31 downto log2(axibits/8));
vwr := (others => '0');
vwr(axibits/8-1 downto 0) := wdq(0).strb;
rbin(1).addr <= vaddr;
rbin(1).wr <= vwr;
rbin(1).din(axibits-1 downto 0) <= wdq(0).data;
if rbin(1).wr /= vwr then
wait until rbin(1).wr = vwr;
end if;
rbin(1).wr <= (others => '0');
if wq(i).len="00000000" then
wq(i).done := true;
end if;
wq(i).addr := std_logic_vector(unsigned(wq(i).addr)+2**(to_integer(unsigned(wq(i).size))));
wq(i).len := std_logic_vector(unsigned(wq(i).len)-1);
wdq(0 to wdq'high-1) := wdq(1 to wdq'high);
wdq(wdq'high).valid := false;
if err_arr.enabled = '1' then
for z in 0 to nerror-1 loop
if err_arr.valid(z) = '1' then
err_match := '1';
for j in 0 to 31 loop
if (wq(0).addr(j) /= err_arr.addr(z)(j)) and (err_arr.mask(z)(j) = '0') then
err_match := '0';
exit;
end if;
end loop;
if err_match = '1' then
if err_arr.dstype(z) = '0' then
wq(0).error := "10";
else
wq(0).error := "11";
end if;
exit;
end if;
end if;
end loop;
end if;
end if;
end if;
if wac_wait_for_valid = '0' then
o.aw.ready := bool10(not wq(wq'high).valid);
else
o.aw.ready := '0';
if (bool10(not wq(wq'high).valid) = '1') and axisi.aw.valid = '1' then
o.aw.ready := '1';
end if;
end if;
if wdc_wait_for_valid = '0' then
o.w.ready := bool10(not wdq(wdq'high).valid);
else
o.w.ready := '0';
if (bool10(not wdq(wdq'high).valid) = '1') and axisi.w.valid = '1' then
o.w.ready := '1';
end if;
end if;
o.b.valid := bool10(wq(0).valid and wq(0).done);
o.b.id := wq(0).id;
o.b.resp := "00";
if bool10(wq(0).valid and wq(0).done) = '1' then
o.b.resp := wq(0).error;
end if;
axiso_int <= o;
rqdbg <= rq;
end process;
err:process
begin
wait until conf_in.err.entry_strobe = '1';
err_arr.enabled <= conf_in.err.enabled;
err_arr.dstype(conf_in.err.id) <= conf_in.err.dstype;
err_arr.valid(conf_in.err.id) <= conf_in.err.valid;
err_arr.addr(conf_in.err.id) <= conf_in.err.addr;
err_arr.mask(conf_in.err.id) <= conf_in.err.mask;
wait until conf_in.err.entry_strobe = '0';
end process;
wac:process
begin
wait until conf_in.wac.entry_strobe = '1';
wac_wait_for_valid <= conf_in.wac.wait_for_valid;
wait until conf_in.wac.entry_strobe = '0';
end process;
wdc:process
begin
wait until conf_in.wdc.entry_strobe = '1';
wdc_wait_for_valid <= conf_in.wdc.wait_for_valid;
wait until conf_in.wdc.entry_strobe = '0';
end process;
rac:process
begin
wait until conf_in.rac.entry_strobe = '1';
rac_wait_for_valid <= conf_in.rac.wait_for_valid;
wait until conf_in.rac.entry_strobe = '0';
end process;
end;
|
<gh_stars>1-10
----------------------------------------------------------------------------------
-- COMPANY: Ruhr University Bochum, Embedded Security & KU Leuven, COSIC
-- AUTHOR: <NAME>, <NAME>, <NAME>
----------------------------------------------------------------------------------
-- Copyright (c) 2019, <NAME>, <NAME>, <NAME>
-- All rights reserved.
-- BSD-3-Clause License
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of the copyright holder, their organization nor the
-- names of its contributors may be used to endorse or promote products
-- derived from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTERS BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- IMPORTS
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
-- ENTITY
----------------------------------------------------------------------------------
ENTITY Counter4 IS
PORT ( CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END Counter4;
-- ARCHITECTURE
----------------------------------------------------------------------------------
ARCHITECTURE Structural OF Counter4 IS
-- SIGNALS
----------------------------------------------------------------------------------
SIGNAL CNT, NEWCNT : STD_LOGIC_VECTOR(3 DOWNTO 0);
-- STRUCTURAL
----------------------------------------------------------------------------------
BEGIN
-- LUTS -----------------------------------------------------------------------
LT0 : LUT6_2 GENERIC MAP (INIT => X"6666666655555555") PORT MAP (NEWCNT(0), NEWCNT(1), CNT(0), CNT(1), CNT(2), CNT(3), '0', '1');
LT1 : LUT6_2 GENERIC MAP (INIT => X"7F807F8078787878") PORT MAP (NEWCNT(2), NEWCNT(3), CNT(0), CNT(1), CNT(2), CNT(3), '0', '1');
-------------------------------------------------------------------------------
-- FLIP-FLOPS -----------------------------------------------------------------
FF0 : FDRE GENERIC MAP (INIT => '0') PORT MAP (C => CLK, CE => EN, R => RST, D => NEWCNT(0), Q => CNT(0));
FF1 : FDRE GENERIC MAP (INIT => '0') PORT MAP (C => CLK, CE => EN, R => RST, D => NEWCNT(1), Q => CNT(1));
FF2 : FDRE GENERIC MAP (INIT => '0') PORT MAP (C => CLK, CE => EN, R => RST, D => NEWCNT(2), Q => CNT(2));
FF3 : FDRE GENERIC MAP (INIT => '0') PORT MAP (C => CLK, CE => EN, R => RST, D => NEWCNT(3), Q => CNT(3));
-------------------------------------------------------------------------------
-- COUNTER OUTPUT -------------------------------------------------------------
Q <= CNT;
-------------------------------------------------------------------------------
END Structural;
|
entity ff is port (
d: in bit;
clk: in bit;
q: out bit
);
end ff;
architecture behav of ff is
begin
process (clk) begin
if (clk 'event and clk = '1') then
q <= d;
end if;
end process;
end behav;
|
-- *!***************************************************************************
-- *! Copyright 2019 International Business Machines
-- *!
-- *! Licensed under the Apache License, Version 2.0 (the "License");
-- *! you may not use this file except in compliance with the License.
-- *! You may obtain a copy of the License at
-- *! http://www.apache.org/licenses/LICENSE-2.0
-- *!
-- *! The patent license granted to you in Section 3 of the License, as applied
-- *! to the "Work," hereby includes implementations of the Work in physical form.
-- *!
-- *! Unless required by applicable law or agreed to in writing, the reference design
-- *! distributed under the License is distributed on an "AS IS" BASIS,
-- *! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- *! See the License for the specific language governing permissions and
-- *! limitations under the License.
-- *!
-- *! The background Specification upon which this is based is managed by and available from
-- *! the OpenCAPI Consortium. More information can be found at https://opencapi.org.
-- *!***************************************************************************
library ieee,support;
use ieee.std_logic_1164.all;
use support.signal_resolution_pkg.all;
package power_logic_pkg is
subtype power_logic is std_logic_alleq;
subtype power_logic_vector is std_logic_vector_alleq;
function tconv( p : power_logic ) return std_logic;
function tconv( p : power_logic ) return std_ulogic_vector;
function tconv( s : std_logic ) return power_logic;
attribute type_convert: boolean;
attribute type_convert of tconv:function is true;
attribute synthesis_return: string;
end package power_logic_pkg;
package body power_logic_pkg is
function tconv ( p : power_logic ) return std_logic is
variable result: std_logic;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ;
begin
case p is
when '0' => result := '0';
when '1' => result := '1';
when 'Z' => result := 'Z';
when 'X' => result := 'X';
end case;
return result;
end tconv ;
function tconv ( p : power_logic ) return std_ulogic_vector is
variable result: std_ulogic_vector(0 to 0);
ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ;
begin
case p is
when '0' => result := "0";
when '1' => result := "1";
when 'Z' => result := "Z";
when 'X' => result := "X";
end case;
return result;
end tconv ;
function tconv ( s : std_logic ) return power_logic is
variable result: power_logic;
ATTRIBUTE synthesis_return OF result:VARIABLE IS "FEED_THROUGH" ;
begin
case s is
when '0' => result := '0';
when '1' => result := '1';
when 'Z' => result := 'Z';
when 'X' => result := 'X';
when 'L' => result := '0';
when 'H' => result := '1';
when others => result := '0';
end case;
return result;
end tconv ;
end power_logic_pkg;
|
<gh_stars>0
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CACHE_ARBITER is
port(
--Input Pipeline
CLOCK : in std_logic;
IF_ADDRESS, MEM_ADDRESS : in std_logic_vector(31 downto 0);
IF_DATA_IN,MEM_DATA_IN : in std_logic_vector(31 downto 0);
IF_RD: in std_logic;
IF_WR : in std_logic;
MEM_RD: in std_logic;
MEM_WR: in std_logic;
--Input Memory
WAITREQUEST : in std_logic;
<<<<<<< HEAD
--Output TO Pipeline
ENABLE_OUT : out std_logic;
DATA_OUT : out std_logic
=======
--Output
ENABLE : out std_logic;
IF_DATA_OUT, MEM_DATA_OUT: out std_logic_vector(31 downto 0);
CACHE_ADDR,CACHE_WRITEDATA: out std_logic_vector(31 downto 0);
CACHE_WRITE,CACHE_READ: out std_logic;
CACHE_READDATA: in std_logic_vector(31 downto 0)
>>>>>>> 26d66bc56e9c605a611addfbdd363953dc9b58d4
--Output TO Cache
C_ADDR : out std_logic_vector(31 downto 0);
C_WRITEDATA : out std_logic_vector(31 downto 0);
C_
C_RD : out std_logic;
C_WR : out std_logic;
C_
);
end entity;
architecture arch of CACHE_ARBITER is
type state_type is (READY,REQUEST,SERVICE);
signal current_state, next_state: state_type := READY;
begin
<<<<<<< HEAD
state_transitions : process(clock)
begin
if(rising_edge(clock)) then
current_state <= next_state;
end if;
end process state_transitions
arbitrate : process(clock)
begin
case current_state is
when READY =>
if(RD = '1' OR WR = '1') then
ENABLE_OUT <= '0';
next_state <= REQUEST;
else
next_state <= READY;
end if;
when REQUEST =>
when SERVICE =>
when others =>
end case;
end process arbitrate;
=======
FSM: process(CLOCK)
begin
current_state <= next_state;
if current_state = READY then
if IF_RD = '1' or IF_WR = '1' or MEM_RD = '1' or MEM_WR = '1' then
ENABLE <= '0';
if IF_WR = '1' or IF_RD = '1' then
CACHE_ADDR <= IF_ADDRESS;
else
CACHE_ADDR <= MEM_ADDRESS;
end if;
if IF_WR = '1' or MEM_WR = '1' then
if IF_WR = '1' then
CACHE_WRITEDATA <= IF_DATA_IN;
else
CACHE_WRITEDATA <= MEM_DATA_IN;
end if;
CACHE_WRITE <= '1';
else
CACHE_READ <= '1';
end if;
next_state <= REQUEST;
end if;
elsif current_state = REQUEST then
if WAITREQUEST = '0' then
if IF_WR = '1' or MEM_WR = '1' then
CACHE_WRITE <= '0';
if IF_WR = '1' then
IF_DATA_OUT <= CACHE_READDATA;
else
MEM_DATA_OUT <= CACHE_READDATA;
end if;
else
CACHE_READ <= '0';
end if;
ENABLE <= '1';
next_state <= READY;
end if;
else
end if;
end process;
-- state_transitions : process(clock)
-- begin
-- if(rising_edge(clock)) then
-- current_state <= next_state;
-- end if;
-- end process state_transitions;
-- -- arbitrate : process(clock)
-- -- begin
-- -- case current_state is
-- -- when READY =>
-- -- when REQUEST =>
-- -- when SERVICE =>
-- -- end case;
-- -- end process arbitrate;
>>>>>>> 26d66bc56e9c605a611addfbdd363953dc9b58d4
end arch;
|
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|
-------------------------------------------------------------------------------
--
-- @author <NAME> <<EMAIL>>
-- @license MIT
--
-- @brief VGA controller.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dual_port_ram is
generic(
ADDR_WIDTH : positive;
DATA_WIDTH : positive
);
port(
i_clk : in std_logic;
-- Port 0.
i_addr0 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
i_data0 : in std_logic_vector(DATA_WIDTH-1 downto 0);
i_we0 : in std_logic;
o_data0 : out std_logic_vector(DATA_WIDTH-1 downto 0);
-- Port 1.
i_addr1 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
i_data1 : in std_logic_vector(DATA_WIDTH-1 downto 0);
i_we1 : in std_logic;
o_data1 : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end entity dual_port_ram;
architecture arch_v1 of dual_port_ram is
constant MEM_LEN : positive := 2**ADDR_WIDTH;
type t_mem is array(MEM_LEN-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal mem : t_mem := (
others => (others => '0')
);
begin
process(i_clk)
begin
if rising_edge(i_clk) then
o_data0 <= mem(conv_integer(i_addr0));
if i_we0 = '1' then
mem(conv_integer(i_addr0)) <= i_data0;
end if;
o_data1 <= mem(conv_integer(i_addr1));
if i_we1 = '1' then
mem(conv_integer(i_addr1)) <= i_data1;
end if;
end if;
end process;
end architecture arch_v1;
|
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<gh_stars>0
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_clock is
generic (
RESET : string := "ACTIVE_HIGH";
DOMAIN : string := "default"
);
port (
clock_out : out std_logic;
clock : in std_logic := '0';
aclr_out : out std_logic;
aclr : in std_logic := '0';
aclr_n : in std_logic := '0'
);
end entity alt_dspbuilder_clock;
architecture rtl of alt_dspbuilder_clock is
component alt_dspbuilder_clock_GNF343OQUJ is
generic (
RESET : string := "ACTIVE_LOW";
DOMAIN : string := "default"
);
port (
aclr_n : in std_logic := '0';
aclr_out : out std_logic;
clock : in std_logic := '0';
clock_out : out std_logic
);
end component alt_dspbuilder_clock_GNF343OQUJ;
component alt_dspbuilder_clock_GNQFU4PUDH is
generic (
RESET : string := "ACTIVE_HIGH";
DOMAIN : string := "default"
);
port (
aclr : in std_logic := '0';
aclr_out : out std_logic;
clock : in std_logic := '0';
clock_out : out std_logic
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
begin
alt_dspbuilder_clock_GNF343OQUJ_0: if ((RESET = "ACTIVE_LOW") and (DOMAIN = "default")) generate
inst_alt_dspbuilder_clock_GNF343OQUJ_0: alt_dspbuilder_clock_GNF343OQUJ
generic map(RESET => "ACTIVE_LOW", DOMAIN => "default")
port map(aclr_n => aclr_n, aclr_out => aclr_out, clock => clock, clock_out => clock_out);
end generate;
alt_dspbuilder_clock_GNQFU4PUDH_1: if ((RESET = "ACTIVE_HIGH") and (DOMAIN = "default")) generate
inst_alt_dspbuilder_clock_GNQFU4PUDH_1: alt_dspbuilder_clock_GNQFU4PUDH
generic map(RESET => "ACTIVE_HIGH", DOMAIN => "default")
port map(aclr => aclr, aclr_out => aclr_out, clock => clock, clock_out => clock_out);
end generate;
assert not (((RESET = "ACTIVE_LOW") and (DOMAIN = "default")) or ((RESET = "ACTIVE_HIGH") and (DOMAIN = "default")))
report "Please run generate again" severity error;
end architecture rtl;
|
ARCHITECTURE RTL OF controller IS
constant opCodeLength : integer := 5;
signal aluOpSel: std_ulogic;
signal regWriteEn: std_ulogic;
signal flagsEn, flagsEnable: std_ulogic;
signal carrySaved: std_ulogic;
signal zeroSaved: std_ulogic;
signal phase: std_ulogic;
BEGIN
------------------------------------------------------------------------------
-- ALU controls
selectdataSource: process(opCode)
begin
aluOpSel <= '0';
portInSel <= '0';
case opCode(opCodeLength-1 downto 0) is
when "00000" => aluOpSel <= '1'; -- load
when "00010" => portInSel <= '1'; -- input
when "00101" => aluOpSel <= '1'; -- and
when "00110" => aluOpSel <= '1'; -- or
when "00111" => aluOpSel <= '1'; -- xor
when "01001" => aluOpSel <= '1'; -- test
when "01010" => aluOpSel <= '1'; -- comp
when "01100" => aluOpSel <= '1'; -- add
when "01101" => aluOpSel <= '1'; -- addcy
when "01110" => aluOpSel <= '1'; -- sub
when "01111" => aluOpSel <= '1'; -- subcy
when "10000" => aluOpSel <= '1'; -- sh/rot
when others => aluOpSel <= '-';
portInSel <= '-';
end case;
end process selectdataSource;
registerFileSel <= aluOpSel and twoRegInstr;
instrDataSel <= aluOpSel and (not twoRegInstr);
regWriteEn <= phase;
regWriteTable: process(opCode, regWriteEn)
begin
case opCode(opCodeLength-1 downto 0) is
when "00000" => regWrite <= regWriteEn; -- load
when "00010" => regWrite <= regWriteEn; -- input
when "00011" => regWrite <= regWriteEn; -- fetch
when "00101" => regWrite <= regWriteEn; -- and
when "00110" => regWrite <= regWriteEn; -- or
when "00111" => regWrite <= regWriteEn; -- xor
when "01100" => regWrite <= regWriteEn; -- add
when "01101" => regWrite <= regWriteEn; -- addcy
when "01110" => regWrite <= regWriteEn; -- sub
when "01111" => regWrite <= regWriteEn; -- subcy
when "10000" => regWrite <= regWriteEn; -- sh/rot
when others => regWrite <= '0';
end case;
end process regWriteTable;
------------------------------------------------------------------------------
-- I/O controls
readStrobe <= not(phase) when opCode = "00010" else '0';
writeStrobe <= phase when opCode = "10110" else '0';
------------------------------------------------------------------------------
-- Carry logic
flagsEn <= '1';
flagsEnableTable: process(opCode, flagsEn)
begin
case opCode(opCodeLength-1 downto 0) is
when "00101" => flagsEnable <= flagsEn; -- and
when "00110" => flagsEnable <= flagsEn; -- or
when "00111" => flagsEnable <= flagsEn; -- xor
when "01001" => flagsEnable <= flagsEn; -- test
when "01010" => flagsEnable <= flagsEn; -- compare
when "01100" => flagsEnable <= flagsEn; -- add
when "01101" => flagsEnable <= flagsEn; -- addcy
when "01110" => flagsEnable <= flagsEn; -- sub
when "01111" => flagsEnable <= flagsEn; -- subcy
when "10000" => flagsEnable <= flagsEn; -- sh/rot
when others => flagsEnable <= '0';
end case;
end process flagsEnableTable;
saveCarries: process(reset, clock)
begin
if reset = '1' then
carrySaved <= '0';
zeroSaved <= '0';
elsif rising_edge(clock) then
if flagsEnable = '1' then
carrySaved <= cOut;
zeroSaved <= zero;
end if;
end if;
end process saveCarries;
cIn <= carrySaved;
------------------------------------------------------------------------------
-- Program counter controls
buildPhases: process(reset, clock)
begin
if reset = '1' then
phase <= '0';
elsif rising_edge(clock) then
phase <= not phase;
end if;
end process buildPhases;
incPC <= phase;
END ARCHITECTURE RTL;
|
<filename>bin_Erosion_Operation/ip/Erosion/math_package_cmd.vhd<gh_stars>0
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated library functions ***
--*** ***
--*** 06/02/08 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE math_package_cmd IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component fp_inv
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
component fp_invsqr
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
end component;
component fp_sqr
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
end component;
component fp_exp
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC;
oneout : OUT STD_LOGIC
);
end component;
component fp_log
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_ldexp
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component fp_fabs
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component fp_neg
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component fp_sin
GENERIC (
device : integer := 0;
width : positive := 30;
depth : positive := 18;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_cos
GENERIC (
device : integer := 0;
width : positive := 30;
depth : positive := 18;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_tan
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_asin
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_acos
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_atan
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component dp_inv
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
component dp_invsqr
GENERIC (
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
end component;
component dp_sqr
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
end component;
component dp_exp
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
end component;
component dp_log
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component dp_ldexp
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component dp_fabs
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component dp_neg
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component dp_fixfloat IS
GENERIC (
unsigned : integer := 0; -- unsigned = 0, signed = 1
decimal : integer := 18;
fractional : integer := 14;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fixed_number : IN STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1);
sign : OUT STD_LOGIC;
exponent : OUT STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23+29*precision DOWNTO 1)
);
END component;
component dp_floatfix IS
GENERIC (
unsigned : integer := 1; -- unsigned = 0, signed = 1
decimal : integer := 14;
fractional : integer := 6;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
sign : IN STD_LOGIC;
exponent : IN STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : IN STD_LOGIC_VECTOR (23+29*precision DOWNTO 1);
fixed_number : OUT STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1)
);
END component;
END math_package_cmd;
|
<reponame>stceum/8-bit-model-machine
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
-- VENDOR "Altera"
-- PROGRAM "Quartus Prime"
-- VERSION "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition"
-- DATE "07/13/2020 19:45:52"
--
-- Device: Altera EP4CE6E22C6 Package TQFP144
--
--
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
--
LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY hard_block IS
PORT (
devoe : IN std_logic;
devclrn : IN std_logic;
devpor : IN std_logic
);
END hard_block;
-- Design Ports Information
-- ~ALTERA_ASDO_DATA1~ => Location: PIN_6, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_8, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_DCLK~ => Location: PIN_12, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_DATA0~ => Location: PIN_13, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_nCEO~ => Location: PIN_101, I/O Standard: 2.5 V, Current Strength: 8mA
ARCHITECTURE structure OF hard_block IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
BEGIN
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
END structure;
LIBRARY ALTERA;
LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY model_machine IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
wr_data : IN std_logic;
wr_addr : IN std_logic_vector(3 DOWNTO 0);
in_data : IN std_logic_vector(7 DOWNTO 0);
test_bus : BUFFER std_logic_vector(7 DOWNTO 0);
test : BUFFER std_logic;
ax : BUFFER std_logic_vector(7 DOWNTO 0);
bx : BUFFER std_logic_vector(7 DOWNTO 0)
);
END model_machine;
-- Design Ports Information
-- test_bus[0] => Location: PIN_128, I/O Standard: 2.5 V, Current Strength: Default
-- test_bus[1] => Location: PIN_114, I/O Standard: 2.5 V, Current Strength: Default
-- test_bus[2] => Location: PIN_112, I/O Standard: 2.5 V, Current Strength: Default
-- test_bus[3] => Location: PIN_119, I/O Standard: 2.5 V, Current Strength: Default
-- test_bus[4] => Location: PIN_113, I/O Standard: 2.5 V, Current Strength: Default
-- test_bus[5] => Location: PIN_115, I/O Standard: 2.5 V, Current Strength: Default
-- test_bus[6] => Location: PIN_129, I/O Standard: 2.5 V, Current Strength: Default
-- test_bus[7] => Location: PIN_120, I/O Standard: 2.5 V, Current Strength: Default
-- test => Location: PIN_141, I/O Standard: 2.5 V, Current Strength: Default
-- ax[0] => Location: PIN_7, I/O Standard: 2.5 V, Current Strength: Default
-- ax[1] => Location: PIN_125, I/O Standard: 2.5 V, Current Strength: Default
-- ax[2] => Location: PIN_53, I/O Standard: 2.5 V, Current Strength: Default
-- ax[3] => Location: PIN_124, I/O Standard: 2.5 V, Current Strength: Default
-- ax[4] => Location: PIN_104, I/O Standard: 2.5 V, Current Strength: Default
-- ax[5] => Location: PIN_106, I/O Standard: 2.5 V, Current Strength: Default
-- ax[6] => Location: PIN_126, I/O Standard: 2.5 V, Current Strength: Default
-- ax[7] => Location: PIN_54, I/O Standard: 2.5 V, Current Strength: Default
-- bx[0] => Location: PIN_55, I/O Standard: 2.5 V, Current Strength: Default
-- bx[1] => Location: PIN_111, I/O Standard: 2.5 V, Current Strength: Default
-- bx[2] => Location: PIN_100, I/O Standard: 2.5 V, Current Strength: Default
-- bx[3] => Location: PIN_137, I/O Standard: 2.5 V, Current Strength: Default
-- bx[4] => Location: PIN_50, I/O Standard: 2.5 V, Current Strength: Default
-- bx[5] => Location: PIN_135, I/O Standard: 2.5 V, Current Strength: Default
-- bx[6] => Location: PIN_121, I/O Standard: 2.5 V, Current Strength: Default
-- bx[7] => Location: PIN_52, I/O Standard: 2.5 V, Current Strength: Default
-- clk => Location: PIN_23, I/O Standard: 2.5 V, Current Strength: Default
-- wr_data => Location: PIN_132, I/O Standard: 2.5 V, Current Strength: Default
-- rst => Location: PIN_127, I/O Standard: 2.5 V, Current Strength: Default
-- in_data[0] => Location: PIN_105, I/O Standard: 2.5 V, Current Strength: Default
-- wr_addr[0] => Location: PIN_103, I/O Standard: 2.5 V, Current Strength: Default
-- wr_addr[1] => Location: PIN_10, I/O Standard: 2.5 V, Current Strength: Default
-- wr_addr[2] => Location: PIN_11, I/O Standard: 2.5 V, Current Strength: Default
-- wr_addr[3] => Location: PIN_51, I/O Standard: 2.5 V, Current Strength: Default
-- in_data[1] => Location: PIN_136, I/O Standard: 2.5 V, Current Strength: Default
-- in_data[2] => Location: PIN_49, I/O Standard: 2.5 V, Current Strength: Default
-- in_data[3] => Location: PIN_138, I/O Standard: 2.5 V, Current Strength: Default
-- in_data[4] => Location: PIN_133, I/O Standard: 2.5 V, Current Strength: Default
-- in_data[5] => Location: PIN_24, I/O Standard: 2.5 V, Current Strength: Default
-- in_data[6] => Location: PIN_25, I/O Standard: 2.5 V, Current Strength: Default
-- in_data[7] => Location: PIN_31, I/O Standard: 2.5 V, Current Strength: Default
ARCHITECTURE structure OF model_machine IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_rst : std_logic;
SIGNAL ww_wr_data : std_logic;
SIGNAL ww_wr_addr : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_in_data : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_test_bus : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_test : std_logic;
SIGNAL ww_ax : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_bx : std_logic_vector(7 DOWNTO 0);
SIGNAL \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(35 DOWNTO 0);
SIGNAL \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(35 DOWNTO 0);
SIGNAL \u8|Equal11~0clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \reset~0clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \clk~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \test_bus[0]~output_o\ : std_logic;
SIGNAL \test_bus[1]~output_o\ : std_logic;
SIGNAL \test_bus[2]~output_o\ : std_logic;
SIGNAL \test_bus[3]~output_o\ : std_logic;
SIGNAL \test_bus[4]~output_o\ : std_logic;
SIGNAL \test_bus[5]~output_o\ : std_logic;
SIGNAL \test_bus[6]~output_o\ : std_logic;
SIGNAL \test_bus[7]~output_o\ : std_logic;
SIGNAL \test~output_o\ : std_logic;
SIGNAL \ax[0]~output_o\ : std_logic;
SIGNAL \ax[1]~output_o\ : std_logic;
SIGNAL \ax[2]~output_o\ : std_logic;
SIGNAL \ax[3]~output_o\ : std_logic;
SIGNAL \ax[4]~output_o\ : std_logic;
SIGNAL \ax[5]~output_o\ : std_logic;
SIGNAL \ax[6]~output_o\ : std_logic;
SIGNAL \ax[7]~output_o\ : std_logic;
SIGNAL \bx[0]~output_o\ : std_logic;
SIGNAL \bx[1]~output_o\ : std_logic;
SIGNAL \bx[2]~output_o\ : std_logic;
SIGNAL \bx[3]~output_o\ : std_logic;
SIGNAL \bx[4]~output_o\ : std_logic;
SIGNAL \bx[5]~output_o\ : std_logic;
SIGNAL \bx[6]~output_o\ : std_logic;
SIGNAL \bx[7]~output_o\ : std_logic;
SIGNAL \clk~input_o\ : std_logic;
SIGNAL \clk~inputclkctrl_outclk\ : std_logic;
SIGNAL \rst~input_o\ : std_logic;
SIGNAL \wr_data~input_o\ : std_logic;
SIGNAL \reset~0_combout\ : std_logic;
SIGNAL \reset~0clkctrl_outclk\ : std_logic;
SIGNAL \u9|temp[0]~1_combout\ : std_logic;
SIGNAL \u9|temp[1]~0_combout\ : std_logic;
SIGNAL \u8|Equal4~0_combout\ : std_logic;
SIGNAL \u10|dr_to_bus~5_combout\ : std_logic;
SIGNAL \u10|alu_add~combout\ : std_logic;
SIGNAL \u10|alu_shl~0_combout\ : std_logic;
SIGNAL \u10|alu_shl~combout\ : std_logic;
SIGNAL \u8|Equal5~0_combout\ : std_logic;
SIGNAL \u8|Equal5~1_combout\ : std_logic;
SIGNAL \u10|dr_to_bus~4_combout\ : std_logic;
SIGNAL \u10|alu_sub~combout\ : std_logic;
SIGNAL \u7|temp[6]~8_combout\ : std_logic;
SIGNAL \u8|Equal1~0_combout\ : std_logic;
SIGNAL \u7|temp~22_combout\ : std_logic;
SIGNAL \u7|temp~19_combout\ : std_logic;
SIGNAL \u6|temp_a~6_combout\ : std_logic;
SIGNAL \u6|temp_a[0]~1_combout\ : std_logic;
SIGNAL \u6|temp_b~6_combout\ : std_logic;
SIGNAL \u6|temp_b[0]~1_combout\ : std_logic;
SIGNAL \u10|a_to_bus~0_combout\ : std_logic;
SIGNAL \u10|a_to_bus~1_combout\ : std_logic;
SIGNAL \u10|a_to_bus~combout\ : std_logic;
SIGNAL \u6|acc_out[5]~5_combout\ : std_logic;
SIGNAL \u7|Add0~17_combout\ : std_logic;
SIGNAL \u7|Add0~14_combout\ : std_logic;
SIGNAL \u7|temp~11_combout\ : std_logic;
SIGNAL \u6|temp_b~2_combout\ : std_logic;
SIGNAL \u6|temp_a~2_combout\ : std_logic;
SIGNAL \u6|acc_out[1]~1_combout\ : std_logic;
SIGNAL \u5|dr_out[1]~26_combout\ : std_logic;
SIGNAL \u7|Add0~8_combout\ : std_logic;
SIGNAL \u7|Add0~5_combout\ : std_logic;
SIGNAL \u7|Add0~0_combout\ : std_logic;
SIGNAL \u7|Add0~2_cout\ : std_logic;
SIGNAL \u7|Add0~4\ : std_logic;
SIGNAL \u7|Add0~7\ : std_logic;
SIGNAL \u7|Add0~9_combout\ : std_logic;
SIGNAL \u7|temp~12_combout\ : std_logic;
SIGNAL \in_data[0]~input_o\ : std_logic;
SIGNAL \u10|dr_to_bus~0_combout\ : std_logic;
SIGNAL \u10|dr_to_bus~1_combout\ : std_logic;
SIGNAL \u10|pc_to_mar~0_combout\ : std_logic;
SIGNAL \u10|pc_sfincs~0_combout\ : std_logic;
SIGNAL \u10|pc_sfincs~1_combout\ : std_logic;
SIGNAL \u10|alu_out~1_combout\ : std_logic;
SIGNAL \u10|pc_sfincs~2_combout\ : std_logic;
SIGNAL \u1|tmp[0]~0_combout\ : std_logic;
SIGNAL \u10|pc_to_mar~1_combout\ : std_logic;
SIGNAL \u10|pc_to_mar~combout\ : std_logic;
SIGNAL \wr_addr[0]~input_o\ : std_logic;
SIGNAL \u3|res[0]~0_combout\ : std_logic;
SIGNAL \wr_addr[1]~input_o\ : std_logic;
SIGNAL \u1|tmp[1]~1_combout\ : std_logic;
SIGNAL \u1|tmp[1]~2_combout\ : std_logic;
SIGNAL \u3|res[1]~1_combout\ : std_logic;
SIGNAL \wr_addr[2]~input_o\ : std_logic;
SIGNAL \u1|tmp[2]~3_combout\ : std_logic;
SIGNAL \u3|res[2]~2_combout\ : std_logic;
SIGNAL \u1|tmp[3]~4_combout\ : std_logic;
SIGNAL \wr_addr[3]~input_o\ : std_logic;
SIGNAL \u3|res[3]~3_combout\ : std_logic;
SIGNAL \in_data[1]~input_o\ : std_logic;
SIGNAL \in_data[2]~input_o\ : std_logic;
SIGNAL \in_data[3]~input_o\ : std_logic;
SIGNAL \in_data[4]~input_o\ : std_logic;
SIGNAL \in_data[5]~input_o\ : std_logic;
SIGNAL \in_data[6]~input_o\ : std_logic;
SIGNAL \in_data[7]~input_o\ : std_logic;
SIGNAL \u4|mem_rtl_0|auto_generated|ram_block1a2\ : std_logic;
SIGNAL \u10|alu_out~0_combout\ : std_logic;
SIGNAL \u10|alu_out~2_combout\ : std_logic;
SIGNAL \u10|alu_out~combout\ : std_logic;
SIGNAL \u5|dr_out[2]~13_combout\ : std_logic;
SIGNAL \u5|dr_out[2]~27_combout\ : std_logic;
SIGNAL \u7|Add0~10\ : std_logic;
SIGNAL \u7|Add0~12_combout\ : std_logic;
SIGNAL \u7|temp~13_combout\ : std_logic;
SIGNAL \u7|temp~14_combout\ : std_logic;
SIGNAL \u4|mem_rtl_0|auto_generated|ram_block1a3\ : std_logic;
SIGNAL \u5|dr_out[3]~15_combout\ : std_logic;
SIGNAL \u7|Add0~11_combout\ : std_logic;
SIGNAL \u7|Add0~13\ : std_logic;
SIGNAL \u7|Add0~16\ : std_logic;
SIGNAL \u7|Add0~18_combout\ : std_logic;
SIGNAL \u7|temp~17_combout\ : std_logic;
SIGNAL \u7|temp~18_combout\ : std_logic;
SIGNAL \u4|mem_rtl_0|auto_generated|ram_block1a5\ : std_logic;
SIGNAL \u5|dr_out[5]~19_combout\ : std_logic;
SIGNAL \u5|dr_out[5]~30_combout\ : std_logic;
SIGNAL \u7|Add0~20_combout\ : std_logic;
SIGNAL \u7|Add0~19\ : std_logic;
SIGNAL \u7|Add0~21_combout\ : std_logic;
SIGNAL \u7|temp~20_combout\ : std_logic;
SIGNAL \u4|mem_rtl_0|auto_generated|ram_block1a6\ : std_logic;
SIGNAL \u5|dr_out[6]~21_combout\ : std_logic;
SIGNAL \u5|dr_out[6]~31_combout\ : std_logic;
SIGNAL \u6|temp_b~7_combout\ : std_logic;
SIGNAL \u6|temp_a~7_combout\ : std_logic;
SIGNAL \u6|acc_out[6]~6_combout\ : std_logic;
SIGNAL \u7|temp~21_combout\ : std_logic;
SIGNAL \u7|temp~4_combout\ : std_logic;
SIGNAL \u7|temp~24_combout\ : std_logic;
SIGNAL \u7|Add0~23_combout\ : std_logic;
SIGNAL \u7|Add0~22\ : std_logic;
SIGNAL \u7|Add0~24_combout\ : std_logic;
SIGNAL \u7|temp~23_combout\ : std_logic;
SIGNAL \u4|mem_rtl_0|auto_generated|ram_block1a7\ : std_logic;
SIGNAL \u5|dr_out[7]~23_combout\ : std_logic;
SIGNAL \u5|dr_out[7]~32_combout\ : std_logic;
SIGNAL \u6|temp_b~8_combout\ : std_logic;
SIGNAL \u6|temp_a~8_combout\ : std_logic;
SIGNAL \u6|acc_out[7]~7_combout\ : std_logic;
SIGNAL \u8|tmp~4_combout\ : std_logic;
SIGNAL \u10|bus_to_ir~combout\ : std_logic;
SIGNAL \u8|tmp[1]~1_combout\ : std_logic;
SIGNAL \u8|tmp~3_combout\ : std_logic;
SIGNAL \u8|tmp~8_combout\ : std_logic;
SIGNAL \u8|Equal3~0_combout\ : std_logic;
SIGNAL \u8|Equal3~1_combout\ : std_logic;
SIGNAL \u10|bus_to_b~0_combout\ : std_logic;
SIGNAL \u10|bus_to_b~1_combout\ : std_logic;
SIGNAL \u10|bus_to_b~combout\ : std_logic;
SIGNAL \u6|temp_b~4_combout\ : std_logic;
SIGNAL \u6|temp_a~4_combout\ : std_logic;
SIGNAL \u6|acc_out[3]~3_combout\ : std_logic;
SIGNAL \u5|dr_out[3]~28_combout\ : std_logic;
SIGNAL \u7|temp~15_combout\ : std_logic;
SIGNAL \u7|Add0~15_combout\ : std_logic;
SIGNAL \u7|temp~16_combout\ : std_logic;
SIGNAL \u4|mem_rtl_0|auto_generated|ram_block1a4\ : std_logic;
SIGNAL \u5|dr_out[4]~17_combout\ : std_logic;
SIGNAL \u5|dr_out[4]~29_combout\ : std_logic;
SIGNAL \u6|temp_a~5_combout\ : std_logic;
SIGNAL \u6|temp_b~5_combout\ : std_logic;
SIGNAL \u6|acc_out[4]~4_combout\ : std_logic;
SIGNAL \u8|tmp~2_combout\ : std_logic;
SIGNAL \u8|Equal0~0_combout\ : std_logic;
SIGNAL \u8|Equal7~0_combout\ : std_logic;
SIGNAL \u10|alu_shr~0_combout\ : std_logic;
SIGNAL \u10|alu_shr~combout\ : std_logic;
SIGNAL \u7|temp~7_combout\ : std_logic;
SIGNAL \u5|dr_out[0]~25_combout\ : std_logic;
SIGNAL \u7|Add0~6_combout\ : std_logic;
SIGNAL \u7|temp~9_combout\ : std_logic;
SIGNAL \u7|temp~10_combout\ : std_logic;
SIGNAL \u4|mem_rtl_0|auto_generated|ram_block1a1\ : std_logic;
SIGNAL \u5|dr_out[1]~11_combout\ : std_logic;
SIGNAL \u8|tmp~6_combout\ : std_logic;
SIGNAL \u10|bus_to_a~1_combout\ : std_logic;
SIGNAL \u10|bus_to_a~0_combout\ : std_logic;
SIGNAL \u10|bus_to_a~2_combout\ : std_logic;
SIGNAL \u10|bus_to_a~combout\ : std_logic;
SIGNAL \u6|temp_a~3_combout\ : std_logic;
SIGNAL \u6|temp_b~3_combout\ : std_logic;
SIGNAL \u6|acc_out[2]~2_combout\ : std_logic;
SIGNAL \u8|tmp~5_combout\ : std_logic;
SIGNAL \u8|Equal0~1_combout\ : std_logic;
SIGNAL \u10|b_to_bus~0_combout\ : std_logic;
SIGNAL \u10|b_to_bus~combout\ : std_logic;
SIGNAL \u5|dr_out[0]~10_combout\ : std_logic;
SIGNAL \u8|tmp~0_combout\ : std_logic;
SIGNAL \u8|Equal11~0_combout\ : std_logic;
SIGNAL \u8|Equal11~0clkctrl_outclk\ : std_logic;
SIGNAL \u10|dr_to_bus~2_combout\ : std_logic;
SIGNAL \u10|dr_to_bus~3_combout\ : std_logic;
SIGNAL \u10|dr_to_bus~combout\ : std_logic;
SIGNAL \u7|Add0~3_combout\ : std_logic;
SIGNAL \u7|temp~5_combout\ : std_logic;
SIGNAL \u7|temp~6_combout\ : std_logic;
SIGNAL \u4|mem_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
SIGNAL \u5|dr_out[0]~8_combout\ : std_logic;
SIGNAL \u8|tmp~7_combout\ : std_logic;
SIGNAL \u8|Equal8~0_combout\ : std_logic;
SIGNAL \u10|acc_xchg~0_combout\ : std_logic;
SIGNAL \u10|acc_xchg~combout\ : std_logic;
SIGNAL \u6|temp_b~0_combout\ : std_logic;
SIGNAL \u6|temp_a~0_combout\ : std_logic;
SIGNAL \u6|acc_out[0]~0_combout\ : std_logic;
SIGNAL \u5|dr_out[0]~9_combout\ : std_logic;
SIGNAL \u5|dr_out[1]~12_combout\ : std_logic;
SIGNAL \u5|dr_out[2]~14_combout\ : std_logic;
SIGNAL \u5|dr_out[3]~16_combout\ : std_logic;
SIGNAL \u5|dr_out[4]~18_combout\ : std_logic;
SIGNAL \u5|dr_out[5]~20_combout\ : std_logic;
SIGNAL \u5|dr_out[6]~22_combout\ : std_logic;
SIGNAL \u5|dr_out[7]~24_combout\ : std_logic;
SIGNAL \u2|temp\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \u6|temp_a\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \u6|temp_b\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \u1|tmp\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \u7|temp\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \u9|temp\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \u8|tmp\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \ALT_INV_reset~0clkctrl_outclk\ : std_logic;
SIGNAL \ALT_INV_wr_data~input_o\ : std_logic;
COMPONENT hard_block
PORT (
devoe : IN std_logic;
devclrn : IN std_logic;
devpor : IN std_logic);
END COMPONENT;
BEGIN
ww_clk <= clk;
ww_rst <= rst;
ww_wr_data <= wr_data;
ww_wr_addr <= wr_addr;
ww_in_data <= in_data;
test_bus <= ww_test_bus;
test <= ww_test;
ax <= ww_ax;
bx <= ww_bx;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\u4|mem_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & \in_data[7]~input_o\ &
\in_data[6]~input_o\ & \in_data[5]~input_o\ & \in_data[4]~input_o\ & \in_data[3]~input_o\ & \in_data[2]~input_o\ & \in_data[1]~input_o\ & \in_data[0]~input_o\);
\u4|mem_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\u3|res[3]~3_combout\ & \u3|res[2]~2_combout\ & \u3|res[1]~1_combout\ & \u3|res[0]~0_combout\);
\u4|mem_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\u3|res[3]~3_combout\ & \u3|res[2]~2_combout\ & \u3|res[1]~1_combout\ & \u3|res[0]~0_combout\);
\u4|mem_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
\u4|mem_rtl_0|auto_generated|ram_block1a1\ <= \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1);
\u4|mem_rtl_0|auto_generated|ram_block1a2\ <= \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2);
\u4|mem_rtl_0|auto_generated|ram_block1a3\ <= \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3);
\u4|mem_rtl_0|auto_generated|ram_block1a4\ <= \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4);
\u4|mem_rtl_0|auto_generated|ram_block1a5\ <= \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5);
\u4|mem_rtl_0|auto_generated|ram_block1a6\ <= \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6);
\u4|mem_rtl_0|auto_generated|ram_block1a7\ <= \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7);
\u8|Equal11~0clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \u8|Equal11~0_combout\);
\reset~0clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \reset~0_combout\);
\clk~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clk~input_o\);
\ALT_INV_reset~0clkctrl_outclk\ <= NOT \reset~0clkctrl_outclk\;
\ALT_INV_wr_data~input_o\ <= NOT \wr_data~input_o\;
auto_generated_inst : hard_block
PORT MAP (
devoe => ww_devoe,
devclrn => ww_devclrn,
devpor => ww_devpor);
-- Location: IOOBUF_X16_Y24_N16
\test_bus[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u5|dr_out[0]~9_combout\,
oe => \u5|dr_out[0]~10_combout\,
devoe => ww_devoe,
o => \test_bus[0]~output_o\);
-- Location: IOOBUF_X28_Y24_N16
\test_bus[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u5|dr_out[1]~12_combout\,
oe => \u5|dr_out[0]~10_combout\,
devoe => ww_devoe,
o => \test_bus[1]~output_o\);
-- Location: IOOBUF_X28_Y24_N2
\test_bus[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u5|dr_out[2]~14_combout\,
oe => \u5|dr_out[0]~10_combout\,
devoe => ww_devoe,
o => \test_bus[2]~output_o\);
-- Location: IOOBUF_X23_Y24_N2
\test_bus[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u5|dr_out[3]~16_combout\,
oe => \u5|dr_out[0]~10_combout\,
devoe => ww_devoe,
o => \test_bus[3]~output_o\);
-- Location: IOOBUF_X28_Y24_N9
\test_bus[4]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u5|dr_out[4]~18_combout\,
oe => \u5|dr_out[0]~10_combout\,
devoe => ww_devoe,
o => \test_bus[4]~output_o\);
-- Location: IOOBUF_X28_Y24_N23
\test_bus[5]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u5|dr_out[5]~20_combout\,
oe => \u5|dr_out[0]~10_combout\,
devoe => ww_devoe,
o => \test_bus[5]~output_o\);
-- Location: IOOBUF_X16_Y24_N23
\test_bus[6]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u5|dr_out[6]~22_combout\,
oe => \u5|dr_out[0]~10_combout\,
devoe => ww_devoe,
o => \test_bus[6]~output_o\);
-- Location: IOOBUF_X23_Y24_N9
\test_bus[7]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u5|dr_out[7]~24_combout\,
oe => \u5|dr_out[0]~10_combout\,
devoe => ww_devoe,
o => \test_bus[7]~output_o\);
-- Location: IOOBUF_X5_Y24_N9
\test~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u10|bus_to_ir~combout\,
devoe => ww_devoe,
o => \test~output_o\);
-- Location: IOOBUF_X0_Y21_N9
\ax[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_a\(0),
devoe => ww_devoe,
o => \ax[0]~output_o\);
-- Location: IOOBUF_X18_Y24_N23
\ax[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_a\(1),
devoe => ww_devoe,
o => \ax[1]~output_o\);
-- Location: IOOBUF_X16_Y0_N2
\ax[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_a\(2),
devoe => ww_devoe,
o => \ax[2]~output_o\);
-- Location: IOOBUF_X18_Y24_N16
\ax[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_a\(3),
devoe => ww_devoe,
o => \ax[3]~output_o\);
-- Location: IOOBUF_X34_Y18_N2
\ax[4]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_a\(4),
devoe => ww_devoe,
o => \ax[4]~output_o\);
-- Location: IOOBUF_X34_Y20_N9
\ax[5]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_a\(5),
devoe => ww_devoe,
o => \ax[5]~output_o\);
-- Location: IOOBUF_X16_Y24_N2
\ax[6]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_a\(6),
devoe => ww_devoe,
o => \ax[6]~output_o\);
-- Location: IOOBUF_X18_Y0_N23
\ax[7]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_a\(7),
devoe => ww_devoe,
o => \ax[7]~output_o\);
-- Location: IOOBUF_X18_Y0_N16
\bx[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_b\(0),
devoe => ww_devoe,
o => \bx[0]~output_o\);
-- Location: IOOBUF_X30_Y24_N23
\bx[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_b\(1),
devoe => ww_devoe,
o => \bx[1]~output_o\);
-- Location: IOOBUF_X34_Y17_N2
\bx[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_b\(2),
devoe => ww_devoe,
o => \bx[2]~output_o\);
-- Location: IOOBUF_X7_Y24_N2
\bx[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_b\(3),
devoe => ww_devoe,
o => \bx[3]~output_o\);
-- Location: IOOBUF_X13_Y0_N2
\bx[4]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_b\(4),
devoe => ww_devoe,
o => \bx[4]~output_o\);
-- Location: IOOBUF_X11_Y24_N16
\bx[5]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_b\(5),
devoe => ww_devoe,
o => \bx[5]~output_o\);
-- Location: IOOBUF_X23_Y24_N16
\bx[6]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_b\(6),
devoe => ww_devoe,
o => \bx[6]~output_o\);
-- Location: IOOBUF_X16_Y0_N9
\bx[7]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \u6|temp_b\(7),
devoe => ww_devoe,
o => \bx[7]~output_o\);
-- Location: IOIBUF_X0_Y11_N8
\clk~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_clk,
o => \clk~input_o\);
-- Location: CLKCTRL_G2
\clk~inputclkctrl\ : cycloneive_clkctrl
-- pragma translate_off
GENERIC MAP (
clock_type => "global clock",
ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
inclk => \clk~inputclkctrl_INCLK_bus\,
devclrn => ww_devclrn,
devpor => ww_devpor,
outclk => \clk~inputclkctrl_outclk\);
-- Location: IOIBUF_X16_Y24_N8
\rst~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_rst,
o => \rst~input_o\);
-- Location: IOIBUF_X13_Y24_N15
\wr_data~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_wr_data,
o => \wr_data~input_o\);
-- Location: LCCOMB_X17_Y20_N2
\reset~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \reset~0_combout\ = (\rst~input_o\) # (!\wr_data~input_o\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111000011111111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datac => \rst~input_o\,
datad => \wr_data~input_o\,
combout => \reset~0_combout\);
-- Location: CLKCTRL_G8
\reset~0clkctrl\ : cycloneive_clkctrl
-- pragma translate_off
GENERIC MAP (
clock_type => "global clock",
ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
inclk => \reset~0clkctrl_INCLK_bus\,
devclrn => ww_devclrn,
devpor => ww_devpor,
outclk => \reset~0clkctrl_outclk\);
-- Location: FF_X19_Y18_N7
\u9|temp[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
asdata => \u9|temp\(4),
clrn => \ALT_INV_reset~0clkctrl_outclk\,
sload => VCC,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u9|temp\(5));
-- Location: FF_X17_Y18_N29
\u9|temp[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
asdata => \u9|temp\(5),
clrn => \ALT_INV_reset~0clkctrl_outclk\,
sload => VCC,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u9|temp\(6));
-- Location: FF_X17_Y18_N3
\u9|temp[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
asdata => \u9|temp\(6),
clrn => \ALT_INV_reset~0clkctrl_outclk\,
sload => VCC,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u9|temp\(7));
-- Location: LCCOMB_X17_Y18_N20
\u9|temp[0]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u9|temp[0]~1_combout\ = !\u9|temp\(7)
-- pragma translate_off
GENERIC MAP (
lut_mask => "0011001100110011",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u9|temp\(7),
combout => \u9|temp[0]~1_combout\);
-- Location: FF_X17_Y18_N7
\u9|temp[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
asdata => \u9|temp[0]~1_combout\,
clrn => \ALT_INV_reset~0clkctrl_outclk\,
sload => VCC,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u9|temp\(0));
-- Location: LCCOMB_X17_Y18_N4
\u9|temp[1]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u9|temp[1]~0_combout\ = !\u9|temp\(0)
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000000011111111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datad => \u9|temp\(0),
combout => \u9|temp[1]~0_combout\);
-- Location: FF_X17_Y18_N5
\u9|temp[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u9|temp[1]~0_combout\,
clrn => \ALT_INV_reset~0clkctrl_outclk\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u9|temp\(1));
-- Location: FF_X17_Y18_N31
\u9|temp[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
asdata => \u9|temp\(1),
clrn => \ALT_INV_reset~0clkctrl_outclk\,
sload => VCC,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u9|temp\(2));
-- Location: FF_X17_Y18_N21
\u9|temp[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
asdata => \u9|temp\(2),
clrn => \ALT_INV_reset~0clkctrl_outclk\,
sload => VCC,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u9|temp\(3));
-- Location: FF_X19_Y18_N23
\u9|temp[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
asdata => \u9|temp\(3),
clrn => \ALT_INV_reset~0clkctrl_outclk\,
sload => VCC,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u9|temp\(4));
-- Location: LCCOMB_X19_Y18_N10
\u8|Equal4~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|Equal4~0_combout\ = (\u8|tmp\(0) & (\u8|tmp\(2) & (!\u8|tmp\(3) & \u8|Equal0~0_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000100000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|tmp\(0),
datab => \u8|tmp\(2),
datac => \u8|tmp\(3),
datad => \u8|Equal0~0_combout\,
combout => \u8|Equal4~0_combout\);
-- Location: LCCOMB_X19_Y20_N20
\u10|dr_to_bus~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|dr_to_bus~5_combout\ = (\u9|temp\(4) & (!\u8|tmp\(1) & \u8|Equal4~0_combout\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0010000000100000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u9|temp\(4),
datab => \u8|tmp\(1),
datac => \u8|Equal4~0_combout\,
combout => \u10|dr_to_bus~5_combout\);
-- Location: LCCOMB_X19_Y20_N30
\u10|alu_add\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|alu_add~combout\ = (GLOBAL(\u8|Equal11~0clkctrl_outclk\) & ((\u10|alu_add~combout\))) # (!GLOBAL(\u8|Equal11~0clkctrl_outclk\) & (\u10|dr_to_bus~5_combout\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111000010101010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|dr_to_bus~5_combout\,
datac => \u10|alu_add~combout\,
datad => \u8|Equal11~0clkctrl_outclk\,
combout => \u10|alu_add~combout\);
-- Location: LCCOMB_X19_Y18_N26
\u10|alu_shl~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|alu_shl~0_combout\ = (\u9|temp\(3) & ((\u8|tmp\(1) & ((\u8|Equal7~0_combout\))) # (!\u8|tmp\(1) & (\u8|Equal8~0_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010100000100000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u9|temp\(3),
datab => \u8|tmp\(1),
datac => \u8|Equal8~0_combout\,
datad => \u8|Equal7~0_combout\,
combout => \u10|alu_shl~0_combout\);
-- Location: LCCOMB_X16_Y18_N22
\u10|alu_shl\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|alu_shl~combout\ = (GLOBAL(\u8|Equal11~0clkctrl_outclk\) & ((\u10|alu_shl~combout\))) # (!GLOBAL(\u8|Equal11~0clkctrl_outclk\) & (\u10|alu_shl~0_combout\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111000010101010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|alu_shl~0_combout\,
datac => \u10|alu_shl~combout\,
datad => \u8|Equal11~0clkctrl_outclk\,
combout => \u10|alu_shl~combout\);
-- Location: LCCOMB_X18_Y18_N0
\u8|Equal5~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|Equal5~0_combout\ = (!\u8|tmp\(3) & \u8|tmp\(1))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000111100000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datac => \u8|tmp\(3),
datad => \u8|tmp\(1),
combout => \u8|Equal5~0_combout\);
-- Location: LCCOMB_X18_Y18_N12
\u8|Equal5~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|Equal5~1_combout\ = (\u8|tmp\(2) & (!\u8|tmp\(0) & (\u8|Equal0~0_combout\ & \u8|Equal5~0_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0010000000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|tmp\(2),
datab => \u8|tmp\(0),
datac => \u8|Equal0~0_combout\,
datad => \u8|Equal5~0_combout\,
combout => \u8|Equal5~1_combout\);
-- Location: LCCOMB_X19_Y20_N18
\u10|dr_to_bus~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|dr_to_bus~4_combout\ = (\u9|temp\(4) & \u8|Equal5~1_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010101000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u9|temp\(4),
datad => \u8|Equal5~1_combout\,
combout => \u10|dr_to_bus~4_combout\);
-- Location: LCCOMB_X19_Y20_N4
\u10|alu_sub\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|alu_sub~combout\ = (GLOBAL(\u8|Equal11~0clkctrl_outclk\) & (\u10|alu_sub~combout\)) # (!GLOBAL(\u8|Equal11~0clkctrl_outclk\) & ((\u10|dr_to_bus~4_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100110011110000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u10|alu_sub~combout\,
datac => \u10|dr_to_bus~4_combout\,
datad => \u8|Equal11~0clkctrl_outclk\,
combout => \u10|alu_sub~combout\);
-- Location: LCCOMB_X16_Y19_N8
\u7|temp[6]~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp[6]~8_combout\ = (\u10|alu_shl~combout\) # ((!\u10|alu_shr~combout\ & ((\u10|alu_add~combout\) # (\u10|alu_sub~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100111111001110",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|alu_add~combout\,
datab => \u10|alu_shl~combout\,
datac => \u10|alu_shr~combout\,
datad => \u10|alu_sub~combout\,
combout => \u7|temp[6]~8_combout\);
-- Location: LCCOMB_X18_Y18_N22
\u8|Equal1~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|Equal1~0_combout\ = (!\u8|tmp\(2) & (!\u8|tmp\(0) & (\u8|Equal0~0_combout\ & \u8|Equal5~0_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0001000000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|tmp\(2),
datab => \u8|tmp\(0),
datac => \u8|Equal0~0_combout\,
datad => \u8|Equal5~0_combout\,
combout => \u8|Equal1~0_combout\);
-- Location: LCCOMB_X16_Y19_N12
\u7|temp~22\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~22_combout\ = (!\u10|alu_shl~combout\ & (!\u10|alu_shr~combout\ & ((\u10|alu_add~combout\) # (\u10|alu_sub~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000001100000010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|alu_add~combout\,
datab => \u10|alu_shl~combout\,
datac => \u10|alu_shr~combout\,
datad => \u10|alu_sub~combout\,
combout => \u7|temp~22_combout\);
-- Location: LCCOMB_X17_Y20_N8
\u7|temp~19\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~19_combout\ = (\u7|temp~7_combout\ & (\u7|temp\(6) & ((!\u7|temp[6]~8_combout\)))) # (!\u7|temp~7_combout\ & (((\u5|dr_out[7]~32_combout\) # (\u7|temp[6]~8_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0011001110111000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp\(6),
datab => \u7|temp~7_combout\,
datac => \u5|dr_out[7]~32_combout\,
datad => \u7|temp[6]~8_combout\,
combout => \u7|temp~19_combout\);
-- Location: LCCOMB_X17_Y20_N24
\u6|temp_a~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_a~6_combout\ = (\u10|acc_xchg~combout\ & (\u6|temp_b\(5))) # (!\u10|acc_xchg~combout\ & (((\u10|bus_to_a~combout\ & \u5|dr_out[5]~30_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010101011000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_b\(5),
datab => \u10|bus_to_a~combout\,
datac => \u5|dr_out[5]~30_combout\,
datad => \u10|acc_xchg~combout\,
combout => \u6|temp_a~6_combout\);
-- Location: LCCOMB_X17_Y20_N4
\u6|temp_a[0]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_a[0]~1_combout\ = (\u10|acc_xchg~combout\) # ((\rst~input_o\) # ((\u10|bus_to_a~combout\) # (!\wr_data~input_o\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111111011111111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|acc_xchg~combout\,
datab => \rst~input_o\,
datac => \u10|bus_to_a~combout\,
datad => \wr_data~input_o\,
combout => \u6|temp_a[0]~1_combout\);
-- Location: FF_X17_Y20_N25
\u6|temp_a[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_a~6_combout\,
ena => \u6|temp_a[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_a\(5));
-- Location: LCCOMB_X18_Y20_N2
\u6|temp_b~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_b~6_combout\ = (\u10|acc_xchg~combout\ & (((\u6|temp_a\(5))))) # (!\u10|acc_xchg~combout\ & (\u10|bus_to_b~combout\ & ((\u5|dr_out[5]~30_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100101011000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|bus_to_b~combout\,
datab => \u6|temp_a\(5),
datac => \u10|acc_xchg~combout\,
datad => \u5|dr_out[5]~30_combout\,
combout => \u6|temp_b~6_combout\);
-- Location: LCCOMB_X17_Y20_N14
\u6|temp_b[0]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_b[0]~1_combout\ = (\u10|acc_xchg~combout\) # ((\rst~input_o\) # ((\u10|bus_to_b~combout\) # (!\wr_data~input_o\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111111011111111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|acc_xchg~combout\,
datab => \rst~input_o\,
datac => \u10|bus_to_b~combout\,
datad => \wr_data~input_o\,
combout => \u6|temp_b[0]~1_combout\);
-- Location: FF_X18_Y20_N3
\u6|temp_b[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_b~6_combout\,
ena => \u6|temp_b[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_b\(5));
-- Location: LCCOMB_X19_Y18_N18
\u10|a_to_bus~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|a_to_bus~0_combout\ = (\u8|Equal1~0_combout\) # ((\u8|tmp\(1) & ((\u8|Equal4~0_combout\))) # (!\u8|tmp\(1) & (\u8|Equal8~0_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111110011111010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|Equal8~0_combout\,
datab => \u8|Equal4~0_combout\,
datac => \u8|Equal1~0_combout\,
datad => \u8|tmp\(1),
combout => \u10|a_to_bus~0_combout\);
-- Location: LCCOMB_X19_Y18_N4
\u10|a_to_bus~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|a_to_bus~1_combout\ = (\u10|a_to_bus~0_combout\ & \u9|temp\(3))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010000010100000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|a_to_bus~0_combout\,
datac => \u9|temp\(3),
combout => \u10|a_to_bus~1_combout\);
-- Location: LCCOMB_X19_Y19_N0
\u10|a_to_bus\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|a_to_bus~combout\ = (GLOBAL(\u8|Equal11~0clkctrl_outclk\) & (\u10|a_to_bus~combout\)) # (!GLOBAL(\u8|Equal11~0clkctrl_outclk\) & ((\u10|a_to_bus~1_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100110011110000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u10|a_to_bus~combout\,
datac => \u10|a_to_bus~1_combout\,
datad => \u8|Equal11~0clkctrl_outclk\,
combout => \u10|a_to_bus~combout\);
-- Location: LCCOMB_X19_Y19_N28
\u6|acc_out[5]~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|acc_out[5]~5_combout\ = (\u10|a_to_bus~combout\ & (((\u6|temp_a\(5))))) # (!\u10|a_to_bus~combout\ & ((\u6|temp_b\(5)) # ((!\u10|b_to_bus~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100110010101111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_b\(5),
datab => \u6|temp_a\(5),
datac => \u10|b_to_bus~combout\,
datad => \u10|a_to_bus~combout\,
combout => \u6|acc_out[5]~5_combout\);
-- Location: LCCOMB_X19_Y19_N12
\u7|Add0~17\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~17_combout\ = \u10|alu_sub~combout\ $ ((((\u6|acc_out[5]~5_combout\ & \u5|dr_out[5]~19_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0110101001010101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|alu_sub~combout\,
datab => \u6|acc_out[5]~5_combout\,
datac => \u5|dr_out[5]~19_combout\,
datad => \u5|dr_out[0]~10_combout\,
combout => \u7|Add0~17_combout\);
-- Location: LCCOMB_X18_Y19_N6
\u7|Add0~14\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~14_combout\ = \u10|alu_sub~combout\ $ ((((\u6|acc_out[4]~4_combout\ & \u5|dr_out[4]~17_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0110001111000011",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|acc_out[4]~4_combout\,
datab => \u10|alu_sub~combout\,
datac => \u5|dr_out[0]~10_combout\,
datad => \u5|dr_out[4]~17_combout\,
combout => \u7|Add0~14_combout\);
-- Location: LCCOMB_X17_Y19_N0
\u7|temp~11\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~11_combout\ = (\u7|temp~7_combout\ & (\u7|temp\(2) & ((!\u7|temp[6]~8_combout\)))) # (!\u7|temp~7_combout\ & (((\u5|dr_out[3]~28_combout\) # (\u7|temp[6]~8_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0011001110111000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp\(2),
datab => \u7|temp~7_combout\,
datac => \u5|dr_out[3]~28_combout\,
datad => \u7|temp[6]~8_combout\,
combout => \u7|temp~11_combout\);
-- Location: LCCOMB_X18_Y20_N30
\u6|temp_b~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_b~2_combout\ = (\u10|acc_xchg~combout\ & (((\u6|temp_a\(1))))) # (!\u10|acc_xchg~combout\ & (\u10|bus_to_b~combout\ & ((\u5|dr_out[1]~26_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100101011000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|bus_to_b~combout\,
datab => \u6|temp_a\(1),
datac => \u10|acc_xchg~combout\,
datad => \u5|dr_out[1]~26_combout\,
combout => \u6|temp_b~2_combout\);
-- Location: FF_X18_Y20_N31
\u6|temp_b[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_b~2_combout\,
ena => \u6|temp_b[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_b\(1));
-- Location: LCCOMB_X18_Y20_N28
\u6|temp_a~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_a~2_combout\ = (\u10|acc_xchg~combout\ & (((\u6|temp_b\(1))))) # (!\u10|acc_xchg~combout\ & (\u10|bus_to_a~combout\ & ((\u5|dr_out[1]~26_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1110001011000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|bus_to_a~combout\,
datab => \u10|acc_xchg~combout\,
datac => \u6|temp_b\(1),
datad => \u5|dr_out[1]~26_combout\,
combout => \u6|temp_a~2_combout\);
-- Location: FF_X18_Y20_N29
\u6|temp_a[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_a~2_combout\,
ena => \u6|temp_a[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_a\(1));
-- Location: LCCOMB_X18_Y19_N22
\u6|acc_out[1]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|acc_out[1]~1_combout\ = (\u10|a_to_bus~combout\ & (\u6|temp_a\(1))) # (!\u10|a_to_bus~combout\ & (((\u6|temp_b\(1)) # (!\u10|b_to_bus~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010110010101111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_a\(1),
datab => \u6|temp_b\(1),
datac => \u10|a_to_bus~combout\,
datad => \u10|b_to_bus~combout\,
combout => \u6|acc_out[1]~1_combout\);
-- Location: LCCOMB_X18_Y20_N10
\u5|dr_out[1]~26\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[1]~26_combout\ = ((\u6|acc_out[1]~1_combout\ & \u5|dr_out[1]~11_combout\)) # (!\u5|dr_out[0]~10_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100111100001111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u6|acc_out[1]~1_combout\,
datac => \u5|dr_out[0]~10_combout\,
datad => \u5|dr_out[1]~11_combout\,
combout => \u5|dr_out[1]~26_combout\);
-- Location: LCCOMB_X19_Y19_N10
\u7|Add0~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~8_combout\ = \u10|alu_sub~combout\ $ ((((\u6|acc_out[2]~2_combout\ & \u5|dr_out[2]~13_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0100101111000011",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|acc_out[2]~2_combout\,
datab => \u5|dr_out[0]~10_combout\,
datac => \u10|alu_sub~combout\,
datad => \u5|dr_out[2]~13_combout\,
combout => \u7|Add0~8_combout\);
-- Location: LCCOMB_X18_Y19_N20
\u7|Add0~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~5_combout\ = \u10|alu_sub~combout\ $ ((((\u6|acc_out[1]~1_combout\ & \u5|dr_out[1]~11_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0110001111000011",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|acc_out[1]~1_combout\,
datab => \u10|alu_sub~combout\,
datac => \u5|dr_out[0]~10_combout\,
datad => \u5|dr_out[1]~11_combout\,
combout => \u7|Add0~5_combout\);
-- Location: LCCOMB_X19_Y19_N6
\u7|Add0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~0_combout\ = \u10|alu_sub~combout\ $ ((((\u6|acc_out[0]~0_combout\ & \u5|dr_out[0]~8_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0110010110100101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|alu_sub~combout\,
datab => \u6|acc_out[0]~0_combout\,
datac => \u5|dr_out[0]~10_combout\,
datad => \u5|dr_out[0]~8_combout\,
combout => \u7|Add0~0_combout\);
-- Location: LCCOMB_X17_Y19_N10
\u7|Add0~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~2_cout\ = CARRY(\u10|alu_sub~combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000000011001100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u10|alu_sub~combout\,
datad => VCC,
cout => \u7|Add0~2_cout\);
-- Location: LCCOMB_X17_Y19_N12
\u7|Add0~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~3_combout\ = (\u6|temp_a\(0) & ((\u7|Add0~0_combout\ & (\u7|Add0~2_cout\ & VCC)) # (!\u7|Add0~0_combout\ & (!\u7|Add0~2_cout\)))) # (!\u6|temp_a\(0) & ((\u7|Add0~0_combout\ & (!\u7|Add0~2_cout\)) # (!\u7|Add0~0_combout\ & ((\u7|Add0~2_cout\) #
-- (GND)))))
-- \u7|Add0~4\ = CARRY((\u6|temp_a\(0) & (!\u7|Add0~0_combout\ & !\u7|Add0~2_cout\)) # (!\u6|temp_a\(0) & ((!\u7|Add0~2_cout\) # (!\u7|Add0~0_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1001011000010111",
sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_a\(0),
datab => \u7|Add0~0_combout\,
datad => VCC,
cin => \u7|Add0~2_cout\,
combout => \u7|Add0~3_combout\,
cout => \u7|Add0~4\);
-- Location: LCCOMB_X17_Y19_N14
\u7|Add0~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~6_combout\ = ((\u7|Add0~5_combout\ $ (\u6|temp_a\(1) $ (!\u7|Add0~4\)))) # (GND)
-- \u7|Add0~7\ = CARRY((\u7|Add0~5_combout\ & ((\u6|temp_a\(1)) # (!\u7|Add0~4\))) # (!\u7|Add0~5_combout\ & (\u6|temp_a\(1) & !\u7|Add0~4\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0110100110001110",
sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
dataa => \u7|Add0~5_combout\,
datab => \u6|temp_a\(1),
datad => VCC,
cin => \u7|Add0~4\,
combout => \u7|Add0~6_combout\,
cout => \u7|Add0~7\);
-- Location: LCCOMB_X17_Y19_N16
\u7|Add0~9\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~9_combout\ = (\u6|temp_a\(2) & ((\u7|Add0~8_combout\ & (\u7|Add0~7\ & VCC)) # (!\u7|Add0~8_combout\ & (!\u7|Add0~7\)))) # (!\u6|temp_a\(2) & ((\u7|Add0~8_combout\ & (!\u7|Add0~7\)) # (!\u7|Add0~8_combout\ & ((\u7|Add0~7\) # (GND)))))
-- \u7|Add0~10\ = CARRY((\u6|temp_a\(2) & (!\u7|Add0~8_combout\ & !\u7|Add0~7\)) # (!\u6|temp_a\(2) & ((!\u7|Add0~7\) # (!\u7|Add0~8_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1001011000010111",
sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_a\(2),
datab => \u7|Add0~8_combout\,
datad => VCC,
cin => \u7|Add0~7\,
combout => \u7|Add0~9_combout\,
cout => \u7|Add0~10\);
-- Location: LCCOMB_X17_Y19_N30
\u7|temp~12\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~12_combout\ = (\u7|temp[6]~8_combout\ & ((\u7|temp~11_combout\ & (\u5|dr_out[1]~26_combout\)) # (!\u7|temp~11_combout\ & ((\u7|Add0~9_combout\))))) # (!\u7|temp[6]~8_combout\ & (\u7|temp~11_combout\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1110011011000100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp[6]~8_combout\,
datab => \u7|temp~11_combout\,
datac => \u5|dr_out[1]~26_combout\,
datad => \u7|Add0~9_combout\,
combout => \u7|temp~12_combout\);
-- Location: FF_X17_Y19_N31
\u7|temp[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u7|temp~12_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u7|temp\(2));
-- Location: IOIBUF_X34_Y19_N15
\in_data[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_in_data(0),
o => \in_data[0]~input_o\);
-- Location: LCCOMB_X18_Y18_N28
\u10|dr_to_bus~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|dr_to_bus~0_combout\ = (\u8|tmp\(3)) # (\u8|tmp\(1) $ (!\u8|tmp\(2)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111110011110011",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u8|tmp\(1),
datac => \u8|tmp\(3),
datad => \u8|tmp\(2),
combout => \u10|dr_to_bus~0_combout\);
-- Location: LCCOMB_X18_Y18_N20
\u10|dr_to_bus~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|dr_to_bus~1_combout\ = ((\u10|dr_to_bus~0_combout\) # (\u8|tmp\(2) $ (!\u8|tmp\(0)))) # (!\u8|Equal0~0_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111111111010111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|Equal0~0_combout\,
datab => \u8|tmp\(2),
datac => \u8|tmp\(0),
datad => \u10|dr_to_bus~0_combout\,
combout => \u10|dr_to_bus~1_combout\);
-- Location: LCCOMB_X17_Y18_N28
\u10|pc_to_mar~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|pc_to_mar~0_combout\ = (!\u8|Equal5~1_combout\ & ((\u8|tmp\(1)) # (!\u8|Equal4~0_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0010001000110011",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|tmp\(1),
datab => \u8|Equal5~1_combout\,
datad => \u8|Equal4~0_combout\,
combout => \u10|pc_to_mar~0_combout\);
-- Location: LCCOMB_X17_Y18_N2
\u10|pc_sfincs~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|pc_sfincs~0_combout\ = (\u9|temp\(5) & ((!\u10|pc_to_mar~0_combout\) # (!\u10|dr_to_bus~1_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0100010011001100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|dr_to_bus~1_combout\,
datab => \u9|temp\(5),
datad => \u10|pc_to_mar~0_combout\,
combout => \u10|pc_sfincs~0_combout\);
-- Location: LCCOMB_X17_Y18_N6
\u10|pc_sfincs~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|pc_sfincs~1_combout\ = (\u8|Equal1~0_combout\) # ((!\u8|tmp\(1) & \u8|Equal0~1_combout\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1101110111001100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|tmp\(1),
datab => \u8|Equal1~0_combout\,
datad => \u8|Equal0~1_combout\,
combout => \u10|pc_sfincs~1_combout\);
-- Location: LCCOMB_X19_Y18_N16
\u10|alu_out~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|alu_out~1_combout\ = (!\u8|Equal7~0_combout\ & ((\u8|tmp\(1) & (!\u8|Equal4~0_combout\)) # (!\u8|tmp\(1) & ((!\u8|Equal8~0_combout\)))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000010000000111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|Equal4~0_combout\,
datab => \u8|tmp\(1),
datac => \u8|Equal7~0_combout\,
datad => \u8|Equal8~0_combout\,
combout => \u10|alu_out~1_combout\);
-- Location: LCCOMB_X17_Y18_N30
\u10|pc_sfincs~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|pc_sfincs~2_combout\ = (\u9|temp\(2)) # ((\u9|temp\(4) & ((\u10|pc_sfincs~1_combout\) # (!\u10|alu_out~1_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111100011111100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|pc_sfincs~1_combout\,
datab => \u9|temp\(4),
datac => \u9|temp\(2),
datad => \u10|alu_out~1_combout\,
combout => \u10|pc_sfincs~2_combout\);
-- Location: LCCOMB_X17_Y18_N22
\u1|tmp[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u1|tmp[0]~0_combout\ = \u1|tmp\(0) $ (((!\u8|Equal11~0_combout\ & ((\u10|pc_sfincs~0_combout\) # (\u10|pc_sfincs~2_combout\)))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111000000011110",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|pc_sfincs~0_combout\,
datab => \u10|pc_sfincs~2_combout\,
datac => \u1|tmp\(0),
datad => \u8|Equal11~0_combout\,
combout => \u1|tmp[0]~0_combout\);
-- Location: FF_X17_Y18_N23
\u1|tmp[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u1|tmp[0]~0_combout\,
clrn => \ALT_INV_reset~0clkctrl_outclk\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u1|tmp\(0));
-- Location: LCCOMB_X17_Y18_N10
\u10|pc_to_mar~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|pc_to_mar~1_combout\ = ((\u9|temp\(3) & ((!\u10|dr_to_bus~1_combout\) # (!\u10|pc_to_mar~0_combout\)))) # (!\u9|temp\(0))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0111010111110101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u9|temp\(0),
datab => \u10|pc_to_mar~0_combout\,
datac => \u9|temp\(3),
datad => \u10|dr_to_bus~1_combout\,
combout => \u10|pc_to_mar~1_combout\);
-- Location: LCCOMB_X17_Y18_N18
\u10|pc_to_mar\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|pc_to_mar~combout\ = (GLOBAL(\u8|Equal11~0clkctrl_outclk\) & (\u10|pc_to_mar~combout\)) # (!GLOBAL(\u8|Equal11~0clkctrl_outclk\) & ((\u10|pc_to_mar~1_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010101011001100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|pc_to_mar~combout\,
datab => \u10|pc_to_mar~1_combout\,
datad => \u8|Equal11~0clkctrl_outclk\,
combout => \u10|pc_to_mar~combout\);
-- Location: FF_X17_Y18_N25
\u2|temp[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
asdata => \u1|tmp\(0),
sload => VCC,
ena => \u10|pc_to_mar~combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u2|temp\(0));
-- Location: IOIBUF_X34_Y18_N15
\wr_addr[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_wr_addr(0),
o => \wr_addr[0]~input_o\);
-- Location: LCCOMB_X17_Y18_N24
\u3|res[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u3|res[0]~0_combout\ = (\wr_data~input_o\ & (\u2|temp\(0))) # (!\wr_data~input_o\ & ((\wr_addr[0]~input_o\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111001111000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \wr_data~input_o\,
datac => \u2|temp\(0),
datad => \wr_addr[0]~input_o\,
combout => \u3|res[0]~0_combout\);
-- Location: IOIBUF_X0_Y18_N15
\wr_addr[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_wr_addr(1),
o => \wr_addr[1]~input_o\);
-- Location: LCCOMB_X17_Y18_N12
\u1|tmp[1]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u1|tmp[1]~1_combout\ = (!\u8|Equal11~0_combout\ & (\u1|tmp\(0) & ((\u10|pc_sfincs~2_combout\) # (\u10|pc_sfincs~0_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0100010001000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|Equal11~0_combout\,
datab => \u1|tmp\(0),
datac => \u10|pc_sfincs~2_combout\,
datad => \u10|pc_sfincs~0_combout\,
combout => \u1|tmp[1]~1_combout\);
-- Location: LCCOMB_X17_Y18_N14
\u1|tmp[1]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \u1|tmp[1]~2_combout\ = \u1|tmp[1]~1_combout\ $ (\u1|tmp\(1))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0101101001011010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u1|tmp[1]~1_combout\,
datac => \u1|tmp\(1),
combout => \u1|tmp[1]~2_combout\);
-- Location: FF_X17_Y18_N15
\u1|tmp[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u1|tmp[1]~2_combout\,
clrn => \ALT_INV_reset~0clkctrl_outclk\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u1|tmp\(1));
-- Location: FF_X17_Y18_N17
\u2|temp[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
asdata => \u1|tmp\(1),
sload => VCC,
ena => \u10|pc_to_mar~combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u2|temp\(1));
-- Location: LCCOMB_X17_Y18_N16
\u3|res[1]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u3|res[1]~1_combout\ = (\wr_data~input_o\ & ((\u2|temp\(1)))) # (!\wr_data~input_o\ & (\wr_addr[1]~input_o\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1110001011100010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \wr_addr[1]~input_o\,
datab => \wr_data~input_o\,
datac => \u2|temp\(1),
combout => \u3|res[1]~1_combout\);
-- Location: IOIBUF_X0_Y18_N22
\wr_addr[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_wr_addr(2),
o => \wr_addr[2]~input_o\);
-- Location: LCCOMB_X17_Y18_N26
\u1|tmp[2]~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \u1|tmp[2]~3_combout\ = \u1|tmp\(2) $ (((\u1|tmp[1]~1_combout\ & \u1|tmp\(1))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0111100001111000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u1|tmp[1]~1_combout\,
datab => \u1|tmp\(1),
datac => \u1|tmp\(2),
combout => \u1|tmp[2]~3_combout\);
-- Location: FF_X17_Y18_N27
\u1|tmp[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u1|tmp[2]~3_combout\,
clrn => \ALT_INV_reset~0clkctrl_outclk\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u1|tmp\(2));
-- Location: FF_X17_Y18_N19
\u2|temp[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
asdata => \u1|tmp\(2),
sload => VCC,
ena => \u10|pc_to_mar~combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u2|temp\(2));
-- Location: LCCOMB_X16_Y18_N24
\u3|res[2]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \u3|res[2]~2_combout\ = (\wr_data~input_o\ & ((\u2|temp\(2)))) # (!\wr_data~input_o\ & (\wr_addr[2]~input_o\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111110000110000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \wr_data~input_o\,
datac => \wr_addr[2]~input_o\,
datad => \u2|temp\(2),
combout => \u3|res[2]~2_combout\);
-- Location: LCCOMB_X17_Y18_N8
\u1|tmp[3]~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \u1|tmp[3]~4_combout\ = \u1|tmp\(3) $ (((\u1|tmp[1]~1_combout\ & (\u1|tmp\(1) & \u1|tmp\(2)))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0111100011110000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u1|tmp[1]~1_combout\,
datab => \u1|tmp\(1),
datac => \u1|tmp\(3),
datad => \u1|tmp\(2),
combout => \u1|tmp[3]~4_combout\);
-- Location: FF_X17_Y18_N9
\u1|tmp[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u1|tmp[3]~4_combout\,
clrn => \ALT_INV_reset~0clkctrl_outclk\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u1|tmp\(3));
-- Location: FF_X17_Y18_N1
\u2|temp[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
asdata => \u1|tmp\(3),
sload => VCC,
ena => \u10|pc_to_mar~combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u2|temp\(3));
-- Location: IOIBUF_X16_Y0_N22
\wr_addr[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_wr_addr(3),
o => \wr_addr[3]~input_o\);
-- Location: LCCOMB_X16_Y18_N18
\u3|res[3]~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \u3|res[3]~3_combout\ = (\wr_data~input_o\ & (\u2|temp\(3))) # (!\wr_data~input_o\ & ((\wr_addr[3]~input_o\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111001111000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \wr_data~input_o\,
datac => \u2|temp\(3),
datad => \wr_addr[3]~input_o\,
combout => \u3|res[3]~3_combout\);
-- Location: IOIBUF_X9_Y24_N8
\in_data[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_in_data(1),
o => \in_data[1]~input_o\);
-- Location: IOIBUF_X13_Y0_N15
\in_data[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_in_data(2),
o => \in_data[2]~input_o\);
-- Location: IOIBUF_X7_Y24_N8
\in_data[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_in_data(3),
o => \in_data[3]~input_o\);
-- Location: IOIBUF_X13_Y24_N22
\in_data[4]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_in_data(4),
o => \in_data[4]~input_o\);
-- Location: IOIBUF_X0_Y11_N15
\in_data[5]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_in_data(5),
o => \in_data[5]~input_o\);
-- Location: IOIBUF_X0_Y11_N22
\in_data[6]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_in_data(6),
o => \in_data[6]~input_o\);
-- Location: IOIBUF_X0_Y7_N1
\in_data[7]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_in_data(7),
o => \in_data[7]~input_o\);
-- Location: M9K_X15_Y19_N0
\u4|mem_rtl_0|auto_generated|ram_block1a0\ : cycloneive_ram_block
-- pragma translate_off
GENERIC MAP (
mem_init0 => X"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
clk0_core_clock_enable => "ena0",
clk1_core_clock_enable => "ena1",
clk1_input_clock_enable => "ena1",
data_interleave_offset_in_bits => 1,
data_interleave_width_in_bits => 1,
init_file => "db/model_machine.ram0_RAM_15119.hdl.mif",
init_file_layout => "port_a",
logical_ram_name => "RAM:u4|altsyncram:mem_rtl_0|altsyncram_76i1:auto_generated|ALTSYNCRAM",
mixed_port_feed_through_mode => "dont_care",
operation_mode => "dual_port",
port_a_address_clear => "none",
port_a_address_width => 4,
port_a_byte_enable_clock => "none",
port_a_data_out_clear => "none",
port_a_data_out_clock => "none",
port_a_data_width => 36,
port_a_first_address => 0,
port_a_first_bit_number => 0,
port_a_last_address => 15,
port_a_logical_ram_depth => 16,
port_a_logical_ram_width => 8,
port_a_read_during_write_mode => "new_data_with_nbe_read",
port_b_address_clear => "none",
port_b_address_clock => "clock1",
port_b_address_width => 4,
port_b_data_out_clear => "none",
port_b_data_out_clock => "none",
port_b_data_width => 36,
port_b_first_address => 0,
port_b_first_bit_number => 0,
port_b_last_address => 15,
port_b_logical_ram_depth => 16,
port_b_logical_ram_width => 8,
port_b_read_during_write_mode => "new_data_with_nbe_read",
port_b_read_enable_clock => "clock1",
ram_block_type => "M9K")
-- pragma translate_on
PORT MAP (
portawe => \ALT_INV_wr_data~input_o\,
portbre => VCC,
clk0 => \clk~inputclkctrl_outclk\,
clk1 => \clk~inputclkctrl_outclk\,
ena0 => \ALT_INV_wr_data~input_o\,
ena1 => \u10|dr_to_bus~combout\,
portadatain => \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\,
portaaddr => \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\,
portbaddr => \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\,
devclrn => ww_devclrn,
devpor => ww_devpor,
portbdataout => \u4|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\);
-- Location: LCCOMB_X19_Y18_N6
\u10|alu_out~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|alu_out~0_combout\ = (\u9|temp\(5) & ((\u8|Equal5~1_combout\) # ((\u8|Equal4~0_combout\ & !\u8|tmp\(1)))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010000011100000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|Equal5~1_combout\,
datab => \u8|Equal4~0_combout\,
datac => \u9|temp\(5),
datad => \u8|tmp\(1),
combout => \u10|alu_out~0_combout\);
-- Location: LCCOMB_X19_Y18_N8
\u10|alu_out~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|alu_out~2_combout\ = (\u10|alu_out~0_combout\) # ((\u9|temp\(4) & !\u10|alu_out~1_combout\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100110011111100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u10|alu_out~0_combout\,
datac => \u9|temp\(4),
datad => \u10|alu_out~1_combout\,
combout => \u10|alu_out~2_combout\);
-- Location: LCCOMB_X19_Y18_N0
\u10|alu_out\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|alu_out~combout\ = (GLOBAL(\u8|Equal11~0clkctrl_outclk\) & ((\u10|alu_out~combout\))) # (!GLOBAL(\u8|Equal11~0clkctrl_outclk\) & (\u10|alu_out~2_combout\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111000011001100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u10|alu_out~2_combout\,
datac => \u10|alu_out~combout\,
datad => \u8|Equal11~0clkctrl_outclk\,
combout => \u10|alu_out~combout\);
-- Location: LCCOMB_X19_Y19_N16
\u5|dr_out[2]~13\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[2]~13_combout\ = (\u10|dr_to_bus~combout\ & (\u4|mem_rtl_0|auto_generated|ram_block1a2\ & ((\u7|temp\(2)) # (!\u10|alu_out~combout\)))) # (!\u10|dr_to_bus~combout\ & ((\u7|temp\(2)) # ((!\u10|alu_out~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100010011110101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|dr_to_bus~combout\,
datab => \u7|temp\(2),
datac => \u4|mem_rtl_0|auto_generated|ram_block1a2\,
datad => \u10|alu_out~combout\,
combout => \u5|dr_out[2]~13_combout\);
-- Location: LCCOMB_X18_Y19_N18
\u5|dr_out[2]~27\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[2]~27_combout\ = ((\u6|acc_out[2]~2_combout\ & \u5|dr_out[2]~13_combout\)) # (!\u5|dr_out[0]~10_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100111100001111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u6|acc_out[2]~2_combout\,
datac => \u5|dr_out[0]~10_combout\,
datad => \u5|dr_out[2]~13_combout\,
combout => \u5|dr_out[2]~27_combout\);
-- Location: LCCOMB_X17_Y19_N18
\u7|Add0~12\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~12_combout\ = ((\u7|Add0~11_combout\ $ (\u6|temp_a\(3) $ (!\u7|Add0~10\)))) # (GND)
-- \u7|Add0~13\ = CARRY((\u7|Add0~11_combout\ & ((\u6|temp_a\(3)) # (!\u7|Add0~10\))) # (!\u7|Add0~11_combout\ & (\u6|temp_a\(3) & !\u7|Add0~10\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0110100110001110",
sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
dataa => \u7|Add0~11_combout\,
datab => \u6|temp_a\(3),
datad => VCC,
cin => \u7|Add0~10\,
combout => \u7|Add0~12_combout\,
cout => \u7|Add0~13\);
-- Location: LCCOMB_X17_Y19_N2
\u7|temp~13\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~13_combout\ = (\u7|temp[6]~8_combout\ & (((\u7|Add0~12_combout\)) # (!\u7|temp~7_combout\))) # (!\u7|temp[6]~8_combout\ & (\u7|temp~7_combout\ & (\u7|temp\(3))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1110101001100010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp[6]~8_combout\,
datab => \u7|temp~7_combout\,
datac => \u7|temp\(3),
datad => \u7|Add0~12_combout\,
combout => \u7|temp~13_combout\);
-- Location: LCCOMB_X17_Y19_N4
\u7|temp~14\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~14_combout\ = (\u7|temp~7_combout\ & (((\u7|temp~13_combout\)))) # (!\u7|temp~7_combout\ & ((\u7|temp~13_combout\ & (\u5|dr_out[2]~27_combout\)) # (!\u7|temp~13_combout\ & ((\u5|dr_out[4]~29_combout\)))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1110111001010000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp~7_combout\,
datab => \u5|dr_out[2]~27_combout\,
datac => \u5|dr_out[4]~29_combout\,
datad => \u7|temp~13_combout\,
combout => \u7|temp~14_combout\);
-- Location: FF_X17_Y19_N5
\u7|temp[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u7|temp~14_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u7|temp\(3));
-- Location: LCCOMB_X18_Y19_N10
\u5|dr_out[3]~15\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[3]~15_combout\ = (\u7|temp\(3) & (((\u4|mem_rtl_0|auto_generated|ram_block1a3\)) # (!\u10|dr_to_bus~combout\))) # (!\u7|temp\(3) & (!\u10|alu_out~combout\ & ((\u4|mem_rtl_0|auto_generated|ram_block1a3\) # (!\u10|dr_to_bus~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010001011110011",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp\(3),
datab => \u10|dr_to_bus~combout\,
datac => \u4|mem_rtl_0|auto_generated|ram_block1a3\,
datad => \u10|alu_out~combout\,
combout => \u5|dr_out[3]~15_combout\);
-- Location: LCCOMB_X18_Y19_N2
\u7|Add0~11\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~11_combout\ = \u10|alu_sub~combout\ $ ((((\u6|acc_out[3]~3_combout\ & \u5|dr_out[3]~15_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0110010110100101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|alu_sub~combout\,
datab => \u6|acc_out[3]~3_combout\,
datac => \u5|dr_out[0]~10_combout\,
datad => \u5|dr_out[3]~15_combout\,
combout => \u7|Add0~11_combout\);
-- Location: LCCOMB_X17_Y19_N20
\u7|Add0~15\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~15_combout\ = (\u7|Add0~14_combout\ & ((\u6|temp_a\(4) & (\u7|Add0~13\ & VCC)) # (!\u6|temp_a\(4) & (!\u7|Add0~13\)))) # (!\u7|Add0~14_combout\ & ((\u6|temp_a\(4) & (!\u7|Add0~13\)) # (!\u6|temp_a\(4) & ((\u7|Add0~13\) # (GND)))))
-- \u7|Add0~16\ = CARRY((\u7|Add0~14_combout\ & (!\u6|temp_a\(4) & !\u7|Add0~13\)) # (!\u7|Add0~14_combout\ & ((!\u7|Add0~13\) # (!\u6|temp_a\(4)))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1001011000010111",
sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
dataa => \u7|Add0~14_combout\,
datab => \u6|temp_a\(4),
datad => VCC,
cin => \u7|Add0~13\,
combout => \u7|Add0~15_combout\,
cout => \u7|Add0~16\);
-- Location: LCCOMB_X17_Y19_N22
\u7|Add0~18\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~18_combout\ = ((\u7|Add0~17_combout\ $ (\u6|temp_a\(5) $ (!\u7|Add0~16\)))) # (GND)
-- \u7|Add0~19\ = CARRY((\u7|Add0~17_combout\ & ((\u6|temp_a\(5)) # (!\u7|Add0~16\))) # (!\u7|Add0~17_combout\ & (\u6|temp_a\(5) & !\u7|Add0~16\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0110100110001110",
sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
dataa => \u7|Add0~17_combout\,
datab => \u6|temp_a\(5),
datad => VCC,
cin => \u7|Add0~16\,
combout => \u7|Add0~18_combout\,
cout => \u7|Add0~19\);
-- Location: LCCOMB_X16_Y19_N14
\u7|temp~17\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~17_combout\ = (\u7|temp[6]~8_combout\ & (((\u7|temp~7_combout\)))) # (!\u7|temp[6]~8_combout\ & ((\u7|temp~7_combout\ & ((\u7|temp\(5)))) # (!\u7|temp~7_combout\ & (\u5|dr_out[6]~31_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111110000001010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u5|dr_out[6]~31_combout\,
datab => \u7|temp\(5),
datac => \u7|temp[6]~8_combout\,
datad => \u7|temp~7_combout\,
combout => \u7|temp~17_combout\);
-- Location: LCCOMB_X17_Y19_N6
\u7|temp~18\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~18_combout\ = (\u7|temp[6]~8_combout\ & ((\u7|temp~17_combout\ & ((\u7|Add0~18_combout\))) # (!\u7|temp~17_combout\ & (\u5|dr_out[4]~29_combout\)))) # (!\u7|temp[6]~8_combout\ & (((\u7|temp~17_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111010110001000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp[6]~8_combout\,
datab => \u5|dr_out[4]~29_combout\,
datac => \u7|Add0~18_combout\,
datad => \u7|temp~17_combout\,
combout => \u7|temp~18_combout\);
-- Location: FF_X17_Y19_N7
\u7|temp[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u7|temp~18_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u7|temp\(5));
-- Location: LCCOMB_X19_Y19_N14
\u5|dr_out[5]~19\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[5]~19_combout\ = (\u10|dr_to_bus~combout\ & (\u4|mem_rtl_0|auto_generated|ram_block1a5\ & ((\u7|temp\(5)) # (!\u10|alu_out~combout\)))) # (!\u10|dr_to_bus~combout\ & ((\u7|temp\(5)) # ((!\u10|alu_out~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100010011110101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|dr_to_bus~combout\,
datab => \u7|temp\(5),
datac => \u4|mem_rtl_0|auto_generated|ram_block1a5\,
datad => \u10|alu_out~combout\,
combout => \u5|dr_out[5]~19_combout\);
-- Location: LCCOMB_X19_Y19_N4
\u5|dr_out[5]~30\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[5]~30_combout\ = ((\u5|dr_out[5]~19_combout\ & \u6|acc_out[5]~5_combout\)) # (!\u5|dr_out[0]~10_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1101110101010101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u5|dr_out[0]~10_combout\,
datab => \u5|dr_out[5]~19_combout\,
datad => \u6|acc_out[5]~5_combout\,
combout => \u5|dr_out[5]~30_combout\);
-- Location: LCCOMB_X16_Y19_N16
\u7|Add0~20\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~20_combout\ = \u10|alu_sub~combout\ $ ((((\u6|acc_out[6]~6_combout\ & \u5|dr_out[6]~21_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0110001111000011",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|acc_out[6]~6_combout\,
datab => \u10|alu_sub~combout\,
datac => \u5|dr_out[0]~10_combout\,
datad => \u5|dr_out[6]~21_combout\,
combout => \u7|Add0~20_combout\);
-- Location: LCCOMB_X17_Y19_N24
\u7|Add0~21\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~21_combout\ = (\u7|Add0~20_combout\ & ((\u6|temp_a\(6) & (\u7|Add0~19\ & VCC)) # (!\u6|temp_a\(6) & (!\u7|Add0~19\)))) # (!\u7|Add0~20_combout\ & ((\u6|temp_a\(6) & (!\u7|Add0~19\)) # (!\u6|temp_a\(6) & ((\u7|Add0~19\) # (GND)))))
-- \u7|Add0~22\ = CARRY((\u7|Add0~20_combout\ & (!\u6|temp_a\(6) & !\u7|Add0~19\)) # (!\u7|Add0~20_combout\ & ((!\u7|Add0~19\) # (!\u6|temp_a\(6)))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1001011000010111",
sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
dataa => \u7|Add0~20_combout\,
datab => \u6|temp_a\(6),
datad => VCC,
cin => \u7|Add0~19\,
combout => \u7|Add0~21_combout\,
cout => \u7|Add0~22\);
-- Location: LCCOMB_X17_Y20_N26
\u7|temp~20\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~20_combout\ = (\u7|temp[6]~8_combout\ & ((\u7|temp~19_combout\ & (\u5|dr_out[5]~30_combout\)) # (!\u7|temp~19_combout\ & ((\u7|Add0~21_combout\))))) # (!\u7|temp[6]~8_combout\ & (\u7|temp~19_combout\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1110011011000100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp[6]~8_combout\,
datab => \u7|temp~19_combout\,
datac => \u5|dr_out[5]~30_combout\,
datad => \u7|Add0~21_combout\,
combout => \u7|temp~20_combout\);
-- Location: FF_X17_Y20_N27
\u7|temp[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u7|temp~20_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u7|temp\(6));
-- Location: LCCOMB_X16_Y19_N24
\u5|dr_out[6]~21\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[6]~21_combout\ = (\u7|temp\(6) & ((\u4|mem_rtl_0|auto_generated|ram_block1a6\) # ((!\u10|dr_to_bus~combout\)))) # (!\u7|temp\(6) & (!\u10|alu_out~combout\ & ((\u4|mem_rtl_0|auto_generated|ram_block1a6\) # (!\u10|dr_to_bus~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1000101011001111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp\(6),
datab => \u4|mem_rtl_0|auto_generated|ram_block1a6\,
datac => \u10|dr_to_bus~combout\,
datad => \u10|alu_out~combout\,
combout => \u5|dr_out[6]~21_combout\);
-- Location: LCCOMB_X16_Y19_N26
\u5|dr_out[6]~31\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[6]~31_combout\ = ((\u5|dr_out[6]~21_combout\ & \u6|acc_out[6]~6_combout\)) # (!\u5|dr_out[0]~10_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100111100001111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u5|dr_out[6]~21_combout\,
datac => \u5|dr_out[0]~10_combout\,
datad => \u6|acc_out[6]~6_combout\,
combout => \u5|dr_out[6]~31_combout\);
-- Location: LCCOMB_X18_Y20_N0
\u6|temp_b~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_b~7_combout\ = (\u10|acc_xchg~combout\ & (\u6|temp_a\(6))) # (!\u10|acc_xchg~combout\ & (((\u10|bus_to_b~combout\ & \u5|dr_out[6]~31_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1011100010001000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_a\(6),
datab => \u10|acc_xchg~combout\,
datac => \u10|bus_to_b~combout\,
datad => \u5|dr_out[6]~31_combout\,
combout => \u6|temp_b~7_combout\);
-- Location: FF_X18_Y20_N1
\u6|temp_b[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_b~7_combout\,
ena => \u6|temp_b[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_b\(6));
-- Location: LCCOMB_X17_Y20_N10
\u6|temp_a~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_a~7_combout\ = (\u10|acc_xchg~combout\ & (\u6|temp_b\(6))) # (!\u10|acc_xchg~combout\ & (((\u10|bus_to_a~combout\ & \u5|dr_out[6]~31_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010101011000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_b\(6),
datab => \u10|bus_to_a~combout\,
datac => \u5|dr_out[6]~31_combout\,
datad => \u10|acc_xchg~combout\,
combout => \u6|temp_a~7_combout\);
-- Location: FF_X17_Y20_N11
\u6|temp_a[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_a~7_combout\,
ena => \u6|temp_a[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_a\(6));
-- Location: LCCOMB_X16_Y19_N10
\u6|acc_out[6]~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|acc_out[6]~6_combout\ = (\u10|a_to_bus~combout\ & (\u6|temp_a\(6))) # (!\u10|a_to_bus~combout\ & (((\u6|temp_b\(6)) # (!\u10|b_to_bus~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010101011001111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_a\(6),
datab => \u6|temp_b\(6),
datac => \u10|b_to_bus~combout\,
datad => \u10|a_to_bus~combout\,
combout => \u6|acc_out[6]~6_combout\);
-- Location: LCCOMB_X16_Y19_N18
\u7|temp~21\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~21_combout\ = (\u10|alu_shl~combout\ & (((\u6|acc_out[6]~6_combout\ & \u5|dr_out[6]~21_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1000110000001100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|acc_out[6]~6_combout\,
datab => \u10|alu_shl~combout\,
datac => \u5|dr_out[0]~10_combout\,
datad => \u5|dr_out[6]~21_combout\,
combout => \u7|temp~21_combout\);
-- Location: LCCOMB_X16_Y19_N20
\u7|temp~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~4_combout\ = (\u10|alu_add~combout\) # (\u10|alu_sub~combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111111110101010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|alu_add~combout\,
datad => \u10|alu_sub~combout\,
combout => \u7|temp~4_combout\);
-- Location: LCCOMB_X16_Y19_N30
\u7|temp~24\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~24_combout\ = (!\u10|alu_shr~combout\ & (\u7|temp\(7) & (!\u10|alu_shl~combout\ & !\u7|temp~4_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000000000000100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|alu_shr~combout\,
datab => \u7|temp\(7),
datac => \u10|alu_shl~combout\,
datad => \u7|temp~4_combout\,
combout => \u7|temp~24_combout\);
-- Location: LCCOMB_X18_Y20_N6
\u7|Add0~23\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~23_combout\ = \u10|alu_sub~combout\ $ ((((\u6|acc_out[7]~7_combout\ & \u5|dr_out[7]~23_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0110010110100101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|alu_sub~combout\,
datab => \u6|acc_out[7]~7_combout\,
datac => \u5|dr_out[0]~10_combout\,
datad => \u5|dr_out[7]~23_combout\,
combout => \u7|Add0~23_combout\);
-- Location: LCCOMB_X17_Y19_N26
\u7|Add0~24\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|Add0~24_combout\ = \u6|temp_a\(7) $ (\u7|Add0~22\ $ (!\u7|Add0~23_combout\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0101101010100101",
sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_a\(7),
datad => \u7|Add0~23_combout\,
cin => \u7|Add0~22\,
combout => \u7|Add0~24_combout\);
-- Location: LCCOMB_X16_Y19_N4
\u7|temp~23\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~23_combout\ = (\u7|temp~21_combout\) # ((\u7|temp~24_combout\) # ((\u7|temp~22_combout\ & \u7|Add0~24_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111111011111100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp~22_combout\,
datab => \u7|temp~21_combout\,
datac => \u7|temp~24_combout\,
datad => \u7|Add0~24_combout\,
combout => \u7|temp~23_combout\);
-- Location: FF_X16_Y19_N5
\u7|temp[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u7|temp~23_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u7|temp\(7));
-- Location: LCCOMB_X18_Y20_N18
\u5|dr_out[7]~23\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[7]~23_combout\ = (\u7|temp\(7) & (((\u4|mem_rtl_0|auto_generated|ram_block1a7\) # (!\u10|dr_to_bus~combout\)))) # (!\u7|temp\(7) & (!\u10|alu_out~combout\ & ((\u4|mem_rtl_0|auto_generated|ram_block1a7\) # (!\u10|dr_to_bus~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1011000010111011",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp\(7),
datab => \u10|alu_out~combout\,
datac => \u4|mem_rtl_0|auto_generated|ram_block1a7\,
datad => \u10|dr_to_bus~combout\,
combout => \u5|dr_out[7]~23_combout\);
-- Location: LCCOMB_X18_Y20_N12
\u5|dr_out[7]~32\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[7]~32_combout\ = ((\u6|acc_out[7]~7_combout\ & \u5|dr_out[7]~23_combout\)) # (!\u5|dr_out[0]~10_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111001100110011",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u5|dr_out[0]~10_combout\,
datac => \u6|acc_out[7]~7_combout\,
datad => \u5|dr_out[7]~23_combout\,
combout => \u5|dr_out[7]~32_combout\);
-- Location: LCCOMB_X18_Y20_N14
\u6|temp_b~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_b~8_combout\ = (\u10|acc_xchg~combout\ & (\u6|temp_a\(7))) # (!\u10|acc_xchg~combout\ & (((\u10|bus_to_b~combout\ & \u5|dr_out[7]~32_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1011100010001000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_a\(7),
datab => \u10|acc_xchg~combout\,
datac => \u10|bus_to_b~combout\,
datad => \u5|dr_out[7]~32_combout\,
combout => \u6|temp_b~8_combout\);
-- Location: FF_X18_Y20_N15
\u6|temp_b[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_b~8_combout\,
ena => \u6|temp_b[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_b\(7));
-- Location: LCCOMB_X18_Y20_N26
\u6|temp_a~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_a~8_combout\ = (\u10|acc_xchg~combout\ & (((\u6|temp_b\(7))))) # (!\u10|acc_xchg~combout\ & (\u10|bus_to_a~combout\ & ((\u5|dr_out[7]~32_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1110001011000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|bus_to_a~combout\,
datab => \u10|acc_xchg~combout\,
datac => \u6|temp_b\(7),
datad => \u5|dr_out[7]~32_combout\,
combout => \u6|temp_a~8_combout\);
-- Location: FF_X18_Y20_N27
\u6|temp_a[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_a~8_combout\,
ena => \u6|temp_a[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_a\(7));
-- Location: LCCOMB_X18_Y20_N4
\u6|acc_out[7]~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|acc_out[7]~7_combout\ = (\u10|a_to_bus~combout\ & (\u6|temp_a\(7))) # (!\u10|a_to_bus~combout\ & (((\u6|temp_b\(7)) # (!\u10|b_to_bus~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010110010101111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_a\(7),
datab => \u6|temp_b\(7),
datac => \u10|a_to_bus~combout\,
datad => \u10|b_to_bus~combout\,
combout => \u6|acc_out[7]~7_combout\);
-- Location: LCCOMB_X18_Y18_N2
\u8|tmp~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|tmp~4_combout\ = (!\reset~0_combout\ & (((\u6|acc_out[7]~7_combout\ & \u5|dr_out[7]~23_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0100010100000101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \reset~0_combout\,
datab => \u6|acc_out[7]~7_combout\,
datac => \u5|dr_out[0]~10_combout\,
datad => \u5|dr_out[7]~23_combout\,
combout => \u8|tmp~4_combout\);
-- Location: LCCOMB_X16_Y18_N4
\u10|bus_to_ir\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|bus_to_ir~combout\ = (GLOBAL(\u8|Equal11~0clkctrl_outclk\) & ((\u10|bus_to_ir~combout\))) # (!GLOBAL(\u8|Equal11~0clkctrl_outclk\) & (\u9|temp\(1)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111000011001100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u9|temp\(1),
datac => \u10|bus_to_ir~combout\,
datad => \u8|Equal11~0clkctrl_outclk\,
combout => \u10|bus_to_ir~combout\);
-- Location: LCCOMB_X17_Y20_N16
\u8|tmp[1]~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|tmp[1]~1_combout\ = ((\rst~input_o\) # (\u10|bus_to_ir~combout\)) # (!\wr_data~input_o\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111111111110011",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \wr_data~input_o\,
datac => \rst~input_o\,
datad => \u10|bus_to_ir~combout\,
combout => \u8|tmp[1]~1_combout\);
-- Location: FF_X18_Y18_N3
\u8|tmp[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~input_o\,
d => \u8|tmp~4_combout\,
ena => \u8|tmp[1]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u8|tmp\(7));
-- Location: LCCOMB_X18_Y18_N4
\u8|tmp~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|tmp~3_combout\ = (!\reset~0_combout\ & (((\u5|dr_out[5]~19_combout\ & \u6|acc_out[5]~5_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0100010100000101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \reset~0_combout\,
datab => \u5|dr_out[5]~19_combout\,
datac => \u5|dr_out[0]~10_combout\,
datad => \u6|acc_out[5]~5_combout\,
combout => \u8|tmp~3_combout\);
-- Location: FF_X18_Y18_N5
\u8|tmp[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~input_o\,
d => \u8|tmp~3_combout\,
ena => \u8|tmp[1]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u8|tmp\(5));
-- Location: LCCOMB_X18_Y18_N14
\u8|tmp~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|tmp~8_combout\ = (!\reset~0_combout\ & (((\u6|acc_out[6]~6_combout\ & \u5|dr_out[6]~21_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0100010100000101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \reset~0_combout\,
datab => \u6|acc_out[6]~6_combout\,
datac => \u5|dr_out[0]~10_combout\,
datad => \u5|dr_out[6]~21_combout\,
combout => \u8|tmp~8_combout\);
-- Location: FF_X18_Y18_N15
\u8|tmp[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~input_o\,
d => \u8|tmp~8_combout\,
ena => \u8|tmp[1]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u8|tmp\(6));
-- Location: LCCOMB_X18_Y18_N6
\u8|Equal3~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|Equal3~0_combout\ = (\u8|tmp\(2) & (!\u8|tmp\(0) & (!\u8|tmp\(6) & !\u8|tmp\(1))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000000000000010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|tmp\(2),
datab => \u8|tmp\(0),
datac => \u8|tmp\(6),
datad => \u8|tmp\(1),
combout => \u8|Equal3~0_combout\);
-- Location: LCCOMB_X18_Y18_N24
\u8|Equal3~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|Equal3~1_combout\ = (!\u8|tmp\(4) & (!\u8|tmp\(7) & (!\u8|tmp\(5) & \u8|Equal3~0_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000000100000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|tmp\(4),
datab => \u8|tmp\(7),
datac => \u8|tmp\(5),
datad => \u8|Equal3~0_combout\,
combout => \u8|Equal3~1_combout\);
-- Location: LCCOMB_X19_Y20_N14
\u10|bus_to_b~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|bus_to_b~0_combout\ = (\u8|Equal7~0_combout\) # ((!\u8|tmp\(3) & \u8|Equal3~1_combout\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111010111110000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|tmp\(3),
datac => \u8|Equal7~0_combout\,
datad => \u8|Equal3~1_combout\,
combout => \u10|bus_to_b~0_combout\);
-- Location: LCCOMB_X19_Y20_N8
\u10|bus_to_b~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|bus_to_b~1_combout\ = (\u9|temp\(4) & ((\u10|bus_to_b~0_combout\) # ((\u8|Equal1~0_combout\ & \u9|temp\(3))))) # (!\u9|temp\(4) & (\u8|Equal1~0_combout\ & ((\u9|temp\(3)))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1110110010100000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u9|temp\(4),
datab => \u8|Equal1~0_combout\,
datac => \u10|bus_to_b~0_combout\,
datad => \u9|temp\(3),
combout => \u10|bus_to_b~1_combout\);
-- Location: LCCOMB_X19_Y20_N26
\u10|bus_to_b\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|bus_to_b~combout\ = (GLOBAL(\u8|Equal11~0clkctrl_outclk\) & (\u10|bus_to_b~combout\)) # (!GLOBAL(\u8|Equal11~0clkctrl_outclk\) & ((\u10|bus_to_b~1_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010101011110000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|bus_to_b~combout\,
datac => \u10|bus_to_b~1_combout\,
datad => \u8|Equal11~0clkctrl_outclk\,
combout => \u10|bus_to_b~combout\);
-- Location: LCCOMB_X18_Y20_N22
\u6|temp_b~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_b~4_combout\ = (\u10|acc_xchg~combout\ & (\u6|temp_a\(3))) # (!\u10|acc_xchg~combout\ & (((\u10|bus_to_b~combout\ & \u5|dr_out[3]~28_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1011100010001000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_a\(3),
datab => \u10|acc_xchg~combout\,
datac => \u10|bus_to_b~combout\,
datad => \u5|dr_out[3]~28_combout\,
combout => \u6|temp_b~4_combout\);
-- Location: FF_X18_Y20_N23
\u6|temp_b[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_b~4_combout\,
ena => \u6|temp_b[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_b\(3));
-- Location: LCCOMB_X17_Y20_N0
\u6|temp_a~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_a~4_combout\ = (\u10|acc_xchg~combout\ & (\u6|temp_b\(3))) # (!\u10|acc_xchg~combout\ & (((\u10|bus_to_a~combout\ & \u5|dr_out[3]~28_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1101100010001000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|acc_xchg~combout\,
datab => \u6|temp_b\(3),
datac => \u10|bus_to_a~combout\,
datad => \u5|dr_out[3]~28_combout\,
combout => \u6|temp_a~4_combout\);
-- Location: FF_X17_Y20_N1
\u6|temp_a[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_a~4_combout\,
ena => \u6|temp_a[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_a\(3));
-- Location: LCCOMB_X18_Y19_N8
\u6|acc_out[3]~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|acc_out[3]~3_combout\ = (\u10|a_to_bus~combout\ & (\u6|temp_a\(3))) # (!\u10|a_to_bus~combout\ & (((\u6|temp_b\(3)) # (!\u10|b_to_bus~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010110010101111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_a\(3),
datab => \u6|temp_b\(3),
datac => \u10|a_to_bus~combout\,
datad => \u10|b_to_bus~combout\,
combout => \u6|acc_out[3]~3_combout\);
-- Location: LCCOMB_X18_Y19_N0
\u5|dr_out[3]~28\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[3]~28_combout\ = ((\u6|acc_out[3]~3_combout\ & \u5|dr_out[3]~15_combout\)) # (!\u5|dr_out[0]~10_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111001100110011",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u5|dr_out[0]~10_combout\,
datac => \u6|acc_out[3]~3_combout\,
datad => \u5|dr_out[3]~15_combout\,
combout => \u5|dr_out[3]~28_combout\);
-- Location: LCCOMB_X17_Y20_N22
\u7|temp~15\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~15_combout\ = (\u7|temp[6]~8_combout\ & (((!\u7|temp~7_combout\)))) # (!\u7|temp[6]~8_combout\ & ((\u7|temp~7_combout\ & (\u7|temp\(4))) # (!\u7|temp~7_combout\ & ((\u5|dr_out[5]~30_combout\)))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0100010011111010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp[6]~8_combout\,
datab => \u7|temp\(4),
datac => \u5|dr_out[5]~30_combout\,
datad => \u7|temp~7_combout\,
combout => \u7|temp~15_combout\);
-- Location: LCCOMB_X17_Y20_N28
\u7|temp~16\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~16_combout\ = (\u7|temp[6]~8_combout\ & ((\u7|temp~15_combout\ & (\u5|dr_out[3]~28_combout\)) # (!\u7|temp~15_combout\ & ((\u7|Add0~15_combout\))))) # (!\u7|temp[6]~8_combout\ & (((\u7|temp~15_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1101101011010000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp[6]~8_combout\,
datab => \u5|dr_out[3]~28_combout\,
datac => \u7|temp~15_combout\,
datad => \u7|Add0~15_combout\,
combout => \u7|temp~16_combout\);
-- Location: FF_X17_Y20_N29
\u7|temp[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u7|temp~16_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u7|temp\(4));
-- Location: LCCOMB_X18_Y19_N24
\u5|dr_out[4]~17\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[4]~17_combout\ = (\u7|temp\(4) & ((\u4|mem_rtl_0|auto_generated|ram_block1a4\) # ((!\u10|dr_to_bus~combout\)))) # (!\u7|temp\(4) & (!\u10|alu_out~combout\ & ((\u4|mem_rtl_0|auto_generated|ram_block1a4\) # (!\u10|dr_to_bus~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1000101011001111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp\(4),
datab => \u4|mem_rtl_0|auto_generated|ram_block1a4\,
datac => \u10|dr_to_bus~combout\,
datad => \u10|alu_out~combout\,
combout => \u5|dr_out[4]~17_combout\);
-- Location: LCCOMB_X18_Y19_N12
\u5|dr_out[4]~29\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[4]~29_combout\ = ((\u6|acc_out[4]~4_combout\ & \u5|dr_out[4]~17_combout\)) # (!\u5|dr_out[0]~10_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1000111110001111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|acc_out[4]~4_combout\,
datab => \u5|dr_out[4]~17_combout\,
datac => \u5|dr_out[0]~10_combout\,
combout => \u5|dr_out[4]~29_combout\);
-- Location: LCCOMB_X17_Y20_N18
\u6|temp_a~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_a~5_combout\ = (\u10|acc_xchg~combout\ & (\u6|temp_b\(4))) # (!\u10|acc_xchg~combout\ & (((\u10|bus_to_a~combout\ & \u5|dr_out[4]~29_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1101100010001000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|acc_xchg~combout\,
datab => \u6|temp_b\(4),
datac => \u10|bus_to_a~combout\,
datad => \u5|dr_out[4]~29_combout\,
combout => \u6|temp_a~5_combout\);
-- Location: FF_X17_Y20_N19
\u6|temp_a[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_a~5_combout\,
ena => \u6|temp_a[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_a\(4));
-- Location: LCCOMB_X18_Y20_N8
\u6|temp_b~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_b~5_combout\ = (\u10|acc_xchg~combout\ & (\u6|temp_a\(4))) # (!\u10|acc_xchg~combout\ & (((\u10|bus_to_b~combout\ & \u5|dr_out[4]~29_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1011100010001000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_a\(4),
datab => \u10|acc_xchg~combout\,
datac => \u10|bus_to_b~combout\,
datad => \u5|dr_out[4]~29_combout\,
combout => \u6|temp_b~5_combout\);
-- Location: FF_X18_Y20_N9
\u6|temp_b[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_b~5_combout\,
ena => \u6|temp_b[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_b\(4));
-- Location: LCCOMB_X19_Y19_N2
\u6|acc_out[4]~4\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|acc_out[4]~4_combout\ = (\u10|a_to_bus~combout\ & (((\u6|temp_a\(4))))) # (!\u10|a_to_bus~combout\ & ((\u6|temp_b\(4)) # ((!\u10|b_to_bus~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100110010101111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_b\(4),
datab => \u6|temp_a\(4),
datac => \u10|b_to_bus~combout\,
datad => \u10|a_to_bus~combout\,
combout => \u6|acc_out[4]~4_combout\);
-- Location: LCCOMB_X18_Y18_N26
\u8|tmp~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|tmp~2_combout\ = (!\reset~0_combout\ & (((\u6|acc_out[4]~4_combout\ & \u5|dr_out[4]~17_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000110100000101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u5|dr_out[0]~10_combout\,
datab => \u6|acc_out[4]~4_combout\,
datac => \reset~0_combout\,
datad => \u5|dr_out[4]~17_combout\,
combout => \u8|tmp~2_combout\);
-- Location: FF_X18_Y18_N27
\u8|tmp[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~input_o\,
d => \u8|tmp~2_combout\,
ena => \u8|tmp[1]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u8|tmp\(4));
-- Location: LCCOMB_X18_Y18_N10
\u8|Equal0~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|Equal0~0_combout\ = (!\u8|tmp\(4) & (!\u8|tmp\(6) & (!\u8|tmp\(5) & !\u8|tmp\(7))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000000000000001",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|tmp\(4),
datab => \u8|tmp\(6),
datac => \u8|tmp\(5),
datad => \u8|tmp\(7),
combout => \u8|Equal0~0_combout\);
-- Location: LCCOMB_X19_Y18_N28
\u8|Equal7~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|Equal7~0_combout\ = (!\u8|tmp\(0) & (!\u8|tmp\(2) & (\u8|tmp\(3) & \u8|Equal0~0_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0001000000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|tmp\(0),
datab => \u8|tmp\(2),
datac => \u8|tmp\(3),
datad => \u8|Equal0~0_combout\,
combout => \u8|Equal7~0_combout\);
-- Location: LCCOMB_X19_Y20_N22
\u10|alu_shr~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|alu_shr~0_combout\ = (\u9|temp\(3) & ((\u8|tmp\(1) & ((\u8|Equal4~0_combout\))) # (!\u8|tmp\(1) & (\u8|Equal7~0_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1110001000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|Equal7~0_combout\,
datab => \u8|tmp\(1),
datac => \u8|Equal4~0_combout\,
datad => \u9|temp\(3),
combout => \u10|alu_shr~0_combout\);
-- Location: LCCOMB_X19_Y20_N28
\u10|alu_shr\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|alu_shr~combout\ = (GLOBAL(\u8|Equal11~0clkctrl_outclk\) & (\u10|alu_shr~combout\)) # (!GLOBAL(\u8|Equal11~0clkctrl_outclk\) & ((\u10|alu_shr~0_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100110011110000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u10|alu_shr~combout\,
datac => \u10|alu_shr~0_combout\,
datad => \u8|Equal11~0clkctrl_outclk\,
combout => \u10|alu_shr~combout\);
-- Location: LCCOMB_X17_Y20_N20
\u7|temp~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~7_combout\ = (!\u10|alu_shr~combout\ & !\u10|alu_shl~combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000000000001111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datac => \u10|alu_shr~combout\,
datad => \u10|alu_shl~combout\,
combout => \u7|temp~7_combout\);
-- Location: LCCOMB_X18_Y20_N20
\u5|dr_out[0]~25\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[0]~25_combout\ = ((\u6|acc_out[0]~0_combout\ & \u5|dr_out[0]~8_combout\)) # (!\u5|dr_out[0]~10_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111001100110011",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u5|dr_out[0]~10_combout\,
datac => \u6|acc_out[0]~0_combout\,
datad => \u5|dr_out[0]~8_combout\,
combout => \u5|dr_out[0]~25_combout\);
-- Location: LCCOMB_X17_Y19_N28
\u7|temp~9\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~9_combout\ = (\u7|temp[6]~8_combout\ & (((\u7|Add0~6_combout\) # (!\u7|temp~7_combout\)))) # (!\u7|temp[6]~8_combout\ & (\u7|temp\(1) & ((\u7|temp~7_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1110010010101010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp[6]~8_combout\,
datab => \u7|temp\(1),
datac => \u7|Add0~6_combout\,
datad => \u7|temp~7_combout\,
combout => \u7|temp~9_combout\);
-- Location: LCCOMB_X17_Y19_N8
\u7|temp~10\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~10_combout\ = (\u7|temp~7_combout\ & (((\u7|temp~9_combout\)))) # (!\u7|temp~7_combout\ & ((\u7|temp~9_combout\ & ((\u5|dr_out[0]~25_combout\))) # (!\u7|temp~9_combout\ & (\u5|dr_out[2]~27_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111101001000100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp~7_combout\,
datab => \u5|dr_out[2]~27_combout\,
datac => \u5|dr_out[0]~25_combout\,
datad => \u7|temp~9_combout\,
combout => \u7|temp~10_combout\);
-- Location: FF_X17_Y19_N9
\u7|temp[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u7|temp~10_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u7|temp\(1));
-- Location: LCCOMB_X18_Y19_N16
\u5|dr_out[1]~11\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[1]~11_combout\ = (\u7|temp\(1) & (((\u4|mem_rtl_0|auto_generated|ram_block1a1\)) # (!\u10|dr_to_bus~combout\))) # (!\u7|temp\(1) & (!\u10|alu_out~combout\ & ((\u4|mem_rtl_0|auto_generated|ram_block1a1\) # (!\u10|dr_to_bus~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010001011110011",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u7|temp\(1),
datab => \u10|dr_to_bus~combout\,
datac => \u4|mem_rtl_0|auto_generated|ram_block1a1\,
datad => \u10|alu_out~combout\,
combout => \u5|dr_out[1]~11_combout\);
-- Location: LCCOMB_X18_Y18_N16
\u8|tmp~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|tmp~6_combout\ = (!\reset~0_combout\ & (((\u5|dr_out[1]~11_combout\ & \u6|acc_out[1]~1_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0100010100000101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \reset~0_combout\,
datab => \u5|dr_out[1]~11_combout\,
datac => \u5|dr_out[0]~10_combout\,
datad => \u6|acc_out[1]~1_combout\,
combout => \u8|tmp~6_combout\);
-- Location: FF_X18_Y18_N17
\u8|tmp[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~input_o\,
d => \u8|tmp~6_combout\,
ena => \u8|tmp[1]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u8|tmp\(1));
-- Location: LCCOMB_X19_Y18_N14
\u10|bus_to_a~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|bus_to_a~1_combout\ = (\u8|tmp\(1) & (((\u8|Equal4~0_combout\) # (\u8|Equal0~1_combout\)))) # (!\u8|tmp\(1) & (\u8|Equal8~0_combout\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1110111011100010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|Equal8~0_combout\,
datab => \u8|tmp\(1),
datac => \u8|Equal4~0_combout\,
datad => \u8|Equal0~1_combout\,
combout => \u10|bus_to_a~1_combout\);
-- Location: LCCOMB_X18_Y18_N30
\u10|bus_to_a~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|bus_to_a~0_combout\ = (\u8|Equal0~1_combout\ & (\u9|temp\(3) & !\u8|tmp\(1)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000000010100000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|Equal0~1_combout\,
datac => \u9|temp\(3),
datad => \u8|tmp\(1),
combout => \u10|bus_to_a~0_combout\);
-- Location: LCCOMB_X19_Y18_N24
\u10|bus_to_a~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|bus_to_a~2_combout\ = (\u10|alu_out~0_combout\) # ((\u10|bus_to_a~0_combout\) # ((\u10|bus_to_a~1_combout\ & \u9|temp\(4))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111111111101100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|bus_to_a~1_combout\,
datab => \u10|alu_out~0_combout\,
datac => \u9|temp\(4),
datad => \u10|bus_to_a~0_combout\,
combout => \u10|bus_to_a~2_combout\);
-- Location: LCCOMB_X19_Y18_N30
\u10|bus_to_a\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|bus_to_a~combout\ = (GLOBAL(\u8|Equal11~0clkctrl_outclk\) & ((\u10|bus_to_a~combout\))) # (!GLOBAL(\u8|Equal11~0clkctrl_outclk\) & (\u10|bus_to_a~2_combout\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111000010101010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|bus_to_a~2_combout\,
datac => \u10|bus_to_a~combout\,
datad => \u8|Equal11~0clkctrl_outclk\,
combout => \u10|bus_to_a~combout\);
-- Location: LCCOMB_X17_Y20_N30
\u6|temp_a~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_a~3_combout\ = (\u10|acc_xchg~combout\ & (\u6|temp_b\(2))) # (!\u10|acc_xchg~combout\ & (((\u10|bus_to_a~combout\ & \u5|dr_out[2]~27_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1101100010001000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|acc_xchg~combout\,
datab => \u6|temp_b\(2),
datac => \u10|bus_to_a~combout\,
datad => \u5|dr_out[2]~27_combout\,
combout => \u6|temp_a~3_combout\);
-- Location: FF_X17_Y20_N31
\u6|temp_a[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_a~3_combout\,
ena => \u6|temp_a[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_a\(2));
-- Location: LCCOMB_X18_Y20_N24
\u6|temp_b~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_b~3_combout\ = (\u10|acc_xchg~combout\ & (\u6|temp_a\(2))) # (!\u10|acc_xchg~combout\ & (((\u10|bus_to_b~combout\ & \u5|dr_out[2]~27_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1011100010001000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_a\(2),
datab => \u10|acc_xchg~combout\,
datac => \u10|bus_to_b~combout\,
datad => \u5|dr_out[2]~27_combout\,
combout => \u6|temp_b~3_combout\);
-- Location: FF_X18_Y20_N25
\u6|temp_b[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_b~3_combout\,
ena => \u6|temp_b[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_b\(2));
-- Location: LCCOMB_X19_Y19_N30
\u6|acc_out[2]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|acc_out[2]~2_combout\ = (\u10|a_to_bus~combout\ & (((\u6|temp_a\(2))))) # (!\u10|a_to_bus~combout\ & ((\u6|temp_b\(2)) # ((!\u10|b_to_bus~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100110010101111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_b\(2),
datab => \u6|temp_a\(2),
datac => \u10|b_to_bus~combout\,
datad => \u10|a_to_bus~combout\,
combout => \u6|acc_out[2]~2_combout\);
-- Location: LCCOMB_X19_Y18_N2
\u8|tmp~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|tmp~5_combout\ = (!\reset~0_combout\ & (((\u6|acc_out[2]~2_combout\ & \u5|dr_out[2]~13_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0010000000110011",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|acc_out[2]~2_combout\,
datab => \reset~0_combout\,
datac => \u5|dr_out[2]~13_combout\,
datad => \u5|dr_out[0]~10_combout\,
combout => \u8|tmp~5_combout\);
-- Location: FF_X19_Y18_N3
\u8|tmp[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~input_o\,
d => \u8|tmp~5_combout\,
ena => \u8|tmp[1]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u8|tmp\(2));
-- Location: LCCOMB_X18_Y18_N8
\u8|Equal0~1\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|Equal0~1_combout\ = (!\u8|tmp\(3) & (!\u8|tmp\(2) & (\u8|tmp\(0) & \u8|Equal0~0_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0001000000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|tmp\(3),
datab => \u8|tmp\(2),
datac => \u8|tmp\(0),
datad => \u8|Equal0~0_combout\,
combout => \u8|Equal0~1_combout\);
-- Location: LCCOMB_X19_Y18_N12
\u10|b_to_bus~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|b_to_bus~0_combout\ = (\u9|temp\(3) & ((\u8|Equal7~0_combout\) # ((\u8|Equal0~1_combout\ & !\u8|tmp\(1)))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100000011100000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|Equal0~1_combout\,
datab => \u8|Equal7~0_combout\,
datac => \u9|temp\(3),
datad => \u8|tmp\(1),
combout => \u10|b_to_bus~0_combout\);
-- Location: LCCOMB_X19_Y19_N26
\u10|b_to_bus\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|b_to_bus~combout\ = (GLOBAL(\u8|Equal11~0clkctrl_outclk\) & ((\u10|b_to_bus~combout\))) # (!GLOBAL(\u8|Equal11~0clkctrl_outclk\) & (\u10|b_to_bus~0_combout\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111000011001100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u10|b_to_bus~0_combout\,
datac => \u10|b_to_bus~combout\,
datad => \u8|Equal11~0clkctrl_outclk\,
combout => \u10|b_to_bus~combout\);
-- Location: LCCOMB_X19_Y19_N8
\u5|dr_out[0]~10\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[0]~10_combout\ = (\u10|b_to_bus~combout\) # ((\u10|a_to_bus~combout\) # ((\u10|dr_to_bus~combout\) # (\u10|alu_out~combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111111111111110",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|b_to_bus~combout\,
datab => \u10|a_to_bus~combout\,
datac => \u10|dr_to_bus~combout\,
datad => \u10|alu_out~combout\,
combout => \u5|dr_out[0]~10_combout\);
-- Location: LCCOMB_X18_Y19_N30
\u8|tmp~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|tmp~0_combout\ = (!\reset~0_combout\ & (((\u6|acc_out[3]~3_combout\ & \u5|dr_out[3]~15_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000000011010101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u5|dr_out[0]~10_combout\,
datab => \u6|acc_out[3]~3_combout\,
datac => \u5|dr_out[3]~15_combout\,
datad => \reset~0_combout\,
combout => \u8|tmp~0_combout\);
-- Location: FF_X18_Y19_N31
\u8|tmp[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~input_o\,
d => \u8|tmp~0_combout\,
ena => \u8|tmp[1]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u8|tmp\(3));
-- Location: LCCOMB_X17_Y18_N0
\u8|Equal11~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|Equal11~0_combout\ = (\u8|tmp\(3) & \u8|Equal3~1_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100110000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u8|tmp\(3),
datad => \u8|Equal3~1_combout\,
combout => \u8|Equal11~0_combout\);
-- Location: CLKCTRL_G7
\u8|Equal11~0clkctrl\ : cycloneive_clkctrl
-- pragma translate_off
GENERIC MAP (
clock_type => "global clock",
ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
inclk => \u8|Equal11~0clkctrl_INCLK_bus\,
devclrn => ww_devclrn,
devpor => ww_devpor,
outclk => \u8|Equal11~0clkctrl_outclk\);
-- Location: LCCOMB_X19_Y18_N22
\u10|dr_to_bus~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|dr_to_bus~2_combout\ = (\u9|temp\(4) & (((\u8|Equal4~0_combout\ & !\u8|tmp\(1))) # (!\u10|dr_to_bus~1_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0011000010110000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|Equal4~0_combout\,
datab => \u10|dr_to_bus~1_combout\,
datac => \u9|temp\(4),
datad => \u8|tmp\(1),
combout => \u10|dr_to_bus~2_combout\);
-- Location: LCCOMB_X19_Y19_N20
\u10|dr_to_bus~3\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|dr_to_bus~3_combout\ = (\u9|temp\(1)) # ((\u10|dr_to_bus~2_combout\) # ((\u9|temp\(4) & \u8|Equal5~1_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111111011111010",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u9|temp\(1),
datab => \u9|temp\(4),
datac => \u10|dr_to_bus~2_combout\,
datad => \u8|Equal5~1_combout\,
combout => \u10|dr_to_bus~3_combout\);
-- Location: LCCOMB_X19_Y19_N22
\u10|dr_to_bus\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|dr_to_bus~combout\ = (GLOBAL(\u8|Equal11~0clkctrl_outclk\) & (\u10|dr_to_bus~combout\)) # (!GLOBAL(\u8|Equal11~0clkctrl_outclk\) & ((\u10|dr_to_bus~3_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010111110100000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|dr_to_bus~combout\,
datac => \u8|Equal11~0clkctrl_outclk\,
datad => \u10|dr_to_bus~3_combout\,
combout => \u10|dr_to_bus~combout\);
-- Location: LCCOMB_X16_Y19_N6
\u7|temp~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~5_combout\ = (!\u10|alu_shr~combout\ & ((\u7|temp~4_combout\ & ((\u7|Add0~3_combout\))) # (!\u7|temp~4_combout\ & (\u7|temp\(0)))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0101000001000100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|alu_shr~combout\,
datab => \u7|temp\(0),
datac => \u7|Add0~3_combout\,
datad => \u7|temp~4_combout\,
combout => \u7|temp~5_combout\);
-- Location: LCCOMB_X16_Y19_N28
\u7|temp~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \u7|temp~6_combout\ = (!\u10|alu_shl~combout\ & ((\u7|temp~5_combout\) # ((\u10|alu_shr~combout\ & \u5|dr_out[1]~26_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0011001100100000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|alu_shr~combout\,
datab => \u10|alu_shl~combout\,
datac => \u5|dr_out[1]~26_combout\,
datad => \u7|temp~5_combout\,
combout => \u7|temp~6_combout\);
-- Location: FF_X16_Y19_N29
\u7|temp[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u7|temp~6_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u7|temp\(0));
-- Location: LCCOMB_X19_Y19_N18
\u5|dr_out[0]~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[0]~8_combout\ = (\u10|dr_to_bus~combout\ & (\u4|mem_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ((\u7|temp\(0)) # (!\u10|alu_out~combout\)))) # (!\u10|dr_to_bus~combout\ & ((\u7|temp\(0)) # ((!\u10|alu_out~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100010011110101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u10|dr_to_bus~combout\,
datab => \u7|temp\(0),
datac => \u4|mem_rtl_0|auto_generated|ram_block1a0~portbdataout\,
datad => \u10|alu_out~combout\,
combout => \u5|dr_out[0]~8_combout\);
-- Location: LCCOMB_X18_Y18_N18
\u8|tmp~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|tmp~7_combout\ = (!\reset~0_combout\ & (((\u5|dr_out[0]~8_combout\ & \u6|acc_out[0]~0_combout\)) # (!\u5|dr_out[0]~10_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0100010100000101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \reset~0_combout\,
datab => \u5|dr_out[0]~8_combout\,
datac => \u5|dr_out[0]~10_combout\,
datad => \u6|acc_out[0]~0_combout\,
combout => \u8|tmp~7_combout\);
-- Location: FF_X18_Y18_N19
\u8|tmp[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u8|tmp~7_combout\,
ena => \u8|tmp[1]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u8|tmp\(0));
-- Location: LCCOMB_X19_Y18_N20
\u8|Equal8~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u8|Equal8~0_combout\ = (\u8|tmp\(0) & (!\u8|tmp\(2) & (\u8|tmp\(3) & \u8|Equal0~0_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0010000000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u8|tmp\(0),
datab => \u8|tmp\(2),
datac => \u8|tmp\(3),
datad => \u8|Equal0~0_combout\,
combout => \u8|Equal8~0_combout\);
-- Location: LCCOMB_X19_Y20_N24
\u10|acc_xchg~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|acc_xchg~0_combout\ = (\u8|Equal8~0_combout\ & (\u8|tmp\(1) & \u9|temp\(3)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100000000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u8|Equal8~0_combout\,
datac => \u8|tmp\(1),
datad => \u9|temp\(3),
combout => \u10|acc_xchg~0_combout\);
-- Location: LCCOMB_X19_Y20_N16
\u10|acc_xchg\ : cycloneive_lcell_comb
-- Equation(s):
-- \u10|acc_xchg~combout\ = (GLOBAL(\u8|Equal11~0clkctrl_outclk\) & (\u10|acc_xchg~combout\)) # (!GLOBAL(\u8|Equal11~0clkctrl_outclk\) & ((\u10|acc_xchg~0_combout\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100110011110000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u10|acc_xchg~combout\,
datac => \u10|acc_xchg~0_combout\,
datad => \u8|Equal11~0clkctrl_outclk\,
combout => \u10|acc_xchg~combout\);
-- Location: LCCOMB_X18_Y20_N16
\u6|temp_b~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_b~0_combout\ = (\u10|acc_xchg~combout\ & (\u6|temp_a\(0))) # (!\u10|acc_xchg~combout\ & (((\u10|bus_to_b~combout\ & \u5|dr_out[0]~25_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1011100010001000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_a\(0),
datab => \u10|acc_xchg~combout\,
datac => \u10|bus_to_b~combout\,
datad => \u5|dr_out[0]~25_combout\,
combout => \u6|temp_b~0_combout\);
-- Location: FF_X18_Y20_N17
\u6|temp_b[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_b~0_combout\,
ena => \u6|temp_b[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_b\(0));
-- Location: LCCOMB_X17_Y20_N12
\u6|temp_a~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|temp_a~0_combout\ = (\u10|acc_xchg~combout\ & (\u6|temp_b\(0))) # (!\u10|acc_xchg~combout\ & (((\u10|bus_to_a~combout\ & \u5|dr_out[0]~25_combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010101011000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_b\(0),
datab => \u10|bus_to_a~combout\,
datac => \u5|dr_out[0]~25_combout\,
datad => \u10|acc_xchg~combout\,
combout => \u6|temp_a~0_combout\);
-- Location: FF_X17_Y20_N13
\u6|temp_a[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
is_wysiwyg => "true",
power_up => "low")
-- pragma translate_on
PORT MAP (
clk => \clk~inputclkctrl_outclk\,
d => \u6|temp_a~0_combout\,
ena => \u6|temp_a[0]~1_combout\,
devclrn => ww_devclrn,
devpor => ww_devpor,
q => \u6|temp_a\(0));
-- Location: LCCOMB_X19_Y19_N24
\u6|acc_out[0]~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \u6|acc_out[0]~0_combout\ = (\u10|a_to_bus~combout\ & (\u6|temp_a\(0))) # (!\u10|a_to_bus~combout\ & (((\u6|temp_b\(0)) # (!\u10|b_to_bus~combout\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010101011001111",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|temp_a\(0),
datab => \u6|temp_b\(0),
datac => \u10|b_to_bus~combout\,
datad => \u10|a_to_bus~combout\,
combout => \u6|acc_out[0]~0_combout\);
-- Location: LCCOMB_X16_Y20_N4
\u5|dr_out[0]~9\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[0]~9_combout\ = (\u6|acc_out[0]~0_combout\ & \u5|dr_out[0]~8_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111000000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datac => \u6|acc_out[0]~0_combout\,
datad => \u5|dr_out[0]~8_combout\,
combout => \u5|dr_out[0]~9_combout\);
-- Location: LCCOMB_X18_Y19_N4
\u5|dr_out[1]~12\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[1]~12_combout\ = (\u5|dr_out[1]~11_combout\ & \u6|acc_out[1]~1_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111000000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datac => \u5|dr_out[1]~11_combout\,
datad => \u6|acc_out[1]~1_combout\,
combout => \u5|dr_out[1]~12_combout\);
-- Location: LCCOMB_X18_Y19_N14
\u5|dr_out[2]~14\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[2]~14_combout\ = (\u5|dr_out[2]~13_combout\ & \u6|acc_out[2]~2_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100110000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u5|dr_out[2]~13_combout\,
datad => \u6|acc_out[2]~2_combout\,
combout => \u5|dr_out[2]~14_combout\);
-- Location: LCCOMB_X18_Y19_N28
\u5|dr_out[3]~16\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[3]~16_combout\ = (\u6|acc_out[3]~3_combout\ & \u5|dr_out[3]~15_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100000011000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u6|acc_out[3]~3_combout\,
datac => \u5|dr_out[3]~15_combout\,
combout => \u5|dr_out[3]~16_combout\);
-- Location: LCCOMB_X18_Y19_N26
\u5|dr_out[4]~18\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[4]~18_combout\ = (\u6|acc_out[4]~4_combout\ & \u5|dr_out[4]~17_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010101000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \u6|acc_out[4]~4_combout\,
datad => \u5|dr_out[4]~17_combout\,
combout => \u5|dr_out[4]~18_combout\);
-- Location: LCCOMB_X18_Y21_N0
\u5|dr_out[5]~20\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[5]~20_combout\ = (\u5|dr_out[5]~19_combout\ & \u6|acc_out[5]~5_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100000011000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u5|dr_out[5]~19_combout\,
datac => \u6|acc_out[5]~5_combout\,
combout => \u5|dr_out[5]~20_combout\);
-- Location: LCCOMB_X16_Y19_N22
\u5|dr_out[6]~22\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[6]~22_combout\ = (\u5|dr_out[6]~21_combout\ & \u6|acc_out[6]~6_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100110000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u5|dr_out[6]~21_combout\,
datad => \u6|acc_out[6]~6_combout\,
combout => \u5|dr_out[6]~22_combout\);
-- Location: LCCOMB_X18_Y21_N6
\u5|dr_out[7]~24\ : cycloneive_lcell_comb
-- Equation(s):
-- \u5|dr_out[7]~24_combout\ = (\u5|dr_out[7]~23_combout\ & \u6|acc_out[7]~7_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100110000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \u5|dr_out[7]~23_combout\,
datad => \u6|acc_out[7]~7_combout\,
combout => \u5|dr_out[7]~24_combout\);
ww_test_bus(0) <= \test_bus[0]~output_o\;
ww_test_bus(1) <= \test_bus[1]~output_o\;
ww_test_bus(2) <= \test_bus[2]~output_o\;
ww_test_bus(3) <= \test_bus[3]~output_o\;
ww_test_bus(4) <= \test_bus[4]~output_o\;
ww_test_bus(5) <= \test_bus[5]~output_o\;
ww_test_bus(6) <= \test_bus[6]~output_o\;
ww_test_bus(7) <= \test_bus[7]~output_o\;
ww_test <= \test~output_o\;
ww_ax(0) <= \ax[0]~output_o\;
ww_ax(1) <= \ax[1]~output_o\;
ww_ax(2) <= \ax[2]~output_o\;
ww_ax(3) <= \ax[3]~output_o\;
ww_ax(4) <= \ax[4]~output_o\;
ww_ax(5) <= \ax[5]~output_o\;
ww_ax(6) <= \ax[6]~output_o\;
ww_ax(7) <= \ax[7]~output_o\;
ww_bx(0) <= \bx[0]~output_o\;
ww_bx(1) <= \bx[1]~output_o\;
ww_bx(2) <= \bx[2]~output_o\;
ww_bx(3) <= \bx[3]~output_o\;
ww_bx(4) <= \bx[4]~output_o\;
ww_bx(5) <= \bx[5]~output_o\;
ww_bx(6) <= \bx[6]~output_o\;
ww_bx(7) <= \bx[7]~output_o\;
END structure;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: <NAME>
--
-- Entity: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2017 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library altera_mf;
use altera_mf.Altera_MF_Components.all;
library PoC;
use PoC.physical.all;
use PoC.components.all;
entity clknet_ClockNetwork_DE4 is
GENERIC (
DEBUG : BOOLEAN := FALSE;
CLOCK_IN_FREQ : FREQ := 100 MHz
);
port (
ClockIn_100MHz : in STD_LOGIC;
ClockNetwork_Reset : in STD_LOGIC;
ClockNetwork_ResetDone : out STD_LOGIC;
Control_Clock_100MHz : out STD_LOGIC;
Clock_250MHz : out STD_LOGIC;
Clock_200MHz : out STD_LOGIC;
Clock_125MHz : out STD_LOGIC;
Clock_100MHz : out STD_LOGIC;
Clock_10MHz : out STD_LOGIC;
Clock_Stable_250MHz : out STD_LOGIC;
Clock_Stable_200MHz : out STD_LOGIC;
Clock_Stable_125MHz : out STD_LOGIC;
Clock_Stable_100MHz : out STD_LOGIC;
Clock_Stable_10MHz : out STD_LOGIC
);
end entity;
architecture rtl of clknet_ClockNetwork_DE4 is
attribute PRESERVE : BOOLEAN;
-- component altpll
-- generic (
-- bandwidth_type : STRING;
-- clk0_divide_by : NATURAL;
-- clk0_duty_cycle : NATURAL;
-- clk0_multiply_by : NATURAL;
-- clk0_phase_shift : STRING;
-- inclk0_input_frequency : NATURAL;
-- intended_device_family : STRING;
-- lpm_hint : STRING;
-- lpm_type : STRING;
-- operation_mode : STRING;
-- pll_type : STRING;
-- port_activeclock : STRING;
-- port_areset : STRING;
-- port_clkbad0 : STRING;
-- port_clkbad1 : STRING;
-- port_clkloss : STRING;
-- port_clkswitch : STRING;
-- port_configupdate : STRING;
-- port_fbin : STRING;
-- port_fbout : STRING;
-- port_inclk0 : STRING;
-- port_inclk1 : STRING;
-- port_locked : STRING;
-- port_pfdena : STRING;
-- port_phasecounterselect : STRING;
-- port_phasedone : STRING;
-- port_phasestep : STRING;
-- port_phaseupdown : STRING;
-- port_pllena : STRING;
-- port_scanaclr : STRING;
-- port_scanclk : STRING;
-- port_scanclkena : STRING;
-- port_scandata : STRING;
-- port_scandataout : STRING;
-- port_scandone : STRING;
-- port_scanread : STRING;
-- port_scanwrite : STRING;
-- port_clk0 : STRING;
-- port_clk1 : STRING;
-- port_clk2 : STRING;
-- port_clk3 : STRING;
-- port_clk4 : STRING;
-- port_clk5 : STRING;
-- port_clk6 : STRING;
-- port_clk7 : STRING;
-- port_clk8 : STRING;
-- port_clk9 : STRING;
-- port_clkena0 : STRING;
-- port_clkena1 : STRING;
-- port_clkena2 : STRING;
-- port_clkena3 : STRING;
-- port_clkena4 : STRING;
-- port_clkena5 : STRING;
-- using_fbmimicbidir_port : STRING;
-- width_clock : NATURAL
-- );
-- port (
-- clk : out STD_LOGIC_VECTOR (9 downto 0);
-- inclk : in STD_LOGIC_VECTOR (1 downto 0)
-- );
-- end component;
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
-- control clock: 100 MHz
-- slowest output clock: 10 MHz
-- worst case delay: (Control_Clock freq / slowest clock in MHz) * register stages + safety
-- => 44 (100 MHz / 10 MHz) * 2 register stages + 4
constant CMB_DELAY_CYCLES : POSITIVE := integer(real(CLOCK_IN_FREQ / 10 MHz) * 2.0 + 4.0);
signal ClkNet_Reset : STD_LOGIC;
signal PLL_Reset : STD_LOGIC;
signal PLL_Reset_clr : STD_LOGIC;
signal PLL_ResetState : STD_LOGIC := '0';
signal PLL_Reset_delayed : STD_LOGIC_VECTOR(CMB_DELAY_CYCLES - 1 downto 0);
signal PLL_Locked_async : STD_LOGIC;
signal PLL_Locked : STD_LOGIC;
signal PLL_Locked_d : STD_LOGIC := '0';
signal PLL_Locked_re : STD_LOGIC;
signal PLL_LockedState : STD_LOGIC := '0';
signal Locked : STD_LOGIC;
signal Reset : STD_LOGIC;
signal Control_Clock : STD_LOGIC;
signal PLL_Clock_250MHz : STD_LOGIC;
signal PLL_Clock_200MHz : STD_LOGIC;
signal PLL_Clock_125MHz : STD_LOGIC;
signal PLL_Clock_100MHz : STD_LOGIC;
signal PLL_Clock_10MHz : STD_LOGIC;
attribute PRESERVE of PLL_Clock_10MHz : signal is DEBUG;
attribute PRESERVE of PLL_Clock_100MHz : signal is DEBUG;
attribute PRESERVE of PLL_Clock_125MHz : signal is DEBUG;
attribute PRESERVE of PLL_Clock_200MHz : signal is DEBUG;
attribute PRESERVE of PLL_Clock_250MHz : signal is DEBUG;
begin
-- ==================================================================
-- ResetControl
-- ==================================================================
-- synchronize external (async) ClockNetwork_Reset and internal (but async) PLL_Locked signals to "Control_Clock" domain
syncControlClock: entity PoC.sync_Bits_Altera
generic map (
BITS => 2 -- number of BITS to synchronize
)
port map (
Clock => Control_Clock, -- Clock to be synchronized to
Input(0) => ClockNetwork_Reset, -- Data to be synchronized
Input(1) => PLL_Locked_async, --
Output(0) => ClkNet_Reset, -- synchronized data
Output(1) => PLL_Locked --
);
-- clear reset signals, if external Reset is low and CMB (clock modifying block) noticed reset -> locked = low
PLL_Reset_clr <= ClkNet_Reset nor PLL_Locked;
-- detect rising edge on CMB locked signals
PLL_Locked_d <= PLL_Locked when rising_edge(Control_Clock);
PLL_Locked_re <= not PLL_Locked_d and PLL_Locked;
-- RS-FF Q RST SET CLK
-- hold reset until external reset goes low and CMB noticed reset
PLL_ResetState <= ffrs(q => PLL_ResetState, rst => PLL_Reset_clr, set => ClkNet_Reset) when rising_edge(Control_Clock);
-- deassert *_LockedState, if CMBs are going to be reseted; assert it if *_Locked is high again
PLL_LockedState <= ffrs(q => PLL_LockedState, rst => ClkNet_Reset, set => PLL_Locked_re) when rising_edge(Control_Clock);
-- delay CMB resets until the slowed syncBlock has noticed that LockedState is low
PLL_Reset_delayed <= sr_left(PLL_Reset_delayed, PLL_ResetState) when rising_edge(Control_Clock);
PLL_Reset <= PLL_Reset_delayed(PLL_Reset_delayed'high);
Locked <= PLL_LockedState;
ClockNetwork_ResetDone <= Locked;
-- ==================================================================
-- ClockBuffers
-- ==================================================================
-- Control_Clock
Control_Clock <= ClockIn_100MHz;
Control_Clock_100MHz <= Control_Clock;
Clock_250MHz <= PLL_Clock_250MHz;
Clock_200MHz <= PLL_Clock_200MHz;
Clock_125MHz <= PLL_Clock_125MHz;
Clock_100MHz <= PLL_Clock_100MHz;
Clock_10MHz <= PLL_Clock_10MHz;
PLL: entity work.mypll
port map (
AReset => PLL_Reset,
inclk0 => ClockIn_100MHz,
Locked => PLL_Locked_async,
c0 => PLL_Clock_100MHz,
c1 => PLL_Clock_200MHz,
c2 => PLL_Clock_250MHz,
c3 => PLL_Clock_125MHz,
c4 => PLL_Clock_10MHz
);
-- synchronize internal Locked signal to output clock domains
syncLocked250MHz: entity PoC.sync_Bits_Altera
port map (
Clock => PLL_Clock_250MHz, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_250MHz -- synchronized data
);
syncLocked200MHz: entity PoC.sync_Bits_Altera
port map (
Clock => PLL_Clock_200MHz, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_200MHz -- synchronized data
);
syncLocked125MHz: entity PoC.sync_Bits_Altera
port map (
Clock => PLL_Clock_125MHz, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_125MHz -- synchronized data
);
syncLocked100MHz: entity PoC.sync_Bits_Altera
port map (
Clock => PLL_Clock_100MHz, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_100MHz -- synchronized data
);
syncLocked10MHz: entity PoC.sync_Bits_Altera
port map (
Clock => PLL_Clock_10MHz, -- Clock to be synchronized to
Input(0) => Locked, -- Data to be synchronized
Output(0) => Clock_Stable_10MHz -- synchronized data
);
end architecture;
|
-------------------------------------------------------------------------------
-- Title :
-------------------------------------------------------------------------------
-- File : AtlasChess2FebAsicRxMsg.vhd
-- Author : <NAME> <<EMAIL>>
-- Company : SLAC National Accelerator Laboratory
-- Created : 2016-06-01
-- Last update: 2017-01-26
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- This file is part of 'ATLAS CHESS2 DEV'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'ATLAS CHESS2 DEV', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.StdRtlPkg.all;
use work.AxiStreamPkg.all;
use work.SsiPkg.all;
use work.Pgp2bPkg.all;
entity AtlasChess2FebAsicRxMsg is
generic (
TPD_G : time := 1 ns;
COMM_MODE_G : boolean := false;
CASCADE_SIZE_G : positive := 4);
port (
-- CHESS2 Interface
dataValid : in slv(2 downto 0);
multiHit : in slv(2 downto 0);
col : in Slv5Array(2 downto 0);
row : in Slv7Array(2 downto 0);
-- CHESS2 Configuration
debugSendCnt : in sl;
destId : in slv(5 downto 0);
opCode : in slv(7 downto 0);
frameType : in slv(31 downto 0);
wordSize : in slv(7 downto 0);
-- Timing Interface
timingClk320MHz : in sl;
timingRst320MHz : in sl;
timingTrig : in sl;
timingMsg : in slv(63 downto 0);
-- AXI Stream Interface
axisClk : in sl;
axisRst : in sl;
extBusy : out sl;
mAxisMaster : out AxiStreamMasterType;
mAxisSlave : in AxiStreamSlaveType);
end AtlasChess2FebAsicRxMsg;
architecture mapping of AtlasChess2FebAsicRxMsg is
constant AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(16);
type StateType is (
IDLE_S,
HDR_S,
CATCHUP_A_S,
CATCHUP_B_S,
MOVE_S);
type RegType is record
wordSize : slv(7 downto 0);
frame : slv(31 downto 0);
trigCnt : slv(15 downto 0);
tData : Slv64Array(2 downto 0);
timingMsg : slv(31 downto 0);
cnt : slv(7 downto 0);
txMaster : AxiStreamMasterType;
state : StateType;
end record RegType;
constant REG_INIT_C : RegType := (
wordSize => (others => '0'),
frame => (others => '0'),
trigCnt => (others => '0'),
tData => (others => (others => '0')),
timingMsg => (others => '0'),
cnt => (others => '0'),
txMaster => AXI_STREAM_MASTER_INIT_C,
state => IDLE_S);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
signal txCtrl : AxiStreamCtrlType;
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "TRUE";
-- attribute dont_touch of txCtrl : signal is "TRUE";
begin
comb : process (col, dataValid, debugSendCnt, destId, frameType, multiHit,
opCode, r, row, timingMsg, timingRst320MHz, timingTrig,
txCtrl, wordSize) is
variable v : RegType;
variable i : natural;
variable data : slv(63 downto 0);
begin
-- Latch the current value
v := r;
-- Format the data word
data := (others => '0');
for i in 2 downto 0 loop
data(13+(16*i) downto (16*i)) := dataValid(i) & multiHit(i) & col(i) & row(i);
end loop;
if (debugSendCnt = '1') then
data := r.cnt & r.cnt & r.cnt & r.cnt & r.cnt & r.cnt & r.cnt & r.cnt;
end if;
-- Reset the flags
v.txMaster.tValid := '0';
v.txMaster.tLast := '0';
v.txMaster.tUser := (others => '0');
-- Wait for trigger
if (timingTrig = '1') then
-- Increment the counter
v.trigCnt := r.trigCnt + 1;
end if;
-- State Machine
case (r.state) is
----------------------------------------------------------------------
when IDLE_S => -- r.cnt = 0
-- Wait for trigger and ready to move data
if (timingTrig = '1') and (txCtrl.pause = '0') then
-- Send the header
v.txMaster.tValid := '1';
v.txMaster.tKeep := x"FFFF";
-- Increment the counter
v.frame := r.frame + 1;
-- Set SOF bit
ssiSetUserSof(AXIS_CONFIG_C, v.txMaster, '1');
-- Set the hdr[0]
v.txMaster.tData(1 downto 0) := "00"; -- Virtual Channel ID = 0x0
v.txMaster.tData(7 downto 2) := destId; -- Destination ID = lane + Z
v.txMaster.tData(31 downto 8) := r.frame(23 downto 0); -- Transaction ID
-- Set the hdr[1]
v.txMaster.tData(47 downto 32) := r.trigCnt; -- Acquire Counter
v.txMaster.tData(55 downto 48) := opCode; -- OP Code
v.txMaster.tData(59 downto 56) := "0000"; -- Element ID
v.txMaster.tData(63 downto 60) := destId(3 downto 0); -- Destination ID = Z only
-- Set the hdr[2]
v.txMaster.tData(95 downto 64) := r.frame; -- Frame Number
-- Set the hdr[3]
v.txMaster.tData(127 downto 96) := timingMsg(31 downto 0); -- Ticks
-- Save the data and reset of the timing message
v.tData(0) := data;
v.timingMsg := timingMsg(63 downto 32);
-- Next state
v.state := HDR_S;
end if;
----------------------------------------------------------------------
when HDR_S => -- r.cnt = 1
-- Send the header
v.txMaster.tValid := '1';
v.txMaster.tKeep := x"FFFF";
-- Set the hdr[4]
v.txMaster.tData(31 downto 0) := r.timingMsg; -- Fiducials
-- Set the hdr[5]
v.txMaster.tData(47 downto 32) := x"0000"; -- sbtemp[0]
v.txMaster.tData(63 downto 48) := x"0000"; -- sbtemp[1]
-- Set the hdr[6]
v.txMaster.tData(79 downto 64) := x"0000"; -- sbtemp[2]
v.txMaster.tData(95 downto 80) := x"0000"; -- sbtemp[3]
-- Set the hdr[7]
v.txMaster.tData(127 downto 96) := frameType; -- =Frame Type
-- Save the data
v.tData(1) := data;
v.wordSize := wordSize;
-- Next state
v.state := CATCHUP_A_S;
----------------------------------------------------------------------
when CATCHUP_A_S => -- r.cnt = 2
-- Send the data
v.txMaster.tValid := '1';
v.txMaster.tData(63 downto 0) := r.tData(0);
v.txMaster.tData(127 downto 64) := r.tData(1);
-- Save the data
v.tData(2) := data;
-- Check the packet length
if r.wordSize = 0 then
-- Terminate the frame
v.txMaster.tKeep := x"00FF";
v.txMaster.tLast := '1';
-- Next state
v.state := IDLE_S;
elsif r.wordSize = 1 then
-- Terminate the frame
v.txMaster.tKeep := x"FFFF";
v.txMaster.tLast := '1';
-- Next state
v.state := IDLE_S;
else
-- Next state
v.state := CATCHUP_B_S;
end if;
----------------------------------------------------------------------
when CATCHUP_B_S => -- r.cnt = 3
-- Send the data
v.txMaster.tValid := '1';
v.txMaster.tData(63 downto 0) := r.tData(2);
v.txMaster.tData(127 downto 64) := data;
-- Check the packet length
if r.wordSize = 2 then
-- Terminate the frame
v.txMaster.tKeep := x"00FF";
v.txMaster.tLast := '1';
-- Next state
v.state := IDLE_S;
elsif r.wordSize = 3 then
-- Terminate the frame
v.txMaster.tKeep := x"FFFF";
v.txMaster.tLast := '1';
-- Next state
v.state := IDLE_S;
else
-- Setup for continuous
v.txMaster.tKeep := x"FFFF";
-- Next state
v.state := MOVE_S;
end if;
----------------------------------------------------------------------
when MOVE_S =>
-- Check for WRD[0]
if r.txMaster.tKeep = x"FFFF" then
v.txMaster.tKeep := x"00FF";
v.txMaster.tData(63 downto 0) := data;
-- Check for WRD[1]
else
v.txMaster.tValid := '1';
v.txMaster.tKeep := x"FFFF";
v.txMaster.tData(127 downto 64) := data;
end if;
-- Check the packet length
if r.wordSize = r.cnt then
-- Terminate the frame
v.txMaster.tValid := '1';
v.txMaster.tLast := '1';
-- Next state
v.state := IDLE_S;
end if;
----------------------------------------------------------------------
end case;
-- Increment the counter
v.cnt := r.cnt + 1;
-- Check if next state is IDLE
if (v.state = IDLE_S) then
-- Reset the counter
v.cnt := x"00";
end if;
-- Synchronous Reset
if timingRst320MHz = '1' then
v := REG_INIT_C;
end if;
-- Register the variable for next clock cycle
rin <= v;
-- Outputs
extBusy <= txCtrl.pause;
end process comb;
seq : process (timingClk320MHz) is
begin
if rising_edge(timingClk320MHz) then
r <= rin after TPD_G;
end if;
end process seq;
TX_FIFO : entity work.AxiStreamFifo
generic map (
-- General Configurations
TPD_G => TPD_G,
INT_PIPE_STAGES_G => 1,
PIPE_STAGES_G => 1,
SLAVE_READY_EN_G => false,
VALID_THOLD_G => 1,
-- FIFO configurations
BRAM_EN_G => true,
USE_BUILT_IN_G => false,
GEN_SYNC_FIFO_G => false,
CASCADE_SIZE_G => CASCADE_SIZE_G,
FIFO_ADDR_WIDTH_G => 9,
FIFO_FIXED_THRESH_G => true,
FIFO_PAUSE_THRESH_G => 250,
CASCADE_PAUSE_SEL_G => (CASCADE_SIZE_G-1),
-- AXI Stream Port Configurations
SLAVE_AXI_CONFIG_G => AXIS_CONFIG_C,
MASTER_AXI_CONFIG_G => ite(COMM_MODE_G, ssiAxiStreamConfig(4), SSI_PGP2B_CONFIG_C))
port map (
-- Slave Port
sAxisClk => timingClk320MHz,
sAxisRst => timingRst320MHz,
sAxisMaster => r.txMaster,
sAxisCtrl => txCtrl,
-- Master Port
mAxisClk => axisClk,
mAxisRst => axisRst,
mAxisMaster => mAxisMaster,
mAxisSlave => mAxisSlave);
end mapping;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity READER is
port(
clk_i : in std_logic;
action_i : in std_logic;
reset_i : in std_logic; -- LOW active
data_i : in std_logic_vector(7 downto 0);
A_o : out std_logic_vector(7 downto 0);
B_o : out std_logic_vector(7 downto 0);
operation_o : out std_logic_vector(7 downto 0)
);
end READER;
architecture Behavioral of READER is
type FAZE_ST is (FAZE_A_ST, FAZE_B_ST, FAZE_OPER_ST);
signal s_state: FAZE_ST := FAZE_A_ST;
signal regA : bit_vector (7 downto 0) := "00000000";
signal regB : bit_vector (7 downto 0) := "00000000";
signal regO : bit_vector (7 downto 0) := "00000000";
begin
process(clk_i, action_i, reset_i, data_i, s_state)
begin
if reset_i = '0' then
regA <= "00000000";
regB <= "00000000";
regO <= "00000000";
s_state <= FAZE_A_ST;
elsif rising_edge(clk_i) and action_i = '1' then
case s_state is
when FAZE_A_ST =>
regA <= To_bitvector(data_i);
s_state <= FAZE_B_ST;
when FAZE_B_ST =>
regB <= To_bitvector(data_i);
s_state <= FAZE_OPER_ST;
when FAZE_OPER_ST =>
regO <= To_bitvector(data_i);
s_state <= FAZE_A_ST;
when others =>
s_state <= FAZE_A_ST;
end case;
end if;
end process;
C2: process(s_state)
begin
case s_state is
when FAZE_A_ST =>
A_o <= To_StdLogicVector(regA);
B_o <= To_StdLogicVector(regB);
operation_o <= To_StdLogicVector(regO);
when FAZE_B_ST =>
when others =>
end case;
end process;
end Behavioral;
|
-- ----------------------------------------------------------------------------
-- FILE: fpgacfg_pkg.vhd
-- DESCRIPTION: Package for fpgacfg module
-- DATE: 11:13 AM Friday, May 11, 2018
-- AUTHOR(s): <NAME>
-- REVISIONS:
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
--NOTES:
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- ----------------------------------------------------------------------------
-- Package declaration
-- ----------------------------------------------------------------------------
package fpgacfg_pkg is
-- Outputs from the fpgacfg.
type t_FROM_FPGACFG is record
--FPGA direct clocking
phase_reg_sel : std_logic_vector(15 downto 0);
clk_ind : std_logic_vector(4 downto 0);
cnt_ind : std_logic_vector(4 downto 0);
load_phase_reg : std_logic;
drct_clk_en : std_logic_vector(15 downto 0);
--Interface Config
ch_en : std_logic_vector(15 downto 0);
smpl_width : std_logic_vector(1 downto 0);
mode : std_logic;
ddr_en : std_logic;
trxiq_pulse : std_logic;
mimo_int_en : std_logic;
synch_dis : std_logic;
synch_mode : std_logic;
smpl_nr_clr : std_logic;
txpct_loss_clr : std_logic;
rx_en : std_logic;
tx_en : std_logic;
rx_ptrn_en : std_logic;
tx_ptrn_en : std_logic;
tx_cnt_en : std_logic;
wfm_ch_en : std_logic_vector(15 downto 0);
wfm_play : std_logic;
wfm_load : std_logic;
wfm_smpl_width : std_logic_vector(1 downto 0);
SPI_SS : std_logic_vector(15 downto 0);
LMS1_SS : std_logic;
-- LMS2_SS : std_logic;
-- ADF_SS : std_logic;
-- DAC_SS : std_logic;
-- POT1_SS : std_logic;
LMS1_RESET : std_logic;
LMS1_CORE_LDO_EN : std_logic;
LMS1_TXNRX1 : std_logic;
LMS1_TXNRX2 : std_logic;
LMS1_TXEN : std_logic;
LMS1_RXEN : std_logic;
-- LMS2_RESET : std_logic;
-- LMS2_CORE_LDO_EN : std_logic;
-- LMS2_TXNRX1 : std_logic;
-- LMS2_TXNRX2 : std_logic;
-- LMS2_TXEN : std_logic;
-- LMS2_RXEN : std_logic;
GPIO : std_logic_vector(6 downto 0);
FPGA_LED1_CTRL : std_logic_vector(2 downto 0);
FPGA_LED2_CTRL : std_logic_vector(2 downto 0);
FX3_LED_CTRL : std_logic_vector(2 downto 0);
CLK_ENA : std_logic_vector(3 downto 0);
sync_pulse_period : std_logic_vector(31 downto 0);
sync_size : std_logic_vector(15 downto 0);
txant_pre : std_logic_vector(15 downto 0);
txant_post : std_logic_vector(15 downto 0);
end record t_FROM_FPGACFG;
-- Inputs to the fpgacfg.
type t_TO_FPGACFG is record
HW_VER : std_logic_vector(3 downto 0);
BOM_VER : std_logic_vector(3 downto 0);
PWR_SRC : std_logic;
end record t_TO_FPGACFG;
end package fpgacfg_pkg;
|
<filename>firmware/src/fpga/profi/rtl/flash/flash.vhd
-------------------------------------------------------------------[25.07.2019]
-- SPI flash parallel interface
--
-- Copyright (c) 2020 <NAME> <<EMAIL>>
--
-- Datasheets:
-- https://www.winbond.com/resource-files/w25q16dv_revi_nov1714_web.pdf
-- https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/m25p/m25p16.pdf
-- https://www.digikey.com/eewiki/pages/viewpage.action?pageId=4096096
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity flash is
generic (
SPI_CMD_SETSTATUS : std_logic_vector(7 downto 0) := X"01"; -- W25Q16 set status register command
SPI_CMD_PAGEPRG : std_logic_vector(7 downto 0) := X"02"; -- W25Q16 page program command
SPI_CMD_READ : std_logic_vector(7 downto 0) := X"03"; -- W25Q16 read command
SPI_CMD_WRITE_DIS : std_logic_vector(7 downto 0) := X"04"; -- W25Q16 write disable command
SPI_CMD_STATUSREG : std_logic_vector(7 downto 0) := X"05"; -- W25Q16 read status register command
SPI_CMD_WRITE_EN : std_logic_vector(7 downto 0) := X"06"; -- W25Q16 write enable command
SPI_CMD_BLOCK_ERASE : std_logic_vector(7 downto 0) := X"D8"; -- W25Q16 64k block erase command
SPI_CMD_POWERON : std_logic_vector(7 downto 0) := X"AB" -- W25Q16 power on command
);
port (
-- bus clock 28 MHz
CLK : in std_logic;
-- global reset
RESET : in std_logic;
-- parallel interface
A : in std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
WR_N : in std_logic := '1';
RD_N : in std_logic := '1';
ER_N : in std_logic := '1';
-- SPI FLASH physical interface (M25P16)
DATA0 : in std_logic;
NCSO : out std_logic;
DCLK : out std_logic;
ASDO : out std_logic;
-- status
BUSY : out std_logic;
DATA_READY : out std_logic
);
end flash;
architecture rtl of flash is
-- SPI
signal spi_di_bus : std_logic_vector(7 downto 0);
signal spi_do_bus : std_logic_vector(7 downto 0);
signal spi_busy : std_logic;
signal spi_busy_prev : std_logic;
signal spi_ena : std_logic;
signal spi_cont : std_logic;
signal spi_si : std_logic;
signal spi_so : std_logic;
signal spi_clk : std_logic;
signal spi_ss_n : std_logic_vector(0 downto 0);
signal prev_rd_n : std_logic;
signal prev_wr_n : std_logic;
signal prev_er_n : std_logic;
-- System
type machine IS( --state machine datatype
init,
idle,
cmd_read,
cmd_wp_off,
cmd_write_en,
cmd_erase_block,
cmd_write,
cmd_check_status,
cmd_write_dis,
cmd_wp_on
);
signal state : machine := init; -- current state
signal next_state : machine := init; -- state to return after some operations
signal is_busy : std_logic := '1';
signal is_ready : std_logic := '0';
begin
-- SPI FLASH 25MHz
U1: entity work.spi_master
generic map (
slaves => 1,
d_width => 8
)
port map (
clock => CLK,
reset_n => not(RESET),
enable => spi_ena,
cpol => '0', -- spi mode 0
cpha => '0',
cont => spi_cont,
clk_div => 1, --2, -- CLK divider
addr => 0,
tx_data => spi_di_bus,
miso => spi_so,
sclk => spi_clk,
ss_n => spi_ss_n,
mosi => spi_si,
busy => spi_busy,
rx_data => spi_do_bus
);
NCSO <= spi_ss_n(0);
spi_so <= DATA0;
ASDO <= spi_si;
DCLK <= spi_clk;
-------------------------------------------------------------------------------
-- flash read / write state machine
process (RESET, CLK)
VARIABLE count : INTEGER := 0;
begin
if RESET = '1' then
spi_ena <= '0';
spi_cont <= '0';
spi_di_bus <= (others => '0');
count := 0;
state <= init;
is_busy <= '1';
is_ready <= '0';
elsif CLK'event and CLK = '1' then
case state is
when init => -- power on command
spi_busy_prev <= spi_busy;
if (spi_busy_prev = '1' and spi_busy = '0') then
count := count + 1;
end if;
case count is
when 0 =>
spi_ena <= '1';
spi_di_bus <= SPI_CMD_POWERON;
when 1 =>
spi_ena <= '0';
when 2 =>
count := 0;
state <= idle;
when others => null;
end case;
when idle => -- ready to begin read / write cycle
is_busy <= '0';
spi_ena <= '0';
spi_cont <= '0';
count := 0;
spi_busy_prev <= '0';
prev_wr_n <= WR_N;
prev_rd_n <= RD_N;
prev_er_n <= ER_N;
if (RD_N = '0') then
state <= cmd_read;
elsif (WR_N = '0' and prev_wr_n = '1') then
state <= cmd_write_en;
next_state <= cmd_write;
elsif (ER_N = '0' and prev_er_n = '1') then
state <= cmd_write_en;
next_state <= cmd_erase_block;
end if;
when cmd_read => -- read command
is_busy <= '1';
spi_busy_prev <= spi_busy;
if (spi_busy_prev = '1' and spi_busy = '0') then
count := count + 1;
end if;
case count is
when 0 =>
if (spi_busy = '0') then
spi_cont <= '1';
spi_ena <= '1';
is_ready <= '0';
spi_di_bus <= SPI_CMD_READ;
else
spi_di_bus <= A(23 downto 16);
end if;
when 1 =>
spi_di_bus <= A(15 downto 8);
when 2 =>
spi_di_bus <= A(7 downto 0);
when 3 =>
spi_di_bus <= "00000000";
when 4 =>
spi_cont <= '0';
spi_ena <= '0';
when 5 =>
count := 0;
is_ready <= '1';
DO <= spi_do_bus;
state <= idle;
when others => null;
end case;
when cmd_write_en => -- write enable
is_busy <= '1';
is_ready <= '0';
spi_busy_prev <= spi_busy;
if (spi_busy_prev = '1' and spi_busy = '0') then
count := count + 1;
end if;
case count is
when 0 =>
spi_ena <= '1';
spi_cont <= '0';
spi_di_bus <= SPI_CMD_WRITE_EN;
when 1 =>
spi_ena <= '0';
when 2 =>
count := 0;
state <= next_state;
when others => null;
end case;
when cmd_erase_block => -- erase 64k block command
spi_busy_prev <= spi_busy;
if (spi_busy_prev = '1' and spi_busy = '0') then
count := count + 1;
end if;
case count is
when 0 =>
if (spi_busy = '0') then
spi_cont <= '1';
spi_ena <= '1';
spi_di_bus <= SPI_CMD_BLOCK_ERASE;
else
spi_di_bus <= A(23 downto 16);
end if;
when 1 =>
spi_di_bus <= A(15 downto 8);
when 2 =>
spi_di_bus <= A(7 downto 0);
when 3 =>
spi_cont <= '0';
spi_ena <= '0';
when 4 =>
count := 0;
state <= cmd_check_status;
next_state <= cmd_write_dis;
when others => null;
end case;
when cmd_write => -- write command
spi_busy_prev <= spi_busy;
if (spi_busy_prev = '1' and spi_busy = '0') then
count := count + 1;
end if;
case count is
when 0 =>
if (spi_busy = '0') then
spi_cont <= '1';
spi_ena <= '1';
spi_di_bus <= SPI_CMD_PAGEPRG;
else
spi_di_bus <= A(23 downto 16);
end if;
when 1 =>
spi_di_bus <= A(15 downto 8);
when 2 =>
spi_di_bus <= A(7 downto 0);
when 3 =>
spi_di_bus <= DI;
when 4 =>
spi_cont <= '0';
spi_ena <= '0';
when 5 =>
count := 0;
state <= cmd_check_status;
next_state <= cmd_write_dis;
when others => null;
end case;
when cmd_check_status => -- check status (after write or erase)
spi_busy_prev <= spi_busy;
if (spi_busy_prev = '1' and spi_busy = '0') then
count := count + 1;
end if;
case count is
when 0 =>
if (spi_busy = '0') then
spi_cont <= '1';
spi_ena <= '1';
is_ready <= '0';
spi_di_bus <= SPI_CMD_STATUSREG;
else
spi_di_bus <= "00000000";
end if;
when 1 =>
spi_cont <= '0';
spi_ena <= '0';
when 2 =>
count := 0;
if spi_do_bus(0) = '1' then
state <= cmd_check_status;
else
state <= next_state;
end if;
when others => null;
end case;
when cmd_write_dis => -- write disable
spi_busy_prev <= spi_busy;
if (spi_busy_prev = '1' and spi_busy = '0') then
count := count + 1;
end if;
case count is
when 0 =>
spi_ena <= '1';
spi_cont <= '0';
spi_di_bus <= SPI_CMD_WRITE_DIS;
when 1 =>
spi_ena <= '0';
when 2 =>
count := 0;
state <= idle;
when others => null;
end case;
when others => null;
end case;
end if;
end process;
BUSY <= is_busy;
DATA_READY <= is_ready;
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TriggerGenerator is
Port(
clk : in STD_LOGIC;
enable : in STD_LOGIC;
trig : out STD_LOGIC
);
end TriggerGenerator;
architecture Behavioral of TriggerGenerator is
component Counter is
generic(n : positive := 10);
Port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
output : out STD_LOGIC_VECTOR(n-1 downto 0)
);
end component;
signal output_signal : STD_LOGIC_VECTOR(23 downto 0);
signal reset_signal : STD_LOGIC;
begin
nanoseconds : Counter generic map(24) port map(clk, enable, reset_signal, output_signal);
process(clk, enable, output_signal)
constant ms100 : STD_LOGIC_VECTOR(23 downto 0) := "010011000100101101000000";
constant ms100And20us : STD_LOGIC_VECTOR(23 downto 0) := "010011000100110100110011";
begin
if enable = '1' then
if(output_signal > ms100 and output_signal < ms100And20us) then
trig <= '1';
else
trig <= '0';
end if;
if(output_signal = ms100And20us or output_signal="XXXXXXXXXXXXXXXXXXXXXXXX") then
reset_signal <= '0';
else
reset_signal <= '1';
end if;
end if;
end process;
end Behavioral;
|
-----Libraries-----
library ieee;
use ieee.std_logic_1164.all;
-----Entities-----
entity testerOinputNAND is
port( SW : in std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(0 downto 0)
);
end testerOinputNAND;
-----Architecture-----
architecture tester of testerOinputNAND is
begin
O1 : entity work.oInputNAND port map (a => SW, y => LEDR(0));
end tester;
|
-------------------------------------------------------------------------------
-- Title :
-------------------------------------------------------------------------------
-- File : PciTxDmaMemReq.vhd
-- Author : <NAME> <<EMAIL>>
-- Company : SLAC National Accelerator Laboratory
-- Created : 2013-07-03
-- Last update: 2015-05-23
-- Platform : Vivado 2015.1
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- This file is part of 'SLAC PGP Gen3 Card'.
-- It is subject to the license terms in the LICENSE.txt file found in the
-- top-level directory of this distribution and at:
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
-- No part of 'SLAC PGP Gen3 Card', including this file,
-- may be copied, modified, propagated, or distributed except according to
-- the terms contained in the LICENSE.txt file.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.StdRtlPkg.all;
use work.AxiStreamPkg.all;
use work.SsiPkg.all;
use work.PciPkg.all;
entity PciTxDmaMemReq is
generic (
TPD_G : time := 1 ns);
port (
-- DMA Interface
dmaIbMaster : out AxiStreamMasterType;
dmaIbSlave : in AxiStreamSlaveType;
dmaDescFromPci : in DescFromPciType;
dmaDescToPci : out DescToPciType;
dmaTranFromPci : in TranFromPciType;
-- Transaction Interface
start : out sl;
done : in sl;
pause : in sl;
remLength : in slv(23 downto 0);
newControl : out slv(7 downto 0);
newLength : out slv(23 downto 0);
-- Clock and reset
pciClk : in sl;
pciRst : in sl);
end PciTxDmaMemReq;
architecture rtl of PciTxDmaMemReq is
type StateType is (
IDLE_S,
CHECK_THRESH_S,
SEND_IO_REQ_HDR_S,
CALC_PIPELINE_DLY_S,
CHECK_LENGTH_S,
TR_DONE_S);
type RegType is record
start : sl;
cnt : slv(3 downto 0);
newControl : slv(7 downto 0);
tranLength : slv(8 downto 0);
newLength : slv(23 downto 0);
pendLength : slv(23 downto 0);
reqLength : slv(23 downto 0);
newAddr : slv(29 downto 0);
dmaDescToPci : DescToPciType;
txMaster : AxiStreamMasterType;
state : StateType;
end record RegType;
constant REG_INIT_C : RegType := (
start => '0',
cnt => (others => '0'),
newControl => (others => '0'),
tranLength => (others => '0'),
newLength => (others => '0'),
pendLength => (others => '0'),
reqLength => (others => '0'),
newAddr => (others => '0'),
dmaDescToPci => DESC_TO_PCI_INIT_C,
txMaster => AXI_STREAM_MASTER_INIT_C,
state => IDLE_S);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
begin
comb : process (dmaDescFromPci, dmaIbSlave, dmaTranFromPci, done, pause, pciRst, r, remLength) is
variable v : RegType;
begin
-- Latch the current value
v := r;
-- Reset strobing signals
v.start := '0';
-- Update tValid register
if dmaIbSlave.tReady = '1' then
v.txMaster.tValid := '0';
end if;
-- Calculate the length difference
v.pendLength := remLength - r.reqLength;
case r.state is
----------------------------------------------------------------------
when IDLE_S =>
-- Ready to send request memory headers
v.dmaDescToPci.newReq := '1';
-- Wait for descriptor to ACK
if dmaDescFromPci.newAck = '1' then
-- De-assert request to descriptor
v.dmaDescToPci.newReq := '0';
-- Start the completion process
v.start := '1';
-- Latch the descriptor values
v.dmaDescToPci.doneAddr := dmaDescFromPci.newAddr;
v.newLength := dmaDescFromPci.newLength;
v.newControl := dmaDescFromPci.newControl;
v.newAddr := dmaDescFromPci.newAddr;
v.reqLength := dmaDescFromPci.newLength;
-- Reset the pending length for next state (won't be updated yet)
v.pendLength := (others => '0');
-- Reset the counter
v.cnt := x"0";
-- Next state
v.state := CHECK_THRESH_S;
end if;
----------------------------------------------------------------------
when CHECK_THRESH_S =>
-- Check pending threshold
if (r.pendLength < (PCIE_MAX_TX_TRANS_LENGTH_C/2)) then
-- Calculate the transaction length
if r.reqLength < PCIE_MAX_TX_TRANS_LENGTH_C then
v.tranLength := r.reqLength(8 downto 0);
else
v.tranLength := toSlv(PCIE_MAX_TX_TRANS_LENGTH_C, 9);
end if;
-- Next state
v.state := SEND_IO_REQ_HDR_S;
end if;
----------------------------------------------------------------------
when SEND_IO_REQ_HDR_S =>
-- Check if the FIFO is ready
if (v.txMaster.tValid = '0') then
------------------------------------------------------
-- generated a TLP 3-DW data transfer without payload
--
-- data(127:96) = Ignored
-- data(095:64) = H2
-- data(063:32) = H1
-- data(031:00) = H0
------------------------------------------------------
-- Empty field
v.txMaster.tData(127 downto 96) := (others => '0');
--H2
v.txMaster.tData(95 downto 66) := r.newAddr;
v.txMaster.tData(65 downto 64) := "00"; --PCIe reserved
--H1
v.txMaster.tData(63 downto 48) := dmaTranFromPci.locId; -- Requester ID
v.txMaster.tData(47 downto 40) := dmaTranFromPci.tag; -- Tag
-- Last DW byte enable must be zero if the transaction is a single DWORD transfer
if r.tranLength = 1 then
v.txMaster.tData(39 downto 36) := "0000"; -- Last DW Byte Enable
else
v.txMaster.tData(39 downto 36) := "1111"; -- Last DW Byte Enable
end if;
v.txMaster.tData(35 downto 32) := "1111"; -- First DW Byte Enable
--H0
v.txMaster.tData(31) := '0'; --PCIe reserved
v.txMaster.tData(30 downto 29) := "00"; -- FMT = Memory read, 3-DW header w/out payload
v.txMaster.tData(28 downto 24) := "00000"; -- Type = Memory read or write
v.txMaster.tData(23) := '0'; --PCIe reserved
v.txMaster.tData(22 downto 20) := "000"; -- TC = 0
v.txMaster.tData(19 downto 16) := "0000"; --PCIe reserved
v.txMaster.tData(15) := '0'; -- TD = 0
v.txMaster.tData(14) := '0'; -- EP = 0
v.txMaster.tData(13 downto 12) := "00"; -- Attr = 0
v.txMaster.tData(11 downto 10) := "00"; --PCIe reserved
v.txMaster.tData(9 downto 0) := '0' & r.tranLength; -- Transaction length
-- Write the header to FIFO
v.txMaster.tValid := '1';
-- Set the EOF bit
v.txMaster.tLast := '1';
-- Set AXIS tKeep
v.txMaster.tKeep := x"0FFF";
-- Calculate next transmit address
v.newAddr := r.newAddr + r.tranLength;
-- Calculate remaining request length
v.reqLength := r.reqLength - r.tranLength;
-- Next state
v.state := CALC_PIPELINE_DLY_S;
end if;
----------------------------------------------------------------------
when CALC_PIPELINE_DLY_S =>
v.cnt := r.cnt + 1;
if r.cnt = x"F" then
v.cnt := x"0";
-- Next state
v.state := CHECK_LENGTH_S;
end if;
----------------------------------------------------------------------
when CHECK_LENGTH_S =>
-- Check if we are done requesting memory
if (r.reqLength /= 0) and (pause = '0') then
-- Next state
v.state := CHECK_THRESH_S;
end if;
----------------------------------------------------------------------
when TR_DONE_S =>
-- Let the descriptor know that we are done
v.dmaDescToPci.doneReq := '1';
-- Wait for descriptor to ACK
if dmaDescFromPci.doneAck = '1' then
-- Reset flag
v.dmaDescToPci.doneReq := '0';
-- Next state
v.state := IDLE_S;
end if;
----------------------------------------------------------------------
end case;
-- Wait for the completion state machine to complete
if done = '1' then
-- Let the descriptor know that we are done
v.dmaDescToPci.doneReq := '1';
-- Next state
v.state := TR_DONE_S;
end if;
-- Reset
if (pciRst = '1') then
v := REG_INIT_C;
end if;
-- Register the variable for next clock cycle
rin <= v;
-- Outputs
start <= r.start;
newControl <= r.newControl;
newLength <= r.newLength;
dmaDescToPci <= r.dmaDescToPci;
dmaIbMaster <= r.txMaster;
end process comb;
seq : process (pciClk) is
begin
if rising_edge(pciClk) then
r <= rin after TPD_G;
end if;
end process seq;
end rtl;
|
-------------------------------------------------------------------------
-- Test2 for H264 transforms - VHDL
--
-- Written by <NAME>
-- Copyright (c) 2008 Zexia Access Ltd
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of the Zexia Access Ltd nor the
-- names of its contributors may be used to endorse or promote products
-- derived from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY ZEXIA ACCESS LTD ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ZEXIA ACCESS LTD OR ANDY HENSON BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------
-- TEST stuff: test2 tests coretransform, quantise, dequantise, invtransform
-- reads in test vectors from stdin (testresidual.txt)
-- outputs stuff to stdout
-- takes about 300us simulation time to run all
-- modify slow to give decent gap between each processing
-- uses READY if slow not set
-- modify verbose to show all intermediate steps
-- output of "ERROR" if reconstructed samples differ lots from input
-- output of "DIFF" if reconstructed samples differ slightly from input
-- UNF
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
use std.textio.all;
use work.h264.all;
use work.misc.all;
entity test_transform2 is
end test_transform2;
architecture test_transform of test_transform2 is
--
signal CLK : std_logic := '0'; --clock
signal CLK2 : std_logic; --2x clock
signal QP : std_logic_vector(5 downto 0) := Conv_std_logic_vector(0,6);
signal READY : std_logic := '0'; --ready for enable when this set
signal ENABLE : std_logic := '0'; --values transfered only when this is 1
signal XXIN : std_logic_vector(35 downto 0) := (others => '0');
signal uuttransform_valid : std_logic := '0';
signal uuttransform_ynout : std_logic_vector(13 downto 0);
signal uutquant_valid : std_logic := '0';
signal uutquant_zout : std_logic_vector(11 downto 0);
signal uutdequant_valid : std_logic := '0';
signal uutdequant_wout : std_logic_vector(15 downto 0);
signal uutinvtransform_valid : std_logic := '0';
signal uutinvtransform_xout : std_logic_vector(35 downto 0);
--
begin
uuttransform : h264coretransform
port map (
CLK => clk2,
READY => ready,
ENABLE => enable,
XXIN => xxin,
VALID => uuttransform_valid,
YNOUT => uuttransform_ynout
);
--
uutquant : h264quantise
port map (
CLK => clk2,
ENABLE => uuttransform_valid,
DCCI => '0',
QP => qp,
YNIN => uuttransform_ynout,
ZOUT => uutquant_zout,
VALID => uutquant_valid
);
--
uutdequant : h264dequantise
port map (
CLK => clk2,
ENABLE => uutquant_valid,
QP => qp,
DCCI => '0',
ZIN => uutquant_zout,
WOUT => uutdequant_wout,
VALID => uutdequant_valid
);
--
uutinvtransform : h264invtransform
port map (
CLK => clk2,
ENABLE => uutdequant_valid,
WIN => uutdequant_wout,
--LAST =>
VALID => uutinvtransform_valid,
XOUT => uutinvtransform_xout
);
--
process --generate CLK2, 100MHz will do for this sim, and CLK at 50MHz
begin
CLK2 <= '0';
wait for 5 ns;
CLK2 <= '1';
CLK <= not CLK;
wait for 5 ns;
end process;
--
process --data input
type Tdata is array(0 to 15) of integer;
variable index : integer;
variable data : Tdata;
--
variable s : line;
variable sout : line;
variable c : character;
variable vali : integer;
variable n : integer;
--
variable slow : boolean := true;
--
begin
enable <= '0';
write(sout,"# Test output from VHDL TEST_TRANSFORM");
writeline(output,sout);
--
cmd: while not endfile(input) loop
readline(input,s);
write(s,' '); --add space to end
--write(sout,"READ:");
--//write(sout,s);
--writeline(output,sout);
read(s,c);
if c = '#' then
next cmd;
end if;
if c /= 'r' then
write(sout,"ERROR EXPECTING residual");
--//write(sout,s);
writeline(output,sout);
next cmd;
end if;
read(s,c);--e
read(s,c);--s
read(s,c);--i
read(s,c);--d
read(s,c);--u
read(s,c);--a
read(s,c);--l
write(sout,"residual ");
for i in 0 to 15 loop
read(s,vali); --first coeff
data(i) := vali;
write(sout,vali);
write(sout," ");
assert vali <= 255 and vali >= -255 report "residual value out of range" severity ERROR;
end loop;
--
-- each coeff line is used for 1 tests:
-- 16 residual coretransform
wait until rising_edge(clk2);
if ready='0' then
wait until ready='1';
end if;
for i in 0 to 3 loop
enable <= '1';
xxin <=
CONV_STD_LOGIC_VECTOR(data(i*4+3),9) &
CONV_STD_LOGIC_VECTOR(data(i*4+2),9) &
CONV_STD_LOGIC_VECTOR(data(i*4+1),9) &
CONV_STD_LOGIC_VECTOR(data(i*4),9);
wait until rising_edge(clk2);
end loop;
enable <= '0';
wait until rising_edge(clk2);
wait until rising_edge(clk2);
writeline(output,sout); --write input line now (quite late so after previous output)
if slow then
wait for 1000 ns; --to output all before next read
end if;
end loop; --all input lines
wait for 1000 ns;
write(sout,"#end of input");
writeline(output,sout);
wait for 1 ms;
assert false report "DONE" severity ERROR;
end process;
--
process(CLK2) --output from uuttransform
variable sout : line;
variable n : integer;
--variable verbose : boolean := false;
variable wasvalid : boolean := false;
begin
if rising_edge(CLK2) then
if uuttransform_valid='1' then
if not wasvalid then
write(sout,"=> coeff");
wasvalid := true;
end if;
n := conv_integer_signed(uuttransform_ynout);
write(sout," ");
write(sout,n);
elsif wasvalid then -- and not VALID
writeline(output,sout);
wasvalid := false;
end if;
end if;
end process;
--
process(CLK2) --output from uutquantise
variable sout : line;
variable n : integer;
--variable verbose : boolean := false;
variable wasvalid : boolean := false;
begin
if rising_edge(CLK2) then
if uutquant_valid='1' then
if not wasvalid then
write(sout,"=> quant(qp:");
write(sout,conv_integer(qp));
write(sout,")");
wasvalid := true;
end if;
if uutquant_zout(11)='0' then
n := conv_integer(uutquant_zout);
else
n := conv_integer(uutquant_zout)-4096;
end if;
write(sout," ");
write(sout,n);
elsif wasvalid then -- and not VALID
writeline(output,sout);
wasvalid := false;
end if;
end if;
end process;
--
process(CLK2) --output from uutdequantise
variable sout : line;
variable n : integer;
--variable verbose : boolean := false;
variable wasvalid : boolean := false;
begin
if rising_edge(CLK2) then
if uutdequant_valid='1' then
if not wasvalid then
write(sout,"=> coeff'");
wasvalid := true;
end if;
if uutdequant_wout(15)='0' then
n := conv_integer(uutdequant_wout);
else
n := conv_integer(uutdequant_wout)-65536;
end if;
write(sout," ");
write(sout,n);
elsif wasvalid then -- and not VALID
writeline(output,sout);
wasvalid := false;
end if;
end if;
end process;
--
process(CLK2) --output from uutinvtransform
variable sout : line;
variable rout : line;
variable n : integer;
variable b : integer;
variable wasvalid : boolean := false;
begin
if rising_edge(CLK2) then
if uutinvtransform_valid='1' then
if not wasvalid then
write(sout,"=> residual");
--write(rout,"=> residual");
wasvalid := true;
end if;
for i in 0 to 3 loop
b := i*9;
if uutinvtransform_xout(8+b)='0' then
n := conv_integer(uutinvtransform_xout(8+b downto b));
else
n := conv_integer(uutinvtransform_xout(8+b downto b))-512;
end if;
write(sout," ");
write(sout,n);
end loop;
write(sout,";");
elsif wasvalid then -- and not VALID
writeline(output,sout);
wasvalid := false;
end if;
end if;
end process;
--
process(CLK2) --check for dequantise
variable sout : line;
variable qout : line;
type intarray is array(0 to 15) of integer;
type table is array(0 to 5) of integer;
variable aquant : intarray;
variable qi : integer;
variable qo : integer;
variable qq : integer;
variable qpi : integer;
variable qpj : integer;
variable zig : integer;
variable v : integer;
variable w : integer;
constant tablea : table := (10,11,13,14,16,18);
constant tableb : table := (16,18,20,23,25,29);
constant tablec : table := (13,14,16,18,20,23);
begin
if rising_edge(CLK2) then
if uutquant_valid='1' then
if uutquant_zout(11)='0' then
aquant(qi) := conv_integer(uutquant_zout);
else
aquant(qi) := conv_integer(uutquant_zout)-4096;
end if;
-- if qi=0 then write(sout,"** quant"); end if;
-- if qi=0 then write(qout,"** coeff"); end if;
-- write(sout," ");
-- write(sout,aquant(qi));
qi := qi+1;
else
qi := 0;
end if;
if uutdequant_valid='1' then
qq := aquant(qo);
qpi := conv_integer(QP);
qpj := qpi / 6; --multiples of 6
qpi := qpi - (qpj*6); --remainder 0..5
assert qpi>=0 and qpi<=5;
assert qpj>=0 and qpj<=8; --51 max / 6 is 8
zig := 15-qo;
if zig=0 or zig=3 or zig=5 or zig=11 then
--positions 0,0; 0,2; 2,0; 2,2 - tablea
v := tablea(qpi);
elsif zig=4 or zig=10 or zig=12 or zig=15 then
--positions 1,1; 1,3; 3,1; 3,3 - tableb
v := tableb(qpi);
else
v := tablec(qpi);
end if;
if qpj > 0 then
for i in 0 to qpj loop
v := v*2;
end loop;
end if;
qq := qq*v;
if uutdequant_wout(15)='0' then
w := conv_integer(uutdequant_wout);
else
w := conv_integer(uutdequant_wout)-65536;
end if;
assert qq = w report "computed qq= differs from dequant component " severity warning;
-- write(qout," ");
-- write(qout,qq);
qo := qo+1;
-- if qo=16 then writeline(output,sout); end if;
-- if qo=16 then writeline(output,qout); end if;
else
qo := 0;
end if;
end if;
end process;
--
process(CLK2) --check for INVTRANSFORM
variable cout : line;
variable sout : line;
variable nullln : line;
type array44 is array(0 to 3, 0 to 3) of integer;
variable d : array44;
variable e : array44;
variable f : array44;
variable g : array44;
variable h : array44;
variable x : integer;
variable y : integer;
variable qi : integer;
variable yo : integer;
variable v : integer;
variable b : integer;
variable n : integer;
variable w : integer;
variable differ : boolean;
begin
if rising_edge(CLK2) then
if uutdequant_valid='1' then
if uutdequant_wout(15)='0' then
w := conv_integer(uutdequant_wout);
else
w := conv_integer(uutdequant_wout)-65536;
end if;
if qi=0 then y:=3; x:=3;
elsif qi=1 then y:=3; x:=2;
elsif qi=2 then y:=2; x:=3;
elsif qi=3 then y:=1; x:=3;
elsif qi=4 then y:=2; x:=2;
elsif qi=5 then y:=3; x:=1;
elsif qi=6 then y:=3; x:=0;
elsif qi=7 then y:=2; x:=1;
elsif qi=8 then y:=1; x:=2;
elsif qi=9 then y:=0; x:=3;
elsif qi=10 then y:=0; x:=2;
elsif qi=11 then y:=1; x:=1;
elsif qi=12 then y:=2; x:=0;
elsif qi=13 then y:=1; x:=0;
elsif qi=14 then y:=0; x:=1;
elsif qi=15 then y:=0; x:=0;
end if;
d(x,y) := w;
qi := qi+1;
else
qi := 0;
end if;
if qi=16 then
write(cout,"** coeff'");
for y in 0 to 3 loop
for x in 0 to 3 loop
write(cout," ");
write(cout,d(x,y));
end loop;
write(cout,";");
end loop;
write(sout,"** residual");
differ := false;
--
--now perform transform on it
--standard para 8.5.8
--
for i in 0 to 3 loop
e(i,0):=d(i,0)+d(i,2);
e(i,1):=d(i,0)-d(i,2);
e(i,2):=(d(i,1)/2)-d(i,3);
e(i,3):=d(i,1)+(d(i,3)/2);
end loop;
for i in 0 to 3 loop
f(i,0):=e(i,0)+e(i,3);
f(i,1):=e(i,1)+e(i,2);
f(i,2):=e(i,1)-e(i,2);
f(i,3):=e(i,0)-e(i,3);
end loop;
for i in 0 to 3 loop
g(0,i):=f(0,i)+f(2,i);
g(1,i):=f(0,i)-f(2,i);
g(2,i):=f(1,i)/2-f(3,i);
g(3,i):=f(1,i)+f(3,i)/2;
end loop;
for i in 0 to 3 loop
h(0,i):=g(0,i)+g(3,i);
h(1,i):=g(1,i)+g(2,i);
h(2,i):=g(1,i)-g(2,i);
h(3,i):=g(0,i)-g(3,i);
end loop;
end if;
if uutinvtransform_valid='1' then
for x in 0 to 3 loop
b := x*9;
v := h(x,yo);
--if v>0 then v := v+32; else v := v-32; end if;
--v := v/64;
v := v+32;
v := shr(v,6);
--optional clipping
if v>255 then v:=255; end if;
if v<-256 then v:=-256; end if;
--if uutinvtransform_xout(8+b)='0' then
n := conv_integer_signed(uutinvtransform_xout(8+b downto b));
--else
-- n := conv_integer(uutinvtransform_xout(8+b downto b))-512;
--end if;
write(sout," ");
write(sout,v);
if n /= v then
differ := true;
end if;
--assert n = v report "computed invtransform differs" severity warning;
end loop;
write(sout,";");
if yo=3 then
if differ then
write(sout," ** DIFFERS");
writeline(output,cout);
writeline(output,sout);
else
cout:=nullln;
sout:=nullln;
end if;
end if;
yo := yo+1;
else
yo := 0;
end if;
end if;
end process;
--
end test_transform;
|
-- Student name: <NAME>
-- Student ID number: 91467123
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;
USE work.Glob_dcls.all;
entity ALU_tb is
end ALU_tb;
architecture ALU_tb_arch of ALU_tb is
-- component declaration
component ALU is
port(
op_code : in ALU_opcode;
in0, in1 : in word;
C : in std_logic_vector(4 downto 0); -- shift amount
ALUout : out word;
Zero : out std_logic
);
end component;
-- component specification
-- signal declaration
signal top_code : ALU_opcode;
signal tin0, tin1 : word;
signal tC : std_logic_vector(4 downto 0); -- shift amount
signal tALUout : word;
signal tZero : std_logic;
begin
ALU_0: ALU port map (top_code, tin0, tin1, tC, tALUout, tZero);
test_ALU : process
begin
-- test ADD 000
top_code <= "000";
-- convert integer 0 to std_logic_vector
-- 0+0=0
tin0 <= std_logic_vector(to_signed(0,tin0'length));
tin1 <= (others => '0');
tC <= (others => '0');
-- check ZERO
-- wait for 10 ns to let values propogate in ALU
wait for 10 ns;
assert tZero = '1' report "0+0=0 Zero!=1";
assert tALUout = std_logic_vector(to_signed(0,tALUout'length)) report "0+0!=0";
-- 1+0=1
-- check not zero
wait for 20 ns;
tin0 <= std_logic_vector(to_signed(1, tin0'length));
wait for 10 ns;
assert tZero = '0' report "1+0=1 Zero!=0";
assert tALUout = std_logic_vector(to_signed(1,tALUout'length)) report "1+0!=1";
-- 1+105=106
wait for 20 ns;
tin1 <= std_logic_vector(to_signed(105, tin1'length));
wait for 10 ns;
assert tALUout = std_logic_vector(to_signed(106,tALUout'length)) report "1+105=106";
-- test negative addition
-- -106+105=-1
wait for 20 ns;
tin0 <= std_logic_vector(to_signed(-106, tin0'length));
wait for 10 ns;
assert tALUout = std_logic_vector(to_signed(-1,tALUout'length)) report "-106+105=-1";
wait for 10 ns;
-- test SUB 001
top_code <= "001";
-- convert integer 0 to std_logic_vector
-- 0-0=0
tin0 <= std_logic_vector(to_signed(0,tin0'length));
tin1 <= (others => '0');
tC <= (others => '0');
-- check ZERO
-- wait for 10 ns to let values propogate in ALU
wait for 10 ns;
assert tZero = '1' report "0-0=0 Zero!=1";
assert tALUout = std_logic_vector(to_signed(0,tALUout'length)) report "0-0!=0";
-- 1064-1024=40
tin0 <= std_logic_vector(to_signed(1064,tin0'length));
tin1 <= std_logic_vector(to_signed(1024,tin1'length));
wait for 10 ns;
assert tALUout = std_logic_vector(to_signed(40,tALUout'length)) report "1064-1024=40";
-- 1064-5000=-3936;
tin1 <= std_logic_vector(to_signed(5000,tin1'length));
wait for 10 ns;
assert tALUout = std_logic_vector(to_signed(-3936,tALUout'length)) report "1064-5000=-3936";
wait for 10 ns;
-- test SLL 010
top_code <= "010";
-- convert integer 0 to std_logic_vector
-- 0 SLL 0=0
tin0 <= std_logic_vector(to_signed(0,tin0'length));
tin1 <= (others => '0');
tC <= (others => '0');
-- check ZERO
-- wait for 10 ns to let values propogate in ALU
wait for 10 ns;
assert tZero = '1' report "0 SLL 0=0 Zero!=1";
assert tALUout = std_logic_vector(to_signed(0,tALUout'length)) report "0 SLL 0!=0";
-- 2 SLL 4 = 2^5
tin0 <= std_logic_vector(to_signed(2,tin0'length));
tC <= std_logic_vector(to_signed(4,tC'length));
-- tin1 = 2 SLL 4
tin1 <= std_logic_vector(shift_left(to_unsigned(2,tin1'length),4));
wait for 10 ns;
assert tALUout = tin1 report "2 SLL 4!=32";
wait for 10 ns;
-- test SRL 011
top_code <= "011";
-- convert integer 0 to std_logic_vector
-- 0 SRL 0=0
tin0 <= std_logic_vector(to_signed(0,tin0'length));
tin1 <= (others => '0');
tC <= (others => '0');
-- check ZERO
-- wait for 10 ns to let values propogate in ALU
wait for 10 ns;
assert tZero = '1' report "0 SRL 0=0 Zero!=1";
assert tALUout = std_logic_vector(to_signed(0,tALUout'length)) report "0 SRL 0!=0";
-- 32 SRL 4 = 2
tin0 <= std_logic_vector(to_signed(32,tin0'length));
tC <= std_logic_vector(to_signed(4,tC'length));
-- tin1 = 32 SRL 4
tin1 <= std_logic_vector(shift_right(to_unsigned(32,tin1'length),4));
wait for 10 ns;
assert tALUout = tin1 report "32 SRL 4!=2";
-- 32 SRL 10 = 0
tC <= std_logic_vector(to_signed(10,tC'length));
tin1 <= std_logic_vector(shift_right(to_unsigned(32,tin1'length),10));
wait for 10 ns;
assert tALUout = tin1 report "32 SRL 10!=0";
wait for 10 ns;
-- test AND 100
top_code <= "100";
-- convert integer 0 to std_logic_vector
-- 0 AND 0=0
tin0 <= std_logic_vector(to_signed(0,tin0'length));
tin1 <= (others => '0');
tC <= (others => '0');
-- check ZERO
-- wait for 10 ns to let values propogate in ALU
wait for 10 ns;
assert tZero = '1' report "0 AND 0=0 Zero!=1";
assert tALUout = std_logic_vector(to_signed(0,tALUout'length)) report "0 AND 0!=0";
-- 255 AND 255 = 255
tin0 <= std_logic_vector(to_signed(255,tin0'length));
tin1 <= std_logic_vector(to_signed(255,tin0'length));
wait for 10 ns;
assert tALUout = std_logic_vector(to_signed(255,tALUout'length)) report "255 AND 255!=255";
-- 255 AND 10 = 10
tin1 <= std_logic_vector(to_signed(10,tin0'length));
wait for 10 ns;
assert tALUout = std_logic_vector(to_signed(10,tALUout'length)) report "255 AND 10!=10";
wait for 10 ns;
-- test OR 101
top_code <= "101";
-- convert integer 0 to std_logic_vector
-- 0 OR 0=0
tin0 <= std_logic_vector(to_signed(0,tin0'length));
tin1 <= (others => '0');
tC <= (others => '0');
-- check ZERO
-- wait for 10 ns to let values propogate in ALU
wait for 10 ns;
assert tZero = '1' report "0 OR 0=0 Zero!=1";
assert tALUout = std_logic_vector(to_signed(0,tALUout'length)) report "0 OR 0!=0";
-- 255 OR 255 = 255
tin0 <= std_logic_vector(to_signed(255,tin0'length));
tin1 <= std_logic_vector(to_signed(255,tin0'length));
wait for 10 ns;
assert tALUout = std_logic_vector(to_signed(255,tALUout'length)) report "255 OR 255!=255";
-- 10 OR 4 = 14
tin0 <= std_logic_vector(to_signed(10,tin0'length));
tin1 <= std_logic_vector(to_signed(4,tin0'length));
wait for 10 ns;
assert tALUout = std_logic_vector(to_signed(14,tALUout'length)) report "10 OR 4 != 14";
wait for 10 ns;
-- test XOR 110
top_code <= "110";
-- convert integer 0 to std_logic_vector
-- 0 XOR 0=0
tin0 <= std_logic_vector(to_signed(0,tin0'length));
tin1 <= (others => '0');
tC <= (others => '0');
-- check ZERO
-- wait for 10 ns to let values propogate in ALU
wait for 10 ns;
assert tZero = '1' report "0 XOR 0=0 Zero!=1";
assert tALUout = std_logic_vector(to_signed(0,tALUout'length)) report "0 XOR 0!=0";
-- 255 XOR 255 = 0
tin0 <= std_logic_vector(to_signed(255,tin0'length));
tin1 <= std_logic_vector(to_signed(255,tin0'length));
wait for 10 ns;
assert tALUout = std_logic_vector(to_signed(0,tALUout'length)) report "255 XOR 255!=0";
-- 10 XOR 4 = 14
tin0 <= std_logic_vector(to_signed(10,tin0'length));
tin1 <= std_logic_vector(to_signed(4,tin0'length));
wait for 10 ns;
assert tALUout = std_logic_vector(to_signed(14,tALUout'length)) report "10 XOR 4 != 14";
wait for 10 ns;
-- test NOR 111
top_code <= "111";
-- convert integer 0 to std_logic_vector
-- 0 NOR 0 = ffff_ffff = -1
tin0 <= std_logic_vector(to_signed(0,tin0'length));
tin1 <= (others => '0');
tC <= (others => '0');
-- check ZERO
-- wait for 10 ns to let values propogate in ALU
wait for 10 ns;
assert tZero = '0' report "0 NOR 0= -1 Zero!=0";
assert tALUout = std_logic_vector(to_signed(-1,tALUout'length)) report "0 NOR 0!= -1";
-- 255 NOR 255 = 2^32 - 1 - 255 = -256
tin0 <= std_logic_vector(to_signed(255,tin0'length));
tin1 <= std_logic_vector(to_signed(255,tin0'length));
wait for 10 ns;
assert tALUout = std_logic_vector(to_signed(-256,tALUout'length)) report "255 NOR 255!=-256";
-- 10 NOR 4 = 2^32 - 1 - 14 = -15
tin0 <= std_logic_vector(to_signed(10,tin0'length));
tin1 <= std_logic_vector(to_signed(4,tin0'length));
wait for 10 ns;
assert tALUout = std_logic_vector(to_signed(-15,tALUout'length)) report "10 NOR 4 != -15";
wait;
end process;
end ALU_tb_arch;
|
<reponame>ikwzm/QCONV-STRIP-ZYBO-Z7<filename>project/ip/qconv_strip_axi3_0.1/src/PIPEWORK/convolution_parameter_buffer.vhd
-----------------------------------------------------------------------------------
--! @file convolution_parameter_buffer.vhd
--! @brief Convolution Parameter Buffer Module
--! @version 1.8.0
--! @date 2019/4/11
--! @author <NAME> <<EMAIL>>
-----------------------------------------------------------------------------------
--
-- Copyright (C) 2019 <NAME>
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-- OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library PIPEWORK;
use PIPEWORK.IMAGE_TYPES.all;
-----------------------------------------------------------------------------------
--! @brief Convolution Parameter Buffer Module
-----------------------------------------------------------------------------------
entity CONVOLUTION_PARAMETER_BUFFER is
generic (
PARAM : --! @brief OUTPUT STREAM PARAMETER :
--! 出力側のストリームのパラメータを指定する.
IMAGE_STREAM_PARAM_TYPE := NEW_IMAGE_STREAM_PARAM(8,1,1,1);
SHAPE : --! @brief PARAMETER SHAPE :
--! ウェイトデータの形(SHAPE)を指定する.
IMAGE_SHAPE_TYPE := NEW_IMAGE_SHAPE_CONSTANT(8,1,1,1,1);
ELEMENT_SIZE : --! @brief PARAMETER ELEMENT SIZE :
integer := 1024;
ID : --! @brief SDPRAM IDENTIFIER :
--! どのモジュールで使われているかを示す識別番号.
integer := 0;
OUT_QUEUE : --! @brief OUTPUT QUEUE SIZE :
--! 出力キューの大きさをワード数で指定する.
--! * QUEUE_SIZE=0 の場合は出力にキューが挿入されずダイレ
--! クトに出力される.
integer := 0
);
port (
-------------------------------------------------------------------------------
-- クロック&リセット信号
-------------------------------------------------------------------------------
CLK : --! @brief CLOCK :
--! クロック信号
in std_logic;
RST : --! @brief ASYNCRONOUSE RESET :
--! 非同期リセット信号.アクティブハイ.
in std_logic;
CLR : --! @brief SYNCRONOUSE RESET :
--! 同期リセット信号.アクティブハイ.
in std_logic;
-------------------------------------------------------------------------------
-- 制御 I/F
-------------------------------------------------------------------------------
REQ_VALID : --! @brief REQUEST VALID :
in std_logic;
REQ_WRITE : --! @brief REQUEST BUFFER WRITE :
in std_logic := '1';
REQ_READ : --! @brief REQUEST BUFFER READ :
in std_logic := '1';
REQ_READY : --! @brief REQUEST READY :
out std_logic;
C_SIZE : --! @brief SHAPE C SIZE :
in integer range 0 to SHAPE.C.MAX_SIZE := SHAPE.C.SIZE;
D_SIZE : --! @brief SHAPE D SIZE :
in integer range 0 to SHAPE.D.MAX_SIZE := SHAPE.D.SIZE;
X_SIZE : --! @brief SHAPE X SIZE :
in integer range 0 to SHAPE.X.MAX_SIZE := SHAPE.X.SIZE;
Y_SIZE : --! @brief SHAPE Y SIZE :
in integer range 0 to SHAPE.Y.MAX_SIZE := SHAPE.Y.SIZE;
RES_VALID : --! @brief RESPONSE VALID :
out std_logic;
RES_READY : --! @brief RESPONSE READY :
in std_logic := '1';
BUSY : --! @brief BUSY
out std_logic;
-------------------------------------------------------------------------------
-- 入力 I/F
-------------------------------------------------------------------------------
I_DATA : --! @brief INPUT PARAMETER DATA :
in std_logic_vector(PARAM.ELEM_BITS-1 downto 0);
I_VALID : --! @brief INPUT PARAMETER DATA VALID :
in std_logic;
I_READY : --! @brief INPUT PARAMETER DATA READY :
out std_logic;
-------------------------------------------------------------------------------
-- 出力側 I/F
-------------------------------------------------------------------------------
O_DATA : --! @brief OUTPUT PARAMETER DATA :
--! ストリームデータ出力.
out std_logic_vector(PARAM.DATA.SIZE-1 downto 0);
O_VALID : --! @brief OUTPUT PARAMETER DATA VALID :
--! 出力ストリームデータ有効信号.
--! * O_DATAが有効であることを示す.
out std_logic;
O_READY : --! @brief OUTPUT PARAMETER DATA READY :
--! 出力ストリームデータレディ信号.
in std_logic
);
end CONVOLUTION_PARAMETER_BUFFER;
-----------------------------------------------------------------------------------
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library PIPEWORK;
use PIPEWORK.COMPONENTS.SDPRAM;
use PIPEWORK.COMPONENTS.QUEUE_REGISTER;
use PIPEWORK.IMAGE_TYPES.all;
use PIPEWORK.CONVOLUTION_COMPONENTS.CONVOLUTION_PARAMETER_BUFFER_WRITER;
use PIPEWORK.CONVOLUTION_COMPONENTS.CONVOLUTION_PARAMETER_BUFFER_READER;
architecture RTL of CONVOLUTION_PARAMETER_BUFFER is
-------------------------------------------------------------------------------
-- BANK_SIZE : バンクの数
-------------------------------------------------------------------------------
constant BANK_SIZE : integer := PARAM.SHAPE.D.SIZE *
PARAM.SHAPE.Y.SIZE *
PARAM.SHAPE.X.SIZE *
PARAM.SHAPE.C.SIZE ;
-------------------------------------------------------------------------------
-- BUF_WIDTH : メモリのビット幅を２のべき乗値で示す
-------------------------------------------------------------------------------
function CALC_BUF_WIDTH(BITS: integer) return integer is
variable width : integer;
begin
width := 0;
while (2**width < BITS) loop
width := width + 1;
end loop;
return width;
end function;
constant BUF_WIDTH : integer := CALC_BUF_WIDTH(PARAM.ELEM_BITS);
-------------------------------------------------------------------------------
-- BUF_DEPTH: メモリバンク１つあたりの深さ(ビット単位)を２のべき乗値で示す
-------------------------------------------------------------------------------
function CALC_BUF_DEPTH return integer is
variable size : integer;
variable depth : integer;
begin
size := ELEMENT_SIZE*(2**BUF_WIDTH);
size := (size + BANK_SIZE - 1)/BANK_SIZE;
depth := 0;
while (2**depth < size) loop
depth := depth + 1;
end loop;
return depth;
end function;
constant BUF_DEPTH : integer := CALC_BUF_DEPTH;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
constant BUF_DATA_BITS : integer := 2**BUF_WIDTH;
constant BUF_ADDR_BITS : integer := BUF_DEPTH - BUF_WIDTH;
constant BUF_WENA_BITS : integer := 1;
constant BUF_SIZE_BITS : integer := BUF_ADDR_BITS + 1;
signal buf_wdata : std_logic_vector(BANK_SIZE*BUF_DATA_BITS-1 downto 0);
signal buf_waddr : std_logic_vector(BANK_SIZE*BUF_ADDR_BITS-1 downto 0);
signal buf_we : std_logic_vector(BANK_SIZE*BUF_WENA_BITS-1 downto 0);
signal buf_rdata : std_logic_vector(BANK_SIZE*BUF_DATA_BITS-1 downto 0);
signal buf_raddr : std_logic_vector(BANK_SIZE*BUF_ADDR_BITS-1 downto 0);
signal buf_push : std_logic;
constant buf_wready : std_logic := '1';
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
constant QUEUE_SIZE : integer := 1;
constant QUEUE_DATA_ADDR_LO : integer := 0;
constant QUEUE_DATA_ADDR_HI : integer := QUEUE_DATA_ADDR_LO + BUF_ADDR_BITS - 1;
constant QUEUE_DATA_SIZE_LO : integer := QUEUE_DATA_ADDR_HI + 1;
constant QUEUE_DATA_SIZE_HI : integer := QUEUE_DATA_SIZE_LO + BUF_SIZE_BITS - 1;
constant QUEUE_DATA_BITS : integer := QUEUE_DATA_SIZE_HI + 1;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
signal wr_req_valid : std_logic;
signal wr_req_ready : std_logic;
signal wr_res_valid : std_logic;
signal wr_res_ready : std_logic;
signal wr_busy : std_logic;
signal wr_res_addr : std_logic_vector(BUF_ADDR_BITS -1 downto 0);
signal wr_res_size : std_logic_vector(BUF_SIZE_BITS -1 downto 0);
signal wr_res_data : std_logic_vector(QUEUE_DATA_BITS-1 downto 0);
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
signal rd_req_addr : std_logic_vector(BUF_ADDR_BITS -1 downto 0);
signal rd_req_addr_valid : std_logic;
signal rd_req_valid : std_logic;
signal rd_req_ready : std_logic;
signal rd_res_valid : std_logic;
signal rd_res_ready : std_logic;
signal rd_res_size : std_logic_vector(BUF_SIZE_BITS -1 downto 0);
signal rd_busy : std_logic;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
type STATE_TYPE is (IDLE_STATE ,
WRITE_REQ_STATE,
WRITE_RES_STATE,
READ_REQ_STATE ,
READ_RES_STATE ,
RES_STATE);
signal state : STATE_TYPE;
signal wr_rd : std_logic;
begin
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
process (CLK, RST) begin
if (RST = '1') then
state <= IDLE_STATE;
wr_rd <= '0';
elsif (CLK'event and CLK = '1') then
if (CLR = '1') then
state <= IDLE_STATE;
wr_rd <= '0';
else
case state is
when IDLE_STATE =>
if (REQ_VALID = '1') then
if (REQ_WRITE = '1') then
state <= WRITE_REQ_STATE;
wr_rd <= REQ_READ;
elsif (REQ_READ = '1') then
state <= READ_REQ_STATE;
wr_rd <= '0';
else
state <= RES_STATE;
wr_rd <= '0';
end if;
else
state <= IDLE_STATE;
end if;
when WRITE_REQ_STATE =>
if (wr_req_ready = '1') then
state <= WRITE_RES_STATE;
else
state <= WRITE_REQ_STATE;
end if;
when WRITE_RES_STATE =>
if (wr_res_valid = '1' and wr_rd = '1') then
state <= READ_REQ_STATE;
elsif (wr_res_valid = '1' and wr_rd = '0') then
state <= RES_STATE;
else
state <= WRITE_RES_STATE;
end if;
when READ_REQ_STATE =>
if (rd_req_ready = '1') then
state <= READ_RES_STATE;
else
state <= READ_REQ_STATE;
end if;
when READ_RES_STATE =>
if (rd_res_valid = '1') then
state <= RES_STATE;
else
state <= READ_RES_STATE;
end if;
when RES_STATE =>
if (RES_READY = '1') then
state <= IDLE_STATE;
else
state <= RES_STATE;
end if;
when others =>
state <= IDLE_STATE;
end case;
end if;
end if;
end process;
REQ_READY <= '1' when (state = IDLE_STATE ) else '0';
RES_VALID <= '1' when (state = RES_STATE ) else '0';
BUSY <= '1' when (state /= IDLE_STATE ) else '0';
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
wr_req_valid <= '1' when (state = WRITE_REQ_STATE) else '0';
wr_res_ready <= '1' when (state = WRITE_RES_STATE) else '0';
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
rd_req_valid <= '1' when (state = READ_REQ_STATE ) else '0';
rd_res_ready <= '1' when (state = READ_RES_STATE ) else '0';
-------------------------------------------------------------------------------
-- WRITER
-------------------------------------------------------------------------------
WR: CONVOLUTION_PARAMETER_BUFFER_WRITER --
generic map ( --
PARAM => PARAM , --
SHAPE => SHAPE , --
BANK_SIZE => BANK_SIZE , --
BUF_ADDR_BITS => BUF_ADDR_BITS , --
BUF_DATA_BITS => BUF_DATA_BITS --
) --
port map ( --
-------------------------------------------------------------------------------
-- クロック&リセット信号
-------------------------------------------------------------------------------
CLK => CLK , -- In :
RST => RST , -- In :
CLR => CLR , -- In :
-------------------------------------------------------------------------------
-- 制御 I/F
-------------------------------------------------------------------------------
REQ_VALID => wr_req_valid , -- In :
REQ_READY => wr_req_ready , -- out :
C_SIZE => C_SIZE , -- In :
D_SIZE => D_SIZE , -- In :
RES_VALID => wr_res_valid , -- Out :
RES_READY => wr_res_ready , -- In :
RES_ADDR => wr_res_addr , -- Out :
RES_SIZE => wr_res_size , -- Out :
BUSY => wr_busy , -- Out :
-------------------------------------------------------------------------------
-- 入力 I/F
-------------------------------------------------------------------------------
I_DATA => I_DATA , -- In :
I_VALID => I_VALID , -- In :
I_READY => I_READY , -- Out :
-------------------------------------------------------------------------------
-- バッファメモリ I/F
-------------------------------------------------------------------------------
BUF_DATA => buf_wdata , -- Out :
BUF_ADDR => buf_waddr , -- Out :
BUF_WE => buf_we , -- Out :
BUF_PUSH => buf_push , -- Out :
BUF_READY => buf_wready -- In :
); --
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
process (CLK, RST) begin
if (RST = '1') then
rd_req_addr <= (others => '0');
rd_res_size <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (CLR = '1' or state = IDLE_STATE) then
rd_req_addr <= (others => '0');
rd_res_size <= (others => '0');
elsif (wr_res_valid = '1' and wr_res_ready = '1') then
rd_req_addr <= wr_res_addr;
rd_res_size <= wr_res_size;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- READER
-------------------------------------------------------------------------------
RD: CONVOLUTION_PARAMETER_BUFFER_READER --
generic map ( --
PARAM => PARAM , --
SHAPE => SHAPE , --
BANK_SIZE => BANK_SIZE , --
BUF_ADDR_BITS => BUF_ADDR_BITS , --
BUF_DATA_BITS => BUF_DATA_BITS , --
QUEUE_SIZE => OUT_QUEUE --
) --
port map ( --
---------------------------------------------------------------------------
-- クロック&リセット信号
---------------------------------------------------------------------------
CLK => CLK , -- In :
RST => RST , -- In :
CLR => CLR , -- In :
---------------------------------------------------------------------------
-- 制御 I/F
---------------------------------------------------------------------------
REQ_VALID => rd_req_valid , -- In :
REQ_READY => rd_req_ready , -- out :
REQ_ADDR_LOAD => wr_rd , -- In :
REQ_ADDR => rd_req_addr , -- In :
C_SIZE => C_SIZE , -- In :
D_SIZE => D_SIZE , -- In :
X_SIZE => X_SIZE , -- In :
Y_SIZE => Y_SIZE , -- In :
RES_VALID => rd_res_valid , -- Out :
RES_READY => rd_res_ready , -- In :
BUSY => rd_busy , -- Out :
---------------------------------------------------------------------------
-- 出力側 I/F
---------------------------------------------------------------------------
O_DATA => O_DATA , -- Out :
O_VALID => O_VALID , -- Out :
O_READY => O_READY , -- In :
---------------------------------------------------------------------------
-- バッファメモリ I/F
---------------------------------------------------------------------------
BUF_DATA => buf_rdata , -- In :
BUF_ADDR => buf_raddr -- Out :
); --
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
BUF: for bank in 0 to BANK_SIZE-1 generate
constant RAM_ID : integer := ID + bank;
signal wdata : std_logic_vector(BUF_DATA_BITS-1 downto 0);
signal waddr : std_logic_vector(BUF_ADDR_BITS-1 downto 0);
signal we : std_logic_vector(BUF_WENA_BITS-1 downto 0);
signal rdata : std_logic_vector(BUF_DATA_BITS-1 downto 0);
signal raddr : std_logic_vector(BUF_ADDR_BITS-1 downto 0);
begin
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
wdata <= buf_wdata((bank+1)*BUF_DATA_BITS-1 downto (bank)*BUF_DATA_BITS);
waddr <= buf_waddr((bank+1)*BUF_ADDR_BITS-1 downto (bank)*BUF_ADDR_BITS);
we <= buf_we ((bank+1)*BUF_WENA_BITS-1 downto (bank)*BUF_WENA_BITS);
raddr <= buf_raddr((bank+1)*BUF_ADDR_BITS-1 downto (bank)*BUF_ADDR_BITS);
buf_rdata((bank+1)*BUF_DATA_BITS-1 downto (bank)*BUF_DATA_BITS) <= rdata;
---------------------------------------------------------------------------
--
---------------------------------------------------------------------------
RAM: SDPRAM --
generic map ( --
DEPTH => BUF_DEPTH, -- メモリの深さ(ビット単位)を2のべき乗値で指定する.
RWIDTH => BUF_WIDTH, -- リードデータ(RDATA)の幅(ビット数)を2のべき乗値で指定する.
WWIDTH => BUF_WIDTH, -- ライトデータ(WDATA)の幅(ビット数)を2のべき乗値で指定する.
WEBIT => 0 , -- ライトイネーブル信号(WE)の幅(ビット数)を2のべき乗値で指定する.
ID => RAM_ID -- どのモジュールで使われているかを示す識別番号.
) --
port map ( --
WCLK => CLK , -- In :
WE => we , -- In :
WADDR => waddr , -- In :
WDATA => wdata , -- In :
RCLK => CLK , -- In :
RADDR => raddr , -- In :
RDATA => rdata -- Out :
); --
end generate;
end RTL;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY InstructionMemory is
PORT (
addr: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
MemRead, Clock: IN STD_LOGIC;
ReadData: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END InstructionMemory;
ARCHITECTURE behavior OF InstructionMemory IS
TYPE memory IS ARRAY (0 TO 2**3 - 1) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
CONSTANT cpu_memory : memory := (
0 => "00011001", -- ADD 01,01,10 00000000
1 => "01111011", -- SUB 11,11,10 00000001
2 => "10010000", -- BEQ 01,00 (Endereço 00000000) 00000010
3 => "00000000", -- 00000011
4 => "11000000", -- JMP 00000000 00000100
5 => "00000000", -- 00000101
6 => "00000000", -- 00000110
7 => "00000000"); -- 00000111
BEGIN
PROCESS (addr, Clock)
BEGIN
IF MemRead = '1' THEN
ReadData <= cpu_memory(TO_INTEGER(UNSIGNED(addr)));
END IF;
END PROCESS;
END ARCHITECTURE;
|
<filename>DSM_Final/fpgaproj/filsrc/mwpingram.vhd
-- ----------------------------------------------
-- File Name: mwpingram.vhd
-- Created: 29-Dec-2017 18:36:24
-- Copyright 2017 MathWorks, Inc.
-- ----------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY mwpingram IS
PORT (
txclk : IN std_logic;
txclk_en : IN std_logic;
rxclk : IN std_logic;
pingrdaddr : IN std_logic_vector(8 DOWNTO 0); -- Read Address for ping data
pingrddata : OUT std_logic_vector(7 DOWNTO 0); -- Read Data for ping data
pingwraddr : IN std_logic_vector(8 DOWNTO 0); -- Write address for ping data
pingwrdata : IN std_logic_vector(7 DOWNTO 0); -- Write data for ping data
pingwren : IN std_logic); -- Write enable for ping data
END mwpingram;
ARCHITECTURE rtl OF mwpingram IS
COMPONENT MWDPRAM
GENERIC (
DATAWIDTH : INTEGER;
ADDRWIDTH : INTEGER);
PORT (
clkA : IN std_logic;
enbA : IN std_logic;
wr_dinA : IN std_logic_vector(DATAWIDTH-1 DOWNTO 0);
wr_addrA : IN std_logic_vector(ADDRWIDTH-1 DOWNTO 0);
wr_enA : IN std_logic;
clkB : IN std_logic;
enbB : IN std_logic;
rd_addrB : IN std_logic_vector(ADDRWIDTH-1 DOWNTO 0);
rd_doutB : OUT std_logic_vector(DATAWIDTH-1 DOWNTO 0));
END COMPONENT;
CONSTANT zeros : STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0');
BEGIN -- rtl
dpram_1: MWDPRAM
GENERIC MAP (
DATAWIDTH => 8,
ADDRWIDTH => 9)
PORT MAP (
clkA => rxclk,
enbA => '1',
wr_dinA => pingwrdata,
wr_addrA => pingwraddr,
wr_enA => pingwren,
--rd_addrA => zeros,
--rd_doutA => rd_doutA,
clkB => txclk,
enbB => txclk_en,
rd_addrB => pingrdaddr,
rd_doutB => pingrddata);
END rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity schermHorizontaal is
Port (
--in
CLK25MHz: in std_logic;
--out
hSync : out std_logic;
hTeller: out integer range 0 to 800;
hDisplayAan: out std_logic
);
end schermHorizontaal;
architecture Behavioral of schermHorizontaal is
--signalen
signal teller: integer range 0 to 800;
--constanten
--timings: lijn (komt overeen met 1 tick van de 25MHz klok)
constant hBackPorchTijd: integer := 48;
constant hFrontPorchTijd: integer := 16;
constant hSyncTijd: integer := 96;
constant hVisTijd: integer := 640;
constant hTotaalTijd: integer := 800;
begin
telKlok: process(CLK25MHZ)
begin
if rising_edge(CLK25MHz) then
if teller < hTotaalTijd-1 then
teller <= teller +1;
else
teller <= 0;
end if;
end if;
end process;
schermLijnGenerator: process(teller)
begin
--standaardwaarden (regels v combinatorisch process)
hDisplayAan <= '0';
hSync <= '1';
hTeller <= teller;
if teller <= hVisTijd-1 then
hDisplayAan <= '1';
hSync <= '1';
elsif teller > hVisTijd-1 and teller <= (hVisTijd + hFrontPorchTijd-1) then
hDisplayAan <= '0';
hSync <= '1';
elsif teller >(hVisTijd + hFrontPorchTijd-1) and teller <= (hVisTijd + hFrontPorchTijd + hSyncTijd-1) then
hDisplayAan <= '0';
hSync <= '0';
elsif teller >(hVisTijd + hFrontPorchTijd + hSyncTijd-1) and teller <= (hVisTijd + hFrontPorchTijd + hSyncTijd + hBackPorchTijd-1) then
hDisplayAan <= '0';
hSync <= '1';
end if;
end process;
end Behavioral;
|
<gh_stars>1-10
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.graph_data_parameters.all;
entity switch_to_array is
port (
switch : in std_logic_vector(17 downto 0);
data : out data_array
) ;
end entity ; -- switch_to_array
architecture arch of switch_to_array is
begin
switch_changes : process( switch )
variable switch_range_width : integer := 18/NUMBER_OF_SAMPLES;
variable pad : std_logic_vector(SAMPLES_DATA_LENGTH - 1 - switch_range_width downto 0);
variable temp : std_logic_vector(SAMPLES_DATA_LENGTH -1 downto 0);
begin
pad := (others => '0');
for j in 0 to NUMBER_OF_SAMPLES-1 loop
temp := pad & switch(j*switch_range_width+switch_range_width-1 downto j*switch_range_width);
data(j) <= temp(SAMPLES_DATA_LENGTH -5 downto 0) & "0000"; -- convert range of switches to data element
end loop;
end process ; -- switch_changes
end architecture ; -- arch
|
<reponame>Basman74/Sweet32
-- <NAME>, copyright 2014
--
-- Create Date: 18:22:00 March 18, 2014
-- Module Name: sdram_simple - RTL
--
-- Simple SDRAM Controller for Winbond W9812G6JH-75
-- Can synthesize: Yes
-- Proven in hardware: Yes
--
-- The MIT License (MIT)
--
-- Copyright (c) 2014 <NAME>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
entity sdram_simple is
port(
-- Host side
clk_100m0_i : in std_logic; -- Master clock
reset_i : in std_logic := '0'; -- Reset, active high
refresh_i : in std_logic := '0'; -- Initiate a refresh cycle, active high
rw_i : in std_logic := '0'; -- Initiate a read or write operation, active high
we_i : in std_logic := '0'; -- Write enable, active low
addr_i : in std_logic_vector(23 downto 0) := (others => '0'); -- Address from host to SDRAM
data_i : in std_logic_vector(15 downto 0) := (others => '0'); -- Data from host to SDRAM
ub_i : in std_logic; -- Data upper byte enable, active low
lb_i : in std_logic; -- Data lower byte enable, active low
ready_o : out std_logic := '0'; -- Set to '1' when the memory is ready
done_o : out std_logic := '0'; -- Read, write, or refresh, operation is done
data_o : out std_logic_vector(15 downto 0); -- Data from SDRAM to host
-- SDRAM side
sdCke_o : out std_logic; -- Clock-enable to SDRAM
sdCe_bo : out std_logic; -- Chip-select to SDRAM
sdRas_bo : out std_logic; -- SDRAM row address strobe
sdCas_bo : out std_logic; -- SDRAM column address strobe
sdWe_bo : out std_logic; -- SDRAM write enable
sdBs_o : out std_logic_vector(1 downto 0); -- SDRAM bank address
sdAddr_o : out std_logic_vector(12 downto 0); -- SDRAM row/column address
sdData_io : inout std_logic_vector(15 downto 0); -- Data to/from SDRAM
sdDqmh_o : out std_logic; -- Enable upper-byte of SDRAM databus if true
sdDqml_o : out std_logic -- Enable lower-byte of SDRAM databus if true
);
end entity;
architecture rtl of sdram_simple is
-- SDRAM controller states.
type fsm_state_type is (
ST_INIT_WAIT, ST_INIT_PRECHARGE, ST_INIT_REFRESH1, ST_INIT_MODE, ST_INIT_REFRESH2,
ST_IDLE, ST_REFRESH, ST_ACTIVATE, ST_RCD, ST_RW, ST_RAS1, ST_RAS2, ST_PRECHARGE);
signal state_r, state_x : fsm_state_type := ST_INIT_WAIT;
-- SDRAM mode register data sent on the address bus.
--
-- | A12-A10 | A9 | A8 A7 | A6 A5 A4 | A3 | A2 A1 A0 |
-- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len|
-- 0 0 0 0 0 0 0 1 0 0 0 0 0
constant MODE_REG : std_logic_vector(12 downto 0) := "000" & "0" & "00" & "010" & "0" & "000";
-- SDRAM commands combine SDRAM inputs: cs, ras, cas, we.
subtype cmd_type is unsigned(3 downto 0);
constant CMD_ACTIVATE : cmd_type := "0011";
constant CMD_PRECHARGE : cmd_type := "0010";
constant CMD_WRITE : cmd_type := "0100";
constant CMD_READ : cmd_type := "0101";
constant CMD_MODE : cmd_type := "0000";
constant CMD_NOP : cmd_type := "0111";
constant CMD_REFRESH : cmd_type := "0001";
signal cmd_r : cmd_type;
signal cmd_x : cmd_type;
signal bank_s : std_logic_vector(1 downto 0);
signal row_s : std_logic_vector(12 downto 0);
signal col_s : std_logic_vector(8 downto 0);
signal addr_r : std_logic_vector(12 downto 0);
signal addr_x : std_logic_vector(12 downto 0); -- SDRAM row/column address.
signal sd_dout_r : std_logic_vector(15 downto 0);
signal sd_dout_x : std_logic_vector(15 downto 0);
signal sd_busdir_r : std_logic;
signal sd_busdir_x : std_logic;
signal timer_r, timer_x : natural range 0 to 20000 := 0;
signal refcnt_r, refcnt_x : natural range 0 to 7 := 0;
signal bank_r, bank_x : std_logic_vector(1 downto 0);
signal cke_r, cke_x : std_logic;
signal sd_dqmu_r, sd_dqmu_x : std_logic;
signal sd_dqml_r, sd_dqml_x : std_logic;
signal ready_r, ready_x : std_logic;
begin
-- SDRAM signals.
(sdCe_bo, sdRas_bo, sdCas_bo, sdWe_bo) <= cmd_r; -- SDRAM operation control bits
sdCke_o <= cke_r; -- SDRAM clock enable
sdBs_o <= bank_r; -- SDRAM bank address
sdAddr_o <= addr_r; -- SDRAM address
sdData_io <= sd_dout_r when sd_busdir_r = '1' else (others => 'Z'); -- SDRAM data bus.
sdDqmh_o <= sd_dqmu_r; -- SDRAM high data byte enable, active low
sdDqml_o <= sd_dqml_r; -- SDRAM low date byte enable, active low
ready_o <= ready_r;
-- Data back to host, not buffered and must be latched when done_o == '1'.
data_o <= sdData_io;
-- 23 22 | 21 20 19 18 17 16 15 14 13 12 11 10 09 | 08 07 06 05 04 03 02 01 00 |
-- BS0 BS1 | ROW (A12-A0) 8192 rows | COL (A8-A0) 512 cols |
bank_s <= addr_i(23 downto 22);
row_s <= addr_i(21 downto 9);
col_s <= addr_i(8 downto 0);
-- When rw_i activates:
-- hold_i | active_r
-- 0 | 0 -> 0 activate the row, issue read/write, precharge all rows when done
-- 1 | 0 -> 1 activate the row, issue read/write, do not precharage when done
-- 1 | 1 -> 1 issue read/write, do not precharge when done
-- 0 | 1 -> 0 issue read/write, precharge all rows when done
--
-- Thus, for a "one time" read / write, hold_i should be low. For a series of reads / writes
-- to the same bank, hold_i should be held high for all reads / writes, but then brought
-- low for the final read / write.
process (
state_r, timer_r, refcnt_r, cke_r, addr_r, sd_dout_r, sd_busdir_r, sd_dqmu_r, sd_dqml_r, ready_r,
bank_s, row_s, col_s,
rw_i, refresh_i, addr_i, data_i, we_i, ub_i, lb_i )
begin
state_x <= state_r; -- Stay in the same state unless changed.
timer_x <= timer_r; -- Hold the cycle timer by default.
refcnt_x <= refcnt_r; -- Hold the refresh timer by default.
cke_x <= cke_r; -- Stay in the same clock mode unless changed.
cmd_x <= CMD_NOP; -- Default to NOP unless changed.
bank_x <= bank_r; -- Register the SDRAM bank.
addr_x <= addr_r; -- Register the SDRAM address.
sd_dout_x <= sd_dout_r; -- Register the SDRAM write data.
sd_busdir_x <= sd_busdir_r; -- Register the SDRAM bus tristate control.
sd_dqmu_x <= sd_dqmu_r;
sd_dqml_x <= sd_dqml_r;
ready_x <= ready_r; -- Always ready unless performing initialization.
done_o <= '0'; -- Done tick, single cycle.
if timer_r /= 0 then
timer_x <= timer_r - 1;
else
cke_x <= '1';
bank_x <= bank_s;
addr_x <= "0000" & col_s; -- A10 low for rd/wr commands to suppress auto-precharge.
sd_dqmu_x <= '0';
sd_dqml_x <= '0';
case state_r is
when ST_INIT_WAIT =>
-- 1. Wait 200us with DQM signals high, cmd NOP.
-- 2. Precharge all banks.
-- 3. Eight refresh cycles.
-- 4. Set mode register.
-- 5. Eight refresh cycles.
state_x <= ST_INIT_PRECHARGE;
timer_x <= 20000; -- Wait 200us (20,000 cycles).
-- timer_x <= 2; -- for simulation
sd_dqmu_x <= '1';
sd_dqml_x <= '1';
when ST_INIT_PRECHARGE =>
state_x <= ST_INIT_REFRESH1;
refcnt_x <= 7; -- Do 8 refresh cycles in the next state.
-- refcnt_x <= 2; -- for simulation
cmd_x <= CMD_PRECHARGE;
timer_x <= 1; -- Wait 1 cycles plus state overhead for 20ns Trp.
addr_x(10) <= '1'; -- Precharge all banks.
when ST_INIT_REFRESH1 =>
if refcnt_r = 0 then
state_x <= ST_INIT_MODE;
else
refcnt_x <= refcnt_r - 1;
cmd_x <= CMD_REFRESH;
timer_x <= 6; -- Wait 6 cycles plus state overhead for 70ns refresh.
end if;
when ST_INIT_MODE =>
state_x <= ST_INIT_REFRESH2;
refcnt_x <= 7; -- Do 8 refresh cycles in the next state.
-- refcnt_x <= 2; -- for simulation
bank_x <= "00";
addr_x <= MODE_REG;
cmd_x <= CMD_MODE;
timer_x <= 1; -- Trsc == 2 cycles after issuing MODE command.
when ST_INIT_REFRESH2 =>
if refcnt_r = 0 then
state_x <= ST_IDLE;
ready_x <= '1';
else
refcnt_x <= refcnt_r - 1;
cmd_x <= CMD_REFRESH;
timer_x <= 6; -- Wait 6 cycles plus state overhead for 70ns refresh.
end if;
--
-- Normal Operation
--
when ST_IDLE =>
-- 60ns since activate when coming from PRECHARGE state.
-- 10ns since PRECHARGE. Trp == 20ns min.
if rw_i = '1' then
state_x <= ST_ACTIVATE;
cmd_x <= CMD_ACTIVATE;
addr_x <= row_s; -- Set bank select and row on activate command.
elsif refresh_i = '1' then
state_x <= ST_REFRESH;
cmd_x <= CMD_REFRESH;
timer_x <= 5; -- Wait 5 cycles plus state overhead for 70ns refresh.
end if;
when ST_REFRESH =>
state_x <= ST_IDLE;
done_o <= '1';
when ST_ACTIVATE =>
-- Trc (Active to Active Command Period) is 65ns min.
-- 70ns since activate when coming from PRECHARGE -> IDLE states.
-- 20ns since PRECHARGE.
-- ACTIVATE command is presented to the SDRAM. The command out of this
-- state will be NOP for one cycle.
state_x <= ST_RCD;
sd_dout_x <= data_i; -- Register any write data, even if not used.
when ST_RCD =>
-- 10ns since activate.
-- Trcd == 20ns min. The clock is 10ns, so the requirement is satisfied by this state.
-- READ or WRITE command will be active in the next cycle.
state_x <= ST_RW;
if we_i = '0' then
cmd_x <= CMD_WRITE;
sd_busdir_x <= '1'; -- The SDRAM latches the input data with the command.
sd_dqmu_x <= ub_i;
sd_dqml_x <= lb_i;
else
cmd_x <= CMD_READ;
end if;
when ST_RW =>
-- 20ns since activate.
-- READ or WRITE command presented to SDRAM.
state_x <= ST_RAS1;
sd_busdir_x <= '0';
when ST_RAS1 =>
-- 30ns since activate.
state_x <= ST_RAS2;
when ST_RAS2 =>
-- 40ns since activate.
-- Tras (Active to precharge Command Period) 45ns min.
-- PRECHARGE command will be active in the next cycle.
state_x <= ST_PRECHARGE;
cmd_x <= CMD_PRECHARGE;
addr_x(10) <= '1'; -- Precharge all banks.
when ST_PRECHARGE =>
-- 50ns since activate.
-- PRECHARGE presented to SDRAM.
state_x <= ST_IDLE;
done_o <= '1'; -- Read data is ready and should be latched by the host.
end case;
end if;
end process;
process (clk_100m0_i)
begin
if falling_edge(clk_100m0_i) then
if reset_i = '0' then
state_r <= ST_INIT_WAIT;
timer_r <= 0;
cmd_r <= CMD_NOP;
cke_r <= '0';
ready_r <= '0';
else
state_r <= state_x;
timer_r <= timer_x;
refcnt_r <= refcnt_x;
cke_r <= cke_x; -- CKE to SDRAM.
cmd_r <= cmd_x; -- Command to SDRAM.
bank_r <= bank_x; -- Bank to SDRAM.
addr_r <= addr_x; -- Address to SDRAM.
sd_dout_r <= sd_dout_x; -- Data to SDRAM.
sd_busdir_r <= sd_busdir_x; -- SDRAM bus direction.
sd_dqmu_r <= sd_dqmu_x; -- Upper byte enable to SDRAM.
sd_dqml_r <= sd_dqml_x; -- Lower byte enable to SDRAM.
ready_r <= ready_x;
end if;
end if;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- LIBRARIES
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library lvin_Interfaces_AxisUart_v1_0;
use lvin_Interfaces_AxisUart_v1_0.AxisUart;
library lvin_Axi4Stream_Framing_v1_0;
use lvin_Axi4Stream_Framing_v1_0.Framing;
library lvin_Axi4Stream_DestPacketizer_v1_0;
use lvin_Axi4Stream_DestPacketizer_v1_0.DestPacketizer;
--library axi_mm2s_mapper_v1_1_19;
-- use axi_mm2s_mapper_v1_1_19.axi_mm2s_mapper_v1_1_19_top;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity AxiUartSlave is
Generic(
g_AClkFrequency : natural := 200000000;
g_BaudRate : natural := 9600;
g_BaudRateSim : natural := 50000000;
g_EscapeByte : std_logic_vector(7 downto 0) := x"7F";
g_StartByte : std_logic_vector(7 downto 0) := x"7D";
g_StopByte : std_logic_vector(7 downto 0) := x"7E"
);
Port (
-- Clock and Reset
AClk : in std_logic;
AResetn : in std_logic;
-- Uart Interface
Uart_TxD : out std_logic;
Uart_RxD : in std_logic;
-- Axi4 Interface
M_AXI_AWValid : out std_logic;
M_AXI_AWReady : in std_logic;
M_AXI_AWAddr : out std_logic_vector (31 downto 0);
M_AXI_AWLen : out std_logic_vector (7 downto 0);
M_AXI_AWSize : out std_logic_vector (2 downto 0);
M_AXI_AWBurst : out std_logic_vector (1 downto 0);
M_AXI_AWLock : out std_logic_vector (0 downto 0);
M_AXI_AWCache : out std_logic_vector (3 downto 0);
M_AXI_AWProt : out std_logic_vector (2 downto 0);
M_AXI_AWQos : out std_logic_vector (3 downto 0);
M_AXI_WValid : out std_logic;
M_AXI_WReady : in std_logic;
M_AXI_WData : out std_logic_vector (31 downto 0);
M_AXI_WStrb : out std_logic_vector (3 downto 0);
M_AXI_WLast : out std_logic;
M_AXI_BValid : in std_logic;
M_AXI_BReady : out std_logic;
M_AXI_BResp : in std_logic_vector (1 downto 0);
M_AXI_ARValid : out std_logic;
M_AXI_ARReady : in std_logic;
M_AXI_ARAddr : out std_logic_vector (31 downto 0);
M_AXI_ARLen : out std_logic_vector (7 downto 0);
M_AXI_ARSize : out std_logic_vector (2 downto 0);
M_AXI_ARBurst : out std_logic_vector (1 downto 0);
M_AXI_ARLock : out std_logic_vector (0 downto 0);
M_AXI_ARCache : out std_logic_vector (3 downto 0);
M_AXI_ARProt : out std_logic_vector (2 downto 0);
M_AXI_ARQos : out std_logic_vector (3 downto 0);
M_AXI_RValid : in std_logic;
M_AXI_RReady : out std_logic;
M_AXI_RData : in std_logic_vector (31 downto 0);
M_AXI_RResp : in std_logic_vector (1 downto 0);
M_AXI_RLast : in std_logic
);
end entity AxiUartSlave;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture rtl of AxiUartSlave is
signal TxByte_TValid : std_logic;
signal TxByte_TReady : std_logic;
signal TxByte_TData : std_logic_vector(7 downto 0);
signal RxByte_TValid : std_logic;
signal RxByte_TReady : std_logic;
signal RxByte_TData : std_logic_vector(7 downto 0);
signal RxFrame_TValid : std_logic;
signal RxFrame_TReady : std_logic;
signal RxFrame_TLast : std_logic;
signal RxFrame_TData : std_logic_vector(7 downto 0);
signal TxFrame_TValid : std_logic;
signal TxFrame_TReady : std_logic;
signal TxFrame_TLast : std_logic;
signal TxFrame_TData : std_logic_vector(7 downto 0);
signal RxPacket_TValid : std_logic;
signal RxPacket_TReady : std_logic;
signal RxPacket_TLast : std_logic;
signal RxPacket_TData : std_logic_vector(7 downto 0);
signal RxPacket_TId : std_logic_vector(2 downto 0);
signal TxPacket_TValid : std_logic;
signal TxPacket_TReady : std_logic;
signal TxPacket_TLast : std_logic;
signal TxPacket_TData : std_logic_vector(7 downto 0);
signal TxPacket_TId : std_logic_vector(2 downto 0);
component axi_mm2s_mapper_v1_1_19_top
generic (
C_FAMILY : string := "artix7";
C_AXI_ID_WIDTH : integer := 1;
C_AXI_ADDR_WIDTH : integer := 32;
C_AXI_DATA_WIDTH : integer := 32;
C_AXI_SUPPORTS_USER_SIGNALS : integer := 0;
C_AXI_SUPPORTS_REGION_SIGNALS : integer := 0;
C_AXI_AWUSER_WIDTH : integer := 1;
C_AXI_ARUSER_WIDTH : integer := 1;
C_AXI_WUSER_WIDTH : integer := 1;
C_AXI_RUSER_WIDTH : integer := 1;
C_AXI_BUSER_WIDTH : integer := 1;
C_AXIS_TDATA_WIDTH : integer := 8;
C_AXIS_TID_WIDTH : integer := 3
);
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_awid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(8-1 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_awlock : in std_logic_vector(1-1 downto 0) := (others => '0');
s_axi_awcache : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_awprot : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_awregion : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_awqos : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_awuser : in std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_wdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0');
s_axi_wuser : in std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_buser : out std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0);
s_axi_bid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
s_axi_bresp : out std_logic_vector(2-1 downto 0);
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_arid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8-1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_arlock : in std_logic_vector(1-1 downto 0) := (others => '0');
s_axi_arcache : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_arprot : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_arregion : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_arqos : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_aruser : in std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_rdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0);
s_axi_ruser : out std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0);
s_axi_rid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(2-1 downto 0);
s_axi_rlast : out std_logic;
m_axi_awvalid : out std_logic;
m_axi_awready : in std_logic;
m_axi_awid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
m_axi_awaddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0);
m_axi_awlen : out std_logic_vector(8-1 downto 0);
m_axi_awsize : out std_logic_vector(3-1 downto 0);
m_axi_awburst : out std_logic_vector(2-1 downto 0);
m_axi_awlock : out std_logic_vector(1-1 downto 0);
m_axi_awcache : out std_logic_vector(4-1 downto 0);
m_axi_awprot : out std_logic_vector(3-1 downto 0);
m_axi_awregion : out std_logic_vector(4-1 downto 0);
m_axi_awqos : out std_logic_vector(4-1 downto 0);
m_axi_awuser : out std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0);
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_wdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0);
m_axi_wstrb : out std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0);
m_axi_wuser : out std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0);
m_axi_wlast : out std_logic;
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
m_axi_buser : in std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0);
m_axi_bid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
m_axi_bresp : in std_logic_vector(2-1 downto 0);
m_axi_arvalid : out std_logic;
m_axi_arready : in std_logic;
m_axi_arid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
m_axi_araddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0);
m_axi_arlen : out std_logic_vector(8-1 downto 0);
m_axi_arsize : out std_logic_vector(3-1 downto 0);
m_axi_arburst : out std_logic_vector(2-1 downto 0);
m_axi_arlock : out std_logic_vector(1-1 downto 0);
m_axi_arcache : out std_logic_vector(4-1 downto 0);
m_axi_arprot : out std_logic_vector(3-1 downto 0);
m_axi_arregion : out std_logic_vector(4-1 downto 0);
m_axi_arqos : out std_logic_vector(4-1 downto 0);
m_axi_aruser : out std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0);
m_axi_rvalid : in std_logic;
m_axi_rready : out std_logic;
m_axi_rdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0);
m_axi_ruser : in std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0);
m_axi_rid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
m_axi_rresp : in std_logic_vector(2-1 downto 0);
m_axi_rlast : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_tkeep : in std_logic_vector(C_AXIS_TDATA_WIDTH/8-1 downto 0);
s_axis_tid : in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0);
s_axis_tlast : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_tkeep : out std_logic_vector(C_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_tid : out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0);
m_axis_tlast : out std_logic
);
end component;
begin
i_AxisUart: entity lvin_Interfaces_AxisUart_v1_0.AxisUart
Generic map(
g_AClkFrequency => g_AClkFrequency,
g_BaudRate => g_BaudRate ,
g_BaudRateSim => g_BaudRateSim
)
Port map(
-- Clock and Reset
AClk => AClk ,
AResetn => AResetn ,
Uart_TxD => Uart_TxD ,
Uart_RxD => Uart_RxD ,
-- Axi4-Stream TxByte Interface
TxByte_TValid => TxByte_TValid,
TxByte_TReady => TxByte_TReady,
TxByte_TData => TxByte_TData ,
-- Axi4-Stream RxByte Interface
RxByte_TValid => RxByte_TValid,
RxByte_TReady => RxByte_TReady,
RxByte_TData => RxByte_TData
);
i_Framing: entity lvin_Axi4Stream_Framing_v1_0.Framing
Generic map(
g_EscapeByte => g_EscapeByte,
g_StartByte => g_StartByte ,
g_StopByte => g_StopByte
)
Port map(
-- Clock and Reset
AClk => AClk ,
AResetn => AResetn,
-- Axi4-Stream RxByte Interface
RxByte_TValid => RxByte_TValid,
RxByte_TReady => RxByte_TReady,
RxByte_TData => RxByte_TData ,
-- Axi4-Stream RxFrame Interface
RxFrame_TValid => RxFrame_TValid,
RxFrame_TReady => RxFrame_TReady,
RxFrame_TData => RxFrame_TData ,
RxFrame_TLast => RxFrame_TLast ,
-- Axi4-Stream TxByte Interface
TxByte_TValid => TxByte_TValid,
TxByte_TReady => TxByte_TReady,
TxByte_TData => TxByte_TData ,
-- Axi4-Stream TxFrame Interface
TxFrame_TValid => TxFrame_TValid,
TxFrame_TReady => TxFrame_TReady,
TxFrame_TData => TxFrame_TData ,
TxFrame_TLast => TxFrame_TLast
);
i_DestPacketizer: entity lvin_Axi4Stream_DestPacketizer_v1_0.DestPacketizer
port map(
-- Clock and reset
AClk => AClk ,
AResetn => AResetn,
-- Axi4-Stream RxFrame interface
RxFrame_TValid => RxFrame_TValid,
RxFrame_TReady => RxFrame_TReady,
RxFrame_TLast => RxFrame_TLast ,
RxFrame_TData => RxFrame_TData ,
-- Axi4-Stream TxFrame interface
TxFrame_TValid => TxFrame_TValid,
TxFrame_TReady => TxFrame_TReady,
TxFrame_TLast => TxFrame_TLast ,
TxFrame_TData => TxFrame_TData ,
-- Axi4-Stream RxPacket interface
RxPacket_TValid => RxPacket_TValid,
RxPacket_TReady => RxPacket_TReady,
RxPacket_TLast => RxPacket_TLast ,
RxPacket_TData => RxPacket_TData ,
RxPacket_TId => RxPacket_TId ,
-- Axi4-Stream TxPacket interface
TxPacket_TValid => TxPacket_TValid,
TxPacket_TReady => TxPacket_TReady,
TxPacket_TLast => TxPacket_TLast ,
TxPacket_TData => TxPacket_TData ,
TxPacket_TId => TxPacket_TId
);
i_AxiStream2MemMapped : entity work.AxiStream2MemMapped
Port map(
-- Clock and Reset
AClk => AClk ,
AResetn => AResetn,
-- Axi4-Stream RxPacket interface
RxPacket_TValid => RxPacket_TValid,
RxPacket_TReady => RxPacket_TReady,
RxPacket_TLast => RxPacket_TLast ,
RxPacket_TData => RxPacket_TData ,
RxPacket_TId => RxPacket_TId ,
-- Axi4-Stream TxPacket interface
TxPacket_TValid => TxPacket_TValid,
TxPacket_TReady => TxPacket_TReady,
TxPacket_TLast => TxPacket_TLast ,
TxPacket_TData => TxPacket_TData ,
TxPacket_TId => TxPacket_TId ,
-- Axi4 Interface
M_AXI_AWValid => M_AXI_AWValid,
M_AXI_AWReady => M_AXI_AWReady,
M_AXI_AWAddr => M_AXI_AWAddr ,
M_AXI_AWLen => M_AXI_AWLen ,
M_AXI_AWSize => M_AXI_AWSize ,
M_AXI_AWBurst => M_AXI_AWBurst,
M_AXI_AWLock => M_AXI_AWLock ,
M_AXI_AWCache => M_AXI_AWCache,
M_AXI_AWProt => M_AXI_AWProt ,
M_AXI_AWQos => M_AXI_AWQos ,
M_AXI_WValid => M_AXI_WValid ,
M_AXI_WReady => M_AXI_WReady ,
M_AXI_WData => M_AXI_WData ,
M_AXI_WStrb => M_AXI_WStrb ,
M_AXI_WLast => M_AXI_WLast ,
M_AXI_BValid => M_AXI_BValid ,
M_AXI_BReady => M_AXI_BReady ,
M_AXI_BResp => M_AXI_BResp ,
M_AXI_ARValid => M_AXI_ARValid,
M_AXI_ARReady => M_AXI_ARReady,
M_AXI_ARAddr => M_AXI_ARAddr ,
M_AXI_ARLen => M_AXI_ARLen ,
M_AXI_ARSize => M_AXI_ARSize ,
M_AXI_ARBurst => M_AXI_ARBurst,
M_AXI_ARLock => M_AXI_ARLock ,
M_AXI_ARCache => M_AXI_ARCache,
M_AXI_ARProt => M_AXI_ARProt ,
M_AXI_ARQos => M_AXI_ARQos ,
M_AXI_RValid => M_AXI_RValid ,
M_AXI_RReady => M_AXI_RReady ,
M_AXI_RData => M_AXI_RData ,
M_AXI_RResp => M_AXI_RResp ,
M_AXI_RLast => M_AXI_RLast
);
--i_Axi4Stream_2_Axi4MM : axi_mm2s_mapper_v1_1_19_top
-- port map (
-- aclk => aclk,
-- aresetn => aresetn,
-- m_axi_awvalid => m_axi_awvalid,
-- m_axi_awready => m_axi_awready,
-- m_axi_awid => open,
-- m_axi_awaddr => m_axi_awaddr,
-- m_axi_awlen => m_axi_awlen,
-- m_axi_awsize => m_axi_awsize,
-- m_axi_awburst => m_axi_awburst,
-- m_axi_awlock => m_axi_awlock,
-- m_axi_awcache => m_axi_awcache,
-- m_axi_awprot => m_axi_awprot,
-- m_axi_awregion => open,
-- m_axi_awqos => m_axi_awqos,
-- m_axi_awuser => open,
-- m_axi_wvalid => m_axi_wvalid,
-- m_axi_wready => m_axi_wready,
-- m_axi_wdata => m_axi_wdata,
-- m_axi_wstrb => m_axi_wstrb,
-- m_axi_wlast => m_axi_wlast,
-- m_axi_wuser => open,
-- m_axi_bvalid => m_axi_bvalid,
-- m_axi_bready => m_axi_bready,
-- m_axi_bid => (others => '0'),
-- m_axi_bresp => m_axi_bresp,
-- m_axi_buser => (others => '0'),
-- m_axi_arvalid => m_axi_arvalid,
-- m_axi_arready => m_axi_arready,
-- m_axi_arid => open,
-- m_axi_araddr => m_axi_araddr,
-- m_axi_arlen => m_axi_arlen,
-- m_axi_arsize => m_axi_arsize,
-- m_axi_arburst => m_axi_arburst,
-- m_axi_arlock => m_axi_arlock,
-- m_axi_arcache => m_axi_arcache,
-- m_axi_arprot => m_axi_arprot,
-- m_axi_arregion => open,
-- m_axi_arqos => m_axi_arqos,
-- m_axi_aruser => open,
-- m_axi_rvalid => m_axi_rvalid,
-- m_axi_rready => m_axi_rready,
-- m_axi_rdata => m_axi_rdata,
-- m_axi_ruser => (others => '0'),
-- m_axi_rid => (others => '0'),
-- m_axi_rresp => m_axi_rresp,
-- m_axi_rlast => m_axi_rlast,
-- s_axis_tvalid => RxPacket_tvalid,
-- s_axis_tready => RxPacket_tready,
-- s_axis_tdata => RxPacket_tdata,
-- s_axis_tkeep => (others => '0'),
-- s_axis_tid => RxPacket_tid,
-- s_axis_tlast => RxPacket_tlast,
-- m_axis_tvalid => TxPacket_TValid,
-- m_axis_tready => TxPacket_TReady,
-- m_axis_tdata => TxPacket_TData,
-- m_axis_tkeep => open,
-- m_axis_tid => TxPacket_TId,
-- m_axis_tlast => TxPacket_TLast
-- );
end architecture rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- This version of the MCU boots and runs from SPI flash.
-- It's intended to have a wrapper containing signal names matching those of
-- the PCB's constraint file. The wrapper also connects the Fishbone bus to peripherals.
ENTITY MCU_V1 IS
generic (
ROMsize : integer := 10; -- log2 (ROM cells)
RAMsize : integer := 10; -- log2 (RAM cells)
clk_Hz : integer := 100000000; -- default clk in Hz
BaseBlock: unsigned(7 downto 0) := x"00"; -- 64KB blocks reserved for bitstream
PID: std_logic_vector(31 downto 0) := x"87654322" -- Product ID (for sfprog)
);
port (
clk : in std_logic; -- System clock
reset : in std_logic; -- Asynchronous reset
bye : out std_logic; -- BYE encountered
-- SPI flash
NCS : out std_logic; -- chip select
SCLK : out std_logic; -- clock
fdata_o : out std_logic_vector(3 downto 0);
fdrive_o: out std_logic_vector(3 downto 0);
fdata_i : in std_logic_vector(3 downto 0);
-- UART
rxd : in std_logic;
txd : out std_logic;
-- Fishbone Bus Master for burst transfers
CYC_O : out std_logic; -- Trigger burst of IMM-1 words
WE_O : out std_logic; -- '1'=write, '0'=read.
BLEN_O : out std_logic_vector(7 downto 0); -- Burst length less 1.
BADR_O : out std_logic_vector(31 downto 0); -- Block address, copy of T.
VALID_O : out std_logic; -- AXI-type handshake for output.
READY_I : in std_logic;
DAT_O : out std_logic_vector(31 downto 0); -- Outgoing data, 32-bit.
VALID_I : in std_logic; -- AXI-type handshake for input.
READY_O : out std_logic;
DAT_I : in std_logic_vector(31 downto 0) -- Incoming data, 32-bit.
);
END MCU_V1;
ARCHITECTURE RTL OF MCU_V1 IS
component m32fb
generic (
RAMsize: integer := 10 -- log2 (RAM cells)
);
port (
clk : in std_logic; -- System clock
reset : in std_logic; -- Asynchronous reset
-- Flash word-read
caddr : out std_logic_vector(25 downto 0); -- Flash memory address
cready : in std_logic; -- Flash memory data ready
cdata : in std_logic_vector(31 downto 0); -- Flash memory read data
-- Peripheral Bus
paddr : out std_logic_vector(8 downto 0); -- address
pwrite : out std_logic; -- write strobe
psel : out std_logic; -- start the cycle
penable : out std_logic; -- delayed psel
pwdata : out std_logic_vector(15 downto 0); -- write data
prdata : in std_logic_vector(15 downto 0); -- read data
pready : in std_logic; -- ready to continue
-- Fishbone Bus Master for burst transfers.
CYC_O : out std_logic; -- Trigger burst of IMM-1 words
WE_O : out std_logic; -- '1'=write, '0'=read.
BLEN_O : out std_logic_vector(7 downto 0); -- Burst length less 1.
BADR_O : out std_logic_vector(31 downto 0); -- Block address, copy of T.
VALID_O : out std_logic; -- AXI-type handshake for output.
READY_I : in std_logic;
DAT_O : out std_logic_vector(31 downto 0); -- Outgoing data, 32-bit.
VALID_I : in std_logic; -- AXI-type handshake for input.
READY_O : out std_logic;
DAT_I : in std_logic_vector(31 downto 0); -- Incoming data, 32-bit.
-- Powerdown
bye : out std_logic -- BYE encountered
);
end component;
signal cready: std_logic;
signal caddr: std_logic_vector(25 downto 0);
signal caddrx: std_logic_vector(29 downto 0);
signal cdata: std_logic_vector(31 downto 0);
signal paddr: std_logic_vector(8 downto 0);
signal pwrite: std_logic;
signal psel: std_logic;
signal pwdata: std_logic_vector(15 downto 0);
signal prdata: std_logic_vector(15 downto 0);
signal pready: std_logic;
signal penable: std_logic;
signal keyready: std_logic;
signal emitready: std_logic;
signal emit_stb: std_logic;
signal key_stb: std_logic;
signal keydata: std_logic_vector(7 downto 0);
signal bitperiod: std_logic_vector(15 downto 0);
signal reset_a, reset_b, reset_i: std_logic; -- reset synchronization
component UART
port(
clk: in std_logic; -- CPU clock
reset: in std_logic; -- sync reset
ready: out std_logic; -- Ready for next byte to send
wstb: in std_logic; -- Send strobe
wdata: in std_logic_vector(7 downto 0); -- Data to send
rxfull: out std_logic; -- RX buffer is full, okay to accept
rstb: in std_logic; -- Accept RX byte
rdata: out std_logic_vector(7 downto 0); -- Received data
bitperiod: in std_logic_vector(15 downto 0); -- Clocks per serial bit
rxd: in std_logic;
txd: out std_logic
);
end component;
signal config: std_logic_vector(7 downto 0);
signal xdata_i: std_logic_vector(9 downto 0);
signal xdata_o: std_logic_vector(7 downto 0);
signal xtrig: std_logic;
signal xbusy: std_logic;
signal fwait: std_logic;
signal sfbusy: std_logic;
COMPONENT sfif
generic (
RAMsize: integer := 10; -- log2 (RAM cells)
CacheSize: integer := 4;
BaseBlock: unsigned(7 downto 0) := x"00"
);
port (clk: in std_logic;
reset: in std_logic; -- reset is async
-- ROM interface
caddr: in std_logic_vector(29 downto 0);
cdata: out std_logic_vector(31 downto 0);
cready: out std_logic;
-- Configuration
config: in std_logic_vector(7 downto 0); -- HW configuration
busy: out std_logic;
-- SPIxfer
xdata_i: in std_logic_vector(9 downto 0);
xdata_o: out std_logic_vector(7 downto 0);
xtrig: in std_logic;
xbusy: out std_logic;
-- 6-wire SPI flash connection
NCS: out std_logic; -- chip select
SCLK: out std_logic; -- clock
data_o: out std_logic_vector(3 downto 0);
drive_o: out std_logic_vector(3 downto 0);
data_i: in std_logic_vector(3 downto 0)
);
END COMPONENT;
signal CPUreset, CPUreset_i: std_logic;
signal xtrigp, xtrigs: std_logic;
signal xdata_op: std_logic_vector(9 downto 0);
-- UART wiring
signal ready_u : std_logic; -- Ready for next byte to send
signal wstb_u : std_logic; -- Send strobe
signal wdata_u : std_logic_vector(7 downto 0);-- Data to send
signal rxfull_u: std_logic; -- RX buffer is full, okay for host to accept
signal rstb_u : std_logic; -- Accept RX byte
signal rdata_u : std_logic_vector(7 downto 0);-- Received data
COMPONENT sfprog
generic (
PID: std_logic_vector(31 downto 0) := x"87654321"; -- Product ID
BaseBlock: unsigned(7 downto 0) := x"00" -- 64KB blocks reserved for bitstream
);
port (
clk : in std_logic; -- System clock
reset : in std_logic; -- Asynchronous reset
hold : out std_logic; -- resets the CPU, makes SFIF trigger from xtrig
busy : in std_logic; -- flash is busy
-- SPI flash
xdata_o : out std_logic_vector(9 downto 0);
xdata_i : in std_logic_vector(7 downto 0);
xtrig : out std_logic;
xbusy : in std_logic;
-- UART register interface: connects to the UART
ready_u : in std_logic; -- Ready for next byte to send
wstb_u : out std_logic; -- Send strobe
wdata_u : out std_logic_vector(7 downto 0); -- Data to send
rxfull_u: in std_logic; -- RX buffer is full, okay for host to accept
rstb_u : out std_logic; -- Accept RX byte
rdata_u : in std_logic_vector(7 downto 0); -- Received data
-- UART register interface: connects to the MCU
ready : out std_logic; -- Ready for next byte to send
wstb : in std_logic; -- Send strobe
wdata : in std_logic_vector(7 downto 0); -- Data to send
rxfull : out std_logic; -- RX buffer is full, okay to accept
rstb : in std_logic; -- Accept RX byte
rdata : out std_logic_vector(7 downto 0) -- Received data
);
END COMPONENT;
---------------------------------------------------------------------------------
BEGIN
-- Create a clean async reset_a signal for the modules.
-- Synchronize the falling edge to the clock.
process(clk, reset)
begin
if (reset = '1') then
reset_a <= '1'; reset_b <= '1';
reset_i <= '1';
elsif rising_edge(clk) then
reset_a <= reset_b; reset_b <= reset_i;
reset_i <= '0';
end if;
end process;
-- Instantiate the components of the MCU: CPU, ROM, and UART
cpu: m32fb
GENERIC MAP ( RAMsize => RAMsize )
PORT MAP (
clk => clk, reset => CPUreset, bye => bye,
caddr => caddr, cready => cready, cdata => cdata,
paddr => paddr, pwrite => pwrite, psel => psel, penable => penable,
pwdata => pwdata, prdata => prdata, pready => pready,
CYC_O => CYC_O, WE_O => WE_O, BLEN_O => BLEN_O, BADR_O => BADR_O,
VALID_O => VALID_O, READY_I => READY_I, DAT_O => DAT_O,
VALID_I => VALID_I, READY_O => READY_O, DAT_I => DAT_I
);
flash: sfif
GENERIC MAP (RAMsize => ROMsize, CacheSize => 4, BaseBlock => BaseBlock)
PORT MAP (
clk => clk, reset => reset, config => config, busy => sfbusy,
caddr => caddrx, cdata => cdata, cready => cready,
xdata_i => xdata_i, xdata_o => xdata_o, xtrig => xtrig, xbusy => xbusy,
NCS => NCS, SCLK => SCLK, data_o => fdata_o, drive_o => fdrive_o, data_i => fdata_i
);
caddrx <= "0000" & caddr;
xtrig <= xtrigp or xtrigs;
ezuart: uart
PORT MAP (
clk => clk, reset => reset_a,
ready => ready_u, wstb => wstb_u, wdata => wdata_u,
rxfull => rxfull_u, rstb => rstb_u, rdata => rdata_u,
bitperiod => bitperiod, rxd => rxd, txd => txd
);
xdata_i <= pwdata(9 downto 0) when CPUreset = '0' else xdata_op;
prog_con: sfprog
GENERIC MAP ( PID => PID, BaseBlock => BaseBlock )
PORT MAP (
clk => clk, reset => reset_a, hold => CPUreset_i, busy => sfbusy,
xdata_o => xdata_op, xdata_i => xdata_o, xbusy => xbusy, xtrig => xtrigp,
ready_u => ready_u, wstb_u => wstb_u, wdata_u => wdata_u,
rxfull_u => rxfull_u, rstb_u => rstb_u, rdata_u => rdata_u,
ready => emitready, wstb => emit_stb, wdata => pwdata(7 downto 0),
rxfull => keyready, rstb => key_stb, rdata => keydata
);
-- decode "APB"
-- clk ___----____----____----____----____----____----____----
-- psel ____----------------___________________________________
-- penable ____________--------___________________________________
-- pready ____________----------------___________________________ if no delay
-- psel ____--------------------------------___________________
-- penable ____________------------------------___________________
-- pready ____________________________----------------___________ 2T delay
DPB_process: process (clk, reset_a) is
begin
if reset_a = '1' then
emit_stb <= '0'; key_stb <= '0'; xtrigs <= '0';
bitperiod <= std_logic_vector(to_unsigned(clk_Hz/115200, 16));
prdata <= x"0000"; pready <= '0'; fwait <= '0';
config <= x"00";
CPUreset <= '1';
elsif rising_edge(clk) then
emit_stb <= '0'; key_stb <= '0'; xtrigs <= '0';
CPUreset <= CPUreset_i; -- synchronize reset from sfcon
if fwait = '1' then
if (xbusy = '0') and (xtrigs = '0') then
fwait <= '0'; pready <= '1'; -- wait for SPI transfer to finish
prdata <= x"00" & xdata_o;
end if;
elsif (psel='1') and (penable='0') then
pready <= '1'; -- usual case: no wait states
case paddr(3 downto 0) is
when "0000" => -- R=qkey, W=emit
prdata <= "000000000000000" & keyready;
emit_stb <= pwrite;
when "0001" => -- R=key, W=spixfer
if pwrite='0' then
prdata <= x"00" & keydata;
key_stb <= '1';
else
xtrigs <= '1'; fwait <= '1'; -- waiting for SPI transfer
pready <= '0';
end if;
when "0010" => -- R=keyformat, W=spiconfig
prdata <= x"0001";
if pwrite='1' then
config <= pwdata(7 downto 0);
end if;
when "0011" => -- R=qemit, W=uartrate
prdata <= "000000000000000" & emitready;
if pwrite='1' then
bitperiod <= pwdata;
end if;
when "0100" => -- R=fbusy
prdata <= "000000000000000" & sfbusy; -- see flash.f
when "0101" => -- R=BaseBlock
prdata <= x"00" & std_logic_vector(BaseBlock); -- see flash.f
when others =>
prdata <= x"0000";
end case;
else
pready <= '0';
end if;
end if;
end process DPB_process;
END RTL;
|
<reponame>YodaEmbedding/experiments
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.all;
entity experiment is
end experiment;
architecture behaviour of experiment is
signal always_false : std_logic := '0';
signal always_true : std_logic := '1';
signal out_nand : std_logic;
begin
yay_nands: entity work.two_port(my_nand) port map(
a => always_true,
b => always_false,
y => out_nand
);
process(out_nand)
variable l : line;
variable y_tmp : std_logic;
begin
y_tmp := out_nand;
--write (l, String'("Hello world!"));
--write (l, std_logic'image(out_nand));
write (l, std_logic'image(y_tmp));
writeline (output, l);
--wait;
end process;
end behaviour;
-- TODO:
-- Testbench
-- Lab 1 (basic things first?)
|
<filename>hardware/HDL/mcore/mcore_exe2.vhd
------------------------------------------------------------------------------
-- Copyright [2014] [Ztachip Technologies Inc]
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
------------------------------------------------------------------------------
-------
-- This module executes all the multi-stage operations: multiplication and division
-- Results are stored in HI and LO registers
-------
library std;
use std.standard.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.hpc_pkg.all;
LIBRARY lpm;
USE lpm.all;
ENTITY mcore_exe2 IS
PORT(
SIGNAL clock_in : IN STD_LOGIC;
SIGNAL reset_in : IN STD_LOGIC;
SIGNAL opcode_in : IN mcore_alu_funct_t;
SIGNAL req_in : IN STD_LOGIC;
SIGNAL x_in : IN mregister_t;
SIGNAL y_in : IN mregister_t;
SIGNAL LO_out : OUT mregister_t;
SIGNAL HI_out : OUT mregister_t;
SIGNAL busy_out : OUT STD_LOGIC
);
END mcore_exe2;
ARCHITECTURE behaviour OF mcore_exe2 IS
COMPONENT lpm_mult
GENERIC (
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_representation : STRING;
lpm_type : STRING;
lpm_widtha : NATURAL;
lpm_widthb : NATURAL;
lpm_widthp : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (lpm_widtha-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (lpm_widthb-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (lpm_widthp-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_divide
GENERIC (
lpm_drepresentation : STRING;
lpm_hint : STRING;
lpm_nrepresentation : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_widthd : NATURAL;
lpm_widthn : NATURAL
);
PORT (
clock : IN STD_LOGIC;
remain : OUT STD_LOGIC_VECTOR (lpm_widthd-1 DOWNTO 0);
denom : IN STD_LOGIC_VECTOR (lpm_widthd-1 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (lpm_widthn-1 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (lpm_widthn-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL LO_r:mregister_t;
SIGNAL HI_r:mregister_t;
SIGNAL mul:STD_LOGIC;
SIGNAL mul_delay:STD_LOGIC;
SIGNAL div:STD_LOGIC;
SIGNAL div_delay:STD_LOGIC;
SIGNAL result_mul:STD_LOGIC_VECTOR(mregister_width_c*2+1 downto 0);
-- WARNING Can only handle max latency=7
SIGNAL busy_count_r:unsigned(5 downto 0);
SIGNAL clear_mul:STD_LOGIC;
SIGNAL clear_div:STD_LOGIC;
SIGNAL div_remain:STD_LOGIC_VECTOR(mregister_width_c downto 0);
SIGNAL div_quotient:STD_LOGIC_VECTOR(mregister_width_c downto 0);
SIGNAL x_mul_r:STD_LOGIC_VECTOR(mregister_width_c downto 0);
SIGNAL y_mul_r:STD_LOGIC_VECTOR(mregister_width_c downto 0);
SIGNAL x_div_r:STD_LOGIC_VECTOR(mregister_width_c downto 0);
SIGNAL y_div_r:STD_LOGIC_VECTOR(mregister_width_c downto 0);
constant MULT_LATENCY:integer:=3;
constant DIV_LATENCY:integer:=33;
BEGIN
LO_out <= LO_r;
HI_out <= HI_r;
busy_out <= '1' when (req_in='1' or (busy_count_r /= to_unsigned(0,busy_count_r'length))) else '0';
delay_i1: delay2 generic map(DEPTH => MULT_LATENCY+1)
port map(clock_in => clock_in,reset_in => reset_in,in_in=>mul,out_out=>mul_delay,enable_in=>'1',clear_in=>clear_mul);
delay_i2: delay2 generic map(DEPTH => DIV_LATENCY+1)
port map(clock_in => clock_in,reset_in => reset_in,in_in=>div,out_out=>div_delay,enable_in=>'1',clear_in=>clear_div);
mul <= '1' when (req_in='1' and (opcode_in=mcore_alu_funct_mult_c or opcode_in=mcore_alu_funct_multu_c)) else '0';
div <= '1' when (req_in='1' and (opcode_in=mcore_alu_funct_div_c or opcode_in=mcore_alu_funct_divu_c)) else '0';
clear_mul <= '1' when (div='1') else '0';
clear_div <= '1' when (mul='1') else '0';
--------
-- Instantiate multiplier
-------
mult_i : lpm_mult
GENERIC MAP (
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5",
lpm_pipeline => MULT_LATENCY,
lpm_representation => "SIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => mregister_width_c+1,
lpm_widthb => mregister_width_c+1,
lpm_widthp => 2*mregister_width_c+2
)
PORT MAP (
clock => clock_in,
dataa => x_mul_r,
datab => y_mul_r,
result => result_mul
);
------
-- Instantiate divider
------
div_i : LPM_DIVIDE
GENERIC MAP (
lpm_drepresentation => "SIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_nrepresentation => "SIGNED",
lpm_pipeline => DIV_LATENCY,
lpm_type => "LPM_DIVIDE",
lpm_widthd => mregister_width_c+1,
lpm_widthn => mregister_width_c+1
)
PORT MAP (
clock => clock_in,
denom => y_div_r,
numer => x_div_r,
remain => div_remain,
quotient => div_quotient
);
-------
-- Latch results from mutiplier/divider to LO/HI registers
-------
process(clock_in,reset_in)
begin
if reset_in='0' then
LO_r <= (others=>'0');
HI_r <= (others=>'0');
busy_count_r <= (others=>'0');
x_mul_r <= (others=>'0');
y_mul_r <= (others=>'0');
x_div_r <= (others=>'0');
y_div_r <= (others=>'0');
else
if clock_in'event and clock_in='1' then
if mul_delay='1' then
-- Result is ready from Multiplier. Latch the result
LO_r <= result_mul(mregister_width_c-1 downto 0);
HI_r <= result_mul(2*mregister_width_c-1 downto mregister_width_c);
elsif div_delay='1' then
-- Result is ready from Divider. Latch the result
LO_r <= div_quotient(mregister_width_c-1 downto 0);
HI_r <= div_remain(mregister_width_c-1 downto 0);
end if;
if mul='1' then
-- Reset count down counter to wait for multiplier's result
busy_count_r <= to_unsigned(MULT_LATENCY,busy_count_r'length);
elsif div='1' then
-- Reset count down counter to wait for divider's result
busy_count_r <= to_unsigned(DIV_LATENCY,busy_count_r'length);
else
if( busy_count_r /= to_unsigned(0,busy_count_r'length)) then
-- Decrement countdownt counter
busy_count_r <= busy_count_r-1;
end if;
end if;
if req_in='1' then
if opcode_in=mcore_alu_funct_mult_c or opcode_in=mcore_alu_funct_div_c then
-- Sign extended for SIGN operation
x_mul_r(mregister_width_c) <= x_in(mregister_width_c-1);
y_mul_r(mregister_width_c) <= y_in(mregister_width_c-1);
x_div_r(mregister_width_c) <= x_in(mregister_width_c-1);
y_div_r(mregister_width_c) <= y_in(mregister_width_c-1);
else
-- Zero the MSB for UNSIGN operation
x_mul_r(mregister_width_c) <= '0';
y_mul_r(mregister_width_c) <= '0';
x_div_r(mregister_width_c) <= '0';
y_div_r(mregister_width_c) <= '0';
end if;
x_mul_r(mregister_width_c-1 downto 0) <= x_in;
y_mul_r(mregister_width_c-1 downto 0) <= y_in;
x_div_r(mregister_width_c-1 downto 0) <= x_in;
y_div_r(mregister_width_c-1 downto 0) <= y_in;
else
x_mul_r(mregister_width_c-1 downto 0) <= (others=>'0');
y_mul_r(mregister_width_c-1 downto 0) <= (others=>'0');
x_div_r(mregister_width_c-1 downto 0) <= (others=>'0');
y_div_r(mregister_width_c-1 downto 0) <= (others=>'0');
end if;
end if;
end if;
end process;
END behaviour;
|
<reponame>NicoLedwith/Dr.AluOpysel<gh_stars>0
----------------------------------------------------------------------------------
-- Company: CPE 233 Productions partnered with Colto Ledstrom
-- Engineer: Various Engineers and <NAME>, <NAME>
--
-- Create Date: 20:59:29 02/04/2013
-- Design Name:
-- Module Name: RAT Control Unit
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Control unit (FSM) for RAT CPU
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Entity CONTROL_UNIT is
Port ( CLK : in STD_LOGIC;
C : in STD_LOGIC;
Z : in STD_LOGIC;
INT : in STD_LOGIC;
RESET : in STD_LOGIC;
OPCODE_HI_5 : in STD_LOGIC_VECTOR (4 downto 0);
OPCODE_LO_2 : in STD_LOGIC_VECTOR (1 downto 0);
PC_LD : out STD_LOGIC;
PC_INC : out STD_LOGIC;
PC_MUX_SEL : out STD_LOGIC_VECTOR (1 downto 0);
PC_OE : out STD_LOGIC;
SP_LD : out STD_LOGIC;
SP_INCR : out STD_LOGIC;
SP_DECR : out STD_LOGIC;
RF_WR : out STD_LOGIC;
RF_WR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
RF_OE : out STD_LOGIC;
ALU_OPY_SEL : out STD_LOGIC;
ALU_SEL : out STD_LOGIC_VECTOR (3 downto 0);
SCR_WR : out STD_LOGIC;
SCR_ADDR_SEL : out STD_LOGIC_VECTOR (1 downto 0);
SCR_OE : out STD_LOGIC;
FLG_C_LD : out STD_LOGIC;
FLG_C_SET : out STD_LOGIC;
FLG_C_CLR : out STD_LOGIC;
FLG_SHAD_LD : out STD_LOGIC;
FLG_LD_SEL : out STD_LOGIC;
FLG_Z_LD : out STD_LOGIC;
I_FLAG_SET : out STD_LOGIC;
I_FLAG_CLR : out STD_LOGIC;
RST : out STD_LOGIC;
IO_STRB : out STD_LOGIC);
end;
architecture Behavioral of CONTROL_UNIT is
type state_type is (ST_init, ST_fet, ST_exec, ST_Interrupt);
signal PS,NS : state_type;
signal sig_OPCODE_7: std_logic_vector (6 downto 0);
begin
-- concatenate the all opcodes into a 7-bit complete opcode for
-- easy instruction decoding.
sig_OPCODE_7 <= OPCODE_HI_5 & OPCODE_LO_2;
sync_p: process (CLK, NS, RESET)
begin
if (RESET = '1') then
PS <= ST_init;
elsif (rising_edge(CLK)) then
PS <= NS;
end if;
end process sync_p;
comb_p: process (sig_OPCODE_7, PS, NS, C, Z, INT)
begin
-- schedule everything to known values -----------------------
PC_LD <= '0';
PC_MUX_SEL <= "00";
PC_OE <= '0';
PC_INC <= '0';
SP_LD <= '0';
SP_INCR <= '0';
SP_DECR <= '0';
RF_WR <= '0';
RF_WR_SEL <= "00";
RF_OE <= '0';
ALU_OPY_SEL <= '0';
ALU_SEL <= "0000";
SCR_WR <= '0';
SCR_OE <= '0';
SCR_ADDR_SEL <= "00";
FLG_C_SET <= '0'; FLG_C_CLR <= '0';
FLG_C_LD <= '0'; FLG_Z_LD <= '0';
FLG_LD_SEL <= '0'; FLG_SHAD_LD <= '0';
I_FLAG_SET <= '0';
I_FLAG_CLR <= '0';
IO_STRB <= '0';
RST <= '0';
case PS is
-- STATE: the init cycle ------------------------------------
-- Initialize all control outputs to non-active states and
-- Reset the PC and SP to all zeros.
when ST_init =>
RST <= '1';
NS <= ST_fet;
-- STATE: the fetch cycle -----------------------------------
when ST_fet =>
RST <= '0';
NS <= ST_exec;
PC_INC <= '1'; -- increment PC
-- STATE: interrupt cycle ----------------------------------
when ST_Interrupt =>
PC_LD <= '1';
PC_INC <= '0';
PC_OE <= '1';
RST <= '0';
PC_MUX_SEL <= "10"; --3ff
SP_LD <= '0';
SP_INCR <= '0';
SP_DECR <= '1';
RST <= '0';
SCR_OE <= '0';
SCR_WR <= '1';
SCR_ADDR_SEL <= "11";
RF_OE <= '0';
I_FLAG_CLR <= '1';
I_FLAG_SET <= '0';
FLG_SHAD_LD <= '1';
NS <= ST_fet;
-- STATE: the execute cycle ---------------------------------
when ST_exec =>
if (INT = '1') then
NS <= ST_Interrupt;
else
NS <= ST_fet;
end if;
PC_INC <= '0'; -- don't increment PC
case sig_OPCODE_7 is
-- BRN -------------------
when "0010000" =>
PC_LD <= '1';
PC_INC <= '0';
PC_OE <= '0';
RST <= '0';
PC_MUX_SEL <= "00";
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- SUB reg-reg --------
when "0000110" =>
ALU_OPY_SEL <= '0';
ALU_SEL <= "0010";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- SUB reg-imm ----------
when "1011000" | "1011001" | "1011010" | "1011011" =>
ALU_OPY_SEL <= '1';
ALU_SEL <= "0010";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- IN reg-immed ------
when "1100100" | "1100101" | "1100110" | "1100111" =>
RF_WR_SEL <= "11";
RF_WR <= '1';
RF_OE <= '0';
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- OUT reg-immed ------
when "1101000" | "1101001" | "1101010" | "1101011" =>
RF_OE <= '1';
RF_WR <= '0';
RF_WR_SEL <= "10"; -- not used
IO_STRB <= '1';
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- MOV reg-immed ------
when "1101100" | "1101101" | "1101110" | "1101111" =>
RF_WR <= '1';
RF_OE <= '0';
RF_WR_SEL <= "00";
ALU_OPY_SEL <= '1';
ALU_SEL <= "1110";
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- MOV reg-reg -----
when "0001001" =>
RF_WR <= '1';
RF_OE <= '0';
RF_WR_SEL <= "00";
ALU_OPY_SEL <= '0';
ALU_SEL <= "1110";
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- ADD reg-reg ------
when "0000100" =>
ALU_OPY_SEL <= '0';
ALU_SEL <= "0000";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- ADD reg-imm ------
when "1010000" | "1010001" | "1010010" | "1010011" =>
ALU_OPY_SEL <= '1';
ALU_SEL <= "0000";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- ADDC reg-reg ------
when "0000101" =>
ALU_OPY_SEL <= '0';
ALU_SEL <= "0001";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- ADDC reg-imm ------
when "1010100" | "1010101" | "1010110" | "1010111" =>
ALU_OPY_SEL <= '1';
ALU_SEL <= "0001";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- AND reg-reg -----
when "0000000" =>
ALU_OPY_SEL <= '0';
ALU_SEL <= "0101";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- AND reg-imm -----
when "1000000" | "1000001" | "1000010" | "1000011" =>
ALU_OPY_SEL <= '1';
ALU_SEL <= "0101";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- ASR reg -----
when "0100100" =>
ALU_OPY_SEL <= '0';
ALU_SEL <= "1101";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- BRCC imm -----
when "0010101" =>
if( C = '0') then
PC_LD <= '1';
PC_INC <= '0';
PC_OE <= '0';
RST <= '0';
PC_MUX_SEL <= "00";
end if;
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- BRCS imm -----
when "0010100" =>
if( C = '1') then
PC_LD <= '1';
PC_INC <= '0';
PC_OE <= '0';
RST <= '0';
PC_MUX_SEL <= "00";
end if;
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- BREQ imm ------
when "0010010" =>
if( Z = '1') then
PC_LD <= '1';
PC_INC <= '0';
PC_OE <= '0';
RST <= '0';
PC_MUX_SEL <= "00";
end if;
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- BRNE imm ------
when "0010011" =>
if( Z = '0') then
PC_LD <= '1';
PC_INC <= '0';
PC_OE <= '0';
RST <= '0';
PC_MUX_SEL <= "00";
end if;
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- CALL imm -------
when "0010001" =>
PC_LD <= '1'; -- pc
PC_INC <= '0';
PC_OE <= '1';
RST <= '0'; -- PC <- imm
SCR_WR <= '1'; -- (SP-1) <- PC
SCR_OE <= '0';
SCR_ADDR_SEL <= "11";
SP_LD <= '0'; -- SP <- SP - 1
SP_INCR <= '0';
SP_DECR <= '1';
RST <= '0';
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- CLC non ------
when "0110000" =>
FLG_C_CLR <= '1';
FLG_C_SET <= '0';
FLG_C_LD <= '0';
FLG_Z_LD <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- CLI non ------
when "0110101" =>
I_FLAG_SET <= '0';
I_FLAG_CLR <= '1';
-- CMP reg-reg ------
when "0001000" =>
ALU_OPY_SEL <= '0';
ALU_SEL <= "0100";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '0';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- CMP reg-imm ------
when "1100000" | "1100001" | "1100010" | "1100011" =>
ALU_OPY_SEL <= '1';
ALU_SEL <= "0100";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '0';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- EXOR reg-reg ----
when "0000010" =>
ALU_OPY_SEL <= '0';
ALU_SEL <= "0111";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- EXOR reg-imm -----
when "1001000" | "1001001" | "1001010" | "1001011" =>
ALU_OPY_SEL <= '1';
ALU_SEL <= "0111";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- LD reg-reg -----
when "0001010" =>
-- Rs <- (RD)
RF_WR_SEL <= "01";
RF_WR <= '1';
RF_OE <= '0';
SCR_WR <= '0';
SCR_OE <= '1';
SCR_ADDR_SEL <= "00";
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- LD reg-imm -----
when "1110000" | "1110001" | "1110010" | "1110011" =>
-- Rs <- (imm)
RF_WR_SEL <= "01";
RF_WR <= '1';
RF_OE <= '0';
SCR_WR <= '0';
SCR_OE <= '1';
SCR_ADDR_SEL <= "01";
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- LSL reg ------
when "0100000" =>
ALU_OPY_SEL <= '0';
ALU_SEL <= "1001";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- LSR reg ------
when "0100001" =>
ALU_OPY_SEL <= '0';
ALU_SEL <= "1010";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- OR reg-reg ----
when "0000001" =>
ALU_OPY_SEL <= '0';
ALU_SEL <= "0110";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- OR reg-imm ----
when "1000100" | "1000101" | "1000110" | "1000111" =>
ALU_OPY_SEL <= '1';
ALU_SEL <= "0110";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- POP reg ----
when "0100110" =>
SP_INCR <= '1';
SP_DECR <= '0';
SP_LD <= '0';
RST <= '0';
SCR_OE <= '1';
SCR_WR <= '0';
SCR_ADDR_SEL <= "10";
RF_WR_SEL <= "01";
RF_OE <= '0';
RF_WR <= '1';
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- PUSH reg ----
when "0100101" =>
SCR_ADDR_SEL <= "11";
SCR_WR <= '1';
SCR_OE <= '0';
RF_OE <= '1';
RF_WR <= '0';
RF_WR_SEL <= "00";
SP_INCR <= '0';
SP_DECR <= '1';
SP_LD <= '0';
RST <= '0';
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- RET non ----
when "0110010" =>
PC_LD <= '1';
PC_INC <= '0';
PC_OE <= '0';
PC_MUX_SEL <= "01";
SCR_ADDR_SEL <= "10";
SCR_OE <= '1';
SCR_WR <= '0';
SP_INCR <= '1';
SP_DECR <= '0';
SP_LD <= '0';
RST <= '0';
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- RETID --
when "0110110" =>
PC_LD <= '1';
PC_INC <= '0';
PC_OE <= '0';
PC_MUX_SEL <= "01";
SCR_ADDR_SEL <= "10";
SCR_OE <= '1';
SCR_WR <= '0';
SP_INCR <= '1';
SP_DECR <= '0';
SP_LD <= '0';
RST <= '0';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '1';
FLG_SHAD_LD <= '0';
I_FLAG_SET <= '0';
I_FLAG_CLR <= '1';
-- RETIE --
when "0110111" =>
PC_LD <= '1';
PC_INC <= '0';
PC_OE <= '0';
PC_MUX_SEL <= "01";
SCR_ADDR_SEL <= "10";
SCR_OE <= '1';
SCR_WR <= '0';
SP_INCR <= '1';
SP_DECR <= '0';
SP_LD <= '0';
RST <= '0';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '1';
FLG_SHAD_LD <= '0';
I_FLAG_SET <= '1';
I_FLAG_CLR <= '0';
-- ROL reg ----
when "0100010" =>
ALU_OPY_SEL <= '0';
ALU_SEL <= "1011";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- ROR reg ----
when "0100011" =>
ALU_OPY_SEL <= '0';
ALU_SEL <= "1100";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- SEC non -----
when "0110001" =>
FLG_C_CLR <= '0';
FLG_C_SET <= '1';
FLG_C_LD <= '0';
FLG_Z_LD <= '0';
-- SEI
when "0110100" =>
I_FLAG_SET <= '1';
I_FLAG_CLR <= '0';
-- ST reg-reg ----
when "0001011" =>
RF_OE <= '1';
RF_WR <= '0';
RF_WR_SEL <= "00";
SCR_ADDR_SEL <= "00";
SCR_WR <= '1';
SCR_OE <= '0';
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- ST reg-imm ----
when "1110100" | "1110101" | "1110110" | "1110111" =>
RF_OE <= '1';
RF_WR <= '0';
RF_WR_SEL <= "00";
SCR_ADDR_SEL <= "01";
SCR_WR <= '1';
SCR_OE <= '0';
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- SUBC reg-reg ----
when "0000111" =>
ALU_OPY_SEL <= '0';
ALU_SEL <= "0011";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
-- SUBC reg-imm -----
when "1011100" | "1011101" | "1011110" | "1011111" =>
ALU_OPY_SEL <= '1';
ALU_SEL <= "0011";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '1';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- TEST reg-reg ------
when "0000011" =>
ALU_OPY_SEL <= '0';
ALU_SEL <= "1000";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '0';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- TEST reg-imm -----
when "1001100" | "1001101" | "1001110" | "1001111" =>
ALU_OPY_SEL <= '1';
ALU_SEL <= "1000";
RF_OE <= '1';
RF_WR_SEL <= "00";
RF_WR <= '0';
FLG_Z_LD <= '1';
FLG_C_LD <= '1';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
-- WSP reg -----
when "0101000" =>
RF_OE <= '1';
RF_WR <= '0';
RF_WR_SEL <= "00";
SP_LD <= '1';
SP_INCR <= '0';
SP_DECR <= '0';
SCR_OE <= '0';
PC_OE <= '0';
FLG_Z_LD <= '0';
FLG_C_LD <= '0';
FLG_C_SET <= '0';
FLG_C_CLR <= '0';
FLG_LD_SEL <= '0';
FLG_SHAD_LD <= '0';
when others => -- for inner case
NS <= ST_fet;
end case; -- inner execute case statement
when others => -- for outer case
NS <= ST_fet;
end case; -- outer init/fetch/execute case
end process comb_p;
end Behavioral;
|
<filename>projects/video/20180218-tmc-test_pattern/vivado/v_tpg_0_ex/v_tpg_0_ex.srcs/sources_1/bd/ex_sim/ip/ex_sim_v_tpg_0_0/hdl/vhdl/ex_sim_v_tpg_0_0_tpgPatternSolidRed.vhd
`protect begin_protected
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`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
<KEY>
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect key_keyowner = "Synopsys", key_keyname= "<KEY>", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
<KEY>
`protect key_keyowner = "Xilinx", key_keyname= "xilinxt_2017_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
<KEY>
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12816)
`protect data_block
<KEY>
`protect end_protected
|
<filename>RCA/16bits/RCA/RCA.vhd
-- Somador 8_bits --
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY RCA IS
PORT (
CarryIn: in std_logic;
val1,val2: in std_logic_vector (15 downto 0);
SomaResult: out std_logic_vector (15 downto 0);
rst:in std_logic;
clk:in std_logic;
CarryOut: out std_logic
);
END RCA ;
ARCHITECTURE strc_RCA OF RCA IS
signal carry: std_logic_vector (15 downto 1);
signal CarryInTemp: std_logic;
signal CarryOutTemp0,CarryOutTemp1: std_logic;
signal A, B, Ssoma: std_logic_vector(15 downto 0);
COMPONENT Soma1
port (
CarryIn,val1,val2: in std_logic ;
SomaResult,CarryOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg1Bit
port(
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
END COMPONENT ;
COMPONENT Reg16Bit
port(
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
END COMPONENT ;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>CarryInTemp
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>CarryOutTemp0,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_A: Reg16Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A
);
Reg_B: Reg16Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B
);
Reg_Ssoma: Reg16Bit PORT MAP (
valIn=>Ssoma,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
--somador--
Som0: Soma1 PORT MAP (
CarryInTemp,
A(0),
B(0),
Ssoma(0),
carry(1)
);
SOM: FOR i IN 1 TO 14 GENERATE
Som1: Soma1 PORT MAP (
carry(i),
A(i),
B(i),
Ssoma(i),
carry(i+1)
);
END GENERATE;
Som7: Soma1 PORT MAP (
carry(15),
A(15),
B(15),
Ssoma(15),
CarryOutTemp0
);
END strc_RCA ;
|
<reponame>sermazz/dlx-pro
--#######################################################################################
--
-- DLX ARCHITECTURE - Custom Implementation (PRO version)
-- Politecnico di Torino
-- Microelectronic Systems, A.Y. 2018/19
-- Prof. Mariagrazia Graziano
--
-- Author: <NAME>
-- Contact: <EMAIL>
--
-- File: testbenches\TEST-a.d-DRAM.vhd
-- Date: August 2019
--
--#######################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
use work.functions.all;
entity dlx_dram_test is
end dlx_dram_test;
architecture TEST of dlx_dram_test is
component DRAM is
generic (
RAM_SIZE : integer := 64; -- in words (of WORD_SIZE bits each; power of 2)
WORD_SIZE : integer := Nbit_DATA -- in bits (multiple of 8 bits)
-- Number of bytes = RAM_SIZE * WORD_SIZE/8
-- Number of bits for address (byte-addressable) = log2(RAM_SIZE * WORD_SIZE/8)
);
port (
Clk : in std_logic; -- Clock
Rst : in std_logic; -- Reset (active-low)
Rd_en : in std_logic; -- Read enable
Wr_en : in std_logic; -- Write enable
Wr_byte : in std_logic; -- 1 = write byte; 0 = write word
Addr : in std_logic_vector(log2(RAM_SIZE*WORD_SIZE/8) - 1 downto 0); -- Read/write address
Din : in std_logic_vector(WORD_SIZE - 1 downto 0); -- Data in for write operations
Dout_w : out std_logic_vector(WORD_SIZE - 1 downto 0); -- Data out for read operations on WORDS
Dout_hw : out std_logic_vector(WORD_SIZE/2 - 1 downto 0); -- Data out for read operations on HALF WORDS
Dout_b : out std_logic_vector(7 downto 0) -- Data out for read operations on BYTES
);
end component;
signal Clock: std_logic := '0';
signal Reset: std_logic := '1';
signal Rd_en_s, Wr_en_s, Wr_byte_s : std_logic := '0';
signal Din_s : std_logic_vector(Nbit_DATA - 1 downto 0) := (OTHERS => '0');
signal Dout_w_s : std_logic_vector(Nbit_DATA - 1 downto 0);
signal Dout_hw_s : std_logic_vector(Nbit_DATA/2 - 1 downto 0);
signal Dout_b_s : std_logic_vector(7 downto 0);
signal Addr_s : std_logic_vector(3 downto 0);
begin
-- instance of Data memory
dut: DRAM generic map (
RAM_SIZE => 4,
WORD_SIZE => Nbit_DATA
)
port map (
Clk => Clock,
Rst => Reset,
Rd_en => Rd_en_s,
Wr_en => Wr_en_s,
Wr_byte => Wr_byte_s,
Addr => Addr_s,
Din => Din_s,
Dout_w => Dout_w_s,
Dout_hw => Dout_hw_s,
Dout_b => Dout_b_s
);
Clock <= not Clock after 1 ns;
Reset <= '0', '1' after 0.5 ns;
STIMULI_PROC: process
begin
Rd_en_s <= '0';
Addr_s <= (OTHERS => '0');
Din_s <= X"FFFFFFFF";
wait until (Clock = '1' AND Clock'EVENT);
-- Test synchronous write of whole word at address 0x00 but addressed as 0x02
wait for 0.5 ns;
Addr_s <= std_logic_vector(to_unsigned(2, Addr_s'LENGTH));
Wr_en_s <= '1';
wait until (Clock = '1' AND Clock'EVENT);
-- Test that only last write within a clock cycle is actually picked
wait for 0.5 ns;
Addr_s <= std_logic_vector(to_unsigned(3, Addr_s'LENGTH));
Din_s <= X"EEEEEEEE";
wait for 0.1 ns;
Addr_s <= std_logic_vector(to_unsigned(4, Addr_s'LENGTH));
Din_s <= X"EEEEEEEE";
wait for 0.1 ns;
Addr_s <= std_logic_vector(to_unsigned(8, Addr_s'LENGTH));
Din_s <= X"EEEEEEEE";
wait until (Clock = '1' AND Clock'EVENT);
-- Test synchronous write of whole word at address 0x04 but addressed as 0x06
wait for 0.5 ns;
Addr_s <= std_logic_vector(to_unsigned(6, Addr_s'LENGTH));
Din_s <= X"AAAAAAAA";
wait until (Clock = '1' AND Clock'EVENT);
-- Test asyncrhonous read of whole word at address 0x04 but addressed as 0x06
wait for 0.5 ns;
Rd_en_s <= '1';
Addr_s <= std_logic_vector(to_unsigned(6, Addr_s'LENGTH));
Din_s <= X"77777777";
Wr_en_s <= '0';
wait until (Clock = '1' AND Clock'EVENT);
-- Test asyncrhonous read of whole word at address 0x00 but addressed as 0x01
wait for 0.5 ns;
Addr_s <= std_logic_vector(to_unsigned(1, Addr_s'LENGTH));
wait until (Clock = '1' AND Clock'EVENT);
-- Test asyncrhonous read of whole word at address 0x04
wait for 0.5 ns;
Addr_s <= std_logic_vector(to_unsigned(4, Addr_s'LENGTH));
wait until (Clock = '1' AND Clock'EVENT);
-- Test synchronous write of byte at address 0x12 (only least significant byte "CB" should be written)
wait for 0.5 ns;
Addr_s <= std_logic_vector(to_unsigned(15, Addr_s'LENGTH));
Din_s <= X"BBBBBBCB";
Wr_en_s <= '1';
Wr_byte_s <= '1';
wait until (Clock = '1' AND Clock'EVENT);
-- Test synchronous write of byte at address 0x00 (only least significant byte "CB" should be written)
wait for 0.5 ns;
Addr_s <= std_logic_vector(to_unsigned(0, Addr_s'LENGTH));
wait;
end process;
end TEST;
configuration TEST_DLX_DRAM of dlx_dram_test is
for TEST
for dut: DRAM
use configuration WORK.CFG_DLX_DRAM;
end for;
end for;
end TEST_DLX_DRAM;
|
<filename>PipelinedProcessor/work/@a@l@u_64_bit/_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ALU_64_bit is
port(
a : in vl_logic_vector(63 downto 0);
b : in vl_logic_vector(63 downto 0);
ALUOp : in vl_logic_vector(3 downto 0);
Result : out vl_logic_vector(63 downto 0);
zero : out vl_logic
);
end ALU_64_bit;
|
<gh_stars>0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.MATH_REAL.ALL;
entity sine_rom is
generic (
addr_bits : integer:= 10; -- range 1 to 30;
data_bits : integer:= 8 -- range 1 to 31
);
port (
clk : in std_logic;
addr : in unsigned(addr_bits - 1 downto 0);
data : out unsigned(data_bits - 1 downto 0)
);
end sine_rom;
architecture Behavioral of sine_rom is
--constant addr_bits
constant MATH_PI : real := 3.14159_26535_89793_23846;
-- value of pi
shared variable seed1, seed2 : integer := 999;
subtype addr_range is integer range 0 to 2**addr_bits - 1;
type rom_type is array (addr_range) of unsigned(data_bits - 1 downto 0);
function init_rom return rom_type is
variable rom_v : rom_type;
variable angle : real;
variable sin_scaled : real;
variable r : real;
begin
for i in addr_range loop
-- uniform(seed1, seed2, r);
angle := real(i) * ((2.0 * MATH_PI) / 2.0**addr_bits);
sin_scaled := (1.0 + sin(angle)) * (2.0**data_bits - 1.0) / 2.0;
rom_v(i) := to_unsigned(integer(round(sin_scaled)), data_bits);
end loop;
return rom_v;
end init_rom;
constant rom : rom_type := init_rom;
begin
ROM_PROC : process(clk)
begin
if rising_edge(clk) then
data <= rom(to_integer(addr));
end if;
end process;
end Behavioral;
|
-- REGISTRADOR 10
library ieee;
use ieee.std_logic_1164.all;
entity reg10 is
port(D10: in std_logic_vector(3 downto 0);
k,RST10,clock: in std_logic;
Q10: out std_logic_vector(3 downto 0)
);
end reg10;
architecture registrador10 of reg10 is
begin process(RST10,clock)
begin
if(RST10 = '1') then
Q10 <= "0000"; -- zera o registrador
elsif(clock' event and clock = '1') then
if(k = '1') then
Q10 <= D10;
end if;
end if;
end process;
end architecture;
|
<gh_stars>0
-- CGA Genlock
-- 2017 <NAME>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity cga_genlock is
port(
clk : in std_logic;
enable : in std_logic;
vblank : in std_logic;
hblank : in std_logic;
r : in std_logic;
g : in std_logic;
b : in std_logic;
int : in std_logic;
wr_ack : in std_logic;
col_number : buffer unsigned(9 downto 0);
row_number : buffer unsigned(9 downto 0);
wren : out std_logic;
wr_req : buffer std_logic;
pixel : out unsigned(5 downto 0);
sram_clk : in std_logic;
vsync : in std_logic;
hsync : in std_logic;
max_col : out unsigned(9 downto 0);
max_row : out unsigned(9 downto 0);
samples : in unsigned(2 downto 0);
top_border : in unsigned(7 downto 0);
left_border : in unsigned(7 downto 0)
);
end cga_genlock;
architecture behavioral of cga_genlock is
--
constant black : unsigned(5 downto 0) := "000000"; -- EGA 0
constant blue : unsigned(5 downto 0) := "000010"; -- EGA 1
constant green : unsigned(5 downto 0) := "001000"; -- EGA 2
constant cyan : unsigned(5 downto 0) := "001010"; -- EGA 3
constant red : unsigned(5 downto 0) := "100000"; -- EGA 4
constant magenta : unsigned(5 downto 0) := "100010"; -- EGA 5
constant brown : unsigned(5 downto 0) := "100100"; -- EGA 20
constant lgray : unsigned(5 downto 0) := "101010"; -- EGA 7
constant dgray : unsigned(5 downto 0) := "010101"; -- EGA 56
constant lblue : unsigned(5 downto 0) := "010111"; -- EGA 57
constant lgreen : unsigned(5 downto 0) := "011101"; -- EGA 58
constant lcyan : unsigned(5 downto 0) := "011111"; -- EGA 59
constant lred : unsigned(5 downto 0) := "110101"; -- EGA 60
constant lmagenta : unsigned(5 downto 0) := "110111"; -- EGA 61
constant yellow : unsigned(5 downto 0) := "111101"; -- EGA 62
constant white : unsigned(5 downto 0) := "111111"; -- EGA 63
signal hcount : unsigned (13 downto 0);
signal vcount : unsigned (13 downto 0);
signal rgbi : unsigned (3 downto 0);
signal store_trg : std_logic := '0';
signal sample_adj : integer range 0 to 7 := 1;
signal s_col_begin : integer range 0 to 2048 := 90;
signal s_col_end : integer range 0 to 2048 := 90+725;
signal s_row_begin : integer range 0 to 2048 := 20;
signal s_row_end : integer range 0 to 2048 := 20+232;
begin
process(clk, enable, samples, left_border, top_border)
begin
if (rising_edge(clk)) then
if (enable = '1') then
s_col_begin <= to_integer(left_border);
s_col_end <= to_integer(left_border) + 752;
s_row_begin <= to_integer(top_border);
s_row_end <= to_integer(top_border) + 232;
sample_adj <= to_integer(samples);
end if;
end if;
end process;
-- colum counter
process(clk, hblank)
begin
if (rising_edge(clk)) then
if (hblank = '1') then
max_col <= col_number;
if (col_number >= 759) then
max_col <= to_unsigned(759, max_col'length);
end if;
hcount <= (others => '0');
else
hcount <= hcount + 1;
end if;
end if;
end process;
-- line counter
process(clk, hblank, vblank)
begin
if (rising_edge(clk)) then
if (hblank = '1') then
vcount <= vcount + 1;
elsif (vblank = '1') then
max_row <= row_number;
vcount <= (others => '0');
end if;
end if;
end process;
-- sram sync
process(sram_clk, hcount, hblank, wr_ack)
begin
if (wr_ack = '1') then
wr_req <= '0';
elsif (rising_edge(sram_clk)) then
if (store_trg = '1') then
wr_req <= '1'; -- dispatch row to SRAM
end if;
end if;
end process;
-- col / row adjustment
process(clk, hcount, s_col_begin, s_col_end, s_row_begin, s_row_end)
begin
if (rising_edge(clk)) then
wren <= '0';
if ((hcount(2 downto 0) = "111") and (hcount(hcount'length-1 downto 3) > s_col_begin and hcount(hcount'length-1 downto 3) < s_col_end) and (vcount > s_row_begin and vcount < s_row_end) ) then
wren <= '1'; -- enable row RAM write
end if;
end if;
end process;
process(clk, vcount, hblank)
begin
if (rising_edge(clk)) then
if (wr_req = '1') then
store_trg <= '0';
end if;
if (hblank = '1') then
if (vcount > s_row_begin and vcount < s_row_end) then
row_number <= row_number + 1;
store_trg <= '1';
end if;
end if;
if (vblank = '1') then
row_number <= (others => '0');
end if;
end if;
end process;
process(clk, hcount, hblank, s_col_begin, s_col_end)
begin
if (rising_edge(clk)) then
if (hcount(2 downto 0) = "111" and hcount(hcount'length-1 downto 3) > s_col_begin and hcount(hcount'length-1 downto 3) < s_col_end) then
col_number <= col_number + 1;
end if;
if (hblank = '1') then
col_number <= (others => '0');
end if;
end if;
end process;
process(clk, hcount, r, sample_adj)
variable i : integer range 0 to 15;
begin
if (rising_edge(clk)) then
if (hcount(2 downto 0) = "110") then
rgbi(3) <= '0';
if (i > sample_adj) then
rgbi(3) <= '1';
end if;
i := 0;
elsif(r = '1' and hcount(2 downto 0) /= "000") then
i := i + 1;
end if;
end if;
end process;
process(clk, hcount, g, sample_adj)
variable i : integer range 0 to 15;
begin
if (rising_edge(clk)) then
if (hcount(2 downto 0) = "110") then
rgbi(2) <= '0';
if (i > sample_adj) then
rgbi(2) <= '1';
end if;
i := 0;
elsif(g = '1' and hcount(2 downto 0) /= "000") then
i := i + 1;
end if;
end if;
end process;
process(clk, hcount, b, sample_adj)
variable i : integer range 0 to 15;
begin
if (rising_edge(clk)) then
if (hcount(2 downto 0) = "110") then
rgbi(1) <= '0';
if (i > sample_adj) then
rgbi(1) <= '1';
end if;
i := 0;
elsif(b = '1' and hcount(2 downto 0) /= "000") then
i := i + 1;
end if;
end if;
end process;
process(clk, hcount, int, sample_adj)
variable i : integer range 0 to 15;
begin
if (rising_edge(clk)) then
if (hcount(2 downto 0) = "110") then
rgbi(0) <= '0';
if (i > sample_adj) then
rgbi(0) <= '1';
end if;
i := 0;
elsif(int = '1' and hcount(2 downto 0) /= "000") then
i := i + 1;
end if;
end if;
end process;
process(clk, rgbi)
variable rgb : unsigned(5 downto 0);
begin
if (rising_edge(clk)) then
if (hcount(2 downto 0) = "111") then
if (rgbi = "0001") then
pixel <= "010101"; -- DARK GRAY
else
rgb := (rgbi(3)&rgbi(0)&rgbi(2)&rgbi(0)&rgbi(1)&rgbi(0)) and (rgbi(3)&rgbi(3)&rgbi(2)&rgbi(2)&rgbi(1)&rgbi(1));
case(rgb) is
when "101000" => pixel <= "100100"; -- BROWN
when others => pixel <= rgb;
end case;
end if;
end if;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- Company: MicroFPGA UG
-- Engineer: <NAME>
--
-- Create Date: 12.01.2019
-- Design Name:
-- Module Name:
-- Project Name: meM "micro embeded Matrix"
-- https://github.com/micro-FPGA/mEM
-- Target Devices: any
-- Tool Versions: any
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- mEM project was born when writing a book "Electronics? Simple! Again :)"
-- https://github.com/micro-FPGA/esa
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity mem_57110 is Port (
-- Configuration interface
cclk : in STD_LOGIC;
cdi : in STD_LOGIC;
cdo : out STD_LOGIC;
creset : in STD_LOGIC := '0';
cdone : in STD_LOGIC := '0';
--
done : out STD_LOGIC; -- embedded Matrix DONE
-- system clock
clk : in STD_LOGIC;
-- We can use BandGap OK as extra input!
BGOK : in STD_LOGIC := '1';
ID : out STD_LOGIC_VECTOR(7 downto 0);
--
dbg_I : out STD_LOGIC_VECTOR(7 downto 0);
P_I : in STD_LOGIC_VECTOR(7 downto 0);
P_T : out STD_LOGIC_VECTOR(7 downto 0);
P_O : out STD_LOGIC_VECTOR(7 downto 0)
);
end mem_57110;
architecture Behavioral of mem_57110 is
attribute DONT_TOUCH : string;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of P_T: SIGNAL is "xilinx.com:interface:gpio:1.0 P TRI_T";
ATTRIBUTE X_INTERFACE_INFO of P_O: SIGNAL is "xilinx.com:interface:gpio:1.0 P TRI_O";
ATTRIBUTE X_INTERFACE_INFO of P_I: SIGNAL is "xilinx.com:interface:gpio:1.0 P TRI_I";
signal lut_en: std_logic;
signal ff_en: std_logic;
signal por: std_logic;
signal cdata: std_logic_vector(9 downto 0);
signal a: std_logic_vector(31 downto 0);
signal q: std_logic_vector(43 downto 0);
attribute DONT_TOUCH of a: signal is "TRUE";
attribute DONT_TOUCH of q: signal is "TRUE";
signal mode : STD_LOGIC_VECTOR(8*4-1 downto 0);
signal rsel : STD_LOGIC_VECTOR(8*3-1 downto 0);
signal drive : STD_LOGIC_VECTOR(8-1 downto 0);
signal port_in: std_logic_vector(7 downto 0);
signal pclk : STD_LOGIC_VECTOR(4 downto 0);
--
begin
done <= cdone;
lut_en <= cdone;
ff_en <= cdone;
por <= creset;
cdata(9) <= cdi;
MISC: entity work.mem_misc
port map (
cclk => cclk,
cdi => cdata(9),
cdo => cdata(8),
cdone => cdone,
ID => ID,
pfd_in => q(37),
pin2_in => P_I(0),
q(1 downto 0) => a(22 downto 21)
);
IOCONFIG: entity work.mem_ioconfig
port map (
mode => mode,
rsel => rsel,
drive => drive,
cclk => cclk,
cdi => cdata(8),
cdo => cdata(7)
);
ACMP: entity work.mem_acmp
port map (
cclk => cclk,
cdi => cdata(7),
cdo => cdata(6),
--
port_in => port_in,
pdb => q(36 downto 35),
q(1 downto 0) => a(20 downto 19)
);
CNTDELAY: entity work.mem_cntdelay
port map (
a(3 downto 0) => q(34 downto 31),
cclk => cclk,
pclkin => pclk,
por => por,
cnt_en => ff_en,
cdi => cdata(6),
cdo => cdata(5),
q(2 downto 0) => a(18 downto 16)
);
OSC: entity work.mem_osc
port map (
cclk => cclk,
cdi => cdata(5),
cdo => cdata(4),
clk => clk,
osc_en => ff_en,
pclkout => pclk,
clkout => a(24 downto 23),
pin12_in => P_I(7),
por => por
);
LUT4CNT: entity work.mem_lut4
port map (
a(3 downto 0) => q(30 downto 27),
cclk => cclk,
cdi => cdata(4),
cdo => cdata(3),
lut_en => lut_en,
q => a(15)
);
LUT3FF: entity work.mem_lut3ff
port map (
a(14 downto 0) => q(26 downto 12),
cclk => cclk,
cdi => cdata(3),
cdo => cdata(2),
ff_en => ff_en,
lut_en => lut_en,
por => por,
q(5 downto 0) => a(14 downto 9)
);
LUT2FF: entity work.mem_lut2ff
port map (
a(7 downto 0) => q(11 downto 4),
cclk => cclk,
cdi => cdata(2),
cdo => cdata(1),
ff_en => ff_en,
lut_en => lut_en,
por => por,
q(3 downto 0) => a(8 downto 5)
);
--
-- Matrix fixed input
--
a(0) <= '0';
a(31) <= '1';
--
-- I/O Ports
--
-- one vector for all port digital inputs
port_in <= a(30 downto 27) & a(4 downto 1);
P2: entity work.mem_io_inp
port map (
-- from config
mode => mode(4*0+3 downto 4*0),
rsel => rsel(3*0+2 downto 3*0),
--
din => a(1),
P_I => P_I(0),
P_O => P_O(0),
P_T => P_T(0)
);
P3: entity work.mem_io_reg
port map (
-- from config
mode => mode(4*1+3 downto 4*1),
rsel => rsel(3*1+2 downto 3*1),
drive => drive(1),
goe => lut_en,
--
din => a(2),
dout => q(0),
P_I => P_I(1),
P_O => P_O(1),
P_T => P_T(1)
);
P4: entity work.mem_io_reg
port map (
-- from config
mode => mode(4*2+3 downto 4*2),
rsel => rsel(3*2+2 downto 3*2),
drive => drive(2),
goe => lut_en,
--
din => a(3),
dout => q(1),
P_I => P_I(2),
P_O => P_O(2),
P_T => P_T(2)
);
P6: entity work.mem_io_oe
port map (
-- from config
mode => mode(4*3+3 downto 4*3),
rsel => rsel(3*3+2 downto 3*3),
drive => drive(3),
goe => lut_en,
--
din => a(4),
dout => q(2),
oe => q(3),
P_I => P_I(3),
P_O => P_O(3),
P_T => P_T(3)
);
P8: entity work.mem_io_reg
port map (
-- from config
mode => mode(4*4+3 downto 4*4),
rsel => rsel(3*4+2 downto 3*4),
drive => drive(4),
goe => lut_en,
--
din => a(27),
dout => q(39),
P_I => P_I(4),
P_O => P_O(4),
P_T => P_T(4)
);
P9: entity work.mem_io_reg
port map (
-- from config
mode => mode(4*5+3 downto 4*5),
rsel => rsel(3*5+2 downto 3*5),
drive => drive(5),
goe => lut_en,
--
din => a(28),
dout => q(40),
P_I => P_I(5),
P_O => P_O(5),
P_T => P_T(5)
);
P10: entity work.mem_io_oe
port map (
-- from config
mode => mode(4*6+3 downto 4*6),
rsel => rsel(3*6+2 downto 3*6),
drive => drive(6),
goe => lut_en,
--
din => a(29),
dout => q(41),
oe => q(42),
P_I => P_I(6),
P_O => P_O(6),
P_T => P_T(6)
);
P12: entity work.mem_io_reg
port map (
-- from config
mode => mode(4*7+3 downto 4*7),
rsel => rsel(3*7+2 downto 3*7),
drive => drive(7),
goe => lut_en,
--
din => a(30),
dout => q(43),
P_I => P_I(7),
P_O => P_O(7),
P_T => P_T(7)
);
MUX: entity work.mux32x44
port map (
a(31 downto 0) => a,
cclk => cclk,
cdi => cdata(1),
cdo => cdata(0),
q(43 downto 0) => q
);
cdo <= cdata(0);
--
dbg_I <= P_I;
end Behavioral;
|
<reponame>OpenPOWERFoundation/a2i
-- © IBM Corp. 2020
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
-- the terms below; you may not use the files in this repository except in
-- compliance with the License as modified.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
--
-- Modified Terms:
--
-- 1) For the purpose of the patent license granted to you in Section 3 of the
-- License, the "Work" hereby includes implementations of the work of authorship
-- in physical form.
--
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
-- necessary for implementation of the Work that are available from OpenPOWER
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
-- of the EULA.
--
-- Unless required by applicable law or agreed to in writing, the reference design
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
-- for the specific language governing permissions and limitations under the License.
--
-- Additional rights, including the ability to physically implement a softcore that
-- is compliant with the required sections of the Power ISA Specification, are
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
library ieee,ibm,support,tri,work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ibm.std_ulogic_unsigned.all;
use ibm.std_ulogic_support.all;
use ibm.std_ulogic_function_support.all;
use support.power_logic_pkg.all;
use tri.tri_latches_pkg.all;
use ibm.std_ulogic_ao_support.all;
use ibm.std_ulogic_mux_support.all;
entity iuq_ic_dir_cmp is
generic( expand_type: integer := 2 ); -- 0 - ibm tech, 1 - other );
port(
vdd :inout power_logic;
gnd :inout power_logic;
nclk :in clk_logic;
delay_lclkr :in std_ulogic;-- LCB input
mpw1_b :in std_ulogic;-- LCB input
mpw2_b :in std_ulogic;-- LCB input
forcee :in std_ulogic;-- LCB input
sg_0 :in std_ulogic;-- LCB input
thold_0_b :in std_ulogic;-- LCB input
scan_in :in std_ulogic;--perv
scan_out :out std_ulogic;--perv
dir_dataout_act :in std_ulogic; --act
iu2_endian :in std_ulogic ;--LE
ierat_iu_iu2_rpn :in std_ulogic_vector(22 to 51) ;--erat
iu2_dir_dataout_0_d :in std_ulogic_vector(22 to 52) ;--directory
iu2_dir_dataout_1_d :in std_ulogic_vector(22 to 52) ;--directory
iu2_dir_dataout_2_d :in std_ulogic_vector(22 to 52) ;--directory
iu2_dir_dataout_3_d :in std_ulogic_vector(22 to 52) ;--directory
ierat_iu_iu2_rpn_noncmp :out std_ulogic_vector(22 to 51) ;-- for noncritical uses of rpn
iu2_dir_dataout_0_noncmp :out std_ulogic_vector(22 to 52) ;-- for spr mux
iu2_dir_dataout_1_noncmp :out std_ulogic_vector(22 to 52) ;-- for spr mux
iu2_dir_dataout_2_noncmp :out std_ulogic_vector(22 to 52) ;-- for spr mux
iu2_dir_dataout_3_noncmp :out std_ulogic_vector(22 to 52) ;-- for spr mux
iu2_dir_rd_val :in std_ulogic_vector(0 to 3) ;
iu2_rd_way_tag_hit :out std_ulogic_vector(0 to 3) ;-- excludes LE
iu2_rd_way_hit :out std_ulogic_vector(0 to 3) ;-- includes LE --2009jun22
iu2_rd_way_hit_insmux_b :out std_ulogic_vector(0 to 3) -- includes LE --2009jun22
);
-- synopsys translate_off
-- synopsys translate_on
end iuq_ic_dir_cmp; -- ENTITY
architecture iuq_ic_dir_cmp of iuq_ic_dir_cmp is
constant tiup : std_ulogic := '1';
constant tidn : std_ulogic := '0';
signal dir_lclk :clk_logic;
signal dir_d1clk :std_ulogic;
signal dir_d2clk :std_ulogic;
signal iu2_dir_dataout_0_l2_b , dir0_q , dir0_si, dir0_so , dir0_slow_b :std_ulogic_vector(0 to 30) ;
signal iu2_dir_dataout_1_l2_b , dir1_q , dir1_si, dir1_so , dir1_slow_b :std_ulogic_vector(0 to 30) ;
signal iu2_dir_dataout_2_l2_b , dir2_q , dir2_si, dir2_so , dir2_slow_b :std_ulogic_vector(0 to 30) ;
signal iu2_dir_dataout_3_l2_b , dir3_q , dir3_si, dir3_so , dir3_slow_b :std_ulogic_vector(0 to 30) ;
signal dir_eq_b :std_ulogic_vector(0 to 3);
signal dir_val_le_b, le_cmp :std_ulogic_vector(0 to 3) ;
-- synopsys translate_off
-- synopsys translate_on
signal erat_i1_b :std_ulogic_vector(0 to 29) ;
-- synopsys translate_off
-- synopsys translate_on
-- synopsys translate_off
-- synopsys translate_on
signal iu2_rd_way_hit_0 :std_ulogic_vector(0 to 3) ;
signal iu2_rd_way_hit_1x_b :std_ulogic_vector(0 to 3) ;
signal iu2_rd_way_hit_1y_b :std_ulogic_vector(0 to 3) ;
signal iu2_rd_way_hit_2x :std_ulogic_vector(0 to 3) ;
-- synopsys translate_off
-- synopsys translate_on
begin
-- ################################################################
-- # inverters from latches
-- ################################################################
u_dir0_q: dir0_q(0 to 30) <= not( iu2_dir_dataout_0_l2_b(0 to 30) );
u_dir1_q: dir1_q(0 to 30) <= not( iu2_dir_dataout_1_l2_b(0 to 30) );
u_dir2_q: dir2_q(0 to 30) <= not( iu2_dir_dataout_2_l2_b(0 to 30) );
u_dir3_q: dir3_q(0 to 30) <= not( iu2_dir_dataout_3_l2_b(0 to 30) );
u_dir0_slowi: dir0_slow_b(0 to 30) <= not( dir0_q(0 to 30) );-- tiny
u_dir1_slowi: dir1_slow_b(0 to 30) <= not( dir1_q(0 to 30) );-- tiny
u_dir2_slowi: dir2_slow_b(0 to 30) <= not( dir2_q(0 to 30) );-- tiny
u_dir3_slowi: dir3_slow_b(0 to 30) <= not( dir3_q(0 to 30) );-- tiny
iu2_dir_dataout_0_noncmp(22 to 52) <= not dir0_slow_b(0 to 30) ;--output-- buffered off
iu2_dir_dataout_1_noncmp(22 to 52) <= not dir1_slow_b(0 to 30) ;--output-- buffered off
iu2_dir_dataout_2_noncmp(22 to 52) <= not dir2_slow_b(0 to 30) ;--output-- buffered off
iu2_dir_dataout_3_noncmp(22 to 52) <= not dir3_slow_b(0 to 30) ;--output-- buffered off
u_erat_i1: erat_i1_b(0 to 29) <= not( ierat_iu_iu2_rpn(22 to 51) );
ierat_iu_iu2_rpn_noncmp(22 to 51) <= ierat_iu_iu2_rpn(22 to 51);
-- ################################################################
-- # directory compares against erat
-- ################################################################
cmp0: entity work.iuq_ic_dir_cmp30(iuq_ic_dir_cmp30) port map(
d0_b(0 to 29) => erat_i1_b (0 to 29) ,--i--iuq_ic_dir_cmp30(dir0cmp)
d1 (0 to 29) => dir0_q (0 to 29) ,--i--iuq_ic_dir_cmp30(dir0cmp)
eq_b => dir_eq_b(0) );--o--iuq_ic_dir_cmp30(dir0cmp)
cmp1: entity work.iuq_ic_dir_cmp30(iuq_ic_dir_cmp30) port map(
d0_b(0 to 29) => erat_i1_b (0 to 29) ,--i--iuq_ic_dir_cmp30(dir1cmp)
d1 (0 to 29) => dir1_q (0 to 29) ,--i--iuq_ic_dir_cmp30(dir1cmp)
eq_b => dir_eq_b(1) );--o--iuq_ic_dir_cmp30(dir1cmp)
cmp2: entity work.iuq_ic_dir_cmp30(iuq_ic_dir_cmp30) port map(
d0_b(0 to 29) => erat_i1_b (0 to 29) ,--i--iuq_ic_dir_cmp30(dir2cmp)
d1 (0 to 29) => dir2_q (0 to 29) ,--i--iuq_ic_dir_cmp30(dir2cmp)
eq_b => dir_eq_b(2) );--o--iuq_ic_dir_cmp30(dir2cmp)
cmp3: entity work.iuq_ic_dir_cmp30(iuq_ic_dir_cmp30) port map(
d0_b(0 to 29) => erat_i1_b (0 to 29) ,--i--iuq_ic_dir_cmp30(dir3cmp)
d1 (0 to 29) => dir3_q (0 to 29) ,--i--iuq_ic_dir_cmp30(dir3cmp)
eq_b => dir_eq_b(3) );--o--iuq_ic_dir_cmp30(dir3cmp)
u_match30: iu2_rd_way_tag_hit(0 to 3) <= not( dir_eq_b(0 to 3) );
u_match31: iu2_rd_way_hit_0(0 to 3) <= not( dir_eq_b(0 to 3) or dir_val_le_b(0 to 3) );
u_match31_1x: iu2_rd_way_hit_1x_b (0 to 3) <= not( iu2_rd_way_hit_0(0 to 3) ) ; --x11 --2009jun22
u_match31_1y: iu2_rd_way_hit_1y_b (0 to 3) <= not( iu2_rd_way_hit_0(0 to 3) ) ; --x11 --2009jun22
u_match31_2x: iu2_rd_way_hit_2x (0 to 3) <= not( iu2_rd_way_hit_1x_b(0 to 3) ) ; --x13 --2009jun22
iu2_rd_way_hit (0 to 3) <= not( iu2_rd_way_hit_1y_b(0 to 3) );--unsized --output-- --2009jun22
u_match31_3x: iu2_rd_way_hit_insmux_b(0 to 3) <= not( iu2_rd_way_hit_2x (0 to 3) ) ; --x13 --output-- --2009jun22
dir_val_le_b(0 to 3) <= not( iu2_dir_rd_val(0 to 3) and le_cmp(0 to 3) ); -- not sized, not placed
le_cmp(0) <= ( dir0_q(30) xnor iu2_endian );-- not sized, not placed
le_cmp(1) <= ( dir1_q(30) xnor iu2_endian );-- not sized, not placed
le_cmp(2) <= ( dir2_q(30) xnor iu2_endian );-- not sized, not placed
le_cmp(3) <= ( dir3_q(30) xnor iu2_endian );-- not sized, not placed
-- ################################################################
-- # Latches
-- ################################################################
iu2_dir_dataout_0_lat: entity tri.tri_inv_nlats generic map (width => 31, btr=> "NLI0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map (
VD => vdd ,
GD => gnd ,
LCLK => dir_lclk ,
D1CLK => dir_d1clk ,
D2CLK => dir_d2clk ,
SCANIN => dir0_si ,
SCANOUT => dir0_so ,
D => iu2_dir_dataout_0_d(22 to 52) ,
QB => iu2_dir_dataout_0_l2_b(0 to 30) );
iu2_dir_dataout_1_lat: entity tri.tri_inv_nlats generic map (width => 31, btr=> "NLI0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map (
VD => vdd ,
GD => gnd ,
LCLK => dir_lclk ,
D1CLK => dir_d1clk ,
D2CLK => dir_d2clk ,
SCANIN => dir1_si ,
SCANOUT => dir1_so ,
D => iu2_dir_dataout_1_d(22 to 52) ,
QB => iu2_dir_dataout_1_l2_b(0 to 30) );
iu2_dir_dataout_2_lat: entity tri.tri_inv_nlats generic map (width => 31, btr=> "NLI0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map (
VD => vdd ,
GD => gnd ,
LCLK => dir_lclk ,
D1CLK => dir_d1clk ,
D2CLK => dir_d2clk ,
SCANIN => dir2_si ,
SCANOUT => dir2_so ,
D => iu2_dir_dataout_2_d(22 to 52) ,
QB => iu2_dir_dataout_2_l2_b(0 to 30) );
iu2_dir_dataout_3_lat: entity tri.tri_inv_nlats generic map (width => 31, btr=> "NLI0001_X2_A12TH", needs_sreset => 0, expand_type => expand_type) port map (
VD => vdd ,
GD => gnd ,
LCLK => dir_lclk ,
D1CLK => dir_d1clk ,
D2CLK => dir_d2clk ,
SCANIN => dir3_si ,
SCANOUT => dir3_so ,
D => iu2_dir_dataout_3_d(22 to 52) ,
QB => iu2_dir_dataout_3_l2_b(0 to 30) );
dir0_si(0 to 30) <= scan_in & dir0_so(0 to 29);
dir1_si(0 to 30) <= dir1_so(1 to 30) & dir0_so(30);
dir2_si(0 to 30) <= dir1_so(0) & dir2_so(0 to 29) ;
dir3_si(0 to 30) <= dir3_so(1 to 30) & dir2_so(30) ;
scan_out <= dir3_so(0) ;
-- ###############################################################
-- # LCBs
-- ###############################################################
dir_lcb : tri_lcbnd generic map (expand_type => expand_type) port map(
nclk => nclk ,--in
vd => vdd ,--inout
gd => gnd ,--inout
act => dir_dataout_act ,--in
delay_lclkr => delay_lclkr ,--in
mpw1_b => mpw1_b ,--in
mpw2_b => mpw2_b ,--in
forcee => forcee,--in
sg => sg_0 ,--in
thold_b => thold_0_b ,--in
d1clk => dir_d1clk ,--out
d2clk => dir_d2clk ,--out
lclk => dir_lclk );--out
--=###############################################################
end; -- iuq_ic_dir_cmp ARCHITECTURE
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